serdescombo5601x.h (49409B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: serdescombo_5601x.h 8 * Purpose: BCM5621X (Raptor) Internal Combo Port PHY Driver 9 * 10/100/1000/2500 with shadow registers 10 */ 11 12 #ifndef _SERDES_COMBO_5601X_H_ 13 #define _SERDES_COMBO_5601X_H_ 14 15 #include <soc/phy.h> 16 #include "phyreg.h" 17 18 /* 19 * Definitions for Internal SerDes 10/100/1000 PHY 20 */ 21 22 /* MII Control Register */ 23 24 /* COMBO SERDES: MII Control bit definitions, same as Standard 10/100 PHY */ 25 #define COMBO_MII_CTRL_RESET MII_CTRL_RESET /* Self clearing SW reset */ 26 #define COMBO_MII_CTRL_SS_LSB MII_CTRL_SS_LSB /* Speed Select, LSB */ 27 #define COMBO_MII_CTRL_SS_MSB MII_CTRL_SS_MSB /* Speed Select, MSB */ 28 #define COMBO_MII_CTRL_SS(_x) MII_CTRL_SS(_x) 29 #define COMBO_MII_CTRL_SS_10 MII_CTRL_SS_10 30 #define COMBO_MII_CTRL_SS_100 MII_CTRL_SS_100 31 #define COMBO_MII_CTRL_SS_1000 MII_CTRL_SS_1000 32 #define COMBO_MII_CTRL_SS_INVALID MII_CTRL_SS_INVALID 33 #define COMBO_MII_CTRL_SS_MASK MII_CTRL_SS_MASK 34 #define COMBO_MII_CTRL_FD MII_CTRL_FD /* Full Duplex */ 35 #define COMBO_MII_CTRL_AN_RESTART (1 << 9) /* Auto Negotiation Enable */ 36 #define COMBO_MII_CTRL_AN_ENABLE (1 << 12) /* Auto Negotiation Enable */ 37 #define COMBO_MII_CTRL_PD MII_CTRL_PD /* Power Down Enable */ 38 #define COMBO_MII_CTRL_LOOPBACK (1 << 14) /* Loopback Enable */ 39 40 /* MII Status Register */ 41 /* COMBO: MII Status Register: not the same as standard 10/100 PHY */ 42 #define COMBO_MII_STAT_RF MII_STAT_RF /* Remote fault */ 43 #define COMBO_MII_STAT_LA MII_STAT_LA /* Link Up */ 44 #define COMBO_MII_STAT_AN_COMPLETE (1 << 5) /* AN complete */ 45 46 /* Bit defines for ANA register */ 47 #define COMBO_MII_ANA_HD (1 << 6) 48 #define COMBO_MII_ANA_FD (1 << 5) 49 #define COMBO_MII_ANA_PAUSE_NONE (0 << 7) 50 #define COMBO_MII_ANA_PAUSE_SYM (1 << 7) 51 #define COMBO_MII_ANA_PAUSE_ASYM (1 << 8) 52 #define COMBO_MII_ANA_PAUSE_MASK (3 << 7) 53 54 /* Auto-Negotiation Link-Partner Ability Register */ 55 #define COMBO_MII_ANP_FIBER_NEXT_PG (1 << 15) 56 #define COMBO_MII_ANP_FIBER_ACK (1 << 14) 57 #define COMBO_MII_ANP_FIBER_RF_SHFT (12) /* Remote fault */ 58 #define COMBO_MII_ANP_FIBER_RF_MASK (0x3000) 59 #define COMBO_MII_ANP_FIBER_PAUSE_ASYM (1 << 8) 60 #define COMBO_MII_ANP_FIBER_PAUSE_SYM (1 << 7) 61 #define COMBO_MII_ANP_FIBER_HD (1 << 6) 62 #define COMBO_MII_ANP_FIBER_FD (1 << 5) 63 64 #define COMBO_MII_ANP_SGMII (1 << 0) 65 #define COMBO_MII_ANP_SGMII_DUPLEX (1 << 12) 66 #define COMBO_MII_ANP_SGMII_SPEED (3 << 10) 67 #define COMBO_MII_ANP_SGMII_SPEED_10 (0) 68 #define COMBO_MII_ANP_SGMII_SPEED_100 (1 << 10) 69 #define COMBO_MII_ANP_SGMII_SPEED_1000 (1 << 11) 70 71 /* Auto-Negotiation Expansion Register */ 72 #define COMBO_ANA_EXPANSION_PR (1 << 1) /* Page received */ 73 74 75 /* If application want to use this header file for accessing PHY registers, 76 * simply redefine SERDESCOMBO_5601X_REG macros to use BCM API as follows. 77 * 78 * #define SERDESCOMBO_5601X_REG_READ(_unit, _port, _flags, _reg_bank, \ 79 * _reg_addr, _val) \ 80 * bcm_port_phy_get((_unit), (_port), 0, 81 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 82 * (_val)) 83 * 84 * #define SERDESCOMBO_5601X_REG_WRITE(_unit, _port, _flags, _reg_bank, \ 85 * _reg_addr, _val) \ 86 * bcm_port_phy_set((_unit), (_port), 0, 87 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 88 * (_val)) 89 * 90 * #define SERDESCOMBO_5601X_REG_MODIFY(_unit, _port, _flags, _reg_bank, \ 91 * _reg_addr, _val)\ 92 * do { \ 93 * return BCM_E_UNAVAIL; \ 94 * } while(0) 95 */ 96 97 /* SERDES register access */ 98 #define SERDESCOMBO_5601X_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 99 _reg_addr, _val) \ 100 phy_serdescombo_5601x_reg_read((_unit), (_phy_ctrl), \ 101 (_reg_bank), (_reg_addr), (_val)) 102 #define SERDESCOMBO_5601X_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 103 _reg_addr, _val) \ 104 phy_serdescombo_5601x_reg_write((_unit), (_phy_ctrl), \ 105 (_reg_bank), (_reg_addr), (_val)) 106 #define SERDESCOMBO_5601X_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 107 _reg_addr, _val, _mask) \ 108 phy_serdescombo_5601x_reg_modify((_unit), (_phy_ctrl), \ 109 (_reg_bank), (_reg_addr), (_val), (_mask)) 110 111 /***************************/ 112 /* Standard IEEE Registers */ 113 /***************************/ 114 115 /* MII Control (Addr 00h) */ 116 #define READ_SERDESCOMBO_5601X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 117 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 118 0x00, 0x0000, 0x00, (_val)) 119 #define WRITE_SERDESCOMBO_5601X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 120 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 121 0x00, 0x0000, 0x00, (_val)) 122 #define MODIFY_SERDESCOMBO_5601X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 123 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 124 (_val), (_mask)) 125 126 /* MII Status (Addr 01h) */ 127 #define READ_SERDESCOMBO_5601X_MII_STATr(_unit, _phy_ctrl, _val) \ 128 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 129 0x00, 0x0000, 0x01, (_val)) 130 #define WRITE_SERDESCOMBO_5601X_MII_STATr(_unit, _phy_ctrl, _val) \ 131 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 132 0x00, 0x0000, 0x01, (_val)) 133 #define MODIFY_SERDESCOMBO_5601X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 134 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 135 (_val), (_mask)) 136 137 /* PHY ID 0 (Addr 02h) */ 138 #define READ_SERDESCOMBO_5601X_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 139 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 140 0x00, 0x0000, 0x02, (_val)) 141 #define WRITE_SERDESCOMBO_5601X_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 142 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 143 0x00, 0x0000, 0x02, (_val)) 144 #define MODIFY_SERDESCOMBO_5601X_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 145 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 146 (_val), (_mask)) 147 148 /* PHY ID 1 (Addr 03h) */ 149 #define READ_SERDESCOMBO_5601X_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 150 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 151 0x00, 0x0000, 0x03, (_val)) 152 #define WRITE_SERDESCOMBO_5601X_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 153 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 154 0x00, 0x0000, 0x03, (_val)) 155 #define MODIFY_SERDESCOMBO_5601X_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 156 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 157 (_val), (_mask)) 158 159 /* Autoneg Adv (Addr 04h) */ 160 #define READ_SERDESCOMBO_5601X_MII_ANAr(_unit, _phy_ctrl, _val) \ 161 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 162 0x00, 0x0000, 0x04, (_val)) 163 #define WRITE_SERDESCOMBO_5601X_MII_ANAr(_unit, _phy_ctrl, _val) \ 164 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 165 0x00, 0x0000, 0x04, (_val)) 166 #define MODIFY_SERDESCOMBO_5601X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 167 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 168 (_val), (_mask)) 169 170 /* Autoneg Link Partner Ability (Addr 05h) */ 171 #define READ_SERDESCOMBO_5601X_MII_ANPr(_unit, _phy_ctrl, _val) \ 172 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 173 0x00, 0x0000, 0x05, (_val)) 174 #define WRITE_SERDESCOMBO_5601X_MII_ANPr(_unit, _phy_ctrl, _val) \ 175 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 176 0x00, 0x0000, 0x05, (_val)) 177 #define MODIFY_SERDESCOMBO_5601X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 178 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 179 (_val), (_mask)) 180 181 /* Autoneg Expansion (Addr 06h) */ 182 #define READ_SERDESCOMBO_5601X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 183 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 184 0x00, 0x0000, 0x06, (_val)) 185 #define WRITE_SERDESCOMBO_5601X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 186 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 187 0x00, 0x0000, 0x06, (_val)) 188 #define MODIFY_SERDESCOMBO_5601X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 189 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 190 (_val), (_mask)) 191 192 /* Extended Status (Addr 0fh) */ 193 194 /*************************/ 195 /* Digital Block (Blk 0) */ 196 /*************************/ 197 /* 1000X Control 1 (Addr 10h) */ 198 #define READ_SERDESCOMBO_5601X_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 199 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 200 0x00, 0x0000, 0x10, (_val)) 201 #define WRITE_SERDESCOMBO_5601X_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 202 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 203 0x00, 0x0000, 0x10, (_val)) 204 #define MODIFY_SERDESCOMBO_5601X_1000X_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 205 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 206 (_val), (_mask)) 207 208 /* 1000X Control 2 (Addr 11h) */ 209 #define READ_SERDESCOMBO_5601X_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 210 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 211 0x00, 0x0000, 0x11, (_val)) 212 #define WRITE_SERDESCOMBO_5601X_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 213 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 214 0x00, 0x0000, 0x11, (_val)) 215 #define MODIFY_SERDESCOMBO_5601X_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 216 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 217 (_val), (_mask)) 218 219 /* 1000X Control 3 (Addr 12h) */ 220 #define READ_SERDESCOMBO_5601X_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 221 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 222 0x00, 0x0000, 0x12, (_val)) 223 #define WRITE_SERDESCOMBO_5601X_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 224 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 225 0x00, 0x0000, 0x12, (_val)) 226 #define MODIFY_SERDESCOMBO_5601X_1000X_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 227 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x12, \ 228 (_val), (_mask)) 229 230 /* 1000X Control 4 (Addr 13h) */ 231 #define READ_SERDESCOMBO_5601X_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 232 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 233 0x00, 0x0000, 0x13, (_val)) 234 #define WRITE_SERDESCOMBO_5601X_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 235 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 236 0x00, 0x0000, 0x13, (_val)) 237 #define MODIFY_SERDESCOMBO_5601X_1000X_CTRL4r(_unit, _phy_ctrl, _val, _mask) \ 238 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x13, \ 239 (_val), (_mask)) 240 241 /* 1000X Status 1 (Addr 14h) */ 242 #define READ_SERDESCOMBO_5601X_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 243 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 244 0x00, 0x0000, 0x14, (_val)) 245 #define WRITE_SERDESCOMBO_5601X_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 246 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 247 0x00, 0x0000, 0x14, (_val)) 248 #define MODIFY_SERDESCOMBO_5601X_1000X_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 249 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x14, \ 250 (_val), (_mask)) 251 252 /* 1000X Status 2 (Addr 15h) */ 253 #define READ_SERDESCOMBO_5601X_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 254 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 255 0x00, 0x0000, 0x15, (_val)) 256 #define WRITE_SERDESCOMBO_5601X_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 257 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 258 0x00, 0x0000, 0x15, (_val)) 259 #define MODIFY_SERDESCOMBO_5601X_1000X_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 260 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x15, \ 261 (_val), (_mask)) 262 263 /* 1000X Status 3 (Addr 16h) */ 264 #define READ_SERDESCOMBO_5601X_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 265 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 266 0x00, 0x0000, 0x16, (_val)) 267 #define WRITE_SERDESCOMBO_5601X_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 268 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 269 0x00, 0x0000, 0x16, (_val)) 270 #define MODIFY_SERDESCOMBO_5601X_1000X_STAT3r(_unit, _phy_ctrl, _val, _mask) \ 271 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x16, \ 272 (_val), (_mask)) 273 274 /* Ber Crc Err Rx Pkt cntr (Addr 17h) */ 275 #define READ_SERDESCOMBO_5601X_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 276 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 277 0x00, 0x0000, 0x17, (_val)) 278 #define WRITE_SERDESCOMBO_5601X_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 279 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 280 0x00, 0x0000, 0x17, (_val)) 281 #define MODIFY_SERDESCOMBO_5601X_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 282 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x17, \ 283 (_val), (_mask)) 284 285 /* Prbs Control (Addr 18h) */ 286 #define READ_SERDESCOMBO_5601X_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 287 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 288 0x00, 0x0000, 0x18, (_val)) 289 #define WRITE_SERDESCOMBO_5601X_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 290 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 291 0x00, 0x0000, 0x18, (_val)) 292 #define MODIFY_SERDESCOMBO_5601X_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 293 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 294 (_val), (_mask)) 295 296 /* Prbs Status (Addr 19h) */ 297 #define READ_SERDESCOMBO_5601X_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 298 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 299 0x00, 0x0000, 0x19, (_val)) 300 #define WRITE_SERDESCOMBO_5601X_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 301 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 302 0x00, 0x0000, 0x19, (_val)) 303 #define MODIFY_SERDESCOMBO_5601X_1000X_PRBS_STATr(_unit, _phy_ctrl, _val, _mask) \ 304 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x19, \ 305 (_val), (_mask)) 306 307 /* Pat Gen Control (Addr 1Ah) */ 308 #define READ_SERDESCOMBO_5601X_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 309 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 310 0x00, 0x0000, 0x1a, (_val)) 311 #define WRITE_SERDESCOMBO_5601X_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 312 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 313 0x00, 0x0000, 0x1a, (_val)) 314 #define MODIFY_SERDESCOMBO_5601X_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 315 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1a, \ 316 (_val), (_mask)) 317 318 /* Pat Gen Status (Addr 1Bh) */ 319 #define READ_SERDESCOMBO_5601X_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 320 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 321 0x00, 0x0000, 0x1b, (_val)) 322 #define WRITE_SERDESCOMBO_5601X_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 323 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 324 0x00, 0x0000, 0x1b, (_val)) 325 #define MODIFY_SERDESCOMBO_5601X_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val, _mask) \ 326 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1b, \ 327 (_val), (_mask)) 328 329 /* Test Mode (Addr 1Ch) */ 330 #define READ_SERDESCOMBO_5601X_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 331 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 332 0x00, 0x0000, 0x1c, (_val)) 333 #define WRITE_SERDESCOMBO_5601X_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 334 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 335 0x00, 0x0000, 0x1c, (_val)) 336 #define MODIFY_SERDESCOMBO_5601X_1000X_TEST_MODEr(_unit, _phy_ctrl, _val, _mask) \ 337 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1c, \ 338 (_val), (_mask)) 339 340 /* Force Tx Data1 (Addr 1Dh) */ 341 #define READ_SERDESCOMBO_5601X_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 342 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 343 0x00, 0x0000, 0x1d, (_val)) 344 #define WRITE_SERDESCOMBO_5601X_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 345 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 346 0x00, 0x0000, 0x1d, (_val)) 347 #define MODIFY_SERDESCOMBO_5601X_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val, _mask) \ 348 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1d, \ 349 (_val), (_mask)) 350 351 /* Force Tx Data2 (Addr 1Eh) */ 352 #define READ_SERDESCOMBO_5601X_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 353 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 354 0x00, 0x0000, 0x1e, (_val)) 355 #define WRITE_SERDESCOMBO_5601X_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 356 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 357 0x00, 0x0000, 0x1e, (_val)) 358 #define MODIFY_SERDESCOMBO_5601X_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val, _mask) \ 359 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 360 (_val), (_mask)) 361 362 /* 1000X Control #1 Register: Controls 10B/SGMII mode */ 363 #define COMBO_1000X_FIBER_MODE (1 << 0) /* Enable SGMII fiber mode */ 364 #define COMBO_1000X_EN10B_MODE (1 << 1) /* Enable TBI 10B interface */ 365 #define COMBO_1000X_INVERT_SD (1 << 3) /* Invert Signal Detect */ 366 #define COMBO_1000X_AUTO_DETECT (1 << 4) /* Auto-detect SGMII and 1000X */ 367 #define COMBO_1000X_RX_PKTS_CNTR_SEL (1 << 11) /* Select receive counter for 17h*/ 368 #define COMBO_1000X_TX_AMPLITUDE_OVRD (1 << 12) 369 370 /* 1000X Control #2 Register Fields */ 371 #define COMBO_1000X_PAR_DET_EN (1 << 0) /* Enable Parallel Detect */ 372 #define COMBO_1000X_FALSE_LNK_DIS (1 << 1) /* Disable false link */ 373 #define COMBO_1000X_FLT_FORCE_EN (1 << 2) /* Enable filter force link */ 374 #define COMBO_1000X_CLRAR_BER_CNTR (1 << 14) /* Clear bit-err-rate counter */ 375 376 /* 1000X Control #3 Register Fields */ 377 #define COMBO_1000X_TX_FIFO_RST (1 << 0) /* Reset TX FIFO */ 378 #define COMBO_1000X_FIFO_ELASTICITY_MASK (0x3 << 1) /* Fifo Elasticity */ 379 #define COMBO_1000X_FIFO_ELASTICITY_5K (0x0 << 1) /* 5 Kbytes */ 380 #define COMBO_1000X_FIFO_ELASTICITY_10K (0x1 << 1) /* 10 Kbytes */ 381 #define COMBO_1000X_FIFO_ELASTICITY_13_5K (0x2 << 1) /* 13.5 Kbytes */ 382 #define COMBO_1000X_RX_FIFO_RST (1 << 14) /* Reset RX FIFO */ 383 384 /* 1000X Control #4 Register Fields */ 385 #define COMBO_1000X_DIG_RESET (1 << 6) /* Reset Datapath */ 386 387 /* 1000X Status #1 Register Fields */ 388 #define COMBO_1000X_STATUS1_SGMII_MODE (1 << 0) 389 #define COMBO_1000X_STATUS1_SPEED (3 << 3) 390 #define COMBO_1000X_STATUS1_SPEED_10 (0) 391 #define COMBO_1000X_STATUS1_SPEED_100 (1 << 3) 392 #define COMBO_1000X_STATUS1_SPEED_1000 (1 << 4) 393 394 395 /************************/ 396 /* Analog Block (Blk 1) */ 397 /************************/ 398 /* Analog Tx (Addr 10h) */ 399 #define READ_SERDESCOMBO_5601X_ANALOG_TXr(_unit, _phy_ctrl, _val) \ 400 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 401 0x00, 0x0001, 0x10, (_val)) 402 #define WRITE_SERDESCOMBO_5601X_ANALOG_TXr(_unit, _phy_ctrl, _val) \ 403 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 404 0x00, 0x0001, 0x10, (_val)) 405 #define MODIFY_SERDESCOMBO_5601X_ANALOG_TXr(_unit, _phy_ctrl, _val, _mask) \ 406 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x10, \ 407 (_val), (_mask)) 408 409 /* Analog RX1 (Addr 11h) */ 410 #define READ_SERDESCOMBO_5601X_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 411 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 412 0x00, 0x0001, 0x11, (_val)) 413 #define WRITE_SERDESCOMBO_5601X_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 414 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 415 0x00, 0x0001, 0x11, (_val)) 416 #define MODIFY_SERDESCOMBO_5601X_ANALOG_RX1r(_unit, _phy_ctrl, _val, _mask) \ 417 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x11, \ 418 (_val), (_mask)) 419 420 /* Analog RX2 (Addr 12h) */ 421 #define READ_SERDESCOMBO_5601X_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 422 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 423 0x00, 0x0001, 0x12, (_val)) 424 #define WRITE_SERDESCOMBO_5601X_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 425 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 426 0x00, 0x0001, 0x12, (_val)) 427 #define MODIFY_SERDESCOMBO_5601X_ANALOG_RX2r(_unit, _phy_ctrl, _val, _mask) \ 428 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x12, \ 429 (_val), (_mask)) 430 431 /* Analog PLL (Addr 13h) */ 432 #define READ_SERDESCOMBO_5601X_ANALOG_PLLr(_unit, _phy_ctrl, _val) \ 433 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 434 0x00, 0x0001, 0x13, (_val)) 435 #define WRITE_SERDESCOMBO_5601X_ANALOG_PLLr(_unit, _phy_ctrl, _val) \ 436 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 437 0x00, 0x0001, 0x13, (_val)) 438 #define MODIFY_SERDESCOMBO_5601X_ANALOG_PLLr(_unit, _phy_ctrl, _val, _mask) \ 439 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x13, \ 440 (_val), (_mask)) 441 442 /* Analog RX3 (Addr 14h) */ 443 #define READ_SERDESCOMBO_5601X_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 444 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 445 0x00, 0x0001, 0x14, (_val)) 446 #define WRITE_SERDESCOMBO_5601X_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 447 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 448 0x00, 0x0001, 0x14, (_val)) 449 #define MODIFY_SERDESCOMBO_5601X_ANALOG_RX3r(_unit, _phy_ctrl, _val, _mask) \ 450 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x14, \ 451 (_val), (_mask)) 452 453 /* TPOUT1 (Addr 18h) */ 454 #define READ_SERDESCOMBO_5601X_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val) \ 455 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 456 0x00, 0x0001, 0x18, (_val)) 457 #define WRITE_SERDESCOMBO_5601X_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val) \ 458 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 459 0x00, 0x0001, 0x18, (_val)) 460 #define MODIFY_SERDESCOMBO_5601X_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val, _mask) \ 461 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 462 (_val), (_mask)) 463 464 /* TPOUT2 (Addr 19h) */ 465 #define READ_SERDESCOMBO_5601X_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val) \ 466 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 467 0x00, 0x0001, 0x19, (_val)) 468 #define WRITE_SERDESCOMBO_5601X_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val) \ 469 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 470 0x00, 0x0001, 0x19, (_val)) 471 #define MODIFY_SERDESCOMBO_5601X_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val, _mask) \ 472 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x19, \ 473 (_val), (_mask)) 474 475 /* Analog Rx 1 Register Fields */ 476 #define COMBO_ANALOG_RX1_IDDQ (1 << 0) 477 #define COMBO_ANALOG_RX1_RESET (1 << 1) 478 #define COMBO_ANALOG_RX1_EDGE_SEL (1 << 8) 479 #define COMBO_ANALOG_RX1_SIG_DET (1 << 10) 480 481 /*****************************/ 482 /* Digital 3 Block (Block 2) */ 483 /*****************************/ 484 /* Digital3 ContCTRL0rol0 Reg (Addr 0x10) */ 485 #define READ_SERDESCOMBO_5601X_DIGI3_CTRL0r(_unit, _phy_ctrl, _val) \ 486 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 487 0x00, 0x0002, 0x10, (_val)) 488 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRL0r(_unit, _phy_ctrl, _val) \ 489 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 490 0x00, 0x0002, 0x10, (_val)) 491 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRL0r(_unit, _phy_ctrl, _val, _mask) \ 492 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 493 0x00, 0x0002, 0x10, (_val), (_mask)) 494 495 /* Digital3 Control1 Reg (Addr 0x11) */ 496 #define READ_SERDESCOMBO_5601X_DIGI3_CTRL1r(_unit, _phy_ctrl, _val) \ 497 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 498 0x00, 0x0002, 0x11, (_val)) 499 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRL1r(_unit, _phy_ctrl, _val) \ 500 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 501 0x00, 0x0002, 0x11, (_val)) 502 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 503 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 504 0x00, 0x0002, 0x11, (_val), (_mask)) 505 506 /* Digital3 Control2 Reg (Addr 0x12) */ 507 #define READ_SERDESCOMBO_5601X_DIGI3_CTRL2r(_unit, _phy_ctrl, _val) \ 508 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 509 0x00, 0x0002, 0x12, (_val)) 510 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRL2r(_unit, _phy_ctrl, _val) \ 511 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 512 0x00, 0x0002, 0x12, (_val)) 513 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 514 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 515 0x00, 0x0002, 0x12, (_val), (_mask)) 516 517 /* Digital3 Control3 Reg (Addr 0x13) */ 518 #define READ_SERDESCOMBO_5601X_DIGI3_CTRL3r(_unit, _phy_ctrl, _val) \ 519 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 520 0x00, 0x0002, 0x13, (_val)) 521 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRL3r(_unit, _phy_ctrl, _val) \ 522 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 523 0x00, 0x0002, 0x13, (_val)) 524 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 525 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 526 0x00, 0x0002, 0x13, (_val), (_mask)) 527 528 /* Digital3 Control4 Reg (Addr 0x14) */ 529 #define READ_SERDESCOMBO_5601X_DIGI3_CTRL4r(_unit, _phy_ctrl, _val) \ 530 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 531 0x00, 0x0002, 0x14, (_val)) 532 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRL4r(_unit, _phy_ctrl, _val) \ 533 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 534 0x00, 0x0002, 0x14, (_val)) 535 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRL4r(_unit, _phy_ctrl, _val, _mask) \ 536 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 537 0x00, 0x0002, 0x14, (_val), (_mask)) 538 539 /* Digital3 ControlB Reg (Addr 0x1B) */ 540 #define READ_SERDESCOMBO_5601X_DIGI3_CTRLBr(_unit, _phy_ctrl, _val) \ 541 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 542 0x00, 0x0002, 0x1b, (_val)) 543 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRLBr(_unit, _phy_ctrl, _val) \ 544 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 545 0x00, 0x0002, 0x1b, (_val)) 546 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRLBr(_unit, _phy_ctrl, _val, _mask) \ 547 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 548 0x00, 0x0002, 0x1b, (_val), (_mask)) 549 550 /* Digital3 ControlC Reg (Addr 0x1C) */ 551 #define READ_SERDESCOMBO_5601X_DIGI3_CTRLCr(_unit, _phy_ctrl, _val) \ 552 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 553 0x00, 0x0002, 0x1c, (_val)) 554 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRLCr(_unit, _phy_ctrl, _val) \ 555 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 556 0x00, 0x0002, 0x1c, (_val)) 557 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRLCr(_unit, _phy_ctrl, _val, _mask) \ 558 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 559 0x00, 0x0002, 0x1c, (_val), (_mask)) 560 561 /* Digital3 ControlD Reg (Addr 0x1D) */ 562 #define READ_SERDESCOMBO_5601X_DIGI3_CTRLDr(_unit, _phy_ctrl, _val) \ 563 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 564 0x00, 0x0002, 0x1d, (_val)) 565 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRLDr(_unit, _phy_ctrl, _val) \ 566 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 567 0x00, 0x0002, 0x1d, (_val)) 568 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRLDr(_unit, _phy_ctrl, _val, _mask) \ 569 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 570 0x00, 0x0002, 0x1d, (_val), (_mask)) 571 572 /* Digital3 ControlE REG (Addr 0x1E) */ 573 #define READ_SERDESCOMBO_5601X_DIGI3_CTRLEr(_unit, _phy_ctrl, _val) \ 574 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 575 0x00, 0x0002, 0x1e, (_val)) 576 #define WRITE_SERDESCOMBO_5601X_DIGI3_CTRLEr(_unit, _phy_ctrl, _val) \ 577 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 578 0x00, 0x0002, 0x1e, (_val)) 579 #define MODIFY_SERDESCOMBO_5601X_DIGI3_CTRLEr(_unit, _phy_ctrl, _val, _mask) \ 580 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 581 0x00, 0x0002, 0x1e, (_val), (_mask)) 582 583 #define COMBO_DIGI3_CTRLB_OVER_1G (1 << 0) 584 #define COMBO_DIGI3_CTRLD_OVER_1G (1 << 0) 585 586 /***********************/ 587 /* PLL Block (Block 3) */ 588 /***********************/ 589 /* PLL STATUS Reg (Addr 0x10) */ 590 #define READ_SERDESCOMBO_5601X_PLL_STATr(_unit, _phy_ctrl, _val) \ 591 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 592 0x00, 0x0003, 0x10, (_val)) 593 #define WRITE_SERDESCOMBO_5601X_PLL_STATr(_unit, _phy_ctrl, _val) \ 594 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 595 0x00, 0x0003, 0x10, (_val)) 596 #define MODIFY_SERDESCOMBO_5601X_PLL_STATr(_unit, _phy_ctrl, _val, _mask) \ 597 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 598 0x00, 0x0003, 0x10, (_val), (_mask)) 599 600 /* PLL CONTROL Reg (Addr 0x11) */ 601 #define READ_SERDESCOMBO_5601X_PLL_CTRLr(_unit, _phy_ctrl, _val) \ 602 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 603 0x00, 0x0003, 0x11, (_val)) 604 #define WRITE_SERDESCOMBO_5601X_PLL_CTRLr(_unit, _phy_ctrl, _val) \ 605 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 606 0x00, 0x0003, 0x11, (_val)) 607 #define MODIFY_SERDESCOMBO_5601X_PLL_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 608 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 609 0x00, 0x0003, 0x11, (_val), (_mask)) 610 611 /* PLL TIMER1 Reg (Addr 0x12) */ 612 #define READ_SERDESCOMBO_5601X_PLL_TIMER1r(_unit, _phy_ctrl, _val) \ 613 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 614 0x00, 0x0003, 0x12, (_val)) 615 #define WRITE_SERDESCOMBO_5601X_PLL_TIMER1r(_unit, _phy_ctrl, _val) \ 616 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 617 0x00, 0x0003, 0x12, (_val)) 618 #define MODIFY_SERDESCOMBO_5601X_PLL_TIMER1r(_unit, _phy_ctrl, _val, _mask) \ 619 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 620 0x00, 0x0003, 0x12, (_val), (_mask)) 621 622 /* PLL TIMER2 Reg (Addr 0x13) */ 623 #define READ_SERDESCOMBO_5601X_PLL_TIMER2r(_unit, _phy_ctrl, _val) \ 624 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 625 0x00, 0x0003, 0x13, (_val)) 626 #define WRITE_SERDESCOMBO_5601X_PLL_TIMER2r(_unit, _phy_ctrl, _val) \ 627 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 628 0x00, 0x0003, 0x13, (_val)) 629 #define MODIFY_SERDESCOMBO_5601X_PLL_TIMER2r(_unit, _phy_ctrl, _val, _mask) \ 630 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 631 0x00, 0x0003, 0x13, (_val), (_mask)) 632 633 /* PLL TIMER3 Reg (Addr 0x14) */ 634 #define READ_SERDESCOMBO_5601X_PLL_TIMER3r(_unit, _phy_ctrl, _val) \ 635 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 636 0x00, 0x0003, 0x14, (_val)) 637 #define WRITE_SERDESCOMBO_5601X_PLL_TIMER3r(_unit, _phy_ctrl, _val) \ 638 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 639 0x00, 0x0003, 0x14, (_val)) 640 #define MODIFY_SERDESCOMBO_5601X_PLL_TIMER3r(_unit, _phy_ctrl, _val, _mask) \ 641 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 642 0x00, 0x0003, 0x14, (_val), (_mask)) 643 644 /* PLL CAP CONTROL Reg (Addr 0x15) */ 645 #define READ_SERDESCOMBO_5601X_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 646 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 647 0x00, 0x0003, 0x15, (_val)) 648 #define WRITE_SERDESCOMBO_5601X_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 649 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 650 0x00, 0x0003, 0x15, (_val)) 651 #define MODIFY_SERDESCOMBO_5601X_PLL_CAP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 652 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 653 0x00, 0x0003, 0x15, (_val), (_mask)) 654 655 /* PLL AMP CONTROL Reg (Addr 0x16) */ 656 #define READ_SERDESCOMBO_5601X_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 657 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 658 0x00, 0x0003, 0x16, (_val)) 659 #define WRITE_SERDESCOMBO_5601X_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 660 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 661 0x00, 0x0003, 0x16, (_val)) 662 #define MODIFY_SERDESCOMBO_5601X_PLL_AMP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 663 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 664 0x00, 0x0003, 0x16, (_val), (_mask)) 665 666 /* PLL FREQ DET CNTR Reg (Addr 0x17) */ 667 #define READ_SERDESCOMBO_5601X_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val) \ 668 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 669 0x00, 0x0003, 0x17, (_val)) 670 #define WRITE_SERDESCOMBO_5601X_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val) \ 671 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 672 0x00, 0x0003, 0x17, (_val)) 673 #define MODIFY_SERDESCOMBO_5601X_PLL_FREQ_DET_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 674 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 675 0x00, 0x0003, 0x17, (_val), (_mask)) 676 677 /* PLL ASTATUS1 Reg (Addr 0x18) */ 678 #define READ_SERDESCOMBO_5601X_PLL_ASTAT1r(_unit, _phy_ctrl, _val) \ 679 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 680 0x00, 0x0003, 0x18, (_val)) 681 #define WRITE_SERDESCOMBO_5601X_PLL_ASTAT1r(_unit, _phy_ctrl, _val) \ 682 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 683 0x00, 0x0003, 0x18, (_val)) 684 #define MODIFY_SERDESCOMBO_5601X_PLL_ASTAT1r(_unit, _phy_ctrl, _val, _mask) \ 685 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 686 0x00, 0x0003, 0x18, (_val), (_mask)) 687 688 /* PLL ASTATUS2 Reg (Addr 0x19) */ 689 #define READ_SERDESCOMBO_5601X_PLL_ASTAT2r(_unit, _phy_ctrl, _val) \ 690 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 691 0x00, 0x0003, 0x19, (_val)) 692 #define WRITE_SERDESCOMBO_5601X_PLL_ASTAT2r(_unit, _phy_ctrl, _val) \ 693 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 694 0x00, 0x0003, 0x19, (_val)) 695 #define MODIFY_SERDESCOMBO_5601X_PLL_ASTAT2r(_unit, _phy_ctrl, _val, _mask) \ 696 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 697 0x00, 0x0003, 0x19, (_val), (_mask)) 698 699 /* PLL ACONTROL1 Reg (Addr 0x1A) */ 700 #define READ_SERDESCOMBO_5601X_PLL_ACTRL1r(_unit, _phy_ctrl, _val) \ 701 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 702 0x00, 0x0003, 0x1a, (_val)) 703 #define WRITE_SERDESCOMBO_5601X_PLL_ACTRL1r(_unit, _phy_ctrl, _val) \ 704 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 705 0x00, 0x0003, 0x1a, (_val)) 706 #define MODIFY_SERDESCOMBO_5601X_PLL_ACTRL1r(_unit, _phy_ctrl, _val, _mask) \ 707 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 708 0x00, 0x0003, 0x1a, (_val), (_mask)) 709 710 /* PLL ACONTROL2 Reg (Addr 0x1B) */ 711 #define READ_SERDESCOMBO_5601X_PLL_ACTRL2r(_unit, _phy_ctrl, _val) \ 712 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 713 0x00, 0x0003, 0x1b, (_val)) 714 #define WRITE_SERDESCOMBO_5601X_PLL_ACTRL2r(_unit, _phy_ctrl, _val) \ 715 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 716 0x00, 0x0003, 0x1b, (_val)) 717 #define MODIFY_SERDESCOMBO_5601X_PLL_ACTRL2r(_unit, _phy_ctrl, _val, _mask) \ 718 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 719 0x00, 0x0003, 0x1b, (_val), (_mask)) 720 721 /* PLL ACONTROL3 Reg (Addr 0x1C) */ 722 #define READ_SERDESCOMBO_5601X_PLL_ACTRL3r(_unit, _phy_ctrl, _val) \ 723 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 724 0x00, 0x0003, 0x1c, (_val)) 725 #define WRITE_SERDESCOMBO_5601X_PLL_ACTRL3r(_unit, _phy_ctrl, _val) \ 726 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 727 0x00, 0x0003, 0x1c, (_val)) 728 #define MODIFY_SERDESCOMBO_5601X_PLL_ACTRL3r(_unit, _phy_ctrl, _val, _mask) \ 729 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 730 0x00, 0x0003, 0x1c, (_val), (_mask)) 731 732 /* PLL ACONTROL4 Reg (Addr 0x1D) */ 733 #define READ_SERDESCOMBO_5601X_PLL_ACTRL4r(_unit, _phy_ctrl, _val) \ 734 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 735 0x00, 0x0003, 0x1d, (_val)) 736 #define WRITE_SERDESCOMBO_5601X_PLL_ACTRL4r(_unit, _phy_ctrl, _val) \ 737 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 738 0x00, 0x0003, 0x1d, (_val)) 739 #define MODIFY_SERDESCOMBO_5601X_PLL_ACTRL4r(_unit, _phy_ctrl, _val, _mask) \ 740 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 741 0x00, 0x0003, 0x1d, (_val), (_mask)) 742 743 /**********************/ 744 /* RX Block (Block 4) */ 745 /**********************/ 746 747 /* RX Status Reg (Addr 0x10) */ 748 /* RX Control Reg (Addr 0x11) */ 749 /* RX Timer1 Reg (Addr 0x12) */ 750 /* RX Timer2 Reg (Addr 0x13) */ 751 /* RX Sig Det Reg (Addr 0x14) */ 752 /* RX CDR Phase Reg (Addr 0x15) */ 753 /* RX CDR Freq Reg (Addr 0x16) */ 754 /* RX EQ Config Reg (Addr 0x17) */ 755 /* RX EQ Force Reg (Addr 0x18) */ 756 /* RX Control 1G Reg (Addr 0x19) */ 757 /* RX AStatus Reg (Addr 0x1A) */ 758 /* RX AControl1 Reg (Addr 0x1B) */ 759 /* RX AControl2 Reg (Addr 0x1C) */ 760 /* RX AControl3 Reg (Addr 0x1D) */ 761 /* RX Acontrol4 Reg (Addr 0x1E) */ 762 763 /************************/ 764 /* Misc Block (Block 5) */ 765 /************************/ 766 /* Misc 2500X Status Reg (Addr 0x10) */ 767 #define READ_SERDESCOMBO_5601X_MISC_2500X_STATr(_unit, _phy_ctrl, _val) \ 768 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 769 0x00, 0x0005, 0x10, (_val)) 770 #define WRITE_SERDESCOMBO_5601X_MISC_2500X_STATr(_unit, _phy_ctrl, _val) \ 771 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 772 0x00, 0x0005, 0x10, (_val)) 773 #define MODIFY_SERDESCOMBO_5601X_MISC_2500X_STATr(_unit, _phy_ctrl, _val, _mask) \ 774 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 775 0x00, 0x0005, 0x10, (_val), (_mask)) 776 777 /* Reserved (Addr 0x11 - 0x13) */ 778 /* Misc AStatus1 Reg (Addr 0x14) */ 779 #define READ_SERDESCOMBO_5601X_MISC_ASTAT1r(_unit, _phy_ctrl, _val) \ 780 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 781 0x00, 0x0005, 0x14, (_val)) 782 #define WRITE_SERDESCOMBO_5601X_MISC_ASTAT1r(_unit, _phy_ctrl, _val) \ 783 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 784 0x00, 0x0005, 0x14, (_val)) 785 #define MODIFY_SERDESCOMBO_5601X_MISC_ASTAT1r(_unit, _phy_ctrl, _val, _mask) \ 786 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 787 0x00, 0x0005, 0x14, (_val), (_mask)) 788 789 /* Misc TX AContTX_ACTRL1rol1 Reg (Addr 0x15) */ 790 #define READ_SERDESCOMBO_5601X_MISC_TX_ACTRL1r(_unit, _phy_ctrl, _val) \ 791 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 792 0x00, 0x0005, 0x15, (_val)) 793 #define WRITE_SERDESCOMBO_5601X_MISC_TX_ACTRL1r(_unit, _phy_ctrl, _val) \ 794 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 795 0x00, 0x0005, 0x15, (_val)) 796 #define MODIFY_SERDESCOMBO_5601X_MISC_TX_ACTRL1r(_unit, _phy_ctrl, _val, _mask) \ 797 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 798 0x00, 0x0005, 0x15, (_val), (_mask)) 799 800 /* Misc TX AContTX_ACTRL2rol2 Reg (Addr 0x16) */ 801 #define READ_SERDESCOMBO_5601X_MISC_TX_ACTRL2r(_unit, _phy_ctrl, _val) \ 802 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctTX_ACTRL2rl), \ 803 0x00, 0x0005, 0x16, (_val)) 804 #define WRITE_SERDESCOMBO_5601X_MISC_TX_ACTRL2r(_unit, _phy_ctrl, _val) \ 805 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctTX_ACTRL2rl), \ 806 0x00, 0x0005, 0x16, (_val)) 807 #define MODIFY_SERDESCOMBO_5601X_MISC_TX_ACTRL2r(_unit, _phy_ctrl, _val, _mask) \ 808 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctTX_ACTRL2rl), \ 809 0x00, 0x0005, 0x16, (_val), (_mask)) 810 811 /* Misc TX AContTX_ACTRL3rol3 Reg (Addr 0x17) */ 812 #define READ_SERDESCOMBO_5601X_MISC_TX_ACTRL3r(_unit, _phy_ctrl, _val) \ 813 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 814 0x00, 0x0005, 0x17, (_val)) 815 #define WRITE_SERDESCOMBO_5601X_MISC_TX_ACTRL3r(_unit, _phy_ctrl, _val) \ 816 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 817 0x00, 0x0005, 0x17, (_val)) 818 #define MODIFY_SERDESCOMBO_5601X_MISC_TX_ACTRL3r(_unit, _phy_ctrl, _val, _mask) \ 819 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 820 0x00, 0x0005, 0x17, (_val), (_mask)) 821 822 /* Reserved (Addr 0x18) */ 823 /* Misc CAP ContCAP_CTRLrols Reg (Addr 0x19) */ 824 #define READ_SERDESCOMBO_5601X_MISC_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 825 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 826 0x00, 0x0005, 0x19, (_val)) 827 #define WRITE_SERDESCOMBO_5601X_MISC_CAP_CTRLr(_unit, _phy_ctrl, _val) \ 828 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 829 0x00, 0x0005, 0x19, (_val)) 830 #define MODIFY_SERDESCOMBO_5601X_MISC_CAP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 831 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 832 0x00, 0x0005, 0x19, (_val), (_mask)) 833 834 /* Misc AMP Controls Reg (Addr 0x1A) */ 835 #define READ_SERDESCOMBO_5601X_MISC_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 836 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 837 0x00, 0x0005, 0x1a, (_val)) 838 #define WRITE_SERDESCOMBO_5601X_MISC_AMP_CTRLr(_unit, _phy_ctrl, _val) \ 839 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 840 0x00, 0x0005, 0x1a, (_val)) 841 #define MODIFY_SERDESCOMBO_5601X_MISC_AMP_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 842 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 843 0x00, 0x0005, 0x1a, (_val), (_mask)) 844 845 /* Misc RX Status Reg (Addr 0x1B) */ 846 #define READ_SERDESCOMBO_5601X_MISC_RX_STATr(_unit, _phy_ctrl, _val) \ 847 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 848 0x00, 0x0005, 0x1b, (_val)) 849 #define WRITE_SERDESCOMBO_5601X_MISC_RX_STATr(_unit, _phy_ctrl, _val) \ 850 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 851 0x00, 0x0005, 0x1b, (_val)) 852 #define MODIFY_SERDESCOMBO_5601X_MISC_RX_STATr(_unit, _phy_ctrl, _val, _mask) \ 853 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 854 0x00, 0x0005, 0x1b, (_val), (_mask)) 855 856 /* Misc IF Reg (Addr 0x1C) */ 857 #define READ_SERDESCOMBO_5601X_MISC_IFr(_unit, _phy_ctrl, _val) \ 858 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 859 0x00, 0x0005, 0x1c, (_val)) 860 #define WRITE_SERDESCOMBO_5601X_MISC_IFr(_unit, _phy_ctrl, _val) \ 861 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 862 0x00, 0x0005, 0x1c, (_val)) 863 #define MODIFY_SERDESCOMBO_5601X_MISC_IFr(_unit, _phy_ctrl, _val, _mask) \ 864 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 865 0x00, 0x0005, 0x1c, (_val), (_mask)) 866 867 /* Misc Misc1 Reg (Addr 0x1D) */ 868 #define READ_SERDESCOMBO_5601X_MISC_MISC1r(_unit, _phy_ctrl, _val) \ 869 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 870 0x00, 0x0005, 0x1d, (_val)) 871 #define WRITE_SERDESCOMBO_5601X_MISC_MISC1r(_unit, _phy_ctrl, _val) \ 872 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 873 0x00, 0x0005, 0x1d, (_val)) 874 #define MODIFY_SERDESCOMBO_5601X_MISC_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 875 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 876 0x00, 0x0005, 0x1d, (_val), (_mask)) 877 878 /* Misc Misc2 Reg (Addr 0x1E) */ 879 #define READ_SERDESCOMBO_5601X_MISC_MISC2r(_unit, _phy_ctrl, _val) \ 880 SERDESCOMBO_5601X_REG_READ((_unit), (_phy_ctrl), \ 881 0x00, 0x0005, 0x1e, (_val)) 882 #define WRITE_SERDESCOMBO_5601X_MISC_MISC2r(_unit, _phy_ctrl, _val) \ 883 SERDESCOMBO_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 884 0x00, 0x0005, 0x1e, (_val)) 885 #define MODIFY_SERDESCOMBO_5601X_MISC_MISC2r(_unit, _phy_ctrl, _val, _mask) \ 886 SERDESCOMBO_5601X_REG_MODIFY((_unit), (_phy_ctrl), \ 887 0x00, 0x0005, 0x1e, (_val), (_mask)) 888 889 #define COMBO_MISC_MISC2_PLL_MODE_DIGITAL (1 << 1) /* (0)1.25Ghz, (1)3.125Ghz */ 890 #define COMBO_MISC_MISC2_PLL_MODE_ANALOG (1 << 0) /* (0)1.25Ghz, (1)3.125Ghz */ 891 892 #define PHY_SERDESCOMBO_5601X_STOP_MAC_DIS (0x01) 893 #define PHY_SERDESCOMBO_5601X_STOP_PHY_DIS (0x02) 894 #define PHY_SERDESCOMBO_5601X_STOP_DRAIN (0x04) 895 #define PHY_SERDESCOMBO_5601X_STOP_DUPLEX_CHG (0x08) 896 #define PHY_SERDESCOMBO_5601X_STOP_SPEED_CHG (0x10) 897 #define PHY_SERDESCOMBO_5601X_STOP_COPPER (0x20) 898 899 #endif /* _SERDES_COMBO_5601X_H_ */