serdes65lp.h (33852B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: serdes65LP.h 8 * Purpose: 65nm Internal (Quad/Octal/Dodeca) Serdes PHY Driver 9 */ 10 11 #ifndef _SERDES_65LP_H_ 12 #define _SERDES_65LP_H_ 13 14 /* 65LP SerDes register access */ 15 #define SERDES65LP_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 16 _reg_addr, _val) \ 17 phy_reg_serdes_read((_unit), (_phy_ctrl), (_reg_bank), \ 18 (_reg_addr), (_val)) 19 #define SERDES65LP_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 20 _reg_addr, _val) \ 21 phy_reg_serdes_write((_unit), (_phy_ctrl), (_reg_bank), \ 22 (_reg_addr), (_val)) 23 #define SERDES65LP_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 24 _reg_addr, _val, _mask) \ 25 phy_reg_serdes_modify((_unit), (_phy_ctrl), (_reg_bank), \ 26 (_reg_addr), (_val), (_mask)) 27 28 29 /***************************/ 30 /* Standard IEEE Registers */ 31 /***************************/ 32 33 /* MII Control (Addr 00h) */ 34 #define READ_SERDES65LP_MII_CTRLr(_unit, _phy_ctrl, _val) \ 35 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 36 0x00, 0x0000, 0x00, (_val)) 37 #define WRITE_SERDES65LP_MII_CTRLr(_unit, _phy_ctrl, _val) \ 38 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 39 0x00, 0x0000, 0x00, (_val)) 40 #define MODIFY_SERDES65LP_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 41 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 42 (_val), (_mask)) 43 44 /* MII Status (Addr 01h) */ 45 #define READ_SERDES65LP_MII_STATr(_unit, _phy_ctrl, _val) \ 46 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 47 0x00, 0x0000, 0x01, (_val)) 48 #define WRITE_SERDES65LP_MII_STATr(_unit, _phy_ctrl, _val) \ 49 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 50 0x00, 0x0000, 0x01, (_val)) 51 #define MODIFY_SERDES65LP_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 52 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 53 (_val), (_mask)) 54 55 /* PHY ID 0 (Addr 02h) */ 56 #define READ_SERDES65LP_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 57 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 58 0x00, 0x0000, 0x02, (_val)) 59 #define WRITE_SERDES65LP_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 60 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 61 0x00, 0x0000, 0x02, (_val)) 62 #define MODIFY_SERDES65LP_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 63 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 64 (_val), (_mask)) 65 66 /* PHY ID 1 (Addr 03h) */ 67 #define READ_SERDES65LP_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 68 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 69 0x00, 0x0000, 0x03, (_val)) 70 #define WRITE_SERDES65LP_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 71 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 72 0x00, 0x0000, 0x03, (_val)) 73 #define MODIFY_SERDES65LP_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 74 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 75 (_val), (_mask)) 76 77 /* Autoneg Adv (Addr 04h) */ 78 #define READ_SERDES65LP_MII_ANAr(_unit, _phy_ctrl, _val) \ 79 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 80 0x00, 0x0000, 0x04, (_val)) 81 #define WRITE_SERDES65LP_MII_ANAr(_unit, _phy_ctrl, _val) \ 82 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 83 0x00, 0x0000, 0x04, (_val)) 84 #define MODIFY_SERDES65LP_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 85 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 86 (_val), (_mask)) 87 88 /* Autoneg Link Partner Ability (Addr 05h) */ 89 #define READ_SERDES65LP_MII_ANPr(_unit, _phy_ctrl, _val) \ 90 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 91 0x00, 0x0000, 0x05, (_val)) 92 #define WRITE_SERDES65LP_MII_ANPr(_unit, _phy_ctrl, _val) \ 93 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 94 0x00, 0x0000, 0x05, (_val)) 95 #define MODIFY_SERDES65LP_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 96 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 97 (_val), (_mask)) 98 99 /* Autoneg Expansion (Addr 06h) */ 100 #define READ_SERDES65LP_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 101 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 102 0x00, 0x0000, 0x06, (_val)) 103 #define WRITE_SERDES65LP_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 104 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 105 0x00, 0x0000, 0x06, (_val)) 106 #define MODIFY_SERDES65LP_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 107 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 108 (_val), (_mask)) 109 110 /* Autoneg Next Page (Addr 07h) */ 111 /* Autoneg Link Partner Ability 2 (Addr 08h) */ 112 113 /* Extended Status (Addr 0fh) */ 114 #define READ_SERDES65LP_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 115 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 116 0x00, 0x0000, 0x0f, (_val)) 117 #define WRITE_SERDES65LP_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 118 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 119 0x00, 0x0000, 0x09, (_val)) 120 #define MODIFY_SERDES65LP_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 121 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 122 (_val), (_mask)) 123 124 /*************************/ 125 /* Digital Block (Blk 0) */ 126 /*************************/ 127 /* 1000X Control 1 (Addr 10h) */ 128 #define READ_SERDES65LP_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 129 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 130 0x00, 0x0000, 0x10, (_val)) 131 #define WRITE_SERDES65LP_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 132 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 133 0x00, 0x0000, 0x10, (_val)) 134 #define MODIFY_SERDES65LP_1000X_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 135 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 136 (_val), (_mask)) 137 138 /* 1000X Control 2 (Addr 11h) */ 139 #define READ_SERDES65LP_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 140 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 141 0x00, 0x0000, 0x11, (_val)) 142 #define WRITE_SERDES65LP_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 143 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 144 0x00, 0x0000, 0x11, (_val)) 145 #define MODIFY_SERDES65LP_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 146 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 147 (_val), (_mask)) 148 149 /* 1000X Control 3 (Addr 12h) */ 150 #define READ_SERDES65LP_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 151 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 152 0x00, 0x0000, 0x12, (_val)) 153 #define WRITE_SERDES65LP_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 154 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 155 0x00, 0x0000, 0x12, (_val)) 156 #define MODIFY_SERDES65LP_1000X_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 157 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x12, \ 158 (_val), (_mask)) 159 160 /* 1000X Control 4 (Addr 13h) */ 161 #define READ_SERDES65LP_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 162 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 163 0x00, 0x0000, 0x13, (_val)) 164 #define WRITE_SERDES65LP_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 165 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 166 0x00, 0x0000, 0x13, (_val)) 167 #define MODIFY_SERDES65LP_1000X_CTRL4r(_unit, _phy_ctrl, _val, _mask) \ 168 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x13, \ 169 (_val), (_mask)) 170 171 /* 1000X Status 1 (Addr 14h) */ 172 #define READ_SERDES65LP_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 173 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 174 0x00, 0x0000, 0x14, (_val)) 175 #define WRITE_SERDES65LP_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 176 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 177 0x00, 0x0000, 0x14, (_val)) 178 #define MODIFY_SERDES65LP_1000X_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 179 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x14, \ 180 (_val), (_mask)) 181 182 /* 1000X Status 2 (Addr 15h) */ 183 #define READ_SERDES65LP_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 184 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 185 0x00, 0x0000, 0x15, (_val)) 186 #define WRITE_SERDES65LP_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 187 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 188 0x00, 0x0000, 0x15, (_val)) 189 #define MODIFY_SERDES65LP_1000X_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 190 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x15, \ 191 (_val), (_mask)) 192 193 /* 1000X Status 3 (Addr 16h) */ 194 #define READ_SERDES65LP_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 195 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 196 0x00, 0x0000, 0x16, (_val)) 197 #define WRITE_SERDES65LP_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 198 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 199 0x00, 0x0000, 0x16, (_val)) 200 #define MODIFY_SERDES65LP_1000X_STAT3r(_unit, _phy_ctrl, _val, _mask) \ 201 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x16, \ 202 (_val), (_mask)) 203 204 /* Ber Crc Err Rx Pkt cntr (Addr 17h) */ 205 #define READ_SERDES65LP_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 206 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 207 0x00, 0x0000, 0x17, (_val)) 208 #define WRITE_SERDES65LP_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 209 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 210 0x00, 0x0000, 0x17, (_val)) 211 #define MODIFY_SERDES65LP_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 212 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x17, \ 213 (_val), (_mask)) 214 215 /* Prbs Control (Addr 18h) */ 216 #define READ_SERDES65LP_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 217 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 218 0x00, 0x0000, 0x18, (_val)) 219 #define WRITE_SERDES65LP_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 220 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 221 0x00, 0x0000, 0x18, (_val)) 222 #define MODIFY_SERDES65LP_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 223 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 224 (_val), (_mask)) 225 226 /* Prbs Status (Addr 19h) */ 227 #define READ_SERDES65LP_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 228 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 229 0x00, 0x0000, 0x19, (_val)) 230 #define WRITE_SERDES65LP_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 231 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 232 0x00, 0x0000, 0x19, (_val)) 233 #define MODIFY_SERDES65LP_1000X_PRBS_STATr(_unit, _phy_ctrl, _val, _mask) \ 234 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x19, \ 235 (_val), (_mask)) 236 237 /* Pat Gen Control (Addr 1Ah) */ 238 #define READ_SERDES65LP_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 239 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 240 0x00, 0x0000, 0x1a, (_val)) 241 #define WRITE_SERDES65LP_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 242 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 243 0x00, 0x0000, 0x1a, (_val)) 244 #define MODIFY_SERDES65LP_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 245 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1a, \ 246 (_val), (_mask)) 247 248 /* Pat Gen Status (Addr 1Bh) */ 249 #define READ_SERDES65LP_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 250 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 251 0x00, 0x0000, 0x1b, (_val)) 252 #define WRITE_SERDES65LP_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 253 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 254 0x00, 0x0000, 0x1b, (_val)) 255 #define MODIFY_SERDES65LP_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val, _mask) \ 256 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1b, \ 257 (_val), (_mask)) 258 259 /* Test Mode (Addr 1Ch) */ 260 #define READ_SERDES65LP_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 261 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 262 0x00, 0x0000, 0x1c, (_val)) 263 #define WRITE_SERDES65LP_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 264 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 265 0x00, 0x0000, 0x1c, (_val)) 266 #define MODIFY_SERDES65LP_1000X_TEST_MODEr(_unit, _phy_ctrl, _val, _mask) \ 267 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1c, \ 268 (_val), (_mask)) 269 270 /* Force Tx Data1 (Addr 1Dh) */ 271 #define READ_SERDES65LP_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 272 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 273 0x00, 0x0000, 0x1d, (_val)) 274 #define WRITE_SERDES65LP_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 275 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 276 0x00, 0x0000, 0x1d, (_val)) 277 #define MODIFY_SERDES65LP_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val, _mask) \ 278 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1d, \ 279 (_val), (_mask)) 280 281 /* Force Tx Data2 (Addr 1Eh) */ 282 #define READ_SERDES65LP_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 283 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 284 0x00, 0x0000, 0x1e, (_val)) 285 #define WRITE_SERDES65LP_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 286 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 287 0x00, 0x0000, 0x1e, (_val)) 288 #define MODIFY_SERDES65LP_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val, _mask) \ 289 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 290 (_val), (_mask)) 291 292 /* 1000X Control #1 Register: Controls 10B/SGMII mode */ 293 #define LP_1000X_FIBER_MODE (1 << 0) /* Enable SGMII fiber mode */ 294 #define LP_1000X_EN10B_MODE (1 << 1) /* Enable TBI 10B interface */ 295 #define LP_1000X_SIGNAL_DETECT_EN (1 << 2) /* Enable Signal Detect From Pin */ 296 #define LP_1000X_INVERT_SD (1 << 3) /* Invert Signal Detect */ 297 #define LP_1000X_AUTO_DETECT (1 << 4) /* Auto-detect SGMII and 1000X */ 298 #define LP_1000X_SGMII_MASTER (1 << 5) 299 #define LP_1000X_PLL_PWRDWN (1 << 6) 300 #define LP_1000X_RX_PKTS_CNTR_SEL (1 << 11) /* Select receive counter for 17h*/ 301 #define LP_1000X_TX_AMPLITUDE_OVRD (1 << 12) 302 303 /* 1000X Control #2 Register Fields */ 304 #define LP_1000X_PAR_DET_EN (1 << 0) /* Enable Parallel Detect */ 305 #define LP_1000X_FALSE_LNK_DIS (1 << 1) /* Disable false link */ 306 #define LP_1000X_FILTER_FORCE_EN (1 << 2) /* Enable filter force link */ 307 /* Allow packet to be transmitted regardless of the condition of the link */ 308 #define LP_1000X_FORCE_XMIT_DATA_ON_TXSIDE (1 << 5) 309 #define LP_1000X_CLRAR_BER_CNTR (1 << 14) /* Clear bit-err-rate counter */ 310 311 /* 1000X Control #3 Register Fields */ 312 #define LP_1000X_TX_FIFO_RST (1 << 0) /* Reset TX FIFO */ 313 #define LP_1000X_FIFO_ELASTICITY_MASK (0x3 << 1) /* Fifo Elasticity */ 314 #define LP_1000X_FIFO_ELASTICITY_5K (0x0 << 1) /* 5 Kbytes */ 315 #define LP_1000X_FIFO_ELASTICITY_10K (0x1 << 1) /* 10 Kbytes */ 316 #define LP_1000X_FIFO_ELASTICITY_13_5K (0x2 << 1) /* 13.5 Kbytes */ 317 #define LP_1000X_FREQ_LOCK_ELASTICITY_RX (1 << 6) 318 #define LP_1000X_FREQ_LOCK_ELASTICITY_TX (1 << 5) 319 #define LP_1000X_RX_FIFO_RST (1 << 14) /* Reset RX FIFO */ 320 321 /* 1000X Control #4 Register Fields */ 322 #define LP_1000X_LINK_FORCE (1 << 7) /* Link Force */ 323 #define LP_1000X_DIG_RESET (1 << 6) /* Reset Datapath */ 324 #define LP_1000X_ANALOG_SIG_DETECT (1 << 0) /* User analog signal det */ 325 326 /* 1000X Status #1 Register Fields */ 327 #define LP_1000X_STATUS1_SGMII_MODE (1 << 0) 328 #define LP_1000X_STATUS1_FULL_DUPLEX (1 << 2) 329 #define LP_1000X_STATUS1_SPEED (3 << 3) 330 #define LP_1000X_STATUS1_SPEED_10 (0) 331 #define LP_1000X_STATUS1_SPEED_100 (1 << 3) 332 #define LP_1000X_STATUS1_SPEED_1000 (1 << 4) 333 334 /***************************/ 335 /* SerDes ID Block (Blk 1) */ 336 /***************************/ 337 /* SerDes ID0 (Addr 10h) */ 338 #define READ_SERDES65LP_SERDES_ID0r(_unit, _phy_ctrl, _val) \ 339 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 340 0x00, 0x0001, 0x10, (_val)) 341 #define WRITE_SERDES65LP_SERDES_ID0r(_unit, _phy_ctrl, _val) \ 342 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 343 0x00, 0x0001, 0x10, (_val)) 344 #define MODIFY_SERDES65LP_SERDES_ID0r(_unit, _phy_ctrl, _val, _mask) \ 345 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x10, \ 346 (_val), (_mask)) 347 348 /* SerDes ID1 (Addr 11h) */ 349 #define READ_SERDES65LP_SERDES_ID1r(_unit, _phy_ctrl, _val) \ 350 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 351 0x00, 0x0001, 0x11, (_val)) 352 #define WRITE_SERDES65LP_SERDES_ID1r(_unit, _phy_ctrl, _val) \ 353 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 354 0x00, 0x0001, 0x11, (_val)) 355 #define MODIFY_SERDES65LP_SERDES_ID1r(_unit, _phy_ctrl, _val, _mask) \ 356 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x11, \ 357 (_val), (_mask)) 358 359 /* SerDes ID2 (Addr 12h) */ 360 #define READ_SERDES65LP_SERDES_ID2r(_unit, _phy_ctrl, _val) \ 361 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 362 0x00, 0x0001, 0x12, (_val)) 363 #define WRITE_SERDES65LP_SERDES_ID2r(_unit, _phy_ctrl, _val) \ 364 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 365 0x00, 0x0001, 0x12, (_val)) 366 #define MODIFY_SERDES65LP_SERDES_ID2r(_unit, _phy_ctrl, _val, _mask) \ 367 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x12, \ 368 (_val), (_mask)) 369 370 /* SerDes ID3 (Addr 13h) */ 371 #define READ_SERDES65LP_SERDES_ID3r(_unit, _phy_ctrl, _val) \ 372 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 373 0x00, 0x0001, 0x13, (_val)) 374 #define WRITE_SERDES65LP_SERDES_ID3r(_unit, _phy_ctrl, _val) \ 375 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 376 0x00, 0x0001, 0x13, (_val)) 377 #define MODIFY_SERDES65LP_SERDES_ID3r(_unit, _phy_ctrl, _val, _mask) \ 378 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x13, \ 379 (_val), (_mask)) 380 381 /* TPOUT 1 (Addr 18h) */ 382 #define READ_SERDES65LP_SERDES_TPOUT1r(_unit, _phy_ctrl, _val) \ 383 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 384 0x00, 0x0001, 0x18, (_val)) 385 #define WRITE_SERDES65LP_SERDES_TPOUT1r(_unit, _phy_ctrl, _val) \ 386 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 387 0x00, 0x0001, 0x18, (_val)) 388 #define MODIFY_SERDES65LP_SERDES_TPOUT1r(_unit, _phy_ctrl, _val, _mask) \ 389 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 390 (_val), (_mask)) 391 392 /* TPOUT 2 (Addr 19h) */ 393 #define READ_SERDES65LP_SERDES_TPOUT2r(_unit, _phy_ctrl, _val) \ 394 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 395 0x00, 0x0001, 0x19, (_val)) 396 #define WRITE_SERDES65LP_SERDES_TPOUT2r(_unit, _phy_ctrl, _val) \ 397 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 398 0x00, 0x0001, 0x19, (_val)) 399 #define MODIFY_SERDES65LP_SERDES_TPOUT2r(_unit, _phy_ctrl, _val, _mask) \ 400 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x19, \ 401 (_val), (_mask)) 402 403 /**************************/ 404 /* FX100 Block (Block 2) */ 405 /**************************/ 406 407 /* FXControl 1 Register (Addr 0x10) */ 408 #define READ_SERDES65LP_FX100_CTRL1r(_unit, _phy_ctrl, _val) \ 409 SERDES65LP_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x10, \ 410 (_val)) 411 #define WRITE_SERDES65LP_FX100_CTRL1r(_unit, _phy_ctrl, _val) \ 412 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x10, \ 413 (_val)) 414 #define MODIFY_SERDES65LP_FX100_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 415 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), \ 416 0x00, 0x0002, 0x10, (_val), (_mask)) 417 418 /* FXControl 2 Register (Addr 0x11) */ 419 #define READ_SERDES65LP_FX100_CTRL2r(_unit, _phy_ctrl, _val) \ 420 SERDES65LP_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x11, \ 421 (_val)) 422 #define WRITE_SERDES65LP_FX100_CTRL2r(_unit, _phy_ctrl, _val) \ 423 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x11, \ 424 (_val)) 425 #define MODIFY_SERDES65LP_FX100_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 426 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), \ 427 0x00, 0x0002, 0x11, (_val), (_mask)) 428 429 /* FXControl 3 Register (Addr 0x12) */ 430 #define READ_SERDES65LP_FX100_CTRL3r(_unit, _phy_ctrl, _val) \ 431 SERDES65LP_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x12, \ 432 (_val)) 433 #define WRITE_SERDES65LP_FX100_CTRL3r(_unit, _phy_ctrl, _val) \ 434 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x12, \ 435 (_val)) 436 #define MODIFY_SERDES65LP_FX100_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 437 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), \ 438 0x00, 0x0002, 0x12, (_val), (_mask)) 439 440 /* FXStatus 1 Register (Addr 0x13) */ 441 #define READ_SERDES65LP_FX100_STAT1r(_unit, _phy_ctrl, _val) \ 442 SERDES65LP_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x13, \ 443 (_val)) 444 #define WRITE_SERDES65LP_FX100_STAT1r(_unit, _phy_ctrl, _val) \ 445 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x13, \ 446 (_val)) 447 #define MODIFY_SERDES65LP_FX100_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 448 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), \ 449 0x00, 0x0002, 0x13, (_val), (_mask)) 450 451 /* FXStatus 2 Register (Addr 0x14) */ 452 #define READ_SERDES65LP_FX100_STAT2r(_unit, _phy_ctrl, _val) \ 453 SERDES65LP_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 454 (_val)) 455 #define WRITE_SERDES65LP_FX100_STAT2r(_unit, _phy_ctrl, _val) \ 456 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 457 (_val)) 458 #define MODIFY_SERDES65LP_FX100_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 459 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), \ 460 0x00, 0x0002, 0x14, (_val), (_mask)) 461 462 /* FXStatus 2 Register (Addr 0x14) */ 463 #define READ_SERDES65LP_FX100_STAT2r(_unit, _phy_ctrl, _val) \ 464 SERDES65LP_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 465 (_val)) 466 #define WRITE_SERDES65LP_FX100_STAT2r(_unit, _phy_ctrl, _val) \ 467 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 468 (_val)) 469 #define MODIFY_SERDES65LP_FX100_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 470 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), \ 471 0x00, 0x0002, 0x14, (_val), (_mask)) 472 473 /* FXStatus 3 Register (Addr 0x14) */ 474 #define READ_SERDES65LP_FX100_STAT3r(_unit, _phy_ctrl, _val) \ 475 SERDES65LP_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 476 (_val)) 477 #define WRITE_SERDES65LP_FX100_STAT3r(_unit, _phy_ctrl, _val) \ 478 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 479 (_val)) 480 #define MODIFY_SERDES65LP_FX100_STAT3r(_unit, _phy_ctrl, _val, _mask) \ 481 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), \ 482 0x00, 0x0002, 0x14, (_val), (_mask)) 483 484 /* FXStatus 4 Register (Addr 0x14) */ 485 #define READ_SERDES65LP_FX100_STAT4r(_unit, _phy_ctrl, _val) \ 486 SERDES65LP_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 487 (_val)) 488 #define WRITE_SERDES65LP_FX100_STAT4r(_unit, _phy_ctrl, _val) \ 489 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 490 (_val)) 491 #define MODIFY_SERDES65LP_FX100_STAT4r(_unit, _phy_ctrl, _val, _mask) \ 492 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), \ 493 0x00, 0x0002, 0x14, (_val), (_mask)) 494 495 /* 100FX Control 1 Register Fields */ 496 #define LP_FX100_CONTROL1_EN (1 << 0) /* Enable 65LP */ 497 #define LP_FX100_CONTROL1_FD (1 << 1) /* 65LP full duplex */ 498 #define LP_FX100_CONTROL1_AUTO_DET (1 << 2) /* Auto detect 499 65LP/1000X */ 500 #define LP_FX100_CTRL1_PWRDWN_WAKEUP_250ms (1 << 14) 501 #define LP_FX100_CTRL1_PWRDWN_PERIOD_3SEC (1 << 13) 502 #define LP_FX100_CTRL1_AUTO_PWRDWN_EN (1 << 12) 503 504 505 /* 100FX Control 2 Register Fields */ 506 #define LP_FX100_CONTROL2_EXT_PKT_SZ (1 << 0) /* Allow pkt sz > 9k*/ 507 508 /* 100FX Control 3 Register Fields */ 509 #define LP_FX100_CONTROL3_FAST_TIMER (1 << 0) 510 511 /************************/ 512 /* Analog Block (Blk 3) */ 513 /************************/ 514 /* Analog Tx 1 (Addr 10h) */ 515 #define READ_SERDES65LP_ANALOG_TX1r(_unit, _phy_ctrl, _val) \ 516 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 517 0x00, 0x0003, 0x10, (_val)) 518 #define WRITE_SERDES65LP_ANALOG_TX1r(_unit, _phy_ctrl, _val) \ 519 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 520 0x00, 0x0003, 0x10, (_val)) 521 #define MODIFY_SERDES65LP_ANALOG_TX1r(_unit, _phy_ctrl, _val, _mask) \ 522 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x10, \ 523 (_val), (_mask)) 524 525 /* Analog Tx 2 (Addr 11h) */ 526 #define READ_SERDES65LP_ANALOG_TX2r(_unit, _phy_ctrl, _val) \ 527 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 528 0x00, 0x0003, 0x11, (_val)) 529 #define WRITE_SERDES65LP_ANALOG_TX2r(_unit, _phy_ctrl, _val) \ 530 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 531 0x00, 0x0003, 0x11, (_val)) 532 #define MODIFY_SERDES65LP_ANALOG_TX2r(_unit, _phy_ctrl, _val, _mask) \ 533 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x11, \ 534 (_val), (_mask)) 535 536 /* Analog Tx Amp (Addr 12h) */ 537 #define READ_SERDES65LP_ANALOG_TX_AMPr(_unit, _phy_ctrl, _val) \ 538 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 539 0x00, 0x0003, 0x12, (_val)) 540 #define WRITE_SERDES65LP_ANALOG_TX_AMPr(_unit, _phy_ctrl, _val) \ 541 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 542 0x00, 0x0003, 0x12, (_val)) 543 #define MODIFY_SERDES65LP_ANALOG_TX_AMPr(_unit, _phy_ctrl, _val, _mask) \ 544 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x12, \ 545 (_val), (_mask)) 546 547 548 /* Analog RX1 (Addr 13h) */ 549 #define READ_SERDES65LP_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 550 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 551 0x00, 0x0003, 0x13, (_val)) 552 #define WRITE_SERDES65LP_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 553 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 554 0x00, 0x0003, 0x13, (_val)) 555 #define MODIFY_SERDES65LP_ANALOG_RX1r(_unit, _phy_ctrl, _val, _mask) \ 556 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x13, \ 557 (_val), (_mask)) 558 559 /* Analog RX2 (Addr 14h) */ 560 #define READ_SERDES65LP_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 561 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 562 0x00, 0x0003, 0x14, (_val)) 563 #define WRITE_SERDES65LP_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 564 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 565 0x00, 0x0003, 0x14, (_val)) 566 #define MODIFY_SERDES65LP_ANALOG_RX2r(_unit, _phy_ctrl, _val, _mask) \ 567 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x14, \ 568 (_val), (_mask)) 569 570 /* Analog RX3 (Addr 15h) */ 571 #define READ_SERDES65LP_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 572 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 573 0x00, 0x0003, 0x15, (_val)) 574 #define WRITE_SERDES65LP_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 575 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 576 0x00, 0x0003, 0x15, (_val)) 577 #define MODIFY_SERDES65LP_ANALOG_RX3r(_unit, _phy_ctrl, _val, _mask) \ 578 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x15, \ 579 (_val), (_mask)) 580 581 /* Analog RX4 (Addr 16h) */ 582 #define READ_SERDES65LP_ANALOG_RX4r(_unit, _phy_ctrl, _val) \ 583 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 584 0x00, 0x0003, 0x16, (_val)) 585 #define WRITE_SERDES65LP_ANALOG_RX4r(_unit, _phy_ctrl, _val) \ 586 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 587 0x00, 0x0003, 0x16, (_val)) 588 #define MODIFY_SERDES65LP_ANALOG_RX4r(_unit, _phy_ctrl, _val, _mask) \ 589 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x16, \ 590 (_val), (_mask)) 591 592 /* Analog PLL 1 (Addr 18h) */ 593 #define READ_SERDES65LP_ANALOG_PLL1r(_unit, _phy_ctrl, _val) \ 594 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 595 0x00, 0x0003, 0x18, (_val)) 596 #define WRITE_SERDES65LP_ANALOG_PLL1r(_unit, _phy_ctrl, _val) \ 597 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 598 0x00, 0x0003, 0x18, (_val)) 599 #define MODIFY_SERDES65LP_ANALOG_PLL1r(_unit, _phy_ctrl, _val, _mask) \ 600 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x18, \ 601 (_val), (_mask)) 602 603 /* Analog PLL 2 (Addr 19h) */ 604 #define READ_SERDES65LP_ANALOG_PLL2r(_unit, _phy_ctrl, _val) \ 605 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 606 0x00, 0x0003, 0x19, (_val)) 607 #define WRITE_SERDES65LP_ANALOG_PLL2r(_unit, _phy_ctrl, _val) \ 608 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 609 0x00, 0x0003, 0x19, (_val)) 610 #define MODIFY_SERDES65LP_ANALOG_PLL2r(_unit, _phy_ctrl, _val, _mask) \ 611 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x19, \ 612 (_val), (_mask)) 613 614 /* Analog PLL 3 (Addr 1Ah) */ 615 #define READ_SERDES65LP_ANALOG_PLL3r(_unit, _phy_ctrl, _val) \ 616 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 617 0x00, 0x0003, 0x1A, (_val)) 618 #define WRITE_SERDES65LP_ANALOG_PLL3r(_unit, _phy_ctrl, _val) \ 619 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 620 0x00, 0x0003, 0x1A, (_val)) 621 #define MODIFY_SERDES65LP_ANALOG_PLL3r(_unit, _phy_ctrl, _val, _mask) \ 622 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1A, \ 623 (_val), (_mask)) 624 625 /* Analog PLL 4 (Addr 1Bh) */ 626 #define READ_SERDES65LP_ANALOG_PLL4r(_unit, _phy_ctrl, _val) \ 627 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 628 0x00, 0x0003, 0x1B, (_val)) 629 #define WRITE_SERDES65LP_ANALOG_PLL4r(_unit, _phy_ctrl, _val) \ 630 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 631 0x00, 0x0003, 0x1B, (_val)) 632 #define MODIFY_SERDES65LP_ANALOG_PLL4r(_unit, _phy_ctrl, _val, _mask) \ 633 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1B, \ 634 (_val), (_mask)) 635 636 /* Analog Misc (Addr 1Ch) */ 637 #define READ_SERDES65LP_ANALOG_MISCr(_unit, _phy_ctrl, _val) \ 638 SERDES65LP_REG_READ((_unit), (_phy_ctrl), \ 639 0x00, 0x0003, 0x1C, (_val)) 640 #define WRITE_SERDES65LP_ANALOG_MISCr(_unit, _phy_ctrl, _val) \ 641 SERDES65LP_REG_WRITE((_unit), (_phy_ctrl), \ 642 0x00, 0x0003, 0x1C, (_val)) 643 #define MODIFY_SERDES65LP_ANALOG_MISCr(_unit, _phy_ctrl, _val, _mask) \ 644 SERDES65LP_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1C, \ 645 (_val), (_mask)) 646 647 #endif /* _SERDES_65LP_H_ */