serdes100fx.h (28191B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: serdes100fx.h 8 * Purpose: (FB2) Internal Dodeca Serdes PHY Driver 9 */ 10 11 #ifndef _SERDES_100FX_H_ 12 #define _SERDES_100FX_H_ 13 14 #include <soc/phy.h> 15 16 /* If application want to use this header file for accessing PHY registers, 17 * simply redefine SERDES100FX_REG macros to use BCM API as follows. 18 * 19 * #define SERDES100FX_REG_READ(_unit, _port, _flags, _reg_bank, 20 * _reg_addr, _val) \ 21 * bcm_port_phy_get((_unit), (_port), 0, 22 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 23 * (_val)) 24 * 25 * #define SERDES100FX_REG_WRITE(_unit, _port, _flags, _reg_bank, 26 * _reg_addr, _val) \ 27 * bcm_port_phy_set((_unit), (_port), 0, 28 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 29 * (_val)) 30 * 31 * #define SERDES100FX_REG_MODIFY(_unit, _port, _flags, \ 32 * _reg_bank, _reg_addr, _val)\ 33 * do { \ 34 * return BCM_E_UNAVAIL; \ 35 * } while(0) 36 */ 37 38 /* 100FX SerDes register access */ 39 #define SERDES100FX_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 40 _reg_addr, _val) \ 41 phy_reg_serdes_read((_unit), (_phy_ctrl), (_reg_bank), \ 42 (_reg_addr), (_val)) 43 #define SERDES100FX_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 44 _reg_addr, _val) \ 45 phy_reg_serdes_write((_unit), (_phy_ctrl), (_reg_bank), \ 46 (_reg_addr), (_val)) 47 #define SERDES100FX_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 48 _reg_addr, _val, _mask) \ 49 phy_reg_serdes_modify((_unit), (_phy_ctrl), (_reg_bank), \ 50 (_reg_addr), (_val), (_mask)) 51 52 53 /* 54 * Definitions for Internal SerDes 10/100/1000 PHY 55 */ 56 57 /* MII Control Register */ 58 59 /* 100FX: MII Control bit definitions, same as Standard 10/100 PHY */ 60 #define FX_MII_CTRL_RESET MII_CTRL_RESET /* Self clearing SW reset */ 61 #define FX_MII_CTRL_SS_LSB MII_CTRL_SS_LSB /* Speed Select, LSB */ 62 #define FX_MII_CTRL_SS_MSB MII_CTRL_SS_MSB /* Speed Select, MSB */ 63 #define FX_MII_CTRL_SS(_x) MII_CTRL_SS(_x) 64 #define FX_MII_CTRL_SS_10 MII_CTRL_SS_10 65 #define FX_MII_CTRL_SS_100 MII_CTRL_SS_100 66 #define FX_MII_CTRL_SS_1000 MII_CTRL_SS_1000 67 #define FX_MII_CTRL_SS_INVALID MII_CTRL_SS_INVALID 68 #define FX_MII_CTRL_SS_MASK MII_CTRL_SS_MASK 69 #define FX_MII_CTRL_FD MII_CTRL_FD /* Full Duplex */ 70 #define FX_MII_CTRL_AN_RESTART (1 << 9) /* Auto Negotiation Enable */ 71 #define FX_MII_CTRL_AN_ENABLE (1 << 12) /* Auto Negotiation Enable */ 72 #define FX_MII_CTRL_PD MII_CTRL_PD /* Power Down Enable */ 73 #define FX_MII_CTRL_LOOPBACK (1 << 14) /* Loopback Enable */ 74 75 /* MII Status Register */ 76 /* 100FX: MII Status Register: not the same as standard 10/100 PHY */ 77 #define FX_MII_STAT_RF MII_STAT_RF /* Remote fault */ 78 #define FX_MII_STAT_LA MII_STAT_LA /* Link Up */ 79 #define FX_MII_STAT_AN_COMPLETE (1 << 5) /* AN complete */ 80 81 /* Bit defines for ANA register */ 82 #define FX_MII_ANA_HD (1 << 6) 83 #define FX_MII_ANA_FD (1 << 5) 84 #define FX_MII_ANA_PAUSE_NONE (0 << 7) 85 #define FX_MII_ANA_PAUSE_SYM (1 << 7) 86 #define FX_MII_ANA_PAUSE_ASYM (1 << 8) 87 #define FX_MII_ANA_PAUSE_MASK (3 << 7) 88 89 /* Auto-Negotiation Link-Partner Ability Register */ 90 91 #define FX_MII_ANP_FIBER_NEXT_PG (1 << 15) 92 #define FX_MII_ANP_FIBER_ACK (1 << 14) 93 #define FX_MII_ANP_FIBER_RF_SHFT (12) /* Remote fault */ 94 #define FX_MII_ANP_FIBER_RF_MASK (0x3000) 95 #define FX_MII_ANP_FIBER_PAUSE_ASYM (1 << 8) 96 #define FX_MII_ANP_FIBER_PAUSE_SYM (1 << 7) 97 #define FX_MII_ANP_FIBER_HD (1 << 6) 98 #define FX_MII_ANP_FIBER_FD (1 << 5) 99 100 #define FX_MII_ANP_SGMII (1 << 0) 101 #define FX_MII_ANP_SGMII_DUPLEX (1 << 12) 102 #define FX_MII_ANP_SGMII_SPEED (3 << 10) 103 #define FX_MII_ANP_SGMII_SPEED_10 (0) 104 #define FX_MII_ANP_SGMII_SPEED_100 (1 << 10) 105 #define FX_MII_ANP_SGMII_SPEED_1000 (1 << 11) 106 107 /* Auto-Negotiation Expansion Register */ 108 #define FX_ANA_EXPANSION_PR (1 << 1) /* Page received */ 109 110 /***************************/ 111 /* Standard IEEE Registers */ 112 /***************************/ 113 114 /* MII Control (Addr 00h) */ 115 #define READ_SERDES100FX_MII_CTRLr(_unit, _phy_ctrl, _val) \ 116 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 117 0x00, 0x0000, 0x00, (_val)) 118 #define WRITE_SERDES100FX_MII_CTRLr(_unit, _phy_ctrl, _val) \ 119 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 120 0x00, 0x0000, 0x00, (_val)) 121 #define MODIFY_SERDES100FX_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 122 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 123 (_val), (_mask)) 124 125 /* MII Status (Addr 01h) */ 126 #define READ_SERDES100FX_MII_STATr(_unit, _phy_ctrl, _val) \ 127 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 128 0x00, 0x0000, 0x01, (_val)) 129 #define WRITE_SERDES100FX_MII_STATr(_unit, _phy_ctrl, _val) \ 130 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 131 0x00, 0x0000, 0x01, (_val)) 132 #define MODIFY_SERDES100FX_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 133 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 134 (_val), (_mask)) 135 136 /* PHY ID 0 (Addr 02h) */ 137 #define READ_SERDES100FX_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 138 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 139 0x00, 0x0000, 0x02, (_val)) 140 #define WRITE_SERDES100FX_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 141 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 142 0x00, 0x0000, 0x02, (_val)) 143 #define MODIFY_SERDES100FX_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 144 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 145 (_val), (_mask)) 146 147 /* PHY ID 1 (Addr 03h) */ 148 #define READ_SERDES100FX_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 149 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 150 0x00, 0x0000, 0x03, (_val)) 151 #define WRITE_SERDES100FX_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 152 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 153 0x00, 0x0000, 0x03, (_val)) 154 #define MODIFY_SERDES100FX_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 155 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 156 (_val), (_mask)) 157 158 /* Autoneg Adv (Addr 04h) */ 159 #define READ_SERDES100FX_MII_ANAr(_unit, _phy_ctrl, _val) \ 160 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 161 0x00, 0x0000, 0x04, (_val)) 162 #define WRITE_SERDES100FX_MII_ANAr(_unit, _phy_ctrl, _val) \ 163 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 164 0x00, 0x0000, 0x04, (_val)) 165 #define MODIFY_SERDES100FX_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 166 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 167 (_val), (_mask)) 168 169 /* Autoneg Link Partner Ability (Addr 05h) */ 170 #define READ_SERDES100FX_MII_ANPr(_unit, _phy_ctrl, _val) \ 171 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 172 0x00, 0x0000, 0x05, (_val)) 173 #define WRITE_SERDES100FX_MII_ANPr(_unit, _phy_ctrl, _val) \ 174 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 175 0x00, 0x0000, 0x05, (_val)) 176 #define MODIFY_SERDES100FX_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 177 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 178 (_val), (_mask)) 179 180 /* Autoneg Expansion (Addr 06h) */ 181 #define READ_SERDES100FX_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 182 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 183 0x00, 0x0000, 0x06, (_val)) 184 #define WRITE_SERDES100FX_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 185 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 186 0x00, 0x0000, 0x06, (_val)) 187 #define MODIFY_SERDES100FX_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 188 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 189 (_val), (_mask)) 190 191 /* Extended Status (Addr 0fh) */ 192 193 /*************************/ 194 /* Digital Block (Blk 0) */ 195 /*************************/ 196 /* 1000X Control 1 (Addr 10h) */ 197 #define READ_SERDES100FX_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 198 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 199 0x00, 0x0000, 0x10, (_val)) 200 #define WRITE_SERDES100FX_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 201 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 202 0x00, 0x0000, 0x10, (_val)) 203 #define MODIFY_SERDES100FX_1000X_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 204 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 205 (_val), (_mask)) 206 207 /* 1000X Control 2 (Addr 11h) */ 208 #define READ_SERDES100FX_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 209 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 210 0x00, 0x0000, 0x11, (_val)) 211 #define WRITE_SERDES100FX_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 212 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 213 0x00, 0x0000, 0x11, (_val)) 214 #define MODIFY_SERDES100FX_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 215 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 216 (_val), (_mask)) 217 218 /* 1000X Control 3 (Addr 12h) */ 219 #define READ_SERDES100FX_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 220 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 221 0x00, 0x0000, 0x12, (_val)) 222 #define WRITE_SERDES100FX_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 223 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 224 0x00, 0x0000, 0x12, (_val)) 225 #define MODIFY_SERDES100FX_1000X_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 226 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x12, \ 227 (_val), (_mask)) 228 229 /* 1000X Control 4 (Addr 13h) */ 230 #define READ_SERDES100FX_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 231 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 232 0x00, 0x0000, 0x13, (_val)) 233 #define WRITE_SERDES100FX_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 234 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 235 0x00, 0x0000, 0x13, (_val)) 236 #define MODIFY_SERDES100FX_1000X_CTRL4r(_unit, _phy_ctrl, _val, _mask) \ 237 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x13, \ 238 (_val), (_mask)) 239 240 /* 1000X Status 1 (Addr 14h) */ 241 #define READ_SERDES100FX_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 242 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 243 0x00, 0x0000, 0x14, (_val)) 244 #define WRITE_SERDES100FX_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 245 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 246 0x00, 0x0000, 0x14, (_val)) 247 #define MODIFY_SERDES100FX_1000X_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 248 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x14, \ 249 (_val), (_mask)) 250 251 /* 1000X Status 2 (Addr 15h) */ 252 #define READ_SERDES100FX_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 253 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 254 0x00, 0x0000, 0x15, (_val)) 255 #define WRITE_SERDES100FX_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 256 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 257 0x00, 0x0000, 0x15, (_val)) 258 #define MODIFY_SERDES100FX_1000X_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 259 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x15, \ 260 (_val), (_mask)) 261 262 /* 1000X Status 3 (Addr 16h) */ 263 #define READ_SERDES100FX_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 264 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 265 0x00, 0x0000, 0x16, (_val)) 266 #define WRITE_SERDES100FX_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 267 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 268 0x00, 0x0000, 0x16, (_val)) 269 #define MODIFY_SERDES100FX_1000X_STAT3r(_unit, _phy_ctrl, _val, _mask) \ 270 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x16, \ 271 (_val), (_mask)) 272 273 /* Ber Crc Err Rx Pkt cntr (Addr 17h) */ 274 #define READ_SERDES100FX_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 275 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 276 0x00, 0x0000, 0x17, (_val)) 277 #define WRITE_SERDES100FX_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 278 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 279 0x00, 0x0000, 0x17, (_val)) 280 #define MODIFY_SERDES100FX_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 281 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x17, \ 282 (_val), (_mask)) 283 284 /* Prbs Control (Addr 18h) */ 285 #define READ_SERDES100FX_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 286 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 287 0x00, 0x0000, 0x18, (_val)) 288 #define WRITE_SERDES100FX_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 289 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 290 0x00, 0x0000, 0x18, (_val)) 291 #define MODIFY_SERDES100FX_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 292 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 293 (_val), (_mask)) 294 295 /* Prbs Status (Addr 19h) */ 296 #define READ_SERDES100FX_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 297 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 298 0x00, 0x0000, 0x19, (_val)) 299 #define WRITE_SERDES100FX_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 300 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 301 0x00, 0x0000, 0x19, (_val)) 302 #define MODIFY_SERDES100FX_1000X_PRBS_STATr(_unit, _phy_ctrl, _val, _mask) \ 303 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x19, \ 304 (_val), (_mask)) 305 306 /* Pat Gen Control (Addr 1Ah) */ 307 #define READ_SERDES100FX_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 308 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 309 0x00, 0x0000, 0x1a, (_val)) 310 #define WRITE_SERDES100FX_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 311 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 312 0x00, 0x0000, 0x1a, (_val)) 313 #define MODIFY_SERDES100FX_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 314 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1a, \ 315 (_val), (_mask)) 316 317 /* Pat Gen Status (Addr 1Bh) */ 318 #define READ_SERDES100FX_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 319 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 320 0x00, 0x0000, 0x1b, (_val)) 321 #define WRITE_SERDES100FX_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 322 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 323 0x00, 0x0000, 0x1b, (_val)) 324 #define MODIFY_SERDES100FX_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val, _mask) \ 325 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1b, \ 326 (_val), (_mask)) 327 328 /* Test Mode (Addr 1Ch) */ 329 #define READ_SERDES100FX_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 330 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 331 0x00, 0x0000, 0x1c, (_val)) 332 #define WRITE_SERDES100FX_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 333 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 334 0x00, 0x0000, 0x1c, (_val)) 335 #define MODIFY_SERDES100FX_1000X_TEST_MODEr(_unit, _phy_ctrl, _val, _mask) \ 336 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1c, \ 337 (_val), (_mask)) 338 339 /* Force Tx Data1 (Addr 1Dh) */ 340 #define READ_SERDES100FX_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 341 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 342 0x00, 0x0000, 0x1d, (_val)) 343 #define WRITE_SERDES100FX_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 344 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 345 0x00, 0x0000, 0x1d, (_val)) 346 #define MODIFY_SERDES100FX_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val, _mask) \ 347 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1d, \ 348 (_val), (_mask)) 349 350 /* Force Tx Data2 (Addr 1Eh) */ 351 #define READ_SERDES100FX_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 352 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 353 0x00, 0x0000, 0x1e, (_val)) 354 #define WRITE_SERDES100FX_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 355 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 356 0x00, 0x0000, 0x1e, (_val)) 357 #define MODIFY_SERDES100FX_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val, _mask) \ 358 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 359 (_val), (_mask)) 360 361 /* 1000X Control #1 Register: Controls 10B/SGMII mode */ 362 #define FX_1000X_FIBER_MODE (1 << 0) /* Enable SGMII fiber mode */ 363 #define FX_1000X_EN10B_MODE (1 << 1) /* Enable TBI 10B interface */ 364 #define FX_1000X_INVERT_SD (1 << 3) /* Invert Signal Detect */ 365 #define FX_1000X_AUTO_DETECT (1 << 4) /* Auto-detect SGMII and 1000X */ 366 #define FX_1000X_SGMII_MASTER (1 << 5) /* SGMII Master mode enable */ 367 #define FX_1000X_RX_PKTS_CNTR_SEL (1 << 11) /* Select receive counter for 17h*/ 368 #define FX_1000X_TX_AMPLITUDE_OVRD (1 << 12) 369 370 /* 1000X Control #2 Register Fields */ 371 #define FX_1000X_PAR_DET_EN (1 << 0) /* Enable Parallel Detect */ 372 #define FX_1000X_FALSE_LNK_DIS (1 << 1) /* Disable false link */ 373 #define FX_1000X_FLT_FORCE_EN (1 << 2) /* Enable filter force link */ 374 #define FX_1000X_FORCE_XMIT_TX (1 << 5) /* Force xmit on tx side */ 375 #define FX_1000X_CLRAR_BER_CNTR (1 << 14) /* Clear bit-err-rate counter */ 376 377 /* 1000X Control #3 Register Fields */ 378 #define FX_1000X_TX_FIFO_RST (1 << 0) /* Reset TX FIFO */ 379 #define FX_1000X_FIFO_ELASTICITY_MASK (0x3 << 1) /* Fifo Elasticity */ 380 #define FX_1000X_FIFO_ELASTICITY_5K (0x0 << 1) /* 5 Kbytes */ 381 #define FX_1000X_FIFO_ELASTICITY_10K (0x1 << 1) /* 10 Kbytes */ 382 #define FX_1000X_FIFO_ELASTICITY_13_5K (0x2 << 1) /* 13.5 Kbytes */ 383 #define FX_1000X_RX_FIFO_RST (1 << 14) /* Reset RX FIFO */ 384 385 /* 1000X Control #4 Register Fields */ 386 #define FX_1000X_LINK_FORCE (1 << 7) /* Link Force */ 387 #define FX_1000X_DIG_RESET (1 << 6) /* Reset Datapath */ 388 #define FX_1000X_ANALOG_SIG_DETECT (1 << 0) /* User analog signal det */ 389 390 391 /* 1000X Status #1 Register Fields */ 392 #define FX_1000X_STATUS1_SGMII_MODE (1 << 0) 393 #define FX_1000X_STATUS1_FULL_DUPLEX (1 << 2) 394 #define FX_1000X_STATUS1_SPEED (3 << 3) 395 #define FX_1000X_STATUS1_SPEED_10 (0) 396 #define FX_1000X_STATUS1_SPEED_100 (1 << 3) 397 #define FX_1000X_STATUS1_SPEED_1000 (1 << 4) 398 399 400 /************************/ 401 /* Analog Block (Blk 1) */ 402 /************************/ 403 /* Analog Tx (Addr 10h) */ 404 #define READ_SERDES100FX_ANALOG_TXr(_unit, _phy_ctrl, _val) \ 405 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 406 0x00, 0x0001, 0x10, (_val)) 407 #define WRITE_SERDES100FX_ANALOG_TXr(_unit, _phy_ctrl, _val) \ 408 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 409 0x00, 0x0001, 0x10, (_val)) 410 #define MODIFY_SERDES100FX_ANALOG_TXr(_unit, _phy_ctrl, _val, _mask) \ 411 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x10, \ 412 (_val), (_mask)) 413 414 /* Analog RX1 (Addr 11h) */ 415 #define READ_SERDES100FX_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 416 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 417 0x00, 0x0001, 0x11, (_val)) 418 #define WRITE_SERDES100FX_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 419 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 420 0x00, 0x0001, 0x11, (_val)) 421 #define MODIFY_SERDES100FX_ANALOG_RX1r(_unit, _phy_ctrl, _val, _mask) \ 422 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x11, \ 423 (_val), (_mask)) 424 425 /* Analog RX2 (Addr 12h) */ 426 #define READ_SERDES100FX_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 427 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 428 0x00, 0x0001, 0x12, (_val)) 429 #define WRITE_SERDES100FX_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 430 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 431 0x00, 0x0001, 0x12, (_val)) 432 #define MODIFY_SERDES100FX_ANALOG_RX2r(_unit, _phy_ctrl, _val, _mask) \ 433 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x12, \ 434 (_val), (_mask)) 435 436 /* Analog PLL (Addr 13h) */ 437 #define READ_SERDES100FX_ANALOG_PLLr(_unit, _phy_ctrl, _val) \ 438 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 439 0x00, 0x0001, 0x13, (_val)) 440 #define WRITE_SERDES100FX_ANALOG_PLLr(_unit, _phy_ctrl, _val) \ 441 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 442 0x00, 0x0001, 0x13, (_val)) 443 #define MODIFY_SERDES100FX_ANALOG_PLLr(_unit, _phy_ctrl, _val, _mask) \ 444 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x13, \ 445 (_val), (_mask)) 446 447 /* Analog RX3 (Addr 14h) */ 448 #define READ_SERDES100FX_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 449 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 450 0x00, 0x0001, 0x14, (_val)) 451 #define WRITE_SERDES100FX_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 452 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 453 0x00, 0x0001, 0x14, (_val)) 454 #define MODIFY_SERDES100FX_ANALOG_RX3r(_unit, _phy_ctrl, _val, _mask) \ 455 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x14, \ 456 (_val), (_mask)) 457 458 /* TPOUT1 (Addr 18h) */ 459 #define READ_SERDES100FX_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val) \ 460 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 461 0x00, 0x0001, 0x18, (_val)) 462 #define WRITE_SERDES100FX_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val) \ 463 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 464 0x00, 0x0001, 0x18, (_val)) 465 #define MODIFY_SERDES100FX_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val, _mask) \ 466 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 467 (_val), (_mask)) 468 469 /* TPOUT2 (Addr 19h) */ 470 #define READ_SERDES100FX_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val) \ 471 SERDES100FX_REG_READ((_unit), (_phy_ctrl), \ 472 0x00, 0x0001, 0x19, (_val)) 473 #define WRITE_SERDES100FX_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val) \ 474 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), \ 475 0x00, 0x0001, 0x19, (_val)) 476 #define MODIFY_SERDES100FX_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val, _mask) \ 477 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x19, \ 478 (_val), (_mask)) 479 480 /* Analog Rx 1 Register Fields */ 481 #define FX_ANALOG_RX1_IDDQ (1 << 0) 482 #define FX_ANALOG_RX1_RESET (1 << 1) 483 #define FX_ANALOG_RX1_EDGE_SEL (1 << 8) 484 #define FX_ANALOG_RX1_SIG_DET (1 << 10) 485 486 /**************************/ 487 /* FX100 Block (Block 2) */ 488 /**************************/ 489 490 /* FxControl 1 Register (Addr 0x10) */ 491 #define READ_SERDES100FX_FX100_CTRL1r(_unit, _phy_ctrl, _val) \ 492 SERDES100FX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x10, \ 493 (_val)) 494 #define WRITE_SERDES100FX_FX100_CTRL1r(_unit, _phy_ctrl, _val) \ 495 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x10, \ 496 (_val)) 497 #define MODIFY_SERDES100FX_FX100_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 498 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), \ 499 0x00, 0x0002, 0x10, (_val), (_mask)) 500 501 /* FxControl 2 Register (Addr 0x11) */ 502 #define READ_SERDES100FX_FX100_CTRL2r(_unit, _phy_ctrl, _val) \ 503 SERDES100FX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x11, \ 504 (_val)) 505 #define WRITE_SERDES100FX_FX100_CTRL2r(_unit, _phy_ctrl, _val) \ 506 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x11, \ 507 (_val)) 508 #define MODIFY_SERDES100FX_FX100_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 509 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), \ 510 0x00, 0x0002, 0x11, (_val), (_mask)) 511 512 /* FxControl 3 Register (Addr 0x12) */ 513 #define READ_SERDES100FX_FX100_CTRL3r(_unit, _phy_ctrl, _val) \ 514 SERDES100FX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x12, \ 515 (_val)) 516 #define WRITE_SERDES100FX_FX100_CTRL3r(_unit, _phy_ctrl, _val) \ 517 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x12, \ 518 (_val)) 519 #define MODIFY_SERDES100FX_FX100_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 520 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), \ 521 0x00, 0x0002, 0x12, (_val), (_mask)) 522 523 /* FxStatus 1 Register (Addr 0x13) */ 524 #define READ_SERDES100FX_FX100_STAT1r(_unit, _phy_ctrl, _val) \ 525 SERDES100FX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x13, \ 526 (_val)) 527 #define WRITE_SERDES100FX_FX100_STAT1r(_unit, _phy_ctrl, _val) \ 528 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x13, \ 529 (_val)) 530 #define MODIFY_SERDES100FX_FX100_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 531 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), \ 532 0x00, 0x0002, 0x13, (_val), (_mask)) 533 534 /* FxStatus 2 Register (Addr 0x14) */ 535 #define READ_SERDES100FX_FX100_STAT2r(_unit, _phy_ctrl, _val) \ 536 SERDES100FX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 537 (_val)) 538 #define WRITE_SERDES100FX_FX100_STAT2r(_unit, _phy_ctrl, _val) \ 539 SERDES100FX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x14, \ 540 (_val)) 541 #define MODIFY_SERDES100FX_FX100_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 542 SERDES100FX_REG_MODIFY((_unit), (_phy_ctrl), \ 543 0x00, 0x0002, 0x14, (_val), (_mask)) 544 545 /* 100FX Control 1 Register Fields */ 546 #define FX_FX100_CONTROL1_EN (1 << 0) /* Enable 100FX */ 547 #define FX_FX100_CONTROL1_FD (1 << 1) /* 100FX full duplex */ 548 #define FX_FX100_CONTROL1_AUTO_DET (1 << 2) /* Auto detect 549 100FX/1000X */ 550 551 /* 100FX Control 2 Register Fields */ 552 #define FX_FX100_CONTROL2_EXT_PKT_SZ (1 << 0) /* Allow pkt sz > 9k*/ 553 554 /* 100FX Control 3 Register Fields */ 555 #define FX_FX100_CONTROL3_FAST_TIMER (1 << 0) 556 557 #endif /* _SERDES_100FX_H_ */