serdes.h (11560B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: serdes.h 8 * Purpose: Defines common PHY driver routines for Broadcom XGXS core. 9 */ 10 #ifndef _PHY_SERDES_H 11 #define _PHY_SERDES_H 12 13 extern int 14 phy_serdes_link_get(int unit, soc_port_t port, int *link); 15 16 extern int 17 phy_serdes_duplex_set(int unit, soc_port_t port, int duplex); 18 19 extern int 20 phy_serdes_an_get(int unit, soc_port_t port, int *an, int *an_done); 21 22 extern int 23 phy_serdes_adv_local_set(int unit, soc_port_t port, soc_port_mode_t mode); 24 25 extern int 26 phy_serdes_adv_local_get(int unit, soc_port_t port, soc_port_mode_t *mode); 27 28 extern int 29 phy_serdes_adv_remote_get(int unit, soc_port_t port, soc_port_mode_t *mode); 30 31 extern int 32 phy_serdes_lb_set(int unit, soc_port_t port, int enable); 33 34 extern int 35 phy_serdes_lb_get(int unit, soc_port_t port, int *enable); 36 37 extern int 38 phy_serdes_interface_set(int unit, soc_port_t port, soc_port_if_t pif); 39 40 extern int 41 phy_serdes_interface_get(int unit, soc_port_t port, soc_port_if_t *pif); 42 43 extern int 44 phy_serdes_medium_config_get(int unit, soc_port_t port, 45 soc_port_medium_t medium, 46 soc_phy_config_t *cfg); 47 48 extern int 49 phy_serdes_medium_status(int unit, soc_port_t port, soc_port_medium_t *medium); 50 51 extern int 52 phy_serdes_master_set(int unit, soc_port_t port, int master); 53 54 extern int 55 phy_serdes_master_get(int unit, soc_port_t port, int *master); 56 57 extern int 58 phy_serdes_reg_read(int unit, soc_port_t port, uint32 flags, 59 uint32 phy_reg_addr, uint32 *phy_data); 60 61 extern int 62 phy_serdes_reg_write(int unit, soc_port_t port, uint32 flags, 63 uint32 phy_reg_addr, uint32 phy_data); 64 65 extern int 66 phy_serdes_reg_modify(int unit, soc_port_t port, uint32 flags, 67 uint32 phy_reg_addr, uint32 phy_data, 68 uint32 phy_data_mask); 69 70 /* SerDes IEEE Registers */ 71 72 /* SerDes register access */ 73 #define SERDES_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 74 _reg_addr, _val) \ 75 phy_reg_serdes_read((_unit), (_phy_ctrl), (_reg_bank), \ 76 (_reg_addr), (_val)) 77 #define SERDES_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 78 _reg_addr, _val) \ 79 phy_reg_serdes_write((_unit), (_phy_ctrl), (_reg_bank), \ 80 (_reg_addr), (_val)) 81 #define SERDES_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 82 _reg_addr, _val, _mask) \ 83 phy_reg_serdes_modify((_unit), (_phy_ctrl), (_reg_bank), \ 84 (_reg_addr), (_val), (_mask)) 85 86 87 /* MII Control (Addr 00h) */ 88 #define READ_SERDES_MII_CTRLr(_unit, _phy_ctrl, _val) \ 89 SERDES_REG_READ((_unit), (_phy_ctrl), \ 90 0x00, 0x0000, 0x00, (_val)) 91 #define WRITE_SERDES_MII_CTRLr(_unit, _phy_ctrl, _val) \ 92 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 93 0x00, 0x0000, 0x00, (_val)) 94 #define MODIFY_SERDES_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 95 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 96 (_val), (_mask)) 97 98 /* MII Status (Addr 01h) */ 99 #define READ_SERDES_MII_STATr(_unit, _phy_ctrl, _val) \ 100 SERDES_REG_READ((_unit), (_phy_ctrl), \ 101 0x00, 0x0000, 0x01, (_val)) 102 #define WRITE_SERDES_MII_STATr(_unit, _phy_ctrl, _val) \ 103 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 104 0x00, 0x0000, 0x01, (_val)) 105 #define MODIFY_SERDES_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 106 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 107 (_val), (_mask)) 108 109 /* PHY ID 0 (Addr 02h) */ 110 #define READ_SERDES_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 111 SERDES_REG_READ((_unit), (_phy_ctrl), \ 112 0x00, 0x0000, 0x02, (_val)) 113 #define WRITE_SERDES_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 114 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 115 0x00, 0x0000, 0x02, (_val)) 116 #define MODIFY_SERDES_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 117 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 118 (_val), (_mask)) 119 120 /* PHY ID 1 (Addr 03h) */ 121 #define READ_SERDES_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 122 SERDES_REG_READ((_unit), (_phy_ctrl), \ 123 0x00, 0x0000, 0x03, (_val)) 124 #define WRITE_SERDES_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 125 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 126 0x00, 0x0000, 0x03, (_val)) 127 #define MODIFY_SERDES_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 128 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 129 (_val), (_mask)) 130 131 /* Autoneg Adv (Addr 04h) */ 132 #define READ_SERDES_MII_ANAr(_unit, _phy_ctrl, _val) \ 133 SERDES_REG_READ((_unit), (_phy_ctrl), \ 134 0x00, 0x0000, 0x04, (_val)) 135 #define WRITE_SERDES_MII_ANAr(_unit, _phy_ctrl, _val) \ 136 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 137 0x00, 0x0000, 0x04, (_val)) 138 #define MODIFY_SERDES_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 139 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 140 (_val), (_mask)) 141 142 /* Autoneg Link Partner Ability (Addr 05h) */ 143 #define READ_SERDES_MII_ANPr(_unit, _phy_ctrl, _val) \ 144 SERDES_REG_READ((_unit), (_phy_ctrl), \ 145 0x00, 0x0000, 0x05, (_val)) 146 #define WRITE_SERDES_MII_ANPr(_unit, _phy_ctrl, _val) \ 147 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 148 0x00, 0x0000, 0x05, (_val)) 149 #define MODIFY_SERDES_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 150 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 151 (_val), (_mask)) 152 153 /* Autoneg Expansion (Addr 06h) */ 154 #define READ_SERDES_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 155 SERDES_REG_READ((_unit), (_phy_ctrl), \ 156 0x00, 0x0000, 0x06, (_val)) 157 #define WRITE_SERDES_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 158 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 159 0x00, 0x0000, 0x06, (_val)) 160 #define MODIFY_SERDES_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 161 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 162 (_val), (_mask)) 163 164 /* Autoneg Next Page (Addr 07h) */ 165 /* Autoneg Link Partner Ability 2 (Addr 08h) */ 166 167 /* Extended Status (Addr 0fh) */ 168 #define READ_SERDES_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 169 SERDES_REG_READ((_unit), (_phy_ctrl), \ 170 0x00, 0x0000, 0x0f, (_val)) 171 #define WRITE_SERDES_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 172 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 173 0x00, 0x0000, 0x09, (_val)) 174 #define MODIFY_SERDES_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 175 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 176 (_val), (_mask)) 177 178 /*************************/ 179 /* Digital Block (Blk 0) */ 180 /*************************/ 181 /* 1000X Control 1 (Addr 10h) */ 182 #define READ_SERDES_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 183 SERDES_REG_READ((_unit), (_phy_ctrl), \ 184 0x00, 0x0000, 0x10, (_val)) 185 #define WRITE_SERDES_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 186 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 187 0x00, 0x0000, 0x10, (_val)) 188 #define MODIFY_SERDES_1000X_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 189 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 190 (_val), (_mask)) 191 192 /* 1000X Control 2 (Addr 11h) */ 193 #define READ_SERDES_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 194 SERDES_REG_READ((_unit), (_phy_ctrl), \ 195 0x00, 0x0000, 0x11, (_val)) 196 #define WRITE_SERDES_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 197 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 198 0x00, 0x0000, 0x11, (_val)) 199 #define MODIFY_SERDES_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 200 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 201 (_val), (_mask)) 202 /* 1000X Control 3 (Addr 12h) */ 203 #define READ_SERDES_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 204 SERDES_REG_READ((_unit), (_phy_ctrl), \ 205 0x00, 0x0000, 0x12, (_val)) 206 #define WRITE_SERDES_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 207 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 208 0x00, 0x0000, 0x12, (_val)) 209 #define MODIFY_SERDES_1000X_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 210 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x12, \ 211 (_val), (_mask)) 212 213 /* 1000X Control 4 (Addr 13h) */ 214 #define READ_SERDES_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 215 SERDES_REG_READ((_unit), (_phy_ctrl), \ 216 0x00, 0x0000, 0x13, (_val)) 217 #define WRITE_SERDES_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 218 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 219 0x00, 0x0000, 0x13, (_val)) 220 #define MODIFY_SERDES_1000X_CTRL4r(_unit, _phy_ctrl, _val, _mask) \ 221 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x13, \ 222 (_val), (_mask)) 223 224 /* 1000X Status 1 (Addr 14h) */ 225 #define READ_SERDES_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 226 SERDES_REG_READ((_unit), (_phy_ctrl), \ 227 0x00, 0x0000, 0x14, (_val)) 228 #define WRITE_SERDES_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 229 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 230 0x00, 0x0000, 0x14, (_val)) 231 #define MODIFY_SERDES_1000X_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 232 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x14, \ 233 (_val), (_mask)) 234 235 /* 1000X Status 2 (Addr 15h) */ 236 #define READ_SERDES_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 237 SERDES_REG_READ((_unit), (_phy_ctrl), \ 238 0x00, 0x0000, 0x15, (_val)) 239 #define WRITE_SERDES_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 240 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 241 0x00, 0x0000, 0x15, (_val)) 242 #define MODIFY_SERDES_1000X_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 243 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x15, \ 244 (_val), (_mask)) 245 246 /* 1000X Status 3 (Addr 16h) */ 247 #define READ_SERDES_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 248 SERDES_REG_READ((_unit), (_phy_ctrl), \ 249 0x00, 0x0000, 0x16, (_val)) 250 #define WRITE_SERDES_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 251 SERDES_REG_WRITE((_unit), (_phy_ctrl), \ 252 0x00, 0x0000, 0x16, (_val)) 253 #define MODIFY_SERDES_1000X_STAT3r(_unit, _phy_ctrl, _val, _mask) \ 254 SERDES_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x16, \ 255 256 /* Reigster Fields */ 257 #define SERDES_1000X_STAT1_SGMII_MODE (1 << 0) 258 #define SERDES_1000X_CTRL2_PAR_DET_EN (1 << 0) 259 #endif /* _PHY_SERDES_H */ 260