qsgmii65.h (15892B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: qsgmii65.h 8 * Purpose: 65nm Internal (Octal) Serdes PHY Driver 9 */ 10 11 #ifndef _QSGMII65_H_ 12 #define _QSGMII65_H_ 13 14 /* 65LP SerDes register access */ 15 #define QSGMII65_REG_READ(_unit, _phy_ctrl, _flags, \ 16 _reg_addr, _val) \ 17 phy_reg_qsgmii_aer_read((_unit), (_phy_ctrl), \ 18 (_reg_addr), (_val)) 19 #define QSGMII65_REG_WRITE(_unit, _phy_ctrl, _flags, \ 20 _reg_addr, _val) \ 21 phy_reg_qsgmii_aer_write((_unit), (_phy_ctrl), \ 22 (_reg_addr), (_val)) 23 #define QSGMII65_REG_MODIFY(_unit, _phy_ctrl, _flags, \ 24 _reg_addr, _val, _mask) \ 25 phy_reg_qsgmii_aer_modify((_unit), (_phy_ctrl), \ 26 (_reg_addr), (_val), (_mask)) 27 28 29 /***************************/ 30 /* Standard IEEE Registers */ 31 /***************************/ 32 33 /* MII Control (Addr 00h) */ 34 #define READ_QSGMII65_MII_CTRLr(_unit, _phy_ctrl, _val) \ 35 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 36 0x00, 0x00000000, (_val)) 37 #define WRITE_QSGMII65_MII_CTRLr(_unit, _phy_ctrl, _val) \ 38 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 39 0x00, 0x00000000, (_val)) 40 #define MODIFY_QSGMII65_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 41 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00000000, \ 42 (_val), (_mask)) 43 44 /* MII Status (Addr 01h) */ 45 #define READ_QSGMII65_MII_STATr(_unit, _phy_ctrl, _val) \ 46 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 47 0x00, 0x00000001, (_val)) 48 #define WRITE_QSGMII65_MII_STATr(_unit, _phy_ctrl, _val) \ 49 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 50 0x00, 0x00000001, (_val)) 51 #define MODIFY_QSGMII65_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 52 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00000001, \ 53 (_val), (_mask)) 54 55 /* PHY ID 0 (Addr 02h) */ 56 #define READ_QSGMII65_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 57 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 58 0x00, 0x00000002, (_val)) 59 #define WRITE_QSGMII65_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 60 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 61 0x00, 0x00000002, (_val)) 62 #define MODIFY_QSGMII65_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 63 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00000002, \ 64 (_val), (_mask)) 65 66 /* PHY ID 1 (Addr 03h) */ 67 #define READ_QSGMII65_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 68 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 69 0x00, 0x00000003, (_val)) 70 #define WRITE_QSGMII65_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 71 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 72 0x00, 0x00000003, (_val)) 73 #define MODIFY_QSGMII65_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 74 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00000003, \ 75 (_val), (_mask)) 76 77 /* Autoneg Adv (Addr 04h) */ 78 #define READ_QSGMII65_MII_ANAr(_unit, _phy_ctrl, _val) \ 79 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 80 0x00, 0x00000004, (_val)) 81 #define WRITE_QSGMII65_MII_ANAr(_unit, _phy_ctrl, _val) \ 82 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 83 0x00, 0x00000004, (_val)) 84 #define MODIFY_QSGMII65_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 85 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00000004, \ 86 (_val), (_mask)) 87 88 /* Autoneg Link Partner Ability (Addr 05h) */ 89 #define READ_QSGMII65_MII_ANPr(_unit, _phy_ctrl, _val) \ 90 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 91 0x00, 0x00000005, (_val)) 92 #define WRITE_QSGMII65_MII_ANPr(_unit, _phy_ctrl, _val) \ 93 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 94 0x00, 0x00000005, (_val)) 95 #define MODIFY_QSGMII65_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 96 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00000005, \ 97 (_val), (_mask)) 98 99 /* Autoneg Expansion (Addr 06h) */ 100 #define READ_QSGMII65_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 101 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 102 0x00, 0x00000006, (_val)) 103 #define WRITE_QSGMII65_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 104 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 105 0x00, 0x00000006, (_val)) 106 #define MODIFY_QSGMII65_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 107 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00000006, \ 108 (_val), (_mask)) 109 110 /* Autoneg Next Page (Addr 07h) */ 111 /* Autoneg Link Partner Ability 2 (Addr 08h) */ 112 113 /* Extended Status (Addr 0fh) */ 114 #define READ_QSGMII65_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 115 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 116 0x00, 0x00000009, (_val)) 117 #define WRITE_QSGMII65_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 118 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 119 0x00, 0x00000009, (_val)) 120 #define MODIFY_QSGMII65_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 121 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00000009, \ 122 (_val), (_mask)) 123 /**************************************************************************** 124 * QSGMII65_USER_XgxsBlk0 125 */ 126 127 /* XgxsBlk0 :: xgxsControl :: start_sequencer [13:13] */ 128 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_MASK 0x2000 129 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_ALIGN 0 130 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_BITS 1 131 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_SHIFT 13 132 133 134 /* XGXG control register */ 135 #define READ_QSGMII65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 136 QSGMII65_REG_READ((_unit), (_pc), 0x00, 0x00008000, (_val)) 137 #define WRITE_QSGMII65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 138 QSGMII65_REG_WRITE((_unit), (_pc), 0x00, 0x00008000, (_val)) 139 #define MODIFY_QSGMII65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val, _mask) \ 140 QSGMII65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008000, (_val), (_mask)) 141 142 143 /*************************/ 144 /* XGXS BLOCK 1 */ 145 /*************************/ 146 /* LANE Control 0 (Addr 15h) */ 147 #define READ_QSGMII65_LANE_CTRL0r(_unit, _phy_ctrl, _val) \ 148 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 149 0x00, 0x00008015, (_val)) 150 #define WRITE_QSGMII65_LANE_CTRL0r(_unit, _phy_ctrl, _val) \ 151 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 152 0x00, 0x00008015, (_val)) 153 #define MODIFY_QSGMII65_LANE_CTRL0r(_unit, _phy_ctrl, _val, _mask) \ 154 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008015, \ 155 (_val), (_mask)) 156 157 /* LANE Control 3 (Addr 18h) */ 158 #define READ_QSGMII65_LANE_CTRL3r(_unit, _phy_ctrl, _val) \ 159 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 160 0x00, 0x00008018, (_val)) 161 #define WRITE_QSGMII65_LANE_CTRL3r(_unit, _phy_ctrl, _val) \ 162 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 163 0x00, 0x00008018, (_val)) 164 #define MODIFY_QSGMII65_LANE_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 165 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008018, \ 166 (_val), (_mask)) 167 168 /*************************/ 169 /* Digital Block (Blk 0) */ 170 /*************************/ 171 /* 1000X Control 1 (Addr 10h) */ 172 #define READ_QSGMII65_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 173 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 174 0x00, 0x00008300, (_val)) 175 #define WRITE_QSGMII65_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 176 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 177 0x00, 0x00008300, (_val)) 178 #define MODIFY_QSGMII65_1000X_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 179 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008300, \ 180 (_val), (_mask)) 181 182 /* 1000X Control 2 (Addr 11h) */ 183 #define READ_QSGMII65_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 184 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 185 0x00, 0x00008301, (_val)) 186 #define WRITE_QSGMII65_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 187 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 188 0x00, 0x00008301, (_val)) 189 #define MODIFY_QSGMII65_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 190 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008301, \ 191 (_val), (_mask)) 192 193 /* 1000X Control 3 (Addr 12h) */ 194 #define READ_QSGMII65_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 195 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 196 0x00, 0x00008302, (_val)) 197 #define WRITE_QSGMII65_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 198 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 199 0x00, 0x00008302, (_val)) 200 #define MODIFY_QSGMII65_1000X_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 201 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008302, \ 202 (_val), (_mask)) 203 204 /* 1000X Status 1 (Addr 14h) */ 205 #define READ_QSGMII65_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 206 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 207 0x00, 0x00008304, (_val)) 208 #define WRITE_QSGMII65_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 209 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 210 0x00, 0x00008304, (_val)) 211 #define MODIFY_QSGMII65_1000X_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 212 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008304, \ 213 (_val), (_mask)) 214 215 /* 1000X Status 2 (Addr 15h) */ 216 #define READ_QSGMII65_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 217 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 218 0x00, 0x00008305, (_val)) 219 #define WRITE_QSGMII65_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 220 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 221 0x00, 0x00008305, (_val)) 222 #define MODIFY_QSGMII65_1000X_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 223 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008305, \ 224 (_val), (_mask)) 225 226 /* Ber Crc Err Rx Pkt cntr (Addr 17h) */ 227 #define READ_QSGMII65_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 228 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 229 0x00, 0x00008307, (_val)) 230 #define WRITE_QSGMII65_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 231 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 232 0x00, 0x00008307, (_val)) 233 #define MODIFY_QSGMII65_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 234 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008307, \ 235 (_val), (_mask)) 236 237 /* Pat Gen Control (Addr 1Ah) */ 238 #define READ_QSGMII65_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 239 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 240 0x00, 0x0000830a, (_val)) 241 #define WRITE_QSGMII65_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 242 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 243 0x00, 0x0000830a, (_val)) 244 #define MODIFY_QSGMII65_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 245 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000830a, \ 246 (_val), (_mask)) 247 248 /* Pat Gen Status (Addr 1Bh) */ 249 #define READ_QSGMII65_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 250 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 251 0x00, 0x0000830b, (_val)) 252 #define WRITE_QSGMII65_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 253 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 254 0x00, 0x0000830b, (_val)) 255 #define MODIFY_QSGMII65_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val, _mask) \ 256 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000830b, \ 257 (_val), (_mask)) 258 259 /* Test Mode (Addr 1Ch) */ 260 #define READ_QSGMII65_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 261 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 262 0x00, 0x0000830c, (_val)) 263 #define WRITE_QSGMII65_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 264 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 265 0x00, 0x0000830c, (_val)) 266 #define MODIFY_QSGMII65_1000X_TEST_MODEr(_unit, _phy_ctrl, _val, _mask) \ 267 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000830c, \ 268 (_val), (_mask)) 269 270 /* 1000X Control #1 Register: Controls 10B/SGMII mode */ 271 #define LP_1000X_FIBER_MODE (1 << 0) /* Enable SGMII fiber mode */ 272 #define LP_1000X_EN10B_MODE (1 << 1) /* Enable TBI 10B interface */ 273 #define LP_1000X_INVERT_SD (1 << 3) /* Invert Signal Detect */ 274 #define LP_1000X_AUTO_DETECT (1 << 4) /* Auto-detect SGMII and 1000X */ 275 #define LP_1000X_SGMII_MASTER (1 << 5) 276 #define LP_1000X_PLL_PWRDWN (1 << 6) 277 #define LP_1000X_RX_PKTS_CNTR_SEL (1 << 11) /* Select receive counter for 17h*/ 278 #define LP_1000X_TX_AMPLITUDE_OVRD (1 << 12) 279 280 /* 1000X Control #2 Register Fields */ 281 #define LP_1000X_PAR_DET_EN (1 << 0) /* Enable Parallel Detect */ 282 #define LP_1000X_FALSE_LNK_DIS (1 << 1) /* Disable false link */ 283 #define LP_1000X_FILTER_FORCE_EN (1 << 2) /* Enable filter force link */ 284 /* Allow packet to be transmitted regardless of the condition of the link */ 285 #define LP_1000X_FORCE_XMIT_DATA_ON_TXSIDE (1 << 5) 286 #define LP_1000X_CLRAR_BER_CNTR (1 << 14) /* Clear bit-err-rate counter */ 287 288 /* 1000X Control #3 Register Fields */ 289 #define LP_1000X_TX_FIFO_RST (1 << 0) /* Reset TX FIFO */ 290 #define LP_1000X_FIFO_ELASTICITY_MASK (0x3 << 1) /* Fifo Elasticity */ 291 #define LP_1000X_FIFO_ELASTICITY_5K (0x0 << 1) /* 5 Kbytes */ 292 #define LP_1000X_FIFO_ELASTICITY_10K (0x1 << 1) /* 10 Kbytes */ 293 #define LP_1000X_FIFO_ELASTICITY_13_5K (0x2 << 1) /* 13.5 Kbytes */ 294 #define LP_1000X_FREQ_LOCK_ELASTICITY_RX (1 << 6) 295 #define LP_1000X_FREQ_LOCK_ELASTICITY_TX (1 << 5) 296 #define LP_1000X_RX_FIFO_RST (1 << 14) /* Reset RX FIFO */ 297 298 /* 1000X Control #4 Register Fields */ 299 #define LP_1000X_DIG_RESET (1 << 6) /* Reset Datapath */ 300 301 /* 1000X Status #1 Register Fields */ 302 #define LP_1000X_STATUS1_SGMII_MODE (1 << 0) 303 #define LP_1000X_STATUS1_SPEED (3 << 3) 304 #define LP_1000X_STATUS1_SPEED_10 (0) 305 #define LP_1000X_STATUS1_SPEED_100 (1 << 3) 306 #define LP_1000X_STATUS1_SPEED_1000 (1 << 4) 307 308 /************************/ 309 /* Analog Block (Blk 3) */ 310 /************************/ 311 /* Analog Tx 1 (Addr 10h) */ 312 #define READ_QSGMII65_ANALOG_TX1r(_unit, _phy_ctrl, _val) \ 313 QSGMII65_REG_READ((_unit), (_phy_ctrl), \ 314 0x00, 0x00008067, (_val)) 315 #define WRITE_QSGMII65_ANALOG_TX1r(_unit, _phy_ctrl, _val) \ 316 QSGMII65_REG_WRITE((_unit), (_phy_ctrl), \ 317 0x00, 0x00008067, (_val)) 318 #define MODIFY_QSGMII65_ANALOG_TX1r(_unit, _phy_ctrl, _val, _mask) \ 319 QSGMII65_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x00008067, \ 320 (_val), (_mask)) 321 #endif /* _QSGMII65_H_ */