phyreg.h (7201B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phyreg.h 8 * 9 * Data structures and function prototypes for PHY register access. 10 */ 11 12 #ifndef _PHYREG_LOCAL_H_ 13 #define _PHYREG_LOCAL_H_ 14 15 #define PHY_AER_REG_ADDR_AER(_addr) (((_addr) >> 16) & 0x0000FFFF) 16 #define PHY_AER_REG_ADDR_BLK(_addr) (((_addr) & 0x000FFF0)) 17 #define PHY_AER_REG_ADDR_REGAD(_addr) ((((_addr) & 0x00008000) >> 11) | \ 18 ((_addr) & 0x0000000F)) 19 #define PHY_AER_REG 0xFFDE 20 #define PHY_AER_REG_ADDR_CL45_DEVID(_addr) (((_addr) >> 27) & 0x0000001F) 21 #define PHY_AER_REG_ADDR_LANE_NUM(_addr) (((_addr) >> 16) & 0x07FF) 22 #define PHY_AER_REG_ADDR_CL45_REGAD(_addr) (((_addr) & 0x000FFFF)) 23 24 #define READ_PHY_REG(_unit, _pc, _addr, _value) \ 25 ((_pc->read)((_unit), (_pc->phy_id), (_addr), (_value))) 26 #define WRITE_PHY_REG(_unit, _pc, _addr, _value) \ 27 ((_pc->write)((_unit), (_pc->phy_id), (_addr), (_value))) 28 #define WRITE_WB_PHY_REG(_unit, _pc, _addr, _value) \ 29 ((_pc->wb_write ? _pc->wb_write : _pc->write)((_unit), (_pc->phy_id), (_addr), (_value))) 30 #define WRITE_ADDR_PHY_REG(_unit, _pc, _addr, _value) \ 31 ((_pc->addr_write)((_unit), (_pc->phy_id), (_addr), (_value))) 32 #define WRITE_DATA_PHY_REG(_unit, _pc, _addr, _value) \ 33 ((_pc->data_write)((_unit), (_pc->phy_id), (_addr), (_value))) 34 #define MODIFY_PHY_REG(_unit, _pc, _addr, _data, _mask) \ 35 (phy_reg_modify((_unit), (_pc), (_addr), (_data), (_mask))) 36 37 extern int phy_reg_modify(int unit, phy_ctrl_t *pc, uint32 phy_addr, 38 uint16 data, uint16 mask); 39 40 extern int phy_reg_fe_read(int unit, phy_ctrl_t *pc, uint16 reg_bank, 41 uint8 reg_addr, uint16 *data); 42 extern int phy_reg_fe_write(int unit, phy_ctrl_t *pc, uint16 reg_bank, 43 uint8 reg_addr, uint16 data); 44 extern int phy_reg_fe_modify(int unit, phy_ctrl_t *pc, uint16 reg_bank, 45 uint8 reg_addr, uint16 data, uint16 mask); 46 47 extern int phy_reg_ge_read(int unit, phy_ctrl_t *pc, uint32 flags, 48 uint16 reg_bank, uint8 reg_addr, uint16 *data); 49 extern int phy_reg_ge_write(int unit, phy_ctrl_t *pc, uint32 flags, 50 uint16 reg_bank, uint8 reg_addr, uint16 data); 51 extern int phy_reg_ge_modify(int unit, phy_ctrl_t *pc, uint32 flags, 52 uint16 reg_bank, uint8 reg_addr, 53 uint16 data, uint16 mask); 54 55 extern int phy_reg_xge_read(int unit, phy_ctrl_t *pc, uint32 flags, uint16 reg_bank, 56 uint8 dev_addr, uint16 reg_addr, uint16 *data); 57 extern int phy_reg_xge_write(int unit, phy_ctrl_t *pc, uint32 flags, uint16 reg_bank, 58 uint8 dev_addr, uint16 reg_addr, uint16 data); 59 extern int phy_reg_xge_modify(int unit, phy_ctrl_t *pc, uint32 flags, uint16 reg_bank, 60 uint8 dev_addr, uint16 reg_addr, uint16 data, uint16 mask); 61 62 63 extern int phy_reg_serdes_read(int unit, phy_ctrl_t *pc, uint16 reg_bank, 64 uint8 reg_addr, uint16 *data); 65 extern int phy_reg_serdes_write(int unit, phy_ctrl_t *pc, uint16 reg_bank, 66 uint8 reg_addr, uint16 data); 67 extern int phy_reg_serdes_modify(int unit, phy_ctrl_t *pc, uint16 reg_bank, 68 uint8 reg_addr, uint16 data, uint16 mask); 69 70 extern int phy_reg_xgxs_read(int unit, phy_ctrl_t *pc, 71 uint16 reg_bank, uint8 reg_addr, uint16 *data); 72 extern int phy_reg_xgxs_write(int unit, phy_ctrl_t *pc, 73 uint16 reg_bank, uint8 reg_addr, uint16 data); 74 extern int phy_reg_xgxs_modify(int unit, phy_ctrl_t *pc, 75 uint16 reg_bank, uint8 reg_addr, 76 uint16 data, uint16 mask); 77 78 extern int phy_reg_xgxs6_read(int unit, phy_ctrl_t *pc, uint32 flags, 79 uint16 reg_bank, uint8 reg_addr, uint16 *data); 80 extern int phy_reg_xgxs6_write(int unit, phy_ctrl_t *pc, uint32 flags, 81 uint16 reg_bank, uint8 reg_addr, uint16 data); 82 extern int phy_reg_xgxs6_modify(int unit, phy_ctrl_t *pc, uint32 flags, 83 uint16 reg_bank, uint8 reg_addr, 84 uint16 data, uint16 mask); 85 86 extern int phy_reg_aer_read(int unit, phy_ctrl_t *pc, uint32 reg_addr, 87 uint16 *data); 88 extern int phy_reg_aer_write(int unit, phy_ctrl_t *pc, uint32 reg_addr, 89 uint16 data); 90 extern int phy_reg_aer_modify(int unit, phy_ctrl_t *pc, uint32 reg_addr, 91 uint16 data, uint16 mask); 92 93 extern int phy_reg_qsgmii_aer_read(int unit, phy_ctrl_t *pc, uint32 reg_addr, 94 uint16 *data); 95 extern int phy_reg_qsgmii_aer_write(int unit, phy_ctrl_t *pc, uint32 reg_addr, 96 uint16 data); 97 extern int phy_reg_qsgmii_aer_modify(int unit, phy_ctrl_t *pc, uint32 reg_addr, 98 uint16 data, uint16 mask); 99 100 /* Register access mappings */ 101 102 /* hl65 register access */ 103 #define HL65_REG_READ(_unit, _pc, _flags, _reg_addr, _val) \ 104 phy_reg_aer_read((_unit), (_pc), \ 105 (((_pc)->flags & PHYCTRL_MDIO_ADDR_SHARE)? \ 106 ((_reg_addr)|(((_pc)->lane_num) <<16)):(_reg_addr)),(_val)) 107 108 #define HL65_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \ 109 phy_reg_aer_write((_unit), (_pc), \ 110 (((_pc)->flags & PHYCTRL_MDIO_ADDR_SHARE)? \ 111 ((_reg_addr)| (((_pc)->lane_num)<<16)):(_reg_addr)),(_val)) 112 113 #define HL65_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \ 114 phy_reg_aer_modify((_unit), (_pc), \ 115 (((_pc)->flags & PHYCTRL_MDIO_ADDR_SHARE)? \ 116 ((_reg_addr) | (((_pc)->lane_num)<<16)):(_reg_addr)),(_val), (_mask)) 117 118 119 /* XGXS_16G register access */ 120 121 #define XGXS16G_REG_READ(_unit, _pc, _flags, _reg_addr, _val) \ 122 phy_reg_aer_read((_unit), (_pc), \ 123 (((_pc)->flags & PHYCTRL_MDIO_ADDR_SHARE)? \ 124 ((_reg_addr) | ((((_pc)->phy_id & 0x1f) \ 125 + (_pc)->lane_num)<<16)):(_reg_addr)),(_val)) 126 127 #define XGXS16G_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \ 128 phy_reg_aer_write((_unit), (_pc), \ 129 (((_pc)->flags & PHYCTRL_MDIO_ADDR_SHARE)? \ 130 ((_reg_addr) | ((((_pc)->phy_id & 0x1f) \ 131 + (_pc)->lane_num)<<16)):(_reg_addr)),(_val)) 132 133 #define XGXS16G_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \ 134 phy_reg_aer_modify((_unit), (_pc), \ 135 (((_pc)->flags & PHYCTRL_MDIO_ADDR_SHARE)? \ 136 ((_reg_addr) | ((((_pc)->phy_id & 0x1f) \ 137 + (_pc)->lane_num)<<16)):(_reg_addr)),(_val), (_mask)) 138 139 #endif /* _PHYREG_LOCAL_H_ */