phymod_port_control.c - openbcm - Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM

phymod_port_control.c (113242B)
      1 /*
      2  * 
      3  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      4  * 
      5  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      6  *
      7  * File:        phymod_ctrl.c
      8  * Purpose:     Interface functions for PHYMOD
      9  */
     10 
     11 #ifdef PHYMOD_SUPPORT
     12 
     13 #include <soc/phy/phymod_port_control.h>
     14 #include <soc/error.h>
     15 
     16 #ifdef _ERR_MSG_MODULE_NAME
     17 #error "_ERR_MSG_MODULE_NAME redefined"
     18 #endif
     19 #define _ERR_MSG_MODULE_NAME BSL_LS_SOC_PHYMOD
     20 
     21 #define LANE_MAP_NOF_LANES (4)
     22 #define PATTERN_MAX_SIZE (8)
     23 
     24 typedef int (*control_set_handler_f)(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2);
     25 typedef int (*control_get_handler_f)(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value);
     26 
     27 int soc_phymod_phy_intf_from_port_intf(int unit, int speed, soc_port_if_t interface,
     28                                        phymod_interface_t *phymod_interface)
     29 {
     30     SOC_INIT_FUNC_DEFS;
     31 
     32     switch(interface) {
     33         case SOC_PORT_IF_SR:
     34             (*phymod_interface) = phymodInterfaceSR;
     35             break ;
     36         case SOC_PORT_IF_SR2:
     37             (*phymod_interface) = phymodInterfaceSR2;
     38             break ;
     39         case SOC_PORT_IF_SR4:
     40             (*phymod_interface) = phymodInterfaceSR4;
     41             break ;
     42         case SOC_PORT_IF_SR10:
     43             (*phymod_interface) = phymodInterfaceSR10;
     44             break ;
     45         case SOC_PORT_IF_DNX_XAUI:
     46             (*phymod_interface) = phymodInterfaceXAUI;
     47              break;
     48         case SOC_PORT_IF_KR:
     49             (*phymod_interface) = phymodInterfaceKR;
     50             break ;
     51         case SOC_PORT_IF_KR2:
     52             (*phymod_interface) = phymodInterfaceKR2;
     53             break ;
     54         case SOC_PORT_IF_KR4:
     55             (*phymod_interface) = phymodInterfaceKR4;
     56             break ;
     57         case SOC_PORT_IF_KR10:
     58             (*phymod_interface) = phymodInterfaceKR10;
     59             break ;
     60         case SOC_PORT_IF_LR10:
     61             (*phymod_interface) = phymodInterfaceLR10;
     62             break ;
     63         case SOC_PORT_IF_CAUI:
     64             (*phymod_interface) = phymodInterfaceCAUI;
     65             break;
     66         case SOC_PORT_IF_XFI2:
     67             (*phymod_interface) = phymodInterfaceSR2;
     68             break;
     69         case SOC_PORT_IF_XFI:
     70             (*phymod_interface) = phymodInterfaceXFI;
     71             break;
     72         case SOC_PORT_IF_SFI:
     73             (*phymod_interface) = phymodInterfaceSFI;
     74             break;
     75         case SOC_PORT_IF_XGMII:
     76             (*phymod_interface) = phymodInterfaceXGMII;
     77              break;
     78         case SOC_PORT_IF_SGMII:
     79             (*phymod_interface) = phymodInterfaceSGMII;
     80              break;
     81         case SOC_PORT_IF_GMII:
     82             (*phymod_interface) = phymodInterface1000X;
     83              break;
     84         case SOC_PORT_IF_RXAUI:
     85             (*phymod_interface) = phymodInterfaceRXAUI;
     86              break;
     87         case SOC_PORT_IF_XLAUI:
     88             (*phymod_interface) = phymodInterfaceXLAUI;
     89             break;
     90         case SOC_PORT_IF_XLAUI2:
     91             (*phymod_interface) = phymodInterfaceXLAUI2;
     92             break;
     93         case SOC_PORT_IF_CR:
     94             (*phymod_interface) = phymodInterfaceCR;
     95              break;
     96         case SOC_PORT_IF_CR2:
     97             (*phymod_interface) = phymodInterfaceCR2;
     98              break;
     99         case SOC_PORT_IF_CR4:
    100             (*phymod_interface) = phymodInterfaceCR4;
    101             break;
    102         case SOC_PORT_IF_CR10:
    103             (*phymod_interface) = phymodInterfaceCR10;
    104              break;
    105         case SOC_PORT_IF_QSGMII:
    106             (*phymod_interface) = phymodInterfaceQSGMII;
    107              break;
    108         case SOC_PORT_IF_ZR:
    109             (*phymod_interface) = phymodInterfaceZR;
    110              break;
    111         case SOC_PORT_IF_LRM:
    112             (*phymod_interface) = phymodInterfaceLRM;
    113              break;
    114         case SOC_PORT_IF_LR:
    115             (*phymod_interface) = phymodInterfaceLR;
    116              break;
    117         case SOC_PORT_IF_LR2:
    118             (*phymod_interface) = phymodInterfaceLR2;
    119              break;
    120         case SOC_PORT_IF_LR4:
    121             (*phymod_interface) = phymodInterfaceLR4;
    122              break;
    123         case SOC_PORT_IF_ILKN:
    124             (*phymod_interface) = phymodInterfaceBypass;
    125              break;
    126         case SOC_PORT_IF_KX:
    127             (*phymod_interface) = phymodInterfaceKX;
    128              break;
    129         case SOC_PORT_IF_ER:
    130             (*phymod_interface) = phymodInterfaceER;
    131             break;
    132         case SOC_PORT_IF_ER2:
    133             (*phymod_interface) = phymodInterfaceER2;
    134             break;
    135         case SOC_PORT_IF_ER4:
    136             (*phymod_interface) = phymodInterfaceER4;
    137             break;
    138         case SOC_PORT_IF_XLPPI:
    139             (*phymod_interface) = phymodInterfaceXLPPI;
    140             break;
    141         case SOC_PORT_IF_VSR:
    142             (*phymod_interface) = phymodInterfaceVSR;
    143             break;
    144         case SOC_PORT_IF_CX:
    145             (*phymod_interface) = phymodInterfaceCX;
    146             break;
    147         case SOC_PORT_IF_CAUI_C2C: 
    148             (*phymod_interface) = phymodInterfaceCAUI4_C2C; 
    149             break;
    150         case SOC_PORT_IF_CAUI_C2M: 
    151             (*phymod_interface) = phymodInterfaceCAUI4_C2M; 
    152             break;
    153         case SOC_PORT_IF_CAUI4:
    154             (*phymod_interface) = phymodInterfaceCAUI4;
    155             break;
    156         case SOC_PORT_IF_COUNT:
    157             (*phymod_interface) = phymodInterfaceCount;
    158             break;
    159         default:
    160             _SOC_EXIT_WITH_ERR(SOC_E_PARAM, (_SOC_MSG("Interface %d not supported in portmod_intf_to"), interface));
    161     }
    162 
    163 exit:
    164         SOC_FUNC_RETURN;
    165 
    166 }
    167 
    168 int soc_phymod_phy_intf_to_port_intf (int unit,
    169                                    phymod_interface_t phymod_interface,
    170                                    soc_port_if_t *interface)
    171 {
    172     SOC_INIT_FUNC_DEFS;
    173 
    174     switch(phymod_interface) {
    175         case phymodInterfaceBypass:
    176             (*interface) = SOC_PORT_IF_ILKN;
    177             break;
    178         case phymodInterfaceSR:
    179             (*interface) = SOC_PORT_IF_SR;
    180             break;
    181         case phymodInterfaceSR2:
    182             (*interface) = SOC_PORT_IF_SR2;
    183             break;
    184         case phymodInterfaceSR4:
    185             (*interface) = SOC_PORT_IF_SR4;
    186             break;
    187         case phymodInterfaceSR10:
    188             (*interface) = SOC_PORT_IF_SR10;
    189             break;
    190         case phymodInterfaceLR10:
    191             (*interface) = SOC_PORT_IF_LR10;
    192             break;
    193         case phymodInterfaceKX:
    194             (*interface) = SOC_PORT_IF_KX;
    195             break;
    196         case phymodInterfaceKX4:
    197         case phymodInterfaceXAUI:
    198             (*interface) = SOC_PORT_IF_DNX_XAUI;
    199             break;
    200         case phymodInterfaceKR:
    201             (*interface) = SOC_PORT_IF_KR;
    202             break;
    203         case phymodInterfaceKR2:
    204             (*interface) = SOC_PORT_IF_KR2;
    205             break;
    206         case phymodInterfaceKR4:
    207             (*interface) = SOC_PORT_IF_KR4;
    208             break;
    209         case phymodInterfaceKR10:
    210             (*interface) = SOC_PORT_IF_KR10;
    211             break;
    212         case phymodInterfaceCR:
    213             (*interface) = SOC_PORT_IF_CR;
    214             break;
    215         case phymodInterfaceCR2:
    216             (*interface) = SOC_PORT_IF_CR2;
    217             break;
    218         case phymodInterfaceCR4:
    219             (*interface) = SOC_PORT_IF_CR4;
    220             break;
    221         case phymodInterfaceCR10:
    222             (*interface) = SOC_PORT_IF_CR10;
    223             break;
    224         case phymodInterfaceXFI:
    225             (*interface) = SOC_PORT_IF_XFI;
    226             break;
    227         case phymodInterfaceSFI:
    228             (*interface) = SOC_PORT_IF_SFI;
    229             break;
    230         case phymodInterfaceXGMII:
    231             (*interface) = SOC_PORT_IF_XGMII;
    232             break;
    233         case phymodInterfaceSGMII:
    234             (*interface) = SOC_PORT_IF_SGMII;
    235              break;
    236         case phymodInterface1000X:
    237             (*interface) = SOC_PORT_IF_GMII;
    238              break;
    239         case phymodInterfaceCX2:
    240             (*interface) = SOC_PORT_IF_RXAUI;
    241              break;
    242         case phymodInterfaceX2:
    243             (*interface) = SOC_PORT_IF_RXAUI;
    244              break;
    245         case phymodInterfaceRXAUI:
    246             (*interface) = SOC_PORT_IF_RXAUI;
    247              break;
    248         case phymodInterfaceXLAUI:
    249             (*interface) = SOC_PORT_IF_XLAUI;
    250             break;
    251         case phymodInterfaceXLAUI2:
    252             (*interface) = SOC_PORT_IF_XLAUI2;
    253             break;
    254         case phymodInterfaceCAUI:
    255             (*interface) = SOC_PORT_IF_CAUI;
    256             break;
    257         case phymodInterfaceCAUI4:
    258             (*interface) = SOC_PORT_IF_CAUI4;
    259             break;
    260         case phymodInterfaceQSGMII:
    261             (*interface) = SOC_PORT_IF_QSGMII;
    262              break;
    263         case phymodInterfaceCX4:
    264             (*interface) = SOC_PORT_IF_CR4;
    265              break;
    266         case phymodInterfaceZR:
    267             (*interface) = SOC_PORT_IF_ZR;
    268              break;
    269         case phymodInterfaceLR:
    270             (*interface) = SOC_PORT_IF_LR;
    271              break;
    272         case phymodInterfaceLR2:
    273             (*interface) = SOC_PORT_IF_LR2;
    274              break;
    275         case phymodInterfaceLR4:
    276             (*interface) = SOC_PORT_IF_LR4;
    277              break;
    278         case phymodInterfaceLRM:
    279             (*interface) = SOC_PORT_IF_LRM;
    280              break;
    281         case phymodInterfaceER:
    282             (*interface) = SOC_PORT_IF_ER;
    283             break;
    284         case phymodInterfaceER2:
    285             (*interface) = SOC_PORT_IF_ER2;
    286             break;
    287         case phymodInterfaceER4:
    288             (*interface) = SOC_PORT_IF_ER4;
    289             break;
    290         case phymodInterfaceXLPPI:
    291             (*interface) = SOC_PORT_IF_XLPPI;
    292              break;
    293         case phymodInterfaceVSR:
    294             (*interface) = SOC_PORT_IF_VSR;
    295              break;
    296         case phymodInterfaceCX:
    297             (*interface) = SOC_PORT_IF_CX;
    298              break;
    299         case phymodInterfaceCAUI4_C2C:
    300             (*interface) = SOC_PORT_IF_CAUI_C2C;
    301             break;
    302         case phymodInterfaceCAUI4_C2M:
    303             (*interface) = SOC_PORT_IF_CAUI_C2M; 
    304             break;
    305         /*
    306               case phymodInterfaceX2:
    307                     (*interface) = SOC_PORT_IF_RXAUI;
    308                     break;
    309              */
    310         default:
    311             _SOC_EXIT_WITH_ERR(SOC_E_PARAM,
    312                 (_SOC_MSG("Phymod Interface %d not supported in soc_phymod_phy_intf_to_port_intf"),
    313                             phymod_interface));
    314     }
    315 
    316 exit:
    317     SOC_FUNC_RETURN;
    318 }
    319 
    320 int soc_phymod_media_type_from_port_intf(int unit, soc_port_if_t interface,
    321                                        phymod_phy_inf_config_t *phy_interface_config)
    322 {
    323     SOC_INIT_FUNC_DEFS;
    324 
    325     PHYMOD_INTF_MODES_FIBER_CLR(phy_interface_config);
    326     PHYMOD_INTF_MODES_COPPER_CLR(phy_interface_config);
    327     PHYMOD_INTF_MODES_BACKPLANE_CLR(phy_interface_config);
    328 
    329     switch(interface) {
    330         case SOC_PORT_IF_SFI:
    331         case SOC_PORT_IF_SR:
    332         case SOC_PORT_IF_SR2:
    333         case SOC_PORT_IF_SR4:
    334         case SOC_PORT_IF_SR10:
    335         case SOC_PORT_IF_LR:
    336         case SOC_PORT_IF_LR2:
    337         case SOC_PORT_IF_LR4:
    338         case SOC_PORT_IF_GMII:
    339         case SOC_PORT_IF_LRM:
    340         case SOC_PORT_IF_ER:
    341         case SOC_PORT_IF_ER2:
    342         case SOC_PORT_IF_ER4:
    343         case SOC_PORT_IF_XFI2:
    344             PHYMOD_INTF_MODES_FIBER_SET(phy_interface_config);
    345             break ;
    346         case SOC_PORT_IF_KR:
    347         case SOC_PORT_IF_KR2:
    348         case SOC_PORT_IF_KR4:
    349         case SOC_PORT_IF_KR10:
    350         case SOC_PORT_IF_CAUI:
    351         case SOC_PORT_IF_CAUI4:
    352         case SOC_PORT_IF_XFI:
    353         case SOC_PORT_IF_SGMII:
    354         case SOC_PORT_IF_QSGMII:
    355         case SOC_PORT_IF_DNX_XAUI:
    356         case SOC_PORT_IF_RXAUI:
    357         case SOC_PORT_IF_XLAUI:
    358         case SOC_PORT_IF_XLAUI2:
    359         case SOC_PORT_IF_XGMII:
    360             PHYMOD_INTF_MODES_BACKPLANE_SET(phy_interface_config);
    361             break;
    362         case SOC_PORT_IF_CR:
    363         case SOC_PORT_IF_CR2:
    364         case SOC_PORT_IF_CR4:
    365         case SOC_PORT_IF_CR10:
    366             PHYMOD_INTF_MODES_COPPER_SET(phy_interface_config);
    367              break;
    368         default:
    369             PHYMOD_INTF_MODES_BACKPLANE_SET(phy_interface_config);
    370     }
    371 
    372     SOC_FUNC_RETURN;
    373 }
    374 
    375 int soc_phymod_intf_mode_from_phymod_intf(int unit, phymod_interface_t phymod_interface,
    376                                        phymod_phy_inf_config_t *phy_interface_config)
    377 {
    378     SOC_INIT_FUNC_DEFS;
    379 
    380     PHYMOD_INTF_MODES_FIBER_CLR(phy_interface_config);
    381     PHYMOD_INTF_MODES_COPPER_CLR(phy_interface_config);
    382     PHYMOD_INTF_MODES_BACKPLANE_CLR(phy_interface_config);
    383 
    384     switch(phymod_interface) {
    385         case phymodInterfaceSFI:
    386         case phymodInterfaceSR:
    387         case phymodInterfaceSR2:
    388         case phymodInterfaceSR4:
    389         case phymodInterfaceSR10:
    390         case phymodInterfaceLR:
    391         case phymodInterfaceLR2:
    392         case phymodInterfaceLR4:
    393         case phymodInterface1000X:
    394         case phymodInterfaceLRM:
    395         case phymodInterfaceER:
    396         case phymodInterfaceER2:
    397         case phymodInterfaceER4:
    398             PHYMOD_INTF_MODES_FIBER_SET(phy_interface_config);
    399             break ;
    400         case phymodInterfaceKR:
    401         case phymodInterfaceKR2:
    402         case phymodInterfaceKR4:
    403         case phymodInterfaceKR10:
    404         case phymodInterfaceCAUI:
    405         case phymodInterfaceCAUI4:
    406         case phymodInterfaceXFI:
    407         case phymodInterfaceSGMII:
    408         case phymodInterfaceQSGMII:
    409         case phymodInterfaceXAUI:
    410         case phymodInterfaceRXAUI:
    411         case phymodInterfaceXLAUI:
    412         case phymodInterfaceXLAUI2:
    413         case phymodInterfaceXGMII:
    414             PHYMOD_INTF_MODES_BACKPLANE_SET(phy_interface_config);
    415             break;
    416         case phymodInterfaceCR:
    417         case phymodInterfaceCR2:
    418         case phymodInterfaceCR4:
    419         case phymodInterfaceCR10:
    420             PHYMOD_INTF_MODES_COPPER_SET(phy_interface_config);
    421              break;
    422         default:
    423             PHYMOD_INTF_MODES_BACKPLANE_SET(phy_interface_config);
    424     }
    425 
    426     SOC_FUNC_RETURN;
    427 }
    428 
    429 int
    430 soc_prbs_poly_to_phymod(uint32 sdk_poly, phymod_prbs_poly_t *phymod_poly){
    431     switch(sdk_poly){
    432     case SOC_PHY_PRBS_POLYNOMIAL_X7_X6_1:
    433         *phymod_poly = phymodPrbsPoly7;
    434         break;
    435     case SOC_PHY_PRBS_POLYNOMIAL_X9_X5_1:
    436         *phymod_poly = phymodPrbsPoly9;
    437         break;
    438     case SOC_PHY_PRBS_POLYNOMIAL_X11_X9_1:
    439         *phymod_poly = phymodPrbsPoly11;
    440         break;
    441     case SOC_PHY_PRBS_POLYNOMIAL_X15_X14_1:
    442         *phymod_poly = phymodPrbsPoly15;
    443         break;
    444     case SOC_PHY_PRBS_POLYNOMIAL_X23_X18_1:
    445         *phymod_poly = phymodPrbsPoly23;
    446         break;
    447     case SOC_PHY_PRBS_POLYNOMIAL_X31_X28_1:
    448         *phymod_poly = phymodPrbsPoly31;
    449         break;
    450     case SOC_PHY_PRBS_POLYNOMIAL_X58_X31_1:
    451         *phymod_poly = phymodPrbsPoly58;
    452         break;
    453     case SOC_PHY_PRBS_POLYNOMIAL_X49_X40_1:
    454         *phymod_poly = phymodPrbsPoly49;
    455         break;
    456     case SOC_PHY_PRBS_POLYNOMIAL_X20_X3_1:
    457         *phymod_poly = phymodPrbsPoly20;
    458         break;
    459     case SOC_PHY_PRBS_POLYNOMIAL_X13_X12_X2_1:
    460         *phymod_poly = phymodPrbsPoly13;
    461         break;
    462     case SOC_PHY_PRBS_POLYNOMIAL_X10_X7_1:
    463         *phymod_poly = phymodPrbsPoly10;
    464         break;
    465     case SOC_PHY_PRBS_POLYNOMIAL_PAM4_13Q:
    466         *phymod_poly = phymodPrbsPolyQ13;
    467         break;
    468     default:
    469         return SOC_E_PARAM;
    470     }
    471     return SOC_E_NONE;
    472 }
    473 
    474 
    475 int
    476 phymod_prbs_poly_to_soc(phymod_prbs_poly_t phymod_poly, uint32 *sdk_poly){
    477     switch(phymod_poly){
    478     case phymodPrbsPoly7:
    479         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X7_X6_1;
    480         break;
    481     case phymodPrbsPoly9:
    482         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X9_X5_1;
    483         break;
    484     case phymodPrbsPoly11:
    485         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X11_X9_1;
    486         break;
    487     case phymodPrbsPoly15:
    488         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X15_X14_1;
    489         break;
    490     case phymodPrbsPoly23:
    491         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X23_X18_1;
    492         break;
    493     case phymodPrbsPoly31:
    494         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X31_X28_1;
    495         break;
    496     case phymodPrbsPoly58:
    497         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X58_X31_1;
    498         break;
    499     case phymodPrbsPoly49:
    500         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X49_X40_1;
    501         break;
    502     case phymodPrbsPoly20:
    503         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X20_X3_1;
    504         break;
    505     case phymodPrbsPoly13:
    506         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X13_X12_X2_1;
    507         break;
    508     case phymodPrbsPoly10:
    509         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_X10_X7_1;
    510         break;
    511     case phymodPrbsPolyQ13:
    512         *sdk_poly = SOC_PHY_PRBS_POLYNOMIAL_PAM4_13Q;
    513         break;
    514     default:
    515         return SOC_E_INTERNAL;
    516     }
    517     return SOC_E_NONE;
    518 }
    519 
    520 /****************************************************************************** 
    521   Set controls handlers
    522  */
    523 STATIC int
    524 control_handler_preemphasis_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    525 {
    526     phymod_tx_t phymod_tx, phymod_tx_def;
    527 
    528     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    529     if (value1 != 0xFFFFFFFF)
    530     {
    531        phymod_tx.pre  = value1 & 0xff;
    532        phymod_tx.main = (value1 >> 8) & 0xff;
    533        phymod_tx.post = (value1 >> 16) & 0xff;  
    534     } else {
    535         SOC_IF_ERROR_RETURN(phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &phymod_tx_def));
    536         phymod_tx.pre = phymod_tx_def.pre;
    537 
    538     }
    539     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    540 
    541     return SOC_E_NONE;
    542 }
    543 
    544 STATIC int
    545 control_handler_tx_fir_mode_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    546 {
    547     phymod_tx_t phymod_tx;
    548 
    549     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    550 
    551     if (value1 == SOC_PHY_TX_FIR_3TAP_MODE) {
    552         phymod_tx.tap_mode = phymodTxTapMode3Tap;
    553     } else if (value1 == SOC_PHY_TX_FIR_6TAP_MODE) {
    554         phymod_tx.tap_mode = phymodTxTapMode6Tap;
    555     } else {
    556         return SOC_E_PARAM;
    557     }
    558 
    559     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    560     return SOC_E_NONE;
    561 }
    562 
    563 STATIC int
    564 control_handler_tx_fir_pre2_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    565 {
    566     phymod_tx_t phymod_tx, phymod_tx_def;
    567 
    568     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    569     if (value1 != 0xFFFFFFFF)
    570     {
    571         phymod_tx.pre2 = value1;
    572     } else {
    573         SOC_IF_ERROR_RETURN(phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &phymod_tx_def));
    574         phymod_tx.pre2 = phymod_tx_def.pre2;
    575 
    576     }
    577     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    578     return SOC_E_NONE;
    579 }
    580 
    581 
    582 STATIC int
    583 control_handler_tx_fir_pre_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    584 {
    585     phymod_tx_t phymod_tx, phymod_tx_def;
    586 
    587     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    588     if (value1 != 0xFFFFFFFF)
    589     {
    590         phymod_tx.pre = value1; 
    591     } else {
    592         SOC_IF_ERROR_RETURN(phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &phymod_tx_def));
    593         phymod_tx.pre = phymod_tx_def.pre;
    594 
    595     }
    596     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    597     return SOC_E_NONE;
    598 }
    599 
    600 
    601 STATIC int
    602 control_handler_tx_fir_main_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    603 {
    604     phymod_tx_t phymod_tx, phymod_tx_def;
    605 
    606     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    607     if (value1 != 0xFFFFFFFF)
    608     {
    609         phymod_tx.main = value1; 
    610     } else {
    611         SOC_IF_ERROR_RETURN(phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &phymod_tx_def));
    612         phymod_tx.main = phymod_tx_def.main;
    613 
    614     }
    615     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    616     return SOC_E_NONE;
    617 }
    618 
    619 
    620 STATIC int
    621 control_handler_tx_fir_post_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    622 {
    623     phymod_tx_t phymod_tx, phymod_tx_def;
    624 
    625     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    626     if (value1 != 0xFFFFFFFF)
    627     {
    628         phymod_tx.post = value1; 
    629     } else {
    630         SOC_IF_ERROR_RETURN(phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &phymod_tx_def));
    631         phymod_tx.post = phymod_tx_def.post;
    632 
    633     }
    634     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    635     return SOC_E_NONE;
    636 }
    637 
    638 
    639 STATIC int
    640 control_handler_tx_fir_post2_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    641 {
    642     phymod_tx_t phymod_tx, phymod_tx_def;
    643 
    644     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    645     if (value1 != 0xFFFFFFFF)
    646     {
    647         phymod_tx.post2 = value1; 
    648     } else {
    649         SOC_IF_ERROR_RETURN(phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &phymod_tx_def));
    650         phymod_tx.post2 = phymod_tx_def.post2;
    651 
    652     }
    653     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    654     return SOC_E_NONE;
    655 }
    656 
    657 
    658 STATIC int
    659 control_handler_tx_fir_post3_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    660 {
    661     phymod_tx_t phymod_tx, phymod_tx_def;
    662 
    663     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    664     if (value1 != 0xFFFFFFFF)
    665     {
    666         phymod_tx.post3 = value1; 
    667     } else {
    668         SOC_IF_ERROR_RETURN(phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &phymod_tx_def));
    669         phymod_tx.post3 = phymod_tx_def.post3;
    670 
    671     }
    672     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    673     return SOC_E_NONE;
    674 }
    675 
    676 STATIC int
    677 control_handler_link_training_tx_fir_post_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    678 {
    679     uint8_t tx_post = 0;
    680 
    681     tx_post = (uint8_t) value1;
    682     SOC_IF_ERROR_RETURN(phymod_phy_training_tx_fir_post_set(phy, tx_post));
    683     return SOC_E_NONE;
    684 }
    685 
    686 STATIC int
    687 control_handler_driver_current_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    688 {
    689     phymod_tx_t phymod_tx, phymod_tx_def;
    690 
    691     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    692     if (value1 != 0xFFFFFFFF)
    693     {
    694         phymod_tx.amp = value1; 
    695     } else {
    696         SOC_IF_ERROR_RETURN(phymod_phy_media_type_tx_get(phy, phymodMediaTypeChipToChip, &phymod_tx_def));
    697         phymod_tx.amp = phymod_tx_def.amp;
    698     }
    699     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    700     return SOC_E_NONE;
    701 }
    702 
    703 STATIC int
    704 control_handler_tx_fir_drivermode_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    705 {
    706     phymod_tx_t phymod_tx;
    707     int drivermode;
    708 
    709     if (phy == NULL) {
    710         return SOC_E_INTERNAL;
    711     }
    712     if(PHYMOD_INTF_CONFIG_TX_FIR_DRIVERMODE_ENABLE_GET(phy)) {
    713         drivermode = 1;
    714     } else {
    715         drivermode = 0;
    716         PHYMOD_INTF_CONFIG_TX_FIR_DRIVERMODE_ENABLE_SET(phy);
    717     }
    718 
    719     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
    720    
    721     phymod_tx.drivermode = value1; 
    722 
    723     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy, &phymod_tx));
    724 
    725     if(drivermode == 0) {
    726         PHYMOD_INTF_CONFIG_TX_FIR_DRIVERMODE_ENABLE_CLR(phy) ;
    727     }
    728 
    729     return SOC_E_NONE;
    730 }
    731 
    732 STATIC int
    733 control_handler_rx_tap_release(int unit, phymod_phy_access_t *phy, uint32 value, uint32 tap)
    734 {
    735     phymod_rx_t phymod_rx;
    736 
    737     /* bounds check "tap" */
    738     if (tap >= COUNTOF(phymod_rx.dfe)) {
    739         return SOC_E_INTERNAL;
    740     }
    741 
    742     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
    743     phymod_rx.dfe[tap].enable = FALSE;
    744     SOC_IF_ERROR_RETURN(phymod_phy_rx_adaptation_resume(phy));
    745 
    746     return SOC_E_NONE;
    747 }
    748 
    749 STATIC int
    750 control_handler_rx_adaptation_resume(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    751 {
    752     if (value1) {
    753         SOC_IF_ERROR_RETURN(phymod_phy_rx_adaptation_resume(phy));
    754     }
    755 
    756     return SOC_E_NONE;
    757 }
    758  
    759 STATIC int 
    760 control_handler_rx_tap_set(int unit, phymod_phy_access_t *phy, uint32 value, uint32 tap)
    761 {
    762     phymod_rx_t phymod_rx;
    763 
    764     /* bounds check "tap" */
    765     if (tap >= COUNTOF(phymod_rx.dfe)) {
    766         return SOC_E_INTERNAL;
    767     }
    768 
    769     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
    770     phymod_rx.dfe[tap].enable = TRUE;
    771     phymod_rx.dfe[tap].value = value;
    772     SOC_IF_ERROR_RETURN(phymod_phy_rx_set(phy, &phymod_rx));
    773 
    774     return SOC_E_NONE;
    775 }
    776 
    777 
    778 STATIC int 
    779 control_handler_pi_control_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    780 {
    781     phymod_tx_override_t tx_override;
    782 
    783     phymod_tx_override_t_init(&tx_override);
    784     tx_override.phase_interpolator.enable = (value1 == 0) ? 0 : 1;
    785     tx_override.phase_interpolator.value = value1;
    786     SOC_IF_ERROR_RETURN(phymod_phy_tx_override_set(phy, &tx_override));
    787 
    788     return SOC_E_NONE;
    789 }
    790 
    791 
    792 STATIC int
    793 control_handler_tx_squelch(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    794 {
    795     phymod_phy_tx_lane_control_t tx_control;
    796 
    797     if (value1 == 1) {
    798         tx_control = phymodTxSquelchOn;
    799     } else {
    800         tx_control = phymodTxSquelchOff;
    801     }
    802     SOC_IF_ERROR_RETURN(phymod_phy_tx_lane_control_set(phy, tx_control));
    803     return SOC_E_NONE;
    804 }
    805 
    806 STATIC int
    807 control_handler_rx_squelch(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    808 {
    809     phymod_phy_rx_lane_control_t rx_control;
    810 
    811     if (value1 == 1) {
    812         rx_control = phymodRxSquelchOn;
    813     } else {
    814         rx_control = phymodRxSquelchOff;
    815     }
    816     SOC_IF_ERROR_RETURN(phymod_phy_rx_lane_control_set(phy, rx_control));
    817     return SOC_E_NONE;
    818 }
    819 
    820 
    821 
    822 STATIC int
    823 control_handler_rx_peak_filter_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    824 {
    825     phymod_rx_t phymod_rx;
    826 
    827 
    828     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
    829     phymod_rx.peaking_filter.enable = TRUE;
    830     phymod_rx.peaking_filter.value = value1;
    831     SOC_IF_ERROR_RETURN(phymod_phy_rx_set(phy, &phymod_rx));
    832 
    833     return SOC_E_NONE;
    834 }
    835 
    836 STATIC int
    837 control_handler_rx_vga_release(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    838 {
    839     phymod_rx_t phymod_rx;
    840 
    841     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
    842     phymod_rx.vga.enable = FALSE;
    843     SOC_IF_ERROR_RETURN(phymod_phy_rx_set(phy, &phymod_rx));
    844     return SOC_E_NONE;
    845 }
    846 
    847 STATIC int 
    848 control_handler_rx_vga_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    849 {
    850     phymod_rx_t phymod_rx;
    851 
    852     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
    853     phymod_rx.vga.enable = TRUE;
    854     phymod_rx.vga.value = value1;
    855     SOC_IF_ERROR_RETURN(phymod_phy_rx_set(phy, &phymod_rx));
    856 
    857     return SOC_E_NONE;
    858 }
    859 
    860 STATIC int 
    861 control_handler_pattern_length_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    862 {
    863     phymod_pattern_t pattern;
    864     uint32 enable;
    865     uint32 pattern_arr[PATTERN_MAX_SIZE];
    866 
    867     pattern.pattern = pattern_arr;
    868 
    869     SOC_IF_ERROR_RETURN(phymod_phy_pattern_config_get(phy, &pattern));
    870     SOC_IF_ERROR_RETURN(phymod_phy_pattern_enable_get(phy, &enable));
    871     pattern.pattern_len = value1;
    872     SOC_IF_ERROR_RETURN(phymod_phy_pattern_enable_set(phy, 1, &pattern));
    873     if (!enable) {
    874         SOC_IF_ERROR_RETURN(phymod_phy_pattern_enable_set(phy, enable, &pattern)); 
    875     }
    876     return SOC_E_NONE;
    877 }
    878 
    879 STATIC int 
    880 control_handler_pattern_enable_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    881 {
    882     phymod_pattern_t pattern;
    883     uint32 enable;
    884     uint32 pattern_arr[PATTERN_MAX_SIZE];
    885 
    886     pattern.pattern = pattern_arr;
    887     enable = value1;
    888     SOC_IF_ERROR_RETURN(phymod_phy_pattern_config_get(phy, &pattern));
    889     SOC_IF_ERROR_RETURN(phymod_phy_pattern_enable_set(phy, enable, &pattern));
    890     return SOC_E_NONE;
    891 }
    892 
    893 STATIC int 
    894 control_handler_pattern_config_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    895 {
    896     phymod_pattern_t pattern;
    897 	uint32 pattern_arr[PATTERN_MAX_SIZE];
    898 
    899     pattern.pattern = pattern_arr;
    900 
    901     SOC_IF_ERROR_RETURN(phymod_phy_pattern_config_get(phy, &pattern));
    902     pattern.pattern[value2] = value1;
    903     SOC_IF_ERROR_RETURN(phymod_phy_pattern_config_set(phy, &pattern));
    904     return SOC_E_NONE;
    905 }
    906 
    907 
    908 STATIC int 
    909 control_handler_prbs_poly_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    910 {
    911     phymod_prbs_t prbs;
    912     uint32_t flags = 0;
    913 
    914     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
    915     SOC_IF_ERROR_RETURN(soc_prbs_poly_to_phymod(value1, &prbs.poly));
    916     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_set(phy, flags, &prbs));
    917     return SOC_E_NONE;
    918 }
    919 
    920 
    921 STATIC int
    922 control_handler_prbs_tx_poly_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    923 {
    924     phymod_prbs_t prbs;
    925     uint32_t flags = 0;
    926 
    927     PHYMOD_PRBS_DIRECTION_TX_SET(flags);
    928     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
    929     SOC_IF_ERROR_RETURN(soc_prbs_poly_to_phymod(value1, &prbs.poly));
    930     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_set(phy, flags, &prbs));
    931     return SOC_E_NONE;
    932 }
    933 
    934 
    935 STATIC int 
    936 control_handler_prbs_rx_poly_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    937 {
    938     phymod_prbs_t prbs;
    939     uint32_t flags = 0;
    940 
    941     PHYMOD_PRBS_DIRECTION_RX_SET(flags);
    942     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
    943     SOC_IF_ERROR_RETURN(soc_prbs_poly_to_phymod(value1, &prbs.poly));
    944     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_set(phy, flags, &prbs));
    945     return SOC_E_NONE;
    946 }
    947 
    948 
    949 STATIC int
    950 control_handler_prbs_tx_invert_data_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    951 {
    952     phymod_prbs_t prbs;
    953     uint32_t flags = 0;
    954 
    955     PHYMOD_PRBS_DIRECTION_TX_SET(flags);
    956     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
    957     prbs.invert = value1;
    958     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_set(phy, flags, &prbs));
    959     return SOC_E_NONE;
    960 }
    961 
    962 
    963 STATIC int
    964 control_handler_prbs_rx_invert_data_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    965 {
    966     phymod_prbs_t prbs;
    967     uint32_t flags = 0;
    968 
    969     PHYMOD_PRBS_DIRECTION_RX_SET(flags);
    970     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
    971     prbs.invert = value1;
    972     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_set(phy, flags, &prbs));
    973     return SOC_E_NONE;
    974 }
    975 
    976 
    977 STATIC int
    978 control_handler_prbs_tx_enable_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    979 {
    980     uint32_t flags = 0;
    981 
    982     PHYMOD_PRBS_DIRECTION_TX_SET(flags);
    983     SOC_IF_ERROR_RETURN(phymod_phy_prbs_enable_set(phy, flags, value1));
    984     return SOC_E_NONE;
    985 }
    986 
    987 
    988 STATIC int
    989 control_handler_prbs_rx_enable_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
    990 {
    991     uint32_t flags = 0;
    992 
    993     PHYMOD_PRBS_DIRECTION_RX_SET(flags);
    994     SOC_IF_ERROR_RETURN(phymod_phy_prbs_enable_set(phy, flags, value1));
    995     return SOC_E_NONE;
    996 }
    997 
    998 
    999 STATIC int
   1000 control_handler_rx_reset_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1001 {
   1002     phymod_phy_reset_t reset;
   1003 
   1004     SOC_IF_ERROR_RETURN(phymod_phy_reset_get(phy, &reset));
   1005     reset.rx = (value1 == 0)?  phymodResetDirectionOut : phymodResetDirectionIn;
   1006     SOC_IF_ERROR_RETURN(phymod_phy_reset_set(phy, &reset));
   1007 
   1008     return SOC_E_NONE;
   1009 }
   1010 
   1011 
   1012 STATIC int
   1013 control_handler_tx_reset_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1014 {
   1015     phymod_phy_reset_t reset;
   1016 
   1017     SOC_IF_ERROR_RETURN(phymod_phy_reset_get(phy, &reset));
   1018     reset.tx = (value1 == 0)?  phymodResetDirectionOut : phymodResetDirectionIn;
   1019     SOC_IF_ERROR_RETURN(phymod_phy_reset_set(phy, &reset));
   1020 
   1021     return SOC_E_NONE;
   1022 }
   1023 
   1024 
   1025 STATIC int
   1026 control_handler_dsc_dump_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1027 {
   1028     int nof_phys = 1;
   1029 
   1030     SOC_IF_ERROR_RETURN(phymod_diag_dsc(phy, nof_phys));
   1031 
   1032     return SOC_E_NONE;
   1033 
   1034         
   1035 
   1036 }
   1037 
   1038 STATIC int
   1039 control_handler_cl72_enable_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1040 {
   1041     SOC_IF_ERROR_RETURN(phymod_phy_cl72_set(phy, value1));
   1042 
   1043     return SOC_E_NONE;
   1044 }
   1045 
   1046 STATIC int
   1047 control_handler_short_chn_mode_enable_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1048 {
   1049     SOC_IF_ERROR_RETURN(phymod_phy_short_chn_mode_enable_set(phy, value1));
   1050 
   1051     return SOC_E_NONE;
   1052 }
   1053 
   1054 
   1055 STATIC int
   1056 control_handler_lane_map_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1057 {
   1058     phymod_core_access_t core;
   1059     phymod_lane_map_t lane_map;
   1060     uint32 idx;
   1061 
   1062     SOC_IF_ERROR_RETURN(phymod_core_access_t_init(&core));
   1063     core.type = phy->type;
   1064     sal_memcpy(&core.access, &phy->access, sizeof(core.access));
   1065     core.access.lane_mask = 0;
   1066 
   1067     lane_map.num_of_lanes = LANE_MAP_NOF_LANES;
   1068     for (idx=0; idx < LANE_MAP_NOF_LANES; idx++) {
   1069         lane_map.lane_map_rx[idx] = (value1 >> (idx * 4 /*4 bit per lane*/)) & 0xf;
   1070     }
   1071     for (idx=0; idx < LANE_MAP_NOF_LANES; idx++) {
   1072         lane_map.lane_map_tx[idx] = (value1 >> (16 + idx * 4 /*4 bit per lane*/)) & 0xf;
   1073     }
   1074     SOC_IF_ERROR_RETURN(phymod_core_lane_map_set(&core, &lane_map));
   1075     return SOC_E_NONE;
   1076 }
   1077 
   1078 
   1079 STATIC int 
   1080 control_handler_loopback_internal_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1081 {
   1082     SOC_IF_ERROR_RETURN
   1083         (phymod_phy_loopback_set(phy, phymodLoopbackGlobal, value1));
   1084 
   1085     return SOC_E_NONE;
   1086 }
   1087 
   1088 STATIC int 
   1089 control_handler_loopback_pmd_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1090 {
   1091     SOC_IF_ERROR_RETURN
   1092         (phymod_phy_loopback_set(phy, phymodLoopbackGlobalPMD, value1));
   1093 
   1094     return SOC_E_NONE;
   1095 }
   1096 
   1097 
   1098 STATIC int 
   1099 control_handler_loopback_remote_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1100 {
   1101     SOC_IF_ERROR_RETURN
   1102         (phymod_phy_loopback_set(phy, phymodLoopbackRemotePMD, value1));
   1103 
   1104     return SOC_E_NONE;
   1105 }
   1106 
   1107 #if 0
   1108 STATIC int 
   1109 control_handler_loopback_remote_pcs_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1110 {
   1111     SOC_IF_ERROR_RETURN
   1112         (phymod_phy_loopback_set(phy, phymodLoopbackRemotePCS, value1));
   1113 
   1114     return SOC_E_NONE;
   1115 }
   1116 #endif
   1117 
   1118 STATIC int
   1119 control_handler_power_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1120 {
   1121     phymod_phy_power_t      power;
   1122 
   1123     phymod_phy_power_t_init(&power);
   1124     if (value1) {
   1125         power.tx = phymodPowerOn;
   1126         power.rx = phymodPowerOn;
   1127     } 
   1128     else {
   1129         power.tx = phymodPowerOff;
   1130         power.rx = phymodPowerOff;
   1131     }
   1132      SOC_IF_ERROR_RETURN(phymod_phy_power_set(phy, &power));
   1133 
   1134     return SOC_E_NONE;
   1135 }
   1136 
   1137 STATIC int
   1138 control_handler_medium_type_set(int unit, phymod_phy_access_t *phy, uint32 medium_type, uint32 ref_clk)
   1139 {
   1140     phymod_phy_inf_config_t config;
   1141 
   1142     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_get(phy, 0 /* flags */, ref_clk, &config));
   1143     PHYMOD_INTF_MODES_FIBER_CLR(&config); 
   1144     PHYMOD_INTF_MODES_COPPER_CLR(&config); 
   1145     if (medium_type == SOC_PORT_MEDIUM_FIBER) {
   1146         PHYMOD_INTF_MODES_FIBER_SET(&config); 
   1147     } else if (medium_type == SOC_PORT_MEDIUM_COPPER){
   1148         PHYMOD_INTF_MODES_COPPER_SET(&config); 
   1149     }
   1150 
   1151     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_set(phy, 0 /* flags */,&config));
   1152 
   1153     return SOC_E_NONE;
   1154 }
   1155 
   1156 STATIC int
   1157 control_handler_rx_low_freq_filter_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1158 {
   1159     phymod_rx_t phymod_rx;
   1160 
   1161     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
   1162     phymod_rx.low_freq_peaking_filter.enable = TRUE;
   1163     phymod_rx.low_freq_peaking_filter.value = value1;
   1164     SOC_IF_ERROR_RETURN(phymod_phy_rx_set(phy, &phymod_rx));
   1165 
   1166     return SOC_E_NONE;
   1167 }
   1168 
   1169 STATIC int
   1170 control_handler_rx_high_freq_filter_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1171 {
   1172     phymod_rx_t phymod_rx;
   1173 
   1174     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
   1175     phymod_rx.high_freq_peaking_filter.enable = TRUE;
   1176     phymod_rx.high_freq_peaking_filter.value = value1;
   1177     SOC_IF_ERROR_RETURN(phymod_phy_rx_set(phy, &phymod_rx));
   1178 
   1179     return SOC_E_NONE;
   1180 }
   1181 
   1182 
   1183 
   1184 STATIC int
   1185 control_handler_firmware_mode_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1186 {
   1187     phymod_firmware_lane_config_t fw_config;
   1188     int mode = value1;
   1189     int control = value2;
   1190 
   1191     SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_get(phy, &fw_config));
   1192 
   1193     switch (control) {
   1194         case SOC_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE: 
   1195             if (mode) {
   1196                 fw_config.ForceBrDfe = 1;
   1197                 fw_config.DfeOn = 1;
   1198             } else {
   1199                 fw_config.ForceBrDfe = 0;
   1200             }
   1201             break;
   1202         case SOC_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE:
   1203             if (mode) {
   1204                 fw_config.LpDfeOn = 1;
   1205                 fw_config.DfeOn = 1;
   1206             } else {
   1207                 fw_config.LpDfeOn = 0;
   1208             }
   1209             break;
   1210         case SOC_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE:
   1211             fw_config.Cl72RestTO = mode ? 1 : 0;
   1212             break;
   1213         case SOC_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE:
   1214             fw_config.Cl72AutoPolEn = mode ? 1 : 0;
   1215             break;
   1216         case SOC_PHY_CONTROL_FIRMWARE_DFE_ENABLE:
   1217             fw_config.DfeOn = mode ? 1 : 0;
   1218             break;
   1219         case SOC_PHY_CONTROL_FIRMWARE_MODE:
   1220             /* Select FW parameters according to mode */
   1221             switch (mode) {
   1222                 case SOC_PHY_FIRMWARE_LP_DFE_ENABLE: 
   1223                     fw_config.LpDfeOn = 1;
   1224                     fw_config.DfeOn = 1;
   1225                     break;
   1226                 case SOC_PHY_FIRMWARE_FORCE_BRDFE:
   1227                     fw_config.ForceBrDfe = 1;
   1228                     fw_config.DfeOn = 1;
   1229                     break;
   1230                 case SOC_PHY_FIRMWARE_FORCE_OSDFE:
   1231                 case SOC_PHY_FIRMWARE_DFE_ENABLE:
   1232                     fw_config.DfeOn = 1;
   1233                     fw_config.ForceBrDfe = 0;
   1234                     break;
   1235                 case SOC_PHY_FIRMWARE_SFP_DAC:
   1236                     fw_config.MediaType = phymodFirmwareMediaTypeCopperCable;
   1237                     break;
   1238                 case SOC_PHY_FIRMWARE_XLAUI:
   1239                     fw_config.MediaType = phymodFirmwareMediaTypePcbTraceBackPlane;
   1240                     break;
   1241                 case SOC_PHY_FIRMWARE_SFP_OPT_SR4:
   1242                     fw_config.MediaType = phymodFirmwareMediaTypeOptics;
   1243                     break;
   1244                 case SOC_PHY_FIRMWARE_DEFAULT:
   1245                 default:
   1246                     fw_config.LaneConfigFromPCS = 0;
   1247                     fw_config.DfeOn = 0;
   1248                     fw_config.LpDfeOn = 0;
   1249                     fw_config.ForceBrDfe = 0;
   1250                     break;
   1251             }
   1252             break;
   1253         case SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE:
   1254             fw_config.ForceExtenedReach = mode ? 1 : 0;
   1255             break;
   1256         case SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE:
   1257             fw_config.ForceNormalReach = mode ? 1 : 0;
   1258             break;
   1259         default:
   1260             break;
   1261     }
   1262 
   1263     SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_set(phy, fw_config));
   1264 
   1265     return SOC_E_NONE;
   1266 }
   1267 
   1268 
   1269 STATIC int
   1270 control_handler_rx_seq_toggle_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1271 {
   1272     SOC_IF_ERROR_RETURN(phymod_phy_rx_restart(phy));
   1273     return SOC_E_NONE;
   1274 }
   1275 
   1276 
   1277 STATIC int
   1278 control_handler_scrambler_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 ref_clk)
   1279 {
   1280     phymod_phy_inf_config_t config;
   1281 
   1282     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_get(phy, 0 /* flags */, ref_clk, &config));
   1283     PHYMOD_INTF_MODES_SCR_SET(&config);
   1284     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_set(phy, PHYMOD_INTF_F_DONT_OVERIDE_TX_PARAMS, &config));
   1285 
   1286     return SOC_E_NONE;
   1287 }
   1288 
   1289 STATIC int
   1290 control_handler_fec_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 ref_clk)
   1291 {
   1292     
   1293     SOC_IF_ERROR_RETURN(phymod_phy_fec_enable_set(phy, value1));
   1294     return SOC_E_NONE;
   1295 }
   1296 
   1297 STATIC int 
   1298 control_handler_fec_override_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1299 {
   1300     
   1301     SOC_IF_ERROR_RETURN(phymod_phy_fec_override_set(phy, value1));
   1302     return SOC_E_NONE;
   1303 }
   1304 
   1305 STATIC int 
   1306 control_handler_tx_polarity_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1307 {
   1308     phymod_polarity_t    polarity;
   1309 
   1310     SOC_IF_ERROR_RETURN(phymod_phy_polarity_get(phy, &polarity));
   1311     polarity.tx_polarity = value1;
   1312     SOC_IF_ERROR_RETURN(phymod_phy_polarity_set(phy, &polarity));
   1313 
   1314     return SOC_E_NONE;
   1315 }
   1316 
   1317 
   1318 STATIC int 
   1319 control_handler_rx_polarity_set(int unit, phymod_phy_access_t *phy, uint32 value1, uint32 value2)
   1320 {
   1321     phymod_polarity_t    polarity;
   1322 
   1323     SOC_IF_ERROR_RETURN(phymod_phy_polarity_get(phy, &polarity));
   1324     polarity.rx_polarity = value1;
   1325     SOC_IF_ERROR_RETURN(phymod_phy_polarity_set(phy, &polarity));
   1326 
   1327     return SOC_E_NONE;
   1328 }
   1329 
   1330 STATIC int
   1331 control_handler_pam4_tx_pattern_set(int unit, phymod_phy_access_t *phy,  uint32 tx_pattern, uint32 param2)
   1332 {
   1333     if (tx_pattern == SOC_PHY_PAM4_TX_PATTERN_OFF) {
   1334         SOC_IF_ERROR_RETURN(phymod_phy_PAM4_tx_pattern_enable_set(phy, phymod_PAM4TxPattern_JP03B, 0));
   1335         SOC_IF_ERROR_RETURN(phymod_phy_PAM4_tx_pattern_enable_set(phy, phymod_PAM4TxPattern_Linear, 0));
   1336     } else if (tx_pattern == SOC_PHY_PAM4_TX_PATTERN_JP03B) {
   1337         SOC_IF_ERROR_RETURN(phymod_phy_PAM4_tx_pattern_enable_set(phy, phymod_PAM4TxPattern_JP03B, 1));
   1338     } else if (tx_pattern == SOC_PHY_PAM4_TX_PATTERN_LINEAR) {
   1339         SOC_IF_ERROR_RETURN(phymod_phy_PAM4_tx_pattern_enable_set(phy, phymod_PAM4TxPattern_Linear, 1));
   1340     } else {
   1341       return SOC_E_PARAM;
   1342     }
   1343     return SOC_E_NONE;
   1344 }
   1345 
   1346 STATIC int
   1347 control_handler_pcs_mode_set (int unit, phymod_phy_access_t *phy,  uint32 pcs_mode, uint32 param2)
   1348 {
   1349     phymod_phy_inf_config_t config;
   1350 
   1351     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_get(phy, 0 /* flags */, param2, &config));
   1352 
   1353     if (phy->type == phymodDispatchTypeTsce) {
   1354         if (PHYMOD_INTF_MODES_HIGIG_GET(&config) && 
   1355             ((config.data_rate == 40000) || (config.data_rate == 42000))) {
   1356             if (pcs_mode == SOC_PHY_CONTROL_PCS_MODE_BRCM) {
   1357                 config.interface_type = phymodInterfaceXGMII;
   1358             } else {
   1359                 if (config.interface_type == phymodInterfaceXGMII) {
   1360                     config.interface_type = phymodInterfaceKR4;
   1361                 }
   1362             }
   1363         } else {
   1364             return SOC_E_UNAVAIL;
   1365         }
   1366     } else {
   1367         return SOC_E_UNAVAIL;
   1368     }
   1369     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_set(phy, 0, &config));
   1370 
   1371     return SOC_E_NONE;
   1372 }
   1373 
   1374 STATIC int
   1375 control_handler_tx_pam4_precoder_enable_set(int unit, phymod_phy_access_t *phy,  uint32 value1, uint32 value2)
   1376 {
   1377     uint32_t  cl72_en = 0;
   1378 
   1379     /* first if link training is enabled */
   1380     SOC_IF_ERROR_RETURN(phymod_phy_cl72_get(phy, &cl72_en));
   1381 
   1382     if (cl72_en) {
   1383         LOG_ERROR(BSL_LS_SOC_COMMON,
   1384                   (BSL_META_U(unit,
   1385                   "ERROR: feature not supported with link training on \n")));
   1386         return SOC_E_FAIL;
   1387 
   1388     } else {
   1389         SOC_IF_ERROR_RETURN(phymod_phy_tx_pam4_precoder_enable_set(phy, (int) value1));
   1390     }
   1391     return SOC_E_NONE;
   1392 }
   1393 
   1394 STATIC int
   1395 control_handler_lp_tx_precoder_enable_set(int unit, phymod_phy_access_t *phy,  uint32 value1, uint32 value2)
   1396 {
   1397     phymod_firmware_lane_config_t fw_config;
   1398     uint32_t  cl72_en = 0;
   1399 
   1400     /* first if link training is enabled */
   1401     SOC_IF_ERROR_RETURN(phymod_phy_cl72_get(phy, &cl72_en));
   1402 
   1403     if (cl72_en) {
   1404         LOG_ERROR(BSL_LS_SOC_COMMON,
   1405                   (BSL_META_U(unit,
   1406                   "ERROR: feature not supported with link training on \n")));
   1407         return SOC_E_FAIL;
   1408     } else {
   1409         SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_get(phy, &fw_config));
   1410         fw_config.LpPrecoderEnabled = value1;
   1411         SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_set(phy, fw_config));
   1412     }
   1413     return SOC_E_NONE;
   1414 }
   1415 
   1416 STATIC int
   1417 control_handler_channel_loss_hint_set(int unit, phymod_phy_access_t *phy,  uint32 value1, uint32 value2)
   1418 {
   1419     SOC_IF_ERROR_RETURN(phymod_phy_channel_loss_hint_set(phy, value1));
   1420     return SOC_E_NONE;
   1421 }
   1422 
   1423 
   1424 
   1425 
   1426 /****************************************************************************** 
   1427  Get controls handlers
   1428  */
   1429 STATIC int
   1430 control_handler_preemphasis_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1431 {
   1432     phymod_tx_t phymod_tx;
   1433 
   1434     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1435     /* the shift is chip dependent.  Need to check later for other chips  */
   1436     *value = phymod_tx.pre  | (phymod_tx.main << 8) | (phymod_tx.post << 16);
   1437 
   1438     return SOC_E_NONE;
   1439 }
   1440 STATIC int
   1441 control_handler_tx_fir_mode_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1442 {
   1443     phymod_tx_t phymod_tx;
   1444 
   1445     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1446 
   1447     if (phymod_tx.tap_mode == phymodTxTapMode3Tap) {
   1448         *value = SOC_PHY_TX_FIR_3TAP_MODE;
   1449     } else if (phymod_tx.tap_mode == phymodTxTapMode6Tap) {
   1450         *value = SOC_PHY_TX_FIR_6TAP_MODE;
   1451     } else {
   1452       return SOC_E_PARAM;
   1453     }
   1454 
   1455 
   1456     return SOC_E_NONE;
   1457 }
   1458 
   1459 
   1460 STATIC int
   1461 control_handler_tx_fir_pre2_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1462 {
   1463     phymod_tx_t phymod_tx;
   1464 
   1465     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1466     *value = phymod_tx.pre2;
   1467     return SOC_E_NONE;
   1468 }
   1469 
   1470 STATIC int
   1471 control_handler_tx_fir_pre_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1472 {
   1473     phymod_tx_t phymod_tx;
   1474 
   1475     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1476     *value = phymod_tx.pre;
   1477     return SOC_E_NONE;
   1478 }
   1479 
   1480 
   1481 STATIC int
   1482 control_handler_tx_fir_main_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1483 {
   1484     phymod_tx_t phymod_tx;
   1485 
   1486     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1487     *value = phymod_tx.main;
   1488     return SOC_E_NONE;
   1489 }
   1490 
   1491 
   1492 STATIC int
   1493 control_handler_tx_fir_post_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1494 {
   1495     phymod_tx_t phymod_tx;
   1496 
   1497     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1498     *value = phymod_tx.post;
   1499     return SOC_E_NONE;
   1500 }
   1501 
   1502 
   1503 STATIC int
   1504 control_handler_tx_fir_post2_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1505 {
   1506     phymod_tx_t phymod_tx;
   1507 
   1508     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1509     *value = phymod_tx.post2;
   1510     return SOC_E_NONE;
   1511 }
   1512 
   1513 
   1514 STATIC int
   1515 control_handler_tx_fir_post3_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1516 {
   1517     phymod_tx_t phymod_tx;
   1518 
   1519     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1520     *value = phymod_tx.post3;
   1521     return SOC_E_NONE;
   1522 }
   1523 
   1524 
   1525 
   1526 STATIC int
   1527 control_handler_driver_current_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1528 {
   1529     phymod_tx_t phymod_tx;
   1530 
   1531     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1532     *value = phymod_tx.amp;
   1533     return SOC_E_NONE;
   1534 }
   1535 
   1536 STATIC int
   1537 control_handler_tx_fir_drivermode_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1538 {
   1539     phymod_tx_t phymod_tx;
   1540 
   1541     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy, &phymod_tx));
   1542     *value = phymod_tx.drivermode;
   1543     return SOC_E_NONE;
   1544 }
   1545 
   1546 STATIC int 
   1547 control_handler_rx_tap_get(int unit, phymod_phy_access_t *phy, uint32 tap, uint32 *value)
   1548 {
   1549     phymod_rx_t phymod_rx;
   1550 
   1551     /* bounds check "tap" */
   1552     if (tap >= COUNTOF(phymod_rx.dfe)) {
   1553         return SOC_E_INTERNAL;
   1554     }
   1555 
   1556     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
   1557     /* use phymod_rx.dfe[tap].enable as the indicator for PAM4 mode for BH*/
   1558     if ((tap == 0) && !phymod_rx.dfe[tap].enable) {
   1559         PHYMOD_DEBUG_ERROR(("ERROR :: DFE1 is not supported on PAM4 mode \n"));
   1560         return SOC_E_PARAM;
   1561     }
   1562     *value = phymod_rx.dfe[tap].value;
   1563 
   1564     return SOC_E_NONE;
   1565 }
   1566 
   1567 
   1568 STATIC int 
   1569 control_handler_pi_control_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1570 {
   1571     phymod_tx_override_t tx_override;
   1572 
   1573     SOC_IF_ERROR_RETURN(phymod_phy_tx_override_get(phy, &tx_override));
   1574     *value = tx_override.phase_interpolator.value;
   1575 
   1576     return SOC_E_NONE;
   1577 }
   1578 
   1579 
   1580 STATIC int
   1581 control_handler_tx_squelch_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1582 {
   1583     phymod_phy_tx_lane_control_t  tx_control;
   1584 
   1585     tx_control = phymodTxSquelchOn;
   1586     SOC_IF_ERROR_RETURN(phymod_phy_tx_lane_control_get(phy, &tx_control));
   1587     *value = (tx_control == phymodTxSquelchOn)? 1 : 0;
   1588 
   1589     return SOC_E_NONE;
   1590 }
   1591 
   1592 STATIC int
   1593 control_handler_rx_squelch_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1594 {
   1595     phymod_phy_rx_lane_control_t  rx_control;
   1596 
   1597     rx_control = phymodRxSquelchOn;
   1598     SOC_IF_ERROR_RETURN(phymod_phy_rx_lane_control_get(phy, &rx_control));
   1599     *value = (rx_control == phymodRxSquelchOn)? 1 : 0;
   1600 
   1601     return SOC_E_NONE;
   1602 }
   1603 
   1604 STATIC int
   1605 control_handler_power_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1606 {
   1607     phymod_phy_power_t      power;
   1608 
   1609     phymod_phy_power_t_init(&power);
   1610     SOC_IF_ERROR_RETURN(phymod_phy_power_get(phy, &power));
   1611 
   1612     if(power.tx == phymodPowerOn && power.rx == phymodPowerOn) {
   1613         *value = 1;
   1614     } else {
   1615         *value = 0;
   1616     }
   1617 
   1618     return SOC_E_NONE;
   1619 }
   1620 
   1621 STATIC int
   1622 control_handler_medium_type_get(int unit, phymod_phy_access_t *phy, uint32 ref_clk, uint32 *value)
   1623 {
   1624     phymod_phy_inf_config_t config;
   1625 
   1626     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_get(phy, 0 /* flags */, ref_clk, &config));
   1627     if (PHYMOD_INTF_MODES_FIBER_GET(&config)) {
   1628         *value = SOC_PORT_MEDIUM_FIBER; 
   1629     } else if (PHYMOD_INTF_MODES_COPPER_GET(&config)) {
   1630         *value = SOC_PORT_MEDIUM_COPPER; 
   1631     } else {
   1632         *value = SOC_PORT_MEDIUM_NONE;
   1633     }
   1634     return SOC_E_NONE;
   1635 }
   1636 
   1637 
   1638 
   1639 STATIC int
   1640 control_handler_rx_peak_filter_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1641 {
   1642     phymod_rx_t phymod_rx;
   1643 
   1644     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
   1645     *value = phymod_rx.peaking_filter.value;
   1646 
   1647     return SOC_E_NONE;
   1648 }
   1649 
   1650 
   1651 STATIC int 
   1652 control_handler_rx_vga_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1653 {
   1654     phymod_rx_t phymod_rx;
   1655 
   1656     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
   1657     *value = phymod_rx.vga.value;
   1658 
   1659     return SOC_E_NONE;
   1660 }
   1661 
   1662 STATIC int 
   1663 control_handler_pattern_length_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1664 {
   1665     phymod_pattern_t pattern;
   1666     uint32 pattern_arr[PATTERN_MAX_SIZE];
   1667 
   1668     pattern.pattern = pattern_arr;
   1669 
   1670     SOC_IF_ERROR_RETURN(phymod_phy_pattern_config_get(phy, &pattern));
   1671     *value = pattern.pattern_len;
   1672     return SOC_E_NONE;
   1673 }
   1674 
   1675 STATIC int 
   1676 control_handler_pattern_enable_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1677 {
   1678     phymod_pattern_t pattern;
   1679     uint32 enable;
   1680     uint32 pattern_arr[PATTERN_MAX_SIZE];
   1681 
   1682     pattern.pattern = pattern_arr;
   1683     SOC_IF_ERROR_RETURN(phymod_phy_pattern_config_get(phy, &pattern));
   1684     SOC_IF_ERROR_RETURN(phymod_phy_pattern_enable_get(phy, &enable));
   1685     *value = enable;
   1686     return SOC_E_NONE;
   1687 }
   1688 
   1689 STATIC int 
   1690 control_handler_pattern_config_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1691 {
   1692     phymod_pattern_t pattern;
   1693 	uint32 pattern_arr[PATTERN_MAX_SIZE];
   1694 
   1695     pattern.pattern = pattern_arr;
   1696 
   1697     SOC_IF_ERROR_RETURN(phymod_phy_pattern_config_get(phy, &pattern));
   1698     *value = pattern.pattern[param];
   1699     return SOC_E_NONE;
   1700 }
   1701 
   1702 STATIC int 
   1703 control_handler_prbs_poly_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1704 {
   1705     phymod_prbs_t prbs;
   1706     uint32_t flags = 0;
   1707 
   1708     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
   1709     SOC_IF_ERROR_RETURN(phymod_prbs_poly_to_soc(prbs.poly, value));
   1710     return SOC_E_NONE;
   1711 }
   1712 
   1713 
   1714 STATIC int
   1715 control_handler_prbs_tx_poly_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1716 {
   1717     phymod_prbs_t prbs;
   1718     uint32_t flags = 0;
   1719 
   1720     PHYMOD_PRBS_DIRECTION_TX_SET(flags);
   1721     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
   1722     SOC_IF_ERROR_RETURN(phymod_prbs_poly_to_soc(prbs.poly, value));
   1723     return SOC_E_NONE;
   1724 }
   1725 
   1726 
   1727 STATIC int 
   1728 control_handler_prbs_rx_poly_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1729 {
   1730     phymod_prbs_t prbs;
   1731     uint32_t flags = 0;
   1732 
   1733     PHYMOD_PRBS_DIRECTION_RX_SET(flags);
   1734     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
   1735     SOC_IF_ERROR_RETURN(phymod_prbs_poly_to_soc(prbs.poly, value));
   1736     return SOC_E_NONE;
   1737 }
   1738 
   1739 
   1740 STATIC int
   1741 control_handler_prbs_tx_invert_data_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1742 {
   1743     phymod_prbs_t prbs;
   1744     uint32_t flags = 0;
   1745 
   1746     PHYMOD_PRBS_DIRECTION_TX_SET(flags);
   1747     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
   1748     *value = prbs.invert;
   1749     return SOC_E_NONE;
   1750 }
   1751 
   1752 
   1753 STATIC int
   1754 control_handler_prbs_rx_invert_data_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1755 {
   1756     phymod_prbs_t prbs;
   1757     uint32_t flags = 0;
   1758 
   1759     PHYMOD_PRBS_DIRECTION_RX_SET(flags);
   1760     SOC_IF_ERROR_RETURN(phymod_phy_prbs_config_get(phy, flags, &prbs));
   1761     *value = prbs.invert;
   1762     return SOC_E_NONE;
   1763 }
   1764 
   1765 
   1766 STATIC int
   1767 control_handler_prbs_tx_enable_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1768 {
   1769     uint32_t flags = 0;
   1770 
   1771     PHYMOD_PRBS_DIRECTION_TX_SET(flags);
   1772     SOC_IF_ERROR_RETURN(phymod_phy_prbs_enable_get(phy, flags, value));
   1773     return SOC_E_NONE;
   1774 }
   1775 
   1776 
   1777 STATIC int
   1778 control_handler_prbs_rx_enable_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1779 {
   1780     uint32_t flags = 0;
   1781 
   1782     PHYMOD_PRBS_DIRECTION_RX_SET(flags);
   1783     SOC_IF_ERROR_RETURN(phymod_phy_prbs_enable_get(phy, flags, value));
   1784     return SOC_E_NONE;
   1785 }
   1786 
   1787 
   1788 
   1789 STATIC int
   1790 control_handler_prbs_rx_status_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1791 {
   1792     uint32_t flags = PHYMOD_PRBS_STATUS_F_CLEAR_ON_READ;
   1793     phymod_prbs_status_t status;
   1794 
   1795     SOC_IF_ERROR_RETURN(phymod_phy_prbs_status_get(phy, flags, &status));
   1796     if (status.prbs_lock==0){
   1797         *value = -1;
   1798     } else if (status.prbs_lock_loss) {
   1799         *value = -2;
   1800     } else{
   1801         *value = status.error_count;
   1802     }
   1803     return SOC_E_NONE;
   1804 }
   1805 
   1806 STATIC int
   1807 control_handler_cl72_enable_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1808 {
   1809     SOC_IF_ERROR_RETURN(phymod_phy_cl72_get(phy, value));
   1810 
   1811     return SOC_E_NONE;
   1812 }
   1813 
   1814 STATIC int
   1815 control_handler_short_chn_mode_enable_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1816 {
   1817     uint32_t status = 0;
   1818 
   1819     SOC_IF_ERROR_RETURN(phymod_phy_short_chn_mode_enable_get(phy, value, &status));
   1820 
   1821     return SOC_E_NONE;
   1822 }
   1823 
   1824 STATIC int
   1825 control_handler_short_chn_mode_status_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1826 {
   1827     uint32_t enable = 0;
   1828 
   1829     SOC_IF_ERROR_RETURN(phymod_phy_short_chn_mode_enable_get(phy, &enable, value));
   1830 
   1831     return SOC_E_NONE;
   1832 }
   1833 
   1834 STATIC int
   1835 control_handler_rx_signal_detect_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1836 {
   1837     SOC_IF_ERROR_RETURN(phymod_phy_rx_signal_detect_get(phy, value));
   1838 
   1839     return SOC_E_NONE;
   1840 }
   1841 
   1842 
   1843 
   1844 STATIC int
   1845 control_handler_cl72_status_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1846 {
   1847     phymod_cl72_status_t status;
   1848     SOC_IF_ERROR_RETURN(phymod_phy_cl72_status_get(phy, &status));
   1849     *value = status.locked;
   1850 
   1851     return SOC_E_NONE;
   1852 }
   1853 
   1854 
   1855 STATIC int
   1856 control_handler_lane_map_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1857 {
   1858     phymod_core_access_t core;
   1859     phymod_lane_map_t lane_map;
   1860     uint32 idx;
   1861 
   1862     SOC_IF_ERROR_RETURN(phymod_core_access_t_init(&core));
   1863     core.type = phy->type;
   1864     sal_memcpy(&core.access, &phy->access, sizeof(core.access));
   1865     core.access.lane_mask = 0;
   1866     *value = 0;
   1867     sal_memset(&lane_map, 0, sizeof(phymod_lane_map_t));
   1868 
   1869     SOC_IF_ERROR_RETURN(phymod_core_lane_map_get(&core, &lane_map));
   1870     if(lane_map.num_of_lanes != LANE_MAP_NOF_LANES){
   1871         return SOC_E_INTERNAL;
   1872     }
   1873     for (idx=0; idx < LANE_MAP_NOF_LANES; idx++) {
   1874         *value += ((lane_map.lane_map_rx[idx] & 0xf) << (idx * 4));
   1875     }
   1876     for (idx=0; idx < LANE_MAP_NOF_LANES; idx++) {
   1877         *value += ((lane_map.lane_map_tx[idx] & 0xf)<< (idx * 4 + 16));
   1878     }
   1879     
   1880     return SOC_E_NONE;
   1881 }
   1882 
   1883 
   1884 
   1885 STATIC int 
   1886 control_handler_loopback_internal_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1887 {
   1888     SOC_IF_ERROR_RETURN
   1889         (phymod_phy_loopback_get(phy, phymodLoopbackGlobal, value));
   1890 
   1891     return SOC_E_NONE;
   1892 }
   1893 
   1894 STATIC int 
   1895 control_handler_loopback_pmd_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1896 {
   1897     SOC_IF_ERROR_RETURN
   1898         (phymod_phy_loopback_get(phy, phymodLoopbackGlobalPMD, value));
   1899 
   1900     return SOC_E_NONE;
   1901 }
   1902 
   1903 STATIC int 
   1904 control_handler_loopback_remote_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1905 {
   1906     SOC_IF_ERROR_RETURN
   1907         (phymod_phy_loopback_get(phy, phymodLoopbackRemotePMD, value));
   1908 
   1909     return SOC_E_NONE;
   1910 }
   1911 
   1912 #if 0
   1913 STATIC int 
   1914 control_handler_loopback_remote_pcs_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1915 {
   1916     SOC_IF_ERROR_RETURN
   1917         (phymod_phy_loopback_get(phy, phymodLoopbackRemotePCS, value));
   1918 
   1919     return SOC_E_NONE;
   1920 }
   1921 #endif
   1922 
   1923 STATIC int
   1924 control_handler_rx_low_freq_filter_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1925 {
   1926     phymod_rx_t phymod_rx;
   1927 
   1928     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
   1929     *value = phymod_rx.low_freq_peaking_filter.value;
   1930 
   1931     return SOC_E_NONE;
   1932 }
   1933 
   1934 STATIC int
   1935 control_handler_rx_high_freq_filter_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1936 {
   1937     phymod_rx_t phymod_rx;
   1938 
   1939     SOC_IF_ERROR_RETURN(phymod_phy_rx_get(phy, &phymod_rx));
   1940     *value = phymod_rx.high_freq_peaking_filter.value;
   1941 
   1942     return SOC_E_NONE;
   1943 }
   1944 
   1945 
   1946 STATIC int
   1947 control_handler_scrambler_get(int unit, phymod_phy_access_t *phy, uint32 ref_clk, uint32 *value)
   1948 {
   1949     phymod_phy_inf_config_t config;
   1950 
   1951     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_get(phy, 0 /* flags */, ref_clk, &config));
   1952     *value = PHYMOD_INTF_MODES_SCR_GET(&config); 
   1953 
   1954     return SOC_E_NONE;
   1955 }
   1956 
   1957 STATIC int
   1958 control_handler_fec_get(int unit, phymod_phy_access_t *phy, uint32 ref_clk, uint32 *value)
   1959 {
   1960     uint32_t               enable = *value;
   1961 
   1962     SOC_IF_ERROR_RETURN(phymod_phy_fec_enable_get(phy,  &enable));
   1963     *value = enable; 
   1964 
   1965     return SOC_E_NONE;
   1966 }
   1967 
   1968 STATIC int
   1969 control_handler_fec_override_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1970 {
   1971 
   1972     SOC_IF_ERROR_RETURN(phymod_phy_fec_override_get(phy, value));
   1973 
   1974     return SOC_E_NONE;
   1975 }
   1976 
   1977 STATIC int
   1978 control_handler_firmware_mode_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   1979 {
   1980     phymod_firmware_lane_config_t fw_config;
   1981     int control = param;
   1982 
   1983     SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_get(phy, &fw_config));
   1984 
   1985     switch (control) {
   1986     case SOC_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE:
   1987         *value = fw_config.DfeOn && fw_config.ForceBrDfe ? 1 : 0;
   1988         break;
   1989     case SOC_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE:
   1990         *value = fw_config.DfeOn && fw_config.LpDfeOn ? 1 : 0;
   1991         break;
   1992     case SOC_PHY_CONTROL_FIRMWARE_DFE_ENABLE:
   1993         *value = fw_config.DfeOn ? 1 : 0;
   1994         break;
   1995     case SOC_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE:
   1996         *value = fw_config.Cl72RestTO ? 1 : 0;
   1997         break;
   1998     case SOC_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE:
   1999         *value = fw_config.Cl72AutoPolEn ? 1 : 0;
   2000         break;
   2001     case SOC_PHY_CONTROL_FIRMWARE_MODE:
   2002         if ((fw_config.LpDfeOn) && (fw_config.DfeOn)) {
   2003             *value = SOC_PHY_FIRMWARE_LP_DFE_ENABLE;
   2004         } else if ((fw_config.ForceBrDfe) && (fw_config.DfeOn)) {
   2005             *value = SOC_PHY_FIRMWARE_FORCE_BRDFE;
   2006         } else if (fw_config.DfeOn) {
   2007             *value = SOC_PHY_FIRMWARE_DFE_ENABLE;
   2008         } else {
   2009             *value = SOC_PHY_FIRMWARE_DEFAULT;
   2010         }
   2011         break;
   2012     case SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE:
   2013         *value = fw_config.ForceExtenedReach ? 1 : 0;
   2014         break;
   2015     case SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE:
   2016         *value = fw_config.ForceNormalReach ? 1 : 0;
   2017         break;
   2018     }
   2019                     
   2020 
   2021     return SOC_E_NONE;
   2022 
   2023 }
   2024 STATIC int
   2025 control_handler_rx_seq_done_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   2026 {
   2027 
   2028     SOC_IF_ERROR_RETURN(phymod_phy_rx_pmd_locked_get(phy, value));
   2029 
   2030     return SOC_E_NONE;
   2031 }
   2032 
   2033 STATIC int 
   2034 control_handler_tx_polarity_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   2035 {
   2036     phymod_polarity_t    polarity;
   2037 
   2038     SOC_IF_ERROR_RETURN(phymod_phy_polarity_get(phy, &polarity));
   2039     *value = polarity.tx_polarity;
   2040 
   2041     return SOC_E_NONE;
   2042 }
   2043 
   2044 
   2045 STATIC int 
   2046 control_handler_rx_polarity_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   2047 {
   2048     phymod_polarity_t    polarity;
   2049 
   2050     SOC_IF_ERROR_RETURN(phymod_phy_polarity_get(phy, &polarity));
   2051     *value = polarity.rx_polarity;
   2052 
   2053     return SOC_E_NONE;
   2054 }
   2055 
   2056 
   2057 STATIC int
   2058 control_handler_rx_reset_get(int unit, phymod_phy_access_t *phy,  uint32 param, uint32 *value)
   2059 {
   2060     phymod_phy_reset_t reset;
   2061 
   2062     SOC_IF_ERROR_RETURN(phymod_phy_reset_get(phy, &reset));
   2063     *value = (reset.rx  == phymodResetDirectionIn) ?  1 : 0;
   2064 
   2065     return SOC_E_NONE;
   2066 }
   2067 
   2068 
   2069 STATIC int
   2070 control_handler_tx_reset_get(int unit, phymod_phy_access_t *phy,  uint32 param, uint32 *value)
   2071 {
   2072     phymod_phy_reset_t reset;
   2073 
   2074     SOC_IF_ERROR_RETURN(phymod_phy_reset_get(phy, &reset));
   2075     *value = (reset.tx  == phymodResetDirectionIn) ?  1 : 0;
   2076 
   2077     return SOC_E_NONE;
   2078 }
   2079 
   2080 STATIC int
   2081 control_handler_interface_set (int unit, phymod_phy_access_t *phy,  uint32 intf_type, uint32 param2)
   2082 {
   2083     phymod_phy_inf_config_t config;
   2084 
   2085     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_get(phy, 0 /* flags */, param2, &config));
   2086     SOC_IF_ERROR_RETURN(soc_phymod_phy_intf_from_port_intf(unit,
   2087                     config.data_rate, intf_type, &(config.interface_type)));
   2088     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_set(phy, 0, &config));
   2089 
   2090     return SOC_E_NONE;
   2091 }
   2092 
   2093 STATIC int
   2094 control_handler_interface_get (int unit, phymod_phy_access_t *phy, uint32_t param2,  uint32_t *intf_type )
   2095 {
   2096     phymod_phy_inf_config_t config;
   2097 
   2098     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_get(phy, 0 /* flags */, param2, &config));
   2099     SOC_IF_ERROR_RETURN(soc_phymod_phy_intf_to_port_intf(unit, config.interface_type, intf_type));
   2100 
   2101     return SOC_E_NONE;
   2102 }
   2103 
   2104 STATIC int
   2105 control_handler_gpio_config_set(int unit, phymod_phy_access_t *phy,  uint32 value, uint32 param2) {
   2106     int gpio_pin_no = 0 ;
   2107     phymod_gpio_mode_t gpio_mode= (value >= phymodGpioModeCount)? phymodGpioModeDisabled : value;
   2108 
   2109     for (gpio_pin_no = 0; gpio_pin_no < 4; gpio_pin_no++) {
   2110         gpio_mode = (value >> (4 * gpio_pin_no)) & 0xF;
   2111         SOC_IF_ERROR_RETURN(phymod_phy_gpio_config_set(phy, gpio_pin_no, gpio_mode));
   2112     }
   2113 
   2114     return SOC_E_NONE;
   2115 }
   2116 
   2117 STATIC int
   2118 control_handler_gpio_config_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2119     int gpio_pin_no = 0 ;
   2120     phymod_gpio_mode_t gpio_mode= phymodGpioModeDisabled;
   2121 
   2122 
   2123     for (gpio_pin_no = 0; gpio_pin_no < 4; gpio_pin_no++) {
   2124         SOC_IF_ERROR_RETURN(phymod_phy_gpio_config_get(phy, gpio_pin_no, &gpio_mode));
   2125         *value |= (gpio_mode << (4 * gpio_pin_no));
   2126     }
   2127 
   2128     return SOC_E_NONE;
   2129 }
   2130 
   2131 STATIC int
   2132 control_handler_gpio_pin_value_set(int unit, phymod_phy_access_t *phy,  uint32 value, uint32 param2) {
   2133     int gpio_pin_no = 0 ;
   2134     int gpio_pin_value = 0 ;
   2135 
   2136     for (gpio_pin_no = 0; gpio_pin_no < 4; gpio_pin_no++) {
   2137         gpio_pin_value = (value >> (4 * gpio_pin_no)) & 0xF;
   2138         SOC_IF_ERROR_RETURN(phymod_phy_gpio_pin_value_set(phy, gpio_pin_no, gpio_pin_value));
   2139     }
   2140 
   2141     return SOC_E_NONE;
   2142 }
   2143 
   2144 STATIC int
   2145 control_handler_gpio_pin_value_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2146     int gpio_pin_no = 0 ;
   2147     int gpio_pin_value = 0 ;
   2148 
   2149 
   2150     for (gpio_pin_no = 0; gpio_pin_no < 4; gpio_pin_no++) {
   2151         SOC_IF_ERROR_RETURN(phymod_phy_gpio_pin_value_get(phy, gpio_pin_no, &gpio_pin_value));
   2152         *value |= (gpio_pin_value << (4 * gpio_pin_no));
   2153     }
   2154 
   2155     return SOC_E_NONE;
   2156 }
   2157 
   2158 STATIC int
   2159 control_handler_intr_status_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2160 
   2161     *value = 0;
   2162     SOC_IF_ERROR_RETURN(phymod_phy_intr_status_get(phy, value));
   2163 
   2164     return(phymod_phy_intr_status_clear(phy, *value));
   2165 }
   2166 
   2167 STATIC int
   2168 control_handler_linkdown_transmit_set(int unit, phymod_phy_access_t *phy,  uint32 value, uint32 param2) {
   2169 
   2170     return SOC_E_NONE;
   2171 }
   2172 
   2173 STATIC int
   2174 control_handler_linkdown_transmit_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2175 
   2176     return SOC_E_NONE;
   2177 }
   2178 
   2179 STATIC int
   2180 control_handler_intr_enable_set(int unit, phymod_phy_access_t *phy,  uint32 value, uint32 param2) {
   2181 
   2182     return(phymod_phy_intr_enable_set(phy, value));
   2183 }
   2184 
   2185 STATIC int
   2186 control_handler_intr_enable_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2187 
   2188     return(phymod_phy_intr_enable_get(phy, value));
   2189 }
   2190 
   2191 STATIC int
   2192 control_handler_unreliable_los_enable_set(int unit, phymod_phy_access_t *phy,  uint32 value, uint32 param2) {
   2193 
   2194     phymod_firmware_lane_config_t config;
   2195     SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_get(phy, &config));
   2196     config.UnreliableLos = value;
   2197     SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_set(phy, config));
   2198 
   2199     return SOC_E_NONE;
   2200 }
   2201 
   2202 STATIC int
   2203 control_handler_unreliable_los_enable_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2204 
   2205     phymod_firmware_lane_config_t config;
   2206     SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_get(phy, &config));
   2207     *value = config.UnreliableLos;
   2208 
   2209     return SOC_E_NONE;
   2210 }
   2211 
   2212 STATIC int
   2213 control_handler_eye_margin_hz_l_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2214 
   2215     SOC_IF_ERROR_RETURN(phymod_phy_eye_margin_est_get(phy, phymod_eye_marign_HZ_L, value));
   2216 
   2217     return SOC_E_NONE;
   2218 }
   2219 
   2220 STATIC int
   2221 control_handler_eye_margin_hz_r_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2222 
   2223     SOC_IF_ERROR_RETURN(phymod_phy_eye_margin_est_get(phy, phymod_eye_marign_HZ_R, value));
   2224 
   2225     return SOC_E_NONE;
   2226 }
   2227 
   2228 STATIC int
   2229 control_handler_eye_margin_vt_u_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2230 
   2231     SOC_IF_ERROR_RETURN(phymod_phy_eye_margin_est_get(phy, phymod_eye_marign_VT_U, value));
   2232 
   2233     return SOC_E_NONE;
   2234 }
   2235 
   2236 STATIC int
   2237 control_handler_eye_margin_vt_d_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value) {
   2238 
   2239     SOC_IF_ERROR_RETURN(phymod_phy_eye_margin_est_get(phy, phymod_eye_marign_VT_D, value));
   2240 
   2241     return SOC_E_NONE;
   2242 }
   2243 
   2244 STATIC int
   2245 control_handler_autoneg_get (int unit, phymod_phy_access_t *phy, uint32_t param2,  uint32_t *value )
   2246 {
   2247     phymod_autoneg_control_t an;
   2248     int an_done;
   2249     SOC_IF_ERROR_RETURN(phymod_phy_autoneg_get(phy, &an, (uint32 *)&an_done));
   2250     switch(an.an_mode) {
   2251         case phymod_AN_MODE_CL37:
   2252             *value= SOC_PHY_CONTROL_AUTONEG_MODE_CL37;
   2253             break;
   2254         case phymod_AN_MODE_CL37BAM:
   2255             *value = SOC_PHY_CONTROL_AUTONEG_MODE_CL37_BAM;
   2256             break;
   2257         case phymod_AN_MODE_CL73:
   2258             *value = SOC_PHY_CONTROL_AUTONEG_MODE_CL73;
   2259             break;
   2260         case phymod_AN_MODE_CL73BAM:
   2261             *value = SOC_PHY_CONTROL_AUTONEG_MODE_CL73_BAM;
   2262             break;
   2263         default:
   2264             return SOC_E_PARAM;
   2265             break;
   2266     }
   2267     return SOC_E_NONE;
   2268 }
   2269 
   2270 STATIC int
   2271 control_handler_pm_codec_enable_set(int unit,
   2272                                    phymod_phy_access_t *phy,
   2273                                    uint32_t value,
   2274                                    uint32_t param2)
   2275 {
   2276     phymod_phy_hg2_codec_t codec_mode;
   2277 
   2278     if (phy == NULL) return SOC_E_INTERNAL;
   2279 
   2280     switch (value) {
   2281         case SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF:
   2282             codec_mode = phymodBcmHG2CodecOff;
   2283             break;
   2284         case SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG:
   2285             codec_mode = phymodBcmHG2CodecOnWith8ByteIPG;
   2286             break;
   2287         case SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG:
   2288             codec_mode = phymodBcmHG2CodecOnWith9ByteIPG;
   2289             break;
   2290         default:
   2291             codec_mode = phymodBcmHG2CodecOff;
   2292             break;
   2293     }
   2294 
   2295     return (phymod_phy_hg2_codec_control_set(phy, codec_mode));
   2296 }
   2297 
   2298 STATIC int
   2299 control_handler_pm_codec_enable_get(int unit,
   2300                                    phymod_phy_access_t *phy,
   2301                                    uint32_t param2,
   2302                                    uint32_t *value)
   2303 {
   2304     phymod_phy_hg2_codec_t codec_mode;
   2305 
   2306     if (phy == NULL) return SOC_E_INTERNAL;
   2307 
   2308     SOC_IF_ERROR_RETURN(phymod_phy_hg2_codec_control_get(phy, &codec_mode));
   2309 
   2310     switch (codec_mode) {
   2311         case phymodBcmHG2CodecOff:
   2312             *value = SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF;
   2313             break;
   2314         case phymodBcmHG2CodecOnWith8ByteIPG:
   2315             *value = SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG;
   2316             break;
   2317         case phymodBcmHG2CodecOnWith9ByteIPG:
   2318             *value = SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG;
   2319             break;
   2320         default:
   2321             *value = SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF;
   2322             break;
   2323 
   2324     }
   2325     return SOC_E_NONE;
   2326 }
   2327 
   2328 STATIC int
   2329 control_handler_eee_set(int unit, phymod_phy_access_t *phy,  uint32 value, uint32 param2) {
   2330     SOC_IF_ERROR_RETURN(phymod_phy_eee_set(phy, value));
   2331     return SOC_E_NONE;
   2332 }
   2333 
   2334 STATIC int
   2335 control_handler_eee_get (int unit, phymod_phy_access_t *phy, uint32_t param2,  uint32_t *value )
   2336 {
   2337     SOC_IF_ERROR_RETURN(phymod_phy_eee_get(phy, value));
   2338     return SOC_E_NONE;
   2339 }
   2340 
   2341 STATIC int
   2342 control_handler_pam4_tx_pattern_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   2343 {
   2344     uint32_t linear_enable = 0;
   2345     uint32_t jp03b_enable = 0;
   2346 
   2347     SOC_IF_ERROR_RETURN(phymod_phy_PAM4_tx_pattern_enable_get(phy, phymod_PAM4TxPattern_JP03B, &jp03b_enable));
   2348     SOC_IF_ERROR_RETURN(phymod_phy_PAM4_tx_pattern_enable_get(phy, phymod_PAM4TxPattern_Linear, &linear_enable));
   2349     if (jp03b_enable) {
   2350         *value = SOC_PHY_PAM4_TX_PATTERN_JP03B;
   2351     } else if (linear_enable) {
   2352         *value = SOC_PHY_PAM4_TX_PATTERN_LINEAR;
   2353     } else {
   2354         *value = SOC_PHY_PAM4_TX_PATTERN_OFF;
   2355     }
   2356     return SOC_E_NONE;
   2357 }
   2358 
   2359 STATIC int
   2360 control_handler_pcs_mode_get (int unit, phymod_phy_access_t *phy, uint32 param2, uint32 *value)
   2361 {
   2362     phymod_phy_inf_config_t config;
   2363 
   2364     SOC_IF_ERROR_RETURN(phymod_phy_interface_config_get(phy, 0 /* flags */, param2, &config));
   2365 
   2366     if (phy->type == phymodDispatchTypeTsce) {
   2367         if (PHYMOD_INTF_MODES_HIGIG_GET(&config)) {
   2368             if (config.interface_type == phymodInterfaceXGMII) {
   2369                 *value = SOC_PHY_CONTROL_PCS_MODE_BRCM;
   2370             } else {
   2371                 *value = SOC_PHY_CONTROL_PCS_MODE_IEEE;
   2372             }
   2373             return SOC_E_NONE;
   2374         }
   2375     }
   2376 
   2377     *value = SOC_PHY_CONTROL_PCS_MODE_IEEE;
   2378     return SOC_E_NONE;
   2379 }
   2380 
   2381 STATIC int
   2382 control_handler_fec_counter_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   2383 {
   2384     if (param) {
   2385         SOC_IF_ERROR_RETURN(phymod_phy_fec_uncorrectable_counter_get(phy, value));
   2386     } else {
   2387         SOC_IF_ERROR_RETURN(phymod_phy_fec_correctable_counter_get(phy, value));
   2388     }
   2389     return SOC_E_NONE;
   2390 }
   2391 
   2392 STATIC int
   2393 control_handler_fec_cl91_counter_get(int unit, phymod_phy_access_t *phy, uint32 param, uint32 *value)
   2394 {
   2395     if (param) {
   2396         SOC_IF_ERROR_RETURN(phymod_phy_fec_cl91_uncorrectable_counter_get(phy, value));
   2397     } else {
   2398         SOC_IF_ERROR_RETURN(phymod_phy_fec_cl91_correctable_counter_get(phy, value));
   2399     }
   2400     return SOC_E_NONE;
   2401 }
   2402 
   2403 STATIC int
   2404 control_handler_fec_bypass_indication_set(int unit, phymod_phy_access_t *phy,  uint32_t value, uint32_t param2) {
   2405     SOC_IF_ERROR_RETURN(phymod_phy_fec_bypass_indication_set(phy, value));
   2406     return SOC_E_NONE;
   2407 }
   2408 
   2409 STATIC int
   2410 control_handler_fec_bypass_indication_get (int unit, phymod_phy_access_t *phy, uint32_t param2,  uint32_t *value )
   2411 {
   2412     SOC_IF_ERROR_RETURN(phymod_phy_fec_bypass_indication_get(phy, value));
   2413     return SOC_E_NONE;
   2414 }
   2415 
   2416 STATIC int
   2417 control_handler_pdet_set(int unit, phymod_phy_access_t *phy,  uint32 value, uint32 param2)
   2418 {
   2419     phymod_autoneg_control_t an_config;
   2420     uint32      an_done;
   2421     int           rv = SOC_E_NONE, num_lane = 0;
   2422     uint32_t lane_mask;
   2423     int control = param2;
   2424 
   2425     sal_memset(&an_config, 0, sizeof(phymod_autoneg_control_t));
   2426 
   2427     SOC_IF_ERROR_RETURN(phymod_phy_autoneg_get(phy, &an_config, &an_done));
   2428     lane_mask = phy->access.lane_mask;
   2429     while (lane_mask) {
   2430         if (lane_mask & 0x1) num_lane++;
   2431         lane_mask >>= 1;
   2432     }
   2433     an_config.num_lane_adv = num_lane;
   2434 
   2435     switch (control) {
   2436         case SOC_PHY_CONTROL_PARALLEL_DETECTION:
   2437             if (value) {
   2438                 PHYMOD_AN_F_SET_CL73_PDET_KX_ENABLE_SET(&an_config);
   2439             } else {
   2440                 PHYMOD_AN_F_SET_CL73_PDET_KX_ENABLE_CLR(&an_config);
   2441             }
   2442             break;
   2443         case SOC_PHY_CONTROL_PARALLEL_DETECTION_10G:
   2444             if (value) {
   2445                 PHYMOD_AN_F_SET_CL73_PDET_KX4_ENABLE_SET(&an_config);
   2446             } else {
   2447                 PHYMOD_AN_F_SET_CL73_PDET_KX4_ENABLE_CLR(&an_config);
   2448             }
   2449             break;
   2450     }
   2451 
   2452     rv = phymod_phy_autoneg_set(phy, &an_config);
   2453     /* Because the returned value PHYMOD_E_UNAVAIL is -12 from tscf phymod driver */
   2454     if (rv == PHYMOD_E_UNAVAIL) {
   2455         rv = SOC_E_UNAVAIL;
   2456     }
   2457 
   2458     return rv;
   2459 
   2460 }
   2461 
   2462 STATIC int
   2463 control_handler_pdet_get (int unit, phymod_phy_access_t *phy, uint32_t param,  uint32_t *value )
   2464 {
   2465     phymod_autoneg_control_t an_config;
   2466     uint32      an_done;
   2467     int control = param;
   2468 
   2469     sal_memset(&an_config, 0, sizeof(phymod_autoneg_control_t));
   2470 
   2471     SOC_IF_ERROR_RETURN(phymod_phy_autoneg_get(phy, &an_config, &an_done));
   2472     switch (control) {
   2473         case SOC_PHY_CONTROL_PARALLEL_DETECTION:
   2474             if (PHYMOD_AN_F_SET_CL73_PDET_KX_ENABLE_GET(&an_config)) {
   2475                 *value = 1;
   2476             } else {
   2477                 *value = 0;
   2478             }
   2479             break;
   2480         case SOC_PHY_CONTROL_PARALLEL_DETECTION_10G:
   2481             if (PHYMOD_AN_F_SET_CL73_PDET_KX4_ENABLE_GET(&an_config)) {
   2482                 *value = 1;
   2483             } else {
   2484                 *value = 0;
   2485             }
   2486             break;
   2487     }
   2488 
   2489     return SOC_E_NONE;
   2490 }
   2491 
   2492 STATIC int
   2493 control_handler_tx_pam4_precoder_enable_get(int unit, phymod_phy_access_t *phy,  uint32 param,  uint32 *value)
   2494 {
   2495     int temp_value; 
   2496     SOC_IF_ERROR_RETURN(phymod_phy_tx_pam4_precoder_enable_get(phy,&temp_value));
   2497     *value = (uint32_t) temp_value;
   2498     return SOC_E_NONE;
   2499 }
   2500 
   2501 STATIC int
   2502 control_handler_lp_tx_precoder_enable_get(int unit, phymod_phy_access_t *phy,  uint32 param,  uint32 *value)
   2503 {
   2504     phymod_firmware_lane_config_t fw_config;
   2505 
   2506     SOC_IF_ERROR_RETURN(phymod_phy_firmware_lane_config_get(phy, &fw_config));
   2507     *value = fw_config.LpPrecoderEnabled;
   2508     return SOC_E_NONE;
   2509 }
   2510 
   2511 STATIC int
   2512 control_handler_rx_ppm_get(int unit, phymod_phy_access_t *phy, uint32_t param2, uint32_t *value)
   2513 {
   2514     int rv = SOC_E_NONE;
   2515     int16 rx_ppm = 0;
   2516 
   2517     rv = phymod_phy_rx_ppm_get(phy, &rx_ppm);
   2518     /* Because the returned value PHYMOD_E_UNAVAIL is -12 from viper phymod driver */
   2519     if (rv == PHYMOD_E_UNAVAIL) {
   2520         rv = SOC_E_UNAVAIL;
   2521     } else {
   2522         *value = (uint32_t)rx_ppm;
   2523     }
   2524 
   2525     return rv;
   2526 }
   2527 
   2528 STATIC int
   2529 control_handler_fast_ber_proj_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value)
   2530 {
   2531 
   2532     SOC_IF_ERROR_RETURN(phymod_phy_fast_ber_proj_get(phy, value));
   2533 
   2534     return SOC_E_NONE;
   2535 }
   2536 
   2537 
   2538 STATIC int
   2539 control_handler_channel_loss_hint_get(int unit, phymod_phy_access_t *phy,  uint32 param2, uint32 *value)
   2540 {
   2541 
   2542     SOC_IF_ERROR_RETURN(phymod_phy_channel_loss_hint_get(phy, value));
   2543 
   2544     return SOC_E_NONE;
   2545 }
   2546 
   2547 
   2548 
   2549 /****************************************************************************** 
   2550   port and phy control set wrapers
   2551  */
   2552 
   2553 
   2554 /* when calling this function,  make sure pack enough array of phymod_phy_access_t if nof_phys != 1, and phys points to the first object */
   2555 /* assume the phymod_phy_access object is just a working copy, no need to make a copy again or reset the object content */
   2556 int soc_port_control_get_wrapper(int unit, phymod_ref_clk_t ref_clock, int is_lane_control, phymod_phy_access_t *phys, int nof_phys, soc_phy_control_t control, uint32 *value)
   2557 {
   2558     control_get_handler_f handler = NULL;
   2559     uint32 param = 0;
   2560     int i;
   2561     int lane_control_support = FALSE;
   2562 
   2563     if ((control < 0) || (control >= SOC_PHY_CONTROL_COUNT)) {
   2564         return (SOC_E_PARAM);
   2565     }
   2566 
   2567     *value = 0;
   2568     switch(control) {
   2569     case SOC_PHY_CONTROL_TX_FIR_MODE:
   2570         handler = control_handler_tx_fir_mode_get;
   2571         lane_control_support = TRUE;
   2572         break;
   2573     case SOC_PHY_CONTROL_TX_FIR_PRE2:
   2574         handler = control_handler_tx_fir_pre2_get;
   2575         lane_control_support = TRUE;
   2576         break;
   2577     case SOC_PHY_CONTROL_TX_FIR_PRE:
   2578         handler = control_handler_tx_fir_pre_get;
   2579         lane_control_support = TRUE;
   2580         break;
   2581     case SOC_PHY_CONTROL_TX_FIR_MAIN:
   2582         handler = control_handler_tx_fir_main_get;
   2583         lane_control_support = TRUE;
   2584         break;
   2585     case SOC_PHY_CONTROL_TX_FIR_POST:
   2586         handler = control_handler_tx_fir_post_get;
   2587         lane_control_support = TRUE;
   2588         break;
   2589     case SOC_PHY_CONTROL_TX_FIR_POST2:
   2590         handler = control_handler_tx_fir_post2_get;
   2591         lane_control_support = TRUE;
   2592         break;
   2593     case SOC_PHY_CONTROL_TX_FIR_POST3:
   2594         handler = control_handler_tx_fir_post3_get;
   2595         lane_control_support = TRUE;
   2596         break;
   2597     /* PREEMPHASIS */
   2598     case SOC_PHY_CONTROL_PREEMPHASIS:
   2599         handler = control_handler_preemphasis_get;
   2600         lane_control_support = TRUE;
   2601         break;
   2602     case SOC_PHY_CONTROL_PREEMPHASIS_LANE0:
   2603         phys->access.lane_mask = 0x1 ;
   2604         handler = control_handler_preemphasis_get;
   2605         lane_control_support = TRUE;
   2606         break;
   2607     case SOC_PHY_CONTROL_PREEMPHASIS_LANE1:
   2608         phys->access.lane_mask = 0x2 ;
   2609         handler = control_handler_preemphasis_get;
   2610         lane_control_support = TRUE;
   2611         break;
   2612     case SOC_PHY_CONTROL_PREEMPHASIS_LANE2:
   2613         phys->access.lane_mask = 0x4 ;
   2614         handler = control_handler_preemphasis_get;
   2615         lane_control_support = TRUE;
   2616         break;
   2617     case SOC_PHY_CONTROL_PREEMPHASIS_LANE3:
   2618         phys->access.lane_mask = 0x8 ;
   2619         handler = control_handler_preemphasis_get;
   2620         lane_control_support = TRUE;
   2621         break;
   2622     /* DRIVER CURRENT */
   2623     case SOC_PHY_CONTROL_DRIVER_CURRENT_LANE0:
   2624         phys->access.lane_mask = 0x1 ;
   2625         handler = control_handler_driver_current_get;
   2626         lane_control_support = TRUE;
   2627         break;
   2628     case SOC_PHY_CONTROL_DRIVER_CURRENT_LANE1:
   2629         phys->access.lane_mask = 0x2 ;
   2630         handler = control_handler_driver_current_get;
   2631         lane_control_support = TRUE;
   2632         break;
   2633     case SOC_PHY_CONTROL_DRIVER_CURRENT_LANE2:
   2634         phys->access.lane_mask = 0x4 ;
   2635         handler = control_handler_driver_current_get;
   2636         lane_control_support = TRUE;
   2637         break;
   2638     case SOC_PHY_CONTROL_DRIVER_CURRENT_LANE3:
   2639         phys->access.lane_mask = 0x8 ;
   2640         handler = control_handler_driver_current_get;
   2641         lane_control_support = TRUE;
   2642         break;
   2643     case SOC_PHY_CONTROL_DRIVER_CURRENT:
   2644         handler = control_handler_driver_current_get;
   2645         lane_control_support = TRUE;
   2646         break;
   2647     case SOC_PHY_CONTROL_TX_FIR_DRIVERMODE:
   2648         handler = control_handler_tx_fir_drivermode_get;
   2649         lane_control_support = TRUE;
   2650         break;
   2651      /* TX LANE SQUELCH */
   2652     case SOC_PHY_CONTROL_TX_LANE_SQUELCH:
   2653         handler = control_handler_tx_squelch_get;
   2654         lane_control_support = TRUE;
   2655         break;
   2656      /* RX LANE SQUELCH */
   2657     case SOC_PHY_CONTROL_RX_LANE_SQUELCH:
   2658         handler = control_handler_rx_squelch_get;
   2659         lane_control_support = TRUE;
   2660         break;
   2661     /* RX PEAK FILTER */
   2662     case SOC_PHY_CONTROL_RX_PEAK_FILTER:
   2663         handler = control_handler_rx_peak_filter_get;
   2664         lane_control_support = TRUE;
   2665         break;
   2666     /* RX VGA */
   2667     case SOC_PHY_CONTROL_RX_VGA:
   2668         handler = control_handler_rx_vga_get;
   2669         lane_control_support = TRUE;
   2670         break;
   2671     /* RX TAP */
   2672     case SOC_PHY_CONTROL_RX_TAP1:
   2673         handler = control_handler_rx_tap_get;
   2674         lane_control_support = TRUE;
   2675         break;
   2676     case SOC_PHY_CONTROL_RX_TAP2:
   2677         handler = control_handler_rx_tap_get;
   2678         lane_control_support = TRUE;
   2679         param = 1;
   2680         break;
   2681     case SOC_PHY_CONTROL_RX_TAP3:
   2682         handler = control_handler_rx_tap_get;
   2683         lane_control_support = TRUE;
   2684         param = 2;
   2685         break;
   2686     case SOC_PHY_CONTROL_RX_TAP4:
   2687         handler = control_handler_rx_tap_get;
   2688         lane_control_support = TRUE;
   2689         param = 3;
   2690         break;
   2691     case SOC_PHY_CONTROL_RX_TAP5:
   2692         handler = control_handler_rx_tap_get;
   2693         lane_control_support = TRUE;
   2694         param = 4;
   2695         break;
   2696     case SOC_PHY_CONTROL_RX_TAP6:
   2697         handler = control_handler_rx_tap_get;
   2698         lane_control_support = TRUE;
   2699         param = 5;
   2700         break;
   2701     /* PHASE INTERPOLATOR */
   2702     case SOC_PHY_CONTROL_PHASE_INTERP:
   2703     case SOC_PHY_CONTROL_TX_PPM_ADJUST:
   2704         handler = control_handler_pi_control_get;
   2705         lane_control_support = TRUE;
   2706         break;
   2707 
   2708     /* RX_SIGNAL_DETECT  */
   2709     case SOC_PHY_CONTROL_RX_SIGNAL_DETECT :
   2710         handler = control_handler_rx_signal_detect_get;
   2711         lane_control_support = TRUE;
   2712         break;
   2713 
   2714     /* CL72 ENABLE */
   2715     case SOC_PHY_CONTROL_CL72:
   2716         handler = control_handler_cl72_enable_get;
   2717         lane_control_support = TRUE;
   2718         break;
   2719 
   2720     /* SHORT_CHANNEL_MODE ENABLE */
   2721     case SOC_PHY_CONTROL_SHORT_CHANNEL_MODE:
   2722         handler = control_handler_short_chn_mode_enable_get;
   2723         lane_control_support = TRUE;
   2724         break;
   2725 
   2726     /* SHORT_CHANNEL_MODE ENABLE STATUS*/
   2727     case SOC_PHY_CONTROL_SHORT_CHANNEL_MODE_STATUS:
   2728         handler = control_handler_short_chn_mode_status_get;
   2729         lane_control_support = TRUE;
   2730         break;
   2731 
   2732     /* CL72 STATUS */
   2733     case SOC_PHY_CONTROL_CL72_STATUS:
   2734         handler = control_handler_cl72_status_get;
   2735         lane_control_support = TRUE;
   2736         break;
   2737 
   2738     /* LANE SWAP */
   2739     case SOC_PHY_CONTROL_LANE_SWAP:
   2740         handler = control_handler_lane_map_get;
   2741         break;
   2742     /* TX PATTERN */
   2743     case SOC_PHY_CONTROL_TX_PATTERN_LENGTH:
   2744         handler = control_handler_pattern_length_get;
   2745         lane_control_support = TRUE;
   2746         break ;
   2747     case SOC_PHY_CONTROL_TX_PATTERN_GEN_ENABLE:
   2748         handler = control_handler_pattern_enable_get;
   2749         lane_control_support = TRUE;
   2750         break ;
   2751     case SOC_PHY_CONTROL_TX_PATTERN_DATA0:
   2752         handler = control_handler_pattern_config_get;
   2753         lane_control_support = TRUE;
   2754         param = 0;
   2755         break;
   2756     case SOC_PHY_CONTROL_TX_PATTERN_DATA1:
   2757         handler = control_handler_pattern_config_get;
   2758         lane_control_support = TRUE;
   2759         param = 1;
   2760         break;
   2761     case SOC_PHY_CONTROL_TX_PATTERN_DATA2:
   2762         handler = control_handler_pattern_config_get;
   2763         lane_control_support = TRUE;
   2764         param = 2;
   2765         break;
   2766     case SOC_PHY_CONTROL_TX_PATTERN_DATA3:
   2767         handler = control_handler_pattern_config_get;
   2768         lane_control_support = TRUE;
   2769         param = 3;
   2770         break;
   2771     case SOC_PHY_CONTROL_TX_PATTERN_DATA4:
   2772         handler = control_handler_pattern_config_get;
   2773         lane_control_support = TRUE;
   2774         param = 4;
   2775         break;
   2776     case SOC_PHY_CONTROL_TX_PATTERN_DATA5:
   2777         handler = control_handler_pattern_config_get;
   2778         lane_control_support = TRUE;
   2779         param = 5;
   2780         break;
   2781     case SOC_PHY_CONTROL_TX_PATTERN_DATA6:
   2782         handler = control_handler_pattern_config_get;
   2783         lane_control_support = TRUE;
   2784         param = 6;
   2785         break;
   2786     case SOC_PHY_CONTROL_TX_PATTERN_DATA7:
   2787         handler = control_handler_pattern_config_get;
   2788         lane_control_support = TRUE;
   2789         param = 7;
   2790         break;
   2791     /* PRBS */
   2792     case SOC_PHY_CONTROL_PRBS_POLYNOMIAL:
   2793         handler = control_handler_prbs_poly_get;
   2794         lane_control_support = TRUE;
   2795         break;
   2796     case SOC_PHY_CONTROL_PRBS_TX_INVERT_DATA:
   2797         handler = control_handler_prbs_tx_invert_data_get;
   2798         lane_control_support = TRUE;
   2799         break;
   2800     case SOC_PHY_CONTROL_PRBS_TX_ENABLE:
   2801         handler = control_handler_prbs_tx_enable_get;
   2802         lane_control_support = TRUE;
   2803         break;
   2804     case SOC_PHY_CONTROL_PRBS_RX_INVERT_DATA:
   2805         handler = control_handler_prbs_rx_invert_data_get;
   2806         lane_control_support = TRUE;
   2807         break;
   2808     case SOC_PHY_CONTROL_PRBS_RX_ENABLE:
   2809         handler = control_handler_prbs_rx_enable_get;
   2810         lane_control_support = TRUE;
   2811         break;
   2812     case SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL:
   2813         handler = control_handler_prbs_tx_poly_get;
   2814         lane_control_support = TRUE;
   2815         break;
   2816     case SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA:
   2817         handler = control_handler_prbs_tx_invert_data_get;
   2818         lane_control_support = TRUE;
   2819         break;
   2820     case SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE:
   2821         handler = control_handler_prbs_tx_enable_get;
   2822         lane_control_support = TRUE;
   2823         break; 
   2824     case SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL:
   2825         handler = control_handler_prbs_rx_poly_get;
   2826         lane_control_support = TRUE;
   2827         break;
   2828     case SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA:
   2829         handler = control_handler_prbs_rx_invert_data_get;
   2830         lane_control_support = TRUE;
   2831         break;
   2832     case SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE:
   2833         handler = control_handler_prbs_rx_enable_get;
   2834         lane_control_support = TRUE;
   2835         break; 
   2836     case SOC_PHY_CONTROL_PRBS_RX_STATUS:
   2837         handler = control_handler_prbs_rx_status_get;
   2838         lane_control_support = TRUE;
   2839         break;
   2840     /* LOOPBACK */
   2841     case SOC_PHY_CONTROL_LOOPBACK_INTERNAL:
   2842         handler = control_handler_loopback_internal_get;
   2843         lane_control_support = TRUE;
   2844        break;
   2845     case SOC_PHY_CONTROL_LOOPBACK_PMD:
   2846         handler = control_handler_loopback_pmd_get;
   2847         lane_control_support = TRUE;
   2848        break;
   2849 
   2850     case SOC_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS:
   2851         handler = control_handler_loopback_remote_get;
   2852         lane_control_support = TRUE;
   2853         break;
   2854 
   2855     /* SCRAMBLER */
   2856     case SOC_PHY_CONTROL_SCRAMBLER:
   2857         handler = control_handler_scrambler_get;
   2858         param = ref_clock;
   2859         break;
   2860     case SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION:
   2861         handler = control_handler_fec_get;
   2862         param = ref_clock;
   2863         lane_control_support = TRUE;
   2864         break;
   2865     case SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91:
   2866         handler = control_handler_fec_get;
   2867         param = ref_clock;
   2868         lane_control_support = TRUE;
   2869         PHYMOD_FEC_CL108_CLR(*value);
   2870         PHYMOD_FEC_CL91_SET(*value);
   2871         break;
   2872     case SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108:
   2873         handler = control_handler_fec_get;
   2874         param = ref_clock;
   2875         lane_control_support = TRUE;
   2876         PHYMOD_FEC_CL91_CLR(*value);
   2877         PHYMOD_FEC_CL108_SET(*value);
   2878         break;
   2879     case SOC_PHY_CONTROL_AUTONEG_FEC_OVERRIDE:
   2880         handler = control_handler_fec_override_get;
   2881         lane_control_support = TRUE;
   2882         break;        
   2883     /* RX_LOW_FREQ_PEAK_FILTER */
   2884     case SOC_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER:
   2885         handler = control_handler_rx_low_freq_filter_get;
   2886         lane_control_support = TRUE;
   2887         break;
   2888     /* RX_HIGH_FREQ_PEAK_FILTER */
   2889     case SOC_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER:
   2890         handler = control_handler_rx_high_freq_filter_get;
   2891         lane_control_support = TRUE;
   2892         break;
   2893     /* RX_SEQ_DONE */
   2894     case SOC_PHY_CONTROL_RX_SEQ_DONE:
   2895        handler = control_handler_rx_seq_done_get;
   2896        lane_control_support = TRUE;
   2897        break;
   2898     case SOC_PHY_CONTROL_TX_POLARITY:
   2899         handler = control_handler_tx_polarity_get;
   2900         lane_control_support = TRUE;
   2901         break;
   2902     case SOC_PHY_CONTROL_RX_POLARITY:
   2903         handler = control_handler_rx_polarity_get;
   2904         lane_control_support = TRUE;
   2905         break;
   2906      /* RESET */
   2907     case SOC_PHY_CONTROL_RX_RESET:
   2908         handler = control_handler_rx_reset_get;
   2909         lane_control_support = TRUE;
   2910         break;
   2911     case SOC_PHY_CONTROL_TX_RESET:
   2912         handler = control_handler_tx_reset_get;
   2913         lane_control_support = TRUE;
   2914         break;
   2915     /* POWER */
   2916     case SOC_PHY_CONTROL_POWER:
   2917         handler = control_handler_power_get;
   2918         lane_control_support = TRUE;
   2919         break;
   2920     case SOC_PHY_CONTROL_FIRMWARE_MODE:
   2921     case SOC_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE:
   2922     case SOC_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE:
   2923     case SOC_PHY_CONTROL_FIRMWARE_DFE_ENABLE:
   2924     case SOC_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE:
   2925     case SOC_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE:
   2926     case SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE:
   2927     case SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE:
   2928         handler = control_handler_firmware_mode_get;
   2929         lane_control_support = TRUE;
   2930         param = control;
   2931         break; 
   2932     case SOC_PHY_CONTROL_MEDIUM_TYPE:
   2933         handler = control_handler_medium_type_get;
   2934         lane_control_support = TRUE;
   2935         param = ref_clock;
   2936         break;
   2937 
   2938     case SOC_PHY_CONTROL_INTERFACE:
   2939         /* value=interface type, control=switch param */ 
   2940         handler = control_handler_interface_get;
   2941         param = ref_clock;
   2942         lane_control_support = TRUE;
   2943         break;
   2944 
   2945     case SOC_PHY_CONTROL_LOOPBACK_REMOTE:
   2946         /* handler = control_handler_loopback_remote_pcs_get; */
   2947         handler = control_handler_loopback_remote_get;
   2948         lane_control_support = TRUE;
   2949         break;
   2950 
   2951     case SOC_PHY_CONTROL_GPIO_CONFIG:
   2952         handler = control_handler_gpio_config_get;
   2953         lane_control_support = TRUE;
   2954         break;
   2955 
   2956     case SOC_PHY_CONTROL_GPIO_VALUE:
   2957         handler = control_handler_gpio_pin_value_get;
   2958         lane_control_support = TRUE;
   2959         break;
   2960 
   2961 
   2962     case SOC_PHY_CONTROL_INTR_STATUS:
   2963         handler = control_handler_intr_status_get;
   2964         lane_control_support = TRUE;
   2965         break;
   2966 
   2967     case SOC_PHY_CONTROL_INTR_MASK:
   2968         handler = control_handler_intr_enable_get;
   2969         lane_control_support = TRUE;
   2970         break;
   2971 
   2972     case SOC_PHY_CONTROL_UNRELIABLE_LOS:
   2973         handler = control_handler_unreliable_los_enable_get;
   2974         lane_control_support = TRUE;
   2975         break;
   2976     case SOC_PHY_CONTROL_EYE_VAL_HZ_L:
   2977         handler = control_handler_eye_margin_hz_l_get;
   2978         lane_control_support = TRUE;
   2979         break;
   2980     case SOC_PHY_CONTROL_EYE_VAL_HZ_R:
   2981         handler = control_handler_eye_margin_hz_r_get;
   2982         lane_control_support = TRUE;
   2983         break;
   2984     case SOC_PHY_CONTROL_EYE_VAL_VT_U:
   2985         handler = control_handler_eye_margin_vt_u_get;
   2986         lane_control_support = TRUE;
   2987         break;
   2988     case SOC_PHY_CONTROL_EYE_VAL_VT_D:
   2989         handler = control_handler_eye_margin_vt_d_get;
   2990         lane_control_support = TRUE;
   2991         break;
   2992     case SOC_PHY_CONTROL_AUTONEG_MODE:
   2993         handler = control_handler_autoneg_get;
   2994         lane_control_support = TRUE;
   2995         break;
   2996     case SOC_PHY_CONTROL_LINKDOWN_TRANSMIT:
   2997 	handler = control_handler_linkdown_transmit_get;
   2998 	lane_control_support = TRUE;
   2999 	break;
   3000     case SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE:
   3001         handler = control_handler_pm_codec_enable_get;
   3002         lane_control_support = TRUE;
   3003         break;
   3004     case SOC_PHY_CONTROL_EEE:
   3005         handler = control_handler_eee_get;
   3006         lane_control_support = TRUE;
   3007         break;
   3008     case SOC_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE:
   3009         handler = control_handler_pam4_tx_pattern_get;
   3010         lane_control_support = TRUE;
   3011         break;
   3012     case SOC_PHY_CONTROL_PCS_MODE:
   3013         handler = control_handler_pcs_mode_get;
   3014         lane_control_support = TRUE;
   3015         break;
   3016     case SOC_PHY_CONTROL_FEC_CORRECTED_BLOCK_COUNT:
   3017         handler = control_handler_fec_counter_get;
   3018         lane_control_support = TRUE;
   3019         break;
   3020     case SOC_PHY_CONTROL_FEC_UNCORRECTED_BLOCK_COUNT:
   3021         handler = control_handler_fec_counter_get;
   3022         lane_control_support = TRUE;
   3023         param = 1;
   3024         break;
   3025     case SOC_PHY_CONTROL_FEC_CORRECTED_CODEWORD_COUNT:
   3026         handler = control_handler_fec_cl91_counter_get;
   3027         break;
   3028     case SOC_PHY_CONTROL_FEC_UNCORRECTED_CODEWORD_COUNT:
   3029         handler = control_handler_fec_cl91_counter_get;
   3030         param = 1;
   3031         break;
   3032     case SOC_PHY_CONTROL_PARALLEL_DETECTION:
   3033     case SOC_PHY_CONTROL_PARALLEL_DETECTION_10G:
   3034         handler = control_handler_pdet_get;
   3035         lane_control_support = TRUE;
   3036         param = control;
   3037         break;
   3038     case SOC_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE:
   3039         handler = control_handler_tx_pam4_precoder_enable_get;
   3040         lane_control_support = TRUE;
   3041         break;
   3042     case SOC_PHY_CONTROL_LP_TX_PRECODER_ENABLE:
   3043         handler = control_handler_lp_tx_precoder_enable_get;
   3044         lane_control_support = TRUE;
   3045         break;
   3046     case SOC_PHY_CONTROL_RX_PPM:
   3047         handler = control_handler_rx_ppm_get;
   3048         lane_control_support = TRUE;
   3049         break;
   3050     case SOC_PHY_CONTROL_FAST_BER_PROJ:
   3051         handler = control_handler_fast_ber_proj_get;
   3052         lane_control_support = TRUE;
   3053         break;
   3054     case SOC_PHY_CONTROL_CHANNEL_LOSS_HINT:
   3055         handler = control_handler_channel_loss_hint_get;
   3056         lane_control_support = TRUE;
   3057         break;
   3058     case SOC_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE:
   3059         handler = control_handler_fec_bypass_indication_get;
   3060         lane_control_support = TRUE;
   3061         break;
   3062     default: 
   3063         return SOC_E_UNAVAIL;
   3064         break; 
   3065     }
   3066     if(is_lane_control && !lane_control_support){
   3067         return SOC_E_UNAVAIL;
   3068     }
   3069     if(handler == NULL){
   3070         return SOC_E_INTERNAL;
   3071     }
   3072 
   3073     if(phys[0].access.lane_mask){
   3074         SOC_IF_ERROR_RETURN(handler(unit, &phys[0], param, value));
   3075     }
   3076 
   3077     if(control == SOC_PHY_CONTROL_PRBS_RX_STATUS){
   3078         uint32 value2 = 0;
   3079         for(i = 1 ; i < nof_phys ; i++){
   3080 
   3081             /* if lane mask is zero, skip it. */
   3082             if(phys[i].access.lane_mask){
   3083                 SOC_IF_ERROR_RETURN(handler(unit, &phys[i], param, &value2));
   3084 
   3085                 /* -1 !prbs_lock ,  -2 prbs_lock_loss, 0 1 2 ... prbs err cnt.
   3086                    -1 supersede everybody.
   3087                    -2 is next in line
   3088                     0 ..   treated equally. */
   3089 
   3090             if( ((int)(*value)) != -1 ) {
   3091                 if((int)value2 < 0){
   3092                         *value = value2;
   3093                 } else if( ((int)(*value)) >=0 ) {
   3094                         *value += value2;
   3095                     }
   3096                 }
   3097             }
   3098         }
   3099     } else {
   3100         for(i = 1 ; i < nof_phys ; i++){
   3101             if(phys[i].access.lane_mask){
   3102                 SOC_IF_ERROR_RETURN(handler(unit, &phys[i], param, value));
   3103             }
   3104         }
   3105     }
   3106 
   3107     return SOC_E_NONE;
   3108 }
   3109 
   3110 int soc_port_control_set_wrapper(int unit, phymod_ref_clk_t ref_clock, int is_lane_control, phymod_phy_access_t *phys, int nof_phys, soc_phy_control_t control, uint32 value)
   3111 {
   3112     control_set_handler_f handler = NULL;
   3113     uint32 param2 = 0;
   3114     int lane_control_support = FALSE;
   3115     int i;
   3116 
   3117     if ((control < 0) || (control >= SOC_PHY_CONTROL_COUNT)) {
   3118         return (SOC_E_PARAM);
   3119     }
   3120 
   3121     switch(control) {
   3122     case SOC_PHY_CONTROL_TX_FIR_MODE:
   3123         handler = control_handler_tx_fir_mode_set;
   3124         lane_control_support = TRUE;
   3125         break;
   3126     case SOC_PHY_CONTROL_TX_FIR_PRE2:
   3127         handler = control_handler_tx_fir_pre2_set;
   3128         lane_control_support = TRUE;
   3129         break;
   3130     case SOC_PHY_CONTROL_TX_FIR_PRE:
   3131         handler = control_handler_tx_fir_pre_set;
   3132         lane_control_support = TRUE;
   3133         break;
   3134     case SOC_PHY_CONTROL_TX_FIR_MAIN:
   3135         handler = control_handler_tx_fir_main_set;
   3136         lane_control_support = TRUE;
   3137         break;
   3138     case SOC_PHY_CONTROL_TX_FIR_POST:
   3139         handler = control_handler_tx_fir_post_set;
   3140         lane_control_support = TRUE;
   3141         break;
   3142     case SOC_PHY_CONTROL_TX_FIR_POST2:
   3143         handler = control_handler_tx_fir_post2_set;
   3144         lane_control_support = TRUE;
   3145         break;
   3146     case SOC_PHY_CONTROL_TX_FIR_POST3:
   3147         handler = control_handler_tx_fir_post3_set;
   3148         lane_control_support = TRUE;
   3149         break;
   3150     case SOC_PHY_CONTROL_LINK_TRAINING_INIT_TX_FIR_POST:
   3151         handler = control_handler_link_training_tx_fir_post_set;
   3152         lane_control_support = TRUE;
   3153         break;
   3154     /* PREEMPHASIS */
   3155     case SOC_PHY_CONTROL_PREEMPHASIS:
   3156         handler = control_handler_preemphasis_set;
   3157         lane_control_support = TRUE;
   3158         break;
   3159     case SOC_PHY_CONTROL_PREEMPHASIS_LANE0:
   3160         phys->access.lane_mask = 0x1 ;
   3161         handler = control_handler_preemphasis_set;
   3162         lane_control_support = TRUE;
   3163         break;
   3164     case SOC_PHY_CONTROL_PREEMPHASIS_LANE1:
   3165         phys->access.lane_mask = 0x2 ;
   3166         handler = control_handler_preemphasis_set;
   3167         lane_control_support = TRUE;
   3168         break;
   3169     case SOC_PHY_CONTROL_PREEMPHASIS_LANE2:
   3170         phys->access.lane_mask = 0x4 ;
   3171         handler = control_handler_preemphasis_set;
   3172         lane_control_support = TRUE;
   3173         break;
   3174     case SOC_PHY_CONTROL_PREEMPHASIS_LANE3:
   3175         phys->access.lane_mask = 0x8 ;
   3176         handler = control_handler_preemphasis_set;
   3177         lane_control_support = TRUE;
   3178         break;
   3179     /* DRIVER CURRENT */
   3180     case SOC_PHY_CONTROL_DRIVER_CURRENT_LANE0:
   3181          phys->access.lane_mask = 0x1 ;
   3182         handler = control_handler_driver_current_set;
   3183         lane_control_support = TRUE;
   3184         break;
   3185     case SOC_PHY_CONTROL_DRIVER_CURRENT_LANE1:
   3186          phys->access.lane_mask = 0x2 ;
   3187         handler = control_handler_driver_current_set;
   3188         lane_control_support = TRUE;
   3189         break;
   3190     case SOC_PHY_CONTROL_DRIVER_CURRENT_LANE2:
   3191          phys->access.lane_mask = 0x4 ;
   3192         handler = control_handler_driver_current_set;
   3193         lane_control_support = TRUE;
   3194         break;
   3195     case SOC_PHY_CONTROL_DRIVER_CURRENT_LANE3:
   3196          phys->access.lane_mask = 0x8 ;
   3197         handler = control_handler_driver_current_set;
   3198         lane_control_support = TRUE;
   3199         break;
   3200     case SOC_PHY_CONTROL_DRIVER_CURRENT:
   3201         handler = control_handler_driver_current_set;
   3202         lane_control_support = TRUE;
   3203         break;
   3204     case SOC_PHY_CONTROL_TX_FIR_DRIVERMODE:
   3205         handler = control_handler_tx_fir_drivermode_set;
   3206         lane_control_support = TRUE;
   3207         break;
   3208      /* TX LANE SQUELCH */
   3209     case SOC_PHY_CONTROL_TX_LANE_SQUELCH:
   3210         handler = control_handler_tx_squelch;
   3211         lane_control_support = TRUE;
   3212         break;
   3213      /* RX LANE SQUELCH */
   3214     case SOC_PHY_CONTROL_RX_LANE_SQUELCH:
   3215         handler = control_handler_rx_squelch;
   3216         lane_control_support = TRUE;
   3217         break;
   3218     /* RX PEAK FILTER */
   3219     case SOC_PHY_CONTROL_RX_PEAK_FILTER:
   3220         handler = control_handler_rx_peak_filter_set;
   3221         lane_control_support = TRUE;
   3222         break;
   3223     /* RX VGA */
   3224     case SOC_PHY_CONTROL_RX_VGA:
   3225         handler = control_handler_rx_vga_set;
   3226         lane_control_support = TRUE;
   3227         break;
   3228     /* RX VGA RELEASE */
   3229     case SOC_PHY_CONTROL_RX_VGA_RELEASE:
   3230         handler = control_handler_rx_vga_release;
   3231         lane_control_support = TRUE;
   3232         break;
   3233     /* RX TAP */
   3234     case SOC_PHY_CONTROL_RX_TAP1:
   3235         handler = control_handler_rx_tap_set;
   3236         lane_control_support = TRUE;
   3237         break;
   3238     case SOC_PHY_CONTROL_RX_TAP2:
   3239         handler = control_handler_rx_tap_set;
   3240         lane_control_support = TRUE;
   3241         param2 = 1;
   3242         break;
   3243     case SOC_PHY_CONTROL_RX_TAP3:
   3244         handler = control_handler_rx_tap_set;
   3245         lane_control_support = TRUE;
   3246         param2 = 2;
   3247         break;
   3248     case SOC_PHY_CONTROL_RX_TAP4:
   3249         handler = control_handler_rx_tap_set;
   3250         lane_control_support = TRUE;
   3251         param2 = 3;
   3252         break;
   3253     case SOC_PHY_CONTROL_RX_TAP5:
   3254         handler = control_handler_rx_tap_set;
   3255         lane_control_support = TRUE;
   3256         param2 = 4;
   3257         break;
   3258     case SOC_PHY_CONTROL_RX_TAP6:
   3259         handler = control_handler_rx_tap_set;
   3260         lane_control_support = TRUE;
   3261         param2 = 5;
   3262         break;
   3263     case SOC_PHY_CONTROL_RX_TAP1_RELEASE:
   3264         handler = control_handler_rx_tap_release;
   3265         lane_control_support = TRUE;
   3266         break;
   3267     case SOC_PHY_CONTROL_RX_TAP2_RELEASE:
   3268         handler = control_handler_rx_tap_release;
   3269         lane_control_support = TRUE;
   3270         param2 = 1;
   3271         break;
   3272     case SOC_PHY_CONTROL_RX_TAP3_RELEASE:
   3273         handler = control_handler_rx_tap_release;
   3274         lane_control_support = TRUE;
   3275         param2 = 2;
   3276         break;
   3277     case SOC_PHY_CONTROL_RX_TAP4_RELEASE:
   3278         handler = control_handler_rx_tap_release;
   3279         lane_control_support = TRUE;
   3280         param2 = 3;
   3281         break;
   3282     case SOC_PHY_CONTROL_RX_TAP5_RELEASE:
   3283         handler = control_handler_rx_tap_release;
   3284         lane_control_support = TRUE;
   3285         param2 = 4;
   3286         break;
   3287     case SOC_PHY_CONTROL_RX_TAP6_RELEASE:
   3288         handler = control_handler_rx_tap_release;
   3289         lane_control_support = TRUE;
   3290         param2 = 5;
   3291         break;
   3292     case SOC_PHY_CONTROL_RX_ADAPTATION_RESUME:
   3293         handler = control_handler_rx_adaptation_resume;
   3294         lane_control_support = TRUE;
   3295         break;
   3296     /* PHASE INTERPOLATOR */
   3297     case SOC_PHY_CONTROL_PHASE_INTERP:
   3298     case SOC_PHY_CONTROL_TX_PPM_ADJUST:
   3299         handler = control_handler_pi_control_set;
   3300         lane_control_support = TRUE;
   3301         break;
   3302     /* POLARITY */
   3303     case SOC_PHY_CONTROL_RX_POLARITY:
   3304         handler = control_handler_rx_polarity_set;
   3305         lane_control_support = TRUE;
   3306         break;
   3307     case SOC_PHY_CONTROL_TX_POLARITY:
   3308         handler = control_handler_tx_polarity_set;
   3309         lane_control_support = TRUE;
   3310         break;
   3311     /* RESET */
   3312     case SOC_PHY_CONTROL_RX_RESET:
   3313         handler = control_handler_rx_reset_set;
   3314         lane_control_support = TRUE;
   3315         break;
   3316     case SOC_PHY_CONTROL_TX_RESET:
   3317         handler = control_handler_tx_reset_set;
   3318         lane_control_support = TRUE;
   3319         break;
   3320 
   3321     case SOC_PHY_CONTROL_DUMP:
   3322         handler = control_handler_dsc_dump_set;
   3323         lane_control_support = TRUE;
   3324         break;
   3325 
   3326     /* CL72 ENABLE */
   3327     case SOC_PHY_CONTROL_CL72:
   3328         handler = control_handler_cl72_enable_set;
   3329         lane_control_support = TRUE;
   3330         break;
   3331 
   3332     /* SHORT_CHANNEL_MODE ENABLE */
   3333     case SOC_PHY_CONTROL_SHORT_CHANNEL_MODE:
   3334         handler = control_handler_short_chn_mode_enable_set;
   3335         lane_control_support = TRUE;
   3336         break;
   3337 
   3338     /* LANE SWAP */
   3339     case SOC_PHY_CONTROL_LANE_SWAP:
   3340         handler = control_handler_lane_map_set;
   3341         break;
   3342 
   3343     /* TX PATTERN */
   3344         
   3345     case SOC_PHY_CONTROL_TX_PATTERN_LENGTH:
   3346         handler = control_handler_pattern_length_set;
   3347         lane_control_support = TRUE;
   3348         break ;
   3349     case SOC_PHY_CONTROL_TX_PATTERN_GEN_ENABLE:
   3350         handler = control_handler_pattern_enable_set;
   3351         lane_control_support = TRUE;
   3352         break ;
   3353     case SOC_PHY_CONTROL_TX_PATTERN_DATA0:
   3354         handler = control_handler_pattern_config_set;
   3355         lane_control_support = TRUE;
   3356         param2 = 0;
   3357         break;
   3358     case SOC_PHY_CONTROL_TX_PATTERN_DATA1:
   3359         handler = control_handler_pattern_config_set;
   3360         lane_control_support = TRUE;
   3361         param2 = 1;
   3362         break;
   3363     case SOC_PHY_CONTROL_TX_PATTERN_DATA2:
   3364         handler = control_handler_pattern_config_set;
   3365         lane_control_support = TRUE;
   3366         param2 = 2;
   3367         break;
   3368     case SOC_PHY_CONTROL_TX_PATTERN_DATA3:
   3369         handler = control_handler_pattern_config_set;
   3370         lane_control_support = TRUE;
   3371         param2 = 3;
   3372         break;
   3373     case SOC_PHY_CONTROL_TX_PATTERN_DATA4:
   3374         handler = control_handler_pattern_config_set;
   3375         lane_control_support = TRUE;
   3376         param2 = 4;
   3377         break;
   3378     case SOC_PHY_CONTROL_TX_PATTERN_DATA5:
   3379         handler = control_handler_pattern_config_set;
   3380         lane_control_support = TRUE;
   3381         param2 = 5;
   3382         break;
   3383     case SOC_PHY_CONTROL_TX_PATTERN_DATA6:
   3384         handler = control_handler_pattern_config_set;
   3385         lane_control_support = TRUE;
   3386         param2 = 6;
   3387         break;
   3388     case SOC_PHY_CONTROL_TX_PATTERN_DATA7:
   3389         handler = control_handler_pattern_config_set;
   3390         lane_control_support = TRUE;
   3391         param2 = 7;
   3392         break;
   3393     /* PRBS */
   3394     case SOC_PHY_CONTROL_PRBS_POLYNOMIAL:
   3395         handler = control_handler_prbs_poly_set;
   3396         lane_control_support = TRUE;
   3397         break;
   3398     case SOC_PHY_CONTROL_PRBS_TX_INVERT_DATA:
   3399         handler = control_handler_prbs_tx_invert_data_set;
   3400         lane_control_support = TRUE;
   3401         break;
   3402     case SOC_PHY_CONTROL_PRBS_TX_ENABLE:
   3403         handler = control_handler_prbs_tx_enable_set;
   3404         lane_control_support = TRUE;
   3405         break;
   3406     case SOC_PHY_CONTROL_PRBS_RX_INVERT_DATA:
   3407         handler = control_handler_prbs_rx_invert_data_set;
   3408         lane_control_support = TRUE;
   3409         break;
   3410     case SOC_PHY_CONTROL_PRBS_RX_ENABLE:
   3411         handler = control_handler_prbs_rx_enable_set;
   3412         lane_control_support = TRUE;
   3413         break;
   3414     case SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL:
   3415         handler = control_handler_prbs_tx_poly_set;
   3416         lane_control_support = TRUE;
   3417         break;
   3418     case SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA:
   3419         handler = control_handler_prbs_tx_invert_data_set;
   3420         lane_control_support = TRUE;
   3421         break;
   3422     case SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE:
   3423         handler = control_handler_prbs_tx_enable_set;
   3424         lane_control_support = TRUE;
   3425         break; 
   3426     case SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL:
   3427         handler = control_handler_prbs_rx_poly_set;
   3428         lane_control_support = TRUE;
   3429         break;
   3430     case SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA:
   3431         handler = control_handler_prbs_rx_invert_data_set;
   3432         lane_control_support = TRUE;
   3433         break;
   3434     case SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE:
   3435         handler = control_handler_prbs_rx_enable_set;
   3436         lane_control_support = TRUE;
   3437         break; 
   3438 
   3439     /* LOOPBACK */
   3440     case SOC_PHY_CONTROL_LOOPBACK_INTERNAL:
   3441         handler = control_handler_loopback_internal_set;
   3442         lane_control_support = TRUE;
   3443        break;
   3444     case SOC_PHY_CONTROL_LOOPBACK_PMD:
   3445         handler = control_handler_loopback_pmd_set;
   3446         lane_control_support = TRUE;
   3447        break;
   3448 
   3449     case SOC_PHY_CONTROL_LOOPBACK_REMOTE:
   3450         /* handler = control_handler_loopback_remote_pcs_set; */
   3451         handler = control_handler_loopback_remote_set;
   3452         lane_control_support = TRUE;
   3453         break;
   3454     case SOC_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS:
   3455         handler = control_handler_loopback_remote_set;
   3456         lane_control_support = TRUE;
   3457         break;
   3458 
   3459     /* SCRAMBLER */
   3460     case SOC_PHY_CONTROL_SCRAMBLER:
   3461         handler = control_handler_scrambler_set;
   3462         lane_control_support = TRUE;
   3463         param2 = ref_clock;
   3464         break;
   3465     case SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION:
   3466         handler = control_handler_fec_set;
   3467         lane_control_support = TRUE;
   3468         param2 = ref_clock;
   3469         break;
   3470     case SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91:
   3471         handler = control_handler_fec_set;
   3472         lane_control_support = TRUE;
   3473         param2 = ref_clock;
   3474         PHYMOD_FEC_CL108_CLR(value);
   3475         PHYMOD_FEC_CL91_SET(value);
   3476         break;
   3477     case SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108:
   3478         handler = control_handler_fec_set;
   3479         lane_control_support = TRUE;
   3480         param2 = ref_clock;
   3481         PHYMOD_FEC_CL91_CLR(value);
   3482         PHYMOD_FEC_CL108_SET(value);
   3483         break;
   3484     case SOC_PHY_CONTROL_AUTONEG_FEC_OVERRIDE:
   3485         handler = control_handler_fec_override_set;
   3486         lane_control_support = TRUE;
   3487         break;        
   3488     case SOC_PHY_CONTROL_CHANNEL_LOSS_HINT:
   3489         handler = control_handler_channel_loss_hint_set;
   3490         lane_control_support = TRUE;
   3491         break;
   3492 #if defined(TODO_CONTROLS) /*not implemented yet*/
   3493     /* 8B10B */
   3494     case SOC_PHY_CONTROL_8B10B:
   3495         rv = tsce_8b10b_set(pmc, value);
   3496         break;
   3497 
   3498     /* 64B65B */
   3499     case SOC_PHY_CONTROL_64B66B:
   3500         rv = tsce_64b65b_set(pmc, value);
   3501         break;
   3502 #endif /*not implemented yet*/
   3503 
   3504     /* POWER */
   3505     case SOC_PHY_CONTROL_POWER:
   3506         handler = control_handler_power_set;
   3507         lane_control_support = TRUE;
   3508         break;
   3509 
   3510     /* RX_LOW_FREQ_PEAK_FILTER */
   3511     case SOC_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER:
   3512         handler = control_handler_rx_low_freq_filter_set;
   3513         lane_control_support = TRUE;
   3514         break;
   3515     /* RX_HIGH_FREQ_PEAK_FILTER */
   3516     case SOC_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER:
   3517         handler = control_handler_rx_high_freq_filter_set;
   3518         lane_control_support = TRUE;
   3519         break;
   3520 
   3521 #if defined(TODO_CONTROLS) /*not implemented yet*/
   3522     /* TX_PPM_ADJUST */
   3523     case SOC_PHY_CONTROL_TX_PPM_ADJUST:
   3524        handler = ;
   3525        break;
   3526     /* VCO_FREQ */
   3527     case SOC_PHY_CONTROL_VCO_FREQ:
   3528        rv = tsce_vco_freq_set(pmc, value);
   3529        break;
   3530 
   3531     /* PLL_DIVIDER */
   3532     case SOC_PHY_CONTROL_PLL_DIVIDER:
   3533        rv = tsce_pll_divider_set(pmc, value);
   3534        break;
   3535 
   3536     /* OVERSAMPLE_MODE */
   3537     case SOC_PHY_CONTROL_OVERSAMPLE_MODE:
   3538        rv = tsce_oversample_mode_set(pmc, value);
   3539        break;
   3540 
   3541     /* REF_CLK */
   3542     case SOC_PHY_CONTROL_REF_CLK:
   3543        rv = tsce_ref_clk_set(pmc, value);
   3544        break;
   3545     /* DRIVER_SUPPLY */
   3546     case SOC_PHY_CONTROL_DRIVER_SUPPLY:
   3547        rv = tsce_driver_supply_set(pmc, value);
   3548        break;
   3549 #endif /*not implemented yet*/
   3550     /* RX_SEQ_TOGGLE */
   3551     case SOC_PHY_CONTROL_RX_SEQ_TOGGLE:
   3552        handler = control_handler_rx_seq_toggle_set;
   3553        lane_control_support = TRUE;
   3554        break;
   3555 
   3556     case SOC_PHY_CONTROL_FIRMWARE_MODE:
   3557     case SOC_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE:
   3558     case SOC_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE:
   3559     case SOC_PHY_CONTROL_FIRMWARE_DFE_ENABLE:
   3560     case SOC_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE:
   3561     case SOC_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE:
   3562     case SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE:
   3563     case SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE:
   3564         handler = control_handler_firmware_mode_set;
   3565         lane_control_support = TRUE;
   3566         param2 = control;
   3567         break; 
   3568     case SOC_PHY_CONTROL_MEDIUM_TYPE:
   3569         handler = control_handler_medium_type_set;
   3570         lane_control_support = TRUE;
   3571         param2 = ref_clock;
   3572         break;
   3573     case SOC_PHY_CONTROL_INTERFACE:
   3574         /* value=interface type, control=switch param */ 
   3575         handler = control_handler_interface_set;
   3576         param2 = ref_clock;
   3577         lane_control_support = TRUE;
   3578         break;
   3579 
   3580     case SOC_PHY_CONTROL_GPIO_CONFIG:
   3581         handler = control_handler_gpio_config_set;
   3582         lane_control_support = TRUE;
   3583         break;
   3584 
   3585     case SOC_PHY_CONTROL_GPIO_VALUE:
   3586         handler = control_handler_gpio_pin_value_set;
   3587         lane_control_support = TRUE;
   3588         break;
   3589 
   3590     case SOC_PHY_CONTROL_INTR_MASK:
   3591         handler = control_handler_intr_enable_set;
   3592         lane_control_support = TRUE;
   3593         break;
   3594 
   3595     case SOC_PHY_CONTROL_UNRELIABLE_LOS:
   3596         handler = control_handler_unreliable_los_enable_set;
   3597         lane_control_support = TRUE;
   3598         break;
   3599 
   3600     /* LINKDOWN TRANSMIT */
   3601     /* Non-legacy phy no need to do register setting */
   3602     case SOC_PHY_CONTROL_LINKDOWN_TRANSMIT:
   3603         handler = control_handler_linkdown_transmit_set;
   3604 	lane_control_support = TRUE;
   3605 	break;
   3606 
   3607     case SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE:
   3608         handler = control_handler_pm_codec_enable_set;
   3609         lane_control_support = TRUE;
   3610         break;
   3611     case SOC_PHY_CONTROL_EEE:
   3612         handler = control_handler_eee_set;
   3613         lane_control_support = TRUE;
   3614         break;
   3615     case SOC_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE:
   3616         handler = control_handler_pam4_tx_pattern_set;
   3617         lane_control_support = TRUE;
   3618         break;
   3619     case SOC_PHY_CONTROL_PCS_MODE:
   3620         handler = control_handler_pcs_mode_set;
   3621         lane_control_support = TRUE;
   3622         break;
   3623     case SOC_PHY_CONTROL_PARALLEL_DETECTION:
   3624     case SOC_PHY_CONTROL_PARALLEL_DETECTION_10G:
   3625         handler = control_handler_pdet_set;
   3626         lane_control_support = TRUE;
   3627         param2 = control;
   3628         break;
   3629     case SOC_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE:
   3630         handler = control_handler_tx_pam4_precoder_enable_set;
   3631         lane_control_support = TRUE;
   3632         break;
   3633     case SOC_PHY_CONTROL_LP_TX_PRECODER_ENABLE:
   3634         handler = control_handler_lp_tx_precoder_enable_set;
   3635         lane_control_support = TRUE;
   3636         break;
   3637     case SOC_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE:
   3638         handler = control_handler_fec_bypass_indication_set;
   3639         lane_control_support = TRUE;
   3640         break;
   3641     default:
   3642         return SOC_E_UNAVAIL;
   3643         break; 
   3644     }
   3645 
   3646     if(is_lane_control && !lane_control_support){
   3647         return SOC_E_UNAVAIL;
   3648     }
   3649 
   3650     if(handler == NULL){
   3651         return SOC_E_INTERNAL;
   3652     }
   3653 
   3654     for(i = 0 ; i < nof_phys ; i++){
   3655         /* if lane mask is 0, skip it. */
   3656         if( phys[i].access.lane_mask) {    
   3657             SOC_IF_ERROR_RETURN(handler(unit, &phys[i], value, param2));
   3658         }
   3659     }
   3660 
   3661     return SOC_E_NONE;
   3662 }
   3663 
   3664 int soc_portctrl_phy_tx_set(int unit, phymod_phy_access_t *phy_access, phymod_tx_t *phy_tx)
   3665 {
   3666 
   3667     SOC_IF_ERROR_RETURN(phymod_phy_tx_set(phy_access, phy_tx));
   3668 
   3669     return SOC_E_NONE;
   3670 }
   3671 
   3672 int soc_portctrl_phy_tx_get(int unit, phymod_phy_access_t *phy_access, phymod_tx_t *phy_tx)
   3673 {
   3674 
   3675     SOC_IF_ERROR_RETURN(phymod_phy_tx_get(phy_access, phy_tx));
   3676 
   3677     return SOC_E_NONE;
   3678 }
   3679 #undef _ERR_MSG_MODULE_NAME
   3680 #else
   3681 int phymod_port_control_not_empty;
   3682 #endif
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