phyident.c (282167B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phyident.c 8 * Purpose: These routines and structures are related to 9 * figuring out phy identification and correlating 10 * addresses to drivers 11 */ 12 13 #include <sal/types.h> 14 #include <sal/core/boot.h> 15 #include <shared/bsl.h> 16 #include <soc/drv.h> 17 #ifdef BCM_CMICM_SUPPORT 18 #include <soc/cmicm.h> 19 #endif 20 #include <soc/debug.h> 21 #include <soc/error.h> 22 #include <soc/phyreg.h> 23 #include <soc/phy.h> 24 #include <soc/phyctrl.h> 25 #include <soc/phy/phyctrl.h> 26 #include <soc/phy/drv.h> 27 28 #ifdef PHYMOD_SUPPORT 29 #include <soc/phy/phymod_sim.h> 30 #include <phymod/chip/tsce_sim.h> 31 #include <phymod/chip/tscf_sim.h> 32 #include <phymod/chip/qsgmiie_sim.h> 33 #include <phymod/chip/viper_sim.h> 34 #include <phymod/chip/eagle_sim.h> 35 #include <phymod/chip/qtce_sim.h> 36 #include <phymod/chip/tscbh_sim.h> 37 #endif 38 39 #ifdef BCM_ARAD_SUPPORT 40 #include <soc/dpp/port_sw_db.h> 41 #include <soc/dpp/ARAD/NIF/ports_manager.h> 42 #include <soc/dpp/drv.h> 43 #endif 44 45 #ifdef BCM_KATANA2_SUPPORT 46 #include <soc/katana2.h> 47 #endif 48 49 #ifdef BCM_SABER2_SUPPORT 50 #include <soc/saber2.h> 51 #endif 52 53 #ifdef BCM_GREYHOUND_SUPPORT 54 #include <soc/greyhound.h> 55 #endif 56 57 #ifdef BCM_HURRICANE3_SUPPORT 58 #include <soc/wolfhound2.h> 59 #endif 60 61 #include "phydefs.h" /* Must include before other phy related includes */ 62 #include "phyident.h" 63 #include "phyaddr.h" 64 #include "physr.h" 65 66 #define _MAX_PHYS 256 67 68 typedef struct { 69 uint16 int_addr; 70 uint16 ext_addr; 71 } port_phy_addr_t; 72 73 /* Per port phy address map. */ 74 static port_phy_addr_t *port_phy_addr[SOC_MAX_NUM_DEVICES]; 75 76 static soc_phy_table_t *phy_table[_MAX_PHYS]; 77 static int _phys_in_table = -1; 78 #if defined(INCLUDE_PHY_82109) 79 static int _chk_huracan(int unit, soc_port_t port, soc_phy_table_t *my_entry, 80 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 81 #endif 82 static int _chk_phy(int unit, soc_port_t port, soc_phy_table_t *my_entry, 83 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 84 85 static int _chk_null(int unit, soc_port_t port, soc_phy_table_t *my_entry, 86 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 87 88 static int _chk_sfp_phy(int unit, soc_port_t port, soc_phy_table_t *my_entry, 89 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 90 91 #if defined(INCLUDE_PHY_SIMUL) 92 static int _chk_simul(int unit, soc_port_t port, soc_phy_table_t *my_entry, 93 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 94 #endif /* INCLUDE_PHY_SIMUL */ 95 96 #if defined(INCLUDE_PHY_5690) 97 static int _chk_fiber5690(int unit, soc_port_t port, 98 soc_phy_table_t *my_entry, 99 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 100 #endif /* INCLUDE_PHY_5690 */ 101 102 #if defined(INCLUDE_XGXS_QSGMII65) 103 static int _chk_qsgmii53314(int unit, soc_port_t port, 104 soc_phy_table_t *my_entry, 105 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 106 #endif /* INCLUDE_XGXS_QSGMII65 */ 107 108 #if defined(INCLUDE_PHY_54680) 109 static int _chk_qgphy_5332x(int unit, soc_port_t port, 110 soc_phy_table_t *my_entry, 111 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 112 #endif /* INCLUDE_PHY_54680 */ 113 114 #if defined(INCLUDE_PHY_56XXX) 115 static int _chk_fiber56xxx(int unit, soc_port_t port, 116 soc_phy_table_t *my_entry, 117 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 118 #endif /* INCLUDE_PHY_56XXX */ 119 120 #if defined(INCLUDE_PHY_56XXX) 121 static int _chk_fiber56xxx_5601x(int unit, soc_port_t port, 122 soc_phy_table_t *my_entry, 123 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 124 #endif /* INCLUDE_PHY_56XXX */ 125 126 #if defined(INCLUDE_SERDES_COMBO) 127 static int _chk_serdes_combo_5601x(int unit, soc_port_t port, 128 soc_phy_table_t *my_entry, 129 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 130 #endif /* INCLUDE_SERDES_COMBO */ 131 132 #if defined(INCLUDE_SERDES_65LP) 133 static int _chk_serdes_65lp(int unit, soc_port_t port, 134 soc_phy_table_t *my_entry, 135 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 136 #endif /* INCLUDE_SERDES_65LP */ 137 138 #if defined(INCLUDE_PHY_XGXS6) 139 static int _chk_unicore(int unit, soc_port_t port, 140 soc_phy_table_t *my_entry, 141 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 142 #endif /* INCLUDE_PHY_XGXS6 */ 143 144 #if defined(INCLUDE_PHY_8706) 145 static int _chk_8706(int unit, soc_port_t port, soc_phy_table_t *my_entry, 146 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 147 #endif /* INCLUDE_PHY_8706 */ 148 149 #if defined(INCLUDE_PHY_8072) 150 static int _chk_8072(int unit, soc_port_t port, soc_phy_table_t *my_entry, 151 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 152 #endif /* INCLUDE_PHY_8072 */ 153 154 #if defined(INCLUDE_PHY_8040) 155 static int _chk_8040(int unit, soc_port_t port, soc_phy_table_t *my_entry, 156 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 157 #endif /* INCLUDE_PHY_8040 */ 158 159 #if defined(INCLUDE_PHY_8481) 160 static int _chk_8481(int unit, soc_port_t port, soc_phy_table_t *my_entry, 161 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 162 #endif /* INCLUDE_PHY_8481 */ 163 164 #if defined(INCLUDE_SERDES_COMBO65) 165 static int 166 _chk_serdescombo65(int unit, soc_port_t port, soc_phy_table_t *my_entry, 167 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 168 169 #endif /* INCLUDE_SERDES_COMBO65 */ 170 171 #if defined(INCLUDE_XGXS_16G) 172 static int 173 _chk_xgxs16g1l(int unit, soc_port_t port, soc_phy_table_t *my_entry, 174 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 175 #endif /* INCLUDE_XGXS_16G */ 176 #if defined(INCLUDE_XGXS_VIPER) 177 static int 178 _chk_viper(int unit, soc_port_t port, soc_phy_table_t *my_entry, 179 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 180 #endif 181 182 #if defined(INCLUDE_XGXS_WCMOD) 183 static int 184 _chk_wcmod(int unit, soc_port_t port, soc_phy_table_t *my_entry, 185 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 186 #endif /* INCLUDE_XGXS_WCMOD */ 187 188 #if defined(INCLUDE_PHY_53XXX) 189 static int _chk_fiber53xxx(int unit, soc_port_t port, 190 soc_phy_table_t *my_entry, 191 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 192 #endif /* INCLUDE_PHY_53XXX */ 193 194 static int _chk_default(int unit, soc_port_t port, soc_phy_table_t *my_entry, 195 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi); 196 197 static soc_known_phy_t 198 _phy_ident_type_get(uint16 phy_id0, uint16 phy_id1); 199 200 static soc_phy_table_t _null_phy_entry = 201 {_chk_null, _phy_id_NULL, "Null", &phy_null, NULL}; 202 203 #if defined(INCLUDE_PHY_SIMUL) 204 static soc_phy_table_t _simul_phy_entry = 205 {_chk_simul, _phy_id_SIMUL, "Simulation", &phy_simul, NULL}; 206 #endif /* INCLUDE_PHY_SIMUL */ 207 208 #if defined(INCLUDE_PHY_5690) 209 static soc_phy_table_t _fiber5690_phy_entry = 210 {_chk_fiber5690, _phy_id_NULL, "Internal SERDES", &phy_5690drv_ge, NULL }; 211 #endif /* INCLUDE_PHY_5690 */ 212 213 #if defined(INCLUDE_PHY_56XXX) 214 static soc_phy_table_t _fiber56xxx_phy_entry = 215 {_chk_fiber56xxx, _phy_id_NULL, "Internal SERDES", &phy_56xxxdrv_ge, NULL }; 216 #endif /* INCLUDE_PHY_56XXX */ 217 218 #if defined(INCLUDE_PHY_53XXX) 219 static soc_phy_table_t _fiber53xxx_phy_entry = 220 {_chk_fiber53xxx, _phy_id_NULL, "Internal SERDES", &phy_53xxxdrv_ge, NULL}; 221 #endif /* INCLUDE_PHY_53XXX */ 222 223 static soc_phy_table_t _default_phy_entry = 224 {_chk_default, _phy_id_NULL, "Unknown", &phy_drv_fe, NULL}; 225 226 227 /* 228 * Variable: 229 * _standard_phy_table 230 * Purpose: 231 * Defines the standard supported Broadcom PHYs, and the corresponding 232 * driver. 233 */ 234 235 static soc_phy_table_t _standard_phy_table[] = { 236 237 #ifdef INCLUDE_PHY_522X 238 {_chk_phy, _phy_id_BCM5218, "BCM5218", &phy_522xdrv_fe, NULL}, 239 {_chk_phy, _phy_id_BCM5220, "BCM5220/21", &phy_522xdrv_fe, NULL}, 240 {_chk_phy, _phy_id_BCM5226, "BCM5226", &phy_522xdrv_fe, NULL}, 241 {_chk_phy, _phy_id_BCM5228, "BCM5228", &phy_522xdrv_fe, NULL}, 242 {_chk_phy, _phy_id_BCM5238, "BCM5238", &phy_522xdrv_fe, NULL}, 243 {_chk_phy, _phy_id_BCM5248, "BCM5248", &phy_522xdrv_fe, NULL}, 244 #endif /* INCLUDE_PHY_522X */ 245 246 {_chk_phy, _phy_id_BCM5400, "BCM5400", &phy_drv_ge, NULL}, 247 248 #ifdef INCLUDE_PHY_54XX 249 {_chk_phy, _phy_id_BCM5401, "BCM5401", &phy_5401drv_ge, NULL}, 250 {_chk_phy, _phy_id_BCM5402, "BCM5402", &phy_5402drv_ge, NULL}, 251 {_chk_phy, _phy_id_BCM5404, "BCM5404", &phy_5404drv_ge, NULL}, 252 {_chk_phy, _phy_id_BCM5424, "BCM5424/34", &phy_5424drv_ge, NULL}, 253 {_chk_phy, _phy_id_BCM5411, "BCM5411", &phy_5411drv_ge, NULL}, 254 #endif /* INCLUDE_PHY_54XX */ 255 256 257 #if defined(INCLUDE_PHY_5464_ESW) 258 {_chk_phy, _phy_id_BCM5461, "BCM5461", &phy_5464drv_ge, NULL}, 259 {_chk_phy, _phy_id_BCM5464, "BCM5464", &phy_5464drv_ge, NULL}, 260 {_chk_phy, _phy_id_BCM5466, "BCM5466", &phy_5464drv_ge, NULL}, 261 {_chk_phy, _phy_id_BCM5478, "BCM5478", &phy_5464drv_ge, NULL}, 262 {_chk_phy, _phy_id_BCM5488, "BCM5488", &phy_5464drv_ge, NULL}, 263 {_chk_phy, _phy_id_BCM54980, "BCM54980", &phy_5464drv_ge, NULL}, 264 {_chk_phy, _phy_id_BCM54980C, "BCM54980", &phy_5464drv_ge, NULL}, 265 {_chk_phy, _phy_id_BCM54980V, "BCM54980", &phy_5464drv_ge, NULL}, 266 {_chk_phy, _phy_id_BCM54980VC, "BCM54980", &phy_5464drv_ge, NULL}, 267 {_chk_phy, _phy_id_BCM53314, "BCM53314", &phy_5464drv_ge, NULL}, 268 #endif /* INCLUDE_PHY_5464 */ 269 270 271 #if defined(INCLUDE_PHY_5482_ESW) 272 {_chk_phy, _phy_id_BCM5482, "BCM5482/801x", &phy_5482drv_ge, NULL}, 273 #endif /* INCLUDE_PHY_5482 */ 274 275 #if defined(INCLUDE_PHY_54684) 276 {_chk_phy, _phy_id_BCM54684, "BCM54684", &phy_54684drv_ge, NULL}, 277 #endif /* defined(INCLUDE_PHY_54684) */ 278 279 #if defined(INCLUDE_PHY_54640) 280 {_chk_phy, _phy_id_BCM54640, "BCM54640", &phy_54640drv_ge, NULL}, 281 #endif /* defined(INCLUDE_PHY_54640) */ 282 283 #if defined(INCLUDE_PHY_54682) 284 {_chk_phy, _phy_id_BCM54682, "BCM54682E", &phy_54682drv_ge, NULL}, 285 {_chk_phy, _phy_id_BCM54684E, "BCM54684E", &phy_54682drv_ge, NULL}, 286 {_chk_phy, _phy_id_BCM54685, "BCM54685", &phy_54682drv_ge, NULL}, 287 #endif /* defined(INCLUDE_PHY_54682) */ 288 289 #ifdef INCLUDE_PHY_54616 290 {_chk_phy, _phy_id_BCM54616 , "BCM54616" , &phy_54616drv_ge, NULL}, 291 {_chk_phy, _phy_id_BCM54618E , "BCM54618E" , &phy_54616drv_ge, NULL}, 292 {_chk_phy, _phy_id_BCM54618SE, "BCM54618SE", &phy_54616drv_ge, NULL}, 293 #endif /* INCLUDE_PHY_54616 */ 294 295 #ifdef INCLUDE_PHY_84728 296 {_chk_phy, _phy_id_BCM84707, "BCM84707", &phy_84728drv_xe, NULL}, 297 {_chk_phy, _phy_id_BCM84073, "BCM84073", &phy_84728drv_xe, NULL}, 298 {_chk_phy, _phy_id_BCM84074, "BCM84074", &phy_84728drv_xe, NULL}, 299 {_chk_phy, _phy_id_BCM84728, "BCM84728", &phy_84728drv_xe, NULL}, 300 {_chk_phy, _phy_id_BCM84748, "BCM84748", &phy_84728drv_xe, NULL}, 301 {_chk_phy, _phy_id_BCM84727, "BCM84727", &phy_84728drv_xe, NULL}, 302 {_chk_phy, _phy_id_BCM84747, "BCM84747", &phy_84728drv_xe, NULL}, 303 {_chk_phy, _phy_id_BCM84762, "BCM84762", &phy_84728drv_xe, NULL}, 304 {_chk_phy, _phy_id_BCM84764, "BCM84764", &phy_84728drv_xe, NULL}, 305 {_chk_phy, _phy_id_BCM84042, "BCM84042", &phy_84728drv_xe, NULL}, 306 {_chk_phy, _phy_id_BCM84044, "BCM84044", &phy_84728drv_xe, NULL}, 307 #endif /* INCLUDE_PHY_84728 */ 308 309 #ifdef INCLUDE_PHY_8806X 310 {_chk_phy, _phy_id_BCM8806x, "BCM8806X", &phy_8806xdrv, NULL}, 311 #endif /* INCLUDE_PHY_8806X */ 312 313 #ifdef INCLUDE_MACSEC 314 #if defined(INCLUDE_PHY_54580) 315 {_chk_phy, _phy_id_BCM54584, "BCM54584", &phy_54580drv_ge, NULL}, 316 {_chk_phy, _phy_id_BCM54580, "BCM54580", &phy_54580drv_ge, NULL}, 317 {_chk_phy, _phy_id_BCM54540, "BCM54540", &phy_54580drv_ge, NULL}, 318 {_chk_phy, _phy_id_BCM54585, "BCM54584", &phy_54580drv_ge, NULL}, 319 #endif /* defined(INCLUDE_PHY_54580) */ 320 #if defined(INCLUDE_PHY_54380) 321 {_chk_phy, _phy_id_BCM54380, "BCM54380", &phy_54380drv_ge, NULL}, 322 {_chk_phy, _phy_id_BCM54382, "BCM54382", &phy_54380drv_ge, NULL}, 323 {_chk_phy, _phy_id_BCM54340, "BCM54340", &phy_54380drv_ge, NULL}, 324 {_chk_phy, _phy_id_BCM54385, "BCM54385", &phy_54380drv_ge, NULL}, 325 #endif /* defined(INCLUDE_PHY_54380) */ 326 #ifdef INCLUDE_PHY_8729 327 {_chk_phy, _phy_id_BCM8729, "BCM8729", &phy_8729drv_gexe, NULL}, 328 #endif /* INCLUDE_PHY_8729 */ 329 #ifdef INCLUDE_PHY_84756 330 {_chk_phy, _phy_id_BCM84756, "BCM84756", &phy_84756drv_xe, NULL}, 331 {_chk_phy, _phy_id_BCM84757, "BCM84757", &phy_84756drv_xe, NULL}, 332 {_chk_phy, _phy_id_BCM84759, "BCM84759", &phy_84756drv_xe, NULL}, 333 #endif /* INCLUDE_PHY_84756 */ 334 #ifdef INCLUDE_PHY_84334 335 {_chk_phy, _phy_id_BCM84334, "BCM84334", &phy_84334drv_xe, NULL}, 336 {_chk_phy, _phy_id_BCM84333, "BCM84333", &phy_84334drv_xe, NULL}, 337 {_chk_phy, _phy_id_BCM84336, "BCM84336", &phy_84334drv_xe, NULL}, 338 {_chk_phy, _phy_id_BCM84844, "BCM84844", &phy_84334drv_xe, NULL}, 339 {_chk_phy, _phy_id_BCM84846, "BCM84846", &phy_84334drv_xe, NULL}, 340 {_chk_phy, _phy_id_BCM84848, "BCM84848", &phy_84334drv_xe, NULL}, 341 #endif /* INCLUDE_PHY_84334 */ 342 #ifdef INCLUDE_PHY_84749 343 {_chk_phy, _phy_id_BCM84749, "BCM84749", &phy_84749drv_xe, NULL}, 344 {_chk_phy, _phy_id_BCM84729, "BCM84729", &phy_84749drv_xe, NULL}, 345 #endif /* INCLUDE_PHY_84749 */ 346 #endif /* INCLUDE_MACSEC */ 347 #if defined(INCLUDE_PHY_542XX) 348 {_chk_phy, _phy_id_BCM54182, "BCM54182", &phy_542xxdrv_ge, NULL}, 349 {_chk_phy, _phy_id_BCM54185, "BCM54185", &phy_542xxdrv_ge, NULL}, 350 {_chk_phy, _phy_id_BCM54180, "BCM54180", &phy_542xxdrv_ge, NULL}, 351 {_chk_phy, _phy_id_BCM54140, "BCM54140", &phy_542xxdrv_ge, NULL}, 352 {_chk_phy, _phy_id_BCM54192, "BCM54192", &phy_542xxdrv_ge, NULL}, 353 {_chk_phy, _phy_id_BCM54195, "BCM54195", &phy_542xxdrv_ge, NULL}, 354 {_chk_phy, _phy_id_BCM54190, "BCM54190", &phy_542xxdrv_ge, NULL}, 355 {_chk_phy, _phy_id_BCM54194, "BCM54194", &phy_542xxdrv_ge, NULL}, 356 {_chk_phy, _phy_id_BCM54210, "BCM54210", &phy_542xxdrv_ge, NULL}, 357 {_chk_phy, _phy_id_BCM54220, "BCM54220", &phy_542xxdrv_ge, NULL}, 358 {_chk_phy, _phy_id_BCM54280, "BCM54280", &phy_542xxdrv_ge, NULL}, 359 {_chk_phy, _phy_id_BCM54282, "BCM54282", &phy_542xxdrv_ge, NULL}, 360 {_chk_phy, _phy_id_BCM54240, "BCM54240", &phy_542xxdrv_ge, NULL}, 361 {_chk_phy, _phy_id_BCM54285, "BCM54285", &phy_542xxdrv_ge, NULL}, 362 {_chk_phy, _phy_id_BCM5428x, "BCM5428X", &phy_542xxdrv_ge, NULL}, 363 {_chk_phy, _phy_id_BCM54290, "BCM54290", &phy_542xxdrv_ge, NULL}, 364 {_chk_phy, _phy_id_BCM54292, "BCM54292", &phy_542xxdrv_ge, NULL}, 365 {_chk_phy, _phy_id_BCM54294, "BCM54294", &phy_542xxdrv_ge, NULL}, 366 {_chk_phy, _phy_id_BCM54295, "BCM54295", &phy_542xxdrv_ge, NULL}, 367 {_chk_phy, _phy_id_BCM54296, "BCM54296", &phy_542xxdrv_ge, NULL}, 368 #endif /* defined(INCLUDE_PHY_542XX) */ 369 #ifdef INCLUDE_PHY_84756 370 #if defined(INCLUDE_FCMAP) || defined(INCLUDE_MACSEC) 371 {_chk_phy, _phy_id_BCM84756, "BCM84756", &phy_84756drv_fcmap_xe, NULL}, 372 {_chk_phy, _phy_id_BCM84757, "BCM84757", &phy_84756drv_fcmap_xe, NULL}, 373 {_chk_phy, _phy_id_BCM84759, "BCM84759", &phy_84756drv_fcmap_xe, NULL}, 374 #endif /* INCLUDE_FCMAP || INCLUDE_MACSEC */ 375 #endif /* INCLUDE_PHY_84756 */ 376 377 #ifdef INCLUDE_PHY_5421S 378 {_chk_phy, _phy_id_BCM5421, "BCM5421S", &phy_5421Sdrv_ge, NULL}, 379 #endif /* INCLUDE_PHY_5421S */ 380 381 #ifdef INCLUDE_PHY_54680 382 {_chk_phy, _phy_id_BCM54680, "BCM54680", &phy_54680drv_ge, NULL}, 383 {_chk_qgphy_5332x, _phy_id_BCM53324, "BCM53324", &phy_54680drv_ge, NULL}, 384 #endif /* INCLUDE_PHY_54680 */ 385 386 #ifdef INCLUDE_PHY_EGPHY28 387 {_chk_phy, _phy_id_BCM56160_GPHY, "BCM56160-GPHY", &phy_egphy28drv_ge, NULL}, 388 {_chk_phy, _phy_id_BCM53540, "BCM53540-GPHY", &phy_egphy28drv_ge, NULL}, 389 #endif /* INCLUDE_PHY_EGPHY28 */ 390 391 #ifdef INCLUDE_PHY_54880 392 {_chk_phy, _phy_id_BCM54880, "BCM54880", &phy_54880drv_ge, NULL}, 393 {_chk_phy, _phy_id_BCM54881, "BCM54881", &phy_54880drv_ge, NULL}, 394 {_chk_phy, _phy_id_BCM54810, "BCM54810", &phy_54880drv_ge, NULL}, 395 {_chk_phy, _phy_id_BCM54811, "BCM54811", &phy_54880drv_ge, NULL}, 396 #endif /* INCLUDE_PHY_54880 */ 397 398 #ifdef INCLUDE_PHY_54640E 399 {_chk_phy, _phy_id_BCM54680E, "BCM54640E", &phy_54640drv_ge, NULL}, 400 #endif /* INCLUDE_PHY_54640E */ 401 402 #ifdef INCLUDE_PHY_54880E 403 {_chk_phy, _phy_id_BCM54880E, "BCM54880E", &phy_54680drv_ge, NULL}, 404 #endif /* INCLUDE_PHY_54880E */ 405 406 #ifdef INCLUDE_PHY_54680E 407 {_chk_phy, _phy_id_BCM54680E, "BCM54680E", &phy_54680drv_ge, NULL}, 408 #endif /* INCLUDE_PHY_54680E */ 409 410 #ifdef INCLUDE_PHY_52681E 411 {_chk_phy, _phy_id_BCM52681E, "BCM52681E", &phy_54680drv_ge, NULL}, 412 #endif /* INCLUDE_PHY_52681E */ 413 414 #ifdef INCLUDE_PHY_8703 415 {_chk_phy, _phy_id_BCM8703, "BCM8703", &phy_8703drv_xe, NULL}, 416 {_chk_phy, _phy_id_BCM8704, "BCM8704", &phy_8703drv_xe, NULL}, 417 #endif /* INCLUDE_PHY_8703 */ 418 #ifdef INCLUDE_PHY_8705 419 {_chk_phy, _phy_id_BCM8705, "BCM8705/24/25", &phy_8705drv_xe, NULL}, 420 #endif /* INCLUDE_PHY_8705 */ 421 #if defined(INCLUDE_PHY_8706) 422 /* BCM8706_A0 and BCM8705 has the same device ID. Therefore, the probe must 423 * check for 8706 before 8705 to correctly attach BCM8706. For 8706, 424 * phy_8706 config must be set. 425 */ 426 {_chk_8706, _phy_id_BCM8706, "BCM8706/8726", &phy_8706drv_xe, NULL}, 427 {_chk_8706, _phy_id_BCM8727, "BCM8727", &phy_8706drv_xe, NULL}, 428 {_chk_8706, _phy_id_BCM8747, "BCM8728/8747", &phy_8706drv_xe, NULL}, 429 #endif /* INCLUDE_PHY_8706 */ 430 #if defined(INCLUDE_PHY_8072) 431 {_chk_8072, _phy_id_BCM8072, "BCM8072", &phy_8072drv_xe, NULL}, 432 {_chk_8072, _phy_id_BCM8073, "BCM8073", &phy_8072drv_xe, NULL}, 433 {_chk_8072, _phy_id_BCM8074, "BCM8074", &phy_8074drv_xe, NULL}, 434 #endif /* INCLUDE_PHY_8072 */ 435 436 #if defined(INCLUDE_PHY_8040) 437 {_chk_8040, _phy_id_BCM8040, "BCM8040", &phy_8040drv_xe, NULL}, 438 #endif /* INCLUDE_PHY_8040 */ 439 440 #if defined(INCLUDE_PHY_8481) 441 {_chk_8481, _phy_id_BCM8481x, "BCM8481X", &phy_8481drv_xe, NULL}, 442 {_chk_8481, _phy_id_BCM84812ce, "BCM84812", &phy_8481drv_xe, NULL}, 443 {_chk_8481, _phy_id_BCM84821, "BCM84821", &phy_8481drv_xe, NULL}, 444 {_chk_8481, _phy_id_BCM84822, "BCM84822", &phy_8481drv_xe, NULL}, 445 {_chk_8481, _phy_id_BCM84823, "BCM84823", &phy_8481drv_xe, NULL}, 446 {_chk_8481, _phy_id_BCM84833, "BCM84833", &phy_8481drv_xe, NULL}, 447 {_chk_8481, _phy_id_BCM84834, "BCM84834", &phy_8481drv_xe, NULL}, 448 {_chk_8481, _phy_id_BCM84835, "BCM84835", &phy_8481drv_xe, NULL}, 449 {_chk_8481, _phy_id_BCM84836, "BCM84836", &phy_8481drv_xe, NULL}, 450 {_chk_8481, _phy_id_BCM84844, "BCM84844", &phy_8481drv_xe, NULL}, 451 {_chk_8481, _phy_id_BCM84846, "BCM84846", &phy_8481drv_xe, NULL}, 452 {_chk_8481, _phy_id_BCM84848, "BCM84848", &phy_8481drv_xe, NULL}, 453 {_chk_8481, _phy_id_BCM84858, "BCM84858", &phy_8481drv_xe, NULL}, 454 {_chk_8481, _phy_id_BCM84856, "BCM84856", &phy_8481drv_xe, NULL}, 455 {_chk_8481, _phy_id_BCM84860, "BCM84860", &phy_8481drv_xe, NULL}, 456 {_chk_8481, _phy_id_BCM84861, "BCM84861", &phy_8481drv_xe, NULL}, 457 {_chk_8481, _phy_id_BCM84864, "BCM84864", &phy_8481drv_xe, NULL}, 458 {_chk_8481, _phy_id_BCM84868, "BCM84868", &phy_8481drv_xe, NULL}, 459 {_chk_8481, _phy_id_BCM84888, "BCM84888", &phy_8481drv_xe, NULL}, 460 {_chk_8481, _phy_id_BCM84884, "BCM84884", &phy_8481drv_xe, NULL}, 461 {_chk_8481, _phy_id_BCM84888E, "BCM84888E", &phy_8481drv_xe, NULL}, 462 {_chk_8481, _phy_id_BCM84884E, "BCM84884E", &phy_8481drv_xe, NULL}, 463 {_chk_8481, _phy_id_BCM84881, "BCM84881", &phy_8481drv_xe, NULL}, 464 {_chk_8481, _phy_id_BCM84880, "BCM84880", &phy_8481drv_xe, NULL}, 465 {_chk_8481, _phy_id_BCM84888S, "BCM84888S", &phy_8481drv_xe, NULL}, 466 {_chk_8481, _phy_id_BCM84887, "BCM84887", &phy_8481drv_xe, NULL}, 467 {_chk_8481, _phy_id_BCM84886, "BCM84886", &phy_8481drv_xe, NULL}, 468 {_chk_8481, _phy_id_BCM84885, "BCM84885", &phy_8481drv_xe, NULL}, 469 #endif /* INCLUDE_PHY_8481 */ 470 #ifdef INCLUDE_PHY_8750 471 {_chk_phy, _phy_id_BCM8750, "BCM8750", &phy_8750drv_xe, NULL}, 472 {_chk_phy, _phy_id_BCM8752, "BCM8752", &phy_8750drv_xe, NULL}, 473 {_chk_phy, _phy_id_BCM8754, "BCM8754", &phy_8750drv_xe, NULL}, 474 #endif /* INCLUDE_PHY_8750 */ 475 #ifdef INCLUDE_PHY_84740 476 {_chk_phy, _phy_id_BCM84740, "BCM84740", &phy_84740drv_xe, NULL}, 477 {_chk_phy, _phy_id_BCM84164, "BCM84164", &phy_84740drv_xe, NULL}, 478 {_chk_phy, _phy_id_BCM84758, "BCM84758", &phy_84740drv_xe, NULL}, 479 {_chk_phy, _phy_id_BCM84780, "BCM84780", &phy_84740drv_xe, NULL}, 480 {_chk_phy, _phy_id_BCM84784, "BCM84784", &phy_84740drv_xe, NULL}, 481 {_chk_phy, _phy_id_BCM84318, "BCM84318", &phy_84740drv_xe, NULL}, 482 #endif /* INCLUDE_PHY_84740 */ 483 #ifdef INCLUDE_PHY_84328 484 {_chk_phy, _phy_id_BCM84328, "BCM84328", &phy_84328drv_xe, NULL}, 485 #endif /* INCLUDE_PHY_84328 */ 486 #ifdef INCLUDE_PHY_84793 487 {_chk_phy, _phy_id_BCM84793, "BCM84793", &phy_84793drv_ce, NULL}, 488 #endif 489 #ifdef INCLUDE_PHY_82328 490 {_chk_phy, _phy_id_BCM82328, "BCM82328", &phy_82328drv_xe, NULL}, 491 #endif 492 #if defined(INCLUDE_PHY_82381) 493 {_chk_phy, _phy_id_BCM82381, "Furia", &phy82381_drv, NULL}, 494 #endif 495 #if defined(INCLUDE_PHY_82109) 496 {_chk_huracan, _phy_id_BCM82109, "Huracan", &phy82109_drv, NULL}, 497 #endif 498 #if defined(INCLUDE_PHY_82764) 499 {_chk_phy, _phy_id_BCM82764, "Sesto", &phy82764_drv, NULL}, 500 #endif 501 #if defined(INCLUDE_PHY_82864) 502 {_chk_phy, _phy_id_BCM82864, "Madura", &phy82864_drv, NULL}, 503 #endif 504 505 #ifdef INCLUDE_PHY_82780 506 {_chk_phy, _phy_id_BCM82780, "BCM82780", &phy82780_drv, NULL}, 507 #endif 508 509 {_chk_sfp_phy,0xffff,"copper sfp",&phy_copper_sfp_drv,NULL}, 510 }; 511 512 /* Internal PHY table */ 513 static soc_phy_table_t _int_phy_table[] = { 514 #if defined(INCLUDE_PHY_56XXX) 515 {_chk_fiber56xxx, _phy_id_NULL, "Internal SERDES", 516 &phy_56xxxdrv_ge, NULL}, 517 #endif /* INCLUDE_PHY_56XXX */ 518 519 #if defined(INCLUDE_PHY_53XXX) 520 {_chk_fiber53xxx, _phy_id_NULL, "Internal SERDES", 521 &phy_53xxxdrv_ge, NULL}, 522 #endif /* INCLUDE_PHY_53XXX */ 523 524 #if defined(INCLUDE_SERDES_COMBO) 525 {_chk_phy, _phy_id_SERDESCOMBO, "COMBO", &phy_serdescombo_ge, NULL}, 526 #endif /* INCLUDE_SERDES_COMBO */ 527 528 #if defined(INCLUDE_SERDES_100FX) 529 {_chk_phy, _phy_id_SERDES100FX, "1000X/100FX", &phy_serdes100fx_ge, NULL}, 530 #endif /* INCLUDE_SERDES_100FX */ 531 532 #if defined(INCLUDE_SERDES_65LP) 533 {_chk_serdes_65lp, _phy_id_SERDES65LP, "65LP", &phy_serdes65lp_ge, NULL}, 534 #endif /* INCLUDE_SERDES_65LP */ 535 536 #ifdef INCLUDE_XGXS_QSGMII65 537 {_chk_qsgmii53314, _phy_id_NULL, "QSGMII65", &phy_qsgmii65_ge, 538 NULL }, 539 #endif /* INCLUDE_XGXS_QSGMII65 */ 540 541 #if defined(INCLUDE_SERDES_COMBO65) 542 {_chk_serdescombo65, _phy_id_SERDESCOMBO65, "COMBO65", 543 &phy_serdescombo65_ge, NULL}, 544 #endif /* INCLUDE_SERDES_COMBO65 */ 545 546 #if defined(INCLUDE_PHY_XGXS1) 547 {_chk_phy, _phy_id_BCMXGXS1, "XGXS1", &phy_xgxs1_hg, NULL}, 548 {_chk_phy, _phy_id_BCMXGXS2, "XGXS2", &phy_xgxs1_hg, NULL}, 549 #endif /* INCLUDE_PHY_XGXS1 */ 550 551 #if defined(INCLUDE_PHY_XGXS5) 552 {_chk_phy, _phy_id_BCMXGXS5, "XGXS5", &phy_xgxs5_hg, NULL}, 553 #endif /* INCLUDE_PHY_XGXS5 */ 554 555 #if defined(INCLUDE_PHY_XGXS6) 556 {_chk_phy, _phy_id_BCMXGXS6, "XGXS6", &phy_xgxs6_hg, NULL}, 557 {_chk_unicore, _phy_id_BCMXGXS2, "XGXS6", &phy_xgxs6_hg, NULL}, 558 #endif /* INCLUDE_PHY_XGXS6 */ 559 560 /* Must probe for newer internal SerDes/XAUI first before probing for 561 * older devices. Newer devices reuse the same device ID and introduce 562 * a new mechanism to differentiate betwee devices. Therefore, newer 563 * PHY drivers implement probe funtion to check for correct device. 564 */ 565 #if defined(INCLUDE_XGXS_WC40) 566 {_chk_phy, _phy_id_XGXS_WC40, "WC40/4", &phy_wc40_hg, NULL}, 567 #endif /* INCLUDE_XGXS_HL65 */ 568 569 #if defined(INCLUDE_XGXS_HL65) 570 {_chk_phy, _phy_id_XGXS_HL65, "HL65/4", &phy_hl65_hg, NULL}, 571 #endif /* INCLUDE_XGXS_HL65 */ 572 573 #if defined(INCLUDE_PHY_56XXX) 574 {_chk_fiber56xxx_5601x, _phy_id_NULL, "Internal SERDES", 575 &phy_56xxx_5601x_drv_ge, NULL}, 576 #endif /* INCLUDE_PHY_56XXX */ 577 578 #if defined(INCLUDE_SERDES_COMBO) 579 {_chk_serdes_combo_5601x, _phy_id_NULL, "COMBO SERDES", 580 &phy_serdescombo_5601x_ge, NULL}, 581 #endif /* INCLUDE_SERDES_COMBO */ 582 583 #if defined(INCLUDE_XGXS_16G) 584 {_chk_phy, _phy_id_XGXS_16G, "XGXS16G", &phy_xgxs16g_hg, NULL}, 585 {_chk_xgxs16g1l, _phy_id_XGXS_16G, "XGXS16G/1", &phy_xgxs16g1l_ge, NULL}, 586 #endif /* INCLUDE_XGXS_16G */ 587 588 #if defined(INCLUDE_XGXS_WCMOD) 589 {_chk_wcmod, _phy_id_XGXS_WL, "WCMOD/4", &phy_wcmod_hg, NULL}, 590 #endif /* INCLUDE_XGXS_WL */ 591 592 #if defined(INCLUDE_XGXS_TSCMOD) 593 {_chk_phy, _phy_id_XGXS_TSC, "TSCMOD/4", &phy_tscmod_hg, NULL}, 594 #endif /* INCLUDE_XGXS_TSC */ 595 596 #if defined(INCLUDE_XGXS_TSCE) 597 {_chk_phy, _phy_id_XGXS_TSC, "TSCE", &phy_tsce_drv, NULL}, 598 #endif /* INCLUDE_XGXS_TSCE */ 599 600 #if defined(INCLUDE_XGXS_TSCF) 601 {_chk_phy, _phy_id_XGXS_TSC, "TSCF", &phy_tscf_drv, NULL}, 602 #endif /* INCLUDE_XGXS_TSCF */ 603 604 #if defined(INCLUDE_SERDES_QSGMIIE) 605 {_chk_phy, _phy_id_SERDES65LP, "QSGMIIE", &phy_qsgmiie_drv, NULL}, 606 #endif 607 608 #if defined(INCLUDE_XGXS_VIPER) 609 {_chk_viper, _phy_id_XGXS_VIPER, "VIPER", &phy_viper_drv, NULL}, 610 #endif /* INCLUDE_XGXS_VIPER */ 611 612 #if defined(INCLUDE_SERDES_QTCE) 613 {_chk_phy, _phy_id_XGXS_TSC, "QTCE", &phy_qtce_drv, NULL}, 614 #endif /* INCLUDE_XGXS_TSCF */ 615 {NULL} 616 617 }; 618 #if defined (INCLUDE_PHY_56XXX) || defined (INCLUDE_SERDES_COMBO) 619 /* 620 * Check corrupted registers by writing zeroes 621 * to block address register and making sure zeroes 622 * are read back. 623 */ 624 STATIC INLINE int 625 _is_corrupted_reg(int unit, uint8 phy_addr) 626 { 627 int rv; 628 uint16 data; 629 630 rv = soc_miim_write(unit, phy_addr, 0x1f, 0); 631 if (rv != SOC_E_NONE) { 632 return FALSE; 633 } 634 rv = soc_miim_read(unit, phy_addr, 0x1f, &data); 635 if (rv != SOC_E_NONE) { 636 return FALSE; 637 } 638 639 return (data != 0); 640 } 641 #endif /* (INCLUDE_PHY_56XXX) || (INCLUDE_SERDES_COMBO)*/ 642 643 /* 644 * Function: 645 * _init_phy_table(void) 646 * Purpose: 647 * Initialize the phy table with known phys. 648 * Parameters: 649 * None 650 */ 651 652 static void 653 _init_phy_table(void) 654 { 655 uint32 i; 656 657 for (i = 0; i < COUNTOF(_standard_phy_table) && i < _MAX_PHYS; i++) { 658 phy_table[i] = &_standard_phy_table[i]; 659 } 660 661 _phys_in_table = i; 662 } 663 664 #if defined(BCM_ENDURO_SUPPORT) 665 static void 666 _enduro_phy_addr_default(int unit, int port, 667 uint16 *phy_addr, uint16 *phy_addr_int) 668 { 669 static const uint16 _soc_enduro_int_phy_addr[] = { 670 0x00, /* Port 0 (cmic) N/A */ 671 0x00, /* Port 1 (N/A) */ 672 0x81, /* Port 2 (8SERDES_0) IntBus=0 Addr=0x01 */ 673 0x82, /* Port 3 (8SERDES_0) IntBus=0 Addr=0x02 */ 674 0x83, /* Port 4 (8SERDES_0) IntBus=0 Addr=0x03 */ 675 0x84, /* Port 5 (8SERDES_0) IntBus=0 Addr=0x04 */ 676 0x85, /* Port 6 (8SERDES_0) IntBus=0 Addr=0x05 */ 677 0x86, /* Port 7 (8SERDES_0) IntBus=0 Addr=0x06 */ 678 0x87, /* Port 8 (8SERDES_0) IntBus=0 Addr=0x07 */ 679 0x88, /* Port 9 (8SERDES_0) IntBus=0 Addr=0x08 */ 680 0x89, /* Port 10 (8SERDES_1) IntBus=0 Addr=0x09 */ 681 0x8a, /* Port 11 (8SERDES_1) IntBus=0 Addr=0x0a */ 682 0x8b, /* Port 12 (8SERDES_1) IntBus=0 Addr=0x0b */ 683 0x8c, /* Port 13 (8SERDES_1) IntBus=0 Addr=0x0c */ 684 0x8d, /* Port 14 (8SERDES_1) IntBus=0 Addr=0x0d */ 685 0x8e, /* Port 15 (8SERDES_1) IntBus=0 Addr=0x0e */ 686 0x8f, /* Port 16 (8SERDES_1) IntBus=0 Addr=0x0f */ 687 0x90, /* Port 17 (8SERDES_1) IntBus=0 Addr=0x10 */ 688 0x91, /* Port 18 (9SERDES) IntBus=0 Addr=0x11 */ 689 0x92, /* Port 19 (9SERDES) IntBus=0 Addr=0x12 */ 690 0x93, /* Port 20 (9SERDES) IntBus=0 Addr=0x13 */ 691 0x94, /* Port 21 (9SERDES) IntBus=0 Addr=0x14 */ 692 0x95, /* Port 22 (9SERDES) IntBus=0 Addr=0x15 */ 693 0x96, /* Port 23 (9SERDES) IntBus=0 Addr=0x16 */ 694 0x97, /* Port 24 (9SERDES) IntBus=0 Addr=0x17 */ 695 0x98, /* Port 25 (9SERDES) IntBus=0 Addr=0x18 */ 696 0x99, /* Port 26 (HC0) IntBus=0 Addr=0x19 */ 697 0x9a, /* Port 27 (HC1) IntBus=0 Addr=0x1a */ 698 0x9b, /* Port 28 (HC2) IntBus=0 Addr=0x1b */ 699 0x9c, /* Port 29 (HC3) IntBus=0 Addr=0x1c */ 700 }; 701 702 static const uint16 _soc_phy_addr_bcm56334[] = { 703 0x00, /* Port 0 (cmic) N/A */ 704 0x00, /* Port 1 ( N/A) */ 705 0x01, /* Port 2 ( ge0) ExtBus=0 Addr=0x01 */ 706 0x02, /* Port 3 ( ge1) ExtBus=0 Addr=0x02 */ 707 0x03, /* Port 4 ( ge2) ExtBus=0 Addr=0x03 */ 708 0x04, /* Port 5 ( ge3) ExtBus=0 Addr=0x04 */ 709 0x05, /* Port 6 ( ge4) ExtBus=0 Addr=0x05 */ 710 0x06, /* Port 7 ( ge5) ExtBus=0 Addr=0x06 */ 711 0x07, /* Port 8 ( ge6) ExtBus=0 Addr=0x07 */ 712 0x08, /* Port 9 ( ge7) ExtBus=0 Addr=0x08 */ 713 0x09, /* Port 10 ( ge8) ExtBus=0 Addr=0x09 */ 714 0x0a, /* Port 11 ( ge9) ExtBus=0 Addr=0x0a */ 715 0x0b, /* Port 12 (ge10) ExtBus=0 Addr=0x0b */ 716 0x0c, /* Port 13 (ge11) ExtBus=0 Addr=0x0c */ 717 0x0d, /* Port 14 (ge12) ExtBus=0 Addr=0x0d */ 718 0x0e, /* Port 15 (ge13) ExtBus=0 Addr=0x0e */ 719 0x0f, /* Port 16 (ge14) ExtBus=0 Addr=0x0f */ 720 0x10, /* Port 17 (ge15) ExtBus=0 Addr=0x10 */ 721 0x11, /* Port 18 (ge16) ExtBus=0 Addr=0x11 */ 722 0x12, /* Port 19 (ge17) ExtBus=0 Addr=0x12 */ 723 0x13, /* Port 20 (ge18) ExtBus=0 Addr=0x13 */ 724 0x14, /* Port 21 (ge19) ExtBus=0 Addr=0x14 */ 725 0x15, /* Port 22 (ge20) ExtBus=0 Addr=0x15 */ 726 0x16, /* Port 23 (ge21) ExtBus=0 Addr=0x16 */ 727 0x17, /* Port 24 (ge22) ExtBus=0 Addr=0x17 */ 728 0x18, /* Port 25 (ge23) ExtBus=0 Addr=0x18 */ 729 0x19, /* Port 26 ( hg0) ExtBus=0 Addr=0x19 */ 730 0x1a, /* Port 27 ( hg1) ExtBus=0 Addr=0x1a */ 731 0x1b, /* Port 28 ( hg2) ExtBus=0 Addr=0x1b */ 732 0x1c, /* Port 29 ( hg3) ExtBus=0 Addr=0x1c */ 733 }; 734 735 uint16 dev_id; 736 uint8 rev_id; 737 738 soc_cm_get_id(unit, &dev_id, &rev_id); 739 740 *phy_addr_int = _soc_enduro_int_phy_addr[port]; 741 switch (dev_id) { 742 case BCM56331_DEVICE_ID: 743 case BCM56333_DEVICE_ID: 744 case BCM56334_DEVICE_ID: 745 case BCM56338_DEVICE_ID: 746 case BCM56320_DEVICE_ID: 747 case BCM56321_DEVICE_ID: 748 case BCM56132_DEVICE_ID: 749 case BCM56134_DEVICE_ID: 750 case BCM56230_DEVICE_ID: 751 case BCM56231_DEVICE_ID: 752 *phy_addr = _soc_phy_addr_bcm56334[port]; 753 break; 754 } 755 } 756 #endif /* BCM_ENDURO_SUPPORT */ 757 758 #if defined(BCM_HURRICANE1_SUPPORT) 759 static void 760 _hurricane_phy_addr_default(int unit, int port, 761 uint16 *phy_addr, uint16 *phy_addr_int) 762 { 763 static const uint16 _soc_hurricane_int_phy_addr[] = { 764 0x00, /* Port 0 (cmic) N/A */ 765 0x00, /* Port 1 (N/A) */ 766 0x81, /* Port 2 (8SERDES_0) IntBus=0 Addr=0x01 */ 767 0x81, /* Port 3 (8SERDES_0) IntBus=0 Addr=0x02 */ 768 0x81, /* Port 4 (8SERDES_0) IntBus=0 Addr=0x03 */ 769 0x81, /* Port 5 (8SERDES_0) IntBus=0 Addr=0x04 */ 770 0x81, /* Port 6 (8SERDES_0) IntBus=0 Addr=0x05 */ 771 0x81, /* Port 7 (8SERDES_0) IntBus=0 Addr=0x06 */ 772 0x81, /* Port 8 (8SERDES_0) IntBus=0 Addr=0x07 */ 773 0x81, /* Port 9 (8SERDES_0) IntBus=0 Addr=0x08 */ 774 0x89, /* Port 10 (8SERDES_1) IntBus=0 Addr=0x09 */ 775 0x89, /* Port 11 (8SERDES_1) IntBus=0 Addr=0x0a */ 776 0x89, /* Port 12 (8SERDES_1) IntBus=0 Addr=0x0b */ 777 0x89, /* Port 13 (8SERDES_1) IntBus=0 Addr=0x0c */ 778 0x89, /* Port 14 (8SERDES_1) IntBus=0 Addr=0x0d */ 779 0x89, /* Port 15 (8SERDES_1) IntBus=0 Addr=0x0e */ 780 0x89, /* Port 16 (8SERDES_1) IntBus=0 Addr=0x0f */ 781 0x89, /* Port 17 (8SERDES_1) IntBus=0 Addr=0x10 */ 782 0x91, /* Port 18 (9SERDES) IntBus=0 Addr=0x11 */ 783 0x91, /* Port 19 (9SERDES) IntBus=0 Addr=0x12 */ 784 0x91, /* Port 20 (9SERDES) IntBus=0 Addr=0x13 */ 785 0x91, /* Port 21 (9SERDES) IntBus=0 Addr=0x14 */ 786 0x91, /* Port 22 (9SERDES) IntBus=0 Addr=0x15 */ 787 0x91, /* Port 23 (9SERDES) IntBus=0 Addr=0x16 */ 788 0x91, /* Port 24 (9SERDES) IntBus=0 Addr=0x17 */ 789 0x91, /* Port 25 (9SERDES) IntBus=0 Addr=0x18 */ 790 0x99, /* Port 26 (HC0) IntBus=0 Addr=0x19 */ 791 0x99, /* Port 27 (HC0) IntBus=0 Addr=0x19 */ 792 0x9a, /* Port 28 (HC1) IntBus=0 Addr=0x1a */ 793 0x9a, /* Port 29 (HC1) IntBus=0 Addr=0x1a */ 794 }; 795 796 static const uint16 _soc_phy_addr_bcm56142[] = { 797 0x00, /* Port 0 (cmic) N/A */ 798 0x00, /* Port 1 ( N/A) */ 799 0x01, /* Port 2 ( ge0) ExtBus=0 Addr=0x01 */ 800 0x02, /* Port 3 ( ge1) ExtBus=0 Addr=0x02 */ 801 0x03, /* Port 4 ( ge2) ExtBus=0 Addr=0x03 */ 802 0x04, /* Port 5 ( ge3) ExtBus=0 Addr=0x04 */ 803 0x05, /* Port 6 ( ge4) ExtBus=0 Addr=0x05 */ 804 0x06, /* Port 7 ( ge5) ExtBus=0 Addr=0x06 */ 805 0x07, /* Port 8 ( ge6) ExtBus=0 Addr=0x07 */ 806 0x08, /* Port 9 ( ge7) ExtBus=0 Addr=0x08 */ 807 0x0a, /* Port 10 ( ge8) ExtBus=0 Addr=0x0a */ 808 0x0b, /* Port 11 ( ge9) ExtBus=0 Addr=0x0b */ 809 0x0c, /* Port 12 (ge10) ExtBus=0 Addr=0x0c */ 810 0x0d, /* Port 13 (ge11) ExtBus=0 Addr=0x0d */ 811 0x0e, /* Port 14 (ge12) ExtBus=0 Addr=0x0e */ 812 0x0f, /* Port 15 (ge13) ExtBus=0 Addr=0x0f */ 813 0x10, /* Port 16 (ge14) ExtBus=0 Addr=0x10 */ 814 0x11, /* Port 17 (ge15) ExtBus=0 Addr=0x11 */ 815 0x13, /* Port 18 (ge16) ExtBus=0 Addr=0x13 */ 816 0x14, /* Port 19 (ge17) ExtBus=0 Addr=0x14 */ 817 0x15, /* Port 20 (ge18) ExtBus=0 Addr=0x15 */ 818 0x16, /* Port 21 (ge19) ExtBus=0 Addr=0x16 */ 819 0x17, /* Port 22 (ge20) ExtBus=0 Addr=0x17 */ 820 0x18, /* Port 23 (ge21) ExtBus=0 Addr=0x18 */ 821 0x19, /* Port 24 (ge22) ExtBus=0 Addr=0x19 */ 822 0x1a, /* Port 25 (ge23) ExtBus=0 Addr=0x1a */ 823 0x1c, /* Port 26 ( hg0) ExtBus=0/1 Addr=0x1c */ 824 0, /* Port 27 ( hg1) */ 825 0x1d, /* Port 28 ( hg2) ExtBus=0/1 Addr=0x1d */ 826 0, /* Port 29 ( hg3) */ 827 }; 828 829 uint16 dev_id; 830 uint8 rev_id; 831 832 soc_cm_get_id(unit, &dev_id, &rev_id); 833 834 *phy_addr_int = _soc_hurricane_int_phy_addr[port]; 835 switch (dev_id) { 836 case BCM56140_DEVICE_ID: 837 case BCM56142_DEVICE_ID: 838 case BCM56143_DEVICE_ID: 839 case BCM56144_DEVICE_ID: 840 case BCM56146_DEVICE_ID: 841 case BCM56147_DEVICE_ID: 842 case BCM56149_DEVICE_ID: 843 *phy_addr = _soc_phy_addr_bcm56142[port]; 844 break; 845 } 846 847 } 848 #endif /* BCM_HURRICANE_SUPPORT */ 849 850 #if defined(BCM_HURRICANE2_SUPPORT) 851 static void 852 _hurricane2_phy_addr_default(int unit, int port, 853 uint16 *phy_addr, uint16 *phy_addr_int) 854 { 855 static const uint16 _soc_hurricane2_int_phy_addr[] = { 856 0x00, /* Port 0 (cmic) N/A */ 857 0x00, /* Port 1 (N/A) */ 858 0x81, /* Port 2 (QSGMII2X_0) IntBus=0 Addr=0x01 */ 859 0x81, /* Port 3 (QSGMII2X_0) IntBus=0 Addr=0x02 */ 860 0x81, /* Port 4 (QSGMII2X_0) IntBus=0 Addr=0x03 */ 861 0x81, /* Port 5 (QSGMII2X_0) IntBus=0 Addr=0x04 */ 862 0x81, /* Port 6 (QSGMII2X_0) IntBus=0 Addr=0x05 */ 863 0x81, /* Port 7 (QSGMII2X_0) IntBus=0 Addr=0x06 */ 864 0x81, /* Port 8 (QSGMII2X_0) IntBus=0 Addr=0x07 */ 865 0x81, /* Port 9 (QSGMII2X_0) IntBus=0 Addr=0x08 */ 866 0x89, /* Port 10 (QSGMII2X_1) IntBus=0 Addr=0x09 */ 867 0x89, /* Port 11 (QSGMII2X_1) IntBus=0 Addr=0x0a */ 868 0x89, /* Port 12 (QSGMII2X_1) IntBus=0 Addr=0x0b */ 869 0x89, /* Port 13 (QSGMII2X_1) IntBus=0 Addr=0x0c */ 870 0x89, /* Port 14 (QSGMII2X_1) IntBus=0 Addr=0x0d */ 871 0x89, /* Port 15 (QSGMII2X_1) IntBus=0 Addr=0x0e */ 872 0x89, /* Port 16 (QSGMII2X_1) IntBus=0 Addr=0x0f */ 873 0x89, /* Port 17 (QSGMII2X_1) IntBus=0 Addr=0x10 */ 874 0xb1, /* Port 18 (QSGMII2X_2) IntBus=1 Addr=0x11 */ 875 0xb1, /* Port 19 (QSGMII2X_2) IntBus=1 Addr=0x12 */ 876 0xb1, /* Port 20 (QSGMII2X_2) IntBus=1 Addr=0x13 */ 877 0xb1, /* Port 21 (QSGMII2X_2) IntBus=1 Addr=0x14 */ 878 0xb1, /* Port 22 (QSGMII2X_2) IntBus=1 Addr=0x15 */ 879 0xb1, /* Port 23 (QSGMII2X_2) IntBus=1 Addr=0x16 */ 880 0xb1, /* Port 24 (QSGMII2X_2) IntBus=1 Addr=0x17 */ 881 0xb1, /* Port 25 (QSGMII2X_2) IntBus=1 Addr=0x18 */ 882 0xa1, /* Port 26 (TSC4_0) IntBus=1 Addr=0x01 */ 883 0xa2, /* Port 27 (TSC4_0) IntBus=1 Addr=0x02 */ 884 0xa3, /* Port 28 (TSC4_0) IntBus=1 Addr=0x03 */ 885 0xa4, /* Port 29 (TSC4_0) IntBus=1 Addr=0x04 */ 886 0xa5, /* Port 30 (TSC4_1) IntBus=1 Addr=0x05 */ 887 0xa6, /* Port 31 (TSC4_1) IntBus=1 Addr=0x06 */ 888 0xa7, /* Port 32 (TSC4_1) IntBus=1 Addr=0x09 */ 889 0xa8 /* Port 33 (TSC4_1) IntBus=1 Addr=0x08 */ 890 }; 891 892 static const uint16 _soc_phy_addr_bcm56150[] = { 893 0x00, /* Port 0 (cmic) N/A */ 894 0x00, /* Port 1 ( N/A) */ 895 0x02, /* Port 2 ( ge0) ExtBus=0 Addr=0x02 */ 896 0x03, /* Port 3 ( ge1) ExtBus=0 Addr=0x03 */ 897 0x04, /* Port 4 ( ge2) ExtBus=0 Addr=0x04 */ 898 0x05, /* Port 5 ( ge3) ExtBus=0 Addr=0x05 */ 899 0x06, /* Port 6 ( ge4) ExtBus=0 Addr=0x06 */ 900 0x07, /* Port 7 ( ge5) ExtBus=0 Addr=0x07 */ 901 0x08, /* Port 8 ( ge6) ExtBus=0 Addr=0x08 */ 902 0x09, /* Port 9 ( ge7) ExtBus=0 Addr=0x09 */ 903 0x0b, /* Port 10 ( ge8) ExtBus=0 Addr=0x0b */ 904 0x0c, /* Port 11 ( ge9) ExtBus=0 Addr=0x0c */ 905 0x0d, /* Port 12 (ge10) ExtBus=0 Addr=0x0d */ 906 0x0e, /* Port 13 (ge11) ExtBus=0 Addr=0x0e */ 907 0x0f, /* Port 14 (ge12) ExtBus=0 Addr=0x0f */ 908 0x10, /* Port 15 (ge13) ExtBus=0 Addr=0x10 */ 909 0x11, /* Port 16 (ge14) ExtBus=0 Addr=0x11 */ 910 0x12, /* Port 17 (ge15) ExtBus=0 Addr=0x12 */ 911 0x14, /* Port 18 (ge16) ExtBus=0 Addr=0x14 */ 912 0x15, /* Port 19 (ge17) ExtBus=0 Addr=0x15 */ 913 0x16, /* Port 20 (ge18) ExtBus=0 Addr=0x16 */ 914 0x17, /* Port 21 (ge19) ExtBus=0 Addr=0x17 */ 915 0x18, /* Port 22 (ge20) ExtBus=0 Addr=0x18 */ 916 0x19, /* Port 23 (ge21) ExtBus=0 Addr=0x19 */ 917 0x1a, /* Port 24 (ge22) ExtBus=0 Addr=0x1a */ 918 0x1b, /* Port 25 (ge23) ExtBus=0 Addr=0x1b */ 919 0x21, /* Port 26 ( hg0) ExtBus=1 Addr=0x01 */ 920 0x22, /* Port 27 ( hg1) ExtBus=1 Addr=0x02 */ 921 0x23, /* Port 28 ( hg2) ExtBus=1 Addr=0x03 */ 922 0x24, /* Port 29 ( hg3) ExtBus=1 Addr=0x04 */ 923 0x25, /* Port 30 ( hg4) ExtBus=1 Addr=0x05 */ 924 0x26, /* Port 31 ( hg5) ExtBus=1 Addr=0x06 */ 925 0x27, /* Port 32 ( hg6) ExtBus=1 Addr=0x07 */ 926 0x28 /* Port 33 ( hg7) ExtBus=1 Addr=0x08 */ 927 }; 928 929 static const uint16 _soc_phy_addr_bcm5339x[] = { 930 0x00, /* Port 0 (cmic) N/A */ 931 0x00, /* Port 1 ( N/A) */ 932 0x02, /* Port 2 ( ge0) ExtBus=0 Addr=0x02 */ 933 0x00, /* Port 3 ( N/A) */ 934 0x00, /* Port 4 ( N/A) */ 935 0x00, /* Port 5 ( N/A) */ 936 0x03, /* Port 6 ( ge1) ExtBus=0 Addr=0x03 */ 937 0x00, /* Port 7 ( N/A) */ 938 0x00, /* Port 8 ( N/A) */ 939 0x00, /* Port 9 ( N/A) */ 940 0x04, /* Port 10 ( ge2) ExtBus=0 Addr=0x04 */ 941 0x00, /* Port 11 ( N/A) */ 942 0x00, /* Port 12 ( N/A) */ 943 0x00, /* Port 13 ( N/A) */ 944 0x05, /* Port 14 ( ge3) ExtBus=0 Addr=0x05 */ 945 0x00, /* Port 15 ( N/A) */ 946 0x00, /* Port 16 ( N/A) */ 947 0x00, /* Port 17 ( N/A) */ 948 0x06, /* Port 18 ( ge4) ExtBus=0 Addr=0x06 */ 949 0x00, /* Port 19 ( N/A) */ 950 0x00, /* Port 20 ( N/A) */ 951 0x00, /* Port 21 ( N/A) */ 952 0x07, /* Port 22 ( ge5) ExtBus=0 Addr=0x07 */ 953 0x00, /* Port 23 ( N/A) */ 954 0x00, /* Port 24 ( N/A) */ 955 0x00, /* Port 25 ( N/A) */ 956 0x00, /* Port 26 ( N/A) */ 957 0x00, /* Port 27 ( N/A) */ 958 0x00, /* Port 28 ( N/A) */ 959 0x00, /* Port 29 ( N/A) */ 960 0x00, /* Port 30 ( N/A) */ 961 0x00, /* Port 31 ( N/A) */ 962 0x00, /* Port 32 ( N/A) */ 963 0x00 /* Port 33 ( N/A) */ 964 }; 965 966 static const uint16 _soc_hurricane2_gphy_addr[] = { 967 0x00, /* Port 0 (cmic) N/A */ 968 0x00, /* Port 1 (N/A) */ 969 0x81, /* Port 2 (QGPHY_0) IntBus=0 Addr=0x01 */ 970 0x82, /* Port 3 (QGPHY_0) IntBus=0 Addr=0x02 */ 971 0x83, /* Port 4 (QGPHY_0) IntBus=0 Addr=0x03 */ 972 0x84, /* Port 5 (QGPHY_0) IntBus=0 Addr=0x04 */ 973 0x86, /* Port 6 (QGPHY_1) IntBus=0 Addr=0x06 */ 974 0x87, /* Port 7 (QGPHY_1) IntBus=0 Addr=0x07 */ 975 0x88, /* Port 8 (QGPHY_1) IntBus=0 Addr=0x08 */ 976 0x89, /* Port 9 (QGPHY_1) IntBus=0 Addr=0x09 */ 977 0x8b, /* Port 10 (QGPHY_2) IntBus=0 Addr=0x0b */ 978 0x8c, /* Port 11 (QGPHY_2) IntBus=0 Addr=0x0c */ 979 0x8d, /* Port 12 (QGPHY_2) IntBus=0 Addr=0x0d */ 980 0x8e, /* Port 13 (QGPHY_2) IntBus=0 Addr=0x0e */ 981 0x90, /* Port 14 (QGPHY_3) IntBus=0 Addr=0x10 */ 982 0x91, /* Port 15 (QGPHY_3) IntBus=0 Addr=0x11 */ 983 0x92, /* Port 16 (QGPHY_3) IntBus=0 Addr=0x12 */ 984 0x93 /* Port 17 (QGPHY_3) IntBus=0 Addr=0x13 */ 985 }; 986 987 uint16 dev_id; 988 uint8 rev_id; 989 int phy_port; 990 991 soc_cm_get_id(unit, &dev_id, &rev_id); 992 993 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 994 *phy_addr_int = _soc_hurricane2_int_phy_addr[phy_port]; 995 switch (dev_id) { 996 case BCM56150_DEVICE_ID: 997 case BCM56151_DEVICE_ID: 998 case BCM56152_DEVICE_ID: 999 case BCM53342_DEVICE_ID: 1000 case BCM53343_DEVICE_ID: 1001 case BCM53344_DEVICE_ID: 1002 case BCM53346_DEVICE_ID: 1003 case BCM53347_DEVICE_ID: 1004 case BCM53333_DEVICE_ID: 1005 case BCM53334_DEVICE_ID: 1006 *phy_addr = _soc_phy_addr_bcm56150[phy_port]; 1007 break; 1008 case BCM53393_DEVICE_ID: 1009 case BCM53394_DEVICE_ID: 1010 *phy_addr = _soc_phy_addr_bcm5339x[phy_port]; 1011 break; 1012 } 1013 if ( soc_feature(unit, soc_feature_gphy) && (phy_port < 18)) { 1014 *phy_addr_int = 0; 1015 *phy_addr = _soc_hurricane2_gphy_addr[phy_port]; 1016 } 1017 } 1018 #endif /* BCM_HURRICANE2_SUPPORT */ 1019 1020 #if defined(BCM_GREYHOUND_SUPPORT) 1021 /* GH's SKUs for TSC0Q at QSGMII mode 1022 * - this mode supports 16 GE ports through SGMII. 1023 */ 1024 #define _GH_PPORT_IN_QSGMII_INT_PHY_RANGE(_pport) \ 1025 ((((_pport) >= 2) && (_pport) <= 17) ? TRUE : FALSE) 1026 1027 static void 1028 _greyhound_phy_addr_default(int unit, int port, 1029 uint16 *phy_addr, uint16 *phy_addr_int) { 1030 1031 /* MDIO address mapping for TSC0Q at QSGMII mode 1032 * - in SKUs of 56064/56063/56062/53411/53401/53456/53457/53424 1033 * 1034 * Note : 1035 * 1. GH's QSGMII SerDes in PM4x10Q has no direct MDIO access interface. 1036 * - This MDIO address mapping is for SW usage only. 1037 */ 1038 static const uint16 _soc_gh_int_phyaddr_qsgmii[] = { 1039 0x00, /* Port 0 (cmic) N/A */ 1040 0x00, /* Port 1 (N/A) */ 1041 GH_QSGMII_MDIO_ADDR, /* Port 2 (QSGMII_0) IntBus=0 Addr=0x01 */ 1042 GH_QSGMII_MDIO_ADDR, /* Port 3 (QSGMII_0) Share the same Addr */ 1043 GH_QSGMII_MDIO_ADDR, /* Port 4 (QSGMII_0) Share the same Addr */ 1044 GH_QSGMII_MDIO_ADDR, /* Port 5 (QSGMII_0) Share the same Addr */ 1045 GH_QSGMII_MDIO_ADDR, /* Port 6 (QSGMII_0) Share the same Addr */ 1046 GH_QSGMII_MDIO_ADDR, /* Port 7 (QSGMII_0) Share the same Addr */ 1047 GH_QSGMII_MDIO_ADDR, /* Port 8 (QSGMII_0) Share the same Addr */ 1048 GH_QSGMII_MDIO_ADDR, /* Port 9 (QSGMII_0) Share the same Addr */ 1049 GH_QSGMII_MDIO_ADDR, /* Port 10 (QSGMII_1) Share the same Addr */ 1050 GH_QSGMII_MDIO_ADDR, /* Port 11 (QSGMII_1) Share the same Addr */ 1051 GH_QSGMII_MDIO_ADDR, /* Port 12 (QSGMII_1) Share the same Addr */ 1052 GH_QSGMII_MDIO_ADDR, /* Port 13 (QSGMII_1) Share the same Addr */ 1053 GH_QSGMII_MDIO_ADDR, /* Port 14 (QSGMII_1) Share the same Addr */ 1054 GH_QSGMII_MDIO_ADDR, /* Port 15 (QSGMII_1) Share the same Addr */ 1055 GH_QSGMII_MDIO_ADDR, /* Port 16 (QSGMII_1) Share the same Addr */ 1056 GH_QSGMII_MDIO_ADDR /* Port 17 (QSGMII_1) Share the same Addr */ 1057 }; 1058 1059 /* Greyhound TOP defined MDIO address for TSCs */ 1060 static const uint16 _soc_gh_int_phyaddr[] = { 1061 0x00, /* Port 0 (cmic) N/A */ 1062 0x00, /* Port 1 (N/A) */ 1063 0x81, /* Port 2 (TSC0Q_0) IntBus=0 Addr=0x01 */ 1064 0x81, /* Port 3 (TSC0Q_1) Share the same Addr */ 1065 0x81, /* Port 4 (TSC0Q_2) Share the same Addr */ 1066 0x81, /* Port 5 (TSC0Q_3) Share the same Addr */ 1067 0x00, /* Port 6 (N/A) */ 1068 0x00, /* Port 7 (N/A) */ 1069 0x00, /* Port 8 (N/A) */ 1070 0x00, /* Port 9 (N/A) */ 1071 0x00, /* Port 10 (N/A) */ 1072 0x00, /* Port 11 (N/A) */ 1073 0x00, /* Port 12 (N/A) */ 1074 0x00, /* Port 13 (N/A) */ 1075 0x00, /* Port 14 (N/A) */ 1076 0x00, /* Port 15 (N/A) */ 1077 0x00, /* Port 16 (N/A) */ 1078 0x00, /* Port 17 (N/A) */ 1079 0xa1, /* Port 18 (TSC0_0) IntBus=1 Addr=0x01 */ 1080 0xa1, /* Port 19 (TSC0_1) Share the same Addr */ 1081 0xa1, /* Port 20 (TSC0_2) Share the same Addr */ 1082 0xa1, /* Port 21 (TSC0_3) Share the same Addr */ 1083 0xa5, /* Port 22 (TSC1_0) IntBus=1 Addr=0x05 */ 1084 0xa5, /* Port 23 (TSC1_1) Share the same Addr */ 1085 0xa5, /* Port 24 (TSC1_2) Share the same Addr */ 1086 0xa5, /* Port 25 (TSC1_3) Share the same Addr */ 1087 0xa9, /* Port 26 (TSC2_0) IntBus=1 Addr=0x09 */ 1088 0xa9, /* Port 27 (TSC2_1) Share the same Addr */ 1089 0xa9, /* Port 28 (TSC2_2) Share the same Addr */ 1090 0xa9, /* Port 29 (TSC2_3) Share the same Addr */ 1091 0xad, /* Port 30 (TSC3_0) IntBus=1 Addr=0x0d */ 1092 0xad, /* Port 31 (TSC3_1) Share the same Addr */ 1093 0xad, /* Port 32 (TSC3_2) Share the same Addr */ 1094 0xad, /* Port 33 (TSC3_3) Share the same Addr */ 1095 0xb1, /* Port 34 (TSC4_0) IntBus=1 Addr=0x11 */ 1096 0xb1, /* Port 35 (TSC4_1) Share the same Addr */ 1097 0xb1, /* Port 36 (TSC4_2) Share the same Addr */ 1098 0xb1 /* Port 37 (TSC4_3) Share the same Addr */ 1099 }; 1100 1101 uint16 dev_id; 1102 uint8 rev_id; 1103 int phy_port; 1104 1105 /* assigning default phy_addr for ext-phy */ 1106 *phy_addr = 0xff; 1107 soc_cm_get_id(unit, &dev_id, &rev_id); 1108 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1109 1110 /* assigning defualt internal PHY address */ 1111 switch (dev_id) { 1112 case BCM56062_DEVICE_ID: 1113 case BCM56063_DEVICE_ID: 1114 case BCM56064_DEVICE_ID: 1115 case BCM53411_DEVICE_ID: 1116 case BCM53401_DEVICE_ID: 1117 case BCM53456_DEVICE_ID: 1118 case BCM53457_DEVICE_ID: 1119 case BCM53424_DEVICE_ID: 1120 if (_GH_PPORT_IN_QSGMII_INT_PHY_RANGE(phy_port)) { 1121 *phy_addr_int = _soc_gh_int_phyaddr_qsgmii[phy_port]; 1122 } else { 1123 *phy_addr_int = _soc_gh_int_phyaddr[phy_port]; 1124 } 1125 break; 1126 default : 1127 *phy_addr_int = _soc_gh_int_phyaddr[phy_port]; 1128 break; 1129 } 1130 } 1131 #endif /* BCM_GREYHOUND_SUPPORT */ 1132 1133 #if defined(BCM_HURRICANE3_SUPPORT) 1134 static void 1135 _wolfhound2_phy_addr_default(int unit, int port, 1136 uint16 *phy_addr, uint16 *phy_addr_int) 1137 { 1138 static const uint16 _soc_wh2_phy_addr[] = { 1139 0x00, /* Port 0 (cmic) N/A */ 1140 0x00, /* Port 1 (N/A) */ 1141 0x81, /* Port 2 IntBus=0 Addr=0x1 */ 1142 0x82, /* Port 3 IntBus=0 Addr=0x2 */ 1143 0x83, /* Port 4 IntBus=0 Addr=0x3 */ 1144 0x84, /* Port 5 IntBus=0 Addr=0x4 */ 1145 0x85, /* Port 6 IntBus=0 Addr=0x5 */ 1146 0x86, /* Port 7 IntBus=0 Addr=0x6 */ 1147 0x87, /* Port 8 IntBus=0 Addr=0x7 */ 1148 0x88, /* Port 9 IntBus=0 Addr=0x8 */ 1149 0x89, /* Port 10 IntBus=0 Addr=0x9 */ 1150 0x8a, /* Port 11 IntBus=0 Addr=0xa */ 1151 0x8b, /* Port 12 IntBus=0 Addr=0xb */ 1152 0x8c, /* Port 13 IntBus=0 Addr=0xc */ 1153 0x00, /* Port 14 */ 1154 0x00, /* Port 15 */ 1155 0x00, /* Port 16 */ 1156 0x00, /* Port 17 */ 1157 0x8d, /* Port 18 IntBus=0 Addr=0xd */ 1158 0x8e, /* Port 19 IntBus=0 Addr=0xe */ 1159 0x8f, /* Port 20 IntBus=0 Addr=0xf */ 1160 0x90, /* Port 21 IntBus=0 Addr=0x10 */ 1161 0x91, /* Port 22 IntBus=0 Addr=0x11 */ 1162 0x92, /* Port 23 IntBus=0 Addr=0x12 */ 1163 0x93, /* Port 24 IntBus=0 Addr=0x13 */ 1164 0x94, /* Port 25 IntBus=0 Addr=0x14 */ 1165 0x95, /* Port 26 IntBus=0 Addr=0x15 */ 1166 0x96, /* Port 27 IntBus=0 Addr=0x16 */ 1167 0x97, /* Port 28 IntBus=0 Addr=0x17 */ 1168 0x98, /* Port 29 IntBus=0 Addr=0x18 */ 1169 0x00, /* Port 30 */ 1170 0x00, /* Port 31 */ 1171 0x00, /* Port 32 */ 1172 0x00, /* Port 33 */ 1173 0x00, /* Port 34 */ 1174 0x00, /* Port 35 */ 1175 0x00, /* Port 36 */ 1176 0x00 /* Port 37 */ 1177 }; 1178 1179 static const uint16 _soc_wh2_int_phy_addr[] = { 1180 0x00, /* Port 0 (cmic) N/A */ 1181 0x00, /* Port 1 (N/A) */ 1182 0x00, /* Port 2 */ 1183 0x00, /* Port 3 */ 1184 0x00, /* Port 4 */ 1185 0x00, /* Port 5 */ 1186 0x00, /* Port 6 */ 1187 0x00, /* Port 7 */ 1188 0x00, /* Port 8 */ 1189 0x00, /* Port 9 */ 1190 0x00, /* Port 10 */ 1191 0x00, /* Port 11 */ 1192 0x00, /* Port 12 */ 1193 0x00, /* Port 13 */ 1194 0x00, /* Port 14 */ 1195 0x00, /* Port 15 */ 1196 0x00, /* Port 16 */ 1197 0x00, /* Port 17 */ 1198 0x00, /* Port 18 */ 1199 0x00, /* Port 19 */ 1200 0x00, /* Port 20 */ 1201 0x00, /* Port 21 */ 1202 0x00, /* Port 22 */ 1203 0x00, /* Port 23 */ 1204 0x00, /* Port 24 */ 1205 0x00, /* Port 25 */ 1206 0xb4, /* Port 26 IntBus=1 Addr=0x14 */ 1207 0xb4, /* Port 27 IntBus=1 Addr=0x15 */ 1208 0xb4, /* Port 28 IntBus=1 Addr=0x16 */ 1209 0xb4, /* Port 29 IntBus=1 Addr=0x17 */ 1210 0x00, /* Port 30 */ 1211 0x00, /* Port 31 */ 1212 0x00, /* Port 32 */ 1213 0x00, /* Port 33 */ 1214 0xb0, /* Port 34 IntBus=1 Addr=0x10 */ 1215 0xb0, /* Port 35 IntBus=1 Addr=0x11 */ 1216 0xb0, /* Port 36 IntBus=1 Addr=0x12 */ 1217 0xb0 /* Port 37 IntBus=1 Addr=0x13 */ 1218 }; 1219 int phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1220 uint8 is_gphy; 1221 if (phy_port >= 34) { 1222 /* SGMII_4P1 ports */ 1223 *phy_addr_int = _soc_wh2_int_phy_addr[phy_port]; 1224 *phy_addr = 0xff; 1225 } else { 1226 soc_wolfhound2_gphy_get(unit, port, &is_gphy); 1227 if (!is_gphy) { 1228 *phy_addr_int = _soc_wh2_int_phy_addr[phy_port]; 1229 *phy_addr = 0xff; 1230 } else { 1231 *phy_addr_int = 0; 1232 *phy_addr = _soc_wh2_phy_addr[phy_port]; 1233 } 1234 } 1235 } 1236 1237 #define _HR3_GPHY_CNT (8) 1238 #define _HR3_GPHY_FIRST_PORT_NUM_PGW0 (10) 1239 #define _HR3_GPHY_FIRST_PORT_NUM_PGW1 (26) 1240 static void 1241 _hurricane3_phy_addr_default(int unit, int port, 1242 uint16 *phy_addr, uint16 *phy_addr_int) 1243 { 1244 static const uint16 _soc_hr3_int_phy_addr[] = { 1245 0x00, /* Port 0 (cmic) N/A */ 1246 0x00, /* Port 1 (N/A) */ 1247 0xa9, /* Port 2 (QTC_0) IntBus=1 Addr=0x09 */ 1248 0xa9, /* Port 3 (QTC_0) IntBus=1 Addr=0x09 */ 1249 0xa9, /* Port 4 (QTC_0) IntBus=1 Addr=0x09 */ 1250 0xa9, /* Port 5 (QTC_0) IntBus=1 Addr=0x09 */ 1251 0xa9, /* Port 6 (QTC_0) IntBus=1 Addr=0x09 */ 1252 0xa9, /* Port 7 (QTC_0) IntBus=1 Addr=0x09 */ 1253 0xa9, /* Port 8 (QTC_0) IntBus=1 Addr=0x09 */ 1254 0xa9, /* Port 9 (QTC_0) IntBus=1 Addr=0x09 */ 1255 0xa9, /* Port 10 (QTC_0) IntBus=1 Addr=0x09 */ 1256 0xa9, /* Port 11 (QTC_0) IntBus=1 Addr=0x09 */ 1257 0xa9, /* Port 12 (QTC_0) IntBus=1 Addr=0x09 */ 1258 0xa9, /* Port 13 (QTC_0) IntBus=1 Addr=0x09 */ 1259 0xa9, /* Port 14 (QTC_0) IntBus=1 Addr=0x09 */ 1260 0xa9, /* Port 15 (QTC_0) IntBus=1 Addr=0x09 */ 1261 0xa9, /* Port 16 (QTC_0) IntBus=1 Addr=0x09 */ 1262 0xa9, /* Port 17 (QTC_0) IntBus=1 Addr=0x09 */ 1263 0xad, /* Port 18 (QTC_1) IntBus=1 Addr=0x0d */ 1264 0xad, /* Port 19 (QTC_1) IntBus=1 Addr=0x0d */ 1265 0xad, /* Port 20 (QTC_1) IntBus=1 Addr=0x0d */ 1266 0xad, /* Port 21 (QTC_1) IntBus=1 Addr=0x0d */ 1267 0xad, /* Port 22 (QTC_1) IntBus=1 Addr=0x0d */ 1268 0xad, /* Port 23 (QTC_1) IntBus=1 Addr=0x0d */ 1269 0xad, /* Port 24 (QTC_1) IntBus=1 Addr=0x0d */ 1270 0xad, /* Port 25 (QTC_1) IntBus=1 Addr=0x0d */ 1271 0xad, /* Port 26 (QTC_1) IntBus=1 Addr=0x0d */ 1272 0xad, /* Port 27 (QTC_1) IntBus=1 Addr=0x0d */ 1273 0xad, /* Port 28 (QTC_1) IntBus=1 Addr=0x0d */ 1274 0xad, /* Port 29 (QTC_1) IntBus=1 Addr=0x0d */ 1275 0xad, /* Port 30 (QTC_1) IntBus=1 Addr=0x0d */ 1276 0xad, /* Port 31 (QTC_1) IntBus=1 Addr=0x0d */ 1277 0xad, /* Port 32 (QTC_1) IntBus=1 Addr=0x0d */ 1278 0xad, /* Port 33 (QTC_1) IntBus=1 Addr=0x0d */ 1279 0xa1, /* Port 34 (TSC_0) IntBus=1 Addr=0x01 */ 1280 0xa1, /* Port 35 (TSC_0) IntBus=1 Addr=0x01 */ 1281 0xa1, /* Port 36 (TSC_0) IntBus=1 Addr=0x01 */ 1282 0xa1, /* Port 37 (TSC_0) IntBus=1 Addr=0x01 */ 1283 0xa5, /* Port 38 (TSC_1) IntBus=1 Addr=0x05 */ 1284 0xa5, /* Port 39 (TSC_1) IntBus=1 Addr=0x05 */ 1285 0xa5, /* Port 40 (TSC_1) IntBus=1 Addr=0x05 */ 1286 0xa5 /* Port 41 (TSC_1) IntBus=1 Addr=0x05 */ 1287 }; 1288 1289 static const uint16 _soc_hr3_gphy_addr[] = { 1290 0x00, /* Port 0 (cmic) N/A */ 1291 0x00, /* Port 1 (N/A) */ 1292 0x00, /* Port 2 (N/A) N/A */ 1293 0x00, /* Port 3 (N/A) N/A */ 1294 0x00, /* Port 4 (N/A) N/A */ 1295 0x00, /* Port 5 (N/A) N/A */ 1296 0x00, /* Port 6 (N/A) N/A */ 1297 0x00, /* Port 7 (N/A) N/A */ 1298 0x00, /* Port 8 (N/A) N/A */ 1299 0x00, /* Port 9 (N/A) N/A */ 1300 0x81, /* Port 10 (QGPHY_0) IntBus=0 Addr=0x01 */ 1301 0x82, /* Port 11 (QGPHY_0) IntBus=0 Addr=0x02 */ 1302 0x83, /* Port 12 (QGPHY_0) IntBus=0 Addr=0x03 */ 1303 0x84, /* Port 13 (QGPHY_0) IntBus=0 Addr=0x04 */ 1304 0x85, /* Port 14 (QGPHY_1) IntBus=0 Addr=0x05 */ 1305 0x86, /* Port 15 (QGPHY_1) IntBus=0 Addr=0x06 */ 1306 0x87, /* Port 16 (QGPHY_1) IntBus=0 Addr=0x07 */ 1307 0x88, /* Port 17 (QGPHY_1) IntBus=0 Addr=0x08 */ 1308 0x00, /* Port 18 (N/A) N/A */ 1309 0x00, /* Port 19 (N/A) N/A */ 1310 0x00, /* Port 20 (N/A) N/A */ 1311 0x00, /* Port 21 (N/A) N/A */ 1312 0x00, /* Port 22 (N/A) N/A */ 1313 0x00, /* Port 23 (N/A) N/A */ 1314 0x00, /* Port 24 (N/A) N/A */ 1315 0x00, /* Port 25 (N/A) N/A */ 1316 0x89, /* Port 26 (QGPHY_2) IntBus=0 Addr=0x09 */ 1317 0x8a, /* Port 27 (QGPHY_2) IntBus=0 Addr=0x0a */ 1318 0x8b, /* Port 28 (QGPHY_2) IntBus=0 Addr=0x0b */ 1319 0x8c, /* Port 29 (QGPHY_2) IntBus=0 Addr=0x0c */ 1320 0x8d, /* Port 30 (QGPHY_3) IntBus=0 Addr=0x0d */ 1321 0x8e, /* Port 31 (QGPHY_3) IntBus=0 Addr=0x0e */ 1322 0x8f, /* Port 32 (QGPHY_3) IntBus=0 Addr=0x0f */ 1323 0x90, /* Port 33 (QGPHY_3) IntBus=0 Addr=0x10 */ 1324 0x00, /* Port 34 (N/A) N/A */ 1325 0x00, /* Port 35 (N/A) N/A */ 1326 0x00, /* Port 36 (N/A) N/A */ 1327 0x00, /* Port 37 (N/A) N/A */ 1328 0x00, /* Port 38 (N/A) N/A */ 1329 0x00, /* Port 39 (N/A) N/A */ 1330 0x00, /* Port 40 (N/A) N/A */ 1331 0x00 /* Port 41 (N/A) N/A */ 1332 }; 1333 1334 int phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1335 1336 /* assigning default phy_addr for ext-phy */ 1337 *phy_addr = 0xff; 1338 1339 *phy_addr_int = _soc_hr3_int_phy_addr[phy_port]; 1340 1341 /* assigning GPHY address */ 1342 if (soc_feature(unit, soc_feature_gphy)) { 1343 if (((phy_port >= _HR3_GPHY_FIRST_PORT_NUM_PGW0) && 1344 (phy_port < _HR3_GPHY_FIRST_PORT_NUM_PGW0 + _HR3_GPHY_CNT)) || 1345 ((phy_port >= _HR3_GPHY_FIRST_PORT_NUM_PGW1) && 1346 (phy_port < _HR3_GPHY_FIRST_PORT_NUM_PGW1 + _HR3_GPHY_CNT))) { 1347 *phy_addr = _soc_hr3_gphy_addr[phy_port]; 1348 *phy_addr_int = 0; 1349 } 1350 } 1351 } 1352 #endif /* BCM_HURRICANE3_SUPPORT */ 1353 1354 #if defined(BCM_GREYHOUND2_SUPPORT) 1355 /* 1356 * Func : _greyhound2_phy_addr_default() 1357 * - to report default Int/Ext PHY_ADDR. 1358 * 1359 * Note : 1360 * - Major for default PHY address on all Int-PHY (for PM/SerDes) 1361 * - Those definitions are defined in GH2's TOP Spec. 1362 */ 1363 static void 1364 _greyhound2_phy_addr_default(int unit, int port, 1365 uint16 *phy_addr, uint16 *phy_addr_int) 1366 { 1367 static const uint16 _soc_gh2_int_phy_addr[] = { 1368 0x00, /* Port 0 (cmic) N/A */ 1369 0x00, /* Port 1 (N/A) */ 1370 0x81, /* Port 2 (SGMII4P_0) IntBus=0 Addr=0x01 */ 1371 0x81, /* Port 3 (SGMII4P_0) Share the same Addr */ 1372 0x81, /* Port 4 (SGMII4P_0) Share the same Addr */ 1373 0x81, /* Port 5 (SGMII4P_0) Share the same Addr */ 1374 0x85, /* Port 6 (SGMII4P_1) Share the same Addr */ 1375 0x85, /* Port 7 (SGMII4P_1) Share the same Addr */ 1376 0x85, /* Port 8 (SGMII4P_1) Share the same Addr */ 1377 0x85, /* Port 9 (SGMII4P_1) Share the same Addr */ 1378 0x89, /* Port 10 (SGMII4P_2) IntBus=0 Addr=0x09 */ 1379 0x89, /* Port 11 (SGMII4P_2) Share the same Addr */ 1380 0x89, /* Port 12 (SGMII4P_2) Share the same Addr */ 1381 0x89, /* Port 13 (SGMII4P_2) Share the same Addr */ 1382 0x8d, /* Port 14 (SGMII4P_4) Share the same Addr */ 1383 0x8d, /* Port 15 (SGMII4P_4) Share the same Addr */ 1384 0x8d, /* Port 16 (SGMII4P_4) Share the same Addr */ 1385 0x8d, /* Port 17 (SGMII4P_4) Share the same Addr */ 1386 0x91, /* Port 18 (SGMII4P_4) IntBus=0 Addr=0x11 */ 1387 0x91, /* Port 19 (SGMII4P_4) Share the same Addr */ 1388 0x91, /* Port 20 (SGMII4P_4) Share the same Addr */ 1389 0x91, /* Port 21 (SGMII4P_4) Share the same Addr */ 1390 0x95, /* Port 22 (SGMII4P_5) Share the same Addr */ 1391 0x95, /* Port 23 (SGMII4P_5) Share the same Addr */ 1392 0x95, /* Port 24 (SGMII4P_5) Share the same Addr */ 1393 0x95, /* Port 25 (SGMII4P_5) Share the same Addr */ 1394 0xc1, /* Port 26 (QTC0-SGMII/QSGMII) IntBus=2 Addr=0x01 */ 1395 0xc1, /* Port 27 (QTC0-SGMII/QSGMII)Share the same Addr */ 1396 0xc1, /* Port 28 (QTC0-SGMII/QSGMII)Share the same Addr */ 1397 0xc1, /* Port 29 (QTC0-SGMII/QSGMII)Share the same Addr */ 1398 0xc1, /* Port 30 (QTC0-QSGMII) Share the same Addr */ 1399 0xc1, /* Port 31 (QTC0-QSGMII) Share the same Addr */ 1400 0xc1, /* Port 32 (QTC0-QSGMII) Share the same Addr */ 1401 0xc1, /* Port 33 (QTC0-QSGMII) Share the same Addr */ 1402 0xc1, /* Port 34 (QTC0-QSGMII) Share the same Addr */ 1403 0xc1, /* Port 35 (QTC0-QSGMII) Share the same Addr */ 1404 0xc1, /* Port 36 (QTC0-QSGMII) Share the same Addr */ 1405 0xc1, /* Port 37 (QTC0-QSGMII) Share the same Addr */ 1406 0xc1, /* Port 38 (QTC0-QSGMII) Share the same Addr */ 1407 0xc1, /* Port 39 (QTC0-QSGMII) Share the same Addr */ 1408 0xc1, /* Port 40 (QTC0-QSGMII) Share the same Addr */ 1409 0xc1, /* Port 41 (QTC0-QSGMII) Share the same Addr */ 1410 0xc5, /* Port 42 (QTC1-SGMII/QSGMII) IntBus=2 Addr=0x05 */ 1411 0xc5, /* Port 43 (QTC1-SGMII/QSGMII)Share the same Addr */ 1412 0xc5, /* Port 44 (QTC1-SGMII/QSGMII)Share the same Addr */ 1413 0xc5, /* Port 45 (QTC1-SGMII/QSGMII)Share the same Addr */ 1414 0xc5, /* Port 46 (QTC1-QSGMII) Share the same Addr */ 1415 0xc5, /* Port 47 (QTC1-QSGMII) Share the same Addr */ 1416 0xc5, /* Port 48 (QTC1-QSGMII) Share the same Addr */ 1417 0xc5, /* Port 49 (QTC1-QSGMII) Share the same Addr */ 1418 0xc5, /* Port 50 (QTC1-QSGMII) Share the same Addr */ 1419 0xc5, /* Port 51 (QTC1-QSGMII) Share the same Addr */ 1420 0xc5, /* Port 52 (QTC1-QSGMII) Share the same Addr */ 1421 0xc5, /* Port 53 (QTC1-QSGMII) Share the same Addr */ 1422 0xc5, /* Port 54 (QTC1-QSGMII) Share the same Addr */ 1423 0xc5, /* Port 55 (QTC1-QSGMII) Share the same Addr */ 1424 0xc5, /* Port 56 (QTC1-QSGMII) Share the same Addr */ 1425 0xc5, /* Port 57 (QTC1-QSGMII) Share the same Addr */ 1426 0xa1, /* Port 58 (TSCE0) IntBus=1 Addr=0x01 */ 1427 0xa1, /* Port 59 (TSCE0) Share the same Addr */ 1428 0xa1, /* Port 60 (TSCE0) Share the same Addr */ 1429 0xa1, /* Port 61 (TSCE0) Share the same Addr */ 1430 0xa5, /* Port 62 (TSCE0) IntBus=1 Addr=0x05 */ 1431 0xa5, /* Port 63 (TSCE1) Share the same Addr */ 1432 0xa5, /* Port 64 (TSCE1) Share the same Addr */ 1433 0xa5, /* Port 65 (TSCE1) Share the same Addr */ 1434 0xa9, /* Port 66 (TSCE2) IntBus=1 Addr=0x09 */ 1435 0xa9, /* Port 67 (TSCE2) Share the same Addr */ 1436 0xa9, /* Port 68 (TSCE2) Share the same Addr */ 1437 0xa9, /* Port 69 (TSCE2) Share the same Addr */ 1438 0xad, /* Port 70 (TSCE3) IntBus=1 Addr=0x0d */ 1439 0xad, /* Port 71 (TSCE3) Share the same Addr */ 1440 0xad, /* Port 72 (TSCE3) Share the same Addr */ 1441 0xad, /* Port 73 (TSCE3) Share the same Addr */ 1442 0xb1, /* Port 74 (TSCE4) IntBus=1 Addr=0x11 */ 1443 0xb1, /* Port 75 (TSCE4) Share the same Addr */ 1444 0xb1, /* Port 76 (TSCE4) Share the same Addr */ 1445 0xb1, /* Port 77 (TSCE4) Share the same Addr */ 1446 0xb5, /* Port 78 (TSCE5) IntBus=1 Addr=0x15 */ 1447 0xb5, /* Port 79 (TSCE5) Share the same Addr */ 1448 0xb5, /* Port 80 (TSCE5) Share the same Addr */ 1449 0xb5, /* Port 81 (TSCE5) Share the same Addr */ 1450 0xb9, /* Port 82 (TSCE6) IntBus=1 Addr=0x19 */ 1451 0xb9, /* Port 83 (TSCE6) Share the same Addr */ 1452 0xb9, /* Port 84 (TSCE6) Share the same Addr */ 1453 0xb9, /* Port 85 (TSCF0) Share the same Addr */ 1454 0xe1, /* Port 86 (TSCF0) IntBus=3 Addr=0x01 */ 1455 0xe1, /* Port 87 (TSCF0) Share the same Addr */ 1456 0xe1, /* Port 88 (TSCF0) Share the same Addr */ 1457 0xe1 /* Port 89 (TSCF0) Share the same Addr */ 1458 }; 1459 1460 int phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1461 1462 /* assigning default phy_addr for ext-phy */ 1463 *phy_addr = 0xff; 1464 1465 *phy_addr_int = _soc_gh2_int_phy_addr[phy_port]; 1466 1467 } 1468 #endif /* BCM_GREYHOUND2_SUPPORT */ 1469 1470 #if defined(BCM_HELIX4_SUPPORT) 1471 1472 static void 1473 _helix4_phy_addr_default(int unit, int port, 1474 uint16 *phy_addr, uint16 *phy_addr_int) 1475 { 1476 static const uint16 _soc_helix4_int_phy_addr[] = { 1477 0x80, /* Port 0 (cmic) N/A */ 1478 1479 0x81, /* Port 1 (QC0) IntBus=0 Addr=0x01 */ 1480 0x81, /* Port 2 (QC0) IntBus=0 Addr=0x02 */ 1481 0x81, /* Port 3 (QC0) IntBus=0 Addr=0x03 */ 1482 0x81, /* Port 4 (QC0) IntBus=0 Addr=0x04 */ 1483 0x81, /* Port 5 (QC0) IntBus=0 Addr=0x05 */ 1484 0x81, /* Port 6 (QC0) IntBus=0 Addr=0x06 */ 1485 0x81, /* Port 7 (QC0) IntBus=0 Addr=0x07 */ 1486 0x81, /* Port 8 (QC0) IntBus=0 Addr=0x08 */ 1487 1488 0x89, /* Port 9 (QC1) IntBus=0 Addr=0x09 */ 1489 0x89, /* Port 10 (QC1) IntBus=0 Addr=0x0A */ 1490 0x89, /* Port 11 (QC1) IntBus=0 Addr=0x0B */ 1491 0x89, /* Port 12 (QC1) IntBus=0 Addr=0x0C */ 1492 0x89, /* Port 13 (QC1) IntBus=0 Addr=0x0D */ 1493 0x89, /* Port 14 (QC1) IntBus=0 Addr=0x0E */ 1494 0x89, /* Port 15 (QC1) IntBus=0 Addr=0x0F */ 1495 0x89, /* Port 16 (QC1) IntBus=0 Addr=0x10 */ 1496 1497 0x91, /* Port 17 (QC2) IntBus=0 Addr=0x11 */ 1498 0x91, /* Port 18 (QC2) IntBus=0 Addr=0x12 */ 1499 0x91, /* Port 19 (QC2) IntBus=0 Addr=0x13 */ 1500 0x91, /* Port 20 (QC2) IntBus=0 Addr=0x14 */ 1501 0x91, /* Port 21 (QC2) IntBus=0 Addr=0x15 */ 1502 0x91, /* Port 22 (QC2) IntBus=0 Addr=0x16 */ 1503 0x91, /* Port 23 (QC2) IntBus=0 Addr=0x17 */ 1504 0x91, /* Port 24 (QC2) IntBus=0 Addr=0x18 */ 1505 1506 0xA1, /* Port 25 (QC3) IntBus=1 Addr=0x01 */ 1507 0xA1, /* Port 26 (QC3) IntBus=1 Addr=0x02 */ 1508 0xA1, /* Port 27 (QC3) IntBus=1 Addr=0x03 */ 1509 0xA1, /* Port 28 (QC3) IntBus=1 Addr=0x04 */ 1510 0xA1, /* Port 29 (QC3) IntBus=1 Addr=0x05 */ 1511 0xA1, /* Port 30 (QC3) IntBus=1 Addr=0x06 */ 1512 0xA1, /* Port 31 (QC3) IntBus=1 Addr=0x07 */ 1513 0xA1, /* Port 32 (QC3) IntBus=1 Addr=0x08 */ 1514 1515 0xA9, /* Port 33 (QC4) IntBus=1 Addr=0x09 */ 1516 0xA9, /* Port 34 (QC4) IntBus=1 Addr=0x0a */ 1517 0xA9, /* Port 35 (QC4) IntBus=1 Addr=0x0b */ 1518 0xA9, /* Port 36 (QC4) IntBus=1 Addr=0x0c */ 1519 0xA9, /* Port 37 (QC4) IntBus=1 Addr=0x0d */ 1520 0xA9, /* Port 38 (QC4) IntBus=1 Addr=0x0e */ 1521 0xA9, /* Port 39 (QC4) IntBus=1 Addr=0x0f */ 1522 0xA9, /* Port 40 (QC4) IntBus=1 Addr=0x10 */ 1523 1524 0xB1, /* Port 41 (QC5) IntBus=1 Addr=0x11 */ 1525 0xB1, /* Port 42 (QC5) IntBus=1 Addr=0x12 */ 1526 0xB1, /* Port 43 (QC5) IntBus=1 Addr=0x13 */ 1527 0xB1, /* Port 44 (QC5) IntBus=1 Addr=0x14 */ 1528 0xB1, /* Port 45 (QC5) IntBus=1 Addr=0x15 */ 1529 0xB1, /* Port 46 (QC5) IntBus=1 Addr=0x16 */ 1530 0xB1, /* Port 47 (QC5) IntBus=1 Addr=0x17 */ 1531 0xB1, /* Port 48 (QC5) IntBus=1 Addr=0x18 */ 1532 1533 0xE3, /* Port 49 (QSG) IntBus=3 Addr=0x03 */ 1534 0xE3, /* Port 50 (---) IntBus=3 Addr=0x04 */ 1535 0xE3, /* Port 51 (---) IntBus= Addr=0x */ 1536 0xE3, /* Port 52 (---) IntBus= Addr=0x */ 1537 1538 0xC1, /* Port 53 (WC0) IntBus=2 Addr=0x01 */ 1539 0xC1, /* Port 54 (WC0) IntBus=2 Addr=0x02 */ 1540 0xC1, /* Port 55 (WC0) IntBus=2 Addr=0x03 */ 1541 0xC1, /* Port 56 (WC0) IntBus=2 Addr=0x04 */ 1542 1543 0xC5, /* Port 57 (WC1) IntBus=2 Addr=0x05 */ 1544 0xC5, /* Port 58 (WC1) IntBus=2 Addr=0x06 */ 1545 0xC5, /* Port 59 (WC1) IntBus=2 Addr=0x07 */ 1546 0xC5, /* Port 60 (WC1) IntBus=2 Addr=0x08 */ 1547 1548 0xC9, /* Port 61 (WC2) IntBus=2 Addr=0x09 */ 1549 0xC9, /* Port 62 (WC2) IntBus=2 Addr=0x0A */ 1550 0xC9, /* Port 63 (WC2) IntBus=2 Addr=0x0B */ 1551 0xC9, /* Port 64 (WC2) IntBus=2 Addr=0x0C */ 1552 }; 1553 1554 static const uint16 _soc_phy_addr_bcm56340[] = { 1555 1556 0x00, /* Port 0 (cmic) N/A */ 1557 1558 0x01, /* Port 1 (QC0) ExtBus=0 Addr=0x01 */ 1559 0x02, /* Port 2 (QC0) ExtBus=0 Addr=0x02 */ 1560 0x03, /* Port 3 (QC0) ExtBus=0 Addr=0x03 */ 1561 0x04, /* Port 4 (QC0) ExtBus=0 Addr=0x04 */ 1562 0x05, /* Port 5 (QC0) ExtBus=0 Addr=0x05 */ 1563 0x06, /* Port 6 (QC0) ExtBus=0 Addr=0x06 */ 1564 0x07, /* Port 7 (QC0) ExtBus=0 Addr=0x07 */ 1565 0x08, /* Port 8 (QC0) ExtBus=0 Addr=0x08 */ 1566 1567 0x0a, /* Port 9 (QC1) ExtBus=0 Addr=0x09 */ 1568 0x0b, /* Port 10 (QC1) ExtBus=0 Addr=0x0A */ 1569 0x0c, /* Port 11 (QC1) ExtBus=0 Addr=0x0B */ 1570 0x0d, /* Port 12 (QC1) ExtBus=0 Addr=0x0C */ 1571 0x0e, /* Port 13 (QC1) ExtBus=0 Addr=0x0D */ 1572 0x0f, /* Port 14 (QC1) ExtBus=0 Addr=0x0E */ 1573 0x10, /* Port 15 (QC1) ExtBus=0 Addr=0x0F */ 1574 0x11, /* Port 16 (QC1) ExtBus=0 Addr=0x10 */ 1575 1576 0x13, /* Port 17 (QC2) ExtBus=0 Addr=0x11 */ 1577 0x14, /* Port 18 (QC2) ExtBus=0 Addr=0x12 */ 1578 0x15, /* Port 19 (QC2) ExtBus=0 Addr=0x13 */ 1579 0x16, /* Port 20 (QC2) ExtBus=0 Addr=0x14 */ 1580 0x17, /* Port 21 (QC2) ExtBus=0 Addr=0x15 */ 1581 0x18, /* Port 22 (QC2) ExtBus=0 Addr=0x16 */ 1582 0x19, /* Port 23 (QC2) ExtBus=0 Addr=0x17 */ 1583 0x1a, /* Port 24 (QC2) ExtBus=0 Addr=0x18 */ 1584 1585 0x21, /* Port 25 (QC3) ExtBus=1 Addr=0x01 */ 1586 0x22, /* Port 26 (QC3) ExtBus=1 Addr=0x02 */ 1587 0x23, /* Port 27 (QC3) ExtBus=1 Addr=0x03 */ 1588 0x24, /* Port 28 (QC3) ExtBus=1 Addr=0x04 */ 1589 0x25, /* Port 29 (QC3) ExtBus=1 Addr=0x05 */ 1590 0x26, /* Port 30 (QC3) ExtBus=1 Addr=0x06 */ 1591 0x27, /* Port 31 (QC3) ExtBus=1 Addr=0x07 */ 1592 0x28, /* Port 32 (QC3) ExtBus=1 Addr=0x08 */ 1593 1594 0x2a, /* Port 33 (QC4) ExtBus=1 Addr=0x09 */ 1595 0x2b, /* Port 34 (QC4) ExtBus=1 Addr=0x0a */ 1596 0x2c, /* Port 35 (QC4) ExtBus=1 Addr=0x0b */ 1597 0x2d, /* Port 36 (QC4) ExtBus=1 Addr=0x0c */ 1598 0x2e, /* Port 37 (QC4) ExtBus=1 Addr=0x0d */ 1599 0x2f, /* Port 38 (QC4) ExtBus=1 Addr=0x0e */ 1600 0x30, /* Port 39 (QC4) ExtBus=1 Addr=0x0f */ 1601 0x31, /* Port 40 (QC4) ExtBus=1 Addr=0x10 */ 1602 1603 0x33, /* Port 41 (QC5) ExtBus=1 Addr=0x11 */ 1604 0x34, /* Port 42 (QC5) ExtBus=1 Addr=0x12 */ 1605 0x35, /* Port 43 (QC5) ExtBus=1 Addr=0x13 */ 1606 0x36, /* Port 44 (QC5) ExtBus=1 Addr=0x14 */ 1607 0x37, /* Port 45 (QC5) ExtBus=1 Addr=0x15 */ 1608 0x38, /* Port 46 (QC5) ExtBus=1 Addr=0x16 */ 1609 0x39, /* Port 47 (QC5) ExtBus=1 Addr=0x17 */ 1610 0x3a, /* Port 48 (QC5) ExtBus=1 Addr=0x18 */ 1611 1612 0x63, /* Port 49 (QSG) ExtBus=3 Addr=0x03 */ 1613 0x63, /* Port 50 (---) ExtBus=3 Addr=0x04 */ 1614 0x63, /* Port 51 (---) ExtBus= Addr=0x */ 1615 0x63, /* Port 52 (---) ExtBus= Addr=0x */ 1616 1617 0x41, /* Port 53 (WC0) ExtBus=2 Addr=0x01 */ 1618 0x42, /* Port 54 (WC0) ExtBus=2 Addr=0x02 */ 1619 0x43, /* Port 55 (WC0) ExtBus=2 Addr=0x03 */ 1620 0x44, /* Port 56 (WC0) ExtBus=2 Addr=0x04 */ 1621 1622 0x45, /* Port 57 (WC1) ExtBus=2 Addr=0x05 */ 1623 0x46, /* Port 58 (WC1) ExtBus=2 Addr=0x06 */ 1624 0x47, /* Port 59 (WC1) ExtBus=2 Addr=0x07 */ 1625 0x48, /* Port 60 (WC1) ExtBus=2 Addr=0x08 */ 1626 1627 0x49, /* Port 61 (WC2) ExtBus=2 Addr=0x09 */ 1628 0x4a, /* Port 62 (WC2) ExtBus=2 Addr=0x0A */ 1629 0x4b, /* Port 63 (WC2) ExtBus=2 Addr=0x0B */ 1630 0x4c, /* Port 64 (WC2) ExtBus=2 Addr=0x0C */ 1631 }; 1632 uint16 dev_id; 1633 uint8 rev_id; 1634 int phy_port; 1635 1636 soc_cm_get_id(unit, &dev_id, &rev_id); 1637 1638 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1639 1640 *phy_addr_int = _soc_helix4_int_phy_addr[phy_port]; 1641 1642 switch (dev_id) { 1643 case BCM56548H_DEVICE_ID: 1644 case BCM56548_DEVICE_ID: 1645 case BCM56547_DEVICE_ID: 1646 case BCM56344_DEVICE_ID: 1647 case BCM56342_DEVICE_ID: 1648 case BCM56340_DEVICE_ID: 1649 case BCM56049_DEVICE_ID: 1650 case BCM56048_DEVICE_ID: 1651 case BCM56047_DEVICE_ID: 1652 case BCM56042_DEVICE_ID: 1653 case BCM56041_DEVICE_ID: 1654 case BCM56040_DEVICE_ID: 1655 *phy_addr = _soc_phy_addr_bcm56340[phy_port]; 1656 break; 1657 default: 1658 *phy_addr = _soc_phy_addr_bcm56340[phy_port]; 1659 break; 1660 } 1661 } 1662 #endif /* BCM_HELIX4_SUPPORT */ 1663 1664 #if defined(BCM_TRIUMPH3_SUPPORT) 1665 1666 static void 1667 _triumph3_phy_addr_default(int unit, int port, 1668 uint16 *phy_addr, uint16 *phy_addr_int) 1669 { 1670 static const uint16 _soc_triumph3_int_phy_addr[] = { 1671 0x80, /* Port 0 (cmic) N/A */ 1672 0x81, /* Port 1 (XC0) IntBus=0 Addr=0x01 */ 1673 0x82, /* Port 2 (XC0) IntBus=0 Addr=0x02 */ 1674 0x83, /* Port 3 (XC0) IntBus=0 Addr=0x03 */ 1675 0x84, /* Port 4 (XC0) IntBus=0 Addr=0x04 */ 1676 0x85, /* Port 5 (XC1) IntBus=0 Addr=0x05 */ 1677 0x86, /* Port 6 (XC1) IntBus=0 Addr=0x06 */ 1678 0x87, /* Port 7 (XC1) IntBus=0 Addr=0x07 */ 1679 0x88, /* Port 8 (XC1) IntBus=0 Addr=0x08 */ 1680 0x89, /* Port 9 (XC2) IntBus=0 Addr=0x09 */ 1681 0x8A, /* Port 10 (XC2) IntBus=0 Addr=0x0A */ 1682 0x8B, /* Port 11 (XC2) IntBus=0 Addr=0x0B */ 1683 0x8C, /* Port 12 (XC2) IntBus=0 Addr=0x0C */ 1684 0x8D, /* Port 13 (XC3) IntBus=0 Addr=0x0D */ 1685 0x8E, /* Port 14 (XC3) IntBus=0 Addr=0x0E */ 1686 0x8F, /* Port 15 (XC3) IntBus=0 Addr=0x0F */ 1687 0x90, /* Port 16 (XC3) IntBus=0 Addr=0x10 */ 1688 0x91, /* Port 17 (XC4) IntBus=0 Addr=0x11 */ 1689 0x92, /* Port 18 (XC4) IntBus=0 Addr=0x12 */ 1690 0x93, /* Port 19 (XC4) IntBus=0 Addr=0x13 */ 1691 0x94, /* Port 20 (XC4) IntBus=0 Addr=0x14 */ 1692 0x95, /* Port 21 (XC5) IntBus=0 Addr=0x15 */ 1693 0x96, /* Port 22 (XC5) IntBus=0 Addr=0x16 */ 1694 0x97, /* Port 23 (XC5) IntBus=0 Addr=0x17 */ 1695 0x98, /* Port 24 (XC5) IntBus=0 Addr=0x18 */ 1696 0x99, /* Port 25 (XC6) IntBus=0 Addr=0x19 */ 1697 0x9A, /* Port 26 (XC6) IntBus=0 Addr=0x1A */ 1698 0x9B, /* Port 27 (XC6) IntBus=0 Addr=0x1B */ 1699 0x9C, /* Port 28 (XC6) IntBus=0 Addr=0x1C */ 1700 1701 0xA1, /* Port 29 (XC7) IntBus=1 Addr=0x01 */ 1702 0xA2, /* Port 30 (XC7) IntBus=1 Addr=0x02 */ 1703 0xA3, /* Port 31 (XC7) IntBus=1 Addr=0x03 */ 1704 0xA4, /* Port 32 (XC7) IntBus=1 Addr=0x04 */ 1705 0xA5, /* Port 33 (XC8) IntBus=1 Addr=0x05 */ 1706 0xA6, /* Port 34 (XC8) IntBus=1 Addr=0x06 */ 1707 0xA7, /* Port 35 (XC8) IntBus=1 Addr=0x07 */ 1708 0xA8, /* Port 36 (XC8) IntBus=1 Addr=0x08 */ 1709 0xA9, /* Port 37 (XC9) IntBus=1 Addr=0x09 */ 1710 0, /* Port 38 (---) IntBus=1 Addr=0 */ 1711 0, /* Port 39 (---) IntBus=1 Addr=0 */ 1712 0, /* Port 40 (---) IntBus=1 Addr=0 */ 1713 0xAD, /* Port 41 (XC10) IntBus=1 Addr=0x0D */ 1714 0xAE, /* Port 42 (XC10) IntBus=1 Addr=0x0E */ 1715 0xAF, /* Port 43 (XC10) IntBus=1 Addr=0x0F */ 1716 0xB0, /* Port 44 (XC10) IntBus=1 Addr=0x10 */ 1717 0xB1, /* Port 45 (XC11) IntBus=1 Addr=0x11 */ 1718 0xB2, /* Port 46 (XC11) IntBus=1 Addr=0x12 */ 1719 0xB3, /* Port 47 (XC11) IntBus=1 Addr=0x13 */ 1720 0xB4, /* Port 48 (XC11) IntBus=1 Addr=0x14 */ 1721 0xB5, /* Port 49 (XC12) IntBus=1 Addr=0x15 */ 1722 0xB6, /* Port 50 (XC12) IntBus=1 Addr=0x16 */ 1723 0xB7, /* Port 51 (XC12) IntBus=1 Addr=0x17 */ 1724 0xB8, /* Port 52 (XC12) IntBus=1 Addr=0x18 */ 1725 1726 #ifdef TR3_WCMOD_MULTIPORT_SUPPORT 1727 1728 0xC1, /* Port 53 (WC0) IntBus=2 Addr=0x01 */ 1729 0xC2, /* Port 54 (WC0) IntBus=2 Addr=0x02 */ 1730 0xC3, /* Port 55 (WC0) IntBus=2 Addr=0x03 */ 1731 0xC4, /* Port 56 (WC0) IntBus=2 Addr=0x04 */ 1732 0xC5, /* Port 57 (WC1) IntBus=2 Addr=0x05 */ 1733 0xC6, /* Port 58 (WC1) IntBus=2 Addr=0x06 */ 1734 0xC7, /* Port 59 (WC1) IntBus=2 Addr=0x07 */ 1735 0xC8, /* Port 60 (WC1) IntBus=2 Addr=0x08 */ 1736 0xC9, /* Port 61 (WC2) IntBus=2 Addr=0x09 */ 1737 0xCA, /* Port 62 (WC2) IntBus=2 Addr=0x0A */ 1738 0xCB, /* Port 63 (WC2) IntBus=2 Addr=0x0B */ 1739 0xCC, /* Port 64 (WC2) IntBus=2 Addr=0x0C */ 1740 0xCD, /* Port 65 (WC3) IntBus=2 Addr=0x0D */ 1741 0xCE, /* Port 66 (WC3) IntBus=2 Addr=0x0E */ 1742 0xCF, /* Port 67 (WC3) IntBus=2 Addr=0x0F */ 1743 0xD0, /* Port 68 (WC3) IntBus=2 Addr=0x10 */ 1744 0xD1, /* Port 69 (WC4) IntBus=2 Addr=0x11 */ 1745 0xD2, /* Port 70 (WC4) IntBus=2 Addr=0x12 */ 1746 0xD3, /* Port 71 (WC4) IntBus=2 Addr=0x13 */ 1747 0xD4, /* Port 72 (WC4) IntBus=2 Addr=0x14 */ 1748 0xD5, /* Port 73 (WC5) IntBus=2 Addr=0x15 */ 1749 0xD6, /* Port 74 (WC5) IntBus=2 Addr=0x16 */ 1750 0xD7, /* Port 75 (WC5) IntBus=2 Addr=0x17 */ 1751 0xD8, /* Port 76 (WC5) IntBus=2 Addr=0x18 */ 1752 0xD9, /* Port 77 (WC6) IntBus=2 Addr=0x19 */ 1753 0xDA, /* Port 78 (WC6) IntBus=2 Addr=0x1A */ 1754 0xDB, /* Port 79 (WC6) IntBus=2 Addr=0x1B */ 1755 0xDC, /* Port 80 (WC6) IntBus=2 Addr=0x1C */ 1756 #else 1757 0xC1, /* Port 53 (WC0) IntBus=2 Addr=0x01 */ 1758 0xC1, /* Port 54 (WC0) IntBus=2 Addr=0x02 */ 1759 0xC1, /* Port 55 (WC0) IntBus=2 Addr=0x03 */ 1760 0xC1, /* Port 56 (WC0) IntBus=2 Addr=0x04 */ 1761 0xC5, /* Port 57 (WC1) IntBus=2 Addr=0x05 */ 1762 0xC5, /* Port 58 (WC1) IntBus=2 Addr=0x06 */ 1763 0xC5, /* Port 59 (WC1) IntBus=2 Addr=0x07 */ 1764 0xC5, /* Port 60 (WC1) IntBus=2 Addr=0x08 */ 1765 0xC9, /* Port 61 (WC2) IntBus=2 Addr=0x09 */ 1766 0xC9, /* Port 62 (WC2) IntBus=2 Addr=0x0A */ 1767 0xC9, /* Port 63 (WC2) IntBus=2 Addr=0x0B */ 1768 0xC9, /* Port 64 (WC2) IntBus=2 Addr=0x0C */ 1769 0xCD, /* Port 65 (WC3) IntBus=2 Addr=0x0D */ 1770 0xCD, /* Port 66 (WC3) IntBus=2 Addr=0x0E */ 1771 0xCD, /* Port 67 (WC3) IntBus=2 Addr=0x0F */ 1772 0xCD, /* Port 68 (WC3) IntBus=2 Addr=0x10 */ 1773 0xD1, /* Port 69 (WC4) IntBus=2 Addr=0x11 */ 1774 0xD1, /* Port 70 (WC4) IntBus=2 Addr=0x12 */ 1775 0xD1, /* Port 71 (WC4) IntBus=2 Addr=0x13 */ 1776 0xD1, /* Port 72 (WC4) IntBus=2 Addr=0x14 */ 1777 0xD5, /* Port 73 (WC5) IntBus=2 Addr=0x15 */ 1778 0xD5, /* Port 74 (WC5) IntBus=2 Addr=0x16 */ 1779 0xD5, /* Port 75 (WC5) IntBus=2 Addr=0x17 */ 1780 0xD5, /* Port 76 (WC5) IntBus=2 Addr=0x18 */ 1781 0xD9, /* Port 77 (WC6) IntBus=2 Addr=0x19 */ 1782 0xD9, /* Port 78 (WC6) IntBus=2 Addr=0x1A */ 1783 0xD9, /* Port 79 (WC6) IntBus=2 Addr=0x1B */ 1784 0xD9, /* Port 80 (WC6) IntBus=2 Addr=0x1C */ 1785 #endif /* TR3_WCMOD_MULTIPORT_SUPPORT */ 1786 }; 1787 1788 static const uint16 _soc_phy_addr_bcm56640[] = { 1789 0x00, /* Port 0 (cmic) N/A */ 1790 0x01, /* Port 1 (XC0) ExtBus=0 Addr=0x01 */ 1791 0x02, /* Port 2 (XC0) ExtBus=0 Addr=0x02 */ 1792 0x03, /* Port 3 (XC0) ExtBus=0 Addr=0x03 */ 1793 0x04, /* Port 4 (XC0) ExtBus=0 Addr=0x04 */ 1794 0x05, /* Port 5 (XC1) ExtBus=0 Addr=0x05 */ 1795 0x06, /* Port 6 (XC1) ExtBus=0 Addr=0x06 */ 1796 0x07, /* Port 7 (XC1) ExtBus=0 Addr=0x07 */ 1797 0x08, /* Port 8 (XC1) ExtBus=0 Addr=0x08 */ 1798 0x09, /* Port 9 (XC2) ExtBus=0 Addr=0x09 */ 1799 0x0A, /* Port 10 (XC2) ExtBus=0 Addr=0x0A */ 1800 0x0B, /* Port 11 (XC2) ExtBus=0 Addr=0x0B */ 1801 0x0C, /* Port 12 (XC2) ExtBus=0 Addr=0x0C */ 1802 0x0D, /* Port 13 (XC3) ExtBus=0 Addr=0x0D */ 1803 0x0E, /* Port 14 (XC3) ExtBus=0 Addr=0x0E */ 1804 0x0F, /* Port 15 (XC3) ExtBus=0 Addr=0x0F */ 1805 0x10, /* Port 16 (XC3) ExtBus=0 Addr=0x10 */ 1806 0x11, /* Port 17 (XC4) ExtBus=0 Addr=0x11 */ 1807 0x12, /* Port 18 (XC4) ExtBus=0 Addr=0x12 */ 1808 0x13, /* Port 19 (XC4) ExtBus=0 Addr=0x13 */ 1809 0x14, /* Port 20 (XC4) ExtBus=0 Addr=0x14 */ 1810 0x15, /* Port 21 (XC5) ExtBus=0 Addr=0x15 */ 1811 0x16, /* Port 22 (XC5) ExtBus=0 Addr=0x16 */ 1812 0x17, /* Port 23 (XC5) ExtBus=0 Addr=0x17 */ 1813 0x18, /* Port 24 (XC5) ExtBus=0 Addr=0x18 */ 1814 1815 0x21, /* Port 25 (XC6) ExtBus=1 Addr=0x01 */ 1816 0x22, /* Port 26 (XC6) ExtBus=1 Addr=0x02 */ 1817 0x23, /* Port 27 (XC6) ExtBus=1 Addr=0x03 */ 1818 0x24, /* Port 28 (XC6) ExtBus=1 Addr=0x04 */ 1819 0x25, /* Port 29 (XC7) ExtBus=1 Addr=0x05 */ 1820 0x26, /* Port 30 (XC7) ExtBus=1 Addr=0x06 */ 1821 0x27, /* Port 31 (XC7) ExtBus=1 Addr=0x07 */ 1822 0x28, /* Port 32 (XC7) ExtBus=1 Addr=0x08 */ 1823 0x29, /* Port 33 (XC8) ExtBus=1 Addr=0x09 */ 1824 0x2A, /* Port 34 (XC8) ExtBus=1 Addr=0x0A */ 1825 0x2B, /* Port 35 (XC8) ExtBus=1 Addr=0x0B */ 1826 0x2C, /* Port 36 (XC8) ExtBus=1 Addr=0x0C */ 1827 0x1D, /* Port 37 (XC9) ExtBus=0 Addr=0x1d */ 1828 0, /* Port 38 (---) ExtBus=1 Addr=0 */ 1829 0, /* Port 39 (---) ExtBus=1 Addr=0 */ 1830 0, /* Port 40 (---) ExtBus=1 Addr=0 */ 1831 0x2D, /* Port 41 (XC10) ExtBus=1 Addr=0x0D */ 1832 0x2E, /* Port 42 (XC10) ExtBus=1 Addr=0x0E */ 1833 0x2F, /* Port 43 (XC10) ExtBus=1 Addr=0x0F */ 1834 0x30, /* Port 44 (XC10) ExtBus=1 Addr=0x10 */ 1835 0x31, /* Port 45 (XC11) ExtBus=1 Addr=0x11 */ 1836 0x32, /* Port 46 (XC11) ExtBus=1 Addr=0x12 */ 1837 0x33, /* Port 47 (XC11) ExtBus=1 Addr=0x13 */ 1838 0x34, /* Port 48 (XC11) ExtBus=1 Addr=0x14 */ 1839 0x35, /* Port 49 (XC12) ExtBus=1 Addr=0x15 */ 1840 0x36, /* Port 50 (XC12) ExtBus=1 Addr=0x16 */ 1841 0x37, /* Port 51 (XC12) ExtBus=1 Addr=0x17 */ 1842 0x38, /* Port 52 (XC12) ExtBus=1 Addr=0x18 */ 1843 1844 0x41, /* Port 53 (WC0) ExtBus=2 Addr=0x01 */ 1845 0x42, /* Port 54 (WC0) ExtBus=2 Addr=0x02 */ 1846 0x43, /* Port 55 (WC0) ExtBus=2 Addr=0x03 */ 1847 0x44, /* Port 56 (WC0) ExtBus=2 Addr=0x04 */ 1848 0x45, /* Port 57 (WC1) ExtBus=2 Addr=0x05 */ 1849 0x46, /* Port 58 (WC1) ExtBus=2 Addr=0x06 */ 1850 0x47, /* Port 59 (WC1) ExtBus=2 Addr=0x07 */ 1851 0x48, /* Port 60 (WC1) ExtBus=2 Addr=0x08 */ 1852 0x49, /* Port 61 (WC2) ExtBus=2 Addr=0x09 */ 1853 0x4A, /* Port 62 (WC2) ExtBus=2 Addr=0x0A */ 1854 0x4B, /* Port 63 (WC2) ExtBus=2 Addr=0x0B */ 1855 0x4C, /* Port 64 (WC2) ExtBus=2 Addr=0x0C */ 1856 0x4D, /* Port 65 (WC3) ExtBus=2 Addr=0x0D */ 1857 0x4E, /* Port 66 (WC3) ExtBus=2 Addr=0x0E */ 1858 0x4F, /* Port 67 (WC3) ExtBus=2 Addr=0x0F */ 1859 0x50, /* Port 68 (WC3) ExtBus=2 Addr=0x10 */ 1860 0x51, /* Port 69 (WC4) ExtBus=2 Addr=0x11 */ 1861 0x52, /* Port 70 (WC4) ExtBus=2 Addr=0x12 */ 1862 1863 0x53, /* Port 71 (WC4) ExtBus=2 Addr=0x13 */ 1864 0x54, /* Port 72 (WC4) ExtBus=2 Addr=0x14 */ 1865 0x55, /* Port 73 (WC5) ExtBus=2 Addr=0x15 */ 1866 0x56, /* Port 74 (WC5) ExtBus=2 Addr=0x16 */ 1867 0x57, /* Port 75 (WC5) ExtBus=2 Addr=0x17 */ 1868 0x58, /* Port 76 (WC5) ExtBus=2 Addr=0x18 */ 1869 0x59, /* Port 77 (WC6) ExtBus=2 Addr=0x19 */ 1870 0x5A, /* Port 78 (WC6) ExtBus=2 Addr=0x1A */ 1871 0x5B, /* Port 79 (WC6) ExtBus=2 Addr=0x1B */ 1872 0x5C, /* Port 80 (WC6) ExtBus=2 Addr=0x1C */ 1873 }; 1874 uint16 dev_id; 1875 uint8 rev_id; 1876 int phy_port; 1877 1878 soc_cm_get_id(unit, &dev_id, &rev_id); 1879 1880 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 1881 1882 *phy_addr_int = _soc_triumph3_int_phy_addr[phy_port]; 1883 1884 switch (dev_id) { 1885 case BCM56640_DEVICE_ID: 1886 1887 case BCM56643_DEVICE_ID: 1888 case BCM56644_DEVICE_ID: 1889 case BCM56649_DEVICE_ID: 1890 case BCM56540_DEVICE_ID: 1891 case BCM56541_DEVICE_ID: 1892 case BCM56542_DEVICE_ID: 1893 case BCM56543_DEVICE_ID: 1894 case BCM56544_DEVICE_ID: 1895 case BCM56545_DEVICE_ID: 1896 case BCM56546_DEVICE_ID: 1897 *phy_addr = _soc_phy_addr_bcm56640[phy_port]; 1898 break; 1899 default: 1900 1901 *phy_addr = _soc_phy_addr_bcm56640[phy_port]; 1902 break; 1903 } 1904 } 1905 #endif /* BCM_TRIUMPH3_SUPPORT */ 1906 1907 #if defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_APOLLO_SUPPORT) || \ 1908 defined(BCM_VALKYRIE2_SUPPORT) 1909 static void 1910 _triumph2_phy_addr_default(int unit, int port, 1911 uint16 *phy_addr, uint16 *phy_addr_int) 1912 { 1913 static const uint16 _soc_triumph2_int_phy_addr[] = { 1914 0x00, /* Port 0 (cmic) N/A */ 1915 0x99, /* Port 1 (9SERDES) IntBus=0 Addr=0x19 */ 1916 0x81, /* Port 2 (8SERDES_0) IntBus=0 Addr=0x01 */ 1917 0x82, /* Port 3 (8SERDES_0) IntBus=0 Addr=0x02 */ 1918 0x83, /* Port 4 (8SERDES_0) IntBus=0 Addr=0x03 */ 1919 0x84, /* Port 5 (8SERDES_0) IntBus=0 Addr=0x04 */ 1920 0x85, /* Port 6 (8SERDES_0) IntBus=0 Addr=0x05 */ 1921 0x86, /* Port 7 (8SERDES_0) IntBus=0 Addr=0x06 */ 1922 0x87, /* Port 8 (8SERDES_0) IntBus=0 Addr=0x07 */ 1923 0x88, /* Port 9 (8SERDES_0) IntBus=0 Addr=0x08 */ 1924 0x89, /* Port 10 (8SERDES_1) IntBus=0 Addr=0x09 */ 1925 0x8a, /* Port 11 (8SERDES_1) IntBus=0 Addr=0x0a */ 1926 0x8b, /* Port 12 (8SERDES_1) IntBus=0 Addr=0x0b */ 1927 0x8c, /* Port 13 (8SERDES_1) IntBus=0 Addr=0x0c */ 1928 0x8d, /* Port 14 (8SERDES_1) IntBus=0 Addr=0x0d */ 1929 0x8e, /* Port 15 (8SERDES_1) IntBus=0 Addr=0x0e */ 1930 0x8f, /* Port 16 (8SERDES_1) IntBus=0 Addr=0x0f */ 1931 0x90, /* Port 17 (8SERDES_1) IntBus=0 Addr=0x10 */ 1932 0x91, /* Port 18 (9SERDES) IntBus=0 Addr=0x11 */ 1933 0x92, /* Port 19 (9SERDES) IntBus=0 Addr=0x12 */ 1934 0x93, /* Port 20 (9SERDES) IntBus=0 Addr=0x13 */ 1935 0x94, /* Port 21 (9SERDES) IntBus=0 Addr=0x14 */ 1936 0x95, /* Port 22 (9SERDES) IntBus=0 Addr=0x15 */ 1937 0x96, /* Port 23 (9SERDES) IntBus=0 Addr=0x16 */ 1938 0x97, /* Port 24 (9SERDES) IntBus=0 Addr=0x17 */ 1939 0x98, /* Port 25 (9SERDES) IntBus=0 Addr=0x18 */ 1940 0xd9, /* Port 26 (HC0) IntBus=2 Addr=0x19 */ 1941 0xda, /* Port 27 (HC1) IntBus=2 Addr=0x1a */ 1942 0xdb, /* Port 28 (HC2) IntBus=2 Addr=0x1b */ 1943 0xdc, /* Port 29 (HC3) IntBus=2 Addr=0x1c */ 1944 0xc1, /* Port 30 (HL0) IntBus=2 Addr=0x01 */ 1945 0xc2, /* Port 31 (HL0) IntBus=2 Addr=0x02 */ 1946 0xc3, /* Port 32 (HL0) IntBus=2 Addr=0x03 */ 1947 0xc4, /* Port 33 (HL0) IntBus=2 Addr=0x04 */ 1948 0xc5, /* Port 34 (HL1) IntBus=2 Addr=0x05 */ 1949 0xc6, /* Port 35 (HL1) IntBus=2 Addr=0x06 */ 1950 0xc7, /* Port 36 (HL1) IntBus=2 Addr=0x07 */ 1951 0xc8, /* Port 37 (HL1) IntBus=2 Addr=0x08 */ 1952 0xc9, /* Port 38 (HL2) IntBus=2 Addr=0x09 */ 1953 0xca, /* Port 39 (HL2) IntBus=2 Addr=0x0a */ 1954 0xcb, /* Port 40 (HL2) IntBus=2 Addr=0x0b */ 1955 0xcc, /* Port 41 (HL2) IntBus=2 Addr=0x0c */ 1956 0xcd, /* Port 42 (HL3) IntBus=2 Addr=0x0d */ 1957 0xce, /* Port 43 (HL3) IntBus=2 Addr=0x0e */ 1958 0xcf, /* Port 44 (HL3) IntBus=2 Addr=0x0f */ 1959 0xd0, /* Port 45 (HL3) IntBus=2 Addr=0x10 */ 1960 0xd1, /* Port 46 (HL4) IntBus=2 Addr=0x11 */ 1961 0xd2, /* Port 47 (HL4) IntBus=2 Addr=0x12 */ 1962 0xd3, /* Port 48 (HL4) IntBus=2 Addr=0x13 */ 1963 0xd4, /* Port 49 (HL4) IntBus=2 Addr=0x14 */ 1964 0xd5, /* Port 50 (HL5) IntBus=2 Addr=0x15 */ 1965 0xd6, /* Port 51 (HL5) IntBus=2 Addr=0x16 */ 1966 0xd7, /* Port 52 (HL5) IntBus=2 Addr=0x17 */ 1967 0xd8, /* Port 53 (HL5) IntBus=2 Addr=0x18 */ 1968 }; 1969 1970 static const uint16 _soc_phy_addr_bcm56630[] = { 1971 0x00, /* Port 0 (cmic) N/A */ 1972 0x19, /* Port 1 ( ge0) ExtBus=0 Addr=0x19 */ 1973 0x00, /* Port 2 ( N/A) */ 1974 0x00, /* Port 3 ( N/A) */ 1975 0x00, /* Port 4 ( N/A) */ 1976 0x00, /* Port 5 ( N/A) */ 1977 0x00, /* Port 6 ( N/A) */ 1978 0x00, /* Port 7 ( N/A) */ 1979 0x00, /* Port 8 ( N/A) */ 1980 0x00, /* Port 9 ( N/A) */ 1981 0x00, /* Port 10 ( N/A) */ 1982 0x00, /* Port 11 ( N/A) */ 1983 0x00, /* Port 12 ( N/A) */ 1984 0x00, /* Port 13 ( N/A) */ 1985 0x00, /* Port 14 ( N/A) */ 1986 0x00, /* Port 15 ( N/A) */ 1987 0x00, /* Port 16 ( N/A) */ 1988 0x00, /* Port 17 ( N/A) */ 1989 0x00, /* Port 18 ( N/A) */ 1990 0x00, /* Port 19 ( N/A) */ 1991 0x00, /* Port 20 ( N/A) */ 1992 0x00, /* Port 21 ( N/A) */ 1993 0x00, /* Port 22 ( N/A) */ 1994 0x00, /* Port 23 ( N/A) */ 1995 0x00, /* Port 24 ( N/A) */ 1996 0x00, /* Port 25 ( N/A) */ 1997 0x41, /* Port 26 ( hg0) ExtBus=2 Addr=0x01 */ 1998 0x42, /* Port 27 ( hg1) ExtBus=2 Addr=0x02 */ 1999 0x43, /* Port 28 ( hg2) ExtBus=2 Addr=0x03 */ 2000 0x44, /* Port 29 ( hg3) ExtBus=2 Addr=0x04 */ 2001 0x01, /* Port 30 ( ge1) ExtBus=0 Addr=0x01 */ 2002 0x02, /* Port 31 ( ge2) ExtBus=0 Addr=0x02 */ 2003 0x03, /* Port 32 ( ge3) ExtBus=0 Addr=0x03 */ 2004 0x04, /* Port 33 ( ge4) ExtBus=0 Addr=0x04 */ 2005 0x05, /* Port 34 ( ge5) ExtBus=0 Addr=0x05 */ 2006 0x06, /* Port 35 ( ge6) ExtBus=0 Addr=0x06 */ 2007 0x07, /* Port 36 ( ge7) ExtBus=0 Addr=0x07 */ 2008 0x08, /* Port 37 ( ge8) ExtBus=0 Addr=0x08 */ 2009 0x09, /* Port 38 ( ge9) ExtBus=0 Addr=0x09 */ 2010 0x0a, /* Port 39 (ge10) ExtBus=0 Addr=0x0a */ 2011 0x0b, /* Port 40 (ge11) ExtBus=0 Addr=0x0b */ 2012 0x0c, /* Port 41 (ge12) ExtBus=0 Addr=0x0c */ 2013 0x0d, /* Port 42 (ge13) ExtBus=0 Addr=0x0d */ 2014 0x0e, /* Port 43 (ge14) ExtBus=0 Addr=0x0e */ 2015 0x0f, /* Port 44 (ge15) ExtBus=0 Addr=0x0f */ 2016 0x10, /* Port 45 (ge16) ExtBus=0 Addr=0x10 */ 2017 0x11, /* Port 46 (ge17) ExtBus=0 Addr=0x11 */ 2018 0x12, /* Port 47 (ge18) ExtBus=0 Addr=0x12 */ 2019 0x13, /* Port 48 (ge19) ExtBus=0 Addr=0x13 */ 2020 0x14, /* Port 49 (ge20) ExtBus=0 Addr=0x14 */ 2021 0x15, /* Port 50 (ge21) ExtBus=0 Addr=0x15 */ 2022 0x16, /* Port 51 (ge22) ExtBus=0 Addr=0x16 */ 2023 0x17, /* Port 52 (ge23) ExtBus=0 Addr=0x17 */ 2024 0x18, /* Port 53 (ge24) ExtBus=0 Addr=0x18 */ 2025 }; 2026 2027 static const uint16 _soc_phy_addr_bcm56634[] = { 2028 0x00, /* Port 0 (cmic) N/A */ 2029 0x19, /* Port 1 ( ge0) ExtBus=0 Addr=0x19 */ 2030 0x09, /* Port 2 ( ge1) ExtBus=0 Addr=0x09 */ 2031 0x0a, /* Port 3 ( ge2) ExtBus=0 Addr=0x0a */ 2032 0x0b, /* Port 4 ( ge3) ExtBus=0 Addr=0x0b */ 2033 0x0c, /* Port 5 ( ge4) ExtBus=0 Addr=0x0c */ 2034 0x0d, /* Port 6 ( ge5) ExtBus=0 Addr=0x0d */ 2035 0x0e, /* Port 7 ( ge6) ExtBus=0 Addr=0x0e */ 2036 0x0f, /* Port 8 ( ge7) ExtBus=0 Addr=0x0f */ 2037 0x10, /* Port 9 ( ge8) ExtBus=0 Addr=0x10 */ 2038 0x15, /* Port 10 ( ge9) ExtBus=0 Addr=0x15 */ 2039 0x16, /* Port 11 (ge10) ExtBus=0 Addr=0x16 */ 2040 0x17, /* Port 12 (ge11) ExtBus=0 Addr=0x17 */ 2041 0x18, /* Port 13 (ge12) ExtBus=0 Addr=0x18 */ 2042 0x21, /* Port 14 (ge13) ExtBus=1 Addr=0x01 */ 2043 0x22, /* Port 15 (ge14) ExtBus=1 Addr=0x02 */ 2044 0x23, /* Port 16 (ge15) ExtBus=1 Addr=0x03 */ 2045 0x24, /* Port 17 (ge16) ExtBus=1 Addr=0x04 */ 2046 0x29, /* Port 18 (ge17) ExtBus=1 Addr=0x09 */ 2047 0x2a, /* Port 19 (ge18) ExtBus=1 Addr=0x0a */ 2048 0x2b, /* Port 20 (ge19) ExtBus=1 Addr=0x0b */ 2049 0x2c, /* Port 21 (ge20) ExtBus=1 Addr=0x0c */ 2050 0x2d, /* Port 22 (ge21) ExtBus=1 Addr=0x0d */ 2051 0x2e, /* Port 23 (ge22) ExtBus=1 Addr=0x0e */ 2052 0x2f, /* Port 24 (ge23) ExtBus=1 Addr=0x0f */ 2053 0x30, /* Port 25 (ge24) ExtBus=1 Addr=0x10 */ 2054 0x41, /* Port 26 ( hg0) ExtBus=2 Addr=0x01 */ 2055 0x42, /* Port 27 ( hg1) ExtBus=2 Addr=0x02 */ 2056 0x43, /* Port 28 ( hg2) ExtBus=2 Addr=0x03 */ 2057 0x44, /* Port 29 ( hg3) ExtBus=2 Addr=0x04 */ 2058 0x01, /* Port 30 (ge25) ExtBus=0 Addr=0x01 */ 2059 0x02, /* Port 31 (ge26) ExtBus=0 Addr=0x02 */ 2060 0x03, /* Port 32 (ge27) ExtBus=0 Addr=0x03 */ 2061 0x04, /* Port 33 (ge28) ExtBus=0 Addr=0x04 */ 2062 0x05, /* Port 34 (ge29) ExtBus=0 Addr=0x05 */ 2063 0x06, /* Port 35 (ge30) ExtBus=0 Addr=0x06 */ 2064 0x07, /* Port 36 (ge31) ExtBus=0 Addr=0x07 */ 2065 0x08, /* Port 37 (ge32) ExtBus=0 Addr=0x08 */ 2066 0x11, /* Port 38 (ge33) ExtBus=0 Addr=0x11 */ 2067 0x12, /* Port 39 (ge34) ExtBus=0 Addr=0x12 */ 2068 0x13, /* Port 40 (ge35) ExtBus=0 Addr=0x13 */ 2069 0x14, /* Port 41 (ge36) ExtBus=0 Addr=0x14 */ 2070 0x25, /* Port 42 (ge37) ExtBus=1 Addr=0x05 */ 2071 0x26, /* Port 43 (ge38) ExtBus=1 Addr=0x06 */ 2072 0x27, /* Port 44 (ge39) ExtBus=1 Addr=0x07 */ 2073 0x28, /* Port 45 (ge40) ExtBus=1 Addr=0x08 */ 2074 0x31, /* Port 46 (ge41) ExtBus=1 Addr=0x11 */ 2075 0x32, /* Port 47 (ge42) ExtBus=1 Addr=0x12 */ 2076 0x33, /* Port 48 (ge43) ExtBus=1 Addr=0x13 */ 2077 0x34, /* Port 49 (ge44) ExtBus=1 Addr=0x14 */ 2078 0x35, /* Port 50 (ge45) ExtBus=1 Addr=0x15 */ 2079 0x36, /* Port 51 (ge46) ExtBus=1 Addr=0x16 */ 2080 0x37, /* Port 52 (ge47) ExtBus=1 Addr=0x17 */ 2081 0x38, /* Port 53 (ge48) ExtBus=1 Addr=0x18 */ 2082 }; 2083 2084 2085 static const uint16 _soc_phy_addr_bcm56636[] = { 2086 0x00, /* Port 0 (cmic) N/A */ 2087 0x19, /* Port 1 ( ge0) ExtBus=1 Addr=0x19 */ 2088 0x09, /* Port 2 ( ge1) ExtBus=0 Addr=0x09 */ 2089 0x0a, /* Port 3 ( ge2) ExtBus=0 Addr=0x0a */ 2090 0x0b, /* Port 4 ( ge3) ExtBus=0 Addr=0x0b */ 2091 0x0c, /* Port 5 ( ge4) ExtBus=0 Addr=0x0c */ 2092 0x0d, /* Port 6 ( ge5) ExtBus=0 Addr=0x0d */ 2093 0x0e, /* Port 7 ( ge6) ExtBus=0 Addr=0x0e */ 2094 0x0f, /* Port 8 ( ge7) ExtBus=0 Addr=0x0f */ 2095 0x10, /* Port 9 ( ge8) ExtBus=0 Addr=0x10 */ 2096 0x15, /* Port 10 ( ge9) ExtBus=0 Addr=0x15 */ 2097 0x16, /* Port 11 (ge10) ExtBus=0 Addr=0x16 */ 2098 0x17, /* Port 12 (ge11) ExtBus=0 Addr=0x17 */ 2099 0x18, /* Port 13 (ge12) ExtBus=0 Addr=0x18 */ 2100 0x00, /* Port 14 ( N/A) */ 2101 0x00, /* Port 15 ( N/A) */ 2102 0x00, /* Port 16 ( N/A) */ 2103 0x00, /* Port 17 ( N/A) */ 2104 0x00, /* Port 18 ( N/A) */ 2105 0x00, /* Port 19 ( N/A) */ 2106 0x00, /* Port 20 ( N/A) */ 2107 0x00, /* Port 21 ( N/A) */ 2108 0x00, /* Port 22 ( N/A) */ 2109 0x00, /* Port 23 ( N/A) */ 2110 0x00, /* Port 24 ( N/A) */ 2111 0x00, /* Port 25 ( N/A) */ 2112 0x41, /* Port 26 ( hg0) ExtBus=2 Addr=0x01 */ 2113 0x42, /* Port 27 ( hg1) ExtBus=2 Addr=0x02 */ 2114 0x43, /* Port 28 ( hg2) ExtBus=2 Addr=0x03 */ 2115 0x44, /* Port 29 ( hg3) ExtBus=2 Addr=0x04 */ 2116 0x01, /* Port 30 (ge25) ExtBus=0 Addr=0x01 */ 2117 0x02, /* Port 31 (ge26) ExtBus=0 Addr=0x02 */ 2118 0x03, /* Port 32 (ge27) ExtBus=0 Addr=0x03 */ 2119 0x04, /* Port 33 (ge28) ExtBus=0 Addr=0x04 */ 2120 0x05, /* Port 34 (ge29) ExtBus=0 Addr=0x05 */ 2121 0x06, /* Port 35 (ge30) ExtBus=0 Addr=0x06 */ 2122 0x07, /* Port 36 (ge31) ExtBus=0 Addr=0x07 */ 2123 0x08, /* Port 37 (ge32) ExtBus=0 Addr=0x08 */ 2124 0x11, /* Port 38 (ge33) ExtBus=0 Addr=0x11 */ 2125 0x12, /* Port 39 (ge34) ExtBus=0 Addr=0x12 */ 2126 0x13, /* Port 40 (ge35) ExtBus=0 Addr=0x13 */ 2127 0x14, /* Port 41 (ge36) ExtBus=0 Addr=0x14 */ 2128 0x45, /* Port 42 (ge37) ExtBus=2 Addr=0x05 */ 2129 0x00, /* Port 43 ( N/A) */ 2130 0x00, /* Port 44 ( N/A) */ 2131 0x00, /* Port 45 ( N/A) */ 2132 0x00, /* Port 46 ( N/A) */ 2133 0x00, /* Port 47 ( N/A) */ 2134 0x00, /* Port 48 ( N/A) */ 2135 0x00, /* Port 49 ( N/A) */ 2136 0x46, /* Port 50 (ge45) ExtBus=2 Addr=0x06 */ 2137 0x00, /* Port 51 ( N/A) */ 2138 0x00, /* Port 52 ( N/A) */ 2139 0x00, /* Port 53 ( N/A) */ 2140 }; 2141 2142 static const uint16 _soc_phy_addr_bcm56638[] = { 2143 0x00, /* Port 0 (cmic) N/A */ 2144 0x19, /* Port 1 ( ge0) ExtBus=1 Addr=0x19 */ 2145 0x00, /* Port 2 ( N/A) */ 2146 0x00, /* Port 3 ( N/A) */ 2147 0x00, /* Port 4 ( N/A) */ 2148 0x00, /* Port 5 ( N/A) */ 2149 0x00, /* Port 6 ( N/A) */ 2150 0x00, /* Port 7 ( N/A) */ 2151 0x00, /* Port 8 ( N/A) */ 2152 0x00, /* Port 9 ( N/A) */ 2153 0x00, /* Port 10 ( N/A) */ 2154 0x00, /* Port 11 ( N/A) */ 2155 0x00, /* Port 12 ( N/A) */ 2156 0x00, /* Port 13 ( N/A) */ 2157 0x00, /* Port 14 ( N/A) */ 2158 0x00, /* Port 15 ( N/A) */ 2159 0x00, /* Port 16 ( N/A) */ 2160 0x00, /* Port 17 ( N/A) */ 2161 0x00, /* Port 18 ( N/A) */ 2162 0x00, /* Port 19 ( N/A) */ 2163 0x00, /* Port 20 ( N/A) */ 2164 0x00, /* Port 21 ( N/A) */ 2165 0x00, /* Port 22 ( N/A) */ 2166 0x00, /* Port 23 ( N/A) */ 2167 0x00, /* Port 24 ( N/A) */ 2168 0x00, /* Port 25 ( N/A) */ 2169 0x41, /* Port 26 ( hg0) ExtBus=2 Addr=0x01 */ 2170 0x42, /* Port 27 ( hg1) ExtBus=2 Addr=0x02 */ 2171 0x43, /* Port 28 ( hg2) ExtBus=2 Addr=0x03 */ 2172 0x44, /* Port 29 ( hg3) ExtBus=2 Addr=0x04 */ 2173 0x45, /* Port 30 ( xe0) ExtBus=2 Addr=0x05 */ 2174 0x00, /* Port 31 ( N/A) */ 2175 0x00, /* Port 32 ( N/A) */ 2176 0x00, /* Port 33 ( N/A) */ 2177 0x00, /* Port 34 ( N/A) */ 2178 0x00, /* Port 35 ( N/A) */ 2179 0x00, /* Port 36 ( N/A) */ 2180 0x00, /* Port 37 ( N/A) */ 2181 0x46, /* Port 38 ( xe1) ExtBus=2 Addr=0x06 */ 2182 0x00, /* Port 39 ( N/A) */ 2183 0x00, /* Port 40 ( N/A) */ 2184 0x00, /* Port 41 ( N/A) */ 2185 0x47, /* Port 42 ( xe2) ExtBus=2 Addr=0x07 */ 2186 0x00, /* Port 43 ( N/A) */ 2187 0x00, /* Port 44 ( N/A) */ 2188 0x00, /* Port 45 ( N/A) */ 2189 0x00, /* Port 46 ( N/A) */ 2190 0x00, /* Port 47 ( N/A) */ 2191 0x00, /* Port 48 ( N/A) */ 2192 0x00, /* Port 49 ( N/A) */ 2193 0x48, /* Port 50 ( xe3) ExtBus=2 Addr=0x08 */ 2194 0x00, /* Port 51 ( N/A) */ 2195 0x00, /* Port 52 ( N/A) */ 2196 0x00, /* Port 53 ( N/A) */ 2197 }; 2198 2199 static const uint16 _soc_phy_addr_bcm56639[] = { 2200 0x00, /* Port 0 (cmic) N/A */ 2201 0x1d, /* Port 1 ( ge0) ExtBus=0 Addr=0x1d */ 2202 0x01, /* Port 2 ( ge1) ExtBus=0 Addr=0x01 */ 2203 0x02, /* Port 3 ( ge2) ExtBus=0 Addr=0x02 */ 2204 0x03, /* Port 4 ( ge3) ExtBus=0 Addr=0x03 */ 2205 0x04, /* Port 5 ( ge4) ExtBus=0 Addr=0x04 */ 2206 0x05, /* Port 6 ( ge5) ExtBus=0 Addr=0x05 */ 2207 0x06, /* Port 7 ( ge6) ExtBus=0 Addr=0x06 */ 2208 0x07, /* Port 8 ( ge7) ExtBus=0 Addr=0x07 */ 2209 0x08, /* Port 9 ( ge8) ExtBus=0 Addr=0x08 */ 2210 0x09, /* Port 10 ( ge9) ExtBus=0 Addr=0x09 */ 2211 0x0a, /* Port 11 (ge10) ExtBus=0 Addr=0x0a */ 2212 0x0b, /* Port 12 (ge11) ExtBus=0 Addr=0x0b */ 2213 0x0c, /* Port 13 (ge12) ExtBus=0 Addr=0x0c */ 2214 0x0d, /* Port 14 (ge13) ExtBus=0 Addr=0x0d */ 2215 0x0e, /* Port 15 (ge14) ExtBus=0 Addr=0x0e */ 2216 0x0f, /* Port 16 (ge15) ExtBus=0 Addr=0x0f */ 2217 0x10, /* Port 17 (ge16) ExtBus=0 Addr=0x10 */ 2218 0x11, /* Port 18 (ge17) ExtBus=0 Addr=0x11 */ 2219 0x12, /* Port 19 (ge18) ExtBus=0 Addr=0x12 */ 2220 0x13, /* Port 20 (ge19) ExtBus=0 Addr=0x13 */ 2221 0x14, /* Port 21 (ge20) ExtBus=0 Addr=0x14 */ 2222 0x15, /* Port 22 (ge21) ExtBus=0 Addr=0x15 */ 2223 0x16, /* Port 23 (ge22) ExtBus=0 Addr=0x16 */ 2224 0x17, /* Port 24 (ge23) ExtBus=0 Addr=0x17 */ 2225 0x18, /* Port 25 (ge24) ExtBus=0 Addr=0x18 */ 2226 0x45, /* Port 26 ( hg0) ExtBus=2 Addr=0x05 */ 2227 0x46, /* Port 27 ( hg1) ExtBus=2 Addr=0x06 */ 2228 0x47, /* Port 28 ( hg2) ExtBus=2 Addr=0x07 */ 2229 0x48, /* Port 29 ( hg3) ExtBus=2 Addr=0x08 */ 2230 0x41, /* Port 30 ( xe0) ExtBus=2 Addr=0x01 */ 2231 0x00, /* Port 31 ( N/A) */ 2232 0x00, /* Port 32 ( N/A) */ 2233 0x00, /* Port 33 ( N/A) */ 2234 0x00, /* Port 34 ( N/A) */ 2235 0x00, /* Port 35 ( N/A) */ 2236 0x00, /* Port 36 ( N/A) */ 2237 0x00, /* Port 37 ( N/A) */ 2238 0x42, /* Port 38 ( xe1) ExtBus=2 Addr=0x02 */ 2239 0x00, /* Port 39 ( N/A) */ 2240 0x00, /* Port 40 ( N/A) */ 2241 0x00, /* Port 41 ( N/A) */ 2242 0x43, /* Port 42 ( xe2) ExtBus=2 Addr=0x03 */ 2243 0x00, /* Port 43 ( N/A) */ 2244 0x00, /* Port 44 ( N/A) */ 2245 0x00, /* Port 45 ( N/A) */ 2246 0x19, /* Port 46 (ge25) ExtBus=0 Addr=0x19 */ 2247 0x1a, /* Port 47 (ge26) ExtBus=0 Addr=0x1a */ 2248 0x1b, /* Port 48 (ge27) ExtBus=0 Addr=0x1b */ 2249 0x1c, /* Port 49 (ge28) ExtBus=0 Addr=0x1c */ 2250 0x44, /* Port 50 ( xe3) ExtBus=2 Addr=0x04 */ 2251 0x00, /* Port 51 ( N/A) */ 2252 0x00, /* Port 52 ( N/A) */ 2253 0x00, /* Port 53 ( N/A) */ 2254 }; 2255 2256 static const uint16 _soc_phy_addr_bcm56521[] = { 2257 0x00, /* Port 0 (cmic) N/A */ 2258 0x00, /* Port 1 ( N/A) */ 2259 0x01, /* Port 2 ( ge0) ExtBus=0 Addr=0x01 */ 2260 0x02, /* Port 3 ( ge1) ExtBus=0 Addr=0x02 */ 2261 0x03, /* Port 4 ( ge2) ExtBus=0 Addr=0x03 */ 2262 0x04, /* Port 5 ( ge3) ExtBus=0 Addr=0x04 */ 2263 0x05, /* Port 6 ( ge4) ExtBus=0 Addr=0x05 */ 2264 0x06, /* Port 7 ( ge5) ExtBus=0 Addr=0x06 */ 2265 0x07, /* Port 8 ( ge6) ExtBus=0 Addr=0x07 */ 2266 0x08, /* Port 9 ( ge7) ExtBus=0 Addr=0x08 */ 2267 0x09, /* Port 10 ( ge8) ExtBus=0 Addr=0x09 */ 2268 0x0a, /* Port 11 ( ge9) ExtBus=0 Addr=0x0a */ 2269 0x0b, /* Port 12 (ge10) ExtBus=0 Addr=0x0b */ 2270 0x0c, /* Port 13 (ge11) ExtBus=0 Addr=0x0c */ 2271 0x0d, /* Port 14 (ge12) ExtBus=0 Addr=0x0d */ 2272 0x0e, /* Port 15 (ge13) ExtBus=0 Addr=0x0e */ 2273 0x0f, /* Port 16 (ge14) ExtBus=0 Addr=0x0f */ 2274 0x10, /* Port 17 (ge15) ExtBus=0 Addr=0x10 */ 2275 0x11, /* Port 18 (ge16) ExtBus=0 Addr=0x11 */ 2276 0x12, /* Port 19 (ge17) ExtBus=0 Addr=0x12 */ 2277 0x13, /* Port 20 (ge18) ExtBus=0 Addr=0x13 */ 2278 0x14, /* Port 21 (ge19) ExtBus=0 Addr=0x14 */ 2279 0x15, /* Port 22 (ge20) ExtBus=0 Addr=0x15 */ 2280 0x16, /* Port 23 (ge21) ExtBus=0 Addr=0x16 */ 2281 0x17, /* Port 24 (ge22) ExtBus=0 Addr=0x17 */ 2282 0x18, /* Port 25 (ge23) ExtBus=0 Addr=0x18 */ 2283 0x41, /* Port 26 ( hg0) ExtBus=2 Addr=0x01 */ 2284 0x42, /* Port 27 ( hg1) ExtBus=2 Addr=0x02 */ 2285 0x43, /* Port 28 ( hg2) ExtBus=2 Addr=0x03 */ 2286 0x44, /* Port 29 ( hg3) ExtBus=2 Addr=0x04 */ 2287 0x00, /* Port 30 ( N/A) */ 2288 0x00, /* Port 31 ( N/A) */ 2289 0x00, /* Port 32 ( N/A) */ 2290 0x00, /* Port 33 ( N/A) */ 2291 0x00, /* Port 34 ( N/A) */ 2292 0x00, /* Port 35 ( N/A) */ 2293 0x00, /* Port 36 ( N/A) */ 2294 0x00, /* Port 37 ( N/A) */ 2295 0x00, /* Port 38 ( N/A) */ 2296 0x00, /* Port 39 ( N/A) */ 2297 0x00, /* Port 40 ( N/A) */ 2298 0x00, /* Port 41 ( N/A) */ 2299 0x00, /* Port 42 ( N/A) */ 2300 0x00, /* Port 43 ( N/A) */ 2301 0x00, /* Port 44 ( N/A) */ 2302 0x00, /* Port 45 ( N/A) */ 2303 0x00, /* Port 46 ( N/A) */ 2304 0x00, /* Port 47 ( N/A) */ 2305 0x00, /* Port 48 ( N/A) */ 2306 0x00, /* Port 49 ( N/A) */ 2307 0x00, /* Port 50 ( N/A) */ 2308 0x00, /* Port 51 ( N/A) */ 2309 0x00, /* Port 52 ( N/A) */ 2310 0x00, /* Port 53 ( N/A) */ 2311 }; 2312 2313 static const uint16 _soc_phy_addr_bcm56526[] = { 2314 0x00, /* Port 0 (cmic) N/A */ 2315 0x1d, /* Port 1 ( ge0) ExtBus=0 Addr=0x19 */ 2316 0x01, /* Port 2 ( ge1) ExtBus=0 Addr=0x01 */ 2317 0x02, /* Port 3 ( ge2) ExtBus=0 Addr=0x02 */ 2318 0x03, /* Port 4 ( ge3) ExtBus=0 Addr=0x03 */ 2319 0x04, /* Port 5 ( ge4) ExtBus=0 Addr=0x04 */ 2320 0x05, /* Port 6 ( ge5) ExtBus=0 Addr=0x05 */ 2321 0x06, /* Port 7 ( ge6) ExtBus=0 Addr=0x06 */ 2322 0x07, /* Port 8 ( ge7) ExtBus=0 Addr=0x07 */ 2323 0x08, /* Port 9 ( ge8) ExtBus=0 Addr=0x08 */ 2324 0x0d, /* Port 10 (ge13) ExtBus=0 Addr=0x0d */ 2325 0x0e, /* Port 11 (ge14) ExtBus=0 Addr=0x0e */ 2326 0x0f, /* Port 12 (ge15) ExtBus=0 Addr=0x0f */ 2327 0x10, /* Port 13 (ge16) ExtBus=0 Addr=0x10 */ 2328 0x11, /* Port 14 (ge17) ExtBus=0 Addr=0x11 */ 2329 0x12, /* Port 15 (ge18) ExtBus=0 Addr=0x12 */ 2330 0x13, /* Port 16 (ge19) ExtBus=0 Addr=0x13 */ 2331 0x14, /* Port 17 (ge20) ExtBus=0 Addr=0x14 */ 2332 0x15, /* Port 18 (ge21) ExtBus=0 Addr=0x15 */ 2333 0x16, /* Port 19 (ge22) ExtBus=0 Addr=0x16 */ 2334 0x17, /* Port 20 (ge23) ExtBus=0 Addr=0x17 */ 2335 0x18, /* Port 21 (ge24) ExtBus=0 Addr=0x18 */ 2336 0x19, /* Port 22 (ge25) ExtBus=0 Addr=0x19 */ 2337 0x1a, /* Port 23 (ge26) ExtBus=0 Addr=0x1a */ 2338 0x1b, /* Port 24 (ge27) ExtBus=0 Addr=0x1b */ 2339 0x1c, /* Port 25 (ge28) ExtBus=0 Addr=0x1c */ 2340 0x41, /* Port 26 ( hg0) ExtBus=2 Addr=0x01 */ 2341 0x42, /* Port 27 ( hg1) ExtBus=2 Addr=0x02 */ 2342 0x43, /* Port 28 ( hg2) ExtBus=2 Addr=0x03 */ 2343 0x44, /* Port 29 ( hg3) ExtBus=2 Addr=0x04 */ 2344 0x00, /* Port 30 ( N/A) */ 2345 0x00, /* Port 31 ( N/A) */ 2346 0x00, /* Port 32 ( N/A) */ 2347 0x00, /* Port 33 ( N/A) */ 2348 0x00, /* Port 34 ( N/A) */ 2349 0x00, /* Port 35 ( N/A) */ 2350 0x00, /* Port 36 ( N/A) */ 2351 0x00, /* Port 37 ( N/A) */ 2352 0x09, /* Port 38 ( ge9) ExtBus=0 Addr=0x09 */ 2353 0x0a, /* Port 39 (ge10) ExtBus=0 Addr=0x0a */ 2354 0x0b, /* Port 40 (ge11) ExtBus=0 Addr=0x0b */ 2355 0x0c, /* Port 41 (ge12) ExtBus=0 Addr=0x0c */ 2356 0x00, /* Port 42 ( N/A) */ 2357 0x00, /* Port 43 ( N/A) */ 2358 0x00, /* Port 44 ( N/A) */ 2359 0x00, /* Port 45 ( N/A) */ 2360 0x45, /* Port 46 ( xe0) ExtBus=2 Addr=0x05 */ 2361 0x00, /* Port 47 ( N/A) */ 2362 0x00, /* Port 48 ( N/A) */ 2363 0x00, /* Port 49 ( N/A) */ 2364 0x46, /* Port 50 ( xe1) ExtBus=2 Addr=0x06 */ 2365 0x00, /* Port 51 ( N/A) */ 2366 0x00, /* Port 52 ( N/A) */ 2367 0x00, /* Port 53 ( N/A) */ 2368 }; 2369 2370 static const uint16 _soc_phy_addr_bcm56685[] = { 2371 0x00, /* Port 0 (cmic) N/A */ 2372 0x39, /* Port 1 ( ge0) ExtBus=1 Addr=0x19 */ 2373 0x00, /* Port 2 ( N/A) */ 2374 0x00, /* Port 3 ( N/A) */ 2375 0x00, /* Port 4 ( N/A) */ 2376 0x00, /* Port 5 ( N/A) */ 2377 0x00, /* Port 6 ( N/A) */ 2378 0x00, /* Port 7 ( N/A) */ 2379 0x00, /* Port 8 ( N/A) */ 2380 0x00, /* Port 9 ( N/A) */ 2381 0x00, /* Port 10 ( N/A) */ 2382 0x00, /* Port 11 ( N/A) */ 2383 0x00, /* Port 12 ( N/A) */ 2384 0x00, /* Port 13 ( N/A) */ 2385 0x00, /* Port 14 ( N/A) */ 2386 0x00, /* Port 15 ( N/A) */ 2387 0x00, /* Port 16 ( N/A) */ 2388 0x00, /* Port 17 ( N/A) */ 2389 0x00, /* Port 18 ( N/A) */ 2390 0x00, /* Port 19 ( N/A) */ 2391 0x00, /* Port 20 ( N/A) */ 2392 0x00, /* Port 21 ( N/A) */ 2393 0x00, /* Port 22 ( N/A) */ 2394 0x00, /* Port 23 ( N/A) */ 2395 0x00, /* Port 24 ( N/A) */ 2396 0x00, /* Port 25 ( N/A) */ 2397 0x41, /* Port 26 ( hg0) ExtBus=2 Addr=0x01 */ 2398 0x42, /* Port 27 ( hg1) ExtBus=2 Addr=0x02 */ 2399 0x43, /* Port 28 ( hg2) ExtBus=2 Addr=0x03 */ 2400 0x44, /* Port 29 ( hg3) ExtBus=2 Addr=0x04 */ 2401 0x01, /* Port 30 ( ge1) ExtBus=0 Addr=0x01 */ 2402 0x02, /* Port 31 ( ge2) ExtBus=0 Addr=0x02 */ 2403 0x03, /* Port 32 ( ge3) ExtBus=0 Addr=0x03 */ 2404 0x04, /* Port 33 ( ge4) ExtBus=0 Addr=0x04 */ 2405 0x05, /* Port 34 ( ge5) ExtBus=0 Addr=0x05 */ 2406 0x06, /* Port 35 ( ge6) ExtBus=0 Addr=0x06 */ 2407 0x07, /* Port 36 ( ge7) ExtBus=0 Addr=0x07 */ 2408 0x08, /* Port 37 ( ge8) ExtBus=0 Addr=0x08 */ 2409 0x09, /* Port 38 ( ge9) ExtBus=0 Addr=0x09 */ 2410 0x0a, /* Port 39 (ge10) ExtBus=0 Addr=0x0a */ 2411 0x0b, /* Port 40 (ge11) ExtBus=0 Addr=0x0b */ 2412 0x0c, /* Port 41 (ge12) ExtBus=0 Addr=0x0c */ 2413 0x0d, /* Port 42 (ge13) ExtBus=0 Addr=0x0d */ 2414 0x0e, /* Port 43 (ge14) ExtBus=0 Addr=0x0e */ 2415 0x0f, /* Port 44 (ge15) ExtBus=0 Addr=0x0f */ 2416 0x10, /* Port 45 (ge16) ExtBus=0 Addr=0x10 */ 2417 0x11, /* Port 46 (ge17) ExtBus=0 Addr=0x11 */ 2418 0x12, /* Port 47 (ge18) ExtBus=0 Addr=0x12 */ 2419 0x13, /* Port 48 (ge19) ExtBus=0 Addr=0x13 */ 2420 0x14, /* Port 49 (ge20) ExtBus=0 Addr=0x14 */ 2421 0x15, /* Port 50 (ge21) ExtBus=0 Addr=0x15 */ 2422 0x16, /* Port 51 (ge22) ExtBus=0 Addr=0x16 */ 2423 0x17, /* Port 52 (ge23) ExtBus=0 Addr=0x17 */ 2424 0x18, /* Port 53 (ge24) ExtBus=0 Addr=0x18 */ 2425 }; 2426 2427 uint16 dev_id; 2428 uint8 rev_id; 2429 2430 soc_cm_get_id(unit, &dev_id, &rev_id); 2431 2432 *phy_addr_int = _soc_triumph2_int_phy_addr[port]; 2433 switch (dev_id) { 2434 case BCM56630_DEVICE_ID: 2435 case BCM56520_DEVICE_ID: 2436 case BCM56522_DEVICE_ID: 2437 case BCM56524_DEVICE_ID: 2438 case BCM56534_DEVICE_ID: 2439 *phy_addr = _soc_phy_addr_bcm56630[port]; 2440 break; 2441 case BCM56636_DEVICE_ID: 2442 *phy_addr = _soc_phy_addr_bcm56636[port]; 2443 break; 2444 case BCM56638_DEVICE_ID: 2445 *phy_addr = _soc_phy_addr_bcm56638[port]; 2446 break; 2447 case BCM56639_DEVICE_ID: 2448 *phy_addr = _soc_phy_addr_bcm56639[port]; 2449 break; 2450 case BCM56521_DEVICE_ID: 2451 *phy_addr = _soc_phy_addr_bcm56521[port]; 2452 break; 2453 case BCM56526_DEVICE_ID: 2454 *phy_addr = _soc_phy_addr_bcm56526[port]; 2455 break; 2456 case BCM56685_DEVICE_ID: 2457 case BCM56689_DEVICE_ID: 2458 *phy_addr = _soc_phy_addr_bcm56685[port]; 2459 break; 2460 case BCM56634_DEVICE_ID: 2461 case BCM56538_DEVICE_ID: 2462 default: 2463 *phy_addr = _soc_phy_addr_bcm56634[port]; 2464 break; 2465 } 2466 } 2467 #endif /* BCM_TRIUMPH2_SUPPORT || BCM_APOLLO_SUPPORT || BCM_VALKYRIE2_SUPPORT */ 2468 2469 #ifdef BCM_TRIUMPH_SUPPORT 2470 static void 2471 _triumph_phy_addr_default(int unit, int port, 2472 uint16 *phy_addr, uint16 *phy_addr_int) 2473 { 2474 static const uint16 _soc_triumph_int_phy_addr[] = { 2475 0x00, /* Port 0 (cmic) N/A */ 2476 0x99, /* Port 1 (serdes2:8) IntBus=0 Addr=0x19 */ 2477 0xc1, /* Port 2 (hyperlite0:0) IntBus=2 Addr=0x01 */ 2478 0xc2, /* Port 3 (hyperlite0:1) IntBus=2 Addr=0x02 */ 2479 0xc3, /* Port 4 (hyperlite0:2) IntBus=2 Addr=0x03 */ 2480 0xc4, /* Port 5 (hyperlite0:3) IntBus=2 Addr=0x04 */ 2481 0xc5, /* Port 6 (hyperlite1:0) IntBus=2 Addr=0x05 */ 2482 0xc6, /* Port 7 (hyperlite1:1) IntBus=2 Addr=0x06 */ 2483 0x81, /* Port 8 (serdes0:0) IntBus=0 Addr=0x01 */ 2484 0x82, /* Port 9 (serdes0:1) IntBus=0 Addr=0x02 */ 2485 0x83, /* Port 10 (serdes0:2) IntBus=0 Addr=0x03 */ 2486 0x84, /* Port 11 (serdes0:3) IntBus=0 Addr=0x04 */ 2487 0x85, /* Port 12 (serdes0:4) IntBus=0 Addr=0x05 */ 2488 0x86, /* Port 13 (serdes0:5) IntBus=0 Addr=0x06 */ 2489 0xc9, /* Port 14 (hyperlite2:0) IntBus=2 Addr=0x09 */ 2490 0xca, /* Port 15 (hyperlite2:1) IntBus=2 Addr=0x0a */ 2491 0xcb, /* Port 16 (hyperlite2:2) IntBus=2 Addr=0x0b */ 2492 0xcc, /* Port 17 (hyperlite2:3) IntBus=2 Addr=0x0c */ 2493 0xc7, /* Port 18 (hyperlite1:2) IntBus=2 Addr=0x07 */ 2494 0xc8, /* Port 19 (hyperlite1:3) IntBus=2 Addr=0x08 */ 2495 0x87, /* Port 20 (serdes0:6) IntBus=0 Addr=0x07 */ 2496 0x88, /* Port 21 (serdes0:7) IntBus=0 Addr=0x08 */ 2497 0x89, /* Port 22 (serdes1:0) IntBus=0 Addr=0x09 */ 2498 0x8a, /* Port 23 (serdes1:1) IntBus=0 Addr=0x0a */ 2499 0x8b, /* Port 24 (serdes1:2) IntBus=0 Addr=0x0b */ 2500 0x8c, /* Port 25 (serdes1:3) IntBus=0 Addr=0x0c */ 2501 0xcd, /* Port 26 (hyperlite3:0) IntBus=2 Addr=0x0d */ 2502 0xd5, /* Port 27 (hyperlite5:0) IntBus=2 Addr=0x15 */ 2503 0xd9, /* Port 28 (unicore0) IntBus=2 Addr=0x19 */ 2504 0xda, /* Port 29 (unicore1) IntBus=2 Addr=0x1a */ 2505 0xdb, /* Port 30 (unicore2) IntBus=2 Addr=0x1b */ 2506 0xdc, /* Port 31 (unicore3) IntBus=2 Addr=0x1c */ 2507 0xce, /* Port 32 (hyperlite3:1) IntBus=2 Addr=0x0e */ 2508 0xcf, /* Port 33 (hyperlite3:2) IntBus=2 Addr=0x0f */ 2509 0xd0, /* Port 34 (hyperlite3:3) IntBus=2 Addr=0x10 */ 2510 0xd1, /* Port 35 (hyperlite4:0) IntBus=2 Addr=0x11 */ 2511 0xd2, /* Port 36 (hyperlite4:1) IntBus=2 Addr=0x12 */ 2512 0x8d, /* Port 37 (serdes1:4) IntBus=0 Addr=0x0d */ 2513 0x8e, /* Port 38 (serdes1:5) IntBus=0 Addr=0x0e */ 2514 0x8f, /* Port 39 (serdes1:6) IntBus=0 Addr=0x0f */ 2515 0x90, /* Port 40 (serdes1:7) IntBus=0 Addr=0x10 */ 2516 0x91, /* Port 41 (serdes2:0) IntBus=0 Addr=0x11 */ 2517 0x92, /* Port 42 (serdes2:1) IntBus=0 Addr=0x12 */ 2518 0xd6, /* Port 43 (hyperlite5:1) IntBus=2 Addr=0x16 */ 2519 0xd7, /* Port 44 (hyperlite5:2) IntBus=2 Addr=0x17 */ 2520 0xd8, /* Port 45 (hyperlite5:3) IntBus=2 Addr=0x18 */ 2521 0xd3, /* Port 46 (hyperlite4:2) IntBus=2 Addr=0x13 */ 2522 0xd4, /* Port 47 (hyperlite4:3) IntBus=2 Addr=0x14 */ 2523 0x93, /* Port 48 (serdes2:2) IntBus=0 Addr=0x13 */ 2524 0x94, /* Port 49 (serdes2:3) IntBus=0 Addr=0x14 */ 2525 0x95, /* Port 50 (serdes2:4) IntBus=0 Addr=0x15 */ 2526 0x96, /* Port 51 (serdes2:5) IntBus=0 Addr=0x16 */ 2527 0x97, /* Port 52 (serdes2:6) IntBus=0 Addr=0x17 */ 2528 0x98, /* Port 53 (serdes2:7) IntBus=0 Addr=0x18 */ 2529 }; 2530 2531 static const uint16 _soc_phy_addr_bcm56624[] = { 2532 0x00, /* Port 0 (cmic) N/A */ 2533 0x19, /* Port 1 ( ge0) ExtBus=1 Addr=0x19 */ 2534 0x01, /* Port 2 ( ge1) ExtBus=0 Addr=0x01 */ 2535 0x02, /* Port 3 ( ge2) ExtBus=0 Addr=0x02 */ 2536 0x03, /* Port 4 ( ge3) ExtBus=0 Addr=0x03 */ 2537 0x04, /* Port 5 ( ge4) ExtBus=0 Addr=0x04 */ 2538 0x05, /* Port 6 ( ge5) ExtBus=0 Addr=0x05 */ 2539 0x06, /* Port 7 ( ge6) ExtBus=0 Addr=0x06 */ 2540 0x09, /* Port 8 ( ge7) ExtBus=0 Addr=0x09 */ 2541 0x0a, /* Port 9 ( ge8) ExtBus=0 Addr=0x0a */ 2542 0x0b, /* Port 10 ( ge9) ExtBus=0 Addr=0x0b */ 2543 0x0c, /* Port 11 (ge10) ExtBus=0 Addr=0x0c */ 2544 0x0d, /* Port 12 (ge11) ExtBus=0 Addr=0x0d */ 2545 0x0e, /* Port 13 (ge12) ExtBus=0 Addr=0x0e */ 2546 0x11, /* Port 14 (ge13) ExtBus=0 Addr=0x11 */ 2547 0x12, /* Port 15 (ge14) ExtBus=0 Addr=0x12 */ 2548 0x13, /* Port 16 (ge15) ExtBus=0 Addr=0x13 */ 2549 0x14, /* Port 17 (ge16) ExtBus=0 Addr=0x14 */ 2550 0x07, /* Port 18 (ge17) ExtBus=0 Addr=0x07 */ 2551 0x08, /* Port 19 (ge18) ExtBus=0 Addr=0x08 */ 2552 0x0f, /* Port 20 (ge19) ExtBus=0 Addr=0x0f */ 2553 0x10, /* Port 21 (ge20) ExtBus=0 Addr=0x10 */ 2554 0x15, /* Port 22 (ge21) ExtBus=0 Addr=0x15 */ 2555 0x16, /* Port 23 (ge22) ExtBus=0 Addr=0x16 */ 2556 0x17, /* Port 24 (ge23) ExtBus=0 Addr=0x17 */ 2557 0x18, /* Port 25 (ge24) ExtBus=0 Addr=0x18 */ 2558 0x25, /* Port 26 (ge25) ExtBus=1 Addr=0x05 */ 2559 0x35, /* Port 27 (ge26) ExtBus=1 Addr=0x15 */ 2560 0x41, /* Port 28 ( xg0) ExtBus=2 Addr=0x01 */ 2561 0x42, /* Port 29 ( xg1) ExtBus=2 Addr=0x02 */ 2562 0x43, /* Port 30 ( xg2) ExtBus=2 Addr=0x03 */ 2563 0x44, /* Port 31 ( xg3) ExtBus=2 Addr=0x04 */ 2564 0x26, /* Port 32 (ge27) ExtBus=1 Addr=0x06 */ 2565 0x27, /* Port 33 (ge28) ExtBus=1 Addr=0x07 */ 2566 0x28, /* Port 34 (ge29) ExtBus=1 Addr=0x08 */ 2567 0x31, /* Port 35 (ge30) ExtBus=1 Addr=0x11 */ 2568 0x32, /* Port 36 (ge31) ExtBus=1 Addr=0x12 */ 2569 0x21, /* Port 37 (ge32) ExtBus=1 Addr=0x01 */ 2570 0x22, /* Port 38 (ge33) ExtBus=1 Addr=0x02 */ 2571 0x23, /* Port 39 (ge34) ExtBus=1 Addr=0x03 */ 2572 0x24, /* Port 40 (ge35) ExtBus=1 Addr=0x04 */ 2573 0x29, /* Port 41 (ge36) ExtBus=1 Addr=0x09 */ 2574 0x2a, /* Port 42 (ge37) ExtBus=1 Addr=0x0a */ 2575 0x36, /* Port 43 (ge38) ExtBus=1 Addr=0x16 */ 2576 0x37, /* Port 44 (ge39) ExtBus=1 Addr=0x17 */ 2577 0x38, /* Port 45 (ge40) ExtBus=1 Addr=0x18 */ 2578 0x33, /* Port 46 (ge41) ExtBus=1 Addr=0x13 */ 2579 0x34, /* Port 47 (ge42) ExtBus=1 Addr=0x14 */ 2580 0x2b, /* Port 48 (ge43) ExtBus=1 Addr=0x0b */ 2581 0x2c, /* Port 49 (ge44) ExtBus=1 Addr=0x0c */ 2582 0x2d, /* Port 50 (ge45) ExtBus=1 Addr=0x0d */ 2583 0x2e, /* Port 51 (ge46) ExtBus=1 Addr=0x0e */ 2584 0x2f, /* Port 52 (ge47) ExtBus=1 Addr=0x0f */ 2585 0x30, /* Port 53 (ge48) ExtBus=1 Addr=0x10 */ 2586 }; 2587 2588 static const uint16 _soc_phy_addr_bcm56626[] = { 2589 0x00, /* Port 0 (cmic) N/A */ 2590 0x19, /* Port 1 ( ge0) ExtBus=1 Addr=0x19 */ 2591 0x01, /* Port 2 ( ge1) ExtBus=0 Addr=0x01 */ 2592 0x02, /* Port 3 ( ge2) ExtBus=0 Addr=0x02 */ 2593 0x03, /* Port 4 ( ge3) ExtBus=0 Addr=0x03 */ 2594 0x04, /* Port 5 ( ge4) ExtBus=0 Addr=0x04 */ 2595 0x05, /* Port 6 ( ge5) ExtBus=0 Addr=0x05 */ 2596 0x06, /* Port 7 ( ge6) ExtBus=0 Addr=0x06 */ 2597 0x09, /* Port 8 ( ge7) ExtBus=0 Addr=0x09 */ 2598 0x0a, /* Port 9 ( ge8) ExtBus=0 Addr=0x0a */ 2599 0x0b, /* Port 10 ( ge9) ExtBus=0 Addr=0x0b */ 2600 0x0c, /* Port 11 (ge10) ExtBus=0 Addr=0x0c */ 2601 0x0d, /* Port 12 (ge11) ExtBus=0 Addr=0x0d */ 2602 0x0e, /* Port 13 (ge12) ExtBus=0 Addr=0x0e */ 2603 0x11, /* Port 14 (ge13) ExtBus=0 Addr=0x11 */ 2604 0x12, /* Port 15 (ge14) ExtBus=0 Addr=0x12 */ 2605 0x13, /* Port 16 (ge15) ExtBus=0 Addr=0x13 */ 2606 0x14, /* Port 17 (ge16) ExtBus=0 Addr=0x14 */ 2607 0x07, /* Port 18 (ge17) ExtBus=0 Addr=0x07 */ 2608 0x08, /* Port 19 (ge18) ExtBus=0 Addr=0x08 */ 2609 0x0f, /* Port 20 (ge19) ExtBus=0 Addr=0x0f */ 2610 0x10, /* Port 21 (ge20) ExtBus=0 Addr=0x10 */ 2611 0x15, /* Port 22 (ge21) ExtBus=0 Addr=0x15 */ 2612 0x16, /* Port 23 (ge22) ExtBus=0 Addr=0x16 */ 2613 0x17, /* Port 24 (ge23) ExtBus=0 Addr=0x17 */ 2614 0x18, /* Port 25 (ge24) ExtBus=0 Addr=0x18 */ 2615 0x45, /* Port 26 ( xe0) ExtBus=2 Addr=0x05 */ 2616 0x46, /* Port 27 ( xe1) ExtBus=2 Addr=0x06 */ 2617 0x41, /* Port 28 ( hg0) ExtBus=2 Addr=0x01 */ 2618 0x42, /* Port 29 ( hg1) ExtBus=2 Addr=0x02 */ 2619 0x43, /* Port 30 ( hg2) ExtBus=2 Addr=0x03 */ 2620 0x44, /* Port 31 ( hg3) ExtBus=2 Addr=0x04 */ 2621 }; 2622 2623 static const uint16 _soc_phy_addr_bcm56628[] = { 2624 0x00, /* Port 0 (cmic) N/A */ 2625 0x19, /* Port 1 ( ge0) ExtBus=1 Addr=0x01 */ 2626 0x45, /* Port 2 ( xe0) ExtBus=2 Addr=0x05 */ 2627 0x00, /* Port 3 ( N/A) */ 2628 0x00, /* Port 4 ( N/A) */ 2629 0x00, /* Port 5 ( N/A) */ 2630 0x00, /* Port 6 ( N/A) */ 2631 0x00, /* Port 7 ( N/A) */ 2632 0x00, /* Port 8 ( N/A) */ 2633 0x00, /* Port 9 ( N/A) */ 2634 0x00, /* Port 10 ( N/A) */ 2635 0x00, /* Port 11 ( N/A) */ 2636 0x00, /* Port 12 ( N/A) */ 2637 0x00, /* Port 13 ( N/A) */ 2638 0x46, /* Port 14 ( xe1) ExtBus=2 Addr=0x06 */ 2639 0x00, /* Port 15 ( N/A) */ 2640 0x00, /* Port 16 ( N/A) */ 2641 0x00, /* Port 17 ( N/A) */ 2642 0x00, /* Port 18 ( N/A) */ 2643 0x00, /* Port 19 ( N/A) */ 2644 0x00, /* Port 20 ( N/A) */ 2645 0x00, /* Port 21 ( N/A) */ 2646 0x00, /* Port 22 ( N/A) */ 2647 0x00, /* Port 23 ( N/A) */ 2648 0x00, /* Port 24 ( N/A) */ 2649 0x00, /* Port 25 ( N/A) */ 2650 0x47, /* Port 26 ( xe2) ExtBus=2 Addr=0x07 */ 2651 0x48, /* Port 27 ( xe3) ExtBus=2 Addr=0x08 */ 2652 0x41, /* Port 28 ( hg0) ExtBus=2 Addr=0x01 */ 2653 0x42, /* Port 29 ( hg1) ExtBus=2 Addr=0x02 */ 2654 0x43, /* Port 30 ( hg2) ExtBus=2 Addr=0x03 */ 2655 0x44, /* Port 31 ( hg3) ExtBus=2 Addr=0x04 */ 2656 }; 2657 2658 static const uint16 _soc_phy_addr_bcm56629[] = { 2659 0x00, /* Port 0 (cmic) N/A */ 2660 0x19, /* Port 1 ( ge0) ExtBus=0 Addr=0x19 */ 2661 0x41, /* Port 2 ( xe0) ExtBus=2 Addr=0x01 */ 2662 0x00, /* Port 3 ( N/A) */ 2663 0x00, /* Port 4 ( N/A) */ 2664 0x00, /* Port 5 ( N/A) */ 2665 0x00, /* Port 6 ( N/A) */ 2666 0x00, /* Port 7 ( N/A) */ 2667 0x01, /* Port 8 ( ge1) ExtBus=0 Addr=0x01 */ 2668 0x02, /* Port 9 ( ge2) ExtBus=0 Addr=0x02 */ 2669 0x03, /* Port 10 ( ge3) ExtBus=0 Addr=0x03 */ 2670 0x04, /* Port 11 ( ge4) ExtBus=0 Addr=0x04 */ 2671 0x05, /* Port 12 ( ge5) ExtBus=0 Addr=0x05 */ 2672 0x06, /* Port 13 ( ge6) ExtBus=0 Addr=0x06 */ 2673 0x42, /* Port 14 ( xe1) ExtBus=2 Addr=0x02 */ 2674 0x00, /* Port 15 ( N/A) */ 2675 0x00, /* Port 16 ( N/A) */ 2676 0x00, /* Port 17 ( N/A) */ 2677 0x00, /* Port 18 ( N/A) */ 2678 0x00, /* Port 19 ( N/A) */ 2679 0x07, /* Port 20 ( ge7) ExtBus=0 Addr=0x07 */ 2680 0x08, /* Port 21 ( ge8) ExtBus=0 Addr=0x08 */ 2681 0x09, /* Port 22 ( ge9) ExtBus=0 Addr=0x09 */ 2682 0x0a, /* Port 23 (ge10) ExtBus=0 Addr=0x0a */ 2683 0x0b, /* Port 24 (ge11) ExtBus=0 Addr=0x0b */ 2684 0x0c, /* Port 25 (ge12) ExtBus=0 Addr=0x0c */ 2685 0x43, /* Port 26 ( xe2) ExtBus=2 Addr=0x03 */ 2686 0x44, /* Port 27 ( xe3) ExtBus=2 Addr=0x04 */ 2687 0x45, /* Port 28 ( hg0) ExtBus=2 Addr=0x05 */ 2688 0x46, /* Port 29 ( hg1) ExtBus=2 Addr=0x06 */ 2689 0x47, /* Port 30 ( hg2) ExtBus=2 Addr=0x07 */ 2690 0x48, /* Port 31 ( hg3) ExtBus=2 Addr=0x08 */ 2691 0x00, /* Port 32 ( N/A) */ 2692 0x00, /* Port 33 ( N/A) */ 2693 0x00, /* Port 34 ( N/A) */ 2694 0x00, /* Port 35 ( N/A) */ 2695 0x00, /* Port 36 ( N/A) */ 2696 0x0d, /* Port 37 (ge13) ExtBus=0 Addr=0x0d */ 2697 0x0e, /* Port 38 (ge14) ExtBus=0 Addr=0x0e */ 2698 0x0f, /* Port 39 (ge15) ExtBus=0 Addr=0x0f */ 2699 0x10, /* Port 40 (ge16) ExtBus=0 Addr=0x10 */ 2700 0x11, /* Port 41 (ge17) ExtBus=0 Addr=0x11 */ 2701 0x12, /* Port 42 (ge18) ExtBus=0 Addr=0x12 */ 2702 0x00, /* Port 43 ( N/A) */ 2703 0x00, /* Port 44 ( N/A) */ 2704 0x00, /* Port 45 ( N/A) */ 2705 0x00, /* Port 46 ( N/A) */ 2706 0x00, /* Port 47 ( N/A) */ 2707 0x13, /* Port 48 (ge19) ExtBus=0 Addr=0x13 */ 2708 0x14, /* Port 49 (ge20) ExtBus=0 Addr=0x14 */ 2709 0x15, /* Port 50 (ge21) ExtBus=0 Addr=0x15 */ 2710 0x16, /* Port 51 (ge22) ExtBus=0 Addr=0x16 */ 2711 0x17, /* Port 52 (ge23) ExtBus=0 Addr=0x17 */ 2712 0x18, /* Port 53 (ge24) ExtBus=0 Addr=0x18 */ 2713 }; 2714 2715 uint16 dev_id; 2716 uint8 rev_id; 2717 2718 soc_cm_get_id(unit, &dev_id, &rev_id); 2719 2720 *phy_addr_int = _soc_triumph_int_phy_addr[port]; 2721 switch (dev_id) { 2722 case BCM56626_DEVICE_ID: 2723 *phy_addr = _soc_phy_addr_bcm56626[port]; 2724 break; 2725 case BCM56628_DEVICE_ID: 2726 *phy_addr = _soc_phy_addr_bcm56628[port]; 2727 break; 2728 case BCM56629_DEVICE_ID: 2729 if (soc_feature(unit, soc_feature_xgport_one_xe_six_ge)) { 2730 if (soc_property_get(unit, spn_BCM56629_40GE, 0)) { 2731 *phy_addr = _soc_phy_addr_bcm56624[port]; 2732 } else { 2733 *phy_addr = _soc_phy_addr_bcm56629[port]; 2734 } 2735 } else { 2736 *phy_addr = _soc_phy_addr_bcm56626[port]; 2737 } 2738 break; 2739 case BCM56624_DEVICE_ID: 2740 default: 2741 *phy_addr = _soc_phy_addr_bcm56624[port]; 2742 break; 2743 } 2744 } 2745 #endif /* BCM_TRIUMPH_SUPPORT */ 2746 2747 #ifdef BCM_VALKYRIE_SUPPORT 2748 static void 2749 _valkyrie_phy_addr_default(int unit, int port, 2750 uint16 *phy_addr, uint16 *phy_addr_int) 2751 { 2752 static const uint16 _soc_valkyrie_int_phy_addr[] = { 2753 0x00, /* Port 0 (cmic) N/A */ 2754 0x99, /* Port 1 (serdes2:8) IntBus=0 Addr=0x19 */ 2755 0xc1, /* Port 2 (hyperlite0:0) IntBus=2 Addr=0x01 */ 2756 0xc2, /* Port 3 (hyperlite0:1) IntBus=2 Addr=0x02 */ 2757 0xc3, /* Port 4 (hyperlite0:2) IntBus=2 Addr=0x03 */ 2758 0xc4, /* Port 5 (hyperlite0:3) IntBus=2 Addr=0x04 */ 2759 0xc5, /* Port 6 (hyperlite1:0) IntBus=2 Addr=0x05 */ 2760 0xc6, /* Port 7 (hyperlite1:1) IntBus=2 Addr=0x06 */ 2761 0x81, /* Port 8 (N/A) */ 2762 0x82, /* Port 9 (N/A) */ 2763 0x83, /* Port 10 (N/A) */ 2764 0x84, /* Port 11 (N/A) */ 2765 0x85, /* Port 12 (N/A) */ 2766 0x86, /* Port 13 (N/A) */ 2767 0xc9, /* Port 14 (hyperlite2:0) IntBus=2 Addr=0x09 */ 2768 0xca, /* Port 15 (hyperlite2:1) IntBus=2 Addr=0x0a */ 2769 0xcb, /* Port 16 (hyperlite2:2) IntBus=2 Addr=0x0b */ 2770 0xcc, /* Port 17 (hyperlite2:3) IntBus=2 Addr=0x0c */ 2771 0xc7, /* Port 18 (hyperlite1:2) IntBus=2 Addr=0x07 */ 2772 0xc8, /* Port 19 (hyperlite1:3) IntBus=2 Addr=0x08 */ 2773 0x87, /* Port 20 (N/A) */ 2774 0x88, /* Port 21 (N/A) */ 2775 0x89, /* Port 22 (N/A) */ 2776 0x8a, /* Port 23 (N/A) */ 2777 0x8b, /* Port 24 (N/A) */ 2778 0x8c, /* Port 25 (N/A) */ 2779 0xcd, /* Port 26 (hyperlite3:0) IntBus=2 Addr=0x0d */ 2780 0xd5, /* Port 27 (hyperlite5:0) IntBus=2 Addr=0x15 */ 2781 0xd9, /* Port 28 (unicore0) IntBus=2 Addr=0x19 */ 2782 0xda, /* Port 29 (unicore1) IntBus=2 Addr=0x1a */ 2783 0xdb, /* Port 30 (unicore2) IntBus=2 Addr=0x1b */ 2784 0xdc, /* Port 31 (unicore3) IntBus=2 Addr=0x1c */ 2785 0xce, /* Port 32 (hyperlite3:1) IntBus=2 Addr=0x0e */ 2786 0xcf, /* Port 33 (hyperlite3:2) IntBus=2 Addr=0x0f */ 2787 0xd0, /* Port 34 (hyperlite3:3) IntBus=2 Addr=0x10 */ 2788 0xd1, /* Port 35 (hyperlite4:0) IntBus=2 Addr=0x11 */ 2789 0xd2, /* Port 36 (hyperlite4:1) IntBus=2 Addr=0x12 */ 2790 0x8d, /* Port 37 (N/A) */ 2791 0x8e, /* Port 38 (N/A) */ 2792 0x8f, /* Port 39 (N/A) */ 2793 0x90, /* Port 40 (N/A) */ 2794 0x91, /* Port 41 (N/A) */ 2795 0x92, /* Port 42 (N/A) */ 2796 0xd6, /* Port 43 (hyperlite5:1) IntBus=2 Addr=0x16 */ 2797 0xd7, /* Port 44 (hyperlite5:2) IntBus=2 Addr=0x17 */ 2798 0xd8, /* Port 45 (hyperlite5:3) IntBus=2 Addr=0x18 */ 2799 0xd3, /* Port 46 (hyperlite4:2) IntBus=2 Addr=0x13 */ 2800 0xd4, /* Port 47 (hyperlite4:3) IntBus=2 Addr=0x14 */ 2801 0x93, /* Port 48 (N/A) */ 2802 0x94, /* Port 49 (N/A) */ 2803 0x95, /* Port 50 (N/A) */ 2804 0x96, /* Port 51 (N/A) */ 2805 0x97, /* Port 52 (N/A) */ 2806 0x98, /* Port 53 (N/A) */ 2807 }; 2808 2809 static const uint16 _soc_phy_addr_bcm56680[] = { 2810 0x00, /* Port 0 (cmic) N/A */ 2811 0x39, /* Port 1 ( ge0) ExtBus=1 Addr=0x19 */ 2812 0x01, /* Port 2 ( ge1) ExtBus=0 Addr=0x01 */ 2813 0x02, /* Port 3 ( ge2) ExtBus=0 Addr=0x02 */ 2814 0x03, /* Port 4 ( ge3) ExtBus=0 Addr=0x03 */ 2815 0x04, /* Port 5 ( ge4) ExtBus=0 Addr=0x04 */ 2816 0x05, /* Port 6 ( ge5) ExtBus=0 Addr=0x05 */ 2817 0x06, /* Port 7 ( ge6) ExtBus=0 Addr=0x06 */ 2818 0x00, /* Port 8 ( N/A) */ 2819 0x00, /* Port 9 ( N/A) */ 2820 0x00, /* Port 10 ( N/A) */ 2821 0x00, /* Port 11 ( N/A) */ 2822 0x00, /* Port 12 ( N/A) */ 2823 0x00, /* Port 13 ( N/A) */ 2824 0x07, /* Port 14 ( ge7) ExtBus=0 Addr=0x07 */ 2825 0x08, /* Port 15 ( ge8) ExtBus=0 Addr=0x08 */ 2826 0x09, /* Port 16 ( ge9) ExtBus=0 Addr=0x09 */ 2827 0x0a, /* Port 17 (ge10) ExtBus=0 Addr=0x0a */ 2828 0x0b, /* Port 18 (ge11) ExtBus=0 Addr=0x0b */ 2829 0x0c, /* Port 19 (ge12) ExtBus=0 Addr=0x0c */ 2830 0x00, /* Port 20 ( N/A) */ 2831 0x00, /* Port 21 ( N/A) */ 2832 0x00, /* Port 22 ( N/A) */ 2833 0x00, /* Port 23 ( N/A) */ 2834 0x00, /* Port 24 ( N/A) */ 2835 0x00, /* Port 25 ( N/A) */ 2836 0x0d, /* Port 26 (ge13) ExtBus=0 Addr=0x0d */ 2837 0x13, /* Port 27 (ge19) ExtBus=0 Addr=0x13 */ 2838 0x41, /* Port 28 ( hg0) ExtBus=2 Addr=0x01 */ 2839 0x42, /* Port 29 ( hg1) ExtBus=2 Addr=0x02 */ 2840 0x43, /* Port 30 ( hg2) ExtBus=2 Addr=0x03 */ 2841 0x44, /* Port 31 ( hg3) ExtBus=2 Addr=0x04 */ 2842 0x0e, /* Port 32 (ge14) ExtBus=0 Addr=0x0e */ 2843 0x0f, /* Port 33 (ge15) ExtBus=0 Addr=0x0f */ 2844 0x10, /* Port 34 (ge16) ExtBus=0 Addr=0x10 */ 2845 0x11, /* Port 35 (ge17) ExtBus=0 Addr=0x11 */ 2846 0x12, /* Port 36 (ge18) ExtBus=0 Addr=0x12 */ 2847 0x00, /* Port 37 ( N/A) */ 2848 0x00, /* Port 38 ( N/A) */ 2849 0x00, /* Port 39 ( N/A) */ 2850 0x00, /* Port 40 ( N/A) */ 2851 0x00, /* Port 41 ( N/A) */ 2852 0x00, /* Port 42 ( N/A) */ 2853 0x14, /* Port 43 (ge20) ExtBus=0 Addr=0x14 */ 2854 0x15, /* Port 44 (ge21) ExtBus=0 Addr=0x15 */ 2855 0x16, /* Port 45 (ge22) ExtBus=0 Addr=0x16 */ 2856 0x17, /* Port 46 (ge23) ExtBus=0 Addr=0x17 */ 2857 0x18, /* Port 47 (ge24) ExtBus=0 Addr=0x18 */ 2858 0x00, /* Port 48 ( N/A) */ 2859 0x00, /* Port 49 ( N/A) */ 2860 0x00, /* Port 50 ( N/A) */ 2861 0x00, /* Port 51 ( N/A) */ 2862 0x00, /* Port 52 ( N/A) */ 2863 0x00, /* Port 53 ( N/A) */ 2864 }; 2865 2866 static const uint16 _soc_phy_addr_bcm56684[] = { 2867 0x00, /* Port 0 (cmic) N/A */ 2868 0x00, /* Port 1 ( N/A) */ 2869 0x01, /* Port 2 ( ge0) ExtBus=0 Addr=0x01 */ 2870 0x02, /* Port 3 ( ge1) ExtBus=0 Addr=0x02 */ 2871 0x03, /* Port 4 ( ge2) ExtBus=0 Addr=0x03 */ 2872 0x04, /* Port 5 ( ge3) ExtBus=0 Addr=0x04 */ 2873 0x05, /* Port 6 ( ge4) ExtBus=0 Addr=0x05 */ 2874 0x06, /* Port 7 ( ge5) ExtBus=0 Addr=0x06 */ 2875 0x00, /* Port 8 ( N/A) */ 2876 0x00, /* Port 9 ( N/A) */ 2877 0x00, /* Port 10 ( N/A) */ 2878 0x00, /* Port 11 ( N/A) */ 2879 0x00, /* Port 12 ( N/A) */ 2880 0x00, /* Port 13 ( N/A) */ 2881 0x09, /* Port 14 ( ge6) ExtBus=0 Addr=0x09 */ 2882 0x0a, /* Port 15 ( ge7) ExtBus=0 Addr=0x0a */ 2883 0x0b, /* Port 16 ( ge8) ExtBus=0 Addr=0x0b */ 2884 0x0c, /* Port 17 ( ge9) ExtBus=0 Addr=0x0c */ 2885 0x07, /* Port 18 (ge10) ExtBus=0 Addr=0x07 */ 2886 0x08, /* Port 19 (ge11) ExtBus=0 Addr=0x08 */ 2887 0x00, /* Port 20 ( N/A) */ 2888 0x00, /* Port 21 ( N/A) */ 2889 0x00, /* Port 22 ( N/A) */ 2890 0x00, /* Port 23 ( N/A) */ 2891 0x00, /* Port 24 ( N/A) */ 2892 0x00, /* Port 25 ( N/A) */ 2893 0x0d, /* Port 26 (ge12) ExtBus=0 Addr=0x0d */ 2894 0x15, /* Port 27 (ge13) ExtBus=0 Addr=0x15 */ 2895 0x41, /* Port 28 ( hg0) ExtBus=2 Addr=0x01 */ 2896 0x42, /* Port 29 ( hg1) ExtBus=2 Addr=0x02 */ 2897 0x43, /* Port 30 ( hg2) ExtBus=2 Addr=0x03 */ 2898 0x44, /* Port 31 ( hg3) ExtBus=2 Addr=0x04 */ 2899 0x0e, /* Port 32 (ge14) ExtBus=0 Addr=0x0e */ 2900 0x0f, /* Port 33 (ge15) ExtBus=0 Addr=0x0f */ 2901 0x10, /* Port 34 (ge16) ExtBus=0 Addr=0x10 */ 2902 0x11, /* Port 35 (ge17) ExtBus=0 Addr=0x11 */ 2903 0x12, /* Port 36 (ge18) ExtBus=0 Addr=0x12 */ 2904 0x00, /* Port 37 ( N/A) */ 2905 0x00, /* Port 38 ( N/A) */ 2906 0x00, /* Port 39 ( N/A) */ 2907 0x00, /* Port 40 ( N/A) */ 2908 0x00, /* Port 41 ( N/A) */ 2909 0x00, /* Port 42 ( N/A) */ 2910 0x16, /* Port 43 (ge19) ExtBus=0 Addr=0x16 */ 2911 0x17, /* Port 44 (ge20) ExtBus=0 Addr=0x17 */ 2912 0x18, /* Port 45 (ge21) ExtBus=0 Addr=0x18 */ 2913 0x13, /* Port 46 (ge22) ExtBus=0 Addr=0x13 */ 2914 0x14, /* Port 47 (ge23) ExtBus=0 Addr=0x14 */ 2915 0x00, /* Port 48 ( N/A) */ 2916 0x00, /* Port 49 ( N/A) */ 2917 0x00, /* Port 50 ( N/A) */ 2918 0x00, /* Port 51 ( N/A) */ 2919 0x00, /* Port 52 ( N/A) */ 2920 0x00, /* Port 53 ( N/A) */ 2921 }; 2922 2923 static const uint16 _soc_phy_addr_bcm56686[] = { 2924 0x00, /* Port 0 (cmic) N/A */ 2925 0x00, /* Port 1 ( N/A) */ 2926 0x45, /* Port 2 ( xe0) ExtBus=2 Addr=0x05 */ 2927 0x00, /* Port 3 ( N/A) */ 2928 0x00, /* Port 4 ( N/A) */ 2929 0x00, /* Port 5 ( N/A) */ 2930 0x00, /* Port 6 ( N/A) */ 2931 0x00, /* Port 7 ( N/A) */ 2932 0x00, /* Port 8 ( N/A) */ 2933 0x00, /* Port 9 ( N/A) */ 2934 0x00, /* Port 10 ( N/A) */ 2935 0x00, /* Port 11 ( N/A) */ 2936 0x00, /* Port 12 ( N/A) */ 2937 0x00, /* Port 13 ( N/A) */ 2938 0x00, /* Port 14 ( N/A) */ 2939 0x00, /* Port 15 ( N/A) */ 2940 0x00, /* Port 16 ( N/A) */ 2941 0x00, /* Port 17 ( N/A) */ 2942 0x00, /* Port 18 ( N/A) */ 2943 0x00, /* Port 19 ( N/A) */ 2944 0x00, /* Port 20 ( N/A) */ 2945 0x00, /* Port 21 ( N/A) */ 2946 0x00, /* Port 22 ( N/A) */ 2947 0x00, /* Port 23 ( N/A) */ 2948 0x00, /* Port 24 ( N/A) */ 2949 0x00, /* Port 25 ( N/A) */ 2950 0x00, /* Port 26 ( N/A) */ 2951 0x46, /* Port 27 ( xe1) ExtBus=2 Addr=0x06 */ 2952 0x41, /* Port 28 ( hg0) ExtBus=2 Addr=0x01 */ 2953 0x42, /* Port 29 ( hg1) ExtBus=2 Addr=0x02 */ 2954 0x43, /* Port 30 ( hg2) ExtBus=2 Addr=0x03 */ 2955 0x44, /* Port 31 ( hg3) ExtBus=2 Addr=0x04 */ 2956 }; 2957 2958 static const uint16 _soc_phy_addr_bcm56620[] = { 2959 0x00, /* Port 0 (cmic) N/A */ 2960 0x00, /* Port 1 ( N/A) */ 2961 0x01, /* Port 2 ( ge0) ExtBus=0 Addr=0x01 */ 2962 0x02, /* Port 3 ( ge1) ExtBus=0 Addr=0x02 */ 2963 0x03, /* Port 4 ( ge2) ExtBus=0 Addr=0x03 */ 2964 0x04, /* Port 5 ( ge3) ExtBus=0 Addr=0x04 */ 2965 0x05, /* Port 6 ( ge4) ExtBus=0 Addr=0x05 */ 2966 0x06, /* Port 7 ( ge5) ExtBus=0 Addr=0x06 */ 2967 0x00, /* Port 8 ( N/A) */ 2968 0x00, /* Port 9 ( N/A) */ 2969 0x00, /* Port 10 ( N/A) */ 2970 0x00, /* Port 11 ( N/A) */ 2971 0x00, /* Port 12 ( N/A) */ 2972 0x00, /* Port 13 ( N/A) */ 2973 0x09, /* Port 14 ( ge6) ExtBus=0 Addr=0x09 */ 2974 0x0a, /* Port 15 ( ge7) ExtBus=0 Addr=0x0a */ 2975 0x0b, /* Port 16 ( ge8) ExtBus=0 Addr=0x0b */ 2976 0x0c, /* Port 17 ( ge9) ExtBus=0 Addr=0x0c */ 2977 0x07, /* Port 18 (ge10) ExtBus=0 Addr=0x07 */ 2978 0x08, /* Port 19 (ge11) ExtBus=0 Addr=0x08 */ 2979 0x00, /* Port 20 ( N/A) */ 2980 0x00, /* Port 21 ( N/A) */ 2981 0x00, /* Port 22 ( N/A) */ 2982 0x00, /* Port 23 ( N/A) */ 2983 0x00, /* Port 24 ( N/A) */ 2984 0x00, /* Port 25 ( N/A) */ 2985 0x0d, /* Port 26 (ge12) ExtBus=0 Addr=0x0d */ 2986 0x15, /* Port 27 (ge13) ExtBus=0 Addr=0x15 */ 2987 0x41, /* Port 28 ( hg0) ExtBus=2 Addr=0x01 */ 2988 0x42, /* Port 29 ( hg1) ExtBus=2 Addr=0x02 */ 2989 0x43, /* Port 30 ( hg2) ExtBus=2 Addr=0x03 */ 2990 0x44, /* Port 31 ( hg3) ExtBus=2 Addr=0x04 */ 2991 0x0e, /* Port 32 (ge14) ExtBus=0 Addr=0x0e */ 2992 0x0f, /* Port 33 (ge15) ExtBus=0 Addr=0x0f */ 2993 0x10, /* Port 34 (ge16) ExtBus=0 Addr=0x10 */ 2994 0x11, /* Port 35 (ge17) ExtBus=0 Addr=0x11 */ 2995 0x12, /* Port 36 (ge18) ExtBus=0 Addr=0x12 */ 2996 0x00, /* Port 37 ( N/A) */ 2997 0x00, /* Port 38 ( N/A) */ 2998 0x00, /* Port 39 ( N/A) */ 2999 0x00, /* Port 40 ( N/A) */ 3000 0x00, /* Port 41 ( N/A) */ 3001 0x00, /* Port 42 ( N/A) */ 3002 0x16, /* Port 43 (ge19) ExtBus=0 Addr=0x16 */ 3003 0x17, /* Port 44 (ge20) ExtBus=0 Addr=0x17 */ 3004 0x18, /* Port 45 (ge21) ExtBus=0 Addr=0x18 */ 3005 0x13, /* Port 46 (ge22) ExtBus=0 Addr=0x13 */ 3006 0x14, /* Port 47 (ge23) ExtBus=0 Addr=0x14 */ 3007 0x00, /* Port 48 ( N/A) */ 3008 0x00, /* Port 49 ( N/A) */ 3009 0x00, /* Port 50 ( N/A) */ 3010 0x00, /* Port 51 ( N/A) */ 3011 0x00, /* Port 52 ( N/A) */ 3012 0x00, /* Port 53 ( N/A) */ 3013 }; 3014 uint16 dev_id; 3015 uint8 rev_id; 3016 3017 soc_cm_get_id(unit, &dev_id, &rev_id); 3018 3019 *phy_addr_int = _soc_valkyrie_int_phy_addr[port]; 3020 switch (dev_id) { 3021 case BCM56620_DEVICE_ID: 3022 *phy_addr = _soc_phy_addr_bcm56620[port]; 3023 break; 3024 case BCM56684_DEVICE_ID: 3025 *phy_addr = _soc_phy_addr_bcm56684[port]; 3026 break; 3027 case BCM56686_DEVICE_ID: 3028 *phy_addr = _soc_phy_addr_bcm56686[port]; 3029 break; 3030 case BCM56680_DEVICE_ID: 3031 default: 3032 *phy_addr = _soc_phy_addr_bcm56680[port]; 3033 break; 3034 } 3035 } 3036 #endif /* BCM_VALKYRIE_SUPPORT */ 3037 3038 #ifdef BCM_PETRA_SUPPORT 3039 int 3040 _dpp_phy_addr_multi_get(int unit, soc_port_t port, int is_logical, int array_max, 3041 int *array_size, phyident_core_info_t *core_info) 3042 { 3043 static const uint16 _soc_phy_addr_arad[] = { 3044 (0x00), /* Phy Port 0 (first phy port is CMIC)*/ 3045 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 1 (WC0 lane 0) Bus=3 Phy=0 */ 3046 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 2 (WC0 lane 1) Bus=3 Phy=0 */ 3047 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 3 (WC0 lane 2) Bus=3 Phy=0 */ 3048 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 4 (WC0 lane 3) Bus=3 Phy=0 */ 3049 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 5 (WC1 lane 0) Bus=3 Phy=4 */ 3050 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 6 (WC1 lane 1) Bus=3 Phy=4 */ 3051 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 7 (WC1 lane 2) Bus=3 Phy=4 */ 3052 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 8 (WC1 lane 3) Bus=3 Phy=4 */ 3053 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 9 (WC2 lane 0) Bus=3 Phy=8 */ 3054 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 10 (WC2 lane 1) Bus=3 Phy=8 */ 3055 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 11 (WC2 lane 2) Bus=3 Phy=8 */ 3056 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 12 (WC2 lane 3) Bus=3 Phy=8 */ 3057 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x0c | 0x80), /* Phy Port 13 (WC3 lane 0) Bus=3 Phy=12 */ 3058 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x0c | 0x80), /* Phy Port 14 (WC3 lane 1) Bus=3 Phy=12 */ 3059 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x0c | 0x80), /* Phy Port 15 (WC3 lane 2) Bus=3 Phy=12 */ 3060 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x0c | 0x80), /* Phy Port 16 (WC3 lane 3) Bus=3 Phy=12 */ 3061 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x10 | 0x80), /* Phy Port 17 (WC4 lane 0) Bus=3 Phy=16 */ 3062 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x10 | 0x80), /* Phy Port 18 (WC4 lane 1) Bus=3 Phy=16 */ 3063 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x10 | 0x80), /* Phy Port 19 (WC4 lane 2) Bus=3 Phy=16 */ 3064 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x10 | 0x80), /* Phy Port 20 (WC4 lane 3) Bus=3 Phy=16 */ 3065 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x14 | 0x80), /* Phy Port 21 (WC5 lane 0) Bus=3 Phy=20 */ 3066 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x14 | 0x80), /* Phy Port 22 (WC5 lane 1) Bus=3 Phy=20 */ 3067 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x14 | 0x80), /* Phy Port 23 (WC5 lane 2) Bus=3 Phy=20 */ 3068 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x14 | 0x80), /* Phy Port 24 (WC5 lane 3) Bus=3 Phy=20 */ 3069 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x18 | 0x80), /* Phy Port 25 (WC6 lane 0) Bus=3 Phy=24 */ 3070 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x18 | 0x80), /* Phy Port 26 (WC6 lane 1) Bus=3 Phy=24 */ 3071 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x18 | 0x80), /* Phy Port 27 (WC6 lane 2) Bus=3 Phy=24 */ 3072 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x18 | 0x80), /* Phy Port 28 (WC6 lane 3) Bus=3 Phy=24 */ 3073 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x0c | 0x80), /* Phy Port 29 (WC7 lane 0) Bus=2 Phy=12 */ 3074 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x0c | 0x80), /* Phy Port 30 (WC7 lane 1) Bus=2 Phy=12 */ 3075 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x0c | 0x80), /* Phy Port 31 (WC7 lane 2) Bus=2 Phy=12 */ 3076 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x0c | 0x80), /* Phy Port 32 (WC7 lane 3) Bus=2 Phy=12 */ 3077 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x1c | 0x80), /* Phy Port 33 (MLD 0) Bus=3 Phy=26 */ 3078 ((3 << PHY_ID_BUS_LOWER_SHIFT) | 0x1d | 0x80), /* Phy Port 34 (MLD 1) Bus=3 Phy=27 */ 3079 0x00, /* Phy Port 35 (N/A) */ 3080 0x00, /* Phy Port 36 (N/A) */ 3081 0x00, /* Phy Port 37 (N/A) */ 3082 0x00, /* Phy Port 38 (N/A) */ 3083 0x00, /* Phy Port 39 (N/A) */ 3084 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 40 (Fabric Link0) Bus=1 Phy=0 */ 3085 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 41 (Fabric Link1) Bus=1 Phy=0 */ 3086 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 42 (Fabric Link2) Bus=1 Phy=0 */ 3087 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 43 (Fabric Link3) Bus=1 Phy=0 */ 3088 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 44 (Fabric Link4) Bus=1 Phy=4 */ 3089 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 45 (Fabric Link5) Bus=1 Phy=4 */ 3090 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 46 (Fabric Link6) Bus=1 Phy=4 */ 3091 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 47 (Fabric Link7) Bus=1 Phy=4 */ 3092 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 48 (Fabric Link8) Bus=1 Phy=8 */ 3093 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 49 (Fabric Link9) Bus=1 Phy=8 */ 3094 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 50 (Fabric Link10) Bus=1 Phy=8 */ 3095 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 51 (Fabric Link11) Bus=1 Phy=8 */ 3096 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x10 | 0x80), /* Phy Port 52 (Fabric Link12) Bus=1 Phy=16 */ 3097 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x10 | 0x80), /* Phy Port 53 (Fabric Link13) Bus=1 Phy=16 */ 3098 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x10 | 0x80), /* Phy Port 54 (Fabric Link14) Bus=1 Phy=16 */ 3099 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x10 | 0x80), /* Phy Port 55 (Fabric Link15) Bus=1 Phy=16 */ 3100 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x14 | 0x80), /* Phy Port 56 (Fabric Link16) Bus=1 Phy=20 */ 3101 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x14 | 0x80), /* Phy Port 57 (Fabric Link17) Bus=1 Phy=20 */ 3102 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x14 | 0x80), /* Phy Port 58 (Fabric Link18) Bus=1 Phy=20 */ 3103 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x14 | 0x80), /* Phy Port 59 (Fabric Link19) Bus=1 Phy=20 */ 3104 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x18 | 0x80), /* Phy Port 60 (Fabric Link20) Bus=1 Phy=24 */ 3105 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x18 | 0x80), /* Phy Port 61 (Fabric Link21) Bus=1 Phy=24 */ 3106 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x18 | 0x80), /* Phy Port 62 (Fabric Link22) Bus=1 Phy=24 */ 3107 ((1 << PHY_ID_BUS_LOWER_SHIFT) | 0x18 | 0x80), /* Phy Port 63 (Fabric Link23) Bus=1 Phy=24 */ 3108 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 64 (Fabric Link24) Bus=2 Phy=0 */ 3109 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 65 (Fabric Link25) Bus=2 Phy=0 */ 3110 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 66 (Fabric Link26) Bus=2 Phy=0 */ 3111 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x00 | 0x80), /* Phy Port 67 (Fabric Link27) Bus=2 Phy=0 */ 3112 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 68 (Fabric Link28) Bus=2 Phy=4 */ 3113 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 69 (Fabric Link29) Bus=2 Phy=4 */ 3114 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 70 (Fabric Link30) Bus=2 Phy=4 */ 3115 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x04 | 0x80), /* Phy Port 71 (Fabric Link31) Bus=2 Phy=4 */ 3116 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 72 (Fabric Link32) Bus=2 Phy=8 */ 3117 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 73 (Fabric Link33) Bus=2 Phy=8 */ 3118 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 74 (Fabric Link34) Bus=2 Phy=8 */ 3119 ((2 << PHY_ID_BUS_LOWER_SHIFT) | 0x08 | 0x80), /* Phy Port 75 (Fabric Link35) Bus=2 Phy=8 */ 3120 }; 3121 3122 uint32 phy_port; 3123 3124 *array_size = 0; 3125 3126 if(!is_logical) { 3127 phy_port = port; 3128 if(array_max != 1) { 3129 return SOC_E_PARAM; 3130 } 3131 } 3132 else{ 3133 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 3134 } 3135 3136 if(phy_port > 75){ 3137 return SOC_E_PARAM; 3138 } 3139 /* array of one element return just the mdio address and type*/ 3140 if(array_max == 1){ 3141 core_info[0].mdio_addr = _soc_phy_addr_arad[phy_port]; 3142 core_info[0].core_type = phyident_core_type_wc; 3143 core_info[0].mld_index = PHYIDENT_INFO_NOT_SET; 3144 core_info[0].index_in_mld = PHYIDENT_INFO_NOT_SET; 3145 core_info[0].first_phy_in_core = PHYIDENT_INFO_NOT_SET; 3146 core_info[0].nof_lanes_in_core = PHYIDENT_INFO_NOT_SET; 3147 *array_size = 1; 3148 return SOC_E_NONE; 3149 } 3150 3151 #ifdef BCM_ARAD_SUPPORT 3152 if (SOC_IS_ARAD(unit)){ 3153 uint32 required_mdio_addr; 3154 soc_port_if_t interface_type; 3155 soc_pbmp_t quads_in_use, phys_in_use; 3156 uint32 lanes_in_quad; 3157 uint32 quad_id; 3158 uint32 mlds_in_use = 0; 3159 uint8 is_elk_ilkn_no_mld = FALSE; 3160 uint8 is_caui_ten_lanes_allowed = FALSE; 3161 int i; 3162 int rv; 3163 3164 rv = soc_port_sw_db_interface_type_get(unit, port, &interface_type); 3165 if (rv != SOC_E_NONE) { 3166 return SOC_E_FAIL; 3167 } 3168 #if defined(INCLUDE_KBP) && defined(BCM_88660) 3169 if(SOC_IS_ARADPLUS(unit)&& (SOC_DPP_CONFIG(unit)->arad->init.elk.ext_interface_mode)){ 3170 uint32 offset; 3171 is_caui_ten_lanes_allowed = TRUE; 3172 if(interface_type == SOC_PORT_IF_ILKN){ 3173 rv = soc_port_sw_db_protocol_offset_get(unit, port, 0, &offset); 3174 if (rv != SOC_E_NONE) { 3175 return SOC_E_FAIL; 3176 } 3177 /* ILKN1 in ext_interface_mode of ARAD PLUS does not use MLDs*/ 3178 is_elk_ilkn_no_mld = (offset == 1); 3179 } 3180 } 3181 #endif 3182 /* calaculate the required mdio entries (WCs+MLDs)*/ 3183 rv = soc_pm_serdes_quads_in_use_get(unit, port, &quads_in_use); 3184 if (rv != SOC_E_NONE) { 3185 return SOC_E_FAIL; 3186 } 3187 SOC_PBMP_COUNT(quads_in_use, required_mdio_addr); 3188 if (!is_elk_ilkn_no_mld) 3189 { 3190 3191 required_mdio_addr += (required_mdio_addr - 1)/ 3 + 1; 3192 } 3193 3194 if(array_max < required_mdio_addr) { 3195 return SOC_E_PARAM; 3196 } 3197 3198 /* add the cores to the array*/ 3199 rv = soc_port_sw_db_phy_ports_get(unit, port, &phys_in_use); 3200 if (rv != SOC_E_NONE) { 3201 return SOC_E_FAIL; 3202 } 3203 SOC_PBMP_ITER(quads_in_use, quad_id) 3204 { 3205 if(quad_id > 7){ 3206 return SOC_E_FAIL; 3207 } 3208 phy_port = (quad_id * LANES_IN_QUAD) + 1; 3209 /*add core_info*/ 3210 core_info[*array_size].mdio_addr = _soc_phy_addr_arad[phy_port]; 3211 core_info[*array_size].core_type = phyident_core_type_wc; 3212 #if defined(INCLUDE_KBP) && defined(BCM_88660) 3213 if (is_elk_ilkn_no_mld){ 3214 core_info[*array_size].mld_index = PHYIDENT_INFO_NOT_SET; 3215 core_info[*array_size].index_in_mld = PHYIDENT_INFO_NOT_SET; 3216 } else 3217 #endif /* defined(INCLUDE_KBP) && defined(BCM_88660) */ 3218 { 3219 core_info[*array_size].mld_index = quad_id < 4 ? 0 : 1; 3220 core_info[*array_size].index_in_mld = quad_id - (quad_id / 4) * 4; 3221 SHR_BITSET(&mlds_in_use, core_info[*array_size].mld_index); 3222 } 3223 if((interface_type == SOC_PORT_IF_ILKN) || (is_caui_ten_lanes_allowed)) 3224 { 3225 lanes_in_quad = 0; 3226 for ( i = 0 ; i < LANES_IN_QUAD; i++) 3227 { 3228 if(SOC_PBMP_MEMBER(phys_in_use, phy_port + i)){ 3229 if(lanes_in_quad == 0){ 3230 core_info[*array_size].first_phy_in_core = i; 3231 } 3232 lanes_in_quad++; 3233 } 3234 } 3235 core_info[*array_size].nof_lanes_in_core = lanes_in_quad; 3236 } 3237 (*array_size)++; 3238 } 3239 3240 /*add the MLDs*/ 3241 for(i = 0 ; i < 2 ; i++) 3242 { 3243 if(!SHR_BITGET(&mlds_in_use, i)){ 3244 continue; 3245 } 3246 core_info[*array_size].mdio_addr = _soc_phy_addr_arad[33+i]; 3247 core_info[*array_size].core_type = phyident_core_type_mld; 3248 core_info[*array_size].mld_index = i; 3249 core_info[*array_size].index_in_mld = 0; 3250 core_info[*array_size].first_phy_in_core = PHYIDENT_INFO_NOT_SET; 3251 core_info[*array_size].nof_lanes_in_core = PHYIDENT_INFO_NOT_SET; 3252 (*array_size)++; 3253 } 3254 } 3255 #endif 3256 return SOC_E_NONE; 3257 } 3258 3259 STATIC void 3260 _dpp_phy_addr_default(int unit, int port, 3261 uint16 *phy_addr, uint16 *phy_addr_int) 3262 { 3263 int array_size, rv; 3264 phyident_core_info_t core_info; 3265 3266 phyident_core_info_t_init(&core_info); 3267 3268 *phy_addr = 0; 3269 rv = _dpp_phy_addr_multi_get(unit, port, 1, 1, &array_size, &core_info); 3270 *phy_addr_int = core_info.mdio_addr; 3271 3272 if(SOC_FAILURE(rv) || array_size==0){ 3273 *phy_addr_int = 0; 3274 LOG_VERBOSE(BSL_LS_SOC_PHY, 3275 (BSL_META_U(unit, 3276 "_dpp_phy_addr_default: failed to get address for port %d\n"), port)); 3277 } 3278 } 3279 #endif /* BCM_PETRA_SUPPORT */ 3280 3281 #ifdef BCM_DFE_SUPPORT 3282 STATIC void 3283 _dfe_phy_addr_default(int unit, int port, 3284 uint16 *phy_addr, uint16 *phy_addr_int) 3285 { 3286 uint32 bus_id; 3287 3288 /* Physical port number starts from 0 3289 * Internal/external MDIO bus number = port number / 32 3290 * Internal MDIO address = (port number % 32) / 4 3291 */ 3292 bus_id = port / 32; 3293 bus_id = ((bus_id & 0x3)<<PHY_ID_BUS_LOWER_SHIFT) | ((bus_id & 0xc)<<PHY_ID_BUS_UPPER_SHIFT); 3294 *phy_addr_int = 0x80 | bus_id | ((port % 32)/4); 3295 3296 /* external MDIO address */ 3297 *phy_addr = bus_id | ((port % 32)/4); 3298 } 3299 #endif /* BCM_DFE_SUPPORT */ 3300 3301 #ifdef BCM_APACHE_SUPPORT 3302 STATIC void 3303 _apache_phy_addr_default(int unit, int port, 3304 uint16 *phy_addr, uint16 *phy_addr_int) 3305 { 3306 soc_info_t *si; 3307 int phy_port, bus_id_encoding, phy_id; 3308 3309 si = &SOC_INFO(unit); 3310 3311 phy_port = si->port_l2p_mapping[port]; 3312 if (phy_port == -1) { 3313 *phy_addr_int = 0; 3314 *phy_addr = 0; 3315 return; 3316 } 3317 3318 /* 3319 * Internal phy address: 3320 * bus 0 phy 1 to 28 are mapped to Physical port 1 to 28 3321 * bus 1 phy 1 to 20 are mapped to Physical port 29 to 48 3322 * bus 2 phy 1 to 24 are mapped to Physical port 49 to 72 3323 */ 3324 if (phy_port < 29) { 3325 bus_id_encoding = 0; /* bus 0, bit {8,6,5} = 0 */ 3326 phy_id = phy_port; 3327 } else if (phy_port < 49) { 3328 bus_id_encoding = 0x020; /* bus 1, bit {8,6,5} = 1 */ 3329 phy_id = phy_port - 28; 3330 } else { 3331 bus_id_encoding = 0x040; /* bus 2, bit {8,6,5} = 2 */ 3332 phy_id = phy_port - 48; 3333 } 3334 *phy_addr_int = 0x80 | bus_id_encoding | phy_id; 3335 3336 /* 3337 * External phy address: 3338 * bus 0 phy 1 to 28 are mapped to Physical port 1 to 28 3339 * bus 1 phy 1 to 20 are mapped to Physical port 29 to 48 3340 * bus 2 phy 1 to 24 are mapped to Physical port 49 to 72 3341 */ 3342 /* external phy address encoding */ 3343 *phy_addr = bus_id_encoding | phy_id; 3344 3345 LOG_VERBOSE(BSL_LS_SOC_PHY, (BSL_META_U(unit, 3346 "_apache_phy_addr_default: port=%d phy_port=%d bus_id=%d phy_id=%d phy_int=%d phy_ext=%d\n"), 3347 port, phy_port, (bus_id_encoding >> 5), phy_id, *phy_addr_int, *phy_addr)); 3348 3349 } 3350 #endif /* BCM_APACHE_SUPPORT */ 3351 3352 3353 #ifdef BCM_TRIDENT_SUPPORT 3354 STATIC void 3355 _trident_phy_addr_default(int unit, int port, 3356 uint16 *phy_addr, uint16 *phy_addr_int) 3357 { 3358 soc_info_t *si; 3359 int phy_port; 3360 3361 si = &SOC_INFO(unit); 3362 3363 phy_port = si->port_l2p_mapping[port]; 3364 if (phy_port == -1) { 3365 *phy_addr_int = 0; 3366 *phy_addr = 0; 3367 return; 3368 } 3369 3370 /* Physical port number starts from 1 3371 * Internal/external MDIO bus number = (physical port number - 1) / 24 3372 * Internal MDIO address = (physical port number - 1) % 24 + 1 3373 */ 3374 *phy_addr_int = 0x80 | (((phy_port - 1) / 24) << 5) | 3375 ((((phy_port - 1) % 24)/4)*4 + 1); 3376 3377 /* external MDIO address */ 3378 *phy_addr = (((phy_port - 1) / 24) << 5) | 3379 ((phy_port - 1) % 24 + 4); 3380 } 3381 #endif /* BCM_TRIDENT_SUPPORT */ 3382 3383 #ifdef BCM_TRIDENT2_SUPPORT 3384 STATIC void 3385 _trident2_phy_addr_default(int unit, int port, 3386 uint16 *phy_addr, uint16 *phy_addr_int) 3387 { 3388 soc_info_t *si; 3389 int phy_port, bus_id_encoding, phy_id; 3390 3391 si = &SOC_INFO(unit); 3392 3393 phy_port = si->port_l2p_mapping[port]; 3394 if (phy_port == -1) { 3395 *phy_addr_int = 0; 3396 *phy_addr = 0; 3397 return; 3398 } 3399 3400 /* 3401 * Internal phy address: 3402 * bus 0 phy 1 to 20 are mapped to Physical port 1 to 20 3403 * bus 1 phy 1 to 24 are mapped to Physical port 21 to 44 3404 * bus 2 phy 1 to 20 are mapped to Physical port 45 to 64 3405 * bus 3 phy 1 to 20 are mapped to Physical port 65 to 84 3406 * bus 4 phy 1 to 24 are mapped to Physical port 85 to 108 3407 * bus 5 phy 1 to 20 are mapped to Physical port 109 to 128 3408 */ 3409 if (phy_port < 65) { /* X pipe */ 3410 if (phy_port < 21) { 3411 bus_id_encoding = 0; /* bus 0, bit {8,6,5} = 0 */ 3412 phy_id = phy_port; 3413 } else if (phy_port < 45) { 3414 bus_id_encoding = 0x020; /* bus 1, bit {8,6,5} = 1 */ 3415 phy_id = phy_port - 20; 3416 } else { 3417 bus_id_encoding = 0x040; /* bus 2, bit {8,6,5} = 2 */ 3418 phy_id = phy_port - 44; 3419 } 3420 } else { 3421 if (phy_port < 85) { 3422 bus_id_encoding = 0x060; /* bus 3, bit {8,6,5} = 3 */ 3423 phy_id = phy_port - 64; 3424 } else if (phy_port < 109) { 3425 bus_id_encoding = 0x100; /* bus 4, bit {8,6,5} = 4 */ 3426 phy_id = phy_port - 84; 3427 } else { 3428 bus_id_encoding = 0x120; /* bus 5, bit {8,6,5} = 5 */ 3429 phy_id = phy_port - 108; 3430 } 3431 } 3432 *phy_addr_int = 0x80 | bus_id_encoding | phy_id; 3433 3434 /* 3435 * External phy address: 3436 * bus 0 phy 1 to 31 are mapped to Physical port 1 to 32 3437 * bus 1 phy 1 to 31 are mapped to Physical port 33 to 64 3438 * bus 2 phy 1 to 31 are mapped to Physical port 65 to 96 3439 * bus 3 phy 1 to 31 are mapped to Physical port 97 to 128 3440 */ 3441 bus_id_encoding = (phy_port - 1) & 0x060; 3442 phy_id = (phy_port - 1) & 0x1f; 3443 /* external phy address encoding */ 3444 *phy_addr = bus_id_encoding | phy_id; 3445 } 3446 #endif /* BCM_TRIDENT2_SUPPORT */ 3447 3448 #ifdef BCM_SHADOW_SUPPORT 3449 STATIC void 3450 _shadow_phy_addr_default(int unit, int port, 3451 uint16 *phy_addr, uint16 *phy_addr_int) 3452 { 3453 soc_info_t *si; 3454 int phy_port; 3455 static const uint16 _soc_phy_addr_bcm88732_a0[] = { 3456 0, 3457 1, 1, 1, 1, /* Radian port 1-4 => WC0 MDIO Port Address 1 */ 3458 5, 5, 5, 5, /* Radian port 5-8 => WC0 MDIO Port Address 5 */ 3459 9, 9, 9, 9, /* Radian port 9-10 => WC0 MDIO Port Address 9 */ 3460 13, 13, 13, 13, /* Radian port 11-12 => WC0 MDIO Port Address 13 */ 3461 17, 17, 17, 17, /* Radian port 13-14 => WC0 MDIO Port Address 17 */ 3462 21, 21, 21, 21 /* Radian port 15-16 => WC0 MDIO Port Address 21 */ 3463 }; 3464 static const uint16 _soc_phy_addr_switch_link_xaui[] = { 3465 9, 9, /* Radian port 9-10 => WC0 MDIO Port Address 9 */ 3466 13, 13, /* Radian port 11-12 => WC0 MDIO Port Address 13 */ 3467 17, 17, /* Radian port 13-14 => WC0 MDIO Port Address 17 */ 3468 21, 21 /* Radian port 15-16 => WC0 MDIO Port Address 21 */ 3469 }; 3470 3471 static const uint16 _soc_phy_addr_switch_link_r2[] = { 3472 9, 9, /* Radian port 9-10 => WC0 MDIO Port Address 9 */ 3473 13, 13, /* Radian port 11-12 => WC0 MDIO Port Address 13 */ 3474 17, 17, /* Radian port 13-14 => WC0 MDIO Port Address 17 */ 3475 21, 21 /* Radian port 15-16 => WC0 MDIO Port Address 21 */ 3476 }; 3477 si = &SOC_INFO(unit); 3478 3479 if (soc_feature(unit, soc_feature_logical_port_num)) { 3480 phy_port = si->port_l2p_mapping[port]; 3481 } else { 3482 phy_port = port; 3483 } 3484 if (phy_port < 1 || phy_port > 16) { 3485 *phy_addr_int = 0; 3486 *phy_addr = 0; 3487 return; 3488 } 3489 if (phy_port < 9) { 3490 *phy_addr_int = 0x80 | (_soc_phy_addr_bcm88732_a0[phy_port]); 3491 *phy_addr = *phy_addr_int; /* no external PHYs */ 3492 } else { /* switch link side */ 3493 if (soc_property_get(unit, spn_BCM88732_1X40_4X10, 0) || 3494 soc_property_get(unit, spn_BCM88732_4X10_4X10, 0)) { 3495 *phy_addr_int = 0x80 | (_soc_phy_addr_switch_link_xaui[phy_port-9]); 3496 *phy_addr = *phy_addr_int; /* no external PHYs */ 3497 } else if (soc_property_get(unit, spn_BCM88732_2X40_8X12, 0) || 3498 soc_property_get(unit, spn_BCM88732_1X40_4X10_8X12, 0) || 3499 soc_property_get(unit, spn_BCM88732_4X10_1X40_8X12, 0) || 3500 soc_property_get(unit, spn_BCM88732_8X10_8X12, 0) || 3501 soc_property_get(unit, spn_BCM88732_8X10_4X12, 0) || 3502 soc_property_get(unit, spn_BCM88732_6X10_2X12, 0) || 3503 soc_property_get(unit, spn_BCM88732_8X10_2X12, 0) || 3504 soc_property_get(unit, spn_BCM88732_2X40_8X10, 0) || 3505 soc_property_get(unit, spn_BCM88732_8X10_8X10, 0)) { 3506 *phy_addr_int = 0x80 | (_soc_phy_addr_switch_link_r2[phy_port-9]); 3507 *phy_addr = *phy_addr_int; /* no external PHYs */ 3508 } else { 3509 *phy_addr_int = 0x80 | (_soc_phy_addr_bcm88732_a0[phy_port]); 3510 if (soc_property_get(unit, spn_BCM88732_2X40_2X40, 0) || 3511 soc_property_get(unit, spn_BCM88732_8X10_2X40, 0) || 3512 (soc_property_get(unit, "IL3125", 0))) { /* for 16Lanes */ 3513 /* 3514 * Use the MDIO address assignment similar to that of 3515 * Switch link port configuration. 3516 */ 3517 *phy_addr_int = 0x80 | (_soc_phy_addr_switch_link_r2[phy_port-9]); 3518 } else { 3519 *phy_addr_int = 0x80 | (_soc_phy_addr_bcm88732_a0[phy_port]); 3520 } 3521 *phy_addr = *phy_addr_int; /* no external PHYs */ 3522 } 3523 } 3524 } 3525 #endif /* BCM_SHADOW_SUPPORT */ 3526 3527 #ifdef BCM_SCORPION_SUPPORT 3528 static int 3529 _scorpion_phy_addr_default(int unit, int port, 3530 uint16 *phy_addr, uint16 *phy_addr_int) 3531 { 3532 static const uint16 _soc_phy_addr_bcm56820_a0[] = { 3533 /* extPhy intPhy */ 3534 0x00, 0x00, /* Port 0 (cmic) N/A */ 3535 0x42, 0xc1, /* Port 1 ( xe0) */ 3536 0x43, 0xc2, /* Port 2 ( xe1) */ 3537 0x44, 0xc3, /* Port 3 ( xe2) */ 3538 0x45, 0xc4, /* Port 4 ( xe3) */ 3539 0x46, 0xc5, /* Port 5 ( xe4) */ 3540 0x47, 0xc6, /* Port 6 ( xe5) */ 3541 0x48, 0xc7, /* Port 7 ( xe6) */ 3542 0x49, 0xc8, /* Port 8 ( xe7) */ 3543 0x4a, 0xc9, /* Port 9 ( xe8) */ 3544 0x4b, 0xca, /* Port 10 ( xe9) */ 3545 0x4c, 0xcb, /* Port 11 (xe10) */ 3546 0x4d, 0xcc, /* Port 12 (xe11) */ 3547 0x4e, 0xcd, /* Port 13 (xe12) */ 3548 0x4f, 0xce, /* Port 14 (xe13) */ 3549 0x50, 0xcf, /* Port 15 (xe14) */ 3550 0x51, 0xd0, /* Port 16 (xe15) */ 3551 0x52, 0xd1, /* Port 17 (xe16) */ 3552 0x53, 0xd2, /* Port 18 (xe17) */ 3553 0x54, 0xd3, /* Port 19 (xe18) */ 3554 0x55, 0xd4, /* Port 20 (xe19) */ 3555 0x21, 0xd5, /* Port 21 (xe20) */ 3556 0x26, 0xd6, /* Port 22 (xe21) */ 3557 0x2b, 0xd7, /* Port 23 (xe22) */ 3558 0x30, 0xd8, /* Port 24 (xe23) */ 3559 0x59, 0xd9, /* Port 25 (ge0) */ 3560 0x5a, 0xda, /* Port 26 (ge1) */ 3561 0x5b, 0xdb, /* Port 27 (ge2) */ 3562 0x5c, 0xdc /* Port 28 (ge3) */ 3563 }; 3564 int rv = TRUE; 3565 uint16 dev_id; 3566 uint8 rev_id; 3567 3568 soc_cm_get_id(unit, &dev_id, &rev_id); 3569 3570 switch (dev_id) { 3571 case BCM56820_DEVICE_ID: 3572 *phy_addr = _soc_phy_addr_bcm56820_a0[port * 2]; 3573 *phy_addr_int = _soc_phy_addr_bcm56820_a0[port * 2 + 1]; 3574 break; 3575 default: 3576 rv = FALSE; 3577 break; 3578 } 3579 return rv; 3580 } 3581 #endif /* BCM_SCORPION_SUPPORT */ 3582 #ifdef BCM_TRIDENT3_SUPPORT 3583 STATIC void 3584 _trident3_phy_addr_default(int unit, int port, 3585 uint16 *phy_addr, uint16 *phy_addr_int) 3586 { 3587 soc_info_t *si; 3588 int phy_port_base, pbm_count = 0, last_pm4x25_phy_port=128; 3589 int phy_port, bus_id_encoding, phy_id; 3590 3591 si = &SOC_INFO(unit); 3592 3593 phy_port = si->port_l2p_mapping[port]; 3594 if (phy_port == -1 || phy_port == 0 || phy_port > 131) { 3595 *phy_addr_int = 0; 3596 *phy_addr = 0; 3597 return; 3598 } 3599 phy_port_base = (1 + ((SOC_INFO(unit).port_l2p_mapping[port] - 1) & ~0x3)); 3600 3601 SOC_PBMP_COUNT(si->management_pbm, pbm_count); 3602 if (pbm_count == 2) last_pm4x25_phy_port = 127; 3603 3604 /* 3605 * Internal phy address: 3606 * bus 0 phy 1 to 24 are mapped to physical port 1 to 24 3607 * bus 1 phy 1 to 16 are mapped to physical port 25 to 40 3608 * bus 2 phy 1 to 24 are mapped to physical port 41 to 64 3609 * bus 3 phy 1 to 24 are mapped to physical port 65 to 88 3610 * bus 4 phy 1 to 16 are mapped to physical port 89 to 104 3611 * bus 5 phy 1 to 24 are mapped to physical port 105 to 128 3612 * bus 6 phy 1 is physical port 129 3613 * bus 6 phy 2 is physical port 128 3614 */ 3615 if (phy_port < 65) { /* PM0 - PM15 */ 3616 if (phy_port < 25) { 3617 bus_id_encoding = 0; /* bus 0, bit {8,6,5} = 0 */ 3618 phy_id = phy_port; 3619 } else if (phy_port < 41) { 3620 bus_id_encoding = 0x020; /* bus 1, bit {8,6,5} = 1 */ 3621 phy_id = phy_port - 24; 3622 } else { 3623 bus_id_encoding = 0x040; /* bus 2, bit {8,6,5} = 2 */ 3624 phy_id = phy_port - 40; 3625 } 3626 } else if (phy_port <= last_pm4x25_phy_port) { /* PM16 - PM31 */ 3627 if (phy_port < 89) { 3628 bus_id_encoding = 0x060; /* bus 3, bit {8,6,5} = 3 */ 3629 phy_id = phy_port - 64; 3630 } else if (phy_port < 105) { 3631 bus_id_encoding = 0x100; /* bus 4, bit {8,6,5} = 4 */ 3632 phy_id = phy_port - 88; 3633 } else { 3634 bus_id_encoding = 0x120; /* bus 5, bit {8,6,5} = 5 */ 3635 phy_id = phy_port - 104; 3636 } 3637 } else { /* PM32 */ 3638 bus_id_encoding = 0x140; /* bus 6, bit {8,6,5} = 6 */ 3639 phy_id = phy_port == 129 ? 1 : 3; 3640 } 3641 phy_id = phy_id - (phy_port - phy_port_base); 3642 *phy_addr_int = 0x80 | bus_id_encoding | phy_id; 3643 3644 /* 3645 * External phy address: 3646 * bus 0 phy 2 to 32 are mapped to Physical port 1 to 32 3647 * bus 1 phy 2 to 32 are mapped to Physical port 33 to 64 3648 * bus 2 phy 2 to 32 are mapped to Physical port 65 to 96 3649 * bus 3 phy 2 to 32 are mapped to Physical port 97 to 128 3650 */ 3651 bus_id_encoding = (phy_port - 1) & 0x060; 3652 phy_id = (((phy_port - 1) & 0x1f) / 4) + 2; 3653 /* external phy address encoding */ 3654 *phy_addr = bus_id_encoding | phy_id; 3655 } 3656 #endif /* BCM_TRIDENT3_SUPPORT */ 3657 3658 #ifdef BCM_TOMAHAWK_SUPPORT 3659 STATIC void 3660 _tomahawk_phy_addr_default(int unit, int port, 3661 uint16 *phy_addr, uint16 *phy_addr_int) 3662 { 3663 soc_info_t *si; 3664 int phy_port_base; 3665 int phy_port, bus_id_encoding, phy_id; 3666 3667 si = &SOC_INFO(unit); 3668 3669 phy_port = si->port_l2p_mapping[port]; 3670 if (phy_port == -1 || phy_port == 0 || phy_port > 131) { 3671 *phy_addr_int = 0; 3672 *phy_addr = 0; 3673 return; 3674 } 3675 phy_port_base = (1 + ((SOC_INFO(unit).port_l2p_mapping[port] - 1) & ~0x3)); 3676 3677 /* 3678 * Internal phy address: 3679 * bus 0 phy 1 to 24 are mapped to physical port 1 to 24 3680 * bus 1 phy 1 to 16 are mapped to physical port 25 to 40 3681 * bus 2 phy 1 to 24 are mapped to physical port 41 to 64 3682 * bus 3 phy 1 to 24 are mapped to physical port 65 to 88 3683 * bus 4 phy 1 to 16 are mapped to physical port 89 to 104 3684 * bus 5 phy 1 to 24 are mapped to physical port 105 to 128 3685 * bus 6 phy 1 is physical port 129 3686 * bus 6 phy 2 is physical port 131 3687 */ 3688 if (phy_port < 65) { /* PM0 - PM15 */ 3689 if (phy_port < 25) { 3690 bus_id_encoding = 0; /* bus 0, bit {8,6,5} = 0 */ 3691 phy_id = phy_port; 3692 } else if (phy_port < 41) { 3693 bus_id_encoding = 0x020; /* bus 1, bit {8,6,5} = 1 */ 3694 phy_id = phy_port - 24; 3695 } else { 3696 bus_id_encoding = 0x040; /* bus 2, bit {8,6,5} = 2 */ 3697 phy_id = phy_port - 40; 3698 } 3699 } else if (phy_port < 129) { /* PM16 - PM31 */ 3700 if (phy_port < 89) { 3701 bus_id_encoding = 0x060; /* bus 3, bit {8,6,5} = 3 */ 3702 phy_id = phy_port - 64; 3703 } else if (phy_port < 105) { 3704 bus_id_encoding = 0x100; /* bus 4, bit {8,6,5} = 4 */ 3705 phy_id = phy_port - 88; 3706 } else { 3707 bus_id_encoding = 0x120; /* bus 5, bit {8,6,5} = 5 */ 3708 phy_id = phy_port - 104; 3709 } 3710 } else { /* PM32 */ 3711 bus_id_encoding = 0x140; /* bus 6, bit {8,6,5} = 6 */ 3712 phy_id = phy_port == 129 ? 1 : 3; 3713 } 3714 phy_id = phy_id - (phy_port - phy_port_base); 3715 *phy_addr_int = 0x80 | bus_id_encoding | phy_id; 3716 3717 /* 3718 * External phy address: 3719 * bus 0 phy 2 to 32 are mapped to Physical port 1 to 32 3720 * bus 1 phy 2 to 32 are mapped to Physical port 33 to 64 3721 * bus 2 phy 2 to 32 are mapped to Physical port 65 to 96 3722 * bus 3 phy 2 to 32 are mapped to Physical port 97 to 128 3723 */ 3724 bus_id_encoding = (phy_port - 1) & 0x060; 3725 phy_id = (((phy_port - 1) & 0x1f) / 4) + 2; 3726 /* external phy address encoding */ 3727 *phy_addr = bus_id_encoding | phy_id; 3728 } 3729 #endif /* BCM_TOMAHAWK_SUPPORT */ 3730 3731 #ifdef BCM_TOMAHAWK2_SUPPORT 3732 STATIC void 3733 _tomahawk2_phy_addr_default(int unit, int port, 3734 uint16 *phy_addr, uint16 *phy_addr_int) 3735 { 3736 soc_info_t *si; 3737 int phy_port, bus_id_encoding, phy_id; 3738 3739 si = &SOC_INFO(unit); 3740 3741 phy_port = si->port_l2p_mapping[port]; 3742 if (phy_port == -1 || phy_port == 0 || phy_port > 259) { 3743 *phy_addr_int = 0; 3744 *phy_addr = 0; 3745 return; 3746 } 3747 3748 /* 3749 * Internal phy address: 3750 * bus 0 phy 1 to 28 are mapped to Physical port 1 to 28 3751 * bus 1 phy 1 to 28 are mapped to Physical port 29 to 56 3752 * bus 2 phy 1 to 16 are mapped to Physical port 57 to 72 3753 * bus 3 phy 1 to 28 are mapped to Physical port 73 to 100 3754 * bus 4 phy 1 to 28 are mapped to Physical port 101 to 128 3755 * bus 5 phy 1 to 28 are mapped to Physical port 129 to 156 3756 * bus 6 phy 1 to 28 are mapped to Physical port 157 to 184 3757 * bus 7 phy 1 to 16 are mapped to Physical port 185 to 200 3758 * bus 8 phy 1 to 28 are mapped to Physical port 201 to 228 3759 * bus 9 phy 1 to 28 are mapped to Physical port 229 to 256 3760 * bus 10 phy 1 is mapped to Physical port 257 and 3761 * phy 3 is mapped to Physical port 259 3762 */ 3763 if (phy_port < 129) { /* PM0 - PM31 */ 3764 if (phy_port < 29) { 3765 bus_id_encoding = 0; /* bus 0, bit {9,8,6,5} = 0 */ 3766 phy_id = phy_port; 3767 } else if (phy_port < 57) { 3768 bus_id_encoding = 0x020; /* bus 1, bit {9,8,6,5} = 1 */ 3769 phy_id = phy_port - 28; 3770 } else if (phy_port < 73) { 3771 bus_id_encoding = 0x040; /* bus 2, bit {9,8,6,5} = 2 */ 3772 phy_id = phy_port - 56; 3773 } else if (phy_port < 101) { 3774 bus_id_encoding = 0x060; /* bus 3, bit {9,8,6,5} = 3 */ 3775 phy_id = phy_port - 72; 3776 } else { 3777 bus_id_encoding = 0x100; /* bus 4, bit {9,8,6,5} = 4 */ 3778 phy_id = phy_port - 100; 3779 } 3780 } else if (phy_port < 257) { /* PM32 - PM63 */ 3781 if (phy_port < 157) { 3782 bus_id_encoding = 0x120; /* bus 5, bit {9,8,6,5} = 5 */ 3783 phy_id = phy_port - 128; 3784 } else if (phy_port < 185) { 3785 bus_id_encoding = 0x140; /* bus 6, bit {9,8,6,5} = 6 */ 3786 phy_id = phy_port - 156; 3787 } else if (phy_port < 201) { 3788 bus_id_encoding = 0x160; /* bus 7, bit {9,8,6,5} = 7 */ 3789 phy_id = phy_port - 184; 3790 } else if (phy_port < 229) { 3791 bus_id_encoding = 0x200; /* bus 8, bit {9,8,6,5} = 8 */ 3792 phy_id = phy_port - 200; 3793 } else { 3794 bus_id_encoding = 0x220; /* bus 9, bit {9,8,6,5} = 9 */ 3795 phy_id = phy_port - 228; 3796 } 3797 } else { /* PM64 */ 3798 bus_id_encoding = 0x240; /* bus 10, bit {9,8,6,5} = 10 */ 3799 phy_id = phy_port == 257 ? 1 : 3; 3800 } 3801 *phy_addr_int = 0x80 | bus_id_encoding | phy_id; 3802 3803 /* 3804 * External phy address: 3805 * bus 0 phy 0 to 31 are mapped to Physical port 1 to 32 3806 * bus 1 phy 0 to 31 are mapped to Physical port 33 to 64 3807 * bus 2 phy 0 to 31 are mapped to Physical port 65 to 96 3808 * bus 3 phy 0 to 31 are mapped to Physical port 97 to 128 3809 * bus 4 phy 0 to 31 are mapped to Physical port 129 to 160 3810 * bus 5 phy 0 to 31 are mapped to Physical port 161 to 192 3811 * bus 6 phy 0 to 31 are mapped to Physical port 193 to 224 3812 * bus 7 phy 0 to 31 are mapped to Physical port 225 to 256 3813 */ 3814 bus_id_encoding = (phy_port - 1) & 0x1e0; 3815 bus_id_encoding = (bus_id_encoding & 0x180) << 1 | 3816 (bus_id_encoding & 0x060); 3817 phy_id = (phy_port - 1) & 0x1f; 3818 /* external phy address encoding */ 3819 *phy_addr = bus_id_encoding | phy_id; 3820 } 3821 #endif /* BCM_TOMAHAWK2_SUPPORT */ 3822 3823 #ifdef BCM_TOMAHAWK3_SUPPORT 3824 STATIC void 3825 _tomahawk3_phy_addr_default(int unit, int port, 3826 uint16 *phy_addr, uint16 *phy_addr_int) 3827 { 3828 soc_info_t *si; 3829 int phy_port, bus_id_encoding, phy_id; 3830 3831 si = &SOC_INFO(unit); 3832 3833 phy_port = si->port_l2p_mapping[port]; 3834 if (phy_port == -1 || phy_port == 0 || phy_port > 258) { 3835 *phy_addr_int = 0; 3836 *phy_addr = 0; 3837 return; 3838 } 3839 /* 3840 * Internal phy address: 3841 * bus 0 phy 1 to 24 are mapped to Physical port 1 to 24 3842 * bus 1 phy 1 to 24 are mapped to Physical port 25 to 48 3843 * bus 2 phy 1 to 24 are mapped to Physical port 49 to 72 3844 * bus 3 phy 1 to 24 are mapped to Physical port 73 to 96 3845 * bus 4 phy 1 to 24 are mapped to Physical port 97 to 120 3846 * bus 5 phy 1 to 24 are mapped to Physical port 121 to 144 3847 * bus 6 phy 1 to 24 are mapped to Physical port 145 to 168 3848 * bus 7 phy 1 to 24 are mapped to Physical port 169 to 192 3849 * bus 8 phy 1 to 24 are mapped to Physical port 193 to 216 3850 * bus 9 phy 1 to 24 are mapped to Physical port 217 to 240 3851 * bus 10 phy 1 to 16 are mapped to Physical port 241 to 256 3852 * bus 11 phy 1 is mapped to Physical port 257 and 3853 * phy 2 is mapped to Physical port 258 3854 */ 3855 if (phy_port < 129) { /* PM0 - PM15 */ 3856 if (phy_port < 25) { 3857 bus_id_encoding = 0; /* bus 0, bit {9,8,6,5} = 0 */ 3858 phy_id = phy_port; 3859 } else if (phy_port < 49) { 3860 bus_id_encoding = 0x020; /* bus 1, bit {9,8,6,5} = 1 */ 3861 phy_id = phy_port - 24; 3862 } else if (phy_port < 73) { 3863 bus_id_encoding = 0x040; /* bus 2, bit {9,8,6,5} = 2 */ 3864 phy_id = phy_port - 48; 3865 } else if (phy_port < 97) { 3866 bus_id_encoding = 0x060; /* bus 3, bit {9,8,6,5} = 3 */ 3867 phy_id = phy_port - 72; 3868 } else if (phy_port < 121) { 3869 bus_id_encoding = 0x100; /* bus 4, bit {9,8,6,5} = 4 */ 3870 phy_id = phy_port - 96; 3871 } else { 3872 bus_id_encoding = 0x120; /* bus 5, bit {9,8,6,5} = 5 */ 3873 phy_id = phy_port - 120; /* PM15 only */ 3874 } 3875 } else if (phy_port < 257) { /* PM16 - PM31 */ 3876 if (phy_port < 145) { /* bus 5, continued, PM16, 17 */ 3877 bus_id_encoding = 0x120; 3878 phy_id = phy_port - 120; 3879 } else if (phy_port < 169) { 3880 bus_id_encoding = 0x140; /* bus 6, bit {9,8,6,5} = 6 */ 3881 phy_id = phy_port - 144; 3882 } else if (phy_port < 193) { 3883 bus_id_encoding = 0x160; /* bus 7, bit {9,8,6,5} = 7 */ 3884 phy_id = phy_port - 168; 3885 } else if (phy_port < 217) { 3886 bus_id_encoding = 0x200; /* bus 8, bit {9,8,6,5} = 8 */ 3887 phy_id = phy_port - 192; 3888 } else if (phy_port < 241) { 3889 bus_id_encoding = 0x220; /* bus 9, bit {9,8,6,5} = 9 */ 3890 phy_id = phy_port - 216; 3891 } else { 3892 bus_id_encoding = 0x240; /* bus 10, bit {9,8,6,5} = 10 */ 3893 phy_id = phy_port - 240; 3894 } 3895 } else { /* PM64 */ 3896 bus_id_encoding = 0x260; /* bus 10, bit {9,8,6,5} = 11 */ 3897 phy_id = phy_port == 257 ? 1 : 2; 3898 } 3899 *phy_addr_int = 0x80 | bus_id_encoding | phy_id; 3900 3901 3902 #if 0 3903 /* 3904 * External phy address: 3905 * bus 0 phy 0 to 31 are mapped to Physical port 1 to 32 3906 * bus 1 phy 0 to 31 are mapped to Physical port 33 to 64 3907 * bus 2 phy 0 to 31 are mapped to Physical port 65 to 96 3908 * bus 3 phy 0 to 31 are mapped to Physical port 97 to 128 3909 * bus 4 phy 0 to 31 are mapped to Physical port 129 to 160 3910 * bus 5 phy 0 to 31 are mapped to Physical port 161 to 192 3911 * bus 6 phy 0 to 31 are mapped to Physical port 193 to 224 3912 * bus 7 phy 0 to 31 are mapped to Physical port 225 to 256 3913 */ 3914 bus_id_encoding = (phy_port - 1) & 0x1e0; 3915 bus_id_encoding = (bus_id_encoding & 0x180) << 1 | 3916 (bus_id_encoding & 0x060); 3917 phy_id = (phy_port - 1) & 0x1f; 3918 /* external phy address encoding */ 3919 *phy_addr = bus_id_encoding | phy_id; 3920 #endif 3921 } 3922 #endif /* BCM_TOMAHAWK3_SUPPORT */ 3923 3924 3925 #ifdef BCM_XGS3_SWITCH_SUPPORT 3926 static void 3927 _xgs3_phy_addr_default(int unit, int port, 3928 uint16 *phy_addr, uint16 *phy_addr_int) 3929 { 3930 int phy_addr_adjust = 0; 3931 3932 if (SOC_IS_GOLDWING(unit)) { 3933 /* In Goldwing due to the hardware port remapping, we need to adjust 3934 * the PHY addresses. The PHY addresses are remapped as follow. 3935 * Original : 0 ... 13 14 15 16 17 18 19 3936 * Remapped : 0 ... 13 16 17 18 19 14 15 3937 */ 3938 if (port == 14 || port == 15) { 3939 phy_addr_adjust = 4; 3940 } else if (port > 15) { 3941 phy_addr_adjust = -2; 3942 } 3943 } 3944 if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port) || 3945 IS_GX_PORT(unit, port)) { 3946 pbmp_t pbm; 3947 int temp_port; 3948 int found = 0; 3949 int mdio_addr = 1; 3950 /* 3951 * Internal XAUI (Internal sel bit 0x80) on XPORT MDIO bus(0x40) 3952 * External Phy (Internal sel bit 0x00) on XPORT MDIO bus(0x40) 3953 * Assume External MDIO address starts at 1 as this is on a 3954 * seperate BUS. 3955 */ 3956 3957 /* 3958 * First, assign lowest addresses to GE ports which are also 3959 * GX ports. 3960 */ 3961 pbm = PBMP_GX_ALL(unit); 3962 SOC_PBMP_AND(pbm, PBMP_GE_ALL(unit)); 3963 3964 PBMP_ITER(pbm, temp_port) { 3965 if (temp_port == port) { 3966 found = 1; 3967 break; 3968 } 3969 mdio_addr++; 3970 } 3971 3972 /* 3973 * Second, assign external addresses for XE ports. 3974 */ 3975 if (!found) { 3976 PBMP_XE_ITER(unit, temp_port) { 3977 if (temp_port == port) { 3978 found = 1; 3979 break; 3980 } 3981 mdio_addr++; 3982 } 3983 } 3984 3985 /* 3986 * Finally, assign external adddresses for HG ports. 3987 */ 3988 if (!found) { 3989 PBMP_HG_ITER(unit, temp_port) { 3990 if (temp_port == port) { 3991 found = 1; 3992 break; 3993 } 3994 mdio_addr++; 3995 } 3996 } 3997 3998 *phy_addr = mdio_addr + 0x40; 3999 *phy_addr_int = port + 0xc0 + phy_addr_adjust; 4000 4001 if (SOC_IS_SC_CQ(unit)) { 4002 *phy_addr_int = port + 0xc0; 4003 *phy_addr = port + 0x41; 4004 } 4005 if (SAL_BOOT_QUICKTURN) { 4006 *phy_addr = port + 0x41; 4007 if (SOC_IS_SCORPION(unit)) { 4008 /* Skip over CMIC at port 0 */ 4009 *phy_addr -= 1; 4010 } 4011 } 4012 } else { 4013 /* 4014 * Internal Serdes (Internal sel bit 0x80) on GPORT MDIO bus(0x00) 4015 * External Phy (Internal sel bit 0x00) on GPORT MDIO bus(0x00) 4016 */ 4017 *phy_addr = port + 1 + phy_addr_adjust; 4018 *phy_addr_int = port + 0x80 + phy_addr_adjust; 4019 if (SOC_IS_SC_CQ(unit)) { 4020 *phy_addr_int = port + 0xc0; 4021 *phy_addr = port + 0x40; 4022 } 4023 } 4024 } 4025 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 4026 4027 #ifdef BCM_HAWKEYE_SUPPORT 4028 static void 4029 _hawkeye_phy_addr_default(int unit, int port, 4030 uint16 *phy_addr, uint16 *phy_addr_int) 4031 { 4032 static const uint16 _soc_phy_addr_bcm53314_a0[] = { 4033 0x80, 0x0, /* Port 0 (cmic) N/A */ 4034 0x81, 0x0, /* Port 1 ( ge0) ExtBus=0 ExtAddr=0x01 */ 4035 0x82, 0x0, /* Port 2 ( ge1) ExtBus=0 ExtAddr=0x02 */ 4036 0x83, 0x0, /* Port 3 ( ge2) ExtBus=0 ExtAddr=0x03 */ 4037 0x84, 0x0, /* Port 4 ( ge3) ExtBus=0 ExtAddr=0x04 */ 4038 0x85, 0x0, /* Port 5 ( ge4) ExtBus=0 ExtAddr=0x05 */ 4039 0x86, 0x0, /* Port 6 ( ge5) ExtBus=0 ExtAddr=0x06 */ 4040 0x87, 0x0, /* Port 7 ( ge6) ExtBus=0 ExtAddr=0x07 */ 4041 0x88, 0x0, /* Port 8 ( ge7) ExtBus=0 ExtAddr=0x08 */ 4042 0x09, 0x89, /* Port 9 ( ge8) ExtBus=0 ExtAddr=0x09 IntBus=0 IntAddr=0x09 */ 4043 0x0a, 0x89, /* Port 10 ( ge9) ExtBus=0 ExtAddr=0x0a IntBus=0 IntAddr=0x09 */ 4044 0x0b, 0x89, /* Port 11 (ge10) ExtBus=0 ExtAddr=0x0b IntBus=0 IntAddr=0x09 */ 4045 0x0c, 0x89, /* Port 12 (ge11) ExtBus=0 ExtAddr=0x0c IntBus=0 IntAddr=0x09*/ 4046 0x0d, 0x89, /* Port 13 (ge12) ExtBus=0 ExtAddr=0x0d IntBus=0 IntAddr=0x09 */ 4047 0x0e, 0x89, /* Port 14 (ge13) ExtBus=0 ExtAddr=0x0e IntBus=0 IntAddr=0x09 */ 4048 0x0f, 0x89, /* Port 15 (ge14) ExtBus=0 ExtAddr=0x0f IntBus=0 IntAddr=0x09 */ 4049 0x10, 0x89, /* Port 16 (ge15) ExtBus=0 ExtAddr=0x10 IntBus=0 IntAddr=0x09 */ 4050 0x12, 0x91, /* Port 17 (ge16) ExtBus=0 ExtAddr=0x12 IntBus=0 IntAddr=0x11 */ 4051 0x13, 0x91, /* Port 18 (ge17) ExtBus=0 ExtAddr=0x13 IntBus=0 IntAddr=0x11 */ 4052 0x14, 0x91, /* Port 19 (ge18) ExtBus=0 ExtAddr=0x14 IntBus=0 IntAddr=0x11 */ 4053 0x15, 0x91, /* Port 20 (ge19) ExtBus=0 ExtAddr=0x15 IntBus=0 IntAddr=0x11 */ 4054 0x16, 0x91, /* Port 21 (ge20) ExtBus=0 ExtAddr=0x16 IntBus=0 IntAddr=0x11 */ 4055 0x17, 0x91, /* Port 22 (ge21) ExtBus=0 ExtAddr=0x17 IntBus=0 IntAddr=0x11 */ 4056 0x18, 0x91, /* Port 23 (ge22) ExtBus=0 ExtAddr=0x18 IntBus=0 IntAddr=0x11 */ 4057 0x19, 0x91, /* Port 24 (ge23) ExtBus=0 ExtAddr=0x19 IntBus=0 IntAddr=0x11 */ 4058 }; 4059 4060 uint16 dev_id; 4061 uint8 rev_id; 4062 4063 soc_cm_get_id(unit, &dev_id, &rev_id); 4064 4065 switch (dev_id) { 4066 case BCM53312_DEVICE_ID: 4067 case BCM53313_DEVICE_ID: 4068 case BCM53314_DEVICE_ID: 4069 case BCM53322_DEVICE_ID: 4070 case BCM53323_DEVICE_ID: 4071 case BCM53324_DEVICE_ID: 4072 *phy_addr = _soc_phy_addr_bcm53314_a0[port * 2]; 4073 *phy_addr_int = _soc_phy_addr_bcm53314_a0[port * 2 + 1]; 4074 break; 4075 } 4076 } 4077 #endif /* BCM_HAWKEYE_SUPPORT */ 4078 4079 #ifdef BCM_KATANA_SUPPORT 4080 STATIC void 4081 _katana_phy_addr_default(int unit, int port, 4082 uint16 *phy_addr, uint16 *phy_addr_int) 4083 { 4084 uint16 _katana_phy_int_addr_mxqport[] = { 4085 0xa0, /* Port 25 Int XG Bus=1 IntAddr=0x80 */ 4086 0xa1, /* Port 26 Int XG Bus=1 IntAddr=0x81 */ 4087 0xa2, /* Port 27 Int XG Bus=1 IntAddr=0x82 */ 4088 0xa6, /* Port 28 Int XG Bus=1 IntAddr=0x86 */ 4089 0xa7, /* Port 29 Int XG Bus=1 IntAddr=0x87 */ 4090 0xa8, /* Port 30 Int XG Bus=1 IntAddr=0x88 */ 4091 0xa9, /* Port 31 Int XG Bus=1 IntAddr=0x89 */ 4092 0xa3, /* Port 32 Int XG Bus=1 IntAddr=0x83 */ 4093 0xa4, /* Port 33 Int XG Bus=1 IntAddr=0x84 */ 4094 0xa5, /* Port 34 Int XG Bus=1 IntAddr=0x85 */ 4095 }; 4096 static const uint16 _katana_phy_ext_addr_mxqport[] = { 4097 0x2c, /* Port 25 Ext Bus=1 ExtAddr=0x0c */ 4098 0x30, /* Port 26 Ext Bus=1 ExtAddr=0x10 */ 4099 0x34, /* Port 27 Ext Bus=1 ExtAddr=0x14 */ 4100 0x38, /* Port 28 Ext Bus=1 ExtAddr=0x18 */ 4101 0x39, /* Port 29 Ext Bus=1 ExtAddr=0x19 */ 4102 0x3a, /* Port 30 Ext Bus=1 ExtAddr=0x1a */ 4103 0x3b, /* Port 31 Ext Bus=1 ExtAddr=0x1b */ 4104 0x35, /* Port 32 Ext Bus=1 ExtAddr=0x15 */ 4105 0x36, /* Port 33 Ext Bus=1 ExtAddr=0x16 */ 4106 0x37, /* Port 34 Ext Bus=1 ExtAddr=0x17 */ 4107 }; 4108 4109 uint16 dev_id; 4110 uint8 rev_id; 4111 soc_pbmp_t pbmp_valid; 4112 int local_port = 0 ; 4113 int mxq2cnt = 4; 4114 int mxq3cnt = 4; 4115 4116 soc_cm_get_id(unit, &dev_id, &rev_id); 4117 pbmp_valid = soc_property_get_pbmp(unit, spn_PBMP_VALID, 0); 4118 4119 SOC_PBMP_ITER (pbmp_valid, local_port) { 4120 if (!SOC_PORT_VALID(unit,port)) { 4121 continue; 4122 } 4123 if ((local_port == 27) || (local_port == 32) || 4124 (local_port == 33) || (local_port == 34)) { 4125 mxq2cnt--; 4126 } 4127 if ((local_port == 28) || (local_port == 29) || 4128 (local_port == 30) || (local_port == 31)) { 4129 mxq3cnt--; 4130 } 4131 } 4132 if ((mxq2cnt != 4) && (!SOC_PORT_VALID(unit, 27))) { 4133 _katana_phy_int_addr_mxqport[27-25] = 0xa2; 4134 _katana_phy_int_addr_mxqport[32-25] = 0xa2; 4135 _katana_phy_int_addr_mxqport[33-25] = 0xa2; 4136 _katana_phy_int_addr_mxqport[34-25] = 0xa2; 4137 } 4138 if ((mxq3cnt != 4) && (!SOC_PORT_VALID(unit, 28))) { 4139 _katana_phy_int_addr_mxqport[28-25] = 0xa6; 4140 _katana_phy_int_addr_mxqport[29-25] = 0xa6; 4141 _katana_phy_int_addr_mxqport[30-25] = 0xa6; 4142 _katana_phy_int_addr_mxqport[31-25] = 0xa6; 4143 } 4144 4145 if(port < 25) { 4146 *phy_addr_int = (0x80 | port); 4147 *phy_addr = port; 4148 } else { 4149 *phy_addr_int = _katana_phy_int_addr_mxqport[port-25]; 4150 switch (dev_id) { 4151 case BCM56440_DEVICE_ID: 4152 case BCM55440_DEVICE_ID: 4153 case BCM55441_DEVICE_ID: 4154 case BCM56445_DEVICE_ID: 4155 case BCM56448_DEVICE_ID: 4156 case BCM56449_DEVICE_ID: 4157 /* Valid ports 25-28 only */ 4158 *phy_addr = (0x20 | port); /* Bus-1 */ 4159 break; 4160 case BCM56441_DEVICE_ID: 4161 case BCM56446_DEVICE_ID: 4162 case BCM56443_DEVICE_ID: 4163 case BCM56240_DEVICE_ID: 4164 case BCM56241_DEVICE_ID: 4165 case BCM56242_DEVICE_ID: 4166 case BCM56243_DEVICE_ID: 4167 case BCM56245_DEVICE_ID: 4168 case BCM56246_DEVICE_ID: 4169 *phy_addr = _katana_phy_ext_addr_mxqport[port-25]; 4170 break; 4171 case BCM56442_DEVICE_ID: 4172 case BCM56447_DEVICE_ID: 4173 /* Shouldn't be here.. 442 only has 16 ports */ 4174 break; 4175 default: 4176 4177 break; 4178 } 4179 } 4180 } 4181 #endif /* BCM_KATANA_SUPPORT */ 4182 #ifdef BCM_SABER2_SUPPORT 4183 void 4184 _saber2_phy_addr_default(int unit, int port, 4185 uint16 *phy_addr, uint16 *phy_addr_int) 4186 { 4187 uint8 mdio_bus_ring=0; 4188 uint8 mdio_phy_addr=0; 4189 4190 static int8 mapped_phy_addr[28+1]={0, 4191 /* Bus=0 PhySical Port versus Phy Addresses mapping */ 4192 0x01, 0x01, 0x01,0x01, /* VIPER 0=1.. 4 */ 4193 0x05, 0x05, 0x05,0x05, /* VIPER 1=5.. 8 */ 4194 0x09, 0x09, 0x09,0x09, /* VIPER 2=9.. 12 */ 4195 0x0d, 0x0d, 0x0d,0x0d, /* VIPER 3=13..16 */ 4196 0x11, 0x11, 0x11,0x11, /* VIPER 4=17..20 */ 4197 0x15, 0x15, 0x15,0x15, /* VIPER 5=21..24 */ 4198 /* Bus=1 PhySical Port versus Phy Addresses mapping */ 4199 0x01, 0x01, 0x01,0x01 /* EAGLE =1.. 4 */ 4200 }; 4201 if ((port < 0 ) || (port > (sizeof(mapped_phy_addr)-1))) { 4202 LOG_CLI((BSL_META_U(unit, 4203 "Internal Error: Invalid port=%d \n"),port)); 4204 return; 4205 } 4206 mdio_bus_ring = (port - 1) / 24; 4207 mdio_phy_addr = mapped_phy_addr[port] ; 4208 /* As per CMIC_CMCx_MIIM_PARAM */ 4209 *phy_addr_int = (1<<7) | (mdio_bus_ring << 5) | mdio_phy_addr; 4210 *phy_addr = /* (0<<7) */ (mdio_bus_ring << 5) | mdio_phy_addr; 4211 } 4212 #endif 4213 4214 #ifdef BCM_METROLITE_SUPPORT 4215 void 4216 _ml_phy_addr_default(int unit, int port, 4217 uint16 *phy_addr, uint16 *phy_addr_int) 4218 { 4219 uint8 mdio_bus_ring=0; 4220 uint8 mdio_phy_addr=0; 4221 4222 static int8 mapped_phy_addr[12+1]={0, 4223 /* Bus=0 PhySical Port versus Phy Addresses mapping */ 4224 0x01, 0x01, 0x01, 0x01, /* VIPER 0=1.. 4 */ 4225 /* Bus=4 PhySical Port versus Phy Addresses mapping */ 4226 0x01, 0x01, 0x01, 0x01, /* EAGLE =1.. 4 */ 4227 0x05, 0x05, 0x05, 0x05 /* EAGLE =5.. 8 */ 4228 }; 4229 if ((port < 0 ) || (port > (sizeof(mapped_phy_addr)-1))) { 4230 LOG_CLI((BSL_META_U(unit, 4231 "Internal Error: Invalid port=%d \n"),port)); 4232 return; 4233 } 4234 4235 if (port > 0 && port < 5) { 4236 mdio_bus_ring = 0; 4237 } else { 4238 mdio_bus_ring = 1; 4239 } 4240 4241 mdio_phy_addr = mapped_phy_addr[port] ; 4242 /* As per CMIC_CMCx_MIIM_PARAM */ 4243 *phy_addr_int = (1<<7) | (mdio_bus_ring << 5) | mdio_phy_addr; 4244 4245 /* external phy address encoding */ 4246 *phy_addr = (1<<4) | (port - mdio_phy_addr); 4247 4248 LOG_VERBOSE(BSL_LS_SOC_PHY, (BSL_META_U(unit, 4249 "_ml_phy_addr_default: port=%d phy_int=0x%x phy_ext=0x%x\n"), 4250 port, *phy_addr_int, *phy_addr)); 4251 } 4252 #endif 4253 4254 #ifdef BCM_KATANA2_SUPPORT 4255 void 4256 _katana2_phy_addr_default(int unit, int port, 4257 uint16 *phy_addr, uint16 *phy_addr_int) 4258 { 4259 uint8 mdio_bus_ring=0; 4260 uint8 mdio_phy_addr=0; 4261 uint8 mxqblock=0; 4262 bcmMxqConnection_t connection_mode = bcmMqxConnectionUniCore; 4263 #if 0 4264 /* Actual Addressing scheme but Looks like WARP Core Not happy with 4265 independent lane mode and works with AER scheme only*/ 4266 /* Keeping this block for JUST REFERENCE */ 4267 static int8 mapped_phy_addr[40+1]={0, 4268 /* Bus=0 PhySical Port versus Phy Addresses mapping */ 4269 /* MXQ0=1..4(0x1..0x4) MXQ1=5..8(0x5..0x8) MXQ2=9..12(0x9..0xc) */ 4270 /* MXQ3=13..16(0xd..0x10) MXQ4=17..20(0x11..0x14) MXQ5=21..24(0x15..0x18) */ 4271 0x01, 0x02, 0x03,0x04, /* MXQ 0=1.. 4 */ 4272 0x05, 0x06, 0x07,0x08, /* MXQ 1=5.. 8 */ 4273 0x09, 0x0a, 0x0b,0x0c, /* MXQ 2=9.. 12 */ 4274 0x0d, 0x0e, 0x0f,0x10, /* MXQ 3=13..16 */ 4275 0x11, 0x12, 0x13,0x14, /* MXQ 4=17..20 */ 4276 0x15, 0x16, 0x17,0x18, /* MXQ 5=21..24 */ 4277 /* Bus=1 PhySical Port versus Phy Addresses mapping */ 4278 /* MXQ6=25,35..37(0x1..0x4) MXQ7=26,38..40(0x5..0x8) */ 4279 /* MXQ8=27,32..34(0x9..0xb) MXQ9=28,35..37(0xc..0x10) */ 4280 0x01, 0x05, 0x09,0x0d, /* 25..28 */ 4281 0x0e, 0x0f, 0x10,0x0a, /* 29..32 */ 4282 0x0b, 0x0c, 0x02,0x03 ,/* 33..36 */ 4283 0x04, 0x06, 0x07,0x08 ,/* 37..40 */ 4284 }; 4285 #else 4286 static int8 mapped_phy_addr[40+1]={0, 4287 /* Bus=0 PhySical Port versus Phy Addresses mapping */ 4288 /* MXQ0=1..4(0x1..0x4) MXQ1=5..8(0x5..0x8) MXQ2=9..12(0x9..0xc) */ 4289 /* MXQ3=13..16(0xd..0x10) MXQ4=17..20(0x11..0x14) MXQ5=21..24(0x15..0x18) */ 4290 0x01, 0x02, 0x03,0x04, /* MXQ 0=1.. 4 */ 4291 0x05, 0x06, 0x07,0x08, /* MXQ 1=5.. 8 */ 4292 0x09, 0x0a, 0x0b,0x0c, /* MXQ 2=9.. 12 */ 4293 0x0d, 0x0e, 0x0f,0x10, /* MXQ 3=13..16 */ 4294 0x11, 0x12, 0x13,0x14, /* MXQ 4=17..20 */ 4295 0x15, 0x16, 0x17,0x18, /* MXQ 5=21..24 */ 4296 /* Bus=1 PhySical Port versus Phy Addresses mapping */ 4297 /* MXQ6=25,35..37(0x1..0x4) MXQ7=26,38..40(0x5..0x8) */ 4298 /* MXQ8=27,32..34(0x9..0xb) MXQ9=28,35..37(0xc..0x10) */ 4299 0x01, 0x05, /* 25..26 */ 4300 0x09, /* WC0:27 */ 4301 0x0d, /* WC1:28 */ 4302 0x0d, 0x0d, 0x0d, /* WC1:29..31 */ 4303 0x09, 0x09, 0x09, /* WC0:32..34 */ 4304 0x02,0x03 ,/* 35..36 */ 4305 0x04, 0x06, 0x07,0x08 ,/* 37..40 */ 4306 }; 4307 4308 #endif 4309 if ((port < 0 ) || (port > (sizeof(mapped_phy_addr)-1))) { 4310 LOG_CLI((BSL_META_U(unit, 4311 "Internal Error: Invalid port=%d \n"),port)); 4312 return; 4313 } 4314 if (SOC_INFO(unit).olp_port[0] && (port == KT2_OLP_PORT)) { 4315 mdio_bus_ring = 2; 4316 mdio_phy_addr = 3; 4317 } else { 4318 if (soc_katana2_get_port_mxqblock( unit,port,&mxqblock) != SOC_E_NONE) { 4319 LOG_CLI((BSL_META_U(unit, 4320 "Unable to get mxqblock : Invalid port=%d \n"), port)); 4321 return; 4322 } 4323 if (soc_katana2_get_phy_connection_mode( 4324 unit, port,mxqblock,&connection_mode) != SOC_E_NONE) { 4325 LOG_CLI((BSL_META_U(unit, 4326 "Unable to get connection mode:Invalid port=%d\n"), port)); 4327 return; 4328 } 4329 if ((mxqblock == 6) && 4330 (connection_mode == bcmMqxConnectionWarpCore)) { 4331 if (port == 25) { 4332 port = 32; 4333 } 4334 if (port == 36) { 4335 port = 34; 4336 } 4337 } 4338 if ((mxqblock == 7) && 4339 (connection_mode == bcmMqxConnectionWarpCore)) { 4340 if (port == 26) { 4341 port = 29; 4342 } 4343 if (port == 39) { 4344 port = 31; 4345 } 4346 } 4347 mdio_bus_ring = (port - 1) / 24; 4348 mdio_phy_addr = mapped_phy_addr[port] ; 4349 } 4350 4351 /* As per CMIC_CMCx_MIIM_PARAM */ 4352 *phy_addr_int = (1<<7) | (mdio_bus_ring << 5) | mdio_phy_addr; 4353 *phy_addr = /* (0<<7) */ (mdio_bus_ring << 5) | mdio_phy_addr; 4354 } 4355 #endif /* BCM_KATANA2_SUPPORT */ 4356 4357 4358 4359 /* 4360 * Function: 4361 * _soc_phy_addr_default 4362 * Purpose: 4363 * Return the default PHY addresses used to initialize the PHY map 4364 * for a port. 4365 * Parameters: 4366 * unit - StrataSwitch unit number 4367 * phy_addr - (OUT) Outer PHY address 4368 * phy_addr_int - (OUT) Intermediate PHY address, 0xff if none 4369 */ 4370 4371 static void 4372 _soc_phy_addr_default(int unit, int port, 4373 uint16 *phy_addr, uint16 *phy_addr_int) 4374 { 4375 4376 #ifdef BCM_XGS12_FABRIC_SUPPORT 4377 if (SOC_IS_XGS12_FABRIC(unit)) { 4378 _XGS12_FABRIC_PHY_ADDR_DEFAULT(unit, port, phy_addr, phy_addr_int); 4379 } else 4380 #endif /* BCM_XGS12_FABRIC_SUPPORT */ 4381 4382 #ifdef BCM_RAPTOR_SUPPORT 4383 if (SOC_IS_RAPTOR(unit) || SOC_IS_RAVEN(unit)) { 4384 _RAPTOR_PHY_ADDR_DEFAULT(unit, port, phy_addr, phy_addr_int); 4385 } else 4386 #endif /* BCM_RAPTOR_SUPPORT */ 4387 4388 #if defined(BCM_ENDURO_SUPPORT) 4389 if (SOC_IS_ENDURO(unit)) { 4390 _enduro_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4391 } else 4392 #endif /* BCM_ENDURO_SUPPORT */ 4393 4394 #if defined(BCM_HURRICANE1_SUPPORT) 4395 if (SOC_IS_HURRICANE(unit)) { 4396 _hurricane_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4397 } else 4398 #endif /* BCM_HURRICANE1_SUPPORT */ 4399 4400 #if defined(BCM_HURRICANE2_SUPPORT) 4401 if (SOC_IS_HURRICANE2(unit)) { 4402 _hurricane2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4403 } else 4404 #endif /* BCM_HURRICANE2_SUPPORT */ 4405 4406 #if defined(BCM_GREYHOUND_SUPPORT) 4407 if (SOC_IS_GREYHOUND(unit)) { 4408 _greyhound_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4409 } else 4410 #endif /* BCM_GREYHOUND_SUPPORT */ 4411 4412 #if defined(BCM_HURRICANE3_SUPPORT) 4413 if (SOC_IS_HURRICANE3(unit)) { 4414 if (soc_feature(unit, soc_feature_wh2)) { 4415 _wolfhound2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4416 } else { 4417 _hurricane3_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4418 } 4419 } else 4420 #endif /* BCM_HURRICANE3_SUPPORT */ 4421 4422 #if defined(BCM_GREYHOUND2_SUPPORT) 4423 if (SOC_IS_GREYHOUND2(unit)) { 4424 _greyhound2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4425 } else 4426 #endif /* BCM_GREYHOUND2_SUPPORT */ 4427 4428 #if defined(BCM_HELIX4_SUPPORT) 4429 if (SOC_IS_HELIX4(unit)) { 4430 _helix4_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4431 } else 4432 #endif /* BCM_HELIX4_SUPPORT */ 4433 4434 #if defined(BCM_TRIUMPH3_SUPPORT) 4435 if (SOC_IS_TRIUMPH3(unit)) { 4436 _triumph3_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4437 } else 4438 #endif /* BCM_TRIUMPH3_SUPPORT */ 4439 4440 #if defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_APOLLO_SUPPORT) || \ 4441 defined(BCM_VALKYRIE2_SUPPORT) 4442 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 4443 SOC_IS_VALKYRIE2(unit)) { 4444 _triumph2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4445 } else 4446 #endif /* BCM_TRIUMPH2_SUPPORT */ 4447 4448 #ifdef BCM_TRIUMPH_SUPPORT 4449 if (SOC_IS_TRIUMPH(unit)) { 4450 _triumph_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4451 } else 4452 #endif /* BCM_TRIUMPH_SUPPORT */ 4453 4454 #ifdef BCM_VALKYRIE_SUPPORT 4455 if (SOC_IS_VALKYRIE(unit)) { 4456 _valkyrie_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4457 } else 4458 #endif /* BCM_VALKYRIE_SUPPORT */ 4459 4460 #ifdef BCM_DFE_SUPPORT 4461 if (SOC_IS_DFE(unit)) { 4462 _dfe_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4463 } else 4464 #endif /* BCM_DFE_SUPPORT */ 4465 4466 #ifdef BCM_PETRA_SUPPORT 4467 if (SOC_IS_DPP(unit)) { 4468 _dpp_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4469 } else 4470 #endif /* BCM_PETRA_SUPPORT */ 4471 4472 #ifdef BCM_TOMAHAWK_SUPPORT 4473 #ifdef BCM_TOMAHAWK3_SUPPORT 4474 if (SOC_IS_TOMAHAWK3(unit)) { 4475 _tomahawk3_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4476 } else 4477 #endif /* BCM_TOMAHAWK3_SUPPORT */ 4478 #ifdef BCM_TOMAHAWK2_SUPPORT 4479 if (SOC_IS_TOMAHAWK2(unit)) { 4480 _tomahawk2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4481 } else 4482 #endif /* BCM_TOMAHAWK2_SUPPORT */ 4483 if (SOC_IS_TOMAHAWK(unit)) { 4484 _tomahawk_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4485 } else 4486 #endif /* BCM_TOMAHAWK_SUPPORT */ 4487 #ifdef BCM_TRIDENT3_SUPPORT 4488 if (SOC_IS_TRIDENT3X(unit)) { 4489 _trident3_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4490 } else 4491 #endif /* BCM_TRIDENT3_SUPPORT */ 4492 4493 #ifdef BCM_APACHE_SUPPORT 4494 if (SOC_IS_APACHE(unit)) { 4495 _apache_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4496 } else 4497 #endif /* BCM_APACHE_SUPPORT */ 4498 #ifdef BCM_TRIDENT_SUPPORT 4499 #ifdef BCM_TRIDENT2_SUPPORT 4500 if (SOC_IS_TD2_TT2(unit)) { 4501 _trident2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4502 } else 4503 #endif /* BCM_TRIDENT2_SUPPORT */ 4504 if (SOC_IS_TD_TT(unit)) { 4505 _trident_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4506 } else 4507 #endif /* BCM_TRIDENT_SUPPORT */ 4508 #ifdef BCM_TRIDENT2PLUS_SUPPORT 4509 if (SOC_IS_TRIDENT2PLUS(unit)) { 4510 _trident2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4511 } else 4512 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 4513 4514 #ifdef BCM_SHADOW_SUPPORT 4515 if (SOC_IS_SHADOW(unit)) { 4516 _shadow_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4517 } else 4518 #endif /* BCM_SHADOW_SUPPORT */ 4519 4520 #ifdef BCM_SCORPION_SUPPORT 4521 if (SOC_IS_SCORPION(unit) && 4522 _scorpion_phy_addr_default(unit, port, phy_addr, phy_addr_int)) { 4523 } else 4524 #endif /* BCM_SCORPION_SUPPORT */ 4525 4526 #ifdef BCM_HAWKEYE_SUPPORT 4527 if (SOC_IS_HAWKEYE(unit)) { 4528 _hawkeye_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4529 } else 4530 #endif /* BCM_HAWKEYE_SUPPORT */ 4531 4532 #ifdef BCM_KATANA_SUPPORT 4533 if (SOC_IS_KATANA(unit)) { 4534 _katana_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4535 } else 4536 #endif /* BCM_KATANA_SUPPORT */ 4537 4538 #ifdef BCM_METROLITE_SUPPORT 4539 if (SOC_IS_METROLITE(unit)) { 4540 _ml_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4541 } else 4542 #endif /* BCM_METROLITE)SUPPORT */ 4543 4544 #ifdef BCM_SABER2_SUPPORT 4545 if (SOC_IS_SABER2(unit)) { 4546 _saber2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4547 } else 4548 #endif /* BCM_SABER2_SUPPORT */ 4549 4550 #ifdef BCM_KATANA2_SUPPORT 4551 if (SOC_IS_KATANA2(unit)) { 4552 _katana2_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4553 } else 4554 #endif /* BCM_KATANA2_SUPPORT */ 4555 4556 #ifdef BCM_XGS3_SWITCH_SUPPORT 4557 if (SOC_IS_XGS3_SWITCH(unit)) { 4558 _xgs3_phy_addr_default(unit, port, phy_addr, phy_addr_int); 4559 } else 4560 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 4561 { 4562 *phy_addr = port + 1; 4563 *phy_addr_int = 0xff; 4564 } 4565 4566 /* 4567 * Override the calculated address(es) with the per-port properties 4568 */ 4569 *phy_addr = soc_property_port_get(unit, port, 4570 spn_PORT_PHY_ADDR, 4571 *phy_addr); 4572 } 4573 4574 int 4575 soc_phy_deinit(int unit) 4576 { 4577 if (port_phy_addr[unit] != NULL) { 4578 sal_free(port_phy_addr[unit]); 4579 } 4580 4581 port_phy_addr[unit] = NULL; 4582 return SOC_E_NONE; 4583 } 4584 4585 /* 4586 * Function: 4587 * soc_phy_init 4588 * Purpose: 4589 * Initialize PHY software subsystem. 4590 * Parameters: 4591 * unit - StrataSwitch unit number 4592 * Returns: 4593 * SOC_E_XXX 4594 */ 4595 int 4596 soc_phy_init(int unit) 4597 { 4598 uint16 phy_addr=0, phy_addr_int=0; 4599 soc_port_t port; 4600 4601 if (_phys_in_table < 0) { 4602 _init_phy_table(); 4603 } 4604 4605 if (port_phy_addr[unit] == NULL) { 4606 port_phy_addr[unit] = sal_alloc(sizeof(port_phy_addr_t) * 4607 SOC_MAX_NUM_PORTS, 4608 "port_phy_addr"); 4609 if (port_phy_addr[unit] == NULL) { 4610 return SOC_E_MEMORY; 4611 } 4612 } 4613 4614 sal_memset(port_phy_addr[unit], 0, 4615 sizeof(port_phy_addr_t) * SOC_MAX_NUM_PORTS); 4616 4617 PBMP_PORT_ITER(unit, port) { 4618 _soc_phy_addr_default(unit, port, &phy_addr, &phy_addr_int); 4619 4620 SOC_IF_ERROR_RETURN 4621 (soc_phy_cfg_addr_set(unit,port,0, phy_addr)); 4622 SOC_IF_ERROR_RETURN 4623 (soc_phy_cfg_addr_set(unit,port,SOC_PHY_INTERNAL, phy_addr_int)); 4624 4625 PHY_ADDR(unit, port) = phy_addr; 4626 PHY_ADDR_INT(unit, port) = phy_addr_int; 4627 } 4628 4629 return SOC_E_NONE; 4630 } 4631 4632 /* 4633 * Function: 4634 * soc_phy_port_init 4635 * Purpose: 4636 * Initialize PHY software for a single port. 4637 * Parameters: 4638 * unit - unit number 4639 * port - port number 4640 * Returns: 4641 * SOC_E_XXX 4642 */ 4643 int 4644 soc_phy_port_init(int unit, soc_port_t port) 4645 { 4646 uint16 phy_addr=0, phy_addr_int=0; 4647 4648 _soc_phy_addr_default(unit, port, &phy_addr, &phy_addr_int); 4649 4650 SOC_IF_ERROR_RETURN 4651 (soc_phy_cfg_addr_set(unit,port,0, phy_addr)); 4652 SOC_IF_ERROR_RETURN 4653 (soc_phy_cfg_addr_set(unit,port,SOC_PHY_INTERNAL, phy_addr_int)); 4654 4655 PHY_ADDR(unit, port) = phy_addr; 4656 PHY_ADDR_INT(unit, port) = phy_addr_int; 4657 4658 4659 return SOC_E_NONE; 4660 } 4661 4662 /* 4663 * Function: 4664 * soc_phy_add_entry 4665 * Purpose: 4666 * Add an entry to the PHY table 4667 * Parameters: 4668 * entry - pointer to the entry 4669 * Returns: 4670 * SOC_E_NONE - no error 4671 * SOC_E_INIT - not initialized 4672 * SOC_E_MEMORY - not no more space in table. 4673 */ 4674 4675 int 4676 soc_phy_add_entry(soc_phy_table_t *entry) 4677 { 4678 assert(_phys_in_table >= 0); /* Fatal if not already inited */ 4679 4680 if (_phys_in_table >= _MAX_PHYS) { 4681 return SOC_E_MEMORY; 4682 } 4683 4684 phy_table[_phys_in_table++] = entry; 4685 4686 return SOC_E_NONE; 4687 } 4688 4689 #if defined(INCLUDE_SERDES_COMBO65) 4690 /* 4691 * Function: 4692 * _chk_serdescombo65 4693 * Purpose: 4694 * Check function for Raven Combo SerDes PHYs 4695 * Parameters: 4696 * See soc_phy_ident_f 4697 * *pi is an output parameter filled with PHY info. 4698 * Returns: 4699 * TRUE if this PHY matches. 4700 * FALSE otherwise. 4701 * Notes: 4702 * Sets the phy_info structure for this port. 4703 */ 4704 4705 static int 4706 _chk_serdescombo65(int unit, soc_port_t port, soc_phy_table_t *my_entry, 4707 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 4708 { 4709 COMPILER_REFERENCE(unit); 4710 4711 if (SOC_IS_RAVEN(unit)) { 4712 if (port == 1 || port == 2 || port == 4 || port == 5) { 4713 pi->phy_name = my_entry->phy_name; 4714 return TRUE; 4715 } 4716 } 4717 4718 4719 return FALSE; 4720 } 4721 4722 #endif /* INCLUDE_SERDES_COMBO65 */ 4723 4724 #if defined(INCLUDE_XGXS_16G) 4725 /* 4726 * Function: 4727 * _chk_xgxs16g1l 4728 * Purpose: 4729 * Standard check function for PHYs (see soc_phy_ident_f) 4730 * Parameters: 4731 * See soc_phy_ident_f 4732 * *pi is an output parameter filled with PHY info. 4733 * Returns: 4734 * TRUE if this PHY matches. 4735 * FALSE otherwise. 4736 * Notes: 4737 * Sets the phy_info structure for this port. 4738 */ 4739 4740 static int 4741 _chk_xgxs16g1l(int unit, soc_port_t port, soc_phy_table_t *my_entry, 4742 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 4743 { 4744 if (my_entry->myNum == _phy_ident_type_get(phy_id0, phy_id1)) { 4745 #ifdef BCM_KATANA_SUPPORT 4746 if (SOC_IS_KATANAX(unit) && IS_GE_PORT(unit,port)) { 4747 uint32 rval; 4748 int port_mode = 2; 4749 4750 if (IS_MXQ_PORT(unit,port)) { 4751 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, port, &rval)); 4752 port_mode = soc_reg_field_get(unit, XPORT_MODE_REGr, rval, PHY_PORT_MODEf); 4753 } 4754 if (port_mode) { 4755 return TRUE; 4756 } else { 4757 return FALSE; 4758 } 4759 } else 4760 #endif /* BCM_KATANA_SUPPORT */ 4761 4762 #ifdef BCM_TRIUMPH3_SUPPORT 4763 if (SOC_IS_TRIUMPH3(unit) && IS_GE_PORT(unit, port)) { 4764 pi->phy_name = my_entry->phy_name; 4765 return TRUE; 4766 } 4767 #endif 4768 4769 if (SOC_IS_SCORPION(unit) && !IS_GX_PORT(unit, port)) { 4770 pi->phy_name = my_entry->phy_name; 4771 return TRUE; 4772 } 4773 4774 #ifdef BCM_ENDURO_SUPPORT 4775 if (SOC_IS_ENDURO(unit) && (port > 25) && IS_GE_PORT(unit,port)) { 4776 pi->phy_name = my_entry->phy_name; 4777 return TRUE; 4778 } 4779 #endif /* BCM_ENDURO_SUPPORT */ 4780 4781 4782 4783 } 4784 return FALSE; 4785 } 4786 #endif /* INCLUDE_XGXS_16G */ 4787 #if defined(INCLUDE_XGXS_VIPER) 4788 /* 4789 * Function: 4790 * _chk_viper 4791 * Purpose: 4792 * Standard check function for VIPER PHYs (see soc_phy_ident_f) 4793 * Parameters: 4794 * See soc_phy_ident_f 4795 * *pi is an output parameter filled with PHY info. 4796 * Returns: 4797 * TRUE if this PHY matches. 4798 * FALSE otherwise. 4799 * Notes: 4800 * Sets the phy_info structure for this port. 4801 */ 4802 static int 4803 _chk_viper(int unit, soc_port_t port, soc_phy_table_t *my_entry, 4804 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 4805 { 4806 if (SOC_IS_SABER2(unit) || SOC_IS_GREYHOUND2(unit) || 4807 soc_feature(unit, soc_feature_wh2)) { 4808 return TRUE; 4809 } 4810 return _chk_phy(unit, port, my_entry, phy_id0, phy_id1, pi); 4811 } 4812 #endif /* INCLUDE_XGXS_VIPER */ 4813 4814 #if defined(INCLUDE_XGXS_WCMOD) 4815 /* 4816 * Function: 4817 * _chk_wcmod 4818 * Purpose: 4819 * Standard check function for PHYs (see soc_phy_ident_f) 4820 * Parameters: 4821 * See soc_phy_ident_f 4822 * *pi is an output parameter filled with PHY info. 4823 * Returns: 4824 * TRUE if this PHY matches. 4825 * FALSE otherwise. 4826 * Notes: 4827 * Sets the phy_info structure for this port. 4828 */ 4829 4830 static int 4831 _chk_wcmod(int unit, soc_port_t port, soc_phy_table_t *my_entry, 4832 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 4833 { 4834 if (SOC_IS_TRIUMPH3(unit)) { 4835 if (IS_GE_PORT(unit, port) && 4836 !soc_property_port_get(unit, port, "phy_wcmod", 1)) { 4837 /* Allow debug fallback to legacy XGXS16g1l PHY driver */ 4838 return FALSE; 4839 } 4840 } 4841 4842 return _chk_phy(unit, port, my_entry, phy_id0, phy_id1, pi); 4843 } 4844 #endif /* INCLUDE_XGXS_WCMOD */ 4845 4846 #if defined(INCLUDE_PHY_82109) 4847 /* 4848 * Function: 4849 * _chk_huracan 4850 * Purpose: 4851 * Standard check function for Huracan PHY's (see soc_phy_ident_f) 4852 * Parameters: 4853 * See soc_phy_ident_f 4854 * *pi is an output parameter filled with PHY info. 4855 * Returns: 4856 * TRUE if this PHY matches. 4857 * FALSE otherwise. 4858 * Notes: 4859 * Sets the phy_info structure for this port. 4860 */ 4861 static int 4862 _chk_huracan(int unit, soc_port_t port, soc_phy_table_t *my_entry, 4863 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 4864 { 4865 COMPILER_REFERENCE(unit); 4866 4867 if (my_entry->myNum == _phy_id_BCM82109 ){ 4868 switch (phy_id0) { 4869 case 0x2109: 4870 case 0x2108: 4871 case 0x2112: 4872 case 0x2181: 4873 pi->phy_name = my_entry->phy_name; 4874 return TRUE; 4875 default: 4876 break; 4877 } 4878 } 4879 4880 return FALSE; 4881 } 4882 #endif 4883 4884 #ifdef INCLUDE_SERDES_65LP 4885 /* 4886 * Function: 4887 * _chk_serdes_65lp 4888 * Purpose: 4889 * Standard check function for serdes 65LP 4890 * Parameters: 4891 * See soc_phy_ident_f 4892 * *pi is an output parameter filled with PHY info. 4893 * Returns: 4894 * TRUE if this PHY matches. 4895 * FALSE otherwise. 4896 * Notes: 4897 * Sets the phy_info structure for this port. 4898 */ 4899 static int 4900 _chk_serdes_65lp(int unit, soc_port_t port, soc_phy_table_t *my_entry, 4901 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 4902 { 4903 COMPILER_REFERENCE(unit); 4904 if (my_entry->myNum == _phy_ident_type_get(phy_id0, phy_id1)) { 4905 pi->phy_name = my_entry->phy_name; 4906 return TRUE; 4907 } 4908 4909 return FALSE; 4910 } 4911 4912 4913 #endif 4914 4915 4916 4917 4918 /* 4919 * Function: 4920 * _chk_phy 4921 * Purpose: 4922 * Standard check function for PHYs (see soc_phy_ident_f) 4923 * Parameters: 4924 * See soc_phy_ident_f 4925 * *pi is an output parameter filled with PHY info. 4926 * Returns: 4927 * TRUE if this PHY matches. 4928 * FALSE otherwise. 4929 * Notes: 4930 * Sets the phy_info structure for this port. 4931 */ 4932 4933 static int 4934 _chk_phy(int unit, soc_port_t port, soc_phy_table_t *my_entry, 4935 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 4936 { 4937 COMPILER_REFERENCE(unit); 4938 4939 if (my_entry->myNum == _phy_ident_type_get(phy_id0, phy_id1)) { 4940 pi->phy_name = my_entry->phy_name; 4941 return TRUE; 4942 } 4943 4944 return FALSE; 4945 } 4946 4947 #if defined(INCLUDE_PHY_SIMUL) 4948 #if defined(SIM_ALL_PHYS) 4949 #define USE_SIMULATION_PHY(unit, port) (TRUE) 4950 #else 4951 #define USE_SIMULATION_PHY(unit, port) \ 4952 (soc_property_port_get(unit, port, spn_PHY_SIMUL, 0)) 4953 #endif 4954 #else 4955 #define USE_SIMULATION_PHY(unit, port) (FALSE) 4956 #endif 4957 4958 /* 4959 * Function: 4960 * _chk_null 4961 * Purpose: 4962 * Check function for NULL phys. 4963 * Returns: 4964 * True if this phy matches. 4965 * False otherwise. 4966 */ 4967 4968 static int 4969 _chk_null(int unit, soc_port_t port, soc_phy_table_t *my_entry, 4970 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 4971 { 4972 #if defined(INCLUDE_CES) 4973 uint16 dev_id; 4974 uint8 rev_id; 4975 #endif 4976 4977 if ((SAL_BOOT_PLISIM && (!SAL_BOOT_RTLSIM && 4978 !USE_SIMULATION_PHY(unit, port))) || 4979 !soc_property_get(unit, spn_PHY_ENABLE, 1) || 4980 soc_property_port_get(unit, port, spn_PHY_NULL, 0) 4981 #ifdef BCM_TRIUMPH3_SUPPORT 4982 || ((SOC_IS_TRIUMPH3(unit) 4983 #ifdef BCM_TRIDENT2_SUPPORT 4984 || SOC_IS_TD2_TT2(unit) 4985 #endif 4986 ) && SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit, all), port)) 4987 #endif 4988 ) { 4989 pi->phy_name = my_entry->phy_name; 4990 4991 return TRUE; 4992 } 4993 4994 #if defined(INCLUDE_CES) 4995 /* 4996 * For CES on the 56441/2/3 where the CES mii port 4997 * is internal and there is no physical phy set the 4998 * phy device to the null phy. 4999 */ 5000 if (soc_feature(unit, soc_feature_ces) && port == 1) { 5001 soc_cm_get_id(unit, &dev_id, &rev_id); 5002 5003 if (dev_id == BCM56441_DEVICE_ID || 5004 dev_id == BCM56442_DEVICE_ID || 5005 dev_id == BCM56443_DEVICE_ID) { 5006 pi->phy_name = my_entry->phy_name; 5007 return TRUE; 5008 } 5009 } 5010 #endif 5011 5012 #if defined(INCLUDE_RCPU) 5013 if (SOC_IS_RCPU_ONLY(unit)) { 5014 pi->phy_name = my_entry->phy_name; 5015 return TRUE; 5016 } 5017 #endif /* INCLUDE_RCPU */ 5018 5019 return FALSE; 5020 } 5021 5022 #if defined(BCM_XGS3_SWITCH_SUPPORT) 5023 /* 5024 * Function: 5025 * _chk_gmii 5026 * Purpose: 5027 * Check function for GMII port. 5028 * Returns: 5029 * True if this phy matches. 5030 * False otherwise. 5031 */ 5032 5033 static int 5034 _chk_gmii(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5035 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5036 { 5037 if (IS_GMII_PORT(unit, port)) { 5038 pi->phy_name = my_entry->phy_name; 5039 5040 return TRUE; 5041 } 5042 5043 return FALSE; 5044 } 5045 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 5046 5047 #if defined(INCLUDE_PHY_SIMUL) 5048 5049 /* 5050 * Function: 5051 * _chk_simul 5052 * Purpose: 5053 * Check function for simulation phys. 5054 * Returns: 5055 * True if this phy matches. 5056 * False otherwise. 5057 */ 5058 5059 static int 5060 _chk_simul(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5061 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5062 { 5063 if (USE_SIMULATION_PHY(unit, port) && !SOC_IS_ARDON(unit)) { 5064 pi->phy_name = my_entry->phy_name; 5065 5066 return TRUE; 5067 } 5068 5069 return FALSE; 5070 } 5071 #endif /* include phy sim */ 5072 5073 #undef USE_SIMULATION_PHY 5074 5075 #ifdef INCLUDE_XGXS_QSGMII65 5076 /* 5077 * Function: 5078 * _chk_qsgmii53314 5079 * Purpose: 5080 * Check for using Internal 53314 SERDES Device 5081 * Returns: 5082 * TRUE if this PHY matches. 5083 * FALSE otherwise. 5084 * Notes: 5085 * This routine should be called after checking for external 5086 * PHYs because it will default the PHY driver to the internal 5087 * SERDES in the absense of any other PHY. 5088 */ 5089 5090 static int 5091 _chk_qsgmii53314(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5092 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5093 { 5094 COMPILER_REFERENCE(my_entry); 5095 COMPILER_REFERENCE(phy_id0); 5096 COMPILER_REFERENCE(phy_id1); 5097 COMPILER_REFERENCE(pi); 5098 5099 if (SOC_IS_HAWKEYE(unit) && port >= 9) { 5100 pi->phy_name = "Phy53314"; 5101 return TRUE; 5102 } 5103 5104 if (IS_GE_PORT(unit, port) && (SOC_IS_HURRICANE(unit) && (port >= 2) && (port <= 25))) { 5105 pi->phy_name = "Phy53314"; 5106 return TRUE; 5107 } 5108 5109 return FALSE; 5110 } 5111 #endif /* INCLUDE_XGXS_QSGMII65 */ 5112 5113 #ifdef INCLUDE_PHY_54680 5114 /* 5115 * Function: 5116 * _chk_qgphy_5332x 5117 * Purpose: 5118 * Check for using 5332x QGPHY Device 5119 * Returns: 5120 * TRUE if this PHY matches. 5121 * FALSE otherwise. 5122 * Notes: 5123 * Because The Id of QGPHY device of HKEEE is same as BCM54682E, 5124 * the _chk_phy can be used for QGPHY device of HKEEE 5125 */ 5126 5127 static int 5128 _chk_qgphy_5332x(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5129 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5130 { 5131 COMPILER_REFERENCE(my_entry); 5132 COMPILER_REFERENCE(phy_id0); 5133 COMPILER_REFERENCE(phy_id1); 5134 COMPILER_REFERENCE(pi); 5135 5136 if (SOC_IS_HAWKEYE(unit) && 5137 soc_feature (unit, soc_feature_eee) && 5138 (port <= 8) && 5139 (port != 0)) { 5140 pi->phy_name = "BCM53324"; 5141 return TRUE; 5142 } 5143 5144 return FALSE; 5145 } 5146 #endif /* INCLUDE_PHY_54680 */ 5147 5148 #if defined(BCM_XGS3_SWITCH_SUPPORT) 5149 /* 5150 * Function: 5151 * _chk_fiber56xxx 5152 * Purpose: 5153 * Check for using Internal 56XXX SERDES Device for fiber 5154 * Returns: 5155 * TRUE if this PHY matches. 5156 * FALSE otherwise. 5157 * Notes: 5158 * This routine should be called after checking for external 5159 * PHYs because it will default the PHY driver to the internal 5160 * SERDES in the absense of any other PHY. 5161 */ 5162 5163 static int 5164 _chk_fiber56xxx(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5165 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5166 { 5167 COMPILER_REFERENCE(my_entry); 5168 COMPILER_REFERENCE(phy_id0); 5169 COMPILER_REFERENCE(phy_id1); 5170 5171 if (IS_GE_PORT(unit, port) && !IS_GMII_PORT(unit, port) && 5172 !SOC_IS_HAWKEYE(unit) && !SOC_IS_HURRICANE2(unit) && 5173 soc_feature(unit, soc_feature_dodeca_serdes)) { 5174 pi->phy_name = "Phy56XXX"; 5175 5176 return TRUE; 5177 } 5178 5179 return FALSE; 5180 } 5181 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 5182 5183 #if defined(INCLUDE_PHY_XGXS6) 5184 /* 5185 * Function: 5186 * _chk_unicore 5187 * Purpose: 5188 * Check for Unicore, which may return two different PHY IDs 5189 * depending on the current IEEE register mapping. One of 5190 * these PHY IDs conflicts with the BCM5673/74 PHY ID, so 5191 * we need to check the port type here as well. 5192 * Parameters: 5193 * See soc_phy_ident_f 5194 * *pi is an output parameter filled with PHY info. 5195 * Returns: 5196 * TRUE if this PHY matches. 5197 * FALSE otherwise. 5198 * Notes: 5199 * Sets the phy_info structure for this port. 5200 */ 5201 5202 static int 5203 _chk_unicore(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5204 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5205 { 5206 COMPILER_REFERENCE(unit); 5207 5208 if (my_entry->myNum == _phy_ident_type_get(phy_id0, phy_id1) && 5209 soc_feature(unit, soc_feature_xgxs_v6)) { 5210 pi->phy_name = my_entry->phy_name; 5211 return TRUE; 5212 } 5213 5214 return FALSE; 5215 } 5216 #endif /* INCLUDE_PHY_XGXS6 */ 5217 5218 static int 5219 _chk_sfp_phy(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5220 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5221 { 5222 COMPILER_REFERENCE(unit); 5223 5224 if (soc_property_port_get(unit, port, spn_PHY_COPPER_SFP, 0)) { 5225 if (!(phy_id0 == (uint16)0xFFFF && phy_id1 == (uint16)0xFFFF)) { 5226 LOG_INFO(BSL_LS_SOC_PHY, 5227 (BSL_META_U(unit, 5228 "_chk_sfp_phy: u=%d p=%d id0=0x%x, id1=0x%x," 5229 " oui=0x%x,model=0x%x,rev=0x%x\n"), 5230 unit, port,phy_id0,phy_id1,PHY_OUI(phy_id0, phy_id1), 5231 PHY_MODEL(phy_id0, phy_id1),PHY_REV(phy_id0, phy_id1))); 5232 pi->phy_name = my_entry->phy_name; 5233 return TRUE; 5234 } 5235 } 5236 return FALSE; 5237 } 5238 5239 #if defined(INCLUDE_PHY_8706) 5240 static int 5241 _chk_8706(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5242 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5243 { 5244 if (my_entry->myNum == _phy_ident_type_get(phy_id0, phy_id1) || 5245 soc_property_port_get(unit, port, spn_PHY_8706, FALSE)) { 5246 pi->phy_name = my_entry->phy_name; 5247 return TRUE; 5248 } 5249 return FALSE; 5250 } 5251 5252 #endif /* INCLUDE_PHY_8706 */ 5253 5254 #if defined(INCLUDE_PHY_8040) 5255 static int 5256 _chk_8040(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5257 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5258 { 5259 if (my_entry->myNum == _phy_ident_type_get(phy_id0, phy_id1)) { 5260 pi->phy_name = my_entry->phy_name; 5261 return TRUE; 5262 } 5263 return FALSE; 5264 } 5265 #endif /* INCLUDE_PHY_8040 */ 5266 5267 #if defined(INCLUDE_PHY_8072) 5268 static int 5269 _chk_8072(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5270 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5271 { 5272 if (my_entry->myNum == _phy_ident_type_get(phy_id0, phy_id1) || 5273 soc_property_port_get(unit, port, spn_PHY_8072, FALSE)) { 5274 pi->phy_name = my_entry->phy_name; 5275 return TRUE; 5276 } 5277 return FALSE; 5278 } 5279 5280 #endif /* INCLUDE_PHY_8072 */ 5281 5282 #if defined(INCLUDE_PHY_8481) 5283 static int 5284 _chk_8481(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5285 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5286 { 5287 /* for GE/XE/HG ports only */ 5288 if ( ! (IS_XE_PORT(unit, port) || IS_HG_PORT(unit, port) 5289 || IS_GE_PORT(unit, port)) ) { 5290 return FALSE; 5291 } 5292 5293 if (my_entry->myNum == _phy_ident_type_get(phy_id0, phy_id1)) { 5294 pi->phy_name = my_entry->phy_name; 5295 return TRUE; 5296 } 5297 5298 return FALSE; 5299 5300 } 5301 #endif /* INCLUDE_PHY_8481 */ 5302 5303 #if defined(INCLUDE_PHY_56XXX) 5304 /* 5305 * Function: 5306 * _chk_fiber56xxx_5601x 5307 * Purpose: 5308 * Check for using Internal SERDES Device for fiber with shadow registers 5309 * Returns: 5310 * TRUE if this PHY matches. 5311 * FALSE otherwise. 5312 * Notes: 5313 * This routine should be called after checking for external 5314 * PHYs because it will default the PHY driver to the internal 5315 * SERDES in the absense of any other PHY. 5316 */ 5317 5318 static int 5319 _chk_fiber56xxx_5601x(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5320 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5321 { 5322 uint8 phy_addr; 5323 5324 COMPILER_REFERENCE(my_entry); 5325 COMPILER_REFERENCE(phy_id0); 5326 COMPILER_REFERENCE(phy_id1); 5327 5328 phy_addr = PORT_TO_PHY_ADDR_INT(unit, port); 5329 5330 if (SOC_IS_RAPTOR(unit) && 5331 soc_feature(unit, soc_feature_fe_ports) && 5332 ((port == 4) || (port == 5)) && 5333 (soc_property_port_get(unit, port, spn_SERDES_SHADOW_DRIVER, FALSE) || 5334 _is_corrupted_reg(unit, phy_addr))) { 5335 pi->phy_name = "Phy56XXX5601x"; 5336 return TRUE; 5337 } 5338 5339 return FALSE; 5340 } 5341 #endif /* INCLUDE_PHY_56XXX */ 5342 5343 #if defined(INCLUDE_SERDES_COMBO) 5344 /* 5345 * Function: 5346 * _chk_serdes_combo_5601x 5347 * Purpose: 5348 * Check for using Internal SERDES Device for fiber with shadow registers 5349 * Returns:q 5350 * TRUE if this PHY matches. 5351 * FALSE otherwise. 5352 * Notes: 5353 * This routine should be called after checking for external 5354 * PHYs because it will default the PHY driver to the internal 5355 * SERDES in the absense of any other PHY. 5356 */ 5357 5358 static int 5359 _chk_serdes_combo_5601x(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5360 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5361 { 5362 uint8 phy_addr; 5363 5364 COMPILER_REFERENCE(my_entry); 5365 COMPILER_REFERENCE(phy_id0); 5366 COMPILER_REFERENCE(phy_id1); 5367 5368 phy_addr = PORT_TO_PHY_ADDR_INT(unit, port); 5369 5370 if (SOC_IS_RAPTOR(unit) && 5371 soc_feature(unit, soc_feature_fe_ports) && 5372 ((port == 1) || (port == 2)) && 5373 (soc_property_port_get(unit, port, spn_SERDES_SHADOW_DRIVER, FALSE) || 5374 _is_corrupted_reg(unit, phy_addr))) { 5375 pi->phy_name = "COMBO5601x"; 5376 return TRUE; 5377 } 5378 5379 return FALSE; 5380 } 5381 #endif /* INCLUDE_SERDES_COMBO */ 5382 5383 #if defined(INCLUDE_PHY_53XXX) 5384 /* 5385 * Function: 5386 * _chk_fiber53xxx 5387 * Purpose: 5388 * Check for using Internal 53XXX SERDES Device for fiber 5389 * Returns: 5390 * TRUE if this PHY matches. 5391 * FALSE otherwise. 5392 * Notes: 5393 * This routine should be called after checking for external 5394 * PHYs because it will default the PHY driver to the internal 5395 * SERDES in the absense of any other PHY. 5396 */ 5397 5398 static int 5399 _chk_fiber53xxx(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5400 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5401 { 5402 COMPILER_REFERENCE(my_entry); 5403 COMPILER_REFERENCE(phy_id0); 5404 COMPILER_REFERENCE(phy_id1); 5405 5406 return FALSE; 5407 } 5408 #endif /* INCLUDE_PHY_53XXX */ 5409 /* 5410 * Function: 5411 * _chk_default 5412 * Purpose: 5413 * Select a default PHY driver. 5414 * Returns: 5415 * TRUE 5416 * Notes: 5417 * This routine always "finds" a default PHY driver and can 5418 * be the last entry in the PHY table (or called explicitly). 5419 */ 5420 5421 static int 5422 _chk_default(int unit, soc_port_t port, soc_phy_table_t *my_entry, 5423 uint16 phy_id0, uint16 phy_id1, soc_phy_info_t *pi) 5424 { 5425 pi->phy_name = my_entry->phy_name; 5426 5427 return TRUE; 5428 } 5429 5430 STATIC int 5431 _forced_phy_probe(int unit, soc_port_t port, 5432 soc_phy_info_t *pi, phy_ctrl_t *ext_pc) 5433 { 5434 #if defined(INCLUDE_PHY_SIMUL) || defined(BCM_XGS3_SWITCH_SUPPORT) 5435 phy_driver_t *phyd = NULL; 5436 #endif 5437 5438 #if defined(INCLUDE_PHY_SIMUL) 5439 /* Similarly, check for simulation driver */ 5440 if (phyd == NULL && 5441 _chk_simul(unit, port, &_simul_phy_entry, 0xffff, 0xffff, pi)) { 5442 ext_pc->pd = _simul_phy_entry.driver; 5443 pi->phy_id0 = 0xffff; 5444 pi->phy_id1 = 0xffff; 5445 } 5446 #endif 5447 5448 #if defined(BCM_XGS3_SWITCH_SUPPORT) 5449 /* Check for property forcing fiber mode on XGS3 switch */ 5450 if (phyd == NULL && 5451 soc_property_port_get(unit, port, spn_PHY_56XXX, FALSE) && 5452 _chk_fiber56xxx(unit, port, &_fiber56xxx_phy_entry, 5453 0xffff, 0xffff, pi)) { 5454 /* Correct internal SerDes PHY driver is already attached by 5455 * internal PHY probe. Therefore, just assign NULL to external PHY 5456 * driver. 5457 */ 5458 ext_pc->pd = NULL; 5459 pi->phy_id0 = 0xffff; 5460 pi->phy_id1 = 0xffff; 5461 } 5462 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 5463 5464 /* Forced PHY will have internal PHY device ID */ 5465 return SOC_E_NONE; 5466 } 5467 5468 STATIC int 5469 _int_phy_probe(int unit, soc_port_t port, 5470 soc_phy_info_t *pi, phy_ctrl_t *int_pc) 5471 { 5472 uint16 phy_addr; 5473 uint16 phy_id0, phy_id1; 5474 int i; 5475 int rv; 5476 phy_driver_t *int_phyd; 5477 #if defined(BCM_KATANA2_SUPPORT) 5478 uint8 lane_num = 0; 5479 uint8 phy_mode = 0; 5480 uint8 chip_num = 0; 5481 #endif 5482 5483 phy_addr = int_pc->phy_id; 5484 int_phyd = NULL; 5485 /* There is always one extra "NULL" entry in the _int_phy_table to satisfy pedants */ 5486 i = sizeof(_int_phy_table) / sizeof(_int_phy_table[0]) - 1; 5487 5488 /* Make sure page 0 is mapped before reading for PHY dev ID */ 5489 5490 #if defined(BCM_TRIUMPH3_SUPPORT) 5491 if (SOC_IS_TRIUMPH3(unit) && 5492 (SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit,all), port))) { 5493 5494 phy_id0 = phy_id1 = 0; 5495 } else 5496 #endif /* BCM_TRIUMPH3_SUPPORT */ 5497 { 5498 if (SOC_IS_ARDON(unit)) { 5499 phy_id0 = 0x600d; 5500 phy_id1 = 0x8770; 5501 } else { 5502 5503 if(SOC_IS_SABER2(unit)) { 5504 /* For saber2, the Sbus mdio access is expected along 5505 * with AER information 5506 */ 5507 (void)int_pc->write(unit, phy_addr, 0x1f, 0xFFD0); 5508 (void)int_pc->write(unit, phy_addr, 0x1e, 0); 5509 } 5510 5511 (void)int_pc->write(unit, phy_addr, 0x1f, 0); 5512 5513 (void)int_pc->read(unit, phy_addr, MII_PHY_ID0_REG, &phy_id0); 5514 (void)int_pc->read(unit, phy_addr, MII_PHY_ID1_REG, &phy_id1); 5515 5516 } 5517 5518 } 5519 5520 5521 pi->phy_id0 = phy_id0; 5522 pi->phy_id1 = phy_id1; 5523 pi->phy_addr_int = phy_addr; 5524 int_pc->phy_id0 = phy_id0; 5525 int_pc->phy_id1 = phy_id1; 5526 int_pc->phy_oui = PHY_OUI(phy_id0, phy_id1); 5527 int_pc->phy_model = PHY_MODEL(phy_id0, phy_id1); 5528 int_pc->phy_rev = PHY_REV(phy_id0, phy_id1); 5529 5530 for (i = i - 1; i >= 0; i--) { 5531 if ((_int_phy_table[i].checkphy)(unit, port, &_int_phy_table[i], 5532 phy_id0, phy_id1, pi)) { 5533 /* Device ID matches. Calls driver probe routine to confirm 5534 * that the driver is the appropriate one. 5535 * Many PHY devices has the same device ID but they are 5536 * actually different. 5537 */ 5538 5539 rv = PHY_PROBE(_int_phy_table[i].driver, unit, int_pc); 5540 if ((rv == SOC_E_NONE) || (rv == SOC_E_UNAVAIL)) { 5541 LOG_INFO(BSL_LS_SOC_PHY, 5542 (BSL_META_U(unit, 5543 "<%d> int Index = %d Mynum = %d %s\n"), 5544 rv, i, _int_phy_table[i].myNum, _int_phy_table[i].phy_name)); 5545 int_phyd = _int_phy_table[i].driver; 5546 break; 5547 } 5548 } 5549 } 5550 5551 #if defined(INCLUDE_XGXS_16G) 5552 if (IS_GE_PORT(unit, port) && (&phy_xgxs16g1l_ge == int_phyd)) { 5553 /* using XGXS16G in independent lane mode on GE port. */ 5554 PHY_FLAGS_SET(unit, port, PHY_FLAGS_INDEPENDENT_LANE); 5555 #if defined(BCM_SCORPION_SUPPORT) 5556 if (SOC_IS_SCORPION(unit)) { 5557 switch(port) { 5558 case 25: 5559 pi->phy_name = "XGXS16G/1/0"; 5560 int_pc->lane_num = 0; 5561 break; 5562 case 26: 5563 pi->phy_name = "XGXS16G/1/1"; 5564 int_pc->lane_num = 1; 5565 break; 5566 case 27: 5567 pi->phy_name = "XGXS16G/1/2"; 5568 int_pc->lane_num = 2; 5569 break; 5570 case 28: 5571 pi->phy_name = "XGXS16G/1/3"; 5572 int_pc->lane_num = 3; 5573 break; 5574 default: 5575 break; 5576 } 5577 } 5578 #endif 5579 } 5580 #endif 5581 5582 #if defined(INCLUDE_XGXS_HL65) 5583 if (IS_GE_PORT(unit, port) && (&phy_hl65_hg == int_phyd)) { 5584 /* If using HyperLite on GE port, use the HyperLite in independent 5585 * lane mode. 5586 */ 5587 PHY_FLAGS_SET(unit, port, PHY_FLAGS_INDEPENDENT_LANE); 5588 pi->phy_name = "HL65/1"; 5589 #if defined(BCM_HURRICANE1_SUPPORT) 5590 if (SOC_IS_HURRICANE(unit)) { 5591 int_pc->phy_mode = PHYCTRL_DUAL_LANE_PORT; 5592 int_pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 5593 switch (port) { 5594 case 26: 5595 pi->phy_name = "HL65/0/0"; 5596 int_pc->lane_num = 0; 5597 break; 5598 case 27: 5599 pi->phy_name = "HL65/0/2"; 5600 int_pc->lane_num = 2; 5601 break; 5602 case 28: 5603 pi->phy_name = "HL65/1/0"; 5604 int_pc->lane_num = 0; 5605 break; 5606 case 29: 5607 pi->phy_name = "HL65/1/2"; 5608 int_pc->lane_num = 2; 5609 break; 5610 default: 5611 break; 5612 } 5613 } 5614 #endif 5615 #if defined(BCM_VALKYRIE_SUPPORT) || defined(BCM_TRIUMPH_SUPPORT) 5616 if (SOC_IS_VALKYRIE(unit) || SOC_IS_TRIUMPH(unit)) { 5617 switch(port) { 5618 case 2: 5619 case 6: 5620 case 14: 5621 case 26: 5622 case 27: 5623 case 35: 5624 pi->phy_name = "HL65/1/0"; 5625 int_pc->lane_num = 0; 5626 break; 5627 5628 case 3: 5629 case 7: 5630 case 15: 5631 case 32: 5632 case 36: 5633 case 43: 5634 pi->phy_name = "HL65/1/1"; 5635 int_pc->lane_num = 1; 5636 break; 5637 5638 case 4: 5639 case 16: 5640 case 18: 5641 case 33: 5642 case 44: 5643 case 46: 5644 pi->phy_name = "HL65/1/2"; 5645 int_pc->lane_num = 2; 5646 break; 5647 5648 case 5: 5649 case 17: 5650 case 19: 5651 case 34: 5652 case 45: 5653 case 47: 5654 pi->phy_name = "HL65/1/3"; 5655 int_pc->lane_num = 3; 5656 break; 5657 5658 default: 5659 break; 5660 5661 } 5662 } 5663 #endif /* BCM_VALKYRIE_SUPPORT */ 5664 #if defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_APOLLO_SUPPORT) || \ 5665 defined(BCM_VALKYRIE2_SUPPORT) 5666 if (SOC_IS_TRIUMPH2(unit) || SOC_IS_APOLLO(unit) || 5667 SOC_IS_VALKYRIE2(unit)) { 5668 switch(port) { 5669 case 30: 5670 case 34: 5671 case 38: 5672 case 42: 5673 case 46: 5674 case 50: 5675 pi->phy_name = "HL65/1/0"; 5676 int_pc->lane_num = 0; 5677 break; 5678 5679 case 31: 5680 case 35: 5681 case 39: 5682 case 43: 5683 case 47: 5684 case 51: 5685 pi->phy_name = "HL65/1/1"; 5686 int_pc->lane_num = 1; 5687 break; 5688 5689 case 32: 5690 case 36: 5691 case 40: 5692 case 44: 5693 case 48: 5694 case 52: 5695 pi->phy_name = "HL65/1/2"; 5696 int_pc->lane_num = 2; 5697 break; 5698 5699 case 33: 5700 case 37: 5701 case 41: 5702 case 45: 5703 case 49: 5704 case 53: 5705 pi->phy_name = "HL65/1/3"; 5706 int_pc->lane_num = 3; 5707 break; 5708 5709 default: 5710 break; 5711 5712 } 5713 } 5714 #endif /* BCM_TRIUMPH2_SUPPORT */ 5715 } 5716 5717 #if defined(BCM_HURRICANE1_SUPPORT) 5718 if ((&phy_hl65_hg == int_phyd) && SOC_IS_HURRICANE(unit) && ((IS_HG_PORT(unit, port)) || IS_XE_PORT(unit, port))) { 5719 if ((port == 26) && (!SOC_PORT_VALID(unit, 27))) { 5720 LOG_INFO(BSL_LS_SOC_PHY, 5721 (BSL_META_U(unit, 5722 "Port 26 in combo mode\n"))); 5723 pi->phy_name = "HL65/0"; 5724 } else if ((port == 28) && (!SOC_PORT_VALID(unit, 29))) { 5725 LOG_INFO(BSL_LS_SOC_PHY, 5726 (BSL_META_U(unit, 5727 "Port 28 in combo mode\n"))); 5728 pi->phy_name = "HL65/1"; 5729 } else { 5730 LOG_INFO(BSL_LS_SOC_PHY, 5731 (BSL_META_U(unit, 5732 "Port %d in HGd mode\n"), port)); 5733 PHY_FLAGS_SET(unit, port, PHY_FLAGS_INDEPENDENT_LANE); 5734 int_pc->phy_mode = PHYCTRL_DUAL_LANE_PORT; 5735 int_pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 5736 switch (port) { 5737 case 26: 5738 pi->phy_name = "HL65/0/0"; 5739 int_pc->lane_num = 0; 5740 break; 5741 case 27: 5742 pi->phy_name = "HL65/0/2"; 5743 int_pc->lane_num = 2; 5744 break; 5745 case 28: 5746 pi->phy_name = "HL65/1/0"; 5747 int_pc->lane_num = 0; 5748 break; 5749 case 29: 5750 pi->phy_name = "HL65/1/2"; 5751 int_pc->lane_num = 2; 5752 break; 5753 default: 5754 break; 5755 } 5756 } 5757 } 5758 #endif /* BCM_HURRICANE_SUPPORT */ 5759 5760 #endif /* INCLUDE_XGXS_HL65 */ 5761 5762 #if defined(INCLUDE_XGXS_QSGMII65) 5763 if (IS_GE_PORT(unit, port) && (&phy_qsgmii65_ge == int_phyd)) { 5764 pi->phy_name = "QSGMII65"; 5765 #if defined(BCM_HAWKEYE_SUPPORT) 5766 if (SOC_IS_HAWKEYE(unit)) { 5767 switch(port) { 5768 case 9: 5769 case 17: 5770 pi->phy_name = "QSGMII65/0"; 5771 int_pc->lane_num = 0; 5772 break; 5773 5774 case 10: 5775 case 18: 5776 pi->phy_name = "QSGMII65/1"; 5777 int_pc->lane_num = 1; 5778 break; 5779 5780 case 11: 5781 case 19: 5782 pi->phy_name = "QSGMII65/2"; 5783 int_pc->lane_num = 2; 5784 break; 5785 5786 case 12: 5787 case 20: 5788 pi->phy_name = "QSGMII65/3"; 5789 int_pc->lane_num = 3; 5790 break; 5791 5792 case 13: 5793 case 21: 5794 pi->phy_name = "QSGMII65/4"; 5795 int_pc->lane_num = 4; 5796 break; 5797 5798 case 14: 5799 case 22: 5800 pi->phy_name = "QSGMII65/5"; 5801 int_pc->lane_num = 5; 5802 break; 5803 5804 case 15: 5805 case 23: 5806 pi->phy_name = "QSGMII65/6"; 5807 int_pc->lane_num = 6; 5808 break; 5809 5810 case 16: 5811 case 24: 5812 pi->phy_name = "QSGMII65/7"; 5813 int_pc->lane_num = 7; 5814 break; 5815 5816 default: 5817 break; 5818 5819 } 5820 } 5821 #endif /* SOC_IS_HAWKEYE */ 5822 #if defined(BCM_HURRICANE1_SUPPORT) 5823 if (SOC_IS_HURRICANE(unit)) { 5824 switch(port) { 5825 case 2: 5826 case 10: 5827 case 18: 5828 pi->phy_name = "QSGMII65/0"; 5829 int_pc->lane_num = 0; 5830 break; 5831 5832 case 3: 5833 case 11: 5834 case 19: 5835 pi->phy_name = "QSGMII65/1"; 5836 int_pc->lane_num = 1; 5837 break; 5838 5839 case 4: 5840 case 12: 5841 case 20: 5842 pi->phy_name = "QSGMII65/2"; 5843 int_pc->lane_num = 2; 5844 break; 5845 5846 case 5: 5847 case 13: 5848 case 21: 5849 pi->phy_name = "QSGMII65/3"; 5850 int_pc->lane_num = 3; 5851 break; 5852 5853 case 6: 5854 case 14: 5855 case 22: 5856 pi->phy_name = "QSGMII65/4"; 5857 int_pc->lane_num = 4; 5858 break; 5859 5860 case 7: 5861 case 15: 5862 case 23: 5863 pi->phy_name = "QSGMII65/5"; 5864 int_pc->lane_num = 5; 5865 break; 5866 5867 case 8: 5868 case 16: 5869 case 24: 5870 pi->phy_name = "QSGMII65/6"; 5871 int_pc->lane_num = 6; 5872 break; 5873 5874 case 9: 5875 case 17: 5876 case 25: 5877 pi->phy_name = "QSGMII65/7"; 5878 int_pc->lane_num = 7; 5879 break; 5880 5881 default: 5882 break; 5883 5884 } 5885 } 5886 #endif /* BCM_HURRICANE_SUPPORT */ 5887 } 5888 #endif /* INCLUDE_XGXS_QSGMII65 */ 5889 5890 #if defined(BCM_GREYHOUND_SUPPORT) 5891 if (SOC_IS_GREYHOUND(unit) && 5892 (IS_GE_PORT(unit, port) && !IS_XL_PORT(unit, port))) { 5893 int_pc->lane_num = (port - 2) % 8; /* lane_num in {0~7} */ 5894 int_pc->chip_num = (port - 2) / 8; /* chip_num in {0,1}*/ 5895 int_pc->phy_mode = PHYCTRL_QSGMII_CORE_PORT; 5896 int_pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 5897 } 5898 #endif /* BCM_GREYHOUND_SUPPORT */ 5899 5900 #if defined(BCM_KATANA2_SUPPORT) 5901 if ((SOC_IS_KATANA2(unit)) && (!SOC_IS_SABER2(unit)) && 5902 (port <= KT2_MAX_PHYSICAL_PORTS)) { 5903 if (katana2_get_wc_phy_info(unit,port,&lane_num, &phy_mode, &chip_num) == SOC_E_NONE) { 5904 int_pc->lane_num = lane_num; 5905 int_pc->phy_mode = phy_mode; 5906 int_pc->chip_num = chip_num; 5907 int_pc->flags |= PHYCTRL_MDIO_ADDR_SHARE; 5908 /* PHY_FLAGS_SET(unit, port, PHY_FLAGS_INDEPENDENT_LANE); */ 5909 } 5910 if ((SOC_INFO(unit).olp_port[0]) && (port == KT2_OLP_PORT)) { 5911 int_pc->lane_num = 2; 5912 } 5913 } 5914 5915 #endif 5916 5917 #if defined(INCLUDE_PHY_56XXX) && defined(INCLUDE_PHY_XGXS6) 5918 /* If we detetcted a Unicore driver for a GE port, attach internal SerDes 5919 * driver. 5920 * Current Unicore driver does not support external GE PHY. 5921 */ 5922 if (IS_GE_PORT(unit, port) && (&phy_xgxs6_hg == int_phyd)) { 5923 if (_chk_fiber56xxx(unit, port, &_fiber56xxx_phy_entry, 5924 phy_id0, phy_id1, pi)) { 5925 int_phyd = &phy_56xxxdrv_ge; 5926 } 5927 } 5928 #endif /* INCLUDE_PHY_56XXX && INCLUDE_PHY_XGXS6 */ 5929 5930 5931 #if defined(INCLUDE_PHY_56XXX) 5932 /* If we detected a shadow register driver, allocate driver data */ 5933 if (&phy_56xxx_5601x_drv_ge == int_phyd) { 5934 serdes_5601x_sregs_t *sr; 5935 5936 /* Allocate shadow registers */ 5937 sr = sal_alloc(sizeof(serdes_5601x_sregs_t), 5938 "SERDES_COMBO shadow regs"); 5939 if (sr == NULL) { 5940 return SOC_E_MEMORY; 5941 } 5942 int_pc->driver_data = sr; 5943 } 5944 #endif /* INCLUDE_PHY_56XXX */ 5945 5946 #if defined(INCLUDE_SERDES_COMBO) 5947 /* If we detected a shadow register driver, allocate driver data */ 5948 if (&phy_serdescombo_5601x_ge == int_phyd) { 5949 serdescombo_5601x_sregs_t *sr; 5950 5951 /* Allocate shadow registers */ 5952 sr = sal_alloc(sizeof(serdescombo_5601x_sregs_t), 5953 "SERDES_COMBO shadow regs"); 5954 if (sr == NULL) { 5955 return SOC_E_MEMORY; 5956 } 5957 int_pc->driver_data = sr; 5958 } 5959 #endif /* INCLUDE_SERDES_COMBO */ 5960 5961 #if defined(INCLUDE_PHY_53XXX) 5962 /* If we detetcted a Unicore driver for a GE port, attach internal SerDes 5963 * driver. 5964 * Current Unicore driver does not support external GE PHY. 5965 */ 5966 if (IS_GE_PORT(unit, port)) { 5967 if (_chk_fiber53xxx(unit, port, &_fiber53xxx_phy_entry, 5968 phy_id0, phy_id1, pi)) { 5969 int_phyd = &phy_53xxxdrv_ge; 5970 } 5971 } 5972 #endif /* INCLUDE_PHY_53XXX */ 5973 5974 #ifdef BCM_XGS_SUPPORT 5975 if (int_phyd == NULL) { 5976 if (IS_XE_PORT(unit, port) || IS_HG_PORT(unit, port)) { 5977 /* If no appropriate driver is installed in the phy driver table 5978 * use a default higig driver for XE port */ 5979 #if defined (INCLUDE_PHY_XGXS6) 5980 if (soc_feature(unit, soc_feature_xgxs_v6)) { 5981 int_phyd = &phy_xgxs6_hg; 5982 } else 5983 #endif /* INCLUDE_PHY_XGXS6*/ 5984 #if defined(INCLUDE_PHY_XGXS5) 5985 if (soc_feature(unit, soc_feature_xgxs_v5)) { 5986 int_phyd = &phy_xgxs5_hg; 5987 } else 5988 #endif /* INCLUDE_PHY_XGXS5 */ 5989 { 5990 int_phyd = &phy_xgxs1_hg; 5991 } 5992 } 5993 } 5994 #endif /* BCM_XGS_SUPPORT */ 5995 5996 5997 #if defined(BCM_XGS3_SWITCH_SUPPORT) 5998 /* If GMII port, attach NULL PHY driver to 5999 * internal PHY driver. GMII port does not have SerDes. 6000 */ 6001 if (_chk_gmii(unit, port, &_null_phy_entry, 0xffff, 0xffff, pi)) { 6002 int_phyd = _null_phy_entry.driver; 6003 } 6004 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 6005 6006 int_pc->pd = int_phyd; 6007 6008 return SOC_E_NONE; 6009 } 6010 6011 6012 6013 int 6014 _ext_phy_probe(int unit, soc_port_t port, 6015 soc_phy_info_t *pi, phy_ctrl_t *ext_pc) 6016 { 6017 uint16 phy_addr; 6018 uint32 id0_addr, id1_addr; 6019 uint16 phy_id0=0, phy_id1=0; 6020 int i; 6021 phy_driver_t *phyd; 6022 int rv; 6023 int cl45_override = 0; 6024 char *propval; 6025 #if defined(BCM_HURRICANE3_SUPPORT) 6026 uint16 dev_id = 0; 6027 uint8 rev_id = 0; 6028 #endif /* BCM_HURRICANE3_SUPPORT */ 6029 6030 phy_addr = ext_pc->phy_id; 6031 phyd = NULL; 6032 6033 if (SOC_IS_ARDON(unit)) { 6034 ext_pc->pd = NULL; 6035 return SOC_E_NONE; 6036 } 6037 /* Clause 45 instead of Clause 22 MDIO access */ 6038 if (soc_property_port_get(unit, port, spn_PORT_PHY_CLAUSE, 22) == 45) { 6039 cl45_override = 1; 6040 } 6041 6042 if (IS_XE_PORT(unit, port) || IS_HG_PORT(unit, port) || IS_CE_PORT(unit, port) || SOC_IS_ARAD(unit)) { 6043 if (SOC_IS_ARAD(unit)) { 6044 if (cl45_override) { 6045 id0_addr = SOC_PHY_CLAUSE45_ADDR(PHY_C45_DEV_PMA_PMD, 6046 MII_PHY_ID0_REG); 6047 id1_addr = SOC_PHY_CLAUSE45_ADDR(PHY_C45_DEV_PMA_PMD, 6048 MII_PHY_ID1_REG); 6049 } else { 6050 id0_addr = MII_PHY_ID0_REG; 6051 id1_addr = MII_PHY_ID1_REG; 6052 } 6053 } else { 6054 id0_addr = SOC_PHY_CLAUSE45_ADDR(PHY_C45_DEV_PMA_PMD, 6055 MII_PHY_ID0_REG); 6056 id1_addr = SOC_PHY_CLAUSE45_ADDR(PHY_C45_DEV_PMA_PMD, 6057 MII_PHY_ID1_REG); 6058 } 6059 } else if ( IS_GE_PORT(unit, port) ) { 6060 if (cl45_override) { 6061 id0_addr = SOC_PHY_CLAUSE45_ADDR(PHY_C45_DEV_PMA_PMD, 6062 MII_PHY_ID0_REG); 6063 id1_addr = SOC_PHY_CLAUSE45_ADDR(PHY_C45_DEV_PMA_PMD, 6064 MII_PHY_ID1_REG); 6065 } else { 6066 id0_addr = MII_PHY_ID0_REG; 6067 id1_addr = MII_PHY_ID1_REG; 6068 } 6069 } else { 6070 id0_addr = MII_PHY_ID0_REG; 6071 id1_addr = MII_PHY_ID1_REG; 6072 } 6073 6074 if (soc_property_port_get(unit, port, 6075 spn_PORT_PHY_PRECONDITION_BEFORE_PROBE, 0)) { 6076 for (i = _phys_in_table - 1; i >= 0; i--) { 6077 rv = PHY_PRECONDITION_BEFORE_PROBE(phy_table[i]->driver, 6078 unit, ext_pc); 6079 if (rv == SOC_E_NONE) { 6080 break; 6081 } 6082 } 6083 } 6084 6085 propval = soc_property_port_get_str(unit, port, spn_PORT_PHY_ID0); 6086 if (propval != NULL){ 6087 phy_id0 = soc_property_port_get(unit, port, spn_PORT_PHY_ID0, 0xFFFF); 6088 } 6089 else{ 6090 (void)ext_pc->read(unit, phy_addr, id0_addr, &phy_id0); 6091 } 6092 propval = soc_property_port_get_str(unit, port, spn_PORT_PHY_ID1); 6093 if (propval != NULL){ 6094 phy_id1 = soc_property_port_get(unit, port, spn_PORT_PHY_ID1, 0xFFFF); 6095 } 6096 else{ 6097 (void)ext_pc->read(unit, phy_addr, id1_addr, &phy_id1); 6098 } 6099 6100 /* Look through table for match */ 6101 for (i = _phys_in_table - 1; i >= 0; i--) { 6102 if ((phy_table[i]->checkphy)(unit, port, phy_table[i], 6103 phy_id0, phy_id1, pi)) { 6104 /* Device ID matches. Calls driver probe routine to confirm 6105 * that the driver is the appropriate one. 6106 * Many PHY devices has the same device ID but they are 6107 * actually different. 6108 */ 6109 rv = PHY_PROBE(phy_table[i]->driver, unit, ext_pc); 6110 if ((rv == SOC_E_NONE) || (rv == SOC_E_UNAVAIL)) { 6111 LOG_INFO(BSL_LS_SOC_PHY, 6112 (BSL_META_U(unit, 6113 "<%d> ext Index = %d Mynum = %d %s\n"), 6114 rv, i, phy_table[i]->myNum, phy_table[i]->phy_name)); 6115 6116 phyd = phy_table[i]->driver; 6117 pi->phy_id0 = phy_id0; 6118 pi->phy_id1 = phy_id1; 6119 pi->phy_addr = phy_addr; 6120 if (ext_pc->dev_name) { 6121 pi->phy_name = ext_pc->dev_name; 6122 } 6123 ext_pc->phy_id0 = phy_id0; 6124 ext_pc->phy_id1 = phy_id1; 6125 ext_pc->phy_oui = PHY_OUI(phy_id0, phy_id1); 6126 ext_pc->phy_model = PHY_MODEL(phy_id0, phy_id1); 6127 ext_pc->phy_rev = PHY_REV(phy_id0, phy_id1); 6128 6129 6130 #ifdef BCM_HURRICANE3_SUPPORT 6131 if (soc_feature(unit, 6132 soc_feature_hr3_egphy28_phyrev_override) && 6133 PHY_IS_BCM56160GPHY(ext_pc)) { 6134 soc_cm_get_id(unit, &dev_id, &rev_id); 6135 ext_pc->phy_rev = rev_id; 6136 } 6137 #endif /* BCM_HURRICANE3_SUPPORT */ 6138 6139 PHY_FLAGS_SET(unit, port, PHY_FLAGS_EXTERNAL_PHY); 6140 6141 break; 6142 } 6143 } 6144 } 6145 6146 6147 6148 #if defined(INCLUDE_PHY_54684) 6149 if (IS_GE_PORT(unit, port) && (phyd == &phy_54684drv_ge)) { 6150 #if defined(BCM_HAWKEYE_SUPPORT) 6151 if (SOC_IS_HAWKEYE(unit)) { 6152 switch(port) { 6153 case 9: 6154 case 17: 6155 ext_pc->lane_num = 0; 6156 break; 6157 6158 case 10: 6159 case 18: 6160 ext_pc->lane_num = 1; 6161 break; 6162 6163 case 11: 6164 case 19: 6165 ext_pc->lane_num = 2; 6166 break; 6167 6168 case 12: 6169 case 20: 6170 ext_pc->lane_num = 3; 6171 break; 6172 6173 case 13: 6174 case 21: 6175 ext_pc->lane_num = 4; 6176 break; 6177 6178 case 14: 6179 case 22: 6180 ext_pc->lane_num = 5; 6181 break; 6182 6183 case 15: 6184 case 23: 6185 ext_pc->lane_num = 6; 6186 break; 6187 6188 case 16: 6189 case 24: 6190 ext_pc->lane_num = 7; 6191 break; 6192 6193 default: 6194 break; 6195 6196 } 6197 } 6198 #endif /* SOC_IS_HAWKEYE */ 6199 #if defined(BCM_HURRICANE1_SUPPORT) 6200 if (SOC_IS_HURRICANE(unit)) { 6201 switch(port) { 6202 case 2: 6203 case 10: 6204 case 18: 6205 ext_pc->lane_num = 0; 6206 break; 6207 6208 case 3: 6209 case 11: 6210 case 19: 6211 ext_pc->lane_num = 1; 6212 break; 6213 6214 case 4: 6215 case 12: 6216 case 20: 6217 ext_pc->lane_num = 2; 6218 break; 6219 6220 case 5: 6221 case 13: 6222 case 21: 6223 ext_pc->lane_num = 3; 6224 break; 6225 6226 case 6: 6227 case 14: 6228 case 22: 6229 ext_pc->lane_num = 4; 6230 break; 6231 6232 case 7: 6233 case 15: 6234 case 23: 6235 ext_pc->lane_num = 5; 6236 break; 6237 6238 case 8: 6239 case 16: 6240 case 24: 6241 ext_pc->lane_num = 6; 6242 break; 6243 6244 case 9: 6245 case 17: 6246 case 25: 6247 ext_pc->lane_num = 7; 6248 break; 6249 6250 default: 6251 break; 6252 6253 } 6254 } 6255 #endif /* BCM_HURRICANE_SUPPORT */ 6256 } 6257 #endif /* INCLUDE_PHY_54684 */ 6258 6259 ext_pc->pd = phyd; 6260 6261 return SOC_E_NONE; 6262 } 6263 6264 /* 6265 * Function: 6266 * soc_phy_probe 6267 * Purpose: 6268 * Probe the PHY on the specified port and return a pointer to the 6269 * drivers for the device found. 6270 * Parameters: 6271 * unit - StrataSwitch unit #. 6272 * port - StrataSwitch port #. 6273 * phyd_ptr - (OUT) Pointer to PHY driver (NULL on error) 6274 * Returns: 6275 * SOC_E_XXX 6276 * Notes: 6277 * Loop thru table making callback for each known PHY. 6278 * We loop from the table from top to bottom so that user additions 6279 * take precedence over default values. The first checkphy function 6280 * returning TRUE is used as the driver. 6281 */ 6282 int 6283 soc_phy_probe(int unit, soc_port_t port, phy_ctrl_t *ext_pc, 6284 phy_ctrl_t *int_pc) 6285 { 6286 soc_phy_info_t *pi; 6287 uint16 phy_addr; 6288 uint16 phy_addr_int; 6289 6290 /* Always use default addresses for probing. 6291 * This make sure that the external PHY probe works correctly even 6292 * when the device is hot plugged or the external PHY address is 6293 * overriden from previous probe. 6294 */ 6295 SOC_IF_ERROR_RETURN 6296 (soc_phy_cfg_addr_get(unit,port,0,&phy_addr)); 6297 SOC_IF_ERROR_RETURN 6298 (soc_phy_cfg_addr_get(unit,port,SOC_PHY_INTERNAL,&phy_addr_int)); 6299 int_pc->phy_id = phy_addr_int; 6300 ext_pc->phy_id = phy_addr; 6301 6302 /* 6303 * Characterize PHY by reading MII registers. 6304 */ 6305 pi = &SOC_PHY_INFO(unit, port); 6306 6307 /* Probe for null PHY configuration first to avoid MII timeouts */ 6308 6309 if (_chk_null(unit, port, &_null_phy_entry, 0xffff, 0xffff, pi)) { 6310 ext_pc->pd = _null_phy_entry.driver; 6311 int_pc->pd = _null_phy_entry.driver; 6312 } 6313 6314 #ifdef PORTMOD_SUPPORT 6315 if (soc_feature(unit, soc_feature_portmod)) { 6316 /* If portmod is enabled all the phymod compliant 6317 * phy probes would be handled by portmod. All the 6318 * internal phys are phymod compliant. We just need 6319 * to probe for legacy external phys */ 6320 6321 /* Assign catch all extphy_to_phymod pd table to intpc 6322 * to handle all the notifications for internal phy 6323 * from external phy */ 6324 6325 int_pc->pd = &phy_ext_to_int_drv; 6326 6327 } else { 6328 #endif /* PORTMOD_SUPPORT */ 6329 /* Search for internal phy */ 6330 if (NULL == int_pc->pd) { 6331 SOC_IF_ERROR_RETURN 6332 (_int_phy_probe(unit, port, pi, int_pc)); 6333 } 6334 6335 #ifdef PORTMOD_SUPPORT 6336 } 6337 #endif 6338 /* Search for external PHY */ 6339 if (NULL == ext_pc->pd) { 6340 SOC_IF_ERROR_RETURN 6341 (_ext_phy_probe(unit, port, pi, ext_pc)); 6342 } 6343 6344 6345 /* Override external PHY driver according to config settings */ 6346 SOC_IF_ERROR_RETURN 6347 (_forced_phy_probe(unit, port, pi, ext_pc)); 6348 6349 6350 if (ext_pc->pd != NULL) { 6351 if (IS_GMII_PORT(unit, port)) { 6352 /* If GMII port has external PHY, remove the NULL PHY driver 6353 * attached to internal PHY in _int_phy_probe(). 6354 */ 6355 int_pc->pd = NULL; 6356 } 6357 if ((int_pc->pd == _null_phy_entry.driver) && 6358 (ext_pc->pd == _null_phy_entry.driver)) { 6359 /* Attach NULL PHY driver as external PHY driver */ 6360 int_pc->pd = NULL; 6361 } 6362 } 6363 6364 if ((ext_pc->pd == NULL) && (int_pc->pd == NULL) && 6365 _chk_default(unit, port, &_default_phy_entry, 0xffff, 0xffff, pi)) { 6366 ext_pc->pd = _default_phy_entry.driver; 6367 } 6368 6369 assert((ext_pc->pd != NULL) || (int_pc->pd != NULL)); 6370 6371 if (ext_pc->pd == NULL || /* No external PHY */ 6372 ext_pc->pd == int_pc->pd) { /* Forced PHY */ 6373 /* Use internal address when application trying to access 6374 * external PHY. 6375 */ 6376 pi->phy_addr = pi->phy_addr_int; 6377 6378 /* If there is no external PHY, the internal PHY must be in 6379 * fiber mode. 6380 */ 6381 if (soc_property_port_get(unit, port, 6382 spn_SERDES_FIBER_PREF, 1)) { 6383 PHY_FLAGS_SET(unit, port, PHY_FLAGS_FIBER); 6384 } else { 6385 PHY_FLAGS_CLR(unit, port, PHY_FLAGS_FIBER); 6386 } 6387 } 6388 6389 /* 6390 * The property if_tbi_port<X> can be used to force TBI mode on a 6391 * port. The individual PHY drivers should key off this flag. 6392 */ 6393 if (soc_property_port_get(unit, port, spn_IF_TBI, 0)) { 6394 PHY_FLAGS_SET(unit, port, PHY_FLAGS_10B); 6395 } 6396 6397 pi->an_timeout = 6398 soc_property_port_get(unit, port, 6399 spn_PHY_AUTONEG_TIMEOUT, 250000); 6400 6401 LOG_INFO(BSL_LS_SOC_PHY, 6402 (BSL_META_U(unit, 6403 "soc_phy_probe: port=%d addr=0x%x " 6404 "id1=0x%x id0=0x%x flg=0x%x driver=\"%s\"\n"), 6405 port, 6406 pi->phy_addr, pi->phy_id0, pi->phy_id1, 6407 pi->phy_flags, pi->phy_name)); 6408 6409 return SOC_E_NONE; 6410 } 6411 6412 int 6413 soc_phy_check_sim(int unit, int port, phy_ctrl_t *pc) 6414 { 6415 #ifdef PHYMOD_SUPPORT 6416 int tsce_sim; 6417 int tscf_sim; 6418 int qsgmiie_sim; 6419 int viper_sim; 6420 int eagle_sim; 6421 int qtce_sim; 6422 int tscbh_sim; 6423 uint16 phy_id; 6424 6425 /* Get PHYAD associated with this port */ 6426 soc_phy_cfg_addr_get(unit, port, SOC_PHY_INTERNAL, &phy_id); 6427 6428 viper_sim = soc_property_port_get(unit, port, "viper_sim", 0); 6429 if (viper_sim) { 6430 if (SOC_IS_GREYHOUND2(unit) || soc_feature(unit, soc_feature_wh2)) { 6431 SOC_IF_ERROR_RETURN( 6432 soc_physim_add(unit, phy_id, &viper_sp2_sim_drv)); 6433 } 6434 else { 6435 SOC_IF_ERROR_RETURN( 6436 soc_physim_add(unit, phy_id, &viper_sim_drv)); 6437 } 6438 pc->read = soc_physim_read; 6439 pc->write = soc_physim_write; 6440 /* Assume MDIO access if viper_sim >= 22 */ 6441 if (viper_sim < 22) { 6442 pc->wrmask = soc_physim_wrmask; 6443 } 6444 } 6445 6446 tsce_sim = soc_property_port_get(unit, port, "tsce_sim", 0); 6447 if (tsce_sim) { 6448 SOC_IF_ERROR_RETURN( 6449 soc_physim_add(unit, phy_id, &tsce_sim_drv)); 6450 pc->read = soc_physim_read; 6451 pc->write = soc_physim_write; 6452 /* Assume MDIO access if tsce_sim >= 22 */ 6453 if (tsce_sim < 22) { 6454 pc->wrmask = soc_physim_wrmask; 6455 } 6456 } 6457 6458 tscf_sim = soc_property_port_get(unit, port, "tscf_sim", 0); 6459 if (tscf_sim) { 6460 SOC_IF_ERROR_RETURN( 6461 soc_physim_add(unit, phy_id, &tscf_sim_drv)); 6462 pc->read = soc_physim_read; 6463 pc->write = soc_physim_write; 6464 /* Assume MDIO access if tscf_sim >= 22 */ 6465 if (tscf_sim < 22) { 6466 pc->wrmask = soc_physim_wrmask; 6467 } 6468 } 6469 6470 tscbh_sim = soc_property_port_get(unit, port, "tscbh_sim", 0); 6471 if (tscbh_sim) { 6472 SOC_IF_ERROR_RETURN( 6473 soc_physim_add(unit, phy_id, &tscbh_sim_drv)); 6474 pc->read = soc_physim_read; 6475 pc->write = soc_physim_write; 6476 /* Assume MDIO access if tscf_sim >= 22 */ 6477 if (tscbh_sim < 22) { 6478 pc->wrmask = soc_physim_wrmask; 6479 } 6480 } 6481 6482 eagle_sim = soc_property_port_get(unit, port, "eagle_sim", 0); 6483 if (eagle_sim) { 6484 SOC_IF_ERROR_RETURN( 6485 soc_physim_add(unit, phy_id, &eagle_sim_drv)); 6486 pc->read = soc_physim_read; 6487 pc->write = soc_physim_write; 6488 /* Assume MDIO access if tsce_sim >= 22 */ 6489 if (eagle_sim < 22) { 6490 pc->wrmask = soc_physim_wrmask; 6491 } 6492 } 6493 6494 qsgmiie_sim = soc_property_port_get(unit, port, "qsgmiie_sim", 0); 6495 if (qsgmiie_sim) { 6496 SOC_IF_ERROR_RETURN( 6497 soc_physim_add(unit, phy_id, &qsgmiie_sim_drv)); 6498 pc->read = soc_physim_read; 6499 pc->write = soc_physim_write; 6500 /* Assume MDIO access if qsgmiie_sim >= 22 */ 6501 if (qsgmiie_sim < 22) { 6502 pc->wrmask = soc_physim_wrmask; 6503 } 6504 } 6505 6506 qtce_sim = soc_property_port_get(unit, port, "qtce_sim", 0); 6507 if (qtce_sim) { 6508 SOC_IF_ERROR_RETURN( 6509 soc_physim_add(unit, phy_id, &qtce_sim_drv)); 6510 pc->read = soc_physim_read; 6511 pc->write = soc_physim_write; 6512 /* Assume MDIO access if qtce_sim >= 22 */ 6513 if (qtce_sim < 22) { 6514 pc->wrmask = soc_physim_wrmask; 6515 } 6516 } 6517 #endif /* PHYMOD_SUPPORT */ 6518 6519 return SOC_E_NONE; 6520 } 6521 6522 void 6523 phyident_core_info_t_init(phyident_core_info_t* core_info) { 6524 core_info->mdio_addr = 0xFFFF; 6525 core_info->core_type = phyident_core_types_count; 6526 core_info->mld_index = PHYIDENT_INFO_NOT_SET; 6527 core_info->index_in_mld = PHYIDENT_INFO_NOT_SET; 6528 core_info->qsmii_lane = PHYIDENT_INFO_NOT_SET; 6529 core_info->first_phy_in_core = 0; 6530 core_info->nof_lanes_in_core = 4; 6531 } 6532 6533 /* 6534 * Function: 6535 * soc_phy_addr_multi_get 6536 * Purpose: 6537 * Provide a list of internal MDIO addresses corresponding to a port. 6538 * Parameters: 6539 * unit - StrataSwitch unit #. 6540 * port - StrataSwitch port #. 6541 * array_max - maximum number of elements in mdio_addr array. 6542 * array_size - (OUT) number of valid elements returned in mdio_addr. 6543 * mdio_addr - (OUT) list of internal mdio addresses for the port. 6544 * Returns: 6545 * SOC_E_XXX 6546 * Notes: 6547 * Return the list of relevant internal MDIO addresses connected 6548 * to a given port. 6549 * Currently, only 100G+ ports require multiple MDIO addresses. 6550 */ 6551 int 6552 soc_phy_addr_multi_get(int unit, soc_port_t port, int array_max, 6553 int *array_size, phyident_core_info_t *core_info) 6554 { 6555 int addr_num = 0; 6556 int i; 6557 6558 if ((0 >= array_max) || (NULL == array_size) || (NULL == core_info)) { 6559 return SOC_E_PARAM; 6560 } 6561 6562 for(i=0 ; i<array_max ; i++) { 6563 phyident_core_info_t_init(&(core_info[i])); 6564 } 6565 6566 #ifdef BCM_PETRA_SUPPORT 6567 if(SOC_IS_DPP(unit)) { 6568 return _dpp_phy_addr_multi_get(unit, port, 1, array_max, array_size, core_info); 6569 } 6570 #endif 6571 6572 if (IS_CL_PORT(unit, port)) { 6573 if (SOC_IS_TRIUMPH3(unit)) { 6574 uint32 mld_index = (0 == SOC_BLOCK_NUMBER(unit, SOC_PORT_BLOCK(unit, 6575 SOC_INFO(unit).port_l2p_mapping[port]))) ? 0 : 1; 6576 if (array_max > 1) { 6577 core_info[addr_num].mdio_addr = port_phy_addr[unit][port].int_addr; 6578 core_info[addr_num].core_type = phyident_core_type_wc; 6579 core_info[addr_num].mld_index = mld_index; 6580 core_info[addr_num].index_in_mld = 0; 6581 addr_num++; 6582 } 6583 if (array_max > 2) { 6584 core_info[addr_num].mdio_addr = core_info[addr_num - 1].mdio_addr + 4; 6585 core_info[addr_num].core_type = phyident_core_type_wc; 6586 core_info[addr_num].mld_index = mld_index; 6587 core_info[addr_num].index_in_mld = 1; 6588 addr_num++; 6589 } 6590 if (array_max > 3) { 6591 core_info[addr_num].mdio_addr = core_info[addr_num - 1].mdio_addr + 4; 6592 core_info[addr_num].core_type = phyident_core_type_wc; 6593 core_info[addr_num].mld_index = mld_index; 6594 core_info[addr_num].index_in_mld = 2; 6595 addr_num++; 6596 } 6597 if (array_max > 4) { 6598 core_info[addr_num].mdio_addr = mld_index ? 0xde : 0xdd; 6599 core_info[addr_num].core_type = phyident_core_type_mld; 6600 core_info[addr_num].mld_index = mld_index; 6601 core_info[addr_num].index_in_mld = 0; 6602 addr_num++; 6603 } 6604 *array_size = addr_num; 6605 } else { 6606 6607 return SOC_E_UNAVAIL; 6608 } 6609 } else { 6610 SOC_IF_ERROR_RETURN 6611 (soc_phy_cfg_addr_get(unit, port, SOC_PHY_INTERNAL, 6612 &(core_info[0].mdio_addr))); 6613 core_info[0].core_type = phyident_core_type_wc; 6614 *array_size = 1; 6615 } 6616 return SOC_E_NONE; 6617 } 6618 6619 /* 6620 * Variable: 6621 * phy_id_map 6622 * Purpose: 6623 * Map the PHY identifier register (OUI and device ID) into 6624 * enumerated PHY type for prototypical devices. 6625 */ 6626 6627 typedef struct phy_id_map_s { 6628 soc_known_phy_t phy_num; /* Enumerated PHY type */ 6629 uint32 oui; /* Device OUI */ 6630 uint16 model; /* Device Model */ 6631 uint16 rev_map; /* Device Revision */ 6632 } phy_id_map_t; 6633 6634 #define PHY_REV_ALL (0xffff) 6635 #define PHY_REV_0_3 (0x000f) 6636 #define PHY_REV_4_7 (PHY_REV_0_3 << 4) 6637 #define PHY_REV_8_11 (PHY_REV_0_3 << 8) 6638 #define PHY_REV_12_15 (PHY_REV_0_3 << 12) 6639 #define PHY_REV_0 (1 << 0) 6640 #define PHY_REV_1 (1 << 1) 6641 #define PHY_REV_2 (1 << 2) 6642 #define PHY_REV_3 (1 << 3) 6643 #define PHY_REV_4 (1 << 4) 6644 #define PHY_REV_5 (1 << 5) 6645 #define PHY_REV_6 (1 << 6) 6646 #define PHY_REV_7 (1 << 7) 6647 #define PHY_REV_8 (1 << 8) 6648 #define PHY_REV_9 (1 << 9) 6649 #define PHY_REV_10 (1 << 10) 6650 #define PHY_REV_11 (1 << 11) 6651 #define PHY_REV_12 (1 << 12) 6652 6653 STATIC phy_id_map_t phy_id_map[] = { 6654 { _phy_id_BCM5218, PHY_BCM5218_OUI, PHY_BCM5218_MODEL, 6655 PHY_REV_ALL }, 6656 { _phy_id_BCM5220, PHY_BCM5220_OUI, PHY_BCM5220_MODEL, 6657 PHY_REV_ALL }, /* & 5221 */ 6658 { _phy_id_BCM5226, PHY_BCM5226_OUI, PHY_BCM5226_MODEL, 6659 PHY_REV_ALL}, 6660 { _phy_id_BCM5228, PHY_BCM5228_OUI, PHY_BCM5228_MODEL, 6661 PHY_REV_ALL}, 6662 { _phy_id_BCM5238, PHY_BCM5238_OUI, PHY_BCM5238_MODEL, 6663 PHY_REV_ALL}, 6664 { _phy_id_BCM5248, PHY_BCM5248_OUI, PHY_BCM5248_MODEL, 6665 PHY_REV_ALL}, 6666 { _phy_id_BCM5400, PHY_BCM5400_OUI, PHY_BCM5400_MODEL, 6667 PHY_REV_ALL}, 6668 { _phy_id_BCM5401, PHY_BCM5401_OUI, PHY_BCM5401_MODEL, 6669 PHY_REV_ALL}, 6670 { _phy_id_BCM5402, PHY_BCM5402_OUI, PHY_BCM5402_MODEL, 6671 PHY_REV_ALL}, 6672 { _phy_id_BCM5404, PHY_BCM5404_OUI, PHY_BCM5404_MODEL, 6673 PHY_REV_ALL}, 6674 { _phy_id_BCM5411, PHY_BCM5411_OUI, PHY_BCM5411_MODEL, 6675 PHY_REV_ALL}, 6676 { _phy_id_BCM5421, PHY_BCM5421_OUI, PHY_BCM5421_MODEL, 6677 PHY_REV_ALL}, /* & 5421S */ 6678 { _phy_id_BCM5424, PHY_BCM5424_OUI, PHY_BCM5424_MODEL, 6679 PHY_REV_ALL}, /* & 5434 */ 6680 { _phy_id_BCM5464, PHY_BCM5464_OUI, PHY_BCM5464_MODEL, 6681 PHY_REV_ALL}, /* & 5464S */ 6682 { _phy_id_BCM5466, PHY_BCM5466_OUI, PHY_BCM5466_MODEL, 6683 PHY_REV_ALL}, /* & 5466S */ 6684 { _phy_id_BCM5461, PHY_BCM5461_OUI, PHY_BCM5461_MODEL, 6685 PHY_REV_ALL}, /* & 5461S */ 6686 { _phy_id_BCM5461, PHY_BCM5462_OUI, PHY_BCM5462_MODEL, 6687 PHY_REV_ALL}, /* & 5461D */ 6688 { _phy_id_BCM5478, PHY_BCM5478_OUI, PHY_BCM5478_MODEL, 6689 PHY_REV_ALL}, /* 5478 */ 6690 { _phy_id_BCM5488, PHY_BCM5488_OUI, PHY_BCM5488_MODEL, 6691 PHY_REV_ALL}, /* 5488 */ 6692 { _phy_id_BCM5482, PHY_BCM5482_OUI, PHY_BCM5482_MODEL, 6693 PHY_REV_ALL}, /* & 5482S */ 6694 { _phy_id_BCM5481, PHY_BCM5481_OUI, PHY_BCM5481_MODEL, 6695 PHY_REV_ALL}, /* & 5481 */ 6696 { _phy_id_BCM54980, PHY_BCM54980_OUI, PHY_BCM54980_MODEL, 6697 PHY_REV_ALL}, 6698 { _phy_id_BCM54980C, PHY_BCM54980C_OUI, PHY_BCM54980C_MODEL, 6699 PHY_REV_ALL}, 6700 { _phy_id_BCM54980V, PHY_BCM54980V_OUI, PHY_BCM54980V_MODEL, 6701 PHY_REV_ALL}, 6702 { _phy_id_BCM54980VC, PHY_BCM54980VC_OUI, PHY_BCM54980VC_MODEL, 6703 PHY_REV_ALL}, 6704 { _phy_id_BCM54680, PHY_BCM54680_OUI, PHY_BCM54680_MODEL, 6705 PHY_REV_ALL}, 6706 { _phy_id_BCM54880, PHY_BCM54880_OUI, PHY_BCM54880_MODEL, 6707 PHY_REV_ALL}, 6708 { _phy_id_BCM54880E, PHY_BCM54880E_OUI, PHY_BCM54880E_MODEL, 6709 PHY_REV_ALL}, 6710 { _phy_id_BCM54680E, PHY_BCM54680E_OUI, PHY_BCM54680E_MODEL, 6711 PHY_REV_ALL}, 6712 { _phy_id_BCM52681E, PHY_BCM52681E_OUI, PHY_BCM52681E_MODEL, 6713 PHY_REV_ALL}, 6714 { _phy_id_BCM54881, PHY_BCM54881_OUI, PHY_BCM54881_MODEL, 6715 PHY_REV_ALL}, 6716 { _phy_id_BCM54810, PHY_BCM54810_OUI, PHY_BCM54810_MODEL, 6717 PHY_REV_ALL}, 6718 { _phy_id_BCM54811, PHY_BCM54811_OUI, PHY_BCM54811_MODEL, 6719 PHY_REV_ALL}, 6720 { _phy_id_BCM54684, PHY_BCM54684_OUI, PHY_BCM54684_MODEL, 6721 PHY_REV_ALL}, 6722 { _phy_id_BCM54684E, PHY_BCM54684E_OUI, PHY_BCM54684E_MODEL, 6723 PHY_REV_ALL}, 6724 { _phy_id_BCM54682, PHY_BCM54682E_OUI, PHY_BCM54682E_MODEL, 6725 PHY_REV_ALL}, 6726 { _phy_id_BCM54685, PHY_BCM54685_OUI, PHY_BCM54685_MODEL, 6727 PHY_REV_ALL}, 6728 { _phy_id_BCM54640, PHY_BCM54640_OUI, PHY_BCM54640_MODEL, 6729 PHY_REV_ALL}, 6730 { _phy_id_BCM54616, PHY_BCM54616_OUI, PHY_BCM54616_MODEL, 6731 PHY_REV_ALL}, 6732 { _phy_id_BCM54618E, PHY_BCM54618E_OUI, PHY_BCM54618E_MODEL, 6733 PHY_REV_ALL}, 6734 { _phy_id_BCM54618SE, PHY_BCM54618SE_OUI, PHY_BCM54618SE_MODEL, 6735 PHY_REV_ALL}, 6736 6737 #ifdef INCLUDE_MACSEC 6738 #if defined(INCLUDE_PHY_54380) 6739 { _phy_id_BCM54380, PHY_BCM54380_OUI, PHY_BCM54380_MODEL, 6740 PHY_REV_ALL}, 6741 { _phy_id_BCM54382, PHY_BCM54380_OUI, PHY_BCM54382_MODEL, 6742 PHY_REV_ALL}, 6743 { _phy_id_BCM54340, PHY_BCM54380_OUI, PHY_BCM54340_MODEL, 6744 PHY_REV_ALL}, 6745 { _phy_id_BCM54385, PHY_BCM54380_OUI, PHY_BCM54385_MODEL, 6746 PHY_REV_ALL}, 6747 #endif 6748 #endif 6749 6750 #if defined(INCLUDE_PHY_542XX) 6751 { _phy_id_BCM54182, PHY_BCM5418X_OUI, PHY_BCM54182_MODEL, 6752 PHY_REV_ALL}, 6753 { _phy_id_BCM54185, PHY_BCM5418X_OUI, PHY_BCM54185_MODEL, 6754 PHY_REV_ALL}, 6755 { _phy_id_BCM54180, PHY_BCM5418X_OUI, PHY_BCM54180_MODEL, 6756 PHY_REV_ALL}, 6757 { _phy_id_BCM54140, PHY_BCM5418X_OUI, PHY_BCM54140_MODEL, 6758 PHY_REV_ALL}, 6759 { _phy_id_BCM54192, PHY_BCM5419X_OUI, PHY_BCM54192_MODEL, 6760 PHY_REV_ALL}, 6761 { _phy_id_BCM54195, PHY_BCM5419X_OUI, PHY_BCM54195_MODEL, 6762 PHY_REV_ALL}, 6763 { _phy_id_BCM54190, PHY_BCM5419X_OUI, PHY_BCM54190_MODEL, 6764 PHY_REV_ALL}, 6765 { _phy_id_BCM54194, PHY_BCM5419X_OUI, PHY_BCM54194_MODEL, 6766 PHY_REV_ALL}, 6767 { _phy_id_BCM54210, PHY_BCM542XX_OUI, PHY_BCM54210_MODEL, 6768 PHY_REV_ALL}, 6769 { _phy_id_BCM54220, PHY_BCM542XX_OUI, PHY_BCM54220_MODEL, 6770 PHY_REV_ALL}, 6771 { _phy_id_BCM54280, PHY_BCM542XX_OUI, PHY_BCM54280_MODEL, 6772 PHY_REV_ALL}, 6773 { _phy_id_BCM54282, PHY_BCM542XX_OUI, PHY_BCM54282_MODEL, 6774 PHY_REV_ALL}, 6775 { _phy_id_BCM54240, PHY_BCM542XX_OUI, PHY_BCM54240_MODEL, 6776 PHY_REV_ALL}, 6777 { _phy_id_BCM54285, PHY_BCM542XX_OUI, PHY_BCM54285_MODEL, 6778 PHY_REV_ALL}, 6779 { _phy_id_BCM54290, PHY_BCM542XX_OUI, PHY_BCM54290_MODEL, 6780 PHY_REV_ALL}, 6781 { _phy_id_BCM54292, PHY_BCM542XX_OUI, PHY_BCM54292_MODEL, 6782 PHY_REV_ALL}, 6783 { _phy_id_BCM54294, PHY_BCM542XX_OUI, PHY_BCM54294_MODEL, 6784 PHY_REV_ALL}, 6785 { _phy_id_BCM54295, PHY_BCM542XX_OUI, PHY_BCM54295_MODEL, 6786 PHY_REV_ALL}, 6787 { _phy_id_BCM54296, PHY_BCM542XX_OUI, PHY_BCM54296_MODEL, 6788 PHY_REV_ALL}, 6789 { _phy_id_BCM5428x, PHY_BCM542XX_OUI, PHY_BCM5428X_MODEL, 6790 PHY_REV_ALL}, 6791 #endif 6792 6793 #if defined(INCLUDE_PHY_8806X) 6794 { _phy_id_BCM8806x, PHY_BCM8806X_OUI, PHY_BCM8806X_MODEL, 6795 PHY_REV_ALL}, 6796 #endif /* INCLUDE_PHY_8806X */ 6797 6798 #ifdef INCLUDE_MACSEC 6799 #if defined(INCLUDE_PHY_54580) 6800 { _phy_id_BCM54584, PHY_BCM54580_OUI, PHY_BCM54584_MODEL, 6801 PHY_REV_ALL}, 6802 { _phy_id_BCM54580, PHY_BCM54580_OUI, PHY_BCM54580_MODEL, 6803 PHY_REV_ALL}, 6804 { _phy_id_BCM54540, PHY_BCM54580_OUI, PHY_BCM54540_MODEL, 6805 PHY_REV_ALL}, 6806 { _phy_id_BCM54585, PHY_BCM54580_OUI, PHY_BCM54585_MODEL, 6807 PHY_REV_ALL}, 6808 #endif 6809 #endif /* INCLUDE_MACSEC */ 6810 { _phy_id_BCM8011, PHY_BCM8011_OUI, PHY_BCM8011_MODEL, 6811 PHY_REV_ALL}, 6812 { _phy_id_BCM8040, PHY_BCM8040_OUI, PHY_BCM8040_MODEL, 6813 PHY_REV_0 | PHY_REV_1 | PHY_REV_2}, 6814 { _phy_id_BCM8703, PHY_BCM8703_OUI, PHY_BCM8703_MODEL, 6815 PHY_REV_0 | PHY_REV_1 | PHY_REV_2}, 6816 { _phy_id_BCM8704, PHY_BCM8704_OUI, PHY_BCM8704_MODEL, 6817 PHY_REV_3}, 6818 { _phy_id_BCM8705, PHY_BCM8705_OUI, PHY_BCM8705_MODEL, 6819 PHY_REV_4}, 6820 { _phy_id_BCM8706, PHY_BCM8706_OUI, PHY_BCM8706_MODEL, 6821 PHY_REV_5}, 6822 { _phy_id_BCM8750, PHY_BCM8750_OUI, PHY_BCM8750_MODEL, 6823 PHY_REV_0}, 6824 { _phy_id_BCM8752, PHY_BCM8752_OUI, PHY_BCM8752_MODEL, 6825 PHY_REV_0}, 6826 { _phy_id_BCM8754, PHY_BCM8754_OUI, PHY_BCM8754_MODEL, 6827 PHY_REV_ALL}, 6828 { _phy_id_BCM8072, PHY_BCM8072_OUI, PHY_BCM8072_MODEL, 6829 PHY_REV_5}, 6830 { _phy_id_BCM8727, PHY_BCM8727_OUI, PHY_BCM8727_MODEL, 6831 PHY_REV_6}, 6832 { _phy_id_BCM8073, PHY_BCM8073_OUI, PHY_BCM8073_MODEL, 6833 PHY_REV_6}, 6834 { _phy_id_BCM8747, PHY_BCM8747_OUI, PHY_BCM8747_MODEL, 6835 PHY_REV_7}, 6836 { _phy_id_BCM84740, PHY_BCM84740_OUI, PHY_BCM84740_MODEL, 6837 PHY_REV_0}, 6838 { _phy_id_BCM84164, PHY_BCM84164_OUI, PHY_BCM84164_MODEL, 6839 PHY_REV_0_3}, 6840 { _phy_id_BCM84758, PHY_BCM84758_OUI, PHY_BCM84758_MODEL, 6841 PHY_REV_0_3}, 6842 { _phy_id_BCM84780, PHY_BCM84780_OUI, PHY_BCM84780_MODEL, 6843 PHY_REV_4_7}, 6844 { _phy_id_BCM84784, PHY_BCM84784_OUI, PHY_BCM84784_MODEL, 6845 PHY_REV_8_11}, 6846 #ifdef INCLUDE_MACSEC 6847 #ifdef INCLUDE_PHY_8729 6848 { _phy_id_BCM8729, PHY_BCM5927_OUI, PHY_BCM5927_MODEL, 6849 PHY_REV_4}, 6850 { _phy_id_BCM8729, PHY_BCM8729_OUI, PHY_BCM8729_MODEL, 6851 PHY_REV_12}, 6852 #endif 6853 #ifdef INCLUDE_PHY_84756 6854 { _phy_id_BCM84756, PHY_BCM84756_OUI, PHY_BCM84756_MODEL, 6855 PHY_REV_0_3}, 6856 { _phy_id_BCM84757, PHY_BCM84756_OUI, PHY_BCM84756_MODEL, 6857 PHY_REV_8_11}, 6858 { _phy_id_BCM84759, PHY_BCM84756_OUI, PHY_BCM84756_MODEL, 6859 PHY_REV_4_7}, 6860 #endif 6861 #ifdef INCLUDE_PHY_84334 6862 { _phy_id_BCM84334, PHY_BCM84334_OUI, PHY_BCM84334_MODEL, 6863 PHY_REV_ALL}, 6864 { _phy_id_BCM84333, PHY_BCM84333_OUI, PHY_BCM84333_MODEL, 6865 PHY_REV_ALL}, 6866 { _phy_id_BCM84336, PHY_BCM84336_OUI, PHY_BCM84336_MODEL, 6867 PHY_REV_ALL}, 6868 { _phy_id_BCM84844, PHY_BCM84844_OUI, PHY_BCM84844_MODEL, 6869 PHY_REV_ALL}, 6870 #endif 6871 #ifdef INCLUDE_PHY_84749 6872 { _phy_id_BCM84749, PHY_BCM84749_OUI, PHY_BCM84749_MODEL, 6873 PHY_REV_0}, 6874 { _phy_id_BCM84729, PHY_BCM84729_OUI, PHY_BCM84729_MODEL, 6875 PHY_REV_0}, 6876 #endif 6877 #endif /* INCLUDE_MACSEC */ 6878 #if defined(INCLUDE_FCMAP) || defined(INCLUDE_MACSEC) 6879 #ifdef INCLUDE_PHY_84756 6880 { _phy_id_BCM84756, PHY_BCM84756_OUI, PHY_BCM84756_MODEL, 6881 PHY_REV_0_3}, 6882 { _phy_id_BCM84757, PHY_BCM84756_OUI, PHY_BCM84756_MODEL, 6883 PHY_REV_8_11}, 6884 { _phy_id_BCM84759, PHY_BCM84756_OUI, PHY_BCM84756_MODEL, 6885 PHY_REV_4_7}, 6886 #endif /*INCLUDE_PHY_84756 */ 6887 #endif /* INCLUDE_FCMAP || INCLUDE_MACSEC */ 6888 #ifdef INCLUDE_PHY_84728 6889 { _phy_id_BCM84707, PHY_BCM84707_OUI, PHY_BCM84707_MODEL, 6890 PHY_REV_4_7}, 6891 { _phy_id_BCM84073, PHY_BCM84073_OUI, PHY_BCM84073_MODEL, 6892 PHY_REV_8_11}, 6893 { _phy_id_BCM84074, PHY_BCM84074_OUI, PHY_BCM84074_MODEL, 6894 PHY_REV_12_15}, 6895 { _phy_id_BCM84728, PHY_BCM84728_OUI, PHY_BCM84728_MODEL, 6896 PHY_REV_0_3}, 6897 { _phy_id_BCM84748, PHY_BCM84748_OUI, PHY_BCM84748_MODEL, 6898 PHY_REV_4_7}, 6899 { _phy_id_BCM84727, PHY_BCM84727_OUI, PHY_BCM84727_MODEL, 6900 PHY_REV_8_11}, 6901 { _phy_id_BCM84747, PHY_BCM84747_OUI, PHY_BCM84747_MODEL, 6902 PHY_REV_12_15}, 6903 { _phy_id_BCM84762, PHY_BCM84762_OUI, PHY_BCM84762_MODEL, 6904 PHY_REV_0_3}, 6905 { _phy_id_BCM84764, PHY_BCM84764_OUI, PHY_BCM84764_MODEL, 6906 PHY_REV_4_7}, 6907 { _phy_id_BCM84042, PHY_BCM84042_OUI, PHY_BCM84042_MODEL, 6908 PHY_REV_8_11}, 6909 { _phy_id_BCM84044, PHY_BCM84044_OUI, PHY_BCM84044_MODEL, 6910 PHY_REV_12_15}, 6911 #endif 6912 { _phy_id_BCM8481x, PHY_BCM8481X_OUI, PHY_BCM8481X_MODEL, 6913 PHY_REV_ALL}, 6914 { _phy_id_BCM84812ce, PHY_BCM84812CE_OUI, PHY_BCM84812CE_MODEL, 6915 PHY_REV_ALL}, 6916 { _phy_id_BCM84821, PHY_BCM84821_OUI, PHY_BCM84821_MODEL, 6917 PHY_REV_ALL}, 6918 { _phy_id_BCM84822, PHY_BCM84822_OUI, PHY_BCM84822_MODEL, 6919 PHY_REV_ALL}, 6920 { _phy_id_BCM84823, PHY_BCM84823_OUI, PHY_BCM84823_MODEL, 6921 PHY_REV_ALL}, 6922 { _phy_id_BCM84833, PHY_BCM84833_OUI, PHY_BCM84833_MODEL, 6923 PHY_REV_ALL}, 6924 { _phy_id_BCM84834, PHY_BCM84834_OUI, PHY_BCM84834_MODEL, 6925 PHY_REV_ALL}, 6926 { _phy_id_BCM84835, PHY_BCM84835_OUI, PHY_BCM84835_MODEL, 6927 PHY_REV_ALL}, 6928 { _phy_id_BCM84836, PHY_BCM84836_OUI, PHY_BCM84836_MODEL, 6929 PHY_REV_ALL}, 6930 { _phy_id_BCM84844, PHY_BCM84844_OUI, PHY_BCM84844_MODEL, 6931 PHY_REV_ALL}, 6932 { _phy_id_BCM84846, PHY_BCM84846_OUI, PHY_BCM84846_MODEL, 6933 PHY_REV_ALL}, 6934 { _phy_id_BCM84848, PHY_BCM84848_OUI, PHY_BCM84848_MODEL, 6935 PHY_REV_ALL}, 6936 { _phy_id_BCM84858, PHY_BCM84858_OUI, PHY_BCM84858_MODEL, 6937 PHY_REV_ALL}, 6938 { _phy_id_BCM84856, PHY_BCM84856_OUI, PHY_BCM84856_MODEL, 6939 PHY_REV_ALL}, 6940 { _phy_id_BCM84860, PHY_BCM84860_OUI, PHY_BCM84860_MODEL, 6941 PHY_REV_ALL}, 6942 { _phy_id_BCM84861, PHY_BCM84861_OUI, PHY_BCM84861_MODEL, 6943 PHY_REV_ALL}, 6944 { _phy_id_BCM84864, PHY_BCM84864_OUI, PHY_BCM84864_MODEL, 6945 PHY_REV_ALL}, 6946 { _phy_id_BCM84868, PHY_BCM84868_OUI, PHY_BCM84868_MODEL, 6947 PHY_REV_ALL}, 6948 { _phy_id_BCM84888, PHY_BCM84888_OUI, PHY_BCM84888_MODEL, 6949 PHY_REV_ALL}, 6950 { _phy_id_BCM84884, PHY_BCM84884_OUI, PHY_BCM84884_MODEL, 6951 PHY_REV_ALL}, 6952 { _phy_id_BCM84888E, PHY_BCM84888E_OUI, PHY_BCM84888E_MODEL, 6953 PHY_REV_ALL}, 6954 { _phy_id_BCM84884E, PHY_BCM84884E_OUI, PHY_BCM84884E_MODEL, 6955 PHY_REV_ALL}, 6956 { _phy_id_BCM84881, PHY_BCM84881_OUI, PHY_BCM84881_MODEL, 6957 PHY_REV_ALL}, 6958 { _phy_id_BCM84880, PHY_BCM84880_OUI, PHY_BCM84880_MODEL, 6959 PHY_REV_ALL}, 6960 { _phy_id_BCM84888S, PHY_BCM84888S_OUI, PHY_BCM84888S_MODEL, 6961 PHY_REV_ALL}, 6962 { _phy_id_BCM84885, PHY_BCM84885_OUI, PHY_BCM84885_MODEL, 6963 PHY_REV_ALL}, 6964 { _phy_id_BCM84886, PHY_BCM84886_OUI, PHY_BCM84886_MODEL, 6965 PHY_REV_ALL}, 6966 { _phy_id_BCM84887, PHY_BCM84887_OUI, PHY_BCM84887_MODEL, 6967 PHY_REV_ALL}, 6968 #ifdef INCLUDE_PHY_84328 6969 { _phy_id_BCM84328, PHY_BCM84328_OUI, PHY_BCM84328_MODEL, 6970 PHY_REV_ALL}, 6971 #endif 6972 #ifdef INCLUDE_PHY_84793 6973 { _phy_id_BCM84793, PHY_BCM84793_OUI, PHY_BCM84793_MODEL, 6974 PHY_REV_ALL}, 6975 #endif 6976 #ifdef INCLUDE_PHY_82328 6977 { _phy_id_BCM82328, PHY_BCM82328_OUI, PHY_BCM82328_MODEL, 6978 PHY_REV_ALL}, 6979 #endif 6980 #ifdef INCLUDE_PHY_82780 6981 { _phy_id_BCM82780, PHY_BCM82780_OUI, PHY_BCM82780_MODEL, 6982 PHY_REV_ALL}, 6983 #endif 6984 6985 #ifdef INCLUDE_PHY_84740 6986 { _phy_id_BCM84318, PHY_BCM84318_OUI, PHY_BCM84318_MODEL, 6987 PHY_REV_ALL}, 6988 #endif 6989 { _phy_id_BCMXGXS1, PHY_BCMXGXS1_OUI, PHY_BCMXGXS1_MODEL, 6990 PHY_REV_ALL}, 6991 /* 6992 * HL65 has the same device ID as XGXS1. 6993 *{ _phy_id_XGXS_HL65, PHY_XGXS_HL65_OUI, PHY_XGXS_HL65_MODEL, 6994 * PHY_REV_ALL } 6995 */ 6996 { _phy_id_BCMXGXS2, PHY_BCMXGXS2_OUI, PHY_BCMXGXS2_MODEL, 6997 PHY_REV_ALL}, 6998 { _phy_id_BCMXGXS5, PHY_BCMXGXS5_OUI, PHY_BCMXGXS5_MODEL, 6999 PHY_REV_ALL}, 7000 { _phy_id_BCMXGXS6, PHY_BCMXGXS6_OUI, PHY_BCMXGXS6_MODEL, 7001 PHY_REV_ALL}, 7002 { _phy_id_BCM53314, PHY_BCM53314_OUI, PHY_BCM53314_MODEL, 7003 PHY_REV_ALL}, 7004 { _phy_id_BCM53324, PHY_BCM53324_OUI, PHY_BCM53324_MODEL, 7005 PHY_REV_ALL}, 7006 { _phy_id_BCM56160_GPHY, PHY_BCM56160GPHY_OUI, PHY_BCM56160GPHY_MODEL, 7007 PHY_REV_ALL}, 7008 { _phy_id_BCM53540, PHY_BCM53540_OUI, PHY_BCM53540_MODEL, 7009 PHY_REV_ALL}, 7010 { _phy_id_SERDES100FX, PHY_SERDES100FX_OUI, PHY_SERDES100FX_MODEL, 7011 PHY_REV_4 | PHY_REV_5}, 7012 { _phy_id_SERDES65LP, PHY_SERDES65LP_OUI, PHY_SERDES65LP_MODEL, 7013 PHY_REV_ALL}, 7014 { _phy_id_SERDESCOMBO, PHY_SERDESCOMBO_OUI, PHY_SERDESCOMBO_MODEL, 7015 PHY_REV_8 }, 7016 { _phy_id_XGXS_16G, PHY_XGXS_16G_OUI, PHY_XGXS_16G_MODEL, 7017 PHY_REV_0 }, 7018 { _phy_id_XGXS_TSC, PHY_XGXS_TSC_OUI, PHY_XGXS_TSC_MODEL, 7019 PHY_REV_0 }, 7020 { _phy_id_XGXS_VIPER, PHY_XGXS_VIPER_OUI, PHY_XGXS_VIPER_MODEL, 7021 PHY_REV_9 }, 7022 #ifdef INCLUDE_PHY_82381 7023 { _phy_id_BCM82381, PHY_BCM82381_OUI, PHY_BCM82381_MODEL, 7024 PHY_REV_ALL}, 7025 #endif 7026 #ifdef INCLUDE_PHY_82764 7027 { _phy_id_BCM82764, PHY_BCM82764_OUI, PHY_BCM82764_MODEL, 7028 PHY_REV_ALL}, 7029 #endif 7030 #ifdef INCLUDE_PHY_82864 7031 { _phy_id_BCM82864, PHY_BCM82864_OUI, PHY_BCM82864_MODEL, 7032 PHY_REV_ALL}, 7033 #endif 7034 7035 7036 }; 7037 7038 /* 7039 * Function: 7040 * _phy_ident_type_get 7041 * Purpose: 7042 * Check the PHY ID and return an enumerated value indicating 7043 * the PHY. This looks very redundant, but in the future, more 7044 * complicated PHY detection may be necessary. In addition, the 7045 * enum value could be used as an index. 7046 * Parameters: 7047 * phy_id0 - PHY ID register 0 (MII register 2) 7048 * phy_id1 - PHY ID register 1 (MII register 3) 7049 */ 7050 7051 static soc_known_phy_t 7052 _phy_ident_type_get(uint16 phy_id0, uint16 phy_id1) 7053 { 7054 int i; 7055 phy_id_map_t *pm; 7056 uint32 oui; 7057 uint16 model, rev_map; 7058 7059 oui = PHY_OUI(phy_id0, phy_id1); 7060 model = PHY_MODEL(phy_id0, phy_id1); 7061 rev_map = 1 << PHY_REV(phy_id0, phy_id1); 7062 7063 LOG_INFO(BSL_LS_SOC_PHY, 7064 (BSL_META("phy_id0 = %04x phy_id1 %04x oui = %04x model = %04x rev_map = %04x\n"), 7065 phy_id0, phy_id1, oui, model, rev_map)); 7066 for (i = 0; i < COUNTOF(phy_id_map); i++) { 7067 pm = &phy_id_map[i]; 7068 if ((pm->oui == oui) && (pm->model == model)) { 7069 if (pm->rev_map & rev_map) { 7070 return pm->phy_num; 7071 } 7072 } 7073 } 7074 7075 return _phy_id_unknown; 7076 } 7077 7078 /* 7079 * Function: 7080 * soc_phy_nocxn 7081 * Purpose: 7082 * Return the no_cxn PHY driver 7083 * Parameters: 7084 * unit - StrataSwitch unit #. 7085 * phyd_ptr - (OUT) Pointer to PHY driver. 7086 * Returns: 7087 * SOC_E_XXX 7088 */ 7089 7090 int 7091 soc_phy_nocxn(int unit, phy_driver_t **phyd_ptr) 7092 { 7093 *phyd_ptr = &phy_nocxn; 7094 7095 return SOC_E_NONE; 7096 } 7097 7098 /* 7099 * Function: 7100 * soc_phy_info_get 7101 * Purpose: 7102 * Accessor function to copy out PHY info structure 7103 * Parameters: 7104 * unit - StrataSwitch unit #. 7105 * port - StrataSwitch port #. 7106 * pi - (OUT) Pointer to output structure. 7107 * Returns: 7108 * SOC_E_XXX 7109 */ 7110 7111 int 7112 soc_phy_info_get(int unit, soc_port_t port, soc_phy_info_t *pi) 7113 { 7114 soc_phy_info_t *source; 7115 7116 source = &SOC_PHY_INFO(unit, port); 7117 7118 sal_memcpy(pi, source, sizeof(soc_phy_info_t)); 7119 return SOC_E_NONE; 7120 } 7121 7122 /* 7123 * Function: 7124 * soc_phy_an_timeout_get 7125 * Purpose: 7126 * Return autonegotiation timeout for a specific port 7127 * Parameters: 7128 * unit - StrataSwitch unit #. 7129 * port - StrataSwitch port #. 7130 * Returns: 7131 * Timeout in usec 7132 */ 7133 7134 sal_usecs_t 7135 soc_phy_an_timeout_get(int unit, soc_port_t port) 7136 { 7137 return PHY_AN_TIMEOUT(unit, port); 7138 } 7139 7140 /* 7141 * Function: 7142 * soc_phy_addr_of_port 7143 * Purpose: 7144 * Return PHY ID of the PHY attached to a specified port. 7145 * Parameters: 7146 * unit - StrataSwitch unit #. 7147 * port - StrataSwitch port #. 7148 * Returns: 7149 * PHY ID 7150 */ 7151 7152 uint16 7153 soc_phy_addr_of_port(int unit, soc_port_t port) 7154 { 7155 return PHY_ADDR(unit, port); 7156 } 7157 7158 /* 7159 * Function: 7160 * soc_phy_addr_int_of_port 7161 * Purpose: 7162 * Return PHY ID of a intermediate PHY on specified port. 7163 * Parameters: 7164 * unit - StrataSwitch unit #. 7165 * port - StrataSwitch port #. 7166 * Returns: 7167 * PHY ID 7168 * Notes: 7169 * Only applies to chip ports that have an intermediate PHY. 7170 */ 7171 7172 uint16 7173 soc_phy_addr_int_of_port(int unit, soc_port_t port) 7174 { 7175 return PHY_ADDR_INT(unit, port); 7176 } 7177 7178 /* 7179 * Function: 7180 * soc_phy_cfg_addr_get 7181 * Purpose: 7182 * Get the configured PHY address for this port. 7183 * Parameters: 7184 * unit - StrataSwitch unit #. 7185 * port - StrataSwitch port #. 7186 * flag - internal phy or external phy 7187 * addr_ptr - hold the retrieved address 7188 * Returns: 7189 * SOC_E_NONE 7190 */ 7191 7192 int 7193 soc_phy_cfg_addr_get(int unit, soc_port_t port, int flags, uint16 *addr_ptr) 7194 { 7195 if (flags & SOC_PHY_INTERNAL) { 7196 *addr_ptr = port_phy_addr[unit][port].int_addr; 7197 } else { 7198 *addr_ptr = soc_property_port_get(unit, port, 7199 spn_PORT_PHY_ADDR, 7200 port_phy_addr[unit][port].ext_addr); 7201 } 7202 return SOC_E_NONE; 7203 } 7204 7205 /* 7206 * Function: 7207 * soc_phy_cfg_addr_set 7208 * Purpose: 7209 * Configure the port with the given PHY address. 7210 * Parameters: 7211 * unit - StrataSwitch unit #. 7212 * port - StrataSwitch port #. 7213 * flag - internal phy or external phy 7214 * addr - the address to set 7215 * Returns: 7216 * SOC_E_NONE 7217 */ 7218 7219 int 7220 soc_phy_cfg_addr_set(int unit, soc_port_t port, int flags, uint16 addr) 7221 { 7222 if (flags & SOC_PHY_INTERNAL) { 7223 port_phy_addr[unit][port].int_addr = addr; 7224 } else { 7225 port_phy_addr[unit][port].ext_addr = addr; 7226 } 7227 return SOC_E_NONE; 7228 } 7229 7230 /* 7231 * Function: 7232 * soc_phy_addr_to_port 7233 * Purpose: 7234 * Return the port to which a given PHY ID corresponds. 7235 * Parameters: 7236 * unit - StrataSwitch unit #. 7237 * port - StrataSwitch port #. 7238 * Returns: 7239 * Port number 7240 */ 7241 7242 soc_port_t 7243 soc_phy_addr_to_port(int unit, uint16 phy_id) 7244 { 7245 return PHY_ADDR_TO_PORT(unit, phy_id); 7246 } 7247 7248 /* 7249 * Function: 7250 * soc_phy_id1reg_get 7251 * Purpose: 7252 * Return the PHY ID1 field from the PHY on a specified port. 7253 * Parameters: 7254 * unit - StrataSwitch unit #. 7255 * port - StrataSwitch port #. 7256 * Returns: 7257 * PHY ID 7258 */ 7259 7260 uint16 7261 soc_phy_id1reg_get(int unit, soc_port_t port) 7262 { 7263 return PHY_ID1_REG(unit, port); 7264 } 7265 7266 /* 7267 * Function: 7268 * soc_phy_id1reg_get 7269 * Purpose: 7270 * Return the PHY ID0 field from the PHY on a specified port. 7271 * Parameters: 7272 * unit - StrataSwitch unit #. 7273 * port - StrataSwitch port #. 7274 * Returns: 7275 * PHY ID 7276 */ 7277 7278 uint16 7279 soc_phy_id0reg_get(int unit, soc_port_t port) 7280 { 7281 return PHY_ID0_REG(unit, port); 7282 } 7283 7284 /* 7285 * Function: 7286 * soc_phy_is_c45_miim 7287 * Purpose: 7288 * Return TRUE if Phy uses Clause 45 MIIM, FALSE otherwise 7289 * Parameters: 7290 * unit - StrataSwitch unit #. 7291 * port - StrataSwitch port #. 7292 * Returns: 7293 * Return TRUE if Phy uses Clause 45 MIIM, FALSE otherwise 7294 */ 7295 7296 int 7297 soc_phy_is_c45_miim(int unit, soc_port_t port) 7298 { 7299 return PHY_CLAUSE45_MODE(unit, port); 7300 } 7301 7302 /* 7303 * Function: 7304 * soc_phy_name_get 7305 * Purpose: 7306 * Return name of PHY driver corresponding to specified port. 7307 * Parameters: 7308 * unit - StrataSwitch unit #. 7309 * port - StrataSwitch port #. 7310 * Returns: 7311 * Static pointer to string. 7312 */ 7313 7314 char * 7315 soc_phy_name_get(int unit, soc_port_t port) 7316 { 7317 if (PHY_NAME(unit, port) != NULL) { 7318 return PHY_NAME(unit, port); 7319 } else { 7320 return "<Unnamed PHY>"; 7321 } 7322 } 7323 7324 #if (defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT)) 7325 #ifdef BROADCOM_DEBUG 7326 /* 7327 * Function: 7328 * soc_phy_dump 7329 * Purpose: 7330 * Display the phy dirvers that are compiled into the driver. 7331 * Parameters: 7332 * unit - StrataSwitch unit #. 7333 * Returns: 7334 * none 7335 */ 7336 7337 void soc_phy_dump(void) 7338 { 7339 int idx1, idx2; 7340 7341 for(idx1 = 0; idx1 < _phys_in_table; idx1 += 4) { 7342 if ( idx1 == 0 ) { 7343 LOG_CLI((BSL_META("PHYs: "))); 7344 } else { 7345 LOG_CLI((BSL_META(" "))); 7346 } 7347 for(idx2 = idx1; idx2 < idx1 + 4 && idx2 < _phys_in_table; idx2++) { 7348 LOG_CLI((BSL_META("\t%s%s"), 7349 phy_table[idx2]->phy_name, 7350 idx2 < _phys_in_table? "," : "")); 7351 } 7352 LOG_CLI((BSL_META("\n"))); 7353 } 7354 7355 return; 7356 } 7357 #endif /* BROADCOM_DEBUG */ 7358 7359 7360 int 7361 soc_phy_list_get(char *phy_list[],int phy_list_size,int *phys_in_list) 7362 { 7363 int idx, base; 7364 7365 if (phy_list == NULL) { 7366 return SOC_E_PARAM; 7367 } 7368 7369 if (phys_in_list == NULL) { 7370 return SOC_E_PARAM; 7371 } 7372 7373 base = *phys_in_list; 7374 7375 /* Check invalid param */ 7376 if ((base < 0) || (base > _MAX_PHYS)) { 7377 return SOC_E_PARAM; 7378 } 7379 7380 /* Check invalid table */ 7381 if ((_phys_in_table < 0) || (_phys_in_table > _MAX_PHYS)) { 7382 return SOC_E_INTERNAL; 7383 } 7384 7385 if ((phy_list_size + base) < _phys_in_table) { 7386 /* If phy_list can be completely filled 7387 i.e the phy_table has more elements starting from base 7388 than the size of phy_list */ 7389 *phys_in_list = phy_list_size; 7390 } else { 7391 /* If phy_list cannot be completely filled 7392 i.e the phy_table has less elements starting from base 7393 than the size of phy_list*/ 7394 *phys_in_list = _phys_in_table - base; 7395 } 7396 7397 /* At this point phys_in_list has the number of items(phys) 7398 that are going to be set in phy_list starting from the base 7399 in phy_table[] 7400 */ 7401 for (idx = 0; (idx < *phys_in_list) && (idx + base < _MAX_PHYS); idx++) { 7402 /* coverity[overrun-local : FALSE] */ 7403 phy_list[idx] = phy_table[idx + base]->phy_name; 7404 } 7405 7406 /* Returns the status to the calling function if 7407 there are still more entries in the list */ 7408 if ((idx + base) < _phys_in_table) { 7409 return SOC_E_FULL; 7410 } 7411 return SOC_E_NONE; 7412 } 7413 7414 #endif /* (defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT)) */