phyfege.h (14184B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phylocal.h 8 * Purpose: 9 */ 10 11 #ifndef _PHYLOCAL_H_ 12 #define _PHYLOCAL_H_ 13 14 /* microsec */ 15 #define PHY_RESET_TIMEOUT_USEC \ 16 (SAL_BOOT_SIMULATION ? 10000000 : 10000) 17 18 /* Driver functions */ 19 extern int phy_fe_ge_reset(int unit, soc_port_t port, void *user_arg); 20 extern int phy_fe_ge_enable_get(int unit, soc_port_t port, int *enable); 21 extern int phy_fe_ge_enable_set(int unit, soc_port_t port, int enable); 22 extern int phy_fe_init(int unit, soc_port_t port); 23 extern int phy_ge_init(int unit, soc_port_t port); 24 extern int phy_fe_ge_link_get(int unit, soc_port_t port, int *link); 25 extern int phy_fe_ge_duplex_set(int unit, soc_port_t port, int duplex); 26 extern int phy_fe_ge_duplex_get(int unit, soc_port_t port, int *duplex); 27 extern int phy_fe_ge_speed_set(int unit, soc_port_t port, int speed); 28 extern int phy_fe_ge_speed_get(int unit, soc_port_t port, int *speed); 29 extern int phy_fe_ge_master_set(int unit, soc_port_t port, int master); 30 extern int phy_fe_ge_master_get(int unit, soc_port_t port, int *master); 31 extern int phy_fe_ge_an_set(int unit, soc_port_t port, int an); 32 extern int phy_fe_ge_an_get(int unit, soc_port_t port, int *an, 33 int *an_done); 34 extern int phy_fe_adv_local_set(int unit, soc_port_t port, 35 soc_port_mode_t mode); 36 extern int phy_fe_adv_local_get(int unit, soc_port_t port, 37 soc_port_mode_t *mode); 38 extern int phy_fe_adv_remote_get(int unit, soc_port_t port, 39 soc_port_mode_t *mode); 40 extern int phy_ge_adv_local_set(int unit, soc_port_t port, 41 soc_port_mode_t mode); 42 extern int phy_ge_adv_local_get(int unit, soc_port_t port, 43 soc_port_mode_t *mode); 44 extern int phy_ge_adv_remote_get(int unit, soc_port_t port, 45 soc_port_mode_t *mode); 46 extern int phy_fe_ge_lb_set(int unit, soc_port_t port, int enable); 47 extern int phy_fe_ge_lb_get(int unit, soc_port_t port, int *enable); 48 extern int phy_fe_interface_set(int unit, soc_port_t port, soc_port_if_t pif); 49 extern int phy_fe_interface_get(int unit, soc_port_t port, soc_port_if_t *pif); 50 extern int phy_ge_interface_set(int unit, soc_port_t port, soc_port_if_t pif); 51 extern int phy_ge_interface_get(int unit, soc_port_t port, soc_port_if_t *pif); 52 extern int phy_fe_ability_get(int unit, soc_port_t port, 53 soc_port_mode_t *mode); 54 extern int phy_ge_ability_get(int unit, soc_port_t port, 55 soc_port_mode_t *mode); 56 extern int phy_fe_ge_mdix_set(int unit, soc_port_t port, 57 soc_port_mdix_t mode); 58 extern int phy_fe_ge_mdix_get(int unit, soc_port_t port, 59 soc_port_mdix_t *mode); 60 extern int phy_fe_ge_mdix_status_get(int unit, soc_port_t port, 61 soc_port_mdix_status_t *status); 62 extern int phy_fe_ge_medium_get(int unit, soc_port_t port, 63 soc_port_medium_t *medium); 64 extern int phy_fe_cable_diag(int unit, soc_port_t port, 65 soc_port_cable_diag_t *status); 66 extern int phy_fe_ge_ability_advert_set(int unit, soc_port_t port, 67 soc_port_ability_t *ability); 68 extern int phy_fe_ge_ability_advert_get(int unit, soc_port_t port, 69 soc_port_ability_t *ability); 70 extern int phy_fe_ge_ability_remote_get(int unit, soc_port_t port, 71 soc_port_ability_t *ability); 72 73 extern int phy_ge_reg_read(int unit, soc_port_t port, uint32 flags, 74 uint32 phy_reg_addr, uint32 *phy_data); 75 extern int phy_ge_reg_write(int unit, soc_port_t port, uint32 flags, 76 uint32 phy_reg_addr, uint32 phy_data); 77 extern int phy_ge_reg_modify(int unit, soc_port_t port, uint32 flags, 78 uint32 phy_reg_addr, uint32 phy_data, 79 uint32 phy_data_mask); 80 81 #define _SOC_PHY_REG_DIRECT \ 82 ((SOC_PHY_REG_1000X << 1) | (SOC_PHY_REG_1000X >> 1)) 83 84 /* PHY register access */ 85 #define PHYFEGE_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 86 READ_PHY_REG((_unit), (_phy_ctrl), (_reg_addr), (_val)) 87 #define PHYFEGE_REG_WRITE(_unit, _phy_ctrl, _flags, \ 88 _reg_bank, _reg_addr, _val) \ 89 phy_reg_ge_write((_unit), (_phy_ctrl), (_SOC_PHY_REG_DIRECT), \ 90 (0), (_reg_addr), (_val)) 91 #define PHYFEGE_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 92 _reg_addr, _val, _mask) \ 93 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_reg_addr), (_val), (_mask)) 94 95 /* IEEE Standard Registers */ 96 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 97 #define READ_PHYFEGE_MII_CTRLr(_unit, _phy_ctrl, _val) \ 98 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 99 #define WRITE_PHYFEGE_MII_CTRLr(_unit, _phy_ctrl, _val) \ 100 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 101 #define MODIFY_PHYFEGE_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 102 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 103 (_val), (_mask)) 104 105 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 106 #define READ_PHYFEGE_MII_STATr(_unit, _phy_ctrl, _val) \ 107 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 108 #define WRITE_PHYFEGE_MII_STATr(_unit, _phy_ctrl, _val) \ 109 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 110 #define MODIFY_PHYFEGE_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 111 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 112 (_val), (_mask)) 113 114 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 115 #define READ_PHYFEGE_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 116 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 117 #define WRITE_PHYFEGE_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 118 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 119 #define MODIFY_PHYFEGE_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 120 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 121 (_val), (_mask)) 122 123 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 124 #define READ_PHYFEGE_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 125 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 126 #define WRITE_PHYFEGE_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 127 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 128 #define MODIFY_PHYFEGE_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 129 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 130 (_val), (_mask)) 131 132 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 133 #define READ_PHYFEGE_MII_ANAr(_unit, _phy_ctrl, _val) \ 134 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 135 #define WRITE_PHYFEGE_MII_ANAr(_unit, _phy_ctrl, _val) \ 136 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 137 #define MODIFY_PHYFEGE_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 138 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 139 (_val), (_mask)) 140 141 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 142 #define READ_PHYFEGE_MII_ANPr(_unit, _phy_ctrl, _val) \ 143 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 144 #define WRITE_PHYFEGE_MII_ANPr(_unit, _phy_ctrl, _val) \ 145 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 146 #define MODIFY_PHYFEGE_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 147 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 148 (_val), (_mask)) 149 150 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 151 #define READ_PHYFEGE_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 152 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 153 #define WRITE_PHYFEGE_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 154 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 155 #define MODIFY_PHYFEGE_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 156 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 157 (_val), (_mask)) 158 159 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 160 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 161 162 /* 1000BASE-T Control Register (ADDR 09h) */ 163 #define READ_PHYFEGE_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 164 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 165 #define WRITE_PHYFEGE_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 166 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 167 #define MODIFY_PHYFEGE_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 168 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 169 (_val), (_mask)) 170 171 /* 1000BASE-T Status Register (ADDR 0ah) */ 172 #define READ_PHYFEGE_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 173 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 174 #define WRITE_PHYFEGE_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 175 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 176 #define MODIFY_PHYFEGE_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 177 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 178 (_val), (_mask)) 179 180 /* (Addr 0ch-0eh) Reserved (Do not read/write to reserved registers. */ 181 182 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 183 #define READ_PHYFEGE_MII_ESRr(_unit, _phy_ctrl, _val) \ 184 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0f, (_val)) 185 #define WRITE_PHYFEGE_MII_ESRr(_unit, _phy_ctrl, _val) \ 186 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0f, (_val)) 187 #define MODIFY_PHYFEGE_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 188 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0f, \ 189 (_val), (_mask)) 190 191 /* None Standard Registers */ 192 /* Extended Control Register (Addr 0x10) */ 193 #define READ_PHYFEGE_MII_ECRr(_unit, _phy_ctrl, _val) \ 194 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 195 #define WRITE_PHYFEGE_MII_ECRr(_unit, _phy_ctrl, _val) \ 196 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 197 #define MODIFY_PHYFEGE_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 198 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 199 (_val), (_mask)) 200 201 /* SHA CD Control Register (Addr 0x13) */ 202 /* SHA CD Sel Register (Addr 0x14) */ 203 204 /* Auxiliary Control/Status Register (Addr 0x18) */ 205 #define READ_PHYFEGE_MII_AUXr(_unit, _phy_ctrl, _val) \ 206 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 207 #define WRITE_PHYFEGE_MII_AUXr(_unit, _phy_ctrl, _val) \ 208 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 209 #define MODIFY_PHYFEGE_MII_AUXr(_unit, _phy_ctrl, _val, _mask) \ 210 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 211 (_val), (_mask)) 212 213 /* Auxiliary Status Summary Register (Addr 0x19) */ 214 #define READ_PHYFEGE_MII_ASSRr(_unit, _phy_ctrl, _val) \ 215 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x19, (_val)) 216 #define WRITE_PHYFEGE_MII_ASSRr(_unit, _phy_ctrl, _val) \ 217 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x19, (_val)) 218 #define MODIFY_PHYFEGE_MII_ASSRr(_unit, _phy_ctrl, _val, _mask) \ 219 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x19, \ 220 (_val), (_mask)) 221 222 /* SHA Auxiliary Status 2 Register (Addr 0x1b) */ 223 224 /* General Status Register (BROADCOM) (Addr 0x1c) */ 225 #define READ_PHYFEGE_MII_GSRr(_unit, _phy_ctrl, _val) \ 226 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1c, (_val)) 227 #define WRITE_PHYFEGE_MII_GSRr(_unit, _phy_ctrl, _val) \ 228 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1c, (_val)) 229 #define MODIFY_PHYFEGE_MII_GSRr(_unit, _phy_ctrl, _val, _mask) \ 230 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1c, \ 231 (_val), (_mask)) 232 233 /* Master/Slave Seed Register (BROADCOM) (Addr 0x1d) */ 234 #define READ_PHYFEGE_MII_MSSEEDr(_unit, _phy_ctrl, _val) \ 235 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1d, (_val)) 236 #define WRITE_PHYFEGE_MII_MSSEEDr(_unit, _phy_ctrl, _val) \ 237 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1d, (_val)) 238 #define MODIFY_PHYFEGE_MII_MSSEEDr(_unit, _phy_ctrl, _val, _mask) \ 239 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1d, \ 240 (_val), (_mask)) 241 242 /* Auxiliary Multiple PHY (BROADCOM) (Addr 0x1e) */ 243 #define READ_PHYFEGE_MII_AUX_MULTI_PHYr(_unit, _phy_ctrl, _val) \ 244 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 245 #define WRITE_PHYFEGE_MII_AUX_MULTI_PHYr(_unit, _phy_ctrl, _val) \ 246 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 247 #define MODIFY_PHYFEGE_MII_AUX_MULTI_PHYr(_unit, _phy_ctrl, _val, _mask) \ 248 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 249 (_val), (_mask)) 250 251 /* Test 2 Register (Addr 0x1f) */ 252 #define READ_PHYFEGE_MII_TEST2r(_unit, _phy_ctrl, _val) \ 253 PHYFEGE_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1f, (_val)) 254 #define WRITE_PHYFEGE_MII_TEST2r(_unit, _phy_ctrl, _val) \ 255 PHYFEGE_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1f, (_val)) 256 #define MODIFY_PHYFEGE_MII_TEST2r(_unit, _phy_ctrl, _val, _mask) \ 257 PHYFEGE_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1f, \ 258 (_val), (_mask)) 259 260 #endif /* _PHYFEGE_H_ */