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phyaddr.h (4125B)


      1 /*
      2  * 
      3  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      4  * 
      5  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      6  *
      7  * File:        phyaddr.h
      8  * Purpose:     Basic defines for PHY configuration
      9  */
     10 
     11 #ifndef _PHY_ADDR_H
     12 #define _PHY_ADDR_H
     13 
     14 #define _XGS12_FABRIC_PHY_ADDR_DEFAULT(_unit, _port, _phy_addr, _phy_addr_int) \
     15         do {                            \
     16             *(_phy_addr)     = (_port); \
     17             *(_phy_addr_int) = (_port); \
     18         } while (0)
     19 
     20 
     21 #define _DRACO_PHY_ADDR_DEFAULT(_unit, _port, _phy_addr, _phy_addr_int) \
     22         do {                                           \
     23             if (IS_GE_PORT((_unit), (_port))) {        \
     24                 *(_phy_addr) = (_port) + 1;            \
     25                 *(_phy_addr_int) = (_port) + 0x80;     \
     26             } else {                                   \
     27                 *(_phy_addr) = (_port) + 0x80;         \
     28                 *(_phy_addr_int) = (_port) + 0x80;     \
     29             }                                          \
     30         } while (0)
     31 
     32 #define _LYNX_PHY_ADDR_DEFAULT(_unit, _port, _phy_addr, _phy_addr_int) \
     33         do {                                           \
     34             *(_phy_addr) = (_port) + 1;                \
     35             *(_phy_addr_int) = (_port) + 0x80;         \
     36         } while (0)
     37 
     38 #define _RAPTOR_PHY_ADDR_DEFAULT(_unit, _port, _phy_addr, _phy_addr_int)    \
     39         do {                                                                \
     40            /*                                                               \
     41             * MDIO address and MDIO bus select for External Phy             \
     42             * port 0  - 0  CPU (_port) no external MDIO address             \
     43             * port 1  - 2  MDIO address 2, 3 (0x2 - 0x3)                    \
     44             * port 3  - 3  No internal MDIO                                 \
     45             * port 4  - 5  MDIO address 4, 6 (0x4 - 0x6)                    \
     46             * port 6  - 29 MDIO address 7,30 (0x7 - 0x1e)                   \
     47             * port 30 - 53 MDIO address 1,24 (0x41 - 0x58 with Bus sel set) \
     48             */                                                              \
     49             *(_phy_addr) = (_port) +                                        \
     50                            (((_port) > 29) ? (0x40 - 29) : (1));            \
     51           /*                                                                \
     52            * MDIO address and MDIO bus select for Internal Phy (Serdes)     \
     53            * port 0  - 0  CPU (_port) no internal MDIO address              \
     54            * port 1  - 2  MDIO address 1,2 (0x81 - 0x82 with Intenal sel set) \
     55            * port 3  - 3  No internal MDIO                                    \
     56            * port 4  - 5  MDIO address 4, 5 (0x84 - 0x85 with Intenal sel set)\
     57            * port 6  - 29 MDIO address 6,29 (0x86 - 0x9D with Intenal sel set)\
     58            * port 30 - 53 MDIO address 0,23 (0xc0 - 0xd7 with Intenal sel set)\
     59            */                                                               \
     60             *(_phy_addr_int) = (_port) +                                    \
     61                                (((_port) > 29) ? (0xc0 - 30) : (0x80));     \
     62          } while (0)
     63 
     64 #define _TUCANA_PHY_ADDR_DEFAULT(_unit, _port, _phy_addr, _phy_addr_int) \
     65         do {                                           \
     66             if (IS_HG_PORT(unit, (_port))) {           \
     67                 *(_phy_addr) = (_port) + 0x80;         \
     68                 *(_phy_addr_int) = (_port) + 0x80;     \
     69             } else {                                   \
     70                 *(_phy_addr) = (_port) + 1;            \
     71                 *(_phy_addr_int) = 0xff;               \
     72             }                                          \
     73          } while (0)
     74 
     75 #define _STRATA_PHY_ADDR_DEFAULT(_unit, _port, _phy_addr, _phy_addr_int) \
     76         do {                                           \
     77             *(_phy_addr) = (_port) + 1;                \
     78             *(_phy_addr_int) = 0xff;                   \
     79         } while (0)
     80 
     81 #endif /* _PHY_ADDR_H */