phy_xmac.h (10749B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 9 #ifndef _XMAC_MAC_H_ 10 #define _XMAC_MAC_H_ 11 12 #include <bbase_types.h> 13 #include "phy_mac_ctrl.h" 14 15 extern int phy_xmac_mac_init(phy_mac_ctrl_t *mmc, int dev_port); 16 17 extern int phy_xmac_mac_fcmap_init(phy_mac_ctrl_t *mmc, int dev_port); 18 19 extern int phy_xmac_mac_reset(phy_mac_ctrl_t *mmc, int dev_port, int fval); 20 21 extern int phy_xmac_mac_enable_set(phy_mac_ctrl_t *mmc, 22 int dev_port, int en); 23 24 extern int phy_xmac_mac_enable_get(phy_mac_ctrl_t *mmc, 25 int dev_port, int *en) ; 26 27 extern int phy_xmac_mac_update_ipg(phy_mac_ctrl_t *mmc, 28 int dev_port, int ipg); 29 30 extern int phy_xmac_mac_max_frame_set(phy_mac_ctrl_t *mmc, 31 int dev_port, buint32_t max_frame); 32 33 extern int phy_xmac_mac_max_frame_get(phy_mac_ctrl_t *mmc, 34 int dev_port, buint32_t *flen); 35 36 extern int phy_xmac_mac_pause_frame_fwd(phy_mac_ctrl_t *mmc, 37 int dev_port, int pause_fwd); 38 39 extern int phy_xmac_mac_pause_set(phy_mac_ctrl_t *mmc, 40 int dev_port, int pause); 41 42 extern int phy_xmac_mac_speed_set(phy_mac_ctrl_t *mmc, 43 int dev_port, int speed); 44 45 extern int phy_xmac_mac_speed_get(phy_mac_ctrl_t *mmc, 46 int dev_port, int *speed); 47 48 extern int phy_xmac_mac_duplex_set(phy_mac_ctrl_t *mmc, 49 int dev_port, int duplex); 50 51 extern int phy_xmac_mac_duplex_get(phy_mac_ctrl_t *mmc, 52 int dev_port, int *duplex); 53 54 extern int phy_xmac_mac_auto_cfg_set(phy_mac_ctrl_t *mmc, 55 int dev_port, int enable); 56 57 extern int phy_xmac_mac_readtx(phy_mac_ctrl_t *mmc, int dev_port); 58 59 #define XMAC_64_HI_SET(u64, val)\ 60 COMPILER_64_SET(u64, (val) , COMPILER_64_LO(u64)); 61 62 #define XMAC_64_LO_SET(u64, val)\ 63 COMPILER_64_SET(u64, COMPILER_64_HI(u64), (val)); 64 65 /* 66 * XMAC Control Register 67 */ 68 #define XMAC_MAC_CTRL_TXEN_MASK (1 << 0) 69 #define XMAC_MAC_CTRL_RXEN_MASK (1 << 1) 70 #define XMAC_MAC_CTRL_LB_LL_MASK (1 << 2) 71 #define XMAC_MAC_CTRL_LB_CL_MASK (1 << 3) 72 #define XMAC_MAC_CTRL_LB_LR_MASK (1 << 4) 73 #define XMAC_MAC_CTRL_LB_CR_MASK (1 << 5) 74 #define XMAC_MAC_CTRL_RESET_MASK (1 << 6) 75 76 #define XMAC_MAC_CTRL_TXEN_SHIFT 0 77 #define XMAC_MAC_CTRL_RXEN_SHIFT 1 78 #define XMAC_MAC_CTRL_RESET_SHIFT 6 79 80 81 /* 82 * XMAC TX Control Register 83 */ 84 #define XMAC_TX_CTRL_CRCMODE_MASK (3 << 0) 85 #define XMAC_TX_CTRL_IPG_MASK (0x7f << 12) 86 87 88 #define XMAC_TX_CTRL_CRCMODE_SHIFT 0 89 #define XMAC_TX_CTRL_IPG_SHIFT 12 90 91 /* DEFAULT IPG */ 92 #define XMAC_MAC_DEFAULT_IPG 12 93 94 95 /* 96 * XMAC RX Control Register 97 */ 98 #define XMAC_RX_CTRL_PASS_MAC_CNTL_MASK (1 << 0) 99 #define XMAC_RX_CTRL_CRCSTRIP_MASK (1 << 2) 100 101 102 #define XMAC_RX_CTRL_PASS_MAC_CNTL_SHIFT 0 103 #define XMAC_RX_CTRL_CRCSTRIP_SHIFT 2 104 105 /* 106 * XMAC RX LSS Control Register 107 */ 108 #define XMAC_RX_LSS_CTRL_DISABLE_MASK (3 << 0) 109 110 /* 111 * XMAC RX MACSEC Control Register 112 */ 113 #define XMAC_MACSEC_CTRL_TX_CRC_CORRUPT_MASK (1 << 1) 114 115 #define XMAC_MACSEC_CTRL_TX_CRC_CORRUPT_SHIFT 1 116 117 /* 118 * XMAC PAUSE Control Register 119 */ 120 #define XMAC_TX_EN_PAUSE_MASK (1 << 17) 121 #define XMAC_RX_EN_PAUSE_MASK (1 << 18) 122 123 #define XMAC_TX_EN_PAUSE_SHIFT 17 124 #define XMAC_RX_EN_PAUSE_SHIFT 18 125 126 127 /* 128 * CRC Forward 129 */ 130 #define XMAC_MAC_CTRL_CRC_FWD_DISABLE 0 131 #define XMAC_MAC_CTRL_CRC_FWD_ENABLE 1 132 133 /* MAX Frame Size */ 134 #define XMAC_MAC_DEFAULT_MAX_FRAME_SIZE 0x00003fe8 135 136 /* 137 * TX Frame Length 138 */ 139 #define XMAC_TXMAXSZ_MAX_FRAME_SIZE \ 140 XMAC_MAC_DEFAULT_MAX_FRAME_SIZE 141 #define XMAC_TXMAXSZ_MAX_FRAME_SIZE_MASK 0x0003fff 142 143 /* 144 * RX Frame Length 145 */ 146 #define XMAC_RXMAXSZ_MAX_FRAME_SIZE \ 147 XMAC_MAC_DEFAULT_MAX_FRAME_SIZE 148 #define XMAC_RXMAXSZ_MAX_FRAME_SIZE_MASK 0x0003fff 149 150 151 152 #define XMAC_IS_V2(m) \ 153 ( (m)->flag & PHY_MAC_CTRL_FLAG_XMAC_V2) 154 155 /* 156 * Register Access Macros 157 */ 158 159 #define XMAC_REG_MAC_CTRLr(p,m) \ 160 (0x01100000 + (((p) & 0x7) << 12)) 161 162 #define XMAC_REG_TX_CTRLr(p,m) \ 163 (0x01100004 + (((p) & 0x7) << 12)) 164 165 #define XMAC_REG_RX_CTRLr(p,m) \ 166 (0x01100006 + (((p) & 0x7) << 12)) 167 168 #define XMAC_REG_RX_MAXSZr(p,m) \ 169 (0x01100008 + (((p) & 0x7) << 12)) 170 171 #define XMAC_REG_RX_LSS_CTRLr(p,m) \ 172 (0x0110000a + (((p) & 0x7) << 12)) 173 174 #define XMAC_REG_PAUSE_CTRLr(p,m) \ 175 (0x0110000d + (((p) & 0x7) << 12)) 176 177 #define XMAC_REG_MAC_MACSEC_CTRLr(p,m) \ 178 ((XMAC_IS_V2(m) ? 0x01100025 : 0x01100024) + (((p) & 0x7) << 12)) 179 180 181 #define BMACSEC_XMAC_REG_SIZE 2 182 #ifdef COMPILER_HAS_LONGLONG_SHIFT 183 #define XMAC_MMI_READ_REG(_mmc, _dev_port, _io_addr, _data) \ 184 ( \ 185 rv = (_mmc)->devio_f((_mmc)->dev_addr, (_dev_port), BLMI_IO_REG_RD, \ 186 (_io_addr), BMACSEC_XMAC_REG_SIZE, 1, \ 187 (buint32_t *)tmp_val), \ 188 COMPILER_64_SET(*(_data), tmp_val[1], tmp_val[0]), \ 189 rv \ 190 ) 191 #else 192 #define XMAC_MMI_READ_REG(_mmc, _dev_port, _io_addr, _data) \ 193 ( \ 194 rv = (_mmc)->devio_f((_mmc)->dev_addr, (_dev_port), BLMI_IO_REG_RD, \ 195 (_io_addr), BMACSEC_XMAC_REG_SIZE, 1, \ 196 (buint32_t *)tmp_val), \ 197 COMPILER_64_LO(*(_data)) = tmp_val[0], \ 198 COMPILER_64_HI(*(_data)) = tmp_val[1], \ 199 rv \ 200 ) 201 #endif 202 203 #define XMAC_MMI_WRITE_REG(_mmc, _dev_port, _io_addr, _data) \ 204 ( \ 205 tmp_val[0] = COMPILER_64_LO((_data)), \ 206 tmp_val[1] = COMPILER_64_HI((_data)), \ 207 rv = (_mmc)->devio_f((_mmc)->dev_addr, (_dev_port), BLMI_IO_REG_WR, \ 208 (_io_addr), BMACSEC_XMAC_REG_SIZE, 1, \ 209 (buint32_t *)tmp_val), \ 210 rv \ 211 ) 212 213 214 /* MAC Control Register */ 215 #define XMAC_READ_MAC_CTRL_REG(_mmc, _dev_port, _data) \ 216 XMAC_MMI_READ_REG((_mmc), (_dev_port), \ 217 XMAC_REG_MAC_CTRLr(_dev_port,_mmc), \ 218 (_data)) 219 220 #define XMAC_WRITE_MAC_CTRL_REG(_mmc, _dev_port, _data) \ 221 XMAC_MMI_WRITE_REG((_mmc), (_dev_port), \ 222 XMAC_REG_MAC_CTRLr(_dev_port,_mmc), \ 223 (_data)) 224 225 /* TX Control Register */ 226 #define XMAC_READ_TXCTRL_REG(_mmc, _dev_port, _data) \ 227 XMAC_MMI_READ_REG((_mmc), (_dev_port), \ 228 XMAC_REG_TX_CTRLr(_dev_port,_mmc), \ 229 (_data)) 230 231 #define XMAC_WRITE_TXCTRL_REG(_mmc, _dev_port, _data) \ 232 XMAC_MMI_WRITE_REG((_mmc), (_dev_port), \ 233 XMAC_REG_TX_CTRLr(_dev_port,_mmc), \ 234 (_data)) 235 236 /* MAC MACSEC Control register */ 237 #define XMAC_READ_MAC_MACSEC_CTRL_REG(_mmc, _dev_port, _data) \ 238 XMAC_MMI_READ_REG((_mmc), (_dev_port), \ 239 XMAC_REG_MAC_MACSEC_CTRLr(_dev_port,_mmc), \ 240 (_data)) 241 242 #define XMAC_WRITE_MAC_MACSEC_CTRL_REG(_mmc, _dev_port, _data) \ 243 XMAC_MMI_WRITE_REG((_mmc), (_dev_port), \ 244 XMAC_REG_MAC_MACSEC_CTRLr(_dev_port,_mmc), \ 245 (_data)) 246 247 /* RX Control register */ 248 #define XMAC_READ_RXCTRL_REG(_mmc, _dev_port, _data) \ 249 XMAC_MMI_READ_REG((_mmc), (_dev_port), \ 250 XMAC_REG_RX_CTRLr(_dev_port,_mmc), \ 251 (_data)) 252 253 #define XMAC_WRITE_RXCTRL_REG(_mmc, _dev_port, _data) \ 254 XMAC_MMI_WRITE_REG((_mmc), (_dev_port), \ 255 XMAC_REG_RX_CTRLr(_dev_port,_mmc), \ 256 (_data)) 257 258 /* RX Max Size register */ 259 #define XMAC_READ_RXMAXSZ_REG(_mmc, _dev_port, _data) \ 260 XMAC_MMI_READ_REG((_mmc), (_dev_port), \ 261 XMAC_REG_RX_MAXSZr(_dev_port,_mmc), \ 262 (_data)) 263 #define XMAC_WRITE_RXMAXSZ_REG(_mmc, _dev_port, _data) \ 264 XMAC_MMI_WRITE_REG((_mmc), (_dev_port), \ 265 XMAC_REG_RX_MAXSZr(_dev_port,_mmc), \ 266 (_data)) 267 268 /* PAUSE Control register */ 269 #define XMAC_READ_PAUSE_CTRL_REG(_mmc, _dev_port, _data) \ 270 XMAC_MMI_READ_REG((_mmc), (_dev_port), \ 271 XMAC_REG_PAUSE_CTRLr(_dev_port,_mmc), \ 272 (_data)) 273 #define XMAC_WRITE_PAUSE_CTRL_REG(_mmc, _dev_port, _data) \ 274 XMAC_MMI_WRITE_REG((_mmc), (_dev_port), \ 275 XMAC_REG_PAUSE_CTRLr(_dev_port,_mmc), \ 276 (_data)) 277 278 279 /* LSS Control register */ 280 #define XMAC_READ_RX_LSS_CTRL_REG(_mmc, _dev_port, _data) \ 281 XMAC_MMI_READ_REG((_mmc), (_dev_port), \ 282 XMAC_REG_RX_LSS_CTRLr(_dev_port,_mmc), \ 283 (_data)) 284 #define XMAC_WRITE_RX_LSS_CTRL_REG(_mmc, _dev_port, _data) \ 285 XMAC_MMI_WRITE_REG((_mmc), (_dev_port), \ 286 XMAC_REG_RX_LSS_CTRLr(_dev_port,_mmc), \ 287 (_data)) 288 289 #endif /* _XMAC_MAC_H_ */ 290