phy_unimac.h (13814B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 8 #ifndef PHY_UNIMAC_H_ 9 #define PHY_UNIMAC_H_ 10 11 #include "phy_mac_ctrl.h" 12 #define BIT_U(_n) (1U << (_n)) 13 extern int phy_unimac_mac_init(phy_mac_ctrl_t *mmc, int dev_port); 14 15 extern int phy_unimac_mac_auto_cfg(phy_mac_ctrl_t *mmc, 16 int dev_port, int fval); 17 18 extern int phy_unimac_mac_reset(phy_mac_ctrl_t *mmc, 19 int dev_port, int fval); 20 21 extern int phy_unimac_mac_enable_set(phy_mac_ctrl_t *mmc, 22 int dev_port, int en); 23 24 extern int phy_unimac_mac_enable_get(phy_mac_ctrl_t *mmc, 25 int dev_port, int *en) ; 26 27 extern int phy_unimac_mac_speed_set(phy_mac_ctrl_t *mmc, 28 int dev_port, int speed); 29 30 extern int phy_unimac_mac_speed_get(phy_mac_ctrl_t *mmc, 31 int dev_port, int *speed); 32 33 extern int phy_unimac_mac_duplex_set(phy_mac_ctrl_t *mmc, 34 int dev_port, int duplex); 35 36 extern int phy_unimac_mac_duplex_get(phy_mac_ctrl_t *mmc, 37 int dev_port, int *fd); 38 39 extern int phy_unimac_mac_pause_set(phy_mac_ctrl_t *mmc, 40 int dev_port, int pause); 41 42 extern int phy_unimac_mac_update_ipg(phy_mac_ctrl_t *mmc, 43 int dev_port, int ipg); 44 45 extern int phy_unimac_mac_max_frame_set(phy_mac_ctrl_t *mmc, 46 int dev_port, uint32 max_frame); 47 48 extern int phy_unimac_mac_max_frame_get(phy_mac_ctrl_t *mmc, 49 int dev_port, uint32 *flen); 50 51 extern int phy_unimac_mac_pause_frame_fwd_set(phy_mac_ctrl_t *mmc, 52 int dev_port, int pause_fwd); 53 extern int phy_unimac_mac_rx_enable_set(phy_mac_ctrl_t *mmc, int dev_port, int enable); 54 extern int phy_unimac_mac_tx_enable_set(phy_mac_ctrl_t *mmc, int dev_port, int enable); 55 extern int phy_unimac_mac_tx_datapath_flush(phy_mac_ctrl_t *mmc, int dev_port, int enable); 56 57 58 /* 59 * Command Register 60 */ 61 62 #define UNIMAC_REG_CMD_CFG_TXEN_SHIFT 0 63 #define UNIMAC_REG_CMD_CFG_RXEN_SHIFT 1 64 #define UNIMAC_REG_CMD_CFG_SPEED_SHIFT 2 65 #define UNIMAC_REG_CMD_CFG_PROMIS_EN_SHIFT 4 66 #define UNIMAC_REG_CMD_CFG_CRC_FWD_SHIFT 6 67 #define UNIMAC_REG_CMD_CFG_PAUSE_FWD_SHIFT 7 68 #define UNIMAC_REG_CMD_CFG_RX_PAUSE_IGNORE_SHIFT 8 69 #define UNIMAC_REG_CMD_CFG_DUPLEX_SHIFT 10 70 #define UNIMAC_REG_CMD_CFG_SW_RESET_SHIFT 13 71 #define UNIMAC_REG_CMD_CFG_SW_OVERRIDE_TX_SHIFT 17 72 #define UNIMAC_REG_CMD_CFG_SW_OVERRIDE_RX_SHIFT 18 73 #define UNIMAC_REG_CMD_CFG_ENA_EXA_CONFIG_SHIFT 22 74 #define UNIMAC_REG_CMD_CTL_FRM_ENA_SHIFT 23 75 #define UNIMAC_REG_CMD_CTL_FRM_NO_LGTH_CHECK 24 76 #define UNIMAC_REG_CMD_CFG_TX_PAUSE_IGNORE_SHIFT 28 77 #define UNIMAC_REG_CMD_CFG_RUNT_FILTER_SHIFT 31 78 79 #define UNIMAC_REG_CMD_CFG_SPEED_SHIFT_L UNIMAC_REG_CMD_CFG_SPEED_SHIFT 80 #define UNIMAC_REG_CMD_CFG_SPEED_SHIFT_H (UNIMAC_REG_CMD_CFG_SPEED_SHIFT + 1) 81 82 #define UNIMAC_REG_CMD_CFG_TXEN_MASK BIT_U(UNIMAC_REG_CMD_CFG_TXEN_SHIFT) 83 #define UNIMAC_REG_CMD_CFG_RXEN_MASK BIT_U(UNIMAC_REG_CMD_CFG_RXEN_SHIFT) 84 #define UNIMAC_REG_CMD_CFG_SPEED_MASK (BIT_U(UNIMAC_REG_CMD_CFG_SPEED_SHIFT_L) \ 85 |BIT_U(UNIMAC_REG_CMD_CFG_SPEED_SHIFT_H)) 86 #define UNIMAC_REG_CMD_CFG_PROMIS_EN_MASK BIT_U(UNIMAC_REG_CMD_CFG_PROMIS_EN_SHIFT) 87 #define UNIMAC_REG_CMD_CFG_CRC_FWD_MASK BIT_U(UNIMAC_REG_CMD_CFG_CRC_FWD_SHIFT) 88 #define UNIMAC_REG_CMD_CFG_PAUSE_FWD_MASK BIT_U(UNIMAC_REG_CMD_CFG_PAUSE_FWD_SHIFT) 89 #define UNIMAC_REG_CMD_CFG_RX_PAUSE_IGNORE_MASK BIT_U(UNIMAC_REG_CMD_CFG_RX_PAUSE_IGNORE_SHIFT) 90 #define UNIMAC_REG_CMD_CFG_DUPLEX_MASK BIT_U(UNIMAC_REG_CMD_CFG_DUPLEX_SHIFT) 91 #define UNIMAC_REG_CMD_CFG_SW_RESET_MASK BIT_U(UNIMAC_REG_CMD_CFG_SW_RESET_SHIFT) 92 #define UNIMAC_REG_CMD_CFG_SW_OVERRIDE_TX_MASK BIT_U(UNIMAC_REG_CMD_CFG_SW_OVERRIDE_TX_SHIFT) 93 #define UNIMAC_REG_CMD_CFG_SW_OVERRIDE_RX_MASK BIT_U(UNIMAC_REG_CMD_CFG_SW_OVERRIDE_RX_SHIFT) 94 #define UNIMAC_REG_CMD_CFG_ENA_EXA_CONFIG_MASK BIT_U(UNIMAC_REG_CMD_CFG_ENA_EXA_CONFIG_SHIFT) 95 #define UNIMAC_REG_CMD_CFG_CTL_FRM_ENA_MASK BIT_U(UNIMAC_REG_CMD_CTL_FRM_ENA_SHIFT) 96 #define UNIMAC_REG_CMD_CFG_CTL_FRM_NO_LGTH_CHECK_MASK BIT_U(UNIMAC_REG_CMD_CTL_FRM_NO_LGTH_CHECK) 97 #define UNIMAC_REG_CMD_CFG_TX_PAUSE_IGNORE_MASK BIT_U(UNIMAC_REG_CMD_CFG_TX_PAUSE_IGNORE_SHIFT) 98 #define UNIMAC_REG_CMD_CFG_RUNT_FILTER_DIS_MASK BIT_U(UNIMAC_REG_CMD_CFG_RUNT_FILTER_SHIFT) 99 #define UNIMAC_REG_GPORT_RSV_FRM_LEN_CHK_MASK (BIT_U(5) | BIT_U(6)) 100 #define UNIMAC_REG_EEE_CTRL_RX_FIFO_CHECK (1<<4) 101 #define UNIMAC_REG_CMD_CFG_OVERFLOW_EN (1<<12) 102 103 /* Unimac MAC_MODE register */ 104 #define UNIMAC_REG_MAC_MODE_DUPLEX_SHIFT 2 105 #define UNIMAC_REG_MAC_MODE_SPEED_SHIFT 0 106 #define UNIMAC_REG_MAC_MODE_SPEED_SHIFT_L UNIMAC_REG_MAC_MODE_SPEED_SHIFT 107 #define UNIMAC_REG_MAC_MODE_SPEED_SHIFT_H (UNIMAC_REG_MAC_MODE_SPEED_SHIFT + 1) 108 109 #define UNIMAC_REG_MAC_MODE_DUPLEX_MASK BIT_U(UNIMAC_REG_MAC_MODE_DUPLEX_SHIFT) 110 #define UNIMAC_REG_MAC_MODE_SPEED_MASK (BIT_U(UNIMAC_REG_MAC_MODE_SPEED_SHIFT_L) \ 111 |BIT_U(UNIMAC_REG_MAC_MODE_SPEED_SHIFT_H)) 112 113 /* UNIMAC TX Flush Control */ 114 #define UNIMAC_REG_TX_FLUSH_CTRL_MASK 1 115 116 #define BMACSEC_PHY54580_LINE_MAC_PORT(p) (p) 117 #define BMACSEC_PHY54580_SWITCH_MAC_PORT(p) ((p) + 8) 118 /* 119 * Half-Duplex Back-Pressure Control register 120 */ 121 #define UNIMAC_REG_BKP_HD_FC_ENA_SHIFT 0 122 #define UNIMAC_REG_BKP_HD_FC_BKOFF_SHIFT 1 123 #define UNIMAC_REG_BKP_HD_FC_ENA_MASK BIT_U(UNIMAC_REG_BKP_HD_FC_ENA_SHIFT) 124 #define UNIMAC_REG_BKP_HD_FC_BKOFF_MASK BIT_U(UNIMAC_REG_BKP_HD_FC_BKOFF_SHIFT) 125 126 127 /* 128 * CRC Forward 129 */ 130 #define UNIMAC_REG_CMD_CFG_CRC_FWD_DISABLE 0 131 #define UNIMAC_REG_CMD_CFG_CRC_FWD_ENABLE 1 132 133 /* 134 * Frame Length 135 */ 136 #define UNIMAC_REG_DUPLEX_GATEWAY_MAX_FRAME_SIZE 0x0003fe4 137 #define UNIMAC_REG_DEFAULT_MAX_FRAME_SIZE 0x0003fff 138 #define UNIMAC_REG_FRM_LENr_FMR_LEN_MASK 0x0003fff 139 140 /* DEFAULT IPG */ 141 #define UNIMAC_REG_DEFAULT_IPG 12 142 143 144 /* MACSEC Control register */ 145 #define UNIMAC_REG_TX_CRC_ENABLE_MASK (1 << 1) 146 #define UNIMAC_REG_TX_CRC_ENABLE_SHIFT 1 147 148 #define UNIMAC_REG_TX_CRC_ENABLE 1 149 150 151 #define UNIMAC_COMMAND_CONFIGr(_mmc, p) \ 152 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 153 (PHY_UNIMAC_V2_GET_SIDE(p) ? 0x00007c08 : 0x00007808 ) : \ 154 (0x00100202 + (((p) & 0xf) << 12)) 155 156 #define UNIMAC_MAC_MODEr(_mmc, p) \ 157 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 158 (PHY_UNIMAC_V2_GET_SIDE(p) ? 0x00007c44 : 0x00007844 ) : \ 159 (0x00100211 + (((p) & 0xf) << 12)) 160 161 162 #define UNIMAC_FRM_LENGTHr(_mmc, p) \ 163 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 164 (PHY_UNIMAC_V2_GET_SIDE(p) ? 0x00007c14 : 0x00007814 ) : \ 165 (0x00100205 + (((p) & 0xf) << 12)) 166 167 #define UNIMAC_TX_IPG_LENGTHr(_mmc, p) \ 168 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 169 (PHY_UNIMAC_V2_GET_SIDE(p) ? 0x00007c5c : 0x0000785c ) : \ 170 (0x00100217 + (((p) & 0xf) << 12)) 171 172 #define UNIMAC_MACSEC_CNTRLr(_mmc, p) \ 173 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 174 (PHY_UNIMAC_V2_GET_SIDE(p) ? 0x00007f14 : 0x00007b14 ) : \ 175 (0x001002c5 + (((p) & 0xf) << 12)) 176 #define UNIMAC_UMAC_EEE_CTRLr(_mmc, p) \ 177 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 178 (PHY_UNIMAC_V2_GET_SIDE(p) ? 0x00007c64 : 0x00007864 ) : \ 179 (0x00100219 + (((p) & 0xf) << 12)) 180 #define UNIMAC_MACSEC_IPG_HD_BKP_CNTLr(_mmc,_p) \ 181 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 182 (PHY_UNIMAC_V2_GET_SIDE(_p) ? 0x00007c04 : 0x00007804 ) : \ 183 (0x00100201 + (((_p) & 0xf) << 12)) 184 #define UNIMAC_MACSEC_GPORT_RSV_MASKr(_mmc,_p) \ 185 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 186 (PHY_UNIMAC_V2_GET_SIDE(_p) ? 0x0000000c : 0x00000008 ) : \ 187 (0x02100036 + (((_p) & 0xf) << 12)) 188 189 #define UNIMAC_TX_FLUSH_CTRLr(_mmc,_p) \ 190 ((_mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? \ 191 (PHY_UNIMAC_V2_GET_SIDE(_p) ? 0x00007f34 : 0x00007b34 ) : \ 192 (0x001002CD + (((_p) & 0xf) << 12)) 193 194 195 #define BMACSEC_NUM_WORDS 1 196 197 #define BMACSEC_MAC_READ_REG(mmc, _dev_port, _io_addr, _data) \ 198 (mmc)->devio_f(((mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? (mmc)->unit : (mmc)->dev_addr, PHY_UNIMAC_V2_GET_PORT(_dev_port), BLMI_IO_REG_RD, \ 199 (_io_addr), BMACSEC_NUM_WORDS, 1, (_data)) 200 201 #define BMACSEC_MAC_WRITE_REG(mmc, _dev_port, _io_addr, _data) \ 202 (mmc)->devio_f(((mmc)->flag & PHY_MAC_CTRL_FLAG_UNIMAC_V2) ? (mmc)->unit : (mmc)->dev_addr, PHY_UNIMAC_V2_GET_PORT(_dev_port), BLMI_IO_REG_WR, \ 203 (_io_addr), BMACSEC_NUM_WORDS, 1, &(_data)) 204 205 206 /* Command Config Register */ 207 #define UNIMAC_READ_CMD_CFG_REG(mmc, _dev_port, _data) \ 208 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 209 UNIMAC_COMMAND_CONFIGr((mmc), _dev_port), \ 210 (_data)) 211 212 #define UNIMAC_WRITE_CMD_CFG_REG(mmc, _dev_port, _data) \ 213 BMACSEC_MAC_WRITE_REG((mmc), (_dev_port), \ 214 UNIMAC_COMMAND_CONFIGr((mmc), _dev_port), \ 215 (_data)) 216 /* UNIMAC Status MAC_MODE Register */ 217 #define UNIMAC_READ_MAC_MODE_REG(mmc, _dev_port, _data) \ 218 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 219 UNIMAC_MAC_MODEr((mmc), _dev_port), \ 220 (_data)) 221 222 /* Frame Length Register */ 223 #define UNIMAC_READ_FRM_LEN_REG(mmc, _dev_port, _data) \ 224 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 225 UNIMAC_FRM_LENGTHr((mmc), _dev_port), \ 226 (_data)) 227 228 #define UNIMAC_WRITE_FRM_LEN_REG(mmc, _dev_port, _data) \ 229 BMACSEC_MAC_WRITE_REG((mmc), (_dev_port), \ 230 UNIMAC_FRM_LENGTHr((mmc), _dev_port), \ 231 (_data)) 232 /* Enable frame length check error by setting mask bit for RSV[21] */ 233 #define UNIMAC_READ_GPORT_RSV_MASK_REG(mmc, _dev_port, _data) \ 234 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 235 UNIMAC_MACSEC_GPORT_RSV_MASKr((mmc), _dev_port), \ 236 (_data)) 237 #define UNIMAC_WRITE_GPORT_RSV_MASK_REG(mmc, _dev_port, _data) \ 238 BMACSEC_MAC_WRITE_REG((mmc), (_dev_port), \ 239 UNIMAC_MACSEC_GPORT_RSV_MASKr((mmc), _dev_port), \ 240 (_data)) 241 242 /* TX IPG Register */ 243 #define UNIMAC_READ_TX_IPG_REG(mmc, _dev_port, _data) \ 244 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 245 UNIMAC_TX_IPG_LENGTHr((mmc), _dev_port), \ 246 (_data)) 247 248 #define UNIMAC_WRITE_TX_IPG_REG(mmc, _dev_port, _data) \ 249 BMACSEC_MAC_WRITE_REG((mmc), (_dev_port), \ 250 UNIMAC_TX_IPG_LENGTHr((mmc), _dev_port), \ 251 (_data)) 252 253 /* MACSEC Control register */ 254 #define UNIMAC_READ_MACSEC_CNTL_REG(mmc, _dev_port, _data) \ 255 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 256 UNIMAC_MACSEC_CNTRLr((mmc), _dev_port), \ 257 (_data)) 258 259 #define UNIMAC_WRITE_MACSEC_CNTL_REG(mmc, _dev_port, _data) \ 260 BMACSEC_MAC_WRITE_REG((mmc), (_dev_port), \ 261 UNIMAC_MACSEC_CNTRLr((mmc), _dev_port), \ 262 (_data)) 263 /* Half-Duplex Back-Pressure Control register */ 264 #define UNIMAC_READ_IPG_HD_BKP_CNTL_REG(mmc, _dev_port, _data) \ 265 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 266 UNIMAC_MACSEC_IPG_HD_BKP_CNTLr((mmc), _dev_port), \ 267 (_data)) 268 269 #define UNIMAC_WRITE_IPG_HD_BKP_CNTL_REG(mmc, _dev_port, _data) \ 270 BMACSEC_MAC_WRITE_REG((mmc), (_dev_port), \ 271 UNIMAC_MACSEC_IPG_HD_BKP_CNTLr((mmc), _dev_port), \ 272 (_data)) 273 /* UMAC_EEE_CTRL read and write function */ 274 #define UNIMAC_READ_UMAC_EEE_CTRL_REG(mmc, _dev_port, _data) \ 275 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 276 UNIMAC_UMAC_EEE_CTRLr((mmc), _dev_port), \ 277 (_data)) 278 #define UNIMAC_WRITE_UMAC_EEE_CTRL_REG(mmc, _dev_port, _data) \ 279 BMACSEC_MAC_WRITE_REG((mmc), (_dev_port), \ 280 UNIMAC_UMAC_EEE_CTRLr((mmc), _dev_port), \ 281 (_data)) 282 /* UNIMAC TX FLUSH_CONTROL read and write function */ 283 #define UNIMAC_READ_TX_FLUSH_CTRL_REG(mmc, _dev_port, _data) \ 284 BMACSEC_MAC_READ_REG((mmc), (_dev_port), \ 285 UNIMAC_TX_FLUSH_CTRLr((mmc), _dev_port), \ 286 (_data)) 287 #define UNIMAC_WRITE_TX_FLUSH_CTRL_REG(mmc, _dev_port, _data) \ 288 BMACSEC_MAC_WRITE_REG((mmc), (_dev_port), \ 289 UNIMAC_TX_FLUSH_CTRLr((mmc), _dev_port), \ 290 (_data)) 291 292 #endif /* PHY_UNIMAC_H_ */ 293