phy_portmod_dispatch.c (22302B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: null.c 8 * Purpose: Defines NULL PHY driver routines 9 */ 10 11 #include <sal/types.h> 12 #include <sal/core/thread.h> 13 14 #include <soc/drv.h> 15 #include <soc/debug.h> 16 #include <soc/error.h> 17 #include <soc/phyreg.h> 18 19 #include <soc/phy.h> 20 #include <soc/phy/phyctrl.h> 21 #include <soc/phy/drv.h> 22 23 #ifdef PORTMOD_SUPPORT 24 #include "phynull.h" 25 #include "phy_portmod_dispatch.h" 26 #include "phyfege.h" 27 #include <soc/portmod/portmod.h> 28 #include <soc/portmod/portmod_common.h> 29 30 /* typedef unsigned int portmod_port_mode_t; */ 31 /* typedef unsigned int portmod_pa_encap_t; */ 32 /* typedef int portmod_port_t */ 33 34 35 /* 36 * Functions: 37 * phy_portmod_dispatch_XXX 38 * 39 * Purpose: 40 * Some dummy routines for null and no 41 * connection PHY drivers. 42 */ 43 44 int 45 _phy_portmod_dispatch_port_ability_init(int unit, soc_port_t port, 46 soc_port_ability_t *ability) 47 { 48 49 int max_speed = SOC_INFO(unit).port_speed_max[port]; 50 51 if ( max_speed == 0) { 52 if (IS_GE_PORT(unit,port)) { 53 max_speed = 1000; 54 } else if (IS_FE_PORT(unit,port)) { 55 max_speed = 100; 56 } 57 } 58 59 switch (max_speed) { 60 case 127000: 61 ability->speed_full_duplex |= SOC_PA_SPEED_127GB; 62 /* fall through */ 63 case 120000: 64 ability->speed_full_duplex |= SOC_PA_SPEED_120GB; 65 /* fall through */ 66 case 106000: 67 ability->speed_full_duplex |= SOC_PA_SPEED_106GB; 68 /* fall through */ 69 case 100000: 70 ability->speed_full_duplex |= SOC_PA_SPEED_100GB; 71 /* fall through */ 72 case 53000: 73 ability->speed_full_duplex |= SOC_PA_SPEED_53GB; 74 /* fall through */ 75 case 50000: 76 ability->speed_full_duplex |= SOC_PA_SPEED_50GB; 77 /* fall through */ 78 case 42000: 79 ability->speed_full_duplex |= SOC_PA_SPEED_42GB; 80 /* fall through */ 81 case 40000: 82 ability->speed_full_duplex |= SOC_PA_SPEED_40GB; 83 /* fall through */ 84 case 32000: 85 ability->speed_full_duplex |= SOC_PA_SPEED_32GB; 86 /* fall through */ 87 case 30000: 88 ability->speed_full_duplex |= SOC_PA_SPEED_30GB; 89 /* fall through */ 90 case 27000: 91 ability->speed_full_duplex |= SOC_PA_SPEED_27GB; 92 /* fall through */ 93 case 25000: 94 ability->speed_full_duplex |= SOC_PA_SPEED_25GB; 95 /* fall through */ 96 case 24000: 97 ability->speed_full_duplex |= SOC_PA_SPEED_24GB; 98 /* fall through */ 99 case 21000: 100 ability->speed_full_duplex |= SOC_PA_SPEED_21GB; 101 /* fall through */ 102 case 20000: 103 ability->speed_full_duplex |= SOC_PA_SPEED_20GB; 104 /* fall through */ 105 case 16000: 106 ability->speed_full_duplex |= SOC_PA_SPEED_16GB; 107 /* fall through */ 108 case 15000: 109 ability->speed_full_duplex |= SOC_PA_SPEED_15GB; 110 /* fall through */ 111 case 13000: 112 ability->speed_full_duplex |= SOC_PA_SPEED_13GB; 113 /* fall through */ 114 case 12500: 115 ability->speed_full_duplex |= SOC_PA_SPEED_12P5GB; 116 /* fall through */ 117 case 12000: 118 ability->speed_full_duplex |= SOC_PA_SPEED_12GB; 119 /* fall through */ 120 case 11000: 121 ability->speed_full_duplex |= SOC_PA_SPEED_11GB; 122 /* fall through */ 123 case 10000: 124 ability->speed_full_duplex |= SOC_PA_SPEED_10GB; 125 /* fall through */ 126 case 6000: 127 ability->speed_full_duplex |= SOC_PA_SPEED_6000MB; 128 /* fall through */ 129 case 5000: 130 ability->speed_full_duplex |= SOC_PA_SPEED_5000MB; 131 /* fall through */ 132 case 3000: 133 ability->speed_full_duplex |= SOC_PA_SPEED_3000MB; 134 /* fall through */ 135 case 2500: 136 ability->speed_full_duplex |= SOC_PA_SPEED_2500MB; 137 /* fall through */ 138 case 1000: 139 ability->speed_full_duplex |= SOC_PA_SPEED_1000MB; 140 /* fall through */ 141 case 100: 142 ability->speed_full_duplex |= SOC_PA_SPEED_100MB; 143 /* fall through */ 144 case 10: 145 ability->speed_full_duplex |= SOC_PA_SPEED_10MB; 146 /* fall through */ 147 default: 148 break; 149 } 150 151 ability->speed_half_duplex = 152 SOC_PA_SPEED_10MB | SOC_PA_SPEED_100MB; 153 154 if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port) || 155 IS_CE_PORT(unit, port)) { 156 ability->interface = SOC_PA_INTF_XGMII; 157 } else if (IS_GE_PORT(unit, port)) { 158 ability->interface = SOC_PA_INTF_MII | SOC_PA_INTF_GMII; 159 } else { 160 ability->interface = SOC_PA_INTF_MII; 161 } 162 163 return SOC_E_NONE; 164 } 165 166 int 167 phy_portmod_dispatch_init(int unit, soc_port_t port) 168 { 169 return SOC_E_NONE; 170 } 171 172 int 173 phy_portmod_dispatch_reset(int unit, soc_port_t port, void *user_arg) 174 { 175 COMPILER_REFERENCE(unit); 176 COMPILER_REFERENCE(port); 177 COMPILER_REFERENCE(user_arg); 178 179 return SOC_E_NONE; 180 } 181 182 int 183 phy_portmod_dispatch_set(int unit, soc_port_t port, int parm) 184 { 185 COMPILER_REFERENCE(unit); 186 COMPILER_REFERENCE(port); 187 COMPILER_REFERENCE(parm); 188 189 return SOC_E_NONE; 190 } 191 192 int 193 phy_portmod_dispatch_an_get(int unit, soc_port_t port, int *an, int *an_done) 194 { 195 int rv = SOC_E_NONE; 196 phymod_autoneg_control_t an_ctrl; 197 soc_info_t *si; 198 199 si = &SOC_INFO(unit); 200 phymod_autoneg_control_t_init(&an_ctrl); 201 an_ctrl.enable = 0; 202 an_ctrl.num_lane_adv = si->port_num_lanes[port]; 203 an_ctrl.an_mode = phymod_AN_MODE_NONE; 204 an_ctrl.flags = 0 ; 205 206 /* only SGMIII AN is supported when there is an external PHY */ 207 if (IS_GE_PORT(unit,port)) 208 an_ctrl.an_mode = phymod_AN_MODE_CL37; 209 210 rv = portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_AN, &an_ctrl); 211 if (rv != SOC_E_NONE) { 212 LOG_VERBOSE(BSL_LS_BCM_PORT, 213 (BSL_META_U(unit, "phy_portmod_dispatch_an_get: portmod_ext_to_int_cmd_get failed"))); 214 return rv; 215 } 216 217 *an = an_ctrl.enable; 218 /* Need to fix this as the portmod curently does 219 not return an_done state */ 220 *an_done = 0; 221 if(an_ctrl.enable) 222 *an_done = 1; 223 224 return rv; 225 } 226 227 int 228 phy_portmod_dispatch_an_set(int unit, soc_port_t port, int an_enable) { 229 int rv = SOC_E_NONE; 230 phymod_autoneg_control_t an; 231 soc_info_t *si; 232 int fiber_pref; 233 234 si = &SOC_INFO(unit); 235 phymod_autoneg_control_t_init(&an); 236 an.enable = an_enable; 237 an.num_lane_adv = si->port_num_lanes[port]; 238 an.an_mode = phymod_AN_MODE_NONE; 239 an.flags = 0 ; 240 fiber_pref=0; 241 242 if (IS_GE_PORT(unit,port)) { 243 fiber_pref = soc_property_port_get(unit, port,spn_SERDES_FIBER_PREF, fiber_pref); 244 if(fiber_pref) { 245 an.an_mode = phymod_AN_MODE_CL37; 246 } else { 247 an.an_mode = phymod_AN_MODE_SGMII; 248 } 249 PHYMOD_AN_F_IGNORE_MEDIUM_CHECK_SET(&an); 250 an.num_lane_adv = 1; 251 } 252 253 an.enable = an_enable; 254 255 rv = portmod_ext_to_int_cmd_set(unit, port, portmodExtToInt_CtrlCode_AN, &an); 256 if (rv != SOC_E_NONE) { 257 LOG_VERBOSE(BSL_LS_BCM_PORT, 258 (BSL_META_U(unit, "phy_portmod_dispatch_an_set: portmod_ext_to_int_cmd_set failed"))); 259 return rv; 260 } 261 return rv; 262 } 263 264 int 265 phy_portmod_dispatch_advert_ability_set(int unit, soc_port_t port, soc_port_ability_t *ability) 266 { 267 int rv = SOC_E_NONE; 268 269 rv = portmod_ext_to_int_cmd_set(unit, port, portmodExtToInt_CtrlCode_AbilityAdvert, ability); 270 if (rv != SOC_E_NONE) { 271 LOG_VERBOSE(BSL_LS_BCM_PORT, 272 (BSL_META_U(unit, "phy_portmod_dispatch_adv_ability_set: portmod_ext_to_int_cmd_set failed"))); 273 return rv; 274 } 275 return rv; 276 } 277 278 int 279 phy_portmod_dispatch_one_get(int unit, soc_port_t port, int *parm) 280 { 281 COMPILER_REFERENCE(unit); 282 COMPILER_REFERENCE(port); 283 284 *parm = 1; 285 286 return SOC_E_NONE; 287 } 288 289 int 290 phy_portmod_dispatch_zero_get(int unit, soc_port_t port, int *parm) 291 { 292 COMPILER_REFERENCE(unit); 293 COMPILER_REFERENCE(port); 294 295 *parm = 0; 296 297 return SOC_E_NONE; 298 } 299 300 301 int 302 phy_portmod_dispatch_link_get(int unit, soc_port_t port, int *up) 303 { 304 int rv = SOC_E_NONE; 305 rv = portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_Link, (void *)up); 306 return rv; 307 308 } 309 310 int 311 phy_portmod_dispatch_enable_set(int unit, soc_port_t port, int enable) 312 { 313 int rv = SOC_E_NONE; 314 315 rv = portmod_ext_to_int_cmd_set(unit, port, portmodExtToInt_CtrlCode_Enable, (void *)(&enable)); 316 return rv; 317 } 318 319 int 320 phy_portmod_dispatch_enable_get(int unit, soc_port_t port, int *enable) 321 { 322 int rv = SOC_E_NONE; 323 324 rv = portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_Enable, enable); 325 return rv; 326 } 327 328 329 330 int 331 phy_portmod_dispatch_mode_set(int unit, soc_port_t port, soc_port_mode_t mode) 332 { 333 COMPILER_REFERENCE(unit); 334 COMPILER_REFERENCE(port); 335 COMPILER_REFERENCE(mode); 336 337 return SOC_E_NONE; 338 } 339 340 int 341 phy_portmod_dispatch_mode_get(int unit, soc_port_t port, soc_port_mode_t *mode) 342 { 343 COMPILER_REFERENCE(unit); 344 COMPILER_REFERENCE(port); 345 346 if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 347 *mode = SOC_PM_10GB_FD | SOC_PM_XGMII; 348 } else if (IS_GE_PORT(unit, port)) { 349 *mode = SOC_PM_1000MB_FD | SOC_PM_GMII | 350 SOC_PM_100MB_FD | SOC_PM_100MB_HD | 351 SOC_PM_10MB_FD | SOC_PM_10MB_HD | SOC_PM_MII; 352 } else { 353 *mode = SOC_PM_100MB_FD | SOC_PM_100MB_HD | 354 SOC_PM_10MB_FD | SOC_PM_10MB_HD | SOC_PM_MII; 355 } 356 357 return SOC_E_NONE; 358 } 359 360 int 361 phy_portmod_dispatch_remote_ability_get(int unit, soc_port_t port, soc_port_ability_t *ability) 362 { 363 portmod_port_ability_t remote_ability; 364 365 sal_memset(&remote_ability, 0, sizeof(portmod_port_ability_t)); 366 portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_AbilityRemote, &remote_ability); 367 sal_memcpy(ability, &remote_ability, sizeof(soc_port_ability_t)); 368 369 return SOC_E_NONE; 370 } 371 372 int 373 phy_portmod_dispatch_advert_ability_get(int unit, soc_port_t port, soc_port_ability_t *ability) 374 { 375 portmod_port_ability_t advert_ability; 376 377 sal_memset(&advert_ability, 0, sizeof(portmod_port_ability_t)); 378 portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_AbilityAdvert, &advert_ability); 379 sal_memcpy(ability, &advert_ability, sizeof(soc_port_ability_t)); 380 381 return SOC_E_NONE; 382 } 383 384 int 385 phy_portmod_dispatch_local_ability_get(int unit, soc_port_t port, soc_port_ability_t *ability) 386 { 387 portmod_port_ability_t local_ability; 388 389 portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_AbilityLocal, &local_ability); 390 sal_memcpy(ability, &local_ability, sizeof(soc_port_ability_t)); 391 392 return SOC_E_NONE; 393 } 394 395 int 396 phy_portmod_dispatch_interface_set(int unit, soc_port_t port, soc_port_if_t pif) 397 { 398 int rv = SOC_E_NONE; 399 400 rv = portmod_ext_to_int_cmd_set(unit, port, portmodExtToInt_CtrlCode_Interface, (void *)(&pif)); 401 402 return rv; 403 } 404 405 int 406 phy_portmod_dispatch_duplex_set(int unit, soc_port_t port, int duplex) 407 { 408 /* Draco Quickturn specific code. */ 409 if (SAL_BOOT_QUICKTURN && IS_GE_PORT(unit, port)) { 410 return phy_fe_ge_duplex_set(unit, port, duplex); 411 } 412 413 return SOC_E_NONE; 414 } 415 416 int 417 phy_portmod_dispatch_duplex_get(int unit, soc_port_t port, int *duplex) 418 { 419 uint8 phy_addr; 420 uint16 mii_ctrl; 421 422 if (SAL_BOOT_QUICKTURN && IS_GE_PORT(unit, port)) { 423 phy_addr = PORT_TO_PHY_ADDR(unit, port); 424 /* Quickturn (may) have mii hooks for reconfiguring */ 425 SOC_IF_ERROR_RETURN( 426 soc_miim_read(unit, phy_addr, MII_CTRL_REG, &mii_ctrl)); 427 *duplex = (mii_ctrl & MII_CTRL_FD) ? 1 : 0; 428 return SOC_E_NONE; 429 } 430 431 /* Otherwise, just get speed from mac */ 432 *duplex = 1; 433 return SOC_E_NONE; 434 } 435 436 int 437 phy_portmod_dispatch_speed_set(int unit, soc_port_t port, int speed) 438 { 439 int rv = SOC_E_NONE; 440 441 rv = portmod_ext_to_int_cmd_set(unit, port, portmodExtToInt_CtrlCode_Speed, (void*)&speed); 442 return rv; 443 444 } 445 446 int 447 phy_portmod_dispatch_speed_get(int unit, soc_port_t port, int *speed) 448 { 449 int rv = SOC_E_NONE; 450 451 rv = portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_Speed, (void*)speed); 452 return rv; 453 454 455 } 456 457 458 int 459 phy_portmod_dispatch_interface_get(int unit, soc_port_t port, soc_port_if_t *pif) 460 { 461 int rv = SOC_E_NONE; 462 463 rv = portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_Interface, (void *)pif); 464 465 return rv; 466 } 467 468 469 470 471 int 472 phy_portmod_dispatch_nocxn_interface_get(int unit, soc_port_t port, soc_port_if_t *pif) 473 { 474 portmod_pdata_t pdata; 475 476 portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_Interface, &pdata); 477 sal_memcpy (pif , &(pdata.pif), sizeof(soc_port_if_t)); 478 479 return SOC_E_NONE; 480 } 481 482 /* 483 * Function: 484 * phy_portmod_dispatch_mdix_set 485 * Description: 486 * Set the Auto-MDIX mode of a port/PHY 487 * Parameters: 488 * unit - Device number 489 * port - Port number 490 * mode - One of: 491 * BCM_PORT_MDIX_AUTO 492 * Enable auto-MDIX when autonegotiation is enabled 493 * BCM_PORT_MDIX_FORCE_AUTO 494 * Enable auto-MDIX always 495 * BCM_PORT_MDIX_NORMAL 496 * Disable auto-MDIX 497 * BCM_PORT_MDIX_XOVER 498 * Disable auto-MDIX, and swap cable pairs 499 * Return Value: 500 * BCM_E_UNAVAIL - feature unsupported by hardware 501 * BCM_E_XXX - other error 502 */ 503 int 504 phy_portmod_dispatch_mdix_set(int unit, soc_port_t port, soc_port_mdix_t mode) 505 { 506 COMPILER_REFERENCE(unit); 507 COMPILER_REFERENCE(port); 508 509 if (mode == SOC_PORT_MDIX_NORMAL) { 510 return SOC_E_NONE; 511 } else { 512 return SOC_E_UNAVAIL; 513 } 514 } 515 516 /* 517 * Function: 518 * phy_portmod_dispatch_mdix_get 519 * Description: 520 * Get the Auto-MDIX mode of a port/PHY 521 * Parameters: 522 * unit - Device number 523 * port - Port number 524 * mode - (Out) One of: 525 * BCM_PORT_MDIX_AUTO 526 * Enable auto-MDIX when autonegotiation is enabled 527 * BCM_PORT_MDIX_FORCE_AUTO 528 * Enable auto-MDIX always 529 * BCM_PORT_MDIX_NORMAL 530 * Disable auto-MDIX 531 * BCM_PORT_MDIX_XOVER 532 * Disable auto-MDIX, and swap cable pairs 533 * Return Value: 534 * BCM_E_UNAVAIL - feature unsupported by hardware 535 * BCM_E_XXX - other error 536 */ 537 int 538 phy_portmod_dispatch_mdix_get(int unit, soc_port_t port, soc_port_mdix_t *mode) 539 { 540 COMPILER_REFERENCE(unit); 541 COMPILER_REFERENCE(port); 542 543 if (mode == NULL) { 544 return SOC_E_PARAM; 545 } 546 547 *mode = SOC_PORT_MDIX_NORMAL; 548 549 return SOC_E_NONE; 550 } 551 552 /* 553 * Function: 554 * phy_portmod_dispatch_mdix_status_get 555 * Description: 556 * Get the current MDIX status on a port/PHY 557 * Parameters: 558 * unit - Device number 559 * port - Port number 560 * status - (OUT) One of: 561 * BCM_PORT_MDIX_STATUS_NORMAL 562 * Straight connection 563 * BCM_PORT_MDIX_STATUS_XOVER 564 * Crossover has been performed 565 * Return Value: 566 * BCM_E_UNAVAIL - feature unsupported by hardware 567 * BCM_E_XXX - other error 568 */ 569 int 570 phy_portmod_dispatch_mdix_status_get(int unit, soc_port_t port, 571 soc_port_mdix_status_t *status) 572 { 573 COMPILER_REFERENCE(unit); 574 COMPILER_REFERENCE(port); 575 576 if (status == NULL) { 577 return SOC_E_PARAM; 578 } 579 580 *status = SOC_PORT_MDIX_STATUS_NORMAL; 581 582 return SOC_E_NONE; 583 } 584 585 /* 586 * Function: 587 * phy_portmod_dispatch_medium_get 588 * Description: 589 * Get the currently chosen medium for the dual-medium PHY 590 * Parameters: 591 * unit -- Device number 592 * port -- Port number 593 * medium -- (Out) One of 594 * SOC_PORT_MEDIUM_NONE 595 * SOC_PORT_MEDIUM_COPPER 596 * SOC_PORT_MEDIUM_FIBER 597 * 598 * Return value: 599 * BCM_E_NONE 600 * BCM_E_PARAM 601 * BCM_E_UNAVAIL 602 */ 603 int 604 phy_portmod_dispatch_medium_get(int unit, soc_port_t port, 605 soc_port_medium_t *medium) 606 { 607 int rv; 608 609 COMPILER_REFERENCE(unit); 610 COMPILER_REFERENCE(port); 611 612 if (medium != NULL) { 613 *medium = SOC_PORT_MEDIUM_NONE; 614 rv = SOC_E_NONE; 615 } else { 616 rv = SOC_E_PARAM; 617 } 618 619 return (rv); 620 } 621 622 /* 623 * Function: 624 * phy_portmod_dispatch_control_set 625 * Description: 626 * Get phy control 627 * Parameters: 628 * unit -- Device number 629 * port -- Port number 630 * param 631 * 632 * Return value: 633 * BCM_E_NONE 634 * BCM_E_PARAM 635 * BCM_E_UNAVAIL 636 */ 637 int 638 phy_portmod_dispatch_control_set(int unit, soc_port_t port, soc_phy_control_t phy_ctrl, uint32 param) 639 { 640 641 COMPILER_REFERENCE(unit); 642 COMPILER_REFERENCE(port); 643 COMPILER_REFERENCE(phy_ctrl); 644 COMPILER_REFERENCE(param); 645 646 return (SOC_E_NONE); 647 } 648 649 /* 650 * Function: 651 * phy_portmod_dispatch_control_get 652 * Description: 653 * Get phy control 654 * Parameters: 655 * unit -- Device number 656 * port -- Port number 657 * param 658 * 659 * Return value: 660 * BCM_E_NONE 661 * BCM_E_PARAM 662 * BCM_E_UNAVAIL 663 */ 664 int 665 phy_portmod_dispatch_control_get(int unit, soc_port_t port, soc_phy_control_t phy_ctrl, uint32 *param) 666 { 667 int rv; 668 669 COMPILER_REFERENCE(unit); 670 COMPILER_REFERENCE(port); 671 COMPILER_REFERENCE(phy_ctrl); 672 673 if (param != NULL) { 674 *param = 0; 675 rv = SOC_E_NONE; 676 } else { 677 rv = SOC_E_PARAM; 678 } 679 680 return (rv); 681 } 682 683 int 684 phy_portmod_dispatch_notify(int unit, soc_port_t port, 685 soc_phy_event_t event, uint32 value) 686 { 687 int cur_speed; 688 int rv; 689 690 if(event == phyEventSpeed) { 691 rv = portmod_ext_to_int_cmd_get(unit, port, portmodExtToInt_CtrlCode_Speed, (void*)&cur_speed); 692 if (rv != SOC_E_NONE) { 693 LOG_VERBOSE(BSL_LS_BCM_PORT, 694 (BSL_META_U(unit, "phy_portmod_dispatch_notify: portmod_ext_to_int_cmd_get failed"))); 695 return rv; 696 } 697 698 if(cur_speed != value){ 699 rv = portmod_ext_to_int_cmd_set(unit, port, portmodExtToInt_CtrlCode_Speed, (void*)&value); 700 if (rv != SOC_E_NONE) { 701 LOG_VERBOSE(BSL_LS_BCM_PORT, 702 (BSL_META_U(unit, "phy_portmod_dispatch_notify: portmod_ext_to_int_cmd_get failed"))); 703 return rv; 704 } 705 } 706 } 707 if(event == phyEventSpeedLine) { 708 rv = portmod_ext_to_int_cmd_set(unit, port, portmodExtToInt_CtrlCode_SpeedLine, (void*)&value); 709 if (rv != SOC_E_NONE) { 710 LOG_VERBOSE(BSL_LS_BCM_PORT, 711 (BSL_META_U(unit, "phy_portmod_dispatch_notify: portmod_ext_to_int_cmd_get failed"))); 712 return rv; 713 } 714 715 } 716 717 return SOC_E_NONE; 718 } 719 720 721 /* 722 * Variable: phy_null 723 * Purpose: Phy driver callouts for legacy ext phy to portmod int phy 724 */ 725 phy_driver_t phy_ext_to_int_drv = { 726 "Ext to Int PHY Driver conduit", 727 phy_portmod_dispatch_init, /* phy_init */ 728 phy_portmod_dispatch_reset, /* phy_reset */ 729 phy_portmod_dispatch_link_get, /* phy_link_get */ 730 phy_portmod_dispatch_enable_set, /* phy_enable_set */ 731 phy_portmod_dispatch_enable_get, /* phy_enable_get */ 732 phy_portmod_dispatch_duplex_set, /* phy_duplex_set */ 733 phy_portmod_dispatch_duplex_get, /* phy_duplex_get */ 734 phy_portmod_dispatch_speed_set, /* phy_speed_set */ 735 phy_portmod_dispatch_speed_get, /* phy_speed_get */ 736 phy_portmod_dispatch_set, /* phy_master_set */ 737 phy_portmod_dispatch_zero_get, /* phy_master_get */ 738 phy_portmod_dispatch_an_set, /* phy_an_set */ 739 phy_portmod_dispatch_an_get, /* phy_an_get */ 740 phy_portmod_dispatch_mode_set, /* phy_adv_local_set */ 741 phy_portmod_dispatch_mode_get, /* phy_adv_local_get */ 742 phy_portmod_dispatch_mode_get, /* phy_adv_remote_get */ 743 phy_portmod_dispatch_set, /* phy_lb_set */ 744 phy_portmod_dispatch_zero_get, /* phy_lb_get */ 745 phy_portmod_dispatch_interface_set, /* phy_interface_set */ 746 phy_portmod_dispatch_interface_get, /* phy_interface_get */ 747 phy_portmod_dispatch_mode_get, /* phy_ability */ 748 NULL, /* phy_linkup_evt */ 749 NULL, /* phy_linkdn_evt */ 750 phy_portmod_dispatch_mdix_set, /* phy_mdix_set */ 751 phy_portmod_dispatch_mdix_get, /* phy_mdix_get */ 752 phy_portmod_dispatch_mdix_status_get, /* phy_mdix_status_get */ 753 NULL, /* phy_medium_config_set */ 754 NULL, /* phy_medium_config_get */ 755 phy_portmod_dispatch_medium_get, /* phy_medium_get */ 756 NULL, /* phy_cable_diag */ 757 NULL, /* phy_link_change */ 758 phy_portmod_dispatch_control_set, /* phy_control_set */ 759 phy_portmod_dispatch_control_get, /* phy_control_get */ 760 NULL, /* phy_reg_read */ 761 NULL, /* phy_reg_write */ 762 NULL, /* phy_reg_modify */ 763 phy_portmod_dispatch_notify,/* phy_notify */ 764 NULL, /* phy_probe */ 765 phy_portmod_dispatch_advert_ability_set,/* phy_ability_advert_set */ 766 phy_portmod_dispatch_advert_ability_get,/* phy_ability_advert_get */ 767 phy_portmod_dispatch_remote_ability_get,/* phy_ability_remote_get */ 768 phy_portmod_dispatch_local_ability_get, /* phy_ability_local_get */ 769 NULL, /* phy_firmware_set */ 770 NULL, /* phy_timesync_config_set */ 771 NULL, /* phy_timesync_config_get */ 772 NULL, /* phy_timesync_control_set */ 773 NULL, /* phy_timesync_control_get */ 774 NULL /* phy_diag_ctrl */ 775 }; 776 #endif /* PORTMOD_SUPPORT */