phy_egphy28.h (41185B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phyegphy28.h 8 * 9 * This driver applies to BCMEGPHY28. 10 */ 11 12 #ifndef _PHYEGPHY28_H_ 13 #define _PHYEGPHY28_H_ 14 15 #include <soc/phy.h> 16 17 /* PHY register access */ 18 #define PHYEGPHY28_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 19 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 20 (_reg_addr), (_val)) 21 #define PHYEGPHY28_REG_WRITE(_unit, _phy_ctrl, _flags, \ 22 _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHYEGPHY28_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 26 _reg_addr, _val, _mask) \ 27 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val), (_mask)) 29 30 31 /* Clause 45 Registers access using Clause 22 register access */ 32 #define PHYEGPHY28_CL45_REG_READ(_unit, _phy_ctrl, _flags, _dev_addr, _reg_addr, _val) \ 33 _phy_egphy28_cl45_reg_read((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 34 (_reg_addr), (_val)) 35 #define PHYEGPHY28_CL45_REG_WRITE(_unit, _phy_ctrl, _flags, \ 36 _dev_addr, _reg_addr, _val) \ 37 _phy_egphy28_cl45_reg_write((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 38 (_reg_addr), (_val)) 39 #define PHYEGPHY28_CL45_REG_MODIFY(_unit, _phy_ctrl, _flags, _dev_addr, \ 40 _reg_addr, _val, _mask) \ 41 _phy_egphy28_cl45_reg_modify((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 42 (_reg_addr), (_val), (_mask)) 43 44 45 /************************************************** 46 * 47 * RDB/Legacy register accessing macros/functions 48 */ 49 #undef PHYEGPHY28_DEFAULT_TO_LEGACY_ADDRESSING /* default to RDB mode */ 50 51 /* Registers used to Rd/Wr using RDB mode */ 52 #define PHYEGPHY28_RDB_ADDR_REG_OFFSET (0x1E) 53 #define PHYEGPHY28_RDB_ADDR_REG_ADDR (0xffff) 54 #define PHYEGPHY28_RDB_DATA_REG_OFFSET (0x1F) 55 #define PHYEGPHY28_RDB_DATA_REG_DATA (0xffff) 56 #define PHYEGPHY28_REG_1E_SELECT_RDB (0x0087) 57 #define PHYEGPHY28_REG_1F_RDB_DIS (0x8000) 58 /* Registers used to enable RDB register access mode */ 59 #define PHYEGPHY28_REG_17_OFFSET (0x17) 60 #define PHYEGPHY28_REG_17_SELECT_EXP_7E (0x0F7E) 61 #define PHYEGPHY28_REG_15_OFFSET (0x15) 62 #define PHYEGPHY28_REG_15_RDB_EN (0x0000) 63 64 /* 65 * Macro for activating the RDB Register Addressing mode * 66 * Enable direct RDB addressing mode, write to Expansion register 0x7E = 0x0000 67 * - MDIO write to reg 0x17 = 0x0F7E 68 * - MDIO write to reg 0x15 = 0x0000 69 */ 70 #define PHYEGPHY28_RDB_ACCESS_MODE(_u, _pc) do { \ 71 SOC_IF_ERROR_RETURN( \ 72 WRITE_PHY_REG((_u), (_pc), PHYEGPHY28_REG_17_OFFSET, \ 73 PHYEGPHY28_REG_17_SELECT_EXP_7E) ); \ 74 SOC_IF_ERROR_RETURN( \ 75 WRITE_PHY_REG((_u), (_pc), PHYEGPHY28_REG_15_OFFSET, \ 76 PHYEGPHY28_REG_15_RDB_EN) ); \ 77 } while ( 0 ) 78 79 /* 80 * Macro for activating the Legacy Register Addressing mode * 81 * Disable direct RDB addressing mode, write to RDB register 0x87 = 0x8000 82 * - MDIO write to reg 0x1E = 0x0087 83 * - MDIO write to reg 0x1F = 0x8000 84 */ 85 #define PHYEGPHY28_LEGACY_ACCESS_MODE(_u, _pc) do { \ 86 SOC_IF_ERROR_RETURN( \ 87 WRITE_PHY_REG((_u), (_pc), PHYEGPHY28_RDB_ADDR_REG_OFFSET, \ 88 PHYEGPHY28_REG_1E_SELECT_RDB) );\ 89 SOC_IF_ERROR_RETURN( \ 90 WRITE_PHY_REG((_u), (_pc), PHYEGPHY28_RDB_DATA_REG_OFFSET, \ 91 PHYEGPHY28_REG_1F_RDB_DIS) ); \ 92 } while ( 0 ) 93 94 95 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 96 #define READ_PHYEGPHY28_MII_CTRLr(_unit, _phy_ctrl, _val) \ 97 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 98 #define WRITE_PHYEGPHY28_MII_CTRLr(_unit, _phy_ctrl, _val) \ 99 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 100 #define MODIFY_PHYEGPHY28_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 101 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 102 (_val), (_mask)) 103 104 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 105 #define READ_PHYEGPHY28_MII_STATr(_unit, _phy_ctrl, _val) \ 106 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 107 #define WRITE_PHYEGPHY28_MII_STATr(_unit, _phy_ctrl, _val) \ 108 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 109 #define MODIFY_PHYEGPHY28_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 110 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 111 (_val), (_mask)) 112 113 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 114 #define READ_PHYEGPHY28_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 115 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 116 #define WRITE_PHYEGPHY28_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 117 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 118 #define MODIFY_PHYEGPHY28_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 119 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 120 (_val), (_mask)) 121 122 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 123 #define READ_PHYEGPHY28_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 124 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 125 #define WRITE_PHYEGPHY28_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 126 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 127 #define MODIFY_PHYEGPHY28_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 128 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 129 (_val), (_mask)) 130 131 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 132 #define READ_PHYEGPHY28_MII_ANAr(_unit, _phy_ctrl, _val) \ 133 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 134 #define WRITE_PHYEGPHY28_MII_ANAr(_unit, _phy_ctrl, _val) \ 135 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 136 #define MODIFY_PHYEGPHY28_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 137 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 138 (_val), (_mask)) 139 140 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 141 #define READ_PHYEGPHY28_MII_ANPr(_unit, _phy_ctrl, _val) \ 142 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 143 #define WRITE_PHYEGPHY28_MII_ANPr(_unit, _phy_ctrl, _val) \ 144 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 145 #define MODIFY_PHYEGPHY28_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 146 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 147 (_val), (_mask)) 148 149 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 150 #define READ_PHYEGPHY28_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 151 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 152 #define WRITE_PHYEGPHY28_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 153 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 154 #define MODIFY_PHYEGPHY28_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 155 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 156 (_val), (_mask)) 157 158 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 159 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 160 161 /* 1000BASE-T Control Register (ADDR 09h) */ 162 #define READ_PHYEGPHY28_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 163 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 164 #define WRITE_PHYEGPHY28_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 165 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 166 #define MODIFY_PHYEGPHY28_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 167 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 168 (_val), (_mask)) 169 170 /* 1000BASE-T Status Register (ADDR 0ah) */ 171 #define READ_PHYEGPHY28_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 172 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 173 #define WRITE_PHYEGPHY28_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 174 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 175 #define MODIFY_PHYEGPHY28_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 176 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 177 (_val), (_mask)) 178 179 /* (Addr 0ch-0eh) Reserved (Do not read/write to reserved registers. */ 180 181 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 182 183 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 184 #define READ_PHYEGPHY28_MII_ECRr(_unit, _phy_ctrl, _val) \ 185 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 186 #define WRITE_PHYEGPHY28_MII_ECRr(_unit, _phy_ctrl, _val) \ 187 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 188 #define MODIFY_PHYEGPHY28_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 189 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 190 (_val), (_mask)) 191 192 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 193 #define READ_PHYEGPHY28_MII_ESRr(_unit, _phy_ctrl, _val) \ 194 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 195 #define WRITE_PHYEGPHY28_MII_ESRr(_unit, _phy_ctrl, _val) \ 196 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 197 #define MODIFY_PHYEGPHY28_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 198 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 199 (_val), (_mask)) 200 201 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 202 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 203 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 204 205 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 206 #define READ_PHYEGPHY28_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 207 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 208 #define WRITE_PHYEGPHY28_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 209 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 210 #define MODIFY_PHYEGPHY28_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 211 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 212 (_val), (_mask)) 213 214 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 215 #define READ_PHYEGPHY28_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 216 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 217 #define WRITE_PHYEGPHY28_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 218 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 219 #define MODIFY_PHYEGPHY28_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 220 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 221 (_val), (_mask)) 222 223 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 224 #define READ_PHYEGPHY28_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 225 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 226 #define WRITE_PHYEGPHY28_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 227 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 228 #define MODIFY_PHYEGPHY28_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 229 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 230 (_val), (_mask)) 231 232 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 233 #define READ_PHYEGPHY28_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 234 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 235 #define WRITE_PHYEGPHY28_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 236 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 237 #define MODIFY_PHYEGPHY28_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 238 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 239 (_val), (_mask)) 240 241 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 242 #define READ_PHYEGPHY28_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 243 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 244 #define WRITE_PHYEGPHY28_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 245 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 246 #define MODIFY_PHYEGPHY28_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 247 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 248 (_val), (_mask)) 249 250 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 251 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 252 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 253 254 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 255 #define READ_PHYEGPHY28_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 256 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 257 #define WRITE_PHYEGPHY28_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 258 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 259 #define MODIFY_PHYEGPHY28_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 260 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 261 (_val), (_mask)) 262 263 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 264 #define READ_PHYEGPHY28_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 265 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 266 #define WRITE_PHYEGPHY28_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 267 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 268 #define MODIFY_PHYEGPHY28_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 269 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 270 (_val), (_mask)) 271 272 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 273 #define READ_PHYEGPHY28_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 274 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 275 #define WRITE_PHYEGPHY28_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 276 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 277 #define MODIFY_PHYEGPHY28_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 278 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 279 (_val), (_mask)) 280 #define PHY_EGPHY28_SPARE_CTRL3_REG_DLL_AUTO_PWR_DOWN (0x1 << 1) 281 282 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 283 #define READ_PHYEGPHY28_LED_STATr(_unit, _phy_ctrl, _val) \ 284 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 285 #define WRITE_PHYEGPHY28_LED_STATr(_unit, _phy_ctrl, _val) \ 286 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 287 #define MODIFY_PHYEGPHY28_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 288 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 289 (_val), (_mask)) 290 291 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 292 #define READ_PHYEGPHY28_LED_CTRLr(_unit, _phy_ctrl, _val) \ 293 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 294 #define WRITE_PHYEGPHY28_LED_CTRLr(_unit, _phy_ctrl, _val) \ 295 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 296 #define MODIFY_PHYEGPHY28_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 297 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 298 (_val), (_mask)) 299 300 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 301 #define READ_PHYEGPHY28_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 302 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 303 #define WRITE_PHYEGPHY28_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 304 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 305 #define MODIFY_PHYEGPHY28_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 306 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 307 (_val), (_mask)) 308 309 #define PHY_EGPHY28_AUTO_PWRDWN_EN (1 << 5) 310 #define PHY_EGPHY28_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 311 #define PHY_EGPHY28_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 312 #define PHY_EGPHY28_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 313 #define PHY_EGPHY28_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 314 #define PHY_EGPHY28_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 315 316 /* SLED_1 Reg (ADDR 1ch shadow 01011) */ 317 #define READ_PHYEGPHY28_SLED_1r(_unit, _phy_ctrl, _val) \ 318 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, (_val)) 319 #define WRITE_PHYEGPHY28_SLED_1r(_unit, _phy_ctrl, _val) \ 320 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, (_val)) 321 #define MODIFY_PHYEGPHY28_SLED_1r(_unit, _phy_ctrl, _val, _mask) \ 322 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, \ 323 (_val), (_mask)) 324 325 /* SLED_2 Reg (ADDR 1ch shadow 01100) */ 326 #define READ_PHYEGPHY28_SLED_2r(_unit, _phy_ctrl, _val) \ 327 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, (_val)) 328 #define WRITE_PHYEGPHY28_SLED_2r(_unit, _phy_ctrl, _val) \ 329 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, (_val)) 330 #define MODIFY_PHYEGPHY28_SLED_2r(_unit, _phy_ctrl, _val, _mask) \ 331 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, \ 332 (_val), (_mask)) 333 334 335 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 336 #define READ_PHYEGPHY28_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 337 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 338 #define WRITE_PHYEGPHY28_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 339 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 340 #define MODIFY_PHYEGPHY28_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 341 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 342 (_val), (_mask)) 343 344 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 345 #define READ_PHYEGPHY28_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 346 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 347 #define WRITE_PHYEGPHY28_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 348 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 349 #define MODIFY_PHYEGPHY28_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 350 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 351 (_val), (_mask)) 352 353 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 354 #define READ_PHYEGPHY28_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 355 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, (_val)) 356 #define WRITE_PHYEGPHY28_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 357 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, (_val)) 358 #define MODIFY_PHYEGPHY28_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 359 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, \ 360 (_val), (_mask)) 361 362 /* External SerDes Control Reg (ADDR 1ch shadow 10100) */ 363 #define READ_PHYEGPHY28_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 364 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 365 #define WRITE_PHYEGPHY28_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 366 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 367 #define MODIFY_PHYEGPHY28_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 368 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, \ 369 (_val), (_mask)) 370 371 /* SGMII SLAVE Reg (ADDR 1ch shadow 10101) */ 372 #define READ_PHYEGPHY28_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 373 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 374 #define WRITE_PHYEGPHY28_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 375 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 376 #define MODIFY_PHYEGPHY28_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 377 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, \ 378 (_val), (_mask)) 379 380 /* Misc. 1000BASE-X Control 2 Reg (ADDR 1ch shadow 10110) */ 381 #define READ_PHYEGPHY28_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 382 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 383 #define WRITE_PHYEGPHY28_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 384 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 385 #define MODIFY_PHYEGPHY28_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 386 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 387 (_val), (_mask)) 388 389 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 390 #define READ_PHYEGPHY28_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 391 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 392 #define WRITE_PHYEGPHY28_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 393 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 394 #define MODIFY_PHYEGPHY28_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 395 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 396 (_val), (_mask)) 397 398 /* Auxiliary Control Reg (ADDR 1ch shadow 11011) */ 399 #define READ_PHYEGPHY28_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 400 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, (_val)) 401 #define WRITE_PHYEGPHY28_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 402 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, (_val)) 403 #define MODIFY_PHYEGPHY28_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 404 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, \ 405 (_val), (_mask)) 406 407 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 408 #define READ_PHYEGPHY28_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 409 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, (_val)) 410 #define WRITE_PHYEGPHY28_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 411 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, (_val)) 412 #define MODIFY_PHYEGPHY28_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 413 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, \ 414 (_val), (_mask)) 415 416 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 417 #define READ_PHYEGPHY28_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 418 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, (_val)) 419 #define WRITE_PHYEGPHY28_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 420 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, (_val)) 421 #define MODIFY_PHYEGPHY28_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 422 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, \ 423 (_val), (_mask)) 424 425 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 426 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 427 428 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 429 #define READ_PHYEGPHY28_TEST1r(_unit, _phy_ctrl, _val) \ 430 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 431 #define WRITE_PHYEGPHY28_TEST1r(_unit, _phy_ctrl, _val) \ 432 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 433 #define MODIFY_PHYEGPHY28_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 434 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 435 (_val), (_mask)) 436 437 /* +---------------------+ 438 * | | 439 * | SGMII Registers | 440 * | | 441 * +---------------------+ 442 */ 443 /* SGMII Control Register (Addr 00h) */ 444 #define READ_PHYEGPHY28_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 445 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 446 0x0000, 0x00, (_val)) 447 #define WRITE_PHYEGPHY28_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 448 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 449 0x0000, 0x00, (_val)) 450 #define MODIFY_PHYEGPHY28_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 451 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 452 0x0000, 0x00, (_val), (_mask)) 453 454 /* SGMII Status Register (Addr 01h) */ 455 #define READ_PHYEGPHY28_SGMII_STATr(_unit, _phy_ctrl, _val) \ 456 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 457 0x0000, 0x01, (_val)) 458 #define WRITE_PHYEGPHY28_SGMII_STATr(_unit, _phy_ctrl, _val) \ 459 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 460 0x0000, 0x01, (_val)) 461 #define MODIFY_PHYEGPHY28_SGMII_STATr(_unit, _phy_ctrl, _val, _mask) \ 462 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 463 0x0000, 0x01, (_val), (_mask)) 464 465 /* SGMII Auto-neg Advertise Register (Addr 04h) */ 466 #define READ_PHYEGPHY28_SGMII_ANAr(_unit, _phy_ctrl, _val) \ 467 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 468 0x0000, 0x04, (_val)) 469 #define WRITE_PHYEGPHY28_SGMII_ANAr(_unit, _phy_ctrl, _val) \ 470 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 471 0x0000, 0x04, (_val)) 472 #define MODIFY_PHYEGPHY28_SGMII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 473 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 474 0x0000, 0x04, (_val), (_mask)) 475 476 /* SGMII Auto-neg Link Partner Ability Register (Addr 05h) */ 477 #define READ_PHYEGPHY28_SGMII_ANPr(_unit, _phy_ctrl, _val) \ 478 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 479 0x0000, 0x05, (_val)) 480 #define WRITE_PHYEGPHY28_SGMII_ANPr(_unit, _phy_ctrl, _val) \ 481 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 482 0x0000, 0x05, (_val)) 483 #define MODIFY_PHYEGPHY28_SGMII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 484 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 485 0x0000, 0x05, (_val), (_mask)) 486 487 /* +-------------------------+ 488 * | | 489 * | Expansion Registers | 490 * | | 491 * +-------------------------+ 492 */ 493 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 494 #define READ_PHYEGPHY28_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 495 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F00, 0x15, (_val)) 496 #define WRITE_PHYEGPHY28_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 497 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F00, \ 498 0x15, (_val)) 499 #define MODIFY_PHYEGPHY28_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 500 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F00, \ 501 0x15, (_val), (_mask)) 502 503 /* Multicolor LED Selector Register (Addr 04h) */ 504 #define READ_PHYEGPHY28_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 505 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F04, 0x15, (_val)) 506 #define WRITE_PHYEGPHY28_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 507 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F04, \ 508 0x15, (_val)) 509 #define MODIFY_PHYEGPHY28_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 510 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F04, \ 511 0x15, (_val), (_mask)) 512 513 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 514 #define READ_PHYEGPHY28_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 515 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F05, 0x15, (_val)) 516 #define WRITE_PHYEGPHY28_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 517 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F05, \ 518 0x15, (_val)) 519 #define MODIFY_PHYEGPHY28_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 520 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F05, \ 521 0x15, (_val), (_mask)) 522 523 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 524 #define READ_PHYEGPHY28_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 525 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F06, 0x15, (_val)) 526 #define WRITE_PHYEGPHY28_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 527 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F06, \ 528 0x15, (_val)) 529 #define MODIFY_PHYEGPHY28_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 530 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F06, \ 531 0x15, (_val), (_mask)) 532 533 /* 100Base-FX Far End Fault egister (Addr 07h) */ 534 #define READ_PHYEGPHY28_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val) \ 535 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F07, 0x15, (_val)) 536 #define WRITE_PHYEGPHY28_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val) \ 537 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F07, \ 538 0x15, (_val)) 539 #define MODIFY_PHYEGPHY28_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val, _mask) \ 540 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F07, \ 541 0x15, (_val), (_mask)) 542 543 /* Port Interrupt Status Register (Addr 0bh) */ 544 #define READ_PHYEGPHY28_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 545 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F0B, 0x15, (_val)) 546 #define WRITE_PHYEGPHY28_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 547 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F0B, \ 548 0x15, (_val)) 549 #define MODIFY_PHYEGPHY28_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val, _mask) \ 550 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F0B, \ 551 0x15, (_val), (_mask)) 552 /* Cable Diag Control Register (Addr 10h) */ 553 #define READ_PHYEGPHY28_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val) \ 554 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F10, 0x15, (_val)) 555 #define WRITE_PHYEGPHY28_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val) \ 556 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F10, \ 557 0x15, (_val)) 558 #define MODIFY_PHYEGPHY28_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 559 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F10, \ 560 0x15, (_val), (_mask)) 561 562 /* Cable Diag Result Register (Addr 11h) */ 563 #define READ_PHYEGPHY28_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val) \ 564 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F11, 0x15, (_val)) 565 #define WRITE_PHYEGPHY28_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val) \ 566 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F11, \ 567 0x15, (_val)) 568 #define MODIFY_PHYEGPHY28_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val, _mask) \ 569 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F11, \ 570 0x15, (_val), (_mask)) 571 572 /* Cable Diag Length Register (Addr 12h) */ 573 #define READ_PHYEGPHY28_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val) \ 574 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F12, 0x15, (_val)) 575 #define WRITE_PHYEGPHY28_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val) \ 576 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F12, \ 577 0x15, (_val)) 578 #define MODIFY_PHYEGPHY28_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val, _mask) \ 579 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F12, \ 580 0x15, (_val), (_mask)) 581 582 583 /* Operating Mode Status Register (Addr 42h) */ 584 #define READ_PHYEGPHY28_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 585 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F42, 0x15, (_val)) 586 #define WRITE_PHYEGPHY28_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 587 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F42, \ 588 0x15, (_val)) 589 #define MODIFY_PHYEGPHY28_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val, _mask) \ 590 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F42, \ 591 0x15, (_val), (_mask)) 592 593 /* SGMII/Lineside Loopback Control Register (Addr 44h) */ 594 #define READ_PHYEGPHY28_EXP_SGMII_LINESIDE_LOOPBACK_CTRLr(_unit, _phy_ctrl, _val) \ 595 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, (_val)) 596 #define WRITE_PHYEGPHY28_EXP_SGMII_LINESIDE_LOOPBACK_CTRLr(_unit, _phy_ctrl, _val) \ 597 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, (_val)) 598 #define MODIFY_PHYEGPHY28_EXP_SGMII_LINESIDE_LOOPBACK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 599 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, \ 600 (_val), (_mask)) 601 602 /* SerDes/SGMII Control Register (Addr 52h) */ 603 #define READ_PHYEGPHY28_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 604 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 605 #define WRITE_PHYEGPHY28_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 606 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 607 #define MODIFY_PHYEGPHY28_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 608 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, \ 609 (_val), (_mask)) 610 611 612 /* EEE related */ 613 614 /* Auto EEE MII_Buffer CNTL/Status 2 Register (Addr AEh) */ 615 #define READ_PHYEGPHY28_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 616 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAE, 0x15, (_val)) 617 #define WRITE_PHYEGPHY28_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 618 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 619 0x15, (_val)) 620 #define MODIFY_PHYEGPHY28_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 621 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 622 0x15, (_val), (_mask)) 623 624 /* Auto EEE MII_Buffer CNTL/Status 1 Register (Addr AFh) */ 625 #define READ_PHYEGPHY28_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 626 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAF, 0x15, (_val)) 627 #define WRITE_PHYEGPHY28_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 628 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 629 0x15, (_val)) 630 #define MODIFY_PHYEGPHY28_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 631 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 632 0x15, (_val), (_mask)) 633 634 /* EEE Statistics related */ 635 /* Local LPI request Counter Reg (Addr ach) */ 636 #define READ_PHYEGPHY28_EXP_EEE_TX_EVENTSr(_unit, _phy_ctrl, _val) \ 637 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAC, 0x15, (_val)) 638 639 /* Remote LPI request Counter Reg (Addr adh) */ 640 #define READ_PHYEGPHY28_EXP_EEE_RX_EVENTSr(_unit, _phy_ctrl, _val) \ 641 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAD, 0x15, (_val)) 642 643 /* Statistic Timer_12_hours_lpi remote Reg (Addr aah) */ 644 #define READ_PHYEGPHY28_EXP_EEE_TX_DURATIONr(_unit, _phy_ctrl, _val) \ 645 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAA, 0x15, (_val)) 646 647 /* Statistic Timer_12_hours_lpi_local Local Reg (Addr abh) */ 648 #define READ_PHYEGPHY28_EXP_EEE_RX_DURATIONr(_unit, _phy_ctrl, _val) \ 649 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAB, 0x15, (_val)) 650 651 /* IEEE 1588 read start/end control Register (Addr f3h) */ 652 #define READ_PHYEGPHY28_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 653 PHYEGPHY28_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 654 #define WRITE_PHYEGPHY28_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 655 PHYEGPHY28_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 656 #define MODIFY_PHYEGPHY28_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 657 PHYEGPHY28_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, \ 658 (_val), (_mask)) 659 660 /* EEE Capability Register */ 661 #define READ_PHYEGPHY28_EEE_CAPr(_unit, _phy_ctrl, _val) \ 662 PHYEGPHY28_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x3, 0x14, _val) 663 664 /* EEE Advertisement Register */ 665 #define READ_PHYEGPHY28_EEE_ADVr(_unit, _phy_ctrl, _val) \ 666 PHYEGPHY28_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 667 #define WRITE_PHYEGPHY28_EEE_ADVr(_unit, _phy_ctrl, _val) \ 668 PHYEGPHY28_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 669 #define MODIFY_PHYEGPHY28_EEE_ADVr(_unit, _phy_ctrl, _val, _mask) \ 670 PHYEGPHY28_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val, _mask) 671 672 #define READ_PHYEGPHY28_EEE_803Dr(_unit, _phy_ctrl, _val) \ 673 PHYEGPHY28_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 674 #define WRITE_PHYEGPHY28_EEE_803Dr(_unit, _phy_ctrl, _val) \ 675 PHYEGPHY28_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 676 #define MODIFY_PHYEGPHY28_EEE_803Dr(_unit, _phy_ctrl, _val, _mask) \ 677 PHYEGPHY28_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val, _mask) 678 679 /* EEE Resolution Status Register */ 680 #define READ_PHYEGPHY28_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 681 PHYEGPHY28_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 682 #define WRITE_PHYEGPHY28_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 683 PHYEGPHY28_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 684 #define MODIFY_PHYEGPHY28_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val, _mask) \ 685 PHYEGPHY28_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val, _mask) 686 687 #define READ_PHYEGPHY28_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 688 PHYEGPHY28_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 689 #define WRITE_PHYEGPHY28_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 690 PHYEGPHY28_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 691 #define MODIFY_PHYEGPHY28_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val, _mask) \ 692 PHYEGPHY28_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val, _mask) 693 694 /* EEE TEST Control Register B*/ 695 #define READ_PHYEGPHY28_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 696 PHYEGPHY28_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 697 #define WRITE_PHYEGPHY28_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 698 PHYEGPHY28_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 699 #define MODIFY_PHYEGPHY28_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val, _mask) \ 700 PHYEGPHY28_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val, _mask) 701 702 typedef struct { 703 uint32 flags; 704 uint16 phy_id_orig; 705 uint16 phy_id_base; /* port 0 addr */ 706 uint16 phy_slice; 707 } PHYEGPHY28_DEV_DESC_t; 708 709 #define PHYEGPHY28_DEV_PHY_ID_ORIG(_pc) (((PHYEGPHY28_DEV_DESC_t *)((_pc) + 1))->phy_id_orig) 710 #define PHYEGPHY28_DEV_PHY_ID_BASE(_pc) (((PHYEGPHY28_DEV_DESC_t *)((_pc) + 1))->phy_id_base) 711 #define PHYEGPHY28_DEV_PHY_SLICE(_pc) (((PHYEGPHY28_DEV_DESC_t *)((_pc) + 1))->phy_slice) 712 #define PHYEGPHY28_FLAGS(_pc) (((PHYEGPHY28_DEV_DESC_t *)((_pc) + 1))->flags) 713 #define PHYEGPHY28_PHYA_REV (1U << 0) 714 715 #define PHYEGPHY28_DEV_SET_BASE_ADDR(_pc) \ 716 PHYEGPHY28_DEV_PHY_ID_BASE(_pc) = (PHYEGPHY28_FLAGS((_pc)) & PHYEGPHY28_PHYA_REV) ?\ 717 PHYEGPHY28_DEV_PHY_ID_ORIG(_pc) + PHYEGPHY28_DEV_PHY_SLICE(_pc) : \ 718 PHYEGPHY28_DEV_PHY_ID_ORIG(_pc) - PHYEGPHY28_DEV_PHY_SLICE(_pc) 719 720 #define PHYEGPHY28_SLICE_ADDR(_pc, _slice) \ 721 (PHYEGPHY28_FLAGS((_pc)) & PHYEGPHY28_PHYA_REV) ? (PHYEGPHY28_DEV_PHY_ID_BASE(_pc) - (_slice)) : \ 722 (PHYEGPHY28_DEV_PHY_ID_BASE(_pc) + (_slice)) 723 724 #endif /* _PHYEGPHY28_H_ */