phy8806x_ctr.h (4469B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8806x_funcs.h 8 */ 9 10 #ifndef _PHY8806X_CTR_H_ 11 #define _PHY8806X_CTR_H_ 12 13 #include <sal/types.h> 14 15 16 /* Make sure this structure matches the matching structure in the MT2 Firmware */ 17 typedef struct mt2_eth_ctr_s { 18 uint64 r64; 19 uint64 r127; 20 uint64 r255; 21 uint64 r511; 22 uint64 r1023; 23 uint64 r1518; 24 uint64 rmgv; 25 uint64 r2047; 26 uint64 r4095; 27 uint64 r9216; 28 uint64 r16383; 29 uint64 rpkt; 30 uint64 ruca; 31 uint64 rmca; 32 uint64 rbca; 33 uint64 rfcs; 34 uint64 rxcf; 35 uint64 rxpf; 36 uint64 rxpp; 37 uint64 rxuo; 38 uint64 rxuda; 39 uint64 rxwsa; 40 uint64 raln; 41 uint64 rflr; 42 uint64 rerpkt; 43 uint64 rfcr; 44 uint64 rovr; 45 uint64 rjbr; 46 uint64 rmtue; 47 uint64 rmcrc; 48 uint64 rprm; 49 uint64 rvln; 50 uint64 rdvln; 51 uint64 rtrfu; 52 uint64 rpok; 53 uint64 rpfcoff0; 54 uint64 rpfcoff1; 55 uint64 rpfcoff2; 56 uint64 rpfcoff3; 57 uint64 rpfcoff4; 58 uint64 rpfcoff5; 59 uint64 rpfcoff6; 60 uint64 rpfcoff7; 61 uint64 rpfc0; 62 uint64 rpfc1; 63 uint64 rpfc2; 64 uint64 rpfc3; 65 uint64 rpfc4; 66 uint64 rpfc5; 67 uint64 rpfc6; 68 uint64 rpfc7; 69 uint64 rschcrc; 70 uint64 rund; 71 uint64 rfrg; 72 uint64 rx_eee_lpi_event_counter; 73 uint64 rx_eee_lpi_duration_counter; 74 uint64 rx_llfc_phy_counter; 75 uint64 rx_llfc_log_counter; 76 uint64 rx_llfc_crc_counter; 77 uint64 rx_hcfc_counter; 78 uint64 rbyt; 79 uint64 rrbyt; 80 uint64 rrpkt; 81 uint64 t64; 82 uint64 t127; 83 uint64 t255; 84 uint64 t511; 85 uint64 t1023; 86 uint64 t1518; 87 uint64 tmgv; 88 uint64 t2047; 89 uint64 t4095; 90 uint64 t9216; 91 uint64 t16383; 92 uint64 tpok; 93 uint64 tpkt; 94 uint64 tuca; 95 uint64 tmca; 96 uint64 tbca; 97 uint64 txpf; 98 uint64 txpp; 99 uint64 tjbr; 100 uint64 tfcs; 101 uint64 txcf; 102 uint64 tovr; 103 uint64 tdfr; 104 uint64 tedf; 105 uint64 tscl; 106 uint64 tmcl; 107 uint64 tlcl; 108 uint64 txcl; 109 uint64 tfrg; 110 uint64 terr; 111 uint64 tvln; 112 uint64 tdvln; 113 uint64 trpkt; 114 uint64 tufl; 115 uint64 tpfc0; 116 uint64 tpfc1; 117 uint64 tpfc2; 118 uint64 tpfc3; 119 uint64 tpfc4; 120 uint64 tpfc5; 121 uint64 tpfc6; 122 uint64 tpfc7; 123 uint64 tx_eee_lpi_event_counter; 124 uint64 tx_eee_lpi_duration_counter; 125 /* uint64 tx_llfc_phy_counter; */ 126 uint64 tx_llfc_log_counter; 127 uint64 tx_hcfc_counter; 128 uint64 tncl; 129 uint64 tbyt; 130 } mt2_eth_ctr_t; 131 132 #ifdef INCLUDE_FCMAP 133 /* Make sure this structure matches the matching structure in the MT2 Firmware */ 134 typedef struct mt2_fc_ctr_s { 135 uint64 fc_c2_rxgoodframes; 136 uint64 fc_c2_rxinvalidcrc; 137 uint64 fc_c2_rxframetoolong; 138 uint64 fc_c3_rxgoodframes; 139 uint64 fc_c3_rxinvalidcrc; 140 uint64 fc_c3_rxframetoolong; 141 uint64 fc_cf_rxgoodframes; 142 uint64 fc_cf_rxinvalidcrc; 143 uint64 fc_cf_rxframetoolong; 144 uint64 fc_rxdelimitererr; 145 uint64 fc_rxbbc0drop; 146 uint64 fc_rxbbcredit0; 147 uint64 fc_rxlinkfail; 148 uint64 fc_rxsyncfail; 149 uint64 fc_rxlosssig; 150 uint64 fc_rxprimseqerr; 151 uint64 fc_rxinvalidset; 152 uint64 fc_rxlpicount; 153 uint64 fc_rxencodedisparity; 154 uint64 fc_rxbadxword; 155 uint64 fc_rx_c2_runtframes; 156 uint64 fc_rx_c3_runtframes; 157 uint64 fc_rx_cf_runtframes; 158 uint64 fc_c2_rxbyt; 159 uint64 fc_c3_rxbyt; 160 uint64 fc_cf_rxbyt; 161 uint64 fc_tx_c2_frames; 162 uint64 fc_tx_c3_frames; 163 uint64 fc_tx_cf_frames; 164 uint64 fc_tx_c2_oversized_frames; 165 uint64 fc_tx_c3_oversized_frames; 166 uint64 fc_tx_cf_oversized_frames; 167 uint64 fc_txbbcredit0; 168 uint64 fc_c2_txbyt; 169 uint64 fc_c3_txbyt; 170 uint64 fc_cf_txbyt; 171 } mt2_fc_ctr_t; 172 #endif /* INCLUDE_FCMAP */ 173 174 #define MT2_CTR_ALL 0x80 175 #define MT2_CTR_SYS 0x01 176 #define MT2_CTR_LINE 0x02 177 #define MT2_CTR_CHANGED 0x04 178 #define MT2_CTR_SAME 0x08 179 #define MT2_CTR_ZERO 0x10 180 #define MT2_CTR_NONZERO 0x20 181 #define MT2_CTR_HEX 0x40 182 183 #define MT2_CTR_DEFAULT (MT2_CTR_SYS | MT2_CTR_LINE | MT2_CTR_CHANGED | MT2_CTR_ZERO | MT2_CTR_NONZERO) 184 185 extern int phy8806x_ctr_start(int unit); 186 extern int phy8806x_ctr_stop(int unit); 187 extern int phy8806x_ctr_show(phy_ctrl_t *pc, uint32_t flags); 188 extern int phy8806x_ctr_interval_set(phy_ctrl_t *pc, uint32_t val); 189 190 #endif /* _PHY8806X_CTR_H_ */ 191