phy8806x.h (38463B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8806x.h 8 */ 9 10 #ifndef _PHY8806X_H_ 11 #define _PHY8806X_H_ 12 13 #include <soc/phy.h> 14 #include <soc/util.h> 15 #include <soc/ll.h> 16 17 #define montreal2_TOP_DEV_REV_IDr 0x02000000 18 19 #define montreal2_TOP_SOFT_RESET_REGr 0x02000100 20 #define montreal2_TOP_RTS_MISC_CTRLr 0x02006f00 21 #define montreal2_TOP_SOFT_RESET_REG_2r 0x02000200 22 #define montreal2_TOP_FC_MODE_CONTROLr 0x02007300 23 24 #define montreal2_AXI_CONTROL_F0r 0x02804600 25 #define montreal2_AXI_CONTROL_F1r 0x02806600 26 27 #define montreal2_AXI_STATUS_F0r 0x02804700 28 #define montreal2_AXI_STATUS_F1r 0x02806700 29 30 #define montreal2_MISC_CONTROLr 0x02808000 31 32 #define montreal2_AXI_ADDR_LOWER_F0r 0x02804100 33 #define montreal2_AXI_ADDR_LOWER_F1r 0x02806100 34 #define montreal2_AXI_ADDR_UPPER_F0r 0x02804000 35 #define montreal2_AXI_ADDR_UPPER_F1r 0x02806000 36 37 #define montreal2_AXI_DATA_BYTES_7_6_F0r 0x02804500 38 #define montreal2_AXI_DATA_BYTES_5_4_F0r 0x02804400 39 #define montreal2_AXI_DATA_BYTES_3_2_F0r 0x02804300 40 #define montreal2_AXI_DATA_BYTES_1_0_F0r 0x02804200 41 42 #define montreal2_AXI_DATA_BYTES_7_6_F1r 0x02806500 43 #define montreal2_AXI_DATA_BYTES_5_4_F1r 0x02806400 44 #define montreal2_AXI_DATA_BYTES_3_2_F1r 0x02806300 45 #define montreal2_AXI_DATA_BYTES_1_0_F1r 0x02806200 46 47 #define montreal2_SBUS_DATA_BYTES_15_14r 0x02802b00 48 #define montreal2_SBUS_DATA_BYTES_13_12r 0x02802a00 49 #define montreal2_SBUS_DATA_BYTES_11_10r 0x02802900 50 #define montreal2_SBUS_DATA_BYTES_9_8r 0x02802800 51 #define montreal2_SBUS_DATA_BYTES_7_6r 0x02802700 52 #define montreal2_SBUS_DATA_BYTES_5_4r 0x02802600 53 #define montreal2_SBUS_DATA_BYTES_3_2r 0x02802500 54 #define montreal2_SBUS_DATA_BYTES_1_0r 0x02802400 55 56 #define montreal2_SBUS_COMMAND_UPPERr 0x02802200 57 #define montreal2_SBUS_COMMAND_LOWERr 0x02802300 58 #define montreal2_SBUS_ADDR_UPPERr 0x02802000 59 #define montreal2_SBUS_ADDR_LOWERr 0x02802100 60 61 #define montreal2_SBUS_STATUSr 0x02802d00 62 #define montreal2_SBUS_CONTROLr 0x02802c00 63 64 #define montreal2_SW_TO_FW_INTERRUPTr 0x00808900 65 #define montreal2_FW_TO_SW_MESSAGEr 0x00808c00 66 #define montreal2_VS3_MISC_STATUS 0x00808400 67 #define montreal2_VS4_MISC_STATUS 0x00808500 68 #define montreal2_VS5_MISC_STATUS 0x00808600 69 #define montreal2_VS6_MISC_STATUS 0x00808700 70 #define montreal2_VS7_MISC_STATUS 0x00808800 71 72 #define montreal2_FCPORT_EXT_TX_DISABLE_CTRLr 0x02002d00 73 74 #define SCHAN_MAX_POLLS 1000 75 #define AXI_MAX_POLLS 1000 76 77 #define SBUS_CTRL_GO 0x8000 78 #define SBUS_STATUS_DONE 0x8000 79 #define SBUS_STATUS_ERR 0x4000 80 #define SBUS_STATUS_NAK 0x0100 81 82 /* Opcodes */ 83 #define SBUS_READ_MEMORY_CMD_MSG 0x07 84 #define SBUS_READ_MEMORY_ACK_MSG 0x08 85 #define SBUS_WRITE_MEMORY_CMD_MSG 0x09 86 #define SBUS_WRITE_MEMORY_ACK_MSG 0x0a 87 #define SBUS_READ_REGISTER_CMD_MSG 0x0b 88 #define SBUS_READ_REGISTER_ACK_MSG 0x0c 89 #define SBUS_WRITE_REGISTER_CMD_MSG 0x0d 90 #define SBUS_WRITE_REGISTER_ACK_MSG 0x0e 91 92 #define montreal2_CMIC_BLOCK 32 93 94 /* Additional block types */ 95 #define montreal2_BLKTYPE_AVS 0 96 #define montreal2_BLKTYPE_CMIC 1 97 #define montreal2_BLKTYPE_FCMAC 2 98 #define montreal2_BLKTYPE_LINESIDE_CL_PM 3 99 /* #define montreal2_BLKTYPE_LINE_FCPORT 4 */ 100 #define montreal2_BLKTYPE_MAPPER 5 101 #define montreal2_BLKTYPE_MDIO 6 102 #define montreal2_BLKTYPE_PSM 7 103 #define montreal2_BLKTYPE_SYSSIDE_CL_PM 8 104 /* #define montreal2_BLKTYPE_SYS_FCPORT 9 */ 105 /* #define montreal2_BLKTYPE_TOP 10 */ 106 #define montreal2_BLKTYPE_UCSS 11 107 108 /* Define blktypes with Schan / Block Numbers */ 109 #define montreal2_BLKTYPE_TOP 34 110 #define montreal2_BLKTYPE_LINE_FCPORT 3 111 #define montreal2_BLKTYPE_SYS_FCPORT 7 112 113 #define PHY8806X_C45_DEV1 0x1 114 115 /* PHY flag definitions */ 116 #define PHY8806X_FWDLM 0x1 /* firmware download master */ 117 #define PHY8806X_BMP0 0x2 /* boot master 0 */ 118 #define PHY8806X_BMP1 0x4 /* boot master 1 */ 119 #define PHY8806X_CHM 0x8 /* chip master */ 120 #define PHY8806X_PM 0x10 /* passive mode */ 121 #define PHY8806X_FLEX 0x20 /* flex reconfiguration */ 122 #define PHY8806X_AC 0x40 /* download to acc chips */ 123 #define PHY8806X_MODE_CHANGE 0x80 /* Mode change, Eth->FC or FC->Eth */ 124 #define PHY8806X_PORTMOD 0x100 /* driver called from portmod */ 125 #define PHY8806X_FW_RESTART 0x200 /* Do not re-download f/w. Restart */ 126 #define PHY8806X_ENCAP_CHANGE 0x400 /* HG->IEEE or IEEE->HG */ 127 128 #define PHY8806X_FLAGS_BMP 0x1 129 130 #define NUM_PATTERN_DATA_INTS 8 131 typedef struct phy8806x_pattern_s { 132 uint32 pattern_data[NUM_PATTERN_DATA_INTS]; 133 uint32 pattern_length; 134 } phy8806x_pattern_t; 135 136 typedef struct phy8806x_speed_config_s { 137 uint32 port_refclk_int; 138 int speed; 139 int sys_lane_count; 140 int ln_lane_count; 141 int port_is_higig; 142 int line_interface; 143 int interface; 144 int pcs_bypass; 145 int fiber_pref; /* line side */ 146 int fiber_pref_sys; /* Sys side */ 147 int pll_divider_req; 148 int an_mode; 149 int an_fec; 150 int an_cl72; 151 int fs_cl72; 152 int fs_cl72_sys; 153 int port_mode; /* Repeater or Retimer mode */ 154 int fs_fec; 155 int fs_fec_sys; 156 int is_flex; 157 int quad_mode; 158 int repeater_an_phase; /* Repeater mode AN state */ 159 int repeater_an_resolved_speed; 160 int repeater_an_retry_phase0; 161 int repeater_an_retry_phase1; 162 mac_driver_t *macd; /* Pointer to MAC */ 163 } phy8806x_speed_config_t; 164 165 /* 166 Config - per logical port 167 */ 168 typedef struct { 169 phymod_polarity_t phy_polarity_config; 170 phymod_phy_reset_t phy_reset_config; 171 phy8806x_pattern_t pattern; 172 phy8806x_speed_config_t speed_config; 173 int fiber_pref; /* spn_SERDES_FIBER_PREF */ 174 int cl73an; /* spn_PHY_AN_C73 */ 175 int an_cl72; /* spn_PHY_AN_C72 */ 176 int forced_init_cl72; /* spn_FORCED_INIT_CL72 */ 177 int hg_mode; /* higig port */ 178 int an_fec; /*enable FEC for AN mode */ 179 int sgmii_mstr; /* sgmii master mode */ 180 uint32 line_intf; /*line interface info */ 181 int flags; /* PHY flags for internal use */ 182 soc_timeout_t to; /* timer for multi pass initialization */ 183 uint8 *firmware; /* firmware pointer */ 184 int firmware_len; /* firmware length in bytes */ 185 int dl_dividend; /* divident for MDC during firmware download */ 186 int dl_divisor; /* divisor for MDC during firmware download */ 187 uint64 inbctr[512]; /* Inband Counters Buffer */ 188 uint16 pmd_size; /* PMD size */ 189 uint16 pmd_crc; /* PMD CRC */ 190 uint32 top_dev_rev_id; /* cached TOP_DEV_REV_IDr */ 191 int user_set_tx; /* this one will indicate if user set the tx or not */ 192 int led_speed; /* Speed */ 193 uint8 led_tx; /* Tx activity */ 194 uint8 led_rx; /* Rx activity */ 195 } phy8806x_config_t; 196 197 typedef enum ether_mode_e { 198 ETH_REPEATER, 199 ETH_RETIMER, 200 ETH_GEARBOX, 201 ETH_ETHERRAM 202 } ether_mode_t; 203 204 #define FLAGS(_pc) (((phy8806x_config_t *)((_pc) + 1))->flags) 205 206 #define PHY8806X_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 207 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 208 #define PHY8806X_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 209 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 210 #define PHY8806X_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 211 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 212 #define PHY8806X_REG_WB_WRITE(_unit, _phy_ctrl, _addr, _val) \ 213 WRITE_WB_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 214 215 #define READ_PHY8806X_DEV1_REG(_unit, _phy_ctrl, _reg,_val) \ 216 PHY8806X_REG_READ((_unit), (_phy_ctrl), \ 217 SOC_PHY_CLAUSE45_ADDR(PHY8806X_C45_DEV1, (_reg)), (_val)) 218 #define WRITE_PHY8806X_DEV1_REG(_unit, _phy_ctrl, _reg,_val) \ 219 PHY8806X_REG_WRITE((_unit), (_phy_ctrl), \ 220 SOC_PHY_CLAUSE45_ADDR(PHY8806X_C45_DEV1, (_reg)), (_val)) 221 #define MODIFY_PHY8806X_DEV1_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 222 PHY8806X_REG_MODIFY((_unit), (_phy_ctrl), \ 223 SOC_PHY_CLAUSE45_ADDR(PHY8806X_C45_DEV1, (_reg)), (_val), (_mask)) 224 225 /* PHY Identifier Register 0 (Addr 0002h) */ 226 #define READ_PHY8806X_DEV1_ID0r(_unit, _phy_ctrl, _val) \ 227 READ_PHY8806X_DEV1_REG((_unit), (_phy_ctrl), 0x0002,(_val)) 228 229 /* PHY Identifier Register 1 (Addr 0003h) */ 230 #define READ_PHY8806X_DEV1_ID1r(_unit, _phy_ctrl, _val) \ 231 READ_PHY8806X_DEV1_REG((_unit), (_phy_ctrl), 0x0003,(_val)) 232 233 int 234 _phy_8806x_toplvl_sbus_write(int unit,phy_ctrl_t *pc, uint32 reg, uint32 arg[], int size); 235 int 236 _phy_8806x_toplvl_sbus_read(int unit,phy_ctrl_t *pc, uint32 reg, uint32 arg[], int size); 237 int 238 _phy_8806x_write_top_soft_reset_reg(int unit, phy_ctrl_t *pc, uint32 val); 239 int 240 _phy_8806x_write_top_rts_misc_ctrl_reg(int unit, phy_ctrl_t *pc, uint32 val); 241 int 242 _phy_8806x_write_top_soft_reset_reg_2(int unit, phy_ctrl_t *pc, uint32 val); 243 244 int 245 _phy_8806x_write_top_fc_mode_control_reg(int unit, phy_ctrl_t *pc, uint32 val); 246 int 247 _phy_8806x_fcport_sbus_write(int unit,phy_ctrl_t *pc, int sys, uint32 reg, uint32 arg[], int size); 248 int 249 _phy_8806x_fcport_sbus_read(int unit,phy_ctrl_t *pc, int sys, uint32 reg, uint32 arg[], int size); 250 int 251 _phy_8806x_write_fcport_ext_tx_disable_ctrl(int unit, phy_ctrl_t *pc, int sys, uint32 val); 252 253 #define READ_TOP_DEV_REV_ID_REG(_unit, _phy_ctrl, _val) \ 254 _phy_8806x_toplvl_sbus_read((unit), (_phy_ctrl), montreal2_TOP_DEV_REV_IDr, (_val), 1) 255 256 #define READ_TOP_SOFT_RESET_REG(_unit, _phy_ctrl, _val) \ 257 _phy_8806x_toplvl_sbus_read((unit), (_phy_ctrl), montreal2_TOP_SOFT_RESET_REGr, (_val), 1) 258 259 #define WRITE_TOP_SOFT_RESET_REG(_unit, _phy_ctrl, _val) \ 260 _phy_8806x_write_top_soft_reset_reg((unit), (_phy_ctrl), (_val)) 261 262 263 #define READ_TOP_RTS_MISC_CTRL_REG(_unit, _phy_ctrl, _val) \ 264 _phy_8806x_toplvl_sbus_read((unit), (_phy_ctrl), montreal2_TOP_RTS_MISC_CTRLr, (_val), 1) 265 266 #define WRITE_TOP_RTS_MISC_CTRL_REG(_unit, _phy_ctrl, _val) \ 267 _phy_8806x_write_top_rts_misc_ctrl_reg((unit), (_phy_ctrl), (_val)) 268 269 #define READ_TOP_SOFT_RESET_REG_2(_unit, _phy_ctrl, _val) \ 270 _phy_8806x_toplvl_sbus_read((unit), (_phy_ctrl), montreal2_TOP_SOFT_RESET_REG_2r, (_val), 1) 271 272 #define WRITE_TOP_SOFT_RESET_REG_2(_unit, _phy_ctrl, _val) \ 273 _phy_8806x_write_top_soft_reset_reg_2((unit), (_phy_ctrl), (_val)) 274 275 #define READ_TOP_FC_MODE_CONTROL_REG(_unit, _phy_ctrl, _val) \ 276 _phy_8806x_toplvl_sbus_read((unit), (_phy_ctrl), montreal2_TOP_FC_MODE_CONTROLr, (_val), 1) 277 278 #define WRITE_TOP_FC_MODE_CONTROL_REG(_unit, _phy_ctrl, _val) \ 279 _phy_8806x_write_top_fc_mode_control_reg((unit), (_phy_ctrl), (_val)) 280 281 #define READ_SYS_FCPORT_EXT_TX_DISABLE_CTRL(_unit, _phy_ctrl, _val) \ 282 _phy_8806x_fcport_sbus_read((unit), (_phy_ctrl), 1, montreal2_FCPORT_EXT_TX_DISABLE_CTRLr, (_val), 1) 283 284 #define READ_LINE_FCPORT_EXT_TX_DISABLE_CTRL(_unit, _phy_ctrl, _val) \ 285 _phy_8806x_fcport_sbus_read((unit), (_phy_ctrl), 0, montreal2_FCPORT_EXT_TX_DISABLE_CTRLr, (_val), 1) 286 287 #define WRITE_SYS_FCPORT_EXT_TX_DISABLE_CTRL(_unit, _phy_ctrl, _val) \ 288 _phy_8806x_write_fcport_ext_tx_disable_ctrl((unit), (_phy_ctrl), 1, (_val)) 289 290 #define WRITE_LINE_FCPORT_EXT_TX_DISABLE_CTRL(_unit, _phy_ctrl, _val) \ 291 _phy_8806x_write_fcport_ext_tx_disable_ctrl((unit), (_phy_ctrl), 0, (_val)) 292 293 #define EXTRACT_REG(x) (((x) >> 8) & 0xffff) 294 295 #define READ_PHY8806X_MDIO_REG(_unit, _phy_ctrl, _reg,_val) \ 296 PHY8806X_REG_READ((_unit), (_phy_ctrl), \ 297 SOC_PHY_CLAUSE45_ADDR(0x1, (_reg)), (_val)) 298 #define WRITE_PHY8806X_MDIO_REG(_unit, _phy_ctrl, _reg,_val) \ 299 PHY8806X_REG_WRITE((_unit), (_phy_ctrl), \ 300 SOC_PHY_CLAUSE45_ADDR(0x1, (_reg)), (_val)) 301 #define MODIFY_PHY8806X_MDIO_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 302 PHY8806X_REG_MODIFY((_unit), (_phy_ctrl), \ 303 SOC_PHY_CLAUSE45_ADDR(0x1, (_reg)), (_val), (_mask)) 304 305 #define WRITE_PHY8806X_MDIO_REG_WB(_unit, _phy_ctrl, _reg,_val) \ 306 PHY8806X_REG_WB_WRITE((_unit), (_phy_ctrl), \ 307 SOC_PHY_CLAUSE45_ADDR(0x1, (_reg)), (_val)) 308 309 310 #define READ_PHY8806X_SBUS_STATUS_REG(_unit, _phy_ctrl, _val) \ 311 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_STATUSr), (_val)) 312 #define WRITE_PHY8806X_SBUS_STATUS_REG(_unit, _phy_ctrl, _val) \ 313 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_STATUSr), (_val)) 314 #define MODIFY_PHY8806X_SBUS_STATUS_REG(_unit, _phy_ctrl, _val, _mask) \ 315 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_STATUSr), (_val), (_mask)) 316 317 #define READ_PHY8806X_SBUS_CONTROL_REG(_unit, _phy_ctrl, _val) \ 318 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_CONTROLr), (_val)) 319 #define WRITE_PHY8806X_SBUS_CONTROL_REG(_unit, _phy_ctrl, _val) \ 320 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_CONTROLr), (_val)) 321 #define MODIFY_PHY8806X_SBUS_CONTROL_REG(_unit, _phy_ctrl, _val, _mask) \ 322 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_CONTROLr), (_val), (_mask)) 323 324 #define READ_PHY8806X_SBUS_COMMAND_UPPER_REG(_unit, _phy_ctrl, _val) \ 325 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_COMMAND_UPPERr), (_val)) 326 #define WRITE_PHY8806X_SBUS_COMMAND_UPPER_REG(_unit, _phy_ctrl, _val) \ 327 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_COMMAND_UPPERr), (_val)) 328 #define MODIFY_PHY8806X_SBUS_COMMAND_UPPER_REG(_unit, _phy_ctrl, _val, _mask) \ 329 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_COMMAND_UPPERr), (_val), (_mask)) 330 331 #define READ_PHY8806X_SBUS_COMMAND_LOWER_REG(_unit, _phy_ctrl, _val) \ 332 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_COMMAND_LOWERr), (_val)) 333 #define WRITE_PHY8806X_SBUS_COMMAND_LOWER_REG(_unit, _phy_ctrl, _val) \ 334 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_COMMAND_LOWERr), (_val)) 335 #define MODIFY_PHY8806X_SBUS_COMMAND_LOWER_REG(_unit, _phy_ctrl, _val, _mask) \ 336 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_COMMAND_LOWERr), (_val), (_mask)) 337 338 #define READ_PHY8806X_SBUS_ADDR_UPPER_REG(_unit, _phy_ctrl, _val) \ 339 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_ADDR_UPPERr), (_val)) 340 #define WRITE_PHY8806X_SBUS_ADDR_UPPER_REG(_unit, _phy_ctrl, _val) \ 341 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_ADDR_UPPERr), (_val)) 342 #define MODIFY_PHY8806X_SBUS_ADDR_UPPER_REG(_unit, _phy_ctrl, _val, _mask) \ 343 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_ADDR_UPPERr), (_val), (_mask)) 344 345 #define READ_PHY8806X_SBUS_ADDR_LOWER_REG(_unit, _phy_ctrl, _val) \ 346 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_ADDR_LOWERr), (_val)) 347 #define WRITE_PHY8806X_SBUS_ADDR_LOWER_REG(_unit, _phy_ctrl, _val) \ 348 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_ADDR_LOWERr), (_val)) 349 #define MODIFY_PHY8806X_SBUS_ADDR_LOWER_REG(_unit, _phy_ctrl, _val, _mask) \ 350 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_ADDR_LOWERr), (_val), (_mask)) 351 352 #define READ_PHY8806X_AXI_CONTROL_F0_REG(_unit, _phy_ctrl, _val) \ 353 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F0r), (_val)) 354 #define WRITE_PHY8806X_AXI_CONTROL_F0_REG(_unit, _phy_ctrl, _val) \ 355 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F0r), (_val)) 356 #define MODIFY_PHY8806X_AXI_CONTROL_F0_REG(_unit, _phy_ctrl, _val, _mask) \ 357 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F0r), (_val), (_mask)) 358 359 #define READ_PHY8806X_AXI_CONTROL_F1_REG(_unit, _phy_ctrl, _val) \ 360 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F1r), (_val)) 361 #define WRITE_PHY8806X_AXI_CONTROL_F1_REG(_unit, _phy_ctrl, _val) \ 362 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F1r), (_val)) 363 #define MODIFY_PHY8806X_AXI_CONTROL_F1_REG(_unit, _phy_ctrl, _val, _mask) \ 364 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F1r), (_val), (_mask)) 365 366 #define READ_PHY8806X_AXI_STATUS_F0_REG(_unit, _phy_ctrl, _val) \ 367 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F0r), (_val)) 368 #define WRITE_PHY8806X_AXI_STATUS_F0_REG(_unit, _phy_ctrl, _val) \ 369 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F0r), (_val)) 370 #define MODIFY_PHY8806X_AXI_STATUS_F0_REG(_unit, _phy_ctrl, _val, _mask) \ 371 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F0r), (_val), (_mask)) 372 373 #define READ_PHY8806X_AXI_STATUS_F1_REG(_unit, _phy_ctrl, _val) \ 374 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F1r), (_val)) 375 #define WRITE_PHY8806X_AXI_STATUS_F1_REG(_unit, _phy_ctrl, _val) \ 376 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F1r), (_val)) 377 #define MODIFY_PHY8806X_AXI_STATUS_F1_REG(_unit, _phy_ctrl, _val, _mask) \ 378 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F1r), (_val), (_mask)) 379 380 #define READ_PHY8806X_MISC_CONTROL_REG(_unit, _phy_ctrl, _val) \ 381 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_MISC_CONTROLr), (_val)) 382 #define WRITE_PHY8806X_MISC_CONTROL_REG(_unit, _phy_ctrl, _val) \ 383 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_MISC_CONTROLr), (_val)) 384 #define MODIFY_PHY8806X_MISC_CONTROL_REG(_unit, _phy_ctrl, _val, _mask) \ 385 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_MISC_CONTROLr), (_val), (_mask)) 386 387 388 #define READ_PHY8806X_AXI_ADDR_LOWER_F0_REG(_unit, _phy_ctrl, _val) \ 389 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F0r), (_val)) 390 #define WRITE_PHY8806X_AXI_ADDR_LOWER_F0_REG(_unit, _phy_ctrl, _val) \ 391 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F0r), (_val)) 392 #define MODIFY_PHY8806X_AXI_ADDR_LOWER_F0_REG(_unit, _phy_ctrl, _val, _mask) \ 393 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F0r), (_val), (_mask)) 394 395 #define READ_PHY8806X_AXI_ADDR_LOWER_F1_REG(_unit, _phy_ctrl, _val) \ 396 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F1r), (_val)) 397 #define WRITE_PHY8806X_AXI_ADDR_LOWER_F1_REG(_unit, _phy_ctrl, _val) \ 398 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F1r), (_val)) 399 #define MODIFY_PHY8806X_AXI_ADDR_LOWER_F1_REG(_unit, _phy_ctrl, _val, _mask) \ 400 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F1r), (_val), (_mask)) 401 402 #define READ_PHY8806X_AXI_ADDR_UPPER_F0_REG(_unit, _phy_ctrl, _val) \ 403 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F0r), (_val)) 404 #define WRITE_PHY8806X_AXI_ADDR_UPPER_F0_REG(_unit, _phy_ctrl, _val) \ 405 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F0r), (_val)) 406 #define MODIFY_PHY8806X_AXI_ADDR_UPPER_F0_REG(_unit, _phy_ctrl, _val, _mask) \ 407 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F0r), (_val), (_mask)) 408 409 #define READ_PHY8806X_AXI_ADDR_UPPER_F1_REG(_unit, _phy_ctrl, _val) \ 410 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F1r), (_val)) 411 #define WRITE_PHY8806X_AXI_ADDR_UPPER_F1_REG(_unit, _phy_ctrl, _val) \ 412 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F1r), (_val)) 413 #define MODIFY_PHY8806X_AXI_ADDR_UPPER_F1_REG(_unit, _phy_ctrl, _val, _mask) \ 414 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F1r), (_val), (_mask)) 415 416 417 #define READ_PHY8806X_SBUS_DATA_BYTES_1_0_REG(_unit, _phy_ctrl, _val) \ 418 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_1_0r), (_val)) 419 #define WRITE_PHY8806X_SBUS_DATA_BYTES_1_0_REG(_unit, _phy_ctrl, _val) \ 420 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_1_0r), (_val)) 421 #define MODIFY_PHY8806X_SBUS_DATA_BYTES_1_0_REG(_unit, _phy_ctrl, _val, _mask) \ 422 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_1_0r), (_val), (_mask)) 423 424 425 #define READ_PHY8806X_SBUS_DATA_BYTES_3_2_REG(_unit, _phy_ctrl, _val) \ 426 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_3_2r), (_val)) 427 #define WRITE_PHY8806X_SBUS_DATA_BYTES_3_2_REG(_unit, _phy_ctrl, _val) \ 428 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_3_2r), (_val)) 429 #define MODIFY_PHY8806X_SBUS_DATA_BYTES_3_2_REG(_unit, _phy_ctrl, _val, _mask) \ 430 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_3_2r), (_val), (_mask)) 431 432 #define READ_PHY8806X_SBUS_DATA_BYTES_5_4_REG(_unit, _phy_ctrl, _val) \ 433 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_5_4r), (_val)) 434 #define WRITE_PHY8806X_SBUS_DATA_BYTES_5_4_REG(_unit, _phy_ctrl, _val) \ 435 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_5_4r), (_val)) 436 #define MODIFY_PHY8806X_SBUS_DATA_BYTES_5_4_REG(_unit, _phy_ctrl, _val, _mask) \ 437 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_5_4r), (_val), (_mask)) 438 439 #define READ_PHY8806X_SBUS_DATA_BYTES_7_6_REG(_unit, _phy_ctrl, _val) \ 440 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_7_6r), (_val)) 441 #define WRITE_PHY8806X_SBUS_DATA_BYTES_7_6_REG(_unit, _phy_ctrl, _val) \ 442 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_7_6r), (_val)) 443 #define MODIFY_PHY8806X_SBUS_DATA_BYTES_7_6_REG(_unit, _phy_ctrl, _val, _mask) \ 444 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_7_6r), (_val), (_mask)) 445 446 #define READ_PHY8806X_SBUS_DATA_BYTES_9_8_REG(_unit, _phy_ctrl, _val) \ 447 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_9_8r), (_val)) 448 #define WRITE_PHY8806X_SBUS_DATA_BYTES_9_8_REG(_unit, _phy_ctrl, _val) \ 449 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_9_8r), (_val)) 450 #define MODIFY_PHY8806X_SBUS_DATA_BYTES_9_8_REG(_unit, _phy_ctrl, _val, _mask) \ 451 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_9_8r), (_val), (_mask)) 452 453 #define READ_PHY8806X_SBUS_DATA_BYTES_11_10_REG(_unit, _phy_ctrl, _val) \ 454 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_11_10r), (_val)) 455 #define WRITE_PHY8806X_SBUS_DATA_BYTES_11_10_REG(_unit, _phy_ctrl, _val) \ 456 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_11_10r), (_val)) 457 #define MODIFY_PHY8806X_SBUS_DATA_BYTES_11_10_REG(_unit, _phy_ctrl, _val, _mask) \ 458 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_11_10r), (_val), (_mask)) 459 460 #define READ_PHY8806X_SBUS_DATA_BYTES_13_12_REG(_unit, _phy_ctrl, _val) \ 461 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_13_12r), (_val)) 462 #define WRITE_PHY8806X_SBUS_DATA_BYTES_13_12_REG(_unit, _phy_ctrl, _val) \ 463 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_13_12r), (_val)) 464 #define MODIFY_PHY8806X_SBUS_DATA_BYTES_13_12_REG(_unit, _phy_ctrl, _val, _mask) \ 465 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_13_12r), (_val), (_mask)) 466 467 #define READ_PHY8806X_SBUS_DATA_BYTES_15_14_REG(_unit, _phy_ctrl, _val) \ 468 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_15_14r), (_val)) 469 #define WRITE_PHY8806X_SBUS_DATA_BYTES_15_14_REG(_unit, _phy_ctrl, _val) \ 470 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_15_14r), (_val)) 471 #define MODIFY_PHY8806X_SBUS_DATA_BYTES_15_14_REG(_unit, _phy_ctrl, _val, _mask) \ 472 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SBUS_DATA_BYTES_15_14r), (_val), (_mask)) 473 474 475 #define READ_PHY8806X_AXI_DATA_BYTES_1_0_F0_REG(_unit, _phy_ctrl, _val) \ 476 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F0r), (_val)) 477 #define WRITE_PHY8806X_AXI_DATA_BYTES_1_0_F0_REG(_unit, _phy_ctrl, _val) \ 478 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F0r), (_val)) 479 #define MODIFY_PHY8806X_AXI_DATA_BYTES_1_0_F0_REG(_unit, _phy_ctrl, _val, _mask) \ 480 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F0r), (_val), (_mask)) 481 482 483 #define READ_PHY8806X_AXI_DATA_BYTES_3_2_F0_REG(_unit, _phy_ctrl, _val) \ 484 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F0r), (_val)) 485 #define WRITE_PHY8806X_AXI_DATA_BYTES_3_2_F0_REG(_unit, _phy_ctrl, _val) \ 486 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F0r), (_val)) 487 #define MODIFY_PHY8806X_AXI_DATA_BYTES_3_2_F0_REG(_unit, _phy_ctrl, _val, _mask) \ 488 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F0r), (_val), (_mask)) 489 490 #define READ_PHY8806X_AXI_DATA_BYTES_5_4_F0_REG(_unit, _phy_ctrl, _val) \ 491 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F0r), (_val)) 492 #define WRITE_PHY8806X_AXI_DATA_BYTES_5_4_F0_REG(_unit, _phy_ctrl, _val) \ 493 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F0r), (_val)) 494 #define MODIFY_PHY8806X_AXI_DATA_BYTES_5_4_F0_REG(_unit, _phy_ctrl, _val, _mask) \ 495 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F0r), (_val), (_mask)) 496 497 #define READ_PHY8806X_AXI_DATA_BYTES_7_6_F0_REG(_unit, _phy_ctrl, _val) \ 498 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F0r), (_val)) 499 #define WRITE_PHY8806X_AXI_DATA_BYTES_7_6_F0_REG(_unit, _phy_ctrl, _val) \ 500 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F0r), (_val)) 501 #define MODIFY_PHY8806X_AXI_DATA_BYTES_7_6_F0_REG(_unit, _phy_ctrl, _val, _mask) \ 502 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F0r), (_val), (_mask)) 503 504 505 #define READ_PHY8806X_AXI_DATA_BYTES_1_0_F1_REG(_unit, _phy_ctrl, _val) \ 506 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F1r), (_val)) 507 #define WRITE_PHY8806X_AXI_DATA_BYTES_1_0_F1_REG(_unit, _phy_ctrl, _val) \ 508 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F1r), (_val)) 509 #define MODIFY_PHY8806X_AXI_DATA_BYTES_1_0_F1_REG(_unit, _phy_ctrl, _val, _mask) \ 510 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F1r), (_val), (_mask)) 511 512 513 #define READ_PHY8806X_AXI_DATA_BYTES_3_2_F1_REG(_unit, _phy_ctrl, _val) \ 514 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F1r), (_val)) 515 #define WRITE_PHY8806X_AXI_DATA_BYTES_3_2_F1_REG(_unit, _phy_ctrl, _val) \ 516 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F1r), (_val)) 517 #define MODIFY_PHY8806X_AXI_DATA_BYTES_3_2_F1_REG(_unit, _phy_ctrl, _val, _mask) \ 518 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F1r), (_val), (_mask)) 519 520 #define READ_PHY8806X_AXI_DATA_BYTES_5_4_F1_REG(_unit, _phy_ctrl, _val) \ 521 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F1r), (_val)) 522 #define WRITE_PHY8806X_AXI_DATA_BYTES_5_4_F1_REG(_unit, _phy_ctrl, _val) \ 523 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F1r), (_val)) 524 #define MODIFY_PHY8806X_AXI_DATA_BYTES_5_4_F1_REG(_unit, _phy_ctrl, _val, _mask) \ 525 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F1r), (_val), (_mask)) 526 527 #define READ_PHY8806X_AXI_DATA_BYTES_7_6_F1_REG(_unit, _phy_ctrl, _val) \ 528 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F1r), (_val)) 529 #define WRITE_PHY8806X_AXI_DATA_BYTES_7_6_F1_REG(_unit, _phy_ctrl, _val) \ 530 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F1r), (_val)) 531 #define MODIFY_PHY8806X_AXI_DATA_BYTES_7_6_F1_REG(_unit, _phy_ctrl, _val, _mask) \ 532 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F1r), (_val), (_mask)) 533 534 535 536 #define AXI_DELTA (EXTRACT_REG(montreal2_AXI_CONTROL_F1r) - EXTRACT_REG(montreal2_AXI_CONTROL_F0r)) 537 538 539 #define READ_PHY8806X_AXI_ADDR_LOWER_FX_REG(_unit, _phy_ctrl, _val) \ 540 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 541 #define WRITE_PHY8806X_AXI_ADDR_LOWER_FX_REG(_unit, _phy_ctrl, _val) \ 542 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 543 #define MODIFY_PHY8806X_AXI_ADDR_LOWER_FX_REG(_unit, _phy_ctrl, _val, _mask) \ 544 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_LOWER_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val), (_mask)) 545 546 #define READ_PHY8806X_AXI_ADDR_UPPER_FX_REG(_unit, _phy_ctrl, _val) \ 547 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 548 #define WRITE_PHY8806X_AXI_ADDR_UPPER_FX_REG(_unit, _phy_ctrl, _val) \ 549 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 550 #define MODIFY_PHY8806X_AXI_ADDR_UPPER_FX_REG(_unit, _phy_ctrl, _val, _mask) \ 551 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_ADDR_UPPER_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val), (_mask)) 552 553 554 #define READ_PHY8806X_AXI_CONTROL_FX_REG(_unit, _phy_ctrl, _val) \ 555 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 556 #define WRITE_PHY8806X_AXI_CONTROL_FX_REG(_unit, _phy_ctrl, _val) \ 557 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 558 #define MODIFY_PHY8806X_AXI_CONTROL_FX_REG(_unit, _phy_ctrl, _val, _mask) \ 559 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_CONTROL_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val), (_mask)) 560 561 #define READ_PHY8806X_AXI_STATUS_FX_REG(_unit, _phy_ctrl, _val) \ 562 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 563 #define WRITE_PHY8806X_AXI_STATUS_FX_REG(_unit, _phy_ctrl, _val) \ 564 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 565 #define MODIFY_PHY8806X_AXI_STATUS_FX_REG(_unit, _phy_ctrl, _val, _mask) \ 566 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_STATUS_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val), (_mask)) 567 568 569 #define READ_PHY8806X_AXI_DATA_BYTES_1_0_FX_REG(_unit, _phy_ctrl, _val) \ 570 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 571 #define WRITE_PHY8806X_AXI_DATA_BYTES_1_0_FX_REG(_unit, _phy_ctrl, _val) \ 572 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 573 #define MODIFY_PHY8806X_AXI_DATA_BYTES_1_0_FX_REG(_unit, _phy_ctrl, _val, _mask) \ 574 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_1_0_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val), (_mask)) 575 576 577 #define READ_PHY8806X_AXI_DATA_BYTES_3_2_FX_REG(_unit, _phy_ctrl, _val) \ 578 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 579 #define WRITE_PHY8806X_AXI_DATA_BYTES_3_2_FX_REG(_unit, _phy_ctrl, _val) \ 580 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 581 #define MODIFY_PHY8806X_AXI_DATA_BYTES_3_2_FX_REG(_unit, _phy_ctrl, _val, _mask) \ 582 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_3_2_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val), (_mask)) 583 584 #define READ_PHY8806X_AXI_DATA_BYTES_5_4_FX_REG(_unit, _phy_ctrl, _val) \ 585 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 586 #define WRITE_PHY8806X_AXI_DATA_BYTES_5_4_FX_REG(_unit, _phy_ctrl, _val) \ 587 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 588 #define MODIFY_PHY8806X_AXI_DATA_BYTES_5_4_FX_REG(_unit, _phy_ctrl, _val, _mask) \ 589 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_5_4_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val), (_mask)) 590 591 #define READ_PHY8806X_AXI_DATA_BYTES_7_6_FX_REG(_unit, _phy_ctrl, _val) \ 592 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 593 #define WRITE_PHY8806X_AXI_DATA_BYTES_7_6_FX_REG(_unit, _phy_ctrl, _val) \ 594 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val)) 595 #define MODIFY_PHY8806X_AXI_DATA_BYTES_7_6_FX_REG(_unit, _phy_ctrl, _val, _mask) \ 596 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_AXI_DATA_BYTES_7_6_F0r) + (((_phy_ctrl)->phy_id & 0x4) ? AXI_DELTA : 0), (_val), (_mask)) 597 598 599 600 #define READ_PHY8806X_SW_TO_FW_INTERRUPT_REG(_unit, _phy_ctrl, _val) \ 601 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SW_TO_FW_INTERRUPTr), (_val)) 602 #define WRITE_PHY8806X_SW_TO_FW_INTERRUPT_REG(_unit, _phy_ctrl, _val) \ 603 WRITE_PHY8806X_MDIO_REG_WB((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SW_TO_FW_INTERRUPTr), (_val)) 604 #define MODIFY_PHY8806X_SW_TO_FW_INTERRUPT_REG(_unit, _phy_ctrl, _val, _mask) \ 605 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_SW_TO_FW_INTERRUPTr), (_val), (_mask)) 606 607 #define READ_PHY8806X_FW_TO_SW_MESSAGE_REG(_unit, _phy_ctrl, _val) \ 608 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_FW_TO_SW_MESSAGEr), (_val)) 609 #define WRITE_PHY8806X_FW_TO_SW_MESSAGE_REG(_unit, _phy_ctrl, _val) \ 610 WRITE_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_FW_TO_SW_MESSAGEr), (_val)) 611 #define MODIFY_PHY8806X_FW_TO_SW_MESSAGE_REG(_unit, _phy_ctrl, _val, _mask) \ 612 MODIFY_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_FW_TO_SW_MESSAGEr), (_val), (_mask)) 613 #define READ_PHY8806X_VS5_MISC_STATUS_REG(_unit, _phy_ctrl, _val) \ 614 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_VS5_MISC_STATUS), (_val)) 615 #define READ_LINK_STATUS_REG READ_PHY8806X_VS5_MISC_STATUS_REG 616 #define VS_MISC_STATUS_LL_STATUS_BIT_MASK 0x8 617 #define VS_MISC_STATUS_LIVE_STATUS_BIT_MASK 0x4 618 #define VS_MISC_STATUS_STATUS_BIT_MASK 0x1 619 620 #define READ_PHY8806X_VS6_MISC_STATUS_REG(_unit, _phy_ctrl, _val) \ 621 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_VS6_MISC_STATUS), (_val)) 622 #define READ_FC_LINK_STATUS_REG READ_PHY8806X_VS6_MISC_STATUS_REG 623 624 #define READ_PHY8806X_VS7_MISC_STATUS_REG(_unit, _phy_ctrl, _val) \ 625 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_VS7_MISC_STATUS), (_val)) 626 #define READ_FC_LINK_FAULT_REG READ_PHY8806X_VS7_MISC_STATUS_REG 627 628 #define READ_PHY8806X_VS3_MISC_STATUS_REG(_unit, _phy_ctrl, _val) \ 629 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_VS3_MISC_STATUS), (_val)) 630 #define READ_ETH_LOCAL_FAULT_REG READ_PHY8806X_VS3_MISC_STATUS_REG 631 632 #define READ_PHY8806X_VS4_MISC_STATUS_REG(_unit, _phy_ctrl, _val) \ 633 READ_PHY8806X_MDIO_REG((_unit), (_phy_ctrl), EXTRACT_REG(montreal2_VS4_MISC_STATUS), (_val)) 634 #define READ_ETH_REMOTE_FAULT_REG READ_PHY8806X_VS4_MISC_STATUS_REG 635 636 /* 13 bit Error code - field width in xmod status for 637 Error code from Firmware to sdk 638 */ 639 #define BFCMAP_ERROR_CODE_MASK 0x1FFF 640 641 #endif /* _PHY8806X_H_ */ 642 643