phy8750.h (12628B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8750.h 8 */ 9 10 #ifndef _PHY8750_H_ 11 #define _PHY8750_H_ 12 13 #include <soc/phy.h> 14 15 16 /* 8750 Devices */ 17 #define PHY8750_C45_DEV_PMA_PMD 0x01 18 #define PHY8750_C45_DEV_PCS 0x03 19 #define PHY8750_C45_DEV_AN 0x07 20 21 #define PHY8750_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 22 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 23 #define PHY8750_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 24 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 25 #define PHY8750_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 26 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 27 28 #define PHY8750_XFI(_unit, _phy_ctrl) \ 29 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 30 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, (0xffff)), 1) 31 32 #define PHY8750_MMF(_unit, _phy_ctrl) \ 33 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 34 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, (0xffff)), 0) 35 36 /* 37 * Line side 38 */ 39 /* PMA/PMD Device (Dev Addr 1) */ 40 #define READ_PHY8750_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 41 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 42 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, (_reg)), (_val)) 43 #define WRITE_PHY8750_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 44 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 45 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, (_reg)), (_val)) 46 #define MODIFY_PHY8750_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 47 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 48 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask)) 49 50 /* PCS Device (Dev Addr 3) */ 51 #define READ_PHY8750_MMF_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 52 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 53 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val)) 54 #define WRITE_PHY8750_MMF_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 55 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 56 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val)) 57 #define MODIFY_PHY8750_MMF_PCS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 58 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 59 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val), (_mask)) 60 61 /* AN Device (Dev Addr 7) */ 62 #define READ_PHY8750_MMF_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 63 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 64 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_AN, (_reg)), (_val)) 65 #define WRITE_PHY8750_MMF_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 66 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 67 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_AN, (_reg)), (_val)) 68 #define MODIFY_PHY8750_MMF_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 69 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 70 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_AN, (_reg)), (_val), (_mask)) 71 72 73 /* 74 * XFI Side 75 */ 76 /* PMA Device (Dev Addr 1) */ 77 #define READ_PHY8750_XFI_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 78 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 79 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, (_reg)), (_val)) \ 80 81 #define WRITE_PHY8750_XFI_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 82 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 83 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, (_reg)), (_val)) \ 84 85 #define MODIFY_PHY8750_XFI_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 86 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 87 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask))\ 88 89 /* PCS Device (Dev Addr 3) */ 90 #define READ_PHY8750_XFI_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 91 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 92 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val)) \ 93 94 #define WRITE_PHY8750_XFI_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 95 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 96 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val)) \ 97 98 #define MODIFY_PHY8750_XFI_PCS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 99 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 100 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val), (_mask))\ 101 102 103 /* AN Device (Dev Addr 1) */ 104 #define READ_PHY8750_XFI_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 105 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 106 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_AN, (_reg)), (_val)) \ 107 108 #define WRITE_PHY8750_XFI_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 109 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 110 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_AN, (_reg)), (_val)) \ 111 112 #define MODIFY_PHY8750_XFI_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 113 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 114 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_AN, (_reg)), (_val), (_mask))\ 115 116 117 118 /* PMA/PMD registers */ 119 #define PHY8750_PMAD_CTRL_REG 0x00 120 #define PHY8750_PMAD_STAT_REG 0x01 121 #define PHY8750_PMAD_ID0_REG 0x02 122 #define PHY8750_PMAD_ID1_REG 0x03 123 #define PHY8750_PMAD_CTRL2_REG 0x07 124 #define PHY8750_PMAD_STAT2_REG 0x08 125 126 #define PHY8750_SPEED_LINK_DETECT_STAT_REG 0xc820 127 #define PHY8750_PMAD_SPA_CTRL_REG 0xC848 128 #define PHY8750_PMAD_RX_ALARM_STAT_REG 0x9003 129 #define PHY8750_PMAD_M8051_MSGIN_REG 0xCA12 130 #define PHY8750_PMAD_M8051_MSGOUT_REG 0xCA13 131 132 /* Optical Configuration Register */ 133 #define PHY8750_PMAD_OPTICAL_CFG_REG 0xc8e4 134 #define PHY8750_RXLOS_OVERRIDE_MASK 0xc0c0 135 #define PHY8750_MOD_ABS_OVERRIDE_MASK 0x0808 136 137 /* Optical signal active level configuration */ 138 #define PHY8750_PMAD_OPTICAL_SIG_LVL_REG 0xc800 139 #define PHY8750_RXLOS_LVL_MASK (1 << 9) 140 #define PHY8750_MOD_ABS_LVL_MASK (1 << 8) 141 142 /* PCS registers */ 143 #define PHY8750_PCS_CTRL_REG 0x00 144 #define PHY8750_PCS_STAT_REG 0x01 145 #define PHY8750_PCS_ID0_REG 0x02 146 #define PHY8750_PCS_ID1_REG 0x03 147 #define PHY8750_PCS_CTRL2_REG 0x07 148 #define PHY8750_PCS_STAT2_REG 0x08 149 150 /* AN Registers */ 151 #define PHY8750_AN_CTRL_REG 0xffe0 152 #define PHY8750_AN_STAT_REG 0xffe1 153 154 155 /* PMA/PMD Standard registers definations */ 156 /* Control Register */ 157 #define PHY8750_MII_CTRL_PMA_LOOPBACK (1 << 0) 158 159 /* PMA/PMD User define registers definations */ 160 /* Speed Link Detect status register definations */ 161 #define PHY8750_1G_MODE 0x0021 162 163 164 /* AN registers definations */ 165 /* AN Status Register definations */ 166 #define PHY8750_AN_STAT_LA 0x0004 167 168 169 170 /* Chip ID register */ 171 #define READ_PHY8750_PMA_PMD_CHIPIDr(_unit, _phy_ctrl, _val) \ 172 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 173 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 0xc802), (_val)) 174 175 /* Chip Revision register */ 176 #define READ_PHY8750_PMA_PMD_CHIPREVr(_unit, _phy_ctrl, _val) \ 177 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 178 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 0xc801), (_val)) 179 180 /* Control Register (Addr 0000h) */ 181 #define READ_PHY8750_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 182 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 183 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 0), (_val)) 184 #define WRITE_PHY8750_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 185 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 186 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 0), (_val)) 187 #define MODIFY_PHY8750_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 188 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 189 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 0), (_val), (_mask)) 190 191 /* Status Register (Addr 0001h) */ 192 #define READ_PHY8750_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 193 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 194 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 1), (_val)) 195 #define WRITE_PHY8750_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 196 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 197 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 1), (_val)) 198 #define MODIFY_PHY8750_PMA_PMD_STATr(_unit, _phy_ctrl, _val, _mask) \ 199 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 200 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 1), (_val), (_mask)) 201 202 /* ID0 Register (Addr 0002h) */ 203 /* ID1 Register (Addr 0003h) */ 204 /* Speed Ability Register (Addr 0004h) */ 205 /* Devices in Package 1 Register (Addr 0005h) */ 206 /* Devices in Package 2 Register (Addr 0006h) */ 207 /* Control 2 Register (Addr 0007h) */ 208 209 #define PHY8750_PMAD_CTRL2r_PMA_TYPE_MASK 0xF 210 #define PHY8750_PMAD_CTRL2r_PMA_TYPE_1G_KX 0xD 211 #define PHY8750_PMAD_CTRL2r_PMA_TYPE_10G_KR 0xB 212 #define PHY8750_PMAD_CTRL2r_PMA_TYPE_10G_LRM 0x8 213 214 /* Status 2 Register (Addr 0008h) */ 215 216 /* Transmit Disable Register (Addr 0009h) */ 217 #define READ_PHY8750_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 218 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 219 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 9), (_val)) 220 #define WRITE_PHY8750_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 221 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 222 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 9), (_val)) 223 #define MODIFY_PHY8750_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 224 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 225 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PMA_PMD, 9), (_val), (_mask)) 226 227 228 /* Receive Signal Detect Register (Addr 000Ah) */ 229 /* Organizationlly Unique Identifier 0 Register (Addr 000Eh) */ 230 /* Organizationlly Unique Identifier 1 Register (Addr 000Fh) */ 231 232 /* PCS Device (Dev Addr 3) */ 233 #define READ_PHY8750_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 234 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 235 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val)) 236 #define WRITE_PHY8750_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 237 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 238 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val)) 239 #define MODIFY_PHY8750_PCS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 240 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 241 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, (_reg)), (_val), (_mask)) 242 243 /* Control 1 Register (Addr 0000h) */ 244 #define READ_PHY8750_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 245 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 246 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, 0), (_val)) 247 #define WRITE_PHY8750_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 248 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 249 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, 0), (_val)) 250 #define MODIFY_PHY8750_PCS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 251 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 252 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, 0), (_val), (_mask)) 253 254 /* Status 1 Register (Addr 0001h) */ 255 #define READ_PHY8750_PCS_STATr(_unit, _phy_ctrl, _val) \ 256 PHY8750_REG_READ((_unit), (_phy_ctrl), \ 257 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, 1), (_val)) 258 #define WRITE_PHY8750_PCS_STATr(_unit, _phy_ctrl, _val) \ 259 PHY8750_REG_WRITE((_unit), (_phy_ctrl), \ 260 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, 1), (_val)) 261 #define MODIFY_PHY8750_PCS_STATr(_unit, _phy_ctrl, _val, _mask) \ 262 PHY8750_REG_MODIFY((_unit), (_phy_ctrl), \ 263 SOC_PHY_CLAUSE45_ADDR(PHY8750_C45_DEV_PCS, 1), (_val), (_mask)) 264 265 /* autoneg control register */ 266 #define PHY8750_AN_EXT_NXT_PAGE (1 << 13) 267 #define PHY8750_AN_ENABLE (1 << 12) 268 #define PHY8750_AN_RESTART (1 << 9) 269 270 /* autoneg status register */ 271 #define PHY8750_AN_STATUS_REG 1 272 #define PHY8750_AN_LINK (1 << 2) 273 #define PHY8750_AN_DONE (1 << 5) 274 275 /* 1G status register for both autoneg mode and forced mode */ 276 #define AN_1G_STATUS_REG 0x8304 277 #define AN_1G_LINKUP 0x2 278 #define AN_1G_LINK_CHANGE 0x80 279 280 #endif /* _phy8750_H_ */