phy8706.h (20302B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8706.h 8 */ 9 10 #ifndef _PHY8706_H_ 11 #define _PHY8706_H_ 12 13 #include <soc/phy.h> 14 15 #define MII_CTRL_PMA_LOOPBACK (1 << 0) 16 17 #define PHY8706_C45_DEV_PMA_PMD 0x01 18 #define PHY8706_C45_DEV_PCS 0x03 19 #define PHY8706_C45_DEV_PHYXS 0x04 20 #define PHY8706_C45_DEV_DTEXS 0x05 21 #define PHY8706_C45_DEV_AN 0x07 22 23 #define PHY8706_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 24 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 25 #define PHY8706_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 26 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 27 #define PHY8706_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 28 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 29 30 /* PMA/PMD Device (Dev Addr 1) */ 31 32 #define READ_PHY8706_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 33 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 34 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, (_reg)), (_val)) 35 #define WRITE_PHY8706_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 36 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 37 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, (_reg)), (_val)) 38 #define MODIFY_PHY8706_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 39 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 40 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask)) 41 42 /* Control Register (Addr 0000h) */ 43 #define READ_PHY8706_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 44 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 45 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0), (_val)) 46 #define WRITE_PHY8706_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 47 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 48 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0), (_val)) 49 #define MODIFY_PHY8706_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 50 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 51 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0), (_val), (_mask)) 52 53 /* Status Register (Addr 0001h) */ 54 #define READ_PHY8706_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 55 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 56 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 1), (_val)) 57 #define WRITE_PHY8706_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 58 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 59 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 1), (_val)) 60 #define MODIFY_PHY8706_PMA_PMD_STATr(_unit, _phy_ctrl, _val, _mask) \ 61 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 62 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 1), (_val), (_mask)) 63 64 /* ID0 Register (Addr 0002h) */ 65 /* ID1 Register (Addr 0003h) */ 66 /* Speed Ability Register (Addr 0004h) */ 67 /* Devices in Package 1 Register (Addr 0005h) */ 68 /* Devices in Package 2 Register (Addr 0006h) */ 69 /* Control 2 Register (Addr 0007h) */ 70 71 #define PMAD_CTRL2_REG 7 72 #define PMAD_CTRL2r_PMA_TYPE_MASK 0xF 73 #define PMAD_CTRL2r_PMA_TYPE_1G_KX 0xD 74 #define PMAD_CTRL2r_PMA_TYPE_10G_KR 0xB 75 #define PMAD_CTRL2r_PMA_TYPE_10G_LRM 0x8 76 77 /* Status 2 Register (Addr 0008h) */ 78 79 /* Transmit Disable Register (Addr 0009h) */ 80 #define READ_PHY8706_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 81 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 82 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 9), (_val)) 83 #define WRITE_PHY8706_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 84 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 85 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 9), (_val)) 86 #define MODIFY_PHY8706_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 87 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 88 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 9), (_val), (_mask)) 89 90 91 /* Receive Signal Detect Register (Addr 000Ah) */ 92 /* Organizationlly Unique Identifier 0 Register (Addr 000Eh) */ 93 /* Organizationlly Unique Identifier 1 Register (Addr 000Fh) */ 94 95 /* PCS Device (Dev Addr 3) */ 96 97 #define READ_PHY8706_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 98 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 99 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, (_reg)), (_val)) 100 #define WRITE_PHY8706_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 101 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 102 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, (_reg)), (_val)) 103 #define MODIFY_PHY8706_PCS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 104 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 105 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, (_reg)), (_val), (_mask)) 106 107 /* Control 1 Register (Addr 0000h) */ 108 #define READ_PHY8706_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 109 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 110 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, 0), (_val)) 111 #define WRITE_PHY8706_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 112 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 113 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, 0), (_val)) 114 #define MODIFY_PHY8706_PCS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 115 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 116 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, 0), (_val), (_mask)) 117 118 /* Status 1 Register (Addr 0001h) */ 119 #define READ_PHY8706_PCS_STATr(_unit, _phy_ctrl, _val) \ 120 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 121 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, 1), (_val)) 122 #define WRITE_PHY8706_PCS_STATr(_unit, _phy_ctrl, _val) \ 123 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 124 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, 1), (_val)) 125 #define MODIFY_PHY8706_PCS_STATr(_unit, _phy_ctrl, _val, _mask) \ 126 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 127 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PCS, 1), (_val), (_mask)) 128 129 /* PCS Identifier 0 Register (Addr 0002h) */ 130 131 /* PCS Identifier 1 Register (Addr 0003h) */ 132 133 /* Speed Ability (Addr 0004h) */ 134 135 /* Devices in Package 1 (Addr 0005h) */ 136 137 /* Devices in Package 2 (Addr 0006h) */ 138 139 /* PCS Control 2 Register (Addr 0007h) */ 140 141 /* PCS Status 2 Register (Addr 0008h) */ 142 143 /* Organizationally Unique Identifier 0 Register (Addr 000eh) */ 144 /* Organizationally Unique Identifier 1 Register (Addr 000fh) */ 145 /* 10GBASE-X PCS Status Register (Addr 0x0018h) */ 146 /* 10GBASE-R PCS Status Register (Addr 0x0020h) */ 147 /* 10GBASE-R PCS Status 2 Register (Addr 0x0021h) */ 148 /* 10GBASE-R PCS Jitter Test Seed A0 Register (Addr 0x0022h) */ 149 /* 10GBASE-R PCS Jitter Test Seed A1 Register (Addr 0x0023h) */ 150 /* 10GBASE-R PCS Jitter Test Seed A2 Register (Addr 0x0024h) */ 151 /* 10GBASE-R PCS Jitter Test Seed A3 Register (Addr 0x0025h) */ 152 /* 10GBASE-R PCS Jitter Test Seed B0 Register (Addr 0x0026h) */ 153 /* 10GBASE-R PCS Jitter Test Seed B1 Register (Addr 0x0027h) */ 154 /* 10GBASE-R PCS Jitter Test Seed B2 Register (Addr 0x0028h) */ 155 /* 10GBASE-R PCS Jitter Test Seed B3 Register (Addr 0x0029h) */ 156 /* 10GBASE-R PCS Jitter Test Control Register (Addr 0x002ah) */ 157 /* 10GBASE-R PCS Jitter Test Error Counter Register (Addr 0x002Bh) */ 158 /* PRBS23 WIN_2 Register (Addr = 0xc92dh) */ 159 160 /****************************/ 161 /* XGXS Device (Dev Addr 4) */ 162 /****************************/ 163 164 #define READ_PHY8706_XS_REG(_unit, _phy_ctrl, _reg,_val) \ 165 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 166 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, (_reg)), (_val)) 167 #define WRITE_PHY8706_XS_REG(_unit, _phy_ctrl, _reg,_val) \ 168 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 169 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, (_reg)), (_val)) 170 #define MODIFY_PHY8706_XS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 171 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 172 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, (_reg)), (_val), (_mask)) 173 174 /* Control 1 Register (Addr 0000h) */ 175 #define READ_PHY8706_PHYXS_CTRLr(_unit, _phy_ctrl, _val) \ 176 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 177 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0), (_val)) 178 #define WRITE_PHY8706_PHYXS_CTRLr(_unit, _phy_ctrl, _val) \ 179 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 180 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0), (_val)) 181 #define MODIFY_PHY8706_PHYXS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 182 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 183 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0), (_val), (_mask)) 184 185 /* Status 1 Register (Addr 0001h) */ 186 #define READ_PHY8706_PHYXS_STATr(_unit, _phy_ctrl, _val) \ 187 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 188 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 1), (_val)) 189 #define WRITE_PHY8706_PHYXS_STATr(_unit, _phy_ctrl, _val) \ 190 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 191 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 1), (_val)) 192 #define MODIFY_PHY8706_PHYXS_STATr(_unit, _phy_ctrl, _val, _mask) \ 193 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 194 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 1), (_val), (_mask)) 195 196 /* PHY Identifier Register 0 (Addr 0002h) */ 197 /* PHY Identifier Register 1 (Addr 0003h) */ 198 /* Speed Ability (Addr 0004h) */ 199 /* Device in Package 2 (Addr 0005h) */ 200 /* Device in Package 1 (Addr 0006h) */ 201 /* Status 2 Register (Addr 0008h) */ 202 /* Organizatioally Unique Identifier 0 Register (Addr 000eh) */ 203 /* Organizationally Unique Identifier 1 Register (Addr 000fh) */ 204 205 /* XGXS Lane Status Register (Addr 0018h) */ 206 #define READ_PHY8706_PHYXS_XGXS_LANE_STATr(_unit, _phy_ctrl, _val) \ 207 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 208 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x18), (_val)) 209 #define WRITE_PHY8706_PHYXS_XGXS_LANE_STATr(_unit, _phy_ctrl, _val) \ 210 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 211 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x18), (_val)) 212 #define MODIFY_PHY8706_PHYXS_XGXS_LANE_STATr(_unit, _phy_ctrl, _val, _mask) \ 213 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 214 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x18), \ 215 (_val), (_mask)) 216 217 /* XGXS Test Control Register (Addr 0019h) */ 218 219 /* Misc Control Register (Addr 800eh) */ 220 #define READ_PHY8706_PHYXS_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 221 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 222 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x800e), (_val)) 223 #define WRITE_PHY8706_PHYXS_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 224 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 225 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x800e), (_val)) 226 #define MODIFY_PHY8706_PHYXS_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 227 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 228 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x800e), (_val), (_mask)) 229 230 /* XGXS control register */ 231 232 #define XGXS_MODE_CTRLr 0x8000 233 #define XGXS_MODE_SHIFTER 8 234 #define XGXS_MODE_NORMAL (0x1 << XGXS_MODE_SHIFTER) 235 #define XGXS_MODE_SYSTEM_LOOPBACK (0x0 << XGXS_MODE_SHIFTER) 236 #define XGXS_MODE_MASK (0xf << XGXS_MODE_SHIFTER) 237 #define XGXS_CTRL_RLOOP (1 << 6) 238 239 /* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 240 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 241 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 242 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 243 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 244 245 #define READ_PHY8706_PHYXS_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 246 READ_PHY8706_XS_REG((_unit), (_pc), 0x0000800e, (_val)) 247 #define WRITE_PHY8706_PHYXS_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 248 WRITE_PHY8706_XS_REG((_unit), (_pc), 0x0000800e, (_val)) 249 #define MODIFY_PHY8706_PHYXS_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val, _mask) \ 250 MODIFY_PHY8706_XS_REG((_unit), (_pc), 0x0000800e, (_val), (_mask)) 251 252 /* dsc_2_0 :: dsc_ctrl0 :: rxSeqStart [15:15] */ 253 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_MASK 0x8000 254 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_ALIGN 0 255 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_BITS 1 256 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_SHIFT 15 257 258 #define READ_PHY8706_PHYXS_RX_ALL_RX_CONTROLr(_unit, _pc, _val) \ 259 READ_PHY8706_XS_REG((_unit), (_pc), 0x000080f1, (_val)) 260 #define WRITE_PHY8706_PHYXS_RX_ALL_RX_CONTROLr(_unit, _pc, _val) \ 261 WRITE_PHY8706_XS_REG((_unit), (_pc), 0x000080f1, (_val)) 262 #define MODIFY_PHY8706_PHYXS_RX_ALL_RX_CONTROLr(_unit, _pc, _val, _mask) \ 263 MODIFY_PHY8706_XS_REG((_unit), (_pc), 0x000080f1, (_val), (_mask)) 264 265 #define READ_PHY8706_PHYXS_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \ 266 READ_PHY8706_XS_REG((_unit), (_pc), 0x00008122, (_val)) 267 #define WRITE_PHY8706_PHYXS_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \ 268 WRITE_PHY8706_XS_REG((_unit), (_pc), 0x00008122, (_val)) 269 #define MODIFY_PHY8706_PHYXS_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val, _mask) \ 270 MODIFY_PHY8706_XS_REG((_unit), (_pc), 0x00008122, (_val), (_mask)) 271 272 #define READ_PHY8706_PHYXS_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \ 273 READ_PHY8706_XS_REG((_unit), (_pc), 0x00008124, (_val)) 274 #define WRITE_PHY8706_PHYXS_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \ 275 WRITE_PHY8706_XS_REG((_unit), (_pc), 0x00008124, (_val)) 276 #define MODIFY_PHY8706_PHYXS_GP_STATUS_STATUS1000X1r(_unit, _pc, _val, _mask) \ 277 MODIFY_PHY8706_XS_REG((_unit), (_pc), 0x00008124, (_val), (_mask)) 278 279 /* XGXG status 3 register */ 280 281 /* GP_Status :: xgxsStatus3 :: link [15:15] */ 282 #define GP_STATUS_XGXSSTATUS3_LINK_MASK 0x8000 283 #define GP_STATUS_XGXSSTATUS3_LINK_ALIGN 0 284 #define GP_STATUS_XGXSSTATUS3_LINK_BITS 1 285 #define GP_STATUS_XGXSSTATUS3_LINK_SHIFT 15 286 287 #define READ_PHY8706_PHYXS_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \ 288 READ_PHY8706_XS_REG((_unit), (_pc), 0x00008129, (_val)) 289 #define WRITE_PHY8706_PHYXS_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \ 290 WRITE_PHY8706_XS_REG((_unit), (_pc), 0x00008129, (_val)) 291 #define MODIFY_PHY8706_PHYXS_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val, _mask) \ 292 MODIFY_PHY8706_XS_REG((_unit), (_pc), 0x00008129, (_val), (_mask)) 293 294 295 296 297 298 #define READ_PHY8706_PMAD_OPTICAL_CFG_REGr(_unit, _phy_ctrl, _val) \ 299 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 300 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xc8e4), (_val)) 301 302 #define WRITE_PHY8706_PMAD_OPTICAL_CFG_REGr(_unit, _phy_ctrl, _val) \ 303 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 304 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xc8e4), (_val)) 305 306 #define MODIFY_PHY8706_PMAD_OPTICAL_CFG_REGr(_unit, _phy_ctrl, _val, _mask) \ 307 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 308 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xc8e4), \ 309 (_val), (_mask)) 310 311 /************************************************/ 312 /* User Defined Registers (Devices 1, 2, and 3) */ 313 /************************************************/ 314 315 #define READ_PHY8706_IDENTIFIERr(_unit, _phy_ctrl, _val) \ 316 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 317 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xc800), (_val)) 318 #define WRITE_PHY8706_IDENTIFIERr(_unit, _phy_ctrl, _val) \ 319 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 320 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xc800), (_val)) 321 #define MODIFY_PHY8706_IDENTIFIERr(_unit, _phy_ctrl, _val, _mask) \ 322 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 323 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xc800), \ 324 (_val), (_mask)) 325 326 #define READ_PHY8706_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 327 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 328 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xca0a), (_val)) 329 #define WRITE_PHY8706_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 330 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 331 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xca0a), (_val)) 332 #define MODIFY_PHY8706_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 333 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 334 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xca0a), \ 335 (_val), (_mask)) 336 337 #define READ_PHY8706_TXA_ACTRL_3r(_unit, _phy_ctrl, _val) \ 338 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 339 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x80a7), (_val)) 340 #define WRITE_PHY8706_TXA_ACTRL_3r(_unit, _phy_ctrl, _val) \ 341 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 342 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x80a7), (_val)) 343 #define MODIFY_PHY8706_TXA_ACTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 344 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 345 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PHYXS, 0x80a7), \ 346 (_val), (_mask)) 347 348 /* General Purpose Register 1 */ 349 #define READ_PHY8706_GENREG1r(_unit, _phy_ctrl, _val) \ 350 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 351 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xca19), (_val)) 352 #define WRITE_PHY8706_GENREG1r(_unit, _phy_ctrl, _val) \ 353 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 354 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xca19), (_val)) 355 #define MODIFY_PHY8706_GENREG1r(_unit, _phy_ctrl, _val, _mask) \ 356 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 357 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_PMA_PMD, 0xca19), \ 358 (_val), (_mask)) 359 360 #define PHY8706_PMAD_SPA_CTRL_REG 0xC848 361 #define PHY8706_PMAD_RX_ALARM_STAT_REG 0x9003 362 #define PHY8706_PMAD_M8051_MSGIN_REG 0xCA12 363 #define PHY8706_PMAD_M8051_MSGOUT_REG 0xCA13 364 365 /************************************************/ 366 /* User Defined Registers (Devices 4) */ 367 /************************************************/ 368 369 #define PHY8706_TXA_CTRL_REG 0x80a1 370 #define PHY8706_TX0_CTRL_REG 0x8061 371 #define PHY8706_TX1_CTRL_REG 0x8071 372 #define PHY8706_TX2_CTRL_REG 0x8081 373 #define PHY8706_TX3_CTRL_REG 0x8091 374 #define PHY8706_TX_POLARITY_FLIP_MASK (1 << 5) 375 376 #define PHY8706_RXA_CTRL_REG 0x80fa 377 #define PHY8706_RX0_CTRL_REG 0x80ba 378 #define PHY8706_RX1_CTRL_REG 0x80ca 379 #define PHY8706_RX2_CTRL_REG 0x80da 380 #define PHY8706_RX3_CTRL_REG 0x80ea 381 #define PHY8706_RX_POLARITY_FLIP_MASK (3 << 2) 382 383 384 /* Auto-Neotiation device */ 385 386 #define READ_PHY8706_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 387 PHY8706_REG_READ((_unit), (_phy_ctrl), \ 388 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_AN, (_reg)), (_val)) 389 #define WRITE_PHY8706_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 390 PHY8706_REG_WRITE((_unit), (_phy_ctrl), \ 391 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_AN, (_reg)), (_val)) 392 #define MODIFY_PHY8706_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 393 PHY8706_REG_MODIFY((_unit), (_phy_ctrl), \ 394 SOC_PHY_CLAUSE45_ADDR(PHY8706_C45_DEV_AN, (_reg)), (_val), (_mask)) 395 396 /* autoneg control register */ 397 398 #define AN_CTRL_REG 0 399 #define AN_EXT_NXT_PAGE (1 << 13) 400 #define AN_ENABLE (1 << 12) 401 #define AN_RESTART (1 << 9) 402 403 /* autoneg status register */ 404 405 #define AN_STATUS_REG 1 406 #define AN_LINK (1 << 2) 407 #define AN_DONE (1 << 5) 408 409 /* BP ethernet status register */ 410 #define AN_ETH_STATUS_REG 0x30 411 #define AN_SPEED_1000BASE_KX (1 << 1) 412 #define AN_SPEED_10GBASE_KR (1 << 3) 413 414 /* 1G status register for both autoneg mode and forced mode */ 415 #define AN_1G_STATUS_REG 0x8304 416 #define AN_1G_LINKUP 0x2 417 #define AN_1G_LINK_CHANGE 0x80 418 419 #endif /* _phy8706_H_ */