phy8705.h (11317B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8705.h 8 */ 9 10 #ifndef _phy8705_H_ 11 #define _phy8705_H_ 12 13 #include <soc/phy.h> 14 15 #define MII_CTRL_PMA_LOOPBACK (1 << 0) 16 #define MII_CTRL_WIS_LOOP_BACK (1 << 14) 17 18 #define PHY8705_C45_DEV_PMA_PMD 0x01 19 #define PHY8705_C45_DEV_WIS 0x02 20 #define PHY8705_C45_DEV_PCS 0x03 21 #define PHY8705_C45_DEV_PHYXS 0x04 22 #define PHY8705_C45_DEV_DTEXS 0x05 23 24 #define PHY8705_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 25 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 26 #define PHY8705_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 27 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 28 #define PHY8705_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 29 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 30 31 /* PMA/PMD Device (Dev Addr 1) */ 32 33 #define READ_PHY8705_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val) \ 34 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 35 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, (_reg)), (_val)) 36 #define WRITE_PHY8705_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val) \ 37 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 38 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, (_reg)), (_val)) 39 #define MODIFY_PHY8705_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 40 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 41 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask)) 42 43 /* Control Register (Addr 0000h) */ 44 #define READ_PHY8705_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 45 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 46 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0), (_val)) 47 #define WRITE_PHY8705_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 48 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 49 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0), (_val)) 50 #define MODIFY_PHY8705_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 51 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 52 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0), (_val), (_mask)) 53 54 /* Status Register (Addr 0001h) */ 55 #define READ_PHY8705_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 56 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 57 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 1), (_val)) 58 #define WRITE_PHY8705_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 59 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 60 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 1), (_val)) 61 #define MODIFY_PHY8705_PMA_PMD_STATr(_unit, _phy_ctrl, _val, _mask) \ 62 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 63 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 1), (_val), (_mask)) 64 65 /* ID0 Register (Addr 0002h) */ 66 /* ID1 Register (Addr 0003h) */ 67 /* Speed Ability Register (Addr 0004h) */ 68 /* Devices in Package 1 Register (Addr 0005h) */ 69 /* Devices in Package 2 Register (Addr 0006h) */ 70 /* Control 2 Register (Addr 0007h) */ 71 /* Status 2 Register (Addr 0008h) */ 72 73 /* Transmit Disable Register (Addr 0009h) */ 74 #define READ_PHY8705_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 75 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 76 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 9), (_val)) 77 #define WRITE_PHY8705_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 78 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 79 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 9), (_val)) 80 #define MODIFY_PHY8705_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 81 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 82 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 9), (_val), (_mask)) 83 84 85 /* Receive Signal Detect Register (Addr 000Ah) */ 86 /* Organizationlly Unique Identifier 0 Register (Addr 000Eh) */ 87 /* Organizationlly Unique Identifier 1 Register (Addr 000Fh) */ 88 89 /* WIS Device (Dev Addr 2) */ 90 /* Control 1 Register (Addr 0000h) */ 91 #define READ_PHY8705_WIS_CTRLr(_unit, _phy_ctrl, _val) \ 92 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 93 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 0), (_val)) 94 #define WRITE_PHY8705_WIS_CTRLr(_unit, _phy_ctrl, _val) \ 95 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 96 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 0), (_val)) 97 #define MODIFY_PHY8705_WIS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 98 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 99 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 0), (_val), (_mask)) 100 101 /* Status 1 Register (Addr 0001h) */ 102 #define READ_PHY8705_WIS_STATr(_unit, _phy_ctrl, _val) \ 103 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 104 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 1), (_val)) 105 #define WRITE_PHY8705_WIS_STATr(_unit, _phy_ctrl, _val) \ 106 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 107 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 1), (_val)) 108 #define MODIFY_PHY8705_WIS_STATr(_unit, _phy_ctrl, _val, _mask) \ 109 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 110 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 1), (_val), (_mask)) 111 112 /* ID0 Register (Addr 0002h) */ 113 /* ID1 Register (Addr 0003h) */ 114 /* Speed Ability Register (Addr 0004h) */ 115 116 /* Devices in Package 1 Register (Addr 0005h) */ 117 #define READ_PHY8705_WIS_DEV_IN_PKGr(_unit, _phy_ctrl, _val) \ 118 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 119 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 5), (_val)) 120 #define WRITE_PHY8705_WIS_DEV_IN_PKGr(_unit, _phy_ctrl, _val) \ 121 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 122 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 5), (_val)) 123 #define MODIFY_PHY8705_WIS_DEV_IN_PKGr(_unit, _phy_ctrl, _val, _mask) \ 124 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 125 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 5), (_val), (_mask)) 126 127 /* Devices in Package 2 Register (Addr 0006h) */ 128 /* Control 2 Register (Addr 0007h) */ 129 /* Status 2 Register (Addr 0008h) */ 130 /* Test Pattern Error Counter (Addr 0009h) */ 131 /* Package Identifier 0 Register (Addr 000Eh) */ 132 /* Package Identifier 1 Register (Addr 000Fh) */ 133 /* Status 3 Register (Addr 0021h) */ 134 /* Far End Path Block Error Counter (Addr 0025h) */ 135 136 /* PCS Device (Dev Addr 3) */ 137 /* Control 1 Register (Addr 0000h) */ 138 #define READ_PHY8705_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 139 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 140 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PCS, 0), (_val)) 141 #define WRITE_PHY8705_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 142 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 143 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PCS, 0), (_val)) 144 #define MODIFY_PHY8705_PCS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 145 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 146 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PCS, 0), (_val), (_mask)) 147 148 /* Status 1 Register (Addr 0001h) */ 149 #define READ_PHY8705_PCS_STATr(_unit, _phy_ctrl, _val) \ 150 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 151 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PCS, 1), (_val)) 152 #define WRITE_PHY8705_PCS_STATr(_unit, _phy_ctrl, _val) \ 153 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 154 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PCS, 1), (_val)) 155 #define MODIFY_PHY8705_PCS_STATr(_unit, _phy_ctrl, _val, _mask) \ 156 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 157 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PCS, 1), (_val), (_mask)) 158 159 /* XGXS Device (Dev Addr 4) */ 160 /* Control 1 Register (Addr 0000h) */ 161 #define READ_PHY8705_PHYXS_CTRLr(_unit, _phy_ctrl, _val) \ 162 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 163 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PHYXS, 0), (_val)) 164 #define WRITE_PHY8705_PHYXS_CTRLr(_unit, _phy_ctrl, _val) \ 165 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 166 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PHYXS, 0), (_val)) 167 #define MODIFY_PHY8705_PHYXS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 168 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 169 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PHYXS, 0), (_val), (_mask)) 170 171 /* Status 1 Register (Addr 0001h) */ 172 #define READ_PHY8705_PHYXS_STATr(_unit, _phy_ctrl, _val) \ 173 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 174 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PHYXS, 1), (_val)) 175 #define WRITE_PHY8705_PHYXS_STATr(_unit, _phy_ctrl, _val) \ 176 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 177 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PHYXS, 1), (_val)) 178 #define MODIFY_PHY8705_PHYXS_STATr(_unit, _phy_ctrl, _val, _mask) \ 179 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 180 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PHYXS, 1), (_val), (_mask)) 181 182 183 /* User Defined Registers */ 184 185 #define READ_PHY8705_IDENTIFIERr(_unit, _phy_ctrl, _val) \ 186 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 187 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xc800), (_val)) 188 #define WRITE_PHY8705_IDENTIFIERr(_unit, _phy_ctrl, _val) \ 189 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 190 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xc800), (_val)) 191 #define MODIFY_PHY8705_IDENTIFIERr(_unit, _phy_ctrl, _val, _mask) \ 192 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 193 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xc800), \ 194 (_val), (_mask)) 195 #define PMAD_IDr_WAN_MODE (1 << 6) 196 197 #define READ_PHY8705_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 198 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 199 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 0xca0a), (_val)) 200 #define WRITE_PHY8705_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 201 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 202 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_WIS, 0xca0a), (_val)) 203 #define MODIFY_PHY8705_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 204 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 205 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xca0a), \ 206 (_val), (_mask)) 207 208 #define READ_PHY8705_PMD_DIGI_CTRLr(_unit, _phy_ctrl, _val) \ 209 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 210 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xc808), (_val)) 211 #define WRITE_PHY8705_PMD_DIGI_CTRLr(_unit, _phy_ctrl, _val) \ 212 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 213 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xc808), (_val)) 214 #define MODIFY_PHY8705_PMD_DIGI_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 215 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 216 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xc808), \ 217 (_val), (_mask)) 218 219 #define READ_PHY8705_OVERRIDE_CTRLr(_unit, _phy_ctrl, _val) \ 220 PHY8705_REG_READ((_unit), (_phy_ctrl), \ 221 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xca09), (_val)) 222 #define WRITE_PHY8705_OVERRIDE_CTRLr(_unit, _phy_ctrl, _val) \ 223 PHY8705_REG_WRITE((_unit), (_phy_ctrl), \ 224 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xca09), (_val)) 225 #define MODIFY_PHY8705_OVERRIDE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 226 PHY8705_REG_MODIFY((_unit), (_phy_ctrl), \ 227 SOC_PHY_CLAUSE45_ADDR(PHY8705_C45_DEV_PMA_PMD, 0xca09), \ 228 (_val), (_mask)) 229 230 231 232 #endif /* _phy8705_H_ */