phy8703.h (9345B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8703.h 8 */ 9 10 #ifndef _PHY8703_H_ 11 #define _PHY8703_H_ 12 13 #include <soc/phy.h> 14 15 #define MII_CTRL_PMA_LOOPBACK (1 << 0) 16 17 #define PHY8703_C45_DEV_PMA_PMD 0x01 18 #define PHY8703_C45_DEV_PCS 0x03 19 #define PHY8703_C45_DEV_PHYXS 0x04 20 #define PHY8703_C45_DEV_DTEXS 0x05 21 22 #define PHY8703_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 23 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 24 #define PHY8703_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 25 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 26 #define PHY8703_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 27 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 28 29 /* PMA/PMD Device (Dev Addr 1) */ 30 31 /* Control Register (Addr 0000h) */ 32 #define READ_PHY8703_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 33 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 34 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0), (_val)) 35 #define WRITE_PHY8703_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 36 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 37 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0), (_val)) 38 #define MODIFY_PHY8703_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 39 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 40 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0), (_val), (_mask)) 41 42 /* Status Register (Addr 0001h) */ 43 #define READ_PHY8703_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 44 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 45 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 1), (_val)) 46 #define WRITE_PHY8703_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 47 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 48 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 1), (_val)) 49 #define MODIFY_PHY8703_PMA_PMD_STATr(_unit, _phy_ctrl, _val, _mask) \ 50 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 51 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 1), (_val), (_mask)) 52 53 /* ID0 Register (Addr 0002h) */ 54 /* ID1 Register (Addr 0003h) */ 55 /* Speed Ability Register (Addr 0004h) */ 56 /* Devices in Package 1 Register (Addr 0005h) */ 57 /* Devices in Package 2 Register (Addr 0006h) */ 58 /* Control 2 Register (Addr 0007h) */ 59 /* Status 2 Register (Addr 0008h) */ 60 61 /* Transmit Disable Register (Addr 0009h) */ 62 #define READ_PHY8703_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 63 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 64 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 9), (_val)) 65 #define WRITE_PHY8703_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 66 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 67 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 9), (_val)) 68 #define MODIFY_PHY8703_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 69 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 70 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 9), (_val), (_mask)) 71 72 73 /* Receive Signal Detect Register (Addr 000Ah) */ 74 /* Organizationlly Unique Identifier 0 Register (Addr 000Eh) */ 75 /* Organizationlly Unique Identifier 1 Register (Addr 000Fh) */ 76 77 /* WIS Device (Dev Addr 2) */ 78 /* Control 1 Register (Addr 0000h) */ 79 #define READ_PHY8703_WIS_CTRLr(_unit, _phy_ctrl, _val) \ 80 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 81 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 0), (_val)) 82 #define WRITE_PHY8703_WIS_CTRLr(_unit, _phy_ctrl, _val) \ 83 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 84 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 0), (_val)) 85 #define MODIFY_PHY8703_WIS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 86 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 87 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 0), (_val), (_mask)) 88 89 /* Status 1 Register (Addr 0001h) */ 90 #define READ_PHY8703_WIS_STATr(_unit, _phy_ctrl, _val) \ 91 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 92 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 1), (_val)) 93 #define WRITE_PHY8703_WIS_STATr(_unit, _phy_ctrl, _val) \ 94 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 95 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 1), (_val)) 96 #define MODIFY_PHY8703_WIS_STATr(_unit, _phy_ctrl, _val, _mask) \ 97 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 98 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 1), (_val), (_mask)) 99 100 /* ID0 Register (Addr 0002h) */ 101 /* ID1 Register (Addr 0003h) */ 102 /* Speed Ability Register (Addr 0004h) */ 103 104 /* Devices in Package 1 Register (Addr 0005h) */ 105 #define READ_PHY8703_WIS_DEV_IN_PKGr(_unit, _phy_ctrl, _val) \ 106 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 107 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 5), (_val)) 108 #define WRITE_PHY8703_WIS_DEV_IN_PKGr(_unit, _phy_ctrl, _val) \ 109 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 110 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 5), (_val)) 111 #define MODIFY_PHY8703_WIS_DEV_IN_PKGr(_unit, _phy_ctrl, _val, _mask) \ 112 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 113 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_WIS, 5), (_val), (_mask)) 114 115 /* Devices in Package 2 Register (Addr 0006h) */ 116 /* Control 2 Register (Addr 0007h) */ 117 /* Status 2 Register (Addr 0008h) */ 118 /* Test Pattern Error Counter (Addr 0009h) */ 119 /* Package Identifier 0 Register (Addr 000Eh) */ 120 /* Package Identifier 1 Register (Addr 000Fh) */ 121 /* Status 3 Register (Addr 0021h) */ 122 /* Far End Path Block Error Counter (Addr 0025h) */ 123 124 /* PCS Device (Dev Addr 3) */ 125 /* Control 1 Register (Addr 0000h) */ 126 #define READ_PHY8703_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 127 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 128 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PCS, 0), (_val)) 129 #define WRITE_PHY8703_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 130 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 131 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PCS, 0), (_val)) 132 #define MODIFY_PHY8703_PCS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 133 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 134 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PCS, 0), (_val), (_mask)) 135 136 /* Status 1 Register (Addr 0001h) */ 137 #define READ_PHY8703_PCS_STATr(_unit, _phy_ctrl, _val) \ 138 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 139 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PCS, 1), (_val)) 140 #define WRITE_PHY8703_PCS_STATr(_unit, _phy_ctrl, _val) \ 141 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 142 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PCS, 1), (_val)) 143 #define MODIFY_PHY8703_PCS_STATr(_unit, _phy_ctrl, _val, _mask) \ 144 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 145 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PCS, 1), (_val), (_mask)) 146 147 /* XGXS Device (Dev Addr 4) */ 148 /* Control 1 Register (Addr 0000h) */ 149 #define READ_PHY8703_PHYXS_CTRLr(_unit, _phy_ctrl, _val) \ 150 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 151 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PHYXS, 0), (_val)) 152 #define WRITE_PHY8703_PHYXS_CTRLr(_unit, _phy_ctrl, _val) \ 153 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 154 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PHYXS, 0), (_val)) 155 #define MODIFY_PHY8703_PHYXS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 156 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 157 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PHYXS, 0), (_val), (_mask)) 158 159 /* Status 1 Register (Addr 0001h) */ 160 #define READ_PHY8703_PHYXS_STATr(_unit, _phy_ctrl, _val) \ 161 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 162 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PHYXS, 1), (_val)) 163 #define WRITE_PHY8703_PHYXS_STATr(_unit, _phy_ctrl, _val) \ 164 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 165 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PHYXS, 1), (_val)) 166 #define MODIFY_PHY8703_PHYXS_STATr(_unit, _phy_ctrl, _val, _mask) \ 167 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 168 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PHYXS, 1), (_val), (_mask)) 169 170 171 /* User Defined Registers */ 172 173 #define READ_PHY8703_IDENTIFIERr(_unit, _phy_ctrl, _val) \ 174 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 175 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0xc800), (_val)) 176 #define WRITE_PHY8703_IDENTIFIERr(_unit, _phy_ctrl, _val) \ 177 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 178 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0xc800), (_val)) 179 #define MODIFY_PHY8703_IDENTIFIERr(_unit, _phy_ctrl, _val, _mask) \ 180 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 181 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0xc800), \ 182 (_val), (_mask)) 183 184 #define READ_PHY8703_PMD_TX_CTRLr(_unit, _phy_ctrl, _val) \ 185 PHY8703_REG_READ((_unit), (_phy_ctrl), \ 186 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0xc803), (_val)) 187 #define WRITE_PHY8703_PMD_TX_CTRLr(_unit, _phy_ctrl, _val) \ 188 PHY8703_REG_WRITE((_unit), (_phy_ctrl), \ 189 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0xc803), (_val)) 190 #define MODIFY_PHY8703_PMD_TX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 191 PHY8703_REG_MODIFY((_unit), (_phy_ctrl), \ 192 SOC_PHY_CLAUSE45_ADDR(PHY8703_C45_DEV_PMA_PMD, 0xc803), \ 193 (_val), (_mask)) 194 195 #endif /* _phy8703_H_ */