phy8481.h (136818B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8481.h 8 */ 9 10 #ifndef _PHY8481_H_ 11 #define _PHY8481_H_ 12 13 #ifdef BCM_PLP_BASE_T_PHY 14 #include "legacy/legacy.h" 15 #else 16 #include <soc/phy.h> 17 #endif 18 19 #define MII_CTRL_PMA_LOOPBACK (1 << 0) 20 21 #define PHY8481_C45_DEV_PMAD 0x01 22 #define PHY8481_C45_DEV_PCS 0x03 23 #define PHY8481_C45_DEV_PHYXS_M 0x04 24 #define PHY8481_C45_DEV_PHYXS_L 0x03 25 #define PHY8481_C45_DEV_AN 0x07 26 #define PHY8481_C45_DEV_TOPLVL1 0x1e 27 #define PHY8481_C45_DEV_TOPLVL2 0x1f 28 #define PHY8481_DUMMY_ACCESS_FLAG 0x10000000 29 30 #define PHY8481_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 31 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 32 #define PHY8481_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 33 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 34 #define PHY8481_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 35 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 36 37 /*******************************/ 38 /* PMA/PMD Device (Dev Addr 1) */ 39 /*******************************/ 40 41 #define PMAD_IEEE_CTL1 0x0000 /* IEEE PMA/PMD control 1 register (reg 1.0) */ 42 #define PMAD_IEEE_CTL1_LPBK (1U<<0) 43 44 #define PMAD_IEEE_ST1 0x0001 /* IEEE PMA/PMD status 1 register (reg 1.1) */ 45 #define PMAD_IEEE_DEV_ID0 0x0002 /* IEEE PMA/PMD device identifier part 0 (reg 1.2) */ 46 #define PMAD_IEEE_DEV_ID1 0x0003 /* IEEE PMA/PMD device identifier part 1 (reg 1.3) */ 47 #define PMAD_IEEE_SP_CAP 0x0004 /* IEEE PMA/PMD speed ability (reg 1.4) */ 48 #define PMAD_IEEE_DEV0 0x0005 /* Devices in package register part 0 (reg 1.5) */ 49 #define PMAD_IEEE_DEV1 0x0006 /* Devices in package register part 1 (reg 1.6) */ 50 #define PMAD_IEEE_CTL2 0x0007 /* PMA/PMD control 2 register (reg 1.7) */ 51 #define PMAD_IEEE_ST2 0x0008 /* 10G PMA/PMD status 2 register (reg 1.8) */ 52 #define PMAD_IEEE_TRAN_DIS 0x0009 /* 10G PMA/PMD transmit disable (reg 1.9) */ 53 #define PMAD_IEEE_RCV_DET 0x000a /* 10G PMD receive signal detect (reg 1.10) */ 54 #define PMAD_IEEE_EXT_AB 0x000b /* 10G PMA/PMD extended ability (reg 1.11) */ 55 #define PMAD_IEEE_PKG_ID0 0x000e /* PMA/PMD package identifier (reg 1.14) */ 56 #define PMAD_IEEE_PKG_ID1 0x000f /* PMA/PMD package identifier (reg 1.15) */ 57 #define PMAD_IEEE_ST_10GT 0x0000 /* 10GBASE-T status (reg 1.129) */ 58 #define PMAD_IEEE_SWAP_POL_10GT 0x0000 /* 10GBASE-T pair swap and polarity (reg 1.130) */ 59 #define PMAD_IEEE_PWRBK_SET_10GT 0x0000 /* 10GBASE-T TX power backoff and PHY short reach setting (reg 1.131) */ 60 #define PMAD_IEEE_TST_MODE_10GT 0x0000 /* 10GBASE-T test mode (reg 1.132) */ 61 #define PMAD_IEEE_SKW_DLY0_10GT 0x0000 /* 10GBASE-T skew delay part 0 (reg 1.145) */ 62 #define PMAD_IEEE_SKW_DLY1_10GT 0x0000 /* 10GBASE-T skew delay part 1 (reg 1.146) */ 63 64 #define PHY8488X_MDC_CLOCK_MASK BIT(0) 65 #define PHY8488X_SOFT_RESET_MASK BIT(0) 66 67 #define READ_PHY8481_PMAD_REG(_unit, _phy_ctrl, _reg,_val) \ 68 PHY8481_REG_READ((_unit), (_phy_ctrl), \ 69 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PMAD, (_reg)), (_val)) 70 #define WRITE_PHY8481_PMAD_REG(_unit, _phy_ctrl, _reg,_val) \ 71 PHY8481_REG_WRITE((_unit), (_phy_ctrl), \ 72 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PMAD, (_reg)), (_val)) 73 #define MODIFY_PHY8481_PMAD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 74 PHY8481_REG_MODIFY((_unit), (_phy_ctrl), \ 75 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PMAD, (_reg)), (_val), (_mask)) 76 77 /* According to 802.3an the GPHY speed selection bits in reg 1.0 are bit 13 - MSB, 78 bit 6 - LSB. However in 8481 bit 13 - LSB and bit 6 - MSB. 79 */ 80 81 #define PMAD_MII_CTRL_SS_LSB (1 << 13) /* Speed select, LSb */ 82 #define PMAD_MII_CTRL_SS_MSB (1 << 6) /* Speed select, MSb */ 83 #define PMAD_MII_CTRL_SS_10 0 84 #define PMAD_MII_CTRL_SS_100 (PMAD_MII_CTRL_SS_LSB) 85 #define PMAD_MII_CTRL_SS_1000 (PMAD_MII_CTRL_SS_MSB) 86 #define PMAD_MII_CTRL_SS_MASK (PMAD_MII_CTRL_SS_LSB | PMAD_MII_CTRL_SS_MSB) 87 88 89 /* Control Register PMAD_IEEE_CTL1 */ 90 91 #define READ_PHY8481_PMAD_CTRLr(_unit, _phy_ctrl, _val) \ 92 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_CTL1,(_val)) 93 #define WRITE_PHY8481_PMAD_CTRLr(_unit, _phy_ctrl, _val) \ 94 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_CTL1,(_val)) 95 #define MODIFY_PHY8481_PMAD_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 96 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_CTL1, (_val), (_mask)) 97 98 99 /* Status Register PMAD_IEEE_ST1 */ 100 101 #define READ_PHY8481_PMAD_STATr(_unit, _phy_ctrl, _val) \ 102 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_ST1,(_val)) 103 #define WRITE_PHY8481_PMAD_STATr(_unit, _phy_ctrl, _val) \ 104 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_ST1,(_val)) 105 #define MODIFY_PHY8481_PMAD_STATr(_unit, _phy_ctrl, _val, _mask) \ 106 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_ST1, (_val), (_mask)) 107 108 109 /* ID0 Register (Addr 0002h) */ 110 #define PMAD_ID0_REG 0x2 111 112 /* ID1 Register (Addr 0003h) */ 113 #define PMAD_ID1_REG 0x3 114 115 /* Speed Ability Register (Addr 0004h) */ 116 /* Devices in Package 1 Register (Addr 0005h) */ 117 /* Devices in Package 2 Register (Addr 0006h) */ 118 119 /* Control 2 Register (Addr 0007h) */ 120 #define PMAD_CTRL2_REG 0x7 121 122 #define IEEE_CTRLr_SPEED_10G_MASK 0x003c 123 #define IEEE_CTRLr_SPEED_10G 0x2040 124 125 /* Control Register PMAD_IEEE_CTL2 */ 126 127 #define READ_PHY8481_PMAD_CTRL2r(_unit, _phy_ctrl, _val) \ 128 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_CTL2,(_val)) 129 #define WRITE_PHY8481_PMAD_CTRL2r(_unit, _phy_ctrl, _val) \ 130 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_CTL2,(_val)) 131 #define MODIFY_PHY8481_PMAD_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 132 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_CTL2, (_val), (_mask)) 133 134 /* Status 2 Register (Addr 0008h) */ 135 136 /* Transmit Disable Register (Addr 0009h) */ 137 138 #define READ_PHY8481_PMAD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 139 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_TRAN_DIS,(_val)) 140 #define WRITE_PHY8481_PMAD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 141 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_TRAN_DIS,(_val)) 142 #define MODIFY_PHY8481_PMAD_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 143 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PMAD_IEEE_TRAN_DIS, (_val), (_mask)) 144 145 /* Receive Signal Detect Register (Addr 000Ah) */ 146 /* Extended Ability Register (Addr 000Bh) */ 147 /* Receive Signal Detect Register (Addr 000Ah) */ 148 /* Receive Signal Detect Register (Addr 000Ah) */ 149 /* Organizationlly Unique Identifier 0 Register (Addr 000Eh) */ 150 /* Organizationlly Unique Identifier 1 Register (Addr 000Fh) */ 151 152 /* EEE Statistics related */ 153 154 #define READ_PHY8481_PHYC_CTL_AI_LPI_CTLr(_unit, _phy_ctrl, _val) \ 155 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa88a : 0xa878,(_val)) 156 #define WRITE_PHY8481_PHYC_CTL_AI_LPI_CTLr(_unit, _phy_ctrl, _val) \ 157 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa88a : 0xa878,(_val)) 158 #define MODIFY_PHY8481_PHYC_CTL_AI_LPI_CTLr(_unit, _phy_ctrl, _val, _mask) \ 159 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa88a : 0xa878, (_val), (_mask)) 160 161 #define READ_PHY8481_EEE_STATISTICS_CTLr(_unit, _phy_ctrl, _val) \ 162 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8f5 : 0xa907,(_val)) 163 #define WRITE_PHY8481_EEE_STATISTICS_CTLr(_unit, _phy_ctrl, _val) \ 164 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8f5 : 0xa907,(_val)) 165 #define MODIFY_PHY8481_EEE_STATISTICS_CTLr(_unit, _phy_ctrl, _val, _mask) \ 166 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8f5 : 0xa907, (_val), (_mask)) 167 168 #define READ_PHY8481_EXP_EEE_TX_EVENTS_HIGHr(_unit, _phy_ctrl, _val) \ 169 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8f6 : 0xa908,(_val)) 170 #define READ_PHY8481_EXP_EEE_TX_EVENTS_LOWr(_unit, _phy_ctrl, _val) \ 171 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8f7 : 0xa909,(_val)) 172 173 #define READ_PHY8481_EXP_EEE_RX_EVENTS_HIGHr(_unit, _phy_ctrl, _val) \ 174 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8fa : 0xa90c,(_val)) 175 #define READ_PHY8481_EXP_EEE_RX_EVENTS_LOWr(_unit, _phy_ctrl, _val) \ 176 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8fb : 0xa90d,(_val)) 177 178 #define READ_PHY8481_EXP_EEE_TX_DURATION_HIGHr(_unit, _phy_ctrl, _val) \ 179 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8f8 : 0xa90a,(_val)) 180 #define READ_PHY8481_EXP_EEE_TX_DURATION_LOWr(_unit, _phy_ctrl, _val) \ 181 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8f9 : 0xa90b,(_val)) 182 183 #define READ_PHY8481_EXP_EEE_RX_DURATION_HIGHr(_unit, _phy_ctrl, _val) \ 184 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8fc : 0xa90e,(_val)) 185 #define READ_PHY8481_EXP_EEE_RX_DURATION_LOWr(_unit, _phy_ctrl, _val) \ 186 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHY_IS_BCM8483X_AND_UP((_phy_ctrl)) ? 0xa8fd : 0xa90f,(_val)) 187 188 189 /****************************/ 190 /* PCS Device (Dev Addr 3) */ 191 /****************************/ 192 193 #define PCS_IEEE_CTL1 0x0000 /* IEEE PCS control 1 register (reg 3.0) */ 194 #define PCS_IEEE_CTL1_LPBK (1U<<14) 195 196 #define PCS_IEEE_ST1 0x0001 /* IEEE PCS status 1 register (reg 3.1) */ 197 #define PCS_IEEE_DEV_ID0 0x0002 /* IEEE PCS device identifier part 0 (reg 3.2) */ 198 #define PCS_IEEE_DEV_ID1 0x0003 /* IEEE PCS device identifier part 1 (reg 3.3) */ 199 #define PCS_IEEE_SP_CAP 0x0004 /* IEEE PCS speed ability (reg 3.4) */ 200 #define PCS_IEEE_DEV0 0x0005 /* Devices in package register part 0 (reg 3.5) */ 201 #define PCS_IEEE_DEV1 0x0006 /* Devices in package register part 1 (reg 3.6) */ 202 #define PCS_IEEE_CTL2 0x0007 /* PCS control 2 register (reg 3.7) */ 203 #define PCS_IEEE_ST2 0x0008 /* 10G PCS status 2 register (reg 3.8) */ 204 #define PCS_IEEE_PKG_ID0 0x000e /* PCS package identifier (reg 3.14) */ 205 #define PCS_IEEE_PKG_ID1 0x000f /* PCS package identifier (reg 3.15) */ 206 #define PCS_IEEE_RT_10G_ST1 0x0020 /* 10GBASE_R & 10GBASE_T PCS status 1 (reg 3.32) */ 207 #define PCS_IEEE_RT_10G_ST2 0x0021 /* 10GBASE_R & 10GBASE_T PCS status 2 (reg 3.33) */ 208 209 210 #define READ_PHY8481_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 211 PHY8481_REG_READ((_unit), (_phy_ctrl), \ 212 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PCS, (_reg)), (_val)) 213 #define WRITE_PHY8481_PCS_REG(_unit, _phy_ctrl, _reg, _val) \ 214 PHY8481_REG_WRITE((_unit), (_phy_ctrl), \ 215 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PCS, (_reg)), (_val)) 216 #define MODIFY_PHY8481_PCS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 217 PHY8481_REG_MODIFY((_unit), (_phy_ctrl), \ 218 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PCS, (_reg)), (_val), (_mask)) 219 220 221 /* Control 1 Register (Addr 0000h) */ 222 #define READ_PHY8481_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 223 READ_PHY8481_PCS_REG((_unit), (_phy_ctrl), PCS_IEEE_CTL1,(_val)) 224 #define WRITE_PHY8481_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 225 WRITE_PHY8481_PCS_REG((_unit), (_phy_ctrl), PCS_IEEE_CTL1,(_val)) 226 #define MODIFY_PHY8481_PCS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 227 MODIFY_PHY8481_PCS_REG((_unit), (_phy_ctrl), PCS_IEEE_CTL1, (_val), (_mask)) 228 229 /* Status 1 Register (Addr 0001h) */ 230 #define READ_PHY8481_PCS_STATr(_unit, _phy_ctrl, _val) \ 231 READ_PHY8481_PCS_REG((_unit), (_phy_ctrl), PCS_IEEE_ST1,(_val)) 232 #define WRITE_PHY8481_PCS_STATr(_unit, _phy_ctrl, _val) \ 233 WRITE_PHY8481_PCS_REG((_unit), (_phy_ctrl), PCS_IEEE_ST1,(_val)) 234 #define MODIFY_PHY8481_PCS_STATr(_unit, _phy_ctrl, _val, _mask) \ 235 MODIFY_PHY8481_PCS_REG((_unit), (_phy_ctrl), PCS_IEEE_ST1, (_val), (_mask)) 236 237 238 /* PCS Identifier 0 Register (Addr 0002h) */ 239 240 /* PCS Identifier 1 Register (Addr 0003h) */ 241 242 /* Speed Ability (Addr 0004h) */ 243 244 /* Devices in Package 1 (Addr 0005h) */ 245 246 /* Devices in Package 2 (Addr 0006h) */ 247 248 /* PCS Control 2 Register (Addr 0007h) */ 249 250 /* PCS Status 2 Register (Addr 0008h) */ 251 252 /* Organizationally Unique Identifier 0 Register (Addr 000eh) */ 253 /* Organizationally Unique Identifier 1 Register (Addr 000fh) */ 254 /* 10GBASE-X PCS Status Register (Addr 0x0018h) */ 255 /* 10GBASE-R PCS Status Register (Addr 0x0020h) */ 256 /* 10GBASE-R PCS Status 2 Register (Addr 0x0021h) */ 257 /* 10GBASE-R PCS Jitter Test Seed A0 Register (Addr 0x0022h) */ 258 /* 10GBASE-R PCS Jitter Test Seed A1 Register (Addr 0x0023h) */ 259 /* 10GBASE-R PCS Jitter Test Seed A2 Register (Addr 0x0024h) */ 260 /* 10GBASE-R PCS Jitter Test Seed A3 Register (Addr 0x0025h) */ 261 /* 10GBASE-R PCS Jitter Test Seed B0 Register (Addr 0x0026h) */ 262 /* 10GBASE-R PCS Jitter Test Seed B1 Register (Addr 0x0027h) */ 263 /* 10GBASE-R PCS Jitter Test Seed B2 Register (Addr 0x0028h) */ 264 /* 10GBASE-R PCS Jitter Test Seed B3 Register (Addr 0x0029h) */ 265 /* 10GBASE-R PCS Jitter Test Control Register (Addr 0x002ah) */ 266 /* 10GBASE-R PCS Jitter Test Error Counter Register (Addr 0x002Bh) */ 267 /* PRBS23 WIN_2 Register (Addr = 0xc92dh) */ 268 269 /****************/ 270 /* XGXS Devices */ 271 /****************/ 272 273 #define XGXS_IEEE_CTL1 0x0000 274 #define XGXS_IEEE_CTL1_LPBK (1U<<14) 275 276 #define XGXS_IEEE_ST1 0x0001 277 #define XGXS_IEEE_ID0 0x0002 278 #define XGXS_IEEE_ID1 0x0003 279 #define XGXS_IEEE_SP_AB 0x0004 280 #define XGXS_IEEE_DEV_IN_PKG2 0x0005 /* NOTE: (020426) this compensates for wrong mapping of spec */ 281 #define XGXS_IEEE_DEV_IN_PKG1 0x0006 282 #define XGXS_IEEE_ST2 0x0008 283 #define XGXS_IEEE_OUID1 0x000e /* Note: only available in Clause45 mode (st_strap = 0) */ 284 #define XGXS_IEEE_OUID2 0x000f /* Note: only available in Clause45 mode (st_strap = 0) */ 285 #define XGXS_IEEE_LANE_ST 0x0018 286 #define XGXS_IEEE_TEST_CTL 0x0019 287 288 /******************************/ 289 /* XGXS_M Device (Dev Addr 4) */ 290 /******************************/ 291 292 #define READ_PHY8481_PHYXS_M_REG(_unit, _phy_ctrl, _reg,_val) \ 293 PHY8481_REG_READ((_unit), (_phy_ctrl), \ 294 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PHYXS_M, (_reg)), (_val)) 295 #define WRITE_PHY8481_PHYXS_M_REG(_unit, _phy_ctrl, _reg,_val) \ 296 PHY8481_REG_WRITE((_unit), (_phy_ctrl), \ 297 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PHYXS_M, (_reg)), (_val)) 298 #define MODIFY_PHY8481_PHYXS_M_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 299 PHY8481_REG_MODIFY((_unit), (_phy_ctrl), \ 300 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PHYXS_M, (_reg)), (_val), (_mask)) 301 302 /* Control 1 Register (Addr 0000h) */ 303 #define READ_PHY8481_PHYXS_M_CTRLr(_unit, _phy_ctrl, _val) \ 304 READ_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_CTL1,(_val)) 305 #define WRITE_PHY8481_PHYXS_M_CTRLr(_unit, _phy_ctrl, _val) \ 306 WRITE_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_CTL1,(_val)) 307 #define MODIFY_PHY8481_PHYXS_M_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 308 MODIFY_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_CTL1, (_val), (_mask)) 309 310 /* Status 1 Register (Addr 0001h) */ 311 #define READ_PHY8481_PHYXS_M_STATr(_unit, _phy_ctrl, _val) \ 312 READ_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_ST1,(_val)) 313 #define WRITE_PHY8481_PHYXS_M_STATr(_unit, _phy_ctrl, _val) \ 314 WRITE_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_ST1,(_val)) 315 #define MODIFY_PHY8481_PHYXS_M_STATr(_unit, _phy_ctrl, _val, _mask) \ 316 MODIFY_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_ST1, (_val), (_mask)) 317 318 319 /* PHY Identifier Register 0 (Addr 0002h) */ 320 #define READ_PHY8481_PHYXS_M_ID0r(_unit, _phy_ctrl, _val) \ 321 READ_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_ID0,(_val)) 322 323 /* PHY Identifier Register 1 (Addr 0003h) */ 324 #define READ_PHY8481_PHYXS_M_ID1r(_unit, _phy_ctrl, _val) \ 325 READ_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_ID1,(_val)) 326 327 /* Speed Ability (Addr 0004h) */ 328 /* Device in Package 2 (Addr 0005h) */ 329 /* Device in Package 1 (Addr 0006h) */ 330 /* Status 2 Register (Addr 0008h) */ 331 /* Organizatioally Unique Identifier 0 Register (Addr 000eh) */ 332 /* Organizationally Unique Identifier 1 Register (Addr 000fh) */ 333 /* XGXS Lane Status Register (Addr 0018h) */ 334 335 /* XGXS Lane Status Register (Addr 0018h) */ 336 #define READ_PHY8481_PHYXS_XGXS_M_LANE_STATr(_unit, _phy_ctrl, _val) \ 337 READ_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_LANE_ST,(_val)) 338 #define WRITE_PHY8481_PHYXS_XGXS_M_LANE_STATr(_unit, _phy_ctrl, _val) \ 339 WRITE_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_LANE_ST,(_val)) 340 #define MODIFY_PHY8481_PHYXS_XGXS_M_LANE_STATr(_unit, _phy_ctrl, _val, _mask) \ 341 MODIFY_PHY8481_PHYXS_M_REG((_unit), (_phy_ctrl), XGXS_IEEE_LANE_ST, (_val), (_mask)) 342 343 /* XGXS Test Control Register (Addr 0019h) */ 344 345 #define READ_PHY8481_PHYXS_M_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 346 READ_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8000, (_val)) 347 #define WRITE_PHY8481_PHYXS_M_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 348 WRITE_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8000, (_val)) 349 #define MODIFY_PHY8481_PHYXS_M_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val, _mask) \ 350 MODIFY_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8000, (_val), (_mask)) 351 352 /* Miscellaneous 1 control register */ 353 #define READ_PHY8481_PHYXS_M_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \ 354 READ_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8308, (_val)) 355 #define WRITE_PHY8481_PHYXS_M_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \ 356 WRITE_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8308, (_val)) 357 #define MODIFY_PHY8481_PHYXS_M_SERDESDIGITAL_MISC1r(_unit, _pc, _val, _mask) \ 358 MODIFY_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8308, (_val), (_mask)) 359 360 /* IEEE MII control register */ 361 #define READ_PHY8481_PHYXS_M_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 362 READ_PHY8481_PHYXS_M_REG((_unit), (_pc), 0xffe0, (_val)) 363 #define WRITE_PHY8481_PHYXS_M_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 364 WRITE_PHY8481_PHYXS_M_REG((_unit), (_pc), 0xffe0, (_val)) 365 #define MODIFY_PHY8481_PHYXS_M_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val, _mask) \ 366 MODIFY_PHY8481_PHYXS_M_REG((_unit), (_pc), 0xffe0, (_val), (_mask)) 367 368 /* IEEE MII status register */ 369 #define READ_PHY8481_PHYXS_M_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \ 370 READ_PHY8481_PHYXS_M_REG((_unit), (_pc), 0xffe1, (_val)) 371 #define WRITE_PHY8481_PHYXS_M_COMBO_IEEE0_STATr(_unit, _pc, _val) \ 372 WRITE_PHY8481_PHYXS_M_REG((_unit), (_pc), 0xffe1, (_val)) 373 #define MODIFY_PHY8481_PHYXS_M_COMBO_IEEE0_STATr(_unit, _pc, _val, _mask) \ 374 MODIFY_PHY8481_PHYXS_M_REG((_unit), (_pc), 0xffe1, (_val), (_mask)) 375 376 /* XGXG status register */ 377 #define READ_PHY8481_PHYXS_M_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 378 READ_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8001, (_val)) 379 #define WRITE_PHY8481_PHYXS_M_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 380 WRITE_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8001, (_val)) 381 #define MODIFY_PHY8481_PHYXS_M_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val, _mask) \ 382 MODIFY_PHY8481_PHYXS_M_REG((_unit), (_pc), 0x8001, (_val), (_mask)) 383 384 385 /******************************/ 386 /* XGXS_L Device (Dev Addr 3) */ 387 /******************************/ 388 #define READ_PHY8481_PHYXS_L_REG(_unit, _phy_ctrl, _reg,_val) \ 389 PHY8481_REG_READ((_unit), (_phy_ctrl), \ 390 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PHYXS_L, (_reg)), (_val)) 391 #define WRITE_PHY8481_PHYXS_L_REG(_unit, _phy_ctrl, _reg,_val) \ 392 PHY8481_REG_WRITE((_unit), (_phy_ctrl), \ 393 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PHYXS_L, (_reg)), (_val)) 394 #define MODIFY_PHY8481_PHYXS_L_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 395 PHY8481_REG_MODIFY((_unit), (_phy_ctrl), \ 396 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_PHYXS_L, (_reg)), (_val), (_mask)) 397 398 399 /* Control 1 Register (Addr 0000h) */ 400 #define READ_PHY8481_PHYXS_L_CTRLr(_unit, _phy_ctrl, _val) \ 401 READ_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_CTL1,(_val)) 402 #define WRITE_PHY8481_PHYXS_L_CTRLr(_unit, _phy_ctrl, _val) \ 403 WRITE_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_CTL1,(_val)) 404 #define MODIFY_PHY8481_PHYXS_L_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 405 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_CTL1, (_val), (_mask)) 406 407 /* Status 1 Register (Addr 0001h) */ 408 #define READ_PHY8481_PHYXS_L_STATr(_unit, _phy_ctrl, _val) \ 409 READ_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_ST1,(_val)) 410 #define WRITE_PHY8481_PHYXS_L_STATr(_unit, _phy_ctrl, _val) \ 411 WRITE_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_ST1,(_val)) 412 #define MODIFY_PHY8481_PHYXS_L_STATr(_unit, _phy_ctrl, _val, _mask) \ 413 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_ST1, (_val), (_mask)) 414 415 /* XGXS Lane Status Register (Addr 0018h) */ 416 #define READ_PHY8481_PHYXS_XGXS_L_LANE_STATr(_unit, _phy_ctrl, _val) \ 417 READ_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_LANE_ST,(_val)) 418 #define WRITE_PHY8481_PHYXS_XGXS_L_LANE_STATr(_unit, _phy_ctrl, _val) \ 419 WRITE_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_LANE_ST,(_val)) 420 #define MODIFY_PHY8481_PHYXS_XGXS_L_LANE_STATr(_unit, _phy_ctrl, _val, _mask) \ 421 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_phy_ctrl), XGXS_IEEE_LANE_ST, (_val), (_mask)) 422 423 /* XGXG status 1 register */ 424 425 /* GP_Status :: xgxsStatus1 :: autoneg_complete [07:07] */ 426 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_MASK 0x0080 427 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_ALIGN 0 428 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_BITS 1 429 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_SHIFT 7 430 431 #define READ_PHY8481_PHYXS_L_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \ 432 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008122, (_val)) 433 #define WRITE_PHY8481_PHYXS_L_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \ 434 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008122, (_val)) 435 #define MODIFY_PHY8481_PHYXS_L_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val, _mask) \ 436 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008122, (_val), (_mask)) 437 438 /* 1000X status 1 register */ 439 440 /* GP_Status :: Status1000X1 :: sgmii_mode [00:00] */ 441 #define GP_STATUS_STATUS1000X1_SGMII_MODE_MASK 0x0001 442 #define GP_STATUS_STATUS1000X1_SGMII_MODE_ALIGN 0 443 #define GP_STATUS_STATUS1000X1_SGMII_MODE_BITS 1 444 #define GP_STATUS_STATUS1000X1_SGMII_MODE_SHIFT 0 445 446 #define READ_PHY8481_PHYXS_L_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \ 447 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008124, (_val)) 448 #define WRITE_PHY8481_PHYXS_L_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \ 449 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008124, (_val)) 450 #define MODIFY_PHY8481_PHYXS_L_GP_STATUS_STATUS1000X1r(_unit, _pc, _val, _mask) \ 451 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008124, (_val), (_mask)) 452 453 /* XGXG status 3 register */ 454 455 /* GP_Status :: xgxsStatus3 :: link [15:15] */ 456 #define GP_STATUS_XGXSSTATUS3_LINK_MASK 0x8000 457 #define GP_STATUS_XGXSSTATUS3_LINK_ALIGN 0 458 #define GP_STATUS_XGXSSTATUS3_LINK_BITS 1 459 #define GP_STATUS_XGXSSTATUS3_LINK_SHIFT 15 460 461 #define READ_PHY8481_PHYXS_L_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \ 462 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008129, (_val)) 463 #define WRITE_PHY8481_PHYXS_L_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \ 464 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008129, (_val)) 465 #define MODIFY_PHY8481_PHYXS_L_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val, _mask) \ 466 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008129, (_val), (_mask)) 467 468 /* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 469 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 470 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 471 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 472 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 473 474 #define READ_PHY8481_PHYXS_L_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 475 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000800e, (_val)) 476 #define WRITE_PHY8481_PHYXS_L_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 477 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000800e, (_val)) 478 #define MODIFY_PHY8481_PHYXS_L_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val, _mask) \ 479 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000800e, (_val), (_mask)) 480 481 /* dsc_2_0 :: dsc_ctrl0 :: rxSeqStart [15:15] */ 482 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_MASK 0x8000 483 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_ALIGN 0 484 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_BITS 1 485 #define DSC_2_0_DSC_CTRL0_RXSEQSTART_SHIFT 15 486 487 #define READ_PHY8481_PHYXS_L_RX_ALL_RX_CONTROLr(_unit, _pc, _val) \ 488 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x000080f1, (_val)) 489 #define WRITE_PHY8481_PHYXS_L_RX_ALL_RX_CONTROLr(_unit, _pc, _val) \ 490 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x000080f1, (_val)) 491 #define MODIFY_PHY8481_PHYXS_L_RX_ALL_RX_CONTROLr(_unit, _pc, _val, _mask) \ 492 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x000080f1, (_val), (_mask)) 493 494 /* XgxsBlk0 :: xgxsControl :: start_sequencer [13:13] */ 495 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_MASK 0x2000 496 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_ALIGN 0 497 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_BITS 1 498 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_SHIFT 13 499 500 #define READ_PHY8481_PHYXS_L_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 501 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008000, (_val)) 502 #define WRITE_PHY8481_PHYXS_L_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 503 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008000, (_val)) 504 #define MODIFY_PHY8481_PHYXS_L_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val, _mask) \ 505 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008000, (_val), (_mask)) 506 507 /* SerdesDigital :: Misc1 :: force_speed_sel [04:04] */ 508 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_MASK 0x0010 509 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_ALIGN 0 510 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_BITS 1 511 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SEL_SHIFT 4 512 513 /* SerdesDigital :: Misc1 :: force_speed [03:00] */ 514 #define SERDESDIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 515 #define SERDESDIGITAL_MISC1_FORCE_SPEED_ALIGN 0 516 #define SERDESDIGITAL_MISC1_FORCE_SPEED_BITS 4 517 #define SERDESDIGITAL_MISC1_FORCE_SPEED_SHIFT 0 518 519 /* Miscellaneous 1 control register */ 520 #define READ_PHY8481_PHYXS_L_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \ 521 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008308, (_val)) 522 #define WRITE_PHY8481_PHYXS_L_SERDESDIGITAL_MISC1r(_unit, _pc, _val) \ 523 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008308, (_val)) 524 #define MODIFY_PHY8481_PHYXS_L_SERDESDIGITAL_MISC1r(_unit, _pc, _val, _mask) \ 525 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008308, (_val), (_mask)) 526 527 /* XgxsBlk0 :: xgxsStatus :: txpll_lock [11:11] */ 528 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_MASK 0x0800 529 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_ALIGN 0 530 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_BITS 1 531 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_SHIFT 11 532 533 /* XGXG status register */ 534 #define READ_PHY8481_PHYXS_L_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 535 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008001, (_val)) 536 #define WRITE_PHY8481_PHYXS_L_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 537 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008001, (_val)) 538 #define MODIFY_PHY8481_PHYXS_L_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val, _mask) \ 539 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008001, (_val), (_mask)) 540 541 /* GP_Status :: topANStatus1 :: cl37_autoneg_complete [01:01] */ 542 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK 0x0002 543 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN 0 544 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS 1 545 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT 1 546 547 /* GP_Status :: topANStatus1 :: cl73_autoneg_complete [00:00] */ 548 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK 0x0001 549 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN 0 550 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS 1 551 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT 0 552 553 /* CL73 AN status 1 register */ 554 #define READ_PHY8481_PHYXS_L_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \ 555 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000812b, (_val)) 556 #define WRITE_PHY8481_PHYXS_L_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \ 557 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000812b, (_val)) 558 #define MODIFY_PHY8481_PHYXS_L_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val, _mask) \ 559 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000812b, (_val), (_mask)) 560 561 /* AN link partner user page 1 */ 562 #define READ_PHY8481_PHYXS_L_GP_STATUS_LP_UP1r(_unit, _pc, _val) \ 563 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000812c, (_val)) 564 #define WRITE_PHY8481_PHYXS_L_GP_STATUS_LP_UP1r(_unit, _pc, _val) \ 565 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000812c, (_val)) 566 #define MODIFY_PHY8481_PHYXS_L_GP_STATUS_LP_UP1r(_unit, _pc, _val, _mask) \ 567 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000812c, (_val), (_mask)) 568 569 /* AN73_pdet :: parDet10GControl :: parDet10g_en [00:00] */ 570 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_MASK 0x0001 571 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_ALIGN 0 572 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_BITS 1 573 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_SHIFT 0 574 575 /* SerdesDigital :: Control1000X2 :: enable_parallel_detection [00:00] */ 576 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK 0x0001 577 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN 0 578 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS 1 579 #define SERDESDIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT 0 580 581 /* MP5, Message Page 5, next page control register */ 582 #define READ_PHY8481_PHYXS_L_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \ 583 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008350, (_val)) 584 #define WRITE_PHY8481_PHYXS_L_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \ 585 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008350, (_val)) 586 #define MODIFY_PHY8481_PHYXS_L_BAM_NEXTPAGE_MP5_NEXTPAGECTRLr(_unit, _pc, _val, _mask) \ 587 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008350, (_val), (_mask)) 588 589 /* 10G parallel detect control register */ 590 #define READ_PHY8481_PHYXS_L_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \ 591 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008131, (_val)) 592 #define WRITE_PHY8481_PHYXS_L_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \ 593 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008131, (_val)) 594 #define MODIFY_PHY8481_PHYXS_L_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val, _mask) \ 595 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008131, (_val), (_mask)) 596 597 /* 1000X control 2 register */ 598 #define READ_PHY8481_PHYXS_L_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 599 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008301, (_val)) 600 #define WRITE_PHY8481_PHYXS_L_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 601 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008301, (_val)) 602 #define MODIFY_PHY8481_PHYXS_L_SERDESDIGITAL_CONTROL1000X2r(_unit, _pc, _val, _mask) \ 603 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008301, (_val), (_mask)) 604 605 /* GP_Status :: topANStatus1 :: actual_speed [13:08] */ 606 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_MASK 0x3f00 607 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_ALIGN 0 608 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_BITS 6 609 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_SHIFT 8 610 611 /* GP_Status :: topANStatus1 :: actual_speed [13:08] */ 612 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_MASK 0x3f00 613 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_ALIGN 0 614 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_BITS 6 615 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_SHIFT 8 616 617 /* IEEE MII control register */ 618 #define READ_PHY8481_PHYXS_L_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 619 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe0, (_val)) 620 #define WRITE_PHY8481_PHYXS_L_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 621 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe0, (_val)) 622 #define MODIFY_PHY8481_PHYXS_L_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val, _mask) \ 623 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe0, (_val), (_mask)) 624 625 /* IEEE MII status register */ 626 #define READ_PHY8481_PHYXS_L_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \ 627 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0xffe1, (_val)) 628 #define WRITE_PHY8481_PHYXS_L_COMBO_IEEE0_STATr(_unit, _pc, _val) \ 629 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0xffe1, (_val)) 630 #define MODIFY_PHY8481_PHYXS_L_COMBO_IEEE0_STATr(_unit, _pc, _val, _mask) \ 631 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0xffe1, (_val), (_mask)) 632 633 /* IEEE auto-negotiation advertiesed abilities register */ 634 #define READ_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \ 635 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe4, (_val)) 636 #define WRITE_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \ 637 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe4, (_val)) 638 #define MODIFY_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val, _mask) \ 639 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe4, (_val), (_mask)) 640 641 /* IEEE auto-negotiation link partner abilities register */ 642 #define READ_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \ 643 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe5, (_val)) 644 #define WRITE_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \ 645 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe5, (_val)) 646 #define MODIFY_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val, _mask) \ 647 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe5, (_val), (_mask)) 648 649 /* IEEE auto-negotiation expansion register */ 650 #define READ_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \ 651 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe6, (_val)) 652 #define WRITE_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \ 653 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe6, (_val)) 654 #define MODIFY_PHY8481_PHYXS_L_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val, _mask) \ 655 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x0000ffe6, (_val), (_mask)) 656 657 /* Over1G :: UP1 :: dataRate_10GCX4 [04:04] */ 658 #define OVER1G_UP1_DATARATE_10GCX4_MASK 0x0010 659 #define OVER1G_UP1_DATARATE_10GCX4_ALIGN 0 660 #define OVER1G_UP1_DATARATE_10GCX4_BITS 1 661 #define OVER1G_UP1_DATARATE_10GCX4_SHIFT 4 662 663 /* Over1G :: LP_UP1 :: dataRate_10GCX4 [04:04] */ 664 #define OVER1G_LP_UP1_DATARATE_10GCX4_MASK 0x0010 665 #define OVER1G_LP_UP1_DATARATE_10GCX4_ALIGN 0 666 #define OVER1G_LP_UP1_DATARATE_10GCX4_BITS 1 667 #define OVER1G_LP_UP1_DATARATE_10GCX4_SHIFT 4 668 669 /* AN local device user page 1 */ 670 #define READ_PHY8481_PHYXS_L_OVER1G_UP1r(_unit, _pc, _val) \ 671 READ_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008329, (_val)) 672 #define WRITE_PHY8481_PHYXS_L_OVER1G_UP1r(_unit, _pc, _val) \ 673 WRITE_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008329, (_val)) 674 #define MODIFY_PHY8481_PHYXS_L_OVER1G_UP1r(_unit, _pc, _val, _mask) \ 675 MODIFY_PHY8481_PHYXS_L_REG((_unit), (_pc), 0x00008329, (_val), (_mask)) 676 677 /************************************************/ 678 /* User Defined Registers (Devices 30 and 31) */ 679 /************************************************/ 680 #define READ_PHY8481_TOPLVL1_REG(_unit, _phy_ctrl, _reg,_val) \ 681 PHY8481_REG_READ((_unit), (_phy_ctrl), \ 682 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_TOPLVL1, (_reg)), (_val)) 683 #define WRITE_PHY8481_TOPLVL1_REG(_unit, _phy_ctrl, _reg,_val) \ 684 PHY8481_REG_WRITE((_unit), (_phy_ctrl), \ 685 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_TOPLVL1, (_reg)), (_val)) 686 #define MODIFY_PHY8481_TOPLVL1_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 687 PHY8481_REG_MODIFY((_unit), (_phy_ctrl), \ 688 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_TOPLVL1, (_reg)), (_val), (_mask)) 689 690 #define READ_PHY8481_TOPLVL2_REG(_unit, _phy_ctrl, _reg,_val) \ 691 PHY8481_REG_READ((_unit), (_phy_ctrl), \ 692 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_TOPLVL2, (_reg)), (_val)) 693 #define WRITE_PHY8481_TOPLVL2_REG(_unit, _phy_ctrl, _reg,_val) \ 694 PHY8481_REG_WRITE((_unit), (_phy_ctrl), \ 695 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_TOPLVL2, (_reg)), (_val)) 696 #define MODIFY_PHY8481_TOPLVL2_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 697 PHY8481_REG_MODIFY((_unit), (_phy_ctrl), \ 698 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_TOPLVL2, (_reg)), (_val), (_mask)) 699 700 /* MGBASE-T AN Control Register */ 701 #define MGBASE_AN_CTRL_REG 0x0000 702 #define MGBASE_AN_CTRL_SPEED_5G (1U << 6) 703 #define MGBASE_AN_CTRL_SPEED_2P5G (1U << 5) 704 #define MGBASE_AN_CTRL_ADV_5G_EEE (1U << 4) 705 #define MGBASE_AN_CTRL_ADV_2P5G_EEE (1U << 3) 706 #define MGBASE_AN_CTRL_ADV_5G (1U << 2) 707 #define MGBASE_AN_CTRL_ADV_2P5G (1U << 1) 708 #define MGBASE_AN_CTRL_MG_ENABLE (1U << 0) 709 710 #define PCS_IEEE_CTL1_SPEED_SEL_2P5G 0x7 711 #define PCS_IEEE_CTL1_SPEED_SEL_5G 0x8 712 713 #define MGBASE_AN_CTRL_SPEED_MASK \ 714 (MGBASE_AN_CTRL_SPEED_5G | MGBASE_AN_CTRL_SPEED_2P5G) 715 #define MGBASE_AN_CTRL_ADV_MASK \ 716 (MGBASE_AN_CTRL_ADV_5G | MGBASE_AN_CTRL_ADV_2P5G) 717 718 #define MGBASE_AN_CTRL_SPEED_MASK_LB \ 719 (MGBASE_AN_CTRL_SPEED_2P5G | MGBASE_AN_CTRL_ADV_5G_EEE | MGBASE_AN_CTRL_ADV_2P5G_EEE | MGBASE_AN_CTRL_ADV_5G ) 720 721 #define READ_PHY8481_MGBASET_AN_CTRLr(_unit, _phy_ctrl, _val) \ 722 READ_PHY8481_TOPLVL1_REG( (_unit), (_phy_ctrl), \ 723 MGBASE_AN_CTRL_REG, (_val) ) 724 #define WRITE_PHY8481_MGBASET_AN_CTRLr(_unit, _phy_ctrl, _val) \ 725 WRITE_PHY8481_TOPLVL1_REG( (_unit), (_phy_ctrl), \ 726 MGBASE_AN_CTRL_REG, (_val) ) 727 #define MODIFY_PHY8481_MGBASET_AN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 728 MODIFY_PHY8481_TOPLVL1_REG( (_unit), (_phy_ctrl), \ 729 MGBASE_AN_CTRL_REG, (_val), (_mask) ) 730 731 /* PHY Identifier Register 0 (Addr 0002h) */ 732 #define READ_PHY8481_TOPLVL1_ID0r(_unit, _phy_ctrl, _val) \ 733 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), 0x0002,(_val)) 734 735 /* PHY Identifier Register 1 (Addr 0003h) */ 736 #define READ_PHY8481_TOPLVL1_ID1r(_unit, _phy_ctrl, _val) \ 737 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), 0x0003,(_val)) 738 739 #define PHY8481_SELECT_REGS_CU(_unit, _phy_ctrl) \ 740 { \ 741 if ( !PHY_FORCED_COPPER_MODE((_unit), (_phy_ctrl)->port)) { \ 742 SOC_IF_ERROR_RETURN \ 743 (WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), 0x4111, 0x0003)); \ 744 } \ 745 } 746 747 #define PHY8481_SELECT_REGS_XAUI_8481(_unit, _phy_ctrl) \ 748 { \ 749 SOC_IF_ERROR_RETURN \ 750 (WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), 0x4111, 0x2004)); \ 751 } 752 753 754 #define PHY8481_SELECT_REGS_XAUI_8482X(_unit, _phy_ctrl) \ 755 { \ 756 SOC_IF_ERROR_RETURN \ 757 (WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), 0x4111, 0x3008)); \ 758 } 759 760 761 #define PHY8481_SELECT_REGS_XAUI(_unit, _phy_ctrl) \ 762 { \ 763 if (PHY_FORCED_COPPER_MODE((_unit), (_phy_ctrl)->port)) { \ 764 return SOC_E_CONFIG; \ 765 } \ 766 if (((_phy_ctrl)->phy_model == PHY_BCM84823_MODEL) || \ 767 ((_phy_ctrl)->phy_model == PHY_BCM84821_MODEL)) { \ 768 PHY8481_SELECT_REGS_XAUI_8482X((_unit), (_phy_ctrl)) \ 769 } else {\ 770 PHY8481_SELECT_REGS_XAUI_8481((_unit), (_phy_ctrl)) \ 771 } \ 772 } 773 774 /***************************************/ 775 /* Auto-Neotiation device (Dev Addr 7) */ 776 /***************************************/ 777 778 #define READ_PHY8481_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 779 PHY8481_REG_READ((_unit), (_phy_ctrl), \ 780 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_AN, (_reg)), (_val)) 781 #define WRITE_PHY8481_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 782 PHY8481_REG_WRITE((_unit), (_phy_ctrl), \ 783 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_AN, (_reg)), (_val)) 784 #define MODIFY_PHY8481_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 785 PHY8481_REG_MODIFY((_unit), (_phy_ctrl), \ 786 SOC_PHY_CLAUSE45_ADDR(PHY8481_C45_DEV_AN, (_reg)), (_val), (_mask)) 787 788 /* autoneg control register */ 789 #define AN_IEEE_CTRL_REG 0x0000 790 #define AN_IEEE_CTRL_REG_AN_RESET (1U << 15) 791 #define AN_IEEE_CTRL_REG_EXT_NXT_PAGE (1U << 13) 792 #define AN_IEEE_CTRL_REG_AN_ENA (1U << 12) 793 #define AN_IEEE_CTRL_REG_AN_RESTART (1U << 9) 794 #define AN_IEEE_CTRL_REG_AN_ENA_RESTART \ 795 (AN_IEEE_CTRL_REG_AN_ENA | AN_IEEE_CTRL_REG_AN_RESTART) 796 797 /* AutoNeg control/status registers */ 798 #define AN_IEEE_STATUS_REG 0x0001 799 #define AN_IEEE_STATUS_REG_AN_DONE (1U << 5) 800 801 802 #define AN_IEEE_DEV_ID_LSB 0x0002 /* Auto Neg Device Identifier Lower 16 bit */ 803 #define AN_IEEE_DEV_ID_MSB 0x0003 /* Auto Neg Device Identifier Upper 16 bit */ 804 #define AN_IEEE_DEV_IN_PKG_LSB 0x0005 /* Auto Neg Device In Package Lower 16 bit */ 805 #define AN_IEEE_DEV_IN_PKG_MSB 0x0006 /* Auto Neg Device In Package Upper 16 bit */ 806 #define AN_IEEE_DEV_PKG_ID_LSB 0x000e /* Auto Neg Package ID Lower 16 bit */ 807 #define AN_IEEE_DEV_PKG_ID_MSB 0x000f /* Auto Neg Package ID Upper 16 bit */ 808 #define AN_IEEE_AD 0x0010 /* Auto Neg Advertisement */ 809 #define AN_IEEE_ADB 0x0011 /* */ 810 #define AN_IEEE_ADC 0x0012 /* */ 811 #define AN_IEEE_LPA 0x0013 /* */ 812 #define AN_IEEE_LPB 0x0014 /* */ 813 #define AN_IEEE_LPC 0x0015 /* */ 814 #define AN_IEEE_XNPA 0x0016 /* */ 815 #define AN_IEEE_XNPB 0x0017 /* */ 816 #define AN_IEEE_XNPC 0x0018 /* */ 817 #define LP_IEEE_XNPA 0x0019 /* Link Partners A Extended Next Page */ 818 #define LP_IEEE_XNPB 0x001a /* Link Partners B Extended Next Page */ 819 #define LP_IEEE_XNPC 0x001b /* Link Partners C Extended Next Page */ 820 821 #define TENG_IEEE_AN_CTRL 0x0020 /* 10G Base-T AN Control Register */ 822 #define TENG_IEEE_AN_CTRL_10GBT (1U<<12) 823 #define TENG_IEEE_AN_CTRL_5GBT (1U<<8) 824 #define TENG_IEEE_AN_CTRL_2p5GBT (1U<<7) 825 826 #define TENG_IEEE_AN_STAT 0x0021 /* 10G Base-T AN Status Register */ 827 #define TENG_IEEE_AN_STAT_LP_10GBT (1U<<11) 828 829 /* Control 1 Register (Addr 0000h) */ 830 #define READ_PHY8481_AN_CTRLr(_unit, _phy_ctrl, _val) \ 831 READ_PHY8481_AN_REG((_unit), (_phy_ctrl), AN_IEEE_CTRL_REG,(_val)) 832 #define WRITE_PHY8481_AN_CTRLr(_unit, _phy_ctrl, _val) \ 833 WRITE_PHY8481_AN_REG((_unit), (_phy_ctrl), AN_IEEE_CTRL_REG,(_val)) 834 #define MODIFY_PHY8481_AN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 835 MODIFY_PHY8481_AN_REG((_unit), (_phy_ctrl), AN_IEEE_CTRL_REG, (_val), (_mask)) 836 837 838 /* Status 1 Register (Addr 0001h) */ 839 #define READ_PHY8481_AN_STATr(_unit, _phy_ctrl, _val) \ 840 READ_PHY8481_AN_REG((_unit), (_phy_ctrl), AN_IEEE_STATUS_REG,(_val)) 841 #define WRITE_PHY8481_AN_STATr(_unit, _phy_ctrl, _val) \ 842 WRITE_PHY8481_AN_REG((_unit), (_phy_ctrl), AN_IEEE_STATUS_REG,(_val)) 843 #define MODIFY_PHY8481_AN_STATr(_unit, _phy_ctrl, _val, _mask) \ 844 MODIFY_PHY8481_AN_REG((_unit), (_phy_ctrl), AN_IEEE_STATUS_REG, (_val), (_mask)) 845 846 847 /* 10G AN Control Register (Addr 0020h) */ 848 #define READ_PHY8481_TENG_AN_CTRLr(_unit, _phy_ctrl, _val) \ 849 READ_PHY8481_AN_REG((_unit), (_phy_ctrl), TENG_IEEE_AN_CTRL,(_val)) 850 #define WRITE_PHY8481_TENG_AN_CTRLr(_unit, _phy_ctrl, _val) \ 851 WRITE_PHY8481_AN_REG((_unit), (_phy_ctrl), TENG_IEEE_AN_CTRL,(_val)) 852 #define MODIFY_PHY8481_TENG_AN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 853 MODIFY_PHY8481_AN_REG((_unit), (_phy_ctrl), TENG_IEEE_AN_CTRL, (_val), (_mask)) 854 855 856 /* 10G Status Register (Addr 0021h) */ 857 #define READ_PHY8481_TENG_AN_STATr(_unit, _phy_ctrl, _val) \ 858 READ_PHY8481_AN_REG((_unit), (_phy_ctrl), TENG_IEEE_AN_STAT,(_val)) 859 #define WRITE_PHY8481_TENG_AN_STATr(_unit, _phy_ctrl, _val) \ 860 WRITE_PHY8481_AN_REG((_unit), (_phy_ctrl), TENG_IEEE_AN_STAT,(_val)) 861 #define MODIFY_PHY8481_TENG_AN_STATr(_unit, _phy_ctrl, _val, _mask) \ 862 MODIFY_PHY8481_AN_REG((_unit), (_phy_ctrl), TENG_IEEE_AN_STAT, (_val), (_mask)) 863 864 /* EEE Advertisement Register (Addr 003ch) */ 865 #define READ_PHY8481_EEE_ADVr(_unit, _phy_ctrl, _val) \ 866 READ_PHY8481_AN_REG((_unit), (_phy_ctrl), 0x3c,(_val)) 867 #define WRITE_PHY8481_EEE_ADVr(_unit, _phy_ctrl, _val) \ 868 WRITE_PHY8481_AN_REG((_unit), (_phy_ctrl), 0x3c,(_val)) 869 #define MODIFY_PHY8481_EEE_ADVr(_unit, _phy_ctrl, _val, _mask) \ 870 MODIFY_PHY8481_AN_REG((_unit), (_phy_ctrl), 0x3c, (_val), (_mask)) 871 872 /* EEE Link Partner Advertisement Register (Addr 003dh) */ 873 #define READ_PHY8481_EEE_LPABILr(_unit, _phy_ctrl, _val) \ 874 READ_PHY8481_AN_REG((_unit), (_phy_ctrl), 0x3d,(_val)) 875 #define WRITE_PHY8481_EEE_LPABILr(_unit, _phy_ctrl, _val) \ 876 WRITE_PHY8481_AN_REG((_unit), (_phy_ctrl), 0x3d,(_val)) 877 #define MODIFY_PHY8481_EEE_LPABILr(_unit, _phy_ctrl, _val, _mask) \ 878 MODIFY_PHY8481_AN_REG((_unit), (_phy_ctrl), 0x3d, (_val), (_mask)) 879 880 /* 10/100/1000-BaseT regs */ 881 882 /* PHY register access */ 883 #if 0 884 #define PHY8481_D7_FFXX_REG_VERIFY(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr) \ 885 do {\ 886 uint16 v1,v2; \ 887 phy_reg_xge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 888 PHY8481_C45_DEV_AN,(_reg_addr), (&v1)); \ 889 phy_8481_reg_xge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 890 PHY8481_C45_DEV_AN,(_reg_addr), (&v2)); \ 891 if (v1 != v2) { 892 soc_cm_print(" u/p/b/r=%d/%d/%08x/%08x val mismatch ( %x != %x ) \n", \ 893 unit , (_phy_ctrl)->port, (_reg_bank), (_reg_addr), v1, v2); \ 894 } \ 895 } while (0); 896 #else 897 #define PHY8481_D7_FFXX_REG_VERIFY(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr) 898 #endif 899 900 #define PHY8481_D7_FFXX_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 901 phy_8481_reg_xge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 902 PHY8481_C45_DEV_AN,(_reg_addr), (_val)) 903 #define PHY8481_D7_FFXX_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 904 phy_8481_reg_xge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 905 PHY8481_C45_DEV_AN,(_reg_addr), (_val)) 906 #define PHY8481_D7_FFXX_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr,_val, _mask) \ 907 phy_8481_reg_xge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 908 PHY8481_C45_DEV_AN,(_reg_addr), (_val), (_mask)) 909 910 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr FFE0h) */ 911 #define READ_PHY8481_MII_CTRLr(_unit, _phy_ctrl, _val) \ 912 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe0, (_val)) 913 #define WRITE_PHY8481_MII_CTRLr(_unit, _phy_ctrl, _val) \ 914 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe0, (_val)) 915 #define MODIFY_PHY8481_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 916 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe0, \ 917 (_val), (_mask)) 918 #define PHY8481_MII_CTRL_LOOPBACK_100M 0x7100 919 #define PHY8481_MII_CTRL_LOOPBACK_1G 0x5140 920 921 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR FFE1h) */ 922 #define READ_PHY8481_MII_STATr(_unit, _phy_ctrl, _val) \ 923 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe1, (_val)) 924 #define WRITE_PHY8481_MII_STATr(_unit, _phy_ctrl, _val) \ 925 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe1, (_val)) 926 #define MODIFY_PHY8481_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 927 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe1, \ 928 (_val), (_mask)) 929 930 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR FFE2h) */ 931 #define READ_PHY8481_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 932 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe2, (_val)) 933 #define WRITE_PHY8481_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 934 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe2, (_val)) 935 #define MODIFY_PHY8481_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 936 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe2, \ 937 (_val), (_mask)) 938 939 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR FFE3h) */ 940 #define READ_PHY8481_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 941 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe3, (_val)) 942 #define WRITE_PHY8481_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 943 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe3, (_val)) 944 #define MODIFY_PHY8481_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 945 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe3, \ 946 (_val), (_mask)) 947 948 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR FFE4h) */ 949 #define READ_PHY8481_MII_ANAr(_unit, _phy_ctrl, _val) \ 950 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe4, (_val)) 951 #define WRITE_PHY8481_MII_ANAr(_unit, _phy_ctrl, _val) \ 952 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe4, (_val)) 953 #define MODIFY_PHY8481_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 954 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe4, \ 955 (_val), (_mask)) 956 957 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR FFE5h) */ 958 #define READ_PHY8481_MII_ANPr(_unit, _phy_ctrl, _val) \ 959 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe5, (_val)) 960 #define WRITE_PHY8481_MII_ANPr(_unit, _phy_ctrl, _val) \ 961 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe5, (_val)) 962 #define MODIFY_PHY8481_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 963 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe5, \ 964 (_val), (_mask)) 965 966 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR FFE6h) */ 967 #define READ_PHY8481_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 968 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe6, (_val)) 969 #define WRITE_PHY8481_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 970 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe6, (_val)) 971 #define MODIFY_PHY8481_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 972 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe6, \ 973 (_val), (_mask)) 974 975 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR FFE7h) */ 976 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR FFE8h) */ 977 978 /* 1000BASE-T Control Register (ADDR FFE9h) */ 979 #define READ_PHY8481_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 980 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe9, (_val)) 981 #define WRITE_PHY8481_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 982 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe9, (_val)) 983 #define MODIFY_PHY8481_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 984 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffe9, \ 985 (_val), (_mask)) 986 987 /* 1000BASE-T Status Register (ADDR FFEAh) */ 988 #define READ_PHY8481_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 989 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffea, (_val)) 990 #define WRITE_PHY8481_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 991 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffea, (_val)) 992 #define MODIFY_PHY8481_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 993 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffea, \ 994 (_val), (_mask)) 995 996 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR FFEFh) */ 997 #define READ_PHY8481_MII_ESRr(_unit, _phy_ctrl, _val) \ 998 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffef, (_val)) 999 #define WRITE_PHY8481_MII_ESRr(_unit, _phy_ctrl, _val) \ 1000 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffef, (_val)) 1001 #define MODIFY_PHY8481_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 1002 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xffef, \ 1003 (_val), (_mask)) 1004 1005 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR FFF0h) */ 1006 #define READ_PHY8481_PHY_ECRr(_unit, _phy_ctrl, _val) \ 1007 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff0, (_val)) 1008 #define WRITE_PHY8481_PHY_ECRr(_unit, _phy_ctrl, _val) \ 1009 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff0, (_val)) 1010 #define MODIFY_PHY8481_PHY_ECRr(_unit, _phy_ctrl, _val, _mask) \ 1011 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff0, \ 1012 (_val), (_mask)) 1013 1014 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR FFF1h) */ 1015 #define READ_PHY8481_PHY_ESRr(_unit, _phy_ctrl, _val) \ 1016 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff1, (_val)) 1017 #define WRITE_PHY8481_PHY_ESRr(_unit, _phy_ctrl, _val) \ 1018 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff1, (_val)) 1019 #define MODIFY_PHY8481_PHY_ESRr(_unit, _phy_ctrl, _val, _mask) \ 1020 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff1, \ 1021 (_val), (_mask)) 1022 1023 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR FFF2h) */ 1024 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR FFF3h) */ 1025 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR FFF4h) */ 1026 1027 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR FFF8h Shadow 000)*/ 1028 #define READ_PHY8481_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 1029 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff8, (_val)) 1030 #define WRITE_PHY8481_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 1031 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff8, (_val)) 1032 #define MODIFY_PHY8481_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1033 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfff8, \ 1034 (_val), (_mask)) 1035 1036 /* 10BASE-T Register (ADDR FFF8h Shadow 001) */ 1037 #define READ_PHY8481_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 1038 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0xfff8, (_val)) 1039 #define WRITE_PHY8481_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 1040 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0xfff8, (_val)) 1041 #define MODIFY_PHY8481_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 1042 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0xfff8, \ 1043 (_val), (_mask)) 1044 1045 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR FFF8h Shadow 010)*/ 1046 #define READ_PHY8481_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 1047 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0xfff8, (_val)) 1048 #define WRITE_PHY8481_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 1049 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0xfff8, (_val)) 1050 #define MODIFY_PHY8481_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1051 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0xfff8, \ 1052 (_val), (_mask)) 1053 1054 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR FFF8h Shadow 100) */ 1055 #define READ_PHY8481_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 1056 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0xfff8, (_val)) 1057 #define WRITE_PHY8481_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 1058 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0xfff8, (_val)) 1059 #define MODIFY_PHY8481_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 1060 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0xfff8, \ 1061 (_val), (_mask)) 1062 1063 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR FFF8h Shadow 111)*/ 1064 #define READ_PHY8481_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 1065 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0xfff8, (_val)) 1066 #define WRITE_PHY8481_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 1067 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0xfff8, (_val)) 1068 #define MODIFY_PHY8481_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1069 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0xfff8, \ 1070 (_val), (_mask)) 1071 1072 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR FFF9h) */ 1073 1074 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR FFFAh) */ 1075 #define READ_PHY8481_INT_STATr(_unit, _phy_ctrl, _val) \ 1076 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfffa, (_val)) 1077 #define WRITE_PHY8481_INT_STATr(_unit, _phy_ctrl, _val) \ 1078 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfffa, (_val)) 1079 #define MODIFY_PHY8481_INT_STATr(_unit, _phy_ctrl, _val, _mask) \ 1080 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfffa, \ 1081 (_val), (_mask)) 1082 1083 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR FFFBh) */ 1084 1085 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR FFFCh shadow 00010) */ 1086 #define READ_PHY8481_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 1087 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0xfffc, (_val)) 1088 #define WRITE_PHY8481_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 1089 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0xfffc, (_val)) 1090 #define MODIFY_PHY8481_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1091 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0xfffc, \ 1092 (_val), (_mask)) 1093 1094 /* 1000BASE-T/100BASE-TX/10BASE-T Clk Alignment Ctrl (ADDR FFFCh shadow 00011) */ 1095 #define READ_PHY8481_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 1096 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0003, 0xfffc, (_val)) 1097 #define WRITE_PHY8481_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 1098 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0003, 0xfffc, (_val)) 1099 #define MODIFY_PHY8481_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1100 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0xfffc, \ 1101 (_val), (_mask)) 1102 1103 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR FFFCh shadow 00100) */ 1104 #define READ_PHY8481_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 1105 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0xfffc, (_val)) 1106 #define WRITE_PHY8481_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 1107 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0xfffc, (_val)) 1108 #define MODIFY_PHY8481_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 1109 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0xfffc, \ 1110 (_val), (_mask)) 1111 1112 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR FFFCh shadow 00101) */ 1113 #define READ_PHY8481_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 1114 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0xfffc, (_val)) 1115 #define WRITE_PHY8481_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 1116 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0xfffc, (_val)) 1117 #define MODIFY_PHY8481_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 1118 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0xfffc, \ 1119 (_val), (_mask)) 1120 1121 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR FFFCh shadow 01000) */ 1122 #define READ_PHY8481_LED_STATr(_unit, _phy_ctrl, _val) \ 1123 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0xfffc, (_val)) 1124 #define WRITE_PHY8481_LED_STATr(_unit, _phy_ctrl, _val) \ 1125 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0xfffc, (_val)) 1126 #define MODIFY_PHY8481_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 1127 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0xfffc, \ 1128 (_val), (_mask)) 1129 1130 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR FFFCh shadow 01001) */ 1131 #define READ_PHY8481_LED_CTRLr(_unit, _phy_ctrl, _val) \ 1132 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0xfffc, (_val)) 1133 #define WRITE_PHY8481_LED_CTRLr(_unit, _phy_ctrl, _val) \ 1134 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0xfffc, (_val)) 1135 #define MODIFY_PHY8481_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1136 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0xfffc, \ 1137 (_val), (_mask)) 1138 1139 /* Auto Power-Down Reg (ADDR FFFCh shadow 01010) */ 1140 #define READ_PHY8481_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 1141 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0xfffc, (_val)) 1142 #define WRITE_PHY8481_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 1143 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0xfffc, (_val)) 1144 #define MODIFY_PHY8481_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 1145 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0xfffc, \ 1146 (_val), (_mask)) 1147 1148 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR FFFCh shadow 01101) */ 1149 #define READ_PHY8481_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 1150 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0xfffc, (_val)) 1151 #define WRITE_PHY8481_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 1152 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0xfffc, (_val)) 1153 #define MODIFY_PHY8481_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 1154 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0xfffc, \ 1155 (_val), (_mask)) 1156 1157 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR FFFCh shadow 01110) */ 1158 #define READ_PHY8481_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 1159 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0xfffc, (_val)) 1160 #define WRITE_PHY8481_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 1161 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0xfffc, (_val)) 1162 #define MODIFY_PHY8481_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 1163 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0xfffc, \ 1164 (_val), (_mask)) 1165 1166 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR FFFCh shadow 01111) */ 1167 #define READ_PHY8481_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 1168 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000f, 0xfffc, (_val)) 1169 #define WRITE_PHY8481_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 1170 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000f, 0xfffc, (_val)) 1171 #define MODIFY_PHY8481_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1172 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000f, 0xfffc, \ 1173 (_val), (_mask)) 1174 1175 /* SerDes 100BASE-FX Status Reg (ADDR FFFCh shadow 10001) */ 1176 #define READ_PHY8481_100FX_STATr(_unit, _phy_ctrl, _val) \ 1177 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0011, 0xfffc, (_val)) 1178 #define WRITE_PHY8481_100FX_STATr(_unit, _phy_ctrl, _val) \ 1179 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0011, 0xfffc, (_val)) 1180 #define MODIFY_PHY8481_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 1181 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0011, 0xfffc, \ 1182 (_val), (_mask)) 1183 1184 /* SerDes 100BASE-FX Control Reg (ADDR FFFCh shadow 10011) */ 1185 #define READ_PHY8481_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 1186 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0xfffc, (_val)) 1187 #define WRITE_PHY8481_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 1188 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0xfffc, (_val)) 1189 #define MODIFY_PHY8481_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1190 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0xfffc, \ 1191 (_val), (_mask)) 1192 1193 /* Secondary SerDes Control Reg (ADDR FFFCh shadow 10100) */ 1194 #define READ_PHY8481_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 1195 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0014, 0xfffc, (_val)) 1196 #define WRITE_PHY8481_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 1197 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0014, 0xfffc, (_val)) 1198 #define MODIFY_PHY8481_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1199 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0014, 0xfffc, \ 1200 (_val), (_mask)) 1201 1202 /* SGMII Slave Reg (ADDR FFFCh shadow 10101) */ 1203 #define READ_PHY8481_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 1204 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0xfffc, (_val)) 1205 #define WRITE_PHY8481_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 1206 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0xfffc, (_val)) 1207 #define MODIFY_PHY8481_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 1208 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0xfffc, \ 1209 (_val), (_mask)) 1210 1211 /* Primary SerDes Control Reg (ADDR FFFCh shadow 10110) */ 1212 #define READ_PHY8481_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 1213 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0xfffc, (_val)) 1214 #define WRITE_PHY8481_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 1215 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0xfffc, (_val)) 1216 #define MODIFY_PHY8481_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 1217 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0xfffc, \ 1218 (_val), (_mask)) 1219 1220 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR FFFCh shadow 11000) */ 1221 #define READ_PHY8481_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 1222 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0xfffc, (_val)) 1223 #define WRITE_PHY8481_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 1224 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0xfffc, (_val)) 1225 #define MODIFY_PHY8481_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 1226 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0xfffc, \ 1227 (_val), (_mask)) 1228 1229 /* 1000BASE-X Auto-neg Debug Reg (ADDR FFFCh shadow 11010) */ 1230 #define READ_PHY8481_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 1231 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001a, 0xfffc, (_val)) 1232 #define WRITE_PHY8481_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 1233 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001a, 0xfffc, (_val)) 1234 #define MODIFY_PHY8481_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 1235 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001a, 0xfffc, \ 1236 (_val), (_mask)) 1237 1238 /* Auxiliary 1000BASE-X Control Reg (ADDR FFFCh shadow 11011) */ 1239 #define READ_PHY8481_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 1240 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001b, 0xfffc, (_val)) 1241 #define WRITE_PHY8481_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 1242 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001b, 0xfffc, (_val)) 1243 #define MODIFY_PHY8481_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1244 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001b, 0xfffc, \ 1245 (_val), (_mask)) 1246 1247 /* Auxiliary 1000BASE-X Status Reg (ADDR FFFCh shadow 11100) */ 1248 #define READ_PHY8481_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 1249 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001c, 0xfffc, (_val)) 1250 #define WRITE_PHY8481_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 1251 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001c, 0xfffc, (_val)) 1252 #define MODIFY_PHY8481_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 1253 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001c, 0xfffc, \ 1254 (_val), (_mask)) 1255 1256 /* Misc 1000BASE-X Status Reg (ADDR FFFCh shadow 11101) */ 1257 #define READ_PHY8481_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 1258 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001d, 0xfffc, (_val)) 1259 #define WRITE_PHY8481_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 1260 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001d, 0xfffc, (_val)) 1261 #define MODIFY_PHY8481_MISC_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 1262 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001d, 0xfffc, \ 1263 (_val), (_mask)) 1264 1265 /* Copper/Fiber Auto-Detect Medium Reg (ADDR FFFCh shadow 11110) */ 1266 #define READ_PHY8481_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 1267 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001e, 0xfffc, (_val)) 1268 #define WRITE_PHY8481_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 1269 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001e, 0xfffc, (_val)) 1270 #define MODIFY_PHY8481_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val, _mask) \ 1271 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001e, 0xfffc, \ 1272 (_val), (_mask)) 1273 1274 /* Mode Control Reg (ADDR FFFCh shadow 11111) */ 1275 #define READ_PHY8481_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 1276 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001f, 0xfffc, (_val)) 1277 #define WRITE_PHY8481_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 1278 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001f, 0xfffc, (_val)) 1279 #define MODIFY_PHY8481_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1280 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001f, 0xfffc, \ 1281 (_val), (_mask)) 1282 1283 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR FFFDh bit 15 = 0) */ 1284 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR FFFDh bit 15 = 1) */ 1285 1286 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR FFFeh) */ 1287 #define READ_PHY8481_TEST1r(_unit, _phy_ctrl, _val) \ 1288 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfffe, (_val)) 1289 #define WRITE_PHY8481_TEST1r(_unit, _phy_ctrl, _val) \ 1290 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfffe, (_val)) 1291 #define MODIFY_PHY8481_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 1292 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0xfffe, \ 1293 (_val), (_mask)) 1294 1295 1296 /* +-------------------------+ 1297 * | | 1298 * | Expansion Registers | 1299 * | | 1300 * +-------------------------+ 1301 */ 1302 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 1303 #define READ_PHY8481_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 1304 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f00, 0xfff5, (_val)) 1305 #define WRITE_PHY8481_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 1306 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f00, \ 1307 0xfff5, (_val)) 1308 #define MODIFY_PHY8481_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 1309 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f00, \ 1310 0xfff5, (_val), (_mask)) 1311 1312 /* Expansion Interrupt Status Register (Addr 01h) */ 1313 #define READ_PHY8481_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 1314 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f01, 0xfff5, (_val)) 1315 #define WRITE_PHY8481_EXP_INTERRUPT_STAT_r(_unit, _phy_ctrl, _val) \ 1316 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f01, \ 1317 0xfff5, (_val)) 1318 #define MODIFY_PHY8481_EXP_INTERRUPT_STAT_r(_unit, _phy_ctrl, _val, _mask) \ 1319 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f01, \ 1320 0xfff5, (_val), (_mask)) 1321 1322 /* Expansion Interrupt Mask Register (Addr 02h) */ 1323 #define READ_PHY8481_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 1324 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f02, 0xfff5, (_val)) 1325 #define WRITE_PHY8481_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 1326 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f02, \ 1327 0xfff5, (_val)) 1328 #define MODIFY_PHY8481_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 1329 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f02, \ 1330 0xfff5, (_val), (_mask)) 1331 1332 /* Expansion Interrupt Mask Register (Addr 09h) */ 1333 #define READ_PHY8481_EXP_AMRR_CTRLr(_unit, _phy_ctrl, _val) \ 1334 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f09, 0xfff5, (_val)) 1335 #define WRITE_PHY8481_EXP_AMRR_CTRLr(_unit, _phy_ctrl, _val) \ 1336 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f09, \ 1337 0xfff5, (_val)) 1338 #define MODIFY_PHY8481_EXP_AMRR_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 1339 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f09, \ 1340 0xfff5, (_val), (_mask)) 1341 1342 /* Expansion Pattern Generator Register (Addr 46h) */ 1343 #define READ_PHY8481_EXP_PATTERN_GENr(_unit, _phy_ctrl, _val) \ 1344 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f46, 0xfff5, (_val)) 1345 #define WRITE_PHY8481_EXP_PATTERN_GENr(_unit, _phy_ctrl, _val) \ 1346 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f46, \ 1347 0xfff5, (_val)) 1348 #define MODIFY_PHY8481_EXP_PATTERN_GENr(_unit, _phy_ctrl, _val, _mask) \ 1349 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f46, \ 1350 0xfff5, (_val), (_mask)) 1351 1352 /* Expansion 1G EEE Register (Addr faf) */ 1353 #define READ_PHY8481_1G_EEE_STATISTICS_CTLr(_unit, _phy_ctrl, _val) \ 1354 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), 0x00, 0xfaf, 0xfff5, (_val)) 1355 #define MODIFY_PHY8481_1G_EEE_STATISTICS_CTLr(_unit, _phy_ctrl, _val, _mask) \ 1356 PHY8481_D7_FFXX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0xfaf, \ 1357 0xfff5, (_val), (_mask)) 1358 #define WRITE_PHY8481_1G_EEE_STATISTICS_CTLr(_unit, _phy_ctrl, _val) \ 1359 PHY8481_D7_FFXX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0xfaf, \ 1360 0xfff5, (_val)) 1361 1362 /* Expansion Transmit Event Register (Addr fac) */ 1363 #define READ_PHY8481_EXP_1G_TX_EVENT(_unit, _phy_ctrl, _val) \ 1364 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), PHY8481_DUMMY_ACCESS_FLAG, 0xfac, 0xfff5, (_val)) 1365 1366 /* Expansion Receive Event Register (Addr fad) */ 1367 #define READ_PHY8481_EXP_1G_RX_EVENT(_unit, _phy_ctrl, _val) \ 1368 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), PHY8481_DUMMY_ACCESS_FLAG, 0xfad, 0xfff5, (_val)) 1369 1370 /* Expansion Receive Duration Register (Addr faa) */ 1371 #define READ_PHY8481_EXP_1G_RX_DURATION(_unit, _phy_ctrl, _val) \ 1372 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), PHY8481_DUMMY_ACCESS_FLAG, 0xfaa, 0xfff5, (_val)) 1373 1374 /* Expansion Transmit Duration Register (Addr fab) */ 1375 #define READ_PHY8481_EXP_1G_TX_DURATION(_unit, _phy_ctrl, _val) \ 1376 PHY8481_D7_FFXX_REG_READ((_unit), (_phy_ctrl), PHY8481_DUMMY_ACCESS_FLAG, 0xfab, 0xfff5, (_val)) 1377 1378 /**************************************************************************** 1379 * CHIP_10G_REG16_100SPC_XGP 1380 */ 1381 #define XGP_PD_DEF_REG_02 0x4102 /* "prtad/devad definition register 02" */ 1382 #define XGP_PD_DEF_REG_06 0x4106 /* "prtad/devad definition register 06" */ 1383 1384 /* XGP :: pd_def_reg_00 :: prtad [09:05] */ 1385 #define XGP_PD_DEF_REG_06_PRTAD_MASK 0x03e0 1386 #define XGP_PD_DEF_REG_06_PRTAD_ALIGN 0 1387 #define XGP_PD_DEF_REG_06_PRTAD_BITS 5 1388 #define XGP_PD_DEF_REG_06_PRTAD_SHIFT 5 1389 1390 /* XGP_PD_DEF_REG_02 (Addr 4102h) */ 1391 #define READ_PHY8481_XGP_PD_DEF_REG_02(_unit, _phy_ctrl, _val) \ 1392 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XGP_PD_DEF_REG_02,(_val)) 1393 1394 #define WRITE_PHY8481_XGP_PD_DEF_REG_02(_unit, _phy_ctrl, _val) \ 1395 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XGP_PD_DEF_REG_02,(_val)) 1396 1397 #define MODIFY_PHY8481_XGP_PD_DEF_REG_02(_unit, _phy_ctrl, _val, _mask) \ 1398 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XGP_PD_DEF_REG_02,(_val),(_mask)) 1399 1400 1401 /* XGP_PD_DEF_REG_06 (Addr 4106h) */ 1402 #define READ_PHY8481_XGP_PD_DEF_REG_06(_unit, _phy_ctrl, _val) \ 1403 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XGP_PD_DEF_REG_06,(_val)) 1404 1405 #define WRITE_PHY8481_XGP_PD_DEF_REG_06(_unit, _phy_ctrl, _val) \ 1406 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XGP_PD_DEF_REG_06,(_val)) 1407 1408 #define MODIFY_PHY8481_XGP_PD_DEF_REG_06(_unit, _phy_ctrl, _val, _mask) \ 1409 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XGP_PD_DEF_REG_06,(_val),(_mask)) 1410 1411 1412 #define WRITE_PHY8481_XGP_PD_DEF_REG_06_PRTAD(_unit, _phy_ctrl, _val) \ 1413 MODIFY_PHY8481_XGP_PD_DEF_REG_06(_unit, _phy_ctrl, \ 1414 (_val)<<XGP_PD_DEF_REG_06_PRTAD_SHIFT, XGP_PD_DEF_REG_06_PRTAD_MASK) 1415 1416 1417 1418 #define XAUI1_MDIO_CTL_REG 0x4080 1419 #define XAUI2_MDIO_CTL_REG 0x4090 1420 1421 1422 /**************************************************************************** 1423 * xaui1 :: mdio_ctl 1424 */ 1425 /* xaui1 :: mdio_ctl :: reserved0 [15:13] */ 1426 #define XAUI1_MDIO_CTL_RESERVED0_MASK 0xe000 1427 #define XAUI1_MDIO_CTL_RESERVED0_ALIGN 0 1428 #define XAUI1_MDIO_CTL_RESERVED0_BITS 3 1429 #define XAUI1_MDIO_CTL_RESERVED0_SHIFT 13 1430 1431 /* xaui1 :: mdio_ctl :: remotemdioreq [12:12] */ 1432 #define XAUI1_MDIO_CTL_REMOTEMDIOREQ_MASK 0x1000 1433 #define XAUI1_MDIO_CTL_REMOTEMDIOREQ_ALIGN 0 1434 #define XAUI1_MDIO_CTL_REMOTEMDIOREQ_BITS 1 1435 #define XAUI1_MDIO_CTL_REMOTEMDIOREQ_SHIFT 12 1436 1437 /* xaui1 :: mdio_ctl :: md_st [11:11] */ 1438 #define XAUI1_MDIO_CTL_MD_ST_MASK 0x0800 1439 #define XAUI1_MDIO_CTL_MD_ST_ALIGN 0 1440 #define XAUI1_MDIO_CTL_MD_ST_BITS 1 1441 #define XAUI1_MDIO_CTL_MD_ST_SHIFT 11 1442 1443 /* xaui1 :: mdio_ctl :: multimmds_strap [10:10] */ 1444 #define XAUI1_MDIO_CTL_MULTIMMDS_STRAP_MASK 0x0400 1445 #define XAUI1_MDIO_CTL_MULTIMMDS_STRAP_ALIGN 0 1446 #define XAUI1_MDIO_CTL_MULTIMMDS_STRAP_BITS 1 1447 #define XAUI1_MDIO_CTL_MULTIMMDS_STRAP_SHIFT 10 1448 1449 /* xaui1 :: mdio_ctl :: md_devad [09:05] */ 1450 #define XAUI1_MDIO_CTL_MD_DEVAD_MASK 0x03e0 1451 #define XAUI1_MDIO_CTL_MD_DEVAD_ALIGN 0 1452 #define XAUI1_MDIO_CTL_MD_DEVAD_BITS 5 1453 #define XAUI1_MDIO_CTL_MD_DEVAD_SHIFT 5 1454 1455 /* xaui1 :: mdio_ctl :: prtad [04:00] */ 1456 #define XAUI1_MDIO_CTL_PRTAD_MASK 0x001f 1457 #define XAUI1_MDIO_CTL_PRTAD_ALIGN 0 1458 #define XAUI1_MDIO_CTL_PRTAD_BITS 5 1459 #define XAUI1_MDIO_CTL_PRTAD_SHIFT 0 1460 1461 1462 /**************************************************************************** 1463 * xaui2 :: mdio_ctl 1464 */ 1465 /* xaui2 :: mdio_ctl :: reserved0 [15:13] */ 1466 #define XAUI2_MDIO_CTL_RESERVED0_MASK 0xe000 1467 #define XAUI2_MDIO_CTL_RESERVED0_ALIGN 0 1468 #define XAUI2_MDIO_CTL_RESERVED0_BITS 3 1469 #define XAUI2_MDIO_CTL_RESERVED0_SHIFT 13 1470 1471 /* xaui2 :: mdio_ctl :: remotemdioreq [12:12] */ 1472 #define XAUI2_MDIO_CTL_REMOTEMDIOREQ_MASK 0x1000 1473 #define XAUI2_MDIO_CTL_REMOTEMDIOREQ_ALIGN 0 1474 #define XAUI2_MDIO_CTL_REMOTEMDIOREQ_BITS 1 1475 #define XAUI2_MDIO_CTL_REMOTEMDIOREQ_SHIFT 12 1476 1477 /* xaui2 :: mdio_ctl :: md_st [11:11] */ 1478 #define XAUI2_MDIO_CTL_MD_ST_MASK 0x0800 1479 #define XAUI2_MDIO_CTL_MD_ST_ALIGN 0 1480 #define XAUI2_MDIO_CTL_MD_ST_BITS 1 1481 #define XAUI2_MDIO_CTL_MD_ST_SHIFT 11 1482 1483 /* xaui2 :: mdio_ctl :: multimmds_strap [10:10] */ 1484 #define XAUI2_MDIO_CTL_MULTIMMDS_STRAP_MASK 0x0400 1485 #define XAUI2_MDIO_CTL_MULTIMMDS_STRAP_ALIGN 0 1486 #define XAUI2_MDIO_CTL_MULTIMMDS_STRAP_BITS 1 1487 #define XAUI2_MDIO_CTL_MULTIMMDS_STRAP_SHIFT 10 1488 1489 /* xaui2 :: mdio_ctl :: md_devad [09:05] */ 1490 #define XAUI2_MDIO_CTL_MD_DEVAD_MASK 0x03e0 1491 #define XAUI2_MDIO_CTL_MD_DEVAD_ALIGN 0 1492 #define XAUI2_MDIO_CTL_MD_DEVAD_BITS 5 1493 #define XAUI2_MDIO_CTL_MD_DEVAD_SHIFT 5 1494 1495 /* xaui2 :: mdio_ctl :: prtad [04:00] */ 1496 #define XAUI2_MDIO_CTL_PRTAD_MASK 0x001f 1497 #define XAUI2_MDIO_CTL_PRTAD_ALIGN 0 1498 #define XAUI2_MDIO_CTL_PRTAD_BITS 5 1499 #define XAUI2_MDIO_CTL_PRTAD_SHIFT 0 1500 1501 1502 /* XAUI1_MDIO_CTL_REG (Addr 4080h) */ 1503 #define READ_PHY8481_XAUI1_MDIO_CTL_REG(_unit, _phy_ctrl, _val) \ 1504 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI1_MDIO_CTL_REG,(_val)) 1505 1506 #define WRITE_PHY8481_XAUI1_MDIO_CTL_REG(_unit, _phy_ctrl, _val) \ 1507 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI1_MDIO_CTL_REG,(_val)) 1508 1509 #define MODIFY_PHY8481_XAUI1_MDIO_CTL_REG(_unit, _phy_ctrl, _val, _mask) \ 1510 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI1_MDIO_CTL_REG,(_val),(_mask)) 1511 1512 #define WRITE_PHY8481_XAUI1_MDIO_CTL_REG_MD_DEVAD(_unit, _phy_ctrl, _val) \ 1513 MODIFY_PHY8481_XAUI1_MDIO_CTL_REG((_unit), (_phy_ctrl), \ 1514 (_val)<<XAUI1_MDIO_CTL_MD_DEVAD_SHIFT, XAUI1_MDIO_CTL_MD_DEVAD_MASK) 1515 1516 #define WRITE_PHY8481_XAUI1_MDIO_CTL_REG_MULTIMMDS_STRAP(_unit, _phy_ctrl, _val) \ 1517 MODIFY_PHY8481_XAUI1_MDIO_CTL_REG((_unit), (_phy_ctrl), \ 1518 (_val)<<XAUI1_MDIO_CTL_MULTIMMDS_STRAP_SHIFT, XAUI1_MDIO_CTL_MULTIMMDS_STRAP_MASK) 1519 1520 1521 /* XAUI2_MDIO_CTL_REG (Addr 4090h) */ 1522 #define READ_PHY8481_XAUI2_MDIO_CTL_REG(_unit, _phy_ctrl, _val) \ 1523 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI2_MDIO_CTL_REG,(_val)) 1524 1525 #define WRITE_PHY8481_XAUI2_MDIO_CTL_REG(_unit, _phy_ctrl, _val) \ 1526 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI2_MDIO_CTL_REG,(_val)) 1527 1528 #define MODIFY_PHY8481_XAUI2_MDIO_CTL_REG(_unit, _phy_ctrl, _val, _mask) \ 1529 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI2_MDIO_CTL_REG,(_val),(_mask)) 1530 1531 #define WRITE_PHY8481_XAUI2_MDIO_CTL_REG_PRTAD(_unit, _phy_ctrl, _val) \ 1532 MODIFY_PHY8481_XAUI2_MDIO_CTL_REG((_unit), (_phy_ctrl), \ 1533 (_val)<<XAUI2_MDIO_CTL_PRTAD_SHIFT, XAUI2_MDIO_CTL_PRTAD_MASK) 1534 1535 #define XAUI1_RESET_CTL_REG 0x4083 1536 #define XAUI2_RESET_CTL_REG 0x4093 1537 1538 /* XAUI1_RESET_CTL (Addr 4083h) */ 1539 1540 #define READ_PHY8481_XAUI1_RESET_CTL_REG(_unit, _phy_ctrl, _val) \ 1541 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI1_RESET_CTL_REG,(_val)) 1542 1543 #define WRITE_PHY8481_XAUI1_RESET_CTL_REG(_unit, _phy_ctrl, _val) \ 1544 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI1_RESET_CTL_REG,(_val)) 1545 1546 #define MODIFY_PHY8481_XAUI1_RESET_CTL_REG(_unit, _phy_ctrl, _val, _mask) \ 1547 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI1_RESET_CTL_REG,(_val),(_mask)) 1548 1549 1550 /* XAUI2_RESET_CTL (Addr 4093h) */ 1551 1552 #define READ_PHY8481_XAUI2_RESET_CTL_REG(_unit, _phy_ctrl, _val) \ 1553 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI2_RESET_CTL_REG,(_val)) 1554 1555 #define WRITE_PHY8481_XAUI2_RESET_CTL_REG(_unit, _phy_ctrl, _val) \ 1556 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI2_RESET_CTL_REG,(_val)) 1557 1558 #define MODIFY_PHY8481_XAUI2_RESET_CTL_REG(_unit, _phy_ctrl, _val, _mask) \ 1559 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), XAUI2_RESET_CTL_REG,(_val),(_mask)) 1560 1561 /* IFC XGPHY CTL */ 1562 1563 #define IFC_XGPHY_CTL 0x40c0 1564 1565 #define READ_PHY8481_IFC_XGPHY_CTL(_unit, _phy_ctrl, _val) \ 1566 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), IFC_XGPHY_CTL,(_val)) 1567 1568 #define WRITE_PHY8481_IFC_XGPHY_CTL(_unit, _phy_ctrl, _val) \ 1569 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), IFC_XGPHY_CTL,(_val)) 1570 1571 #define MODIFY_PHY8481_IFC_XGPHY_CTL(_unit, _phy_ctrl, _val, _mask) \ 1572 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), IFC_XGPHY_CTL,(_val),(_mask)) 1573 1574 1575 /* Macros for MDIO2ARM operations */ 1576 1577 #define MDIO2ARM_CTL 0xa817 1578 1579 /* PHYC_CTL :: MDIO2ARM_CTL :: reserved0 [15:06] */ 1580 #define MDIO2ARM_CTL_RESERVED0_MASK 0xffc0 1581 #define MDIO2ARM_CTL_RESERVED0_ALIGN 0 1582 #define MDIO2ARM_CTL_RESERVED0_BITS 10 1583 #define MDIO2ARM_CTL_RESERVED0_SHIFT 6 1584 1585 /* PHYC_CTL :: MDIO2ARM_CTL :: MDIO2ARM_SELF_INC_ADDR [05:05] */ 1586 #define MDIO2ARM_CTL_MDIO2ARM_SELF_INC_ADDR_MASK 0x0020 1587 #define MDIO2ARM_CTL_MDIO2ARM_SELF_INC_ADDR_ALIGN 0 1588 #define MDIO2ARM_CTL_MDIO2ARM_SELF_INC_ADDR_BITS 1 1589 #define MDIO2ARM_CTL_MDIO2ARM_SELF_INC_ADDR_SHIFT 5 1590 1591 /* PHYC_CTL :: MDIO2ARM_CTL :: MDIO2ARM_BURST [04:04] */ 1592 #define MDIO2ARM_CTL_MDIO2ARM_BURST_MASK 0x0010 1593 #define MDIO2ARM_CTL_MDIO2ARM_BURST_ALIGN 0 1594 #define MDIO2ARM_CTL_MDIO2ARM_BURST_BITS 1 1595 #define MDIO2ARM_CTL_MDIO2ARM_BURST_SHIFT 4 1596 1597 /* PHYC_CTL :: MDIO2ARM_CTL :: MDIO2ARM_SIZE [03:02] */ 1598 #define MDIO2ARM_CTL_MDIO2ARM_SIZE_MASK 0x000c 1599 #define MDIO2ARM_CTL_MDIO2ARM_SIZE_ALIGN 0 1600 #define MDIO2ARM_CTL_MDIO2ARM_SIZE_BITS 2 1601 #define MDIO2ARM_CTL_MDIO2ARM_SIZE_SHIFT 2 1602 1603 /* PHYC_CTL :: MDIO2ARM_CTL :: MDIO2ARM_RD [01:01] */ 1604 #define MDIO2ARM_CTL_MDIO2ARM_RD_MASK 0x0002 1605 #define MDIO2ARM_CTL_MDIO2ARM_RD_ALIGN 0 1606 #define MDIO2ARM_CTL_MDIO2ARM_RD_BITS 1 1607 #define MDIO2ARM_CTL_MDIO2ARM_RD_SHIFT 1 1608 1609 /* PHYC_CTL :: MDIO2ARM_CTL :: MDIO2ARM_WR [00:00] */ 1610 #define MDIO2ARM_CTL_MDIO2ARM_WR_MASK 0x0001 1611 #define MDIO2ARM_CTL_MDIO2ARM_WR_ALIGN 0 1612 #define MDIO2ARM_CTL_MDIO2ARM_WR_BITS 1 1613 #define MDIO2ARM_CTL_MDIO2ARM_WR_SHIFT 0 1614 1615 1616 #define MDIO2ARM_STS 0xa818 1617 1618 /* PHYC_CTL :: MDIO2ARM_STS :: reserved0 [15:01] */ 1619 #define MDIO2ARM_STS_RESERVED0_MASK 0xfffe 1620 #define MDIO2ARM_STS_RESERVED0_ALIGN 0 1621 #define MDIO2ARM_STS_RESERVED0_BITS 15 1622 #define MDIO2ARM_STS_RESERVED0_SHIFT 1 1623 1624 /* PHYC_CTL :: MDIO2ARM_STS :: MDIO2ARM_DONE [00:00] */ 1625 #define MDIO2ARM_STS_MDIO2ARM_DONE_MASK 0x0001 1626 #define MDIO2ARM_STS_MDIO2ARM_DONE_ALIGN 0 1627 #define MDIO2ARM_STS_MDIO2ARM_DONE_BITS 1 1628 #define MDIO2ARM_STS_MDIO2ARM_DONE_SHIFT 0 1629 1630 1631 #define MDIO2ARM_ADDR_LOW 0xa819 1632 #define MDIO2ARM_ADDR_HIGH 0xa81a 1633 1634 #define MDIO2ARM_DATA_LOW 0xa81b 1635 #define MDIO2ARM_DATA_HIGH 0xa81c 1636 1637 #define WRITE_PHY8481_MDIO2ARM_ADDR_LOW_REG(_unit, _phy_ctrl, _val) \ 1638 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_ADDR_LOW, (_val)) 1639 1640 #define WRITE_PHY8481_MDIO2ARM_ADDR_HIGH_REG(_unit, _phy_ctrl, _val) \ 1641 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_ADDR_HIGH, (_val)) 1642 1643 1644 #define READ_PHY8481_MDIO2ARM_DATA_LOW_REG(_unit, _phy_ctrl, _val) \ 1645 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_DATA_LOW, (_val)) 1646 1647 #define READ_PHY8481_MDIO2ARM_DATA_HIGH_REG(_unit, _phy_ctrl, _val) \ 1648 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_DATA_HIGH, (_val)) 1649 1650 #define WRITE_PHY8481_MDIO2ARM_DATA_LOW_REG(_unit, _phy_ctrl, _val) \ 1651 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_DATA_LOW, (_val)) 1652 1653 #define WRITE_PHY8481_MDIO2ARM_DATA_HIGH_REG(_unit, _phy_ctrl, _val) \ 1654 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_DATA_HIGH, (_val)) 1655 1656 1657 #define READ_PHY8481_MDIO2ARM_CTL_REG(_unit, _phy_ctrl, _val) \ 1658 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_CTL,(_val)) 1659 1660 #define WRITE_PHY8481_MDIO2ARM_CTL_REG(_unit, _phy_ctrl, _val) \ 1661 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_CTL,(_val)) 1662 1663 #define MODIFY_PHY8481_MDIO2ARM_CTL_REG(_unit, _phy_ctrl, _val, _mask) \ 1664 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_CTL,(_val),(_mask)) 1665 1666 1667 #define READ_PHY8481_MDIO2ARM_STS_REG(_unit, _phy_ctrl, _val) \ 1668 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_STS,(_val)) 1669 1670 #define WRITE_PHY8481_MDIO2ARM_STS_REG(_unit, _phy_ctrl, _val) \ 1671 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_STS,(_val)) 1672 1673 #define MODIFY_PHY8481_MDIO2ARM_STS_REG(_unit, _phy_ctrl, _val, _mask) \ 1674 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), MDIO2ARM_STS,(_val),(_mask)) 1675 1676 1677 /* 1678 1679 The register is TOP_CONFIG_LINK_STATUS_REG, dev = 0x1e, mdio_addr = 0x400d or 0x418b. The bits are: 1680 1681 TOP_CONFIG_LINK_STATUS_REG[0] - fiber detected, 1=active, 0=inactive 1682 TOP_CONFIG_LINK_STATUS_REG[1] - copper detected, 1=active, 0=inactive 1683 TOP_CONFIG_LINK_STATUS_REG[2] - priority, 1=fiber priority, 0=copper priority 1684 TOP_CONFIG_LINK_STATUS_REG[4:3] - copper speed, 11=10G, 10=1G, 01=100M, 00=10M 1685 TOP_CONFIG_LINK_STATUS_REG[5] - copper link, 1=link up, 0=link down 1686 TOP_CONFIG_LINK_STATUS_REG[7:6] - fiber speed, 11=10G, 10=1G, 01=100M, 00=10M 1687 TOP_CONFIG_LINK_STATUS_REG[8] - fiber link, 1=link up, 0=link down 1688 1689 */ 1690 1691 #define TOP_CONFIG_LINK_STATUS_REG(_unit, _phy_ctrl) ((PHY_MODEL((_phy_ctrl)->phy_id0, (_phy_ctrl)->phy_id1) == PHY_BCM8481X_MODEL) ? 0x418b : 0x400d ) 1692 1693 #define TOP_CONFIG_LINK_STATUS_REG_FIBER_ACT 0x0001 /* fiber detected, 1=active, 0=inactive */ 1694 #define TOP_CONFIG_LINK_STATUS_REG_COPPER_ACT 0x0002 /* copper detected, 1=active, 0=inactive */ 1695 #define TOP_CONFIG_LINK_STATUS_REG_FIBER_PRIO 0x0004 /* 1=fiber priority, 0=copper priority */ 1696 #define TOP_CONFIG_LINK_STATUS_REG_COPPER_LINK 0x0020 /* copper link, 1=link up, 0=link down */ 1697 #define TOP_CONFIG_LINK_STATUS_REG_FIBER_LINK 0x0100 /* fiber link, 1=link up, 0=link down */ 1698 1699 #define READ_PHY8481_TOP_CONFIG_LINK_STATUS_REG(_unit, _phy_ctrl, _val) \ 1700 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1701 TOP_CONFIG_LINK_STATUS_REG((_unit), (_phy_ctrl)), (_val)) 1702 1703 #define WRITE_PHY8481_TOP_CONFIG_LINK_STATUS_REG(_unit, _phy_ctrl, _val) \ 1704 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1705 TOP_CONFIG_LINK_STATUS_REG((_unit), (_phy_ctrl)), (_val)) 1706 1707 #define MODIFY_PHY8481_TOP_CONFIG_LINK_STATUS_REG(_unit, _phy_ctrl, _val, _mask) \ 1708 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1709 TOP_CONFIG_LINK_STATUS_REG((_unit), (_phy_ctrl)), (_val), (_mask)) 1710 1711 #define TOP_CONFIG_AUTOGREEN_CONFIG1_REG 0x400a 1712 1713 #define READ_PHY8481_TOP_CONFIG_AUTOGREEN_CONFIG1r(_unit, _phy_ctrl, _val) \ 1714 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1715 TOP_CONFIG_AUTOGREEN_CONFIG1_REG, (_val)) 1716 1717 #define WRITE_PHY8481_TOP_CONFIG_AUTOGREEN_CONFIG1r(_unit, _phy_ctrl, _val) \ 1718 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1719 TOP_CONFIG_AUTOGREEN_CONFIG1_REG, (_val)) 1720 1721 #define MODIFY_PHY8481_TOP_CONFIG_AUTOGREEN_CONFIG1r(_unit, _phy_ctrl, _val, _mask) \ 1722 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1723 TOP_CONFIG_AUTOGREEN_CONFIG1_REG, (_val), (_mask)) 1724 1725 #define TOP_CONFIG_AUTOGREEN_THRESHOLD_LOW_REG 0x400c 1726 1727 #define READ_PHY8481_TOP_CONFIG_AUTOGREEN_THRESHOLD_LOWr(_unit, _phy_ctrl, _val) \ 1728 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1729 TOP_CONFIG_AUTOGREEN_THRESHOLD_LOW_REG, (_val)) 1730 1731 #define WRITE_PHY8481_TOP_CONFIG_AUTOGREEN_THRESHOLD_LOWr(_unit, _phy_ctrl, _val) \ 1732 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1733 TOP_CONFIG_AUTOGREEN_THRESHOLD_LOW_REG, (_val)) 1734 1735 #define MODIFY_PHY8481_TOP_CONFIG_AUTOGREEN_THRESHOLD_LOWr(_unit, _phy_ctrl, _val, _mask) \ 1736 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1737 TOP_CONFIG_AUTOGREEN_THRESHOLD_LOW_REG, (_val), (_mask)) 1738 1739 1740 #define TOP_CONFIG_AUTOGREEN_THRESHOLD_HIGH_REG 0x400b 1741 1742 #define READ_PHY8481_TOP_CONFIG_AUTOGREEN_THRESHOLD_HIGHr(_unit, _phy_ctrl, _val) \ 1743 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1744 TOP_CONFIG_AUTOGREEN_THRESHOLD_HIGH_REG, (_val)) 1745 1746 #define WRITE_PHY8481_TOP_CONFIG_AUTOGREEN_THRESHOLD_HIGHr(_unit, _phy_ctrl, _val) \ 1747 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1748 TOP_CONFIG_AUTOGREEN_THRESHOLD_HIGH_REG, (_val)) 1749 1750 #define MODIFY_PHY8481_TOP_CONFIG_AUTOGREEN_THRESHOLD_HIGHr(_unit, _phy_ctrl, _val, _mask) \ 1751 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1752 TOP_CONFIG_AUTOGREEN_THRESHOLD_HIGH_REG, (_val), (_mask)) 1753 1754 1755 #define TOP_CONFIG_CABLE_DIAG_CTRL_STAT_REG(_unit, _phy_ctrl) ((PHY_MODEL((_phy_ctrl)->phy_id0, (_phy_ctrl)->phy_id1) == \ 1756 PHY_BCM8481X_MODEL) ? 0x402A : 0x4006 ) 1757 1758 #define READ_PHY8481_TOP_CONFIG_CABLE_DIAG_CTRL_STAT_REG(_unit, _phy_ctrl, _val) \ 1759 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1760 TOP_CONFIG_CABLE_DIAG_CTRL_STAT_REG((_unit), (_phy_ctrl)), (_val)) 1761 1762 #define WRITE_PHY8481_TOP_CONFIG_CABLE_DIAG_CTRL_STAT_REG(_unit, _phy_ctrl, _val) \ 1763 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1764 TOP_CONFIG_CABLE_DIAG_CTRL_STAT_REG((_unit), (_phy_ctrl)), (_val)) 1765 1766 #define MODIFY_PHY8481_TOP_CONFIG_CABLE_DIAG_CTRL_STAT_REG(_unit, _phy_ctrl, _val, _mask) \ 1767 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1768 TOP_CONFIG_CABLE_DIAG_CTRL_STAT_REG((_unit), (_phy_ctrl)), (_val), (_mask)) 1769 1770 1771 #define PHYC_CTL_CABLE_DIAG_RESULT_REG(_unit, _phy_ctrl) ((PHY_MODEL((_phy_ctrl)->phy_id0, (_phy_ctrl)->phy_id1) == \ 1772 PHY_BCM8481X_MODEL) ? 0xA863 : 0xA896 ) 1773 #define READ_PHY8481_PHYC_CTL_CABLE_DIAG_RESULT_REG(_unit, _phy_ctrl, _val) \ 1774 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHYC_CTL_CABLE_DIAG_RESULT_REG((_unit), (_phy_ctrl)), (_val)) 1775 1776 1777 #define PHYC_CTL_CABLE_DIAG_PAIR12_LEN_REG(_unit, _phy_ctrl) ((PHY_MODEL((_phy_ctrl)->phy_id0, (_phy_ctrl)->phy_id1) == \ 1778 PHY_BCM8481X_MODEL) ? 0xA864 : 0xA897 ) 1779 #define READ_PHY8481_PHYC_CTL_CABLE_DIAG_PAIR12_LEN_REG(_unit, _phy_ctrl, _val) \ 1780 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHYC_CTL_CABLE_DIAG_PAIR12_LEN_REG((_unit), (_phy_ctrl)), (_val)) 1781 1782 1783 #define PHYC_CTL_CABLE_DIAG_PAIR34_LEN_REG(_unit, _phy_ctrl) ((PHY_MODEL((_phy_ctrl)->phy_id0, (_phy_ctrl)->phy_id1) == \ 1784 PHY_BCM8481X_MODEL) ? 0xA865 : 0xA898 ) 1785 #define READ_PHY8481_PHYC_CTL_CABLE_DIAG_PAIR34_LEN_REG(_unit, _phy_ctrl, _val) \ 1786 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHYC_CTL_CABLE_DIAG_PAIR34_LEN_REG((_unit), (_phy_ctrl)), (_val)) 1787 1788 1789 #define PHYC_CTL_CABLE_DIAG_PAIR56_LEN_REG(_unit, _phy_ctrl) ((PHY_MODEL((_phy_ctrl)->phy_id0, (_phy_ctrl)->phy_id1) == \ 1790 PHY_BCM8481X_MODEL) ? 0xA866 : 0xA899 ) 1791 #define READ_PHY8481_PHYC_CTL_CABLE_DIAG_PAIR56_LEN_REG(_unit, _phy_ctrl, _val) \ 1792 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHYC_CTL_CABLE_DIAG_PAIR56_LEN_REG((_unit), (_phy_ctrl)), (_val)) 1793 1794 1795 #define PHYC_CTL_CABLE_DIAG_PAIR78_LEN_REG(_unit, _phy_ctrl) ((PHY_MODEL((_phy_ctrl)->phy_id0, (_phy_ctrl)->phy_id1) == \ 1796 PHY_BCM8481X_MODEL) ? 0xA867 : 0xA89A ) 1797 #define READ_PHY8481_PHYC_CTL_CABLE_DIAG_PAIR78_LEN_REG(_unit, _phy_ctrl, _val) \ 1798 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), PHYC_CTL_CABLE_DIAG_PAIR78_LEN_REG((_unit), (_phy_ctrl)), (_val)) 1799 1800 1801 #define READ_PHY8481_PMD_IEEE_TST_MODE_10G_REG(_unit, _phy_ctrl, _val) \ 1802 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0x0084, (_val)) 1803 1804 #define WRITE_PHY8481_PMD_IEEE_TST_MODE_10G_REG(_unit, _phy_ctrl, _val) \ 1805 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0x0084, (_val)) 1806 1807 #define MODIFY_PHY8481_PMD_IEEE_TST_MODE_10G_REG(_unit, _phy_ctrl, _val, _mask) \ 1808 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0x0084, (_val), (_mask)) 1809 1810 1811 #define READ_PHY8481_PHYC_CTL_SPARE_GRP5_REG(_unit, _phy_ctrl, _val) \ 1812 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0xa89b, (_val)) 1813 1814 #define WRITE_PHY8481_PHYC_CTL_SPARE_GRP5_REG(_unit, _phy_ctrl, _val) \ 1815 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0xa89b, (_val)) 1816 1817 #define MODIFY_PHY8481_PHYC_CTL_SPARE_GRP5_REG(_unit, _phy_ctrl, _val, _mask) \ 1818 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0xa89b, (_val), (_mask)) 1819 1820 1821 #define READ_PHY8481_PHYC_CTL_SPARE_GRP6_REG(_unit, _phy_ctrl, _val) \ 1822 READ_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0xa89c, (_val)) 1823 1824 #define WRITE_PHY8481_PHYC_CTL_SPARE_GRP6_REG(_unit, _phy_ctrl, _val) \ 1825 WRITE_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0xa89c, (_val)) 1826 1827 #define MODIFY_PHY8481_PHYC_CTL_SPARE_GRP6_REG(_unit, _phy_ctrl, _val, _mask) \ 1828 MODIFY_PHY8481_PMAD_REG((_unit), (_phy_ctrl), 0xa89c, (_val), (_mask)) 1829 1830 1831 #define TOP_CONFIG_XGPHY_STRAP1_REG 0x401a 1832 1833 #define READ_PHY8481_TOP_CONFIG_XGPHY_STRAP1_REG(_unit, _phy_ctrl, _val) \ 1834 READ_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1835 TOP_CONFIG_XGPHY_STRAP1_REG,(_val)) 1836 1837 #define WRITE_PHY8481_TOP_CONFIG_XGPHY_STRAP1_REG(_unit, _phy_ctrl, _val) \ 1838 WRITE_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1839 TOP_CONFIG_XGPHY_STRAP1_REG,(_val)) 1840 1841 #define MODIFY_PHY8481_TOP_CONFIG_XGPHY_STRAP1_REG(_unit, _phy_ctrl, _val, _mask) \ 1842 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_phy_ctrl), \ 1843 TOP_CONFIG_XGPHY_STRAP1_REG,(_val),(_mask)) 1844 1845 #define TOP_CONFIG_XGPHY_STRAP1_SUPER_ISOLATE (1U << 15) 1846 #define TOP_CONFIG_XGPHY_STRAP1_XGPH_DISABLE (1U << 7) 1847 #define TOP_CONFIG_XGPHY_DISABLE (TOP_CONFIG_XGPHY_STRAP1_XGPH_DISABLE | \ 1848 TOP_CONFIG_XGPHY_STRAP1_SUPER_ISOLATE) 1849 1850 1851 #define READ_PHY84834_TOP_CONFIG_SCRATCH_0r(_unit, _pc, _val) \ 1852 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4005, (_val)) 1853 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_0r(_unit, _pc, _val) \ 1854 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4005, (_val)) 1855 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_0r(_unit, _pc, _val, _mask) \ 1856 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4005, \ 1857 (_val), (_mask)) 1858 1859 #define READ_PHY84834_TOP_CONFIG_SCRATCH_1r(_unit, _pc, _val) \ 1860 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4006, (_val)) 1861 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_1r(_unit, _pc, _val) \ 1862 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4006, (_val)) 1863 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_1r(_unit, _pc, _val, _mask) \ 1864 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4006, \ 1865 (_val), (_mask)) 1866 1867 #define READ_PHY84834_TOP_CONFIG_SCRATCH_2r(_unit, _pc, _val) \ 1868 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4007, (_val)) 1869 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_2r(_unit, _pc, _val) \ 1870 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4007, (_val)) 1871 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_2r(_unit, _pc, _val, _mask) \ 1872 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4007, \ 1873 (_val), (_mask)) 1874 1875 #define READ_PHY84834_TOP_CONFIG_SCRATCH_3r(_unit, _pc, _val) \ 1876 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4008, (_val)) 1877 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_3r(_unit, _pc, _val) \ 1878 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4008, (_val)) 1879 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_3r(_unit, _pc, _val, _mask) \ 1880 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4008, \ 1881 (_val), (_mask)) 1882 1883 #define READ_PHY84834_TOP_CONFIG_SCRATCH_4r(_unit, _pc, _val) \ 1884 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4009, (_val)) 1885 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_4r(_unit, _pc, _val) \ 1886 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4009, (_val)) 1887 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_4r(_unit, _pc, _val, _mask) \ 1888 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4009, \ 1889 (_val), (_mask)) 1890 1891 #define READ_PHY84834_TOP_CONFIG_SCRATCH_5r(_unit, _pc, _val) \ 1892 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400a, (_val)) 1893 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_5r(_unit, _pc, _val) \ 1894 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400a, (_val)) 1895 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_5r(_unit, _pc, _val, _mask) \ 1896 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400a, \ 1897 (_val), (_mask)) 1898 1899 #define READ_PHY84834_TOP_CONFIG_SCRATCH_6r(_unit, _pc, _val) \ 1900 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400b, (_val)) 1901 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_6r(_unit, _pc, _val) \ 1902 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400b, (_val)) 1903 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_6r(_unit, _pc, _val, _mask) \ 1904 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400b, \ 1905 (_val), (_mask)) 1906 1907 #define READ_PHY84834_TOP_CONFIG_SCRATCH_7r(_unit, _pc, _val) \ 1908 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400c, (_val)) 1909 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_7r(_unit, _pc, _val) \ 1910 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400c, (_val)) 1911 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_7r(_unit, _pc, _val, _mask) \ 1912 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400c, \ 1913 (_val), (_mask)) 1914 1915 #define READ_PHY84834_TOP_CONFIG_SCRATCH_8r(_unit, _pc, _val) \ 1916 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400d, (_val)) 1917 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_8r(_unit, _pc, _val) \ 1918 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400d, (_val)) 1919 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_8r(_unit, _pc, _val, _mask) \ 1920 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400d, \ 1921 (_val), (_mask)) 1922 1923 #define CORE_CFG_LINK_STATUS_REG 0x400d 1924 #define READ_PHY84834_CORE_CFG_LINK_STATUSr(_unit, _pc, _val) \ 1925 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), \ 1926 CORE_CFG_LINK_STATUS_REG, (_val)) 1927 #define WRITE_PHY84834_CORE_CFG_LINK_STATUSr(_unit, _pc, _val) \ 1928 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), \ 1929 CORE_CFG_LINK_STATUS_REG, (_val)) 1930 #define MODIFY_PHY84834_CORE_CFG_LINK_STATUSr(_unit, _pc, _val, _mask) \ 1931 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), \ 1932 CORE_CFG_LINK_STATUS_REG, (_val), (_mask)) 1933 1934 #define CORE_CFG_LINK_STAT_MAC_LINK_STATUS (1U << 13) 1935 #define CORE_CFG_LINK_STAT_SPEED_LSB ((1U << 4) | (1U << 3)) 1936 #define CORE_CFG_LINK_STAT_SPEED_MSB (1U << 2) 1937 #define CORE_CFG_LINK_STAT_SPEED_LSB_SHIFT 3 1938 1939 #define READ_PHY84834_TOP_CONFIG_SCRATCH_9r(_unit, _pc, _val) \ 1940 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400e, (_val)) 1941 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_9r(_unit, _pc, _val) \ 1942 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400e, (_val)) 1943 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_9r(_unit, _pc, _val, _mask) \ 1944 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400e, \ 1945 (_val), (_mask)) 1946 1947 #define READ_PHY84834_TOP_CONFIG_SCRATCH_10r(_unit, _pc, _val) \ 1948 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400f, (_val)) 1949 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_10r(_unit, _pc, _val) \ 1950 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400f, (_val)) 1951 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_10r(_unit, _pc, _val, _mask) \ 1952 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x400f, \ 1953 (_val), (_mask)) 1954 1955 #define READ_PHY84834_TOP_CONFIG_SCRATCH_11r(_unit, _pc, _val) \ 1956 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4010, (_val)) 1957 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_11r(_unit, _pc, _val) \ 1958 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4010, (_val)) 1959 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_11r(_unit, _pc, _val, _mask) \ 1960 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4010, \ 1961 (_val), (_mask)) 1962 1963 #define READ_PHY84834_TOP_CONFIG_SCRATCH_12r(_unit, _pc, _val) \ 1964 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4011, (_val)) 1965 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_12r(_unit, _pc, _val) \ 1966 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4011, (_val)) 1967 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_12r(_unit, _pc, _val, _mask) \ 1968 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4011, \ 1969 (_val), (_mask)) 1970 1971 #define READ_PHY84834_TOP_CONFIG_SCRATCH_13r(_unit, _pc, _val) \ 1972 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4012, (_val)) 1973 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_13r(_unit, _pc, _val) \ 1974 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4012, (_val)) 1975 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_13r(_unit, _pc, _val, _mask) \ 1976 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4012, \ 1977 (_val), (_mask)) 1978 1979 #define READ_PHY84834_TOP_CONFIG_SCRATCH_14r(_unit, _pc, _val) \ 1980 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4013, (_val)) 1981 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_14r(_unit, _pc, _val) \ 1982 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4013, (_val)) 1983 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_14r(_unit, _pc, _val, _mask) \ 1984 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4013, \ 1985 (_val), (_mask)) 1986 1987 #define READ_PHY84834_TOP_CONFIG_SCRATCH_15r(_unit, _pc, _val) \ 1988 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4014, (_val)) 1989 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_15r(_unit, _pc, _val) \ 1990 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4014, (_val)) 1991 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_15r(_unit, _pc, _val, _mask) \ 1992 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4014, \ 1993 (_val), (_mask)) 1994 1995 #define READ_PHY84834_TOP_CONFIG_SCRATCH_26r(_unit, _pc, _val) \ 1996 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4037, (_val)) 1997 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_26r(_unit, _pc, _val) \ 1998 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4037, (_val)) 1999 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_26r(_unit, _pc, _val, _mask) \ 2000 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4037, \ 2001 (_val), (_mask)) 2002 2003 #define READ_PHY84834_TOP_CONFIG_SCRATCH_27r(_unit, _pc, _val) \ 2004 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4038, (_val)) 2005 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_27r(_unit, _pc, _val) \ 2006 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4038, (_val)) 2007 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_27r(_unit, _pc, _val, _mask) \ 2008 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4038, \ 2009 (_val), (_mask)) 2010 2011 #define READ_PHY84834_TOP_CONFIG_SCRATCH_28r(_unit, _pc, _val) \ 2012 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4039, (_val)) 2013 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_28r(_unit, _pc, _val) \ 2014 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4039, (_val)) 2015 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_28r(_unit, _pc, _val, _mask) \ 2016 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x4039, \ 2017 (_val), (_mask)) 2018 2019 #define READ_PHY84834_TOP_CONFIG_SCRATCH_29r(_unit, _pc, _val) \ 2020 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403a, (_val)) 2021 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_29r(_unit, _pc, _val) \ 2022 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403a, (_val)) 2023 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_29r(_unit, _pc, _val, _mask) \ 2024 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403a, \ 2025 (_val), (_mask)) 2026 2027 #define READ_PHY84834_TOP_CONFIG_SCRATCH_30r(_unit, _pc, _val) \ 2028 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403b, (_val)) 2029 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_30r(_unit, _pc, _val) \ 2030 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403b, (_val)) 2031 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_30r(_unit, _pc, _val, _mask) \ 2032 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403b, \ 2033 (_val), (_mask)) 2034 2035 #define READ_PHY84834_TOP_CONFIG_SCRATCH_31r(_unit, _pc, _val) \ 2036 READ_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403c, (_val)) 2037 #define WRITE_PHY84834_TOP_CONFIG_SCRATCH_31r(_unit, _pc, _val) \ 2038 WRITE_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403c, (_val)) 2039 #define MODIFY_PHY84834_TOP_CONFIG_SCRATCH_31r(_unit, _pc, _val, _mask) \ 2040 MODIFY_PHY8481_TOPLVL1_REG((_unit), (_pc), 0x403c, \ 2041 (_val), (_mask)) 2042 2043 2044 #define PHY84834_DIAG_CMD_NOP 0 2045 #define PHY84834_DIAG_CMD_BLK_LF_RF_ENABLE 1 2046 #define PHY84834_DIAG_CMD_PAIR_SWAP_CHANGE 2 2047 #define PHY84834_DIAG_CMD_3 3 2048 #define PHY84834_DIAG_CMD_DISABLE_TRAFFIC_LED 4 2049 #define PHY84834_DIAG_CMD_5 5 2050 #define PHY84834_DIAG_CMD_6 6 2051 #define PHY84834_DIAG_CMD_7 7 2052 #define PHY84834_DIAG_CMD_DISABLE_RX_LF 8 2053 #define PHY84834_DIAG_CMD_GET_HEALTH_MONITOR_STATUS 9 2054 #define PHY84834_DIAG_CMD_CLEAR_HEALTH_MONITOR_STATUS 10 2055 #define PHY84834_DIAG_CMD_GET_MATLAB_VARIABLE_ADDRESSES 11 2056 #define PHY84834_DIAG_CMD_SET_UPPER_TEMP_WARNING_LEVEL 12 2057 #define PHY84834_DIAG_CMD_GET_UPPER_TEMP_WARNING_LEVEL 13 2058 #define PHY84834_DIAG_CMD_SET_LOWER_TEMP_WARNING_LEVEL 14 2059 #define PHY84834_DIAG_CMD_GET_LOWER_TEMP_WARNING_LEVEL 15 2060 #define PHY84834_DIAG_CMD_16 16 2061 #define PHY84834_DIAG_CMD_GET_CURRENT_TEMP 17 2062 #define PHY84834_DIAG_CMD_GET_DATA_BUF_ADDRESSES 18 2063 #define PHY84834_DIAG_CMD_PEEK_WORD 19 2064 #define PHY84834_DIAG_CMD_POKE_WORD 20 2065 #define PHY84834_DIAG_CMD_GET_EXP_VALUES 21 2066 #define PHY84834_DIAG_CMD_SET_MASTER_LOG_ENABLE 22 2067 #define PHY84834_DIAG_CMD_GET_MASTER_LOG_ENABLE 23 2068 #define PHY84834_DIAG_CMD_SET_MASTER_HANG_PC_CAPTURE_ENABLE 24 2069 #define PHY84834_DIAG_CMD_GET_MASTER_HANG_PC_CAPTURE_ENABLE 25 2070 #define PHY84834_DIAG_CMD_GET_AUTONEG_RESULTS 26 2071 #define PHY84834_DIAG_CMD_GET_XAUI1_REG_VALUES 27 2072 #define PHY84834_DIAG_CMD_SET_XAUI1_REG_VALUES 28 2073 #define PHY84834_DIAG_CMD_GET_MACSEC_ENABLE 33 2074 #define PHY84834_DIAG_CMD_SET_MACSEC_ENABLE 34 2075 #define PHY84834_DIAG_CMD_GET_1588_ENABLE 35 2076 #define PHY84834_DIAG_CMD_SET_1588_ENABLE 36 2077 #define PHY84834_DIAG_CMD_GET_SHORT_REACH_ENABLE 37 2078 #define PHY84834_DIAG_CMD_SET_SHORT_REACH_ENABLE 38 2079 #define PHY84834_DIAG_CMD_GET_EEE_MODE 39 2080 #define PHY84834_DIAG_CMD_SET_EEE_MODE 40 2081 #define PHY84834_DIAG_CMD_GET_PAIR_SWAP 41 2082 #define PHY84834_DIAG_CMD_GET_EMI_MODE_ENABLE 42 2083 #define PHY84834_DIAG_CMD_SET_EMI_MODE_ENABLE 43 2084 #define PHY84834_DIAG_CMD_GET_AUTONEG_RESULTS_ENHANCED 44 2085 2086 #define PHY84834_CMD_RECEIVED 0x0001 2087 #define PHY84834_CMD_IN_PROGRESS 0x0002 2088 #define PHY84834_CMD_COMPLETE_PASS 0x0004 2089 #define PHY84834_CMD_COMPLETE_ERROR 0x0008 2090 #define PHY84834_CMD_OPEN_FOR_CMDS 0x0010 2091 #define PHY84834_CMD_SYSTEM_BOOT 0x0020 2092 #define PHY84834_CMD_NOT_OPEN_FOR_CMDS 0x0040 2093 #define PHY84834_CMD_CLEAR_COMPLETE 0x0080 2094 #define PHY84834_CMD_OPEN_OVERRIDE 0xA5A5 2095 2096 2097 #define PHY8481_CMD_COMPLETE_PASS PHY84834_CMD_COMPLETE_PASS 2098 #define PHY8481_CMD_COMPLETE_ERROR PHY84834_CMD_COMPLETE_ERROR 2099 2100 #define PHY8485X_CMD_RECEIVED 0x0001 2101 #define PHY8485X_CMD_IN_PROGRESS 0x0002 2102 #define PHY8485X_CMD_OPEN_FOR_CMDS PHY8481_CMD_COMPLETE_PASS 2103 #define PHY8485X_CMD_COMPLETE_ERROR 0x0008 2104 #define PHY8485X_CMD_SYSTEM_BUSY 0xBBBB 2105 2106 /* Command Handler Version 2 */ 2107 #define PHY84834_DIAG_CMD_NOP_V2 0x0000 2108 2109 #define PHY84834_DIAG_CMD_GET_PAIR_SWAP_V2 0x8000 2110 #define PHY84834_DIAG_CMD_SET_PAIR_SWAP_V2 0x8001 2111 #define PHY84834_DIAG_CMD_GET_MACSEC_ENABLE_V2 0x8002 2112 #define PHY84834_DIAG_CMD_SET_MACSEC_ENABLE_V2 0x8003 2113 #define PHY84834_DIAG_CMD_GET_1588_ENABLE_V2 0x8004 2114 #define PHY84834_DIAG_CMD_SET_1588_ENABLE_V2 0x8005 2115 #define PHY84834_DIAG_CMD_GET_SHORT_REACH_ENABLE_V2 0x8006 2116 #define PHY84834_DIAG_CMD_SET_SHORT_REACH_ENABLE_V2 0x8007 2117 #define PHY84834_DIAG_CMD_GET_EEE_MODE_V2 0x8008 2118 #define PHY84834_DIAG_CMD_SET_EEE_MODE_V2 0x8009 2119 #define PHY84834_DIAG_CMD_GET_EMI_MODE_ENABLE_V2 0x800a 2120 #define PHY84834_DIAG_CMD_SET_EMI_MODE_ENABLE_V2 0x800b 2121 #define PHY84834_DIAG_CMD_GET_SUB_LF_RF_STATUS_V2 0x800c 2122 #define PHY84834_DIAG_CMD_GET_KR_MODE_ENABLE_V2 0x800e 2123 #define PHY84834_DIAG_CMD_SET_KR_MODE_ENABLE_V2 0x800f 2124 #define PHY84834_DIAG_CMD_CLEAR_SUB_LF_RF_V2 0x8010 2125 #define PHY84834_DIAG_CMD_SET_SUB_LF_RF_V2 0x8011 2126 #define PHY84834_DIAG_CMD_GET_XFI_2P5G_MODE_V2 0x8016 2127 #define PHY84834_DIAG_CMD_SET_XFI_2P5G_MODE_V2 0x8017 2128 #define PHY84834_DIAG_CMD_SET_PAUSE_FRAME_MODE 0x8020 2129 #define PHY84834_DIAG_CMD_GET_LED_TYPE 0x8021 2130 #define PHY84834_DIAG_CMD_SET_LED_TYPE 0x8022 2131 #define PHY84834_DIAG_CMD_GET_MGBASET_802_3BZ_TYPE 0x8023 2132 #define PHY84834_DIAG_CMD_SET_MGBASET_802_3BZ_TYPE 0x8024 2133 #define PHY84834_DIAG_CMD_GET_PAUSE_FRAME_MODE 0x801F 2134 #define PHY84834_DIAG_CMD_SET_USXGMII 0x8026 2135 #define PHY84834_DIAG_CMD_GET_USXGMII 0x8027 2136 #define PHY84834_DIAG_CMD_GET_SNR_V2 0x8030 2137 #define PHY84834_DIAG_CMD_GET_CURRENT_TEMP_V2 0x8031 2138 #define PHY84834_DIAG_CMD_SET_UPPER_TEMP_WARNING_LEVEL_V2 0x8032 2139 #define PHY84834_DIAG_CMD_GET_UPPER_TEMP_WARNING_LEVEL_V2 0x8033 2140 #define PHY84834_DIAG_CMD_SET_LOWER_TEMP_WARNING_LEVEL_V2 0x8034 2141 #define PHY84834_DIAG_CMD_GET_LOWER_TEMP_WARNING_LEVEL_V2 0x8035 2142 #define PHY8485X_DIAG_CMD_WRITE_SHADOW_REG_V2 0x8015 2143 #define PHY8485X_DIAG_CMD_READ_SHADOW_REG_V2 0x8014 2144 #define PHY848X_DIAG_CMD_WRITE_JUMBO_FRAME_REG_V2 0x801C 2145 #define PHY848X_DIAG_CMD_READ_JUMBO_FRAME_REG_V2 0x801D 2146 2147 2148 #define PHY84834_DIAG_CMD_GET_XAUI_M_REG_VALUES_V2 0x8100 2149 #define PHY84834_DIAG_CMD_SET_XAUI_M_REG_VALUES_V2 0x8101 2150 #define PHY84834_DIAG_CMD_GET_XFI_M_REG_VALUES_V2 0x8102 2151 #define PHY84834_DIAG_CMD_SET_XFI_M_REG_VALUES_V2 0x8103 2152 #define PHY84834_DIAG_CMD_GET_XAUI_L_REG_VALUES_V2 0x8104 2153 #define PHY84834_DIAG_CMD_SET_XAUI_L_REG_VALUES_V2 0x8105 2154 #define PHY84834_DIAG_CMD_GET_XFI_L_REG_VALUES_V2 0x8106 2155 #define PHY84834_DIAG_CMD_SET_XFI_L_REG_VALUES_V2 0x8107 2156 #define PHY84834_DIAG_CMD_SET_XFI_TX_FILTERS 0x802c 2157 #define PHY84834_DIAG_CMD_GET_XFI_TX_FILTERS 0x802b 2158 2159 #define PHY84834_DIAG_CMD_PEEK_WORD_V2 0xc000 2160 #define PHY84834_DIAG_CMD_POKE_WORD_V2 0xc001 2161 #define PHY84834_DIAG_CMD_GET_DATA_BUF_ADDRESSES_V2 0xc002 2162 2163 #define PHY84834_DIAG_CMD_XFI_2P5G_MODE_XFI 0 2164 #define PHY84834_DIAG_CMD_XFI_2P5G_MODE_2500X 1 2165 2166 /* 2167 * PTP_INT_EN 2168 */ 2169 #define PHY84834_PTP_INT_EN_REG (0xd808) 2170 2171 #define PHY84834_PTP_INT_PIC_EN (1U<<1) 2172 #define PHY84834_PTP_INT_FSYNC_EN (1U<<0) 2173 2174 2175 /* 2176 * PTP_INT_STATUS 2177 */ 2178 #define PHY84834_PTP_INT_STATUS_REG (0xd809) 2179 2180 #define PHY84834_PTP_INT_STATUS_PIC (1U<<1) 2181 #define PHY84834_PTP_INT_STATUS_FSYNC (1U<<0) 2182 2183 /* 2184 * PTP_INT_CLEAR 2185 */ 2186 #define PHY84834_PTP_INT_CLEAR_REG (0xd80a) 2187 2188 #define PHY84834_PTP_INT_CLEAR_PIC (1U<<1) 2189 #define PHY84834_PTP_INT_CLEAR_FSYNC (1U<<0) 2190 2191 /* 2192 * PTP_NSE_SHDW_CTL 2193 */ 2194 #define PHY84834_PTP_NSE_SHDW_CTL_REG (0xd882) 2195 2196 #define PHY84834_PTP_NSW_SHDW_CTL_LOAD_NTP_TIME (1U<<14) 2197 #define PHY84834_PTP_NSW_SHDW_CTL_LOAD_TIME (1U<<13) 2198 #define PHY84834_PTP_NSW_SHDW_CTL_LOAD_COUNT_HIGH (1U<<12) 2199 #define PHY84834_PTP_NSW_SHDW_CTL_LOAD_COUNT_LOW (1U<<11) 2200 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_NCO_FCW (1U<<10) 2201 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_DPLL_FCW (1U<<9) 2202 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_REF_PHASE (1U<<8) 2203 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_REF_PERIOD (1U<<7) 2204 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_DPLL_GAIN3 (1U<<6) 2205 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_DPLL_GAIN2 (1U<<5) 2206 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_DPLL_GAIN1 (1U<<4) 2207 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_SYNCOUT (1U<<3) 2208 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_SYNC_DIV (1U<<2) 2209 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_NEG_CORR (1U<<1) 2210 #define PHY84834_PTP_NSE_SHDW_CTL_LOAD_ORIG_TS (1U<<0) 2211 #define PHY84834_PTP_NSW_SHDW_CTL_LOAD_TIME_COUNT \ 2212 (PHY84834_PTP_NSW_SHDW_CTL_LOAD_TIME | \ 2213 PHY84834_PTP_NSW_SHDW_CTL_LOAD_COUNT_LOW | \ 2214 PHY84834_PTP_NSW_SHDW_CTL_LOAD_COUNT_HIGH) 2215 2216 2217 /* 2218 * PTP_NSE_SHDW_CLR 2219 */ 2220 #define PHY84834_PTP_NSE_SHDW_CLR_REG (0xd883) 2221 2222 #define PHY84834_PTP_NSW_SHDW_CLR_LOAD_NTP_TIME (1U<<14) 2223 #define PHY84834_PTP_NSW_SHDW_CLR_LOAD_TIME (1U<<13) 2224 #define PHY84834_PTP_NSW_SHDW_CLR_LOAD_COUNT_HIGH (1U<<12) 2225 #define PHY84834_PTP_NSW_SHDW_CLR_LOAD_COUNT_LOW (1U<<11) 2226 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_NCO_FCW (1U<<10) 2227 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_DPLL_FCW (1U<<9) 2228 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_REF_PHASE (1U<<8) 2229 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_REF_PERIOD (1U<<7) 2230 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_DPLL_GAIN3 (1U<<6) 2231 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_DPLL_GAIN2 (1U<<5) 2232 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_DPLL_GAIN1 (1U<<4) 2233 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_SYNCOUT (1U<<3) 2234 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_SYNC_DIV (1U<<2) 2235 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_NEG_CORR (1U<<1) 2236 #define PHY84834_PTP_NSE_SHDW_CLR_LOAD_ORIG_TS (1U<<0) 2237 #define PHY84834_PTP_NSW_SHDW_CLR_LOAD_TIME_COUNT \ 2238 (PHY84834_PTP_NSW_SHDW_CLR_LOAD_TIME | \ 2239 PHY84834_PTP_NSW_SHDW_CLR_LOAD_COUNT_LOW | \ 2240 PHY84834_PTP_NSW_SHDW_CLR_LOAD_COUNT_HIGH) 2241 2242 /* 2243 * PTP_NSE_SHDW_ORG_TS_0 2244 */ 2245 #define PHY84834_PTP_NSE_SHDW_ORG_TS_0_REG (0xd890) 2246 2247 2248 /* 2249 * PTP_NSE_SHDW_ORG_TS_1 2250 */ 2251 #define PHY84834_PTP_NSE_SHDW_ORG_TS_1_REG (0xd891) 2252 2253 2254 /* 2255 * PTP_NSE_SHDW_ORG_TS_2 2256 */ 2257 #define PHY84834_PTP_NSE_SHDW_ORG_TS_2_REG (0xd892) 2258 2259 /* 2260 * PTP_NSE_SHDW_ORG_TS_3 2261 */ 2262 #define PHY84834_PTP_NSE_SHDW_ORG_TS_3_REG (0xd893) 2263 2264 /* 2265 * PTP_NSE_SHDW_ORG_TS_4 2266 */ 2267 #define PHY84834_PTP_NSE_SHDW_ORG_TS_4_REG (0xd894) 2268 2269 2270 /* 2271 * PTP_NSE_SC_CFG 2272 */ 2273 #define PHY84834_PTP_NSE_SC_CFG_REG (0xd8a0) 2274 2275 #define PHY84834_PTP_NSE_SC_CFG_FSYNC_TS_EN (1U<<13) 2276 #define PHY84834_PTP_NSE_SC_CFG_FSYNC_EN (1U<<12) 2277 #define PHY84834_PTP_NSE_SC_CFG_SO_MODE (1U<<9 | 1U<<8) 2278 #define PHY84834_PTP_NSE_SC_CFG_SI_MODE (1U<<6 | 1U<<5 | 1U<<4) 2279 #define PHY84834_PTP_NSE_SC_CFG_GS_MODE (1U<<1 | 1U<<0) 2280 2281 2282 /* 2283 * PTP_NSE_SYNCIN_FSYNC_LEN_0 2284 */ 2285 #define PHY84834_NSE_SYNCIN_FSYNC_LEN_0_REG (0xd8a1) 2286 2287 2288 /* 2289 * PTP_NSE_SYNCIN_FSYNC_LEN_1 2290 */ 2291 #define PHY84834_NSE_SYNCIN_FSYNC_LEN_1_REG (0xd8a2) 2292 2293 /* 2294 * PTP_NSE_SYNCIN_FSYNC_DLY_0 2295 */ 2296 #define PHY84834_NSE_SYNCIN_FSYNC_DLY_0_REG (0xd8a3) 2297 2298 2299 /* 2300 * PTP_NSE_SYNCIN_FSYNC_DLY_1 2301 */ 2302 #define PHY84834_NSE_SYNCIN_FSYNC_DLY_1_REG (0xd8a4) 2303 2304 2305 /* 2306 * PTP_NSE_SOUT_TS_CMP_0 2307 */ 2308 #define PHY84834_PTP_NSE_SOUT_TS_CMP_0_REG (0xd8a5) 2309 2310 2311 /* 2312 * PTP_NSE_SOUT_TS_CMP_1 2313 */ 2314 #define PHY84834_PTP_NSE_SOUT_TS_CMP_1_REG (0xd8a6) 2315 2316 /* 2317 * PTP_NSE_SOUT_TS_CMP_2 2318 */ 2319 #define PHY84834_PTP_NSE_SOUT_TS_CMP_2_REG (0xd8a7) 2320 2321 /* 2322 * PTP_NSE_SHDW_DPLL_SYNC_DIV 2323 */ 2324 #define PHY84834_PTP_NSE_SHDW_DPLL_SYNC_DIV_REG (0xd8a8) 2325 2326 2327 /* 2328 * PTP_NSE_SHDW_SOUT_INTERVAL_0 2329 */ 2330 #define PHY84834_PTP_NSE_SHDW_SOUT_INTERVAL_0_REG (0xd8a9) 2331 2332 2333 /* 2334 * PTP_NSE_SHDW_SOUT_INTERVAL_1 2335 */ 2336 #define PHY84834_PTP_NSE_SHDW_SOUT_INTERVAL_1_REG (0xd8aa) 2337 2338 /* 2339 * PTP_NSE_SHDW_SOUT_PULSE1_LEN 2340 */ 2341 #define PHY84834_PTP_NSE_SHDW_SOUT_PULSE1_LEN_REG (0xd8ab) 2342 2343 2344 /* 2345 * PTP_NSE_SHDW_SOUT_PULSE2_LEN 2346 */ 2347 #define PHY84834_PTP_NSE_SHDW_SOUT_PULSE2_LEN_REG (0xd8ac) 2348 2349 2350 /* 2351 * PTP_NSE_SC_TS_FSYNC_0 2352 */ 2353 #define PHY84834_PTP_NSE_SC_COUNTSTAMP_FSYNC_0_REG (0xd8b0) 2354 2355 2356 /* 2357 * PTP_NSE_SC_TS_FSYNC_1 2358 */ 2359 #define PHY84834_PTP_NSE_SC_COUNTSTAMP_FSYNC_1_REG (0xd8b1) 2360 2361 2362 /* 2363 * PTP_NSE_SC_TS_FSYNC_2 2364 */ 2365 #define PHY84834_PTP_NSE_SC_COUNTSTAMP_FSYNC_2_REG (0xd8b2) 2366 2367 #define PHY84834_PTP_NSE_SC_TIMESTAMP_FSYNC_0_REG (0xd8b3) 2368 #define PHY84834_PTP_NSE_SC_TIMESTAMP_FSYNC_1_REG (0xd8b4) 2369 #define PHY84834_PTP_NSE_SC_TIMESTAMP_FSYNC_2_REG (0xd8b5) 2370 #define PHY84834_PTP_NSE_SC_TIMESTAMP_FSYNC_3_REG (0xd8b6) 2371 #define PHY84834_PTP_NSE_SC_TIMESTAMP_FSYNC_4_REG (0xd8b7) 2372 2373 #define PHY84834_PTP_NSE_NTP_TIMESTAMP_FSYNC_0_REG (0xd8b8) 2374 #define PHY84834_PTP_NSE_NTP_TIMESTAMP_FSYNC_1_REG (0xd8b9) 2375 #define PHY84834_PTP_NSE_NTP_TIMESTAMP_FSYNC_2_REG (0xd8ba) 2376 #define PHY84834_PTP_NSE_NTP_TIMESTAMP_FSYNC_3_REG (0xd8bb) 2377 2378 2379 /* 2380 * PTP_NSE_DPLL_SHDW_GAIN_1 2381 */ 2382 #define PHY84834_PTP_NSE_DPLL_SHDW_GAIN_1_REG (0xd8c1) 2383 2384 2385 /* 2386 * PTP_NSE_DPLL_SHDW_GAIN_2 2387 */ 2388 #define PHY84834_PTP_NSE_DPLL_SHDW_GAIN_2_REG (0xd8c2) 2389 2390 2391 /* 2392 * PTP_NSE_DPLL_SHDW_GAIN_3 2393 */ 2394 #define PHY84834_PTP_NSE_DPLL_SHDW_GAIN_3_REG (0xd8c3) 2395 2396 2397 /* 2398 * PTP_NSE_DPLL_SHDW_REF_PERIOD_0 2399 */ 2400 #define PHY84834_PTP_NSE_DPLL_SHDW_REF_PERIOD_0_REG (0xd8c4) 2401 2402 /* 2403 * PTP_NSE_DPLL_SHDW_REF_PERIOD_1 2404 */ 2405 #define PHY84834_PTP_NSE_DPLL_SHDW_REF_PERIOD_1_REG (0xd8c5) 2406 2407 2408 /* 2409 * PTP_NSE_DPLL_SHDW_REF_PHASE_0 2410 */ 2411 #define PHY84834_PTP_NSE_DPLL_SHDW_REF_PHASE_0_REG (0xd8c6) 2412 2413 2414 /* 2415 * PTP_NSE_SHDW_REF_PHASE_1 2416 */ 2417 #define PHY84834_PTP_NSE_DPLL_SHDW_REF_PHASE_1_REG (0xd8c7) 2418 2419 2420 /* 2421 * PTP_NSE_SHDW_REF_PHASE_2 2422 */ 2423 #define PHY84834_PTP_NSE_DPLL_SHDW_REF_PHASE_2_REG (0xd8c8) 2424 2425 2426 /* 2427 * PTP_NSE_NCO_CFG 2428 */ 2429 #define PHY84834_PTP_NSE_NCO_CFG_REG (0xd8e0) 2430 2431 #define PHY84834_PTP_NSE_NCO_CFG_FCW_SEL (1U<<0) 2432 #define NCO_SHADOW_REG_STATIC_FCW 0 2433 #define NCO_DYNAMIC_DPLL_FCW 1 2434 2435 2436 /* 2437 * PTP_NSE_NCO_SHADOW_FCW_0 2438 */ 2439 #define PHY84834_NSE_NCO_SHADOW_FCW_0_REG (0xd8e1) 2440 2441 2442 /* 2443 * PTP_NSE_NCO_SHADOW_FCW_1 2444 */ 2445 #define PHY84834_NSE_NCO_SHADOW_FCW_1_REG (0xd8e2) 2446 2447 2448 /* 2449 * PTP_NSE_NCO_SHADOW_TIME_HIGH_0 2450 */ 2451 #define PHY84834_NSE_NCO_SHADOW_TIME_HIGH_0_REG (0xd8e5) 2452 2453 2454 /* 2455 * PTP_NSE_NCO_SHADOW_TIME_HIGH_1 2456 */ 2457 #define PHY84834_NSE_NCO_SHADOW_TIME_HIGH_1_REG (0xd8e6) 2458 2459 2460 /* 2461 * PTP_NSE_NCO_SHADOW_TIME_HIGH_2 2462 */ 2463 #define PHY84834_NSE_NCO_SHADOW_TIME_HIGH_2_REG (0xd8e7) 2464 2465 2466 /* 2467 * PTP_TS_EG_SOP_OFFSET_0 2468 */ 2469 #define PHY84834_PTP_TS_EG_SOP_OFFSET_0_REG (0xd908) 2470 2471 2472 /* 2473 * PTP_TS_EG_SOP_OFFSET_1 2474 */ 2475 #define PHY84834_PTP_TS_EG_SOP_OFFSET_1_REG (0xd909) 2476 2477 /* 2478 * PTP_TS_IG_SOP_OFFSET_0 2479 */ 2480 #define PHY84834_PTP_TS_IG_SOP_OFFSET_0_REG (0xd910) 2481 2482 2483 /* 2484 * PTP_TS_IG_SOP_OFFSET_1 2485 */ 2486 #define PHY84834_PTP_TS_IG_SOP_OFFSET_1_REG (0xd911) 2487 2488 2489 2490 /* 2491 * PTP_VLAN_1TAG_TPID 2492 */ 2493 #define PHY84834_PTP_VLAN_1TAG_TPID_REG (0xd990) 2494 2495 /* 2496 * PTP_VLAN_2TAG_OTPID 2497 */ 2498 #define PHY84834_PTP_VLAN_2TAG_OTPID_REG (0xd991) 2499 2500 /* 2501 * PTP_VLAN_2TAG_OTPID_1 2502 */ 2503 #define PHY84834_PTP_VLAN_2TAG_OTPID_1_REG (0xd992) 2504 2505 2506 /* 2507 * PTP_EG_CFG 2508 */ 2509 #define PHY84834_PTP_EG_CFG_REG (0xda01) 2510 2511 #define PHY84834_PTP_EG_CFG_L4_IP6_UDP_ACH_EN (1U<<13) 2512 #define PHY84834_PTP_EG_CFG_L4_IP4_UDP_ACH_EN (1U<<9) 2513 #define PHY84834_PTP_EG_CFG_L2_802AS_ACH_EN (1U<<8) 2514 #define PHY84834_PTP_EG_CFG_L4_IP6_UDP_EN (1U<<6) 2515 #define PHY84834_PTP_EG_CFG_L4_IP4_UDP_EN (1U<<5) 2516 #define PHY84834_PTP_EG_CFG_L2_802AS_EN (1U<<4) 2517 #define PHY84834_PTP_EG_CFG_FCS_CHECK_EN (1U<<0) 2518 2519 /* 2520 * PTP_EG_PTP_PKT_CFG 2521 */ 2522 #define PHY84834_PTP_EG_PTP_PKT_CFG_REG (0xda08) 2523 2524 #define PHY84834_PTP_EG_PTP_PKT_CFG_ACTION_PTP_SYNC (0x7 << 0) 2525 #define PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_SYNC (0x8 << 0) 2526 #define PHY84834_PTP_EG_PTP_PKT_CFG_ACTION_PTP_DREQ (0x7 << 4) 2527 #define PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_DREQ (0x8 << 4) 2528 #define PHY84834_PTP_EG_PTP_PKT_CFG_ACTION_PTP_PDREQ (0x7 << 8) 2529 #define PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_PDREQ (0x8 << 8) 2530 #define PHY84834_PTP_EG_PTP_PKT_CFG_ACTION_PTP_PDRESP (0x7 << 12) 2531 #define PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_PDRESP (0x8 << 12) 2532 #define PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_ALL \ 2533 (PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_SYNC | \ 2534 PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_DREQ | \ 2535 PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_PDREQ | \ 2536 PHY84834_PTP_EG_PTP_PKT_CFG_CAPT_PTP_PDRESP) 2537 2538 /* 2539 * PTP_IG_CFG 2540 */ 2541 #define PHY84834_PTP_IG_CFG_REG (0xda81) 2542 2543 #define PHY84834_PTP_IG_CFG_L4_IP6_UDP_ACH_EN (1U<<13) 2544 #define PHY84834_PTP_IG_CFG_L4_IP4_UDP_ACH_EN (1U<<9) 2545 #define PHY84834_PTP_IG_CFG_L2_802AS_ACH_EN (1U<<8) 2546 #define PHY84834_PTP_IG_CFG_L4_IP6_UDP_EN (1U<<6) 2547 #define PHY84834_PTP_IG_CFG_L4_IP4_UDP_EN (1U<<5) 2548 #define PHY84834_PTP_IG_CFG_L2_802AS_EN (1U<<4) 2549 #define PHY84834_PTP_IG_CFG_FCS_CHECK_EN (1U<<0) 2550 2551 2552 /* 2553 * PTP_IG_PTP_PKT_CFG 2554 */ 2555 #define PHY84834_PTP_IG_PTP_PKT_CFG_REG (0xda88) 2556 2557 #if 0 2558 #define PHY84834_PTP_IG_PTP_PKT_CFG_ACTION_PTP_SYNC (0x7) 2559 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_SYNC (1U<<3) 2560 #define PHY84834_PTP_IG_PTP_PKT_CFG_ACTION_PTP_DREQ (0x07) 2561 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_DREQ (1U<<7) 2562 #define PHY84834_PTP_IG_PTP_PKT_CFG_ACTION_PTP_PDREQ (0x007) 2563 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_PDREQ (1U<<11) 2564 #define PHY84834_PTP_IG_PTP_PKT_CFG_ACTION_PTP_PDRESP (0x7000) 2565 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_PDRESP (1U<<15) 2566 #endif 2567 2568 #define PHY84834_PTP_IG_PTP_PKT_CFG_ACTION_PTP_SYNC (0x7 << 0) 2569 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_SYNC (0x8 << 0) 2570 #define PHY84834_PTP_IG_PTP_PKT_CFG_ACTION_PTP_DREQ (0x7 << 4) 2571 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_DREQ (0x8 << 4) 2572 #define PHY84834_PTP_IG_PTP_PKT_CFG_ACTION_PTP_PDREQ (0x7 << 8) 2573 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_PDREQ (0x8 << 8) 2574 #define PHY84834_PTP_IG_PTP_PKT_CFG_ACTION_PTP_PDRESP (0x7 << 12) 2575 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_PDRESP (0x8 << 12) 2576 #define PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_ALL \ 2577 (PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_SYNC | \ 2578 PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_DREQ | \ 2579 PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_PDREQ | \ 2580 PHY84834_PTP_IG_PTP_PKT_CFG_CAPT_PTP_PDRESP) 2581 2582 #define PHY84834_PTP_PARSER_EG_CNTR_ALL_PKT_EN (0xda20) 2583 #define PHY84834_PTP_PARSER_EG_CNTR_ALL_PKT_CLR (0xda21) 2584 #define PHY84834_PTP_PARSER_EG_CNTR_ALL_PKT_0 (0xda28) 2585 #define PHY84834_PTP_PARSER_EG_CNTR_ALL_PKT_1 (0xda29) 2586 #define PHY84834_PTP_PARSER_EG_CNTR_PTP_PKT_EN (0xda30) 2587 #define PHY84834_PTP_PARSER_EG_CNTR_PTP_PKT_CLR (0xda31) 2588 #define PHY84834_PTP_PARSER_EG_CNTR_PTP_PKT (0xda38) 2589 2590 #define PHY84834_PTP_PARSER_IG_CNTR_ALL_PKT_EN (0xdaa0) 2591 #define PHY84834_PTP_PARSER_IG_CNTR_ALL_PKT_CLR (0xdaa1) 2592 #define PHY84834_PTP_PARSER_IG_CNTR_ALL_PKT_0 (0xdaa8) 2593 #define PHY84834_PTP_PARSER_IG_CNTR_ALL_PKT_1 (0xdaa9) 2594 #define PHY84834_PTP_PARSER_IG_CNTR_PTP_PKT_EN (0xdab0) 2595 #define PHY84834_PTP_PARSER_IG_CNTR_PTP_PKT_CLR (0xdab1) 2596 #define PHY84834_PTP_PARSER_IG_CNTR_PTP_PKT (0xdab8) 2597 2598 #define PHY84834_PTP_PIC_FIFO_CTL_REG (0xdb08) 2599 #define PHY84834_PTP_PIC_FIFO_STAT_REG (0xdb09) 2600 2601 /* 2602 * PIC Configuration Register (PIC_SOURCE_PORT / PIC_STAMP_SEL) 2603 */ 2604 #define PHY8486X_PTP_PIC_CONFIG_REG (0xdb01) 2605 #define PHY8486X_PTP_PIC_CONFIG_FULL_SRC_PORT BIT(1) 2606 #define PHY8486X_PTP_PIC_CONFIG_LONG_TIMESTAMP BIT(0) 2607 #define PHY8486X_PTP_PIC_CONFIG_MASK \ 2608 (PHY8486X_PTP_PIC_CONFIG_FULL_SRC_PORT | \ 2609 PHY8486X_PTP_PIC_CONFIG_LONG_TIMESTAMP) 2610 2611 /* 2612 * PTP_PIC_FIFO_RD_PKT_TS_0 1 2 2613 */ 2614 #define PHY84834_PTP_PIC_FIFO_RD_PKT_TS_0_REG (0xdb20) 2615 #define PHY84834_PTP_PIC_FIFO_RD_PKT_TS_1_REG (0xdb21) 2616 #define PHY84834_PTP_PIC_FIFO_RD_PKT_TS_2_REG (0xdb22) 2617 #define PHY84834_PTP_PIC_FIFO_RD_PKT_TS_3_REG (0xdb23) 2618 #define PHY84834_PTP_PIC_FIFO_RD_PKT_TS_4_REG (0xdb24) 2619 2620 /* 2621 #define PHY84834_PTP_PIC_FIFO_RD_PKT_TS_0_REG (0xdb10) 2622 #define PHY84834_PTP_PIC_FIFO_RD_PKT_TS_1_REG (0xdb11) 2623 #define PHY84834_PTP_PIC_FIFO_RD_PKT_TS_2_REG (0xdb12) 2624 */ 2625 2626 /* 2627 * PTP_INBAND_CONTROL 2628 */ 2629 #define PHY848XX_PTP_INBAND_CNTL_REG (0xdc00) 2630 2631 #define PHY848XX_PTP_INBAND_CNTL_IP_ADDR_EN BIT(15) 2632 #define PHY848XX_PTP_INBAND_CNTL_IP_MAC_SEL BIT(14) 2633 #define PHY848XX_PTP_INBAND_CNTL_TS_SEL BIT(13) 2634 #define PHY848XX_PTP_INBAND_CNTL_TS_UPD_DELAY_RSP BIT(12) 2635 #define PHY848XX_PTP_INBAND_CNTL_TS_UPD_FOLLOW_UP BIT(11) 2636 #define PHY848XX_PTP_INBAND_CNTL_TS_CAP_MODE BIT(10) 2637 #define PHY848XX_PTP_INBAND_CNTL_RESV0_ID_UPDATE BIT(9) 2638 #define PHY848XX_PTP_INBAND_CNTL_RESV0_ID_CHECK BIT(8) 2639 #define PHY848XX_PTP_INBAND_CNTL_RESV0_ID (BIT(7)|BIT(6)|BIT(5)|BIT(4)) 2640 #define PHY848XX_PTP_INBAND_CNTL_PRSP_EN BIT(3) 2641 #define PHY848XX_PTP_INBAND_CNTL_PREQ_EN BIT(2) 2642 #define PHY848XX_PTP_INBAND_CNTL_DREQ_EN BIT(1) 2643 #define PHY848XX_PTP_INBAND_CNTL_SYNC_EN BIT(0) 2644 #define PHY848XX_PTP_INBAND_CNTL_EN \ 2645 (PHY848XX_PTP_INBAND_CNTL_PRSP_EN | \ 2646 PHY848XX_PTP_INBAND_CNTL_PREQ_EN | \ 2647 PHY848XX_PTP_INBAND_CNTL_DREQ_EN | \ 2648 PHY848XX_PTP_INBAND_CNTL_SYNC_EN) 2649 #define PHY848XX_PTP_INBAND_CNTL_RESV0_ID_SHIFT (4) 2650 2651 /* 2652 * PTP_INBAND_CONTROL_2 2653 */ 2654 #define PHY848XX_PTP_INBAND_CTL2_REG (0xdc01) 2655 2656 #define PHY848XX_PTP_INBAND_CTL2_CMP_VLAN_ID BIT(2) 2657 #define PHY848XX_PTP_INBAND_CTL2_CMP_SRC_PORT BIT(1) 2658 #define PHY848XX_PTP_INBAND_CTL2_CMP_IP_ADDR BIT(0) 2659 #define PHY848XX_PTP_INBAND_CTL2_CMP_MASK \ 2660 (PHY848XX_PTP_INBAND_CTL2_CMP_VLAN_ID | \ 2661 PHY848XX_PTP_INBAND_CTL2_CMP_SRC_PORT | \ 2662 PHY848XX_PTP_INBAND_CTL2_CMP_IP_ADDR) 2663 2664 #endif /* _PHY8481_H_ */