phy84793.h (622015B)
1 /*************************************************************************** 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * Copyright (c) 1999-2013, Broadcom Corporation 7 * All Rights Reserved 8 * Confidential Property of Broadcom Corporation 9 * 10 * 11 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 12 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 13 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 14 * 15 * $brcm_Workfile: $ 16 * $brcm_Revision: $ 17 * $brcm_Date: $ 18 * 19 * Module Description: 20 * DO NOT EDIT THIS FILE DIRECTLY 21 * 22 * This module was generated magically with RDB from a source description 23 * file. You must edit the source file for changes to be made to this file. 24 * 25 * 26 * Date: Generated on Sun Feb 17 21:44:14 2013 27 * MD5 Checksum d546e11aade78f6ba77a368ccf3444ae 28 * 29 * Compiled with: RDB Utility 5.0 30 * RDB Parser 3.0 31 * rdb2macro.pm 4.0 32 * Perl Interpreter 5.008008 33 * Operating System linux 34 * 35 * Spec Versions: common_por_regs 1 36 * ctl_regs 1 37 * hs_rx_cdr 1 38 * hs_rx_cdr_cm 1 39 * hs_rx_cdr_sh 1 40 * hs_tx_cdr_tpc 1 41 * ieee_pma_pmd_control_2_regs1 42 * ieee_pma_pmd_regs 1 43 * rg_rx 2 44 * rg_tx 2 45 * slice_regs 1 46 * vsr40_rx_ana25g 1 47 * vsr40_rx_dig_regs 1 48 * vsr40_rx_pll 1 49 * vsr40_tx_ana25g 1 50 * vsr40_tx_dig_regs 1 51 * vsr40_tx_pll 1 52 * 53 * RDB Files: /projects/ntsw-sw2/home/arunkuma/enzo_sdk/sdk/src/soc/phy/regs/scripts/Linux/single_rdb.rdb 54 * 55 * Revision History: 56 * 57 * $brcm_Log: $ 58 */ 59 60 #ifndef PHY84793_H__ 61 #define PHY84793_H__ 62 63 /** 64 * m = memory, c = core, r = register, f = field, d = data. 65 */ 66 #if !defined(GET_FIELD) && !defined(SET_FIELD) 67 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 68 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 69 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 70 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 71 72 #define GET_FIELD(m,c,r,f) \ 73 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 74 75 #define SET_FIELD(m,c,r,f,d) \ 76 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 77 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 78 ) 79 80 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 81 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 82 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 83 84 #endif /* GET & SET */ 85 86 /* PHY84793 MACROS */ 87 #define PHY84793_C45_DEV_PMA_PMD 0x01 88 89 #define PHY84793_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 90 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 91 #define PHY84793_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 92 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 93 #define PHY84793_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 94 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 95 96 /* PMA/PMD Device (Dev Addr 1) */ 97 #define READ_PHY84793_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 98 PHY84793_REG_READ((_unit), (_phy_ctrl), \ 99 SOC_PHY_CLAUSE45_ADDR(PHY84793_C45_DEV_PMA_PMD, (_reg)), (_val)) 100 #define WRITE_PHY84793_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 101 PHY84793_REG_WRITE((_unit), (_phy_ctrl), \ 102 SOC_PHY_CLAUSE45_ADDR(PHY84793_C45_DEV_PMA_PMD, (_reg)), (_val)) 103 #define MODIFY_PHY84793_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 104 PHY84793_REG_MODIFY((_unit), (_phy_ctrl), \ 105 SOC_PHY_CLAUSE45_ADDR(PHY84793_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask)) 106 107 /**************************************************************************** 108 * Core Enums. 109 */ 110 /**************************************************************************** 111 * common_por_regs_regs 112 */ 113 #define COMMON_POR_REGS_BOOT_POR 0x0000f416 /* Micro boot registers */ 114 115 116 /**************************************************************************** 117 * ctl_regs_regs 118 */ 119 #define CTL_REGS_TX_EEPROM_CONTROL 0x0000f351 /* TX EEPROM control register. */ 120 #define CTL_REGS_COMMON_CHIP_ID 0x0000f400 /* COMMON_CHIPID */ 121 #define CTL_REGS_COMMON_REV_ID 0x0000f401 /* COMMON_REVID */ 122 #define CTL_REGS_COMMON_CTRL1 0x0000f402 /* COMMON_CTRL1 */ 123 #define CTL_REGS_USER_MODESEL_REG 0x0000f403 /* COMMON_USER_MODESEL_REG */ 124 #define CTL_REGS_REFCLK_SEL_REG 0x0000f404 /* COMMON_USER_MODESEL_REG */ 125 #define CTL_REGS_COMMON_CTRL2 0x0000f405 /* COMMON_CTRL2 */ 126 #define CTL_REGS_COMMON_STATUS1 0x0000f406 /* COMMON_STATUS1 */ 127 #define CTL_REGS_IEEE_MODESEL_DEFAULT 0x0000f407 /* IEEE Modesel Default value */ 128 #define CTL_REGS_LED_CTRL 0x0000f408 /* Controls LED activity */ 129 #define CTL_REGS_EISR 0x0000f409 /* External Interrupt Status Register (EISR) */ 130 #define CTL_REGS_EIMR 0x0000f40a /* External Interrupt Mask Register (EIMR) */ 131 #define CTL_REGS_EIPR 0x0000f40b /* External Interrupt Pending Register (EIPR) */ 132 #define CTL_REGS_PWRUP 0x0000f40c /* Power up state machine control & status */ 133 #define CTL_REGS_MISR 0x0000f40e /* Micro Interrupt Status Register (MISR) */ 134 #define CTL_REGS_MIMR 0x0000f40f /* Micro Interrupt Mask Register (MIMR) */ 135 #define CTL_REGS_MIPM 0x0000f411 /* Micro Interrupt Pending Register (MIPR) */ 136 #define CTL_REGS_MSCR 0x0000f412 /* Micro Subsystem Configuration Register (MSCR) */ 137 #define CTL_REGS_MSGOUT 0x0000f413 /* Outgoing message from micro to external world. */ 138 #define CTL_REGS_MSGIN 0x0000f414 /* Incoming message to micro from external world */ 139 #define CTL_REGS_BOOT 0x0000f415 /* Micro boot registers */ 140 #define CTL_REGS_GPREG0 0x0000f417 /* general-purpose scratch-pad register 0 for micro/external communications */ 141 #define CTL_REGS_GPREG1 0x0000f418 /* general-purpose scratch-pad register 1 for micro/external communications */ 142 #define CTL_REGS_GPREG2 0x0000f419 /* general-purpose scratch-pad register 2 for micro/external communications */ 143 #define CTL_REGS_GPREG3 0x0000f41a /* general-purpose scratch-pad register 3 for micro/external communications */ 144 #define CTL_REGS_GPREG4 0x0000f41b /* general-purpose scratch-pad register 4 for micro/external communications */ 145 #define CTL_REGS_GPREG5 0x0000f41c /* general-purpose scratch-pad register 5 for micro/external communications */ 146 #define CTL_REGS_GPREG6 0x0000f41d /* general-purpose scratch-pad register 6 for micro/external communications */ 147 #define CTL_REGS_GPREG7 0x0000f41e /* general-purpose scratch-pad register 7 for micro/external communications */ 148 #define CTL_REGS_GPREG8 0x0000f41f /* general-purpose scratch-pad register 8 for micro/external communications */ 149 #define CTL_REGS_GPREG9 0x0000f420 /* general-purpose scratch-pad register 9 for micro/external communications */ 150 #define CTL_REGS_GPREG10 0x0000f421 /* general-purpose scratch-pad register 10 for micro/external communications */ 151 #define CTL_REGS_GPREG11 0x0000f422 /* general-purpose scratch-pad register 11 for micro/external communications */ 152 #define CTL_REGS_GPREG12 0x0000f423 /* general-purpose scratch-pad register 12 for micro/external communications */ 153 #define CTL_REGS_GPREG13 0x0000f424 /* general-purpose scratch-pad register 13 for micro/external communications */ 154 #define CTL_REGS_GPREG14 0x0000f425 /* general-purpose scratch-pad register 14 for micro/external communications */ 155 #define CTL_REGS_GPREG15 0x0000f426 /* general-purpose scratch-pad register 15 for micro/external communications */ 156 #define CTL_REGS_FW_ENABLE_TYPE 0x0000f427 /* Register to enable proprietary firmware features */ 157 #define CTL_REGS_SYS_RX_RESET 0x0000f435 /* System side Rx Lane Reset */ 158 #define CTL_REGS_SYS_TX_RESET 0x0000f436 /* System side Tx Lane Reset */ 159 #define CTL_REGS_LINE_RX_RESET 0x0000f437 /* Line side Rx Lane Reset */ 160 #define CTL_REGS_LINE_TX_RESET 0x0000f438 /* Line side Tx Lane Reset */ 161 #define CTL_REGS_DC_RESET 0x0000f439 /* Deca Core common Resets */ 162 #define CTL_REGS_FRC_DC_HW_RESET 0x0000f43a /* Forces for Deca core HW resets */ 163 #define CTL_REGS_DC_HW_RESET 0x0000f43b /* Deca core HW Resets */ 164 #define CTL_REGS_FRC_DC_MDIO_RESET 0x0000f43c /* Forces for Deca core mdio resets */ 165 #define CTL_REGS_DC_MDIO_RESET 0x0000f43d /* Deca core mdio resets */ 166 #define CTL_REGS_FRC_HCTX_DIG_RESET 0x0000f43e /* Forces for Hexa Core Tx dig resets */ 167 #define CTL_REGS_HCTX_DIG_RESET 0x0000f43f /* Hexa Core Tx dig resets */ 168 #define CTL_REGS_FRC_HCTX_MDIO_RESET 0x0000f440 /* Forces for Hexa Core Tx mdio resets */ 169 #define CTL_REGS_HCTX_MDIO_RESET 0x0000f441 /* Hexa Core Tx mdio resets */ 170 #define CTL_REGS_FRC_HCRX_DIG_RESET 0x0000f442 /* Forces for Hexa Core Rx dig resets */ 171 #define CTL_REGS_HCRX_DIG_RESET 0x0000f443 /* Hexa Core Rx dig resets */ 172 #define CTL_REGS_FRC_HCRX_MDIO_RESET 0x0000f444 /* Forces for Hexa Core Rx mdio resets */ 173 #define CTL_REGS_HCRX_MDIO_RESET 0x0000f445 /* Hexa Core Rx mdio resets */ 174 #define CTL_REGS_FRC_DCRX_PD 0x0000f446 /* Forces for Deca Core Rx Lanes Power down */ 175 #define CTL_REGS_DCRX_PD 0x0000f447 /* Deca Core Rx Lanes Power down */ 176 #define CTL_REGS_FRC_DCTX_PD 0x0000f448 /* Forces for Deca Core Tx Lanes Power down */ 177 #define CTL_REGS_DCTX_PD 0x0000f449 /* Deca Core Tx Lanes Power down */ 178 #define CTL_REGS_FRC_HCRX_PD 0x0000f44a /* Forces for Hexa Core Rx Lanes Power down */ 179 #define CTL_REGS_HCRX_PD 0x0000f44b /* Hexa Core Rx Lanes Power down */ 180 #define CTL_REGS_FRC_HCTX_PD 0x0000f44c /* Forces for Hexa Core Tx Lanes Power down */ 181 #define CTL_REGS_HCTX_PD 0x0000f44d /* Hexa Core Tx Lanes Power down */ 182 #define CTL_REGS_FRC_VSR40_TX_PD 0x0000f44e /* Forces for VSR40 Tx Lanes Power down */ 183 #define CTL_REGS_VSR40_TX_PD 0x0000f44f /* VSR40 Tx Lanes Power down */ 184 #define CTL_REGS_FRC_VSR40_RX_PD 0x0000f450 /* Forces for VSR40 Rx Lanes Power down */ 185 #define CTL_REGS_VSR40_RX_PD 0x0000f451 /* VSR40 Rx Lanes Power down */ 186 #define CTL_REGS_PCB_CTRL_TYPE 0x0000f452 /* PCB bus control register */ 187 #define CTL_REGS_PCB_ADR_MSW_TYPE 0x0000f453 /* PCB address MSW register */ 188 #define CTL_REGS_PCB_ADR_LSW_TYPE 0x0000f454 /* PCB address LSW register */ 189 #define CTL_REGS_PCB_DATA_IN_TYPE 0x0000f455 /* PCB write value register */ 190 #define CTL_REGS_PCB_DATA_OUT_TYPE 0x0000f456 /* PCB read value register */ 191 #define CTL_REGS_SYS_LOOPBACK_EN 0x0000f457 /* System Loopback Enable */ 192 #define CTL_REGS_LINE_LOOPBACK_EN 0x0000f458 /* Line Loopback Enable */ 193 #define CTL_REGS_PVTMON_CTRL1 0x0000f45b /* PVTMON control1 */ 194 #define CTL_REGS_PVTMON_CTRL2 0x0000f45c /* PVTMON control2 */ 195 #define CTL_REGS_PVTMON_CTRL3 0x0000f45d /* PVTMON control3 */ 196 #define CTL_REGS_PVTMON_CTRL4 0x0000f45e /* PVTMON control4 */ 197 #define CTL_REGS_PVTMON_STATUS 0x0000f45f /* PVTMON status */ 198 #define CTL_REGS_RESCAL_CTRL 0x0000f460 /* resistor calibration control */ 199 #define CTL_REGS_RESCAL_STATUS 0x0000f461 /* resistor calibration status */ 200 #define CTL_REGS_PAD_OSC_CONTROL 0x0000f462 /* Pad oscillator control */ 201 #define CTL_REGS_OTP_CTRL_STATUS 0x0000f463 /* OTP control and status */ 202 #define CTL_REGS_VREGCNTL_TYPE 0x0000f464 /* voltage regulator configuration bits */ 203 #define CTL_REGS_FRC_LINE_LN 0x0000f466 /* Forces for enabling line side lanes */ 204 #define CTL_REGS_LINE_LN 0x0000f467 /* Enables for line side lanes */ 205 #define CTL_REGS_FRC_SYS_LN 0x0000f468 /* Forces for enabling sys side lanes */ 206 #define CTL_REGS_SYS_LN 0x0000f469 /* Enables for sys side lanes */ 207 #define CTL_REGS_GPIO_0_CTRL_STATUS 0x0000f470 /* gpio 0 control and status */ 208 #define CTL_REGS_GPIO_1_CTRL_STATUS 0x0000f471 /* gpio 1 control and status */ 209 #define CTL_REGS_GPIO_2_CTRL_STATUS 0x0000f472 /* gpio 2 control and status */ 210 #define CTL_REGS_GPIO_3_CTRL_STATUS 0x0000f473 /* gpio 3 control and status */ 211 #define CTL_REGS_GPIO_4_CTRL_STATUS 0x0000f474 /* gpio 4 control and status */ 212 #define CTL_REGS_GPIO_5_CTRL_STATUS 0x0000f475 /* gpio 5 control and status */ 213 #define CTL_REGS_STATUS_CTRL1 0x0000f476 /* Status pin control1 */ 214 #define CTL_REGS_STATUS_CTRL2 0x0000f477 /* Status pin control2 */ 215 #define CTL_REGS_INPUT_STATUS 0x0000f478 /* Control Input pin latched status */ 216 #define CTL_REGS_IEEE_REGS_RST_LATCH 0x0000f479 /* IEEE regs reset latched high status */ 217 #define CTL_REGS_DIS_SYS_CDR_LOCK 0x0000f47a /* Disable Sys CDR Lock status */ 218 #define CTL_REGS_DIS_SYS_SIGDET 0x0000f47b /* Disable Sys Sigdet status */ 219 #define CTL_REGS_DIS_LINE_CDR_LOCK 0x0000f47c /* Disable Line CDR Lock status */ 220 #define CTL_REGS_DIS_LINE_SIGDET 0x0000f47d /* Disable Line sigdet status */ 221 #define CTL_REGS_STATUS_MUX_CTRL 0x0000f47e /* Status Mux control */ 222 #define CTL_REGS_SEISR 0x0000f480 /* System side External Interrupt Status Register (SEISR) */ 223 #define CTL_REGS_SEIMR 0x0000f481 /* System side External Interrupt Mask Register (SEIMR) */ 224 #define CTL_REGS_SEIPR 0x0000f482 /* System side External Interrupt Pending Register (SEIPR) */ 225 #define CTL_REGS_LEISR 0x0000f483 /* Line side External Interrupt Status Register (LEISR) */ 226 #define CTL_REGS_LEIMR 0x0000f484 /* Line side External Interrupt Mask Register (LEIMR) */ 227 #define CTL_REGS_LEIPR 0x0000f485 /* Line side External Interrupt Pending Register (LEIPR) */ 228 #define CTL_REGS_SUSM_CM_CTRL1 0x0000f490 /* Common startup statemachine control1 */ 229 #define CTL_REGS_SUSM_LTX_CTRL1 0x0000f491 /* Line TX startup statemachine control1 */ 230 #define CTL_REGS_SUSM_LTX_CTRL2 0x0000f492 /* Line TX startup statemachine control2 */ 231 #define CTL_REGS_SUSM_LTX_CTRL3 0x0000f493 /* Line TX startup statemachine control3 */ 232 #define CTL_REGS_SUSM_LTX_CTRL4 0x0000f494 /* Line TX startup statemachine control4 */ 233 #define CTL_REGS_SUSM_LTX_CTRL5 0x0000f495 /* Line TX startup statemachine control5 */ 234 #define CTL_REGS_SUSM_LTX_CTRL6 0x0000f496 /* Line TX startup statemachine control6 */ 235 #define CTL_REGS_SUSM_LTX_CTRL7 0x0000f497 /* Line TX startup statemachine control7 */ 236 #define CTL_REGS_SUSM_LTX_CTRL8 0x0000f498 /* Line TX startup statemachine control8 */ 237 #define CTL_REGS_SUSM_LTX_CTRL9 0x0000f499 /* Line TX startup statemachine control9 */ 238 #define CTL_REGS_SUSM_LTX_CTRL10 0x0000f49a /* Line TX startup statemachine control10 */ 239 #define CTL_REGS_SUSM_LTX_CTRL11 0x0000f49b /* Line TX startup statemachine control11 */ 240 #define CTL_REGS_SUSM_LRX_CTRL1 0x0000f49c /* Line RX startup statemachine control1 */ 241 #define CTL_REGS_SUSM_LRX_CTRL2 0x0000f49d /* Line RX startup statemachine control2 */ 242 #define CTL_REGS_SUSM_LRX_CTRL3 0x0000f49e /* Line RX startup statemachine control3 */ 243 #define CTL_REGS_SUSM_SYS_CTRL1 0x0000f49f /* System startup statemachine control1 */ 244 #define CTL_REGS_SUSM_SYS_CTRL2 0x0000f4a0 /* Systemstartup statemachine control2 */ 245 #define CTL_REGS_SUSM_SYS_CTRL3 0x0000f4a1 /* System startup statemachine control3 */ 246 #define CTL_REGS_SUSM_SYS_CTRL4 0x0000f4a2 /* System startup statemachine control4 */ 247 #define CTL_REGS_SUSM_SYS_CTRL5 0x0000f4a3 /* System startup statemachine control5 */ 248 #define CTL_REGS_SUSM_SYS_CTRL6 0x0000f4a4 /* System startup statemachine control6 */ 249 #define CTL_REGS_SUSM_SYS_CTRL7 0x0000f4a5 /* System startup statemachine control7 */ 250 #define CTL_REGS_SUSM_SYS_CTRL8 0x0000f4a6 /* System startup statemachine control8 */ 251 #define CTL_REGS_SUSM_SYS_CTRL9 0x0000f4a7 /* System startup statemachine control9 */ 252 #define CTL_REGS_SUSM_SYS_CTRL10 0x0000f4a8 /* System startup statemachine control10 */ 253 #define CTL_REGS_SUSM_SYS_CTRL11 0x0000f4a9 /* System startup statemachine control11 */ 254 #define CTL_REGS_SUSM_SYS_CTRL12 0x0000f4aa /* System startup statemachine control12 */ 255 #define CTL_REGS_SUSM_SYS_CTRL13 0x0000f4ab /* System startup statemachine control13 */ 256 #define CTL_REGS_SUSM_SYS_CTRL14 0x0000f4ac /* System startup statemachine control14 */ 257 #define CTL_REGS_SUSM_STATUS1 0x0000f4ad /* Startup statemachine status1 */ 258 #define CTL_REGS_SUSM_STATUS2 0x0000f4ae /* Startup statemachine status2 */ 259 #define CTL_REGS_SUSM_STATUS3 0x0000f4af /* Startup statemachine status3 */ 260 #define CTL_REGS_SUSM_STATUS4 0x0000f4b0 /* Startup statemachine status4 */ 261 #define CTL_REGS_SUSM_STATUS5 0x0000f4b1 /* Startup statemachine status5 */ 262 #define CTL_REGS_SUSM_STATUS6 0x0000f4b2 /* Startup statemachine status6 */ 263 #define CTL_REGS_DEVICE_IDENTIFIER_LSB_CTRL1 0x0000f4b3 /* Dev ID LSB */ 264 #define CTL_REGS_DEVICE_IDENTIFIER_MSB_CTRL1 0x0000f4b4 /* Dev ID MSB */ 265 #define CTL_REGS_PACKAGE_IDENTIFIER_LSB_CTRL1 0x0000f4b5 /* Pkg ID LSB */ 266 #define CTL_REGS_PACKAGE_IDENTIFIER_MSB_CTRL1 0x0000f4b6 /* Pkg ID MSB */ 267 #define CTL_REGS_IP_TMUX_CTRL 0x0000f4c0 /* Hexacore & Decacore tmux output control */ 268 #define CTL_REGS_OTP_FOUT_3 0x0000f4c1 /* OTP Fout bus */ 269 #define CTL_REGS_OTP_FOUT_2 0x0000f4c2 /* OTP Fout bus */ 270 #define CTL_REGS_OTP_FOUT_1 0x0000f4c3 /* OTP Fout bus */ 271 #define CTL_REGS_OTP_FOUT_0 0x0000f4c4 /* OTP Fout bus */ 272 273 274 /**************************************************************************** 275 * hs_rx_cdr_regs 276 */ 277 #define HS_RX_CDR_CDR_RESET 0x00000000 /* CDR controls: Reset and enable */ 278 #define HS_RX_CDR_CDR_LOOP 0x00000001 /* CDR controls: Loop parameters */ 279 #define HS_RX_CDR_CDR_PE_OFFSET 0x00000002 /* CDR controls: Phase error offset */ 280 #define HS_RX_CDR_CDR_INTEG 0x00000003 /* CDR controls: integ initial value */ 281 #define HS_RX_CDR_CDR_NCO_RDP 0x00000004 /* PI controls: initial phases for NCO at 0 and 90 degrees */ 282 #define HS_RX_CDR_CDR_NCO_EYE 0x00000005 /* PI controls: initial phases for NCO for eye monitor */ 283 #define HS_RX_CDR_PI_OS_CTRL 0x00000006 /* PI controls: offset adjustment */ 284 #define HS_RX_CDR_MAN_PI_CTRL 0x00000007 /* PI controls: manual phase adjustment */ 285 #define HS_RX_CDR_EM_CTRL 0x00000008 /* EM controls: general */ 286 #define HS_RX_CDR_EM_CNT_15_0 0x00000009 /* EM control: monitor counter */ 287 #define HS_RX_CDR_EM_CNT_31_16 0x0000000a /* EM control: monitor counter */ 288 #define HS_RX_CDR_EM_CNT_47_32 0x0000000b /* EM control: monitor counter */ 289 #define HS_RX_CDR_PFC_CTRL 0x0000000c /* PF controls: calibration */ 290 #define HS_RX_CDR_PFC_CNT 0x0000000d /* PF control: calibration counter */ 291 #define HS_RX_CDR_SWG_PERIOD 0x0000000e /* SWG control: period */ 292 #define HS_RX_CDR_SWG_Y_VAL 0x0000000f /* SWG control: y value */ 293 #define HS_RX_CDR_SWG_YSCALE 0x00000010 /* SWG controls: scale */ 294 #define HS_RX_CDR_SWG_DELTA_1 0x00000011 /* SWG control: delta1 value */ 295 #define HS_RX_CDR_SWG_DELTA_2 0x00000012 /* SWG control: delta2 value */ 296 #define HS_RX_CDR_SWG_DELTA_3 0x00000013 /* SWG control: delta3 value */ 297 #define HS_RX_CDR_CDR_STAT_TASKS 0x00000014 /* General status: operations done */ 298 #define HS_RX_CDR_CDR_STAT_INTEG 0x00000015 /* CDR status: integral register */ 299 #define HS_RX_CDR_CDR_STAT_NCO_RDP 0x00000016 /* PI status: phases for NCO at 0 and 90 degrees */ 300 #define HS_RX_CDR_CDR_STAT_NCO_EYE 0x00000017 /* PI status: phases for eye monitor NCO */ 301 #define HS_RX_CDR_EML_STAT_ACC_HI 0x00000018 /* EML status: mismatch count high bits */ 302 #define HS_RX_CDR_EML_STAT_ACC_LO 0x00000019 /* EML status: mismatch count low bits */ 303 #define HS_RX_CDR_PFC_STAT_ACC_HI 0x0000001a /* PF status: calibration acc high bits */ 304 #define HS_RX_CDR_PFC_STAT_ACC_LO 0x0000001b /* PF status: calibration acc low bits */ 305 306 307 /**************************************************************************** 308 * hs_rx_cdr_cm_regs 309 */ 310 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN 0x00000000 /* Write-enable signals for CDR loop parameters for all lanes */ 311 312 313 /**************************************************************************** 314 * hs_rx_cdr_sh_regs 315 */ 316 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS 0x00000000 /* Shadow general status: operations done */ 317 #define HS_RX_CDR_SH_SH_CDR_STAT_INTEG 0x00000001 /* Shadow CDR status: integral register */ 318 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP 0x00000002 /* Shadow PI status: phases for NCO at 0 and 90 degrees */ 319 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE 0x00000003 /* Shadow PI status: phases for eye monitor NCO */ 320 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI 0x00000004 /* Shadow EML status: mismatch count high bits */ 321 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_LO 0x00000005 /* Shadow EML status: mismatch count low bits */ 322 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_HI 0x00000006 /* Shadow PF status: calibration acc high bits */ 323 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_LO 0x00000007 /* Shadow PF status: calibration acc low bits */ 324 325 326 /**************************************************************************** 327 * hs_tx_cdr_tpc_regs 328 */ 329 #define HS_TX_CDR_TPC_TPC_CTRL 0x00000000 /* TPC controls: general */ 330 #define HS_TX_CDR_TPC_TPC_IIR 0x00000001 /* TPC controls: IIR MSB forcing */ 331 #define HS_TX_CDR_TPC_TPC_NCO 0x00000002 /* PI controls: initial phases for NCO for Tx PI */ 332 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL 0x00000003 /* TPC controls: manual PI adjustments */ 333 #define HS_TX_CDR_TPC_TPC_STAT_PI 0x00000004 /* TPC status: PI 0 NCO value */ 334 #define HS_TX_CDR_TPC_TPC_STAT_IIR 0x00000005 /* TPC status: IIR MSB */ 335 336 337 /**************************************************************************** 338 * ieee_pma_pmd_control_2_regs_regs 339 */ 340 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2 0x00000007 /* Mode selection via PMD type */ 341 342 343 /**************************************************************************** 344 * ieee_pma_pmd_regs_regs 345 */ 346 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1 0x00000000 /* IEEE_PMA_PMD_CONTROL_1 */ 347 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1 0x00000001 /* IEEE_PMA_PMD_STATUS_1 */ 348 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_MSB 0x00000002 /* IEEE_PMA_PMD_DEVICE_IDENTIFIER_MSB */ 349 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_LSB 0x00000003 /* IEEE_PMA_PMD_DEVICE_IDENTIFIER_LSB */ 350 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY 0x00000004 /* IEEE_PMA_PMD_SPEED_ABILITY */ 351 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB 0x00000005 /* IEEE_DEVICES_IN_PACKAGE_LSB */ 352 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB 0x00000006 /* IEEE_DEVICES_IN_PACKAGE_MSB */ 353 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2 0x00000008 /* IEEE_PMA_PMD_STATUS_2 */ 354 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE 0x00000009 /* IEEE_PMD_TRANSMIT_DISABLE */ 355 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT 0x0000000a /* IEEE_PMD_RECEIVE_SIGNAL_DETECT */ 356 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY 0x0000000b /* IEEE_PMA_PMD_EXTENDED_ABILITY */ 357 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY 0x0000000d /* IEEE_PMA_PMD_40G_100G_EXTENDED_ABILITY */ 358 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_MSB 0x0000000e /* IEEE_PMA_PMD_PACKAGE_IDENTIFIER_MSB */ 359 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_LSB 0x0000000f /* IEEE_PMA_PMD_PACKAGE_IDENTIFIER_LSB */ 360 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY 0x000005dc /* IEEE_PMA_PMD_TEST_PATTERN_ABILITY */ 361 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL 0x000005dd /* IEEE_PMA_PMD_PRBS_PATTERN_TEST_CONTROL */ 362 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL 0x000005e6 /* IEEE_PMA_PMD_SQUARE_WAVE_TEST_CONTROL */ 363 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0 0x00000640 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0 */ 364 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1 0x00000641 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1 */ 365 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2 0x00000642 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2 */ 366 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3 0x00000643 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3 */ 367 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4 0x00000644 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4 */ 368 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5 0x00000645 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5 */ 369 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6 0x00000646 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6 */ 370 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7 0x00000647 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7 */ 371 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8 0x00000648 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8 */ 372 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9 0x00000649 /* IEEE_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9 */ 373 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0 0x000006a4 /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0 */ 374 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1 0x000006a5 /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1 */ 375 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2 0x000006a6 /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2 */ 376 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3 0x000006a7 /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3 */ 377 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4 0x000006a8 /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4 */ 378 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5 0x000006a9 /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5 */ 379 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6 0x000006aa /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6 */ 380 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7 0x000006ab /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7 */ 381 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8 0x000006ac /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8 */ 382 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9 0x000006ad /* IEEE_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9 */ 383 384 385 /**************************************************************************** 386 * rg_rx_regs 387 */ 388 #define RG_RX_RX_GB_SYSTEM_RESET 0x0000f500 /* System side per lane software reset force value */ 389 #define RG_RX_RX_GB_SYSTEM_RESET_FRC 0x0000f501 /* System side per lane software reset force control */ 390 #define RG_RX_RX_GB_LINE_RESET 0x0000f502 /* Line side per lane software reset force value */ 391 #define RG_RX_RX_GB_LINE_RESET_FRC 0x0000f503 /* Line side per lane software reset force control */ 392 #define RG_RX_RX_GB_DB_TEST_CTRL 0x0000f504 /* Line side duobinary decoder and test checker control */ 393 #define RG_RX_RX_GB_TEST_CTRL_LN49 0x0000f505 /* Line side pattern check control for lane 4 to 9 */ 394 #define RG_RX_RX_GB_TEST_CTRL_LN03 0x0000f506 /* Line side PRBS/Pattern check main control for lane 0 to 3 */ 395 #define RG_RX_RX_GB_PRBS_INV_IN 0x0000f507 /* Line side PRBS check control in manual mode */ 396 #define RG_RX_RX_GB_BER_TIMER_CNT0 0x0000f508 /* PRBS/Pattern checker timer 15:0 */ 397 #define RG_RX_RX_GB_BER_TIMER_CNT1 0x0000f509 /* PRBS/Pattern checker timer 31:16 */ 398 #define RG_RX_RX_GB_TEST_MISC_CTRL 0x0000f50a /* PRBS/Pattern misc control */ 399 #define RG_RX_RX_GB_LP_PTR_SYNC0 0x0000f50b /* loopback FIFO pointer separation control for lane 0 to 3 */ 400 #define RG_RX_RX_GB_LP_PTR_SYNC1 0x0000f50c /* loopback FIFO pointer separation control for lane 4 to 7 */ 401 #define RG_RX_RX_GB_LN89_PTR_SYNC 0x0000f50d /* FIFO pointer separation control for lane 8 and 9 */ 402 #define RG_RX_RX_GB_PTR_SYNC1 0x0000f50e /* Pass Through FIFO pointer separation control for lane 4 to 7 */ 403 #define RG_RX_RX_GB_PTR_SYNC0 0x0000f50f /* Rate Converter pointer separation control for lane 0 to 3 */ 404 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0 0x0000f510 /* collision detection threshold for loopback FIFO lane 0 to 3 */ 405 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1 0x0000f511 /* collision detection threshold for loopback FIFO lane 4 to 7 */ 406 #define RG_RX_RX_GB_COL_THRESHOLD89 0x0000f512 /* collision detection threshold for FIFO lane 8 to 9 */ 407 #define RG_RX_RX_GB_COL_THRESHOLD1 0x0000f513 /* collision detection threshold for pass through FIFO lane 4 to 7 */ 408 #define RG_RX_RX_GB_COL_THRESHOLD0 0x0000f514 /* collision detection threshold for pass through FIFO lane 0 to 3 */ 409 #define RG_RX_RX_GB_PRBS_GEN_IERR 0x0000f515 /* insert bit error to output PRBS pattern */ 410 #define RG_RX_RX_GB_IO_BIT_CTRL 0x0000f516 /* System side output data polarity inversion and io bit swap enable */ 411 #define RG_RX_RX_GB_CAUI_CLK_SEL 0x0000f517 /* System side common clock selection */ 412 #define RG_RX_RX_GB_BER_MNTR_STATUS 0x0000f520 /* Bit Error Monitor status */ 413 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT 0x0000f521 /* line side PRBS/Pattern present */ 414 #define RG_RX_RX_GB_PRBS_LOCK 0x0000f522 /* line side PRBS/Pattern lock status */ 415 #define RG_RX_RX_GB_PRBS_LOCK_LL 0x0000f523 /* line side PRBS/Pattern lose of lock status */ 416 #define RG_RX_RX_GB_PRBS_STATUS_OUT 0x0000f524 /* line side PRBS/Pattern is inverted */ 417 #define RG_RX_RX_GB_LSB_ERR_CNT 0x0000f525 /* Lower 16 bits of BER counter */ 418 #define RG_RX_RX_GB_MSB_ERR_CNT 0x0000f526 /* higher 16 bits of BER counter */ 419 #define RG_RX_RX_GB_COLLIDE_LPBK 0x0000f527 /* line side loopback FIFO live status */ 420 #define RG_RX_RX_GB_COLLIDE_LPBK_LH 0x0000f528 /* line side loopback FIFO collision latch high status */ 421 #define RG_RX_RX_GB_COLLIDE 0x0000f529 /* data path phase FIFO or rate converter live status */ 422 #define RG_RX_RX_GB_COLLIDE_LH 0x0000f52a /* data path phase FIFO or rate converter collision latch high status */ 423 #define RG_RX_RX_GB_ERR_DATA_0 0x0000f52b /* captured error PRBS/Pattern data, bit [15:0] */ 424 #define RG_RX_RX_GB_ERR_DATA_1 0x0000f52c /* captured error PRBS/Pattern data, bit [31:16] */ 425 #define RG_RX_RX_GB_ERR_DATA_2 0x0000f52d /* captured error PRBS/Pattern data, bit [47:32] */ 426 #define RG_RX_RX_GB_ERR_DATA_3 0x0000f52e /* captured error PRBS/Pattern data, bit [63:48] */ 427 #define RG_RX_RX_GB_ERR_DATA_4 0x0000f52f /* captured error PRBS/Pattern data, bit [79:64] */ 428 #define RG_RX_RX_GB_ERR_DATA_5 0x0000f530 /* captured error PRBS/Pattern data, bit [95:80] */ 429 #define RG_RX_RX_GB_ERR_DATA_6 0x0000f531 /* captured error PRBS/Pattern data, bit [111:96] */ 430 #define RG_RX_RX_GB_ERR_DATA_7 0x0000f532 /* captured error PRBS/Pattern data, bit [127:112] */ 431 #define RG_RX_RX_GB_ERR_DATA_8 0x0000f533 /* captured error PRBS/Pattern data, bit [131:128] */ 432 433 434 /**************************************************************************** 435 * rg_tx_regs 436 */ 437 #define RG_TX_TX_GB_SYSTEM_RESET 0x0000f600 /* System side per lane software reset force value */ 438 #define RG_TX_TX_GB_SYSTEM_RESET_FRC 0x0000f601 /* System side per lane software reset force control */ 439 #define RG_TX_TX_GB_LINE_RESET 0x0000f602 /* Line side per lane software reset force value */ 440 #define RG_TX_TX_GB_LINE_RESET_FRC 0x0000f603 /* Line side per lane software reset force control */ 441 #define RG_TX_TX_GB_PRBS_DB_CTRL 0x0000f604 /* Line side test pattern generation and duobinary encoder control */ 442 #define RG_TX_TX_GB_TEST_IERR 0x0000f605 /* Line side PRBS/Pattern error insertion control */ 443 #define RG_TX_TX_GB_TEST_GEN_CTRL 0x0000f606 /* Line side PRBS/Pattern generation control for lane 0 to 3 */ 444 #define RG_TX_TX_GB_PATTERN0_0 0x0000f607 /* Fixed pattern to be sent in lane 0 line side 15:0 */ 445 #define RG_TX_TX_GB_PATTERN0_1 0x0000f608 /* Fixed pattern to be sent in lane 0 line side 31:16 */ 446 #define RG_TX_TX_GB_PATTERN0_2 0x0000f609 /* Fixed pattern to be sent in lane 0 line side 47:32 */ 447 #define RG_TX_TX_GB_PATTERN0_3 0x0000f60a /* Fixed pattern to be sent in lane 0 line side 63:48 */ 448 #define RG_TX_TX_GB_PATTERN0_4 0x0000f60b /* Fixed pattern to be sent in lane 0 line side 79:64 */ 449 #define RG_TX_TX_GB_PATTERN0_5 0x0000f60c /* Fixed pattern to be sent in lane 0 line side 95:80 */ 450 #define RG_TX_TX_GB_PATTERN0_6 0x0000f60d /* Fixed pattern to be sent in lane 0 line side 111:96 */ 451 #define RG_TX_TX_GB_PATTERN0_7 0x0000f60e /* Fixed pattern to be sent in lane 0 line side 127:112 */ 452 #define RG_TX_TX_GB_PATTERN1_0 0x0000f60f /* Fixed pattern to be sent in lane 1 line side 15:0 */ 453 #define RG_TX_TX_GB_PATTERN1_1 0x0000f610 /* Fixed pattern to be sent in lane 1 line side 31:16 */ 454 #define RG_TX_TX_GB_PATTERN1_2 0x0000f611 /* Fixed pattern to be sent in lane 1 line side 47:32 */ 455 #define RG_TX_TX_GB_PATTERN1_3 0x0000f612 /* Fixed pattern to be sent in lane 1 line side 63:48 */ 456 #define RG_TX_TX_GB_PATTERN1_4 0x0000f613 /* Fixed pattern to be sent in lane 1 line side 79:64 */ 457 #define RG_TX_TX_GB_PATTERN1_5 0x0000f614 /* Fixed pattern to be sent in lane 1 line side 95:80 */ 458 #define RG_TX_TX_GB_PATTERN1_6 0x0000f615 /* Fixed pattern to be sent in lane 1 line side 111:96 */ 459 #define RG_TX_TX_GB_PATTERN1_7 0x0000f616 /* Fixed pattern to be sent in lane 1 line side 127:112 */ 460 #define RG_TX_TX_GB_PATTERN2_0 0x0000f617 /* Fixed pattern to be sent in lane 2 line side 15:0 */ 461 #define RG_TX_TX_GB_PATTERN2_1 0x0000f618 /* Fixed pattern to be sent in lane 2 line side 31:16 */ 462 #define RG_TX_TX_GB_PATTERN2_2 0x0000f619 /* Fixed pattern to be sent in lane 2 line side 47:32 */ 463 #define RG_TX_TX_GB_PATTERN2_3 0x0000f61a /* Fixed pattern to be sent in lane 2 line side 63:48 */ 464 #define RG_TX_TX_GB_PATTERN2_4 0x0000f61b /* Fixed pattern to be sent in lane 2 line side 79:64 */ 465 #define RG_TX_TX_GB_PATTERN2_5 0x0000f61c /* Fixed pattern to be sent in lane 2 line side 95:80 */ 466 #define RG_TX_TX_GB_PATTERN2_6 0x0000f61d /* Fixed pattern to be sent in lane 2 line side 111:96 */ 467 #define RG_TX_TX_GB_PATTERN2_7 0x0000f61e /* Fixed pattern to be sent in lane 2 line side 127:112 */ 468 #define RG_TX_TX_GB_PATTERN3_0 0x0000f61f /* Fixed pattern to be sent in lane 3 line side 15:0 */ 469 #define RG_TX_TX_GB_PATTERN3_1 0x0000f620 /* Fixed pattern to be sent in lane 3 line side 31:16 */ 470 #define RG_TX_TX_GB_PATTERN3_2 0x0000f621 /* Fixed pattern to be sent in lane 3 line side 47:32 */ 471 #define RG_TX_TX_GB_PATTERN3_3 0x0000f622 /* Fixed pattern to be sent in lane 3 line side 63:48 */ 472 #define RG_TX_TX_GB_PATTERN3_4 0x0000f623 /* Fixed pattern to be sent in lane 3 line side 79:64 */ 473 #define RG_TX_TX_GB_PATTERN3_5 0x0000f624 /* Fixed pattern to be sent in lane 3 line side 95:80 */ 474 #define RG_TX_TX_GB_PATTERN3_6 0x0000f625 /* Fixed pattern to be sent in lane 3 line side 111:96 */ 475 #define RG_TX_TX_GB_PATTERN3_7 0x0000f626 /* Fixed pattern to be sent in lane 3 line side 127:112 */ 476 #define RG_TX_TX_GB_PATTERN_8 0x0000f627 /* Fixed pattern to be sent for all lanes bit 131:128 */ 477 #define RG_TX_TX_GB_LPBK_PTR_SYNC0 0x0000f628 /* loopback FIFO pointer separation control for lane 0 to 3 */ 478 #define RG_TX_TX_GB_LPBK_PTR_SYNC1 0x0000f629 /* loopback FIFO pointer separation control for lane 4 to 7 */ 479 #define RG_TX_TX_GB_LN89_PTR_SYNC 0x0000f62a /* FIFO pointer separation control for lane 8 and 9 */ 480 #define RG_TX_TX_GB_PTR_SYNC1 0x0000f62b /* Pass Through FIFO pointer separation control for lane 4 to 7 */ 481 #define RG_TX_TX_GB_PTR_SYNC0 0x0000f62c /* Pass Through FIFO or rate converter pointer separation control for lane 0 to 3 */ 482 #define RG_TX_TX_GB_50TO64_CTRL 0x0000f62d /* Pointer separation and collision detection threshold control for 4 x 50to64 rate converter */ 483 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0 0x0000f62e /* collision detection threshold for loopback FIFO lane 0 to 3 */ 484 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1 0x0000f62f /* collision detection threshold for loopback FIFO lane 4 to 7 */ 485 #define RG_TX_TX_GB_COL_THRESHOLD89 0x0000f630 /* collision detection threshold for FIFO lane 8 to 9 */ 486 #define RG_TX_TX_GB_COL_THRESHOLD1 0x0000f631 /* collision detection threshold for pass through FIFO lane 4 to 7 */ 487 #define RG_TX_TX_GB_COL_THRESHOLD0 0x0000f632 /* collision detection threshold for pass through FIFO lane 0 to 3 */ 488 #define RG_TX_TX_GB_IO_BIT_CONTROL 0x0000f633 /* Line side output data polarity inversion and io bit swap enable */ 489 #define RG_TX_TX_GB_LOGIC_LANE_TEST 0x0000f634 /* Per logic lane test control in CAUI mode */ 490 #define RG_TX_TX_GB_COLLIDE_LPBK 0x0000f640 /* line side loopback FIFO live status */ 491 #define RG_TX_TX_GB_COLLIDE_LPBK_LH 0x0000f641 /* line side loopback FIFO collision latch high status */ 492 #define RG_TX_TX_GB_COLLIDE 0x0000f642 /* data path phase FIFO or rate converter live status */ 493 #define RG_TX_TX_GB_COLLIDE_LH 0x0000f643 /* data path phase FIFO or rate converter collision latch high status */ 494 495 496 /**************************************************************************** 497 * slice_regs_regs 498 */ 499 #define SLICE_REGS_SLICE 0x00008000 /* Slice Register */ 500 501 502 /**************************************************************************** 503 * vsr40_rx_ana25g_regs 504 */ 505 #define VSR40_RX_ANA25G_CONTROL11 0x00000000 /* VSR40 RX Analog Interface Control 11 Register */ 506 #define VSR40_RX_ANA25G_CONTROL10 0x00000001 /* VSR40 RX Analog Interface Control 10 Register */ 507 #define VSR40_RX_ANA25G_CONTROL9 0x00000002 /* VSR40 RX Analog Interface Control 9 Register */ 508 #define VSR40_RX_ANA25G_CONTROL8 0x00000003 /* VSR40 RX Analog Interface Control 8 Register */ 509 #define VSR40_RX_ANA25G_CONTROL7 0x00000004 /* VSR40 RX Analog Interface Control 7 Register */ 510 #define VSR40_RX_ANA25G_CONTROL6 0x00000005 /* VSR40 RX Analog Interface Control 6 Register */ 511 #define VSR40_RX_ANA25G_CONTROL5 0x00000006 /* VSR40 RX Analog Interface Control 5 Register */ 512 #define VSR40_RX_ANA25G_CONTROL4 0x00000007 /* VSR40 RX Analog Interface Control 4 Register */ 513 #define VSR40_RX_ANA25G_CONTROL3 0x00000008 /* VSR40 RX Analog Interface Control 3 Register */ 514 #define VSR40_RX_ANA25G_CONTROL2 0x00000009 /* VSR40 RX Analog Interface Control 2 Register */ 515 #define VSR40_RX_ANA25G_CONTROL1 0x0000000a /* VSR40 RX Analog Interface Control 1 Register */ 516 #define VSR40_RX_ANA25G_CONTROL0 0x0000000b /* VSR40 RX Analog Interface Control 0 Register */ 517 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0 0x0000000c /* VSR40 RX Analog Signal Interface Control 0 Register */ 518 #define VSR40_RX_ANA25G_ANA_IF_STATUS 0x0000000d /* VSR40 RX Analog Signal Interface Status Register */ 519 520 521 /**************************************************************************** 522 * vsr40_rx_dig_regs_regs 523 */ 524 #define VSR40_RX_DIG_REGS_CDR_CONTROL 0x00009800 /* Reset Control */ 525 #define VSR40_RX_DIG_REGS_RESET_CONTROL 0x00009801 /* Reset Control */ 526 #define VSR40_RX_DIG_REGS_CLK_CONTROL 0x00009802 /* Clock Control */ 527 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL 0x00009803 /* VCO cal Control */ 528 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL1 0x00009804 /* Lockdet Control 1 */ 529 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL2 0x00009805 /* Lockdet Control 2 */ 530 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3 0x00009806 /* Lockdet Control 3 */ 531 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4 0x00009807 /* Lockdet Control 4 */ 532 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL 0x00009808 /* Reserve Control */ 533 #define VSR40_RX_DIG_REGS_STATUS 0x0000980a /* Status Register */ 534 #define VSR40_RX_DIG_REGS_RX_MISR 0x0000980b /* Level 2 VSR40 digital RX micro interrupt status register (MISR-L2) */ 535 #define VSR40_RX_DIG_REGS_RX_MIMR 0x0000980c /* Level 2 VSR40 digital RX micro interrupt mask register (MIMR-L2) */ 536 #define VSR40_RX_DIG_REGS_RX_P_MISR 0x0000980d /* Level 2 VSR40 digital pending RX micro interrupt status register (PMISR-L2) */ 537 #define VSR40_RX_DIG_REGS_CDR_MISR 0x0000980e /* Level 2 VSR40 RX CDR micro interrupt status register (MISR-L2) */ 538 #define VSR40_RX_DIG_REGS_CDR_MIMR 0x0000980f /* Level 2 VSR40 RX CDR micro interrupt mask register (MIMR-L2) */ 539 #define VSR40_RX_DIG_REGS_CDR_P_MISR 0x00009810 /* Level 2 VSR40 RX pending CDR micro interrupt status register (PMISR-L2) */ 540 #define VSR40_RX_DIG_REGS_DP_CTRL 0x00009811 /* Datapath control. */ 541 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN 0x00009812 /* CDR common write enable register. */ 542 543 544 /**************************************************************************** 545 * vsr40_rx_pll_regs 546 */ 547 #define VSR40_RX_PLL_CONTROL7 0x00009880 /* VSR40 RX PLL Interface Control 7 Register */ 548 #define VSR40_RX_PLL_CONTROL6 0x00009881 /* VSR40 RX PLL Interface Control 6 Register */ 549 #define VSR40_RX_PLL_CONTROL5 0x00009882 /* VSR40 RX PLL Interface Control 5 Register */ 550 #define VSR40_RX_PLL_CONTROL4 0x00009883 /* VSR40 RX PLL Interface Control 4 Register */ 551 #define VSR40_RX_PLL_CONTROL3 0x00009884 /* VSR40 RX PLL Interface Control 3 Register */ 552 #define VSR40_RX_PLL_CONTROL2 0x00009885 /* VSR40 RX PLL Interface Control 2 Register */ 553 #define VSR40_RX_PLL_CONTROL1 0x00009886 /* VSR40 RX PLL Interface Control 1 Register */ 554 #define VSR40_RX_PLL_CONTROL0 0x00009887 /* VSR40 RX PLL Interface Control 0 Register */ 555 556 557 /**************************************************************************** 558 * vsr40_tx_ana25g_regs 559 */ 560 #define VSR40_TX_ANA25G_CONTROL8 0x00000001 /* VSR40 TX Analog Interface Control 8 Register */ 561 #define VSR40_TX_ANA25G_CONTROL7 0x00000002 /* VSR40 TX Analog Interface Control 7 Register */ 562 #define VSR40_TX_ANA25G_CONTROL6 0x00000003 /* VSR40 TX Analog Interface Control 6 Register */ 563 #define VSR40_TX_ANA25G_CONTROL5 0x00000004 /* VSR40 TX Analog Interface Control 5 Register */ 564 #define VSR40_TX_ANA25G_CONTROL4 0x00000005 /* VSR40 TX Analog Interface Control 4 Register */ 565 #define VSR40_TX_ANA25G_CONTROL3 0x00000006 /* VSR40 TX Analog Interface Control 3 Register */ 566 #define VSR40_TX_ANA25G_CONTROL2 0x00000007 /* VSR40 TX Analog Interface Control 2 Register */ 567 #define VSR40_TX_ANA25G_CONTROL1 0x00000008 /* VSR40 TX Analog Interface Control 1 Register */ 568 #define VSR40_TX_ANA25G_CONTROL0 0x00000009 /* VSR40 TX Analog Interface Control 0 Register */ 569 570 571 /**************************************************************************** 572 * vsr40_tx_dig_regs_regs 573 */ 574 #define VSR40_TX_DIG_REGS_RESET_CONTROL 0x00009900 /* Reset Control */ 575 #define VSR40_TX_DIG_REGS_CLK_CONTROL 0x00009901 /* Clock Control */ 576 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL 0x00009902 /* VCO cal Control */ 577 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL1 0x00009903 /* Lockdet Control 1 */ 578 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL2 0x00009904 /* Lockdet Control 2 */ 579 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3 0x00009905 /* Lockdet Control 3 */ 580 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4 0x00009906 /* Lockdet Control 4 */ 581 #define VSR40_TX_DIG_REGS_RESERVE_CONTROL 0x00009907 /* Reserve Control */ 582 #define VSR40_TX_DIG_REGS_STATUS 0x0000990a /* Status Register */ 583 #define VSR40_TX_DIG_REGS_TX_MISR 0x0000990b /* Level 2 VSR40 digital TX micro interrupt status register (MISR-L2) */ 584 #define VSR40_TX_DIG_REGS_TX_MIMR 0x0000990c /* Level 2 VSR40 digital TX micro interrupt mask register (MIMR-L2) */ 585 #define VSR40_TX_DIG_REGS_TX_P_MISR 0x0000990d /* Level 2 VSR40 digital pending TX micro interrupt status register (PMISR-L2) */ 586 #define VSR40_TX_DIG_REGS_TCA_CTRL 0x0000990e /* VSR40 (4x25G) TX Clock Alignment Control register */ 587 #define VSR40_TX_DIG_REGS_TCA_STATUS 0x0000990f /* VSR40 (4x25G) TX Clock Alignment Status register */ 588 589 590 /**************************************************************************** 591 * vsr40_tx_pll_regs 592 */ 593 #define VSR40_TX_PLL_CONTROL7 0x00009980 /* VSR40 TX PLL Interface Control 7 Register */ 594 #define VSR40_TX_PLL_CONTROL6 0x00009981 /* VSR40 TX PLL Interface Control 6 Register */ 595 #define VSR40_TX_PLL_CONTROL5 0x00009982 /* VSR40 TX PLL Interface Control 5 Register */ 596 #define VSR40_TX_PLL_CONTROL4 0x00009983 /* VSR40 TX PLL Interface Control 4 Register */ 597 #define VSR40_TX_PLL_CONTROL3 0x00009984 /* VSR40 TX PLL Interface Control 3 Register */ 598 #define VSR40_TX_PLL_CONTROL2 0x00009985 /* VSR40 TX PLL Interface Control 2 Register */ 599 #define VSR40_TX_PLL_CONTROL1 0x00009986 /* VSR40 TX PLL Interface Control 1 Register */ 600 #define VSR40_TX_PLL_CONTROL0 0x00009987 /* VSR40 TX PLL Interface Control 0 Register */ 601 602 603 /**************************************************************************** 604 * common_por_regs_regs 605 */ 606 /**************************************************************************** 607 * common_por_regs :: boot_por 608 */ 609 /* common_por_regs :: boot_por :: spi_port_used [15:15] */ 610 #define COMMON_POR_REGS_BOOT_POR_SPI_PORT_USED_MASK 0x8000 611 #define COMMON_POR_REGS_BOOT_POR_SPI_PORT_USED_ALIGN 0 612 #define COMMON_POR_REGS_BOOT_POR_SPI_PORT_USED_BITS 1 613 #define COMMON_POR_REGS_BOOT_POR_SPI_PORT_USED_SHIFT 15 614 615 /* common_por_regs :: boot_por :: ser_boot [14:14] */ 616 #define COMMON_POR_REGS_BOOT_POR_SER_BOOT_MASK 0x4000 617 #define COMMON_POR_REGS_BOOT_POR_SER_BOOT_ALIGN 0 618 #define COMMON_POR_REGS_BOOT_POR_SER_BOOT_BITS 1 619 #define COMMON_POR_REGS_BOOT_POR_SER_BOOT_SHIFT 14 620 621 /* common_por_regs :: boot_por :: spi_dwld_done [13:13] */ 622 #define COMMON_POR_REGS_BOOT_POR_SPI_DWLD_DONE_MASK 0x2000 623 #define COMMON_POR_REGS_BOOT_POR_SPI_DWLD_DONE_ALIGN 0 624 #define COMMON_POR_REGS_BOOT_POR_SPI_DWLD_DONE_BITS 1 625 #define COMMON_POR_REGS_BOOT_POR_SPI_DWLD_DONE_SHIFT 13 626 627 /* common_por_regs :: boot_por :: reserved0 [12:08] */ 628 #define COMMON_POR_REGS_BOOT_POR_RESERVED0_MASK 0x1f00 629 #define COMMON_POR_REGS_BOOT_POR_RESERVED0_ALIGN 0 630 #define COMMON_POR_REGS_BOOT_POR_RESERVED0_BITS 5 631 #define COMMON_POR_REGS_BOOT_POR_RESERVED0_SHIFT 8 632 633 /* common_por_regs :: boot_por :: gpreg [07:00] */ 634 #define COMMON_POR_REGS_BOOT_POR_GPREG_MASK 0x00ff 635 #define COMMON_POR_REGS_BOOT_POR_GPREG_ALIGN 0 636 #define COMMON_POR_REGS_BOOT_POR_GPREG_BITS 8 637 #define COMMON_POR_REGS_BOOT_POR_GPREG_SHIFT 0 638 639 640 /**************************************************************************** 641 * ctl_regs_regs 642 */ 643 /**************************************************************************** 644 * ctl_regs :: tx_eeprom_control 645 */ 646 /* ctl_regs :: tx_eeprom_control :: reserved0 [15:06] */ 647 #define CTL_REGS_TX_EEPROM_CONTROL_RESERVED0_MASK 0xffc0 648 #define CTL_REGS_TX_EEPROM_CONTROL_RESERVED0_ALIGN 0 649 #define CTL_REGS_TX_EEPROM_CONTROL_RESERVED0_BITS 10 650 #define CTL_REGS_TX_EEPROM_CONTROL_RESERVED0_SHIFT 6 651 652 /* ctl_regs :: tx_eeprom_control :: eeprom_offset [05:03] */ 653 #define CTL_REGS_TX_EEPROM_CONTROL_EEPROM_OFFSET_MASK 0x0038 654 #define CTL_REGS_TX_EEPROM_CONTROL_EEPROM_OFFSET_ALIGN 0 655 #define CTL_REGS_TX_EEPROM_CONTROL_EEPROM_OFFSET_BITS 3 656 #define CTL_REGS_TX_EEPROM_CONTROL_EEPROM_OFFSET_SHIFT 3 657 658 /* ctl_regs :: tx_eeprom_control :: eeprom_count [02:00] */ 659 #define CTL_REGS_TX_EEPROM_CONTROL_EEPROM_COUNT_MASK 0x0007 660 #define CTL_REGS_TX_EEPROM_CONTROL_EEPROM_COUNT_ALIGN 0 661 #define CTL_REGS_TX_EEPROM_CONTROL_EEPROM_COUNT_BITS 3 662 #define CTL_REGS_TX_EEPROM_CONTROL_EEPROM_COUNT_SHIFT 0 663 664 665 /**************************************************************************** 666 * ctl_regs :: common_chip_id 667 */ 668 /* ctl_regs :: common_chip_id :: chip_id_15_0 [15:00] */ 669 #define CTL_REGS_COMMON_CHIP_ID_CHIP_ID_15_0_MASK 0xffff 670 #define CTL_REGS_COMMON_CHIP_ID_CHIP_ID_15_0_ALIGN 0 671 #define CTL_REGS_COMMON_CHIP_ID_CHIP_ID_15_0_BITS 16 672 #define CTL_REGS_COMMON_CHIP_ID_CHIP_ID_15_0_SHIFT 0 673 674 675 /**************************************************************************** 676 * ctl_regs :: common_rev_id 677 */ 678 /* ctl_regs :: common_rev_id :: chip_id_19_16 [15:12] */ 679 #define CTL_REGS_COMMON_REV_ID_CHIP_ID_19_16_MASK 0xf000 680 #define CTL_REGS_COMMON_REV_ID_CHIP_ID_19_16_ALIGN 0 681 #define CTL_REGS_COMMON_REV_ID_CHIP_ID_19_16_BITS 4 682 #define CTL_REGS_COMMON_REV_ID_CHIP_ID_19_16_SHIFT 12 683 684 /* ctl_regs :: common_rev_id :: reserved_for_eco0 [11:08] */ 685 #define CTL_REGS_COMMON_REV_ID_RESERVED_FOR_ECO0_MASK 0x0f00 686 #define CTL_REGS_COMMON_REV_ID_RESERVED_FOR_ECO0_ALIGN 0 687 #define CTL_REGS_COMMON_REV_ID_RESERVED_FOR_ECO0_BITS 4 688 #define CTL_REGS_COMMON_REV_ID_RESERVED_FOR_ECO0_SHIFT 8 689 690 /* ctl_regs :: common_rev_id :: chip_rev [07:00] */ 691 #define CTL_REGS_COMMON_REV_ID_CHIP_REV_MASK 0x00ff 692 #define CTL_REGS_COMMON_REV_ID_CHIP_REV_ALIGN 0 693 #define CTL_REGS_COMMON_REV_ID_CHIP_REV_BITS 8 694 #define CTL_REGS_COMMON_REV_ID_CHIP_REV_SHIFT 0 695 696 697 /**************************************************************************** 698 * ctl_regs :: common_ctrl1 699 */ 700 /* ctl_regs :: common_ctrl1 :: reserved_for_eco0 [15:10] */ 701 #define CTL_REGS_COMMON_CTRL1_RESERVED_FOR_ECO0_MASK 0xfc00 702 #define CTL_REGS_COMMON_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 703 #define CTL_REGS_COMMON_CTRL1_RESERVED_FOR_ECO0_BITS 6 704 #define CTL_REGS_COMMON_CTRL1_RESERVED_FOR_ECO0_SHIFT 10 705 706 /* ctl_regs :: common_ctrl1 :: en_rst_on_pd [09:09] */ 707 #define CTL_REGS_COMMON_CTRL1_EN_RST_ON_PD_MASK 0x0200 708 #define CTL_REGS_COMMON_CTRL1_EN_RST_ON_PD_ALIGN 0 709 #define CTL_REGS_COMMON_CTRL1_EN_RST_ON_PD_BITS 1 710 #define CTL_REGS_COMMON_CTRL1_EN_RST_ON_PD_SHIFT 9 711 712 /* ctl_regs :: common_ctrl1 :: rx_dp_rstb [08:08] */ 713 #define CTL_REGS_COMMON_CTRL1_RX_DP_RSTB_MASK 0x0100 714 #define CTL_REGS_COMMON_CTRL1_RX_DP_RSTB_ALIGN 0 715 #define CTL_REGS_COMMON_CTRL1_RX_DP_RSTB_BITS 1 716 #define CTL_REGS_COMMON_CTRL1_RX_DP_RSTB_SHIFT 8 717 718 /* ctl_regs :: common_ctrl1 :: tx_dp_rstb [07:07] */ 719 #define CTL_REGS_COMMON_CTRL1_TX_DP_RSTB_MASK 0x0080 720 #define CTL_REGS_COMMON_CTRL1_TX_DP_RSTB_ALIGN 0 721 #define CTL_REGS_COMMON_CTRL1_TX_DP_RSTB_BITS 1 722 #define CTL_REGS_COMMON_CTRL1_TX_DP_RSTB_SHIFT 7 723 724 /* ctl_regs :: common_ctrl1 :: rescal_rstb [06:06] */ 725 #define CTL_REGS_COMMON_CTRL1_RESCAL_RSTB_MASK 0x0040 726 #define CTL_REGS_COMMON_CTRL1_RESCAL_RSTB_ALIGN 0 727 #define CTL_REGS_COMMON_CTRL1_RESCAL_RSTB_BITS 1 728 #define CTL_REGS_COMMON_CTRL1_RESCAL_RSTB_SHIFT 6 729 730 /* ctl_regs :: common_ctrl1 :: spi_rstb [05:05] */ 731 #define CTL_REGS_COMMON_CTRL1_SPI_RSTB_MASK 0x0020 732 #define CTL_REGS_COMMON_CTRL1_SPI_RSTB_ALIGN 0 733 #define CTL_REGS_COMMON_CTRL1_SPI_RSTB_BITS 1 734 #define CTL_REGS_COMMON_CTRL1_SPI_RSTB_SHIFT 5 735 736 /* ctl_regs :: common_ctrl1 :: spi2x_rstb [04:04] */ 737 #define CTL_REGS_COMMON_CTRL1_SPI2X_RSTB_MASK 0x0010 738 #define CTL_REGS_COMMON_CTRL1_SPI2X_RSTB_ALIGN 0 739 #define CTL_REGS_COMMON_CTRL1_SPI2X_RSTB_BITS 1 740 #define CTL_REGS_COMMON_CTRL1_SPI2X_RSTB_SHIFT 4 741 742 /* ctl_regs :: common_ctrl1 :: uc_rstb [03:03] */ 743 #define CTL_REGS_COMMON_CTRL1_UC_RSTB_MASK 0x0008 744 #define CTL_REGS_COMMON_CTRL1_UC_RSTB_ALIGN 0 745 #define CTL_REGS_COMMON_CTRL1_UC_RSTB_BITS 1 746 #define CTL_REGS_COMMON_CTRL1_UC_RSTB_SHIFT 3 747 748 /* ctl_regs :: common_ctrl1 :: arb_rstb [02:02] */ 749 #define CTL_REGS_COMMON_CTRL1_ARB_RSTB_MASK 0x0004 750 #define CTL_REGS_COMMON_CTRL1_ARB_RSTB_ALIGN 0 751 #define CTL_REGS_COMMON_CTRL1_ARB_RSTB_BITS 1 752 #define CTL_REGS_COMMON_CTRL1_ARB_RSTB_SHIFT 2 753 754 /* ctl_regs :: common_ctrl1 :: reg_rstb [01:01] */ 755 #define CTL_REGS_COMMON_CTRL1_REG_RSTB_MASK 0x0002 756 #define CTL_REGS_COMMON_CTRL1_REG_RSTB_ALIGN 0 757 #define CTL_REGS_COMMON_CTRL1_REG_RSTB_BITS 1 758 #define CTL_REGS_COMMON_CTRL1_REG_RSTB_SHIFT 1 759 760 /* ctl_regs :: common_ctrl1 :: resetb [00:00] */ 761 #define CTL_REGS_COMMON_CTRL1_RESETB_MASK 0x0001 762 #define CTL_REGS_COMMON_CTRL1_RESETB_ALIGN 0 763 #define CTL_REGS_COMMON_CTRL1_RESETB_BITS 1 764 #define CTL_REGS_COMMON_CTRL1_RESETB_SHIFT 0 765 766 767 /**************************************************************************** 768 * ctl_regs :: user_modesel_reg 769 */ 770 /* ctl_regs :: user_modesel_reg :: reserved_for_eco0 [15:04] */ 771 #define CTL_REGS_USER_MODESEL_REG_RESERVED_FOR_ECO0_MASK 0xfff0 772 #define CTL_REGS_USER_MODESEL_REG_RESERVED_FOR_ECO0_ALIGN 0 773 #define CTL_REGS_USER_MODESEL_REG_RESERVED_FOR_ECO0_BITS 12 774 #define CTL_REGS_USER_MODESEL_REG_RESERVED_FOR_ECO0_SHIFT 4 775 776 /* ctl_regs :: user_modesel_reg :: user_modesel_frc [03:03] */ 777 #define CTL_REGS_USER_MODESEL_REG_USER_MODESEL_FRC_MASK 0x0008 778 #define CTL_REGS_USER_MODESEL_REG_USER_MODESEL_FRC_ALIGN 0 779 #define CTL_REGS_USER_MODESEL_REG_USER_MODESEL_FRC_BITS 1 780 #define CTL_REGS_USER_MODESEL_REG_USER_MODESEL_FRC_SHIFT 3 781 782 /* ctl_regs :: user_modesel_reg :: user_modesel [02:00] */ 783 #define CTL_REGS_USER_MODESEL_REG_USER_MODESEL_MASK 0x0007 784 #define CTL_REGS_USER_MODESEL_REG_USER_MODESEL_ALIGN 0 785 #define CTL_REGS_USER_MODESEL_REG_USER_MODESEL_BITS 3 786 #define CTL_REGS_USER_MODESEL_REG_USER_MODESEL_SHIFT 0 787 788 789 /**************************************************************************** 790 * ctl_regs :: refclk_sel_reg 791 */ 792 /* ctl_regs :: refclk_sel_reg :: reserved_for_eco0 [15:04] */ 793 #define CTL_REGS_REFCLK_SEL_REG_RESERVED_FOR_ECO0_MASK 0xfff0 794 #define CTL_REGS_REFCLK_SEL_REG_RESERVED_FOR_ECO0_ALIGN 0 795 #define CTL_REGS_REFCLK_SEL_REG_RESERVED_FOR_ECO0_BITS 12 796 #define CTL_REGS_REFCLK_SEL_REG_RESERVED_FOR_ECO0_SHIFT 4 797 798 /* ctl_regs :: refclk_sel_reg :: refclk_code [03:00] */ 799 #define CTL_REGS_REFCLK_SEL_REG_REFCLK_CODE_MASK 0x000f 800 #define CTL_REGS_REFCLK_SEL_REG_REFCLK_CODE_ALIGN 0 801 #define CTL_REGS_REFCLK_SEL_REG_REFCLK_CODE_BITS 4 802 #define CTL_REGS_REFCLK_SEL_REG_REFCLK_CODE_SHIFT 0 803 804 805 /**************************************************************************** 806 * ctl_regs :: common_ctrl2 807 */ 808 /* ctl_regs :: common_ctrl2 :: spi_rom_mode [15:15] */ 809 #define CTL_REGS_COMMON_CTRL2_SPI_ROM_MODE_MASK 0x8000 810 #define CTL_REGS_COMMON_CTRL2_SPI_ROM_MODE_ALIGN 0 811 #define CTL_REGS_COMMON_CTRL2_SPI_ROM_MODE_BITS 1 812 #define CTL_REGS_COMMON_CTRL2_SPI_ROM_MODE_SHIFT 15 813 814 /* ctl_regs :: common_ctrl2 :: tx_dis_pin_frc [14:14] */ 815 #define CTL_REGS_COMMON_CTRL2_TX_DIS_PIN_FRC_MASK 0x4000 816 #define CTL_REGS_COMMON_CTRL2_TX_DIS_PIN_FRC_ALIGN 0 817 #define CTL_REGS_COMMON_CTRL2_TX_DIS_PIN_FRC_BITS 1 818 #define CTL_REGS_COMMON_CTRL2_TX_DIS_PIN_FRC_SHIFT 14 819 820 /* ctl_regs :: common_ctrl2 :: tx_dis_pin_frcval [13:13] */ 821 #define CTL_REGS_COMMON_CTRL2_TX_DIS_PIN_FRCVAL_MASK 0x2000 822 #define CTL_REGS_COMMON_CTRL2_TX_DIS_PIN_FRCVAL_ALIGN 0 823 #define CTL_REGS_COMMON_CTRL2_TX_DIS_PIN_FRCVAL_BITS 1 824 #define CTL_REGS_COMMON_CTRL2_TX_DIS_PIN_FRCVAL_SHIFT 13 825 826 /* ctl_regs :: common_ctrl2 :: mod_lowpr_pin_frc [12:12] */ 827 #define CTL_REGS_COMMON_CTRL2_MOD_LOWPR_PIN_FRC_MASK 0x1000 828 #define CTL_REGS_COMMON_CTRL2_MOD_LOWPR_PIN_FRC_ALIGN 0 829 #define CTL_REGS_COMMON_CTRL2_MOD_LOWPR_PIN_FRC_BITS 1 830 #define CTL_REGS_COMMON_CTRL2_MOD_LOWPR_PIN_FRC_SHIFT 12 831 832 /* ctl_regs :: common_ctrl2 :: mod_lowpr_pin_frcval [11:11] */ 833 #define CTL_REGS_COMMON_CTRL2_MOD_LOWPR_PIN_FRCVAL_MASK 0x0800 834 #define CTL_REGS_COMMON_CTRL2_MOD_LOWPR_PIN_FRCVAL_ALIGN 0 835 #define CTL_REGS_COMMON_CTRL2_MOD_LOWPR_PIN_FRCVAL_BITS 1 836 #define CTL_REGS_COMMON_CTRL2_MOD_LOWPR_PIN_FRCVAL_SHIFT 11 837 838 /* ctl_regs :: common_ctrl2 :: reserved_for_eco0 [10:00] */ 839 #define CTL_REGS_COMMON_CTRL2_RESERVED_FOR_ECO0_MASK 0x07ff 840 #define CTL_REGS_COMMON_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 841 #define CTL_REGS_COMMON_CTRL2_RESERVED_FOR_ECO0_BITS 11 842 #define CTL_REGS_COMMON_CTRL2_RESERVED_FOR_ECO0_SHIFT 0 843 844 845 /**************************************************************************** 846 * ctl_regs :: common_status1 847 */ 848 /* ctl_regs :: common_status1 :: reserved_for_eco0 [15:06] */ 849 #define CTL_REGS_COMMON_STATUS1_RESERVED_FOR_ECO0_MASK 0xffc0 850 #define CTL_REGS_COMMON_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 851 #define CTL_REGS_COMMON_STATUS1_RESERVED_FOR_ECO0_BITS 10 852 #define CTL_REGS_COMMON_STATUS1_RESERVED_FOR_ECO0_SHIFT 6 853 854 /* ctl_regs :: common_status1 :: refsel_pad [05:05] */ 855 #define CTL_REGS_COMMON_STATUS1_REFSEL_PAD_MASK 0x0020 856 #define CTL_REGS_COMMON_STATUS1_REFSEL_PAD_ALIGN 0 857 #define CTL_REGS_COMMON_STATUS1_REFSEL_PAD_BITS 1 858 #define CTL_REGS_COMMON_STATUS1_REFSEL_PAD_SHIFT 5 859 860 /* ctl_regs :: common_status1 :: reserved1 [04:04] */ 861 #define CTL_REGS_COMMON_STATUS1_RESERVED1_MASK 0x0010 862 #define CTL_REGS_COMMON_STATUS1_RESERVED1_ALIGN 0 863 #define CTL_REGS_COMMON_STATUS1_RESERVED1_BITS 1 864 #define CTL_REGS_COMMON_STATUS1_RESERVED1_SHIFT 4 865 866 /* ctl_regs :: common_status1 :: reserved2 [03:03] */ 867 #define CTL_REGS_COMMON_STATUS1_RESERVED2_MASK 0x0008 868 #define CTL_REGS_COMMON_STATUS1_RESERVED2_ALIGN 0 869 #define CTL_REGS_COMMON_STATUS1_RESERVED2_BITS 1 870 #define CTL_REGS_COMMON_STATUS1_RESERVED2_SHIFT 3 871 872 /* ctl_regs :: common_status1 :: reserved3 [02:00] */ 873 #define CTL_REGS_COMMON_STATUS1_RESERVED3_MASK 0x0007 874 #define CTL_REGS_COMMON_STATUS1_RESERVED3_ALIGN 0 875 #define CTL_REGS_COMMON_STATUS1_RESERVED3_BITS 3 876 #define CTL_REGS_COMMON_STATUS1_RESERVED3_SHIFT 0 877 878 879 /**************************************************************************** 880 * ctl_regs :: ieee_modesel_default 881 */ 882 /* ctl_regs :: ieee_modesel_default :: reserved0 [15:08] */ 883 #define CTL_REGS_IEEE_MODESEL_DEFAULT_RESERVED0_MASK 0xff00 884 #define CTL_REGS_IEEE_MODESEL_DEFAULT_RESERVED0_ALIGN 0 885 #define CTL_REGS_IEEE_MODESEL_DEFAULT_RESERVED0_BITS 8 886 #define CTL_REGS_IEEE_MODESEL_DEFAULT_RESERVED0_SHIFT 8 887 888 /* ctl_regs :: ieee_modesel_default :: ieee_modesel_cfg_hold [07:07] */ 889 #define CTL_REGS_IEEE_MODESEL_DEFAULT_IEEE_MODESEL_CFG_HOLD_MASK 0x0080 890 #define CTL_REGS_IEEE_MODESEL_DEFAULT_IEEE_MODESEL_CFG_HOLD_ALIGN 0 891 #define CTL_REGS_IEEE_MODESEL_DEFAULT_IEEE_MODESEL_CFG_HOLD_BITS 1 892 #define CTL_REGS_IEEE_MODESEL_DEFAULT_IEEE_MODESEL_CFG_HOLD_SHIFT 7 893 894 /* ctl_regs :: ieee_modesel_default :: frc_ieee_modesel_def [06:06] */ 895 #define CTL_REGS_IEEE_MODESEL_DEFAULT_FRC_IEEE_MODESEL_DEF_MASK 0x0040 896 #define CTL_REGS_IEEE_MODESEL_DEFAULT_FRC_IEEE_MODESEL_DEF_ALIGN 0 897 #define CTL_REGS_IEEE_MODESEL_DEFAULT_FRC_IEEE_MODESEL_DEF_BITS 1 898 #define CTL_REGS_IEEE_MODESEL_DEFAULT_FRC_IEEE_MODESEL_DEF_SHIFT 6 899 900 /* ctl_regs :: ieee_modesel_default :: ieee_modesel_def [05:00] */ 901 #define CTL_REGS_IEEE_MODESEL_DEFAULT_IEEE_MODESEL_DEF_MASK 0x003f 902 #define CTL_REGS_IEEE_MODESEL_DEFAULT_IEEE_MODESEL_DEF_ALIGN 0 903 #define CTL_REGS_IEEE_MODESEL_DEFAULT_IEEE_MODESEL_DEF_BITS 6 904 #define CTL_REGS_IEEE_MODESEL_DEFAULT_IEEE_MODESEL_DEF_SHIFT 0 905 906 907 /**************************************************************************** 908 * ctl_regs :: led_ctrl 909 */ 910 /* ctl_regs :: led_ctrl :: reserved0 [15:12] */ 911 #define CTL_REGS_LED_CTRL_RESERVED0_MASK 0xf000 912 #define CTL_REGS_LED_CTRL_RESERVED0_ALIGN 0 913 #define CTL_REGS_LED_CTRL_RESERVED0_BITS 4 914 #define CTL_REGS_LED_CTRL_RESERVED0_SHIFT 12 915 916 /* ctl_regs :: led_ctrl :: led_gpio_select [11:09] */ 917 #define CTL_REGS_LED_CTRL_LED_GPIO_SELECT_MASK 0x0e00 918 #define CTL_REGS_LED_CTRL_LED_GPIO_SELECT_ALIGN 0 919 #define CTL_REGS_LED_CTRL_LED_GPIO_SELECT_BITS 3 920 #define CTL_REGS_LED_CTRL_LED_GPIO_SELECT_SHIFT 9 921 922 /* ctl_regs :: led_ctrl :: led_en [08:08] */ 923 #define CTL_REGS_LED_CTRL_LED_EN_MASK 0x0100 924 #define CTL_REGS_LED_CTRL_LED_EN_ALIGN 0 925 #define CTL_REGS_LED_CTRL_LED_EN_BITS 1 926 #define CTL_REGS_LED_CTRL_LED_EN_SHIFT 8 927 928 /* ctl_regs :: led_ctrl :: led_base_div [07:06] */ 929 #define CTL_REGS_LED_CTRL_LED_BASE_DIV_MASK 0x00c0 930 #define CTL_REGS_LED_CTRL_LED_BASE_DIV_ALIGN 0 931 #define CTL_REGS_LED_CTRL_LED_BASE_DIV_BITS 2 932 #define CTL_REGS_LED_CTRL_LED_BASE_DIV_SHIFT 6 933 934 /* ctl_regs :: led_ctrl :: led_on_time [05:03] */ 935 #define CTL_REGS_LED_CTRL_LED_ON_TIME_MASK 0x0038 936 #define CTL_REGS_LED_CTRL_LED_ON_TIME_ALIGN 0 937 #define CTL_REGS_LED_CTRL_LED_ON_TIME_BITS 3 938 #define CTL_REGS_LED_CTRL_LED_ON_TIME_SHIFT 3 939 940 /* ctl_regs :: led_ctrl :: led_off_time [02:00] */ 941 #define CTL_REGS_LED_CTRL_LED_OFF_TIME_MASK 0x0007 942 #define CTL_REGS_LED_CTRL_LED_OFF_TIME_ALIGN 0 943 #define CTL_REGS_LED_CTRL_LED_OFF_TIME_BITS 3 944 #define CTL_REGS_LED_CTRL_LED_OFF_TIME_SHIFT 0 945 946 947 /**************************************************************************** 948 * ctl_regs :: eisr 949 */ 950 /* ctl_regs :: eisr :: reserved0 [15:07] */ 951 #define CTL_REGS_EISR_RESERVED0_MASK 0xff80 952 #define CTL_REGS_EISR_RESERVED0_ALIGN 0 953 #define CTL_REGS_EISR_RESERVED0_BITS 9 954 #define CTL_REGS_EISR_RESERVED0_SHIFT 7 955 956 /* ctl_regs :: eisr :: watch_dog_timer [06:06] */ 957 #define CTL_REGS_EISR_WATCH_DOG_TIMER_MASK 0x0040 958 #define CTL_REGS_EISR_WATCH_DOG_TIMER_ALIGN 0 959 #define CTL_REGS_EISR_WATCH_DOG_TIMER_BITS 1 960 #define CTL_REGS_EISR_WATCH_DOG_TIMER_SHIFT 6 961 962 /* ctl_regs :: eisr :: msg_out [05:05] */ 963 #define CTL_REGS_EISR_MSG_OUT_MASK 0x0020 964 #define CTL_REGS_EISR_MSG_OUT_ALIGN 0 965 #define CTL_REGS_EISR_MSG_OUT_BITS 1 966 #define CTL_REGS_EISR_MSG_OUT_SHIFT 5 967 968 /* ctl_regs :: eisr :: reserved1 [04:02] */ 969 #define CTL_REGS_EISR_RESERVED1_MASK 0x001c 970 #define CTL_REGS_EISR_RESERVED1_ALIGN 0 971 #define CTL_REGS_EISR_RESERVED1_BITS 3 972 #define CTL_REGS_EISR_RESERVED1_SHIFT 2 973 974 /* ctl_regs :: eisr :: tx_fifo_error [01:01] */ 975 #define CTL_REGS_EISR_TX_FIFO_ERROR_MASK 0x0002 976 #define CTL_REGS_EISR_TX_FIFO_ERROR_ALIGN 0 977 #define CTL_REGS_EISR_TX_FIFO_ERROR_BITS 1 978 #define CTL_REGS_EISR_TX_FIFO_ERROR_SHIFT 1 979 980 /* ctl_regs :: eisr :: rx_fifo_error [00:00] */ 981 #define CTL_REGS_EISR_RX_FIFO_ERROR_MASK 0x0001 982 #define CTL_REGS_EISR_RX_FIFO_ERROR_ALIGN 0 983 #define CTL_REGS_EISR_RX_FIFO_ERROR_BITS 1 984 #define CTL_REGS_EISR_RX_FIFO_ERROR_SHIFT 0 985 986 987 /**************************************************************************** 988 * ctl_regs :: eimr 989 */ 990 /* ctl_regs :: eimr :: reserved0 [15:07] */ 991 #define CTL_REGS_EIMR_RESERVED0_MASK 0xff80 992 #define CTL_REGS_EIMR_RESERVED0_ALIGN 0 993 #define CTL_REGS_EIMR_RESERVED0_BITS 9 994 #define CTL_REGS_EIMR_RESERVED0_SHIFT 7 995 996 /* ctl_regs :: eimr :: mask_watch_dog_timer [06:06] */ 997 #define CTL_REGS_EIMR_MASK_WATCH_DOG_TIMER_MASK 0x0040 998 #define CTL_REGS_EIMR_MASK_WATCH_DOG_TIMER_ALIGN 0 999 #define CTL_REGS_EIMR_MASK_WATCH_DOG_TIMER_BITS 1 1000 #define CTL_REGS_EIMR_MASK_WATCH_DOG_TIMER_SHIFT 6 1001 1002 /* ctl_regs :: eimr :: mask_msg_out [05:05] */ 1003 #define CTL_REGS_EIMR_MASK_MSG_OUT_MASK 0x0020 1004 #define CTL_REGS_EIMR_MASK_MSG_OUT_ALIGN 0 1005 #define CTL_REGS_EIMR_MASK_MSG_OUT_BITS 1 1006 #define CTL_REGS_EIMR_MASK_MSG_OUT_SHIFT 5 1007 1008 /* ctl_regs :: eimr :: reserved1 [04:02] */ 1009 #define CTL_REGS_EIMR_RESERVED1_MASK 0x001c 1010 #define CTL_REGS_EIMR_RESERVED1_ALIGN 0 1011 #define CTL_REGS_EIMR_RESERVED1_BITS 3 1012 #define CTL_REGS_EIMR_RESERVED1_SHIFT 2 1013 1014 /* ctl_regs :: eimr :: mask_tx_fifo_error [01:01] */ 1015 #define CTL_REGS_EIMR_MASK_TX_FIFO_ERROR_MASK 0x0002 1016 #define CTL_REGS_EIMR_MASK_TX_FIFO_ERROR_ALIGN 0 1017 #define CTL_REGS_EIMR_MASK_TX_FIFO_ERROR_BITS 1 1018 #define CTL_REGS_EIMR_MASK_TX_FIFO_ERROR_SHIFT 1 1019 1020 /* ctl_regs :: eimr :: mask_rx_fifo_error [00:00] */ 1021 #define CTL_REGS_EIMR_MASK_RX_FIFO_ERROR_MASK 0x0001 1022 #define CTL_REGS_EIMR_MASK_RX_FIFO_ERROR_ALIGN 0 1023 #define CTL_REGS_EIMR_MASK_RX_FIFO_ERROR_BITS 1 1024 #define CTL_REGS_EIMR_MASK_RX_FIFO_ERROR_SHIFT 0 1025 1026 1027 /**************************************************************************** 1028 * ctl_regs :: eipr 1029 */ 1030 /* ctl_regs :: eipr :: reserved0 [15:07] */ 1031 #define CTL_REGS_EIPR_RESERVED0_MASK 0xff80 1032 #define CTL_REGS_EIPR_RESERVED0_ALIGN 0 1033 #define CTL_REGS_EIPR_RESERVED0_BITS 9 1034 #define CTL_REGS_EIPR_RESERVED0_SHIFT 7 1035 1036 /* ctl_regs :: eipr :: p_watch_dog_timer [06:06] */ 1037 #define CTL_REGS_EIPR_P_WATCH_DOG_TIMER_MASK 0x0040 1038 #define CTL_REGS_EIPR_P_WATCH_DOG_TIMER_ALIGN 0 1039 #define CTL_REGS_EIPR_P_WATCH_DOG_TIMER_BITS 1 1040 #define CTL_REGS_EIPR_P_WATCH_DOG_TIMER_SHIFT 6 1041 1042 /* ctl_regs :: eipr :: p_msg_out [05:05] */ 1043 #define CTL_REGS_EIPR_P_MSG_OUT_MASK 0x0020 1044 #define CTL_REGS_EIPR_P_MSG_OUT_ALIGN 0 1045 #define CTL_REGS_EIPR_P_MSG_OUT_BITS 1 1046 #define CTL_REGS_EIPR_P_MSG_OUT_SHIFT 5 1047 1048 /* ctl_regs :: eipr :: reserved1 [04:02] */ 1049 #define CTL_REGS_EIPR_RESERVED1_MASK 0x001c 1050 #define CTL_REGS_EIPR_RESERVED1_ALIGN 0 1051 #define CTL_REGS_EIPR_RESERVED1_BITS 3 1052 #define CTL_REGS_EIPR_RESERVED1_SHIFT 2 1053 1054 /* ctl_regs :: eipr :: p_tx_fifo_error [01:01] */ 1055 #define CTL_REGS_EIPR_P_TX_FIFO_ERROR_MASK 0x0002 1056 #define CTL_REGS_EIPR_P_TX_FIFO_ERROR_ALIGN 0 1057 #define CTL_REGS_EIPR_P_TX_FIFO_ERROR_BITS 1 1058 #define CTL_REGS_EIPR_P_TX_FIFO_ERROR_SHIFT 1 1059 1060 /* ctl_regs :: eipr :: p_rx_fifo_error [00:00] */ 1061 #define CTL_REGS_EIPR_P_RX_FIFO_ERROR_MASK 0x0001 1062 #define CTL_REGS_EIPR_P_RX_FIFO_ERROR_ALIGN 0 1063 #define CTL_REGS_EIPR_P_RX_FIFO_ERROR_BITS 1 1064 #define CTL_REGS_EIPR_P_RX_FIFO_ERROR_SHIFT 0 1065 1066 1067 /**************************************************************************** 1068 * ctl_regs :: pwrup 1069 */ 1070 /* ctl_regs :: pwrup :: reserved0 [15:03] */ 1071 #define CTL_REGS_PWRUP_RESERVED0_MASK 0xfff8 1072 #define CTL_REGS_PWRUP_RESERVED0_ALIGN 0 1073 #define CTL_REGS_PWRUP_RESERVED0_BITS 13 1074 #define CTL_REGS_PWRUP_RESERVED0_SHIFT 3 1075 1076 /* ctl_regs :: pwrup :: pwrup_done [02:02] */ 1077 #define CTL_REGS_PWRUP_PWRUP_DONE_MASK 0x0004 1078 #define CTL_REGS_PWRUP_PWRUP_DONE_ALIGN 0 1079 #define CTL_REGS_PWRUP_PWRUP_DONE_BITS 1 1080 #define CTL_REGS_PWRUP_PWRUP_DONE_SHIFT 2 1081 1082 /* ctl_regs :: pwrup :: frc_pwrup_done [01:01] */ 1083 #define CTL_REGS_PWRUP_FRC_PWRUP_DONE_MASK 0x0002 1084 #define CTL_REGS_PWRUP_FRC_PWRUP_DONE_ALIGN 0 1085 #define CTL_REGS_PWRUP_FRC_PWRUP_DONE_BITS 1 1086 #define CTL_REGS_PWRUP_FRC_PWRUP_DONE_SHIFT 1 1087 1088 /* ctl_regs :: pwrup :: dis_pwr_seq [00:00] */ 1089 #define CTL_REGS_PWRUP_DIS_PWR_SEQ_MASK 0x0001 1090 #define CTL_REGS_PWRUP_DIS_PWR_SEQ_ALIGN 0 1091 #define CTL_REGS_PWRUP_DIS_PWR_SEQ_BITS 1 1092 #define CTL_REGS_PWRUP_DIS_PWR_SEQ_SHIFT 0 1093 1094 1095 /**************************************************************************** 1096 * ctl_regs :: misr 1097 */ 1098 /* ctl_regs :: misr :: token_req_intr [15:15] */ 1099 #define CTL_REGS_MISR_TOKEN_REQ_INTR_MASK 0x8000 1100 #define CTL_REGS_MISR_TOKEN_REQ_INTR_ALIGN 0 1101 #define CTL_REGS_MISR_TOKEN_REQ_INTR_BITS 1 1102 #define CTL_REGS_MISR_TOKEN_REQ_INTR_SHIFT 15 1103 1104 /* ctl_regs :: misr :: timer_intr [14:07] */ 1105 #define CTL_REGS_MISR_TIMER_INTR_MASK 0x7f80 1106 #define CTL_REGS_MISR_TIMER_INTR_ALIGN 0 1107 #define CTL_REGS_MISR_TIMER_INTR_BITS 8 1108 #define CTL_REGS_MISR_TIMER_INTR_SHIFT 7 1109 1110 /* ctl_regs :: misr :: reserved_for_eco0 [06:03] */ 1111 #define CTL_REGS_MISR_RESERVED_FOR_ECO0_MASK 0x0078 1112 #define CTL_REGS_MISR_RESERVED_FOR_ECO0_ALIGN 0 1113 #define CTL_REGS_MISR_RESERVED_FOR_ECO0_BITS 4 1114 #define CTL_REGS_MISR_RESERVED_FOR_ECO0_SHIFT 3 1115 1116 /* ctl_regs :: misr :: cdr_channel_intr [02:02] */ 1117 #define CTL_REGS_MISR_CDR_CHANNEL_INTR_MASK 0x0004 1118 #define CTL_REGS_MISR_CDR_CHANNEL_INTR_ALIGN 0 1119 #define CTL_REGS_MISR_CDR_CHANNEL_INTR_BITS 1 1120 #define CTL_REGS_MISR_CDR_CHANNEL_INTR_SHIFT 2 1121 1122 /* ctl_regs :: misr :: tx_analog_intr [01:01] */ 1123 #define CTL_REGS_MISR_TX_ANALOG_INTR_MASK 0x0002 1124 #define CTL_REGS_MISR_TX_ANALOG_INTR_ALIGN 0 1125 #define CTL_REGS_MISR_TX_ANALOG_INTR_BITS 1 1126 #define CTL_REGS_MISR_TX_ANALOG_INTR_SHIFT 1 1127 1128 /* ctl_regs :: misr :: rx_analog_intr [00:00] */ 1129 #define CTL_REGS_MISR_RX_ANALOG_INTR_MASK 0x0001 1130 #define CTL_REGS_MISR_RX_ANALOG_INTR_ALIGN 0 1131 #define CTL_REGS_MISR_RX_ANALOG_INTR_BITS 1 1132 #define CTL_REGS_MISR_RX_ANALOG_INTR_SHIFT 0 1133 1134 1135 /**************************************************************************** 1136 * ctl_regs :: mimr 1137 */ 1138 /* ctl_regs :: mimr :: token_req_mask [15:15] */ 1139 #define CTL_REGS_MIMR_TOKEN_REQ_MASK_MASK 0x8000 1140 #define CTL_REGS_MIMR_TOKEN_REQ_MASK_ALIGN 0 1141 #define CTL_REGS_MIMR_TOKEN_REQ_MASK_BITS 1 1142 #define CTL_REGS_MIMR_TOKEN_REQ_MASK_SHIFT 15 1143 1144 /* ctl_regs :: mimr :: timer_mask [14:07] */ 1145 #define CTL_REGS_MIMR_TIMER_MASK_MASK 0x7f80 1146 #define CTL_REGS_MIMR_TIMER_MASK_ALIGN 0 1147 #define CTL_REGS_MIMR_TIMER_MASK_BITS 8 1148 #define CTL_REGS_MIMR_TIMER_MASK_SHIFT 7 1149 1150 /* ctl_regs :: mimr :: reserved_for_eco0 [06:03] */ 1151 #define CTL_REGS_MIMR_RESERVED_FOR_ECO0_MASK 0x0078 1152 #define CTL_REGS_MIMR_RESERVED_FOR_ECO0_ALIGN 0 1153 #define CTL_REGS_MIMR_RESERVED_FOR_ECO0_BITS 4 1154 #define CTL_REGS_MIMR_RESERVED_FOR_ECO0_SHIFT 3 1155 1156 /* ctl_regs :: mimr :: cdr_channel_mask [02:02] */ 1157 #define CTL_REGS_MIMR_CDR_CHANNEL_MASK_MASK 0x0004 1158 #define CTL_REGS_MIMR_CDR_CHANNEL_MASK_ALIGN 0 1159 #define CTL_REGS_MIMR_CDR_CHANNEL_MASK_BITS 1 1160 #define CTL_REGS_MIMR_CDR_CHANNEL_MASK_SHIFT 2 1161 1162 /* ctl_regs :: mimr :: tx_analog_mask [01:01] */ 1163 #define CTL_REGS_MIMR_TX_ANALOG_MASK_MASK 0x0002 1164 #define CTL_REGS_MIMR_TX_ANALOG_MASK_ALIGN 0 1165 #define CTL_REGS_MIMR_TX_ANALOG_MASK_BITS 1 1166 #define CTL_REGS_MIMR_TX_ANALOG_MASK_SHIFT 1 1167 1168 /* ctl_regs :: mimr :: rx_analog_mask [00:00] */ 1169 #define CTL_REGS_MIMR_RX_ANALOG_MASK_MASK 0x0001 1170 #define CTL_REGS_MIMR_RX_ANALOG_MASK_ALIGN 0 1171 #define CTL_REGS_MIMR_RX_ANALOG_MASK_BITS 1 1172 #define CTL_REGS_MIMR_RX_ANALOG_MASK_SHIFT 0 1173 1174 1175 /**************************************************************************** 1176 * ctl_regs :: mipm 1177 */ 1178 /* ctl_regs :: mipm :: p_token_req_intr [15:15] */ 1179 #define CTL_REGS_MIPM_P_TOKEN_REQ_INTR_MASK 0x8000 1180 #define CTL_REGS_MIPM_P_TOKEN_REQ_INTR_ALIGN 0 1181 #define CTL_REGS_MIPM_P_TOKEN_REQ_INTR_BITS 1 1182 #define CTL_REGS_MIPM_P_TOKEN_REQ_INTR_SHIFT 15 1183 1184 /* ctl_regs :: mipm :: p_timer_intr [14:07] */ 1185 #define CTL_REGS_MIPM_P_TIMER_INTR_MASK 0x7f80 1186 #define CTL_REGS_MIPM_P_TIMER_INTR_ALIGN 0 1187 #define CTL_REGS_MIPM_P_TIMER_INTR_BITS 8 1188 #define CTL_REGS_MIPM_P_TIMER_INTR_SHIFT 7 1189 1190 /* ctl_regs :: mipm :: reserved_for_eco0 [06:03] */ 1191 #define CTL_REGS_MIPM_RESERVED_FOR_ECO0_MASK 0x0078 1192 #define CTL_REGS_MIPM_RESERVED_FOR_ECO0_ALIGN 0 1193 #define CTL_REGS_MIPM_RESERVED_FOR_ECO0_BITS 4 1194 #define CTL_REGS_MIPM_RESERVED_FOR_ECO0_SHIFT 3 1195 1196 /* ctl_regs :: mipm :: p_cdr_channel_intr [02:02] */ 1197 #define CTL_REGS_MIPM_P_CDR_CHANNEL_INTR_MASK 0x0004 1198 #define CTL_REGS_MIPM_P_CDR_CHANNEL_INTR_ALIGN 0 1199 #define CTL_REGS_MIPM_P_CDR_CHANNEL_INTR_BITS 1 1200 #define CTL_REGS_MIPM_P_CDR_CHANNEL_INTR_SHIFT 2 1201 1202 /* ctl_regs :: mipm :: p_tx_analog_intr [01:01] */ 1203 #define CTL_REGS_MIPM_P_TX_ANALOG_INTR_MASK 0x0002 1204 #define CTL_REGS_MIPM_P_TX_ANALOG_INTR_ALIGN 0 1205 #define CTL_REGS_MIPM_P_TX_ANALOG_INTR_BITS 1 1206 #define CTL_REGS_MIPM_P_TX_ANALOG_INTR_SHIFT 1 1207 1208 /* ctl_regs :: mipm :: p_rx_analog_intr [00:00] */ 1209 #define CTL_REGS_MIPM_P_RX_ANALOG_INTR_MASK 0x0001 1210 #define CTL_REGS_MIPM_P_RX_ANALOG_INTR_ALIGN 0 1211 #define CTL_REGS_MIPM_P_RX_ANALOG_INTR_BITS 1 1212 #define CTL_REGS_MIPM_P_RX_ANALOG_INTR_SHIFT 0 1213 1214 1215 /**************************************************************************** 1216 * ctl_regs :: mscr 1217 */ 1218 /* ctl_regs :: mscr :: global_intr_mask [15:15] */ 1219 #define CTL_REGS_MSCR_GLOBAL_INTR_MASK_MASK 0x8000 1220 #define CTL_REGS_MSCR_GLOBAL_INTR_MASK_ALIGN 0 1221 #define CTL_REGS_MSCR_GLOBAL_INTR_MASK_BITS 1 1222 #define CTL_REGS_MSCR_GLOBAL_INTR_MASK_SHIFT 15 1223 1224 /* ctl_regs :: mscr :: reserved0 [14:04] */ 1225 #define CTL_REGS_MSCR_RESERVED0_MASK 0x7ff0 1226 #define CTL_REGS_MSCR_RESERVED0_ALIGN 0 1227 #define CTL_REGS_MSCR_RESERVED0_BITS 11 1228 #define CTL_REGS_MSCR_RESERVED0_SHIFT 4 1229 1230 /* ctl_regs :: mscr :: isr_ram_en [03:03] */ 1231 #define CTL_REGS_MSCR_ISR_RAM_EN_MASK 0x0008 1232 #define CTL_REGS_MSCR_ISR_RAM_EN_ALIGN 0 1233 #define CTL_REGS_MSCR_ISR_RAM_EN_BITS 1 1234 #define CTL_REGS_MSCR_ISR_RAM_EN_SHIFT 3 1235 1236 /* ctl_regs :: mscr :: dtna_micro_access [02:02] */ 1237 #define CTL_REGS_MSCR_DTNA_MICRO_ACCESS_MASK 0x0004 1238 #define CTL_REGS_MSCR_DTNA_MICRO_ACCESS_ALIGN 0 1239 #define CTL_REGS_MSCR_DTNA_MICRO_ACCESS_BITS 1 1240 #define CTL_REGS_MSCR_DTNA_MICRO_ACCESS_SHIFT 2 1241 1242 /* ctl_regs :: mscr :: uc_reboot_ctl [01:01] */ 1243 #define CTL_REGS_MSCR_UC_REBOOT_CTL_MASK 0x0002 1244 #define CTL_REGS_MSCR_UC_REBOOT_CTL_ALIGN 0 1245 #define CTL_REGS_MSCR_UC_REBOOT_CTL_BITS 1 1246 #define CTL_REGS_MSCR_UC_REBOOT_CTL_SHIFT 1 1247 1248 /* ctl_regs :: mscr :: reserved1 [00:00] */ 1249 #define CTL_REGS_MSCR_RESERVED1_MASK 0x0001 1250 #define CTL_REGS_MSCR_RESERVED1_ALIGN 0 1251 #define CTL_REGS_MSCR_RESERVED1_BITS 1 1252 #define CTL_REGS_MSCR_RESERVED1_SHIFT 0 1253 1254 1255 /**************************************************************************** 1256 * ctl_regs :: msgout 1257 */ 1258 /* ctl_regs :: msgout :: msgout_val [15:00] */ 1259 #define CTL_REGS_MSGOUT_MSGOUT_VAL_MASK 0xffff 1260 #define CTL_REGS_MSGOUT_MSGOUT_VAL_ALIGN 0 1261 #define CTL_REGS_MSGOUT_MSGOUT_VAL_BITS 16 1262 #define CTL_REGS_MSGOUT_MSGOUT_VAL_SHIFT 0 1263 1264 1265 /**************************************************************************** 1266 * ctl_regs :: msgin 1267 */ 1268 /* ctl_regs :: msgin :: msgin_val [15:00] */ 1269 #define CTL_REGS_MSGIN_MSGIN_VAL_MASK 0xffff 1270 #define CTL_REGS_MSGIN_MSGIN_VAL_ALIGN 0 1271 #define CTL_REGS_MSGIN_MSGIN_VAL_BITS 16 1272 #define CTL_REGS_MSGIN_MSGIN_VAL_SHIFT 0 1273 1274 1275 /**************************************************************************** 1276 * ctl_regs :: boot 1277 */ 1278 /* ctl_regs :: boot :: reserved0 [15:12] */ 1279 #define CTL_REGS_BOOT_RESERVED0_MASK 0xf000 1280 #define CTL_REGS_BOOT_RESERVED0_ALIGN 0 1281 #define CTL_REGS_BOOT_RESERVED0_BITS 4 1282 #define CTL_REGS_BOOT_RESERVED0_SHIFT 12 1283 1284 /* ctl_regs :: boot :: spi_tristate_ctrl [11:11] */ 1285 #define CTL_REGS_BOOT_SPI_TRISTATE_CTRL_MASK 0x0800 1286 #define CTL_REGS_BOOT_SPI_TRISTATE_CTRL_ALIGN 0 1287 #define CTL_REGS_BOOT_SPI_TRISTATE_CTRL_BITS 1 1288 #define CTL_REGS_BOOT_SPI_TRISTATE_CTRL_SHIFT 11 1289 1290 /* ctl_regs :: boot :: reserved1 [10:03] */ 1291 #define CTL_REGS_BOOT_RESERVED1_MASK 0x07f8 1292 #define CTL_REGS_BOOT_RESERVED1_ALIGN 0 1293 #define CTL_REGS_BOOT_RESERVED1_BITS 8 1294 #define CTL_REGS_BOOT_RESERVED1_SHIFT 3 1295 1296 /* ctl_regs :: boot :: serboot_done_once [02:02] */ 1297 #define CTL_REGS_BOOT_SERBOOT_DONE_ONCE_MASK 0x0004 1298 #define CTL_REGS_BOOT_SERBOOT_DONE_ONCE_ALIGN 0 1299 #define CTL_REGS_BOOT_SERBOOT_DONE_ONCE_BITS 1 1300 #define CTL_REGS_BOOT_SERBOOT_DONE_ONCE_SHIFT 2 1301 1302 /* ctl_regs :: boot :: serboot_busy [01:01] */ 1303 #define CTL_REGS_BOOT_SERBOOT_BUSY_MASK 0x0002 1304 #define CTL_REGS_BOOT_SERBOOT_BUSY_ALIGN 0 1305 #define CTL_REGS_BOOT_SERBOOT_BUSY_BITS 1 1306 #define CTL_REGS_BOOT_SERBOOT_BUSY_SHIFT 1 1307 1308 /* ctl_regs :: boot :: firmware_loaded [00:00] */ 1309 #define CTL_REGS_BOOT_FIRMWARE_LOADED_MASK 0x0001 1310 #define CTL_REGS_BOOT_FIRMWARE_LOADED_ALIGN 0 1311 #define CTL_REGS_BOOT_FIRMWARE_LOADED_BITS 1 1312 #define CTL_REGS_BOOT_FIRMWARE_LOADED_SHIFT 0 1313 1314 1315 /**************************************************************************** 1316 * ctl_regs :: gpreg0 1317 */ 1318 /* ctl_regs :: gpreg0 :: gpreg0_data [15:00] */ 1319 #define CTL_REGS_GPREG0_GPREG0_DATA_MASK 0xffff 1320 #define CTL_REGS_GPREG0_GPREG0_DATA_ALIGN 0 1321 #define CTL_REGS_GPREG0_GPREG0_DATA_BITS 16 1322 #define CTL_REGS_GPREG0_GPREG0_DATA_SHIFT 0 1323 1324 1325 /**************************************************************************** 1326 * ctl_regs :: gpreg1 1327 */ 1328 /* ctl_regs :: gpreg1 :: gpreg1_data [15:00] */ 1329 #define CTL_REGS_GPREG1_GPREG1_DATA_MASK 0xffff 1330 #define CTL_REGS_GPREG1_GPREG1_DATA_ALIGN 0 1331 #define CTL_REGS_GPREG1_GPREG1_DATA_BITS 16 1332 #define CTL_REGS_GPREG1_GPREG1_DATA_SHIFT 0 1333 1334 1335 /**************************************************************************** 1336 * ctl_regs :: gpreg2 1337 */ 1338 /* ctl_regs :: gpreg2 :: gpreg2_data [15:00] */ 1339 #define CTL_REGS_GPREG2_GPREG2_DATA_MASK 0xffff 1340 #define CTL_REGS_GPREG2_GPREG2_DATA_ALIGN 0 1341 #define CTL_REGS_GPREG2_GPREG2_DATA_BITS 16 1342 #define CTL_REGS_GPREG2_GPREG2_DATA_SHIFT 0 1343 1344 1345 /**************************************************************************** 1346 * ctl_regs :: gpreg3 1347 */ 1348 /* ctl_regs :: gpreg3 :: gpreg3_data [15:00] */ 1349 #define CTL_REGS_GPREG3_GPREG3_DATA_MASK 0xffff 1350 #define CTL_REGS_GPREG3_GPREG3_DATA_ALIGN 0 1351 #define CTL_REGS_GPREG3_GPREG3_DATA_BITS 16 1352 #define CTL_REGS_GPREG3_GPREG3_DATA_SHIFT 0 1353 1354 1355 /**************************************************************************** 1356 * ctl_regs :: gpreg4 1357 */ 1358 /* ctl_regs :: gpreg4 :: gpreg4_data [15:00] */ 1359 #define CTL_REGS_GPREG4_GPREG4_DATA_MASK 0xffff 1360 #define CTL_REGS_GPREG4_GPREG4_DATA_ALIGN 0 1361 #define CTL_REGS_GPREG4_GPREG4_DATA_BITS 16 1362 #define CTL_REGS_GPREG4_GPREG4_DATA_SHIFT 0 1363 1364 1365 /**************************************************************************** 1366 * ctl_regs :: gpreg5 1367 */ 1368 /* ctl_regs :: gpreg5 :: gpreg5_data [15:00] */ 1369 #define CTL_REGS_GPREG5_GPREG5_DATA_MASK 0xffff 1370 #define CTL_REGS_GPREG5_GPREG5_DATA_ALIGN 0 1371 #define CTL_REGS_GPREG5_GPREG5_DATA_BITS 16 1372 #define CTL_REGS_GPREG5_GPREG5_DATA_SHIFT 0 1373 1374 1375 /**************************************************************************** 1376 * ctl_regs :: gpreg6 1377 */ 1378 /* ctl_regs :: gpreg6 :: gpreg6_data [15:00] */ 1379 #define CTL_REGS_GPREG6_GPREG6_DATA_MASK 0xffff 1380 #define CTL_REGS_GPREG6_GPREG6_DATA_ALIGN 0 1381 #define CTL_REGS_GPREG6_GPREG6_DATA_BITS 16 1382 #define CTL_REGS_GPREG6_GPREG6_DATA_SHIFT 0 1383 1384 1385 /**************************************************************************** 1386 * ctl_regs :: gpreg7 1387 */ 1388 /* ctl_regs :: gpreg7 :: gpreg7_data [15:00] */ 1389 #define CTL_REGS_GPREG7_GPREG7_DATA_MASK 0xffff 1390 #define CTL_REGS_GPREG7_GPREG7_DATA_ALIGN 0 1391 #define CTL_REGS_GPREG7_GPREG7_DATA_BITS 16 1392 #define CTL_REGS_GPREG7_GPREG7_DATA_SHIFT 0 1393 1394 1395 /**************************************************************************** 1396 * ctl_regs :: gpreg8 1397 */ 1398 /* ctl_regs :: gpreg8 :: gpreg8_data [15:00] */ 1399 #define CTL_REGS_GPREG8_GPREG8_DATA_MASK 0xffff 1400 #define CTL_REGS_GPREG8_GPREG8_DATA_ALIGN 0 1401 #define CTL_REGS_GPREG8_GPREG8_DATA_BITS 16 1402 #define CTL_REGS_GPREG8_GPREG8_DATA_SHIFT 0 1403 1404 1405 /**************************************************************************** 1406 * ctl_regs :: gpreg9 1407 */ 1408 /* ctl_regs :: gpreg9 :: gpreg9_data [15:00] */ 1409 #define CTL_REGS_GPREG9_GPREG9_DATA_MASK 0xffff 1410 #define CTL_REGS_GPREG9_GPREG9_DATA_ALIGN 0 1411 #define CTL_REGS_GPREG9_GPREG9_DATA_BITS 16 1412 #define CTL_REGS_GPREG9_GPREG9_DATA_SHIFT 0 1413 1414 1415 /**************************************************************************** 1416 * ctl_regs :: gpreg10 1417 */ 1418 /* ctl_regs :: gpreg10 :: gpreg10_data [15:00] */ 1419 #define CTL_REGS_GPREG10_GPREG10_DATA_MASK 0xffff 1420 #define CTL_REGS_GPREG10_GPREG10_DATA_ALIGN 0 1421 #define CTL_REGS_GPREG10_GPREG10_DATA_BITS 16 1422 #define CTL_REGS_GPREG10_GPREG10_DATA_SHIFT 0 1423 1424 1425 /**************************************************************************** 1426 * ctl_regs :: gpreg11 1427 */ 1428 /* ctl_regs :: gpreg11 :: gpreg11_data [15:00] */ 1429 #define CTL_REGS_GPREG11_GPREG11_DATA_MASK 0xffff 1430 #define CTL_REGS_GPREG11_GPREG11_DATA_ALIGN 0 1431 #define CTL_REGS_GPREG11_GPREG11_DATA_BITS 16 1432 #define CTL_REGS_GPREG11_GPREG11_DATA_SHIFT 0 1433 1434 1435 /**************************************************************************** 1436 * ctl_regs :: gpreg12 1437 */ 1438 /* ctl_regs :: gpreg12 :: gpreg12_data [15:00] */ 1439 #define CTL_REGS_GPREG12_GPREG12_DATA_MASK 0xffff 1440 #define CTL_REGS_GPREG12_GPREG12_DATA_ALIGN 0 1441 #define CTL_REGS_GPREG12_GPREG12_DATA_BITS 16 1442 #define CTL_REGS_GPREG12_GPREG12_DATA_SHIFT 0 1443 1444 1445 /**************************************************************************** 1446 * ctl_regs :: gpreg13 1447 */ 1448 /* ctl_regs :: gpreg13 :: gpreg13_data [15:00] */ 1449 #define CTL_REGS_GPREG13_GPREG13_DATA_MASK 0xffff 1450 #define CTL_REGS_GPREG13_GPREG13_DATA_ALIGN 0 1451 #define CTL_REGS_GPREG13_GPREG13_DATA_BITS 16 1452 #define CTL_REGS_GPREG13_GPREG13_DATA_SHIFT 0 1453 1454 1455 /**************************************************************************** 1456 * ctl_regs :: gpreg14 1457 */ 1458 /* ctl_regs :: gpreg14 :: gpreg14_data [15:00] */ 1459 #define CTL_REGS_GPREG14_GPREG14_DATA_MASK 0xffff 1460 #define CTL_REGS_GPREG14_GPREG14_DATA_ALIGN 0 1461 #define CTL_REGS_GPREG14_GPREG14_DATA_BITS 16 1462 #define CTL_REGS_GPREG14_GPREG14_DATA_SHIFT 0 1463 1464 1465 /**************************************************************************** 1466 * ctl_regs :: gpreg15 1467 */ 1468 /* ctl_regs :: gpreg15 :: gpreg15_data [15:00] */ 1469 #define CTL_REGS_GPREG15_GPREG15_DATA_MASK 0xffff 1470 #define CTL_REGS_GPREG15_GPREG15_DATA_ALIGN 0 1471 #define CTL_REGS_GPREG15_GPREG15_DATA_BITS 16 1472 #define CTL_REGS_GPREG15_GPREG15_DATA_SHIFT 0 1473 1474 1475 /**************************************************************************** 1476 * ctl_regs :: fw_enable_type 1477 */ 1478 /* ctl_regs :: fw_enable_type :: fw_enable [15:00] */ 1479 #define CTL_REGS_FW_ENABLE_TYPE_FW_ENABLE_MASK 0xffff 1480 #define CTL_REGS_FW_ENABLE_TYPE_FW_ENABLE_ALIGN 0 1481 #define CTL_REGS_FW_ENABLE_TYPE_FW_ENABLE_BITS 16 1482 #define CTL_REGS_FW_ENABLE_TYPE_FW_ENABLE_SHIFT 0 1483 1484 1485 /**************************************************************************** 1486 * ctl_regs :: sys_rx_reset 1487 */ 1488 /* ctl_regs :: sys_rx_reset :: reserved0 [15:10] */ 1489 #define CTL_REGS_SYS_RX_RESET_RESERVED0_MASK 0xfc00 1490 #define CTL_REGS_SYS_RX_RESET_RESERVED0_ALIGN 0 1491 #define CTL_REGS_SYS_RX_RESET_RESERVED0_BITS 6 1492 #define CTL_REGS_SYS_RX_RESET_RESERVED0_SHIFT 10 1493 1494 /* ctl_regs :: sys_rx_reset :: srx_ln_rstb [09:00] */ 1495 #define CTL_REGS_SYS_RX_RESET_SRX_LN_RSTB_MASK 0x03ff 1496 #define CTL_REGS_SYS_RX_RESET_SRX_LN_RSTB_ALIGN 0 1497 #define CTL_REGS_SYS_RX_RESET_SRX_LN_RSTB_BITS 10 1498 #define CTL_REGS_SYS_RX_RESET_SRX_LN_RSTB_SHIFT 0 1499 1500 1501 /**************************************************************************** 1502 * ctl_regs :: sys_tx_reset 1503 */ 1504 /* ctl_regs :: sys_tx_reset :: reserved0 [15:10] */ 1505 #define CTL_REGS_SYS_TX_RESET_RESERVED0_MASK 0xfc00 1506 #define CTL_REGS_SYS_TX_RESET_RESERVED0_ALIGN 0 1507 #define CTL_REGS_SYS_TX_RESET_RESERVED0_BITS 6 1508 #define CTL_REGS_SYS_TX_RESET_RESERVED0_SHIFT 10 1509 1510 /* ctl_regs :: sys_tx_reset :: stx_ln_rstb [09:00] */ 1511 #define CTL_REGS_SYS_TX_RESET_STX_LN_RSTB_MASK 0x03ff 1512 #define CTL_REGS_SYS_TX_RESET_STX_LN_RSTB_ALIGN 0 1513 #define CTL_REGS_SYS_TX_RESET_STX_LN_RSTB_BITS 10 1514 #define CTL_REGS_SYS_TX_RESET_STX_LN_RSTB_SHIFT 0 1515 1516 1517 /**************************************************************************** 1518 * ctl_regs :: line_rx_reset 1519 */ 1520 /* ctl_regs :: line_rx_reset :: reserved0 [15:10] */ 1521 #define CTL_REGS_LINE_RX_RESET_RESERVED0_MASK 0xfc00 1522 #define CTL_REGS_LINE_RX_RESET_RESERVED0_ALIGN 0 1523 #define CTL_REGS_LINE_RX_RESET_RESERVED0_BITS 6 1524 #define CTL_REGS_LINE_RX_RESET_RESERVED0_SHIFT 10 1525 1526 /* ctl_regs :: line_rx_reset :: lrx_ln_rstb [09:00] */ 1527 #define CTL_REGS_LINE_RX_RESET_LRX_LN_RSTB_MASK 0x03ff 1528 #define CTL_REGS_LINE_RX_RESET_LRX_LN_RSTB_ALIGN 0 1529 #define CTL_REGS_LINE_RX_RESET_LRX_LN_RSTB_BITS 10 1530 #define CTL_REGS_LINE_RX_RESET_LRX_LN_RSTB_SHIFT 0 1531 1532 1533 /**************************************************************************** 1534 * ctl_regs :: line_tx_reset 1535 */ 1536 /* ctl_regs :: line_tx_reset :: reserved0 [15:10] */ 1537 #define CTL_REGS_LINE_TX_RESET_RESERVED0_MASK 0xfc00 1538 #define CTL_REGS_LINE_TX_RESET_RESERVED0_ALIGN 0 1539 #define CTL_REGS_LINE_TX_RESET_RESERVED0_BITS 6 1540 #define CTL_REGS_LINE_TX_RESET_RESERVED0_SHIFT 10 1541 1542 /* ctl_regs :: line_tx_reset :: ltx_ln_rstb [09:00] */ 1543 #define CTL_REGS_LINE_TX_RESET_LTX_LN_RSTB_MASK 0x03ff 1544 #define CTL_REGS_LINE_TX_RESET_LTX_LN_RSTB_ALIGN 0 1545 #define CTL_REGS_LINE_TX_RESET_LTX_LN_RSTB_BITS 10 1546 #define CTL_REGS_LINE_TX_RESET_LTX_LN_RSTB_SHIFT 0 1547 1548 1549 /**************************************************************************** 1550 * ctl_regs :: dc_reset 1551 */ 1552 /* ctl_regs :: dc_reset :: reserved0 [15:07] */ 1553 #define CTL_REGS_DC_RESET_RESERVED0_MASK 0xff80 1554 #define CTL_REGS_DC_RESET_RESERVED0_ALIGN 0 1555 #define CTL_REGS_DC_RESET_RESERVED0_BITS 9 1556 #define CTL_REGS_DC_RESET_RESERVED0_SHIFT 7 1557 1558 /* ctl_regs :: dc_reset :: dc_pll_reset_rescal_ovrd [06:06] */ 1559 #define CTL_REGS_DC_RESET_DC_PLL_RESET_RESCAL_OVRD_MASK 0x0040 1560 #define CTL_REGS_DC_RESET_DC_PLL_RESET_RESCAL_OVRD_ALIGN 0 1561 #define CTL_REGS_DC_RESET_DC_PLL_RESET_RESCAL_OVRD_BITS 1 1562 #define CTL_REGS_DC_RESET_DC_PLL_RESET_RESCAL_OVRD_SHIFT 6 1563 1564 /* ctl_regs :: dc_reset :: frc_dc_mdio_rstb [05:05] */ 1565 #define CTL_REGS_DC_RESET_FRC_DC_MDIO_RSTB_MASK 0x0020 1566 #define CTL_REGS_DC_RESET_FRC_DC_MDIO_RSTB_ALIGN 0 1567 #define CTL_REGS_DC_RESET_FRC_DC_MDIO_RSTB_BITS 1 1568 #define CTL_REGS_DC_RESET_FRC_DC_MDIO_RSTB_SHIFT 5 1569 1570 /* ctl_regs :: dc_reset :: dc_mdio_rstb [04:04] */ 1571 #define CTL_REGS_DC_RESET_DC_MDIO_RSTB_MASK 0x0010 1572 #define CTL_REGS_DC_RESET_DC_MDIO_RSTB_ALIGN 0 1573 #define CTL_REGS_DC_RESET_DC_MDIO_RSTB_BITS 1 1574 #define CTL_REGS_DC_RESET_DC_MDIO_RSTB_SHIFT 4 1575 1576 /* ctl_regs :: dc_reset :: frc_dc_pll_rstb [03:03] */ 1577 #define CTL_REGS_DC_RESET_FRC_DC_PLL_RSTB_MASK 0x0008 1578 #define CTL_REGS_DC_RESET_FRC_DC_PLL_RSTB_ALIGN 0 1579 #define CTL_REGS_DC_RESET_FRC_DC_PLL_RSTB_BITS 1 1580 #define CTL_REGS_DC_RESET_FRC_DC_PLL_RSTB_SHIFT 3 1581 1582 /* ctl_regs :: dc_reset :: dc_pll_rstb [02:02] */ 1583 #define CTL_REGS_DC_RESET_DC_PLL_RSTB_MASK 0x0004 1584 #define CTL_REGS_DC_RESET_DC_PLL_RSTB_ALIGN 0 1585 #define CTL_REGS_DC_RESET_DC_PLL_RSTB_BITS 1 1586 #define CTL_REGS_DC_RESET_DC_PLL_RSTB_SHIFT 2 1587 1588 /* ctl_regs :: dc_reset :: frc_dc_hw_rstb [01:01] */ 1589 #define CTL_REGS_DC_RESET_FRC_DC_HW_RSTB_MASK 0x0002 1590 #define CTL_REGS_DC_RESET_FRC_DC_HW_RSTB_ALIGN 0 1591 #define CTL_REGS_DC_RESET_FRC_DC_HW_RSTB_BITS 1 1592 #define CTL_REGS_DC_RESET_FRC_DC_HW_RSTB_SHIFT 1 1593 1594 /* ctl_regs :: dc_reset :: dc_hw_rstb [00:00] */ 1595 #define CTL_REGS_DC_RESET_DC_HW_RSTB_MASK 0x0001 1596 #define CTL_REGS_DC_RESET_DC_HW_RSTB_ALIGN 0 1597 #define CTL_REGS_DC_RESET_DC_HW_RSTB_BITS 1 1598 #define CTL_REGS_DC_RESET_DC_HW_RSTB_SHIFT 0 1599 1600 1601 /**************************************************************************** 1602 * ctl_regs :: frc_dc_hw_reset 1603 */ 1604 /* ctl_regs :: frc_dc_hw_reset :: reserved0 [15:10] */ 1605 #define CTL_REGS_FRC_DC_HW_RESET_RESERVED0_MASK 0xfc00 1606 #define CTL_REGS_FRC_DC_HW_RESET_RESERVED0_ALIGN 0 1607 #define CTL_REGS_FRC_DC_HW_RESET_RESERVED0_BITS 6 1608 #define CTL_REGS_FRC_DC_HW_RESET_RESERVED0_SHIFT 10 1609 1610 /* ctl_regs :: frc_dc_hw_reset :: frc_dc_hw_ln_rstb [09:00] */ 1611 #define CTL_REGS_FRC_DC_HW_RESET_FRC_DC_HW_LN_RSTB_MASK 0x03ff 1612 #define CTL_REGS_FRC_DC_HW_RESET_FRC_DC_HW_LN_RSTB_ALIGN 0 1613 #define CTL_REGS_FRC_DC_HW_RESET_FRC_DC_HW_LN_RSTB_BITS 10 1614 #define CTL_REGS_FRC_DC_HW_RESET_FRC_DC_HW_LN_RSTB_SHIFT 0 1615 1616 1617 /**************************************************************************** 1618 * ctl_regs :: dc_hw_reset 1619 */ 1620 /* ctl_regs :: dc_hw_reset :: reserved0 [15:10] */ 1621 #define CTL_REGS_DC_HW_RESET_RESERVED0_MASK 0xfc00 1622 #define CTL_REGS_DC_HW_RESET_RESERVED0_ALIGN 0 1623 #define CTL_REGS_DC_HW_RESET_RESERVED0_BITS 6 1624 #define CTL_REGS_DC_HW_RESET_RESERVED0_SHIFT 10 1625 1626 /* ctl_regs :: dc_hw_reset :: dc_hw_ln_rstb [09:00] */ 1627 #define CTL_REGS_DC_HW_RESET_DC_HW_LN_RSTB_MASK 0x03ff 1628 #define CTL_REGS_DC_HW_RESET_DC_HW_LN_RSTB_ALIGN 0 1629 #define CTL_REGS_DC_HW_RESET_DC_HW_LN_RSTB_BITS 10 1630 #define CTL_REGS_DC_HW_RESET_DC_HW_LN_RSTB_SHIFT 0 1631 1632 1633 /**************************************************************************** 1634 * ctl_regs :: frc_dc_mdio_reset 1635 */ 1636 /* ctl_regs :: frc_dc_mdio_reset :: reserved0 [15:10] */ 1637 #define CTL_REGS_FRC_DC_MDIO_RESET_RESERVED0_MASK 0xfc00 1638 #define CTL_REGS_FRC_DC_MDIO_RESET_RESERVED0_ALIGN 0 1639 #define CTL_REGS_FRC_DC_MDIO_RESET_RESERVED0_BITS 6 1640 #define CTL_REGS_FRC_DC_MDIO_RESET_RESERVED0_SHIFT 10 1641 1642 /* ctl_regs :: frc_dc_mdio_reset :: frc_dc_mdio_ln_rstb [09:00] */ 1643 #define CTL_REGS_FRC_DC_MDIO_RESET_FRC_DC_MDIO_LN_RSTB_MASK 0x03ff 1644 #define CTL_REGS_FRC_DC_MDIO_RESET_FRC_DC_MDIO_LN_RSTB_ALIGN 0 1645 #define CTL_REGS_FRC_DC_MDIO_RESET_FRC_DC_MDIO_LN_RSTB_BITS 10 1646 #define CTL_REGS_FRC_DC_MDIO_RESET_FRC_DC_MDIO_LN_RSTB_SHIFT 0 1647 1648 1649 /**************************************************************************** 1650 * ctl_regs :: dc_mdio_reset 1651 */ 1652 /* ctl_regs :: dc_mdio_reset :: reserved0 [15:10] */ 1653 #define CTL_REGS_DC_MDIO_RESET_RESERVED0_MASK 0xfc00 1654 #define CTL_REGS_DC_MDIO_RESET_RESERVED0_ALIGN 0 1655 #define CTL_REGS_DC_MDIO_RESET_RESERVED0_BITS 6 1656 #define CTL_REGS_DC_MDIO_RESET_RESERVED0_SHIFT 10 1657 1658 /* ctl_regs :: dc_mdio_reset :: dc_mdio_ln_rstb [09:00] */ 1659 #define CTL_REGS_DC_MDIO_RESET_DC_MDIO_LN_RSTB_MASK 0x03ff 1660 #define CTL_REGS_DC_MDIO_RESET_DC_MDIO_LN_RSTB_ALIGN 0 1661 #define CTL_REGS_DC_MDIO_RESET_DC_MDIO_LN_RSTB_BITS 10 1662 #define CTL_REGS_DC_MDIO_RESET_DC_MDIO_LN_RSTB_SHIFT 0 1663 1664 1665 /**************************************************************************** 1666 * ctl_regs :: frc_hctx_dig_reset 1667 */ 1668 /* ctl_regs :: frc_hctx_dig_reset :: reserved0 [15:07] */ 1669 #define CTL_REGS_FRC_HCTX_DIG_RESET_RESERVED0_MASK 0xff80 1670 #define CTL_REGS_FRC_HCTX_DIG_RESET_RESERVED0_ALIGN 0 1671 #define CTL_REGS_FRC_HCTX_DIG_RESET_RESERVED0_BITS 9 1672 #define CTL_REGS_FRC_HCTX_DIG_RESET_RESERVED0_SHIFT 7 1673 1674 /* ctl_regs :: frc_hctx_dig_reset :: frc_hctx_lfck_rstb [06:06] */ 1675 #define CTL_REGS_FRC_HCTX_DIG_RESET_FRC_HCTX_LFCK_RSTB_MASK 0x0040 1676 #define CTL_REGS_FRC_HCTX_DIG_RESET_FRC_HCTX_LFCK_RSTB_ALIGN 0 1677 #define CTL_REGS_FRC_HCTX_DIG_RESET_FRC_HCTX_LFCK_RSTB_BITS 1 1678 #define CTL_REGS_FRC_HCTX_DIG_RESET_FRC_HCTX_LFCK_RSTB_SHIFT 6 1679 1680 /* ctl_regs :: frc_hctx_dig_reset :: frc_hctx_dig_rstb [05:00] */ 1681 #define CTL_REGS_FRC_HCTX_DIG_RESET_FRC_HCTX_DIG_RSTB_MASK 0x003f 1682 #define CTL_REGS_FRC_HCTX_DIG_RESET_FRC_HCTX_DIG_RSTB_ALIGN 0 1683 #define CTL_REGS_FRC_HCTX_DIG_RESET_FRC_HCTX_DIG_RSTB_BITS 6 1684 #define CTL_REGS_FRC_HCTX_DIG_RESET_FRC_HCTX_DIG_RSTB_SHIFT 0 1685 1686 1687 /**************************************************************************** 1688 * ctl_regs :: hctx_dig_reset 1689 */ 1690 /* ctl_regs :: hctx_dig_reset :: reserved0 [15:07] */ 1691 #define CTL_REGS_HCTX_DIG_RESET_RESERVED0_MASK 0xff80 1692 #define CTL_REGS_HCTX_DIG_RESET_RESERVED0_ALIGN 0 1693 #define CTL_REGS_HCTX_DIG_RESET_RESERVED0_BITS 9 1694 #define CTL_REGS_HCTX_DIG_RESET_RESERVED0_SHIFT 7 1695 1696 /* ctl_regs :: hctx_dig_reset :: hctx_lfck_rstb [06:06] */ 1697 #define CTL_REGS_HCTX_DIG_RESET_HCTX_LFCK_RSTB_MASK 0x0040 1698 #define CTL_REGS_HCTX_DIG_RESET_HCTX_LFCK_RSTB_ALIGN 0 1699 #define CTL_REGS_HCTX_DIG_RESET_HCTX_LFCK_RSTB_BITS 1 1700 #define CTL_REGS_HCTX_DIG_RESET_HCTX_LFCK_RSTB_SHIFT 6 1701 1702 /* ctl_regs :: hctx_dig_reset :: hctx_dig_rstb [05:00] */ 1703 #define CTL_REGS_HCTX_DIG_RESET_HCTX_DIG_RSTB_MASK 0x003f 1704 #define CTL_REGS_HCTX_DIG_RESET_HCTX_DIG_RSTB_ALIGN 0 1705 #define CTL_REGS_HCTX_DIG_RESET_HCTX_DIG_RSTB_BITS 6 1706 #define CTL_REGS_HCTX_DIG_RESET_HCTX_DIG_RSTB_SHIFT 0 1707 1708 1709 /**************************************************************************** 1710 * ctl_regs :: frc_hctx_mdio_reset 1711 */ 1712 /* ctl_regs :: frc_hctx_mdio_reset :: reserved0 [15:06] */ 1713 #define CTL_REGS_FRC_HCTX_MDIO_RESET_RESERVED0_MASK 0xffc0 1714 #define CTL_REGS_FRC_HCTX_MDIO_RESET_RESERVED0_ALIGN 0 1715 #define CTL_REGS_FRC_HCTX_MDIO_RESET_RESERVED0_BITS 10 1716 #define CTL_REGS_FRC_HCTX_MDIO_RESET_RESERVED0_SHIFT 6 1717 1718 /* ctl_regs :: frc_hctx_mdio_reset :: frc_hctx_mdio_rstb [05:00] */ 1719 #define CTL_REGS_FRC_HCTX_MDIO_RESET_FRC_HCTX_MDIO_RSTB_MASK 0x003f 1720 #define CTL_REGS_FRC_HCTX_MDIO_RESET_FRC_HCTX_MDIO_RSTB_ALIGN 0 1721 #define CTL_REGS_FRC_HCTX_MDIO_RESET_FRC_HCTX_MDIO_RSTB_BITS 6 1722 #define CTL_REGS_FRC_HCTX_MDIO_RESET_FRC_HCTX_MDIO_RSTB_SHIFT 0 1723 1724 1725 /**************************************************************************** 1726 * ctl_regs :: hctx_mdio_reset 1727 */ 1728 /* ctl_regs :: hctx_mdio_reset :: reserved0 [15:06] */ 1729 #define CTL_REGS_HCTX_MDIO_RESET_RESERVED0_MASK 0xffc0 1730 #define CTL_REGS_HCTX_MDIO_RESET_RESERVED0_ALIGN 0 1731 #define CTL_REGS_HCTX_MDIO_RESET_RESERVED0_BITS 10 1732 #define CTL_REGS_HCTX_MDIO_RESET_RESERVED0_SHIFT 6 1733 1734 /* ctl_regs :: hctx_mdio_reset :: hctx_mdio_rstb [05:00] */ 1735 #define CTL_REGS_HCTX_MDIO_RESET_HCTX_MDIO_RSTB_MASK 0x003f 1736 #define CTL_REGS_HCTX_MDIO_RESET_HCTX_MDIO_RSTB_ALIGN 0 1737 #define CTL_REGS_HCTX_MDIO_RESET_HCTX_MDIO_RSTB_BITS 6 1738 #define CTL_REGS_HCTX_MDIO_RESET_HCTX_MDIO_RSTB_SHIFT 0 1739 1740 1741 /**************************************************************************** 1742 * ctl_regs :: frc_hcrx_dig_reset 1743 */ 1744 /* ctl_regs :: frc_hcrx_dig_reset :: reserved0 [15:07] */ 1745 #define CTL_REGS_FRC_HCRX_DIG_RESET_RESERVED0_MASK 0xff80 1746 #define CTL_REGS_FRC_HCRX_DIG_RESET_RESERVED0_ALIGN 0 1747 #define CTL_REGS_FRC_HCRX_DIG_RESET_RESERVED0_BITS 9 1748 #define CTL_REGS_FRC_HCRX_DIG_RESET_RESERVED0_SHIFT 7 1749 1750 /* ctl_regs :: frc_hcrx_dig_reset :: frc_hcrx_lfck_rstb [06:06] */ 1751 #define CTL_REGS_FRC_HCRX_DIG_RESET_FRC_HCRX_LFCK_RSTB_MASK 0x0040 1752 #define CTL_REGS_FRC_HCRX_DIG_RESET_FRC_HCRX_LFCK_RSTB_ALIGN 0 1753 #define CTL_REGS_FRC_HCRX_DIG_RESET_FRC_HCRX_LFCK_RSTB_BITS 1 1754 #define CTL_REGS_FRC_HCRX_DIG_RESET_FRC_HCRX_LFCK_RSTB_SHIFT 6 1755 1756 /* ctl_regs :: frc_hcrx_dig_reset :: frc_hcrx_dig_rstb [05:00] */ 1757 #define CTL_REGS_FRC_HCRX_DIG_RESET_FRC_HCRX_DIG_RSTB_MASK 0x003f 1758 #define CTL_REGS_FRC_HCRX_DIG_RESET_FRC_HCRX_DIG_RSTB_ALIGN 0 1759 #define CTL_REGS_FRC_HCRX_DIG_RESET_FRC_HCRX_DIG_RSTB_BITS 6 1760 #define CTL_REGS_FRC_HCRX_DIG_RESET_FRC_HCRX_DIG_RSTB_SHIFT 0 1761 1762 1763 /**************************************************************************** 1764 * ctl_regs :: hcrx_dig_reset 1765 */ 1766 /* ctl_regs :: hcrx_dig_reset :: reserved0 [15:07] */ 1767 #define CTL_REGS_HCRX_DIG_RESET_RESERVED0_MASK 0xff80 1768 #define CTL_REGS_HCRX_DIG_RESET_RESERVED0_ALIGN 0 1769 #define CTL_REGS_HCRX_DIG_RESET_RESERVED0_BITS 9 1770 #define CTL_REGS_HCRX_DIG_RESET_RESERVED0_SHIFT 7 1771 1772 /* ctl_regs :: hcrx_dig_reset :: hcrx_lfck_rstb [06:06] */ 1773 #define CTL_REGS_HCRX_DIG_RESET_HCRX_LFCK_RSTB_MASK 0x0040 1774 #define CTL_REGS_HCRX_DIG_RESET_HCRX_LFCK_RSTB_ALIGN 0 1775 #define CTL_REGS_HCRX_DIG_RESET_HCRX_LFCK_RSTB_BITS 1 1776 #define CTL_REGS_HCRX_DIG_RESET_HCRX_LFCK_RSTB_SHIFT 6 1777 1778 /* ctl_regs :: hcrx_dig_reset :: hcrx_dig_rstb [05:00] */ 1779 #define CTL_REGS_HCRX_DIG_RESET_HCRX_DIG_RSTB_MASK 0x003f 1780 #define CTL_REGS_HCRX_DIG_RESET_HCRX_DIG_RSTB_ALIGN 0 1781 #define CTL_REGS_HCRX_DIG_RESET_HCRX_DIG_RSTB_BITS 6 1782 #define CTL_REGS_HCRX_DIG_RESET_HCRX_DIG_RSTB_SHIFT 0 1783 1784 1785 /**************************************************************************** 1786 * ctl_regs :: frc_hcrx_mdio_reset 1787 */ 1788 /* ctl_regs :: frc_hcrx_mdio_reset :: reserved0 [15:06] */ 1789 #define CTL_REGS_FRC_HCRX_MDIO_RESET_RESERVED0_MASK 0xffc0 1790 #define CTL_REGS_FRC_HCRX_MDIO_RESET_RESERVED0_ALIGN 0 1791 #define CTL_REGS_FRC_HCRX_MDIO_RESET_RESERVED0_BITS 10 1792 #define CTL_REGS_FRC_HCRX_MDIO_RESET_RESERVED0_SHIFT 6 1793 1794 /* ctl_regs :: frc_hcrx_mdio_reset :: frc_hcrx_mdio_rstb [05:00] */ 1795 #define CTL_REGS_FRC_HCRX_MDIO_RESET_FRC_HCRX_MDIO_RSTB_MASK 0x003f 1796 #define CTL_REGS_FRC_HCRX_MDIO_RESET_FRC_HCRX_MDIO_RSTB_ALIGN 0 1797 #define CTL_REGS_FRC_HCRX_MDIO_RESET_FRC_HCRX_MDIO_RSTB_BITS 6 1798 #define CTL_REGS_FRC_HCRX_MDIO_RESET_FRC_HCRX_MDIO_RSTB_SHIFT 0 1799 1800 1801 /**************************************************************************** 1802 * ctl_regs :: hcrx_mdio_reset 1803 */ 1804 /* ctl_regs :: hcrx_mdio_reset :: reserved0 [15:06] */ 1805 #define CTL_REGS_HCRX_MDIO_RESET_RESERVED0_MASK 0xffc0 1806 #define CTL_REGS_HCRX_MDIO_RESET_RESERVED0_ALIGN 0 1807 #define CTL_REGS_HCRX_MDIO_RESET_RESERVED0_BITS 10 1808 #define CTL_REGS_HCRX_MDIO_RESET_RESERVED0_SHIFT 6 1809 1810 /* ctl_regs :: hcrx_mdio_reset :: hcrx_mdio_rstb [05:00] */ 1811 #define CTL_REGS_HCRX_MDIO_RESET_HCRX_MDIO_RSTB_MASK 0x003f 1812 #define CTL_REGS_HCRX_MDIO_RESET_HCRX_MDIO_RSTB_ALIGN 0 1813 #define CTL_REGS_HCRX_MDIO_RESET_HCRX_MDIO_RSTB_BITS 6 1814 #define CTL_REGS_HCRX_MDIO_RESET_HCRX_MDIO_RSTB_SHIFT 0 1815 1816 1817 /**************************************************************************** 1818 * ctl_regs :: frc_dcrx_pd 1819 */ 1820 /* ctl_regs :: frc_dcrx_pd :: reserved0 [15:10] */ 1821 #define CTL_REGS_FRC_DCRX_PD_RESERVED0_MASK 0xfc00 1822 #define CTL_REGS_FRC_DCRX_PD_RESERVED0_ALIGN 0 1823 #define CTL_REGS_FRC_DCRX_PD_RESERVED0_BITS 6 1824 #define CTL_REGS_FRC_DCRX_PD_RESERVED0_SHIFT 10 1825 1826 /* ctl_regs :: frc_dcrx_pd :: frc_dcrx_pwrdn [09:00] */ 1827 #define CTL_REGS_FRC_DCRX_PD_FRC_DCRX_PWRDN_MASK 0x03ff 1828 #define CTL_REGS_FRC_DCRX_PD_FRC_DCRX_PWRDN_ALIGN 0 1829 #define CTL_REGS_FRC_DCRX_PD_FRC_DCRX_PWRDN_BITS 10 1830 #define CTL_REGS_FRC_DCRX_PD_FRC_DCRX_PWRDN_SHIFT 0 1831 1832 1833 /**************************************************************************** 1834 * ctl_regs :: dcrx_pd 1835 */ 1836 /* ctl_regs :: dcrx_pd :: reserved0 [15:10] */ 1837 #define CTL_REGS_DCRX_PD_RESERVED0_MASK 0xfc00 1838 #define CTL_REGS_DCRX_PD_RESERVED0_ALIGN 0 1839 #define CTL_REGS_DCRX_PD_RESERVED0_BITS 6 1840 #define CTL_REGS_DCRX_PD_RESERVED0_SHIFT 10 1841 1842 /* ctl_regs :: dcrx_pd :: dcrx_pwrdn [09:00] */ 1843 #define CTL_REGS_DCRX_PD_DCRX_PWRDN_MASK 0x03ff 1844 #define CTL_REGS_DCRX_PD_DCRX_PWRDN_ALIGN 0 1845 #define CTL_REGS_DCRX_PD_DCRX_PWRDN_BITS 10 1846 #define CTL_REGS_DCRX_PD_DCRX_PWRDN_SHIFT 0 1847 1848 1849 /**************************************************************************** 1850 * ctl_regs :: frc_dctx_pd 1851 */ 1852 /* ctl_regs :: frc_dctx_pd :: reserved0 [15:11] */ 1853 #define CTL_REGS_FRC_DCTX_PD_RESERVED0_MASK 0xf800 1854 #define CTL_REGS_FRC_DCTX_PD_RESERVED0_ALIGN 0 1855 #define CTL_REGS_FRC_DCTX_PD_RESERVED0_BITS 5 1856 #define CTL_REGS_FRC_DCTX_PD_RESERVED0_SHIFT 11 1857 1858 /* ctl_regs :: frc_dctx_pd :: frc_dc_pll_pwrdn [10:10] */ 1859 #define CTL_REGS_FRC_DCTX_PD_FRC_DC_PLL_PWRDN_MASK 0x0400 1860 #define CTL_REGS_FRC_DCTX_PD_FRC_DC_PLL_PWRDN_ALIGN 0 1861 #define CTL_REGS_FRC_DCTX_PD_FRC_DC_PLL_PWRDN_BITS 1 1862 #define CTL_REGS_FRC_DCTX_PD_FRC_DC_PLL_PWRDN_SHIFT 10 1863 1864 /* ctl_regs :: frc_dctx_pd :: frc_dctx_pwrdn [09:00] */ 1865 #define CTL_REGS_FRC_DCTX_PD_FRC_DCTX_PWRDN_MASK 0x03ff 1866 #define CTL_REGS_FRC_DCTX_PD_FRC_DCTX_PWRDN_ALIGN 0 1867 #define CTL_REGS_FRC_DCTX_PD_FRC_DCTX_PWRDN_BITS 10 1868 #define CTL_REGS_FRC_DCTX_PD_FRC_DCTX_PWRDN_SHIFT 0 1869 1870 1871 /**************************************************************************** 1872 * ctl_regs :: dctx_pd 1873 */ 1874 /* ctl_regs :: dctx_pd :: reserved0 [15:11] */ 1875 #define CTL_REGS_DCTX_PD_RESERVED0_MASK 0xf800 1876 #define CTL_REGS_DCTX_PD_RESERVED0_ALIGN 0 1877 #define CTL_REGS_DCTX_PD_RESERVED0_BITS 5 1878 #define CTL_REGS_DCTX_PD_RESERVED0_SHIFT 11 1879 1880 /* ctl_regs :: dctx_pd :: dc_pll_pwrdn [10:10] */ 1881 #define CTL_REGS_DCTX_PD_DC_PLL_PWRDN_MASK 0x0400 1882 #define CTL_REGS_DCTX_PD_DC_PLL_PWRDN_ALIGN 0 1883 #define CTL_REGS_DCTX_PD_DC_PLL_PWRDN_BITS 1 1884 #define CTL_REGS_DCTX_PD_DC_PLL_PWRDN_SHIFT 10 1885 1886 /* ctl_regs :: dctx_pd :: dctx_pwrdn [09:00] */ 1887 #define CTL_REGS_DCTX_PD_DCTX_PWRDN_MASK 0x03ff 1888 #define CTL_REGS_DCTX_PD_DCTX_PWRDN_ALIGN 0 1889 #define CTL_REGS_DCTX_PD_DCTX_PWRDN_BITS 10 1890 #define CTL_REGS_DCTX_PD_DCTX_PWRDN_SHIFT 0 1891 1892 1893 /**************************************************************************** 1894 * ctl_regs :: frc_hcrx_pd 1895 */ 1896 /* ctl_regs :: frc_hcrx_pd :: reserved0 [15:06] */ 1897 #define CTL_REGS_FRC_HCRX_PD_RESERVED0_MASK 0xffc0 1898 #define CTL_REGS_FRC_HCRX_PD_RESERVED0_ALIGN 0 1899 #define CTL_REGS_FRC_HCRX_PD_RESERVED0_BITS 10 1900 #define CTL_REGS_FRC_HCRX_PD_RESERVED0_SHIFT 6 1901 1902 /* ctl_regs :: frc_hcrx_pd :: frc_hcrx_pwrdn [05:00] */ 1903 #define CTL_REGS_FRC_HCRX_PD_FRC_HCRX_PWRDN_MASK 0x003f 1904 #define CTL_REGS_FRC_HCRX_PD_FRC_HCRX_PWRDN_ALIGN 0 1905 #define CTL_REGS_FRC_HCRX_PD_FRC_HCRX_PWRDN_BITS 6 1906 #define CTL_REGS_FRC_HCRX_PD_FRC_HCRX_PWRDN_SHIFT 0 1907 1908 1909 /**************************************************************************** 1910 * ctl_regs :: hcrx_pd 1911 */ 1912 /* ctl_regs :: hcrx_pd :: reserved0 [15:06] */ 1913 #define CTL_REGS_HCRX_PD_RESERVED0_MASK 0xffc0 1914 #define CTL_REGS_HCRX_PD_RESERVED0_ALIGN 0 1915 #define CTL_REGS_HCRX_PD_RESERVED0_BITS 10 1916 #define CTL_REGS_HCRX_PD_RESERVED0_SHIFT 6 1917 1918 /* ctl_regs :: hcrx_pd :: hcrx_pwrdn [05:00] */ 1919 #define CTL_REGS_HCRX_PD_HCRX_PWRDN_MASK 0x003f 1920 #define CTL_REGS_HCRX_PD_HCRX_PWRDN_ALIGN 0 1921 #define CTL_REGS_HCRX_PD_HCRX_PWRDN_BITS 6 1922 #define CTL_REGS_HCRX_PD_HCRX_PWRDN_SHIFT 0 1923 1924 1925 /**************************************************************************** 1926 * ctl_regs :: frc_hctx_pd 1927 */ 1928 /* ctl_regs :: frc_hctx_pd :: reserved0 [15:06] */ 1929 #define CTL_REGS_FRC_HCTX_PD_RESERVED0_MASK 0xffc0 1930 #define CTL_REGS_FRC_HCTX_PD_RESERVED0_ALIGN 0 1931 #define CTL_REGS_FRC_HCTX_PD_RESERVED0_BITS 10 1932 #define CTL_REGS_FRC_HCTX_PD_RESERVED0_SHIFT 6 1933 1934 /* ctl_regs :: frc_hctx_pd :: frc_hctx_pwrdn [05:00] */ 1935 #define CTL_REGS_FRC_HCTX_PD_FRC_HCTX_PWRDN_MASK 0x003f 1936 #define CTL_REGS_FRC_HCTX_PD_FRC_HCTX_PWRDN_ALIGN 0 1937 #define CTL_REGS_FRC_HCTX_PD_FRC_HCTX_PWRDN_BITS 6 1938 #define CTL_REGS_FRC_HCTX_PD_FRC_HCTX_PWRDN_SHIFT 0 1939 1940 1941 /**************************************************************************** 1942 * ctl_regs :: hctx_pd 1943 */ 1944 /* ctl_regs :: hctx_pd :: reserved0 [15:06] */ 1945 #define CTL_REGS_HCTX_PD_RESERVED0_MASK 0xffc0 1946 #define CTL_REGS_HCTX_PD_RESERVED0_ALIGN 0 1947 #define CTL_REGS_HCTX_PD_RESERVED0_BITS 10 1948 #define CTL_REGS_HCTX_PD_RESERVED0_SHIFT 6 1949 1950 /* ctl_regs :: hctx_pd :: hctx_pwrdn [05:00] */ 1951 #define CTL_REGS_HCTX_PD_HCTX_PWRDN_MASK 0x003f 1952 #define CTL_REGS_HCTX_PD_HCTX_PWRDN_ALIGN 0 1953 #define CTL_REGS_HCTX_PD_HCTX_PWRDN_BITS 6 1954 #define CTL_REGS_HCTX_PD_HCTX_PWRDN_SHIFT 0 1955 1956 1957 /**************************************************************************** 1958 * ctl_regs :: frc_vsr40_tx_pd 1959 */ 1960 /* ctl_regs :: frc_vsr40_tx_pd :: reserved0 [15:04] */ 1961 #define CTL_REGS_FRC_VSR40_TX_PD_RESERVED0_MASK 0xfff0 1962 #define CTL_REGS_FRC_VSR40_TX_PD_RESERVED0_ALIGN 0 1963 #define CTL_REGS_FRC_VSR40_TX_PD_RESERVED0_BITS 12 1964 #define CTL_REGS_FRC_VSR40_TX_PD_RESERVED0_SHIFT 4 1965 1966 /* ctl_regs :: frc_vsr40_tx_pd :: frc_vsr40_tx_pwrdn [03:00] */ 1967 #define CTL_REGS_FRC_VSR40_TX_PD_FRC_VSR40_TX_PWRDN_MASK 0x000f 1968 #define CTL_REGS_FRC_VSR40_TX_PD_FRC_VSR40_TX_PWRDN_ALIGN 0 1969 #define CTL_REGS_FRC_VSR40_TX_PD_FRC_VSR40_TX_PWRDN_BITS 4 1970 #define CTL_REGS_FRC_VSR40_TX_PD_FRC_VSR40_TX_PWRDN_SHIFT 0 1971 1972 1973 /**************************************************************************** 1974 * ctl_regs :: vsr40_tx_pd 1975 */ 1976 /* ctl_regs :: vsr40_tx_pd :: reserved0 [15:04] */ 1977 #define CTL_REGS_VSR40_TX_PD_RESERVED0_MASK 0xfff0 1978 #define CTL_REGS_VSR40_TX_PD_RESERVED0_ALIGN 0 1979 #define CTL_REGS_VSR40_TX_PD_RESERVED0_BITS 12 1980 #define CTL_REGS_VSR40_TX_PD_RESERVED0_SHIFT 4 1981 1982 /* ctl_regs :: vsr40_tx_pd :: vsr40_tx_pwrdn [03:00] */ 1983 #define CTL_REGS_VSR40_TX_PD_VSR40_TX_PWRDN_MASK 0x000f 1984 #define CTL_REGS_VSR40_TX_PD_VSR40_TX_PWRDN_ALIGN 0 1985 #define CTL_REGS_VSR40_TX_PD_VSR40_TX_PWRDN_BITS 4 1986 #define CTL_REGS_VSR40_TX_PD_VSR40_TX_PWRDN_SHIFT 0 1987 1988 1989 /**************************************************************************** 1990 * ctl_regs :: frc_vsr40_rx_pd 1991 */ 1992 /* ctl_regs :: frc_vsr40_rx_pd :: reserved0 [15:04] */ 1993 #define CTL_REGS_FRC_VSR40_RX_PD_RESERVED0_MASK 0xfff0 1994 #define CTL_REGS_FRC_VSR40_RX_PD_RESERVED0_ALIGN 0 1995 #define CTL_REGS_FRC_VSR40_RX_PD_RESERVED0_BITS 12 1996 #define CTL_REGS_FRC_VSR40_RX_PD_RESERVED0_SHIFT 4 1997 1998 /* ctl_regs :: frc_vsr40_rx_pd :: frc_vsr40_rx_pwrdn [03:00] */ 1999 #define CTL_REGS_FRC_VSR40_RX_PD_FRC_VSR40_RX_PWRDN_MASK 0x000f 2000 #define CTL_REGS_FRC_VSR40_RX_PD_FRC_VSR40_RX_PWRDN_ALIGN 0 2001 #define CTL_REGS_FRC_VSR40_RX_PD_FRC_VSR40_RX_PWRDN_BITS 4 2002 #define CTL_REGS_FRC_VSR40_RX_PD_FRC_VSR40_RX_PWRDN_SHIFT 0 2003 2004 2005 /**************************************************************************** 2006 * ctl_regs :: vsr40_rx_pd 2007 */ 2008 /* ctl_regs :: vsr40_rx_pd :: reserved0 [15:04] */ 2009 #define CTL_REGS_VSR40_RX_PD_RESERVED0_MASK 0xfff0 2010 #define CTL_REGS_VSR40_RX_PD_RESERVED0_ALIGN 0 2011 #define CTL_REGS_VSR40_RX_PD_RESERVED0_BITS 12 2012 #define CTL_REGS_VSR40_RX_PD_RESERVED0_SHIFT 4 2013 2014 /* ctl_regs :: vsr40_rx_pd :: vsr40_rx_pwrdn [03:00] */ 2015 #define CTL_REGS_VSR40_RX_PD_VSR40_RX_PWRDN_MASK 0x000f 2016 #define CTL_REGS_VSR40_RX_PD_VSR40_RX_PWRDN_ALIGN 0 2017 #define CTL_REGS_VSR40_RX_PD_VSR40_RX_PWRDN_BITS 4 2018 #define CTL_REGS_VSR40_RX_PD_VSR40_RX_PWRDN_SHIFT 0 2019 2020 2021 /**************************************************************************** 2022 * ctl_regs :: pcb_ctrl_type 2023 */ 2024 /* ctl_regs :: pcb_ctrl_type :: reserved0 [15:06] */ 2025 #define CTL_REGS_PCB_CTRL_TYPE_RESERVED0_MASK 0xffc0 2026 #define CTL_REGS_PCB_CTRL_TYPE_RESERVED0_ALIGN 0 2027 #define CTL_REGS_PCB_CTRL_TYPE_RESERVED0_BITS 10 2028 #define CTL_REGS_PCB_CTRL_TYPE_RESERVED0_SHIFT 6 2029 2030 /* ctl_regs :: pcb_ctrl_type :: pcb_clear [05:05] */ 2031 #define CTL_REGS_PCB_CTRL_TYPE_PCB_CLEAR_MASK 0x0020 2032 #define CTL_REGS_PCB_CTRL_TYPE_PCB_CLEAR_ALIGN 0 2033 #define CTL_REGS_PCB_CTRL_TYPE_PCB_CLEAR_BITS 1 2034 #define CTL_REGS_PCB_CTRL_TYPE_PCB_CLEAR_SHIFT 5 2035 2036 /* ctl_regs :: pcb_ctrl_type :: pcb_rd [04:04] */ 2037 #define CTL_REGS_PCB_CTRL_TYPE_PCB_RD_MASK 0x0010 2038 #define CTL_REGS_PCB_CTRL_TYPE_PCB_RD_ALIGN 0 2039 #define CTL_REGS_PCB_CTRL_TYPE_PCB_RD_BITS 1 2040 #define CTL_REGS_PCB_CTRL_TYPE_PCB_RD_SHIFT 4 2041 2042 /* ctl_regs :: pcb_ctrl_type :: pcb_wr [03:03] */ 2043 #define CTL_REGS_PCB_CTRL_TYPE_PCB_WR_MASK 0x0008 2044 #define CTL_REGS_PCB_CTRL_TYPE_PCB_WR_ALIGN 0 2045 #define CTL_REGS_PCB_CTRL_TYPE_PCB_WR_BITS 1 2046 #define CTL_REGS_PCB_CTRL_TYPE_PCB_WR_SHIFT 3 2047 2048 /* ctl_regs :: pcb_ctrl_type :: hctx_pcb_en [02:02] */ 2049 #define CTL_REGS_PCB_CTRL_TYPE_HCTX_PCB_EN_MASK 0x0004 2050 #define CTL_REGS_PCB_CTRL_TYPE_HCTX_PCB_EN_ALIGN 0 2051 #define CTL_REGS_PCB_CTRL_TYPE_HCTX_PCB_EN_BITS 1 2052 #define CTL_REGS_PCB_CTRL_TYPE_HCTX_PCB_EN_SHIFT 2 2053 2054 /* ctl_regs :: pcb_ctrl_type :: hcrx_pcb_en [01:01] */ 2055 #define CTL_REGS_PCB_CTRL_TYPE_HCRX_PCB_EN_MASK 0x0002 2056 #define CTL_REGS_PCB_CTRL_TYPE_HCRX_PCB_EN_ALIGN 0 2057 #define CTL_REGS_PCB_CTRL_TYPE_HCRX_PCB_EN_BITS 1 2058 #define CTL_REGS_PCB_CTRL_TYPE_HCRX_PCB_EN_SHIFT 1 2059 2060 /* ctl_regs :: pcb_ctrl_type :: dc_pcb_en [00:00] */ 2061 #define CTL_REGS_PCB_CTRL_TYPE_DC_PCB_EN_MASK 0x0001 2062 #define CTL_REGS_PCB_CTRL_TYPE_DC_PCB_EN_ALIGN 0 2063 #define CTL_REGS_PCB_CTRL_TYPE_DC_PCB_EN_BITS 1 2064 #define CTL_REGS_PCB_CTRL_TYPE_DC_PCB_EN_SHIFT 0 2065 2066 2067 /**************************************************************************** 2068 * ctl_regs :: pcb_adr_msw_type 2069 */ 2070 /* ctl_regs :: pcb_adr_msw_type :: pcb_adr_msw [15:00] */ 2071 #define CTL_REGS_PCB_ADR_MSW_TYPE_PCB_ADR_MSW_MASK 0xffff 2072 #define CTL_REGS_PCB_ADR_MSW_TYPE_PCB_ADR_MSW_ALIGN 0 2073 #define CTL_REGS_PCB_ADR_MSW_TYPE_PCB_ADR_MSW_BITS 16 2074 #define CTL_REGS_PCB_ADR_MSW_TYPE_PCB_ADR_MSW_SHIFT 0 2075 2076 2077 /**************************************************************************** 2078 * ctl_regs :: pcb_adr_lsw_type 2079 */ 2080 /* ctl_regs :: pcb_adr_lsw_type :: pcb_adr_lsw [15:00] */ 2081 #define CTL_REGS_PCB_ADR_LSW_TYPE_PCB_ADR_LSW_MASK 0xffff 2082 #define CTL_REGS_PCB_ADR_LSW_TYPE_PCB_ADR_LSW_ALIGN 0 2083 #define CTL_REGS_PCB_ADR_LSW_TYPE_PCB_ADR_LSW_BITS 16 2084 #define CTL_REGS_PCB_ADR_LSW_TYPE_PCB_ADR_LSW_SHIFT 0 2085 2086 2087 /**************************************************************************** 2088 * ctl_regs :: pcb_data_in_type 2089 */ 2090 /* ctl_regs :: pcb_data_in_type :: pcb_data_in [15:00] */ 2091 #define CTL_REGS_PCB_DATA_IN_TYPE_PCB_DATA_IN_MASK 0xffff 2092 #define CTL_REGS_PCB_DATA_IN_TYPE_PCB_DATA_IN_ALIGN 0 2093 #define CTL_REGS_PCB_DATA_IN_TYPE_PCB_DATA_IN_BITS 16 2094 #define CTL_REGS_PCB_DATA_IN_TYPE_PCB_DATA_IN_SHIFT 0 2095 2096 2097 /**************************************************************************** 2098 * ctl_regs :: pcb_data_out_type 2099 */ 2100 /* ctl_regs :: pcb_data_out_type :: pcb_data_out [15:00] */ 2101 #define CTL_REGS_PCB_DATA_OUT_TYPE_PCB_DATA_OUT_MASK 0xffff 2102 #define CTL_REGS_PCB_DATA_OUT_TYPE_PCB_DATA_OUT_ALIGN 0 2103 #define CTL_REGS_PCB_DATA_OUT_TYPE_PCB_DATA_OUT_BITS 16 2104 #define CTL_REGS_PCB_DATA_OUT_TYPE_PCB_DATA_OUT_SHIFT 0 2105 2106 2107 /**************************************************************************** 2108 * ctl_regs :: sys_loopback_en 2109 */ 2110 /* ctl_regs :: sys_loopback_en :: reserved0 [15:10] */ 2111 #define CTL_REGS_SYS_LOOPBACK_EN_RESERVED0_MASK 0xfc00 2112 #define CTL_REGS_SYS_LOOPBACK_EN_RESERVED0_ALIGN 0 2113 #define CTL_REGS_SYS_LOOPBACK_EN_RESERVED0_BITS 6 2114 #define CTL_REGS_SYS_LOOPBACK_EN_RESERVED0_SHIFT 10 2115 2116 /* ctl_regs :: sys_loopback_en :: sys_lpbk_en [09:00] */ 2117 #define CTL_REGS_SYS_LOOPBACK_EN_SYS_LPBK_EN_MASK 0x03ff 2118 #define CTL_REGS_SYS_LOOPBACK_EN_SYS_LPBK_EN_ALIGN 0 2119 #define CTL_REGS_SYS_LOOPBACK_EN_SYS_LPBK_EN_BITS 10 2120 #define CTL_REGS_SYS_LOOPBACK_EN_SYS_LPBK_EN_SHIFT 0 2121 2122 2123 /**************************************************************************** 2124 * ctl_regs :: line_loopback_en 2125 */ 2126 /* ctl_regs :: line_loopback_en :: reserved0 [15:10] */ 2127 #define CTL_REGS_LINE_LOOPBACK_EN_RESERVED0_MASK 0xfc00 2128 #define CTL_REGS_LINE_LOOPBACK_EN_RESERVED0_ALIGN 0 2129 #define CTL_REGS_LINE_LOOPBACK_EN_RESERVED0_BITS 6 2130 #define CTL_REGS_LINE_LOOPBACK_EN_RESERVED0_SHIFT 10 2131 2132 /* ctl_regs :: line_loopback_en :: line_lpbk_en [09:00] */ 2133 #define CTL_REGS_LINE_LOOPBACK_EN_LINE_LPBK_EN_MASK 0x03ff 2134 #define CTL_REGS_LINE_LOOPBACK_EN_LINE_LPBK_EN_ALIGN 0 2135 #define CTL_REGS_LINE_LOOPBACK_EN_LINE_LPBK_EN_BITS 10 2136 #define CTL_REGS_LINE_LOOPBACK_EN_LINE_LPBK_EN_SHIFT 0 2137 2138 2139 /**************************************************************************** 2140 * ctl_regs :: pvtmon_ctrl1 2141 */ 2142 /* ctl_regs :: pvtmon_ctrl1 :: reserved0 [15:13] */ 2143 #define CTL_REGS_PVTMON_CTRL1_RESERVED0_MASK 0xe000 2144 #define CTL_REGS_PVTMON_CTRL1_RESERVED0_ALIGN 0 2145 #define CTL_REGS_PVTMON_CTRL1_RESERVED0_BITS 3 2146 #define CTL_REGS_PVTMON_CTRL1_RESERVED0_SHIFT 13 2147 2148 /* ctl_regs :: pvtmon_ctrl1 :: pvtmon_freq_output [12:12] */ 2149 #define CTL_REGS_PVTMON_CTRL1_PVTMON_FREQ_OUTPUT_MASK 0x1000 2150 #define CTL_REGS_PVTMON_CTRL1_PVTMON_FREQ_OUTPUT_ALIGN 0 2151 #define CTL_REGS_PVTMON_CTRL1_PVTMON_FREQ_OUTPUT_BITS 1 2152 #define CTL_REGS_PVTMON_CTRL1_PVTMON_FREQ_OUTPUT_SHIFT 12 2153 2154 /* ctl_regs :: pvtmon_ctrl1 :: i_IDOFFMON_pwrdn [11:11] */ 2155 #define CTL_REGS_PVTMON_CTRL1_I_IDOFFMON_PWRDN_MASK 0x0800 2156 #define CTL_REGS_PVTMON_CTRL1_I_IDOFFMON_PWRDN_ALIGN 0 2157 #define CTL_REGS_PVTMON_CTRL1_I_IDOFFMON_PWRDN_BITS 1 2158 #define CTL_REGS_PVTMON_CTRL1_I_IDOFFMON_PWRDN_SHIFT 11 2159 2160 /* ctl_regs :: pvtmon_ctrl1 :: reserved1 [10:06] */ 2161 #define CTL_REGS_PVTMON_CTRL1_RESERVED1_MASK 0x07c0 2162 #define CTL_REGS_PVTMON_CTRL1_RESERVED1_ALIGN 0 2163 #define CTL_REGS_PVTMON_CTRL1_RESERVED1_BITS 5 2164 #define CTL_REGS_PVTMON_CTRL1_RESERVED1_SHIFT 6 2165 2166 /* ctl_regs :: pvtmon_ctrl1 :: i_PVTMON_pwrdn [05:05] */ 2167 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_PWRDN_MASK 0x0020 2168 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_PWRDN_ALIGN 0 2169 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_PWRDN_BITS 1 2170 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_PWRDN_SHIFT 5 2171 2172 /* ctl_regs :: pvtmon_ctrl1 :: i_PVTMON_resetb [04:04] */ 2173 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_RESETB_MASK 0x0010 2174 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_RESETB_ALIGN 0 2175 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_RESETB_BITS 1 2176 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_RESETB_SHIFT 4 2177 2178 /* ctl_regs :: pvtmon_ctrl1 :: i_PVTMON_reg_en [03:03] */ 2179 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_REG_EN_MASK 0x0008 2180 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_REG_EN_ALIGN 0 2181 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_REG_EN_BITS 1 2182 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_REG_EN_SHIFT 3 2183 2184 /* ctl_regs :: pvtmon_ctrl1 :: i_PVTMON_sel [02:00] */ 2185 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_SEL_MASK 0x0007 2186 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_SEL_ALIGN 0 2187 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_SEL_BITS 3 2188 #define CTL_REGS_PVTMON_CTRL1_I_PVTMON_SEL_SHIFT 0 2189 2190 2191 /**************************************************************************** 2192 * ctl_regs :: pvtmon_ctrl2 2193 */ 2194 /* ctl_regs :: pvtmon_ctrl2 :: reserved0 [15:10] */ 2195 #define CTL_REGS_PVTMON_CTRL2_RESERVED0_MASK 0xfc00 2196 #define CTL_REGS_PVTMON_CTRL2_RESERVED0_ALIGN 0 2197 #define CTL_REGS_PVTMON_CTRL2_RESERVED0_BITS 6 2198 #define CTL_REGS_PVTMON_CTRL2_RESERVED0_SHIFT 10 2199 2200 /* ctl_regs :: pvtmon_ctrl2 :: i_PVTMON_vdac [09:00] */ 2201 #define CTL_REGS_PVTMON_CTRL2_I_PVTMON_VDAC_MASK 0x03ff 2202 #define CTL_REGS_PVTMON_CTRL2_I_PVTMON_VDAC_ALIGN 0 2203 #define CTL_REGS_PVTMON_CTRL2_I_PVTMON_VDAC_BITS 10 2204 #define CTL_REGS_PVTMON_CTRL2_I_PVTMON_VDAC_SHIFT 0 2205 2206 2207 /**************************************************************************** 2208 * ctl_regs :: pvtmon_ctrl3 2209 */ 2210 /* ctl_regs :: pvtmon_ctrl3 :: i_PVTMON_ctrl_15_0 [15:00] */ 2211 #define CTL_REGS_PVTMON_CTRL3_I_PVTMON_CTRL_15_0_MASK 0xffff 2212 #define CTL_REGS_PVTMON_CTRL3_I_PVTMON_CTRL_15_0_ALIGN 0 2213 #define CTL_REGS_PVTMON_CTRL3_I_PVTMON_CTRL_15_0_BITS 16 2214 #define CTL_REGS_PVTMON_CTRL3_I_PVTMON_CTRL_15_0_SHIFT 0 2215 2216 2217 /**************************************************************************** 2218 * ctl_regs :: pvtmon_ctrl4 2219 */ 2220 /* ctl_regs :: pvtmon_ctrl4 :: i_PVTMON_ctrl_31_16 [15:00] */ 2221 #define CTL_REGS_PVTMON_CTRL4_I_PVTMON_CTRL_31_16_MASK 0xffff 2222 #define CTL_REGS_PVTMON_CTRL4_I_PVTMON_CTRL_31_16_ALIGN 0 2223 #define CTL_REGS_PVTMON_CTRL4_I_PVTMON_CTRL_31_16_BITS 16 2224 #define CTL_REGS_PVTMON_CTRL4_I_PVTMON_CTRL_31_16_SHIFT 0 2225 2226 2227 /**************************************************************************** 2228 * ctl_regs :: pvtmon_status 2229 */ 2230 /* ctl_regs :: pvtmon_status :: reserved_for_eco0 [15:10] */ 2231 #define CTL_REGS_PVTMON_STATUS_RESERVED_FOR_ECO0_MASK 0xfc00 2232 #define CTL_REGS_PVTMON_STATUS_RESERVED_FOR_ECO0_ALIGN 0 2233 #define CTL_REGS_PVTMON_STATUS_RESERVED_FOR_ECO0_BITS 6 2234 #define CTL_REGS_PVTMON_STATUS_RESERVED_FOR_ECO0_SHIFT 10 2235 2236 /* ctl_regs :: pvtmon_status :: o_PVTMON_data [09:00] */ 2237 #define CTL_REGS_PVTMON_STATUS_O_PVTMON_DATA_MASK 0x03ff 2238 #define CTL_REGS_PVTMON_STATUS_O_PVTMON_DATA_ALIGN 0 2239 #define CTL_REGS_PVTMON_STATUS_O_PVTMON_DATA_BITS 10 2240 #define CTL_REGS_PVTMON_STATUS_O_PVTMON_DATA_SHIFT 0 2241 2242 2243 /**************************************************************************** 2244 * ctl_regs :: rescal_ctrl 2245 */ 2246 /* ctl_regs :: rescal_ctrl :: reserved0 [15:09] */ 2247 #define CTL_REGS_RESCAL_CTRL_RESERVED0_MASK 0xfe00 2248 #define CTL_REGS_RESCAL_CTRL_RESERVED0_ALIGN 0 2249 #define CTL_REGS_RESCAL_CTRL_RESERVED0_BITS 7 2250 #define CTL_REGS_RESCAL_CTRL_RESERVED0_SHIFT 9 2251 2252 /* ctl_regs :: rescal_ctrl :: rescal_done_frcval [08:08] */ 2253 #define CTL_REGS_RESCAL_CTRL_RESCAL_DONE_FRCVAL_MASK 0x0100 2254 #define CTL_REGS_RESCAL_CTRL_RESCAL_DONE_FRCVAL_ALIGN 0 2255 #define CTL_REGS_RESCAL_CTRL_RESCAL_DONE_FRCVAL_BITS 1 2256 #define CTL_REGS_RESCAL_CTRL_RESCAL_DONE_FRCVAL_SHIFT 8 2257 2258 /* ctl_regs :: rescal_ctrl :: rescal_done_frc [07:07] */ 2259 #define CTL_REGS_RESCAL_CTRL_RESCAL_DONE_FRC_MASK 0x0080 2260 #define CTL_REGS_RESCAL_CTRL_RESCAL_DONE_FRC_ALIGN 0 2261 #define CTL_REGS_RESCAL_CTRL_RESCAL_DONE_FRC_BITS 1 2262 #define CTL_REGS_RESCAL_CTRL_RESCAL_DONE_FRC_SHIFT 7 2263 2264 /* ctl_regs :: rescal_ctrl :: reserved1 [06:06] */ 2265 #define CTL_REGS_RESCAL_CTRL_RESERVED1_MASK 0x0040 2266 #define CTL_REGS_RESCAL_CTRL_RESERVED1_ALIGN 0 2267 #define CTL_REGS_RESCAL_CTRL_RESERVED1_BITS 1 2268 #define CTL_REGS_RESCAL_CTRL_RESERVED1_SHIFT 6 2269 2270 /* ctl_regs :: rescal_ctrl :: rescal_pon_frcval [05:03] */ 2271 #define CTL_REGS_RESCAL_CTRL_RESCAL_PON_FRCVAL_MASK 0x0038 2272 #define CTL_REGS_RESCAL_CTRL_RESCAL_PON_FRCVAL_ALIGN 0 2273 #define CTL_REGS_RESCAL_CTRL_RESCAL_PON_FRCVAL_BITS 3 2274 #define CTL_REGS_RESCAL_CTRL_RESCAL_PON_FRCVAL_SHIFT 3 2275 2276 /* ctl_regs :: rescal_ctrl :: rescal_pon_frc [02:02] */ 2277 #define CTL_REGS_RESCAL_CTRL_RESCAL_PON_FRC_MASK 0x0004 2278 #define CTL_REGS_RESCAL_CTRL_RESCAL_PON_FRC_ALIGN 0 2279 #define CTL_REGS_RESCAL_CTRL_RESCAL_PON_FRC_BITS 1 2280 #define CTL_REGS_RESCAL_CTRL_RESCAL_PON_FRC_SHIFT 2 2281 2282 /* ctl_regs :: rescal_ctrl :: rescal_pwrdn [01:01] */ 2283 #define CTL_REGS_RESCAL_CTRL_RESCAL_PWRDN_MASK 0x0002 2284 #define CTL_REGS_RESCAL_CTRL_RESCAL_PWRDN_ALIGN 0 2285 #define CTL_REGS_RESCAL_CTRL_RESCAL_PWRDN_BITS 1 2286 #define CTL_REGS_RESCAL_CTRL_RESCAL_PWRDN_SHIFT 1 2287 2288 /* ctl_regs :: rescal_ctrl :: rescal_enable [00:00] */ 2289 #define CTL_REGS_RESCAL_CTRL_RESCAL_ENABLE_MASK 0x0001 2290 #define CTL_REGS_RESCAL_CTRL_RESCAL_ENABLE_ALIGN 0 2291 #define CTL_REGS_RESCAL_CTRL_RESCAL_ENABLE_BITS 1 2292 #define CTL_REGS_RESCAL_CTRL_RESCAL_ENABLE_SHIFT 0 2293 2294 2295 /**************************************************************************** 2296 * ctl_regs :: rescal_status 2297 */ 2298 /* ctl_regs :: rescal_status :: reserved_for_eco0 [15:04] */ 2299 #define CTL_REGS_RESCAL_STATUS_RESERVED_FOR_ECO0_MASK 0xfff0 2300 #define CTL_REGS_RESCAL_STATUS_RESERVED_FOR_ECO0_ALIGN 0 2301 #define CTL_REGS_RESCAL_STATUS_RESERVED_FOR_ECO0_BITS 12 2302 #define CTL_REGS_RESCAL_STATUS_RESERVED_FOR_ECO0_SHIFT 4 2303 2304 /* ctl_regs :: rescal_status :: rescal_pon [03:01] */ 2305 #define CTL_REGS_RESCAL_STATUS_RESCAL_PON_MASK 0x000e 2306 #define CTL_REGS_RESCAL_STATUS_RESCAL_PON_ALIGN 0 2307 #define CTL_REGS_RESCAL_STATUS_RESCAL_PON_BITS 3 2308 #define CTL_REGS_RESCAL_STATUS_RESCAL_PON_SHIFT 1 2309 2310 /* ctl_regs :: rescal_status :: rescal_done [00:00] */ 2311 #define CTL_REGS_RESCAL_STATUS_RESCAL_DONE_MASK 0x0001 2312 #define CTL_REGS_RESCAL_STATUS_RESCAL_DONE_ALIGN 0 2313 #define CTL_REGS_RESCAL_STATUS_RESCAL_DONE_BITS 1 2314 #define CTL_REGS_RESCAL_STATUS_RESCAL_DONE_SHIFT 0 2315 2316 2317 /**************************************************************************** 2318 * ctl_regs :: pad_osc_control 2319 */ 2320 /* ctl_regs :: pad_osc_control :: reserved0 [15:10] */ 2321 #define CTL_REGS_PAD_OSC_CONTROL_RESERVED0_MASK 0xfc00 2322 #define CTL_REGS_PAD_OSC_CONTROL_RESERVED0_ALIGN 0 2323 #define CTL_REGS_PAD_OSC_CONTROL_RESERVED0_BITS 6 2324 #define CTL_REGS_PAD_OSC_CONTROL_RESERVED0_SHIFT 10 2325 2326 /* ctl_regs :: pad_osc_control :: osc_left_output [09:09] */ 2327 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_OUTPUT_MASK 0x0200 2328 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_OUTPUT_ALIGN 0 2329 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_OUTPUT_BITS 1 2330 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_OUTPUT_SHIFT 9 2331 2332 /* ctl_regs :: pad_osc_control :: osc_right_output [08:08] */ 2333 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_OUTPUT_MASK 0x0100 2334 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_OUTPUT_ALIGN 0 2335 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_OUTPUT_BITS 1 2336 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_OUTPUT_SHIFT 8 2337 2338 /* ctl_regs :: pad_osc_control :: osc_right_sel1 [07:07] */ 2339 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_SEL1_MASK 0x0080 2340 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_SEL1_ALIGN 0 2341 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_SEL1_BITS 1 2342 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_SEL1_SHIFT 7 2343 2344 /* ctl_regs :: pad_osc_control :: osc_right_sel0 [06:06] */ 2345 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_SEL0_MASK 0x0040 2346 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_SEL0_ALIGN 0 2347 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_SEL0_BITS 1 2348 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_SEL0_SHIFT 6 2349 2350 /* ctl_regs :: pad_osc_control :: osc_right_enable [05:05] */ 2351 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_ENABLE_MASK 0x0020 2352 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_ENABLE_ALIGN 0 2353 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_ENABLE_BITS 1 2354 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_ENABLE_SHIFT 5 2355 2356 /* ctl_regs :: pad_osc_control :: osc_right_pwenb [04:04] */ 2357 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_PWENB_MASK 0x0010 2358 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_PWENB_ALIGN 0 2359 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_PWENB_BITS 1 2360 #define CTL_REGS_PAD_OSC_CONTROL_OSC_RIGHT_PWENB_SHIFT 4 2361 2362 /* ctl_regs :: pad_osc_control :: osc_left_sel1 [03:03] */ 2363 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_SEL1_MASK 0x0008 2364 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_SEL1_ALIGN 0 2365 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_SEL1_BITS 1 2366 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_SEL1_SHIFT 3 2367 2368 /* ctl_regs :: pad_osc_control :: osc_left_sel0 [02:02] */ 2369 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_SEL0_MASK 0x0004 2370 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_SEL0_ALIGN 0 2371 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_SEL0_BITS 1 2372 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_SEL0_SHIFT 2 2373 2374 /* ctl_regs :: pad_osc_control :: osc_left_enable [01:01] */ 2375 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_ENABLE_MASK 0x0002 2376 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_ENABLE_ALIGN 0 2377 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_ENABLE_BITS 1 2378 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_ENABLE_SHIFT 1 2379 2380 /* ctl_regs :: pad_osc_control :: osc_left_pwenb [00:00] */ 2381 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_PWENB_MASK 0x0001 2382 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_PWENB_ALIGN 0 2383 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_PWENB_BITS 1 2384 #define CTL_REGS_PAD_OSC_CONTROL_OSC_LEFT_PWENB_SHIFT 0 2385 2386 2387 /**************************************************************************** 2388 * ctl_regs :: otp_ctrl_status 2389 */ 2390 /* ctl_regs :: otp_ctrl_status :: reserved0 [15:05] */ 2391 #define CTL_REGS_OTP_CTRL_STATUS_RESERVED0_MASK 0xffe0 2392 #define CTL_REGS_OTP_CTRL_STATUS_RESERVED0_ALIGN 0 2393 #define CTL_REGS_OTP_CTRL_STATUS_RESERVED0_BITS 11 2394 #define CTL_REGS_OTP_CTRL_STATUS_RESERVED0_SHIFT 5 2395 2396 /* ctl_regs :: otp_ctrl_status :: frc_otp_porb [04:04] */ 2397 #define CTL_REGS_OTP_CTRL_STATUS_FRC_OTP_PORB_MASK 0x0010 2398 #define CTL_REGS_OTP_CTRL_STATUS_FRC_OTP_PORB_ALIGN 0 2399 #define CTL_REGS_OTP_CTRL_STATUS_FRC_OTP_PORB_BITS 1 2400 #define CTL_REGS_OTP_CTRL_STATUS_FRC_OTP_PORB_SHIFT 4 2401 2402 /* ctl_regs :: otp_ctrl_status :: otp_porb [03:03] */ 2403 #define CTL_REGS_OTP_CTRL_STATUS_OTP_PORB_MASK 0x0008 2404 #define CTL_REGS_OTP_CTRL_STATUS_OTP_PORB_ALIGN 0 2405 #define CTL_REGS_OTP_CTRL_STATUS_OTP_PORB_BITS 1 2406 #define CTL_REGS_OTP_CTRL_STATUS_OTP_PORB_SHIFT 3 2407 2408 /* ctl_regs :: otp_ctrl_status :: otp_config_done [02:02] */ 2409 #define CTL_REGS_OTP_CTRL_STATUS_OTP_CONFIG_DONE_MASK 0x0004 2410 #define CTL_REGS_OTP_CTRL_STATUS_OTP_CONFIG_DONE_ALIGN 0 2411 #define CTL_REGS_OTP_CTRL_STATUS_OTP_CONFIG_DONE_BITS 1 2412 #define CTL_REGS_OTP_CTRL_STATUS_OTP_CONFIG_DONE_SHIFT 2 2413 2414 /* ctl_regs :: otp_ctrl_status :: otp_ready [01:01] */ 2415 #define CTL_REGS_OTP_CTRL_STATUS_OTP_READY_MASK 0x0002 2416 #define CTL_REGS_OTP_CTRL_STATUS_OTP_READY_ALIGN 0 2417 #define CTL_REGS_OTP_CTRL_STATUS_OTP_READY_BITS 1 2418 #define CTL_REGS_OTP_CTRL_STATUS_OTP_READY_SHIFT 1 2419 2420 /* ctl_regs :: otp_ctrl_status :: otp_sft_reset [00:00] */ 2421 #define CTL_REGS_OTP_CTRL_STATUS_OTP_SFT_RESET_MASK 0x0001 2422 #define CTL_REGS_OTP_CTRL_STATUS_OTP_SFT_RESET_ALIGN 0 2423 #define CTL_REGS_OTP_CTRL_STATUS_OTP_SFT_RESET_BITS 1 2424 #define CTL_REGS_OTP_CTRL_STATUS_OTP_SFT_RESET_SHIFT 0 2425 2426 2427 /**************************************************************************** 2428 * ctl_regs :: vregcntl_type 2429 */ 2430 /* ctl_regs :: vregcntl_type :: reserved0 [15:13] */ 2431 #define CTL_REGS_VREGCNTL_TYPE_RESERVED0_MASK 0xe000 2432 #define CTL_REGS_VREGCNTL_TYPE_RESERVED0_ALIGN 0 2433 #define CTL_REGS_VREGCNTL_TYPE_RESERVED0_BITS 3 2434 #define CTL_REGS_VREGCNTL_TYPE_RESERVED0_SHIFT 13 2435 2436 /* ctl_regs :: vregcntl_type :: o_vregcntl [12:00] */ 2437 #define CTL_REGS_VREGCNTL_TYPE_O_VREGCNTL_MASK 0x1fff 2438 #define CTL_REGS_VREGCNTL_TYPE_O_VREGCNTL_ALIGN 0 2439 #define CTL_REGS_VREGCNTL_TYPE_O_VREGCNTL_BITS 13 2440 #define CTL_REGS_VREGCNTL_TYPE_O_VREGCNTL_SHIFT 0 2441 2442 2443 /**************************************************************************** 2444 * ctl_regs :: frc_line_ln 2445 */ 2446 /* ctl_regs :: frc_line_ln :: reserved0 [15:10] */ 2447 #define CTL_REGS_FRC_LINE_LN_RESERVED0_MASK 0xfc00 2448 #define CTL_REGS_FRC_LINE_LN_RESERVED0_ALIGN 0 2449 #define CTL_REGS_FRC_LINE_LN_RESERVED0_BITS 6 2450 #define CTL_REGS_FRC_LINE_LN_RESERVED0_SHIFT 10 2451 2452 /* ctl_regs :: frc_line_ln :: frc_line_ln_en [09:00] */ 2453 #define CTL_REGS_FRC_LINE_LN_FRC_LINE_LN_EN_MASK 0x03ff 2454 #define CTL_REGS_FRC_LINE_LN_FRC_LINE_LN_EN_ALIGN 0 2455 #define CTL_REGS_FRC_LINE_LN_FRC_LINE_LN_EN_BITS 10 2456 #define CTL_REGS_FRC_LINE_LN_FRC_LINE_LN_EN_SHIFT 0 2457 2458 2459 /**************************************************************************** 2460 * ctl_regs :: line_ln 2461 */ 2462 /* ctl_regs :: line_ln :: reserved0 [15:10] */ 2463 #define CTL_REGS_LINE_LN_RESERVED0_MASK 0xfc00 2464 #define CTL_REGS_LINE_LN_RESERVED0_ALIGN 0 2465 #define CTL_REGS_LINE_LN_RESERVED0_BITS 6 2466 #define CTL_REGS_LINE_LN_RESERVED0_SHIFT 10 2467 2468 /* ctl_regs :: line_ln :: line_ln_en [09:00] */ 2469 #define CTL_REGS_LINE_LN_LINE_LN_EN_MASK 0x03ff 2470 #define CTL_REGS_LINE_LN_LINE_LN_EN_ALIGN 0 2471 #define CTL_REGS_LINE_LN_LINE_LN_EN_BITS 10 2472 #define CTL_REGS_LINE_LN_LINE_LN_EN_SHIFT 0 2473 2474 2475 /**************************************************************************** 2476 * ctl_regs :: frc_sys_ln 2477 */ 2478 /* ctl_regs :: frc_sys_ln :: reserved0 [15:10] */ 2479 #define CTL_REGS_FRC_SYS_LN_RESERVED0_MASK 0xfc00 2480 #define CTL_REGS_FRC_SYS_LN_RESERVED0_ALIGN 0 2481 #define CTL_REGS_FRC_SYS_LN_RESERVED0_BITS 6 2482 #define CTL_REGS_FRC_SYS_LN_RESERVED0_SHIFT 10 2483 2484 /* ctl_regs :: frc_sys_ln :: frc_sys_ln_en [09:00] */ 2485 #define CTL_REGS_FRC_SYS_LN_FRC_SYS_LN_EN_MASK 0x03ff 2486 #define CTL_REGS_FRC_SYS_LN_FRC_SYS_LN_EN_ALIGN 0 2487 #define CTL_REGS_FRC_SYS_LN_FRC_SYS_LN_EN_BITS 10 2488 #define CTL_REGS_FRC_SYS_LN_FRC_SYS_LN_EN_SHIFT 0 2489 2490 2491 /**************************************************************************** 2492 * ctl_regs :: sys_ln 2493 */ 2494 /* ctl_regs :: sys_ln :: reserved0 [15:10] */ 2495 #define CTL_REGS_SYS_LN_RESERVED0_MASK 0xfc00 2496 #define CTL_REGS_SYS_LN_RESERVED0_ALIGN 0 2497 #define CTL_REGS_SYS_LN_RESERVED0_BITS 6 2498 #define CTL_REGS_SYS_LN_RESERVED0_SHIFT 10 2499 2500 /* ctl_regs :: sys_ln :: sys_ln_en [09:00] */ 2501 #define CTL_REGS_SYS_LN_SYS_LN_EN_MASK 0x03ff 2502 #define CTL_REGS_SYS_LN_SYS_LN_EN_ALIGN 0 2503 #define CTL_REGS_SYS_LN_SYS_LN_EN_BITS 10 2504 #define CTL_REGS_SYS_LN_SYS_LN_EN_SHIFT 0 2505 2506 2507 /**************************************************************************** 2508 * ctl_regs :: gpio_0_ctrl_status 2509 */ 2510 /* ctl_regs :: gpio_0_ctrl_status :: reserved0 [15:06] */ 2511 #define CTL_REGS_GPIO_0_CTRL_STATUS_RESERVED0_MASK 0xffc0 2512 #define CTL_REGS_GPIO_0_CTRL_STATUS_RESERVED0_ALIGN 0 2513 #define CTL_REGS_GPIO_0_CTRL_STATUS_RESERVED0_BITS 10 2514 #define CTL_REGS_GPIO_0_CTRL_STATUS_RESERVED0_SHIFT 6 2515 2516 /* ctl_regs :: gpio_0_ctrl_status :: gpio_pdn_ctrl_0 [05:05] */ 2517 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PDN_CTRL_0_MASK 0x0020 2518 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PDN_CTRL_0_ALIGN 0 2519 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PDN_CTRL_0_BITS 1 2520 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PDN_CTRL_0_SHIFT 5 2521 2522 /* ctl_regs :: gpio_0_ctrl_status :: gpio_pup_ctrl_0 [04:04] */ 2523 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PUP_CTRL_0_MASK 0x0010 2524 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PUP_CTRL_0_ALIGN 0 2525 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PUP_CTRL_0_BITS 1 2526 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PUP_CTRL_0_SHIFT 4 2527 2528 /* ctl_regs :: gpio_0_ctrl_status :: gpio_oeb_ctrl_0 [03:03] */ 2529 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_OEB_CTRL_0_MASK 0x0008 2530 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_OEB_CTRL_0_ALIGN 0 2531 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_OEB_CTRL_0_BITS 1 2532 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_OEB_CTRL_0_SHIFT 3 2533 2534 /* ctl_regs :: gpio_0_ctrl_status :: gpio_in_status_0 [02:02] */ 2535 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_IN_STATUS_0_MASK 0x0004 2536 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_IN_STATUS_0_ALIGN 0 2537 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_IN_STATUS_0_BITS 1 2538 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_IN_STATUS_0_SHIFT 2 2539 2540 /* ctl_regs :: gpio_0_ctrl_status :: gpio_out_ctrl_0 [01:01] */ 2541 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_OUT_CTRL_0_MASK 0x0002 2542 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_OUT_CTRL_0_ALIGN 0 2543 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_OUT_CTRL_0_BITS 1 2544 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_OUT_CTRL_0_SHIFT 1 2545 2546 /* ctl_regs :: gpio_0_ctrl_status :: gpio_pad_ctrl_0 [00:00] */ 2547 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PAD_CTRL_0_MASK 0x0001 2548 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PAD_CTRL_0_ALIGN 0 2549 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PAD_CTRL_0_BITS 1 2550 #define CTL_REGS_GPIO_0_CTRL_STATUS_GPIO_PAD_CTRL_0_SHIFT 0 2551 2552 2553 /**************************************************************************** 2554 * ctl_regs :: gpio_1_ctrl_status 2555 */ 2556 /* ctl_regs :: gpio_1_ctrl_status :: reserved0 [15:06] */ 2557 #define CTL_REGS_GPIO_1_CTRL_STATUS_RESERVED0_MASK 0xffc0 2558 #define CTL_REGS_GPIO_1_CTRL_STATUS_RESERVED0_ALIGN 0 2559 #define CTL_REGS_GPIO_1_CTRL_STATUS_RESERVED0_BITS 10 2560 #define CTL_REGS_GPIO_1_CTRL_STATUS_RESERVED0_SHIFT 6 2561 2562 /* ctl_regs :: gpio_1_ctrl_status :: gpio_pdn_ctrl_1 [05:05] */ 2563 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PDN_CTRL_1_MASK 0x0020 2564 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PDN_CTRL_1_ALIGN 0 2565 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PDN_CTRL_1_BITS 1 2566 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PDN_CTRL_1_SHIFT 5 2567 2568 /* ctl_regs :: gpio_1_ctrl_status :: gpio_pup_ctrl_1 [04:04] */ 2569 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PUP_CTRL_1_MASK 0x0010 2570 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PUP_CTRL_1_ALIGN 0 2571 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PUP_CTRL_1_BITS 1 2572 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PUP_CTRL_1_SHIFT 4 2573 2574 /* ctl_regs :: gpio_1_ctrl_status :: gpio_oeb_ctrl_1 [03:03] */ 2575 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_OEB_CTRL_1_MASK 0x0008 2576 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_OEB_CTRL_1_ALIGN 0 2577 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_OEB_CTRL_1_BITS 1 2578 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_OEB_CTRL_1_SHIFT 3 2579 2580 /* ctl_regs :: gpio_1_ctrl_status :: gpio_in_status_1 [02:02] */ 2581 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_IN_STATUS_1_MASK 0x0004 2582 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_IN_STATUS_1_ALIGN 0 2583 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_IN_STATUS_1_BITS 1 2584 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_IN_STATUS_1_SHIFT 2 2585 2586 /* ctl_regs :: gpio_1_ctrl_status :: gpio_out_ctrl_1 [01:01] */ 2587 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_OUT_CTRL_1_MASK 0x0002 2588 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_OUT_CTRL_1_ALIGN 0 2589 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_OUT_CTRL_1_BITS 1 2590 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_OUT_CTRL_1_SHIFT 1 2591 2592 /* ctl_regs :: gpio_1_ctrl_status :: gpio_pad_ctrl_1 [00:00] */ 2593 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PAD_CTRL_1_MASK 0x0001 2594 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PAD_CTRL_1_ALIGN 0 2595 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PAD_CTRL_1_BITS 1 2596 #define CTL_REGS_GPIO_1_CTRL_STATUS_GPIO_PAD_CTRL_1_SHIFT 0 2597 2598 2599 /**************************************************************************** 2600 * ctl_regs :: gpio_2_ctrl_status 2601 */ 2602 /* ctl_regs :: gpio_2_ctrl_status :: reserved0 [15:06] */ 2603 #define CTL_REGS_GPIO_2_CTRL_STATUS_RESERVED0_MASK 0xffc0 2604 #define CTL_REGS_GPIO_2_CTRL_STATUS_RESERVED0_ALIGN 0 2605 #define CTL_REGS_GPIO_2_CTRL_STATUS_RESERVED0_BITS 10 2606 #define CTL_REGS_GPIO_2_CTRL_STATUS_RESERVED0_SHIFT 6 2607 2608 /* ctl_regs :: gpio_2_ctrl_status :: gpio_pdn_ctrl_2 [05:05] */ 2609 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PDN_CTRL_2_MASK 0x0020 2610 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PDN_CTRL_2_ALIGN 0 2611 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PDN_CTRL_2_BITS 1 2612 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PDN_CTRL_2_SHIFT 5 2613 2614 /* ctl_regs :: gpio_2_ctrl_status :: gpio_pup_ctrl_2 [04:04] */ 2615 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PUP_CTRL_2_MASK 0x0010 2616 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PUP_CTRL_2_ALIGN 0 2617 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PUP_CTRL_2_BITS 1 2618 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PUP_CTRL_2_SHIFT 4 2619 2620 /* ctl_regs :: gpio_2_ctrl_status :: gpio_oeb_ctrl_2 [03:03] */ 2621 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_OEB_CTRL_2_MASK 0x0008 2622 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_OEB_CTRL_2_ALIGN 0 2623 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_OEB_CTRL_2_BITS 1 2624 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_OEB_CTRL_2_SHIFT 3 2625 2626 /* ctl_regs :: gpio_2_ctrl_status :: gpio_in_status_2 [02:02] */ 2627 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_IN_STATUS_2_MASK 0x0004 2628 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_IN_STATUS_2_ALIGN 0 2629 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_IN_STATUS_2_BITS 1 2630 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_IN_STATUS_2_SHIFT 2 2631 2632 /* ctl_regs :: gpio_2_ctrl_status :: gpio_out_ctrl_2 [01:01] */ 2633 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_OUT_CTRL_2_MASK 0x0002 2634 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_OUT_CTRL_2_ALIGN 0 2635 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_OUT_CTRL_2_BITS 1 2636 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_OUT_CTRL_2_SHIFT 1 2637 2638 /* ctl_regs :: gpio_2_ctrl_status :: gpio_pad_ctrl_2 [00:00] */ 2639 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PAD_CTRL_2_MASK 0x0001 2640 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PAD_CTRL_2_ALIGN 0 2641 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PAD_CTRL_2_BITS 1 2642 #define CTL_REGS_GPIO_2_CTRL_STATUS_GPIO_PAD_CTRL_2_SHIFT 0 2643 2644 2645 /**************************************************************************** 2646 * ctl_regs :: gpio_3_ctrl_status 2647 */ 2648 /* ctl_regs :: gpio_3_ctrl_status :: reserved0 [15:06] */ 2649 #define CTL_REGS_GPIO_3_CTRL_STATUS_RESERVED0_MASK 0xffc0 2650 #define CTL_REGS_GPIO_3_CTRL_STATUS_RESERVED0_ALIGN 0 2651 #define CTL_REGS_GPIO_3_CTRL_STATUS_RESERVED0_BITS 10 2652 #define CTL_REGS_GPIO_3_CTRL_STATUS_RESERVED0_SHIFT 6 2653 2654 /* ctl_regs :: gpio_3_ctrl_status :: gpio_pdn_ctrl_3 [05:05] */ 2655 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PDN_CTRL_3_MASK 0x0020 2656 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PDN_CTRL_3_ALIGN 0 2657 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PDN_CTRL_3_BITS 1 2658 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PDN_CTRL_3_SHIFT 5 2659 2660 /* ctl_regs :: gpio_3_ctrl_status :: gpio_pup_ctrl_3 [04:04] */ 2661 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PUP_CTRL_3_MASK 0x0010 2662 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PUP_CTRL_3_ALIGN 0 2663 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PUP_CTRL_3_BITS 1 2664 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PUP_CTRL_3_SHIFT 4 2665 2666 /* ctl_regs :: gpio_3_ctrl_status :: gpio_oeb_ctrl_3 [03:03] */ 2667 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_OEB_CTRL_3_MASK 0x0008 2668 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_OEB_CTRL_3_ALIGN 0 2669 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_OEB_CTRL_3_BITS 1 2670 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_OEB_CTRL_3_SHIFT 3 2671 2672 /* ctl_regs :: gpio_3_ctrl_status :: gpio_in_status_3 [02:02] */ 2673 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_IN_STATUS_3_MASK 0x0004 2674 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_IN_STATUS_3_ALIGN 0 2675 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_IN_STATUS_3_BITS 1 2676 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_IN_STATUS_3_SHIFT 2 2677 2678 /* ctl_regs :: gpio_3_ctrl_status :: gpio_out_ctrl_3 [01:01] */ 2679 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_OUT_CTRL_3_MASK 0x0002 2680 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_OUT_CTRL_3_ALIGN 0 2681 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_OUT_CTRL_3_BITS 1 2682 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_OUT_CTRL_3_SHIFT 1 2683 2684 /* ctl_regs :: gpio_3_ctrl_status :: gpio_pad_ctrl_3 [00:00] */ 2685 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PAD_CTRL_3_MASK 0x0001 2686 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PAD_CTRL_3_ALIGN 0 2687 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PAD_CTRL_3_BITS 1 2688 #define CTL_REGS_GPIO_3_CTRL_STATUS_GPIO_PAD_CTRL_3_SHIFT 0 2689 2690 2691 /**************************************************************************** 2692 * ctl_regs :: gpio_4_ctrl_status 2693 */ 2694 /* ctl_regs :: gpio_4_ctrl_status :: reserved0 [15:06] */ 2695 #define CTL_REGS_GPIO_4_CTRL_STATUS_RESERVED0_MASK 0xffc0 2696 #define CTL_REGS_GPIO_4_CTRL_STATUS_RESERVED0_ALIGN 0 2697 #define CTL_REGS_GPIO_4_CTRL_STATUS_RESERVED0_BITS 10 2698 #define CTL_REGS_GPIO_4_CTRL_STATUS_RESERVED0_SHIFT 6 2699 2700 /* ctl_regs :: gpio_4_ctrl_status :: gpio_pdn_ctrl_4 [05:05] */ 2701 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PDN_CTRL_4_MASK 0x0020 2702 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PDN_CTRL_4_ALIGN 0 2703 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PDN_CTRL_4_BITS 1 2704 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PDN_CTRL_4_SHIFT 5 2705 2706 /* ctl_regs :: gpio_4_ctrl_status :: gpio_pup_ctrl_4 [04:04] */ 2707 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PUP_CTRL_4_MASK 0x0010 2708 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PUP_CTRL_4_ALIGN 0 2709 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PUP_CTRL_4_BITS 1 2710 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PUP_CTRL_4_SHIFT 4 2711 2712 /* ctl_regs :: gpio_4_ctrl_status :: gpio_oeb_ctrl_4 [03:03] */ 2713 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_OEB_CTRL_4_MASK 0x0008 2714 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_OEB_CTRL_4_ALIGN 0 2715 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_OEB_CTRL_4_BITS 1 2716 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_OEB_CTRL_4_SHIFT 3 2717 2718 /* ctl_regs :: gpio_4_ctrl_status :: gpio_in_status_4 [02:02] */ 2719 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_IN_STATUS_4_MASK 0x0004 2720 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_IN_STATUS_4_ALIGN 0 2721 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_IN_STATUS_4_BITS 1 2722 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_IN_STATUS_4_SHIFT 2 2723 2724 /* ctl_regs :: gpio_4_ctrl_status :: gpio_out_ctrl_4 [01:01] */ 2725 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_OUT_CTRL_4_MASK 0x0002 2726 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_OUT_CTRL_4_ALIGN 0 2727 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_OUT_CTRL_4_BITS 1 2728 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_OUT_CTRL_4_SHIFT 1 2729 2730 /* ctl_regs :: gpio_4_ctrl_status :: gpio_pad_ctrl_4 [00:00] */ 2731 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PAD_CTRL_4_MASK 0x0001 2732 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PAD_CTRL_4_ALIGN 0 2733 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PAD_CTRL_4_BITS 1 2734 #define CTL_REGS_GPIO_4_CTRL_STATUS_GPIO_PAD_CTRL_4_SHIFT 0 2735 2736 2737 /**************************************************************************** 2738 * ctl_regs :: gpio_5_ctrl_status 2739 */ 2740 /* ctl_regs :: gpio_5_ctrl_status :: reserved0 [15:06] */ 2741 #define CTL_REGS_GPIO_5_CTRL_STATUS_RESERVED0_MASK 0xffc0 2742 #define CTL_REGS_GPIO_5_CTRL_STATUS_RESERVED0_ALIGN 0 2743 #define CTL_REGS_GPIO_5_CTRL_STATUS_RESERVED0_BITS 10 2744 #define CTL_REGS_GPIO_5_CTRL_STATUS_RESERVED0_SHIFT 6 2745 2746 /* ctl_regs :: gpio_5_ctrl_status :: gpio_pdn_ctrl_5 [05:05] */ 2747 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PDN_CTRL_5_MASK 0x0020 2748 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PDN_CTRL_5_ALIGN 0 2749 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PDN_CTRL_5_BITS 1 2750 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PDN_CTRL_5_SHIFT 5 2751 2752 /* ctl_regs :: gpio_5_ctrl_status :: gpio_pup_ctrl_5 [04:04] */ 2753 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PUP_CTRL_5_MASK 0x0010 2754 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PUP_CTRL_5_ALIGN 0 2755 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PUP_CTRL_5_BITS 1 2756 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PUP_CTRL_5_SHIFT 4 2757 2758 /* ctl_regs :: gpio_5_ctrl_status :: gpio_oeb_ctrl_5 [03:03] */ 2759 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_OEB_CTRL_5_MASK 0x0008 2760 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_OEB_CTRL_5_ALIGN 0 2761 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_OEB_CTRL_5_BITS 1 2762 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_OEB_CTRL_5_SHIFT 3 2763 2764 /* ctl_regs :: gpio_5_ctrl_status :: gpio_in_status_5 [02:02] */ 2765 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_IN_STATUS_5_MASK 0x0004 2766 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_IN_STATUS_5_ALIGN 0 2767 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_IN_STATUS_5_BITS 1 2768 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_IN_STATUS_5_SHIFT 2 2769 2770 /* ctl_regs :: gpio_5_ctrl_status :: gpio_out_ctrl_5 [01:01] */ 2771 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_OUT_CTRL_5_MASK 0x0002 2772 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_OUT_CTRL_5_ALIGN 0 2773 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_OUT_CTRL_5_BITS 1 2774 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_OUT_CTRL_5_SHIFT 1 2775 2776 /* ctl_regs :: gpio_5_ctrl_status :: gpio_pad_ctrl_5 [00:00] */ 2777 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PAD_CTRL_5_MASK 0x0001 2778 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PAD_CTRL_5_ALIGN 0 2779 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PAD_CTRL_5_BITS 1 2780 #define CTL_REGS_GPIO_5_CTRL_STATUS_GPIO_PAD_CTRL_5_SHIFT 0 2781 2782 2783 /**************************************************************************** 2784 * ctl_regs :: status_ctrl1 2785 */ 2786 /* ctl_regs :: status_ctrl1 :: reserved0 [15:15] */ 2787 #define CTL_REGS_STATUS_CTRL1_RESERVED0_MASK 0x8000 2788 #define CTL_REGS_STATUS_CTRL1_RESERVED0_ALIGN 0 2789 #define CTL_REGS_STATUS_CTRL1_RESERVED0_BITS 1 2790 #define CTL_REGS_STATUS_CTRL1_RESERVED0_SHIFT 15 2791 2792 /* ctl_regs :: status_ctrl1 :: frc_ext_intr_status [14:14] */ 2793 #define CTL_REGS_STATUS_CTRL1_FRC_EXT_INTR_STATUS_MASK 0x4000 2794 #define CTL_REGS_STATUS_CTRL1_FRC_EXT_INTR_STATUS_ALIGN 0 2795 #define CTL_REGS_STATUS_CTRL1_FRC_EXT_INTR_STATUS_BITS 1 2796 #define CTL_REGS_STATUS_CTRL1_FRC_EXT_INTR_STATUS_SHIFT 14 2797 2798 /* ctl_regs :: status_ctrl1 :: ext_intr_status [13:13] */ 2799 #define CTL_REGS_STATUS_CTRL1_EXT_INTR_STATUS_MASK 0x2000 2800 #define CTL_REGS_STATUS_CTRL1_EXT_INTR_STATUS_ALIGN 0 2801 #define CTL_REGS_STATUS_CTRL1_EXT_INTR_STATUS_BITS 1 2802 #define CTL_REGS_STATUS_CTRL1_EXT_INTR_STATUS_SHIFT 13 2803 2804 /* ctl_regs :: status_ctrl1 :: inv_ext_intr_status [12:12] */ 2805 #define CTL_REGS_STATUS_CTRL1_INV_EXT_INTR_STATUS_MASK 0x1000 2806 #define CTL_REGS_STATUS_CTRL1_INV_EXT_INTR_STATUS_ALIGN 0 2807 #define CTL_REGS_STATUS_CTRL1_INV_EXT_INTR_STATUS_BITS 1 2808 #define CTL_REGS_STATUS_CTRL1_INV_EXT_INTR_STATUS_SHIFT 12 2809 2810 /* ctl_regs :: status_ctrl1 :: frc_sys_lol_status [11:11] */ 2811 #define CTL_REGS_STATUS_CTRL1_FRC_SYS_LOL_STATUS_MASK 0x0800 2812 #define CTL_REGS_STATUS_CTRL1_FRC_SYS_LOL_STATUS_ALIGN 0 2813 #define CTL_REGS_STATUS_CTRL1_FRC_SYS_LOL_STATUS_BITS 1 2814 #define CTL_REGS_STATUS_CTRL1_FRC_SYS_LOL_STATUS_SHIFT 11 2815 2816 /* ctl_regs :: status_ctrl1 :: sys_lol_status [10:10] */ 2817 #define CTL_REGS_STATUS_CTRL1_SYS_LOL_STATUS_MASK 0x0400 2818 #define CTL_REGS_STATUS_CTRL1_SYS_LOL_STATUS_ALIGN 0 2819 #define CTL_REGS_STATUS_CTRL1_SYS_LOL_STATUS_BITS 1 2820 #define CTL_REGS_STATUS_CTRL1_SYS_LOL_STATUS_SHIFT 10 2821 2822 /* ctl_regs :: status_ctrl1 :: inv_sys_lol_status [09:09] */ 2823 #define CTL_REGS_STATUS_CTRL1_INV_SYS_LOL_STATUS_MASK 0x0200 2824 #define CTL_REGS_STATUS_CTRL1_INV_SYS_LOL_STATUS_ALIGN 0 2825 #define CTL_REGS_STATUS_CTRL1_INV_SYS_LOL_STATUS_BITS 1 2826 #define CTL_REGS_STATUS_CTRL1_INV_SYS_LOL_STATUS_SHIFT 9 2827 2828 /* ctl_regs :: status_ctrl1 :: frc_rx_los_status [08:08] */ 2829 #define CTL_REGS_STATUS_CTRL1_FRC_RX_LOS_STATUS_MASK 0x0100 2830 #define CTL_REGS_STATUS_CTRL1_FRC_RX_LOS_STATUS_ALIGN 0 2831 #define CTL_REGS_STATUS_CTRL1_FRC_RX_LOS_STATUS_BITS 1 2832 #define CTL_REGS_STATUS_CTRL1_FRC_RX_LOS_STATUS_SHIFT 8 2833 2834 /* ctl_regs :: status_ctrl1 :: rx_los_status [07:07] */ 2835 #define CTL_REGS_STATUS_CTRL1_RX_LOS_STATUS_MASK 0x0080 2836 #define CTL_REGS_STATUS_CTRL1_RX_LOS_STATUS_ALIGN 0 2837 #define CTL_REGS_STATUS_CTRL1_RX_LOS_STATUS_BITS 1 2838 #define CTL_REGS_STATUS_CTRL1_RX_LOS_STATUS_SHIFT 7 2839 2840 /* ctl_regs :: status_ctrl1 :: inv_rx_los_status [06:06] */ 2841 #define CTL_REGS_STATUS_CTRL1_INV_RX_LOS_STATUS_MASK 0x0040 2842 #define CTL_REGS_STATUS_CTRL1_INV_RX_LOS_STATUS_ALIGN 0 2843 #define CTL_REGS_STATUS_CTRL1_INV_RX_LOS_STATUS_BITS 1 2844 #define CTL_REGS_STATUS_CTRL1_INV_RX_LOS_STATUS_SHIFT 6 2845 2846 /* ctl_regs :: status_ctrl1 :: frc_rx_line_lol_status [05:05] */ 2847 #define CTL_REGS_STATUS_CTRL1_FRC_RX_LINE_LOL_STATUS_MASK 0x0020 2848 #define CTL_REGS_STATUS_CTRL1_FRC_RX_LINE_LOL_STATUS_ALIGN 0 2849 #define CTL_REGS_STATUS_CTRL1_FRC_RX_LINE_LOL_STATUS_BITS 1 2850 #define CTL_REGS_STATUS_CTRL1_FRC_RX_LINE_LOL_STATUS_SHIFT 5 2851 2852 /* ctl_regs :: status_ctrl1 :: rx_line_lol_status [04:04] */ 2853 #define CTL_REGS_STATUS_CTRL1_RX_LINE_LOL_STATUS_MASK 0x0010 2854 #define CTL_REGS_STATUS_CTRL1_RX_LINE_LOL_STATUS_ALIGN 0 2855 #define CTL_REGS_STATUS_CTRL1_RX_LINE_LOL_STATUS_BITS 1 2856 #define CTL_REGS_STATUS_CTRL1_RX_LINE_LOL_STATUS_SHIFT 4 2857 2858 /* ctl_regs :: status_ctrl1 :: inv_rx_line_lol_status [03:03] */ 2859 #define CTL_REGS_STATUS_CTRL1_INV_RX_LINE_LOL_STATUS_MASK 0x0008 2860 #define CTL_REGS_STATUS_CTRL1_INV_RX_LINE_LOL_STATUS_ALIGN 0 2861 #define CTL_REGS_STATUS_CTRL1_INV_RX_LINE_LOL_STATUS_BITS 1 2862 #define CTL_REGS_STATUS_CTRL1_INV_RX_LINE_LOL_STATUS_SHIFT 3 2863 2864 /* ctl_regs :: status_ctrl1 :: frc_tx_line_lol_status [02:02] */ 2865 #define CTL_REGS_STATUS_CTRL1_FRC_TX_LINE_LOL_STATUS_MASK 0x0004 2866 #define CTL_REGS_STATUS_CTRL1_FRC_TX_LINE_LOL_STATUS_ALIGN 0 2867 #define CTL_REGS_STATUS_CTRL1_FRC_TX_LINE_LOL_STATUS_BITS 1 2868 #define CTL_REGS_STATUS_CTRL1_FRC_TX_LINE_LOL_STATUS_SHIFT 2 2869 2870 /* ctl_regs :: status_ctrl1 :: tx_line_lol_status [01:01] */ 2871 #define CTL_REGS_STATUS_CTRL1_TX_LINE_LOL_STATUS_MASK 0x0002 2872 #define CTL_REGS_STATUS_CTRL1_TX_LINE_LOL_STATUS_ALIGN 0 2873 #define CTL_REGS_STATUS_CTRL1_TX_LINE_LOL_STATUS_BITS 1 2874 #define CTL_REGS_STATUS_CTRL1_TX_LINE_LOL_STATUS_SHIFT 1 2875 2876 /* ctl_regs :: status_ctrl1 :: inv_tx_line_lol_status [00:00] */ 2877 #define CTL_REGS_STATUS_CTRL1_INV_TX_LINE_LOL_STATUS_MASK 0x0001 2878 #define CTL_REGS_STATUS_CTRL1_INV_TX_LINE_LOL_STATUS_ALIGN 0 2879 #define CTL_REGS_STATUS_CTRL1_INV_TX_LINE_LOL_STATUS_BITS 1 2880 #define CTL_REGS_STATUS_CTRL1_INV_TX_LINE_LOL_STATUS_SHIFT 0 2881 2882 2883 /**************************************************************************** 2884 * ctl_regs :: status_ctrl2 2885 */ 2886 /* ctl_regs :: status_ctrl2 :: reserved0 [15:03] */ 2887 #define CTL_REGS_STATUS_CTRL2_RESERVED0_MASK 0xfff8 2888 #define CTL_REGS_STATUS_CTRL2_RESERVED0_ALIGN 0 2889 #define CTL_REGS_STATUS_CTRL2_RESERVED0_BITS 13 2890 #define CTL_REGS_STATUS_CTRL2_RESERVED0_SHIFT 3 2891 2892 /* ctl_regs :: status_ctrl2 :: frc_tx_vcxo_lol_status [02:02] */ 2893 #define CTL_REGS_STATUS_CTRL2_FRC_TX_VCXO_LOL_STATUS_MASK 0x0004 2894 #define CTL_REGS_STATUS_CTRL2_FRC_TX_VCXO_LOL_STATUS_ALIGN 0 2895 #define CTL_REGS_STATUS_CTRL2_FRC_TX_VCXO_LOL_STATUS_BITS 1 2896 #define CTL_REGS_STATUS_CTRL2_FRC_TX_VCXO_LOL_STATUS_SHIFT 2 2897 2898 /* ctl_regs :: status_ctrl2 :: tx_vcxo_lol_status [01:01] */ 2899 #define CTL_REGS_STATUS_CTRL2_TX_VCXO_LOL_STATUS_MASK 0x0002 2900 #define CTL_REGS_STATUS_CTRL2_TX_VCXO_LOL_STATUS_ALIGN 0 2901 #define CTL_REGS_STATUS_CTRL2_TX_VCXO_LOL_STATUS_BITS 1 2902 #define CTL_REGS_STATUS_CTRL2_TX_VCXO_LOL_STATUS_SHIFT 1 2903 2904 /* ctl_regs :: status_ctrl2 :: inv_tx_vcxo_lol_status [00:00] */ 2905 #define CTL_REGS_STATUS_CTRL2_INV_TX_VCXO_LOL_STATUS_MASK 0x0001 2906 #define CTL_REGS_STATUS_CTRL2_INV_TX_VCXO_LOL_STATUS_ALIGN 0 2907 #define CTL_REGS_STATUS_CTRL2_INV_TX_VCXO_LOL_STATUS_BITS 1 2908 #define CTL_REGS_STATUS_CTRL2_INV_TX_VCXO_LOL_STATUS_SHIFT 0 2909 2910 2911 /**************************************************************************** 2912 * ctl_regs :: input_status 2913 */ 2914 /* ctl_regs :: input_status :: reserved0 [15:06] */ 2915 #define CTL_REGS_INPUT_STATUS_RESERVED0_MASK 0xffc0 2916 #define CTL_REGS_INPUT_STATUS_RESERVED0_ALIGN 0 2917 #define CTL_REGS_INPUT_STATUS_RESERVED0_BITS 10 2918 #define CTL_REGS_INPUT_STATUS_RESERVED0_SHIFT 6 2919 2920 /* ctl_regs :: input_status :: tx_dis_lh [05:05] */ 2921 #define CTL_REGS_INPUT_STATUS_TX_DIS_LH_MASK 0x0020 2922 #define CTL_REGS_INPUT_STATUS_TX_DIS_LH_ALIGN 0 2923 #define CTL_REGS_INPUT_STATUS_TX_DIS_LH_BITS 1 2924 #define CTL_REGS_INPUT_STATUS_TX_DIS_LH_SHIFT 5 2925 2926 /* ctl_regs :: input_status :: tx_dis_ll [04:04] */ 2927 #define CTL_REGS_INPUT_STATUS_TX_DIS_LL_MASK 0x0010 2928 #define CTL_REGS_INPUT_STATUS_TX_DIS_LL_ALIGN 0 2929 #define CTL_REGS_INPUT_STATUS_TX_DIS_LL_BITS 1 2930 #define CTL_REGS_INPUT_STATUS_TX_DIS_LL_SHIFT 4 2931 2932 /* ctl_regs :: input_status :: mod_lopwr_lh [03:03] */ 2933 #define CTL_REGS_INPUT_STATUS_MOD_LOPWR_LH_MASK 0x0008 2934 #define CTL_REGS_INPUT_STATUS_MOD_LOPWR_LH_ALIGN 0 2935 #define CTL_REGS_INPUT_STATUS_MOD_LOPWR_LH_BITS 1 2936 #define CTL_REGS_INPUT_STATUS_MOD_LOPWR_LH_SHIFT 3 2937 2938 /* ctl_regs :: input_status :: mod_lopwr_ll [02:02] */ 2939 #define CTL_REGS_INPUT_STATUS_MOD_LOPWR_LL_MASK 0x0004 2940 #define CTL_REGS_INPUT_STATUS_MOD_LOPWR_LL_ALIGN 0 2941 #define CTL_REGS_INPUT_STATUS_MOD_LOPWR_LL_BITS 1 2942 #define CTL_REGS_INPUT_STATUS_MOD_LOPWR_LL_SHIFT 2 2943 2944 /* ctl_regs :: input_status :: mod_abs_lh [01:01] */ 2945 #define CTL_REGS_INPUT_STATUS_MOD_ABS_LH_MASK 0x0002 2946 #define CTL_REGS_INPUT_STATUS_MOD_ABS_LH_ALIGN 0 2947 #define CTL_REGS_INPUT_STATUS_MOD_ABS_LH_BITS 1 2948 #define CTL_REGS_INPUT_STATUS_MOD_ABS_LH_SHIFT 1 2949 2950 /* ctl_regs :: input_status :: mod_abs_ll [00:00] */ 2951 #define CTL_REGS_INPUT_STATUS_MOD_ABS_LL_MASK 0x0001 2952 #define CTL_REGS_INPUT_STATUS_MOD_ABS_LL_ALIGN 0 2953 #define CTL_REGS_INPUT_STATUS_MOD_ABS_LL_BITS 1 2954 #define CTL_REGS_INPUT_STATUS_MOD_ABS_LL_SHIFT 0 2955 2956 2957 /**************************************************************************** 2958 * ctl_regs :: ieee_regs_rst_latch 2959 */ 2960 /* ctl_regs :: ieee_regs_rst_latch :: reserved0 [15:14] */ 2961 #define CTL_REGS_IEEE_REGS_RST_LATCH_RESERVED0_MASK 0xc000 2962 #define CTL_REGS_IEEE_REGS_RST_LATCH_RESERVED0_ALIGN 0 2963 #define CTL_REGS_IEEE_REGS_RST_LATCH_RESERVED0_BITS 2 2964 #define CTL_REGS_IEEE_REGS_RST_LATCH_RESERVED0_SHIFT 14 2965 2966 /* ctl_regs :: ieee_regs_rst_latch :: ieee_regs_rst_lh [13:00] */ 2967 #define CTL_REGS_IEEE_REGS_RST_LATCH_IEEE_REGS_RST_LH_MASK 0x3fff 2968 #define CTL_REGS_IEEE_REGS_RST_LATCH_IEEE_REGS_RST_LH_ALIGN 0 2969 #define CTL_REGS_IEEE_REGS_RST_LATCH_IEEE_REGS_RST_LH_BITS 14 2970 #define CTL_REGS_IEEE_REGS_RST_LATCH_IEEE_REGS_RST_LH_SHIFT 0 2971 2972 2973 /**************************************************************************** 2974 * ctl_regs :: dis_sys_cdr_lock 2975 */ 2976 /* ctl_regs :: dis_sys_cdr_lock :: reserved0 [15:10] */ 2977 #define CTL_REGS_DIS_SYS_CDR_LOCK_RESERVED0_MASK 0xfc00 2978 #define CTL_REGS_DIS_SYS_CDR_LOCK_RESERVED0_ALIGN 0 2979 #define CTL_REGS_DIS_SYS_CDR_LOCK_RESERVED0_BITS 6 2980 #define CTL_REGS_DIS_SYS_CDR_LOCK_RESERVED0_SHIFT 10 2981 2982 /* ctl_regs :: dis_sys_cdr_lock :: dis_sys_cdr_lock_status [09:00] */ 2983 #define CTL_REGS_DIS_SYS_CDR_LOCK_DIS_SYS_CDR_LOCK_STATUS_MASK 0x03ff 2984 #define CTL_REGS_DIS_SYS_CDR_LOCK_DIS_SYS_CDR_LOCK_STATUS_ALIGN 0 2985 #define CTL_REGS_DIS_SYS_CDR_LOCK_DIS_SYS_CDR_LOCK_STATUS_BITS 10 2986 #define CTL_REGS_DIS_SYS_CDR_LOCK_DIS_SYS_CDR_LOCK_STATUS_SHIFT 0 2987 2988 2989 /**************************************************************************** 2990 * ctl_regs :: dis_sys_sigdet 2991 */ 2992 /* ctl_regs :: dis_sys_sigdet :: reserved0 [15:10] */ 2993 #define CTL_REGS_DIS_SYS_SIGDET_RESERVED0_MASK 0xfc00 2994 #define CTL_REGS_DIS_SYS_SIGDET_RESERVED0_ALIGN 0 2995 #define CTL_REGS_DIS_SYS_SIGDET_RESERVED0_BITS 6 2996 #define CTL_REGS_DIS_SYS_SIGDET_RESERVED0_SHIFT 10 2997 2998 /* ctl_regs :: dis_sys_sigdet :: dis_sys_sigdet_status [09:00] */ 2999 #define CTL_REGS_DIS_SYS_SIGDET_DIS_SYS_SIGDET_STATUS_MASK 0x03ff 3000 #define CTL_REGS_DIS_SYS_SIGDET_DIS_SYS_SIGDET_STATUS_ALIGN 0 3001 #define CTL_REGS_DIS_SYS_SIGDET_DIS_SYS_SIGDET_STATUS_BITS 10 3002 #define CTL_REGS_DIS_SYS_SIGDET_DIS_SYS_SIGDET_STATUS_SHIFT 0 3003 3004 3005 /**************************************************************************** 3006 * ctl_regs :: dis_line_cdr_lock 3007 */ 3008 /* ctl_regs :: dis_line_cdr_lock :: reserved0 [15:10] */ 3009 #define CTL_REGS_DIS_LINE_CDR_LOCK_RESERVED0_MASK 0xfc00 3010 #define CTL_REGS_DIS_LINE_CDR_LOCK_RESERVED0_ALIGN 0 3011 #define CTL_REGS_DIS_LINE_CDR_LOCK_RESERVED0_BITS 6 3012 #define CTL_REGS_DIS_LINE_CDR_LOCK_RESERVED0_SHIFT 10 3013 3014 /* ctl_regs :: dis_line_cdr_lock :: dis_line_cdr_lock_status [09:00] */ 3015 #define CTL_REGS_DIS_LINE_CDR_LOCK_DIS_LINE_CDR_LOCK_STATUS_MASK 0x03ff 3016 #define CTL_REGS_DIS_LINE_CDR_LOCK_DIS_LINE_CDR_LOCK_STATUS_ALIGN 0 3017 #define CTL_REGS_DIS_LINE_CDR_LOCK_DIS_LINE_CDR_LOCK_STATUS_BITS 10 3018 #define CTL_REGS_DIS_LINE_CDR_LOCK_DIS_LINE_CDR_LOCK_STATUS_SHIFT 0 3019 3020 3021 /**************************************************************************** 3022 * ctl_regs :: dis_line_sigdet 3023 */ 3024 /* ctl_regs :: dis_line_sigdet :: reserved0 [15:10] */ 3025 #define CTL_REGS_DIS_LINE_SIGDET_RESERVED0_MASK 0xfc00 3026 #define CTL_REGS_DIS_LINE_SIGDET_RESERVED0_ALIGN 0 3027 #define CTL_REGS_DIS_LINE_SIGDET_RESERVED0_BITS 6 3028 #define CTL_REGS_DIS_LINE_SIGDET_RESERVED0_SHIFT 10 3029 3030 /* ctl_regs :: dis_line_sigdet :: dis_line_sigdet_status [09:00] */ 3031 #define CTL_REGS_DIS_LINE_SIGDET_DIS_LINE_SIGDET_STATUS_MASK 0x03ff 3032 #define CTL_REGS_DIS_LINE_SIGDET_DIS_LINE_SIGDET_STATUS_ALIGN 0 3033 #define CTL_REGS_DIS_LINE_SIGDET_DIS_LINE_SIGDET_STATUS_BITS 10 3034 #define CTL_REGS_DIS_LINE_SIGDET_DIS_LINE_SIGDET_STATUS_SHIFT 0 3035 3036 3037 /**************************************************************************** 3038 * ctl_regs :: status_mux_ctrl 3039 */ 3040 /* ctl_regs :: status_mux_ctrl :: reserved0 [15:03] */ 3041 #define CTL_REGS_STATUS_MUX_CTRL_RESERVED0_MASK 0xfff8 3042 #define CTL_REGS_STATUS_MUX_CTRL_RESERVED0_ALIGN 0 3043 #define CTL_REGS_STATUS_MUX_CTRL_RESERVED0_BITS 13 3044 #define CTL_REGS_STATUS_MUX_CTRL_RESERVED0_SHIFT 3 3045 3046 /* ctl_regs :: status_mux_ctrl :: status_mux_sel [02:01] */ 3047 #define CTL_REGS_STATUS_MUX_CTRL_STATUS_MUX_SEL_MASK 0x0006 3048 #define CTL_REGS_STATUS_MUX_CTRL_STATUS_MUX_SEL_ALIGN 0 3049 #define CTL_REGS_STATUS_MUX_CTRL_STATUS_MUX_SEL_BITS 2 3050 #define CTL_REGS_STATUS_MUX_CTRL_STATUS_MUX_SEL_SHIFT 1 3051 3052 /* ctl_regs :: status_mux_ctrl :: status_mux_en [00:00] */ 3053 #define CTL_REGS_STATUS_MUX_CTRL_STATUS_MUX_EN_MASK 0x0001 3054 #define CTL_REGS_STATUS_MUX_CTRL_STATUS_MUX_EN_ALIGN 0 3055 #define CTL_REGS_STATUS_MUX_CTRL_STATUS_MUX_EN_BITS 1 3056 #define CTL_REGS_STATUS_MUX_CTRL_STATUS_MUX_EN_SHIFT 0 3057 3058 3059 /**************************************************************************** 3060 * ctl_regs :: seisr 3061 */ 3062 /* ctl_regs :: seisr :: reserved0 [15:06] */ 3063 #define CTL_REGS_SEISR_RESERVED0_MASK 0xffc0 3064 #define CTL_REGS_SEISR_RESERVED0_ALIGN 0 3065 #define CTL_REGS_SEISR_RESERVED0_BITS 10 3066 #define CTL_REGS_SEISR_RESERVED0_SHIFT 6 3067 3068 /* ctl_regs :: seisr :: found_sys_sigdet [05:05] */ 3069 #define CTL_REGS_SEISR_FOUND_SYS_SIGDET_MASK 0x0020 3070 #define CTL_REGS_SEISR_FOUND_SYS_SIGDET_ALIGN 0 3071 #define CTL_REGS_SEISR_FOUND_SYS_SIGDET_BITS 1 3072 #define CTL_REGS_SEISR_FOUND_SYS_SIGDET_SHIFT 5 3073 3074 /* ctl_regs :: seisr :: lost_sys_sigdet [04:04] */ 3075 #define CTL_REGS_SEISR_LOST_SYS_SIGDET_MASK 0x0010 3076 #define CTL_REGS_SEISR_LOST_SYS_SIGDET_ALIGN 0 3077 #define CTL_REGS_SEISR_LOST_SYS_SIGDET_BITS 1 3078 #define CTL_REGS_SEISR_LOST_SYS_SIGDET_SHIFT 4 3079 3080 /* ctl_regs :: seisr :: found_sys_pll_lock [03:03] */ 3081 #define CTL_REGS_SEISR_FOUND_SYS_PLL_LOCK_MASK 0x0008 3082 #define CTL_REGS_SEISR_FOUND_SYS_PLL_LOCK_ALIGN 0 3083 #define CTL_REGS_SEISR_FOUND_SYS_PLL_LOCK_BITS 1 3084 #define CTL_REGS_SEISR_FOUND_SYS_PLL_LOCK_SHIFT 3 3085 3086 /* ctl_regs :: seisr :: lost_sys_pll_lock [02:02] */ 3087 #define CTL_REGS_SEISR_LOST_SYS_PLL_LOCK_MASK 0x0004 3088 #define CTL_REGS_SEISR_LOST_SYS_PLL_LOCK_ALIGN 0 3089 #define CTL_REGS_SEISR_LOST_SYS_PLL_LOCK_BITS 1 3090 #define CTL_REGS_SEISR_LOST_SYS_PLL_LOCK_SHIFT 2 3091 3092 /* ctl_regs :: seisr :: found_sys_cdr_lock [01:01] */ 3093 #define CTL_REGS_SEISR_FOUND_SYS_CDR_LOCK_MASK 0x0002 3094 #define CTL_REGS_SEISR_FOUND_SYS_CDR_LOCK_ALIGN 0 3095 #define CTL_REGS_SEISR_FOUND_SYS_CDR_LOCK_BITS 1 3096 #define CTL_REGS_SEISR_FOUND_SYS_CDR_LOCK_SHIFT 1 3097 3098 /* ctl_regs :: seisr :: lost_sys_cdr_lock [00:00] */ 3099 #define CTL_REGS_SEISR_LOST_SYS_CDR_LOCK_MASK 0x0001 3100 #define CTL_REGS_SEISR_LOST_SYS_CDR_LOCK_ALIGN 0 3101 #define CTL_REGS_SEISR_LOST_SYS_CDR_LOCK_BITS 1 3102 #define CTL_REGS_SEISR_LOST_SYS_CDR_LOCK_SHIFT 0 3103 3104 3105 /**************************************************************************** 3106 * ctl_regs :: seimr 3107 */ 3108 /* ctl_regs :: seimr :: reserved0 [15:06] */ 3109 #define CTL_REGS_SEIMR_RESERVED0_MASK 0xffc0 3110 #define CTL_REGS_SEIMR_RESERVED0_ALIGN 0 3111 #define CTL_REGS_SEIMR_RESERVED0_BITS 10 3112 #define CTL_REGS_SEIMR_RESERVED0_SHIFT 6 3113 3114 /* ctl_regs :: seimr :: mask_found_sys_sigdet [05:05] */ 3115 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_SIGDET_MASK 0x0020 3116 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_SIGDET_ALIGN 0 3117 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_SIGDET_BITS 1 3118 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_SIGDET_SHIFT 5 3119 3120 /* ctl_regs :: seimr :: mask_lost_sys_sigdet [04:04] */ 3121 #define CTL_REGS_SEIMR_MASK_LOST_SYS_SIGDET_MASK 0x0010 3122 #define CTL_REGS_SEIMR_MASK_LOST_SYS_SIGDET_ALIGN 0 3123 #define CTL_REGS_SEIMR_MASK_LOST_SYS_SIGDET_BITS 1 3124 #define CTL_REGS_SEIMR_MASK_LOST_SYS_SIGDET_SHIFT 4 3125 3126 /* ctl_regs :: seimr :: mask_found_sys_pll_lock [03:03] */ 3127 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_PLL_LOCK_MASK 0x0008 3128 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_PLL_LOCK_ALIGN 0 3129 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_PLL_LOCK_BITS 1 3130 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_PLL_LOCK_SHIFT 3 3131 3132 /* ctl_regs :: seimr :: mask_lost_sys_pll_lock [02:02] */ 3133 #define CTL_REGS_SEIMR_MASK_LOST_SYS_PLL_LOCK_MASK 0x0004 3134 #define CTL_REGS_SEIMR_MASK_LOST_SYS_PLL_LOCK_ALIGN 0 3135 #define CTL_REGS_SEIMR_MASK_LOST_SYS_PLL_LOCK_BITS 1 3136 #define CTL_REGS_SEIMR_MASK_LOST_SYS_PLL_LOCK_SHIFT 2 3137 3138 /* ctl_regs :: seimr :: mask_found_sys_cdr_lock [01:01] */ 3139 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_CDR_LOCK_MASK 0x0002 3140 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_CDR_LOCK_ALIGN 0 3141 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_CDR_LOCK_BITS 1 3142 #define CTL_REGS_SEIMR_MASK_FOUND_SYS_CDR_LOCK_SHIFT 1 3143 3144 /* ctl_regs :: seimr :: mask_lost_sys_cdr_lock [00:00] */ 3145 #define CTL_REGS_SEIMR_MASK_LOST_SYS_CDR_LOCK_MASK 0x0001 3146 #define CTL_REGS_SEIMR_MASK_LOST_SYS_CDR_LOCK_ALIGN 0 3147 #define CTL_REGS_SEIMR_MASK_LOST_SYS_CDR_LOCK_BITS 1 3148 #define CTL_REGS_SEIMR_MASK_LOST_SYS_CDR_LOCK_SHIFT 0 3149 3150 3151 /**************************************************************************** 3152 * ctl_regs :: seipr 3153 */ 3154 /* ctl_regs :: seipr :: reserved0 [15:06] */ 3155 #define CTL_REGS_SEIPR_RESERVED0_MASK 0xffc0 3156 #define CTL_REGS_SEIPR_RESERVED0_ALIGN 0 3157 #define CTL_REGS_SEIPR_RESERVED0_BITS 10 3158 #define CTL_REGS_SEIPR_RESERVED0_SHIFT 6 3159 3160 /* ctl_regs :: seipr :: p_found_sys_sigdet [05:05] */ 3161 #define CTL_REGS_SEIPR_P_FOUND_SYS_SIGDET_MASK 0x0020 3162 #define CTL_REGS_SEIPR_P_FOUND_SYS_SIGDET_ALIGN 0 3163 #define CTL_REGS_SEIPR_P_FOUND_SYS_SIGDET_BITS 1 3164 #define CTL_REGS_SEIPR_P_FOUND_SYS_SIGDET_SHIFT 5 3165 3166 /* ctl_regs :: seipr :: p_lost_sys_sigdet [04:04] */ 3167 #define CTL_REGS_SEIPR_P_LOST_SYS_SIGDET_MASK 0x0010 3168 #define CTL_REGS_SEIPR_P_LOST_SYS_SIGDET_ALIGN 0 3169 #define CTL_REGS_SEIPR_P_LOST_SYS_SIGDET_BITS 1 3170 #define CTL_REGS_SEIPR_P_LOST_SYS_SIGDET_SHIFT 4 3171 3172 /* ctl_regs :: seipr :: p_found_sys_pll_lock [03:03] */ 3173 #define CTL_REGS_SEIPR_P_FOUND_SYS_PLL_LOCK_MASK 0x0008 3174 #define CTL_REGS_SEIPR_P_FOUND_SYS_PLL_LOCK_ALIGN 0 3175 #define CTL_REGS_SEIPR_P_FOUND_SYS_PLL_LOCK_BITS 1 3176 #define CTL_REGS_SEIPR_P_FOUND_SYS_PLL_LOCK_SHIFT 3 3177 3178 /* ctl_regs :: seipr :: p_lost_sys_pll_lock [02:02] */ 3179 #define CTL_REGS_SEIPR_P_LOST_SYS_PLL_LOCK_MASK 0x0004 3180 #define CTL_REGS_SEIPR_P_LOST_SYS_PLL_LOCK_ALIGN 0 3181 #define CTL_REGS_SEIPR_P_LOST_SYS_PLL_LOCK_BITS 1 3182 #define CTL_REGS_SEIPR_P_LOST_SYS_PLL_LOCK_SHIFT 2 3183 3184 /* ctl_regs :: seipr :: p_found_sys_cdr_lock [01:01] */ 3185 #define CTL_REGS_SEIPR_P_FOUND_SYS_CDR_LOCK_MASK 0x0002 3186 #define CTL_REGS_SEIPR_P_FOUND_SYS_CDR_LOCK_ALIGN 0 3187 #define CTL_REGS_SEIPR_P_FOUND_SYS_CDR_LOCK_BITS 1 3188 #define CTL_REGS_SEIPR_P_FOUND_SYS_CDR_LOCK_SHIFT 1 3189 3190 /* ctl_regs :: seipr :: p_lost_sys_cdr_lock [00:00] */ 3191 #define CTL_REGS_SEIPR_P_LOST_SYS_CDR_LOCK_MASK 0x0001 3192 #define CTL_REGS_SEIPR_P_LOST_SYS_CDR_LOCK_ALIGN 0 3193 #define CTL_REGS_SEIPR_P_LOST_SYS_CDR_LOCK_BITS 1 3194 #define CTL_REGS_SEIPR_P_LOST_SYS_CDR_LOCK_SHIFT 0 3195 3196 3197 /**************************************************************************** 3198 * ctl_regs :: leisr 3199 */ 3200 /* ctl_regs :: leisr :: reserved0 [15:08] */ 3201 #define CTL_REGS_LEISR_RESERVED0_MASK 0xff00 3202 #define CTL_REGS_LEISR_RESERVED0_ALIGN 0 3203 #define CTL_REGS_LEISR_RESERVED0_BITS 8 3204 #define CTL_REGS_LEISR_RESERVED0_SHIFT 8 3205 3206 /* ctl_regs :: leisr :: found_line_sigdet [07:07] */ 3207 #define CTL_REGS_LEISR_FOUND_LINE_SIGDET_MASK 0x0080 3208 #define CTL_REGS_LEISR_FOUND_LINE_SIGDET_ALIGN 0 3209 #define CTL_REGS_LEISR_FOUND_LINE_SIGDET_BITS 1 3210 #define CTL_REGS_LEISR_FOUND_LINE_SIGDET_SHIFT 7 3211 3212 /* ctl_regs :: leisr :: lost_line_sigdet [06:06] */ 3213 #define CTL_REGS_LEISR_LOST_LINE_SIGDET_MASK 0x0040 3214 #define CTL_REGS_LEISR_LOST_LINE_SIGDET_ALIGN 0 3215 #define CTL_REGS_LEISR_LOST_LINE_SIGDET_BITS 1 3216 #define CTL_REGS_LEISR_LOST_LINE_SIGDET_SHIFT 6 3217 3218 /* ctl_regs :: leisr :: found_line_rx_pll_lock [05:05] */ 3219 #define CTL_REGS_LEISR_FOUND_LINE_RX_PLL_LOCK_MASK 0x0020 3220 #define CTL_REGS_LEISR_FOUND_LINE_RX_PLL_LOCK_ALIGN 0 3221 #define CTL_REGS_LEISR_FOUND_LINE_RX_PLL_LOCK_BITS 1 3222 #define CTL_REGS_LEISR_FOUND_LINE_RX_PLL_LOCK_SHIFT 5 3223 3224 /* ctl_regs :: leisr :: lost_line_rx_pll_lock [04:04] */ 3225 #define CTL_REGS_LEISR_LOST_LINE_RX_PLL_LOCK_MASK 0x0010 3226 #define CTL_REGS_LEISR_LOST_LINE_RX_PLL_LOCK_ALIGN 0 3227 #define CTL_REGS_LEISR_LOST_LINE_RX_PLL_LOCK_BITS 1 3228 #define CTL_REGS_LEISR_LOST_LINE_RX_PLL_LOCK_SHIFT 4 3229 3230 /* ctl_regs :: leisr :: found_line_tx_pll_lock [03:03] */ 3231 #define CTL_REGS_LEISR_FOUND_LINE_TX_PLL_LOCK_MASK 0x0008 3232 #define CTL_REGS_LEISR_FOUND_LINE_TX_PLL_LOCK_ALIGN 0 3233 #define CTL_REGS_LEISR_FOUND_LINE_TX_PLL_LOCK_BITS 1 3234 #define CTL_REGS_LEISR_FOUND_LINE_TX_PLL_LOCK_SHIFT 3 3235 3236 /* ctl_regs :: leisr :: lost_line_tx_pll_lock [02:02] */ 3237 #define CTL_REGS_LEISR_LOST_LINE_TX_PLL_LOCK_MASK 0x0004 3238 #define CTL_REGS_LEISR_LOST_LINE_TX_PLL_LOCK_ALIGN 0 3239 #define CTL_REGS_LEISR_LOST_LINE_TX_PLL_LOCK_BITS 1 3240 #define CTL_REGS_LEISR_LOST_LINE_TX_PLL_LOCK_SHIFT 2 3241 3242 /* ctl_regs :: leisr :: found_line_cdr_lock [01:01] */ 3243 #define CTL_REGS_LEISR_FOUND_LINE_CDR_LOCK_MASK 0x0002 3244 #define CTL_REGS_LEISR_FOUND_LINE_CDR_LOCK_ALIGN 0 3245 #define CTL_REGS_LEISR_FOUND_LINE_CDR_LOCK_BITS 1 3246 #define CTL_REGS_LEISR_FOUND_LINE_CDR_LOCK_SHIFT 1 3247 3248 /* ctl_regs :: leisr :: lost_line_cdr_lock [00:00] */ 3249 #define CTL_REGS_LEISR_LOST_LINE_CDR_LOCK_MASK 0x0001 3250 #define CTL_REGS_LEISR_LOST_LINE_CDR_LOCK_ALIGN 0 3251 #define CTL_REGS_LEISR_LOST_LINE_CDR_LOCK_BITS 1 3252 #define CTL_REGS_LEISR_LOST_LINE_CDR_LOCK_SHIFT 0 3253 3254 3255 /**************************************************************************** 3256 * ctl_regs :: leimr 3257 */ 3258 /* ctl_regs :: leimr :: reserved0 [15:08] */ 3259 #define CTL_REGS_LEIMR_RESERVED0_MASK 0xff00 3260 #define CTL_REGS_LEIMR_RESERVED0_ALIGN 0 3261 #define CTL_REGS_LEIMR_RESERVED0_BITS 8 3262 #define CTL_REGS_LEIMR_RESERVED0_SHIFT 8 3263 3264 /* ctl_regs :: leimr :: mask_found_line_sigdet [07:07] */ 3265 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_SIGDET_MASK 0x0080 3266 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_SIGDET_ALIGN 0 3267 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_SIGDET_BITS 1 3268 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_SIGDET_SHIFT 7 3269 3270 /* ctl_regs :: leimr :: mask_lost_line_sigdet [06:06] */ 3271 #define CTL_REGS_LEIMR_MASK_LOST_LINE_SIGDET_MASK 0x0040 3272 #define CTL_REGS_LEIMR_MASK_LOST_LINE_SIGDET_ALIGN 0 3273 #define CTL_REGS_LEIMR_MASK_LOST_LINE_SIGDET_BITS 1 3274 #define CTL_REGS_LEIMR_MASK_LOST_LINE_SIGDET_SHIFT 6 3275 3276 /* ctl_regs :: leimr :: mask_found_line_rx_pll_lock [05:05] */ 3277 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_RX_PLL_LOCK_MASK 0x0020 3278 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_RX_PLL_LOCK_ALIGN 0 3279 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_RX_PLL_LOCK_BITS 1 3280 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_RX_PLL_LOCK_SHIFT 5 3281 3282 /* ctl_regs :: leimr :: mask_lost_line_rx_pll_lock [04:04] */ 3283 #define CTL_REGS_LEIMR_MASK_LOST_LINE_RX_PLL_LOCK_MASK 0x0010 3284 #define CTL_REGS_LEIMR_MASK_LOST_LINE_RX_PLL_LOCK_ALIGN 0 3285 #define CTL_REGS_LEIMR_MASK_LOST_LINE_RX_PLL_LOCK_BITS 1 3286 #define CTL_REGS_LEIMR_MASK_LOST_LINE_RX_PLL_LOCK_SHIFT 4 3287 3288 /* ctl_regs :: leimr :: mask_found_line_tx_pll_lock [03:03] */ 3289 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_TX_PLL_LOCK_MASK 0x0008 3290 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_TX_PLL_LOCK_ALIGN 0 3291 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_TX_PLL_LOCK_BITS 1 3292 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_TX_PLL_LOCK_SHIFT 3 3293 3294 /* ctl_regs :: leimr :: mask_lost_line_tx_pll_lock [02:02] */ 3295 #define CTL_REGS_LEIMR_MASK_LOST_LINE_TX_PLL_LOCK_MASK 0x0004 3296 #define CTL_REGS_LEIMR_MASK_LOST_LINE_TX_PLL_LOCK_ALIGN 0 3297 #define CTL_REGS_LEIMR_MASK_LOST_LINE_TX_PLL_LOCK_BITS 1 3298 #define CTL_REGS_LEIMR_MASK_LOST_LINE_TX_PLL_LOCK_SHIFT 2 3299 3300 /* ctl_regs :: leimr :: mask_found_line_cdr_lock [01:01] */ 3301 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_CDR_LOCK_MASK 0x0002 3302 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_CDR_LOCK_ALIGN 0 3303 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_CDR_LOCK_BITS 1 3304 #define CTL_REGS_LEIMR_MASK_FOUND_LINE_CDR_LOCK_SHIFT 1 3305 3306 /* ctl_regs :: leimr :: mask_lost_line_cdr_lock [00:00] */ 3307 #define CTL_REGS_LEIMR_MASK_LOST_LINE_CDR_LOCK_MASK 0x0001 3308 #define CTL_REGS_LEIMR_MASK_LOST_LINE_CDR_LOCK_ALIGN 0 3309 #define CTL_REGS_LEIMR_MASK_LOST_LINE_CDR_LOCK_BITS 1 3310 #define CTL_REGS_LEIMR_MASK_LOST_LINE_CDR_LOCK_SHIFT 0 3311 3312 3313 /**************************************************************************** 3314 * ctl_regs :: leipr 3315 */ 3316 /* ctl_regs :: leipr :: reserved0 [15:08] */ 3317 #define CTL_REGS_LEIPR_RESERVED0_MASK 0xff00 3318 #define CTL_REGS_LEIPR_RESERVED0_ALIGN 0 3319 #define CTL_REGS_LEIPR_RESERVED0_BITS 8 3320 #define CTL_REGS_LEIPR_RESERVED0_SHIFT 8 3321 3322 /* ctl_regs :: leipr :: p_found_line_sigdet [07:07] */ 3323 #define CTL_REGS_LEIPR_P_FOUND_LINE_SIGDET_MASK 0x0080 3324 #define CTL_REGS_LEIPR_P_FOUND_LINE_SIGDET_ALIGN 0 3325 #define CTL_REGS_LEIPR_P_FOUND_LINE_SIGDET_BITS 1 3326 #define CTL_REGS_LEIPR_P_FOUND_LINE_SIGDET_SHIFT 7 3327 3328 /* ctl_regs :: leipr :: p_lost_line_sigdet [06:06] */ 3329 #define CTL_REGS_LEIPR_P_LOST_LINE_SIGDET_MASK 0x0040 3330 #define CTL_REGS_LEIPR_P_LOST_LINE_SIGDET_ALIGN 0 3331 #define CTL_REGS_LEIPR_P_LOST_LINE_SIGDET_BITS 1 3332 #define CTL_REGS_LEIPR_P_LOST_LINE_SIGDET_SHIFT 6 3333 3334 /* ctl_regs :: leipr :: p_found_line_rx_pll_lock [05:05] */ 3335 #define CTL_REGS_LEIPR_P_FOUND_LINE_RX_PLL_LOCK_MASK 0x0020 3336 #define CTL_REGS_LEIPR_P_FOUND_LINE_RX_PLL_LOCK_ALIGN 0 3337 #define CTL_REGS_LEIPR_P_FOUND_LINE_RX_PLL_LOCK_BITS 1 3338 #define CTL_REGS_LEIPR_P_FOUND_LINE_RX_PLL_LOCK_SHIFT 5 3339 3340 /* ctl_regs :: leipr :: p_lost_line_rx_pll_lock [04:04] */ 3341 #define CTL_REGS_LEIPR_P_LOST_LINE_RX_PLL_LOCK_MASK 0x0010 3342 #define CTL_REGS_LEIPR_P_LOST_LINE_RX_PLL_LOCK_ALIGN 0 3343 #define CTL_REGS_LEIPR_P_LOST_LINE_RX_PLL_LOCK_BITS 1 3344 #define CTL_REGS_LEIPR_P_LOST_LINE_RX_PLL_LOCK_SHIFT 4 3345 3346 /* ctl_regs :: leipr :: p_found_line_tx_pll_lock [03:03] */ 3347 #define CTL_REGS_LEIPR_P_FOUND_LINE_TX_PLL_LOCK_MASK 0x0008 3348 #define CTL_REGS_LEIPR_P_FOUND_LINE_TX_PLL_LOCK_ALIGN 0 3349 #define CTL_REGS_LEIPR_P_FOUND_LINE_TX_PLL_LOCK_BITS 1 3350 #define CTL_REGS_LEIPR_P_FOUND_LINE_TX_PLL_LOCK_SHIFT 3 3351 3352 /* ctl_regs :: leipr :: p_lost_line_tx_pll_lock [02:02] */ 3353 #define CTL_REGS_LEIPR_P_LOST_LINE_TX_PLL_LOCK_MASK 0x0004 3354 #define CTL_REGS_LEIPR_P_LOST_LINE_TX_PLL_LOCK_ALIGN 0 3355 #define CTL_REGS_LEIPR_P_LOST_LINE_TX_PLL_LOCK_BITS 1 3356 #define CTL_REGS_LEIPR_P_LOST_LINE_TX_PLL_LOCK_SHIFT 2 3357 3358 /* ctl_regs :: leipr :: p_found_line_cdr_lock [01:01] */ 3359 #define CTL_REGS_LEIPR_P_FOUND_LINE_CDR_LOCK_MASK 0x0002 3360 #define CTL_REGS_LEIPR_P_FOUND_LINE_CDR_LOCK_ALIGN 0 3361 #define CTL_REGS_LEIPR_P_FOUND_LINE_CDR_LOCK_BITS 1 3362 #define CTL_REGS_LEIPR_P_FOUND_LINE_CDR_LOCK_SHIFT 1 3363 3364 /* ctl_regs :: leipr :: p_lost_line_cdr_lock [00:00] */ 3365 #define CTL_REGS_LEIPR_P_LOST_LINE_CDR_LOCK_MASK 0x0001 3366 #define CTL_REGS_LEIPR_P_LOST_LINE_CDR_LOCK_ALIGN 0 3367 #define CTL_REGS_LEIPR_P_LOST_LINE_CDR_LOCK_BITS 1 3368 #define CTL_REGS_LEIPR_P_LOST_LINE_CDR_LOCK_SHIFT 0 3369 3370 3371 /**************************************************************************** 3372 * ctl_regs :: susm_cm_ctrl1 3373 */ 3374 /* ctl_regs :: susm_cm_ctrl1 :: reserved0 [15:15] */ 3375 #define CTL_REGS_SUSM_CM_CTRL1_RESERVED0_MASK 0x8000 3376 #define CTL_REGS_SUSM_CM_CTRL1_RESERVED0_ALIGN 0 3377 #define CTL_REGS_SUSM_CM_CTRL1_RESERVED0_BITS 1 3378 #define CTL_REGS_SUSM_CM_CTRL1_RESERVED0_SHIFT 15 3379 3380 /* ctl_regs :: susm_cm_ctrl1 :: susm_rescal_frc [14:14] */ 3381 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_RESCAL_FRC_MASK 0x4000 3382 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_RESCAL_FRC_ALIGN 0 3383 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_RESCAL_FRC_BITS 1 3384 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_RESCAL_FRC_SHIFT 14 3385 3386 /* ctl_regs :: susm_cm_ctrl1 :: susm_rescal_frcval [13:13] */ 3387 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_RESCAL_FRCVAL_MASK 0x2000 3388 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_RESCAL_FRCVAL_ALIGN 0 3389 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_RESCAL_FRCVAL_BITS 1 3390 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_RESCAL_FRCVAL_SHIFT 13 3391 3392 /* ctl_regs :: susm_cm_ctrl1 :: susm_afe_pll_mode_frc [12:12] */ 3393 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_PLL_MODE_FRC_MASK 0x1000 3394 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_PLL_MODE_FRC_ALIGN 0 3395 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_PLL_MODE_FRC_BITS 1 3396 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_PLL_MODE_FRC_SHIFT 12 3397 3398 /* ctl_regs :: susm_cm_ctrl1 :: susm_afe_pll_mode_frcval [11:10] */ 3399 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_PLL_MODE_FRCVAL_MASK 0x0c00 3400 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_PLL_MODE_FRCVAL_ALIGN 0 3401 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_PLL_MODE_FRCVAL_BITS 2 3402 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_PLL_MODE_FRCVAL_SHIFT 10 3403 3404 /* ctl_regs :: susm_cm_ctrl1 :: susm_afe_ref_mode_frc [09:09] */ 3405 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_REF_MODE_FRC_MASK 0x0200 3406 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_REF_MODE_FRC_ALIGN 0 3407 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_REF_MODE_FRC_BITS 1 3408 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_REF_MODE_FRC_SHIFT 9 3409 3410 /* ctl_regs :: susm_cm_ctrl1 :: susm_afe_ref_mode_frcval [08:07] */ 3411 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_REF_MODE_FRCVAL_MASK 0x0180 3412 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_REF_MODE_FRCVAL_ALIGN 0 3413 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_REF_MODE_FRCVAL_BITS 2 3414 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_AFE_REF_MODE_FRCVAL_SHIFT 7 3415 3416 /* ctl_regs :: susm_cm_ctrl1 :: susm_tca_en_frc [06:06] */ 3417 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_TCA_EN_FRC_MASK 0x0040 3418 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_TCA_EN_FRC_ALIGN 0 3419 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_TCA_EN_FRC_BITS 1 3420 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_TCA_EN_FRC_SHIFT 6 3421 3422 /* ctl_regs :: susm_cm_ctrl1 :: susm_tca_en_frcval [05:05] */ 3423 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_TCA_EN_FRCVAL_MASK 0x0020 3424 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_TCA_EN_FRCVAL_ALIGN 0 3425 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_TCA_EN_FRCVAL_BITS 1 3426 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_TCA_EN_FRCVAL_SHIFT 5 3427 3428 /* ctl_regs :: susm_cm_ctrl1 :: susm_cm_modesel_trigger_frc [04:04] */ 3429 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_MODESEL_TRIGGER_FRC_MASK 0x0010 3430 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_MODESEL_TRIGGER_FRC_ALIGN 0 3431 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_MODESEL_TRIGGER_FRC_BITS 1 3432 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_MODESEL_TRIGGER_FRC_SHIFT 4 3433 3434 /* ctl_regs :: susm_cm_ctrl1 :: susm_cm_modesel_trigger_frcval [03:03] */ 3435 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_MODESEL_TRIGGER_FRCVAL_MASK 0x0008 3436 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_MODESEL_TRIGGER_FRCVAL_ALIGN 0 3437 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_MODESEL_TRIGGER_FRCVAL_BITS 1 3438 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_MODESEL_TRIGGER_FRCVAL_SHIFT 3 3439 3440 /* ctl_regs :: susm_cm_ctrl1 :: susm_cm_trigger_frc [02:02] */ 3441 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_TRIGGER_FRC_MASK 0x0004 3442 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_TRIGGER_FRC_ALIGN 0 3443 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_TRIGGER_FRC_BITS 1 3444 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_TRIGGER_FRC_SHIFT 2 3445 3446 /* ctl_regs :: susm_cm_ctrl1 :: susm_cm_trigger_frcval [01:01] */ 3447 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_TRIGGER_FRCVAL_MASK 0x0002 3448 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_TRIGGER_FRCVAL_ALIGN 0 3449 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_TRIGGER_FRCVAL_BITS 1 3450 #define CTL_REGS_SUSM_CM_CTRL1_SUSM_CM_TRIGGER_FRCVAL_SHIFT 1 3451 3452 /* ctl_regs :: susm_cm_ctrl1 :: dis_susm_cm [00:00] */ 3453 #define CTL_REGS_SUSM_CM_CTRL1_DIS_SUSM_CM_MASK 0x0001 3454 #define CTL_REGS_SUSM_CM_CTRL1_DIS_SUSM_CM_ALIGN 0 3455 #define CTL_REGS_SUSM_CM_CTRL1_DIS_SUSM_CM_BITS 1 3456 #define CTL_REGS_SUSM_CM_CTRL1_DIS_SUSM_CM_SHIFT 0 3457 3458 3459 /**************************************************************************** 3460 * ctl_regs :: susm_ltx_ctrl1 3461 */ 3462 /* ctl_regs :: susm_ltx_ctrl1 :: reserved0 [15:12] */ 3463 #define CTL_REGS_SUSM_LTX_CTRL1_RESERVED0_MASK 0xf000 3464 #define CTL_REGS_SUSM_LTX_CTRL1_RESERVED0_ALIGN 0 3465 #define CTL_REGS_SUSM_LTX_CTRL1_RESERVED0_BITS 4 3466 #define CTL_REGS_SUSM_LTX_CTRL1_RESERVED0_SHIFT 12 3467 3468 /* ctl_regs :: susm_ltx_ctrl1 :: dis_hstx_pi_lock [11:11] */ 3469 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_HSTX_PI_LOCK_MASK 0x0800 3470 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_HSTX_PI_LOCK_ALIGN 0 3471 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_HSTX_PI_LOCK_BITS 1 3472 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_HSTX_PI_LOCK_SHIFT 11 3473 3474 /* ctl_regs :: susm_ltx_ctrl1 :: dis_hc_tx_pi_lock [10:10] */ 3475 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_HC_TX_PI_LOCK_MASK 0x0400 3476 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_HC_TX_PI_LOCK_ALIGN 0 3477 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_HC_TX_PI_LOCK_BITS 1 3478 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_HC_TX_PI_LOCK_SHIFT 10 3479 3480 /* ctl_regs :: susm_ltx_ctrl1 :: hc_tx_tca_start [09:09] */ 3481 #define CTL_REGS_SUSM_LTX_CTRL1_HC_TX_TCA_START_MASK 0x0200 3482 #define CTL_REGS_SUSM_LTX_CTRL1_HC_TX_TCA_START_ALIGN 0 3483 #define CTL_REGS_SUSM_LTX_CTRL1_HC_TX_TCA_START_BITS 1 3484 #define CTL_REGS_SUSM_LTX_CTRL1_HC_TX_TCA_START_SHIFT 9 3485 3486 /* ctl_regs :: susm_ltx_ctrl1 :: hc_tx_tca_enable [08:08] */ 3487 #define CTL_REGS_SUSM_LTX_CTRL1_HC_TX_TCA_ENABLE_MASK 0x0100 3488 #define CTL_REGS_SUSM_LTX_CTRL1_HC_TX_TCA_ENABLE_ALIGN 0 3489 #define CTL_REGS_SUSM_LTX_CTRL1_HC_TX_TCA_ENABLE_BITS 1 3490 #define CTL_REGS_SUSM_LTX_CTRL1_HC_TX_TCA_ENABLE_SHIFT 8 3491 3492 /* ctl_regs :: susm_ltx_ctrl1 :: restart_tca [07:07] */ 3493 #define CTL_REGS_SUSM_LTX_CTRL1_RESTART_TCA_MASK 0x0080 3494 #define CTL_REGS_SUSM_LTX_CTRL1_RESTART_TCA_ALIGN 0 3495 #define CTL_REGS_SUSM_LTX_CTRL1_RESTART_TCA_BITS 1 3496 #define CTL_REGS_SUSM_LTX_CTRL1_RESTART_TCA_SHIFT 7 3497 3498 /* ctl_regs :: susm_ltx_ctrl1 :: ltx_tca_enable_frc [06:06] */ 3499 #define CTL_REGS_SUSM_LTX_CTRL1_LTX_TCA_ENABLE_FRC_MASK 0x0040 3500 #define CTL_REGS_SUSM_LTX_CTRL1_LTX_TCA_ENABLE_FRC_ALIGN 0 3501 #define CTL_REGS_SUSM_LTX_CTRL1_LTX_TCA_ENABLE_FRC_BITS 1 3502 #define CTL_REGS_SUSM_LTX_CTRL1_LTX_TCA_ENABLE_FRC_SHIFT 6 3503 3504 /* ctl_regs :: susm_ltx_ctrl1 :: ltx_tca_enable_frcval [05:05] */ 3505 #define CTL_REGS_SUSM_LTX_CTRL1_LTX_TCA_ENABLE_FRCVAL_MASK 0x0020 3506 #define CTL_REGS_SUSM_LTX_CTRL1_LTX_TCA_ENABLE_FRCVAL_ALIGN 0 3507 #define CTL_REGS_SUSM_LTX_CTRL1_LTX_TCA_ENABLE_FRCVAL_BITS 1 3508 #define CTL_REGS_SUSM_LTX_CTRL1_LTX_TCA_ENABLE_FRCVAL_SHIFT 5 3509 3510 /* ctl_regs :: susm_ltx_ctrl1 :: susm_ltx_tca_start_frc [04:04] */ 3511 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TCA_START_FRC_MASK 0x0010 3512 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TCA_START_FRC_ALIGN 0 3513 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TCA_START_FRC_BITS 1 3514 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TCA_START_FRC_SHIFT 4 3515 3516 /* ctl_regs :: susm_ltx_ctrl1 :: susm_ltx_tca_start_frcval [03:03] */ 3517 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TCA_START_FRCVAL_MASK 0x0008 3518 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TCA_START_FRCVAL_ALIGN 0 3519 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TCA_START_FRCVAL_BITS 1 3520 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TCA_START_FRCVAL_SHIFT 3 3521 3522 /* ctl_regs :: susm_ltx_ctrl1 :: susm_ltx_trigger_frc [02:02] */ 3523 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TRIGGER_FRC_MASK 0x0004 3524 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TRIGGER_FRC_ALIGN 0 3525 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TRIGGER_FRC_BITS 1 3526 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TRIGGER_FRC_SHIFT 2 3527 3528 /* ctl_regs :: susm_ltx_ctrl1 :: susm_ltx_trigger_frcval [01:01] */ 3529 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TRIGGER_FRCVAL_MASK 0x0002 3530 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TRIGGER_FRCVAL_ALIGN 0 3531 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TRIGGER_FRCVAL_BITS 1 3532 #define CTL_REGS_SUSM_LTX_CTRL1_SUSM_LTX_TRIGGER_FRCVAL_SHIFT 1 3533 3534 /* ctl_regs :: susm_ltx_ctrl1 :: dis_susm_ltx [00:00] */ 3535 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_SUSM_LTX_MASK 0x0001 3536 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_SUSM_LTX_ALIGN 0 3537 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_SUSM_LTX_BITS 1 3538 #define CTL_REGS_SUSM_LTX_CTRL1_DIS_SUSM_LTX_SHIFT 0 3539 3540 3541 /**************************************************************************** 3542 * ctl_regs :: susm_ltx_ctrl2 3543 */ 3544 /* ctl_regs :: susm_ltx_ctrl2 :: reserved0 [15:10] */ 3545 #define CTL_REGS_SUSM_LTX_CTRL2_RESERVED0_MASK 0xfc00 3546 #define CTL_REGS_SUSM_LTX_CTRL2_RESERVED0_ALIGN 0 3547 #define CTL_REGS_SUSM_LTX_CTRL2_RESERVED0_BITS 6 3548 #define CTL_REGS_SUSM_LTX_CTRL2_RESERVED0_SHIFT 10 3549 3550 /* ctl_regs :: susm_ltx_ctrl2 :: susm_ltx_rdy_frc [09:00] */ 3551 #define CTL_REGS_SUSM_LTX_CTRL2_SUSM_LTX_RDY_FRC_MASK 0x03ff 3552 #define CTL_REGS_SUSM_LTX_CTRL2_SUSM_LTX_RDY_FRC_ALIGN 0 3553 #define CTL_REGS_SUSM_LTX_CTRL2_SUSM_LTX_RDY_FRC_BITS 10 3554 #define CTL_REGS_SUSM_LTX_CTRL2_SUSM_LTX_RDY_FRC_SHIFT 0 3555 3556 3557 /**************************************************************************** 3558 * ctl_regs :: susm_ltx_ctrl3 3559 */ 3560 /* ctl_regs :: susm_ltx_ctrl3 :: reserved0 [15:10] */ 3561 #define CTL_REGS_SUSM_LTX_CTRL3_RESERVED0_MASK 0xfc00 3562 #define CTL_REGS_SUSM_LTX_CTRL3_RESERVED0_ALIGN 0 3563 #define CTL_REGS_SUSM_LTX_CTRL3_RESERVED0_BITS 6 3564 #define CTL_REGS_SUSM_LTX_CTRL3_RESERVED0_SHIFT 10 3565 3566 /* ctl_regs :: susm_ltx_ctrl3 :: susm_ltx_rdy_frcval [09:00] */ 3567 #define CTL_REGS_SUSM_LTX_CTRL3_SUSM_LTX_RDY_FRCVAL_MASK 0x03ff 3568 #define CTL_REGS_SUSM_LTX_CTRL3_SUSM_LTX_RDY_FRCVAL_ALIGN 0 3569 #define CTL_REGS_SUSM_LTX_CTRL3_SUSM_LTX_RDY_FRCVAL_BITS 10 3570 #define CTL_REGS_SUSM_LTX_CTRL3_SUSM_LTX_RDY_FRCVAL_SHIFT 0 3571 3572 3573 /**************************************************************************** 3574 * ctl_regs :: susm_ltx_ctrl4 3575 */ 3576 /* ctl_regs :: susm_ltx_ctrl4 :: susm_tpc_clk_en_frc [15:12] */ 3577 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_CLK_EN_FRC_MASK 0xf000 3578 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_CLK_EN_FRC_ALIGN 0 3579 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_CLK_EN_FRC_BITS 4 3580 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_CLK_EN_FRC_SHIFT 12 3581 3582 /* ctl_regs :: susm_ltx_ctrl4 :: susm_tpc_clk_en_frcval [11:08] */ 3583 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_CLK_EN_FRCVAL_MASK 0x0f00 3584 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_CLK_EN_FRCVAL_ALIGN 0 3585 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_CLK_EN_FRCVAL_BITS 4 3586 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_CLK_EN_FRCVAL_SHIFT 8 3587 3588 /* ctl_regs :: susm_ltx_ctrl4 :: susm_tpc_sel_tca_frc [07:04] */ 3589 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_SEL_TCA_FRC_MASK 0x00f0 3590 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_SEL_TCA_FRC_ALIGN 0 3591 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_SEL_TCA_FRC_BITS 4 3592 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_SEL_TCA_FRC_SHIFT 4 3593 3594 /* ctl_regs :: susm_ltx_ctrl4 :: susm_tpc_sel_tca_frcval [03:00] */ 3595 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_SEL_TCA_FRCVAL_MASK 0x000f 3596 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_SEL_TCA_FRCVAL_ALIGN 0 3597 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_SEL_TCA_FRCVAL_BITS 4 3598 #define CTL_REGS_SUSM_LTX_CTRL4_SUSM_TPC_SEL_TCA_FRCVAL_SHIFT 0 3599 3600 3601 /**************************************************************************** 3602 * ctl_regs :: susm_ltx_ctrl5 3603 */ 3604 /* ctl_regs :: susm_ltx_ctrl5 :: reserved0 [15:06] */ 3605 #define CTL_REGS_SUSM_LTX_CTRL5_RESERVED0_MASK 0xffc0 3606 #define CTL_REGS_SUSM_LTX_CTRL5_RESERVED0_ALIGN 0 3607 #define CTL_REGS_SUSM_LTX_CTRL5_RESERVED0_BITS 10 3608 #define CTL_REGS_SUSM_LTX_CTRL5_RESERVED0_SHIFT 6 3609 3610 /* ctl_regs :: susm_ltx_ctrl5 :: hc_tx_pictrl_sel_tjf [05:00] */ 3611 #define CTL_REGS_SUSM_LTX_CTRL5_HC_TX_PICTRL_SEL_TJF_MASK 0x003f 3612 #define CTL_REGS_SUSM_LTX_CTRL5_HC_TX_PICTRL_SEL_TJF_ALIGN 0 3613 #define CTL_REGS_SUSM_LTX_CTRL5_HC_TX_PICTRL_SEL_TJF_BITS 6 3614 #define CTL_REGS_SUSM_LTX_CTRL5_HC_TX_PICTRL_SEL_TJF_SHIFT 0 3615 3616 3617 /**************************************************************************** 3618 * ctl_regs :: susm_ltx_ctrl6 3619 */ 3620 /* ctl_regs :: susm_ltx_ctrl6 :: reserved0 [15:06] */ 3621 #define CTL_REGS_SUSM_LTX_CTRL6_RESERVED0_MASK 0xffc0 3622 #define CTL_REGS_SUSM_LTX_CTRL6_RESERVED0_ALIGN 0 3623 #define CTL_REGS_SUSM_LTX_CTRL6_RESERVED0_BITS 10 3624 #define CTL_REGS_SUSM_LTX_CTRL6_RESERVED0_SHIFT 6 3625 3626 /* ctl_regs :: susm_ltx_ctrl6 :: hc_tx_ra_soft_reset_frcval [05:00] */ 3627 #define CTL_REGS_SUSM_LTX_CTRL6_HC_TX_RA_SOFT_RESET_FRCVAL_MASK 0x003f 3628 #define CTL_REGS_SUSM_LTX_CTRL6_HC_TX_RA_SOFT_RESET_FRCVAL_ALIGN 0 3629 #define CTL_REGS_SUSM_LTX_CTRL6_HC_TX_RA_SOFT_RESET_FRCVAL_BITS 6 3630 #define CTL_REGS_SUSM_LTX_CTRL6_HC_TX_RA_SOFT_RESET_FRCVAL_SHIFT 0 3631 3632 3633 /**************************************************************************** 3634 * ctl_regs :: susm_ltx_ctrl7 3635 */ 3636 /* ctl_regs :: susm_ltx_ctrl7 :: reserved0 [15:06] */ 3637 #define CTL_REGS_SUSM_LTX_CTRL7_RESERVED0_MASK 0xffc0 3638 #define CTL_REGS_SUSM_LTX_CTRL7_RESERVED0_ALIGN 0 3639 #define CTL_REGS_SUSM_LTX_CTRL7_RESERVED0_BITS 10 3640 #define CTL_REGS_SUSM_LTX_CTRL7_RESERVED0_SHIFT 6 3641 3642 /* ctl_regs :: susm_ltx_ctrl7 :: hc_tx_ra_soft_reset_frc [05:00] */ 3643 #define CTL_REGS_SUSM_LTX_CTRL7_HC_TX_RA_SOFT_RESET_FRC_MASK 0x003f 3644 #define CTL_REGS_SUSM_LTX_CTRL7_HC_TX_RA_SOFT_RESET_FRC_ALIGN 0 3645 #define CTL_REGS_SUSM_LTX_CTRL7_HC_TX_RA_SOFT_RESET_FRC_BITS 6 3646 #define CTL_REGS_SUSM_LTX_CTRL7_HC_TX_RA_SOFT_RESET_FRC_SHIFT 0 3647 3648 3649 /**************************************************************************** 3650 * ctl_regs :: susm_ltx_ctrl8 3651 */ 3652 /* ctl_regs :: susm_ltx_ctrl8 :: reserved0 [15:15] */ 3653 #define CTL_REGS_SUSM_LTX_CTRL8_RESERVED0_MASK 0x8000 3654 #define CTL_REGS_SUSM_LTX_CTRL8_RESERVED0_ALIGN 0 3655 #define CTL_REGS_SUSM_LTX_CTRL8_RESERVED0_BITS 1 3656 #define CTL_REGS_SUSM_LTX_CTRL8_RESERVED0_SHIFT 15 3657 3658 /* ctl_regs :: susm_ltx_ctrl8 :: hc_tx_pi_ln4_cnt [14:12] */ 3659 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN4_CNT_MASK 0x7000 3660 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN4_CNT_ALIGN 0 3661 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN4_CNT_BITS 3 3662 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN4_CNT_SHIFT 12 3663 3664 /* ctl_regs :: susm_ltx_ctrl8 :: hc_tx_pi_ln3_cnt [11:09] */ 3665 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN3_CNT_MASK 0x0e00 3666 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN3_CNT_ALIGN 0 3667 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN3_CNT_BITS 3 3668 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN3_CNT_SHIFT 9 3669 3670 /* ctl_regs :: susm_ltx_ctrl8 :: hc_tx_pi_ln2_cnt [08:06] */ 3671 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN2_CNT_MASK 0x01c0 3672 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN2_CNT_ALIGN 0 3673 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN2_CNT_BITS 3 3674 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN2_CNT_SHIFT 6 3675 3676 /* ctl_regs :: susm_ltx_ctrl8 :: hc_tx_pi_ln1_cnt [05:03] */ 3677 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN1_CNT_MASK 0x0038 3678 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN1_CNT_ALIGN 0 3679 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN1_CNT_BITS 3 3680 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN1_CNT_SHIFT 3 3681 3682 /* ctl_regs :: susm_ltx_ctrl8 :: hc_tx_pi_ln0_cnt [02:00] */ 3683 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN0_CNT_MASK 0x0007 3684 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN0_CNT_ALIGN 0 3685 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN0_CNT_BITS 3 3686 #define CTL_REGS_SUSM_LTX_CTRL8_HC_TX_PI_LN0_CNT_SHIFT 0 3687 3688 3689 /**************************************************************************** 3690 * ctl_regs :: susm_ltx_ctrl9 3691 */ 3692 /* ctl_regs :: susm_ltx_ctrl9 :: reserved0 [15:15] */ 3693 #define CTL_REGS_SUSM_LTX_CTRL9_RESERVED0_MASK 0x8000 3694 #define CTL_REGS_SUSM_LTX_CTRL9_RESERVED0_ALIGN 0 3695 #define CTL_REGS_SUSM_LTX_CTRL9_RESERVED0_BITS 1 3696 #define CTL_REGS_SUSM_LTX_CTRL9_RESERVED0_SHIFT 15 3697 3698 /* ctl_regs :: susm_ltx_ctrl9 :: hstx_pi_ln3_cnt [14:12] */ 3699 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN3_CNT_MASK 0x7000 3700 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN3_CNT_ALIGN 0 3701 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN3_CNT_BITS 3 3702 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN3_CNT_SHIFT 12 3703 3704 /* ctl_regs :: susm_ltx_ctrl9 :: hstx_pi_ln2_cnt [11:09] */ 3705 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN2_CNT_MASK 0x0e00 3706 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN2_CNT_ALIGN 0 3707 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN2_CNT_BITS 3 3708 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN2_CNT_SHIFT 9 3709 3710 /* ctl_regs :: susm_ltx_ctrl9 :: hstx_pi_ln1_cnt [08:06] */ 3711 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN1_CNT_MASK 0x01c0 3712 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN1_CNT_ALIGN 0 3713 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN1_CNT_BITS 3 3714 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN1_CNT_SHIFT 6 3715 3716 /* ctl_regs :: susm_ltx_ctrl9 :: hstx_pi_ln0_cnt [05:03] */ 3717 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN0_CNT_MASK 0x0038 3718 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN0_CNT_ALIGN 0 3719 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN0_CNT_BITS 3 3720 #define CTL_REGS_SUSM_LTX_CTRL9_HSTX_PI_LN0_CNT_SHIFT 3 3721 3722 /* ctl_regs :: susm_ltx_ctrl9 :: hc_tx_pi_ln5_cnt [02:00] */ 3723 #define CTL_REGS_SUSM_LTX_CTRL9_HC_TX_PI_LN5_CNT_MASK 0x0007 3724 #define CTL_REGS_SUSM_LTX_CTRL9_HC_TX_PI_LN5_CNT_ALIGN 0 3725 #define CTL_REGS_SUSM_LTX_CTRL9_HC_TX_PI_LN5_CNT_BITS 3 3726 #define CTL_REGS_SUSM_LTX_CTRL9_HC_TX_PI_LN5_CNT_SHIFT 0 3727 3728 3729 /**************************************************************************** 3730 * ctl_regs :: susm_ltx_ctrl10 3731 */ 3732 /* ctl_regs :: susm_ltx_ctrl10 :: reserved0 [15:10] */ 3733 #define CTL_REGS_SUSM_LTX_CTRL10_RESERVED0_MASK 0xfc00 3734 #define CTL_REGS_SUSM_LTX_CTRL10_RESERVED0_ALIGN 0 3735 #define CTL_REGS_SUSM_LTX_CTRL10_RESERVED0_BITS 6 3736 #define CTL_REGS_SUSM_LTX_CTRL10_RESERVED0_SHIFT 10 3737 3738 /* ctl_regs :: susm_ltx_ctrl10 :: hstx_pi_lock_frc [09:06] */ 3739 #define CTL_REGS_SUSM_LTX_CTRL10_HSTX_PI_LOCK_FRC_MASK 0x03c0 3740 #define CTL_REGS_SUSM_LTX_CTRL10_HSTX_PI_LOCK_FRC_ALIGN 0 3741 #define CTL_REGS_SUSM_LTX_CTRL10_HSTX_PI_LOCK_FRC_BITS 4 3742 #define CTL_REGS_SUSM_LTX_CTRL10_HSTX_PI_LOCK_FRC_SHIFT 6 3743 3744 /* ctl_regs :: susm_ltx_ctrl10 :: hc_tx_pi_lock_frc [05:00] */ 3745 #define CTL_REGS_SUSM_LTX_CTRL10_HC_TX_PI_LOCK_FRC_MASK 0x003f 3746 #define CTL_REGS_SUSM_LTX_CTRL10_HC_TX_PI_LOCK_FRC_ALIGN 0 3747 #define CTL_REGS_SUSM_LTX_CTRL10_HC_TX_PI_LOCK_FRC_BITS 6 3748 #define CTL_REGS_SUSM_LTX_CTRL10_HC_TX_PI_LOCK_FRC_SHIFT 0 3749 3750 3751 /**************************************************************************** 3752 * ctl_regs :: susm_ltx_ctrl11 3753 */ 3754 /* ctl_regs :: susm_ltx_ctrl11 :: reserved0 [15:10] */ 3755 #define CTL_REGS_SUSM_LTX_CTRL11_RESERVED0_MASK 0xfc00 3756 #define CTL_REGS_SUSM_LTX_CTRL11_RESERVED0_ALIGN 0 3757 #define CTL_REGS_SUSM_LTX_CTRL11_RESERVED0_BITS 6 3758 #define CTL_REGS_SUSM_LTX_CTRL11_RESERVED0_SHIFT 10 3759 3760 /* ctl_regs :: susm_ltx_ctrl11 :: hstx_pi_lock_frcval [09:06] */ 3761 #define CTL_REGS_SUSM_LTX_CTRL11_HSTX_PI_LOCK_FRCVAL_MASK 0x03c0 3762 #define CTL_REGS_SUSM_LTX_CTRL11_HSTX_PI_LOCK_FRCVAL_ALIGN 0 3763 #define CTL_REGS_SUSM_LTX_CTRL11_HSTX_PI_LOCK_FRCVAL_BITS 4 3764 #define CTL_REGS_SUSM_LTX_CTRL11_HSTX_PI_LOCK_FRCVAL_SHIFT 6 3765 3766 /* ctl_regs :: susm_ltx_ctrl11 :: hc_tx_pi_lock_frcval [05:00] */ 3767 #define CTL_REGS_SUSM_LTX_CTRL11_HC_TX_PI_LOCK_FRCVAL_MASK 0x003f 3768 #define CTL_REGS_SUSM_LTX_CTRL11_HC_TX_PI_LOCK_FRCVAL_ALIGN 0 3769 #define CTL_REGS_SUSM_LTX_CTRL11_HC_TX_PI_LOCK_FRCVAL_BITS 6 3770 #define CTL_REGS_SUSM_LTX_CTRL11_HC_TX_PI_LOCK_FRCVAL_SHIFT 0 3771 3772 3773 /**************************************************************************** 3774 * ctl_regs :: susm_lrx_ctrl1 3775 */ 3776 /* ctl_regs :: susm_lrx_ctrl1 :: reserved0 [15:05] */ 3777 #define CTL_REGS_SUSM_LRX_CTRL1_RESERVED0_MASK 0xffe0 3778 #define CTL_REGS_SUSM_LRX_CTRL1_RESERVED0_ALIGN 0 3779 #define CTL_REGS_SUSM_LRX_CTRL1_RESERVED0_BITS 11 3780 #define CTL_REGS_SUSM_LRX_CTRL1_RESERVED0_SHIFT 5 3781 3782 /* ctl_regs :: susm_lrx_ctrl1 :: susm_pua_clk_en_frc [04:04] */ 3783 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_PUA_CLK_EN_FRC_MASK 0x0010 3784 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_PUA_CLK_EN_FRC_ALIGN 0 3785 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_PUA_CLK_EN_FRC_BITS 1 3786 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_PUA_CLK_EN_FRC_SHIFT 4 3787 3788 /* ctl_regs :: susm_lrx_ctrl1 :: susm_pua_clk_en_frcval [03:03] */ 3789 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_PUA_CLK_EN_FRCVAL_MASK 0x0008 3790 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_PUA_CLK_EN_FRCVAL_ALIGN 0 3791 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_PUA_CLK_EN_FRCVAL_BITS 1 3792 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_PUA_CLK_EN_FRCVAL_SHIFT 3 3793 3794 /* ctl_regs :: susm_lrx_ctrl1 :: susm_lrx_trigger_frc [02:02] */ 3795 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_LRX_TRIGGER_FRC_MASK 0x0004 3796 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_LRX_TRIGGER_FRC_ALIGN 0 3797 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_LRX_TRIGGER_FRC_BITS 1 3798 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_LRX_TRIGGER_FRC_SHIFT 2 3799 3800 /* ctl_regs :: susm_lrx_ctrl1 :: susm_lrx_trigger_frcval [01:01] */ 3801 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_LRX_TRIGGER_FRCVAL_MASK 0x0002 3802 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_LRX_TRIGGER_FRCVAL_ALIGN 0 3803 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_LRX_TRIGGER_FRCVAL_BITS 1 3804 #define CTL_REGS_SUSM_LRX_CTRL1_SUSM_LRX_TRIGGER_FRCVAL_SHIFT 1 3805 3806 /* ctl_regs :: susm_lrx_ctrl1 :: dis_susm_lrx [00:00] */ 3807 #define CTL_REGS_SUSM_LRX_CTRL1_DIS_SUSM_LRX_MASK 0x0001 3808 #define CTL_REGS_SUSM_LRX_CTRL1_DIS_SUSM_LRX_ALIGN 0 3809 #define CTL_REGS_SUSM_LRX_CTRL1_DIS_SUSM_LRX_BITS 1 3810 #define CTL_REGS_SUSM_LRX_CTRL1_DIS_SUSM_LRX_SHIFT 0 3811 3812 3813 /**************************************************************************** 3814 * ctl_regs :: susm_lrx_ctrl2 3815 */ 3816 /* ctl_regs :: susm_lrx_ctrl2 :: reserved0 [15:10] */ 3817 #define CTL_REGS_SUSM_LRX_CTRL2_RESERVED0_MASK 0xfc00 3818 #define CTL_REGS_SUSM_LRX_CTRL2_RESERVED0_ALIGN 0 3819 #define CTL_REGS_SUSM_LRX_CTRL2_RESERVED0_BITS 6 3820 #define CTL_REGS_SUSM_LRX_CTRL2_RESERVED0_SHIFT 10 3821 3822 /* ctl_regs :: susm_lrx_ctrl2 :: susm_lrx_rdy_frc [09:00] */ 3823 #define CTL_REGS_SUSM_LRX_CTRL2_SUSM_LRX_RDY_FRC_MASK 0x03ff 3824 #define CTL_REGS_SUSM_LRX_CTRL2_SUSM_LRX_RDY_FRC_ALIGN 0 3825 #define CTL_REGS_SUSM_LRX_CTRL2_SUSM_LRX_RDY_FRC_BITS 10 3826 #define CTL_REGS_SUSM_LRX_CTRL2_SUSM_LRX_RDY_FRC_SHIFT 0 3827 3828 3829 /**************************************************************************** 3830 * ctl_regs :: susm_lrx_ctrl3 3831 */ 3832 /* ctl_regs :: susm_lrx_ctrl3 :: reserved0 [15:10] */ 3833 #define CTL_REGS_SUSM_LRX_CTRL3_RESERVED0_MASK 0xfc00 3834 #define CTL_REGS_SUSM_LRX_CTRL3_RESERVED0_ALIGN 0 3835 #define CTL_REGS_SUSM_LRX_CTRL3_RESERVED0_BITS 6 3836 #define CTL_REGS_SUSM_LRX_CTRL3_RESERVED0_SHIFT 10 3837 3838 /* ctl_regs :: susm_lrx_ctrl3 :: susm_lrx_rdy_frcval [09:00] */ 3839 #define CTL_REGS_SUSM_LRX_CTRL3_SUSM_LRX_RDY_FRCVAL_MASK 0x03ff 3840 #define CTL_REGS_SUSM_LRX_CTRL3_SUSM_LRX_RDY_FRCVAL_ALIGN 0 3841 #define CTL_REGS_SUSM_LRX_CTRL3_SUSM_LRX_RDY_FRCVAL_BITS 10 3842 #define CTL_REGS_SUSM_LRX_CTRL3_SUSM_LRX_RDY_FRCVAL_SHIFT 0 3843 3844 3845 /**************************************************************************** 3846 * ctl_regs :: susm_sys_ctrl1 3847 */ 3848 /* ctl_regs :: susm_sys_ctrl1 :: reserved0 [15:09] */ 3849 #define CTL_REGS_SUSM_SYS_CTRL1_RESERVED0_MASK 0xfe00 3850 #define CTL_REGS_SUSM_SYS_CTRL1_RESERVED0_ALIGN 0 3851 #define CTL_REGS_SUSM_SYS_CTRL1_RESERVED0_BITS 7 3852 #define CTL_REGS_SUSM_SYS_CTRL1_RESERVED0_SHIFT 9 3853 3854 /* ctl_regs :: susm_sys_ctrl1 :: dis_dcrx_pi_lock [08:08] */ 3855 #define CTL_REGS_SUSM_SYS_CTRL1_DIS_DCRX_PI_LOCK_MASK 0x0100 3856 #define CTL_REGS_SUSM_SYS_CTRL1_DIS_DCRX_PI_LOCK_ALIGN 0 3857 #define CTL_REGS_SUSM_SYS_CTRL1_DIS_DCRX_PI_LOCK_BITS 1 3858 #define CTL_REGS_SUSM_SYS_CTRL1_DIS_DCRX_PI_LOCK_SHIFT 8 3859 3860 /* ctl_regs :: susm_sys_ctrl1 :: dctx_restart_tca [07:07] */ 3861 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_RESTART_TCA_MASK 0x0080 3862 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_RESTART_TCA_ALIGN 0 3863 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_RESTART_TCA_BITS 1 3864 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_RESTART_TCA_SHIFT 7 3865 3866 /* ctl_regs :: susm_sys_ctrl1 :: dctx_tca_start_frc [06:06] */ 3867 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_START_FRC_MASK 0x0040 3868 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_START_FRC_ALIGN 0 3869 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_START_FRC_BITS 1 3870 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_START_FRC_SHIFT 6 3871 3872 /* ctl_regs :: susm_sys_ctrl1 :: dctx_tca_start_frcval [05:05] */ 3873 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_START_FRCVAL_MASK 0x0020 3874 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_START_FRCVAL_ALIGN 0 3875 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_START_FRCVAL_BITS 1 3876 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_START_FRCVAL_SHIFT 5 3877 3878 /* ctl_regs :: susm_sys_ctrl1 :: dctx_tca_enable_frc [04:04] */ 3879 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_ENABLE_FRC_MASK 0x0010 3880 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_ENABLE_FRC_ALIGN 0 3881 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_ENABLE_FRC_BITS 1 3882 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_ENABLE_FRC_SHIFT 4 3883 3884 /* ctl_regs :: susm_sys_ctrl1 :: dctx_tca_enable_frcval [03:03] */ 3885 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_ENABLE_FRCVAL_MASK 0x0008 3886 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_ENABLE_FRCVAL_ALIGN 0 3887 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_ENABLE_FRCVAL_BITS 1 3888 #define CTL_REGS_SUSM_SYS_CTRL1_DCTX_TCA_ENABLE_FRCVAL_SHIFT 3 3889 3890 /* ctl_regs :: susm_sys_ctrl1 :: susm_sys_trigger_frc [02:02] */ 3891 #define CTL_REGS_SUSM_SYS_CTRL1_SUSM_SYS_TRIGGER_FRC_MASK 0x0004 3892 #define CTL_REGS_SUSM_SYS_CTRL1_SUSM_SYS_TRIGGER_FRC_ALIGN 0 3893 #define CTL_REGS_SUSM_SYS_CTRL1_SUSM_SYS_TRIGGER_FRC_BITS 1 3894 #define CTL_REGS_SUSM_SYS_CTRL1_SUSM_SYS_TRIGGER_FRC_SHIFT 2 3895 3896 /* ctl_regs :: susm_sys_ctrl1 :: susm_sys_trigger_frcval [01:01] */ 3897 #define CTL_REGS_SUSM_SYS_CTRL1_SUSM_SYS_TRIGGER_FRCVAL_MASK 0x0002 3898 #define CTL_REGS_SUSM_SYS_CTRL1_SUSM_SYS_TRIGGER_FRCVAL_ALIGN 0 3899 #define CTL_REGS_SUSM_SYS_CTRL1_SUSM_SYS_TRIGGER_FRCVAL_BITS 1 3900 #define CTL_REGS_SUSM_SYS_CTRL1_SUSM_SYS_TRIGGER_FRCVAL_SHIFT 1 3901 3902 /* ctl_regs :: susm_sys_ctrl1 :: dis_susm_sys [00:00] */ 3903 #define CTL_REGS_SUSM_SYS_CTRL1_DIS_SUSM_SYS_MASK 0x0001 3904 #define CTL_REGS_SUSM_SYS_CTRL1_DIS_SUSM_SYS_ALIGN 0 3905 #define CTL_REGS_SUSM_SYS_CTRL1_DIS_SUSM_SYS_BITS 1 3906 #define CTL_REGS_SUSM_SYS_CTRL1_DIS_SUSM_SYS_SHIFT 0 3907 3908 3909 /**************************************************************************** 3910 * ctl_regs :: susm_sys_ctrl2 3911 */ 3912 /* ctl_regs :: susm_sys_ctrl2 :: reserved0 [15:10] */ 3913 #define CTL_REGS_SUSM_SYS_CTRL2_RESERVED0_MASK 0xfc00 3914 #define CTL_REGS_SUSM_SYS_CTRL2_RESERVED0_ALIGN 0 3915 #define CTL_REGS_SUSM_SYS_CTRL2_RESERVED0_BITS 6 3916 #define CTL_REGS_SUSM_SYS_CTRL2_RESERVED0_SHIFT 10 3917 3918 /* ctl_regs :: susm_sys_ctrl2 :: susm_stx_rdy_frc [09:00] */ 3919 #define CTL_REGS_SUSM_SYS_CTRL2_SUSM_STX_RDY_FRC_MASK 0x03ff 3920 #define CTL_REGS_SUSM_SYS_CTRL2_SUSM_STX_RDY_FRC_ALIGN 0 3921 #define CTL_REGS_SUSM_SYS_CTRL2_SUSM_STX_RDY_FRC_BITS 10 3922 #define CTL_REGS_SUSM_SYS_CTRL2_SUSM_STX_RDY_FRC_SHIFT 0 3923 3924 3925 /**************************************************************************** 3926 * ctl_regs :: susm_sys_ctrl3 3927 */ 3928 /* ctl_regs :: susm_sys_ctrl3 :: reserved0 [15:10] */ 3929 #define CTL_REGS_SUSM_SYS_CTRL3_RESERVED0_MASK 0xfc00 3930 #define CTL_REGS_SUSM_SYS_CTRL3_RESERVED0_ALIGN 0 3931 #define CTL_REGS_SUSM_SYS_CTRL3_RESERVED0_BITS 6 3932 #define CTL_REGS_SUSM_SYS_CTRL3_RESERVED0_SHIFT 10 3933 3934 /* ctl_regs :: susm_sys_ctrl3 :: susm_stx_rdy_frcval [09:00] */ 3935 #define CTL_REGS_SUSM_SYS_CTRL3_SUSM_STX_RDY_FRCVAL_MASK 0x03ff 3936 #define CTL_REGS_SUSM_SYS_CTRL3_SUSM_STX_RDY_FRCVAL_ALIGN 0 3937 #define CTL_REGS_SUSM_SYS_CTRL3_SUSM_STX_RDY_FRCVAL_BITS 10 3938 #define CTL_REGS_SUSM_SYS_CTRL3_SUSM_STX_RDY_FRCVAL_SHIFT 0 3939 3940 3941 /**************************************************************************** 3942 * ctl_regs :: susm_sys_ctrl4 3943 */ 3944 /* ctl_regs :: susm_sys_ctrl4 :: reserved0 [15:10] */ 3945 #define CTL_REGS_SUSM_SYS_CTRL4_RESERVED0_MASK 0xfc00 3946 #define CTL_REGS_SUSM_SYS_CTRL4_RESERVED0_ALIGN 0 3947 #define CTL_REGS_SUSM_SYS_CTRL4_RESERVED0_BITS 6 3948 #define CTL_REGS_SUSM_SYS_CTRL4_RESERVED0_SHIFT 10 3949 3950 /* ctl_regs :: susm_sys_ctrl4 :: susm_srx_rdy_frc [09:00] */ 3951 #define CTL_REGS_SUSM_SYS_CTRL4_SUSM_SRX_RDY_FRC_MASK 0x03ff 3952 #define CTL_REGS_SUSM_SYS_CTRL4_SUSM_SRX_RDY_FRC_ALIGN 0 3953 #define CTL_REGS_SUSM_SYS_CTRL4_SUSM_SRX_RDY_FRC_BITS 10 3954 #define CTL_REGS_SUSM_SYS_CTRL4_SUSM_SRX_RDY_FRC_SHIFT 0 3955 3956 3957 /**************************************************************************** 3958 * ctl_regs :: susm_sys_ctrl5 3959 */ 3960 /* ctl_regs :: susm_sys_ctrl5 :: reserved0 [15:10] */ 3961 #define CTL_REGS_SUSM_SYS_CTRL5_RESERVED0_MASK 0xfc00 3962 #define CTL_REGS_SUSM_SYS_CTRL5_RESERVED0_ALIGN 0 3963 #define CTL_REGS_SUSM_SYS_CTRL5_RESERVED0_BITS 6 3964 #define CTL_REGS_SUSM_SYS_CTRL5_RESERVED0_SHIFT 10 3965 3966 /* ctl_regs :: susm_sys_ctrl5 :: susm_srx_rdy_frcval [09:00] */ 3967 #define CTL_REGS_SUSM_SYS_CTRL5_SUSM_SRX_RDY_FRCVAL_MASK 0x03ff 3968 #define CTL_REGS_SUSM_SYS_CTRL5_SUSM_SRX_RDY_FRCVAL_ALIGN 0 3969 #define CTL_REGS_SUSM_SYS_CTRL5_SUSM_SRX_RDY_FRCVAL_BITS 10 3970 #define CTL_REGS_SUSM_SYS_CTRL5_SUSM_SRX_RDY_FRCVAL_SHIFT 0 3971 3972 3973 /**************************************************************************** 3974 * ctl_regs :: susm_sys_ctrl6 3975 */ 3976 /* ctl_regs :: susm_sys_ctrl6 :: reserved0 [15:10] */ 3977 #define CTL_REGS_SUSM_SYS_CTRL6_RESERVED0_MASK 0xfc00 3978 #define CTL_REGS_SUSM_SYS_CTRL6_RESERVED0_ALIGN 0 3979 #define CTL_REGS_SUSM_SYS_CTRL6_RESERVED0_BITS 6 3980 #define CTL_REGS_SUSM_SYS_CTRL6_RESERVED0_SHIFT 10 3981 3982 /* ctl_regs :: susm_sys_ctrl6 :: dctx_sel_tjf_frc [09:00] */ 3983 #define CTL_REGS_SUSM_SYS_CTRL6_DCTX_SEL_TJF_FRC_MASK 0x03ff 3984 #define CTL_REGS_SUSM_SYS_CTRL6_DCTX_SEL_TJF_FRC_ALIGN 0 3985 #define CTL_REGS_SUSM_SYS_CTRL6_DCTX_SEL_TJF_FRC_BITS 10 3986 #define CTL_REGS_SUSM_SYS_CTRL6_DCTX_SEL_TJF_FRC_SHIFT 0 3987 3988 3989 /**************************************************************************** 3990 * ctl_regs :: susm_sys_ctrl7 3991 */ 3992 /* ctl_regs :: susm_sys_ctrl7 :: reserved0 [15:10] */ 3993 #define CTL_REGS_SUSM_SYS_CTRL7_RESERVED0_MASK 0xfc00 3994 #define CTL_REGS_SUSM_SYS_CTRL7_RESERVED0_ALIGN 0 3995 #define CTL_REGS_SUSM_SYS_CTRL7_RESERVED0_BITS 6 3996 #define CTL_REGS_SUSM_SYS_CTRL7_RESERVED0_SHIFT 10 3997 3998 /* ctl_regs :: susm_sys_ctrl7 :: dctx_sel_tjf_frcval [09:00] */ 3999 #define CTL_REGS_SUSM_SYS_CTRL7_DCTX_SEL_TJF_FRCVAL_MASK 0x03ff 4000 #define CTL_REGS_SUSM_SYS_CTRL7_DCTX_SEL_TJF_FRCVAL_ALIGN 0 4001 #define CTL_REGS_SUSM_SYS_CTRL7_DCTX_SEL_TJF_FRCVAL_BITS 10 4002 #define CTL_REGS_SUSM_SYS_CTRL7_DCTX_SEL_TJF_FRCVAL_SHIFT 0 4003 4004 4005 /**************************************************************************** 4006 * ctl_regs :: susm_sys_ctrl8 4007 */ 4008 /* ctl_regs :: susm_sys_ctrl8 :: reserved0 [15:10] */ 4009 #define CTL_REGS_SUSM_SYS_CTRL8_RESERVED0_MASK 0xfc00 4010 #define CTL_REGS_SUSM_SYS_CTRL8_RESERVED0_ALIGN 0 4011 #define CTL_REGS_SUSM_SYS_CTRL8_RESERVED0_BITS 6 4012 #define CTL_REGS_SUSM_SYS_CTRL8_RESERVED0_SHIFT 10 4013 4014 /* ctl_regs :: susm_sys_ctrl8 :: dctx_ra_soft_reset_frc [09:00] */ 4015 #define CTL_REGS_SUSM_SYS_CTRL8_DCTX_RA_SOFT_RESET_FRC_MASK 0x03ff 4016 #define CTL_REGS_SUSM_SYS_CTRL8_DCTX_RA_SOFT_RESET_FRC_ALIGN 0 4017 #define CTL_REGS_SUSM_SYS_CTRL8_DCTX_RA_SOFT_RESET_FRC_BITS 10 4018 #define CTL_REGS_SUSM_SYS_CTRL8_DCTX_RA_SOFT_RESET_FRC_SHIFT 0 4019 4020 4021 /**************************************************************************** 4022 * ctl_regs :: susm_sys_ctrl9 4023 */ 4024 /* ctl_regs :: susm_sys_ctrl9 :: reserved0 [15:10] */ 4025 #define CTL_REGS_SUSM_SYS_CTRL9_RESERVED0_MASK 0xfc00 4026 #define CTL_REGS_SUSM_SYS_CTRL9_RESERVED0_ALIGN 0 4027 #define CTL_REGS_SUSM_SYS_CTRL9_RESERVED0_BITS 6 4028 #define CTL_REGS_SUSM_SYS_CTRL9_RESERVED0_SHIFT 10 4029 4030 /* ctl_regs :: susm_sys_ctrl9 :: dctx_ra_soft_reset_frcval [09:00] */ 4031 #define CTL_REGS_SUSM_SYS_CTRL9_DCTX_RA_SOFT_RESET_FRCVAL_MASK 0x03ff 4032 #define CTL_REGS_SUSM_SYS_CTRL9_DCTX_RA_SOFT_RESET_FRCVAL_ALIGN 0 4033 #define CTL_REGS_SUSM_SYS_CTRL9_DCTX_RA_SOFT_RESET_FRCVAL_BITS 10 4034 #define CTL_REGS_SUSM_SYS_CTRL9_DCTX_RA_SOFT_RESET_FRCVAL_SHIFT 0 4035 4036 4037 /**************************************************************************** 4038 * ctl_regs :: susm_sys_ctrl10 4039 */ 4040 /* ctl_regs :: susm_sys_ctrl10 :: reserved0 [15:15] */ 4041 #define CTL_REGS_SUSM_SYS_CTRL10_RESERVED0_MASK 0x8000 4042 #define CTL_REGS_SUSM_SYS_CTRL10_RESERVED0_ALIGN 0 4043 #define CTL_REGS_SUSM_SYS_CTRL10_RESERVED0_BITS 1 4044 #define CTL_REGS_SUSM_SYS_CTRL10_RESERVED0_SHIFT 15 4045 4046 /* ctl_regs :: susm_sys_ctrl10 :: dcrx_pi_ln4_cnt [14:12] */ 4047 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN4_CNT_MASK 0x7000 4048 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN4_CNT_ALIGN 0 4049 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN4_CNT_BITS 3 4050 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN4_CNT_SHIFT 12 4051 4052 /* ctl_regs :: susm_sys_ctrl10 :: dcrx_pi_ln3_cnt [11:09] */ 4053 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN3_CNT_MASK 0x0e00 4054 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN3_CNT_ALIGN 0 4055 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN3_CNT_BITS 3 4056 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN3_CNT_SHIFT 9 4057 4058 /* ctl_regs :: susm_sys_ctrl10 :: dcrx_pi_ln2_cnt [08:06] */ 4059 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN2_CNT_MASK 0x01c0 4060 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN2_CNT_ALIGN 0 4061 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN2_CNT_BITS 3 4062 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN2_CNT_SHIFT 6 4063 4064 /* ctl_regs :: susm_sys_ctrl10 :: dcrx_pi_ln1_cnt [05:03] */ 4065 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN1_CNT_MASK 0x0038 4066 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN1_CNT_ALIGN 0 4067 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN1_CNT_BITS 3 4068 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN1_CNT_SHIFT 3 4069 4070 /* ctl_regs :: susm_sys_ctrl10 :: dcrx_pi_ln0_cnt [02:00] */ 4071 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN0_CNT_MASK 0x0007 4072 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN0_CNT_ALIGN 0 4073 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN0_CNT_BITS 3 4074 #define CTL_REGS_SUSM_SYS_CTRL10_DCRX_PI_LN0_CNT_SHIFT 0 4075 4076 4077 /**************************************************************************** 4078 * ctl_regs :: susm_sys_ctrl11 4079 */ 4080 /* ctl_regs :: susm_sys_ctrl11 :: reserved0 [15:15] */ 4081 #define CTL_REGS_SUSM_SYS_CTRL11_RESERVED0_MASK 0x8000 4082 #define CTL_REGS_SUSM_SYS_CTRL11_RESERVED0_ALIGN 0 4083 #define CTL_REGS_SUSM_SYS_CTRL11_RESERVED0_BITS 1 4084 #define CTL_REGS_SUSM_SYS_CTRL11_RESERVED0_SHIFT 15 4085 4086 /* ctl_regs :: susm_sys_ctrl11 :: dcrx_pi_ln9_cnt [14:12] */ 4087 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN9_CNT_MASK 0x7000 4088 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN9_CNT_ALIGN 0 4089 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN9_CNT_BITS 3 4090 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN9_CNT_SHIFT 12 4091 4092 /* ctl_regs :: susm_sys_ctrl11 :: dcrx_pi_ln8_cnt [11:09] */ 4093 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN8_CNT_MASK 0x0e00 4094 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN8_CNT_ALIGN 0 4095 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN8_CNT_BITS 3 4096 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN8_CNT_SHIFT 9 4097 4098 /* ctl_regs :: susm_sys_ctrl11 :: dcrx_pi_ln7_cnt [08:06] */ 4099 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN7_CNT_MASK 0x01c0 4100 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN7_CNT_ALIGN 0 4101 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN7_CNT_BITS 3 4102 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN7_CNT_SHIFT 6 4103 4104 /* ctl_regs :: susm_sys_ctrl11 :: dcrx_pi_ln6_cnt [05:03] */ 4105 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN6_CNT_MASK 0x0038 4106 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN6_CNT_ALIGN 0 4107 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN6_CNT_BITS 3 4108 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN6_CNT_SHIFT 3 4109 4110 /* ctl_regs :: susm_sys_ctrl11 :: dcrx_pi_ln5_cnt [02:00] */ 4111 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN5_CNT_MASK 0x0007 4112 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN5_CNT_ALIGN 0 4113 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN5_CNT_BITS 3 4114 #define CTL_REGS_SUSM_SYS_CTRL11_DCRX_PI_LN5_CNT_SHIFT 0 4115 4116 4117 /**************************************************************************** 4118 * ctl_regs :: susm_sys_ctrl12 4119 */ 4120 /* ctl_regs :: susm_sys_ctrl12 :: reserved0 [15:10] */ 4121 #define CTL_REGS_SUSM_SYS_CTRL12_RESERVED0_MASK 0xfc00 4122 #define CTL_REGS_SUSM_SYS_CTRL12_RESERVED0_ALIGN 0 4123 #define CTL_REGS_SUSM_SYS_CTRL12_RESERVED0_BITS 6 4124 #define CTL_REGS_SUSM_SYS_CTRL12_RESERVED0_SHIFT 10 4125 4126 /* ctl_regs :: susm_sys_ctrl12 :: dcrx_pi_lock_frc [09:00] */ 4127 #define CTL_REGS_SUSM_SYS_CTRL12_DCRX_PI_LOCK_FRC_MASK 0x03ff 4128 #define CTL_REGS_SUSM_SYS_CTRL12_DCRX_PI_LOCK_FRC_ALIGN 0 4129 #define CTL_REGS_SUSM_SYS_CTRL12_DCRX_PI_LOCK_FRC_BITS 10 4130 #define CTL_REGS_SUSM_SYS_CTRL12_DCRX_PI_LOCK_FRC_SHIFT 0 4131 4132 4133 /**************************************************************************** 4134 * ctl_regs :: susm_sys_ctrl13 4135 */ 4136 /* ctl_regs :: susm_sys_ctrl13 :: reserved0 [15:10] */ 4137 #define CTL_REGS_SUSM_SYS_CTRL13_RESERVED0_MASK 0xfc00 4138 #define CTL_REGS_SUSM_SYS_CTRL13_RESERVED0_ALIGN 0 4139 #define CTL_REGS_SUSM_SYS_CTRL13_RESERVED0_BITS 6 4140 #define CTL_REGS_SUSM_SYS_CTRL13_RESERVED0_SHIFT 10 4141 4142 /* ctl_regs :: susm_sys_ctrl13 :: dcrx_pi_lock_frcval [09:00] */ 4143 #define CTL_REGS_SUSM_SYS_CTRL13_DCRX_PI_LOCK_FRCVAL_MASK 0x03ff 4144 #define CTL_REGS_SUSM_SYS_CTRL13_DCRX_PI_LOCK_FRCVAL_ALIGN 0 4145 #define CTL_REGS_SUSM_SYS_CTRL13_DCRX_PI_LOCK_FRCVAL_BITS 10 4146 #define CTL_REGS_SUSM_SYS_CTRL13_DCRX_PI_LOCK_FRCVAL_SHIFT 0 4147 4148 4149 /**************************************************************************** 4150 * ctl_regs :: susm_sys_ctrl14 4151 */ 4152 /* ctl_regs :: susm_sys_ctrl14 :: reserved0 [15:10] */ 4153 #define CTL_REGS_SUSM_SYS_CTRL14_RESERVED0_MASK 0xfc00 4154 #define CTL_REGS_SUSM_SYS_CTRL14_RESERVED0_ALIGN 0 4155 #define CTL_REGS_SUSM_SYS_CTRL14_RESERVED0_BITS 6 4156 #define CTL_REGS_SUSM_SYS_CTRL14_RESERVED0_SHIFT 10 4157 4158 /* ctl_regs :: susm_sys_ctrl14 :: dcrx_lpbk_pi_lock [09:00] */ 4159 #define CTL_REGS_SUSM_SYS_CTRL14_DCRX_LPBK_PI_LOCK_MASK 0x03ff 4160 #define CTL_REGS_SUSM_SYS_CTRL14_DCRX_LPBK_PI_LOCK_ALIGN 0 4161 #define CTL_REGS_SUSM_SYS_CTRL14_DCRX_LPBK_PI_LOCK_BITS 10 4162 #define CTL_REGS_SUSM_SYS_CTRL14_DCRX_LPBK_PI_LOCK_SHIFT 0 4163 4164 4165 /**************************************************************************** 4166 * ctl_regs :: susm_status1 4167 */ 4168 /* ctl_regs :: susm_status1 :: reserved_for_eco0 [15:10] */ 4169 #define CTL_REGS_SUSM_STATUS1_RESERVED_FOR_ECO0_MASK 0xfc00 4170 #define CTL_REGS_SUSM_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 4171 #define CTL_REGS_SUSM_STATUS1_RESERVED_FOR_ECO0_BITS 6 4172 #define CTL_REGS_SUSM_STATUS1_RESERVED_FOR_ECO0_SHIFT 10 4173 4174 /* ctl_regs :: susm_status1 :: lrx_ready [09:00] */ 4175 #define CTL_REGS_SUSM_STATUS1_LRX_READY_MASK 0x03ff 4176 #define CTL_REGS_SUSM_STATUS1_LRX_READY_ALIGN 0 4177 #define CTL_REGS_SUSM_STATUS1_LRX_READY_BITS 10 4178 #define CTL_REGS_SUSM_STATUS1_LRX_READY_SHIFT 0 4179 4180 4181 /**************************************************************************** 4182 * ctl_regs :: susm_status2 4183 */ 4184 /* ctl_regs :: susm_status2 :: reserved_for_eco0 [15:12] */ 4185 #define CTL_REGS_SUSM_STATUS2_RESERVED_FOR_ECO0_MASK 0xf000 4186 #define CTL_REGS_SUSM_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 4187 #define CTL_REGS_SUSM_STATUS2_RESERVED_FOR_ECO0_BITS 4 4188 #define CTL_REGS_SUSM_STATUS2_RESERVED_FOR_ECO0_SHIFT 12 4189 4190 /* ctl_regs :: susm_status2 :: hc_tx_algnmnt_done [11:11] */ 4191 #define CTL_REGS_SUSM_STATUS2_HC_TX_ALGNMNT_DONE_MASK 0x0800 4192 #define CTL_REGS_SUSM_STATUS2_HC_TX_ALGNMNT_DONE_ALIGN 0 4193 #define CTL_REGS_SUSM_STATUS2_HC_TX_ALGNMNT_DONE_BITS 1 4194 #define CTL_REGS_SUSM_STATUS2_HC_TX_ALGNMNT_DONE_SHIFT 11 4195 4196 /* ctl_regs :: susm_status2 :: vsr40_tx_algnmnt_done [10:10] */ 4197 #define CTL_REGS_SUSM_STATUS2_VSR40_TX_ALGNMNT_DONE_MASK 0x0400 4198 #define CTL_REGS_SUSM_STATUS2_VSR40_TX_ALGNMNT_DONE_ALIGN 0 4199 #define CTL_REGS_SUSM_STATUS2_VSR40_TX_ALGNMNT_DONE_BITS 1 4200 #define CTL_REGS_SUSM_STATUS2_VSR40_TX_ALGNMNT_DONE_SHIFT 10 4201 4202 /* ctl_regs :: susm_status2 :: ltx_ready [09:00] */ 4203 #define CTL_REGS_SUSM_STATUS2_LTX_READY_MASK 0x03ff 4204 #define CTL_REGS_SUSM_STATUS2_LTX_READY_ALIGN 0 4205 #define CTL_REGS_SUSM_STATUS2_LTX_READY_BITS 10 4206 #define CTL_REGS_SUSM_STATUS2_LTX_READY_SHIFT 0 4207 4208 4209 /**************************************************************************** 4210 * ctl_regs :: susm_status3 4211 */ 4212 /* ctl_regs :: susm_status3 :: reserved_for_eco0 [15:13] */ 4213 #define CTL_REGS_SUSM_STATUS3_RESERVED_FOR_ECO0_MASK 0xe000 4214 #define CTL_REGS_SUSM_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 4215 #define CTL_REGS_SUSM_STATUS3_RESERVED_FOR_ECO0_BITS 3 4216 #define CTL_REGS_SUSM_STATUS3_RESERVED_FOR_ECO0_SHIFT 13 4217 4218 /* ctl_regs :: susm_status3 :: dc_tx_tca_start [12:12] */ 4219 #define CTL_REGS_SUSM_STATUS3_DC_TX_TCA_START_MASK 0x1000 4220 #define CTL_REGS_SUSM_STATUS3_DC_TX_TCA_START_ALIGN 0 4221 #define CTL_REGS_SUSM_STATUS3_DC_TX_TCA_START_BITS 1 4222 #define CTL_REGS_SUSM_STATUS3_DC_TX_TCA_START_SHIFT 12 4223 4224 /* ctl_regs :: susm_status3 :: dc_tx_tca_enable [11:11] */ 4225 #define CTL_REGS_SUSM_STATUS3_DC_TX_TCA_ENABLE_MASK 0x0800 4226 #define CTL_REGS_SUSM_STATUS3_DC_TX_TCA_ENABLE_ALIGN 0 4227 #define CTL_REGS_SUSM_STATUS3_DC_TX_TCA_ENABLE_BITS 1 4228 #define CTL_REGS_SUSM_STATUS3_DC_TX_TCA_ENABLE_SHIFT 11 4229 4230 /* ctl_regs :: susm_status3 :: dc_tx_algnmnt_done [10:10] */ 4231 #define CTL_REGS_SUSM_STATUS3_DC_TX_ALGNMNT_DONE_MASK 0x0400 4232 #define CTL_REGS_SUSM_STATUS3_DC_TX_ALGNMNT_DONE_ALIGN 0 4233 #define CTL_REGS_SUSM_STATUS3_DC_TX_ALGNMNT_DONE_BITS 1 4234 #define CTL_REGS_SUSM_STATUS3_DC_TX_ALGNMNT_DONE_SHIFT 10 4235 4236 /* ctl_regs :: susm_status3 :: srx_ready [09:00] */ 4237 #define CTL_REGS_SUSM_STATUS3_SRX_READY_MASK 0x03ff 4238 #define CTL_REGS_SUSM_STATUS3_SRX_READY_ALIGN 0 4239 #define CTL_REGS_SUSM_STATUS3_SRX_READY_BITS 10 4240 #define CTL_REGS_SUSM_STATUS3_SRX_READY_SHIFT 0 4241 4242 4243 /**************************************************************************** 4244 * ctl_regs :: susm_status4 4245 */ 4246 /* ctl_regs :: susm_status4 :: reserved_for_eco0 [15:10] */ 4247 #define CTL_REGS_SUSM_STATUS4_RESERVED_FOR_ECO0_MASK 0xfc00 4248 #define CTL_REGS_SUSM_STATUS4_RESERVED_FOR_ECO0_ALIGN 0 4249 #define CTL_REGS_SUSM_STATUS4_RESERVED_FOR_ECO0_BITS 6 4250 #define CTL_REGS_SUSM_STATUS4_RESERVED_FOR_ECO0_SHIFT 10 4251 4252 /* ctl_regs :: susm_status4 :: stx_ready [09:00] */ 4253 #define CTL_REGS_SUSM_STATUS4_STX_READY_MASK 0x03ff 4254 #define CTL_REGS_SUSM_STATUS4_STX_READY_ALIGN 0 4255 #define CTL_REGS_SUSM_STATUS4_STX_READY_BITS 10 4256 #define CTL_REGS_SUSM_STATUS4_STX_READY_SHIFT 0 4257 4258 4259 /**************************************************************************** 4260 * ctl_regs :: susm_status5 4261 */ 4262 /* ctl_regs :: susm_status5 :: reserved_for_eco0 [15:10] */ 4263 #define CTL_REGS_SUSM_STATUS5_RESERVED_FOR_ECO0_MASK 0xfc00 4264 #define CTL_REGS_SUSM_STATUS5_RESERVED_FOR_ECO0_ALIGN 0 4265 #define CTL_REGS_SUSM_STATUS5_RESERVED_FOR_ECO0_BITS 6 4266 #define CTL_REGS_SUSM_STATUS5_RESERVED_FOR_ECO0_SHIFT 10 4267 4268 /* ctl_regs :: susm_status5 :: srx_pi_lock [09:00] */ 4269 #define CTL_REGS_SUSM_STATUS5_SRX_PI_LOCK_MASK 0x03ff 4270 #define CTL_REGS_SUSM_STATUS5_SRX_PI_LOCK_ALIGN 0 4271 #define CTL_REGS_SUSM_STATUS5_SRX_PI_LOCK_BITS 10 4272 #define CTL_REGS_SUSM_STATUS5_SRX_PI_LOCK_SHIFT 0 4273 4274 4275 /**************************************************************************** 4276 * ctl_regs :: susm_status6 4277 */ 4278 /* ctl_regs :: susm_status6 :: reserved_for_eco0 [15:10] */ 4279 #define CTL_REGS_SUSM_STATUS6_RESERVED_FOR_ECO0_MASK 0xfc00 4280 #define CTL_REGS_SUSM_STATUS6_RESERVED_FOR_ECO0_ALIGN 0 4281 #define CTL_REGS_SUSM_STATUS6_RESERVED_FOR_ECO0_BITS 6 4282 #define CTL_REGS_SUSM_STATUS6_RESERVED_FOR_ECO0_SHIFT 10 4283 4284 /* ctl_regs :: susm_status6 :: ltx_pi_lock [09:00] */ 4285 #define CTL_REGS_SUSM_STATUS6_LTX_PI_LOCK_MASK 0x03ff 4286 #define CTL_REGS_SUSM_STATUS6_LTX_PI_LOCK_ALIGN 0 4287 #define CTL_REGS_SUSM_STATUS6_LTX_PI_LOCK_BITS 10 4288 #define CTL_REGS_SUSM_STATUS6_LTX_PI_LOCK_SHIFT 0 4289 4290 4291 /**************************************************************************** 4292 * ctl_regs :: device_identifier_lsb_ctrl1 4293 */ 4294 /* ctl_regs :: device_identifier_lsb_ctrl1 :: pma_pmd_device_identifier_lsb [15:00] */ 4295 #define CTL_REGS_DEVICE_IDENTIFIER_LSB_CTRL1_PMA_PMD_DEVICE_IDENTIFIER_LSB_MASK 0xffff 4296 #define CTL_REGS_DEVICE_IDENTIFIER_LSB_CTRL1_PMA_PMD_DEVICE_IDENTIFIER_LSB_ALIGN 0 4297 #define CTL_REGS_DEVICE_IDENTIFIER_LSB_CTRL1_PMA_PMD_DEVICE_IDENTIFIER_LSB_BITS 16 4298 #define CTL_REGS_DEVICE_IDENTIFIER_LSB_CTRL1_PMA_PMD_DEVICE_IDENTIFIER_LSB_SHIFT 0 4299 4300 4301 /**************************************************************************** 4302 * ctl_regs :: device_identifier_msb_ctrl1 4303 */ 4304 /* ctl_regs :: device_identifier_msb_ctrl1 :: pma_pmd_device_identifier_msb [15:00] */ 4305 #define CTL_REGS_DEVICE_IDENTIFIER_MSB_CTRL1_PMA_PMD_DEVICE_IDENTIFIER_MSB_MASK 0xffff 4306 #define CTL_REGS_DEVICE_IDENTIFIER_MSB_CTRL1_PMA_PMD_DEVICE_IDENTIFIER_MSB_ALIGN 0 4307 #define CTL_REGS_DEVICE_IDENTIFIER_MSB_CTRL1_PMA_PMD_DEVICE_IDENTIFIER_MSB_BITS 16 4308 #define CTL_REGS_DEVICE_IDENTIFIER_MSB_CTRL1_PMA_PMD_DEVICE_IDENTIFIER_MSB_SHIFT 0 4309 4310 4311 /**************************************************************************** 4312 * ctl_regs :: package_identifier_lsb_ctrl1 4313 */ 4314 /* ctl_regs :: package_identifier_lsb_ctrl1 :: pma_pmd_package_identifier_lsb [15:00] */ 4315 #define CTL_REGS_PACKAGE_IDENTIFIER_LSB_CTRL1_PMA_PMD_PACKAGE_IDENTIFIER_LSB_MASK 0xffff 4316 #define CTL_REGS_PACKAGE_IDENTIFIER_LSB_CTRL1_PMA_PMD_PACKAGE_IDENTIFIER_LSB_ALIGN 0 4317 #define CTL_REGS_PACKAGE_IDENTIFIER_LSB_CTRL1_PMA_PMD_PACKAGE_IDENTIFIER_LSB_BITS 16 4318 #define CTL_REGS_PACKAGE_IDENTIFIER_LSB_CTRL1_PMA_PMD_PACKAGE_IDENTIFIER_LSB_SHIFT 0 4319 4320 4321 /**************************************************************************** 4322 * ctl_regs :: package_identifier_msb_ctrl1 4323 */ 4324 /* ctl_regs :: package_identifier_msb_ctrl1 :: pma_pmd_package_identifier_msb [15:00] */ 4325 #define CTL_REGS_PACKAGE_IDENTIFIER_MSB_CTRL1_PMA_PMD_PACKAGE_IDENTIFIER_MSB_MASK 0xffff 4326 #define CTL_REGS_PACKAGE_IDENTIFIER_MSB_CTRL1_PMA_PMD_PACKAGE_IDENTIFIER_MSB_ALIGN 0 4327 #define CTL_REGS_PACKAGE_IDENTIFIER_MSB_CTRL1_PMA_PMD_PACKAGE_IDENTIFIER_MSB_BITS 16 4328 #define CTL_REGS_PACKAGE_IDENTIFIER_MSB_CTRL1_PMA_PMD_PACKAGE_IDENTIFIER_MSB_SHIFT 0 4329 4330 4331 /**************************************************************************** 4332 * ctl_regs :: ip_tmux_ctrl 4333 */ 4334 /* ctl_regs :: ip_tmux_ctrl :: reserved0 [15:14] */ 4335 #define CTL_REGS_IP_TMUX_CTRL_RESERVED0_MASK 0xc000 4336 #define CTL_REGS_IP_TMUX_CTRL_RESERVED0_ALIGN 0 4337 #define CTL_REGS_IP_TMUX_CTRL_RESERVED0_BITS 2 4338 #define CTL_REGS_IP_TMUX_CTRL_RESERVED0_SHIFT 14 4339 4340 /* ctl_regs :: ip_tmux_ctrl :: hc_tx_rx_select [13:13] */ 4341 #define CTL_REGS_IP_TMUX_CTRL_HC_TX_RX_SELECT_MASK 0x2000 4342 #define CTL_REGS_IP_TMUX_CTRL_HC_TX_RX_SELECT_ALIGN 0 4343 #define CTL_REGS_IP_TMUX_CTRL_HC_TX_RX_SELECT_BITS 1 4344 #define CTL_REGS_IP_TMUX_CTRL_HC_TX_RX_SELECT_SHIFT 13 4345 4346 /* ctl_regs :: ip_tmux_ctrl :: hc_tmux_select [12:09] */ 4347 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_SELECT_MASK 0x1e00 4348 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_SELECT_ALIGN 0 4349 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_SELECT_BITS 4 4350 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_SELECT_SHIFT 9 4351 4352 /* ctl_regs :: ip_tmux_ctrl :: hc_tmux_out_select [08:06] */ 4353 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_OUT_SELECT_MASK 0x01c0 4354 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_OUT_SELECT_ALIGN 0 4355 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_OUT_SELECT_BITS 3 4356 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_OUT_SELECT_SHIFT 6 4357 4358 /* ctl_regs :: ip_tmux_ctrl :: hc_tmux_out_en [05:05] */ 4359 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_OUT_EN_MASK 0x0020 4360 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_OUT_EN_ALIGN 0 4361 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_OUT_EN_BITS 1 4362 #define CTL_REGS_IP_TMUX_CTRL_HC_TMUX_OUT_EN_SHIFT 5 4363 4364 /* ctl_regs :: ip_tmux_ctrl :: dc_tmux_out_select [04:01] */ 4365 #define CTL_REGS_IP_TMUX_CTRL_DC_TMUX_OUT_SELECT_MASK 0x001e 4366 #define CTL_REGS_IP_TMUX_CTRL_DC_TMUX_OUT_SELECT_ALIGN 0 4367 #define CTL_REGS_IP_TMUX_CTRL_DC_TMUX_OUT_SELECT_BITS 4 4368 #define CTL_REGS_IP_TMUX_CTRL_DC_TMUX_OUT_SELECT_SHIFT 1 4369 4370 /* ctl_regs :: ip_tmux_ctrl :: dc_tmux_out_en [00:00] */ 4371 #define CTL_REGS_IP_TMUX_CTRL_DC_TMUX_OUT_EN_MASK 0x0001 4372 #define CTL_REGS_IP_TMUX_CTRL_DC_TMUX_OUT_EN_ALIGN 0 4373 #define CTL_REGS_IP_TMUX_CTRL_DC_TMUX_OUT_EN_BITS 1 4374 #define CTL_REGS_IP_TMUX_CTRL_DC_TMUX_OUT_EN_SHIFT 0 4375 4376 4377 /**************************************************************************** 4378 * ctl_regs :: otp_fout_3 4379 */ 4380 /* ctl_regs :: otp_fout_3 :: otp_fout3 [15:00] */ 4381 #define CTL_REGS_OTP_FOUT_3_OTP_FOUT3_MASK 0xffff 4382 #define CTL_REGS_OTP_FOUT_3_OTP_FOUT3_ALIGN 0 4383 #define CTL_REGS_OTP_FOUT_3_OTP_FOUT3_BITS 16 4384 #define CTL_REGS_OTP_FOUT_3_OTP_FOUT3_SHIFT 0 4385 4386 4387 /**************************************************************************** 4388 * ctl_regs :: otp_fout_2 4389 */ 4390 /* ctl_regs :: otp_fout_2 :: otp_fout2 [15:00] */ 4391 #define CTL_REGS_OTP_FOUT_2_OTP_FOUT2_MASK 0xffff 4392 #define CTL_REGS_OTP_FOUT_2_OTP_FOUT2_ALIGN 0 4393 #define CTL_REGS_OTP_FOUT_2_OTP_FOUT2_BITS 16 4394 #define CTL_REGS_OTP_FOUT_2_OTP_FOUT2_SHIFT 0 4395 4396 4397 /**************************************************************************** 4398 * ctl_regs :: otp_fout_1 4399 */ 4400 /* ctl_regs :: otp_fout_1 :: otp_fout1 [15:00] */ 4401 #define CTL_REGS_OTP_FOUT_1_OTP_FOUT1_MASK 0xffff 4402 #define CTL_REGS_OTP_FOUT_1_OTP_FOUT1_ALIGN 0 4403 #define CTL_REGS_OTP_FOUT_1_OTP_FOUT1_BITS 16 4404 #define CTL_REGS_OTP_FOUT_1_OTP_FOUT1_SHIFT 0 4405 4406 4407 /**************************************************************************** 4408 * ctl_regs :: otp_fout_0 4409 */ 4410 /* ctl_regs :: otp_fout_0 :: otp_fout0 [15:00] */ 4411 #define CTL_REGS_OTP_FOUT_0_OTP_FOUT0_MASK 0xffff 4412 #define CTL_REGS_OTP_FOUT_0_OTP_FOUT0_ALIGN 0 4413 #define CTL_REGS_OTP_FOUT_0_OTP_FOUT0_BITS 16 4414 #define CTL_REGS_OTP_FOUT_0_OTP_FOUT0_SHIFT 0 4415 4416 4417 /**************************************************************************** 4418 * hs_rx_cdr_regs 4419 */ 4420 /**************************************************************************** 4421 * hs_rx_cdr :: cdr_reset 4422 */ 4423 /* hs_rx_cdr :: cdr_reset :: rg_hlr_hs_dsp_soft_rstb [15:15] */ 4424 #define HS_RX_CDR_CDR_RESET_RG_HLR_HS_DSP_SOFT_RSTB_MASK 0x8000 4425 #define HS_RX_CDR_CDR_RESET_RG_HLR_HS_DSP_SOFT_RSTB_ALIGN 0 4426 #define HS_RX_CDR_CDR_RESET_RG_HLR_HS_DSP_SOFT_RSTB_BITS 1 4427 #define HS_RX_CDR_CDR_RESET_RG_HLR_HS_DSP_SOFT_RSTB_SHIFT 15 4428 4429 /* hs_rx_cdr :: cdr_reset :: rg_pit_clk_en [14:14] */ 4430 #define HS_RX_CDR_CDR_RESET_RG_PIT_CLK_EN_MASK 0x4000 4431 #define HS_RX_CDR_CDR_RESET_RG_PIT_CLK_EN_ALIGN 0 4432 #define HS_RX_CDR_CDR_RESET_RG_PIT_CLK_EN_BITS 1 4433 #define HS_RX_CDR_CDR_RESET_RG_PIT_CLK_EN_SHIFT 14 4434 4435 /* hs_rx_cdr :: cdr_reset :: reserved0 [13:13] */ 4436 #define HS_RX_CDR_CDR_RESET_RESERVED0_MASK 0x2000 4437 #define HS_RX_CDR_CDR_RESET_RESERVED0_ALIGN 0 4438 #define HS_RX_CDR_CDR_RESET_RESERVED0_BITS 1 4439 #define HS_RX_CDR_CDR_RESET_RESERVED0_SHIFT 13 4440 4441 /* hs_rx_cdr :: cdr_reset :: rg_pua_lrx2ltx_soft_rstb [12:12] */ 4442 #define HS_RX_CDR_CDR_RESET_RG_PUA_LRX2LTX_SOFT_RSTB_MASK 0x1000 4443 #define HS_RX_CDR_CDR_RESET_RG_PUA_LRX2LTX_SOFT_RSTB_ALIGN 0 4444 #define HS_RX_CDR_CDR_RESET_RG_PUA_LRX2LTX_SOFT_RSTB_BITS 1 4445 #define HS_RX_CDR_CDR_RESET_RG_PUA_LRX2LTX_SOFT_RSTB_SHIFT 12 4446 4447 /* hs_rx_cdr :: cdr_reset :: rg_pua_lrx2stx_soft_rstb [11:11] */ 4448 #define HS_RX_CDR_CDR_RESET_RG_PUA_LRX2STX_SOFT_RSTB_MASK 0x0800 4449 #define HS_RX_CDR_CDR_RESET_RG_PUA_LRX2STX_SOFT_RSTB_ALIGN 0 4450 #define HS_RX_CDR_CDR_RESET_RG_PUA_LRX2STX_SOFT_RSTB_BITS 1 4451 #define HS_RX_CDR_CDR_RESET_RG_PUA_LRX2STX_SOFT_RSTB_SHIFT 11 4452 4453 /* hs_rx_cdr :: cdr_reset :: rg_swg_clk_en [10:10] */ 4454 #define HS_RX_CDR_CDR_RESET_RG_SWG_CLK_EN_MASK 0x0400 4455 #define HS_RX_CDR_CDR_RESET_RG_SWG_CLK_EN_ALIGN 0 4456 #define HS_RX_CDR_CDR_RESET_RG_SWG_CLK_EN_BITS 1 4457 #define HS_RX_CDR_CDR_RESET_RG_SWG_CLK_EN_SHIFT 10 4458 4459 /* hs_rx_cdr :: cdr_reset :: rg_swg_soft_rstb [09:09] */ 4460 #define HS_RX_CDR_CDR_RESET_RG_SWG_SOFT_RSTB_MASK 0x0200 4461 #define HS_RX_CDR_CDR_RESET_RG_SWG_SOFT_RSTB_ALIGN 0 4462 #define HS_RX_CDR_CDR_RESET_RG_SWG_SOFT_RSTB_BITS 1 4463 #define HS_RX_CDR_CDR_RESET_RG_SWG_SOFT_RSTB_SHIFT 9 4464 4465 /* hs_rx_cdr :: cdr_reset :: rg_pfc_clk_en [08:08] */ 4466 #define HS_RX_CDR_CDR_RESET_RG_PFC_CLK_EN_MASK 0x0100 4467 #define HS_RX_CDR_CDR_RESET_RG_PFC_CLK_EN_ALIGN 0 4468 #define HS_RX_CDR_CDR_RESET_RG_PFC_CLK_EN_BITS 1 4469 #define HS_RX_CDR_CDR_RESET_RG_PFC_CLK_EN_SHIFT 8 4470 4471 /* hs_rx_cdr :: cdr_reset :: rg_pfc_soft_rstb [07:07] */ 4472 #define HS_RX_CDR_CDR_RESET_RG_PFC_SOFT_RSTB_MASK 0x0080 4473 #define HS_RX_CDR_CDR_RESET_RG_PFC_SOFT_RSTB_ALIGN 0 4474 #define HS_RX_CDR_CDR_RESET_RG_PFC_SOFT_RSTB_BITS 1 4475 #define HS_RX_CDR_CDR_RESET_RG_PFC_SOFT_RSTB_SHIFT 7 4476 4477 /* hs_rx_cdr :: cdr_reset :: rg_eml_clk_en [06:06] */ 4478 #define HS_RX_CDR_CDR_RESET_RG_EML_CLK_EN_MASK 0x0040 4479 #define HS_RX_CDR_CDR_RESET_RG_EML_CLK_EN_ALIGN 0 4480 #define HS_RX_CDR_CDR_RESET_RG_EML_CLK_EN_BITS 1 4481 #define HS_RX_CDR_CDR_RESET_RG_EML_CLK_EN_SHIFT 6 4482 4483 /* hs_rx_cdr :: cdr_reset :: rg_eml_soft_rstb [05:05] */ 4484 #define HS_RX_CDR_CDR_RESET_RG_EML_SOFT_RSTB_MASK 0x0020 4485 #define HS_RX_CDR_CDR_RESET_RG_EML_SOFT_RSTB_ALIGN 0 4486 #define HS_RX_CDR_CDR_RESET_RG_EML_SOFT_RSTB_BITS 1 4487 #define HS_RX_CDR_CDR_RESET_RG_EML_SOFT_RSTB_SHIFT 5 4488 4489 /* hs_rx_cdr :: cdr_reset :: rg_cdr_ip_sum_sd_soft_rstb [04:04] */ 4490 #define HS_RX_CDR_CDR_RESET_RG_CDR_IP_SUM_SD_SOFT_RSTB_MASK 0x0010 4491 #define HS_RX_CDR_CDR_RESET_RG_CDR_IP_SUM_SD_SOFT_RSTB_ALIGN 0 4492 #define HS_RX_CDR_CDR_RESET_RG_CDR_IP_SUM_SD_SOFT_RSTB_BITS 1 4493 #define HS_RX_CDR_CDR_RESET_RG_CDR_IP_SUM_SD_SOFT_RSTB_SHIFT 4 4494 4495 /* hs_rx_cdr :: cdr_reset :: rg_cdr_integ_sd_soft_rstb [03:03] */ 4496 #define HS_RX_CDR_CDR_RESET_RG_CDR_INTEG_SD_SOFT_RSTB_MASK 0x0008 4497 #define HS_RX_CDR_CDR_RESET_RG_CDR_INTEG_SD_SOFT_RSTB_ALIGN 0 4498 #define HS_RX_CDR_CDR_RESET_RG_CDR_INTEG_SD_SOFT_RSTB_BITS 1 4499 #define HS_RX_CDR_CDR_RESET_RG_CDR_INTEG_SD_SOFT_RSTB_SHIFT 3 4500 4501 /* hs_rx_cdr :: cdr_reset :: rg_cdr_integ_soft_rstb [02:02] */ 4502 #define HS_RX_CDR_CDR_RESET_RG_CDR_INTEG_SOFT_RSTB_MASK 0x0004 4503 #define HS_RX_CDR_CDR_RESET_RG_CDR_INTEG_SOFT_RSTB_ALIGN 0 4504 #define HS_RX_CDR_CDR_RESET_RG_CDR_INTEG_SOFT_RSTB_BITS 1 4505 #define HS_RX_CDR_CDR_RESET_RG_CDR_INTEG_SOFT_RSTB_SHIFT 2 4506 4507 /* hs_rx_cdr :: cdr_reset :: rg_rdp_soft_rstb [01:01] */ 4508 #define HS_RX_CDR_CDR_RESET_RG_RDP_SOFT_RSTB_MASK 0x0002 4509 #define HS_RX_CDR_CDR_RESET_RG_RDP_SOFT_RSTB_ALIGN 0 4510 #define HS_RX_CDR_CDR_RESET_RG_RDP_SOFT_RSTB_BITS 1 4511 #define HS_RX_CDR_CDR_RESET_RG_RDP_SOFT_RSTB_SHIFT 1 4512 4513 /* hs_rx_cdr :: cdr_reset :: rg_cdr_soft_rstb [00:00] */ 4514 #define HS_RX_CDR_CDR_RESET_RG_CDR_SOFT_RSTB_MASK 0x0001 4515 #define HS_RX_CDR_CDR_RESET_RG_CDR_SOFT_RSTB_ALIGN 0 4516 #define HS_RX_CDR_CDR_RESET_RG_CDR_SOFT_RSTB_BITS 1 4517 #define HS_RX_CDR_CDR_RESET_RG_CDR_SOFT_RSTB_SHIFT 0 4518 4519 4520 /**************************************************************************** 4521 * hs_rx_cdr :: cdr_loop 4522 */ 4523 /* hs_rx_cdr :: cdr_loop :: reserved0 [15:13] */ 4524 #define HS_RX_CDR_CDR_LOOP_RESERVED0_MASK 0xe000 4525 #define HS_RX_CDR_CDR_LOOP_RESERVED0_ALIGN 0 4526 #define HS_RX_CDR_CDR_LOOP_RESERVED0_BITS 3 4527 #define HS_RX_CDR_CDR_LOOP_RESERVED0_SHIFT 13 4528 4529 /* hs_rx_cdr :: cdr_loop :: rg_cdr_integ_consec_sat_det_cntrl [12:09] */ 4530 #define HS_RX_CDR_CDR_LOOP_RG_CDR_INTEG_CONSEC_SAT_DET_CNTRL_MASK 0x1e00 4531 #define HS_RX_CDR_CDR_LOOP_RG_CDR_INTEG_CONSEC_SAT_DET_CNTRL_ALIGN 0 4532 #define HS_RX_CDR_CDR_LOOP_RG_CDR_INTEG_CONSEC_SAT_DET_CNTRL_BITS 4 4533 #define HS_RX_CDR_CDR_LOOP_RG_CDR_INTEG_CONSEC_SAT_DET_CNTRL_SHIFT 9 4534 4535 /* hs_rx_cdr :: cdr_loop :: reserved1 [08:08] */ 4536 #define HS_RX_CDR_CDR_LOOP_RESERVED1_MASK 0x0100 4537 #define HS_RX_CDR_CDR_LOOP_RESERVED1_ALIGN 0 4538 #define HS_RX_CDR_CDR_LOOP_RESERVED1_BITS 1 4539 #define HS_RX_CDR_CDR_LOOP_RESERVED1_SHIFT 8 4540 4541 /* hs_rx_cdr :: cdr_loop :: rg_cdr_integ_byp [07:07] */ 4542 #define HS_RX_CDR_CDR_LOOP_RG_CDR_INTEG_BYP_MASK 0x0080 4543 #define HS_RX_CDR_CDR_LOOP_RG_CDR_INTEG_BYP_ALIGN 0 4544 #define HS_RX_CDR_CDR_LOOP_RG_CDR_INTEG_BYP_BITS 1 4545 #define HS_RX_CDR_CDR_LOOP_RG_CDR_INTEG_BYP_SHIFT 7 4546 4547 /* hs_rx_cdr :: cdr_loop :: rg_cdr_kf [06:04] */ 4548 #define HS_RX_CDR_CDR_LOOP_RG_CDR_KF_MASK 0x0070 4549 #define HS_RX_CDR_CDR_LOOP_RG_CDR_KF_ALIGN 0 4550 #define HS_RX_CDR_CDR_LOOP_RG_CDR_KF_BITS 3 4551 #define HS_RX_CDR_CDR_LOOP_RG_CDR_KF_SHIFT 4 4552 4553 /* hs_rx_cdr :: cdr_loop :: reserved2 [03:02] */ 4554 #define HS_RX_CDR_CDR_LOOP_RESERVED2_MASK 0x000c 4555 #define HS_RX_CDR_CDR_LOOP_RESERVED2_ALIGN 0 4556 #define HS_RX_CDR_CDR_LOOP_RESERVED2_BITS 2 4557 #define HS_RX_CDR_CDR_LOOP_RESERVED2_SHIFT 2 4558 4559 /* hs_rx_cdr :: cdr_loop :: rg_cdr_kp [01:00] */ 4560 #define HS_RX_CDR_CDR_LOOP_RG_CDR_KP_MASK 0x0003 4561 #define HS_RX_CDR_CDR_LOOP_RG_CDR_KP_ALIGN 0 4562 #define HS_RX_CDR_CDR_LOOP_RG_CDR_KP_BITS 2 4563 #define HS_RX_CDR_CDR_LOOP_RG_CDR_KP_SHIFT 0 4564 4565 4566 /**************************************************************************** 4567 * hs_rx_cdr :: cdr_pe_offset 4568 */ 4569 /* hs_rx_cdr :: cdr_pe_offset :: reserved0 [15:11] */ 4570 #define HS_RX_CDR_CDR_PE_OFFSET_RESERVED0_MASK 0xf800 4571 #define HS_RX_CDR_CDR_PE_OFFSET_RESERVED0_ALIGN 0 4572 #define HS_RX_CDR_CDR_PE_OFFSET_RESERVED0_BITS 5 4573 #define HS_RX_CDR_CDR_PE_OFFSET_RESERVED0_SHIFT 11 4574 4575 /* hs_rx_cdr :: cdr_pe_offset :: rg_cdr_pe_os_common [10:08] */ 4576 #define HS_RX_CDR_CDR_PE_OFFSET_RG_CDR_PE_OS_COMMON_MASK 0x0700 4577 #define HS_RX_CDR_CDR_PE_OFFSET_RG_CDR_PE_OS_COMMON_ALIGN 0 4578 #define HS_RX_CDR_CDR_PE_OFFSET_RG_CDR_PE_OS_COMMON_BITS 3 4579 #define HS_RX_CDR_CDR_PE_OFFSET_RG_CDR_PE_OS_COMMON_SHIFT 8 4580 4581 /* hs_rx_cdr :: cdr_pe_offset :: reserved1 [07:05] */ 4582 #define HS_RX_CDR_CDR_PE_OFFSET_RESERVED1_MASK 0x00e0 4583 #define HS_RX_CDR_CDR_PE_OFFSET_RESERVED1_ALIGN 0 4584 #define HS_RX_CDR_CDR_PE_OFFSET_RESERVED1_BITS 3 4585 #define HS_RX_CDR_CDR_PE_OFFSET_RESERVED1_SHIFT 5 4586 4587 /* hs_rx_cdr :: cdr_pe_offset :: rg_cdr_pe_os_integ [04:00] */ 4588 #define HS_RX_CDR_CDR_PE_OFFSET_RG_CDR_PE_OS_INTEG_MASK 0x001f 4589 #define HS_RX_CDR_CDR_PE_OFFSET_RG_CDR_PE_OS_INTEG_ALIGN 0 4590 #define HS_RX_CDR_CDR_PE_OFFSET_RG_CDR_PE_OS_INTEG_BITS 5 4591 #define HS_RX_CDR_CDR_PE_OFFSET_RG_CDR_PE_OS_INTEG_SHIFT 0 4592 4593 4594 /**************************************************************************** 4595 * hs_rx_cdr :: cdr_integ 4596 */ 4597 /* hs_rx_cdr :: cdr_integ :: rg_cdr_integ_val [15:00] */ 4598 #define HS_RX_CDR_CDR_INTEG_RG_CDR_INTEG_VAL_MASK 0xffff 4599 #define HS_RX_CDR_CDR_INTEG_RG_CDR_INTEG_VAL_ALIGN 0 4600 #define HS_RX_CDR_CDR_INTEG_RG_CDR_INTEG_VAL_BITS 16 4601 #define HS_RX_CDR_CDR_INTEG_RG_CDR_INTEG_VAL_SHIFT 0 4602 4603 4604 /**************************************************************************** 4605 * hs_rx_cdr :: cdr_nco_rdp 4606 */ 4607 /* hs_rx_cdr :: cdr_nco_rdp :: reserved0 [15:15] */ 4608 #define HS_RX_CDR_CDR_NCO_RDP_RESERVED0_MASK 0x8000 4609 #define HS_RX_CDR_CDR_NCO_RDP_RESERVED0_ALIGN 0 4610 #define HS_RX_CDR_CDR_NCO_RDP_RESERVED0_BITS 1 4611 #define HS_RX_CDR_CDR_NCO_RDP_RESERVED0_SHIFT 15 4612 4613 /* hs_rx_cdr :: cdr_nco_rdp :: rg_cdr_pi_90_nco_def [14:08] */ 4614 #define HS_RX_CDR_CDR_NCO_RDP_RG_CDR_PI_90_NCO_DEF_MASK 0x7f00 4615 #define HS_RX_CDR_CDR_NCO_RDP_RG_CDR_PI_90_NCO_DEF_ALIGN 0 4616 #define HS_RX_CDR_CDR_NCO_RDP_RG_CDR_PI_90_NCO_DEF_BITS 7 4617 #define HS_RX_CDR_CDR_NCO_RDP_RG_CDR_PI_90_NCO_DEF_SHIFT 8 4618 4619 /* hs_rx_cdr :: cdr_nco_rdp :: reserved1 [07:07] */ 4620 #define HS_RX_CDR_CDR_NCO_RDP_RESERVED1_MASK 0x0080 4621 #define HS_RX_CDR_CDR_NCO_RDP_RESERVED1_ALIGN 0 4622 #define HS_RX_CDR_CDR_NCO_RDP_RESERVED1_BITS 1 4623 #define HS_RX_CDR_CDR_NCO_RDP_RESERVED1_SHIFT 7 4624 4625 /* hs_rx_cdr :: cdr_nco_rdp :: rg_cdr_pi_0_nco_def [06:00] */ 4626 #define HS_RX_CDR_CDR_NCO_RDP_RG_CDR_PI_0_NCO_DEF_MASK 0x007f 4627 #define HS_RX_CDR_CDR_NCO_RDP_RG_CDR_PI_0_NCO_DEF_ALIGN 0 4628 #define HS_RX_CDR_CDR_NCO_RDP_RG_CDR_PI_0_NCO_DEF_BITS 7 4629 #define HS_RX_CDR_CDR_NCO_RDP_RG_CDR_PI_0_NCO_DEF_SHIFT 0 4630 4631 4632 /**************************************************************************** 4633 * hs_rx_cdr :: cdr_nco_eye 4634 */ 4635 /* hs_rx_cdr :: cdr_nco_eye :: reserved0 [15:07] */ 4636 #define HS_RX_CDR_CDR_NCO_EYE_RESERVED0_MASK 0xff80 4637 #define HS_RX_CDR_CDR_NCO_EYE_RESERVED0_ALIGN 0 4638 #define HS_RX_CDR_CDR_NCO_EYE_RESERVED0_BITS 9 4639 #define HS_RX_CDR_CDR_NCO_EYE_RESERVED0_SHIFT 7 4640 4641 /* hs_rx_cdr :: cdr_nco_eye :: rg_cdr_pi_eye_nco_def [06:00] */ 4642 #define HS_RX_CDR_CDR_NCO_EYE_RG_CDR_PI_EYE_NCO_DEF_MASK 0x007f 4643 #define HS_RX_CDR_CDR_NCO_EYE_RG_CDR_PI_EYE_NCO_DEF_ALIGN 0 4644 #define HS_RX_CDR_CDR_NCO_EYE_RG_CDR_PI_EYE_NCO_DEF_BITS 7 4645 #define HS_RX_CDR_CDR_NCO_EYE_RG_CDR_PI_EYE_NCO_DEF_SHIFT 0 4646 4647 4648 /**************************************************************************** 4649 * hs_rx_cdr :: pi_os_ctrl 4650 */ 4651 /* hs_rx_cdr :: pi_os_ctrl :: reserved0 [15:12] */ 4652 #define HS_RX_CDR_PI_OS_CTRL_RESERVED0_MASK 0xf000 4653 #define HS_RX_CDR_PI_OS_CTRL_RESERVED0_ALIGN 0 4654 #define HS_RX_CDR_PI_OS_CTRL_RESERVED0_BITS 4 4655 #define HS_RX_CDR_PI_OS_CTRL_RESERVED0_SHIFT 12 4656 4657 /* hs_rx_cdr :: pi_os_ctrl :: rg_cdr_pi_eye_pha_adj_en [11:11] */ 4658 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_EYE_PHA_ADJ_EN_MASK 0x0800 4659 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_EYE_PHA_ADJ_EN_ALIGN 0 4660 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_EYE_PHA_ADJ_EN_BITS 1 4661 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_EYE_PHA_ADJ_EN_SHIFT 11 4662 4663 /* hs_rx_cdr :: pi_os_ctrl :: rg_cdr_pi_90_pha_adj_en [10:10] */ 4664 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_90_PHA_ADJ_EN_MASK 0x0400 4665 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_90_PHA_ADJ_EN_ALIGN 0 4666 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_90_PHA_ADJ_EN_BITS 1 4667 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_90_PHA_ADJ_EN_SHIFT 10 4668 4669 /* hs_rx_cdr :: pi_os_ctrl :: rg_cdr_pi_0_pha_adj_en [09:09] */ 4670 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_0_PHA_ADJ_EN_MASK 0x0200 4671 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_0_PHA_ADJ_EN_ALIGN 0 4672 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_0_PHA_ADJ_EN_BITS 1 4673 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_0_PHA_ADJ_EN_SHIFT 9 4674 4675 /* hs_rx_cdr :: pi_os_ctrl :: rg_cdr_pi_os_start [08:08] */ 4676 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_OS_START_MASK 0x0100 4677 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_OS_START_ALIGN 0 4678 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_OS_START_BITS 1 4679 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_OS_START_SHIFT 8 4680 4681 /* hs_rx_cdr :: pi_os_ctrl :: rg_cdr_pi_pha_adj_val [07:05] */ 4682 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_PHA_ADJ_VAL_MASK 0x00e0 4683 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_PHA_ADJ_VAL_ALIGN 0 4684 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_PHA_ADJ_VAL_BITS 3 4685 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_PHA_ADJ_VAL_SHIFT 5 4686 4687 /* hs_rx_cdr :: pi_os_ctrl :: rg_cdr_pi_os_cnt [04:00] */ 4688 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_OS_CNT_MASK 0x001f 4689 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_OS_CNT_ALIGN 0 4690 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_OS_CNT_BITS 5 4691 #define HS_RX_CDR_PI_OS_CTRL_RG_CDR_PI_OS_CNT_SHIFT 0 4692 4693 4694 /**************************************************************************** 4695 * hs_rx_cdr :: man_pi_ctrl 4696 */ 4697 /* hs_rx_cdr :: man_pi_ctrl :: reserved0 [15:11] */ 4698 #define HS_RX_CDR_MAN_PI_CTRL_RESERVED0_MASK 0xf800 4699 #define HS_RX_CDR_MAN_PI_CTRL_RESERVED0_ALIGN 0 4700 #define HS_RX_CDR_MAN_PI_CTRL_RESERVED0_BITS 5 4701 #define HS_RX_CDR_MAN_PI_CTRL_RESERVED0_SHIFT 11 4702 4703 /* hs_rx_cdr :: man_pi_ctrl :: rg_cdr_negate_pua_pi_updn [10:10] */ 4704 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_NEGATE_PUA_PI_UPDN_MASK 0x0400 4705 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_NEGATE_PUA_PI_UPDN_ALIGN 0 4706 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_NEGATE_PUA_PI_UPDN_BITS 1 4707 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_NEGATE_PUA_PI_UPDN_SHIFT 10 4708 4709 /* hs_rx_cdr :: man_pi_ctrl :: rg_cdr_man_pha_adj_mode [09:09] */ 4710 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_MODE_MASK 0x0200 4711 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_MODE_ALIGN 0 4712 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_MODE_BITS 1 4713 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_MODE_SHIFT 9 4714 4715 /* hs_rx_cdr :: man_pi_ctrl :: rg_cdr_man_pha_adj_start [08:08] */ 4716 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_START_MASK 0x0100 4717 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_START_ALIGN 0 4718 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_START_BITS 1 4719 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_START_SHIFT 8 4720 4721 /* hs_rx_cdr :: man_pi_ctrl :: rg_cdr_man_pha_adj_cnt [07:00] */ 4722 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_CNT_MASK 0x00ff 4723 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_CNT_ALIGN 0 4724 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_CNT_BITS 8 4725 #define HS_RX_CDR_MAN_PI_CTRL_RG_CDR_MAN_PHA_ADJ_CNT_SHIFT 0 4726 4727 4728 /**************************************************************************** 4729 * hs_rx_cdr :: em_ctrl 4730 */ 4731 /* hs_rx_cdr :: em_ctrl :: reserved0 [15:11] */ 4732 #define HS_RX_CDR_EM_CTRL_RESERVED0_MASK 0xf800 4733 #define HS_RX_CDR_EM_CTRL_RESERVED0_ALIGN 0 4734 #define HS_RX_CDR_EM_CTRL_RESERVED0_BITS 5 4735 #define HS_RX_CDR_EM_CTRL_RESERVED0_SHIFT 11 4736 4737 /* hs_rx_cdr :: em_ctrl :: rg_eml_zero_out_eye [10:10] */ 4738 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_EYE_MASK 0x0400 4739 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_EYE_ALIGN 0 4740 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_EYE_BITS 1 4741 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_EYE_SHIFT 10 4742 4743 /* hs_rx_cdr :: em_ctrl :: rg_eml_zero_out_odd_p [09:09] */ 4744 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_ODD_P_MASK 0x0200 4745 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_ODD_P_ALIGN 0 4746 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_ODD_P_BITS 1 4747 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_ODD_P_SHIFT 9 4748 4749 /* hs_rx_cdr :: em_ctrl :: rg_eml_zero_out_even_p [08:08] */ 4750 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_EVEN_P_MASK 0x0100 4751 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_EVEN_P_ALIGN 0 4752 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_EVEN_P_BITS 1 4753 #define HS_RX_CDR_EM_CTRL_RG_EML_ZERO_OUT_EVEN_P_SHIFT 8 4754 4755 /* hs_rx_cdr :: em_ctrl :: reserved1 [07:07] */ 4756 #define HS_RX_CDR_EM_CTRL_RESERVED1_MASK 0x0080 4757 #define HS_RX_CDR_EM_CTRL_RESERVED1_ALIGN 0 4758 #define HS_RX_CDR_EM_CTRL_RESERVED1_BITS 1 4759 #define HS_RX_CDR_EM_CTRL_RESERVED1_SHIFT 7 4760 4761 /* hs_rx_cdr :: em_ctrl :: rg_eml_comp_start [06:06] */ 4762 #define HS_RX_CDR_EM_CTRL_RG_EML_COMP_START_MASK 0x0040 4763 #define HS_RX_CDR_EM_CTRL_RG_EML_COMP_START_ALIGN 0 4764 #define HS_RX_CDR_EM_CTRL_RG_EML_COMP_START_BITS 1 4765 #define HS_RX_CDR_EM_CTRL_RG_EML_COMP_START_SHIFT 6 4766 4767 /* hs_rx_cdr :: em_ctrl :: rg_eml_comp_p_dly_sel [05:00] */ 4768 #define HS_RX_CDR_EM_CTRL_RG_EML_COMP_P_DLY_SEL_MASK 0x003f 4769 #define HS_RX_CDR_EM_CTRL_RG_EML_COMP_P_DLY_SEL_ALIGN 0 4770 #define HS_RX_CDR_EM_CTRL_RG_EML_COMP_P_DLY_SEL_BITS 6 4771 #define HS_RX_CDR_EM_CTRL_RG_EML_COMP_P_DLY_SEL_SHIFT 0 4772 4773 4774 /**************************************************************************** 4775 * hs_rx_cdr :: em_cnt_15_0 4776 */ 4777 /* hs_rx_cdr :: em_cnt_15_0 :: rg_eml_comp_cnt_15_0 [15:00] */ 4778 #define HS_RX_CDR_EM_CNT_15_0_RG_EML_COMP_CNT_15_0_MASK 0xffff 4779 #define HS_RX_CDR_EM_CNT_15_0_RG_EML_COMP_CNT_15_0_ALIGN 0 4780 #define HS_RX_CDR_EM_CNT_15_0_RG_EML_COMP_CNT_15_0_BITS 16 4781 #define HS_RX_CDR_EM_CNT_15_0_RG_EML_COMP_CNT_15_0_SHIFT 0 4782 4783 4784 /**************************************************************************** 4785 * hs_rx_cdr :: em_cnt_31_16 4786 */ 4787 /* hs_rx_cdr :: em_cnt_31_16 :: rg_eml_comp_cnt_31_16 [15:00] */ 4788 #define HS_RX_CDR_EM_CNT_31_16_RG_EML_COMP_CNT_31_16_MASK 0xffff 4789 #define HS_RX_CDR_EM_CNT_31_16_RG_EML_COMP_CNT_31_16_ALIGN 0 4790 #define HS_RX_CDR_EM_CNT_31_16_RG_EML_COMP_CNT_31_16_BITS 16 4791 #define HS_RX_CDR_EM_CNT_31_16_RG_EML_COMP_CNT_31_16_SHIFT 0 4792 4793 4794 /**************************************************************************** 4795 * hs_rx_cdr :: em_cnt_47_32 4796 */ 4797 /* hs_rx_cdr :: em_cnt_47_32 :: rg_eml_comp_cnt_47_32 [15:00] */ 4798 #define HS_RX_CDR_EM_CNT_47_32_RG_EML_COMP_CNT_47_32_MASK 0xffff 4799 #define HS_RX_CDR_EM_CNT_47_32_RG_EML_COMP_CNT_47_32_ALIGN 0 4800 #define HS_RX_CDR_EM_CNT_47_32_RG_EML_COMP_CNT_47_32_BITS 16 4801 #define HS_RX_CDR_EM_CNT_47_32_RG_EML_COMP_CNT_47_32_SHIFT 0 4802 4803 4804 /**************************************************************************** 4805 * hs_rx_cdr :: pfc_ctrl 4806 */ 4807 /* hs_rx_cdr :: pfc_ctrl :: reserved0 [15:14] */ 4808 #define HS_RX_CDR_PFC_CTRL_RESERVED0_MASK 0xc000 4809 #define HS_RX_CDR_PFC_CTRL_RESERVED0_ALIGN 0 4810 #define HS_RX_CDR_PFC_CTRL_RESERVED0_BITS 2 4811 #define HS_RX_CDR_PFC_CTRL_RESERVED0_SHIFT 14 4812 4813 /* hs_rx_cdr :: pfc_ctrl :: rg_pfc_xcor_cnt_hi [13:08] */ 4814 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_CNT_HI_MASK 0x3f00 4815 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_CNT_HI_ALIGN 0 4816 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_CNT_HI_BITS 6 4817 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_CNT_HI_SHIFT 8 4818 4819 /* hs_rx_cdr :: pfc_ctrl :: rg_pfc_byp_p_tran_chk [07:07] */ 4820 #define HS_RX_CDR_PFC_CTRL_RG_PFC_BYP_P_TRAN_CHK_MASK 0x0080 4821 #define HS_RX_CDR_PFC_CTRL_RG_PFC_BYP_P_TRAN_CHK_ALIGN 0 4822 #define HS_RX_CDR_PFC_CTRL_RG_PFC_BYP_P_TRAN_CHK_BITS 1 4823 #define HS_RX_CDR_PFC_CTRL_RG_PFC_BYP_P_TRAN_CHK_SHIFT 7 4824 4825 /* hs_rx_cdr :: pfc_ctrl :: rg_pfc_xcor_start [06:06] */ 4826 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_START_MASK 0x0040 4827 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_START_ALIGN 0 4828 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_START_BITS 1 4829 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_START_SHIFT 6 4830 4831 /* hs_rx_cdr :: pfc_ctrl :: rg_pfc_xcor_p_dly_sel [05:00] */ 4832 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_P_DLY_SEL_MASK 0x003f 4833 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_P_DLY_SEL_ALIGN 0 4834 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_P_DLY_SEL_BITS 6 4835 #define HS_RX_CDR_PFC_CTRL_RG_PFC_XCOR_P_DLY_SEL_SHIFT 0 4836 4837 4838 /**************************************************************************** 4839 * hs_rx_cdr :: pfc_cnt 4840 */ 4841 /* hs_rx_cdr :: pfc_cnt :: rg_pfc_xcor_cnt_lo [15:00] */ 4842 #define HS_RX_CDR_PFC_CNT_RG_PFC_XCOR_CNT_LO_MASK 0xffff 4843 #define HS_RX_CDR_PFC_CNT_RG_PFC_XCOR_CNT_LO_ALIGN 0 4844 #define HS_RX_CDR_PFC_CNT_RG_PFC_XCOR_CNT_LO_BITS 16 4845 #define HS_RX_CDR_PFC_CNT_RG_PFC_XCOR_CNT_LO_SHIFT 0 4846 4847 4848 /**************************************************************************** 4849 * hs_rx_cdr :: swg_period 4850 */ 4851 /* hs_rx_cdr :: swg_period :: rg_swg_half_period_val [15:00] */ 4852 #define HS_RX_CDR_SWG_PERIOD_RG_SWG_HALF_PERIOD_VAL_MASK 0xffff 4853 #define HS_RX_CDR_SWG_PERIOD_RG_SWG_HALF_PERIOD_VAL_ALIGN 0 4854 #define HS_RX_CDR_SWG_PERIOD_RG_SWG_HALF_PERIOD_VAL_BITS 16 4855 #define HS_RX_CDR_SWG_PERIOD_RG_SWG_HALF_PERIOD_VAL_SHIFT 0 4856 4857 4858 /**************************************************************************** 4859 * hs_rx_cdr :: swg_y_val 4860 */ 4861 /* hs_rx_cdr :: swg_y_val :: rg_swg_y_init_val_lo [15:00] */ 4862 #define HS_RX_CDR_SWG_Y_VAL_RG_SWG_Y_INIT_VAL_LO_MASK 0xffff 4863 #define HS_RX_CDR_SWG_Y_VAL_RG_SWG_Y_INIT_VAL_LO_ALIGN 0 4864 #define HS_RX_CDR_SWG_Y_VAL_RG_SWG_Y_INIT_VAL_LO_BITS 16 4865 #define HS_RX_CDR_SWG_Y_VAL_RG_SWG_Y_INIT_VAL_LO_SHIFT 0 4866 4867 4868 /**************************************************************************** 4869 * hs_rx_cdr :: swg_yscale 4870 */ 4871 /* hs_rx_cdr :: swg_yscale :: rg_swg_delta1_shift_val [15:13] */ 4872 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_DELTA1_SHIFT_VAL_MASK 0xe000 4873 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_DELTA1_SHIFT_VAL_ALIGN 0 4874 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_DELTA1_SHIFT_VAL_BITS 3 4875 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_DELTA1_SHIFT_VAL_SHIFT 13 4876 4877 /* hs_rx_cdr :: swg_yscale :: rg_swg_delta2_shift_val [12:10] */ 4878 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_DELTA2_SHIFT_VAL_MASK 0x1c00 4879 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_DELTA2_SHIFT_VAL_ALIGN 0 4880 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_DELTA2_SHIFT_VAL_BITS 3 4881 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_DELTA2_SHIFT_VAL_SHIFT 10 4882 4883 /* hs_rx_cdr :: swg_yscale :: rg_swg_y_init_val_hi [09:08] */ 4884 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_Y_INIT_VAL_HI_MASK 0x0300 4885 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_Y_INIT_VAL_HI_ALIGN 0 4886 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_Y_INIT_VAL_HI_BITS 2 4887 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_Y_INIT_VAL_HI_SHIFT 8 4888 4889 /* hs_rx_cdr :: swg_yscale :: reserved0 [07:07] */ 4890 #define HS_RX_CDR_SWG_YSCALE_RESERVED0_MASK 0x0080 4891 #define HS_RX_CDR_SWG_YSCALE_RESERVED0_ALIGN 0 4892 #define HS_RX_CDR_SWG_YSCALE_RESERVED0_BITS 1 4893 #define HS_RX_CDR_SWG_YSCALE_RESERVED0_SHIFT 7 4894 4895 /* hs_rx_cdr :: swg_yscale :: rg_swg_enable [06:06] */ 4896 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_ENABLE_MASK 0x0040 4897 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_ENABLE_ALIGN 0 4898 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_ENABLE_BITS 1 4899 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_ENABLE_SHIFT 6 4900 4901 /* hs_rx_cdr :: swg_yscale :: rg_swg_y_scale_val [05:00] */ 4902 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_Y_SCALE_VAL_MASK 0x003f 4903 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_Y_SCALE_VAL_ALIGN 0 4904 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_Y_SCALE_VAL_BITS 6 4905 #define HS_RX_CDR_SWG_YSCALE_RG_SWG_Y_SCALE_VAL_SHIFT 0 4906 4907 4908 /**************************************************************************** 4909 * hs_rx_cdr :: swg_delta_1 4910 */ 4911 /* hs_rx_cdr :: swg_delta_1 :: rg_swg_delta1_init_val_lo [15:00] */ 4912 #define HS_RX_CDR_SWG_DELTA_1_RG_SWG_DELTA1_INIT_VAL_LO_MASK 0xffff 4913 #define HS_RX_CDR_SWG_DELTA_1_RG_SWG_DELTA1_INIT_VAL_LO_ALIGN 0 4914 #define HS_RX_CDR_SWG_DELTA_1_RG_SWG_DELTA1_INIT_VAL_LO_BITS 16 4915 #define HS_RX_CDR_SWG_DELTA_1_RG_SWG_DELTA1_INIT_VAL_LO_SHIFT 0 4916 4917 4918 /**************************************************************************** 4919 * hs_rx_cdr :: swg_delta_2 4920 */ 4921 /* hs_rx_cdr :: swg_delta_2 :: rg_swg_delta2_init_val_lo [15:00] */ 4922 #define HS_RX_CDR_SWG_DELTA_2_RG_SWG_DELTA2_INIT_VAL_LO_MASK 0xffff 4923 #define HS_RX_CDR_SWG_DELTA_2_RG_SWG_DELTA2_INIT_VAL_LO_ALIGN 0 4924 #define HS_RX_CDR_SWG_DELTA_2_RG_SWG_DELTA2_INIT_VAL_LO_BITS 16 4925 #define HS_RX_CDR_SWG_DELTA_2_RG_SWG_DELTA2_INIT_VAL_LO_SHIFT 0 4926 4927 4928 /**************************************************************************** 4929 * hs_rx_cdr :: swg_delta_3 4930 */ 4931 /* hs_rx_cdr :: swg_delta_3 :: rg_swg_delta1_init_val_hi [15:14] */ 4932 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA1_INIT_VAL_HI_MASK 0xc000 4933 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA1_INIT_VAL_HI_ALIGN 0 4934 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA1_INIT_VAL_HI_BITS 2 4935 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA1_INIT_VAL_HI_SHIFT 14 4936 4937 /* hs_rx_cdr :: swg_delta_3 :: rg_swg_delta2_init_val_hi [13:12] */ 4938 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA2_INIT_VAL_HI_MASK 0x3000 4939 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA2_INIT_VAL_HI_ALIGN 0 4940 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA2_INIT_VAL_HI_BITS 2 4941 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA2_INIT_VAL_HI_SHIFT 12 4942 4943 /* hs_rx_cdr :: swg_delta_3 :: rg_swg_delta3_val [11:00] */ 4944 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA3_VAL_MASK 0x0fff 4945 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA3_VAL_ALIGN 0 4946 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA3_VAL_BITS 12 4947 #define HS_RX_CDR_SWG_DELTA_3_RG_SWG_DELTA3_VAL_SHIFT 0 4948 4949 4950 /**************************************************************************** 4951 * hs_rx_cdr :: cdr_stat_tasks 4952 */ 4953 /* hs_rx_cdr :: cdr_stat_tasks :: reserved0 [15:14] */ 4954 #define HS_RX_CDR_CDR_STAT_TASKS_RESERVED0_MASK 0xc000 4955 #define HS_RX_CDR_CDR_STAT_TASKS_RESERVED0_ALIGN 0 4956 #define HS_RX_CDR_CDR_STAT_TASKS_RESERVED0_BITS 2 4957 #define HS_RX_CDR_CDR_STAT_TASKS_RESERVED0_SHIFT 14 4958 4959 /* hs_rx_cdr :: cdr_stat_tasks :: cdr_rg_integ_sat_det_lh [13:13] */ 4960 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_INTEG_SAT_DET_LH_MASK 0x2000 4961 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_INTEG_SAT_DET_LH_ALIGN 0 4962 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_INTEG_SAT_DET_LH_BITS 1 4963 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_INTEG_SAT_DET_LH_SHIFT 13 4964 4965 /* hs_rx_cdr :: cdr_stat_tasks :: cdr_rg_integ_consec_sat_det_lh [12:12] */ 4966 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_INTEG_CONSEC_SAT_DET_LH_MASK 0x1000 4967 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_INTEG_CONSEC_SAT_DET_LH_ALIGN 0 4968 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_INTEG_CONSEC_SAT_DET_LH_BITS 1 4969 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_INTEG_CONSEC_SAT_DET_LH_SHIFT 12 4970 4971 /* hs_rx_cdr :: cdr_stat_tasks :: pfc_rg_xcor_done_lh [11:11] */ 4972 #define HS_RX_CDR_CDR_STAT_TASKS_PFC_RG_XCOR_DONE_LH_MASK 0x0800 4973 #define HS_RX_CDR_CDR_STAT_TASKS_PFC_RG_XCOR_DONE_LH_ALIGN 0 4974 #define HS_RX_CDR_CDR_STAT_TASKS_PFC_RG_XCOR_DONE_LH_BITS 1 4975 #define HS_RX_CDR_CDR_STAT_TASKS_PFC_RG_XCOR_DONE_LH_SHIFT 11 4976 4977 /* hs_rx_cdr :: cdr_stat_tasks :: eml_rg_comp_done_lh [10:10] */ 4978 #define HS_RX_CDR_CDR_STAT_TASKS_EML_RG_COMP_DONE_LH_MASK 0x0400 4979 #define HS_RX_CDR_CDR_STAT_TASKS_EML_RG_COMP_DONE_LH_ALIGN 0 4980 #define HS_RX_CDR_CDR_STAT_TASKS_EML_RG_COMP_DONE_LH_BITS 1 4981 #define HS_RX_CDR_CDR_STAT_TASKS_EML_RG_COMP_DONE_LH_SHIFT 10 4982 4983 /* hs_rx_cdr :: cdr_stat_tasks :: cdr_rg_man_pha_adj_done_lh [09:09] */ 4984 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_MAN_PHA_ADJ_DONE_LH_MASK 0x0200 4985 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_MAN_PHA_ADJ_DONE_LH_ALIGN 0 4986 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_MAN_PHA_ADJ_DONE_LH_BITS 1 4987 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_MAN_PHA_ADJ_DONE_LH_SHIFT 9 4988 4989 /* hs_rx_cdr :: cdr_stat_tasks :: cdr_rg_pi_os_done_lh [08:08] */ 4990 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_PI_OS_DONE_LH_MASK 0x0100 4991 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_PI_OS_DONE_LH_ALIGN 0 4992 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_PI_OS_DONE_LH_BITS 1 4993 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_PI_OS_DONE_LH_SHIFT 8 4994 4995 /* hs_rx_cdr :: cdr_stat_tasks :: reserved1 [07:07] */ 4996 #define HS_RX_CDR_CDR_STAT_TASKS_RESERVED1_MASK 0x0080 4997 #define HS_RX_CDR_CDR_STAT_TASKS_RESERVED1_ALIGN 0 4998 #define HS_RX_CDR_CDR_STAT_TASKS_RESERVED1_BITS 1 4999 #define HS_RX_CDR_CDR_STAT_TASKS_RESERVED1_SHIFT 7 5000 5001 /* hs_rx_cdr :: cdr_stat_tasks :: cdr_rg_pe_sum [06:00] */ 5002 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_PE_SUM_MASK 0x007f 5003 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_PE_SUM_ALIGN 0 5004 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_PE_SUM_BITS 7 5005 #define HS_RX_CDR_CDR_STAT_TASKS_CDR_RG_PE_SUM_SHIFT 0 5006 5007 5008 /**************************************************************************** 5009 * hs_rx_cdr :: cdr_stat_integ 5010 */ 5011 /* hs_rx_cdr :: cdr_stat_integ :: cdr_rg_integ_val [15:00] */ 5012 #define HS_RX_CDR_CDR_STAT_INTEG_CDR_RG_INTEG_VAL_MASK 0xffff 5013 #define HS_RX_CDR_CDR_STAT_INTEG_CDR_RG_INTEG_VAL_ALIGN 0 5014 #define HS_RX_CDR_CDR_STAT_INTEG_CDR_RG_INTEG_VAL_BITS 16 5015 #define HS_RX_CDR_CDR_STAT_INTEG_CDR_RG_INTEG_VAL_SHIFT 0 5016 5017 5018 /**************************************************************************** 5019 * hs_rx_cdr :: cdr_stat_nco_rdp 5020 */ 5021 /* hs_rx_cdr :: cdr_stat_nco_rdp :: reserved0 [15:15] */ 5022 #define HS_RX_CDR_CDR_STAT_NCO_RDP_RESERVED0_MASK 0x8000 5023 #define HS_RX_CDR_CDR_STAT_NCO_RDP_RESERVED0_ALIGN 0 5024 #define HS_RX_CDR_CDR_STAT_NCO_RDP_RESERVED0_BITS 1 5025 #define HS_RX_CDR_CDR_STAT_NCO_RDP_RESERVED0_SHIFT 15 5026 5027 /* hs_rx_cdr :: cdr_stat_nco_rdp :: cdr_rg_pi_90_nco [14:08] */ 5028 #define HS_RX_CDR_CDR_STAT_NCO_RDP_CDR_RG_PI_90_NCO_MASK 0x7f00 5029 #define HS_RX_CDR_CDR_STAT_NCO_RDP_CDR_RG_PI_90_NCO_ALIGN 0 5030 #define HS_RX_CDR_CDR_STAT_NCO_RDP_CDR_RG_PI_90_NCO_BITS 7 5031 #define HS_RX_CDR_CDR_STAT_NCO_RDP_CDR_RG_PI_90_NCO_SHIFT 8 5032 5033 /* hs_rx_cdr :: cdr_stat_nco_rdp :: reserved1 [07:07] */ 5034 #define HS_RX_CDR_CDR_STAT_NCO_RDP_RESERVED1_MASK 0x0080 5035 #define HS_RX_CDR_CDR_STAT_NCO_RDP_RESERVED1_ALIGN 0 5036 #define HS_RX_CDR_CDR_STAT_NCO_RDP_RESERVED1_BITS 1 5037 #define HS_RX_CDR_CDR_STAT_NCO_RDP_RESERVED1_SHIFT 7 5038 5039 /* hs_rx_cdr :: cdr_stat_nco_rdp :: cdr_rg_pi_0_nco [06:00] */ 5040 #define HS_RX_CDR_CDR_STAT_NCO_RDP_CDR_RG_PI_0_NCO_MASK 0x007f 5041 #define HS_RX_CDR_CDR_STAT_NCO_RDP_CDR_RG_PI_0_NCO_ALIGN 0 5042 #define HS_RX_CDR_CDR_STAT_NCO_RDP_CDR_RG_PI_0_NCO_BITS 7 5043 #define HS_RX_CDR_CDR_STAT_NCO_RDP_CDR_RG_PI_0_NCO_SHIFT 0 5044 5045 5046 /**************************************************************************** 5047 * hs_rx_cdr :: cdr_stat_nco_eye 5048 */ 5049 /* hs_rx_cdr :: cdr_stat_nco_eye :: reserved0 [15:07] */ 5050 #define HS_RX_CDR_CDR_STAT_NCO_EYE_RESERVED0_MASK 0xff80 5051 #define HS_RX_CDR_CDR_STAT_NCO_EYE_RESERVED0_ALIGN 0 5052 #define HS_RX_CDR_CDR_STAT_NCO_EYE_RESERVED0_BITS 9 5053 #define HS_RX_CDR_CDR_STAT_NCO_EYE_RESERVED0_SHIFT 7 5054 5055 /* hs_rx_cdr :: cdr_stat_nco_eye :: cdr_rg_pi_eye_nco [06:00] */ 5056 #define HS_RX_CDR_CDR_STAT_NCO_EYE_CDR_RG_PI_EYE_NCO_MASK 0x007f 5057 #define HS_RX_CDR_CDR_STAT_NCO_EYE_CDR_RG_PI_EYE_NCO_ALIGN 0 5058 #define HS_RX_CDR_CDR_STAT_NCO_EYE_CDR_RG_PI_EYE_NCO_BITS 7 5059 #define HS_RX_CDR_CDR_STAT_NCO_EYE_CDR_RG_PI_EYE_NCO_SHIFT 0 5060 5061 5062 /**************************************************************************** 5063 * hs_rx_cdr :: eml_stat_acc_hi 5064 */ 5065 /* hs_rx_cdr :: eml_stat_acc_hi :: reserved0 [15:08] */ 5066 #define HS_RX_CDR_EML_STAT_ACC_HI_RESERVED0_MASK 0xff00 5067 #define HS_RX_CDR_EML_STAT_ACC_HI_RESERVED0_ALIGN 0 5068 #define HS_RX_CDR_EML_STAT_ACC_HI_RESERVED0_BITS 8 5069 #define HS_RX_CDR_EML_STAT_ACC_HI_RESERVED0_SHIFT 8 5070 5071 /* hs_rx_cdr :: eml_stat_acc_hi :: eml_rg_comp_mismatch_cnt_hi [07:00] */ 5072 #define HS_RX_CDR_EML_STAT_ACC_HI_EML_RG_COMP_MISMATCH_CNT_HI_MASK 0x00ff 5073 #define HS_RX_CDR_EML_STAT_ACC_HI_EML_RG_COMP_MISMATCH_CNT_HI_ALIGN 0 5074 #define HS_RX_CDR_EML_STAT_ACC_HI_EML_RG_COMP_MISMATCH_CNT_HI_BITS 8 5075 #define HS_RX_CDR_EML_STAT_ACC_HI_EML_RG_COMP_MISMATCH_CNT_HI_SHIFT 0 5076 5077 5078 /**************************************************************************** 5079 * hs_rx_cdr :: eml_stat_acc_lo 5080 */ 5081 /* hs_rx_cdr :: eml_stat_acc_lo :: eml_rg_comp_mismatch_cnt_lo [15:00] */ 5082 #define HS_RX_CDR_EML_STAT_ACC_LO_EML_RG_COMP_MISMATCH_CNT_LO_MASK 0xffff 5083 #define HS_RX_CDR_EML_STAT_ACC_LO_EML_RG_COMP_MISMATCH_CNT_LO_ALIGN 0 5084 #define HS_RX_CDR_EML_STAT_ACC_LO_EML_RG_COMP_MISMATCH_CNT_LO_BITS 16 5085 #define HS_RX_CDR_EML_STAT_ACC_LO_EML_RG_COMP_MISMATCH_CNT_LO_SHIFT 0 5086 5087 5088 /**************************************************************************** 5089 * hs_rx_cdr :: pfc_stat_acc_hi 5090 */ 5091 /* hs_rx_cdr :: pfc_stat_acc_hi :: pfc_rg_xcor_val_hi [15:00] */ 5092 #define HS_RX_CDR_PFC_STAT_ACC_HI_PFC_RG_XCOR_VAL_HI_MASK 0xffff 5093 #define HS_RX_CDR_PFC_STAT_ACC_HI_PFC_RG_XCOR_VAL_HI_ALIGN 0 5094 #define HS_RX_CDR_PFC_STAT_ACC_HI_PFC_RG_XCOR_VAL_HI_BITS 16 5095 #define HS_RX_CDR_PFC_STAT_ACC_HI_PFC_RG_XCOR_VAL_HI_SHIFT 0 5096 5097 5098 /**************************************************************************** 5099 * hs_rx_cdr :: pfc_stat_acc_lo 5100 */ 5101 /* hs_rx_cdr :: pfc_stat_acc_lo :: pfc_rg_xcor_val_lo [15:00] */ 5102 #define HS_RX_CDR_PFC_STAT_ACC_LO_PFC_RG_XCOR_VAL_LO_MASK 0xffff 5103 #define HS_RX_CDR_PFC_STAT_ACC_LO_PFC_RG_XCOR_VAL_LO_ALIGN 0 5104 #define HS_RX_CDR_PFC_STAT_ACC_LO_PFC_RG_XCOR_VAL_LO_BITS 16 5105 #define HS_RX_CDR_PFC_STAT_ACC_LO_PFC_RG_XCOR_VAL_LO_SHIFT 0 5106 5107 5108 /**************************************************************************** 5109 * hs_rx_cdr_cm_regs 5110 */ 5111 /**************************************************************************** 5112 * hs_rx_cdr_cm :: cdr_common_wr_en 5113 */ 5114 /* hs_rx_cdr_cm :: cdr_common_wr_en :: reserved0 [15:06] */ 5115 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RESERVED0_MASK 0xffc0 5116 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RESERVED0_ALIGN 0 5117 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RESERVED0_BITS 10 5118 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RESERVED0_SHIFT 6 5119 5120 /* hs_rx_cdr_cm :: cdr_common_wr_en :: rg_cdr_integ_consec_sat_det_cntrl_wr_en [05:05] */ 5121 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_INTEG_CONSEC_SAT_DET_CNTRL_WR_EN_MASK 0x0020 5122 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_INTEG_CONSEC_SAT_DET_CNTRL_WR_EN_ALIGN 0 5123 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_INTEG_CONSEC_SAT_DET_CNTRL_WR_EN_BITS 1 5124 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_INTEG_CONSEC_SAT_DET_CNTRL_WR_EN_SHIFT 5 5125 5126 /* hs_rx_cdr_cm :: cdr_common_wr_en :: rg_cdr_pe_os_integ_wr_en [04:04] */ 5127 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_PE_OS_INTEG_WR_EN_MASK 0x0010 5128 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_PE_OS_INTEG_WR_EN_ALIGN 0 5129 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_PE_OS_INTEG_WR_EN_BITS 1 5130 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_PE_OS_INTEG_WR_EN_SHIFT 4 5131 5132 /* hs_rx_cdr_cm :: cdr_common_wr_en :: rg_cdr_pe_os_common_wr_en [03:03] */ 5133 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_PE_OS_COMMON_WR_EN_MASK 0x0008 5134 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_PE_OS_COMMON_WR_EN_ALIGN 0 5135 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_PE_OS_COMMON_WR_EN_BITS 1 5136 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_PE_OS_COMMON_WR_EN_SHIFT 3 5137 5138 /* hs_rx_cdr_cm :: cdr_common_wr_en :: rg_cdr_integ_wr_en [02:02] */ 5139 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_INTEG_WR_EN_MASK 0x0004 5140 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_INTEG_WR_EN_ALIGN 0 5141 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_INTEG_WR_EN_BITS 1 5142 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_INTEG_WR_EN_SHIFT 2 5143 5144 /* hs_rx_cdr_cm :: cdr_common_wr_en :: rg_cdr_kf_wr_en [01:01] */ 5145 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_KF_WR_EN_MASK 0x0002 5146 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_KF_WR_EN_ALIGN 0 5147 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_KF_WR_EN_BITS 1 5148 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_KF_WR_EN_SHIFT 1 5149 5150 /* hs_rx_cdr_cm :: cdr_common_wr_en :: rg_cdr_kp_wr_en [00:00] */ 5151 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_KP_WR_EN_MASK 0x0001 5152 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_KP_WR_EN_ALIGN 0 5153 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_KP_WR_EN_BITS 1 5154 #define HS_RX_CDR_CM_CDR_COMMON_WR_EN_RG_CDR_KP_WR_EN_SHIFT 0 5155 5156 5157 /**************************************************************************** 5158 * hs_rx_cdr_sh_regs 5159 */ 5160 /**************************************************************************** 5161 * hs_rx_cdr_sh :: sh_cdr_stat_tasks 5162 */ 5163 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: reserved0 [15:14] */ 5164 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_RESERVED0_MASK 0xc000 5165 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_RESERVED0_ALIGN 0 5166 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_RESERVED0_BITS 2 5167 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_RESERVED0_SHIFT 14 5168 5169 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: cdr_rg_sh_integ_sat_det_lh [13:13] */ 5170 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_INTEG_SAT_DET_LH_MASK 0x2000 5171 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_INTEG_SAT_DET_LH_ALIGN 0 5172 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_INTEG_SAT_DET_LH_BITS 1 5173 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_INTEG_SAT_DET_LH_SHIFT 13 5174 5175 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: cdr_rg_sh_integ_consec_sat_det_lh [12:12] */ 5176 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_INTEG_CONSEC_SAT_DET_LH_MASK 0x1000 5177 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_INTEG_CONSEC_SAT_DET_LH_ALIGN 0 5178 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_INTEG_CONSEC_SAT_DET_LH_BITS 1 5179 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_INTEG_CONSEC_SAT_DET_LH_SHIFT 12 5180 5181 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: pfc_rg_sh_xcor_done_lh [11:11] */ 5182 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_PFC_RG_SH_XCOR_DONE_LH_MASK 0x0800 5183 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_PFC_RG_SH_XCOR_DONE_LH_ALIGN 0 5184 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_PFC_RG_SH_XCOR_DONE_LH_BITS 1 5185 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_PFC_RG_SH_XCOR_DONE_LH_SHIFT 11 5186 5187 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: eml_rg_sh_comp_done_lh [10:10] */ 5188 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_EML_RG_SH_COMP_DONE_LH_MASK 0x0400 5189 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_EML_RG_SH_COMP_DONE_LH_ALIGN 0 5190 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_EML_RG_SH_COMP_DONE_LH_BITS 1 5191 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_EML_RG_SH_COMP_DONE_LH_SHIFT 10 5192 5193 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: cdr_rg_sh_man_pha_adj_done_lh [09:09] */ 5194 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_MAN_PHA_ADJ_DONE_LH_MASK 0x0200 5195 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_MAN_PHA_ADJ_DONE_LH_ALIGN 0 5196 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_MAN_PHA_ADJ_DONE_LH_BITS 1 5197 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_MAN_PHA_ADJ_DONE_LH_SHIFT 9 5198 5199 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: cdr_rg_sh_pi_os_done_lh [08:08] */ 5200 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_PI_OS_DONE_LH_MASK 0x0100 5201 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_PI_OS_DONE_LH_ALIGN 0 5202 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_PI_OS_DONE_LH_BITS 1 5203 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_PI_OS_DONE_LH_SHIFT 8 5204 5205 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: reserved1 [07:07] */ 5206 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_RESERVED1_MASK 0x0080 5207 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_RESERVED1_ALIGN 0 5208 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_RESERVED1_BITS 1 5209 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_RESERVED1_SHIFT 7 5210 5211 /* hs_rx_cdr_sh :: sh_cdr_stat_tasks :: cdr_rg_sh_pe_sum [06:00] */ 5212 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_PE_SUM_MASK 0x007f 5213 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_PE_SUM_ALIGN 0 5214 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_PE_SUM_BITS 7 5215 #define HS_RX_CDR_SH_SH_CDR_STAT_TASKS_CDR_RG_SH_PE_SUM_SHIFT 0 5216 5217 5218 /**************************************************************************** 5219 * hs_rx_cdr_sh :: sh_cdr_stat_integ 5220 */ 5221 /* hs_rx_cdr_sh :: sh_cdr_stat_integ :: cdr_rg_sh_integ_val [15:00] */ 5222 #define HS_RX_CDR_SH_SH_CDR_STAT_INTEG_CDR_RG_SH_INTEG_VAL_MASK 0xffff 5223 #define HS_RX_CDR_SH_SH_CDR_STAT_INTEG_CDR_RG_SH_INTEG_VAL_ALIGN 0 5224 #define HS_RX_CDR_SH_SH_CDR_STAT_INTEG_CDR_RG_SH_INTEG_VAL_BITS 16 5225 #define HS_RX_CDR_SH_SH_CDR_STAT_INTEG_CDR_RG_SH_INTEG_VAL_SHIFT 0 5226 5227 5228 /**************************************************************************** 5229 * hs_rx_cdr_sh :: sh_cdr_stat_nco_rdp 5230 */ 5231 /* hs_rx_cdr_sh :: sh_cdr_stat_nco_rdp :: reserved0 [15:15] */ 5232 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_RESERVED0_MASK 0x8000 5233 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_RESERVED0_ALIGN 0 5234 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_RESERVED0_BITS 1 5235 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_RESERVED0_SHIFT 15 5236 5237 /* hs_rx_cdr_sh :: sh_cdr_stat_nco_rdp :: cdr_rg_sh_pi_90_nco [14:08] */ 5238 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_CDR_RG_SH_PI_90_NCO_MASK 0x7f00 5239 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_CDR_RG_SH_PI_90_NCO_ALIGN 0 5240 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_CDR_RG_SH_PI_90_NCO_BITS 7 5241 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_CDR_RG_SH_PI_90_NCO_SHIFT 8 5242 5243 /* hs_rx_cdr_sh :: sh_cdr_stat_nco_rdp :: reserved1 [07:07] */ 5244 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_RESERVED1_MASK 0x0080 5245 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_RESERVED1_ALIGN 0 5246 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_RESERVED1_BITS 1 5247 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_RESERVED1_SHIFT 7 5248 5249 /* hs_rx_cdr_sh :: sh_cdr_stat_nco_rdp :: cdr_rg_sh_pi_0_nco [06:00] */ 5250 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_CDR_RG_SH_PI_0_NCO_MASK 0x007f 5251 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_CDR_RG_SH_PI_0_NCO_ALIGN 0 5252 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_CDR_RG_SH_PI_0_NCO_BITS 7 5253 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_RDP_CDR_RG_SH_PI_0_NCO_SHIFT 0 5254 5255 5256 /**************************************************************************** 5257 * hs_rx_cdr_sh :: sh_cdr_stat_nco_eye 5258 */ 5259 /* hs_rx_cdr_sh :: sh_cdr_stat_nco_eye :: reserved0 [15:07] */ 5260 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE_RESERVED0_MASK 0xff80 5261 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE_RESERVED0_ALIGN 0 5262 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE_RESERVED0_BITS 9 5263 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE_RESERVED0_SHIFT 7 5264 5265 /* hs_rx_cdr_sh :: sh_cdr_stat_nco_eye :: cdr_rg_sh_pi_eye_nco [06:00] */ 5266 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE_CDR_RG_SH_PI_EYE_NCO_MASK 0x007f 5267 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE_CDR_RG_SH_PI_EYE_NCO_ALIGN 0 5268 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE_CDR_RG_SH_PI_EYE_NCO_BITS 7 5269 #define HS_RX_CDR_SH_SH_CDR_STAT_NCO_EYE_CDR_RG_SH_PI_EYE_NCO_SHIFT 0 5270 5271 5272 /**************************************************************************** 5273 * hs_rx_cdr_sh :: sh_eml_stat_acc_hi 5274 */ 5275 /* hs_rx_cdr_sh :: sh_eml_stat_acc_hi :: reserved0 [15:08] */ 5276 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI_RESERVED0_MASK 0xff00 5277 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI_RESERVED0_ALIGN 0 5278 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI_RESERVED0_BITS 8 5279 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI_RESERVED0_SHIFT 8 5280 5281 /* hs_rx_cdr_sh :: sh_eml_stat_acc_hi :: eml_rg_sh_comp_mismatch_cnt_hi [07:00] */ 5282 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI_EML_RG_SH_COMP_MISMATCH_CNT_HI_MASK 0x00ff 5283 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI_EML_RG_SH_COMP_MISMATCH_CNT_HI_ALIGN 0 5284 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI_EML_RG_SH_COMP_MISMATCH_CNT_HI_BITS 8 5285 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_HI_EML_RG_SH_COMP_MISMATCH_CNT_HI_SHIFT 0 5286 5287 5288 /**************************************************************************** 5289 * hs_rx_cdr_sh :: sh_eml_stat_acc_lo 5290 */ 5291 /* hs_rx_cdr_sh :: sh_eml_stat_acc_lo :: eml_rg_sh_comp_mismatch_cnt_lo [15:00] */ 5292 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_LO_EML_RG_SH_COMP_MISMATCH_CNT_LO_MASK 0xffff 5293 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_LO_EML_RG_SH_COMP_MISMATCH_CNT_LO_ALIGN 0 5294 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_LO_EML_RG_SH_COMP_MISMATCH_CNT_LO_BITS 16 5295 #define HS_RX_CDR_SH_SH_EML_STAT_ACC_LO_EML_RG_SH_COMP_MISMATCH_CNT_LO_SHIFT 0 5296 5297 5298 /**************************************************************************** 5299 * hs_rx_cdr_sh :: sh_pfc_stat_acc_hi 5300 */ 5301 /* hs_rx_cdr_sh :: sh_pfc_stat_acc_hi :: pfc_rg_sh_xcor_val_hi [15:00] */ 5302 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_HI_PFC_RG_SH_XCOR_VAL_HI_MASK 0xffff 5303 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_HI_PFC_RG_SH_XCOR_VAL_HI_ALIGN 0 5304 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_HI_PFC_RG_SH_XCOR_VAL_HI_BITS 16 5305 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_HI_PFC_RG_SH_XCOR_VAL_HI_SHIFT 0 5306 5307 5308 /**************************************************************************** 5309 * hs_rx_cdr_sh :: sh_pfc_stat_acc_lo 5310 */ 5311 /* hs_rx_cdr_sh :: sh_pfc_stat_acc_lo :: pfc_rg_sh_xcor_val_lo [15:00] */ 5312 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_LO_PFC_RG_SH_XCOR_VAL_LO_MASK 0xffff 5313 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_LO_PFC_RG_SH_XCOR_VAL_LO_ALIGN 0 5314 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_LO_PFC_RG_SH_XCOR_VAL_LO_BITS 16 5315 #define HS_RX_CDR_SH_SH_PFC_STAT_ACC_LO_PFC_RG_SH_XCOR_VAL_LO_SHIFT 0 5316 5317 5318 /**************************************************************************** 5319 * hs_tx_cdr_tpc_regs 5320 */ 5321 /**************************************************************************** 5322 * hs_tx_cdr_tpc :: tpc_ctrl 5323 */ 5324 /* hs_tx_cdr_tpc :: tpc_ctrl :: reserved0 [15:07] */ 5325 #define HS_TX_CDR_TPC_TPC_CTRL_RESERVED0_MASK 0xff80 5326 #define HS_TX_CDR_TPC_TPC_CTRL_RESERVED0_ALIGN 0 5327 #define HS_TX_CDR_TPC_TPC_CTRL_RESERVED0_BITS 9 5328 #define HS_TX_CDR_TPC_TPC_CTRL_RESERVED0_SHIFT 7 5329 5330 /* hs_tx_cdr_tpc :: tpc_ctrl :: rg_tpc_soft_rstb [06:06] */ 5331 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_SOFT_RSTB_MASK 0x0040 5332 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_SOFT_RSTB_ALIGN 0 5333 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_SOFT_RSTB_BITS 1 5334 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_SOFT_RSTB_SHIFT 6 5335 5336 /* hs_tx_cdr_tpc :: tpc_ctrl :: rg_tpc_bw_cntrl_wr_en [05:05] */ 5337 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_BW_CNTRL_WR_EN_MASK 0x0020 5338 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_BW_CNTRL_WR_EN_ALIGN 0 5339 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_BW_CNTRL_WR_EN_BITS 1 5340 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_BW_CNTRL_WR_EN_SHIFT 5 5341 5342 /* hs_tx_cdr_tpc :: tpc_ctrl :: rg_tpc_bw_cntrl [04:02] */ 5343 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_BW_CNTRL_MASK 0x001c 5344 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_BW_CNTRL_ALIGN 0 5345 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_BW_CNTRL_BITS 3 5346 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_BW_CNTRL_SHIFT 2 5347 5348 /* hs_tx_cdr_tpc :: tpc_ctrl :: rg_tpc_iir_soft_rstb [01:01] */ 5349 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_IIR_SOFT_RSTB_MASK 0x0002 5350 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_IIR_SOFT_RSTB_ALIGN 0 5351 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_IIR_SOFT_RSTB_BITS 1 5352 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_IIR_SOFT_RSTB_SHIFT 1 5353 5354 /* hs_tx_cdr_tpc :: tpc_ctrl :: rg_tpc_sd_soft_rstb [00:00] */ 5355 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_SD_SOFT_RSTB_MASK 0x0001 5356 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_SD_SOFT_RSTB_ALIGN 0 5357 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_SD_SOFT_RSTB_BITS 1 5358 #define HS_TX_CDR_TPC_TPC_CTRL_RG_TPC_SD_SOFT_RSTB_SHIFT 0 5359 5360 5361 /**************************************************************************** 5362 * hs_tx_cdr_tpc :: tpc_iir 5363 */ 5364 /* hs_tx_cdr_tpc :: tpc_iir :: rg_tpc_iir_msb_15b_force [15:15] */ 5365 #define HS_TX_CDR_TPC_TPC_IIR_RG_TPC_IIR_MSB_15B_FORCE_MASK 0x8000 5366 #define HS_TX_CDR_TPC_TPC_IIR_RG_TPC_IIR_MSB_15B_FORCE_ALIGN 0 5367 #define HS_TX_CDR_TPC_TPC_IIR_RG_TPC_IIR_MSB_15B_FORCE_BITS 1 5368 #define HS_TX_CDR_TPC_TPC_IIR_RG_TPC_IIR_MSB_15B_FORCE_SHIFT 15 5369 5370 /* hs_tx_cdr_tpc :: tpc_iir :: rg_tpc_iir_msb_15b_force_val [14:00] */ 5371 #define HS_TX_CDR_TPC_TPC_IIR_RG_TPC_IIR_MSB_15B_FORCE_VAL_MASK 0x7fff 5372 #define HS_TX_CDR_TPC_TPC_IIR_RG_TPC_IIR_MSB_15B_FORCE_VAL_ALIGN 0 5373 #define HS_TX_CDR_TPC_TPC_IIR_RG_TPC_IIR_MSB_15B_FORCE_VAL_BITS 15 5374 #define HS_TX_CDR_TPC_TPC_IIR_RG_TPC_IIR_MSB_15B_FORCE_VAL_SHIFT 0 5375 5376 5377 /**************************************************************************** 5378 * hs_tx_cdr_tpc :: tpc_nco 5379 */ 5380 /* hs_tx_cdr_tpc :: tpc_nco :: reserved0 [15:07] */ 5381 #define HS_TX_CDR_TPC_TPC_NCO_RESERVED0_MASK 0xff80 5382 #define HS_TX_CDR_TPC_TPC_NCO_RESERVED0_ALIGN 0 5383 #define HS_TX_CDR_TPC_TPC_NCO_RESERVED0_BITS 9 5384 #define HS_TX_CDR_TPC_TPC_NCO_RESERVED0_SHIFT 7 5385 5386 /* hs_tx_cdr_tpc :: tpc_nco :: rg_tpc_pi_nco_def [06:00] */ 5387 #define HS_TX_CDR_TPC_TPC_NCO_RG_TPC_PI_NCO_DEF_MASK 0x007f 5388 #define HS_TX_CDR_TPC_TPC_NCO_RG_TPC_PI_NCO_DEF_ALIGN 0 5389 #define HS_TX_CDR_TPC_TPC_NCO_RG_TPC_PI_NCO_DEF_BITS 7 5390 #define HS_TX_CDR_TPC_TPC_NCO_RG_TPC_PI_NCO_DEF_SHIFT 0 5391 5392 5393 /**************************************************************************** 5394 * hs_tx_cdr_tpc :: tpc_pi_man_ctrl 5395 */ 5396 /* hs_tx_cdr_tpc :: tpc_pi_man_ctrl :: rg_tpc_man_pha_adj_cnt [15:08] */ 5397 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_CNT_MASK 0xff00 5398 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_CNT_ALIGN 0 5399 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_CNT_BITS 8 5400 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_CNT_SHIFT 8 5401 5402 /* hs_tx_cdr_tpc :: tpc_pi_man_ctrl :: reserved0 [07:05] */ 5403 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RESERVED0_MASK 0x00e0 5404 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RESERVED0_ALIGN 0 5405 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RESERVED0_BITS 3 5406 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RESERVED0_SHIFT 5 5407 5408 /* hs_tx_cdr_tpc :: tpc_pi_man_ctrl :: rg_tpc_pi_pha_adj_val [04:02] */ 5409 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_PI_PHA_ADJ_VAL_MASK 0x001c 5410 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_PI_PHA_ADJ_VAL_ALIGN 0 5411 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_PI_PHA_ADJ_VAL_BITS 3 5412 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_PI_PHA_ADJ_VAL_SHIFT 2 5413 5414 /* hs_tx_cdr_tpc :: tpc_pi_man_ctrl :: rg_tpc_man_pha_adj_mode [01:01] */ 5415 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_MODE_MASK 0x0002 5416 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_MODE_ALIGN 0 5417 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_MODE_BITS 1 5418 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_MODE_SHIFT 1 5419 5420 /* hs_tx_cdr_tpc :: tpc_pi_man_ctrl :: rg_tpc_man_pha_adj_start [00:00] */ 5421 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_START_MASK 0x0001 5422 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_START_ALIGN 0 5423 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_START_BITS 1 5424 #define HS_TX_CDR_TPC_TPC_PI_MAN_CTRL_RG_TPC_MAN_PHA_ADJ_START_SHIFT 0 5425 5426 5427 /**************************************************************************** 5428 * hs_tx_cdr_tpc :: tpc_stat_pi 5429 */ 5430 /* hs_tx_cdr_tpc :: tpc_stat_pi :: reserved0 [15:08] */ 5431 #define HS_TX_CDR_TPC_TPC_STAT_PI_RESERVED0_MASK 0xff00 5432 #define HS_TX_CDR_TPC_TPC_STAT_PI_RESERVED0_ALIGN 0 5433 #define HS_TX_CDR_TPC_TPC_STAT_PI_RESERVED0_BITS 8 5434 #define HS_TX_CDR_TPC_TPC_STAT_PI_RESERVED0_SHIFT 8 5435 5436 /* hs_tx_cdr_tpc :: tpc_stat_pi :: tpc_rg_man_pha_adj_done_lh [07:07] */ 5437 #define HS_TX_CDR_TPC_TPC_STAT_PI_TPC_RG_MAN_PHA_ADJ_DONE_LH_MASK 0x0080 5438 #define HS_TX_CDR_TPC_TPC_STAT_PI_TPC_RG_MAN_PHA_ADJ_DONE_LH_ALIGN 0 5439 #define HS_TX_CDR_TPC_TPC_STAT_PI_TPC_RG_MAN_PHA_ADJ_DONE_LH_BITS 1 5440 #define HS_TX_CDR_TPC_TPC_STAT_PI_TPC_RG_MAN_PHA_ADJ_DONE_LH_SHIFT 7 5441 5442 /* hs_tx_cdr_tpc :: tpc_stat_pi :: tpc_rg_pi_nco [06:00] */ 5443 #define HS_TX_CDR_TPC_TPC_STAT_PI_TPC_RG_PI_NCO_MASK 0x007f 5444 #define HS_TX_CDR_TPC_TPC_STAT_PI_TPC_RG_PI_NCO_ALIGN 0 5445 #define HS_TX_CDR_TPC_TPC_STAT_PI_TPC_RG_PI_NCO_BITS 7 5446 #define HS_TX_CDR_TPC_TPC_STAT_PI_TPC_RG_PI_NCO_SHIFT 0 5447 5448 5449 /**************************************************************************** 5450 * hs_tx_cdr_tpc :: tpc_stat_iir 5451 */ 5452 /* hs_tx_cdr_tpc :: tpc_stat_iir :: reserved0 [15:15] */ 5453 #define HS_TX_CDR_TPC_TPC_STAT_IIR_RESERVED0_MASK 0x8000 5454 #define HS_TX_CDR_TPC_TPC_STAT_IIR_RESERVED0_ALIGN 0 5455 #define HS_TX_CDR_TPC_TPC_STAT_IIR_RESERVED0_BITS 1 5456 #define HS_TX_CDR_TPC_TPC_STAT_IIR_RESERVED0_SHIFT 15 5457 5458 /* hs_tx_cdr_tpc :: tpc_stat_iir :: tpc_rg_iir_msb_15b [14:00] */ 5459 #define HS_TX_CDR_TPC_TPC_STAT_IIR_TPC_RG_IIR_MSB_15B_MASK 0x7fff 5460 #define HS_TX_CDR_TPC_TPC_STAT_IIR_TPC_RG_IIR_MSB_15B_ALIGN 0 5461 #define HS_TX_CDR_TPC_TPC_STAT_IIR_TPC_RG_IIR_MSB_15B_BITS 15 5462 #define HS_TX_CDR_TPC_TPC_STAT_IIR_TPC_RG_IIR_MSB_15B_SHIFT 0 5463 5464 5465 /**************************************************************************** 5466 * ieee_pma_pmd_control_2_regs_regs 5467 */ 5468 /**************************************************************************** 5469 * ieee_pma_pmd_control_2_regs :: pma_pmd_control_2 5470 */ 5471 /* ieee_pma_pmd_control_2_regs :: pma_pmd_control_2 :: reserved0 [15:06] */ 5472 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2_RESERVED0_MASK 0xffc0 5473 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2_RESERVED0_ALIGN 0 5474 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2_RESERVED0_BITS 10 5475 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2_RESERVED0_SHIFT 6 5476 5477 /* ieee_pma_pmd_control_2_regs :: pma_pmd_control_2 :: pma_pmd_type_selection [05:00] */ 5478 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2_PMA_PMD_TYPE_SELECTION_MASK 0x003f 5479 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2_PMA_PMD_TYPE_SELECTION_ALIGN 0 5480 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2_PMA_PMD_TYPE_SELECTION_BITS 6 5481 #define IEEE_PMA_PMD_CONTROL_2_REGS_PMA_PMD_CONTROL_2_PMA_PMD_TYPE_SELECTION_SHIFT 0 5482 5483 5484 /**************************************************************************** 5485 * ieee_pma_pmd_regs_regs 5486 */ 5487 /**************************************************************************** 5488 * ieee_pma_pmd_regs :: pma_pmd_control_1 5489 */ 5490 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: pma_pmd_reg_reset [15:15] */ 5491 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_REG_RESET_MASK 0x8000 5492 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_REG_RESET_ALIGN 0 5493 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_REG_RESET_BITS 1 5494 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_REG_RESET_SHIFT 15 5495 5496 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: reserved0 [14:14] */ 5497 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED0_MASK 0x4000 5498 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED0_ALIGN 0 5499 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED0_BITS 1 5500 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED0_SHIFT 14 5501 5502 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: speed_sel_lsb_unused [13:13] */ 5503 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_SPEED_SEL_LSB_UNUSED_MASK 0x2000 5504 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_SPEED_SEL_LSB_UNUSED_ALIGN 0 5505 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_SPEED_SEL_LSB_UNUSED_BITS 1 5506 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_SPEED_SEL_LSB_UNUSED_SHIFT 13 5507 5508 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: reserved1 [12:12] */ 5509 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED1_MASK 0x1000 5510 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED1_ALIGN 0 5511 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED1_BITS 1 5512 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED1_SHIFT 12 5513 5514 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: pma_pmd_low_power_mode [11:11] */ 5515 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_LOW_POWER_MODE_MASK 0x0800 5516 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_LOW_POWER_MODE_ALIGN 0 5517 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_LOW_POWER_MODE_BITS 1 5518 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_LOW_POWER_MODE_SHIFT 11 5519 5520 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: reserved2 [10:07] */ 5521 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED2_MASK 0x0780 5522 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED2_ALIGN 0 5523 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED2_BITS 4 5524 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_RESERVED2_SHIFT 7 5525 5526 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: speed_sel_msb_unused [06:06] */ 5527 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_SPEED_SEL_MSB_UNUSED_MASK 0x0040 5528 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_SPEED_SEL_MSB_UNUSED_ALIGN 0 5529 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_SPEED_SEL_MSB_UNUSED_BITS 1 5530 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_SPEED_SEL_MSB_UNUSED_SHIFT 6 5531 5532 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: pma_pmd_speed_selection [05:02] */ 5533 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_SPEED_SELECTION_MASK 0x003c 5534 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_SPEED_SELECTION_ALIGN 0 5535 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_SPEED_SELECTION_BITS 4 5536 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_PMD_SPEED_SELECTION_SHIFT 2 5537 5538 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: pma_remote_loopback [01:01] */ 5539 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_REMOTE_LOOPBACK_MASK 0x0002 5540 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_REMOTE_LOOPBACK_ALIGN 0 5541 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_REMOTE_LOOPBACK_BITS 1 5542 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_REMOTE_LOOPBACK_SHIFT 1 5543 5544 /* ieee_pma_pmd_regs :: pma_pmd_control_1 :: pma_local_loopback [00:00] */ 5545 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_LOCAL_LOOPBACK_MASK 0x0001 5546 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_LOCAL_LOOPBACK_ALIGN 0 5547 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_LOCAL_LOOPBACK_BITS 1 5548 #define IEEE_PMA_PMD_REGS_PMA_PMD_CONTROL_1_PMA_LOCAL_LOOPBACK_SHIFT 0 5549 5550 5551 /**************************************************************************** 5552 * ieee_pma_pmd_regs :: pma_pmd_status_1 5553 */ 5554 /* ieee_pma_pmd_regs :: pma_pmd_status_1 :: reserved0 [15:08] */ 5555 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED0_MASK 0xff00 5556 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED0_ALIGN 0 5557 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED0_BITS 8 5558 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED0_SHIFT 8 5559 5560 /* ieee_pma_pmd_regs :: pma_pmd_status_1 :: pma_pmd_fault [07:07] */ 5561 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_FAULT_MASK 0x0080 5562 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_FAULT_ALIGN 0 5563 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_FAULT_BITS 1 5564 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_FAULT_SHIFT 7 5565 5566 /* ieee_pma_pmd_regs :: pma_pmd_status_1 :: reserved1 [06:03] */ 5567 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED1_MASK 0x0078 5568 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED1_ALIGN 0 5569 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED1_BITS 4 5570 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED1_SHIFT 3 5571 5572 /* ieee_pma_pmd_regs :: pma_pmd_status_1 :: pma_pmd_rx_link_status [02:02] */ 5573 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_RX_LINK_STATUS_MASK 0x0004 5574 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_RX_LINK_STATUS_ALIGN 0 5575 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_RX_LINK_STATUS_BITS 1 5576 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_RX_LINK_STATUS_SHIFT 2 5577 5578 /* ieee_pma_pmd_regs :: pma_pmd_status_1 :: pma_pmd_low_power_ability [01:01] */ 5579 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_LOW_POWER_ABILITY_MASK 0x0002 5580 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_LOW_POWER_ABILITY_ALIGN 0 5581 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_LOW_POWER_ABILITY_BITS 1 5582 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_PMA_PMD_LOW_POWER_ABILITY_SHIFT 1 5583 5584 /* ieee_pma_pmd_regs :: pma_pmd_status_1 :: reserved2 [00:00] */ 5585 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED2_MASK 0x0001 5586 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED2_ALIGN 0 5587 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED2_BITS 1 5588 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_1_RESERVED2_SHIFT 0 5589 5590 5591 /**************************************************************************** 5592 * ieee_pma_pmd_regs :: pma_pmd_device_identifier_msb 5593 */ 5594 /* ieee_pma_pmd_regs :: pma_pmd_device_identifier_msb :: pma_pmd_device_identifier_msb_f [15:00] */ 5595 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_MSB_PMA_PMD_DEVICE_IDENTIFIER_MSB_F_MASK 0xffff 5596 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_MSB_PMA_PMD_DEVICE_IDENTIFIER_MSB_F_ALIGN 0 5597 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_MSB_PMA_PMD_DEVICE_IDENTIFIER_MSB_F_BITS 16 5598 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_MSB_PMA_PMD_DEVICE_IDENTIFIER_MSB_F_SHIFT 0 5599 5600 5601 /**************************************************************************** 5602 * ieee_pma_pmd_regs :: pma_pmd_device_identifier_lsb 5603 */ 5604 /* ieee_pma_pmd_regs :: pma_pmd_device_identifier_lsb :: pma_pmd_device_identifier_lsb_f [15:00] */ 5605 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_LSB_PMA_PMD_DEVICE_IDENTIFIER_LSB_F_MASK 0xffff 5606 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_LSB_PMA_PMD_DEVICE_IDENTIFIER_LSB_F_ALIGN 0 5607 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_LSB_PMA_PMD_DEVICE_IDENTIFIER_LSB_F_BITS 16 5608 #define IEEE_PMA_PMD_REGS_PMA_PMD_DEVICE_IDENTIFIER_LSB_PMA_PMD_DEVICE_IDENTIFIER_LSB_F_SHIFT 0 5609 5610 5611 /**************************************************************************** 5612 * ieee_pma_pmd_regs :: pma_pmd_speed_ability 5613 */ 5614 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: reserved0 [15:10] */ 5615 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED0_MASK 0xfc00 5616 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED0_ALIGN 0 5617 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED0_BITS 6 5618 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED0_SHIFT 10 5619 5620 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: pma_pmd_100g_capable [09:09] */ 5621 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_100G_CAPABLE_MASK 0x0200 5622 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_100G_CAPABLE_ALIGN 0 5623 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_100G_CAPABLE_BITS 1 5624 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_100G_CAPABLE_SHIFT 9 5625 5626 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: pma_pmd_40g_capable [08:08] */ 5627 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_40G_CAPABLE_MASK 0x0100 5628 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_40G_CAPABLE_ALIGN 0 5629 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_40G_CAPABLE_BITS 1 5630 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_40G_CAPABLE_SHIFT 8 5631 5632 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: reserved1 [07:07] */ 5633 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED1_MASK 0x0080 5634 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED1_ALIGN 0 5635 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED1_BITS 1 5636 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED1_SHIFT 7 5637 5638 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: pma_pmd_10m_capable [06:06] */ 5639 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10M_CAPABLE_MASK 0x0040 5640 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10M_CAPABLE_ALIGN 0 5641 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10M_CAPABLE_BITS 1 5642 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10M_CAPABLE_SHIFT 6 5643 5644 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: pma_pmd_100m_capable [05:05] */ 5645 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_100M_CAPABLE_MASK 0x0020 5646 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_100M_CAPABLE_ALIGN 0 5647 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_100M_CAPABLE_BITS 1 5648 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_100M_CAPABLE_SHIFT 5 5649 5650 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: pma_pmd_1000m_capable [04:04] */ 5651 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_1000M_CAPABLE_MASK 0x0010 5652 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_1000M_CAPABLE_ALIGN 0 5653 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_1000M_CAPABLE_BITS 1 5654 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_1000M_CAPABLE_SHIFT 4 5655 5656 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: reserved2 [03:03] */ 5657 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED2_MASK 0x0008 5658 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED2_ALIGN 0 5659 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED2_BITS 1 5660 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_RESERVED2_SHIFT 3 5661 5662 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: pma_pmd_10pass_ts_capable [02:02] */ 5663 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10PASS_TS_CAPABLE_MASK 0x0004 5664 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10PASS_TS_CAPABLE_ALIGN 0 5665 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10PASS_TS_CAPABLE_BITS 1 5666 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10PASS_TS_CAPABLE_SHIFT 2 5667 5668 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: pma_pmd_2base_tl_capable [01:01] */ 5669 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_2BASE_TL_CAPABLE_MASK 0x0002 5670 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_2BASE_TL_CAPABLE_ALIGN 0 5671 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_2BASE_TL_CAPABLE_BITS 1 5672 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_2BASE_TL_CAPABLE_SHIFT 1 5673 5674 /* ieee_pma_pmd_regs :: pma_pmd_speed_ability :: pma_pmd_10g_capable [00:00] */ 5675 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10G_CAPABLE_MASK 0x0001 5676 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10G_CAPABLE_ALIGN 0 5677 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10G_CAPABLE_BITS 1 5678 #define IEEE_PMA_PMD_REGS_PMA_PMD_SPEED_ABILITY_PMA_PMD_10G_CAPABLE_SHIFT 0 5679 5680 5681 /**************************************************************************** 5682 * ieee_pma_pmd_regs :: devices_in_package_lsb 5683 */ 5684 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: reserved0 [15:12] */ 5685 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_RESERVED0_MASK 0xf000 5686 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_RESERVED0_ALIGN 0 5687 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_RESERVED0_BITS 4 5688 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_RESERVED0_SHIFT 12 5689 5690 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: separated_pma_4_present [11:11] */ 5691 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_4_PRESENT_MASK 0x0800 5692 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_4_PRESENT_ALIGN 0 5693 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_4_PRESENT_BITS 1 5694 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_4_PRESENT_SHIFT 11 5695 5696 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: separated_pma_3_present [10:10] */ 5697 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_3_PRESENT_MASK 0x0400 5698 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_3_PRESENT_ALIGN 0 5699 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_3_PRESENT_BITS 1 5700 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_3_PRESENT_SHIFT 10 5701 5702 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: separated_pma_2_present [09:09] */ 5703 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_2_PRESENT_MASK 0x0200 5704 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_2_PRESENT_ALIGN 0 5705 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_2_PRESENT_BITS 1 5706 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_2_PRESENT_SHIFT 9 5707 5708 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: separated_pma_1_present [08:08] */ 5709 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_1_PRESENT_MASK 0x0100 5710 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_1_PRESENT_ALIGN 0 5711 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_1_PRESENT_BITS 1 5712 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_SEPARATED_PMA_1_PRESENT_SHIFT 8 5713 5714 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: auto_negotiation_present [07:07] */ 5715 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_AUTO_NEGOTIATION_PRESENT_MASK 0x0080 5716 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_AUTO_NEGOTIATION_PRESENT_ALIGN 0 5717 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_AUTO_NEGOTIATION_PRESENT_BITS 1 5718 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_AUTO_NEGOTIATION_PRESENT_SHIFT 7 5719 5720 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: tc_present [06:06] */ 5721 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_TC_PRESENT_MASK 0x0040 5722 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_TC_PRESENT_ALIGN 0 5723 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_TC_PRESENT_BITS 1 5724 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_TC_PRESENT_SHIFT 6 5725 5726 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: dte_xs_present [05:05] */ 5727 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_DTE_XS_PRESENT_MASK 0x0020 5728 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_DTE_XS_PRESENT_ALIGN 0 5729 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_DTE_XS_PRESENT_BITS 1 5730 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_DTE_XS_PRESENT_SHIFT 5 5731 5732 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: phy_xs_present [04:04] */ 5733 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PHY_XS_PRESENT_MASK 0x0010 5734 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PHY_XS_PRESENT_ALIGN 0 5735 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PHY_XS_PRESENT_BITS 1 5736 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PHY_XS_PRESENT_SHIFT 4 5737 5738 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: pcs_present [03:03] */ 5739 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PCS_PRESENT_MASK 0x0008 5740 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PCS_PRESENT_ALIGN 0 5741 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PCS_PRESENT_BITS 1 5742 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PCS_PRESENT_SHIFT 3 5743 5744 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: wis_present [02:02] */ 5745 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_WIS_PRESENT_MASK 0x0004 5746 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_WIS_PRESENT_ALIGN 0 5747 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_WIS_PRESENT_BITS 1 5748 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_WIS_PRESENT_SHIFT 2 5749 5750 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: pma_pmd_present [01:01] */ 5751 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PMA_PMD_PRESENT_MASK 0x0002 5752 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PMA_PMD_PRESENT_ALIGN 0 5753 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PMA_PMD_PRESENT_BITS 1 5754 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_PMA_PMD_PRESENT_SHIFT 1 5755 5756 /* ieee_pma_pmd_regs :: devices_in_package_lsb :: clause_22_present [00:00] */ 5757 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_CLAUSE_22_PRESENT_MASK 0x0001 5758 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_CLAUSE_22_PRESENT_ALIGN 0 5759 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_CLAUSE_22_PRESENT_BITS 1 5760 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_LSB_CLAUSE_22_PRESENT_SHIFT 0 5761 5762 5763 /**************************************************************************** 5764 * ieee_pma_pmd_regs :: devices_in_package_msb 5765 */ 5766 /* ieee_pma_pmd_regs :: devices_in_package_msb :: vendor_specific_device_2_present [15:15] */ 5767 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_VENDOR_SPECIFIC_DEVICE_2_PRESENT_MASK 0x8000 5768 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_VENDOR_SPECIFIC_DEVICE_2_PRESENT_ALIGN 0 5769 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_VENDOR_SPECIFIC_DEVICE_2_PRESENT_BITS 1 5770 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_VENDOR_SPECIFIC_DEVICE_2_PRESENT_SHIFT 15 5771 5772 /* ieee_pma_pmd_regs :: devices_in_package_msb :: vendor_specific_device_1_present [14:14] */ 5773 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_VENDOR_SPECIFIC_DEVICE_1_PRESENT_MASK 0x4000 5774 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_VENDOR_SPECIFIC_DEVICE_1_PRESENT_ALIGN 0 5775 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_VENDOR_SPECIFIC_DEVICE_1_PRESENT_BITS 1 5776 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_VENDOR_SPECIFIC_DEVICE_1_PRESENT_SHIFT 14 5777 5778 /* ieee_pma_pmd_regs :: devices_in_package_msb :: clause_22_extension_present [13:13] */ 5779 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_CLAUSE_22_EXTENSION_PRESENT_MASK 0x2000 5780 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_CLAUSE_22_EXTENSION_PRESENT_ALIGN 0 5781 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_CLAUSE_22_EXTENSION_PRESENT_BITS 1 5782 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_CLAUSE_22_EXTENSION_PRESENT_SHIFT 13 5783 5784 /* ieee_pma_pmd_regs :: devices_in_package_msb :: reserved0 [12:00] */ 5785 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_RESERVED0_MASK 0x1fff 5786 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_RESERVED0_ALIGN 0 5787 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_RESERVED0_BITS 13 5788 #define IEEE_PMA_PMD_REGS_DEVICES_IN_PACKAGE_MSB_RESERVED0_SHIFT 0 5789 5790 5791 /**************************************************************************** 5792 * ieee_pma_pmd_regs :: pma_pmd_status_2 5793 */ 5794 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pma_pmd_device_present [15:14] */ 5795 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_DEVICE_PRESENT_MASK 0xc000 5796 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_DEVICE_PRESENT_ALIGN 0 5797 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_DEVICE_PRESENT_BITS 2 5798 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_DEVICE_PRESENT_SHIFT 14 5799 5800 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pma_pmd_transmit_fault_ability [13:13] */ 5801 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_TRANSMIT_FAULT_ABILITY_MASK 0x2000 5802 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_TRANSMIT_FAULT_ABILITY_ALIGN 0 5803 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_TRANSMIT_FAULT_ABILITY_BITS 1 5804 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_TRANSMIT_FAULT_ABILITY_SHIFT 13 5805 5806 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pma_pmd_receive_fault_ability [12:12] */ 5807 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_RECEIVE_FAULT_ABILITY_MASK 0x1000 5808 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_RECEIVE_FAULT_ABILITY_ALIGN 0 5809 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_RECEIVE_FAULT_ABILITY_BITS 1 5810 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_RECEIVE_FAULT_ABILITY_SHIFT 12 5811 5812 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pma_pmd_transmit_fault [11:11] */ 5813 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_TRANSMIT_FAULT_MASK 0x0800 5814 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_TRANSMIT_FAULT_ALIGN 0 5815 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_TRANSMIT_FAULT_BITS 1 5816 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_TRANSMIT_FAULT_SHIFT 11 5817 5818 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pma_pmd_receive_fault [10:10] */ 5819 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_RECEIVE_FAULT_MASK 0x0400 5820 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_RECEIVE_FAULT_ALIGN 0 5821 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_RECEIVE_FAULT_BITS 1 5822 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_RECEIVE_FAULT_SHIFT 10 5823 5824 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pma_pmd_extended_abilites [09:09] */ 5825 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_EXTENDED_ABILITES_MASK 0x0200 5826 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_EXTENDED_ABILITES_ALIGN 0 5827 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_EXTENDED_ABILITES_BITS 1 5828 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_PMD_EXTENDED_ABILITES_SHIFT 9 5829 5830 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pmd_transmit_disable_ability [08:08] */ 5831 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_TRANSMIT_DISABLE_ABILITY_MASK 0x0100 5832 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_TRANSMIT_DISABLE_ABILITY_ALIGN 0 5833 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_TRANSMIT_DISABLE_ABILITY_BITS 1 5834 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_TRANSMIT_DISABLE_ABILITY_SHIFT 8 5835 5836 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pmd_10gbase_sr_ability [07:07] */ 5837 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_SR_ABILITY_MASK 0x0080 5838 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_SR_ABILITY_ALIGN 0 5839 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_SR_ABILITY_BITS 1 5840 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_SR_ABILITY_SHIFT 7 5841 5842 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pmd_10gbase_lr_abiity [06:06] */ 5843 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LR_ABIITY_MASK 0x0040 5844 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LR_ABIITY_ALIGN 0 5845 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LR_ABIITY_BITS 1 5846 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LR_ABIITY_SHIFT 6 5847 5848 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pmd_10gbase_er_abiity [05:05] */ 5849 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_ER_ABIITY_MASK 0x0020 5850 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_ER_ABIITY_ALIGN 0 5851 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_ER_ABIITY_BITS 1 5852 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_ER_ABIITY_SHIFT 5 5853 5854 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pmd_10gbase_lx4_abiity [04:04] */ 5855 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LX4_ABIITY_MASK 0x0010 5856 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LX4_ABIITY_ALIGN 0 5857 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LX4_ABIITY_BITS 1 5858 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LX4_ABIITY_SHIFT 4 5859 5860 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pmd_10gbase_sw_abiity [03:03] */ 5861 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_SW_ABIITY_MASK 0x0008 5862 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_SW_ABIITY_ALIGN 0 5863 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_SW_ABIITY_BITS 1 5864 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_SW_ABIITY_SHIFT 3 5865 5866 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pmd_10gbase_lw_abiity [02:02] */ 5867 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LW_ABIITY_MASK 0x0004 5868 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LW_ABIITY_ALIGN 0 5869 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LW_ABIITY_BITS 1 5870 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_LW_ABIITY_SHIFT 2 5871 5872 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pmd_10gbase_ew_abiity [01:01] */ 5873 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_EW_ABIITY_MASK 0x0002 5874 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_EW_ABIITY_ALIGN 0 5875 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_EW_ABIITY_BITS 1 5876 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMD_10GBASE_EW_ABIITY_SHIFT 1 5877 5878 /* ieee_pma_pmd_regs :: pma_pmd_status_2 :: pma_local_loopback_ability [00:00] */ 5879 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_LOCAL_LOOPBACK_ABILITY_MASK 0x0001 5880 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_LOCAL_LOOPBACK_ABILITY_ALIGN 0 5881 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_LOCAL_LOOPBACK_ABILITY_BITS 1 5882 #define IEEE_PMA_PMD_REGS_PMA_PMD_STATUS_2_PMA_LOCAL_LOOPBACK_ABILITY_SHIFT 0 5883 5884 5885 /**************************************************************************** 5886 * ieee_pma_pmd_regs :: pmd_transmit_disable 5887 */ 5888 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: reserved0 [15:11] */ 5889 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_RESERVED0_MASK 0xf800 5890 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_RESERVED0_ALIGN 0 5891 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_RESERVED0_BITS 5 5892 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_RESERVED0_SHIFT 11 5893 5894 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_9 [10:10] */ 5895 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_9_MASK 0x0400 5896 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_9_ALIGN 0 5897 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_9_BITS 1 5898 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_9_SHIFT 10 5899 5900 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_8 [09:09] */ 5901 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_8_MASK 0x0200 5902 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_8_ALIGN 0 5903 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_8_BITS 1 5904 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_8_SHIFT 9 5905 5906 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_7 [08:08] */ 5907 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_7_MASK 0x0100 5908 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_7_ALIGN 0 5909 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_7_BITS 1 5910 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_7_SHIFT 8 5911 5912 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_6 [07:07] */ 5913 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_6_MASK 0x0080 5914 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_6_ALIGN 0 5915 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_6_BITS 1 5916 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_6_SHIFT 7 5917 5918 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_5 [06:06] */ 5919 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_5_MASK 0x0040 5920 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_5_ALIGN 0 5921 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_5_BITS 1 5922 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_5_SHIFT 6 5923 5924 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_4 [05:05] */ 5925 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_4_MASK 0x0020 5926 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_4_ALIGN 0 5927 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_4_BITS 1 5928 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_4_SHIFT 5 5929 5930 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_3 [04:04] */ 5931 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_3_MASK 0x0010 5932 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_3_ALIGN 0 5933 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_3_BITS 1 5934 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_3_SHIFT 4 5935 5936 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_2 [03:03] */ 5937 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_2_MASK 0x0008 5938 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_2_ALIGN 0 5939 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_2_BITS 1 5940 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_2_SHIFT 3 5941 5942 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_1 [02:02] */ 5943 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_1_MASK 0x0004 5944 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_1_ALIGN 0 5945 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_1_BITS 1 5946 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_1_SHIFT 2 5947 5948 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_transmit_disable_0 [01:01] */ 5949 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_0_MASK 0x0002 5950 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_0_ALIGN 0 5951 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_0_BITS 1 5952 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_TRANSMIT_DISABLE_0_SHIFT 1 5953 5954 /* ieee_pma_pmd_regs :: pmd_transmit_disable :: pmd_global_transmit_disable [00:00] */ 5955 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_GLOBAL_TRANSMIT_DISABLE_MASK 0x0001 5956 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_GLOBAL_TRANSMIT_DISABLE_ALIGN 0 5957 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_GLOBAL_TRANSMIT_DISABLE_BITS 1 5958 #define IEEE_PMA_PMD_REGS_PMD_TRANSMIT_DISABLE_PMD_GLOBAL_TRANSMIT_DISABLE_SHIFT 0 5959 5960 5961 /**************************************************************************** 5962 * ieee_pma_pmd_regs :: pmd_receive_signal_detect 5963 */ 5964 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: reserved0 [15:11] */ 5965 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_RESERVED0_MASK 0xf800 5966 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_RESERVED0_ALIGN 0 5967 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_RESERVED0_BITS 5 5968 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_RESERVED0_SHIFT 11 5969 5970 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_9 [10:10] */ 5971 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_9_MASK 0x0400 5972 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_9_ALIGN 0 5973 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_9_BITS 1 5974 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_9_SHIFT 10 5975 5976 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_8 [09:09] */ 5977 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_8_MASK 0x0200 5978 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_8_ALIGN 0 5979 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_8_BITS 1 5980 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_8_SHIFT 9 5981 5982 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_7 [08:08] */ 5983 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_7_MASK 0x0100 5984 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_7_ALIGN 0 5985 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_7_BITS 1 5986 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_7_SHIFT 8 5987 5988 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_6 [07:07] */ 5989 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_6_MASK 0x0080 5990 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_6_ALIGN 0 5991 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_6_BITS 1 5992 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_6_SHIFT 7 5993 5994 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_5 [06:06] */ 5995 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_5_MASK 0x0040 5996 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_5_ALIGN 0 5997 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_5_BITS 1 5998 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_5_SHIFT 6 5999 6000 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_4 [05:05] */ 6001 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_4_MASK 0x0020 6002 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_4_ALIGN 0 6003 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_4_BITS 1 6004 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_4_SHIFT 5 6005 6006 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_3 [04:04] */ 6007 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_3_MASK 0x0010 6008 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_3_ALIGN 0 6009 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_3_BITS 1 6010 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_3_SHIFT 4 6011 6012 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_2 [03:03] */ 6013 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_2_MASK 0x0008 6014 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_2_ALIGN 0 6015 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_2_BITS 1 6016 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_2_SHIFT 3 6017 6018 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_1 [02:02] */ 6019 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_1_MASK 0x0004 6020 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_1_ALIGN 0 6021 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_1_BITS 1 6022 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_1_SHIFT 2 6023 6024 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_receive_signal_detect_0 [01:01] */ 6025 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_0_MASK 0x0002 6026 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_0_ALIGN 0 6027 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_0_BITS 1 6028 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_RECEIVE_SIGNAL_DETECT_0_SHIFT 1 6029 6030 /* ieee_pma_pmd_regs :: pmd_receive_signal_detect :: pmd_global_receive_signal_detect [00:00] */ 6031 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_GLOBAL_RECEIVE_SIGNAL_DETECT_MASK 0x0001 6032 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_GLOBAL_RECEIVE_SIGNAL_DETECT_ALIGN 0 6033 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_GLOBAL_RECEIVE_SIGNAL_DETECT_BITS 1 6034 #define IEEE_PMA_PMD_REGS_PMD_RECEIVE_SIGNAL_DETECT_PMD_GLOBAL_RECEIVE_SIGNAL_DETECT_SHIFT 0 6035 6036 6037 /**************************************************************************** 6038 * ieee_pma_pmd_regs :: pma_pmd_extended_ability 6039 */ 6040 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: reserved0 [15:11] */ 6041 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_RESERVED0_MASK 0xf800 6042 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_RESERVED0_ALIGN 0 6043 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_RESERVED0_BITS 5 6044 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_RESERVED0_SHIFT 11 6045 6046 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_40g_100g_extended_abilities [10:10] */ 6047 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_40G_100G_EXTENDED_ABILITIES_MASK 0x0400 6048 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_40G_100G_EXTENDED_ABILITIES_ALIGN 0 6049 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_40G_100G_EXTENDED_ABILITIES_BITS 1 6050 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_40G_100G_EXTENDED_ABILITIES_SHIFT 10 6051 6052 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: reserved1 [09:09] */ 6053 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_RESERVED1_MASK 0x0200 6054 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_RESERVED1_ALIGN 0 6055 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_RESERVED1_BITS 1 6056 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_RESERVED1_SHIFT 9 6057 6058 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_10base_t_ability [08:08] */ 6059 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10BASE_T_ABILITY_MASK 0x0100 6060 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10BASE_T_ABILITY_ALIGN 0 6061 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10BASE_T_ABILITY_BITS 1 6062 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10BASE_T_ABILITY_SHIFT 8 6063 6064 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_100base_tx_ability [07:07] */ 6065 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_100BASE_TX_ABILITY_MASK 0x0080 6066 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_100BASE_TX_ABILITY_ALIGN 0 6067 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_100BASE_TX_ABILITY_BITS 1 6068 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_100BASE_TX_ABILITY_SHIFT 7 6069 6070 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_1000base_kx_ability [06:06] */ 6071 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_1000BASE_KX_ABILITY_MASK 0x0040 6072 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_1000BASE_KX_ABILITY_ALIGN 0 6073 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_1000BASE_KX_ABILITY_BITS 1 6074 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_1000BASE_KX_ABILITY_SHIFT 6 6075 6076 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_1000base_t_ability [05:05] */ 6077 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_1000BASE_T_ABILITY_MASK 0x0020 6078 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_1000BASE_T_ABILITY_ALIGN 0 6079 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_1000BASE_T_ABILITY_BITS 1 6080 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_1000BASE_T_ABILITY_SHIFT 5 6081 6082 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_10gbase_kr_ability [04:04] */ 6083 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_KR_ABILITY_MASK 0x0010 6084 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_KR_ABILITY_ALIGN 0 6085 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_KR_ABILITY_BITS 1 6086 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_KR_ABILITY_SHIFT 4 6087 6088 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_10gbase_kx4_ability [03:03] */ 6089 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_KX4_ABILITY_MASK 0x0008 6090 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_KX4_ABILITY_ALIGN 0 6091 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_KX4_ABILITY_BITS 1 6092 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_KX4_ABILITY_SHIFT 3 6093 6094 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_10gbase_t_ability [02:02] */ 6095 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_T_ABILITY_MASK 0x0004 6096 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_T_ABILITY_ALIGN 0 6097 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_T_ABILITY_BITS 1 6098 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_T_ABILITY_SHIFT 2 6099 6100 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_10gbase_lrm_ability [01:01] */ 6101 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_LRM_ABILITY_MASK 0x0002 6102 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_LRM_ABILITY_ALIGN 0 6103 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_LRM_ABILITY_BITS 1 6104 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_LRM_ABILITY_SHIFT 1 6105 6106 /* ieee_pma_pmd_regs :: pma_pmd_extended_ability :: pma_pmd_10gbase_cx4_ability [00:00] */ 6107 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_CX4_ABILITY_MASK 0x0001 6108 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_CX4_ABILITY_ALIGN 0 6109 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_CX4_ABILITY_BITS 1 6110 #define IEEE_PMA_PMD_REGS_PMA_PMD_EXTENDED_ABILITY_PMA_PMD_10GBASE_CX4_ABILITY_SHIFT 0 6111 6112 6113 /**************************************************************************** 6114 * ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability 6115 */ 6116 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_remote_loopback_ability [15:15] */ 6117 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_REMOTE_LOOPBACK_ABILITY_MASK 0x8000 6118 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_REMOTE_LOOPBACK_ABILITY_ALIGN 0 6119 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_REMOTE_LOOPBACK_ABILITY_BITS 1 6120 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_REMOTE_LOOPBACK_ABILITY_SHIFT 15 6121 6122 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: reserved0 [14:12] */ 6123 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_RESERVED0_MASK 0x7000 6124 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_RESERVED0_ALIGN 0 6125 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_RESERVED0_BITS 3 6126 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_RESERVED0_SHIFT 12 6127 6128 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_100gbase_er4_ability [11:11] */ 6129 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_ER4_ABILITY_MASK 0x0800 6130 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_ER4_ABILITY_ALIGN 0 6131 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_ER4_ABILITY_BITS 1 6132 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_ER4_ABILITY_SHIFT 11 6133 6134 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_100gbase_lr4_ability [10:10] */ 6135 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_LR4_ABILITY_MASK 0x0400 6136 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_LR4_ABILITY_ALIGN 0 6137 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_LR4_ABILITY_BITS 1 6138 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_LR4_ABILITY_SHIFT 10 6139 6140 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_100gbase_sr10_ability [09:09] */ 6141 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_SR10_ABILITY_MASK 0x0200 6142 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_SR10_ABILITY_ALIGN 0 6143 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_SR10_ABILITY_BITS 1 6144 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_SR10_ABILITY_SHIFT 9 6145 6146 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_100gbase_cr10_ability [08:08] */ 6147 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_CR10_ABILITY_MASK 0x0100 6148 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_CR10_ABILITY_ALIGN 0 6149 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_CR10_ABILITY_BITS 1 6150 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_100GBASE_CR10_ABILITY_SHIFT 8 6151 6152 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: reserved1 [07:04] */ 6153 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_RESERVED1_MASK 0x00f0 6154 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_RESERVED1_ALIGN 0 6155 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_RESERVED1_BITS 4 6156 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_RESERVED1_SHIFT 4 6157 6158 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_40gbase_lr4_ability [03:03] */ 6159 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_LR4_ABILITY_MASK 0x0008 6160 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_LR4_ABILITY_ALIGN 0 6161 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_LR4_ABILITY_BITS 1 6162 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_LR4_ABILITY_SHIFT 3 6163 6164 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_40gbase_sr4_ability [02:02] */ 6165 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_SR4_ABILITY_MASK 0x0004 6166 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_SR4_ABILITY_ALIGN 0 6167 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_SR4_ABILITY_BITS 1 6168 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_SR4_ABILITY_SHIFT 2 6169 6170 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_40gbase_cr4_ability [01:01] */ 6171 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_CR4_ABILITY_MASK 0x0002 6172 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_CR4_ABILITY_ALIGN 0 6173 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_CR4_ABILITY_BITS 1 6174 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_CR4_ABILITY_SHIFT 1 6175 6176 /* ieee_pma_pmd_regs :: pma_pmd_40g_100g_extended_ability :: pma_pmd_40gbase_kr4_ability [00:00] */ 6177 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_KR4_ABILITY_MASK 0x0001 6178 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_KR4_ABILITY_ALIGN 0 6179 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_KR4_ABILITY_BITS 1 6180 #define IEEE_PMA_PMD_REGS_PMA_PMD_40G_100G_EXTENDED_ABILITY_PMA_PMD_40GBASE_KR4_ABILITY_SHIFT 0 6181 6182 6183 /**************************************************************************** 6184 * ieee_pma_pmd_regs :: pma_pmd_package_identifier_msb 6185 */ 6186 /* ieee_pma_pmd_regs :: pma_pmd_package_identifier_msb :: pma_pmd_package_identifier_msb_f [15:00] */ 6187 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_MSB_PMA_PMD_PACKAGE_IDENTIFIER_MSB_F_MASK 0xffff 6188 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_MSB_PMA_PMD_PACKAGE_IDENTIFIER_MSB_F_ALIGN 0 6189 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_MSB_PMA_PMD_PACKAGE_IDENTIFIER_MSB_F_BITS 16 6190 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_MSB_PMA_PMD_PACKAGE_IDENTIFIER_MSB_F_SHIFT 0 6191 6192 6193 /**************************************************************************** 6194 * ieee_pma_pmd_regs :: pma_pmd_package_identifier_lsb 6195 */ 6196 /* ieee_pma_pmd_regs :: pma_pmd_package_identifier_lsb :: pma_pmd_package_identifier_lsb_f [15:00] */ 6197 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_LSB_PMA_PMD_PACKAGE_IDENTIFIER_LSB_F_MASK 0xffff 6198 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_LSB_PMA_PMD_PACKAGE_IDENTIFIER_LSB_F_ALIGN 0 6199 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_LSB_PMA_PMD_PACKAGE_IDENTIFIER_LSB_F_BITS 16 6200 #define IEEE_PMA_PMD_REGS_PMA_PMD_PACKAGE_IDENTIFIER_LSB_PMA_PMD_PACKAGE_IDENTIFIER_LSB_F_SHIFT 0 6201 6202 6203 /**************************************************************************** 6204 * ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability 6205 */ 6206 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: reserved0 [15:13] */ 6207 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_RESERVED0_MASK 0xe000 6208 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_RESERVED0_ALIGN 0 6209 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_RESERVED0_BITS 3 6210 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_RESERVED0_SHIFT 13 6211 6212 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: pma_square_wave_test_ability [12:12] */ 6213 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_SQUARE_WAVE_TEST_ABILITY_MASK 0x1000 6214 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_SQUARE_WAVE_TEST_ABILITY_ALIGN 0 6215 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_SQUARE_WAVE_TEST_ABILITY_BITS 1 6216 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_SQUARE_WAVE_TEST_ABILITY_SHIFT 12 6217 6218 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: reserved1 [11:06] */ 6219 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_RESERVED1_MASK 0x0fc0 6220 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_RESERVED1_ALIGN 0 6221 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_RESERVED1_BITS 6 6222 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_RESERVED1_SHIFT 6 6223 6224 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: pma_prbs9_tx_generator_ability [05:05] */ 6225 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS9_TX_GENERATOR_ABILITY_MASK 0x0020 6226 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS9_TX_GENERATOR_ABILITY_ALIGN 0 6227 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS9_TX_GENERATOR_ABILITY_BITS 1 6228 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS9_TX_GENERATOR_ABILITY_SHIFT 5 6229 6230 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: pma_prbs9_rx_generator_ability [04:04] */ 6231 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS9_RX_GENERATOR_ABILITY_MASK 0x0010 6232 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS9_RX_GENERATOR_ABILITY_ALIGN 0 6233 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS9_RX_GENERATOR_ABILITY_BITS 1 6234 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS9_RX_GENERATOR_ABILITY_SHIFT 4 6235 6236 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: pma_prbs31_tx_generator_ability [03:03] */ 6237 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_TX_GENERATOR_ABILITY_MASK 0x0008 6238 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_TX_GENERATOR_ABILITY_ALIGN 0 6239 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_TX_GENERATOR_ABILITY_BITS 1 6240 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_TX_GENERATOR_ABILITY_SHIFT 3 6241 6242 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: pma_prbs31_tx_checker_ability [02:02] */ 6243 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_TX_CHECKER_ABILITY_MASK 0x0004 6244 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_TX_CHECKER_ABILITY_ALIGN 0 6245 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_TX_CHECKER_ABILITY_BITS 1 6246 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_TX_CHECKER_ABILITY_SHIFT 2 6247 6248 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: pma_prbs31_rx_generator_ability [01:01] */ 6249 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_RX_GENERATOR_ABILITY_MASK 0x0002 6250 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_RX_GENERATOR_ABILITY_ALIGN 0 6251 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_RX_GENERATOR_ABILITY_BITS 1 6252 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_RX_GENERATOR_ABILITY_SHIFT 1 6253 6254 /* ieee_pma_pmd_regs :: pma_pmd_test_pattern_ability :: pma_prbs31_rx_checker_ability [00:00] */ 6255 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_RX_CHECKER_ABILITY_MASK 0x0001 6256 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_RX_CHECKER_ABILITY_ALIGN 0 6257 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_RX_CHECKER_ABILITY_BITS 1 6258 #define IEEE_PMA_PMD_REGS_PMA_PMD_TEST_PATTERN_ABILITY_PMA_PRBS31_RX_CHECKER_ABILITY_SHIFT 0 6259 6260 6261 /**************************************************************************** 6262 * ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control 6263 */ 6264 /* ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control :: reserved0 [15:08] */ 6265 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_RESERVED0_MASK 0xff00 6266 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_RESERVED0_ALIGN 0 6267 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_RESERVED0_BITS 8 6268 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_RESERVED0_SHIFT 8 6269 6270 /* ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control :: pma_prbs31_pattern_enable [07:07] */ 6271 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_PRBS31_PATTERN_ENABLE_MASK 0x0080 6272 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_PRBS31_PATTERN_ENABLE_ALIGN 0 6273 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_PRBS31_PATTERN_ENABLE_BITS 1 6274 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_PRBS31_PATTERN_ENABLE_SHIFT 7 6275 6276 /* ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control :: pma_prbs9_pattern_enable [06:06] */ 6277 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_PRBS9_PATTERN_ENABLE_MASK 0x0040 6278 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_PRBS9_PATTERN_ENABLE_ALIGN 0 6279 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_PRBS9_PATTERN_ENABLE_BITS 1 6280 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_PRBS9_PATTERN_ENABLE_SHIFT 6 6281 6282 /* ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control :: reserved1 [05:04] */ 6283 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_RESERVED1_MASK 0x0030 6284 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_RESERVED1_ALIGN 0 6285 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_RESERVED1_BITS 2 6286 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_RESERVED1_SHIFT 4 6287 6288 /* ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control :: pma_tx_generator_enable [03:03] */ 6289 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_TX_GENERATOR_ENABLE_MASK 0x0008 6290 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_TX_GENERATOR_ENABLE_ALIGN 0 6291 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_TX_GENERATOR_ENABLE_BITS 1 6292 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_TX_GENERATOR_ENABLE_SHIFT 3 6293 6294 /* ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control :: pma_tx_checker_enable [02:02] */ 6295 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_TX_CHECKER_ENABLE_MASK 0x0004 6296 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_TX_CHECKER_ENABLE_ALIGN 0 6297 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_TX_CHECKER_ENABLE_BITS 1 6298 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_TX_CHECKER_ENABLE_SHIFT 2 6299 6300 /* ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control :: pma_rx_generator_enable [01:01] */ 6301 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_RX_GENERATOR_ENABLE_MASK 0x0002 6302 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_RX_GENERATOR_ENABLE_ALIGN 0 6303 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_RX_GENERATOR_ENABLE_BITS 1 6304 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_RX_GENERATOR_ENABLE_SHIFT 1 6305 6306 /* ieee_pma_pmd_regs :: pma_pmd_prbs_pattern_test_control :: pma_rx_checker_enable [00:00] */ 6307 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_RX_CHECKER_ENABLE_MASK 0x0001 6308 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_RX_CHECKER_ENABLE_ALIGN 0 6309 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_RX_CHECKER_ENABLE_BITS 1 6310 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_PATTERN_TEST_CONTROL_PMA_RX_CHECKER_ENABLE_SHIFT 0 6311 6312 6313 /**************************************************************************** 6314 * ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control 6315 */ 6316 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: reserved0 [15:10] */ 6317 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_RESERVED0_MASK 0xfc00 6318 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_RESERVED0_ALIGN 0 6319 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_RESERVED0_BITS 6 6320 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_RESERVED0_SHIFT 10 6321 6322 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane9_sw_enable [09:09] */ 6323 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE9_SW_ENABLE_MASK 0x0200 6324 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE9_SW_ENABLE_ALIGN 0 6325 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE9_SW_ENABLE_BITS 1 6326 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE9_SW_ENABLE_SHIFT 9 6327 6328 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane8_sw_enable [08:08] */ 6329 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE8_SW_ENABLE_MASK 0x0100 6330 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE8_SW_ENABLE_ALIGN 0 6331 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE8_SW_ENABLE_BITS 1 6332 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE8_SW_ENABLE_SHIFT 8 6333 6334 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane7_sw_enable [07:07] */ 6335 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE7_SW_ENABLE_MASK 0x0080 6336 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE7_SW_ENABLE_ALIGN 0 6337 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE7_SW_ENABLE_BITS 1 6338 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE7_SW_ENABLE_SHIFT 7 6339 6340 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane6_sw_enable [06:06] */ 6341 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE6_SW_ENABLE_MASK 0x0040 6342 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE6_SW_ENABLE_ALIGN 0 6343 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE6_SW_ENABLE_BITS 1 6344 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE6_SW_ENABLE_SHIFT 6 6345 6346 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane5_sw_enable [05:05] */ 6347 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE5_SW_ENABLE_MASK 0x0020 6348 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE5_SW_ENABLE_ALIGN 0 6349 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE5_SW_ENABLE_BITS 1 6350 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE5_SW_ENABLE_SHIFT 5 6351 6352 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane4_sw_enable [04:04] */ 6353 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE4_SW_ENABLE_MASK 0x0010 6354 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE4_SW_ENABLE_ALIGN 0 6355 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE4_SW_ENABLE_BITS 1 6356 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE4_SW_ENABLE_SHIFT 4 6357 6358 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane3_sw_enable [03:03] */ 6359 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE3_SW_ENABLE_MASK 0x0008 6360 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE3_SW_ENABLE_ALIGN 0 6361 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE3_SW_ENABLE_BITS 1 6362 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE3_SW_ENABLE_SHIFT 3 6363 6364 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane2_sw_enable [02:02] */ 6365 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE2_SW_ENABLE_MASK 0x0004 6366 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE2_SW_ENABLE_ALIGN 0 6367 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE2_SW_ENABLE_BITS 1 6368 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE2_SW_ENABLE_SHIFT 2 6369 6370 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane1_sw_enable [01:01] */ 6371 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE1_SW_ENABLE_MASK 0x0002 6372 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE1_SW_ENABLE_ALIGN 0 6373 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE1_SW_ENABLE_BITS 1 6374 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE1_SW_ENABLE_SHIFT 1 6375 6376 /* ieee_pma_pmd_regs :: pma_pmd_square_wave_test_control :: pma_lane0_sw_enable [00:00] */ 6377 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE0_SW_ENABLE_MASK 0x0001 6378 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE0_SW_ENABLE_ALIGN 0 6379 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE0_SW_ENABLE_BITS 1 6380 #define IEEE_PMA_PMD_REGS_PMA_PMD_SQUARE_WAVE_TEST_CONTROL_PMA_LANE0_SW_ENABLE_SHIFT 0 6381 6382 6383 /**************************************************************************** 6384 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_0 6385 */ 6386 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_0 :: pma_pmd_prbs_tx_error_counter_lane_0_f [15:00] */ 6387 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0_F_MASK 0xffff 6388 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0_F_ALIGN 0 6389 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0_F_BITS 16 6390 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_0_F_SHIFT 0 6391 6392 6393 /**************************************************************************** 6394 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_1 6395 */ 6396 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_1 :: pma_pmd_prbs_tx_error_counter_lane_1_f [15:00] */ 6397 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1_F_MASK 0xffff 6398 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1_F_ALIGN 0 6399 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1_F_BITS 16 6400 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_1_F_SHIFT 0 6401 6402 6403 /**************************************************************************** 6404 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_2 6405 */ 6406 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_2 :: pma_pmd_prbs_tx_error_counter_lane_2_f [15:00] */ 6407 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2_F_MASK 0xffff 6408 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2_F_ALIGN 0 6409 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2_F_BITS 16 6410 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_2_F_SHIFT 0 6411 6412 6413 /**************************************************************************** 6414 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_3 6415 */ 6416 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_3 :: pma_pmd_prbs_tx_error_counter_lane_3_f [15:00] */ 6417 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3_F_MASK 0xffff 6418 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3_F_ALIGN 0 6419 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3_F_BITS 16 6420 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_3_F_SHIFT 0 6421 6422 6423 /**************************************************************************** 6424 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_4 6425 */ 6426 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_4 :: pma_pmd_prbs_tx_error_counter_lane_4_f [15:00] */ 6427 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4_F_MASK 0xffff 6428 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4_F_ALIGN 0 6429 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4_F_BITS 16 6430 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_4_F_SHIFT 0 6431 6432 6433 /**************************************************************************** 6434 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_5 6435 */ 6436 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_5 :: pma_pmd_prbs_tx_error_counter_lane_5_f [15:00] */ 6437 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5_F_MASK 0xffff 6438 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5_F_ALIGN 0 6439 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5_F_BITS 16 6440 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_5_F_SHIFT 0 6441 6442 6443 /**************************************************************************** 6444 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_6 6445 */ 6446 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_6 :: pma_pmd_prbs_tx_error_counter_lane_6_f [15:00] */ 6447 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6_F_MASK 0xffff 6448 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6_F_ALIGN 0 6449 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6_F_BITS 16 6450 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_6_F_SHIFT 0 6451 6452 6453 /**************************************************************************** 6454 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_7 6455 */ 6456 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_7 :: pma_pmd_prbs_tx_error_counter_lane_7_f [15:00] */ 6457 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7_F_MASK 0xffff 6458 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7_F_ALIGN 0 6459 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7_F_BITS 16 6460 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_7_F_SHIFT 0 6461 6462 6463 /**************************************************************************** 6464 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_8 6465 */ 6466 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_8 :: pma_pmd_prbs_tx_error_counter_lane_8_f [15:00] */ 6467 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8_F_MASK 0xffff 6468 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8_F_ALIGN 0 6469 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8_F_BITS 16 6470 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_8_F_SHIFT 0 6471 6472 6473 /**************************************************************************** 6474 * ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_9 6475 */ 6476 /* ieee_pma_pmd_regs :: pma_pmd_prbs_tx_error_counter_lane_9 :: pma_pmd_prbs_tx_error_counter_lane_9_f [15:00] */ 6477 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9_F_MASK 0xffff 6478 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9_F_ALIGN 0 6479 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9_F_BITS 16 6480 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9_PMA_PMD_PRBS_TX_ERROR_COUNTER_LANE_9_F_SHIFT 0 6481 6482 6483 /**************************************************************************** 6484 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_0 6485 */ 6486 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_0 :: pma_pmd_prbs_rx_error_counter_lane_0_f [15:00] */ 6487 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0_F_MASK 0xffff 6488 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0_F_ALIGN 0 6489 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0_F_BITS 16 6490 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_0_F_SHIFT 0 6491 6492 6493 /**************************************************************************** 6494 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_1 6495 */ 6496 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_1 :: pma_pmd_prbs_rx_error_counter_lane_1_f [15:00] */ 6497 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1_F_MASK 0xffff 6498 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1_F_ALIGN 0 6499 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1_F_BITS 16 6500 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_1_F_SHIFT 0 6501 6502 6503 /**************************************************************************** 6504 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_2 6505 */ 6506 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_2 :: pma_pmd_prbs_rx_error_counter_lane_2_f [15:00] */ 6507 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2_F_MASK 0xffff 6508 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2_F_ALIGN 0 6509 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2_F_BITS 16 6510 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_2_F_SHIFT 0 6511 6512 6513 /**************************************************************************** 6514 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_3 6515 */ 6516 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_3 :: pma_pmd_prbs_rx_error_counter_lane_3_f [15:00] */ 6517 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3_F_MASK 0xffff 6518 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3_F_ALIGN 0 6519 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3_F_BITS 16 6520 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_3_F_SHIFT 0 6521 6522 6523 /**************************************************************************** 6524 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_4 6525 */ 6526 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_4 :: pma_pmd_prbs_rx_error_counter_lane_4_f [15:00] */ 6527 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4_F_MASK 0xffff 6528 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4_F_ALIGN 0 6529 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4_F_BITS 16 6530 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_4_F_SHIFT 0 6531 6532 6533 /**************************************************************************** 6534 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_5 6535 */ 6536 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_5 :: pma_pmd_prbs_rx_error_counter_lane_5_f [15:00] */ 6537 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5_F_MASK 0xffff 6538 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5_F_ALIGN 0 6539 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5_F_BITS 16 6540 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_5_F_SHIFT 0 6541 6542 6543 /**************************************************************************** 6544 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_6 6545 */ 6546 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_6 :: pma_pmd_prbs_rx_error_counter_lane_6_f [15:00] */ 6547 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6_F_MASK 0xffff 6548 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6_F_ALIGN 0 6549 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6_F_BITS 16 6550 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_6_F_SHIFT 0 6551 6552 6553 /**************************************************************************** 6554 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_7 6555 */ 6556 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_7 :: pma_pmd_prbs_rx_error_counter_lane_7_f [15:00] */ 6557 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7_F_MASK 0xffff 6558 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7_F_ALIGN 0 6559 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7_F_BITS 16 6560 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_7_F_SHIFT 0 6561 6562 6563 /**************************************************************************** 6564 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_8 6565 */ 6566 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_8 :: pma_pmd_prbs_rx_error_counter_lane_8_f [15:00] */ 6567 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8_F_MASK 0xffff 6568 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8_F_ALIGN 0 6569 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8_F_BITS 16 6570 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_8_F_SHIFT 0 6571 6572 6573 /**************************************************************************** 6574 * ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_9 6575 */ 6576 /* ieee_pma_pmd_regs :: pma_pmd_prbs_rx_error_counter_lane_9 :: pma_pmd_prbs_rx_error_counter_lane_9_f [15:00] */ 6577 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9_F_MASK 0xffff 6578 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9_F_ALIGN 0 6579 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9_F_BITS 16 6580 #define IEEE_PMA_PMD_REGS_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9_PMA_PMD_PRBS_RX_ERROR_COUNTER_LANE_9_F_SHIFT 0 6581 6582 6583 /**************************************************************************** 6584 * rg_rx_regs 6585 */ 6586 /**************************************************************************** 6587 * rg_rx :: rx_gb_system_reset 6588 */ 6589 /* rg_rx :: rx_gb_system_reset :: reserved0 [15:10] */ 6590 #define RG_RX_RX_GB_SYSTEM_RESET_RESERVED0_MASK 0xfc00 6591 #define RG_RX_RX_GB_SYSTEM_RESET_RESERVED0_ALIGN 0 6592 #define RG_RX_RX_GB_SYSTEM_RESET_RESERVED0_BITS 6 6593 #define RG_RX_RX_GB_SYSTEM_RESET_RESERVED0_SHIFT 10 6594 6595 /* rg_rx :: rx_gb_system_reset :: srx_rstb [09:00] */ 6596 #define RG_RX_RX_GB_SYSTEM_RESET_SRX_RSTB_MASK 0x03ff 6597 #define RG_RX_RX_GB_SYSTEM_RESET_SRX_RSTB_ALIGN 0 6598 #define RG_RX_RX_GB_SYSTEM_RESET_SRX_RSTB_BITS 10 6599 #define RG_RX_RX_GB_SYSTEM_RESET_SRX_RSTB_SHIFT 0 6600 6601 6602 /**************************************************************************** 6603 * rg_rx :: rx_gb_system_reset_frc 6604 */ 6605 /* rg_rx :: rx_gb_system_reset_frc :: reserved0 [15:10] */ 6606 #define RG_RX_RX_GB_SYSTEM_RESET_FRC_RESERVED0_MASK 0xfc00 6607 #define RG_RX_RX_GB_SYSTEM_RESET_FRC_RESERVED0_ALIGN 0 6608 #define RG_RX_RX_GB_SYSTEM_RESET_FRC_RESERVED0_BITS 6 6609 #define RG_RX_RX_GB_SYSTEM_RESET_FRC_RESERVED0_SHIFT 10 6610 6611 /* rg_rx :: rx_gb_system_reset_frc :: srx_rstb_frc [09:00] */ 6612 #define RG_RX_RX_GB_SYSTEM_RESET_FRC_SRX_RSTB_FRC_MASK 0x03ff 6613 #define RG_RX_RX_GB_SYSTEM_RESET_FRC_SRX_RSTB_FRC_ALIGN 0 6614 #define RG_RX_RX_GB_SYSTEM_RESET_FRC_SRX_RSTB_FRC_BITS 10 6615 #define RG_RX_RX_GB_SYSTEM_RESET_FRC_SRX_RSTB_FRC_SHIFT 0 6616 6617 6618 /**************************************************************************** 6619 * rg_rx :: rx_gb_line_reset 6620 */ 6621 /* rg_rx :: rx_gb_line_reset :: reserved0 [15:10] */ 6622 #define RG_RX_RX_GB_LINE_RESET_RESERVED0_MASK 0xfc00 6623 #define RG_RX_RX_GB_LINE_RESET_RESERVED0_ALIGN 0 6624 #define RG_RX_RX_GB_LINE_RESET_RESERVED0_BITS 6 6625 #define RG_RX_RX_GB_LINE_RESET_RESERVED0_SHIFT 10 6626 6627 /* rg_rx :: rx_gb_line_reset :: lrx_rstb [09:00] */ 6628 #define RG_RX_RX_GB_LINE_RESET_LRX_RSTB_MASK 0x03ff 6629 #define RG_RX_RX_GB_LINE_RESET_LRX_RSTB_ALIGN 0 6630 #define RG_RX_RX_GB_LINE_RESET_LRX_RSTB_BITS 10 6631 #define RG_RX_RX_GB_LINE_RESET_LRX_RSTB_SHIFT 0 6632 6633 6634 /**************************************************************************** 6635 * rg_rx :: rx_gb_line_reset_frc 6636 */ 6637 /* rg_rx :: rx_gb_line_reset_frc :: reserved0 [15:10] */ 6638 #define RG_RX_RX_GB_LINE_RESET_FRC_RESERVED0_MASK 0xfc00 6639 #define RG_RX_RX_GB_LINE_RESET_FRC_RESERVED0_ALIGN 0 6640 #define RG_RX_RX_GB_LINE_RESET_FRC_RESERVED0_BITS 6 6641 #define RG_RX_RX_GB_LINE_RESET_FRC_RESERVED0_SHIFT 10 6642 6643 /* rg_rx :: rx_gb_line_reset_frc :: lrx_rstb_frc [09:00] */ 6644 #define RG_RX_RX_GB_LINE_RESET_FRC_LRX_RSTB_FRC_MASK 0x03ff 6645 #define RG_RX_RX_GB_LINE_RESET_FRC_LRX_RSTB_FRC_ALIGN 0 6646 #define RG_RX_RX_GB_LINE_RESET_FRC_LRX_RSTB_FRC_BITS 10 6647 #define RG_RX_RX_GB_LINE_RESET_FRC_LRX_RSTB_FRC_SHIFT 0 6648 6649 6650 /**************************************************************************** 6651 * rg_rx :: rx_gb_db_test_ctrl 6652 */ 6653 /* rg_rx :: rx_gb_db_test_ctrl :: db_bypass [15:12] */ 6654 #define RG_RX_RX_GB_DB_TEST_CTRL_DB_BYPASS_MASK 0xf000 6655 #define RG_RX_RX_GB_DB_TEST_CTRL_DB_BYPASS_ALIGN 0 6656 #define RG_RX_RX_GB_DB_TEST_CTRL_DB_BYPASS_BITS 4 6657 #define RG_RX_RX_GB_DB_TEST_CTRL_DB_BYPASS_SHIFT 12 6658 6659 /* rg_rx :: rx_gb_db_test_ctrl :: db_inv_en [11:08] */ 6660 #define RG_RX_RX_GB_DB_TEST_CTRL_DB_INV_EN_MASK 0x0f00 6661 #define RG_RX_RX_GB_DB_TEST_CTRL_DB_INV_EN_ALIGN 0 6662 #define RG_RX_RX_GB_DB_TEST_CTRL_DB_INV_EN_BITS 4 6663 #define RG_RX_RX_GB_DB_TEST_CTRL_DB_INV_EN_SHIFT 8 6664 6665 /* rg_rx :: rx_gb_db_test_ctrl :: ber_mntr_en [07:04] */ 6666 #define RG_RX_RX_GB_DB_TEST_CTRL_BER_MNTR_EN_MASK 0x00f0 6667 #define RG_RX_RX_GB_DB_TEST_CTRL_BER_MNTR_EN_ALIGN 0 6668 #define RG_RX_RX_GB_DB_TEST_CTRL_BER_MNTR_EN_BITS 4 6669 #define RG_RX_RX_GB_DB_TEST_CTRL_BER_MNTR_EN_SHIFT 4 6670 6671 /* rg_rx :: rx_gb_db_test_ctrl :: ieee_mode [03:00] */ 6672 #define RG_RX_RX_GB_DB_TEST_CTRL_IEEE_MODE_MASK 0x000f 6673 #define RG_RX_RX_GB_DB_TEST_CTRL_IEEE_MODE_ALIGN 0 6674 #define RG_RX_RX_GB_DB_TEST_CTRL_IEEE_MODE_BITS 4 6675 #define RG_RX_RX_GB_DB_TEST_CTRL_IEEE_MODE_SHIFT 0 6676 6677 6678 /**************************************************************************** 6679 * rg_rx :: rx_gb_test_ctrl_ln49 6680 */ 6681 /* rg_rx :: rx_gb_test_ctrl_ln49 :: reserved0 [15:14] */ 6682 #define RG_RX_RX_GB_TEST_CTRL_LN49_RESERVED0_MASK 0xc000 6683 #define RG_RX_RX_GB_TEST_CTRL_LN49_RESERVED0_ALIGN 0 6684 #define RG_RX_RX_GB_TEST_CTRL_LN49_RESERVED0_BITS 2 6685 #define RG_RX_RX_GB_TEST_CTRL_LN49_RESERVED0_SHIFT 14 6686 6687 /* rg_rx :: rx_gb_test_ctrl_ln49 :: ieee_prbs_inv [13:13] */ 6688 #define RG_RX_RX_GB_TEST_CTRL_LN49_IEEE_PRBS_INV_MASK 0x2000 6689 #define RG_RX_RX_GB_TEST_CTRL_LN49_IEEE_PRBS_INV_ALIGN 0 6690 #define RG_RX_RX_GB_TEST_CTRL_LN49_IEEE_PRBS_INV_BITS 1 6691 #define RG_RX_RX_GB_TEST_CTRL_LN49_IEEE_PRBS_INV_SHIFT 13 6692 6693 /* rg_rx :: rx_gb_test_ctrl_ln49 :: ieee_cnt_div3 [12:12] */ 6694 #define RG_RX_RX_GB_TEST_CTRL_LN49_IEEE_CNT_DIV3_MASK 0x1000 6695 #define RG_RX_RX_GB_TEST_CTRL_LN49_IEEE_CNT_DIV3_ALIGN 0 6696 #define RG_RX_RX_GB_TEST_CTRL_LN49_IEEE_CNT_DIV3_BITS 1 6697 #define RG_RX_RX_GB_TEST_CTRL_LN49_IEEE_CNT_DIV3_SHIFT 12 6698 6699 /* rg_rx :: rx_gb_test_ctrl_ln49 :: prbs_err_cap_en [11:06] */ 6700 #define RG_RX_RX_GB_TEST_CTRL_LN49_PRBS_ERR_CAP_EN_MASK 0x0fc0 6701 #define RG_RX_RX_GB_TEST_CTRL_LN49_PRBS_ERR_CAP_EN_ALIGN 0 6702 #define RG_RX_RX_GB_TEST_CTRL_LN49_PRBS_ERR_CAP_EN_BITS 6 6703 #define RG_RX_RX_GB_TEST_CTRL_LN49_PRBS_ERR_CAP_EN_SHIFT 6 6704 6705 /* rg_rx :: rx_gb_test_ctrl_ln49 :: prbs_chk_en [05:00] */ 6706 #define RG_RX_RX_GB_TEST_CTRL_LN49_PRBS_CHK_EN_MASK 0x003f 6707 #define RG_RX_RX_GB_TEST_CTRL_LN49_PRBS_CHK_EN_ALIGN 0 6708 #define RG_RX_RX_GB_TEST_CTRL_LN49_PRBS_CHK_EN_BITS 6 6709 #define RG_RX_RX_GB_TEST_CTRL_LN49_PRBS_CHK_EN_SHIFT 0 6710 6711 6712 /**************************************************************************** 6713 * rg_rx :: rx_gb_test_ctrl_ln03 6714 */ 6715 /* rg_rx :: rx_gb_test_ctrl_ln03 :: prbs_err_cap_en [15:12] */ 6716 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_ERR_CAP_EN_MASK 0xf000 6717 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_ERR_CAP_EN_ALIGN 0 6718 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_ERR_CAP_EN_BITS 4 6719 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_ERR_CAP_EN_SHIFT 12 6720 6721 /* rg_rx :: rx_gb_test_ctrl_ln03 :: prbs_unlock_dis [11:08] */ 6722 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_UNLOCK_DIS_MASK 0x0f00 6723 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_UNLOCK_DIS_ALIGN 0 6724 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_UNLOCK_DIS_BITS 4 6725 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_UNLOCK_DIS_SHIFT 8 6726 6727 /* rg_rx :: rx_gb_test_ctrl_ln03 :: prbs_autodet_dis [07:04] */ 6728 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_AUTODET_DIS_MASK 0x00f0 6729 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_AUTODET_DIS_ALIGN 0 6730 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_AUTODET_DIS_BITS 4 6731 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_AUTODET_DIS_SHIFT 4 6732 6733 /* rg_rx :: rx_gb_test_ctrl_ln03 :: prbs_chk_en [03:00] */ 6734 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_CHK_EN_MASK 0x000f 6735 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_CHK_EN_ALIGN 0 6736 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_CHK_EN_BITS 4 6737 #define RG_RX_RX_GB_TEST_CTRL_LN03_PRBS_CHK_EN_SHIFT 0 6738 6739 6740 /**************************************************************************** 6741 * rg_rx :: rx_gb_prbs_inv_in 6742 */ 6743 /* rg_rx :: rx_gb_prbs_inv_in :: prbs_inv_in [15:12] */ 6744 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_INV_IN_MASK 0xf000 6745 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_INV_IN_ALIGN 0 6746 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_INV_IN_BITS 4 6747 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_INV_IN_SHIFT 12 6748 6749 /* rg_rx :: rx_gb_prbs_inv_in :: prbs_sel_in3 [11:09] */ 6750 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN3_MASK 0x0e00 6751 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN3_ALIGN 0 6752 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN3_BITS 3 6753 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN3_SHIFT 9 6754 6755 /* rg_rx :: rx_gb_prbs_inv_in :: prbs_sel_in2 [08:06] */ 6756 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN2_MASK 0x01c0 6757 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN2_ALIGN 0 6758 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN2_BITS 3 6759 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN2_SHIFT 6 6760 6761 /* rg_rx :: rx_gb_prbs_inv_in :: prbs_sel_in1 [05:03] */ 6762 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN1_MASK 0x0038 6763 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN1_ALIGN 0 6764 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN1_BITS 3 6765 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN1_SHIFT 3 6766 6767 /* rg_rx :: rx_gb_prbs_inv_in :: prbs_sel_in0 [02:00] */ 6768 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN0_MASK 0x0007 6769 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN0_ALIGN 0 6770 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN0_BITS 3 6771 #define RG_RX_RX_GB_PRBS_INV_IN_PRBS_SEL_IN0_SHIFT 0 6772 6773 6774 /**************************************************************************** 6775 * rg_rx :: rx_gb_ber_timer_cnt0 6776 */ 6777 /* rg_rx :: rx_gb_ber_timer_cnt0 :: ber_timer_cnt_lsb [15:00] */ 6778 #define RG_RX_RX_GB_BER_TIMER_CNT0_BER_TIMER_CNT_LSB_MASK 0xffff 6779 #define RG_RX_RX_GB_BER_TIMER_CNT0_BER_TIMER_CNT_LSB_ALIGN 0 6780 #define RG_RX_RX_GB_BER_TIMER_CNT0_BER_TIMER_CNT_LSB_BITS 16 6781 #define RG_RX_RX_GB_BER_TIMER_CNT0_BER_TIMER_CNT_LSB_SHIFT 0 6782 6783 6784 /**************************************************************************** 6785 * rg_rx :: rx_gb_ber_timer_cnt1 6786 */ 6787 /* rg_rx :: rx_gb_ber_timer_cnt1 :: ber_timer_cnt_lsb1 [15:00] */ 6788 #define RG_RX_RX_GB_BER_TIMER_CNT1_BER_TIMER_CNT_LSB1_MASK 0xffff 6789 #define RG_RX_RX_GB_BER_TIMER_CNT1_BER_TIMER_CNT_LSB1_ALIGN 0 6790 #define RG_RX_RX_GB_BER_TIMER_CNT1_BER_TIMER_CNT_LSB1_BITS 16 6791 #define RG_RX_RX_GB_BER_TIMER_CNT1_BER_TIMER_CNT_LSB1_SHIFT 0 6792 6793 6794 /**************************************************************************** 6795 * rg_rx :: rx_gb_test_misc_ctrl 6796 */ 6797 /* rg_rx :: rx_gb_test_misc_ctrl :: reserved0 [15:12] */ 6798 #define RG_RX_RX_GB_TEST_MISC_CTRL_RESERVED0_MASK 0xf000 6799 #define RG_RX_RX_GB_TEST_MISC_CTRL_RESERVED0_ALIGN 0 6800 #define RG_RX_RX_GB_TEST_MISC_CTRL_RESERVED0_BITS 4 6801 #define RG_RX_RX_GB_TEST_MISC_CTRL_RESERVED0_SHIFT 12 6802 6803 /* rg_rx :: rx_gb_test_misc_ctrl :: check_port [11:08] */ 6804 #define RG_RX_RX_GB_TEST_MISC_CTRL_CHECK_PORT_MASK 0x0f00 6805 #define RG_RX_RX_GB_TEST_MISC_CTRL_CHECK_PORT_ALIGN 0 6806 #define RG_RX_RX_GB_TEST_MISC_CTRL_CHECK_PORT_BITS 4 6807 #define RG_RX_RX_GB_TEST_MISC_CTRL_CHECK_PORT_SHIFT 8 6808 6809 /* rg_rx :: rx_gb_test_misc_ctrl :: start_ber_mntr [07:04] */ 6810 #define RG_RX_RX_GB_TEST_MISC_CTRL_START_BER_MNTR_MASK 0x00f0 6811 #define RG_RX_RX_GB_TEST_MISC_CTRL_START_BER_MNTR_ALIGN 0 6812 #define RG_RX_RX_GB_TEST_MISC_CTRL_START_BER_MNTR_BITS 4 6813 #define RG_RX_RX_GB_TEST_MISC_CTRL_START_BER_MNTR_SHIFT 4 6814 6815 /* rg_rx :: rx_gb_test_misc_ctrl :: ber_timer_cnt_msb [03:00] */ 6816 #define RG_RX_RX_GB_TEST_MISC_CTRL_BER_TIMER_CNT_MSB_MASK 0x000f 6817 #define RG_RX_RX_GB_TEST_MISC_CTRL_BER_TIMER_CNT_MSB_ALIGN 0 6818 #define RG_RX_RX_GB_TEST_MISC_CTRL_BER_TIMER_CNT_MSB_BITS 4 6819 #define RG_RX_RX_GB_TEST_MISC_CTRL_BER_TIMER_CNT_MSB_SHIFT 0 6820 6821 6822 /**************************************************************************** 6823 * rg_rx :: rx_gb_lp_ptr_sync0 6824 */ 6825 /* rg_rx :: rx_gb_lp_ptr_sync0 :: lp_ptr_sync3 [15:12] */ 6826 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC3_MASK 0xf000 6827 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC3_ALIGN 0 6828 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC3_BITS 4 6829 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC3_SHIFT 12 6830 6831 /* rg_rx :: rx_gb_lp_ptr_sync0 :: lp_ptr_sync2 [11:08] */ 6832 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC2_MASK 0x0f00 6833 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC2_ALIGN 0 6834 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC2_BITS 4 6835 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC2_SHIFT 8 6836 6837 /* rg_rx :: rx_gb_lp_ptr_sync0 :: lp_ptr_sync1 [07:04] */ 6838 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC1_MASK 0x00f0 6839 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC1_ALIGN 0 6840 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC1_BITS 4 6841 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC1_SHIFT 4 6842 6843 /* rg_rx :: rx_gb_lp_ptr_sync0 :: lp_ptr_sync0 [03:00] */ 6844 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC0_MASK 0x000f 6845 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC0_ALIGN 0 6846 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC0_BITS 4 6847 #define RG_RX_RX_GB_LP_PTR_SYNC0_LP_PTR_SYNC0_SHIFT 0 6848 6849 6850 /**************************************************************************** 6851 * rg_rx :: rx_gb_lp_ptr_sync1 6852 */ 6853 /* rg_rx :: rx_gb_lp_ptr_sync1 :: lp_ptr_sync7 [15:12] */ 6854 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC7_MASK 0xf000 6855 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC7_ALIGN 0 6856 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC7_BITS 4 6857 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC7_SHIFT 12 6858 6859 /* rg_rx :: rx_gb_lp_ptr_sync1 :: lp_ptr_sync6 [11:08] */ 6860 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC6_MASK 0x0f00 6861 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC6_ALIGN 0 6862 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC6_BITS 4 6863 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC6_SHIFT 8 6864 6865 /* rg_rx :: rx_gb_lp_ptr_sync1 :: lp_ptr_sync5 [07:04] */ 6866 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC5_MASK 0x00f0 6867 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC5_ALIGN 0 6868 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC5_BITS 4 6869 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC5_SHIFT 4 6870 6871 /* rg_rx :: rx_gb_lp_ptr_sync1 :: lp_ptr_sync4 [03:00] */ 6872 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC4_MASK 0x000f 6873 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC4_ALIGN 0 6874 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC4_BITS 4 6875 #define RG_RX_RX_GB_LP_PTR_SYNC1_LP_PTR_SYNC4_SHIFT 0 6876 6877 6878 /**************************************************************************** 6879 * rg_rx :: rx_gb_ln89_ptr_sync 6880 */ 6881 /* rg_rx :: rx_gb_ln89_ptr_sync :: ptr_sync9 [15:12] */ 6882 #define RG_RX_RX_GB_LN89_PTR_SYNC_PTR_SYNC9_MASK 0xf000 6883 #define RG_RX_RX_GB_LN89_PTR_SYNC_PTR_SYNC9_ALIGN 0 6884 #define RG_RX_RX_GB_LN89_PTR_SYNC_PTR_SYNC9_BITS 4 6885 #define RG_RX_RX_GB_LN89_PTR_SYNC_PTR_SYNC9_SHIFT 12 6886 6887 /* rg_rx :: rx_gb_ln89_ptr_sync :: ptr_sync8 [11:08] */ 6888 #define RG_RX_RX_GB_LN89_PTR_SYNC_PTR_SYNC8_MASK 0x0f00 6889 #define RG_RX_RX_GB_LN89_PTR_SYNC_PTR_SYNC8_ALIGN 0 6890 #define RG_RX_RX_GB_LN89_PTR_SYNC_PTR_SYNC8_BITS 4 6891 #define RG_RX_RX_GB_LN89_PTR_SYNC_PTR_SYNC8_SHIFT 8 6892 6893 /* rg_rx :: rx_gb_ln89_ptr_sync :: lp_ptr_sync9 [07:04] */ 6894 #define RG_RX_RX_GB_LN89_PTR_SYNC_LP_PTR_SYNC9_MASK 0x00f0 6895 #define RG_RX_RX_GB_LN89_PTR_SYNC_LP_PTR_SYNC9_ALIGN 0 6896 #define RG_RX_RX_GB_LN89_PTR_SYNC_LP_PTR_SYNC9_BITS 4 6897 #define RG_RX_RX_GB_LN89_PTR_SYNC_LP_PTR_SYNC9_SHIFT 4 6898 6899 /* rg_rx :: rx_gb_ln89_ptr_sync :: lp_ptr_sync8 [03:00] */ 6900 #define RG_RX_RX_GB_LN89_PTR_SYNC_LP_PTR_SYNC8_MASK 0x000f 6901 #define RG_RX_RX_GB_LN89_PTR_SYNC_LP_PTR_SYNC8_ALIGN 0 6902 #define RG_RX_RX_GB_LN89_PTR_SYNC_LP_PTR_SYNC8_BITS 4 6903 #define RG_RX_RX_GB_LN89_PTR_SYNC_LP_PTR_SYNC8_SHIFT 0 6904 6905 6906 /**************************************************************************** 6907 * rg_rx :: rx_gb_ptr_sync1 6908 */ 6909 /* rg_rx :: rx_gb_ptr_sync1 :: ptr_sync7 [15:12] */ 6910 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC7_MASK 0xf000 6911 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC7_ALIGN 0 6912 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC7_BITS 4 6913 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC7_SHIFT 12 6914 6915 /* rg_rx :: rx_gb_ptr_sync1 :: ptr_sync6 [11:08] */ 6916 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC6_MASK 0x0f00 6917 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC6_ALIGN 0 6918 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC6_BITS 4 6919 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC6_SHIFT 8 6920 6921 /* rg_rx :: rx_gb_ptr_sync1 :: ptr_sync5 [07:04] */ 6922 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC5_MASK 0x00f0 6923 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC5_ALIGN 0 6924 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC5_BITS 4 6925 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC5_SHIFT 4 6926 6927 /* rg_rx :: rx_gb_ptr_sync1 :: ptr_sync4 [03:00] */ 6928 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC4_MASK 0x000f 6929 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC4_ALIGN 0 6930 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC4_BITS 4 6931 #define RG_RX_RX_GB_PTR_SYNC1_PTR_SYNC4_SHIFT 0 6932 6933 6934 /**************************************************************************** 6935 * rg_rx :: rx_gb_ptr_sync0 6936 */ 6937 /* rg_rx :: rx_gb_ptr_sync0 :: ptr_sync3 [15:12] */ 6938 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC3_MASK 0xf000 6939 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC3_ALIGN 0 6940 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC3_BITS 4 6941 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC3_SHIFT 12 6942 6943 /* rg_rx :: rx_gb_ptr_sync0 :: ptr_sync2 [11:08] */ 6944 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC2_MASK 0x0f00 6945 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC2_ALIGN 0 6946 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC2_BITS 4 6947 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC2_SHIFT 8 6948 6949 /* rg_rx :: rx_gb_ptr_sync0 :: ptr_sync1 [07:04] */ 6950 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC1_MASK 0x00f0 6951 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC1_ALIGN 0 6952 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC1_BITS 4 6953 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC1_SHIFT 4 6954 6955 /* rg_rx :: rx_gb_ptr_sync0 :: ptr_sync0 [03:00] */ 6956 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC0_MASK 0x000f 6957 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC0_ALIGN 0 6958 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC0_BITS 4 6959 #define RG_RX_RX_GB_PTR_SYNC0_PTR_SYNC0_SHIFT 0 6960 6961 6962 /**************************************************************************** 6963 * rg_rx :: rx_gb_lpbk_col_threshold0 6964 */ 6965 /* rg_rx :: rx_gb_lpbk_col_threshold0 :: lpbk_col_threshold3 [15:12] */ 6966 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD3_MASK 0xf000 6967 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD3_ALIGN 0 6968 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD3_BITS 4 6969 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD3_SHIFT 12 6970 6971 /* rg_rx :: rx_gb_lpbk_col_threshold0 :: lpbk_col_threshold2 [11:08] */ 6972 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD2_MASK 0x0f00 6973 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD2_ALIGN 0 6974 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD2_BITS 4 6975 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD2_SHIFT 8 6976 6977 /* rg_rx :: rx_gb_lpbk_col_threshold0 :: lpbk_col_threshold1 [07:04] */ 6978 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD1_MASK 0x00f0 6979 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD1_ALIGN 0 6980 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD1_BITS 4 6981 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD1_SHIFT 4 6982 6983 /* rg_rx :: rx_gb_lpbk_col_threshold0 :: lpbk_col_threshold0 [03:00] */ 6984 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD0_MASK 0x000f 6985 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD0_ALIGN 0 6986 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD0_BITS 4 6987 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD0_SHIFT 0 6988 6989 6990 /**************************************************************************** 6991 * rg_rx :: rx_gb_lpbk_col_threshold1 6992 */ 6993 /* rg_rx :: rx_gb_lpbk_col_threshold1 :: lpbk_col_threshold7 [15:12] */ 6994 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD7_MASK 0xf000 6995 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD7_ALIGN 0 6996 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD7_BITS 4 6997 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD7_SHIFT 12 6998 6999 /* rg_rx :: rx_gb_lpbk_col_threshold1 :: lpbk_col_threshold6 [11:08] */ 7000 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD6_MASK 0x0f00 7001 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD6_ALIGN 0 7002 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD6_BITS 4 7003 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD6_SHIFT 8 7004 7005 /* rg_rx :: rx_gb_lpbk_col_threshold1 :: lpbk_col_threshold5 [07:04] */ 7006 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD5_MASK 0x00f0 7007 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD5_ALIGN 0 7008 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD5_BITS 4 7009 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD5_SHIFT 4 7010 7011 /* rg_rx :: rx_gb_lpbk_col_threshold1 :: lpbk_col_threshold4 [03:00] */ 7012 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD4_MASK 0x000f 7013 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD4_ALIGN 0 7014 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD4_BITS 4 7015 #define RG_RX_RX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD4_SHIFT 0 7016 7017 7018 /**************************************************************************** 7019 * rg_rx :: rx_gb_col_threshold89 7020 */ 7021 /* rg_rx :: rx_gb_col_threshold89 :: col_threshold9 [15:12] */ 7022 #define RG_RX_RX_GB_COL_THRESHOLD89_COL_THRESHOLD9_MASK 0xf000 7023 #define RG_RX_RX_GB_COL_THRESHOLD89_COL_THRESHOLD9_ALIGN 0 7024 #define RG_RX_RX_GB_COL_THRESHOLD89_COL_THRESHOLD9_BITS 4 7025 #define RG_RX_RX_GB_COL_THRESHOLD89_COL_THRESHOLD9_SHIFT 12 7026 7027 /* rg_rx :: rx_gb_col_threshold89 :: col_threshold8 [11:08] */ 7028 #define RG_RX_RX_GB_COL_THRESHOLD89_COL_THRESHOLD8_MASK 0x0f00 7029 #define RG_RX_RX_GB_COL_THRESHOLD89_COL_THRESHOLD8_ALIGN 0 7030 #define RG_RX_RX_GB_COL_THRESHOLD89_COL_THRESHOLD8_BITS 4 7031 #define RG_RX_RX_GB_COL_THRESHOLD89_COL_THRESHOLD8_SHIFT 8 7032 7033 /* rg_rx :: rx_gb_col_threshold89 :: lpbk_col_threshold9 [07:04] */ 7034 #define RG_RX_RX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD9_MASK 0x00f0 7035 #define RG_RX_RX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD9_ALIGN 0 7036 #define RG_RX_RX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD9_BITS 4 7037 #define RG_RX_RX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD9_SHIFT 4 7038 7039 /* rg_rx :: rx_gb_col_threshold89 :: lpbk_col_threshold8 [03:00] */ 7040 #define RG_RX_RX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD8_MASK 0x000f 7041 #define RG_RX_RX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD8_ALIGN 0 7042 #define RG_RX_RX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD8_BITS 4 7043 #define RG_RX_RX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD8_SHIFT 0 7044 7045 7046 /**************************************************************************** 7047 * rg_rx :: rx_gb_col_threshold1 7048 */ 7049 /* rg_rx :: rx_gb_col_threshold1 :: col_threshold7 [15:12] */ 7050 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD7_MASK 0xf000 7051 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD7_ALIGN 0 7052 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD7_BITS 4 7053 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD7_SHIFT 12 7054 7055 /* rg_rx :: rx_gb_col_threshold1 :: col_threshold6 [11:08] */ 7056 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD6_MASK 0x0f00 7057 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD6_ALIGN 0 7058 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD6_BITS 4 7059 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD6_SHIFT 8 7060 7061 /* rg_rx :: rx_gb_col_threshold1 :: col_threshold5 [07:04] */ 7062 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD5_MASK 0x00f0 7063 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD5_ALIGN 0 7064 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD5_BITS 4 7065 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD5_SHIFT 4 7066 7067 /* rg_rx :: rx_gb_col_threshold1 :: col_threshold4 [03:00] */ 7068 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD4_MASK 0x000f 7069 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD4_ALIGN 0 7070 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD4_BITS 4 7071 #define RG_RX_RX_GB_COL_THRESHOLD1_COL_THRESHOLD4_SHIFT 0 7072 7073 7074 /**************************************************************************** 7075 * rg_rx :: rx_gb_col_threshold0 7076 */ 7077 /* rg_rx :: rx_gb_col_threshold0 :: col_threshold3 [15:12] */ 7078 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD3_MASK 0xf000 7079 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD3_ALIGN 0 7080 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD3_BITS 4 7081 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD3_SHIFT 12 7082 7083 /* rg_rx :: rx_gb_col_threshold0 :: col_threshold2 [11:08] */ 7084 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD2_MASK 0x0f00 7085 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD2_ALIGN 0 7086 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD2_BITS 4 7087 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD2_SHIFT 8 7088 7089 /* rg_rx :: rx_gb_col_threshold0 :: col_threshold1 [07:04] */ 7090 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD1_MASK 0x00f0 7091 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD1_ALIGN 0 7092 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD1_BITS 4 7093 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD1_SHIFT 4 7094 7095 /* rg_rx :: rx_gb_col_threshold0 :: col_threshold0 [03:00] */ 7096 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD0_MASK 0x000f 7097 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD0_ALIGN 0 7098 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD0_BITS 4 7099 #define RG_RX_RX_GB_COL_THRESHOLD0_COL_THRESHOLD0_SHIFT 0 7100 7101 7102 /**************************************************************************** 7103 * rg_rx :: rx_gb_prbs_gen_ierr 7104 */ 7105 /* rg_rx :: rx_gb_prbs_gen_ierr :: reserved0 [15:10] */ 7106 #define RG_RX_RX_GB_PRBS_GEN_IERR_RESERVED0_MASK 0xfc00 7107 #define RG_RX_RX_GB_PRBS_GEN_IERR_RESERVED0_ALIGN 0 7108 #define RG_RX_RX_GB_PRBS_GEN_IERR_RESERVED0_BITS 6 7109 #define RG_RX_RX_GB_PRBS_GEN_IERR_RESERVED0_SHIFT 10 7110 7111 /* rg_rx :: rx_gb_prbs_gen_ierr :: prbs_ierr [09:00] */ 7112 #define RG_RX_RX_GB_PRBS_GEN_IERR_PRBS_IERR_MASK 0x03ff 7113 #define RG_RX_RX_GB_PRBS_GEN_IERR_PRBS_IERR_ALIGN 0 7114 #define RG_RX_RX_GB_PRBS_GEN_IERR_PRBS_IERR_BITS 10 7115 #define RG_RX_RX_GB_PRBS_GEN_IERR_PRBS_IERR_SHIFT 0 7116 7117 7118 /**************************************************************************** 7119 * rg_rx :: rx_gb_io_bit_ctrl 7120 */ 7121 /* rg_rx :: rx_gb_io_bit_ctrl :: reserved0 [15:13] */ 7122 #define RG_RX_RX_GB_IO_BIT_CTRL_RESERVED0_MASK 0xe000 7123 #define RG_RX_RX_GB_IO_BIT_CTRL_RESERVED0_ALIGN 0 7124 #define RG_RX_RX_GB_IO_BIT_CTRL_RESERVED0_BITS 3 7125 #define RG_RX_RX_GB_IO_BIT_CTRL_RESERVED0_SHIFT 13 7126 7127 /* rg_rx :: rx_gb_io_bit_ctrl :: srx_rev_en [12:12] */ 7128 #define RG_RX_RX_GB_IO_BIT_CTRL_SRX_REV_EN_MASK 0x1000 7129 #define RG_RX_RX_GB_IO_BIT_CTRL_SRX_REV_EN_ALIGN 0 7130 #define RG_RX_RX_GB_IO_BIT_CTRL_SRX_REV_EN_BITS 1 7131 #define RG_RX_RX_GB_IO_BIT_CTRL_SRX_REV_EN_SHIFT 12 7132 7133 /* rg_rx :: rx_gb_io_bit_ctrl :: lrx_ds_rev_en [11:11] */ 7134 #define RG_RX_RX_GB_IO_BIT_CTRL_LRX_DS_REV_EN_MASK 0x0800 7135 #define RG_RX_RX_GB_IO_BIT_CTRL_LRX_DS_REV_EN_ALIGN 0 7136 #define RG_RX_RX_GB_IO_BIT_CTRL_LRX_DS_REV_EN_BITS 1 7137 #define RG_RX_RX_GB_IO_BIT_CTRL_LRX_DS_REV_EN_SHIFT 11 7138 7139 /* rg_rx :: rx_gb_io_bit_ctrl :: lrx_10g_rev_en [10:10] */ 7140 #define RG_RX_RX_GB_IO_BIT_CTRL_LRX_10G_REV_EN_MASK 0x0400 7141 #define RG_RX_RX_GB_IO_BIT_CTRL_LRX_10G_REV_EN_ALIGN 0 7142 #define RG_RX_RX_GB_IO_BIT_CTRL_LRX_10G_REV_EN_BITS 1 7143 #define RG_RX_RX_GB_IO_BIT_CTRL_LRX_10G_REV_EN_SHIFT 10 7144 7145 /* rg_rx :: rx_gb_io_bit_ctrl :: output_invert [09:00] */ 7146 #define RG_RX_RX_GB_IO_BIT_CTRL_OUTPUT_INVERT_MASK 0x03ff 7147 #define RG_RX_RX_GB_IO_BIT_CTRL_OUTPUT_INVERT_ALIGN 0 7148 #define RG_RX_RX_GB_IO_BIT_CTRL_OUTPUT_INVERT_BITS 10 7149 #define RG_RX_RX_GB_IO_BIT_CTRL_OUTPUT_INVERT_SHIFT 0 7150 7151 7152 /**************************************************************************** 7153 * rg_rx :: rx_gb_caui_clk_sel 7154 */ 7155 /* rg_rx :: rx_gb_caui_clk_sel :: caui_clk_sel [15:15] */ 7156 #define RG_RX_RX_GB_CAUI_CLK_SEL_CAUI_CLK_SEL_MASK 0x8000 7157 #define RG_RX_RX_GB_CAUI_CLK_SEL_CAUI_CLK_SEL_ALIGN 0 7158 #define RG_RX_RX_GB_CAUI_CLK_SEL_CAUI_CLK_SEL_BITS 1 7159 #define RG_RX_RX_GB_CAUI_CLK_SEL_CAUI_CLK_SEL_SHIFT 15 7160 7161 /* rg_rx :: rx_gb_caui_clk_sel :: logic_lane_test [14:14] */ 7162 #define RG_RX_RX_GB_CAUI_CLK_SEL_LOGIC_LANE_TEST_MASK 0x4000 7163 #define RG_RX_RX_GB_CAUI_CLK_SEL_LOGIC_LANE_TEST_ALIGN 0 7164 #define RG_RX_RX_GB_CAUI_CLK_SEL_LOGIC_LANE_TEST_BITS 1 7165 #define RG_RX_RX_GB_CAUI_CLK_SEL_LOGIC_LANE_TEST_SHIFT 14 7166 7167 /* rg_rx :: rx_gb_caui_clk_sel :: gen_next_lane [13:04] */ 7168 #define RG_RX_RX_GB_CAUI_CLK_SEL_GEN_NEXT_LANE_MASK 0x3ff0 7169 #define RG_RX_RX_GB_CAUI_CLK_SEL_GEN_NEXT_LANE_ALIGN 0 7170 #define RG_RX_RX_GB_CAUI_CLK_SEL_GEN_NEXT_LANE_BITS 10 7171 #define RG_RX_RX_GB_CAUI_CLK_SEL_GEN_NEXT_LANE_SHIFT 4 7172 7173 /* rg_rx :: rx_gb_caui_clk_sel :: check_next_lane [03:00] */ 7174 #define RG_RX_RX_GB_CAUI_CLK_SEL_CHECK_NEXT_LANE_MASK 0x000f 7175 #define RG_RX_RX_GB_CAUI_CLK_SEL_CHECK_NEXT_LANE_ALIGN 0 7176 #define RG_RX_RX_GB_CAUI_CLK_SEL_CHECK_NEXT_LANE_BITS 4 7177 #define RG_RX_RX_GB_CAUI_CLK_SEL_CHECK_NEXT_LANE_SHIFT 0 7178 7179 7180 /**************************************************************************** 7181 * rg_rx :: rx_gb_ber_mntr_status 7182 */ 7183 /* rg_rx :: rx_gb_ber_mntr_status :: reserved0 [15:08] */ 7184 #define RG_RX_RX_GB_BER_MNTR_STATUS_RESERVED0_MASK 0xff00 7185 #define RG_RX_RX_GB_BER_MNTR_STATUS_RESERVED0_ALIGN 0 7186 #define RG_RX_RX_GB_BER_MNTR_STATUS_RESERVED0_BITS 8 7187 #define RG_RX_RX_GB_BER_MNTR_STATUS_RESERVED0_SHIFT 8 7188 7189 /* rg_rx :: rx_gb_ber_mntr_status :: ber_mntr_done [07:04] */ 7190 #define RG_RX_RX_GB_BER_MNTR_STATUS_BER_MNTR_DONE_MASK 0x00f0 7191 #define RG_RX_RX_GB_BER_MNTR_STATUS_BER_MNTR_DONE_ALIGN 0 7192 #define RG_RX_RX_GB_BER_MNTR_STATUS_BER_MNTR_DONE_BITS 4 7193 #define RG_RX_RX_GB_BER_MNTR_STATUS_BER_MNTR_DONE_SHIFT 4 7194 7195 /* rg_rx :: rx_gb_ber_mntr_status :: waiting_for_lock [03:00] */ 7196 #define RG_RX_RX_GB_BER_MNTR_STATUS_WAITING_FOR_LOCK_MASK 0x000f 7197 #define RG_RX_RX_GB_BER_MNTR_STATUS_WAITING_FOR_LOCK_ALIGN 0 7198 #define RG_RX_RX_GB_BER_MNTR_STATUS_WAITING_FOR_LOCK_BITS 4 7199 #define RG_RX_RX_GB_BER_MNTR_STATUS_WAITING_FOR_LOCK_SHIFT 0 7200 7201 7202 /**************************************************************************** 7203 * rg_rx :: rx_gb_prbs_pattern_present 7204 */ 7205 /* rg_rx :: rx_gb_prbs_pattern_present :: reserved0 [15:10] */ 7206 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT_RESERVED0_MASK 0xfc00 7207 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT_RESERVED0_ALIGN 0 7208 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT_RESERVED0_BITS 6 7209 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT_RESERVED0_SHIFT 10 7210 7211 /* rg_rx :: rx_gb_prbs_pattern_present :: pattern_present [09:00] */ 7212 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT_PATTERN_PRESENT_MASK 0x03ff 7213 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT_PATTERN_PRESENT_ALIGN 0 7214 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT_PATTERN_PRESENT_BITS 10 7215 #define RG_RX_RX_GB_PRBS_PATTERN_PRESENT_PATTERN_PRESENT_SHIFT 0 7216 7217 7218 /**************************************************************************** 7219 * rg_rx :: rx_gb_prbs_lock 7220 */ 7221 /* rg_rx :: rx_gb_prbs_lock :: reserved0 [15:10] */ 7222 #define RG_RX_RX_GB_PRBS_LOCK_RESERVED0_MASK 0xfc00 7223 #define RG_RX_RX_GB_PRBS_LOCK_RESERVED0_ALIGN 0 7224 #define RG_RX_RX_GB_PRBS_LOCK_RESERVED0_BITS 6 7225 #define RG_RX_RX_GB_PRBS_LOCK_RESERVED0_SHIFT 10 7226 7227 /* rg_rx :: rx_gb_prbs_lock :: prbs_lock [09:00] */ 7228 #define RG_RX_RX_GB_PRBS_LOCK_PRBS_LOCK_MASK 0x03ff 7229 #define RG_RX_RX_GB_PRBS_LOCK_PRBS_LOCK_ALIGN 0 7230 #define RG_RX_RX_GB_PRBS_LOCK_PRBS_LOCK_BITS 10 7231 #define RG_RX_RX_GB_PRBS_LOCK_PRBS_LOCK_SHIFT 0 7232 7233 7234 /**************************************************************************** 7235 * rg_rx :: rx_gb_prbs_lock_ll 7236 */ 7237 /* rg_rx :: rx_gb_prbs_lock_ll :: reserved0 [15:10] */ 7238 #define RG_RX_RX_GB_PRBS_LOCK_LL_RESERVED0_MASK 0xfc00 7239 #define RG_RX_RX_GB_PRBS_LOCK_LL_RESERVED0_ALIGN 0 7240 #define RG_RX_RX_GB_PRBS_LOCK_LL_RESERVED0_BITS 6 7241 #define RG_RX_RX_GB_PRBS_LOCK_LL_RESERVED0_SHIFT 10 7242 7243 /* rg_rx :: rx_gb_prbs_lock_ll :: prbs_lock_ll [09:00] */ 7244 #define RG_RX_RX_GB_PRBS_LOCK_LL_PRBS_LOCK_LL_MASK 0x03ff 7245 #define RG_RX_RX_GB_PRBS_LOCK_LL_PRBS_LOCK_LL_ALIGN 0 7246 #define RG_RX_RX_GB_PRBS_LOCK_LL_PRBS_LOCK_LL_BITS 10 7247 #define RG_RX_RX_GB_PRBS_LOCK_LL_PRBS_LOCK_LL_SHIFT 0 7248 7249 7250 /**************************************************************************** 7251 * rg_rx :: rx_gb_prbs_status_out 7252 */ 7253 /* rg_rx :: rx_gb_prbs_status_out :: prbs_inv_out [15:12] */ 7254 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_INV_OUT_MASK 0xf000 7255 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_INV_OUT_ALIGN 0 7256 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_INV_OUT_BITS 4 7257 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_INV_OUT_SHIFT 12 7258 7259 /* rg_rx :: rx_gb_prbs_status_out :: prbs_sel_out3 [11:09] */ 7260 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT3_MASK 0x0e00 7261 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT3_ALIGN 0 7262 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT3_BITS 3 7263 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT3_SHIFT 9 7264 7265 /* rg_rx :: rx_gb_prbs_status_out :: prbs_sel_out2 [08:06] */ 7266 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT2_MASK 0x01c0 7267 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT2_ALIGN 0 7268 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT2_BITS 3 7269 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT2_SHIFT 6 7270 7271 /* rg_rx :: rx_gb_prbs_status_out :: prbs_sel_out1 [05:03] */ 7272 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT1_MASK 0x0038 7273 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT1_ALIGN 0 7274 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT1_BITS 3 7275 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT1_SHIFT 3 7276 7277 /* rg_rx :: rx_gb_prbs_status_out :: prbs_sel_out0 [02:00] */ 7278 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT0_MASK 0x0007 7279 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT0_ALIGN 0 7280 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT0_BITS 3 7281 #define RG_RX_RX_GB_PRBS_STATUS_OUT_PRBS_SEL_OUT0_SHIFT 0 7282 7283 7284 /**************************************************************************** 7285 * rg_rx :: rx_gb_lsb_err_cnt 7286 */ 7287 /* rg_rx :: rx_gb_lsb_err_cnt :: lsb_err_cnt [15:00] */ 7288 #define RG_RX_RX_GB_LSB_ERR_CNT_LSB_ERR_CNT_MASK 0xffff 7289 #define RG_RX_RX_GB_LSB_ERR_CNT_LSB_ERR_CNT_ALIGN 0 7290 #define RG_RX_RX_GB_LSB_ERR_CNT_LSB_ERR_CNT_BITS 16 7291 #define RG_RX_RX_GB_LSB_ERR_CNT_LSB_ERR_CNT_SHIFT 0 7292 7293 7294 /**************************************************************************** 7295 * rg_rx :: rx_gb_msb_err_cnt 7296 */ 7297 /* rg_rx :: rx_gb_msb_err_cnt :: msb_err_cnt [15:00] */ 7298 #define RG_RX_RX_GB_MSB_ERR_CNT_MSB_ERR_CNT_MASK 0xffff 7299 #define RG_RX_RX_GB_MSB_ERR_CNT_MSB_ERR_CNT_ALIGN 0 7300 #define RG_RX_RX_GB_MSB_ERR_CNT_MSB_ERR_CNT_BITS 16 7301 #define RG_RX_RX_GB_MSB_ERR_CNT_MSB_ERR_CNT_SHIFT 0 7302 7303 7304 /**************************************************************************** 7305 * rg_rx :: rx_gb_collide_lpbk 7306 */ 7307 /* rg_rx :: rx_gb_collide_lpbk :: reserved0 [15:10] */ 7308 #define RG_RX_RX_GB_COLLIDE_LPBK_RESERVED0_MASK 0xfc00 7309 #define RG_RX_RX_GB_COLLIDE_LPBK_RESERVED0_ALIGN 0 7310 #define RG_RX_RX_GB_COLLIDE_LPBK_RESERVED0_BITS 6 7311 #define RG_RX_RX_GB_COLLIDE_LPBK_RESERVED0_SHIFT 10 7312 7313 /* rg_rx :: rx_gb_collide_lpbk :: collide_lpbk [09:00] */ 7314 #define RG_RX_RX_GB_COLLIDE_LPBK_COLLIDE_LPBK_MASK 0x03ff 7315 #define RG_RX_RX_GB_COLLIDE_LPBK_COLLIDE_LPBK_ALIGN 0 7316 #define RG_RX_RX_GB_COLLIDE_LPBK_COLLIDE_LPBK_BITS 10 7317 #define RG_RX_RX_GB_COLLIDE_LPBK_COLLIDE_LPBK_SHIFT 0 7318 7319 7320 /**************************************************************************** 7321 * rg_rx :: rx_gb_collide_lpbk_lh 7322 */ 7323 /* rg_rx :: rx_gb_collide_lpbk_lh :: reserved0 [15:10] */ 7324 #define RG_RX_RX_GB_COLLIDE_LPBK_LH_RESERVED0_MASK 0xfc00 7325 #define RG_RX_RX_GB_COLLIDE_LPBK_LH_RESERVED0_ALIGN 0 7326 #define RG_RX_RX_GB_COLLIDE_LPBK_LH_RESERVED0_BITS 6 7327 #define RG_RX_RX_GB_COLLIDE_LPBK_LH_RESERVED0_SHIFT 10 7328 7329 /* rg_rx :: rx_gb_collide_lpbk_lh :: collide_lpbk_lh [09:00] */ 7330 #define RG_RX_RX_GB_COLLIDE_LPBK_LH_COLLIDE_LPBK_LH_MASK 0x03ff 7331 #define RG_RX_RX_GB_COLLIDE_LPBK_LH_COLLIDE_LPBK_LH_ALIGN 0 7332 #define RG_RX_RX_GB_COLLIDE_LPBK_LH_COLLIDE_LPBK_LH_BITS 10 7333 #define RG_RX_RX_GB_COLLIDE_LPBK_LH_COLLIDE_LPBK_LH_SHIFT 0 7334 7335 7336 /**************************************************************************** 7337 * rg_rx :: rx_gb_collide 7338 */ 7339 /* rg_rx :: rx_gb_collide :: reserved0 [15:10] */ 7340 #define RG_RX_RX_GB_COLLIDE_RESERVED0_MASK 0xfc00 7341 #define RG_RX_RX_GB_COLLIDE_RESERVED0_ALIGN 0 7342 #define RG_RX_RX_GB_COLLIDE_RESERVED0_BITS 6 7343 #define RG_RX_RX_GB_COLLIDE_RESERVED0_SHIFT 10 7344 7345 /* rg_rx :: rx_gb_collide :: collide [09:00] */ 7346 #define RG_RX_RX_GB_COLLIDE_COLLIDE_MASK 0x03ff 7347 #define RG_RX_RX_GB_COLLIDE_COLLIDE_ALIGN 0 7348 #define RG_RX_RX_GB_COLLIDE_COLLIDE_BITS 10 7349 #define RG_RX_RX_GB_COLLIDE_COLLIDE_SHIFT 0 7350 7351 7352 /**************************************************************************** 7353 * rg_rx :: rx_gb_collide_lh 7354 */ 7355 /* rg_rx :: rx_gb_collide_lh :: reserved0 [15:10] */ 7356 #define RG_RX_RX_GB_COLLIDE_LH_RESERVED0_MASK 0xfc00 7357 #define RG_RX_RX_GB_COLLIDE_LH_RESERVED0_ALIGN 0 7358 #define RG_RX_RX_GB_COLLIDE_LH_RESERVED0_BITS 6 7359 #define RG_RX_RX_GB_COLLIDE_LH_RESERVED0_SHIFT 10 7360 7361 /* rg_rx :: rx_gb_collide_lh :: collide_lh [09:00] */ 7362 #define RG_RX_RX_GB_COLLIDE_LH_COLLIDE_LH_MASK 0x03ff 7363 #define RG_RX_RX_GB_COLLIDE_LH_COLLIDE_LH_ALIGN 0 7364 #define RG_RX_RX_GB_COLLIDE_LH_COLLIDE_LH_BITS 10 7365 #define RG_RX_RX_GB_COLLIDE_LH_COLLIDE_LH_SHIFT 0 7366 7367 7368 /**************************************************************************** 7369 * rg_rx :: rx_gb_err_data_0 7370 */ 7371 /* rg_rx :: rx_gb_err_data_0 :: err_data_0 [15:00] */ 7372 #define RG_RX_RX_GB_ERR_DATA_0_ERR_DATA_0_MASK 0xffff 7373 #define RG_RX_RX_GB_ERR_DATA_0_ERR_DATA_0_ALIGN 0 7374 #define RG_RX_RX_GB_ERR_DATA_0_ERR_DATA_0_BITS 16 7375 #define RG_RX_RX_GB_ERR_DATA_0_ERR_DATA_0_SHIFT 0 7376 7377 7378 /**************************************************************************** 7379 * rg_rx :: rx_gb_err_data_1 7380 */ 7381 /* rg_rx :: rx_gb_err_data_1 :: err_data_1 [15:00] */ 7382 #define RG_RX_RX_GB_ERR_DATA_1_ERR_DATA_1_MASK 0xffff 7383 #define RG_RX_RX_GB_ERR_DATA_1_ERR_DATA_1_ALIGN 0 7384 #define RG_RX_RX_GB_ERR_DATA_1_ERR_DATA_1_BITS 16 7385 #define RG_RX_RX_GB_ERR_DATA_1_ERR_DATA_1_SHIFT 0 7386 7387 7388 /**************************************************************************** 7389 * rg_rx :: rx_gb_err_data_2 7390 */ 7391 /* rg_rx :: rx_gb_err_data_2 :: err_data_2 [15:00] */ 7392 #define RG_RX_RX_GB_ERR_DATA_2_ERR_DATA_2_MASK 0xffff 7393 #define RG_RX_RX_GB_ERR_DATA_2_ERR_DATA_2_ALIGN 0 7394 #define RG_RX_RX_GB_ERR_DATA_2_ERR_DATA_2_BITS 16 7395 #define RG_RX_RX_GB_ERR_DATA_2_ERR_DATA_2_SHIFT 0 7396 7397 7398 /**************************************************************************** 7399 * rg_rx :: rx_gb_err_data_3 7400 */ 7401 /* rg_rx :: rx_gb_err_data_3 :: err_data_3 [15:00] */ 7402 #define RG_RX_RX_GB_ERR_DATA_3_ERR_DATA_3_MASK 0xffff 7403 #define RG_RX_RX_GB_ERR_DATA_3_ERR_DATA_3_ALIGN 0 7404 #define RG_RX_RX_GB_ERR_DATA_3_ERR_DATA_3_BITS 16 7405 #define RG_RX_RX_GB_ERR_DATA_3_ERR_DATA_3_SHIFT 0 7406 7407 7408 /**************************************************************************** 7409 * rg_rx :: rx_gb_err_data_4 7410 */ 7411 /* rg_rx :: rx_gb_err_data_4 :: err_data_4 [15:00] */ 7412 #define RG_RX_RX_GB_ERR_DATA_4_ERR_DATA_4_MASK 0xffff 7413 #define RG_RX_RX_GB_ERR_DATA_4_ERR_DATA_4_ALIGN 0 7414 #define RG_RX_RX_GB_ERR_DATA_4_ERR_DATA_4_BITS 16 7415 #define RG_RX_RX_GB_ERR_DATA_4_ERR_DATA_4_SHIFT 0 7416 7417 7418 /**************************************************************************** 7419 * rg_rx :: rx_gb_err_data_5 7420 */ 7421 /* rg_rx :: rx_gb_err_data_5 :: err_data_5 [15:00] */ 7422 #define RG_RX_RX_GB_ERR_DATA_5_ERR_DATA_5_MASK 0xffff 7423 #define RG_RX_RX_GB_ERR_DATA_5_ERR_DATA_5_ALIGN 0 7424 #define RG_RX_RX_GB_ERR_DATA_5_ERR_DATA_5_BITS 16 7425 #define RG_RX_RX_GB_ERR_DATA_5_ERR_DATA_5_SHIFT 0 7426 7427 7428 /**************************************************************************** 7429 * rg_rx :: rx_gb_err_data_6 7430 */ 7431 /* rg_rx :: rx_gb_err_data_6 :: err_data_6 [15:00] */ 7432 #define RG_RX_RX_GB_ERR_DATA_6_ERR_DATA_6_MASK 0xffff 7433 #define RG_RX_RX_GB_ERR_DATA_6_ERR_DATA_6_ALIGN 0 7434 #define RG_RX_RX_GB_ERR_DATA_6_ERR_DATA_6_BITS 16 7435 #define RG_RX_RX_GB_ERR_DATA_6_ERR_DATA_6_SHIFT 0 7436 7437 7438 /**************************************************************************** 7439 * rg_rx :: rx_gb_err_data_7 7440 */ 7441 /* rg_rx :: rx_gb_err_data_7 :: err_data_7 [15:00] */ 7442 #define RG_RX_RX_GB_ERR_DATA_7_ERR_DATA_7_MASK 0xffff 7443 #define RG_RX_RX_GB_ERR_DATA_7_ERR_DATA_7_ALIGN 0 7444 #define RG_RX_RX_GB_ERR_DATA_7_ERR_DATA_7_BITS 16 7445 #define RG_RX_RX_GB_ERR_DATA_7_ERR_DATA_7_SHIFT 0 7446 7447 7448 /**************************************************************************** 7449 * rg_rx :: rx_gb_err_data_8 7450 */ 7451 /* rg_rx :: rx_gb_err_data_8 :: err_data_8 [15:00] */ 7452 #define RG_RX_RX_GB_ERR_DATA_8_ERR_DATA_8_MASK 0xffff 7453 #define RG_RX_RX_GB_ERR_DATA_8_ERR_DATA_8_ALIGN 0 7454 #define RG_RX_RX_GB_ERR_DATA_8_ERR_DATA_8_BITS 16 7455 #define RG_RX_RX_GB_ERR_DATA_8_ERR_DATA_8_SHIFT 0 7456 7457 7458 /**************************************************************************** 7459 * rg_tx_regs 7460 */ 7461 /**************************************************************************** 7462 * rg_tx :: tx_gb_system_reset 7463 */ 7464 /* rg_tx :: tx_gb_system_reset :: reserved0 [15:10] */ 7465 #define RG_TX_TX_GB_SYSTEM_RESET_RESERVED0_MASK 0xfc00 7466 #define RG_TX_TX_GB_SYSTEM_RESET_RESERVED0_ALIGN 0 7467 #define RG_TX_TX_GB_SYSTEM_RESET_RESERVED0_BITS 6 7468 #define RG_TX_TX_GB_SYSTEM_RESET_RESERVED0_SHIFT 10 7469 7470 /* rg_tx :: tx_gb_system_reset :: stx_rstb [09:00] */ 7471 #define RG_TX_TX_GB_SYSTEM_RESET_STX_RSTB_MASK 0x03ff 7472 #define RG_TX_TX_GB_SYSTEM_RESET_STX_RSTB_ALIGN 0 7473 #define RG_TX_TX_GB_SYSTEM_RESET_STX_RSTB_BITS 10 7474 #define RG_TX_TX_GB_SYSTEM_RESET_STX_RSTB_SHIFT 0 7475 7476 7477 /**************************************************************************** 7478 * rg_tx :: tx_gb_system_reset_frc 7479 */ 7480 /* rg_tx :: tx_gb_system_reset_frc :: reserved0 [15:10] */ 7481 #define RG_TX_TX_GB_SYSTEM_RESET_FRC_RESERVED0_MASK 0xfc00 7482 #define RG_TX_TX_GB_SYSTEM_RESET_FRC_RESERVED0_ALIGN 0 7483 #define RG_TX_TX_GB_SYSTEM_RESET_FRC_RESERVED0_BITS 6 7484 #define RG_TX_TX_GB_SYSTEM_RESET_FRC_RESERVED0_SHIFT 10 7485 7486 /* rg_tx :: tx_gb_system_reset_frc :: stx_rstb_frc [09:00] */ 7487 #define RG_TX_TX_GB_SYSTEM_RESET_FRC_STX_RSTB_FRC_MASK 0x03ff 7488 #define RG_TX_TX_GB_SYSTEM_RESET_FRC_STX_RSTB_FRC_ALIGN 0 7489 #define RG_TX_TX_GB_SYSTEM_RESET_FRC_STX_RSTB_FRC_BITS 10 7490 #define RG_TX_TX_GB_SYSTEM_RESET_FRC_STX_RSTB_FRC_SHIFT 0 7491 7492 7493 /**************************************************************************** 7494 * rg_tx :: tx_gb_line_reset 7495 */ 7496 /* rg_tx :: tx_gb_line_reset :: reserved0 [15:10] */ 7497 #define RG_TX_TX_GB_LINE_RESET_RESERVED0_MASK 0xfc00 7498 #define RG_TX_TX_GB_LINE_RESET_RESERVED0_ALIGN 0 7499 #define RG_TX_TX_GB_LINE_RESET_RESERVED0_BITS 6 7500 #define RG_TX_TX_GB_LINE_RESET_RESERVED0_SHIFT 10 7501 7502 /* rg_tx :: tx_gb_line_reset :: ltx_rstb [09:00] */ 7503 #define RG_TX_TX_GB_LINE_RESET_LTX_RSTB_MASK 0x03ff 7504 #define RG_TX_TX_GB_LINE_RESET_LTX_RSTB_ALIGN 0 7505 #define RG_TX_TX_GB_LINE_RESET_LTX_RSTB_BITS 10 7506 #define RG_TX_TX_GB_LINE_RESET_LTX_RSTB_SHIFT 0 7507 7508 7509 /**************************************************************************** 7510 * rg_tx :: tx_gb_line_reset_frc 7511 */ 7512 /* rg_tx :: tx_gb_line_reset_frc :: reserved0 [15:10] */ 7513 #define RG_TX_TX_GB_LINE_RESET_FRC_RESERVED0_MASK 0xfc00 7514 #define RG_TX_TX_GB_LINE_RESET_FRC_RESERVED0_ALIGN 0 7515 #define RG_TX_TX_GB_LINE_RESET_FRC_RESERVED0_BITS 6 7516 #define RG_TX_TX_GB_LINE_RESET_FRC_RESERVED0_SHIFT 10 7517 7518 /* rg_tx :: tx_gb_line_reset_frc :: ltx_rstb_frc [09:00] */ 7519 #define RG_TX_TX_GB_LINE_RESET_FRC_LTX_RSTB_FRC_MASK 0x03ff 7520 #define RG_TX_TX_GB_LINE_RESET_FRC_LTX_RSTB_FRC_ALIGN 0 7521 #define RG_TX_TX_GB_LINE_RESET_FRC_LTX_RSTB_FRC_BITS 10 7522 #define RG_TX_TX_GB_LINE_RESET_FRC_LTX_RSTB_FRC_SHIFT 0 7523 7524 7525 /**************************************************************************** 7526 * rg_tx :: tx_gb_prbs_db_ctrl 7527 */ 7528 /* rg_tx :: tx_gb_prbs_db_ctrl :: reserved0 [15:14] */ 7529 #define RG_TX_TX_GB_PRBS_DB_CTRL_RESERVED0_MASK 0xc000 7530 #define RG_TX_TX_GB_PRBS_DB_CTRL_RESERVED0_ALIGN 0 7531 #define RG_TX_TX_GB_PRBS_DB_CTRL_RESERVED0_BITS 2 7532 #define RG_TX_TX_GB_PRBS_DB_CTRL_RESERVED0_SHIFT 14 7533 7534 /* rg_tx :: tx_gb_prbs_db_ctrl :: ieee_prbs_inv [13:13] */ 7535 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_PRBS_INV_MASK 0x2000 7536 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_PRBS_INV_ALIGN 0 7537 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_PRBS_INV_BITS 1 7538 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_PRBS_INV_SHIFT 13 7539 7540 /* rg_tx :: tx_gb_prbs_db_ctrl :: ieee_cnt_div3 [12:12] */ 7541 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_CNT_DIV3_MASK 0x1000 7542 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_CNT_DIV3_ALIGN 0 7543 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_CNT_DIV3_BITS 1 7544 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_CNT_DIV3_SHIFT 12 7545 7546 /* rg_tx :: tx_gb_prbs_db_ctrl :: ieee_mode [11:08] */ 7547 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_MODE_MASK 0x0f00 7548 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_MODE_ALIGN 0 7549 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_MODE_BITS 4 7550 #define RG_TX_TX_GB_PRBS_DB_CTRL_IEEE_MODE_SHIFT 8 7551 7552 /* rg_tx :: tx_gb_prbs_db_ctrl :: prbs_gen_en [07:04] */ 7553 #define RG_TX_TX_GB_PRBS_DB_CTRL_PRBS_GEN_EN_MASK 0x00f0 7554 #define RG_TX_TX_GB_PRBS_DB_CTRL_PRBS_GEN_EN_ALIGN 0 7555 #define RG_TX_TX_GB_PRBS_DB_CTRL_PRBS_GEN_EN_BITS 4 7556 #define RG_TX_TX_GB_PRBS_DB_CTRL_PRBS_GEN_EN_SHIFT 4 7557 7558 /* rg_tx :: tx_gb_prbs_db_ctrl :: db_bypass [03:00] */ 7559 #define RG_TX_TX_GB_PRBS_DB_CTRL_DB_BYPASS_MASK 0x000f 7560 #define RG_TX_TX_GB_PRBS_DB_CTRL_DB_BYPASS_ALIGN 0 7561 #define RG_TX_TX_GB_PRBS_DB_CTRL_DB_BYPASS_BITS 4 7562 #define RG_TX_TX_GB_PRBS_DB_CTRL_DB_BYPASS_SHIFT 0 7563 7564 7565 /**************************************************************************** 7566 * rg_tx :: tx_gb_test_ierr 7567 */ 7568 /* rg_tx :: tx_gb_test_ierr :: reserved0 [15:10] */ 7569 #define RG_TX_TX_GB_TEST_IERR_RESERVED0_MASK 0xfc00 7570 #define RG_TX_TX_GB_TEST_IERR_RESERVED0_ALIGN 0 7571 #define RG_TX_TX_GB_TEST_IERR_RESERVED0_BITS 6 7572 #define RG_TX_TX_GB_TEST_IERR_RESERVED0_SHIFT 10 7573 7574 /* rg_tx :: tx_gb_test_ierr :: prbs_ierr [09:00] */ 7575 #define RG_TX_TX_GB_TEST_IERR_PRBS_IERR_MASK 0x03ff 7576 #define RG_TX_TX_GB_TEST_IERR_PRBS_IERR_ALIGN 0 7577 #define RG_TX_TX_GB_TEST_IERR_PRBS_IERR_BITS 10 7578 #define RG_TX_TX_GB_TEST_IERR_PRBS_IERR_SHIFT 0 7579 7580 7581 /**************************************************************************** 7582 * rg_tx :: tx_gb_test_gen_ctrl 7583 */ 7584 /* rg_tx :: tx_gb_test_gen_ctrl :: prbs_inv [15:12] */ 7585 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_INV_MASK 0xf000 7586 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_INV_ALIGN 0 7587 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_INV_BITS 4 7588 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_INV_SHIFT 12 7589 7590 /* rg_tx :: tx_gb_test_gen_ctrl :: prbs_sel3 [11:09] */ 7591 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL3_MASK 0x0e00 7592 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL3_ALIGN 0 7593 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL3_BITS 3 7594 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL3_SHIFT 9 7595 7596 /* rg_tx :: tx_gb_test_gen_ctrl :: prbs_sel2 [08:06] */ 7597 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL2_MASK 0x01c0 7598 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL2_ALIGN 0 7599 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL2_BITS 3 7600 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL2_SHIFT 6 7601 7602 /* rg_tx :: tx_gb_test_gen_ctrl :: prbs_sel1 [05:03] */ 7603 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL1_MASK 0x0038 7604 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL1_ALIGN 0 7605 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL1_BITS 3 7606 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL1_SHIFT 3 7607 7608 /* rg_tx :: tx_gb_test_gen_ctrl :: prbs_sel0 [02:00] */ 7609 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL0_MASK 0x0007 7610 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL0_ALIGN 0 7611 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL0_BITS 3 7612 #define RG_TX_TX_GB_TEST_GEN_CTRL_PRBS_SEL0_SHIFT 0 7613 7614 7615 /**************************************************************************** 7616 * rg_tx :: tx_gb_pattern0_0 7617 */ 7618 /* rg_tx :: tx_gb_pattern0_0 :: pattern0_0 [15:00] */ 7619 #define RG_TX_TX_GB_PATTERN0_0_PATTERN0_0_MASK 0xffff 7620 #define RG_TX_TX_GB_PATTERN0_0_PATTERN0_0_ALIGN 0 7621 #define RG_TX_TX_GB_PATTERN0_0_PATTERN0_0_BITS 16 7622 #define RG_TX_TX_GB_PATTERN0_0_PATTERN0_0_SHIFT 0 7623 7624 7625 /**************************************************************************** 7626 * rg_tx :: tx_gb_pattern0_1 7627 */ 7628 /* rg_tx :: tx_gb_pattern0_1 :: pattern0_1 [15:00] */ 7629 #define RG_TX_TX_GB_PATTERN0_1_PATTERN0_1_MASK 0xffff 7630 #define RG_TX_TX_GB_PATTERN0_1_PATTERN0_1_ALIGN 0 7631 #define RG_TX_TX_GB_PATTERN0_1_PATTERN0_1_BITS 16 7632 #define RG_TX_TX_GB_PATTERN0_1_PATTERN0_1_SHIFT 0 7633 7634 7635 /**************************************************************************** 7636 * rg_tx :: tx_gb_pattern0_2 7637 */ 7638 /* rg_tx :: tx_gb_pattern0_2 :: pattern0_2 [15:00] */ 7639 #define RG_TX_TX_GB_PATTERN0_2_PATTERN0_2_MASK 0xffff 7640 #define RG_TX_TX_GB_PATTERN0_2_PATTERN0_2_ALIGN 0 7641 #define RG_TX_TX_GB_PATTERN0_2_PATTERN0_2_BITS 16 7642 #define RG_TX_TX_GB_PATTERN0_2_PATTERN0_2_SHIFT 0 7643 7644 7645 /**************************************************************************** 7646 * rg_tx :: tx_gb_pattern0_3 7647 */ 7648 /* rg_tx :: tx_gb_pattern0_3 :: pattern0_3 [15:00] */ 7649 #define RG_TX_TX_GB_PATTERN0_3_PATTERN0_3_MASK 0xffff 7650 #define RG_TX_TX_GB_PATTERN0_3_PATTERN0_3_ALIGN 0 7651 #define RG_TX_TX_GB_PATTERN0_3_PATTERN0_3_BITS 16 7652 #define RG_TX_TX_GB_PATTERN0_3_PATTERN0_3_SHIFT 0 7653 7654 7655 /**************************************************************************** 7656 * rg_tx :: tx_gb_pattern0_4 7657 */ 7658 /* rg_tx :: tx_gb_pattern0_4 :: pattern0_4 [15:00] */ 7659 #define RG_TX_TX_GB_PATTERN0_4_PATTERN0_4_MASK 0xffff 7660 #define RG_TX_TX_GB_PATTERN0_4_PATTERN0_4_ALIGN 0 7661 #define RG_TX_TX_GB_PATTERN0_4_PATTERN0_4_BITS 16 7662 #define RG_TX_TX_GB_PATTERN0_4_PATTERN0_4_SHIFT 0 7663 7664 7665 /**************************************************************************** 7666 * rg_tx :: tx_gb_pattern0_5 7667 */ 7668 /* rg_tx :: tx_gb_pattern0_5 :: pattern0_5 [15:00] */ 7669 #define RG_TX_TX_GB_PATTERN0_5_PATTERN0_5_MASK 0xffff 7670 #define RG_TX_TX_GB_PATTERN0_5_PATTERN0_5_ALIGN 0 7671 #define RG_TX_TX_GB_PATTERN0_5_PATTERN0_5_BITS 16 7672 #define RG_TX_TX_GB_PATTERN0_5_PATTERN0_5_SHIFT 0 7673 7674 7675 /**************************************************************************** 7676 * rg_tx :: tx_gb_pattern0_6 7677 */ 7678 /* rg_tx :: tx_gb_pattern0_6 :: pattern0_6 [15:00] */ 7679 #define RG_TX_TX_GB_PATTERN0_6_PATTERN0_6_MASK 0xffff 7680 #define RG_TX_TX_GB_PATTERN0_6_PATTERN0_6_ALIGN 0 7681 #define RG_TX_TX_GB_PATTERN0_6_PATTERN0_6_BITS 16 7682 #define RG_TX_TX_GB_PATTERN0_6_PATTERN0_6_SHIFT 0 7683 7684 7685 /**************************************************************************** 7686 * rg_tx :: tx_gb_pattern0_7 7687 */ 7688 /* rg_tx :: tx_gb_pattern0_7 :: pattern0_7 [15:00] */ 7689 #define RG_TX_TX_GB_PATTERN0_7_PATTERN0_7_MASK 0xffff 7690 #define RG_TX_TX_GB_PATTERN0_7_PATTERN0_7_ALIGN 0 7691 #define RG_TX_TX_GB_PATTERN0_7_PATTERN0_7_BITS 16 7692 #define RG_TX_TX_GB_PATTERN0_7_PATTERN0_7_SHIFT 0 7693 7694 7695 /**************************************************************************** 7696 * rg_tx :: tx_gb_pattern1_0 7697 */ 7698 /* rg_tx :: tx_gb_pattern1_0 :: pattern1_0 [15:00] */ 7699 #define RG_TX_TX_GB_PATTERN1_0_PATTERN1_0_MASK 0xffff 7700 #define RG_TX_TX_GB_PATTERN1_0_PATTERN1_0_ALIGN 0 7701 #define RG_TX_TX_GB_PATTERN1_0_PATTERN1_0_BITS 16 7702 #define RG_TX_TX_GB_PATTERN1_0_PATTERN1_0_SHIFT 0 7703 7704 7705 /**************************************************************************** 7706 * rg_tx :: tx_gb_pattern1_1 7707 */ 7708 /* rg_tx :: tx_gb_pattern1_1 :: pattern1_1 [15:00] */ 7709 #define RG_TX_TX_GB_PATTERN1_1_PATTERN1_1_MASK 0xffff 7710 #define RG_TX_TX_GB_PATTERN1_1_PATTERN1_1_ALIGN 0 7711 #define RG_TX_TX_GB_PATTERN1_1_PATTERN1_1_BITS 16 7712 #define RG_TX_TX_GB_PATTERN1_1_PATTERN1_1_SHIFT 0 7713 7714 7715 /**************************************************************************** 7716 * rg_tx :: tx_gb_pattern1_2 7717 */ 7718 /* rg_tx :: tx_gb_pattern1_2 :: pattern1_2 [15:00] */ 7719 #define RG_TX_TX_GB_PATTERN1_2_PATTERN1_2_MASK 0xffff 7720 #define RG_TX_TX_GB_PATTERN1_2_PATTERN1_2_ALIGN 0 7721 #define RG_TX_TX_GB_PATTERN1_2_PATTERN1_2_BITS 16 7722 #define RG_TX_TX_GB_PATTERN1_2_PATTERN1_2_SHIFT 0 7723 7724 7725 /**************************************************************************** 7726 * rg_tx :: tx_gb_pattern1_3 7727 */ 7728 /* rg_tx :: tx_gb_pattern1_3 :: pattern1_3 [15:00] */ 7729 #define RG_TX_TX_GB_PATTERN1_3_PATTERN1_3_MASK 0xffff 7730 #define RG_TX_TX_GB_PATTERN1_3_PATTERN1_3_ALIGN 0 7731 #define RG_TX_TX_GB_PATTERN1_3_PATTERN1_3_BITS 16 7732 #define RG_TX_TX_GB_PATTERN1_3_PATTERN1_3_SHIFT 0 7733 7734 7735 /**************************************************************************** 7736 * rg_tx :: tx_gb_pattern1_4 7737 */ 7738 /* rg_tx :: tx_gb_pattern1_4 :: pattern1_4 [15:00] */ 7739 #define RG_TX_TX_GB_PATTERN1_4_PATTERN1_4_MASK 0xffff 7740 #define RG_TX_TX_GB_PATTERN1_4_PATTERN1_4_ALIGN 0 7741 #define RG_TX_TX_GB_PATTERN1_4_PATTERN1_4_BITS 16 7742 #define RG_TX_TX_GB_PATTERN1_4_PATTERN1_4_SHIFT 0 7743 7744 7745 /**************************************************************************** 7746 * rg_tx :: tx_gb_pattern1_5 7747 */ 7748 /* rg_tx :: tx_gb_pattern1_5 :: pattern1_5 [15:00] */ 7749 #define RG_TX_TX_GB_PATTERN1_5_PATTERN1_5_MASK 0xffff 7750 #define RG_TX_TX_GB_PATTERN1_5_PATTERN1_5_ALIGN 0 7751 #define RG_TX_TX_GB_PATTERN1_5_PATTERN1_5_BITS 16 7752 #define RG_TX_TX_GB_PATTERN1_5_PATTERN1_5_SHIFT 0 7753 7754 7755 /**************************************************************************** 7756 * rg_tx :: tx_gb_pattern1_6 7757 */ 7758 /* rg_tx :: tx_gb_pattern1_6 :: pattern1_6 [15:00] */ 7759 #define RG_TX_TX_GB_PATTERN1_6_PATTERN1_6_MASK 0xffff 7760 #define RG_TX_TX_GB_PATTERN1_6_PATTERN1_6_ALIGN 0 7761 #define RG_TX_TX_GB_PATTERN1_6_PATTERN1_6_BITS 16 7762 #define RG_TX_TX_GB_PATTERN1_6_PATTERN1_6_SHIFT 0 7763 7764 7765 /**************************************************************************** 7766 * rg_tx :: tx_gb_pattern1_7 7767 */ 7768 /* rg_tx :: tx_gb_pattern1_7 :: pattern1_7 [15:00] */ 7769 #define RG_TX_TX_GB_PATTERN1_7_PATTERN1_7_MASK 0xffff 7770 #define RG_TX_TX_GB_PATTERN1_7_PATTERN1_7_ALIGN 0 7771 #define RG_TX_TX_GB_PATTERN1_7_PATTERN1_7_BITS 16 7772 #define RG_TX_TX_GB_PATTERN1_7_PATTERN1_7_SHIFT 0 7773 7774 7775 /**************************************************************************** 7776 * rg_tx :: tx_gb_pattern2_0 7777 */ 7778 /* rg_tx :: tx_gb_pattern2_0 :: pattern2_0 [15:00] */ 7779 #define RG_TX_TX_GB_PATTERN2_0_PATTERN2_0_MASK 0xffff 7780 #define RG_TX_TX_GB_PATTERN2_0_PATTERN2_0_ALIGN 0 7781 #define RG_TX_TX_GB_PATTERN2_0_PATTERN2_0_BITS 16 7782 #define RG_TX_TX_GB_PATTERN2_0_PATTERN2_0_SHIFT 0 7783 7784 7785 /**************************************************************************** 7786 * rg_tx :: tx_gb_pattern2_1 7787 */ 7788 /* rg_tx :: tx_gb_pattern2_1 :: pattern2_1 [15:00] */ 7789 #define RG_TX_TX_GB_PATTERN2_1_PATTERN2_1_MASK 0xffff 7790 #define RG_TX_TX_GB_PATTERN2_1_PATTERN2_1_ALIGN 0 7791 #define RG_TX_TX_GB_PATTERN2_1_PATTERN2_1_BITS 16 7792 #define RG_TX_TX_GB_PATTERN2_1_PATTERN2_1_SHIFT 0 7793 7794 7795 /**************************************************************************** 7796 * rg_tx :: tx_gb_pattern2_2 7797 */ 7798 /* rg_tx :: tx_gb_pattern2_2 :: pattern2_2 [15:00] */ 7799 #define RG_TX_TX_GB_PATTERN2_2_PATTERN2_2_MASK 0xffff 7800 #define RG_TX_TX_GB_PATTERN2_2_PATTERN2_2_ALIGN 0 7801 #define RG_TX_TX_GB_PATTERN2_2_PATTERN2_2_BITS 16 7802 #define RG_TX_TX_GB_PATTERN2_2_PATTERN2_2_SHIFT 0 7803 7804 7805 /**************************************************************************** 7806 * rg_tx :: tx_gb_pattern2_3 7807 */ 7808 /* rg_tx :: tx_gb_pattern2_3 :: pattern2_3 [15:00] */ 7809 #define RG_TX_TX_GB_PATTERN2_3_PATTERN2_3_MASK 0xffff 7810 #define RG_TX_TX_GB_PATTERN2_3_PATTERN2_3_ALIGN 0 7811 #define RG_TX_TX_GB_PATTERN2_3_PATTERN2_3_BITS 16 7812 #define RG_TX_TX_GB_PATTERN2_3_PATTERN2_3_SHIFT 0 7813 7814 7815 /**************************************************************************** 7816 * rg_tx :: tx_gb_pattern2_4 7817 */ 7818 /* rg_tx :: tx_gb_pattern2_4 :: pattern2_4 [15:00] */ 7819 #define RG_TX_TX_GB_PATTERN2_4_PATTERN2_4_MASK 0xffff 7820 #define RG_TX_TX_GB_PATTERN2_4_PATTERN2_4_ALIGN 0 7821 #define RG_TX_TX_GB_PATTERN2_4_PATTERN2_4_BITS 16 7822 #define RG_TX_TX_GB_PATTERN2_4_PATTERN2_4_SHIFT 0 7823 7824 7825 /**************************************************************************** 7826 * rg_tx :: tx_gb_pattern2_5 7827 */ 7828 /* rg_tx :: tx_gb_pattern2_5 :: pattern2_5 [15:00] */ 7829 #define RG_TX_TX_GB_PATTERN2_5_PATTERN2_5_MASK 0xffff 7830 #define RG_TX_TX_GB_PATTERN2_5_PATTERN2_5_ALIGN 0 7831 #define RG_TX_TX_GB_PATTERN2_5_PATTERN2_5_BITS 16 7832 #define RG_TX_TX_GB_PATTERN2_5_PATTERN2_5_SHIFT 0 7833 7834 7835 /**************************************************************************** 7836 * rg_tx :: tx_gb_pattern2_6 7837 */ 7838 /* rg_tx :: tx_gb_pattern2_6 :: pattern2_6 [15:00] */ 7839 #define RG_TX_TX_GB_PATTERN2_6_PATTERN2_6_MASK 0xffff 7840 #define RG_TX_TX_GB_PATTERN2_6_PATTERN2_6_ALIGN 0 7841 #define RG_TX_TX_GB_PATTERN2_6_PATTERN2_6_BITS 16 7842 #define RG_TX_TX_GB_PATTERN2_6_PATTERN2_6_SHIFT 0 7843 7844 7845 /**************************************************************************** 7846 * rg_tx :: tx_gb_pattern2_7 7847 */ 7848 /* rg_tx :: tx_gb_pattern2_7 :: pattern2_7 [15:00] */ 7849 #define RG_TX_TX_GB_PATTERN2_7_PATTERN2_7_MASK 0xffff 7850 #define RG_TX_TX_GB_PATTERN2_7_PATTERN2_7_ALIGN 0 7851 #define RG_TX_TX_GB_PATTERN2_7_PATTERN2_7_BITS 16 7852 #define RG_TX_TX_GB_PATTERN2_7_PATTERN2_7_SHIFT 0 7853 7854 7855 /**************************************************************************** 7856 * rg_tx :: tx_gb_pattern3_0 7857 */ 7858 /* rg_tx :: tx_gb_pattern3_0 :: pattern3_0 [15:00] */ 7859 #define RG_TX_TX_GB_PATTERN3_0_PATTERN3_0_MASK 0xffff 7860 #define RG_TX_TX_GB_PATTERN3_0_PATTERN3_0_ALIGN 0 7861 #define RG_TX_TX_GB_PATTERN3_0_PATTERN3_0_BITS 16 7862 #define RG_TX_TX_GB_PATTERN3_0_PATTERN3_0_SHIFT 0 7863 7864 7865 /**************************************************************************** 7866 * rg_tx :: tx_gb_pattern3_1 7867 */ 7868 /* rg_tx :: tx_gb_pattern3_1 :: pattern3_1 [15:00] */ 7869 #define RG_TX_TX_GB_PATTERN3_1_PATTERN3_1_MASK 0xffff 7870 #define RG_TX_TX_GB_PATTERN3_1_PATTERN3_1_ALIGN 0 7871 #define RG_TX_TX_GB_PATTERN3_1_PATTERN3_1_BITS 16 7872 #define RG_TX_TX_GB_PATTERN3_1_PATTERN3_1_SHIFT 0 7873 7874 7875 /**************************************************************************** 7876 * rg_tx :: tx_gb_pattern3_2 7877 */ 7878 /* rg_tx :: tx_gb_pattern3_2 :: pattern3_2 [15:00] */ 7879 #define RG_TX_TX_GB_PATTERN3_2_PATTERN3_2_MASK 0xffff 7880 #define RG_TX_TX_GB_PATTERN3_2_PATTERN3_2_ALIGN 0 7881 #define RG_TX_TX_GB_PATTERN3_2_PATTERN3_2_BITS 16 7882 #define RG_TX_TX_GB_PATTERN3_2_PATTERN3_2_SHIFT 0 7883 7884 7885 /**************************************************************************** 7886 * rg_tx :: tx_gb_pattern3_3 7887 */ 7888 /* rg_tx :: tx_gb_pattern3_3 :: pattern3_3 [15:00] */ 7889 #define RG_TX_TX_GB_PATTERN3_3_PATTERN3_3_MASK 0xffff 7890 #define RG_TX_TX_GB_PATTERN3_3_PATTERN3_3_ALIGN 0 7891 #define RG_TX_TX_GB_PATTERN3_3_PATTERN3_3_BITS 16 7892 #define RG_TX_TX_GB_PATTERN3_3_PATTERN3_3_SHIFT 0 7893 7894 7895 /**************************************************************************** 7896 * rg_tx :: tx_gb_pattern3_4 7897 */ 7898 /* rg_tx :: tx_gb_pattern3_4 :: pattern3_4 [15:00] */ 7899 #define RG_TX_TX_GB_PATTERN3_4_PATTERN3_4_MASK 0xffff 7900 #define RG_TX_TX_GB_PATTERN3_4_PATTERN3_4_ALIGN 0 7901 #define RG_TX_TX_GB_PATTERN3_4_PATTERN3_4_BITS 16 7902 #define RG_TX_TX_GB_PATTERN3_4_PATTERN3_4_SHIFT 0 7903 7904 7905 /**************************************************************************** 7906 * rg_tx :: tx_gb_pattern3_5 7907 */ 7908 /* rg_tx :: tx_gb_pattern3_5 :: pattern3_5 [15:00] */ 7909 #define RG_TX_TX_GB_PATTERN3_5_PATTERN3_5_MASK 0xffff 7910 #define RG_TX_TX_GB_PATTERN3_5_PATTERN3_5_ALIGN 0 7911 #define RG_TX_TX_GB_PATTERN3_5_PATTERN3_5_BITS 16 7912 #define RG_TX_TX_GB_PATTERN3_5_PATTERN3_5_SHIFT 0 7913 7914 7915 /**************************************************************************** 7916 * rg_tx :: tx_gb_pattern3_6 7917 */ 7918 /* rg_tx :: tx_gb_pattern3_6 :: pattern3_6 [15:00] */ 7919 #define RG_TX_TX_GB_PATTERN3_6_PATTERN3_6_MASK 0xffff 7920 #define RG_TX_TX_GB_PATTERN3_6_PATTERN3_6_ALIGN 0 7921 #define RG_TX_TX_GB_PATTERN3_6_PATTERN3_6_BITS 16 7922 #define RG_TX_TX_GB_PATTERN3_6_PATTERN3_6_SHIFT 0 7923 7924 7925 /**************************************************************************** 7926 * rg_tx :: tx_gb_pattern3_7 7927 */ 7928 /* rg_tx :: tx_gb_pattern3_7 :: pattern3_7 [15:00] */ 7929 #define RG_TX_TX_GB_PATTERN3_7_PATTERN3_7_MASK 0xffff 7930 #define RG_TX_TX_GB_PATTERN3_7_PATTERN3_7_ALIGN 0 7931 #define RG_TX_TX_GB_PATTERN3_7_PATTERN3_7_BITS 16 7932 #define RG_TX_TX_GB_PATTERN3_7_PATTERN3_7_SHIFT 0 7933 7934 7935 /**************************************************************************** 7936 * rg_tx :: tx_gb_pattern_8 7937 */ 7938 /* rg_tx :: tx_gb_pattern_8 :: pattern3_8 [15:12] */ 7939 #define RG_TX_TX_GB_PATTERN_8_PATTERN3_8_MASK 0xf000 7940 #define RG_TX_TX_GB_PATTERN_8_PATTERN3_8_ALIGN 0 7941 #define RG_TX_TX_GB_PATTERN_8_PATTERN3_8_BITS 4 7942 #define RG_TX_TX_GB_PATTERN_8_PATTERN3_8_SHIFT 12 7943 7944 /* rg_tx :: tx_gb_pattern_8 :: pattern2_8 [11:08] */ 7945 #define RG_TX_TX_GB_PATTERN_8_PATTERN2_8_MASK 0x0f00 7946 #define RG_TX_TX_GB_PATTERN_8_PATTERN2_8_ALIGN 0 7947 #define RG_TX_TX_GB_PATTERN_8_PATTERN2_8_BITS 4 7948 #define RG_TX_TX_GB_PATTERN_8_PATTERN2_8_SHIFT 8 7949 7950 /* rg_tx :: tx_gb_pattern_8 :: pattern1_8 [07:04] */ 7951 #define RG_TX_TX_GB_PATTERN_8_PATTERN1_8_MASK 0x00f0 7952 #define RG_TX_TX_GB_PATTERN_8_PATTERN1_8_ALIGN 0 7953 #define RG_TX_TX_GB_PATTERN_8_PATTERN1_8_BITS 4 7954 #define RG_TX_TX_GB_PATTERN_8_PATTERN1_8_SHIFT 4 7955 7956 /* rg_tx :: tx_gb_pattern_8 :: pattern0_8 [03:00] */ 7957 #define RG_TX_TX_GB_PATTERN_8_PATTERN0_8_MASK 0x000f 7958 #define RG_TX_TX_GB_PATTERN_8_PATTERN0_8_ALIGN 0 7959 #define RG_TX_TX_GB_PATTERN_8_PATTERN0_8_BITS 4 7960 #define RG_TX_TX_GB_PATTERN_8_PATTERN0_8_SHIFT 0 7961 7962 7963 /**************************************************************************** 7964 * rg_tx :: tx_gb_lpbk_ptr_sync0 7965 */ 7966 /* rg_tx :: tx_gb_lpbk_ptr_sync0 :: lpbk_ptr_sync3 [15:12] */ 7967 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC3_MASK 0xf000 7968 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC3_ALIGN 0 7969 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC3_BITS 4 7970 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC3_SHIFT 12 7971 7972 /* rg_tx :: tx_gb_lpbk_ptr_sync0 :: lpbk_ptr_sync2 [11:08] */ 7973 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC2_MASK 0x0f00 7974 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC2_ALIGN 0 7975 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC2_BITS 4 7976 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC2_SHIFT 8 7977 7978 /* rg_tx :: tx_gb_lpbk_ptr_sync0 :: lpbk_ptr_sync1 [07:04] */ 7979 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC1_MASK 0x00f0 7980 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC1_ALIGN 0 7981 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC1_BITS 4 7982 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC1_SHIFT 4 7983 7984 /* rg_tx :: tx_gb_lpbk_ptr_sync0 :: lpbk_ptr_sync0 [03:00] */ 7985 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC0_MASK 0x000f 7986 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC0_ALIGN 0 7987 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC0_BITS 4 7988 #define RG_TX_TX_GB_LPBK_PTR_SYNC0_LPBK_PTR_SYNC0_SHIFT 0 7989 7990 7991 /**************************************************************************** 7992 * rg_tx :: tx_gb_lpbk_ptr_sync1 7993 */ 7994 /* rg_tx :: tx_gb_lpbk_ptr_sync1 :: lpbk_ptr_sync7 [15:12] */ 7995 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC7_MASK 0xf000 7996 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC7_ALIGN 0 7997 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC7_BITS 4 7998 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC7_SHIFT 12 7999 8000 /* rg_tx :: tx_gb_lpbk_ptr_sync1 :: lpbk_ptr_sync6 [11:08] */ 8001 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC6_MASK 0x0f00 8002 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC6_ALIGN 0 8003 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC6_BITS 4 8004 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC6_SHIFT 8 8005 8006 /* rg_tx :: tx_gb_lpbk_ptr_sync1 :: lpbk_ptr_sync5 [07:04] */ 8007 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC5_MASK 0x00f0 8008 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC5_ALIGN 0 8009 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC5_BITS 4 8010 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC5_SHIFT 4 8011 8012 /* rg_tx :: tx_gb_lpbk_ptr_sync1 :: lpbk_ptr_sync4 [03:00] */ 8013 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC4_MASK 0x000f 8014 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC4_ALIGN 0 8015 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC4_BITS 4 8016 #define RG_TX_TX_GB_LPBK_PTR_SYNC1_LPBK_PTR_SYNC4_SHIFT 0 8017 8018 8019 /**************************************************************************** 8020 * rg_tx :: tx_gb_ln89_ptr_sync 8021 */ 8022 /* rg_tx :: tx_gb_ln89_ptr_sync :: ptr_sync9 [15:12] */ 8023 #define RG_TX_TX_GB_LN89_PTR_SYNC_PTR_SYNC9_MASK 0xf000 8024 #define RG_TX_TX_GB_LN89_PTR_SYNC_PTR_SYNC9_ALIGN 0 8025 #define RG_TX_TX_GB_LN89_PTR_SYNC_PTR_SYNC9_BITS 4 8026 #define RG_TX_TX_GB_LN89_PTR_SYNC_PTR_SYNC9_SHIFT 12 8027 8028 /* rg_tx :: tx_gb_ln89_ptr_sync :: ptr_sync8 [11:08] */ 8029 #define RG_TX_TX_GB_LN89_PTR_SYNC_PTR_SYNC8_MASK 0x0f00 8030 #define RG_TX_TX_GB_LN89_PTR_SYNC_PTR_SYNC8_ALIGN 0 8031 #define RG_TX_TX_GB_LN89_PTR_SYNC_PTR_SYNC8_BITS 4 8032 #define RG_TX_TX_GB_LN89_PTR_SYNC_PTR_SYNC8_SHIFT 8 8033 8034 /* rg_tx :: tx_gb_ln89_ptr_sync :: lpbk_ptr_sync9 [07:04] */ 8035 #define RG_TX_TX_GB_LN89_PTR_SYNC_LPBK_PTR_SYNC9_MASK 0x00f0 8036 #define RG_TX_TX_GB_LN89_PTR_SYNC_LPBK_PTR_SYNC9_ALIGN 0 8037 #define RG_TX_TX_GB_LN89_PTR_SYNC_LPBK_PTR_SYNC9_BITS 4 8038 #define RG_TX_TX_GB_LN89_PTR_SYNC_LPBK_PTR_SYNC9_SHIFT 4 8039 8040 /* rg_tx :: tx_gb_ln89_ptr_sync :: lpbk_ptr_sync8 [03:00] */ 8041 #define RG_TX_TX_GB_LN89_PTR_SYNC_LPBK_PTR_SYNC8_MASK 0x000f 8042 #define RG_TX_TX_GB_LN89_PTR_SYNC_LPBK_PTR_SYNC8_ALIGN 0 8043 #define RG_TX_TX_GB_LN89_PTR_SYNC_LPBK_PTR_SYNC8_BITS 4 8044 #define RG_TX_TX_GB_LN89_PTR_SYNC_LPBK_PTR_SYNC8_SHIFT 0 8045 8046 8047 /**************************************************************************** 8048 * rg_tx :: tx_gb_ptr_sync1 8049 */ 8050 /* rg_tx :: tx_gb_ptr_sync1 :: ptr_sync7 [15:12] */ 8051 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC7_MASK 0xf000 8052 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC7_ALIGN 0 8053 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC7_BITS 4 8054 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC7_SHIFT 12 8055 8056 /* rg_tx :: tx_gb_ptr_sync1 :: ptr_sync6 [11:08] */ 8057 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC6_MASK 0x0f00 8058 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC6_ALIGN 0 8059 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC6_BITS 4 8060 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC6_SHIFT 8 8061 8062 /* rg_tx :: tx_gb_ptr_sync1 :: ptr_sync5 [07:04] */ 8063 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC5_MASK 0x00f0 8064 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC5_ALIGN 0 8065 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC5_BITS 4 8066 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC5_SHIFT 4 8067 8068 /* rg_tx :: tx_gb_ptr_sync1 :: ptr_sync4 [03:00] */ 8069 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC4_MASK 0x000f 8070 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC4_ALIGN 0 8071 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC4_BITS 4 8072 #define RG_TX_TX_GB_PTR_SYNC1_PTR_SYNC4_SHIFT 0 8073 8074 8075 /**************************************************************************** 8076 * rg_tx :: tx_gb_ptr_sync0 8077 */ 8078 /* rg_tx :: tx_gb_ptr_sync0 :: ptr_sync3 [15:12] */ 8079 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC3_MASK 0xf000 8080 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC3_ALIGN 0 8081 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC3_BITS 4 8082 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC3_SHIFT 12 8083 8084 /* rg_tx :: tx_gb_ptr_sync0 :: ptr_sync2 [11:08] */ 8085 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC2_MASK 0x0f00 8086 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC2_ALIGN 0 8087 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC2_BITS 4 8088 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC2_SHIFT 8 8089 8090 /* rg_tx :: tx_gb_ptr_sync0 :: ptr_sync1 [07:04] */ 8091 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC1_MASK 0x00f0 8092 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC1_ALIGN 0 8093 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC1_BITS 4 8094 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC1_SHIFT 4 8095 8096 /* rg_tx :: tx_gb_ptr_sync0 :: ptr_sync0 [03:00] */ 8097 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC0_MASK 0x000f 8098 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC0_ALIGN 0 8099 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC0_BITS 4 8100 #define RG_TX_TX_GB_PTR_SYNC0_PTR_SYNC0_SHIFT 0 8101 8102 8103 /**************************************************************************** 8104 * rg_tx :: tx_gb_50to64_ctrl 8105 */ 8106 /* rg_tx :: tx_gb_50to64_ctrl :: reserved0 [15:08] */ 8107 #define RG_TX_TX_GB_50TO64_CTRL_RESERVED0_MASK 0xff00 8108 #define RG_TX_TX_GB_50TO64_CTRL_RESERVED0_ALIGN 0 8109 #define RG_TX_TX_GB_50TO64_CTRL_RESERVED0_BITS 8 8110 #define RG_TX_TX_GB_50TO64_CTRL_RESERVED0_SHIFT 8 8111 8112 /* rg_tx :: tx_gb_50to64_ctrl :: col_threshold10 [07:04] */ 8113 #define RG_TX_TX_GB_50TO64_CTRL_COL_THRESHOLD10_MASK 0x00f0 8114 #define RG_TX_TX_GB_50TO64_CTRL_COL_THRESHOLD10_ALIGN 0 8115 #define RG_TX_TX_GB_50TO64_CTRL_COL_THRESHOLD10_BITS 4 8116 #define RG_TX_TX_GB_50TO64_CTRL_COL_THRESHOLD10_SHIFT 4 8117 8118 /* rg_tx :: tx_gb_50to64_ctrl :: ptr_sync10 [03:00] */ 8119 #define RG_TX_TX_GB_50TO64_CTRL_PTR_SYNC10_MASK 0x000f 8120 #define RG_TX_TX_GB_50TO64_CTRL_PTR_SYNC10_ALIGN 0 8121 #define RG_TX_TX_GB_50TO64_CTRL_PTR_SYNC10_BITS 4 8122 #define RG_TX_TX_GB_50TO64_CTRL_PTR_SYNC10_SHIFT 0 8123 8124 8125 /**************************************************************************** 8126 * rg_tx :: tx_gb_lpbk_col_threshold0 8127 */ 8128 /* rg_tx :: tx_gb_lpbk_col_threshold0 :: lpbk_col_threshold3 [15:12] */ 8129 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD3_MASK 0xf000 8130 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD3_ALIGN 0 8131 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD3_BITS 4 8132 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD3_SHIFT 12 8133 8134 /* rg_tx :: tx_gb_lpbk_col_threshold0 :: lpbk_col_threshold2 [11:08] */ 8135 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD2_MASK 0x0f00 8136 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD2_ALIGN 0 8137 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD2_BITS 4 8138 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD2_SHIFT 8 8139 8140 /* rg_tx :: tx_gb_lpbk_col_threshold0 :: lpbk_col_threshold1 [07:04] */ 8141 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD1_MASK 0x00f0 8142 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD1_ALIGN 0 8143 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD1_BITS 4 8144 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD1_SHIFT 4 8145 8146 /* rg_tx :: tx_gb_lpbk_col_threshold0 :: lpbk_col_threshold0 [03:00] */ 8147 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD0_MASK 0x000f 8148 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD0_ALIGN 0 8149 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD0_BITS 4 8150 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD0_LPBK_COL_THRESHOLD0_SHIFT 0 8151 8152 8153 /**************************************************************************** 8154 * rg_tx :: tx_gb_lpbk_col_threshold1 8155 */ 8156 /* rg_tx :: tx_gb_lpbk_col_threshold1 :: lpbk_col_threshold7 [15:12] */ 8157 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD7_MASK 0xf000 8158 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD7_ALIGN 0 8159 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD7_BITS 4 8160 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD7_SHIFT 12 8161 8162 /* rg_tx :: tx_gb_lpbk_col_threshold1 :: lpbk_col_threshold6 [11:08] */ 8163 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD6_MASK 0x0f00 8164 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD6_ALIGN 0 8165 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD6_BITS 4 8166 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD6_SHIFT 8 8167 8168 /* rg_tx :: tx_gb_lpbk_col_threshold1 :: lpbk_col_threshold5 [07:04] */ 8169 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD5_MASK 0x00f0 8170 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD5_ALIGN 0 8171 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD5_BITS 4 8172 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD5_SHIFT 4 8173 8174 /* rg_tx :: tx_gb_lpbk_col_threshold1 :: lpbk_col_threshold4 [03:00] */ 8175 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD4_MASK 0x000f 8176 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD4_ALIGN 0 8177 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD4_BITS 4 8178 #define RG_TX_TX_GB_LPBK_COL_THRESHOLD1_LPBK_COL_THRESHOLD4_SHIFT 0 8179 8180 8181 /**************************************************************************** 8182 * rg_tx :: tx_gb_col_threshold89 8183 */ 8184 /* rg_tx :: tx_gb_col_threshold89 :: col_threshold9 [15:12] */ 8185 #define RG_TX_TX_GB_COL_THRESHOLD89_COL_THRESHOLD9_MASK 0xf000 8186 #define RG_TX_TX_GB_COL_THRESHOLD89_COL_THRESHOLD9_ALIGN 0 8187 #define RG_TX_TX_GB_COL_THRESHOLD89_COL_THRESHOLD9_BITS 4 8188 #define RG_TX_TX_GB_COL_THRESHOLD89_COL_THRESHOLD9_SHIFT 12 8189 8190 /* rg_tx :: tx_gb_col_threshold89 :: col_threshold8 [11:08] */ 8191 #define RG_TX_TX_GB_COL_THRESHOLD89_COL_THRESHOLD8_MASK 0x0f00 8192 #define RG_TX_TX_GB_COL_THRESHOLD89_COL_THRESHOLD8_ALIGN 0 8193 #define RG_TX_TX_GB_COL_THRESHOLD89_COL_THRESHOLD8_BITS 4 8194 #define RG_TX_TX_GB_COL_THRESHOLD89_COL_THRESHOLD8_SHIFT 8 8195 8196 /* rg_tx :: tx_gb_col_threshold89 :: lpbk_col_threshold9 [07:04] */ 8197 #define RG_TX_TX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD9_MASK 0x00f0 8198 #define RG_TX_TX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD9_ALIGN 0 8199 #define RG_TX_TX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD9_BITS 4 8200 #define RG_TX_TX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD9_SHIFT 4 8201 8202 /* rg_tx :: tx_gb_col_threshold89 :: lpbk_col_threshold8 [03:00] */ 8203 #define RG_TX_TX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD8_MASK 0x000f 8204 #define RG_TX_TX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD8_ALIGN 0 8205 #define RG_TX_TX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD8_BITS 4 8206 #define RG_TX_TX_GB_COL_THRESHOLD89_LPBK_COL_THRESHOLD8_SHIFT 0 8207 8208 8209 /**************************************************************************** 8210 * rg_tx :: tx_gb_col_threshold1 8211 */ 8212 /* rg_tx :: tx_gb_col_threshold1 :: col_threshold7 [15:12] */ 8213 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD7_MASK 0xf000 8214 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD7_ALIGN 0 8215 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD7_BITS 4 8216 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD7_SHIFT 12 8217 8218 /* rg_tx :: tx_gb_col_threshold1 :: col_threshold6 [11:08] */ 8219 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD6_MASK 0x0f00 8220 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD6_ALIGN 0 8221 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD6_BITS 4 8222 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD6_SHIFT 8 8223 8224 /* rg_tx :: tx_gb_col_threshold1 :: col_threshold5 [07:04] */ 8225 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD5_MASK 0x00f0 8226 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD5_ALIGN 0 8227 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD5_BITS 4 8228 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD5_SHIFT 4 8229 8230 /* rg_tx :: tx_gb_col_threshold1 :: col_threshold4 [03:00] */ 8231 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD4_MASK 0x000f 8232 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD4_ALIGN 0 8233 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD4_BITS 4 8234 #define RG_TX_TX_GB_COL_THRESHOLD1_COL_THRESHOLD4_SHIFT 0 8235 8236 8237 /**************************************************************************** 8238 * rg_tx :: tx_gb_col_threshold0 8239 */ 8240 /* rg_tx :: tx_gb_col_threshold0 :: col_threshold3 [15:12] */ 8241 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD3_MASK 0xf000 8242 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD3_ALIGN 0 8243 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD3_BITS 4 8244 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD3_SHIFT 12 8245 8246 /* rg_tx :: tx_gb_col_threshold0 :: col_threshold2 [11:08] */ 8247 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD2_MASK 0x0f00 8248 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD2_ALIGN 0 8249 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD2_BITS 4 8250 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD2_SHIFT 8 8251 8252 /* rg_tx :: tx_gb_col_threshold0 :: col_threshold1 [07:04] */ 8253 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD1_MASK 0x00f0 8254 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD1_ALIGN 0 8255 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD1_BITS 4 8256 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD1_SHIFT 4 8257 8258 /* rg_tx :: tx_gb_col_threshold0 :: col_threshold0 [03:00] */ 8259 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD0_MASK 0x000f 8260 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD0_ALIGN 0 8261 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD0_BITS 4 8262 #define RG_TX_TX_GB_COL_THRESHOLD0_COL_THRESHOLD0_SHIFT 0 8263 8264 8265 /**************************************************************************** 8266 * rg_tx :: tx_gb_io_bit_control 8267 */ 8268 /* rg_tx :: tx_gb_io_bit_control :: reserved0 [15:13] */ 8269 #define RG_TX_TX_GB_IO_BIT_CONTROL_RESERVED0_MASK 0xe000 8270 #define RG_TX_TX_GB_IO_BIT_CONTROL_RESERVED0_ALIGN 0 8271 #define RG_TX_TX_GB_IO_BIT_CONTROL_RESERVED0_BITS 3 8272 #define RG_TX_TX_GB_IO_BIT_CONTROL_RESERVED0_SHIFT 13 8273 8274 /* rg_tx :: tx_gb_io_bit_control :: stx_rev_en [12:12] */ 8275 #define RG_TX_TX_GB_IO_BIT_CONTROL_STX_REV_EN_MASK 0x1000 8276 #define RG_TX_TX_GB_IO_BIT_CONTROL_STX_REV_EN_ALIGN 0 8277 #define RG_TX_TX_GB_IO_BIT_CONTROL_STX_REV_EN_BITS 1 8278 #define RG_TX_TX_GB_IO_BIT_CONTROL_STX_REV_EN_SHIFT 12 8279 8280 /* rg_tx :: tx_gb_io_bit_control :: ltx_ds_rev_en [11:11] */ 8281 #define RG_TX_TX_GB_IO_BIT_CONTROL_LTX_DS_REV_EN_MASK 0x0800 8282 #define RG_TX_TX_GB_IO_BIT_CONTROL_LTX_DS_REV_EN_ALIGN 0 8283 #define RG_TX_TX_GB_IO_BIT_CONTROL_LTX_DS_REV_EN_BITS 1 8284 #define RG_TX_TX_GB_IO_BIT_CONTROL_LTX_DS_REV_EN_SHIFT 11 8285 8286 /* rg_tx :: tx_gb_io_bit_control :: ltx_10g_rev_en [10:10] */ 8287 #define RG_TX_TX_GB_IO_BIT_CONTROL_LTX_10G_REV_EN_MASK 0x0400 8288 #define RG_TX_TX_GB_IO_BIT_CONTROL_LTX_10G_REV_EN_ALIGN 0 8289 #define RG_TX_TX_GB_IO_BIT_CONTROL_LTX_10G_REV_EN_BITS 1 8290 #define RG_TX_TX_GB_IO_BIT_CONTROL_LTX_10G_REV_EN_SHIFT 10 8291 8292 /* rg_tx :: tx_gb_io_bit_control :: output_invert [09:00] */ 8293 #define RG_TX_TX_GB_IO_BIT_CONTROL_OUTPUT_INVERT_MASK 0x03ff 8294 #define RG_TX_TX_GB_IO_BIT_CONTROL_OUTPUT_INVERT_ALIGN 0 8295 #define RG_TX_TX_GB_IO_BIT_CONTROL_OUTPUT_INVERT_BITS 10 8296 #define RG_TX_TX_GB_IO_BIT_CONTROL_OUTPUT_INVERT_SHIFT 0 8297 8298 8299 /**************************************************************************** 8300 * rg_tx :: tx_gb_logic_lane_test 8301 */ 8302 /* rg_tx :: tx_gb_logic_lane_test :: reserved0 [15:15] */ 8303 #define RG_TX_TX_GB_LOGIC_LANE_TEST_RESERVED0_MASK 0x8000 8304 #define RG_TX_TX_GB_LOGIC_LANE_TEST_RESERVED0_ALIGN 0 8305 #define RG_TX_TX_GB_LOGIC_LANE_TEST_RESERVED0_BITS 1 8306 #define RG_TX_TX_GB_LOGIC_LANE_TEST_RESERVED0_SHIFT 15 8307 8308 /* rg_tx :: tx_gb_logic_lane_test :: logic_lane_test [14:14] */ 8309 #define RG_TX_TX_GB_LOGIC_LANE_TEST_LOGIC_LANE_TEST_MASK 0x4000 8310 #define RG_TX_TX_GB_LOGIC_LANE_TEST_LOGIC_LANE_TEST_ALIGN 0 8311 #define RG_TX_TX_GB_LOGIC_LANE_TEST_LOGIC_LANE_TEST_BITS 1 8312 #define RG_TX_TX_GB_LOGIC_LANE_TEST_LOGIC_LANE_TEST_SHIFT 14 8313 8314 /* rg_tx :: tx_gb_logic_lane_test :: check_next_lane [13:04] */ 8315 #define RG_TX_TX_GB_LOGIC_LANE_TEST_CHECK_NEXT_LANE_MASK 0x3ff0 8316 #define RG_TX_TX_GB_LOGIC_LANE_TEST_CHECK_NEXT_LANE_ALIGN 0 8317 #define RG_TX_TX_GB_LOGIC_LANE_TEST_CHECK_NEXT_LANE_BITS 10 8318 #define RG_TX_TX_GB_LOGIC_LANE_TEST_CHECK_NEXT_LANE_SHIFT 4 8319 8320 /* rg_tx :: tx_gb_logic_lane_test :: gen_next_lane [03:00] */ 8321 #define RG_TX_TX_GB_LOGIC_LANE_TEST_GEN_NEXT_LANE_MASK 0x000f 8322 #define RG_TX_TX_GB_LOGIC_LANE_TEST_GEN_NEXT_LANE_ALIGN 0 8323 #define RG_TX_TX_GB_LOGIC_LANE_TEST_GEN_NEXT_LANE_BITS 4 8324 #define RG_TX_TX_GB_LOGIC_LANE_TEST_GEN_NEXT_LANE_SHIFT 0 8325 8326 8327 /**************************************************************************** 8328 * rg_tx :: tx_gb_collide_lpbk 8329 */ 8330 /* rg_tx :: tx_gb_collide_lpbk :: reserved0 [15:10] */ 8331 #define RG_TX_TX_GB_COLLIDE_LPBK_RESERVED0_MASK 0xfc00 8332 #define RG_TX_TX_GB_COLLIDE_LPBK_RESERVED0_ALIGN 0 8333 #define RG_TX_TX_GB_COLLIDE_LPBK_RESERVED0_BITS 6 8334 #define RG_TX_TX_GB_COLLIDE_LPBK_RESERVED0_SHIFT 10 8335 8336 /* rg_tx :: tx_gb_collide_lpbk :: collide_lb [09:00] */ 8337 #define RG_TX_TX_GB_COLLIDE_LPBK_COLLIDE_LB_MASK 0x03ff 8338 #define RG_TX_TX_GB_COLLIDE_LPBK_COLLIDE_LB_ALIGN 0 8339 #define RG_TX_TX_GB_COLLIDE_LPBK_COLLIDE_LB_BITS 10 8340 #define RG_TX_TX_GB_COLLIDE_LPBK_COLLIDE_LB_SHIFT 0 8341 8342 8343 /**************************************************************************** 8344 * rg_tx :: tx_gb_collide_lpbk_lh 8345 */ 8346 /* rg_tx :: tx_gb_collide_lpbk_lh :: reserved0 [15:10] */ 8347 #define RG_TX_TX_GB_COLLIDE_LPBK_LH_RESERVED0_MASK 0xfc00 8348 #define RG_TX_TX_GB_COLLIDE_LPBK_LH_RESERVED0_ALIGN 0 8349 #define RG_TX_TX_GB_COLLIDE_LPBK_LH_RESERVED0_BITS 6 8350 #define RG_TX_TX_GB_COLLIDE_LPBK_LH_RESERVED0_SHIFT 10 8351 8352 /* rg_tx :: tx_gb_collide_lpbk_lh :: collide_lb_lh [09:00] */ 8353 #define RG_TX_TX_GB_COLLIDE_LPBK_LH_COLLIDE_LB_LH_MASK 0x03ff 8354 #define RG_TX_TX_GB_COLLIDE_LPBK_LH_COLLIDE_LB_LH_ALIGN 0 8355 #define RG_TX_TX_GB_COLLIDE_LPBK_LH_COLLIDE_LB_LH_BITS 10 8356 #define RG_TX_TX_GB_COLLIDE_LPBK_LH_COLLIDE_LB_LH_SHIFT 0 8357 8358 8359 /**************************************************************************** 8360 * rg_tx :: tx_gb_collide 8361 */ 8362 /* rg_tx :: tx_gb_collide :: reserved0 [15:14] */ 8363 #define RG_TX_TX_GB_COLLIDE_RESERVED0_MASK 0xc000 8364 #define RG_TX_TX_GB_COLLIDE_RESERVED0_ALIGN 0 8365 #define RG_TX_TX_GB_COLLIDE_RESERVED0_BITS 2 8366 #define RG_TX_TX_GB_COLLIDE_RESERVED0_SHIFT 14 8367 8368 /* rg_tx :: tx_gb_collide :: collide_pt [13:00] */ 8369 #define RG_TX_TX_GB_COLLIDE_COLLIDE_PT_MASK 0x3fff 8370 #define RG_TX_TX_GB_COLLIDE_COLLIDE_PT_ALIGN 0 8371 #define RG_TX_TX_GB_COLLIDE_COLLIDE_PT_BITS 14 8372 #define RG_TX_TX_GB_COLLIDE_COLLIDE_PT_SHIFT 0 8373 8374 8375 /**************************************************************************** 8376 * rg_tx :: tx_gb_collide_lh 8377 */ 8378 /* rg_tx :: tx_gb_collide_lh :: reserved0 [15:14] */ 8379 #define RG_TX_TX_GB_COLLIDE_LH_RESERVED0_MASK 0xc000 8380 #define RG_TX_TX_GB_COLLIDE_LH_RESERVED0_ALIGN 0 8381 #define RG_TX_TX_GB_COLLIDE_LH_RESERVED0_BITS 2 8382 #define RG_TX_TX_GB_COLLIDE_LH_RESERVED0_SHIFT 14 8383 8384 /* rg_tx :: tx_gb_collide_lh :: collide_pt_lh [13:00] */ 8385 #define RG_TX_TX_GB_COLLIDE_LH_COLLIDE_PT_LH_MASK 0x3fff 8386 #define RG_TX_TX_GB_COLLIDE_LH_COLLIDE_PT_LH_ALIGN 0 8387 #define RG_TX_TX_GB_COLLIDE_LH_COLLIDE_PT_LH_BITS 14 8388 #define RG_TX_TX_GB_COLLIDE_LH_COLLIDE_PT_LH_SHIFT 0 8389 8390 8391 /**************************************************************************** 8392 * slice_regs_regs 8393 */ 8394 /**************************************************************************** 8395 * slice_regs :: slice 8396 */ 8397 /* slice_regs :: slice :: reserved0 [15:04] */ 8398 #define SLICE_REGS_SLICE_RESERVED0_MASK 0xfff0 8399 #define SLICE_REGS_SLICE_RESERVED0_ALIGN 0 8400 #define SLICE_REGS_SLICE_RESERVED0_BITS 12 8401 #define SLICE_REGS_SLICE_RESERVED0_SHIFT 4 8402 8403 /* slice_regs :: slice :: slice_f [03:00] */ 8404 #define SLICE_REGS_SLICE_SLICE_F_MASK 0x000f 8405 #define SLICE_REGS_SLICE_SLICE_F_ALIGN 0 8406 #define SLICE_REGS_SLICE_SLICE_F_BITS 4 8407 #define SLICE_REGS_SLICE_SLICE_F_SHIFT 0 8408 8409 8410 /**************************************************************************** 8411 * vsr40_rx_ana25g_regs 8412 */ 8413 /**************************************************************************** 8414 * vsr40_rx_ana25g :: control11 8415 */ 8416 /* vsr40_rx_ana25g :: control11 :: rsrvd_for_eco_143_135 [15:07] */ 8417 #define VSR40_RX_ANA25G_CONTROL11_RSRVD_FOR_ECO_143_135_MASK 0xff80 8418 #define VSR40_RX_ANA25G_CONTROL11_RSRVD_FOR_ECO_143_135_ALIGN 0 8419 #define VSR40_RX_ANA25G_CONTROL11_RSRVD_FOR_ECO_143_135_BITS 9 8420 #define VSR40_RX_ANA25G_CONTROL11_RSRVD_FOR_ECO_143_135_SHIFT 7 8421 8422 /* vsr40_rx_ana25g :: control11 :: sel_testclk8T [06:06] */ 8423 #define VSR40_RX_ANA25G_CONTROL11_SEL_TESTCLK8T_MASK 0x0040 8424 #define VSR40_RX_ANA25G_CONTROL11_SEL_TESTCLK8T_ALIGN 0 8425 #define VSR40_RX_ANA25G_CONTROL11_SEL_TESTCLK8T_BITS 1 8426 #define VSR40_RX_ANA25G_CONTROL11_SEL_TESTCLK8T_SHIFT 6 8427 8428 /* vsr40_rx_ana25g :: control11 :: Slcr_offset_cal_en [05:05] */ 8429 #define VSR40_RX_ANA25G_CONTROL11_SLCR_OFFSET_CAL_EN_MASK 0x0020 8430 #define VSR40_RX_ANA25G_CONTROL11_SLCR_OFFSET_CAL_EN_ALIGN 0 8431 #define VSR40_RX_ANA25G_CONTROL11_SLCR_OFFSET_CAL_EN_BITS 1 8432 #define VSR40_RX_ANA25G_CONTROL11_SLCR_OFFSET_CAL_EN_SHIFT 5 8433 8434 /* vsr40_rx_ana25g :: control11 :: Slcr_offset_ib_Ctrl [04:02] */ 8435 #define VSR40_RX_ANA25G_CONTROL11_SLCR_OFFSET_IB_CTRL_MASK 0x001c 8436 #define VSR40_RX_ANA25G_CONTROL11_SLCR_OFFSET_IB_CTRL_ALIGN 0 8437 #define VSR40_RX_ANA25G_CONTROL11_SLCR_OFFSET_IB_CTRL_BITS 3 8438 #define VSR40_RX_ANA25G_CONTROL11_SLCR_OFFSET_IB_CTRL_SHIFT 2 8439 8440 /* vsr40_rx_ana25g :: control11 :: Rx_offset_Z_mode [01:01] */ 8441 #define VSR40_RX_ANA25G_CONTROL11_RX_OFFSET_Z_MODE_MASK 0x0002 8442 #define VSR40_RX_ANA25G_CONTROL11_RX_OFFSET_Z_MODE_ALIGN 0 8443 #define VSR40_RX_ANA25G_CONTROL11_RX_OFFSET_Z_MODE_BITS 1 8444 #define VSR40_RX_ANA25G_CONTROL11_RX_OFFSET_Z_MODE_SHIFT 1 8445 8446 /* vsr40_rx_ana25g :: control11 :: Rx_pwrdn_offset [00:00] */ 8447 #define VSR40_RX_ANA25G_CONTROL11_RX_PWRDN_OFFSET_MASK 0x0001 8448 #define VSR40_RX_ANA25G_CONTROL11_RX_PWRDN_OFFSET_ALIGN 0 8449 #define VSR40_RX_ANA25G_CONTROL11_RX_PWRDN_OFFSET_BITS 1 8450 #define VSR40_RX_ANA25G_CONTROL11_RX_PWRDN_OFFSET_SHIFT 0 8451 8452 8453 /**************************************************************************** 8454 * vsr40_rx_ana25g :: control10 8455 */ 8456 /* vsr40_rx_ana25g :: control10 :: Idac_offset_Z1 [15:12] */ 8457 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_Z1_MASK 0xf000 8458 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_Z1_ALIGN 0 8459 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_Z1_BITS 4 8460 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_Z1_SHIFT 12 8461 8462 /* vsr40_rx_ana25g :: control10 :: Idac_offset_Z0 [11:08] */ 8463 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_Z0_MASK 0x0f00 8464 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_Z0_ALIGN 0 8465 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_Z0_BITS 4 8466 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_Z0_SHIFT 8 8467 8468 /* vsr40_rx_ana25g :: control10 :: Idac_offset_P1 [07:04] */ 8469 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_P1_MASK 0x00f0 8470 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_P1_ALIGN 0 8471 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_P1_BITS 4 8472 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_P1_SHIFT 4 8473 8474 /* vsr40_rx_ana25g :: control10 :: Idac_offset_P0 [03:00] */ 8475 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_P0_MASK 0x000f 8476 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_P0_ALIGN 0 8477 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_P0_BITS 4 8478 #define VSR40_RX_ANA25G_CONTROL10_IDAC_OFFSET_P0_SHIFT 0 8479 8480 8481 /**************************************************************************** 8482 * vsr40_rx_ana25g :: control9 8483 */ 8484 /* vsr40_rx_ana25g :: control9 :: clk_test_sel_1_0 [15:14] */ 8485 #define VSR40_RX_ANA25G_CONTROL9_CLK_TEST_SEL_1_0_MASK 0xc000 8486 #define VSR40_RX_ANA25G_CONTROL9_CLK_TEST_SEL_1_0_ALIGN 0 8487 #define VSR40_RX_ANA25G_CONTROL9_CLK_TEST_SEL_1_0_BITS 2 8488 #define VSR40_RX_ANA25G_CONTROL9_CLK_TEST_SEL_1_0_SHIFT 14 8489 8490 /* vsr40_rx_ana25g :: control9 :: susm_sel_10g_mode_frc [13:13] */ 8491 #define VSR40_RX_ANA25G_CONTROL9_SUSM_SEL_10G_MODE_FRC_MASK 0x2000 8492 #define VSR40_RX_ANA25G_CONTROL9_SUSM_SEL_10G_MODE_FRC_ALIGN 0 8493 #define VSR40_RX_ANA25G_CONTROL9_SUSM_SEL_10G_MODE_FRC_BITS 1 8494 #define VSR40_RX_ANA25G_CONTROL9_SUSM_SEL_10G_MODE_FRC_SHIFT 13 8495 8496 /* vsr40_rx_ana25g :: control9 :: susm_sel_10g_mode [12:12] */ 8497 #define VSR40_RX_ANA25G_CONTROL9_SUSM_SEL_10G_MODE_MASK 0x1000 8498 #define VSR40_RX_ANA25G_CONTROL9_SUSM_SEL_10G_MODE_ALIGN 0 8499 #define VSR40_RX_ANA25G_CONTROL9_SUSM_SEL_10G_MODE_BITS 1 8500 #define VSR40_RX_ANA25G_CONTROL9_SUSM_SEL_10G_MODE_SHIFT 12 8501 8502 /* vsr40_rx_ana25g :: control9 :: dis_intofst [11:11] */ 8503 #define VSR40_RX_ANA25G_CONTROL9_DIS_INTOFST_MASK 0x0800 8504 #define VSR40_RX_ANA25G_CONTROL9_DIS_INTOFST_ALIGN 0 8505 #define VSR40_RX_ANA25G_CONTROL9_DIS_INTOFST_BITS 1 8506 #define VSR40_RX_ANA25G_CONTROL9_DIS_INTOFST_SHIFT 11 8507 8508 /* vsr40_rx_ana25g :: control9 :: rx_mref_selhigh [10:10] */ 8509 #define VSR40_RX_ANA25G_CONTROL9_RX_MREF_SELHIGH_MASK 0x0400 8510 #define VSR40_RX_ANA25G_CONTROL9_RX_MREF_SELHIGH_ALIGN 0 8511 #define VSR40_RX_ANA25G_CONTROL9_RX_MREF_SELHIGH_BITS 1 8512 #define VSR40_RX_ANA25G_CONTROL9_RX_MREF_SELHIGH_SHIFT 10 8513 8514 /* vsr40_rx_ana25g :: control9 :: rclk_test_enable [09:09] */ 8515 #define VSR40_RX_ANA25G_CONTROL9_RCLK_TEST_ENABLE_MASK 0x0200 8516 #define VSR40_RX_ANA25G_CONTROL9_RCLK_TEST_ENABLE_ALIGN 0 8517 #define VSR40_RX_ANA25G_CONTROL9_RCLK_TEST_ENABLE_BITS 1 8518 #define VSR40_RX_ANA25G_CONTROL9_RCLK_TEST_ENABLE_SHIFT 9 8519 8520 /* vsr40_rx_ana25g :: control9 :: rclk_test_lane_sel [08:08] */ 8521 #define VSR40_RX_ANA25G_CONTROL9_RCLK_TEST_LANE_SEL_MASK 0x0100 8522 #define VSR40_RX_ANA25G_CONTROL9_RCLK_TEST_LANE_SEL_ALIGN 0 8523 #define VSR40_RX_ANA25G_CONTROL9_RCLK_TEST_LANE_SEL_BITS 1 8524 #define VSR40_RX_ANA25G_CONTROL9_RCLK_TEST_LANE_SEL_SHIFT 8 8525 8526 /* vsr40_rx_ana25g :: control9 :: rsrvd_for_eco_104 [07:07] */ 8527 #define VSR40_RX_ANA25G_CONTROL9_RSRVD_FOR_ECO_104_MASK 0x0080 8528 #define VSR40_RX_ANA25G_CONTROL9_RSRVD_FOR_ECO_104_ALIGN 0 8529 #define VSR40_RX_ANA25G_CONTROL9_RSRVD_FOR_ECO_104_BITS 1 8530 #define VSR40_RX_ANA25G_CONTROL9_RSRVD_FOR_ECO_104_SHIFT 7 8531 8532 /* vsr40_rx_ana25g :: control9 :: Clk2Tdiv_ibp_ctrl [06:04] */ 8533 #define VSR40_RX_ANA25G_CONTROL9_CLK2TDIV_IBP_CTRL_MASK 0x0070 8534 #define VSR40_RX_ANA25G_CONTROL9_CLK2TDIV_IBP_CTRL_ALIGN 0 8535 #define VSR40_RX_ANA25G_CONTROL9_CLK2TDIV_IBP_CTRL_BITS 3 8536 #define VSR40_RX_ANA25G_CONTROL9_CLK2TDIV_IBP_CTRL_SHIFT 4 8537 8538 /* vsr40_rx_ana25g :: control9 :: reserved0 [03:03] */ 8539 #define VSR40_RX_ANA25G_CONTROL9_RESERVED0_MASK 0x0008 8540 #define VSR40_RX_ANA25G_CONTROL9_RESERVED0_ALIGN 0 8541 #define VSR40_RX_ANA25G_CONTROL9_RESERVED0_BITS 1 8542 #define VSR40_RX_ANA25G_CONTROL9_RESERVED0_SHIFT 3 8543 8544 /* vsr40_rx_ana25g :: control9 :: Pibufout_ib_Ctrl [02:00] */ 8545 #define VSR40_RX_ANA25G_CONTROL9_PIBUFOUT_IB_CTRL_MASK 0x0007 8546 #define VSR40_RX_ANA25G_CONTROL9_PIBUFOUT_IB_CTRL_ALIGN 0 8547 #define VSR40_RX_ANA25G_CONTROL9_PIBUFOUT_IB_CTRL_BITS 3 8548 #define VSR40_RX_ANA25G_CONTROL9_PIBUFOUT_IB_CTRL_SHIFT 0 8549 8550 8551 /**************************************************************************** 8552 * vsr40_rx_ana25g :: control8 8553 */ 8554 /* vsr40_rx_ana25g :: control8 :: reserved0 [15:06] */ 8555 #define VSR40_RX_ANA25G_CONTROL8_RESERVED0_MASK 0xffc0 8556 #define VSR40_RX_ANA25G_CONTROL8_RESERVED0_ALIGN 0 8557 #define VSR40_RX_ANA25G_CONTROL8_RESERVED0_BITS 10 8558 #define VSR40_RX_ANA25G_CONTROL8_RESERVED0_SHIFT 6 8559 8560 /* vsr40_rx_ana25g :: control8 :: Pibufin_ib_ctrl [05:03] */ 8561 #define VSR40_RX_ANA25G_CONTROL8_PIBUFIN_IB_CTRL_MASK 0x0038 8562 #define VSR40_RX_ANA25G_CONTROL8_PIBUFIN_IB_CTRL_ALIGN 0 8563 #define VSR40_RX_ANA25G_CONTROL8_PIBUFIN_IB_CTRL_BITS 3 8564 #define VSR40_RX_ANA25G_CONTROL8_PIBUFIN_IB_CTRL_SHIFT 3 8565 8566 /* vsr40_rx_ana25g :: control8 :: Laf_ib_ctrl [02:00] */ 8567 #define VSR40_RX_ANA25G_CONTROL8_LAF_IB_CTRL_MASK 0x0007 8568 #define VSR40_RX_ANA25G_CONTROL8_LAF_IB_CTRL_ALIGN 0 8569 #define VSR40_RX_ANA25G_CONTROL8_LAF_IB_CTRL_BITS 3 8570 #define VSR40_RX_ANA25G_CONTROL8_LAF_IB_CTRL_SHIFT 0 8571 8572 8573 /**************************************************************************** 8574 * vsr40_rx_ana25g :: control7 8575 */ 8576 /* vsr40_rx_ana25g :: control7 :: reserved0 [15:14] */ 8577 #define VSR40_RX_ANA25G_CONTROL7_RESERVED0_MASK 0xc000 8578 #define VSR40_RX_ANA25G_CONTROL7_RESERVED0_ALIGN 0 8579 #define VSR40_RX_ANA25G_CONTROL7_RESERVED0_BITS 2 8580 #define VSR40_RX_ANA25G_CONTROL7_RESERVED0_SHIFT 14 8581 8582 /* vsr40_rx_ana25g :: control7 :: rsrvd_for_eco_91_90 [13:12] */ 8583 #define VSR40_RX_ANA25G_CONTROL7_RSRVD_FOR_ECO_91_90_MASK 0x3000 8584 #define VSR40_RX_ANA25G_CONTROL7_RSRVD_FOR_ECO_91_90_ALIGN 0 8585 #define VSR40_RX_ANA25G_CONTROL7_RSRVD_FOR_ECO_91_90_BITS 2 8586 #define VSR40_RX_ANA25G_CONTROL7_RSRVD_FOR_ECO_91_90_SHIFT 12 8587 8588 /* vsr40_rx_ana25g :: control7 :: Invert_zero_10g_pd [11:11] */ 8589 #define VSR40_RX_ANA25G_CONTROL7_INVERT_ZERO_10G_PD_MASK 0x0800 8590 #define VSR40_RX_ANA25G_CONTROL7_INVERT_ZERO_10G_PD_ALIGN 0 8591 #define VSR40_RX_ANA25G_CONTROL7_INVERT_ZERO_10G_PD_BITS 1 8592 #define VSR40_RX_ANA25G_CONTROL7_INVERT_ZERO_10G_PD_SHIFT 11 8593 8594 /* vsr40_rx_ana25g :: control7 :: Invert_zero_25g [10:10] */ 8595 #define VSR40_RX_ANA25G_CONTROL7_INVERT_ZERO_25G_MASK 0x0400 8596 #define VSR40_RX_ANA25G_CONTROL7_INVERT_ZERO_25G_ALIGN 0 8597 #define VSR40_RX_ANA25G_CONTROL7_INVERT_ZERO_25G_BITS 1 8598 #define VSR40_RX_ANA25G_CONTROL7_INVERT_ZERO_25G_SHIFT 10 8599 8600 /* vsr40_rx_ana25g :: control7 :: Pkz_enind [09:09] */ 8601 #define VSR40_RX_ANA25G_CONTROL7_PKZ_ENIND_MASK 0x0200 8602 #define VSR40_RX_ANA25G_CONTROL7_PKZ_ENIND_ALIGN 0 8603 #define VSR40_RX_ANA25G_CONTROL7_PKZ_ENIND_BITS 1 8604 #define VSR40_RX_ANA25G_CONTROL7_PKZ_ENIND_SHIFT 9 8605 8606 /* vsr40_rx_ana25g :: control7 :: Mon_enind [08:07] */ 8607 #define VSR40_RX_ANA25G_CONTROL7_MON_ENIND_MASK 0x0180 8608 #define VSR40_RX_ANA25G_CONTROL7_MON_ENIND_ALIGN 0 8609 #define VSR40_RX_ANA25G_CONTROL7_MON_ENIND_BITS 2 8610 #define VSR40_RX_ANA25G_CONTROL7_MON_ENIND_SHIFT 7 8611 8612 /* vsr40_rx_ana25g :: control7 :: Invert_peak [06:06] */ 8613 #define VSR40_RX_ANA25G_CONTROL7_INVERT_PEAK_MASK 0x0040 8614 #define VSR40_RX_ANA25G_CONTROL7_INVERT_PEAK_ALIGN 0 8615 #define VSR40_RX_ANA25G_CONTROL7_INVERT_PEAK_BITS 1 8616 #define VSR40_RX_ANA25G_CONTROL7_INVERT_PEAK_SHIFT 6 8617 8618 /* vsr40_rx_ana25g :: control7 :: Clk_pkdet_ref [05:03] */ 8619 #define VSR40_RX_ANA25G_CONTROL7_CLK_PKDET_REF_MASK 0x0038 8620 #define VSR40_RX_ANA25G_CONTROL7_CLK_PKDET_REF_ALIGN 0 8621 #define VSR40_RX_ANA25G_CONTROL7_CLK_PKDET_REF_BITS 3 8622 #define VSR40_RX_ANA25G_CONTROL7_CLK_PKDET_REF_SHIFT 3 8623 8624 /* vsr40_rx_ana25g :: control7 :: Mon_ref_ib_ctrl [02:00] */ 8625 #define VSR40_RX_ANA25G_CONTROL7_MON_REF_IB_CTRL_MASK 0x0007 8626 #define VSR40_RX_ANA25G_CONTROL7_MON_REF_IB_CTRL_ALIGN 0 8627 #define VSR40_RX_ANA25G_CONTROL7_MON_REF_IB_CTRL_BITS 3 8628 #define VSR40_RX_ANA25G_CONTROL7_MON_REF_IB_CTRL_SHIFT 0 8629 8630 8631 /**************************************************************************** 8632 * vsr40_rx_ana25g :: control6 8633 */ 8634 /* vsr40_rx_ana25g :: control6 :: Rx_pon_PI_frc [15:15] */ 8635 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_PI_FRC_MASK 0x8000 8636 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_PI_FRC_ALIGN 0 8637 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_PI_FRC_BITS 1 8638 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_PI_FRC_SHIFT 15 8639 8640 /* vsr40_rx_ana25g :: control6 :: Rx_pon_PI [14:12] */ 8641 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_PI_MASK 0x7000 8642 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_PI_ALIGN 0 8643 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_PI_BITS 3 8644 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_PI_SHIFT 12 8645 8646 /* vsr40_rx_ana25g :: control6 :: Rx_pon_Div2T_frc [11:11] */ 8647 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_DIV2T_FRC_MASK 0x0800 8648 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_DIV2T_FRC_ALIGN 0 8649 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_DIV2T_FRC_BITS 1 8650 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_DIV2T_FRC_SHIFT 11 8651 8652 /* vsr40_rx_ana25g :: control6 :: Rx_pon_Div2T [10:08] */ 8653 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_DIV2T_MASK 0x0700 8654 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_DIV2T_ALIGN 0 8655 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_DIV2T_BITS 3 8656 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_DIV2T_SHIFT 8 8657 8658 /* vsr40_rx_ana25g :: control6 :: Rx_pon_slicer_frc [07:07] */ 8659 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_SLICER_FRC_MASK 0x0080 8660 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_SLICER_FRC_ALIGN 0 8661 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_SLICER_FRC_BITS 1 8662 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_SLICER_FRC_SHIFT 7 8663 8664 /* vsr40_rx_ana25g :: control6 :: Rx_pon_slicer [06:04] */ 8665 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_SLICER_MASK 0x0070 8666 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_SLICER_ALIGN 0 8667 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_SLICER_BITS 3 8668 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_SLICER_SHIFT 4 8669 8670 /* vsr40_rx_ana25g :: control6 :: Rx_pon_LA_frc [03:03] */ 8671 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_LA_FRC_MASK 0x0008 8672 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_LA_FRC_ALIGN 0 8673 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_LA_FRC_BITS 1 8674 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_LA_FRC_SHIFT 3 8675 8676 /* vsr40_rx_ana25g :: control6 :: Rx_pon_LA [02:00] */ 8677 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_LA_MASK 0x0007 8678 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_LA_ALIGN 0 8679 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_LA_BITS 3 8680 #define VSR40_RX_ANA25G_CONTROL6_RX_PON_LA_SHIFT 0 8681 8682 8683 /**************************************************************************** 8684 * vsr40_rx_ana25g :: control5 8685 */ 8686 /* vsr40_rx_ana25g :: control5 :: reserved0 [15:07] */ 8687 #define VSR40_RX_ANA25G_CONTROL5_RESERVED0_MASK 0xff80 8688 #define VSR40_RX_ANA25G_CONTROL5_RESERVED0_ALIGN 0 8689 #define VSR40_RX_ANA25G_CONTROL5_RESERVED0_BITS 9 8690 #define VSR40_RX_ANA25G_CONTROL5_RESERVED0_SHIFT 7 8691 8692 /* vsr40_rx_ana25g :: control5 :: los_filter_ctrl [06:05] */ 8693 #define VSR40_RX_ANA25G_CONTROL5_LOS_FILTER_CTRL_MASK 0x0060 8694 #define VSR40_RX_ANA25G_CONTROL5_LOS_FILTER_CTRL_ALIGN 0 8695 #define VSR40_RX_ANA25G_CONTROL5_LOS_FILTER_CTRL_BITS 2 8696 #define VSR40_RX_ANA25G_CONTROL5_LOS_FILTER_CTRL_SHIFT 5 8697 8698 /* vsr40_rx_ana25g :: control5 :: los_vth_ctrl [04:02] */ 8699 #define VSR40_RX_ANA25G_CONTROL5_LOS_VTH_CTRL_MASK 0x001c 8700 #define VSR40_RX_ANA25G_CONTROL5_LOS_VTH_CTRL_ALIGN 0 8701 #define VSR40_RX_ANA25G_CONTROL5_LOS_VTH_CTRL_BITS 3 8702 #define VSR40_RX_ANA25G_CONTROL5_LOS_VTH_CTRL_SHIFT 2 8703 8704 /* vsr40_rx_ana25g :: control5 :: los_hysb_frc [01:01] */ 8705 #define VSR40_RX_ANA25G_CONTROL5_LOS_HYSB_FRC_MASK 0x0002 8706 #define VSR40_RX_ANA25G_CONTROL5_LOS_HYSB_FRC_ALIGN 0 8707 #define VSR40_RX_ANA25G_CONTROL5_LOS_HYSB_FRC_BITS 1 8708 #define VSR40_RX_ANA25G_CONTROL5_LOS_HYSB_FRC_SHIFT 1 8709 8710 /* vsr40_rx_ana25g :: control5 :: los_hysb [00:00] */ 8711 #define VSR40_RX_ANA25G_CONTROL5_LOS_HYSB_MASK 0x0001 8712 #define VSR40_RX_ANA25G_CONTROL5_LOS_HYSB_ALIGN 0 8713 #define VSR40_RX_ANA25G_CONTROL5_LOS_HYSB_BITS 1 8714 #define VSR40_RX_ANA25G_CONTROL5_LOS_HYSB_SHIFT 0 8715 8716 8717 /**************************************************************************** 8718 * vsr40_rx_ana25g :: control4 8719 */ 8720 /* vsr40_rx_ana25g :: control4 :: reserved0 [15:15] */ 8721 #define VSR40_RX_ANA25G_CONTROL4_RESERVED0_MASK 0x8000 8722 #define VSR40_RX_ANA25G_CONTROL4_RESERVED0_ALIGN 0 8723 #define VSR40_RX_ANA25G_CONTROL4_RESERVED0_BITS 1 8724 #define VSR40_RX_ANA25G_CONTROL4_RESERVED0_SHIFT 15 8725 8726 /* vsr40_rx_ana25g :: control4 :: Pi_peak_ib_ctrl [14:12] */ 8727 #define VSR40_RX_ANA25G_CONTROL4_PI_PEAK_IB_CTRL_MASK 0x7000 8728 #define VSR40_RX_ANA25G_CONTROL4_PI_PEAK_IB_CTRL_ALIGN 0 8729 #define VSR40_RX_ANA25G_CONTROL4_PI_PEAK_IB_CTRL_BITS 3 8730 #define VSR40_RX_ANA25G_CONTROL4_PI_PEAK_IB_CTRL_SHIFT 12 8731 8732 /* vsr40_rx_ana25g :: control4 :: Pi_zero_ib_ctrl [11:09] */ 8733 #define VSR40_RX_ANA25G_CONTROL4_PI_ZERO_IB_CTRL_MASK 0x0e00 8734 #define VSR40_RX_ANA25G_CONTROL4_PI_ZERO_IB_CTRL_ALIGN 0 8735 #define VSR40_RX_ANA25G_CONTROL4_PI_ZERO_IB_CTRL_BITS 3 8736 #define VSR40_RX_ANA25G_CONTROL4_PI_ZERO_IB_CTRL_SHIFT 9 8737 8738 /* vsr40_rx_ana25g :: control4 :: Pi_mon_ib_ctrl [08:06] */ 8739 #define VSR40_RX_ANA25G_CONTROL4_PI_MON_IB_CTRL_MASK 0x01c0 8740 #define VSR40_RX_ANA25G_CONTROL4_PI_MON_IB_CTRL_ALIGN 0 8741 #define VSR40_RX_ANA25G_CONTROL4_PI_MON_IB_CTRL_BITS 3 8742 #define VSR40_RX_ANA25G_CONTROL4_PI_MON_IB_CTRL_SHIFT 6 8743 8744 /* vsr40_rx_ana25g :: control4 :: en_2Tpin_hicur [05:03] */ 8745 #define VSR40_RX_ANA25G_CONTROL4_EN_2TPIN_HICUR_MASK 0x0038 8746 #define VSR40_RX_ANA25G_CONTROL4_EN_2TPIN_HICUR_ALIGN 0 8747 #define VSR40_RX_ANA25G_CONTROL4_EN_2TPIN_HICUR_BITS 3 8748 #define VSR40_RX_ANA25G_CONTROL4_EN_2TPIN_HICUR_SHIFT 3 8749 8750 /* vsr40_rx_ana25g :: control4 :: susm_pibufout_tbuf_frc [02:02] */ 8751 #define VSR40_RX_ANA25G_CONTROL4_SUSM_PIBUFOUT_TBUF_FRC_MASK 0x0004 8752 #define VSR40_RX_ANA25G_CONTROL4_SUSM_PIBUFOUT_TBUF_FRC_ALIGN 0 8753 #define VSR40_RX_ANA25G_CONTROL4_SUSM_PIBUFOUT_TBUF_FRC_BITS 1 8754 #define VSR40_RX_ANA25G_CONTROL4_SUSM_PIBUFOUT_TBUF_FRC_SHIFT 2 8755 8756 /* vsr40_rx_ana25g :: control4 :: susm_pibufout_tbuf [01:00] */ 8757 #define VSR40_RX_ANA25G_CONTROL4_SUSM_PIBUFOUT_TBUF_MASK 0x0003 8758 #define VSR40_RX_ANA25G_CONTROL4_SUSM_PIBUFOUT_TBUF_ALIGN 0 8759 #define VSR40_RX_ANA25G_CONTROL4_SUSM_PIBUFOUT_TBUF_BITS 2 8760 #define VSR40_RX_ANA25G_CONTROL4_SUSM_PIBUFOUT_TBUF_SHIFT 0 8761 8762 8763 /**************************************************************************** 8764 * vsr40_rx_ana25g :: control3 8765 */ 8766 /* vsr40_rx_ana25g :: control3 :: reserved0 [15:15] */ 8767 #define VSR40_RX_ANA25G_CONTROL3_RESERVED0_MASK 0x8000 8768 #define VSR40_RX_ANA25G_CONTROL3_RESERVED0_ALIGN 0 8769 #define VSR40_RX_ANA25G_CONTROL3_RESERVED0_BITS 1 8770 #define VSR40_RX_ANA25G_CONTROL3_RESERVED0_SHIFT 15 8771 8772 /* vsr40_rx_ana25g :: control3 :: DmuxZ_ib_ctrl [14:12] */ 8773 #define VSR40_RX_ANA25G_CONTROL3_DMUXZ_IB_CTRL_MASK 0x7000 8774 #define VSR40_RX_ANA25G_CONTROL3_DMUXZ_IB_CTRL_ALIGN 0 8775 #define VSR40_RX_ANA25G_CONTROL3_DMUXZ_IB_CTRL_BITS 3 8776 #define VSR40_RX_ANA25G_CONTROL3_DMUXZ_IB_CTRL_SHIFT 12 8777 8778 /* vsr40_rx_ana25g :: control3 :: DmuxP_ib_ctrl [11:09] */ 8779 #define VSR40_RX_ANA25G_CONTROL3_DMUXP_IB_CTRL_MASK 0x0e00 8780 #define VSR40_RX_ANA25G_CONTROL3_DMUXP_IB_CTRL_ALIGN 0 8781 #define VSR40_RX_ANA25G_CONTROL3_DMUXP_IB_CTRL_BITS 3 8782 #define VSR40_RX_ANA25G_CONTROL3_DMUXP_IB_CTRL_SHIFT 9 8783 8784 /* vsr40_rx_ana25g :: control3 :: DmuxM_ib_ctrl [08:06] */ 8785 #define VSR40_RX_ANA25G_CONTROL3_DMUXM_IB_CTRL_MASK 0x01c0 8786 #define VSR40_RX_ANA25G_CONTROL3_DMUXM_IB_CTRL_ALIGN 0 8787 #define VSR40_RX_ANA25G_CONTROL3_DMUXM_IB_CTRL_BITS 3 8788 #define VSR40_RX_ANA25G_CONTROL3_DMUXM_IB_CTRL_SHIFT 6 8789 8790 /* vsr40_rx_ana25g :: control3 :: SlicerP_ib_Ctrl [05:03] */ 8791 #define VSR40_RX_ANA25G_CONTROL3_SLICERP_IB_CTRL_MASK 0x0038 8792 #define VSR40_RX_ANA25G_CONTROL3_SLICERP_IB_CTRL_ALIGN 0 8793 #define VSR40_RX_ANA25G_CONTROL3_SLICERP_IB_CTRL_BITS 3 8794 #define VSR40_RX_ANA25G_CONTROL3_SLICERP_IB_CTRL_SHIFT 3 8795 8796 /* vsr40_rx_ana25g :: control3 :: SlicerZ_ib_Ctrl [02:00] */ 8797 #define VSR40_RX_ANA25G_CONTROL3_SLICERZ_IB_CTRL_MASK 0x0007 8798 #define VSR40_RX_ANA25G_CONTROL3_SLICERZ_IB_CTRL_ALIGN 0 8799 #define VSR40_RX_ANA25G_CONTROL3_SLICERZ_IB_CTRL_BITS 3 8800 #define VSR40_RX_ANA25G_CONTROL3_SLICERZ_IB_CTRL_SHIFT 0 8801 8802 8803 /**************************************************************************** 8804 * vsr40_rx_ana25g :: control2 8805 */ 8806 /* vsr40_rx_ana25g :: control2 :: reserved0 [15:13] */ 8807 #define VSR40_RX_ANA25G_CONTROL2_RESERVED0_MASK 0xe000 8808 #define VSR40_RX_ANA25G_CONTROL2_RESERVED0_ALIGN 0 8809 #define VSR40_RX_ANA25G_CONTROL2_RESERVED0_BITS 3 8810 #define VSR40_RX_ANA25G_CONTROL2_RESERVED0_SHIFT 13 8811 8812 /* vsr40_rx_ana25g :: control2 :: SlicerM_ib_Ctrl [12:10] */ 8813 #define VSR40_RX_ANA25G_CONTROL2_SLICERM_IB_CTRL_MASK 0x1c00 8814 #define VSR40_RX_ANA25G_CONTROL2_SLICERM_IB_CTRL_ALIGN 0 8815 #define VSR40_RX_ANA25G_CONTROL2_SLICERM_IB_CTRL_BITS 3 8816 #define VSR40_RX_ANA25G_CONTROL2_SLICERM_IB_CTRL_SHIFT 10 8817 8818 /* vsr40_rx_ana25g :: control2 :: Clk2Tdiv_ibg_ctrl [09:07] */ 8819 #define VSR40_RX_ANA25G_CONTROL2_CLK2TDIV_IBG_CTRL_MASK 0x0380 8820 #define VSR40_RX_ANA25G_CONTROL2_CLK2TDIV_IBG_CTRL_ALIGN 0 8821 #define VSR40_RX_ANA25G_CONTROL2_CLK2TDIV_IBG_CTRL_BITS 3 8822 #define VSR40_RX_ANA25G_CONTROL2_CLK2TDIV_IBG_CTRL_SHIFT 7 8823 8824 /* vsr40_rx_ana25g :: control2 :: Pkdet_ib_ctrl [06:04] */ 8825 #define VSR40_RX_ANA25G_CONTROL2_PKDET_IB_CTRL_MASK 0x0070 8826 #define VSR40_RX_ANA25G_CONTROL2_PKDET_IB_CTRL_ALIGN 0 8827 #define VSR40_RX_ANA25G_CONTROL2_PKDET_IB_CTRL_BITS 3 8828 #define VSR40_RX_ANA25G_CONTROL2_PKDET_IB_CTRL_SHIFT 4 8829 8830 /* vsr40_rx_ana25g :: control2 :: rsrvd_for_eco_21 [03:03] */ 8831 #define VSR40_RX_ANA25G_CONTROL2_RSRVD_FOR_ECO_21_MASK 0x0008 8832 #define VSR40_RX_ANA25G_CONTROL2_RSRVD_FOR_ECO_21_ALIGN 0 8833 #define VSR40_RX_ANA25G_CONTROL2_RSRVD_FOR_ECO_21_BITS 1 8834 #define VSR40_RX_ANA25G_CONTROL2_RSRVD_FOR_ECO_21_SHIFT 3 8835 8836 /* vsr40_rx_ana25g :: control2 :: LOS_ctrl_n50 [02:00] */ 8837 #define VSR40_RX_ANA25G_CONTROL2_LOS_CTRL_N50_MASK 0x0007 8838 #define VSR40_RX_ANA25G_CONTROL2_LOS_CTRL_N50_ALIGN 0 8839 #define VSR40_RX_ANA25G_CONTROL2_LOS_CTRL_N50_BITS 3 8840 #define VSR40_RX_ANA25G_CONTROL2_LOS_CTRL_N50_SHIFT 0 8841 8842 8843 /**************************************************************************** 8844 * vsr40_rx_ana25g :: control1 8845 */ 8846 /* vsr40_rx_ana25g :: control1 :: reserved0 [15:11] */ 8847 #define VSR40_RX_ANA25G_CONTROL1_RESERVED0_MASK 0xf800 8848 #define VSR40_RX_ANA25G_CONTROL1_RESERVED0_ALIGN 0 8849 #define VSR40_RX_ANA25G_CONTROL1_RESERVED0_BITS 5 8850 #define VSR40_RX_ANA25G_CONTROL1_RESERVED0_SHIFT 11 8851 8852 /* vsr40_rx_ana25g :: control1 :: eq_ib_ctrl [10:07] */ 8853 #define VSR40_RX_ANA25G_CONTROL1_EQ_IB_CTRL_MASK 0x0780 8854 #define VSR40_RX_ANA25G_CONTROL1_EQ_IB_CTRL_ALIGN 0 8855 #define VSR40_RX_ANA25G_CONTROL1_EQ_IB_CTRL_BITS 4 8856 #define VSR40_RX_ANA25G_CONTROL1_EQ_IB_CTRL_SHIFT 7 8857 8858 /* vsr40_rx_ana25g :: control1 :: la_ib_ctrl [06:03] */ 8859 #define VSR40_RX_ANA25G_CONTROL1_LA_IB_CTRL_MASK 0x0078 8860 #define VSR40_RX_ANA25G_CONTROL1_LA_IB_CTRL_ALIGN 0 8861 #define VSR40_RX_ANA25G_CONTROL1_LA_IB_CTRL_BITS 4 8862 #define VSR40_RX_ANA25G_CONTROL1_LA_IB_CTRL_SHIFT 3 8863 8864 /* vsr40_rx_ana25g :: control1 :: en_progc [02:00] */ 8865 #define VSR40_RX_ANA25G_CONTROL1_EN_PROGC_MASK 0x0007 8866 #define VSR40_RX_ANA25G_CONTROL1_EN_PROGC_ALIGN 0 8867 #define VSR40_RX_ANA25G_CONTROL1_EN_PROGC_BITS 3 8868 #define VSR40_RX_ANA25G_CONTROL1_EN_PROGC_SHIFT 0 8869 8870 8871 /**************************************************************************** 8872 * vsr40_rx_ana25g :: control0 8873 */ 8874 /* vsr40_rx_ana25g :: control0 :: reserved0 [15:07] */ 8875 #define VSR40_RX_ANA25G_CONTROL0_RESERVED0_MASK 0xff80 8876 #define VSR40_RX_ANA25G_CONTROL0_RESERVED0_ALIGN 0 8877 #define VSR40_RX_ANA25G_CONTROL0_RESERVED0_BITS 9 8878 #define VSR40_RX_ANA25G_CONTROL0_RESERVED0_SHIFT 7 8879 8880 /* vsr40_rx_ana25g :: control0 :: Rx_pwrdn_zero [06:06] */ 8881 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_ZERO_MASK 0x0040 8882 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_ZERO_ALIGN 0 8883 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_ZERO_BITS 1 8884 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_ZERO_SHIFT 6 8885 8886 /* vsr40_rx_ana25g :: control0 :: los_pwrdn [05:05] */ 8887 #define VSR40_RX_ANA25G_CONTROL0_LOS_PWRDN_MASK 0x0020 8888 #define VSR40_RX_ANA25G_CONTROL0_LOS_PWRDN_ALIGN 0 8889 #define VSR40_RX_ANA25G_CONTROL0_LOS_PWRDN_BITS 1 8890 #define VSR40_RX_ANA25G_CONTROL0_LOS_PWRDN_SHIFT 5 8891 8892 /* vsr40_rx_ana25g :: control0 :: Rx_pwrdn_mon [04:04] */ 8893 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_MON_MASK 0x0010 8894 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_MON_ALIGN 0 8895 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_MON_BITS 1 8896 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_MON_SHIFT 4 8897 8898 /* vsr40_rx_ana25g :: control0 :: Rx_pwrdn_slp [03:03] */ 8899 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_SLP_MASK 0x0008 8900 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_SLP_ALIGN 0 8901 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_SLP_BITS 1 8902 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_SLP_SHIFT 3 8903 8904 /* vsr40_rx_ana25g :: control0 :: Rx_pwrdn_la [02:02] */ 8905 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_LA_MASK 0x0004 8906 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_LA_ALIGN 0 8907 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_LA_BITS 1 8908 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_LA_SHIFT 2 8909 8910 /* vsr40_rx_ana25g :: control0 :: Rx_pwrdn_pkdet [01:01] */ 8911 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_PKDET_MASK 0x0002 8912 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_PKDET_ALIGN 0 8913 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_PKDET_BITS 1 8914 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_PKDET_SHIFT 1 8915 8916 /* vsr40_rx_ana25g :: control0 :: Rx_pwrdn_peak [00:00] */ 8917 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_PEAK_MASK 0x0001 8918 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_PEAK_ALIGN 0 8919 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_PEAK_BITS 1 8920 #define VSR40_RX_ANA25G_CONTROL0_RX_PWRDN_PEAK_SHIFT 0 8921 8922 8923 /**************************************************************************** 8924 * vsr40_rx_ana25g :: ana_if_control0 8925 */ 8926 /* vsr40_rx_ana25g :: ana_if_control0 :: reserved0 [15:12] */ 8927 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RESERVED0_MASK 0xf000 8928 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RESERVED0_ALIGN 0 8929 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RESERVED0_BITS 4 8930 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RESERVED0_SHIFT 12 8931 8932 /* vsr40_rx_ana25g :: ana_if_control0 :: man_rx_mref [11:11] */ 8933 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_MAN_RX_MREF_MASK 0x0800 8934 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_MAN_RX_MREF_ALIGN 0 8935 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_MAN_RX_MREF_BITS 1 8936 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_MAN_RX_MREF_SHIFT 11 8937 8938 /* vsr40_rx_ana25g :: ana_if_control0 :: rx_mref [10:05] */ 8939 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RX_MREF_MASK 0x07e0 8940 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RX_MREF_ALIGN 0 8941 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RX_MREF_BITS 6 8942 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RX_MREF_SHIFT 5 8943 8944 /* vsr40_rx_ana25g :: ana_if_control0 :: man_rx_eq_en [04:04] */ 8945 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_MAN_RX_EQ_EN_MASK 0x0010 8946 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_MAN_RX_EQ_EN_ALIGN 0 8947 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_MAN_RX_EQ_EN_BITS 1 8948 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_MAN_RX_EQ_EN_SHIFT 4 8949 8950 /* vsr40_rx_ana25g :: ana_if_control0 :: rx_eq [03:00] */ 8951 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RX_EQ_MASK 0x000f 8952 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RX_EQ_ALIGN 0 8953 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RX_EQ_BITS 4 8954 #define VSR40_RX_ANA25G_ANA_IF_CONTROL0_RX_EQ_SHIFT 0 8955 8956 8957 /**************************************************************************** 8958 * vsr40_rx_ana25g :: ana_if_status 8959 */ 8960 /* vsr40_rx_ana25g :: ana_if_status :: reserved0 [15:12] */ 8961 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RESERVED0_MASK 0xf000 8962 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RESERVED0_ALIGN 0 8963 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RESERVED0_BITS 4 8964 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RESERVED0_SHIFT 12 8965 8966 /* vsr40_rx_ana25g :: ana_if_status :: rx_clk_pkdet_low_dgltch [11:11] */ 8967 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_CLK_PKDET_LOW_DGLTCH_MASK 0x0800 8968 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_CLK_PKDET_LOW_DGLTCH_ALIGN 0 8969 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_CLK_PKDET_LOW_DGLTCH_BITS 1 8970 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_CLK_PKDET_LOW_DGLTCH_SHIFT 11 8971 8972 /* vsr40_rx_ana25g :: ana_if_status :: rx_clk_pkdet_high_dgltch [10:10] */ 8973 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_CLK_PKDET_HIGH_DGLTCH_MASK 0x0400 8974 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_CLK_PKDET_HIGH_DGLTCH_ALIGN 0 8975 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_CLK_PKDET_HIGH_DGLTCH_BITS 1 8976 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_CLK_PKDET_HIGH_DGLTCH_SHIFT 10 8977 8978 /* vsr40_rx_ana25g :: ana_if_status :: rx_mref_gray_read [09:04] */ 8979 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_MREF_GRAY_READ_MASK 0x03f0 8980 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_MREF_GRAY_READ_ALIGN 0 8981 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_MREF_GRAY_READ_BITS 6 8982 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_MREF_GRAY_READ_SHIFT 4 8983 8984 /* vsr40_rx_ana25g :: ana_if_status :: rx_eq_gray_read [03:00] */ 8985 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_EQ_GRAY_READ_MASK 0x000f 8986 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_EQ_GRAY_READ_ALIGN 0 8987 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_EQ_GRAY_READ_BITS 4 8988 #define VSR40_RX_ANA25G_ANA_IF_STATUS_RX_EQ_GRAY_READ_SHIFT 0 8989 8990 8991 /**************************************************************************** 8992 * vsr40_rx_dig_regs_regs 8993 */ 8994 /**************************************************************************** 8995 * vsr40_rx_dig_regs :: cdr_control 8996 */ 8997 /* vsr40_rx_dig_regs :: cdr_control :: reserved_for_eco0 [15:08] */ 8998 #define VSR40_RX_DIG_REGS_CDR_CONTROL_RESERVED_FOR_ECO0_MASK 0xff00 8999 #define VSR40_RX_DIG_REGS_CDR_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 9000 #define VSR40_RX_DIG_REGS_CDR_CONTROL_RESERVED_FOR_ECO0_BITS 8 9001 #define VSR40_RX_DIG_REGS_CDR_CONTROL_RESERVED_FOR_ECO0_SHIFT 8 9002 9003 /* vsr40_rx_dig_regs :: cdr_control :: cdrlock_status_ln3 [07:07] */ 9004 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN3_MASK 0x0080 9005 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN3_ALIGN 0 9006 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN3_BITS 1 9007 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN3_SHIFT 7 9008 9009 /* vsr40_rx_dig_regs :: cdr_control :: cdrlock_status_ln2 [06:06] */ 9010 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN2_MASK 0x0040 9011 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN2_ALIGN 0 9012 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN2_BITS 1 9013 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN2_SHIFT 6 9014 9015 /* vsr40_rx_dig_regs :: cdr_control :: cdrlock_status_ln1 [05:05] */ 9016 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN1_MASK 0x0020 9017 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN1_ALIGN 0 9018 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN1_BITS 1 9019 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN1_SHIFT 5 9020 9021 /* vsr40_rx_dig_regs :: cdr_control :: cdrlock_status_ln0 [04:04] */ 9022 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN0_MASK 0x0010 9023 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN0_ALIGN 0 9024 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN0_BITS 1 9025 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_STATUS_LN0_SHIFT 4 9026 9027 /* vsr40_rx_dig_regs :: cdr_control :: cdrlock_ln3 [03:03] */ 9028 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN3_MASK 0x0008 9029 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN3_ALIGN 0 9030 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN3_BITS 1 9031 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN3_SHIFT 3 9032 9033 /* vsr40_rx_dig_regs :: cdr_control :: cdrlock_ln2 [02:02] */ 9034 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN2_MASK 0x0004 9035 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN2_ALIGN 0 9036 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN2_BITS 1 9037 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN2_SHIFT 2 9038 9039 /* vsr40_rx_dig_regs :: cdr_control :: cdrlock_ln1 [01:01] */ 9040 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN1_MASK 0x0002 9041 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN1_ALIGN 0 9042 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN1_BITS 1 9043 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN1_SHIFT 1 9044 9045 /* vsr40_rx_dig_regs :: cdr_control :: cdrlock_ln0 [00:00] */ 9046 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN0_MASK 0x0001 9047 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN0_ALIGN 0 9048 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN0_BITS 1 9049 #define VSR40_RX_DIG_REGS_CDR_CONTROL_CDRLOCK_LN0_SHIFT 0 9050 9051 9052 /**************************************************************************** 9053 * vsr40_rx_dig_regs :: reset_control 9054 */ 9055 /* vsr40_rx_dig_regs :: reset_control :: rescal_reset_ovrd [15:15] */ 9056 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESCAL_RESET_OVRD_MASK 0x8000 9057 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESCAL_RESET_OVRD_ALIGN 0 9058 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESCAL_RESET_OVRD_BITS 1 9059 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESCAL_RESET_OVRD_SHIFT 15 9060 9061 /* vsr40_rx_dig_regs :: reset_control :: pll_pwrdn_ovrd [14:14] */ 9062 #define VSR40_RX_DIG_REGS_RESET_CONTROL_PLL_PWRDN_OVRD_MASK 0x4000 9063 #define VSR40_RX_DIG_REGS_RESET_CONTROL_PLL_PWRDN_OVRD_ALIGN 0 9064 #define VSR40_RX_DIG_REGS_RESET_CONTROL_PLL_PWRDN_OVRD_BITS 1 9065 #define VSR40_RX_DIG_REGS_RESET_CONTROL_PLL_PWRDN_OVRD_SHIFT 14 9066 9067 /* vsr40_rx_dig_regs :: reset_control :: reserved_for_eco0 [13:12] */ 9068 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO0_MASK 0x3000 9069 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 9070 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO0_BITS 2 9071 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO0_SHIFT 12 9072 9073 /* vsr40_rx_dig_regs :: reset_control :: hs_ln3_rstb [11:11] */ 9074 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN3_RSTB_MASK 0x0800 9075 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN3_RSTB_ALIGN 0 9076 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN3_RSTB_BITS 1 9077 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN3_RSTB_SHIFT 11 9078 9079 /* vsr40_rx_dig_regs :: reset_control :: hs_ln2_rstb [10:10] */ 9080 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN2_RSTB_MASK 0x0400 9081 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN2_RSTB_ALIGN 0 9082 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN2_RSTB_BITS 1 9083 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN2_RSTB_SHIFT 10 9084 9085 /* vsr40_rx_dig_regs :: reset_control :: hs_ln1_rstb [09:09] */ 9086 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN1_RSTB_MASK 0x0200 9087 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN1_RSTB_ALIGN 0 9088 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN1_RSTB_BITS 1 9089 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN1_RSTB_SHIFT 9 9090 9091 /* vsr40_rx_dig_regs :: reset_control :: hs_ln0_rstb [08:08] */ 9092 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN0_RSTB_MASK 0x0100 9093 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN0_RSTB_ALIGN 0 9094 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN0_RSTB_BITS 1 9095 #define VSR40_RX_DIG_REGS_RESET_CONTROL_HS_LN0_RSTB_SHIFT 8 9096 9097 /* vsr40_rx_dig_regs :: reset_control :: reserved_for_eco1 [07:02] */ 9098 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO1_MASK 0x00fc 9099 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO1_ALIGN 0 9100 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO1_BITS 6 9101 #define VSR40_RX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO1_SHIFT 2 9102 9103 /* vsr40_rx_dig_regs :: reset_control :: cal_rstb [01:01] */ 9104 #define VSR40_RX_DIG_REGS_RESET_CONTROL_CAL_RSTB_MASK 0x0002 9105 #define VSR40_RX_DIG_REGS_RESET_CONTROL_CAL_RSTB_ALIGN 0 9106 #define VSR40_RX_DIG_REGS_RESET_CONTROL_CAL_RSTB_BITS 1 9107 #define VSR40_RX_DIG_REGS_RESET_CONTROL_CAL_RSTB_SHIFT 1 9108 9109 /* vsr40_rx_dig_regs :: reset_control :: lkdt_rstb [00:00] */ 9110 #define VSR40_RX_DIG_REGS_RESET_CONTROL_LKDT_RSTB_MASK 0x0001 9111 #define VSR40_RX_DIG_REGS_RESET_CONTROL_LKDT_RSTB_ALIGN 0 9112 #define VSR40_RX_DIG_REGS_RESET_CONTROL_LKDT_RSTB_BITS 1 9113 #define VSR40_RX_DIG_REGS_RESET_CONTROL_LKDT_RSTB_SHIFT 0 9114 9115 9116 /**************************************************************************** 9117 * vsr40_rx_dig_regs :: clk_control 9118 */ 9119 /* vsr40_rx_dig_regs :: clk_control :: reserved_for_eco0 [15:00] */ 9120 #define VSR40_RX_DIG_REGS_CLK_CONTROL_RESERVED_FOR_ECO0_MASK 0xffff 9121 #define VSR40_RX_DIG_REGS_CLK_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 9122 #define VSR40_RX_DIG_REGS_CLK_CONTROL_RESERVED_FOR_ECO0_BITS 16 9123 #define VSR40_RX_DIG_REGS_CLK_CONTROL_RESERVED_FOR_ECO0_SHIFT 0 9124 9125 9126 /**************************************************************************** 9127 * vsr40_rx_dig_regs :: vcocal_control 9128 */ 9129 /* vsr40_rx_dig_regs :: vcocal_control :: reserved_for_eco0 [15:03] */ 9130 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_RESERVED_FOR_ECO0_MASK 0xfff8 9131 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 9132 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_RESERVED_FOR_ECO0_BITS 13 9133 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_RESERVED_FOR_ECO0_SHIFT 3 9134 9135 /* vsr40_rx_dig_regs :: vcocal_control :: cal_th [02:01] */ 9136 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_CAL_TH_MASK 0x0006 9137 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_CAL_TH_ALIGN 0 9138 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_CAL_TH_BITS 2 9139 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_CAL_TH_SHIFT 1 9140 9141 /* vsr40_rx_dig_regs :: vcocal_control :: cap_delay [00:00] */ 9142 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_CAP_DELAY_MASK 0x0001 9143 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_CAP_DELAY_ALIGN 0 9144 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_CAP_DELAY_BITS 1 9145 #define VSR40_RX_DIG_REGS_VCOCAL_CONTROL_CAP_DELAY_SHIFT 0 9146 9147 9148 /**************************************************************************** 9149 * vsr40_rx_dig_regs :: lockdet_control1 9150 */ 9151 /* vsr40_rx_dig_regs :: lockdet_control1 :: lkdt_assrt_cmpr [15:00] */ 9152 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL1_LKDT_ASSRT_CMPR_MASK 0xffff 9153 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL1_LKDT_ASSRT_CMPR_ALIGN 0 9154 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL1_LKDT_ASSRT_CMPR_BITS 16 9155 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL1_LKDT_ASSRT_CMPR_SHIFT 0 9156 9157 9158 /**************************************************************************** 9159 * vsr40_rx_dig_regs :: lockdet_control2 9160 */ 9161 /* vsr40_rx_dig_regs :: lockdet_control2 :: lkdt_deassrt_cmpr [15:00] */ 9162 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL2_LKDT_DEASSRT_CMPR_MASK 0xffff 9163 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL2_LKDT_DEASSRT_CMPR_ALIGN 0 9164 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL2_LKDT_DEASSRT_CMPR_BITS 16 9165 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL2_LKDT_DEASSRT_CMPR_SHIFT 0 9166 9167 9168 /**************************************************************************** 9169 * vsr40_rx_dig_regs :: lockdet_control3 9170 */ 9171 /* vsr40_rx_dig_regs :: lockdet_control3 :: lkdt_byp [15:15] */ 9172 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_LKDT_BYP_MASK 0x8000 9173 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_LKDT_BYP_ALIGN 0 9174 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_LKDT_BYP_BITS 1 9175 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_LKDT_BYP_SHIFT 15 9176 9177 /* vsr40_rx_dig_regs :: lockdet_control3 :: lkdt_cnt [14:12] */ 9178 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_LKDT_CNT_MASK 0x7000 9179 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_LKDT_CNT_ALIGN 0 9180 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_LKDT_CNT_BITS 3 9181 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_LKDT_CNT_SHIFT 12 9182 9183 /* vsr40_rx_dig_regs :: lockdet_control3 :: ppm_offset_deassrt [11:06] */ 9184 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_DEASSRT_MASK 0x0fc0 9185 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_DEASSRT_ALIGN 0 9186 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_DEASSRT_BITS 6 9187 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_DEASSRT_SHIFT 6 9188 9189 /* vsr40_rx_dig_regs :: lockdet_control3 :: ppm_offset_assrt [05:00] */ 9190 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_ASSRT_MASK 0x003f 9191 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_ASSRT_ALIGN 0 9192 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_ASSRT_BITS 6 9193 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_ASSRT_SHIFT 0 9194 9195 9196 /**************************************************************************** 9197 * vsr40_rx_dig_regs :: lockdet_control4 9198 */ 9199 /* vsr40_rx_dig_regs :: lockdet_control4 :: reserved_for_eco0 [15:03] */ 9200 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4_RESERVED_FOR_ECO0_MASK 0xfff8 9201 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4_RESERVED_FOR_ECO0_ALIGN 0 9202 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4_RESERVED_FOR_ECO0_BITS 13 9203 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4_RESERVED_FOR_ECO0_SHIFT 3 9204 9205 /* vsr40_rx_dig_regs :: lockdet_control4 :: dec_pre_lkdt_cnt [02:00] */ 9206 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4_DEC_PRE_LKDT_CNT_MASK 0x0007 9207 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4_DEC_PRE_LKDT_CNT_ALIGN 0 9208 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4_DEC_PRE_LKDT_CNT_BITS 3 9209 #define VSR40_RX_DIG_REGS_LOCKDET_CONTROL4_DEC_PRE_LKDT_CNT_SHIFT 0 9210 9211 9212 /**************************************************************************** 9213 * vsr40_rx_dig_regs :: reserve_control 9214 */ 9215 /* vsr40_rx_dig_regs :: reserve_control :: dig_rsvd_1 [15:03] */ 9216 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_DIG_RSVD_1_MASK 0xfff8 9217 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_DIG_RSVD_1_ALIGN 0 9218 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_DIG_RSVD_1_BITS 13 9219 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_DIG_RSVD_1_SHIFT 3 9220 9221 /* vsr40_rx_dig_regs :: reserve_control :: alosb_degltch_sel [02:01] */ 9222 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_ALOSB_DEGLTCH_SEL_MASK 0x0006 9223 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_ALOSB_DEGLTCH_SEL_ALIGN 0 9224 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_ALOSB_DEGLTCH_SEL_BITS 2 9225 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_ALOSB_DEGLTCH_SEL_SHIFT 1 9226 9227 /* vsr40_rx_dig_regs :: reserve_control :: alosb_degltch_en [00:00] */ 9228 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_ALOSB_DEGLTCH_EN_MASK 0x0001 9229 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_ALOSB_DEGLTCH_EN_ALIGN 0 9230 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_ALOSB_DEGLTCH_EN_BITS 1 9231 #define VSR40_RX_DIG_REGS_RESERVE_CONTROL_ALOSB_DEGLTCH_EN_SHIFT 0 9232 9233 9234 /**************************************************************************** 9235 * vsr40_rx_dig_regs :: status 9236 */ 9237 /* vsr40_rx_dig_regs :: status :: reserved_for_eco0 [15:11] */ 9238 #define VSR40_RX_DIG_REGS_STATUS_RESERVED_FOR_ECO0_MASK 0xf800 9239 #define VSR40_RX_DIG_REGS_STATUS_RESERVED_FOR_ECO0_ALIGN 0 9240 #define VSR40_RX_DIG_REGS_STATUS_RESERVED_FOR_ECO0_BITS 5 9241 #define VSR40_RX_DIG_REGS_STATUS_RESERVED_FOR_ECO0_SHIFT 11 9242 9243 /* vsr40_rx_dig_regs :: status :: alosb [10:07] */ 9244 #define VSR40_RX_DIG_REGS_STATUS_ALOSB_MASK 0x0780 9245 #define VSR40_RX_DIG_REGS_STATUS_ALOSB_ALIGN 0 9246 #define VSR40_RX_DIG_REGS_STATUS_ALOSB_BITS 4 9247 #define VSR40_RX_DIG_REGS_STATUS_ALOSB_SHIFT 7 9248 9249 /* vsr40_rx_dig_regs :: status :: cal_state [06:04] */ 9250 #define VSR40_RX_DIG_REGS_STATUS_CAL_STATE_MASK 0x0070 9251 #define VSR40_RX_DIG_REGS_STATUS_CAL_STATE_ALIGN 0 9252 #define VSR40_RX_DIG_REGS_STATUS_CAL_STATE_BITS 3 9253 #define VSR40_RX_DIG_REGS_STATUS_CAL_STATE_SHIFT 4 9254 9255 /* vsr40_rx_dig_regs :: status :: cal_valid [03:03] */ 9256 #define VSR40_RX_DIG_REGS_STATUS_CAL_VALID_MASK 0x0008 9257 #define VSR40_RX_DIG_REGS_STATUS_CAL_VALID_ALIGN 0 9258 #define VSR40_RX_DIG_REGS_STATUS_CAL_VALID_BITS 1 9259 #define VSR40_RX_DIG_REGS_STATUS_CAL_VALID_SHIFT 3 9260 9261 /* vsr40_rx_dig_regs :: status :: cal_valid_ll [02:02] */ 9262 #define VSR40_RX_DIG_REGS_STATUS_CAL_VALID_LL_MASK 0x0004 9263 #define VSR40_RX_DIG_REGS_STATUS_CAL_VALID_LL_ALIGN 0 9264 #define VSR40_RX_DIG_REGS_STATUS_CAL_VALID_LL_BITS 1 9265 #define VSR40_RX_DIG_REGS_STATUS_CAL_VALID_LL_SHIFT 2 9266 9267 /* vsr40_rx_dig_regs :: status :: lockerrb [01:01] */ 9268 #define VSR40_RX_DIG_REGS_STATUS_LOCKERRB_MASK 0x0002 9269 #define VSR40_RX_DIG_REGS_STATUS_LOCKERRB_ALIGN 0 9270 #define VSR40_RX_DIG_REGS_STATUS_LOCKERRB_BITS 1 9271 #define VSR40_RX_DIG_REGS_STATUS_LOCKERRB_SHIFT 1 9272 9273 /* vsr40_rx_dig_regs :: status :: lockerrb_ll [00:00] */ 9274 #define VSR40_RX_DIG_REGS_STATUS_LOCKERRB_LL_MASK 0x0001 9275 #define VSR40_RX_DIG_REGS_STATUS_LOCKERRB_LL_ALIGN 0 9276 #define VSR40_RX_DIG_REGS_STATUS_LOCKERRB_LL_BITS 1 9277 #define VSR40_RX_DIG_REGS_STATUS_LOCKERRB_LL_SHIFT 0 9278 9279 9280 /**************************************************************************** 9281 * vsr40_rx_dig_regs :: rx_misr 9282 */ 9283 /* vsr40_rx_dig_regs :: rx_misr :: rx_intr_rsvd [15:04] */ 9284 #define VSR40_RX_DIG_REGS_RX_MISR_RX_INTR_RSVD_MASK 0xfff0 9285 #define VSR40_RX_DIG_REGS_RX_MISR_RX_INTR_RSVD_ALIGN 0 9286 #define VSR40_RX_DIG_REGS_RX_MISR_RX_INTR_RSVD_BITS 12 9287 #define VSR40_RX_DIG_REGS_RX_MISR_RX_INTR_RSVD_SHIFT 4 9288 9289 /* vsr40_rx_dig_regs :: rx_misr :: rx_vco_cal_lost [03:03] */ 9290 #define VSR40_RX_DIG_REGS_RX_MISR_RX_VCO_CAL_LOST_MASK 0x0008 9291 #define VSR40_RX_DIG_REGS_RX_MISR_RX_VCO_CAL_LOST_ALIGN 0 9292 #define VSR40_RX_DIG_REGS_RX_MISR_RX_VCO_CAL_LOST_BITS 1 9293 #define VSR40_RX_DIG_REGS_RX_MISR_RX_VCO_CAL_LOST_SHIFT 3 9294 9295 /* vsr40_rx_dig_regs :: rx_misr :: rx_vco_cal_done [02:02] */ 9296 #define VSR40_RX_DIG_REGS_RX_MISR_RX_VCO_CAL_DONE_MASK 0x0004 9297 #define VSR40_RX_DIG_REGS_RX_MISR_RX_VCO_CAL_DONE_ALIGN 0 9298 #define VSR40_RX_DIG_REGS_RX_MISR_RX_VCO_CAL_DONE_BITS 1 9299 #define VSR40_RX_DIG_REGS_RX_MISR_RX_VCO_CAL_DONE_SHIFT 2 9300 9301 /* vsr40_rx_dig_regs :: rx_misr :: rx_pll_lost_lock [01:01] */ 9302 #define VSR40_RX_DIG_REGS_RX_MISR_RX_PLL_LOST_LOCK_MASK 0x0002 9303 #define VSR40_RX_DIG_REGS_RX_MISR_RX_PLL_LOST_LOCK_ALIGN 0 9304 #define VSR40_RX_DIG_REGS_RX_MISR_RX_PLL_LOST_LOCK_BITS 1 9305 #define VSR40_RX_DIG_REGS_RX_MISR_RX_PLL_LOST_LOCK_SHIFT 1 9306 9307 /* vsr40_rx_dig_regs :: rx_misr :: rx_pll_lock [00:00] */ 9308 #define VSR40_RX_DIG_REGS_RX_MISR_RX_PLL_LOCK_MASK 0x0001 9309 #define VSR40_RX_DIG_REGS_RX_MISR_RX_PLL_LOCK_ALIGN 0 9310 #define VSR40_RX_DIG_REGS_RX_MISR_RX_PLL_LOCK_BITS 1 9311 #define VSR40_RX_DIG_REGS_RX_MISR_RX_PLL_LOCK_SHIFT 0 9312 9313 9314 /**************************************************************************** 9315 * vsr40_rx_dig_regs :: rx_mimr 9316 */ 9317 /* vsr40_rx_dig_regs :: rx_mimr :: mask_rx_intr_rsvd [15:04] */ 9318 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_INTR_RSVD_MASK 0xfff0 9319 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_INTR_RSVD_ALIGN 0 9320 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_INTR_RSVD_BITS 12 9321 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_INTR_RSVD_SHIFT 4 9322 9323 /* vsr40_rx_dig_regs :: rx_mimr :: mask_rx_vco_cal_lost [03:03] */ 9324 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_VCO_CAL_LOST_MASK 0x0008 9325 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_VCO_CAL_LOST_ALIGN 0 9326 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_VCO_CAL_LOST_BITS 1 9327 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_VCO_CAL_LOST_SHIFT 3 9328 9329 /* vsr40_rx_dig_regs :: rx_mimr :: mask_rx_vco_cal_done [02:02] */ 9330 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_VCO_CAL_DONE_MASK 0x0004 9331 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_VCO_CAL_DONE_ALIGN 0 9332 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_VCO_CAL_DONE_BITS 1 9333 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_VCO_CAL_DONE_SHIFT 2 9334 9335 /* vsr40_rx_dig_regs :: rx_mimr :: mask_rx_pll_lost_lock [01:01] */ 9336 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_PLL_LOST_LOCK_MASK 0x0002 9337 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_PLL_LOST_LOCK_ALIGN 0 9338 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_PLL_LOST_LOCK_BITS 1 9339 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_PLL_LOST_LOCK_SHIFT 1 9340 9341 /* vsr40_rx_dig_regs :: rx_mimr :: mask_rx_pll_lock [00:00] */ 9342 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_PLL_LOCK_MASK 0x0001 9343 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_PLL_LOCK_ALIGN 0 9344 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_PLL_LOCK_BITS 1 9345 #define VSR40_RX_DIG_REGS_RX_MIMR_MASK_RX_PLL_LOCK_SHIFT 0 9346 9347 9348 /**************************************************************************** 9349 * vsr40_rx_dig_regs :: rx_p_misr 9350 */ 9351 /* vsr40_rx_dig_regs :: rx_p_misr :: p_rx_intr_rsvd [15:04] */ 9352 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_INTR_RSVD_MASK 0xfff0 9353 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_INTR_RSVD_ALIGN 0 9354 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_INTR_RSVD_BITS 12 9355 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_INTR_RSVD_SHIFT 4 9356 9357 /* vsr40_rx_dig_regs :: rx_p_misr :: p_rx_vco_cal_lost [03:03] */ 9358 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_VCO_CAL_LOST_MASK 0x0008 9359 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_VCO_CAL_LOST_ALIGN 0 9360 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_VCO_CAL_LOST_BITS 1 9361 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_VCO_CAL_LOST_SHIFT 3 9362 9363 /* vsr40_rx_dig_regs :: rx_p_misr :: p_rx_vco_cal_done [02:02] */ 9364 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_VCO_CAL_DONE_MASK 0x0004 9365 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_VCO_CAL_DONE_ALIGN 0 9366 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_VCO_CAL_DONE_BITS 1 9367 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_VCO_CAL_DONE_SHIFT 2 9368 9369 /* vsr40_rx_dig_regs :: rx_p_misr :: p_rx_pll_lost_lock [01:01] */ 9370 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_PLL_LOST_LOCK_MASK 0x0002 9371 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_PLL_LOST_LOCK_ALIGN 0 9372 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_PLL_LOST_LOCK_BITS 1 9373 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_PLL_LOST_LOCK_SHIFT 1 9374 9375 /* vsr40_rx_dig_regs :: rx_p_misr :: p_rx_pll_lock [00:00] */ 9376 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_PLL_LOCK_MASK 0x0001 9377 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_PLL_LOCK_ALIGN 0 9378 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_PLL_LOCK_BITS 1 9379 #define VSR40_RX_DIG_REGS_RX_P_MISR_P_RX_PLL_LOCK_SHIFT 0 9380 9381 9382 /**************************************************************************** 9383 * vsr40_rx_dig_regs :: cdr_misr 9384 */ 9385 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_intr_rsvd [15:12] */ 9386 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTR_RSVD_MASK 0xf000 9387 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTR_RSVD_ALIGN 0 9388 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTR_RSVD_BITS 4 9389 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTR_RSVD_SHIFT 12 9390 9391 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_eml_comp_done_ch3 [11:11] */ 9392 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH3_MASK 0x0800 9393 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH3_ALIGN 0 9394 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH3_BITS 1 9395 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH3_SHIFT 11 9396 9397 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_pfc_xcor_done_ch3 [10:10] */ 9398 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH3_MASK 0x0400 9399 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH3_ALIGN 0 9400 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH3_BITS 1 9401 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH3_SHIFT 10 9402 9403 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_integ_sat_ch3 [09:09] */ 9404 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH3_MASK 0x0200 9405 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH3_ALIGN 0 9406 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH3_BITS 1 9407 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH3_SHIFT 9 9408 9409 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_eml_comp_done_ch2 [08:08] */ 9410 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH2_MASK 0x0100 9411 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH2_ALIGN 0 9412 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH2_BITS 1 9413 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH2_SHIFT 8 9414 9415 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_pfc_xcor_done_ch2 [07:07] */ 9416 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH2_MASK 0x0080 9417 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH2_ALIGN 0 9418 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH2_BITS 1 9419 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH2_SHIFT 7 9420 9421 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_integ_sat_ch2 [06:06] */ 9422 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH2_MASK 0x0040 9423 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH2_ALIGN 0 9424 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH2_BITS 1 9425 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH2_SHIFT 6 9426 9427 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_eml_comp_done_ch1 [05:05] */ 9428 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH1_MASK 0x0020 9429 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH1_ALIGN 0 9430 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH1_BITS 1 9431 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH1_SHIFT 5 9432 9433 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_pfc_xcor_done_ch1 [04:04] */ 9434 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH1_MASK 0x0010 9435 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH1_ALIGN 0 9436 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH1_BITS 1 9437 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH1_SHIFT 4 9438 9439 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_integ_sat_ch1 [03:03] */ 9440 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH1_MASK 0x0008 9441 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH1_ALIGN 0 9442 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH1_BITS 1 9443 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH1_SHIFT 3 9444 9445 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_eml_comp_done_ch0 [02:02] */ 9446 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH0_MASK 0x0004 9447 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH0_ALIGN 0 9448 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH0_BITS 1 9449 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_EML_COMP_DONE_CH0_SHIFT 2 9450 9451 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_pfc_xcor_done_ch0 [01:01] */ 9452 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH0_MASK 0x0002 9453 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH0_ALIGN 0 9454 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH0_BITS 1 9455 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_PFC_XCOR_DONE_CH0_SHIFT 1 9456 9457 /* vsr40_rx_dig_regs :: cdr_misr :: cdr_integ_sat_ch0 [00:00] */ 9458 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH0_MASK 0x0001 9459 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH0_ALIGN 0 9460 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH0_BITS 1 9461 #define VSR40_RX_DIG_REGS_CDR_MISR_CDR_INTEG_SAT_CH0_SHIFT 0 9462 9463 9464 /**************************************************************************** 9465 * vsr40_rx_dig_regs :: cdr_mimr 9466 */ 9467 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_intr_rsvd [15:12] */ 9468 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTR_RSVD_MASK 0xf000 9469 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTR_RSVD_ALIGN 0 9470 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTR_RSVD_BITS 4 9471 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTR_RSVD_SHIFT 12 9472 9473 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_eml_comp_done_ch3 [11:11] */ 9474 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH3_MASK 0x0800 9475 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH3_ALIGN 0 9476 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH3_BITS 1 9477 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH3_SHIFT 11 9478 9479 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_pfc_xcor_done_ch3 [10:10] */ 9480 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH3_MASK 0x0400 9481 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH3_ALIGN 0 9482 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH3_BITS 1 9483 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH3_SHIFT 10 9484 9485 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_integ_sat_ch3 [09:09] */ 9486 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH3_MASK 0x0200 9487 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH3_ALIGN 0 9488 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH3_BITS 1 9489 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH3_SHIFT 9 9490 9491 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_eml_comp_done_ch2 [08:08] */ 9492 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH2_MASK 0x0100 9493 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH2_ALIGN 0 9494 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH2_BITS 1 9495 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH2_SHIFT 8 9496 9497 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_pfc_xcor_done_ch2 [07:07] */ 9498 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH2_MASK 0x0080 9499 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH2_ALIGN 0 9500 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH2_BITS 1 9501 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH2_SHIFT 7 9502 9503 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_integ_sat_ch2 [06:06] */ 9504 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH2_MASK 0x0040 9505 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH2_ALIGN 0 9506 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH2_BITS 1 9507 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH2_SHIFT 6 9508 9509 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_eml_comp_done_ch1 [05:05] */ 9510 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH1_MASK 0x0020 9511 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH1_ALIGN 0 9512 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH1_BITS 1 9513 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH1_SHIFT 5 9514 9515 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_pfc_xcor_done_ch1 [04:04] */ 9516 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH1_MASK 0x0010 9517 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH1_ALIGN 0 9518 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH1_BITS 1 9519 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH1_SHIFT 4 9520 9521 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_integ_sat_ch1 [03:03] */ 9522 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH1_MASK 0x0008 9523 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH1_ALIGN 0 9524 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH1_BITS 1 9525 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH1_SHIFT 3 9526 9527 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_eml_comp_done_ch0 [02:02] */ 9528 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH0_MASK 0x0004 9529 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH0_ALIGN 0 9530 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH0_BITS 1 9531 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_EML_COMP_DONE_CH0_SHIFT 2 9532 9533 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_pfc_xcor_done_ch0 [01:01] */ 9534 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH0_MASK 0x0002 9535 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH0_ALIGN 0 9536 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH0_BITS 1 9537 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_PFC_XCOR_DONE_CH0_SHIFT 1 9538 9539 /* vsr40_rx_dig_regs :: cdr_mimr :: mask_cdr_integ_sat_ch0 [00:00] */ 9540 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH0_MASK 0x0001 9541 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH0_ALIGN 0 9542 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH0_BITS 1 9543 #define VSR40_RX_DIG_REGS_CDR_MIMR_MASK_CDR_INTEG_SAT_CH0_SHIFT 0 9544 9545 9546 /**************************************************************************** 9547 * vsr40_rx_dig_regs :: cdr_p_misr 9548 */ 9549 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_intr_rsvd [15:12] */ 9550 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTR_RSVD_MASK 0xf000 9551 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTR_RSVD_ALIGN 0 9552 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTR_RSVD_BITS 4 9553 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTR_RSVD_SHIFT 12 9554 9555 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_eml_comp_done_ch3 [11:11] */ 9556 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH3_MASK 0x0800 9557 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH3_ALIGN 0 9558 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH3_BITS 1 9559 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH3_SHIFT 11 9560 9561 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_pfc_xcor_done_ch3 [10:10] */ 9562 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH3_MASK 0x0400 9563 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH3_ALIGN 0 9564 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH3_BITS 1 9565 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH3_SHIFT 10 9566 9567 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_integ_sat_ch3 [09:09] */ 9568 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH3_MASK 0x0200 9569 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH3_ALIGN 0 9570 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH3_BITS 1 9571 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH3_SHIFT 9 9572 9573 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_eml_comp_done_ch2 [08:08] */ 9574 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH2_MASK 0x0100 9575 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH2_ALIGN 0 9576 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH2_BITS 1 9577 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH2_SHIFT 8 9578 9579 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_pfc_xcor_done_ch2 [07:07] */ 9580 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH2_MASK 0x0080 9581 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH2_ALIGN 0 9582 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH2_BITS 1 9583 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH2_SHIFT 7 9584 9585 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_integ_sat_ch2 [06:06] */ 9586 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH2_MASK 0x0040 9587 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH2_ALIGN 0 9588 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH2_BITS 1 9589 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH2_SHIFT 6 9590 9591 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_eml_comp_done_ch1 [05:05] */ 9592 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH1_MASK 0x0020 9593 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH1_ALIGN 0 9594 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH1_BITS 1 9595 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH1_SHIFT 5 9596 9597 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_pfc_xcor_done_ch1 [04:04] */ 9598 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH1_MASK 0x0010 9599 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH1_ALIGN 0 9600 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH1_BITS 1 9601 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH1_SHIFT 4 9602 9603 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_integ_sat_ch1 [03:03] */ 9604 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH1_MASK 0x0008 9605 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH1_ALIGN 0 9606 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH1_BITS 1 9607 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH1_SHIFT 3 9608 9609 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_eml_comp_done_ch0 [02:02] */ 9610 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH0_MASK 0x0004 9611 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH0_ALIGN 0 9612 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH0_BITS 1 9613 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_EML_COMP_DONE_CH0_SHIFT 2 9614 9615 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_pfc_xcor_done_ch0 [01:01] */ 9616 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH0_MASK 0x0002 9617 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH0_ALIGN 0 9618 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH0_BITS 1 9619 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_PFC_XCOR_DONE_CH0_SHIFT 1 9620 9621 /* vsr40_rx_dig_regs :: cdr_p_misr :: p_cdr_integ_sat_ch0 [00:00] */ 9622 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH0_MASK 0x0001 9623 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH0_ALIGN 0 9624 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH0_BITS 1 9625 #define VSR40_RX_DIG_REGS_CDR_P_MISR_P_CDR_INTEG_SAT_CH0_SHIFT 0 9626 9627 9628 /**************************************************************************** 9629 * vsr40_rx_dig_regs :: dp_ctrl 9630 */ 9631 /* vsr40_rx_dig_regs :: dp_ctrl :: reserved0 [15:08] */ 9632 #define VSR40_RX_DIG_REGS_DP_CTRL_RESERVED0_MASK 0xff00 9633 #define VSR40_RX_DIG_REGS_DP_CTRL_RESERVED0_ALIGN 0 9634 #define VSR40_RX_DIG_REGS_DP_CTRL_RESERVED0_BITS 8 9635 #define VSR40_RX_DIG_REGS_DP_CTRL_RESERVED0_SHIFT 8 9636 9637 /* vsr40_rx_dig_regs :: dp_ctrl :: swap_dp [07:04] */ 9638 #define VSR40_RX_DIG_REGS_DP_CTRL_SWAP_DP_MASK 0x00f0 9639 #define VSR40_RX_DIG_REGS_DP_CTRL_SWAP_DP_ALIGN 0 9640 #define VSR40_RX_DIG_REGS_DP_CTRL_SWAP_DP_BITS 4 9641 #define VSR40_RX_DIG_REGS_DP_CTRL_SWAP_DP_SHIFT 4 9642 9643 /* vsr40_rx_dig_regs :: dp_ctrl :: invert_dp [03:00] */ 9644 #define VSR40_RX_DIG_REGS_DP_CTRL_INVERT_DP_MASK 0x000f 9645 #define VSR40_RX_DIG_REGS_DP_CTRL_INVERT_DP_ALIGN 0 9646 #define VSR40_RX_DIG_REGS_DP_CTRL_INVERT_DP_BITS 4 9647 #define VSR40_RX_DIG_REGS_DP_CTRL_INVERT_DP_SHIFT 0 9648 9649 9650 /**************************************************************************** 9651 * vsr40_rx_dig_regs :: cdr_common_wr_en 9652 */ 9653 /* vsr40_rx_dig_regs :: cdr_common_wr_en :: reserved0 [15:06] */ 9654 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_RESERVED0_MASK 0xffc0 9655 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_RESERVED0_ALIGN 0 9656 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_RESERVED0_BITS 10 9657 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_RESERVED0_SHIFT 6 9658 9659 /* vsr40_rx_dig_regs :: cdr_common_wr_en :: cdr_integ_consec_sat_det_cntrl_wr_en [05:05] */ 9660 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_INTEG_CONSEC_SAT_DET_CNTRL_WR_EN_MASK 0x0020 9661 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_INTEG_CONSEC_SAT_DET_CNTRL_WR_EN_ALIGN 0 9662 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_INTEG_CONSEC_SAT_DET_CNTRL_WR_EN_BITS 1 9663 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_INTEG_CONSEC_SAT_DET_CNTRL_WR_EN_SHIFT 5 9664 9665 /* vsr40_rx_dig_regs :: cdr_common_wr_en :: cdr_pe_os_integ_wr_en [04:04] */ 9666 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_PE_OS_INTEG_WR_EN_MASK 0x0010 9667 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_PE_OS_INTEG_WR_EN_ALIGN 0 9668 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_PE_OS_INTEG_WR_EN_BITS 1 9669 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_PE_OS_INTEG_WR_EN_SHIFT 4 9670 9671 /* vsr40_rx_dig_regs :: cdr_common_wr_en :: cdr_pe_os_common_wr_en [03:03] */ 9672 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_PE_OS_COMMON_WR_EN_MASK 0x0008 9673 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_PE_OS_COMMON_WR_EN_ALIGN 0 9674 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_PE_OS_COMMON_WR_EN_BITS 1 9675 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_PE_OS_COMMON_WR_EN_SHIFT 3 9676 9677 /* vsr40_rx_dig_regs :: cdr_common_wr_en :: cdr_integ_wr_en [02:02] */ 9678 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_INTEG_WR_EN_MASK 0x0004 9679 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_INTEG_WR_EN_ALIGN 0 9680 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_INTEG_WR_EN_BITS 1 9681 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_INTEG_WR_EN_SHIFT 2 9682 9683 /* vsr40_rx_dig_regs :: cdr_common_wr_en :: cdr_kf_wr_en [01:01] */ 9684 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_KF_WR_EN_MASK 0x0002 9685 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_KF_WR_EN_ALIGN 0 9686 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_KF_WR_EN_BITS 1 9687 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_KF_WR_EN_SHIFT 1 9688 9689 /* vsr40_rx_dig_regs :: cdr_common_wr_en :: cdr_kp_wr_en [00:00] */ 9690 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_KP_WR_EN_MASK 0x0001 9691 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_KP_WR_EN_ALIGN 0 9692 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_KP_WR_EN_BITS 1 9693 #define VSR40_RX_DIG_REGS_CDR_COMMON_WR_EN_CDR_KP_WR_EN_SHIFT 0 9694 9695 9696 /**************************************************************************** 9697 * vsr40_rx_pll_regs 9698 */ 9699 /**************************************************************************** 9700 * vsr40_rx_pll :: control7 9701 */ 9702 /* vsr40_rx_pll :: control7 :: pll_rsrvd_103_90 [15:02] */ 9703 #define VSR40_RX_PLL_CONTROL7_PLL_RSRVD_103_90_MASK 0xfffc 9704 #define VSR40_RX_PLL_CONTROL7_PLL_RSRVD_103_90_ALIGN 0 9705 #define VSR40_RX_PLL_CONTROL7_PLL_RSRVD_103_90_BITS 14 9706 #define VSR40_RX_PLL_CONTROL7_PLL_RSRVD_103_90_SHIFT 2 9707 9708 /* vsr40_rx_pll :: control7 :: Rx_tport_cur [01:00] */ 9709 #define VSR40_RX_PLL_CONTROL7_RX_TPORT_CUR_MASK 0x0003 9710 #define VSR40_RX_PLL_CONTROL7_RX_TPORT_CUR_ALIGN 0 9711 #define VSR40_RX_PLL_CONTROL7_RX_TPORT_CUR_BITS 2 9712 #define VSR40_RX_PLL_CONTROL7_RX_TPORT_CUR_SHIFT 0 9713 9714 9715 /**************************************************************************** 9716 * vsr40_rx_pll :: control6 9717 */ 9718 /* vsr40_rx_pll :: control6 :: reserved_for_eco0 [15:08] */ 9719 #define VSR40_RX_PLL_CONTROL6_RESERVED_FOR_ECO0_MASK 0xff00 9720 #define VSR40_RX_PLL_CONTROL6_RESERVED_FOR_ECO0_ALIGN 0 9721 #define VSR40_RX_PLL_CONTROL6_RESERVED_FOR_ECO0_BITS 8 9722 #define VSR40_RX_PLL_CONTROL6_RESERVED_FOR_ECO0_SHIFT 8 9723 9724 /* vsr40_rx_pll :: control6 :: Rx_2T_IQbuf_ptat [07:04] */ 9725 #define VSR40_RX_PLL_CONTROL6_RX_2T_IQBUF_PTAT_MASK 0x00f0 9726 #define VSR40_RX_PLL_CONTROL6_RX_2T_IQBUF_PTAT_ALIGN 0 9727 #define VSR40_RX_PLL_CONTROL6_RX_2T_IQBUF_PTAT_BITS 4 9728 #define VSR40_RX_PLL_CONTROL6_RX_2T_IQBUF_PTAT_SHIFT 4 9729 9730 /* vsr40_rx_pll :: control6 :: Rx_2T_IQbuf_bgcr [03:00] */ 9731 #define VSR40_RX_PLL_CONTROL6_RX_2T_IQBUF_BGCR_MASK 0x000f 9732 #define VSR40_RX_PLL_CONTROL6_RX_2T_IQBUF_BGCR_ALIGN 0 9733 #define VSR40_RX_PLL_CONTROL6_RX_2T_IQBUF_BGCR_BITS 4 9734 #define VSR40_RX_PLL_CONTROL6_RX_2T_IQBUF_BGCR_SHIFT 0 9735 9736 9737 /**************************************************************************** 9738 * vsr40_rx_pll :: control5 9739 */ 9740 /* vsr40_rx_pll :: control5 :: reserved_for_eco0 [15:13] */ 9741 #define VSR40_RX_PLL_CONTROL5_RESERVED_FOR_ECO0_MASK 0xe000 9742 #define VSR40_RX_PLL_CONTROL5_RESERVED_FOR_ECO0_ALIGN 0 9743 #define VSR40_RX_PLL_CONTROL5_RESERVED_FOR_ECO0_BITS 3 9744 #define VSR40_RX_PLL_CONTROL5_RESERVED_FOR_ECO0_SHIFT 13 9745 9746 /* vsr40_rx_pll :: control5 :: Not_used_in_RX_PLL [12:11] */ 9747 #define VSR40_RX_PLL_CONTROL5_NOT_USED_IN_RX_PLL_MASK 0x1800 9748 #define VSR40_RX_PLL_CONTROL5_NOT_USED_IN_RX_PLL_ALIGN 0 9749 #define VSR40_RX_PLL_CONTROL5_NOT_USED_IN_RX_PLL_BITS 2 9750 #define VSR40_RX_PLL_CONTROL5_NOT_USED_IN_RX_PLL_SHIFT 11 9751 9752 /* vsr40_rx_pll :: control5 :: Rx_pll_test_ref_sel [10:10] */ 9753 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_REF_SEL_MASK 0x0400 9754 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_REF_SEL_ALIGN 0 9755 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_REF_SEL_BITS 1 9756 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_REF_SEL_SHIFT 10 9757 9758 /* vsr40_rx_pll :: control5 :: Not_used_in_RX_PLL_76_72 [09:05] */ 9759 #define VSR40_RX_PLL_CONTROL5_NOT_USED_IN_RX_PLL_76_72_MASK 0x03e0 9760 #define VSR40_RX_PLL_CONTROL5_NOT_USED_IN_RX_PLL_76_72_ALIGN 0 9761 #define VSR40_RX_PLL_CONTROL5_NOT_USED_IN_RX_PLL_76_72_BITS 5 9762 #define VSR40_RX_PLL_CONTROL5_NOT_USED_IN_RX_PLL_76_72_SHIFT 5 9763 9764 /* vsr40_rx_pll :: control5 :: Rx_pll_test_clk [04:04] */ 9765 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_CLK_MASK 0x0010 9766 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_CLK_ALIGN 0 9767 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_CLK_BITS 1 9768 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_CLK_SHIFT 4 9769 9770 /* vsr40_rx_pll :: control5 :: Rx_pll_test_vc [03:03] */ 9771 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_VC_MASK 0x0008 9772 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_VC_ALIGN 0 9773 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_VC_BITS 1 9774 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TEST_VC_SHIFT 3 9775 9776 /* vsr40_rx_pll :: control5 :: Rx_bg_test_vbg [02:02] */ 9777 #define VSR40_RX_PLL_CONTROL5_RX_BG_TEST_VBG_MASK 0x0004 9778 #define VSR40_RX_PLL_CONTROL5_RX_BG_TEST_VBG_ALIGN 0 9779 #define VSR40_RX_PLL_CONTROL5_RX_BG_TEST_VBG_BITS 1 9780 #define VSR40_RX_PLL_CONTROL5_RX_BG_TEST_VBG_SHIFT 2 9781 9782 /* vsr40_rx_pll :: control5 :: rx_pll_rsrvd_68 [01:01] */ 9783 #define VSR40_RX_PLL_CONTROL5_RX_PLL_RSRVD_68_MASK 0x0002 9784 #define VSR40_RX_PLL_CONTROL5_RX_PLL_RSRVD_68_ALIGN 0 9785 #define VSR40_RX_PLL_CONTROL5_RX_PLL_RSRVD_68_BITS 1 9786 #define VSR40_RX_PLL_CONTROL5_RX_PLL_RSRVD_68_SHIFT 1 9787 9788 /* vsr40_rx_pll :: control5 :: Rx_pll_tp_tailchg_en [00:00] */ 9789 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TP_TAILCHG_EN_MASK 0x0001 9790 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TP_TAILCHG_EN_ALIGN 0 9791 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TP_TAILCHG_EN_BITS 1 9792 #define VSR40_RX_PLL_CONTROL5_RX_PLL_TP_TAILCHG_EN_SHIFT 0 9793 9794 9795 /**************************************************************************** 9796 * vsr40_rx_pll :: control4 9797 */ 9798 /* vsr40_rx_pll :: control4 :: susm_rx_refsel_frc [15:15] */ 9799 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_REFSEL_FRC_MASK 0x8000 9800 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_REFSEL_FRC_ALIGN 0 9801 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_REFSEL_FRC_BITS 1 9802 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_REFSEL_FRC_SHIFT 15 9803 9804 /* vsr40_rx_pll :: control4 :: susm_rx_refsel [14:13] */ 9805 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_REFSEL_MASK 0x6000 9806 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_REFSEL_ALIGN 0 9807 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_REFSEL_BITS 2 9808 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_REFSEL_SHIFT 13 9809 9810 /* vsr40_rx_pll :: control4 :: susm_rx_en_e100g_frc [12:12] */ 9811 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_E100G_FRC_MASK 0x1000 9812 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_E100G_FRC_ALIGN 0 9813 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_E100G_FRC_BITS 1 9814 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_E100G_FRC_SHIFT 12 9815 9816 /* vsr40_rx_pll :: control4 :: susm_rx_en_e100g [11:11] */ 9817 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_E100G_MASK 0x0800 9818 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_E100G_ALIGN 0 9819 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_E100G_BITS 1 9820 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_E100G_SHIFT 11 9821 9822 /* vsr40_rx_pll :: control4 :: susm_rx_en_25g_frc [10:10] */ 9823 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_25G_FRC_MASK 0x0400 9824 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_25G_FRC_ALIGN 0 9825 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_25G_FRC_BITS 1 9826 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_25G_FRC_SHIFT 10 9827 9828 /* vsr40_rx_pll :: control4 :: susm_rx_en_25g [09:09] */ 9829 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_25G_MASK 0x0200 9830 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_25G_ALIGN 0 9831 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_25G_BITS 1 9832 #define VSR40_RX_PLL_CONTROL4_SUSM_RX_EN_25G_SHIFT 9 9833 9834 /* vsr40_rx_pll :: control4 :: ENDUALREF [08:08] */ 9835 #define VSR40_RX_PLL_CONTROL4_ENDUALREF_MASK 0x0100 9836 #define VSR40_RX_PLL_CONTROL4_ENDUALREF_ALIGN 0 9837 #define VSR40_RX_PLL_CONTROL4_ENDUALREF_BITS 1 9838 #define VSR40_RX_PLL_CONTROL4_ENDUALREF_SHIFT 8 9839 9840 /* vsr40_rx_pll :: control4 :: CMUSEL [07:06] */ 9841 #define VSR40_RX_PLL_CONTROL4_CMUSEL_MASK 0x00c0 9842 #define VSR40_RX_PLL_CONTROL4_CMUSEL_ALIGN 0 9843 #define VSR40_RX_PLL_CONTROL4_CMUSEL_BITS 2 9844 #define VSR40_RX_PLL_CONTROL4_CMUSEL_SHIFT 6 9845 9846 /* vsr40_rx_pll :: control4 :: Rx_bg_pwrdn [05:05] */ 9847 #define VSR40_RX_PLL_CONTROL4_RX_BG_PWRDN_MASK 0x0020 9848 #define VSR40_RX_PLL_CONTROL4_RX_BG_PWRDN_ALIGN 0 9849 #define VSR40_RX_PLL_CONTROL4_RX_BG_PWRDN_BITS 1 9850 #define VSR40_RX_PLL_CONTROL4_RX_BG_PWRDN_SHIFT 5 9851 9852 /* vsr40_rx_pll :: control4 :: Rx_pll_pwrdn [04:04] */ 9853 #define VSR40_RX_PLL_CONTROL4_RX_PLL_PWRDN_MASK 0x0010 9854 #define VSR40_RX_PLL_CONTROL4_RX_PLL_PWRDN_ALIGN 0 9855 #define VSR40_RX_PLL_CONTROL4_RX_PLL_PWRDN_BITS 1 9856 #define VSR40_RX_PLL_CONTROL4_RX_PLL_PWRDN_SHIFT 4 9857 9858 /* vsr40_rx_pll :: control4 :: Rx_bg_ptatadj [03:00] */ 9859 #define VSR40_RX_PLL_CONTROL4_RX_BG_PTATADJ_MASK 0x000f 9860 #define VSR40_RX_PLL_CONTROL4_RX_BG_PTATADJ_ALIGN 0 9861 #define VSR40_RX_PLL_CONTROL4_RX_BG_PTATADJ_BITS 4 9862 #define VSR40_RX_PLL_CONTROL4_RX_BG_PTATADJ_SHIFT 0 9863 9864 9865 /**************************************************************************** 9866 * vsr40_rx_pll :: control3 9867 */ 9868 /* vsr40_rx_pll :: control3 :: Rx_bg_ctatadj [15:12] */ 9869 #define VSR40_RX_PLL_CONTROL3_RX_BG_CTATADJ_MASK 0xf000 9870 #define VSR40_RX_PLL_CONTROL3_RX_BG_CTATADJ_ALIGN 0 9871 #define VSR40_RX_PLL_CONTROL3_RX_BG_CTATADJ_BITS 4 9872 #define VSR40_RX_PLL_CONTROL3_RX_BG_CTATADJ_SHIFT 12 9873 9874 /* vsr40_rx_pll :: control3 :: Not_used_in_RX_PLL_49_46 [11:08] */ 9875 #define VSR40_RX_PLL_CONTROL3_NOT_USED_IN_RX_PLL_49_46_MASK 0x0f00 9876 #define VSR40_RX_PLL_CONTROL3_NOT_USED_IN_RX_PLL_49_46_ALIGN 0 9877 #define VSR40_RX_PLL_CONTROL3_NOT_USED_IN_RX_PLL_49_46_BITS 4 9878 #define VSR40_RX_PLL_CONTROL3_NOT_USED_IN_RX_PLL_49_46_SHIFT 8 9879 9880 /* vsr40_rx_pll :: control3 :: Rx_vco_range_frc [07:07] */ 9881 #define VSR40_RX_PLL_CONTROL3_RX_VCO_RANGE_FRC_MASK 0x0080 9882 #define VSR40_RX_PLL_CONTROL3_RX_VCO_RANGE_FRC_ALIGN 0 9883 #define VSR40_RX_PLL_CONTROL3_RX_VCO_RANGE_FRC_BITS 1 9884 #define VSR40_RX_PLL_CONTROL3_RX_VCO_RANGE_FRC_SHIFT 7 9885 9886 /* vsr40_rx_pll :: control3 :: Rx_vco_range [06:00] */ 9887 #define VSR40_RX_PLL_CONTROL3_RX_VCO_RANGE_MASK 0x007f 9888 #define VSR40_RX_PLL_CONTROL3_RX_VCO_RANGE_ALIGN 0 9889 #define VSR40_RX_PLL_CONTROL3_RX_VCO_RANGE_BITS 7 9890 #define VSR40_RX_PLL_CONTROL3_RX_VCO_RANGE_SHIFT 0 9891 9892 9893 /**************************************************************************** 9894 * vsr40_rx_pll :: control2 9895 */ 9896 /* vsr40_rx_pll :: control2 :: Rx_vco_cur [15:15] */ 9897 #define VSR40_RX_PLL_CONTROL2_RX_VCO_CUR_MASK 0x8000 9898 #define VSR40_RX_PLL_CONTROL2_RX_VCO_CUR_ALIGN 0 9899 #define VSR40_RX_PLL_CONTROL2_RX_VCO_CUR_BITS 1 9900 #define VSR40_RX_PLL_CONTROL2_RX_VCO_CUR_SHIFT 15 9901 9902 /* vsr40_rx_pll :: control2 :: susm_rx_vco_en25G_frc [14:14] */ 9903 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_VCO_EN25G_FRC_MASK 0x4000 9904 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_VCO_EN25G_FRC_ALIGN 0 9905 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_VCO_EN25G_FRC_BITS 1 9906 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_VCO_EN25G_FRC_SHIFT 14 9907 9908 /* vsr40_rx_pll :: control2 :: susm_rx_vco_en25G [13:13] */ 9909 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_VCO_EN25G_MASK 0x2000 9910 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_VCO_EN25G_ALIGN 0 9911 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_VCO_EN25G_BITS 1 9912 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_VCO_EN25G_SHIFT 13 9913 9914 /* vsr40_rx_pll :: control2 :: susm_rx_en_VSR_frc [12:12] */ 9915 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_EN_VSR_FRC_MASK 0x1000 9916 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_EN_VSR_FRC_ALIGN 0 9917 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_EN_VSR_FRC_BITS 1 9918 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_EN_VSR_FRC_SHIFT 12 9919 9920 /* vsr40_rx_pll :: control2 :: susm_rx_en_VSR [11:11] */ 9921 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_EN_VSR_MASK 0x0800 9922 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_EN_VSR_ALIGN 0 9923 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_EN_VSR_BITS 1 9924 #define VSR40_RX_PLL_CONTROL2_SUSM_RX_EN_VSR_SHIFT 11 9925 9926 /* vsr40_rx_pll :: control2 :: Rx_test_rx1_sel [10:10] */ 9927 #define VSR40_RX_PLL_CONTROL2_RX_TEST_RX1_SEL_MASK 0x0400 9928 #define VSR40_RX_PLL_CONTROL2_RX_TEST_RX1_SEL_ALIGN 0 9929 #define VSR40_RX_PLL_CONTROL2_RX_TEST_RX1_SEL_BITS 1 9930 #define VSR40_RX_PLL_CONTROL2_RX_TEST_RX1_SEL_SHIFT 10 9931 9932 /* vsr40_rx_pll :: control2 :: Rx_test_rx_clk [09:09] */ 9933 #define VSR40_RX_PLL_CONTROL2_RX_TEST_RX_CLK_MASK 0x0200 9934 #define VSR40_RX_PLL_CONTROL2_RX_TEST_RX_CLK_ALIGN 0 9935 #define VSR40_RX_PLL_CONTROL2_RX_TEST_RX_CLK_BITS 1 9936 #define VSR40_RX_PLL_CONTROL2_RX_TEST_RX_CLK_SHIFT 9 9937 9938 /* vsr40_rx_pll :: control2 :: Rxpll_rescal_frc [08:08] */ 9939 #define VSR40_RX_PLL_CONTROL2_RXPLL_RESCAL_FRC_MASK 0x0100 9940 #define VSR40_RX_PLL_CONTROL2_RXPLL_RESCAL_FRC_ALIGN 0 9941 #define VSR40_RX_PLL_CONTROL2_RXPLL_RESCAL_FRC_BITS 1 9942 #define VSR40_RX_PLL_CONTROL2_RXPLL_RESCAL_FRC_SHIFT 8 9943 9944 /* vsr40_rx_pll :: control2 :: Rxpll_rescal [07:05] */ 9945 #define VSR40_RX_PLL_CONTROL2_RXPLL_RESCAL_MASK 0x00e0 9946 #define VSR40_RX_PLL_CONTROL2_RXPLL_RESCAL_ALIGN 0 9947 #define VSR40_RX_PLL_CONTROL2_RXPLL_RESCAL_BITS 3 9948 #define VSR40_RX_PLL_CONTROL2_RXPLL_RESCAL_SHIFT 5 9949 9950 /* vsr40_rx_pll :: control2 :: Rx_1Tbuf1_band_frc [04:04] */ 9951 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_BAND_FRC_MASK 0x0010 9952 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_BAND_FRC_ALIGN 0 9953 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_BAND_FRC_BITS 1 9954 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_BAND_FRC_SHIFT 4 9955 9956 /* vsr40_rx_pll :: control2 :: Rx_1Tbuf1_band [03:02] */ 9957 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_BAND_MASK 0x000c 9958 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_BAND_ALIGN 0 9959 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_BAND_BITS 2 9960 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_BAND_SHIFT 2 9961 9962 /* vsr40_rx_pll :: control2 :: Rx_1Tbuf1_cur [01:00] */ 9963 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_CUR_MASK 0x0003 9964 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_CUR_ALIGN 0 9965 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_CUR_BITS 2 9966 #define VSR40_RX_PLL_CONTROL2_RX_1TBUF1_CUR_SHIFT 0 9967 9968 9969 /**************************************************************************** 9970 * vsr40_rx_pll :: control1 9971 */ 9972 /* vsr40_rx_pll :: control1 :: reserved_for_eco0 [15:15] */ 9973 #define VSR40_RX_PLL_CONTROL1_RESERVED_FOR_ECO0_MASK 0x8000 9974 #define VSR40_RX_PLL_CONTROL1_RESERVED_FOR_ECO0_ALIGN 0 9975 #define VSR40_RX_PLL_CONTROL1_RESERVED_FOR_ECO0_BITS 1 9976 #define VSR40_RX_PLL_CONTROL1_RESERVED_FOR_ECO0_SHIFT 15 9977 9978 /* vsr40_rx_pll :: control1 :: Rx_capctrl_IQbuf [14:11] */ 9979 #define VSR40_RX_PLL_CONTROL1_RX_CAPCTRL_IQBUF_MASK 0x7800 9980 #define VSR40_RX_PLL_CONTROL1_RX_CAPCTRL_IQBUF_ALIGN 0 9981 #define VSR40_RX_PLL_CONTROL1_RX_CAPCTRL_IQBUF_BITS 4 9982 #define VSR40_RX_PLL_CONTROL1_RX_CAPCTRL_IQBUF_SHIFT 11 9983 9984 /* vsr40_rx_pll :: control1 :: Rx_encurrent_IQbuf_frc [10:10] */ 9985 #define VSR40_RX_PLL_CONTROL1_RX_ENCURRENT_IQBUF_FRC_MASK 0x0400 9986 #define VSR40_RX_PLL_CONTROL1_RX_ENCURRENT_IQBUF_FRC_ALIGN 0 9987 #define VSR40_RX_PLL_CONTROL1_RX_ENCURRENT_IQBUF_FRC_BITS 1 9988 #define VSR40_RX_PLL_CONTROL1_RX_ENCURRENT_IQBUF_FRC_SHIFT 10 9989 9990 /* vsr40_rx_pll :: control1 :: Rx_encurrent_IQbuf [09:09] */ 9991 #define VSR40_RX_PLL_CONTROL1_RX_ENCURRENT_IQBUF_MASK 0x0200 9992 #define VSR40_RX_PLL_CONTROL1_RX_ENCURRENT_IQBUF_ALIGN 0 9993 #define VSR40_RX_PLL_CONTROL1_RX_ENCURRENT_IQBUF_BITS 1 9994 #define VSR40_RX_PLL_CONTROL1_RX_ENCURRENT_IQBUF_SHIFT 9 9995 9996 /* vsr40_rx_pll :: control1 :: Rx_1Tdiv_cur [08:06] */ 9997 #define VSR40_RX_PLL_CONTROL1_RX_1TDIV_CUR_MASK 0x01c0 9998 #define VSR40_RX_PLL_CONTROL1_RX_1TDIV_CUR_ALIGN 0 9999 #define VSR40_RX_PLL_CONTROL1_RX_1TDIV_CUR_BITS 3 10000 #define VSR40_RX_PLL_CONTROL1_RX_1TDIV_CUR_SHIFT 6 10001 10002 /* vsr40_rx_pll :: control1 :: susm_rx_ref_div_frc [05:05] */ 10003 #define VSR40_RX_PLL_CONTROL1_SUSM_RX_REF_DIV_FRC_MASK 0x0020 10004 #define VSR40_RX_PLL_CONTROL1_SUSM_RX_REF_DIV_FRC_ALIGN 0 10005 #define VSR40_RX_PLL_CONTROL1_SUSM_RX_REF_DIV_FRC_BITS 1 10006 #define VSR40_RX_PLL_CONTROL1_SUSM_RX_REF_DIV_FRC_SHIFT 5 10007 10008 /* vsr40_rx_pll :: control1 :: susm_rx_ref_div [04:03] */ 10009 #define VSR40_RX_PLL_CONTROL1_SUSM_RX_REF_DIV_MASK 0x0018 10010 #define VSR40_RX_PLL_CONTROL1_SUSM_RX_REF_DIV_ALIGN 0 10011 #define VSR40_RX_PLL_CONTROL1_SUSM_RX_REF_DIV_BITS 2 10012 #define VSR40_RX_PLL_CONTROL1_SUSM_RX_REF_DIV_SHIFT 3 10013 10014 /* vsr40_rx_pll :: control1 :: Rx_2Tbufdiv_cur [02:00] */ 10015 #define VSR40_RX_PLL_CONTROL1_RX_2TBUFDIV_CUR_MASK 0x0007 10016 #define VSR40_RX_PLL_CONTROL1_RX_2TBUFDIV_CUR_ALIGN 0 10017 #define VSR40_RX_PLL_CONTROL1_RX_2TBUFDIV_CUR_BITS 3 10018 #define VSR40_RX_PLL_CONTROL1_RX_2TBUFDIV_CUR_SHIFT 0 10019 10020 10021 /**************************************************************************** 10022 * vsr40_rx_pll :: control0 10023 */ 10024 /* vsr40_rx_pll :: control0 :: reserved_for_eco0 [15:14] */ 10025 #define VSR40_RX_PLL_CONTROL0_RESERVED_FOR_ECO0_MASK 0xc000 10026 #define VSR40_RX_PLL_CONTROL0_RESERVED_FOR_ECO0_ALIGN 0 10027 #define VSR40_RX_PLL_CONTROL0_RESERVED_FOR_ECO0_BITS 2 10028 #define VSR40_RX_PLL_CONTROL0_RESERVED_FOR_ECO0_SHIFT 14 10029 10030 /* vsr40_rx_pll :: control0 :: Rx_tport_hicur [13:13] */ 10031 #define VSR40_RX_PLL_CONTROL0_RX_TPORT_HICUR_MASK 0x2000 10032 #define VSR40_RX_PLL_CONTROL0_RX_TPORT_HICUR_ALIGN 0 10033 #define VSR40_RX_PLL_CONTROL0_RX_TPORT_HICUR_BITS 1 10034 #define VSR40_RX_PLL_CONTROL0_RX_TPORT_HICUR_SHIFT 13 10035 10036 /* vsr40_rx_pll :: control0 :: pll_rsrvd_12 [12:12] */ 10037 #define VSR40_RX_PLL_CONTROL0_PLL_RSRVD_12_MASK 0x1000 10038 #define VSR40_RX_PLL_CONTROL0_PLL_RSRVD_12_ALIGN 0 10039 #define VSR40_RX_PLL_CONTROL0_PLL_RSRVD_12_BITS 1 10040 #define VSR40_RX_PLL_CONTROL0_PLL_RSRVD_12_SHIFT 12 10041 10042 /* vsr40_rx_pll :: control0 :: pll_rsrvd_11 [11:11] */ 10043 #define VSR40_RX_PLL_CONTROL0_PLL_RSRVD_11_MASK 0x0800 10044 #define VSR40_RX_PLL_CONTROL0_PLL_RSRVD_11_ALIGN 0 10045 #define VSR40_RX_PLL_CONTROL0_PLL_RSRVD_11_BITS 1 10046 #define VSR40_RX_PLL_CONTROL0_PLL_RSRVD_11_SHIFT 11 10047 10048 /* vsr40_rx_pll :: control0 :: Rx_cp [10:09] */ 10049 #define VSR40_RX_PLL_CONTROL0_RX_CP_MASK 0x0600 10050 #define VSR40_RX_PLL_CONTROL0_RX_CP_ALIGN 0 10051 #define VSR40_RX_PLL_CONTROL0_RX_CP_BITS 2 10052 #define VSR40_RX_PLL_CONTROL0_RX_CP_SHIFT 9 10053 10054 /* vsr40_rx_pll :: control0 :: Rx_rz [08:06] */ 10055 #define VSR40_RX_PLL_CONTROL0_RX_RZ_MASK 0x01c0 10056 #define VSR40_RX_PLL_CONTROL0_RX_RZ_ALIGN 0 10057 #define VSR40_RX_PLL_CONTROL0_RX_RZ_BITS 3 10058 #define VSR40_RX_PLL_CONTROL0_RX_RZ_SHIFT 6 10059 10060 /* vsr40_rx_pll :: control0 :: Rx_qp_cur [05:02] */ 10061 #define VSR40_RX_PLL_CONTROL0_RX_QP_CUR_MASK 0x003c 10062 #define VSR40_RX_PLL_CONTROL0_RX_QP_CUR_ALIGN 0 10063 #define VSR40_RX_PLL_CONTROL0_RX_QP_CUR_BITS 4 10064 #define VSR40_RX_PLL_CONTROL0_RX_QP_CUR_SHIFT 2 10065 10066 /* vsr40_rx_pll :: control0 :: Rx_qp_VDD_BGb [01:01] */ 10067 #define VSR40_RX_PLL_CONTROL0_RX_QP_VDD_BGB_MASK 0x0002 10068 #define VSR40_RX_PLL_CONTROL0_RX_QP_VDD_BGB_ALIGN 0 10069 #define VSR40_RX_PLL_CONTROL0_RX_QP_VDD_BGB_BITS 1 10070 #define VSR40_RX_PLL_CONTROL0_RX_QP_VDD_BGB_SHIFT 1 10071 10072 /* vsr40_rx_pll :: control0 :: Rx_testport_sel_ana_n [00:00] */ 10073 #define VSR40_RX_PLL_CONTROL0_RX_TESTPORT_SEL_ANA_N_MASK 0x0001 10074 #define VSR40_RX_PLL_CONTROL0_RX_TESTPORT_SEL_ANA_N_ALIGN 0 10075 #define VSR40_RX_PLL_CONTROL0_RX_TESTPORT_SEL_ANA_N_BITS 1 10076 #define VSR40_RX_PLL_CONTROL0_RX_TESTPORT_SEL_ANA_N_SHIFT 0 10077 10078 10079 /**************************************************************************** 10080 * vsr40_tx_ana25g_regs 10081 */ 10082 /**************************************************************************** 10083 * vsr40_tx_ana25g :: control8 10084 */ 10085 /* vsr40_tx_ana25g :: control8 :: ana_rsrvd_103_91 [15:03] */ 10086 #define VSR40_TX_ANA25G_CONTROL8_ANA_RSRVD_103_91_MASK 0xfff8 10087 #define VSR40_TX_ANA25G_CONTROL8_ANA_RSRVD_103_91_ALIGN 0 10088 #define VSR40_TX_ANA25G_CONTROL8_ANA_RSRVD_103_91_BITS 13 10089 #define VSR40_TX_ANA25G_CONTROL8_ANA_RSRVD_103_91_SHIFT 3 10090 10091 /* vsr40_tx_ana25g :: control8 :: sel_testclk8T [02:02] */ 10092 #define VSR40_TX_ANA25G_CONTROL8_SEL_TESTCLK8T_MASK 0x0004 10093 #define VSR40_TX_ANA25G_CONTROL8_SEL_TESTCLK8T_ALIGN 0 10094 #define VSR40_TX_ANA25G_CONTROL8_SEL_TESTCLK8T_BITS 1 10095 #define VSR40_TX_ANA25G_CONTROL8_SEL_TESTCLK8T_SHIFT 2 10096 10097 /* vsr40_tx_ana25g :: control8 :: test_clk_rate_sel [01:00] */ 10098 #define VSR40_TX_ANA25G_CONTROL8_TEST_CLK_RATE_SEL_MASK 0x0003 10099 #define VSR40_TX_ANA25G_CONTROL8_TEST_CLK_RATE_SEL_ALIGN 0 10100 #define VSR40_TX_ANA25G_CONTROL8_TEST_CLK_RATE_SEL_BITS 2 10101 #define VSR40_TX_ANA25G_CONTROL8_TEST_CLK_RATE_SEL_SHIFT 0 10102 10103 10104 /**************************************************************************** 10105 * vsr40_tx_ana25g :: control7 10106 */ 10107 /* vsr40_tx_ana25g :: control7 :: reserved_for_eco0 [15:15] */ 10108 #define VSR40_TX_ANA25G_CONTROL7_RESERVED_FOR_ECO0_MASK 0x8000 10109 #define VSR40_TX_ANA25G_CONTROL7_RESERVED_FOR_ECO0_ALIGN 0 10110 #define VSR40_TX_ANA25G_CONTROL7_RESERVED_FOR_ECO0_BITS 1 10111 #define VSR40_TX_ANA25G_CONTROL7_RESERVED_FOR_ECO0_SHIFT 15 10112 10113 /* vsr40_tx_ana25g :: control7 :: test_clk_en [14:14] */ 10114 #define VSR40_TX_ANA25G_CONTROL7_TEST_CLK_EN_MASK 0x4000 10115 #define VSR40_TX_ANA25G_CONTROL7_TEST_CLK_EN_ALIGN 0 10116 #define VSR40_TX_ANA25G_CONTROL7_TEST_CLK_EN_BITS 1 10117 #define VSR40_TX_ANA25G_CONTROL7_TEST_CLK_EN_SHIFT 14 10118 10119 /* vsr40_tx_ana25g :: control7 :: test_clk_ch_sel [13:13] */ 10120 #define VSR40_TX_ANA25G_CONTROL7_TEST_CLK_CH_SEL_MASK 0x2000 10121 #define VSR40_TX_ANA25G_CONTROL7_TEST_CLK_CH_SEL_ALIGN 0 10122 #define VSR40_TX_ANA25G_CONTROL7_TEST_CLK_CH_SEL_BITS 1 10123 #define VSR40_TX_ANA25G_CONTROL7_TEST_CLK_CH_SEL_SHIFT 13 10124 10125 /* vsr40_tx_ana25g :: control7 :: ana_rsrvd_85 [12:12] */ 10126 #define VSR40_TX_ANA25G_CONTROL7_ANA_RSRVD_85_MASK 0x1000 10127 #define VSR40_TX_ANA25G_CONTROL7_ANA_RSRVD_85_ALIGN 0 10128 #define VSR40_TX_ANA25G_CONTROL7_ANA_RSRVD_85_BITS 1 10129 #define VSR40_TX_ANA25G_CONTROL7_ANA_RSRVD_85_SHIFT 12 10130 10131 /* vsr40_tx_ana25g :: control7 :: tx_pon_frc [11:11] */ 10132 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_FRC_MASK 0x0800 10133 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_FRC_ALIGN 0 10134 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_FRC_BITS 1 10135 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_FRC_SHIFT 11 10136 10137 /* vsr40_tx_ana25g :: control7 :: tx_pon [10:08] */ 10138 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_MASK 0x0700 10139 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_ALIGN 0 10140 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_BITS 3 10141 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_SHIFT 8 10142 10143 /* vsr40_tx_ana25g :: control7 :: tx_pon_pdrv_frc [07:07] */ 10144 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_PDRV_FRC_MASK 0x0080 10145 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_PDRV_FRC_ALIGN 0 10146 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_PDRV_FRC_BITS 1 10147 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_PDRV_FRC_SHIFT 7 10148 10149 /* vsr40_tx_ana25g :: control7 :: tx_pon_pdrv [06:04] */ 10150 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_PDRV_MASK 0x0070 10151 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_PDRV_ALIGN 0 10152 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_PDRV_BITS 3 10153 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_PDRV_SHIFT 4 10154 10155 /* vsr40_tx_ana25g :: control7 :: tx_pon_drv_frc [03:03] */ 10156 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_DRV_FRC_MASK 0x0008 10157 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_DRV_FRC_ALIGN 0 10158 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_DRV_FRC_BITS 1 10159 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_DRV_FRC_SHIFT 3 10160 10161 /* vsr40_tx_ana25g :: control7 :: tx_pon_drv [02:00] */ 10162 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_DRV_MASK 0x0007 10163 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_DRV_ALIGN 0 10164 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_DRV_BITS 3 10165 #define VSR40_TX_ANA25G_CONTROL7_TX_PON_DRV_SHIFT 0 10166 10167 10168 /**************************************************************************** 10169 * vsr40_tx_ana25g :: control6 10170 */ 10171 /* vsr40_tx_ana25g :: control6 :: tx_pon_hs_frc [15:15] */ 10172 #define VSR40_TX_ANA25G_CONTROL6_TX_PON_HS_FRC_MASK 0x8000 10173 #define VSR40_TX_ANA25G_CONTROL6_TX_PON_HS_FRC_ALIGN 0 10174 #define VSR40_TX_ANA25G_CONTROL6_TX_PON_HS_FRC_BITS 1 10175 #define VSR40_TX_ANA25G_CONTROL6_TX_PON_HS_FRC_SHIFT 15 10176 10177 /* vsr40_tx_ana25g :: control6 :: tx_pon_hs [14:12] */ 10178 #define VSR40_TX_ANA25G_CONTROL6_TX_PON_HS_MASK 0x7000 10179 #define VSR40_TX_ANA25G_CONTROL6_TX_PON_HS_ALIGN 0 10180 #define VSR40_TX_ANA25G_CONTROL6_TX_PON_HS_BITS 3 10181 #define VSR40_TX_ANA25G_CONTROL6_TX_PON_HS_SHIFT 12 10182 10183 /* vsr40_tx_ana25g :: control6 :: reserved0 [11:03] */ 10184 #define VSR40_TX_ANA25G_CONTROL6_RESERVED0_MASK 0x0ff8 10185 #define VSR40_TX_ANA25G_CONTROL6_RESERVED0_ALIGN 0 10186 #define VSR40_TX_ANA25G_CONTROL6_RESERVED0_BITS 9 10187 #define VSR40_TX_ANA25G_CONTROL6_RESERVED0_SHIFT 3 10188 10189 /* vsr40_tx_ana25g :: control6 :: ana_rsrvd_72 [02:02] */ 10190 #define VSR40_TX_ANA25G_CONTROL6_ANA_RSRVD_72_MASK 0x0004 10191 #define VSR40_TX_ANA25G_CONTROL6_ANA_RSRVD_72_ALIGN 0 10192 #define VSR40_TX_ANA25G_CONTROL6_ANA_RSRVD_72_BITS 1 10193 #define VSR40_TX_ANA25G_CONTROL6_ANA_RSRVD_72_SHIFT 2 10194 10195 /* vsr40_tx_ana25g :: control6 :: ticksel [01:00] */ 10196 #define VSR40_TX_ANA25G_CONTROL6_TICKSEL_MASK 0x0003 10197 #define VSR40_TX_ANA25G_CONTROL6_TICKSEL_ALIGN 0 10198 #define VSR40_TX_ANA25G_CONTROL6_TICKSEL_BITS 2 10199 #define VSR40_TX_ANA25G_CONTROL6_TICKSEL_SHIFT 0 10200 10201 10202 /**************************************************************************** 10203 * vsr40_tx_ana25g :: control5 10204 */ 10205 /* vsr40_tx_ana25g :: control5 :: reserved0 [15:15] */ 10206 #define VSR40_TX_ANA25G_CONTROL5_RESERVED0_MASK 0x8000 10207 #define VSR40_TX_ANA25G_CONTROL5_RESERVED0_ALIGN 0 10208 #define VSR40_TX_ANA25G_CONTROL5_RESERVED0_BITS 1 10209 #define VSR40_TX_ANA25G_CONTROL5_RESERVED0_SHIFT 15 10210 10211 /* vsr40_tx_ana25g :: control5 :: pre_tap [14:11] */ 10212 #define VSR40_TX_ANA25G_CONTROL5_PRE_TAP_MASK 0x7800 10213 #define VSR40_TX_ANA25G_CONTROL5_PRE_TAP_ALIGN 0 10214 #define VSR40_TX_ANA25G_CONTROL5_PRE_TAP_BITS 4 10215 #define VSR40_TX_ANA25G_CONTROL5_PRE_TAP_SHIFT 11 10216 10217 /* vsr40_tx_ana25g :: control5 :: post_tap [10:06] */ 10218 #define VSR40_TX_ANA25G_CONTROL5_POST_TAP_MASK 0x07c0 10219 #define VSR40_TX_ANA25G_CONTROL5_POST_TAP_ALIGN 0 10220 #define VSR40_TX_ANA25G_CONTROL5_POST_TAP_BITS 5 10221 #define VSR40_TX_ANA25G_CONTROL5_POST_TAP_SHIFT 6 10222 10223 /* vsr40_tx_ana25g :: control5 :: main_tap [05:00] */ 10224 #define VSR40_TX_ANA25G_CONTROL5_MAIN_TAP_MASK 0x003f 10225 #define VSR40_TX_ANA25G_CONTROL5_MAIN_TAP_ALIGN 0 10226 #define VSR40_TX_ANA25G_CONTROL5_MAIN_TAP_BITS 6 10227 #define VSR40_TX_ANA25G_CONTROL5_MAIN_TAP_SHIFT 0 10228 10229 10230 /**************************************************************************** 10231 * vsr40_tx_ana25g :: control4 10232 */ 10233 /* vsr40_tx_ana25g :: control4 :: reserved0 [15:15] */ 10234 #define VSR40_TX_ANA25G_CONTROL4_RESERVED0_MASK 0x8000 10235 #define VSR40_TX_ANA25G_CONTROL4_RESERVED0_ALIGN 0 10236 #define VSR40_TX_ANA25G_CONTROL4_RESERVED0_BITS 1 10237 #define VSR40_TX_ANA25G_CONTROL4_RESERVED0_SHIFT 15 10238 10239 /* vsr40_tx_ana25g :: control4 :: susm_en_clk4T_5G_frc [14:14] */ 10240 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN_CLK4T_5G_FRC_MASK 0x4000 10241 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN_CLK4T_5G_FRC_ALIGN 0 10242 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN_CLK4T_5G_FRC_BITS 1 10243 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN_CLK4T_5G_FRC_SHIFT 14 10244 10245 /* vsr40_tx_ana25g :: control4 :: susm_en_clk4T_5G [13:13] */ 10246 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN_CLK4T_5G_MASK 0x2000 10247 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN_CLK4T_5G_ALIGN 0 10248 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN_CLK4T_5G_BITS 1 10249 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN_CLK4T_5G_SHIFT 13 10250 10251 /* vsr40_tx_ana25g :: control4 :: susm_en10G_frc [12:12] */ 10252 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN10G_FRC_MASK 0x1000 10253 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN10G_FRC_ALIGN 0 10254 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN10G_FRC_BITS 1 10255 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN10G_FRC_SHIFT 12 10256 10257 /* vsr40_tx_ana25g :: control4 :: susm_en10G [11:11] */ 10258 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN10G_MASK 0x0800 10259 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN10G_ALIGN 0 10260 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN10G_BITS 1 10261 #define VSR40_TX_ANA25G_CONTROL4_SUSM_EN10G_SHIFT 11 10262 10263 /* vsr40_tx_ana25g :: control4 :: tx_phadj_5g [10:09] */ 10264 #define VSR40_TX_ANA25G_CONTROL4_TX_PHADJ_5G_MASK 0x0600 10265 #define VSR40_TX_ANA25G_CONTROL4_TX_PHADJ_5G_ALIGN 0 10266 #define VSR40_TX_ANA25G_CONTROL4_TX_PHADJ_5G_BITS 2 10267 #define VSR40_TX_ANA25G_CONTROL4_TX_PHADJ_5G_SHIFT 9 10268 10269 /* vsr40_tx_ana25g :: control4 :: i_ctrl_band_clk4T_frc [08:08] */ 10270 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK4T_FRC_MASK 0x0100 10271 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK4T_FRC_ALIGN 0 10272 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK4T_FRC_BITS 1 10273 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK4T_FRC_SHIFT 8 10274 10275 /* vsr40_tx_ana25g :: control4 :: i_ctrl_band_clk4T [07:06] */ 10276 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK4T_MASK 0x00c0 10277 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK4T_ALIGN 0 10278 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK4T_BITS 2 10279 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK4T_SHIFT 6 10280 10281 /* vsr40_tx_ana25g :: control4 :: i_ctrl_band_clk2T_frc [05:05] */ 10282 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK2T_FRC_MASK 0x0020 10283 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK2T_FRC_ALIGN 0 10284 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK2T_FRC_BITS 1 10285 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK2T_FRC_SHIFT 5 10286 10287 /* vsr40_tx_ana25g :: control4 :: i_ctrl_band_clk2T [04:03] */ 10288 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK2T_MASK 0x0018 10289 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK2T_ALIGN 0 10290 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK2T_BITS 2 10291 #define VSR40_TX_ANA25G_CONTROL4_I_CTRL_BAND_CLK2T_SHIFT 3 10292 10293 /* vsr40_tx_ana25g :: control4 :: en_hcur_4T [02:02] */ 10294 #define VSR40_TX_ANA25G_CONTROL4_EN_HCUR_4T_MASK 0x0004 10295 #define VSR40_TX_ANA25G_CONTROL4_EN_HCUR_4T_ALIGN 0 10296 #define VSR40_TX_ANA25G_CONTROL4_EN_HCUR_4T_BITS 1 10297 #define VSR40_TX_ANA25G_CONTROL4_EN_HCUR_4T_SHIFT 2 10298 10299 /* vsr40_tx_ana25g :: control4 :: en_hcur_2T [01:01] */ 10300 #define VSR40_TX_ANA25G_CONTROL4_EN_HCUR_2T_MASK 0x0002 10301 #define VSR40_TX_ANA25G_CONTROL4_EN_HCUR_2T_ALIGN 0 10302 #define VSR40_TX_ANA25G_CONTROL4_EN_HCUR_2T_BITS 1 10303 #define VSR40_TX_ANA25G_CONTROL4_EN_HCUR_2T_SHIFT 1 10304 10305 /* vsr40_tx_ana25g :: control4 :: test_drv [00:00] */ 10306 #define VSR40_TX_ANA25G_CONTROL4_TEST_DRV_MASK 0x0001 10307 #define VSR40_TX_ANA25G_CONTROL4_TEST_DRV_ALIGN 0 10308 #define VSR40_TX_ANA25G_CONTROL4_TEST_DRV_BITS 1 10309 #define VSR40_TX_ANA25G_CONTROL4_TEST_DRV_SHIFT 0 10310 10311 10312 /**************************************************************************** 10313 * vsr40_tx_ana25g :: control3 10314 */ 10315 /* vsr40_tx_ana25g :: control3 :: reserved0 [15:08] */ 10316 #define VSR40_TX_ANA25G_CONTROL3_RESERVED0_MASK 0xff00 10317 #define VSR40_TX_ANA25G_CONTROL3_RESERVED0_ALIGN 0 10318 #define VSR40_TX_ANA25G_CONTROL3_RESERVED0_BITS 8 10319 #define VSR40_TX_ANA25G_CONTROL3_RESERVED0_SHIFT 8 10320 10321 /* vsr40_tx_ana25g :: control3 :: tx_drv_opamp_bias_en [07:07] */ 10322 #define VSR40_TX_ANA25G_CONTROL3_TX_DRV_OPAMP_BIAS_EN_MASK 0x0080 10323 #define VSR40_TX_ANA25G_CONTROL3_TX_DRV_OPAMP_BIAS_EN_ALIGN 0 10324 #define VSR40_TX_ANA25G_CONTROL3_TX_DRV_OPAMP_BIAS_EN_BITS 1 10325 #define VSR40_TX_ANA25G_CONTROL3_TX_DRV_OPAMP_BIAS_EN_SHIFT 7 10326 10327 /* vsr40_tx_ana25g :: control3 :: imux4to2 [06:04] */ 10328 #define VSR40_TX_ANA25G_CONTROL3_IMUX4TO2_MASK 0x0070 10329 #define VSR40_TX_ANA25G_CONTROL3_IMUX4TO2_ALIGN 0 10330 #define VSR40_TX_ANA25G_CONTROL3_IMUX4TO2_BITS 3 10331 #define VSR40_TX_ANA25G_CONTROL3_IMUX4TO2_SHIFT 4 10332 10333 /* vsr40_tx_ana25g :: control3 :: i_clk4T [03:00] */ 10334 #define VSR40_TX_ANA25G_CONTROL3_I_CLK4T_MASK 0x000f 10335 #define VSR40_TX_ANA25G_CONTROL3_I_CLK4T_ALIGN 0 10336 #define VSR40_TX_ANA25G_CONTROL3_I_CLK4T_BITS 4 10337 #define VSR40_TX_ANA25G_CONTROL3_I_CLK4T_SHIFT 0 10338 10339 10340 /**************************************************************************** 10341 * vsr40_tx_ana25g :: control2 10342 */ 10343 /* vsr40_tx_ana25g :: control2 :: I_clk_pibuf [15:12] */ 10344 #define VSR40_TX_ANA25G_CONTROL2_I_CLK_PIBUF_MASK 0xf000 10345 #define VSR40_TX_ANA25G_CONTROL2_I_CLK_PIBUF_ALIGN 0 10346 #define VSR40_TX_ANA25G_CONTROL2_I_CLK_PIBUF_BITS 4 10347 #define VSR40_TX_ANA25G_CONTROL2_I_CLK_PIBUF_SHIFT 12 10348 10349 /* vsr40_tx_ana25g :: control2 :: I_clk_pi [11:08] */ 10350 #define VSR40_TX_ANA25G_CONTROL2_I_CLK_PI_MASK 0x0f00 10351 #define VSR40_TX_ANA25G_CONTROL2_I_CLK_PI_ALIGN 0 10352 #define VSR40_TX_ANA25G_CONTROL2_I_CLK_PI_BITS 4 10353 #define VSR40_TX_ANA25G_CONTROL2_I_CLK_PI_SHIFT 8 10354 10355 /* vsr40_tx_ana25g :: control2 :: iclk_tune_2T [07:04] */ 10356 #define VSR40_TX_ANA25G_CONTROL2_ICLK_TUNE_2T_MASK 0x00f0 10357 #define VSR40_TX_ANA25G_CONTROL2_ICLK_TUNE_2T_ALIGN 0 10358 #define VSR40_TX_ANA25G_CONTROL2_ICLK_TUNE_2T_BITS 4 10359 #define VSR40_TX_ANA25G_CONTROL2_ICLK_TUNE_2T_SHIFT 4 10360 10361 /* vsr40_tx_ana25g :: control2 :: imux2to1_pre [03:00] */ 10362 #define VSR40_TX_ANA25G_CONTROL2_IMUX2TO1_PRE_MASK 0x000f 10363 #define VSR40_TX_ANA25G_CONTROL2_IMUX2TO1_PRE_ALIGN 0 10364 #define VSR40_TX_ANA25G_CONTROL2_IMUX2TO1_PRE_BITS 4 10365 #define VSR40_TX_ANA25G_CONTROL2_IMUX2TO1_PRE_SHIFT 0 10366 10367 10368 /**************************************************************************** 10369 * vsr40_tx_ana25g :: control1 10370 */ 10371 /* vsr40_tx_ana25g :: control1 :: imux2to1_post [15:12] */ 10372 #define VSR40_TX_ANA25G_CONTROL1_IMUX2TO1_POST_MASK 0xf000 10373 #define VSR40_TX_ANA25G_CONTROL1_IMUX2TO1_POST_ALIGN 0 10374 #define VSR40_TX_ANA25G_CONTROL1_IMUX2TO1_POST_BITS 4 10375 #define VSR40_TX_ANA25G_CONTROL1_IMUX2TO1_POST_SHIFT 12 10376 10377 /* vsr40_tx_ana25g :: control1 :: imux2to1 [11:08] */ 10378 #define VSR40_TX_ANA25G_CONTROL1_IMUX2TO1_MASK 0x0f00 10379 #define VSR40_TX_ANA25G_CONTROL1_IMUX2TO1_ALIGN 0 10380 #define VSR40_TX_ANA25G_CONTROL1_IMUX2TO1_BITS 4 10381 #define VSR40_TX_ANA25G_CONTROL1_IMUX2TO1_SHIFT 8 10382 10383 /* vsr40_tx_ana25g :: control1 :: ipredriver [07:04] */ 10384 #define VSR40_TX_ANA25G_CONTROL1_IPREDRIVER_MASK 0x00f0 10385 #define VSR40_TX_ANA25G_CONTROL1_IPREDRIVER_ALIGN 0 10386 #define VSR40_TX_ANA25G_CONTROL1_IPREDRIVER_BITS 4 10387 #define VSR40_TX_ANA25G_CONTROL1_IPREDRIVER_SHIFT 4 10388 10389 /* vsr40_tx_ana25g :: control1 :: idriver [03:00] */ 10390 #define VSR40_TX_ANA25G_CONTROL1_IDRIVER_MASK 0x000f 10391 #define VSR40_TX_ANA25G_CONTROL1_IDRIVER_ALIGN 0 10392 #define VSR40_TX_ANA25G_CONTROL1_IDRIVER_BITS 4 10393 #define VSR40_TX_ANA25G_CONTROL1_IDRIVER_SHIFT 0 10394 10395 10396 /**************************************************************************** 10397 * vsr40_tx_ana25g :: control0 10398 */ 10399 /* vsr40_tx_ana25g :: control0 :: reserved_for_eco0 [15:04] */ 10400 #define VSR40_TX_ANA25G_CONTROL0_RESERVED_FOR_ECO0_MASK 0xfff0 10401 #define VSR40_TX_ANA25G_CONTROL0_RESERVED_FOR_ECO0_ALIGN 0 10402 #define VSR40_TX_ANA25G_CONTROL0_RESERVED_FOR_ECO0_BITS 12 10403 #define VSR40_TX_ANA25G_CONTROL0_RESERVED_FOR_ECO0_SHIFT 4 10404 10405 /* vsr40_tx_ana25g :: control0 :: tx_pwrdn [03:03] */ 10406 #define VSR40_TX_ANA25G_CONTROL0_TX_PWRDN_MASK 0x0008 10407 #define VSR40_TX_ANA25G_CONTROL0_TX_PWRDN_ALIGN 0 10408 #define VSR40_TX_ANA25G_CONTROL0_TX_PWRDN_BITS 1 10409 #define VSR40_TX_ANA25G_CONTROL0_TX_PWRDN_SHIFT 3 10410 10411 /* vsr40_tx_ana25g :: control0 :: tx_clk_pwrdn [02:02] */ 10412 #define VSR40_TX_ANA25G_CONTROL0_TX_CLK_PWRDN_MASK 0x0004 10413 #define VSR40_TX_ANA25G_CONTROL0_TX_CLK_PWRDN_ALIGN 0 10414 #define VSR40_TX_ANA25G_CONTROL0_TX_CLK_PWRDN_BITS 1 10415 #define VSR40_TX_ANA25G_CONTROL0_TX_CLK_PWRDN_SHIFT 2 10416 10417 /* vsr40_tx_ana25g :: control0 :: ana_rsrvd_for_eco_1_0 [01:00] */ 10418 #define VSR40_TX_ANA25G_CONTROL0_ANA_RSRVD_FOR_ECO_1_0_MASK 0x0003 10419 #define VSR40_TX_ANA25G_CONTROL0_ANA_RSRVD_FOR_ECO_1_0_ALIGN 0 10420 #define VSR40_TX_ANA25G_CONTROL0_ANA_RSRVD_FOR_ECO_1_0_BITS 2 10421 #define VSR40_TX_ANA25G_CONTROL0_ANA_RSRVD_FOR_ECO_1_0_SHIFT 0 10422 10423 10424 /**************************************************************************** 10425 * vsr40_tx_dig_regs_regs 10426 */ 10427 /**************************************************************************** 10428 * vsr40_tx_dig_regs :: reset_control 10429 */ 10430 /* vsr40_tx_dig_regs :: reset_control :: rescal_reset_ovrd [15:15] */ 10431 #define VSR40_TX_DIG_REGS_RESET_CONTROL_RESCAL_RESET_OVRD_MASK 0x8000 10432 #define VSR40_TX_DIG_REGS_RESET_CONTROL_RESCAL_RESET_OVRD_ALIGN 0 10433 #define VSR40_TX_DIG_REGS_RESET_CONTROL_RESCAL_RESET_OVRD_BITS 1 10434 #define VSR40_TX_DIG_REGS_RESET_CONTROL_RESCAL_RESET_OVRD_SHIFT 15 10435 10436 /* vsr40_tx_dig_regs :: reset_control :: pll_pwrdn_st_ovrd [14:14] */ 10437 #define VSR40_TX_DIG_REGS_RESET_CONTROL_PLL_PWRDN_ST_OVRD_MASK 0x4000 10438 #define VSR40_TX_DIG_REGS_RESET_CONTROL_PLL_PWRDN_ST_OVRD_ALIGN 0 10439 #define VSR40_TX_DIG_REGS_RESET_CONTROL_PLL_PWRDN_ST_OVRD_BITS 1 10440 #define VSR40_TX_DIG_REGS_RESET_CONTROL_PLL_PWRDN_ST_OVRD_SHIFT 14 10441 10442 /* vsr40_tx_dig_regs :: reset_control :: reserved_for_eco0 [13:03] */ 10443 #define VSR40_TX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO0_MASK 0x3ff8 10444 #define VSR40_TX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 10445 #define VSR40_TX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO0_BITS 11 10446 #define VSR40_TX_DIG_REGS_RESET_CONTROL_RESERVED_FOR_ECO0_SHIFT 3 10447 10448 /* vsr40_tx_dig_regs :: reset_control :: tca_rstb [02:02] */ 10449 #define VSR40_TX_DIG_REGS_RESET_CONTROL_TCA_RSTB_MASK 0x0004 10450 #define VSR40_TX_DIG_REGS_RESET_CONTROL_TCA_RSTB_ALIGN 0 10451 #define VSR40_TX_DIG_REGS_RESET_CONTROL_TCA_RSTB_BITS 1 10452 #define VSR40_TX_DIG_REGS_RESET_CONTROL_TCA_RSTB_SHIFT 2 10453 10454 /* vsr40_tx_dig_regs :: reset_control :: cal_rstb [01:01] */ 10455 #define VSR40_TX_DIG_REGS_RESET_CONTROL_CAL_RSTB_MASK 0x0002 10456 #define VSR40_TX_DIG_REGS_RESET_CONTROL_CAL_RSTB_ALIGN 0 10457 #define VSR40_TX_DIG_REGS_RESET_CONTROL_CAL_RSTB_BITS 1 10458 #define VSR40_TX_DIG_REGS_RESET_CONTROL_CAL_RSTB_SHIFT 1 10459 10460 /* vsr40_tx_dig_regs :: reset_control :: lkdt_rstb [00:00] */ 10461 #define VSR40_TX_DIG_REGS_RESET_CONTROL_LKDT_RSTB_MASK 0x0001 10462 #define VSR40_TX_DIG_REGS_RESET_CONTROL_LKDT_RSTB_ALIGN 0 10463 #define VSR40_TX_DIG_REGS_RESET_CONTROL_LKDT_RSTB_BITS 1 10464 #define VSR40_TX_DIG_REGS_RESET_CONTROL_LKDT_RSTB_SHIFT 0 10465 10466 10467 /**************************************************************************** 10468 * vsr40_tx_dig_regs :: clk_control 10469 */ 10470 /* vsr40_tx_dig_regs :: clk_control :: reserved_for_eco0 [15:00] */ 10471 #define VSR40_TX_DIG_REGS_CLK_CONTROL_RESERVED_FOR_ECO0_MASK 0xffff 10472 #define VSR40_TX_DIG_REGS_CLK_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 10473 #define VSR40_TX_DIG_REGS_CLK_CONTROL_RESERVED_FOR_ECO0_BITS 16 10474 #define VSR40_TX_DIG_REGS_CLK_CONTROL_RESERVED_FOR_ECO0_SHIFT 0 10475 10476 10477 /**************************************************************************** 10478 * vsr40_tx_dig_regs :: vcocal_control 10479 */ 10480 /* vsr40_tx_dig_regs :: vcocal_control :: reserved_for_eco0 [15:03] */ 10481 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_RESERVED_FOR_ECO0_MASK 0xfff8 10482 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 10483 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_RESERVED_FOR_ECO0_BITS 13 10484 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_RESERVED_FOR_ECO0_SHIFT 3 10485 10486 /* vsr40_tx_dig_regs :: vcocal_control :: cal_th [02:01] */ 10487 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_CAL_TH_MASK 0x0006 10488 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_CAL_TH_ALIGN 0 10489 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_CAL_TH_BITS 2 10490 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_CAL_TH_SHIFT 1 10491 10492 /* vsr40_tx_dig_regs :: vcocal_control :: cap_delay [00:00] */ 10493 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_CAP_DELAY_MASK 0x0001 10494 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_CAP_DELAY_ALIGN 0 10495 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_CAP_DELAY_BITS 1 10496 #define VSR40_TX_DIG_REGS_VCOCAL_CONTROL_CAP_DELAY_SHIFT 0 10497 10498 10499 /**************************************************************************** 10500 * vsr40_tx_dig_regs :: lockdet_control1 10501 */ 10502 /* vsr40_tx_dig_regs :: lockdet_control1 :: lkdt_assrt_cmpr [15:00] */ 10503 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL1_LKDT_ASSRT_CMPR_MASK 0xffff 10504 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL1_LKDT_ASSRT_CMPR_ALIGN 0 10505 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL1_LKDT_ASSRT_CMPR_BITS 16 10506 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL1_LKDT_ASSRT_CMPR_SHIFT 0 10507 10508 10509 /**************************************************************************** 10510 * vsr40_tx_dig_regs :: lockdet_control2 10511 */ 10512 /* vsr40_tx_dig_regs :: lockdet_control2 :: lkdt_deassrt_cmpr [15:00] */ 10513 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL2_LKDT_DEASSRT_CMPR_MASK 0xffff 10514 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL2_LKDT_DEASSRT_CMPR_ALIGN 0 10515 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL2_LKDT_DEASSRT_CMPR_BITS 16 10516 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL2_LKDT_DEASSRT_CMPR_SHIFT 0 10517 10518 10519 /**************************************************************************** 10520 * vsr40_tx_dig_regs :: lockdet_control3 10521 */ 10522 /* vsr40_tx_dig_regs :: lockdet_control3 :: lkdt_byp [15:15] */ 10523 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_LKDT_BYP_MASK 0x8000 10524 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_LKDT_BYP_ALIGN 0 10525 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_LKDT_BYP_BITS 1 10526 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_LKDT_BYP_SHIFT 15 10527 10528 /* vsr40_tx_dig_regs :: lockdet_control3 :: lkdt_cnt [14:12] */ 10529 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_LKDT_CNT_MASK 0x7000 10530 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_LKDT_CNT_ALIGN 0 10531 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_LKDT_CNT_BITS 3 10532 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_LKDT_CNT_SHIFT 12 10533 10534 /* vsr40_tx_dig_regs :: lockdet_control3 :: ppm_offset_deassrt [11:06] */ 10535 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_DEASSRT_MASK 0x0fc0 10536 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_DEASSRT_ALIGN 0 10537 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_DEASSRT_BITS 6 10538 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_DEASSRT_SHIFT 6 10539 10540 /* vsr40_tx_dig_regs :: lockdet_control3 :: ppm_offset_assrt [05:00] */ 10541 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_ASSRT_MASK 0x003f 10542 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_ASSRT_ALIGN 0 10543 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_ASSRT_BITS 6 10544 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL3_PPM_OFFSET_ASSRT_SHIFT 0 10545 10546 10547 /**************************************************************************** 10548 * vsr40_tx_dig_regs :: lockdet_control4 10549 */ 10550 /* vsr40_tx_dig_regs :: lockdet_control4 :: reserved_for_eco0 [15:03] */ 10551 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4_RESERVED_FOR_ECO0_MASK 0xfff8 10552 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4_RESERVED_FOR_ECO0_ALIGN 0 10553 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4_RESERVED_FOR_ECO0_BITS 13 10554 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4_RESERVED_FOR_ECO0_SHIFT 3 10555 10556 /* vsr40_tx_dig_regs :: lockdet_control4 :: dec_pre_lkdt_cnt [02:00] */ 10557 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4_DEC_PRE_LKDT_CNT_MASK 0x0007 10558 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4_DEC_PRE_LKDT_CNT_ALIGN 0 10559 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4_DEC_PRE_LKDT_CNT_BITS 3 10560 #define VSR40_TX_DIG_REGS_LOCKDET_CONTROL4_DEC_PRE_LKDT_CNT_SHIFT 0 10561 10562 10563 /**************************************************************************** 10564 * vsr40_tx_dig_regs :: reserve_control 10565 */ 10566 /* vsr40_tx_dig_regs :: reserve_control :: dig_rsvd_1 [15:00] */ 10567 #define VSR40_TX_DIG_REGS_RESERVE_CONTROL_DIG_RSVD_1_MASK 0xffff 10568 #define VSR40_TX_DIG_REGS_RESERVE_CONTROL_DIG_RSVD_1_ALIGN 0 10569 #define VSR40_TX_DIG_REGS_RESERVE_CONTROL_DIG_RSVD_1_BITS 16 10570 #define VSR40_TX_DIG_REGS_RESERVE_CONTROL_DIG_RSVD_1_SHIFT 0 10571 10572 10573 /**************************************************************************** 10574 * vsr40_tx_dig_regs :: status 10575 */ 10576 /* vsr40_tx_dig_regs :: status :: reserved_for_eco0 [15:09] */ 10577 #define VSR40_TX_DIG_REGS_STATUS_RESERVED_FOR_ECO0_MASK 0xfe00 10578 #define VSR40_TX_DIG_REGS_STATUS_RESERVED_FOR_ECO0_ALIGN 0 10579 #define VSR40_TX_DIG_REGS_STATUS_RESERVED_FOR_ECO0_BITS 7 10580 #define VSR40_TX_DIG_REGS_STATUS_RESERVED_FOR_ECO0_SHIFT 9 10581 10582 /* vsr40_tx_dig_regs :: status :: vcxo_lockerrb [08:08] */ 10583 #define VSR40_TX_DIG_REGS_STATUS_VCXO_LOCKERRB_MASK 0x0100 10584 #define VSR40_TX_DIG_REGS_STATUS_VCXO_LOCKERRB_ALIGN 0 10585 #define VSR40_TX_DIG_REGS_STATUS_VCXO_LOCKERRB_BITS 1 10586 #define VSR40_TX_DIG_REGS_STATUS_VCXO_LOCKERRB_SHIFT 8 10587 10588 /* vsr40_tx_dig_regs :: status :: vcxo_lockerrb_ll [07:07] */ 10589 #define VSR40_TX_DIG_REGS_STATUS_VCXO_LOCKERRB_LL_MASK 0x0080 10590 #define VSR40_TX_DIG_REGS_STATUS_VCXO_LOCKERRB_LL_ALIGN 0 10591 #define VSR40_TX_DIG_REGS_STATUS_VCXO_LOCKERRB_LL_BITS 1 10592 #define VSR40_TX_DIG_REGS_STATUS_VCXO_LOCKERRB_LL_SHIFT 7 10593 10594 /* vsr40_tx_dig_regs :: status :: cal_state [06:04] */ 10595 #define VSR40_TX_DIG_REGS_STATUS_CAL_STATE_MASK 0x0070 10596 #define VSR40_TX_DIG_REGS_STATUS_CAL_STATE_ALIGN 0 10597 #define VSR40_TX_DIG_REGS_STATUS_CAL_STATE_BITS 3 10598 #define VSR40_TX_DIG_REGS_STATUS_CAL_STATE_SHIFT 4 10599 10600 /* vsr40_tx_dig_regs :: status :: cal_valid [03:03] */ 10601 #define VSR40_TX_DIG_REGS_STATUS_CAL_VALID_MASK 0x0008 10602 #define VSR40_TX_DIG_REGS_STATUS_CAL_VALID_ALIGN 0 10603 #define VSR40_TX_DIG_REGS_STATUS_CAL_VALID_BITS 1 10604 #define VSR40_TX_DIG_REGS_STATUS_CAL_VALID_SHIFT 3 10605 10606 /* vsr40_tx_dig_regs :: status :: cal_valid_ll [02:02] */ 10607 #define VSR40_TX_DIG_REGS_STATUS_CAL_VALID_LL_MASK 0x0004 10608 #define VSR40_TX_DIG_REGS_STATUS_CAL_VALID_LL_ALIGN 0 10609 #define VSR40_TX_DIG_REGS_STATUS_CAL_VALID_LL_BITS 1 10610 #define VSR40_TX_DIG_REGS_STATUS_CAL_VALID_LL_SHIFT 2 10611 10612 /* vsr40_tx_dig_regs :: status :: lockerrb [01:01] */ 10613 #define VSR40_TX_DIG_REGS_STATUS_LOCKERRB_MASK 0x0002 10614 #define VSR40_TX_DIG_REGS_STATUS_LOCKERRB_ALIGN 0 10615 #define VSR40_TX_DIG_REGS_STATUS_LOCKERRB_BITS 1 10616 #define VSR40_TX_DIG_REGS_STATUS_LOCKERRB_SHIFT 1 10617 10618 /* vsr40_tx_dig_regs :: status :: lockerrb_ll [00:00] */ 10619 #define VSR40_TX_DIG_REGS_STATUS_LOCKERRB_LL_MASK 0x0001 10620 #define VSR40_TX_DIG_REGS_STATUS_LOCKERRB_LL_ALIGN 0 10621 #define VSR40_TX_DIG_REGS_STATUS_LOCKERRB_LL_BITS 1 10622 #define VSR40_TX_DIG_REGS_STATUS_LOCKERRB_LL_SHIFT 0 10623 10624 10625 /**************************************************************************** 10626 * vsr40_tx_dig_regs :: tx_misr 10627 */ 10628 /* vsr40_tx_dig_regs :: tx_misr :: tx_intr_rsvd [15:08] */ 10629 #define VSR40_TX_DIG_REGS_TX_MISR_TX_INTR_RSVD_MASK 0xff00 10630 #define VSR40_TX_DIG_REGS_TX_MISR_TX_INTR_RSVD_ALIGN 0 10631 #define VSR40_TX_DIG_REGS_TX_MISR_TX_INTR_RSVD_BITS 8 10632 #define VSR40_TX_DIG_REGS_TX_MISR_TX_INTR_RSVD_SHIFT 8 10633 10634 /* vsr40_tx_dig_regs :: tx_misr :: tpc_iir_sat_ch3 [07:07] */ 10635 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH3_MASK 0x0080 10636 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH3_ALIGN 0 10637 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH3_BITS 1 10638 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH3_SHIFT 7 10639 10640 /* vsr40_tx_dig_regs :: tx_misr :: tpc_iir_sat_ch2 [06:06] */ 10641 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH2_MASK 0x0040 10642 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH2_ALIGN 0 10643 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH2_BITS 1 10644 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH2_SHIFT 6 10645 10646 /* vsr40_tx_dig_regs :: tx_misr :: tpc_iir_sat_ch1 [05:05] */ 10647 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH1_MASK 0x0020 10648 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH1_ALIGN 0 10649 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH1_BITS 1 10650 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH1_SHIFT 5 10651 10652 /* vsr40_tx_dig_regs :: tx_misr :: tpc_iir_sat_ch0 [04:04] */ 10653 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH0_MASK 0x0010 10654 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH0_ALIGN 0 10655 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH0_BITS 1 10656 #define VSR40_TX_DIG_REGS_TX_MISR_TPC_IIR_SAT_CH0_SHIFT 4 10657 10658 /* vsr40_tx_dig_regs :: tx_misr :: tx_vco_cal_lost [03:03] */ 10659 #define VSR40_TX_DIG_REGS_TX_MISR_TX_VCO_CAL_LOST_MASK 0x0008 10660 #define VSR40_TX_DIG_REGS_TX_MISR_TX_VCO_CAL_LOST_ALIGN 0 10661 #define VSR40_TX_DIG_REGS_TX_MISR_TX_VCO_CAL_LOST_BITS 1 10662 #define VSR40_TX_DIG_REGS_TX_MISR_TX_VCO_CAL_LOST_SHIFT 3 10663 10664 /* vsr40_tx_dig_regs :: tx_misr :: tx_vco_cal_done [02:02] */ 10665 #define VSR40_TX_DIG_REGS_TX_MISR_TX_VCO_CAL_DONE_MASK 0x0004 10666 #define VSR40_TX_DIG_REGS_TX_MISR_TX_VCO_CAL_DONE_ALIGN 0 10667 #define VSR40_TX_DIG_REGS_TX_MISR_TX_VCO_CAL_DONE_BITS 1 10668 #define VSR40_TX_DIG_REGS_TX_MISR_TX_VCO_CAL_DONE_SHIFT 2 10669 10670 /* vsr40_tx_dig_regs :: tx_misr :: tx_pll_lost_lock [01:01] */ 10671 #define VSR40_TX_DIG_REGS_TX_MISR_TX_PLL_LOST_LOCK_MASK 0x0002 10672 #define VSR40_TX_DIG_REGS_TX_MISR_TX_PLL_LOST_LOCK_ALIGN 0 10673 #define VSR40_TX_DIG_REGS_TX_MISR_TX_PLL_LOST_LOCK_BITS 1 10674 #define VSR40_TX_DIG_REGS_TX_MISR_TX_PLL_LOST_LOCK_SHIFT 1 10675 10676 /* vsr40_tx_dig_regs :: tx_misr :: tx_pll_lock [00:00] */ 10677 #define VSR40_TX_DIG_REGS_TX_MISR_TX_PLL_LOCK_MASK 0x0001 10678 #define VSR40_TX_DIG_REGS_TX_MISR_TX_PLL_LOCK_ALIGN 0 10679 #define VSR40_TX_DIG_REGS_TX_MISR_TX_PLL_LOCK_BITS 1 10680 #define VSR40_TX_DIG_REGS_TX_MISR_TX_PLL_LOCK_SHIFT 0 10681 10682 10683 /**************************************************************************** 10684 * vsr40_tx_dig_regs :: tx_mimr 10685 */ 10686 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tx_intr_rsvd [15:08] */ 10687 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_INTR_RSVD_MASK 0xff00 10688 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_INTR_RSVD_ALIGN 0 10689 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_INTR_RSVD_BITS 8 10690 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_INTR_RSVD_SHIFT 8 10691 10692 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tpc_iir_sat_ch3 [07:07] */ 10693 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH3_MASK 0x0080 10694 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH3_ALIGN 0 10695 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH3_BITS 1 10696 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH3_SHIFT 7 10697 10698 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tpc_iir_sat_ch2 [06:06] */ 10699 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH2_MASK 0x0040 10700 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH2_ALIGN 0 10701 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH2_BITS 1 10702 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH2_SHIFT 6 10703 10704 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tpc_iir_sat_ch1 [05:05] */ 10705 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH1_MASK 0x0020 10706 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH1_ALIGN 0 10707 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH1_BITS 1 10708 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH1_SHIFT 5 10709 10710 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tpc_iir_sat_ch0 [04:04] */ 10711 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH0_MASK 0x0010 10712 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH0_ALIGN 0 10713 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH0_BITS 1 10714 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TPC_IIR_SAT_CH0_SHIFT 4 10715 10716 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tx_vco_cal_lost [03:03] */ 10717 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_VCO_CAL_LOST_MASK 0x0008 10718 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_VCO_CAL_LOST_ALIGN 0 10719 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_VCO_CAL_LOST_BITS 1 10720 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_VCO_CAL_LOST_SHIFT 3 10721 10722 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tx_vco_cal_done [02:02] */ 10723 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_VCO_CAL_DONE_MASK 0x0004 10724 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_VCO_CAL_DONE_ALIGN 0 10725 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_VCO_CAL_DONE_BITS 1 10726 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_VCO_CAL_DONE_SHIFT 2 10727 10728 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tx_pll_lost_lock [01:01] */ 10729 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_PLL_LOST_LOCK_MASK 0x0002 10730 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_PLL_LOST_LOCK_ALIGN 0 10731 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_PLL_LOST_LOCK_BITS 1 10732 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_PLL_LOST_LOCK_SHIFT 1 10733 10734 /* vsr40_tx_dig_regs :: tx_mimr :: mask_tx_pll_lock [00:00] */ 10735 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_PLL_LOCK_MASK 0x0001 10736 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_PLL_LOCK_ALIGN 0 10737 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_PLL_LOCK_BITS 1 10738 #define VSR40_TX_DIG_REGS_TX_MIMR_MASK_TX_PLL_LOCK_SHIFT 0 10739 10740 10741 /**************************************************************************** 10742 * vsr40_tx_dig_regs :: tx_p_misr 10743 */ 10744 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tx_intr_rsvd [15:08] */ 10745 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_INTR_RSVD_MASK 0xff00 10746 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_INTR_RSVD_ALIGN 0 10747 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_INTR_RSVD_BITS 8 10748 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_INTR_RSVD_SHIFT 8 10749 10750 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tpc_iir_sat_ch3 [07:07] */ 10751 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH3_MASK 0x0080 10752 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH3_ALIGN 0 10753 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH3_BITS 1 10754 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH3_SHIFT 7 10755 10756 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tpc_iir_sat_ch2 [06:06] */ 10757 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH2_MASK 0x0040 10758 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH2_ALIGN 0 10759 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH2_BITS 1 10760 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH2_SHIFT 6 10761 10762 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tpc_iir_sat_ch1 [05:05] */ 10763 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH1_MASK 0x0020 10764 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH1_ALIGN 0 10765 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH1_BITS 1 10766 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH1_SHIFT 5 10767 10768 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tpc_iir_sat_ch0 [04:04] */ 10769 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH0_MASK 0x0010 10770 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH0_ALIGN 0 10771 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH0_BITS 1 10772 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TPC_IIR_SAT_CH0_SHIFT 4 10773 10774 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tx_vco_cal_lost [03:03] */ 10775 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_VCO_CAL_LOST_MASK 0x0008 10776 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_VCO_CAL_LOST_ALIGN 0 10777 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_VCO_CAL_LOST_BITS 1 10778 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_VCO_CAL_LOST_SHIFT 3 10779 10780 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tx_vco_cal_done [02:02] */ 10781 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_VCO_CAL_DONE_MASK 0x0004 10782 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_VCO_CAL_DONE_ALIGN 0 10783 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_VCO_CAL_DONE_BITS 1 10784 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_VCO_CAL_DONE_SHIFT 2 10785 10786 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tx_pll_lost_lock [01:01] */ 10787 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_PLL_LOST_LOCK_MASK 0x0002 10788 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_PLL_LOST_LOCK_ALIGN 0 10789 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_PLL_LOST_LOCK_BITS 1 10790 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_PLL_LOST_LOCK_SHIFT 1 10791 10792 /* vsr40_tx_dig_regs :: tx_p_misr :: p_tx_pll_lock [00:00] */ 10793 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_PLL_LOCK_MASK 0x0001 10794 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_PLL_LOCK_ALIGN 0 10795 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_PLL_LOCK_BITS 1 10796 #define VSR40_TX_DIG_REGS_TX_P_MISR_P_TX_PLL_LOCK_SHIFT 0 10797 10798 10799 /**************************************************************************** 10800 * vsr40_tx_dig_regs :: tca_ctrl 10801 */ 10802 /* vsr40_tx_dig_regs :: tca_ctrl :: reserved0 [15:08] */ 10803 #define VSR40_TX_DIG_REGS_TCA_CTRL_RESERVED0_MASK 0xff00 10804 #define VSR40_TX_DIG_REGS_TCA_CTRL_RESERVED0_ALIGN 0 10805 #define VSR40_TX_DIG_REGS_TCA_CTRL_RESERVED0_BITS 8 10806 #define VSR40_TX_DIG_REGS_TCA_CTRL_RESERVED0_SHIFT 8 10807 10808 /* vsr40_tx_dig_regs :: tca_ctrl :: tca_k_frc [07:07] */ 10809 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_K_FRC_MASK 0x0080 10810 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_K_FRC_ALIGN 0 10811 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_K_FRC_BITS 1 10812 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_K_FRC_SHIFT 7 10813 10814 /* vsr40_tx_dig_regs :: tca_ctrl :: tca_k_frc_val [06:05] */ 10815 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_K_FRC_VAL_MASK 0x0060 10816 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_K_FRC_VAL_ALIGN 0 10817 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_K_FRC_VAL_BITS 2 10818 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_K_FRC_VAL_SHIFT 5 10819 10820 /* vsr40_tx_dig_regs :: tca_ctrl :: tca_add_pdoffst [04:04] */ 10821 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_ADD_PDOFFST_MASK 0x0010 10822 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_ADD_PDOFFST_ALIGN 0 10823 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_ADD_PDOFFST_BITS 1 10824 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_ADD_PDOFFST_SHIFT 4 10825 10826 /* vsr40_tx_dig_regs :: tca_ctrl :: tca_timer_sel [03:02] */ 10827 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_TIMER_SEL_MASK 0x000c 10828 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_TIMER_SEL_ALIGN 0 10829 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_TIMER_SEL_BITS 2 10830 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_TIMER_SEL_SHIFT 2 10831 10832 /* vsr40_tx_dig_regs :: tca_ctrl :: tca_pdout_inv [01:01] */ 10833 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_PDOUT_INV_MASK 0x0002 10834 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_PDOUT_INV_ALIGN 0 10835 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_PDOUT_INV_BITS 1 10836 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_PDOUT_INV_SHIFT 1 10837 10838 /* vsr40_tx_dig_regs :: tca_ctrl :: tca_phs_step_size_sel [00:00] */ 10839 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_PHS_STEP_SIZE_SEL_MASK 0x0001 10840 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_PHS_STEP_SIZE_SEL_ALIGN 0 10841 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_PHS_STEP_SIZE_SEL_BITS 1 10842 #define VSR40_TX_DIG_REGS_TCA_CTRL_TCA_PHS_STEP_SIZE_SEL_SHIFT 0 10843 10844 10845 /**************************************************************************** 10846 * vsr40_tx_dig_regs :: tca_status 10847 */ 10848 /* vsr40_tx_dig_regs :: tca_status :: reserved0 [15:03] */ 10849 #define VSR40_TX_DIG_REGS_TCA_STATUS_RESERVED0_MASK 0xfff8 10850 #define VSR40_TX_DIG_REGS_TCA_STATUS_RESERVED0_ALIGN 0 10851 #define VSR40_TX_DIG_REGS_TCA_STATUS_RESERVED0_BITS 13 10852 #define VSR40_TX_DIG_REGS_TCA_STATUS_RESERVED0_SHIFT 3 10853 10854 /* vsr40_tx_dig_regs :: tca_status :: vsr40_tx_algnmnt_done_ch3 [02:02] */ 10855 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH3_MASK 0x0004 10856 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH3_ALIGN 0 10857 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH3_BITS 1 10858 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH3_SHIFT 2 10859 10860 /* vsr40_tx_dig_regs :: tca_status :: vsr40_tx_algnmnt_done_ch2 [01:01] */ 10861 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH2_MASK 0x0002 10862 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH2_ALIGN 0 10863 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH2_BITS 1 10864 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH2_SHIFT 1 10865 10866 /* vsr40_tx_dig_regs :: tca_status :: vsr40_tx_algnmnt_done_ch1 [00:00] */ 10867 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH1_MASK 0x0001 10868 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH1_ALIGN 0 10869 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH1_BITS 1 10870 #define VSR40_TX_DIG_REGS_TCA_STATUS_VSR40_TX_ALGNMNT_DONE_CH1_SHIFT 0 10871 10872 10873 /**************************************************************************** 10874 * vsr40_tx_pll_regs 10875 */ 10876 /**************************************************************************** 10877 * vsr40_tx_pll :: control7 10878 */ 10879 /* vsr40_tx_pll :: control7 :: tx_pll_rsvd_103_90 [15:02] */ 10880 #define VSR40_TX_PLL_CONTROL7_TX_PLL_RSVD_103_90_MASK 0xfffc 10881 #define VSR40_TX_PLL_CONTROL7_TX_PLL_RSVD_103_90_ALIGN 0 10882 #define VSR40_TX_PLL_CONTROL7_TX_PLL_RSVD_103_90_BITS 14 10883 #define VSR40_TX_PLL_CONTROL7_TX_PLL_RSVD_103_90_SHIFT 2 10884 10885 /* vsr40_tx_pll :: control7 :: Tx_tport_cur [01:00] */ 10886 #define VSR40_TX_PLL_CONTROL7_TX_TPORT_CUR_MASK 0x0003 10887 #define VSR40_TX_PLL_CONTROL7_TX_TPORT_CUR_ALIGN 0 10888 #define VSR40_TX_PLL_CONTROL7_TX_TPORT_CUR_BITS 2 10889 #define VSR40_TX_PLL_CONTROL7_TX_TPORT_CUR_SHIFT 0 10890 10891 10892 /**************************************************************************** 10893 * vsr40_tx_pll :: control6 10894 */ 10895 /* vsr40_tx_pll :: control6 :: reserved0 [15:08] */ 10896 #define VSR40_TX_PLL_CONTROL6_RESERVED0_MASK 0xff00 10897 #define VSR40_TX_PLL_CONTROL6_RESERVED0_ALIGN 0 10898 #define VSR40_TX_PLL_CONTROL6_RESERVED0_BITS 8 10899 #define VSR40_TX_PLL_CONTROL6_RESERVED0_SHIFT 8 10900 10901 /* vsr40_tx_pll :: control6 :: Tx_2T_IQbuf_ptat [07:04] */ 10902 #define VSR40_TX_PLL_CONTROL6_TX_2T_IQBUF_PTAT_MASK 0x00f0 10903 #define VSR40_TX_PLL_CONTROL6_TX_2T_IQBUF_PTAT_ALIGN 0 10904 #define VSR40_TX_PLL_CONTROL6_TX_2T_IQBUF_PTAT_BITS 4 10905 #define VSR40_TX_PLL_CONTROL6_TX_2T_IQBUF_PTAT_SHIFT 4 10906 10907 /* vsr40_tx_pll :: control6 :: Tx_2T_IQbuf_bgcr [03:00] */ 10908 #define VSR40_TX_PLL_CONTROL6_TX_2T_IQBUF_BGCR_MASK 0x000f 10909 #define VSR40_TX_PLL_CONTROL6_TX_2T_IQBUF_BGCR_ALIGN 0 10910 #define VSR40_TX_PLL_CONTROL6_TX_2T_IQBUF_BGCR_BITS 4 10911 #define VSR40_TX_PLL_CONTROL6_TX_2T_IQBUF_BGCR_SHIFT 0 10912 10913 10914 /**************************************************************************** 10915 * vsr40_tx_pll :: control5 10916 */ 10917 /* vsr40_tx_pll :: control5 :: reserved_for_eco0 [15:13] */ 10918 #define VSR40_TX_PLL_CONTROL5_RESERVED_FOR_ECO0_MASK 0xe000 10919 #define VSR40_TX_PLL_CONTROL5_RESERVED_FOR_ECO0_ALIGN 0 10920 #define VSR40_TX_PLL_CONTROL5_RESERVED_FOR_ECO0_BITS 3 10921 #define VSR40_TX_PLL_CONTROL5_RESERVED_FOR_ECO0_SHIFT 13 10922 10923 /* vsr40_tx_pll :: control5 :: Tx_cupll_vcxosel [12:11] */ 10924 #define VSR40_TX_PLL_CONTROL5_TX_CUPLL_VCXOSEL_MASK 0x1800 10925 #define VSR40_TX_PLL_CONTROL5_TX_CUPLL_VCXOSEL_ALIGN 0 10926 #define VSR40_TX_PLL_CONTROL5_TX_CUPLL_VCXOSEL_BITS 2 10927 #define VSR40_TX_PLL_CONTROL5_TX_CUPLL_VCXOSEL_SHIFT 11 10928 10929 /* vsr40_tx_pll :: control5 :: Tx_pll_test_ref_sel [10:10] */ 10930 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_REF_SEL_MASK 0x0400 10931 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_REF_SEL_ALIGN 0 10932 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_REF_SEL_BITS 1 10933 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_REF_SEL_SHIFT 10 10934 10935 /* vsr40_tx_pll :: control5 :: Tx_cupll_qpcur [09:05] */ 10936 #define VSR40_TX_PLL_CONTROL5_TX_CUPLL_QPCUR_MASK 0x03e0 10937 #define VSR40_TX_PLL_CONTROL5_TX_CUPLL_QPCUR_ALIGN 0 10938 #define VSR40_TX_PLL_CONTROL5_TX_CUPLL_QPCUR_BITS 5 10939 #define VSR40_TX_PLL_CONTROL5_TX_CUPLL_QPCUR_SHIFT 5 10940 10941 /* vsr40_tx_pll :: control5 :: Tx_pll_test_clk [04:04] */ 10942 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_CLK_MASK 0x0010 10943 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_CLK_ALIGN 0 10944 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_CLK_BITS 1 10945 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_CLK_SHIFT 4 10946 10947 /* vsr40_tx_pll :: control5 :: Tx_pll_test_vc [03:03] */ 10948 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_VC_MASK 0x0008 10949 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_VC_ALIGN 0 10950 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_VC_BITS 1 10951 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TEST_VC_SHIFT 3 10952 10953 /* vsr40_tx_pll :: control5 :: Tx_bg_test_vbg [02:02] */ 10954 #define VSR40_TX_PLL_CONTROL5_TX_BG_TEST_VBG_MASK 0x0004 10955 #define VSR40_TX_PLL_CONTROL5_TX_BG_TEST_VBG_ALIGN 0 10956 #define VSR40_TX_PLL_CONTROL5_TX_BG_TEST_VBG_BITS 1 10957 #define VSR40_TX_PLL_CONTROL5_TX_BG_TEST_VBG_SHIFT 2 10958 10959 /* vsr40_tx_pll :: control5 :: tx_pll_rsvd_68 [01:01] */ 10960 #define VSR40_TX_PLL_CONTROL5_TX_PLL_RSVD_68_MASK 0x0002 10961 #define VSR40_TX_PLL_CONTROL5_TX_PLL_RSVD_68_ALIGN 0 10962 #define VSR40_TX_PLL_CONTROL5_TX_PLL_RSVD_68_BITS 1 10963 #define VSR40_TX_PLL_CONTROL5_TX_PLL_RSVD_68_SHIFT 1 10964 10965 /* vsr40_tx_pll :: control5 :: Tx_pll_tp_tailchg_en [00:00] */ 10966 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TP_TAILCHG_EN_MASK 0x0001 10967 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TP_TAILCHG_EN_ALIGN 0 10968 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TP_TAILCHG_EN_BITS 1 10969 #define VSR40_TX_PLL_CONTROL5_TX_PLL_TP_TAILCHG_EN_SHIFT 0 10970 10971 10972 /**************************************************************************** 10973 * vsr40_tx_pll :: control4 10974 */ 10975 /* vsr40_tx_pll :: control4 :: susm_tx_refsel_frc [15:15] */ 10976 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_REFSEL_FRC_MASK 0x8000 10977 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_REFSEL_FRC_ALIGN 0 10978 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_REFSEL_FRC_BITS 1 10979 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_REFSEL_FRC_SHIFT 15 10980 10981 /* vsr40_tx_pll :: control4 :: susm_tx_refsel [14:13] */ 10982 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_REFSEL_MASK 0x6000 10983 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_REFSEL_ALIGN 0 10984 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_REFSEL_BITS 2 10985 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_REFSEL_SHIFT 13 10986 10987 /* vsr40_tx_pll :: control4 :: susm_tx_en_e100g_frc [12:12] */ 10988 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_E100G_FRC_MASK 0x1000 10989 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_E100G_FRC_ALIGN 0 10990 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_E100G_FRC_BITS 1 10991 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_E100G_FRC_SHIFT 12 10992 10993 /* vsr40_tx_pll :: control4 :: susm_tx_en_e100g [11:11] */ 10994 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_E100G_MASK 0x0800 10995 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_E100G_ALIGN 0 10996 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_E100G_BITS 1 10997 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_E100G_SHIFT 11 10998 10999 /* vsr40_tx_pll :: control4 :: susm_tx_en_25g_frc [10:10] */ 11000 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_25G_FRC_MASK 0x0400 11001 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_25G_FRC_ALIGN 0 11002 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_25G_FRC_BITS 1 11003 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_25G_FRC_SHIFT 10 11004 11005 /* vsr40_tx_pll :: control4 :: susm_tx_en_25g [09:09] */ 11006 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_25G_MASK 0x0200 11007 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_25G_ALIGN 0 11008 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_25G_BITS 1 11009 #define VSR40_TX_PLL_CONTROL4_SUSM_TX_EN_25G_SHIFT 9 11010 11011 /* vsr40_tx_pll :: control4 :: ENDUALREF [08:08] */ 11012 #define VSR40_TX_PLL_CONTROL4_ENDUALREF_MASK 0x0100 11013 #define VSR40_TX_PLL_CONTROL4_ENDUALREF_ALIGN 0 11014 #define VSR40_TX_PLL_CONTROL4_ENDUALREF_BITS 1 11015 #define VSR40_TX_PLL_CONTROL4_ENDUALREF_SHIFT 8 11016 11017 /* vsr40_tx_pll :: control4 :: CMUSEL_1 [07:07] */ 11018 #define VSR40_TX_PLL_CONTROL4_CMUSEL_1_MASK 0x0080 11019 #define VSR40_TX_PLL_CONTROL4_CMUSEL_1_ALIGN 0 11020 #define VSR40_TX_PLL_CONTROL4_CMUSEL_1_BITS 1 11021 #define VSR40_TX_PLL_CONTROL4_CMUSEL_1_SHIFT 7 11022 11023 /* vsr40_tx_pll :: control4 :: CMUSEL_0 [06:06] */ 11024 #define VSR40_TX_PLL_CONTROL4_CMUSEL_0_MASK 0x0040 11025 #define VSR40_TX_PLL_CONTROL4_CMUSEL_0_ALIGN 0 11026 #define VSR40_TX_PLL_CONTROL4_CMUSEL_0_BITS 1 11027 #define VSR40_TX_PLL_CONTROL4_CMUSEL_0_SHIFT 6 11028 11029 /* vsr40_tx_pll :: control4 :: Tx_bg_pwrdn [05:05] */ 11030 #define VSR40_TX_PLL_CONTROL4_TX_BG_PWRDN_MASK 0x0020 11031 #define VSR40_TX_PLL_CONTROL4_TX_BG_PWRDN_ALIGN 0 11032 #define VSR40_TX_PLL_CONTROL4_TX_BG_PWRDN_BITS 1 11033 #define VSR40_TX_PLL_CONTROL4_TX_BG_PWRDN_SHIFT 5 11034 11035 /* vsr40_tx_pll :: control4 :: Tx_pll_pwrdn [04:04] */ 11036 #define VSR40_TX_PLL_CONTROL4_TX_PLL_PWRDN_MASK 0x0010 11037 #define VSR40_TX_PLL_CONTROL4_TX_PLL_PWRDN_ALIGN 0 11038 #define VSR40_TX_PLL_CONTROL4_TX_PLL_PWRDN_BITS 1 11039 #define VSR40_TX_PLL_CONTROL4_TX_PLL_PWRDN_SHIFT 4 11040 11041 /* vsr40_tx_pll :: control4 :: Tx_bg_ptatadj [03:00] */ 11042 #define VSR40_TX_PLL_CONTROL4_TX_BG_PTATADJ_MASK 0x000f 11043 #define VSR40_TX_PLL_CONTROL4_TX_BG_PTATADJ_ALIGN 0 11044 #define VSR40_TX_PLL_CONTROL4_TX_BG_PTATADJ_BITS 4 11045 #define VSR40_TX_PLL_CONTROL4_TX_BG_PTATADJ_SHIFT 0 11046 11047 11048 /**************************************************************************** 11049 * vsr40_tx_pll :: control3 11050 */ 11051 /* vsr40_tx_pll :: control3 :: Tx_bg_ctatadj [15:12] */ 11052 #define VSR40_TX_PLL_CONTROL3_TX_BG_CTATADJ_MASK 0xf000 11053 #define VSR40_TX_PLL_CONTROL3_TX_BG_CTATADJ_ALIGN 0 11054 #define VSR40_TX_PLL_CONTROL3_TX_BG_CTATADJ_BITS 4 11055 #define VSR40_TX_PLL_CONTROL3_TX_BG_CTATADJ_SHIFT 12 11056 11057 /* vsr40_tx_pll :: control3 :: Tx_cupll_gmcur [11:10] */ 11058 #define VSR40_TX_PLL_CONTROL3_TX_CUPLL_GMCUR_MASK 0x0c00 11059 #define VSR40_TX_PLL_CONTROL3_TX_CUPLL_GMCUR_ALIGN 0 11060 #define VSR40_TX_PLL_CONTROL3_TX_CUPLL_GMCUR_BITS 2 11061 #define VSR40_TX_PLL_CONTROL3_TX_CUPLL_GMCUR_SHIFT 10 11062 11063 /* vsr40_tx_pll :: control3 :: Tx_cupll_cmv [09:08] */ 11064 #define VSR40_TX_PLL_CONTROL3_TX_CUPLL_CMV_MASK 0x0300 11065 #define VSR40_TX_PLL_CONTROL3_TX_CUPLL_CMV_ALIGN 0 11066 #define VSR40_TX_PLL_CONTROL3_TX_CUPLL_CMV_BITS 2 11067 #define VSR40_TX_PLL_CONTROL3_TX_CUPLL_CMV_SHIFT 8 11068 11069 /* vsr40_tx_pll :: control3 :: Tx_vco_range_frc [07:07] */ 11070 #define VSR40_TX_PLL_CONTROL3_TX_VCO_RANGE_FRC_MASK 0x0080 11071 #define VSR40_TX_PLL_CONTROL3_TX_VCO_RANGE_FRC_ALIGN 0 11072 #define VSR40_TX_PLL_CONTROL3_TX_VCO_RANGE_FRC_BITS 1 11073 #define VSR40_TX_PLL_CONTROL3_TX_VCO_RANGE_FRC_SHIFT 7 11074 11075 /* vsr40_tx_pll :: control3 :: Tx_vco_range [06:00] */ 11076 #define VSR40_TX_PLL_CONTROL3_TX_VCO_RANGE_MASK 0x007f 11077 #define VSR40_TX_PLL_CONTROL3_TX_VCO_RANGE_ALIGN 0 11078 #define VSR40_TX_PLL_CONTROL3_TX_VCO_RANGE_BITS 7 11079 #define VSR40_TX_PLL_CONTROL3_TX_VCO_RANGE_SHIFT 0 11080 11081 11082 /**************************************************************************** 11083 * vsr40_tx_pll :: control2 11084 */ 11085 /* vsr40_tx_pll :: control2 :: Tx_vco_cur [15:15] */ 11086 #define VSR40_TX_PLL_CONTROL2_TX_VCO_CUR_MASK 0x8000 11087 #define VSR40_TX_PLL_CONTROL2_TX_VCO_CUR_ALIGN 0 11088 #define VSR40_TX_PLL_CONTROL2_TX_VCO_CUR_BITS 1 11089 #define VSR40_TX_PLL_CONTROL2_TX_VCO_CUR_SHIFT 15 11090 11091 /* vsr40_tx_pll :: control2 :: susm_tx_vco_en25G_frc [14:14] */ 11092 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_VCO_EN25G_FRC_MASK 0x4000 11093 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_VCO_EN25G_FRC_ALIGN 0 11094 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_VCO_EN25G_FRC_BITS 1 11095 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_VCO_EN25G_FRC_SHIFT 14 11096 11097 /* vsr40_tx_pll :: control2 :: susm_tx_vco_en25G [13:13] */ 11098 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_VCO_EN25G_MASK 0x2000 11099 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_VCO_EN25G_ALIGN 0 11100 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_VCO_EN25G_BITS 1 11101 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_VCO_EN25G_SHIFT 13 11102 11103 /* vsr40_tx_pll :: control2 :: susm_tx_en_VSR_frc [12:12] */ 11104 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_EN_VSR_FRC_MASK 0x1000 11105 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_EN_VSR_FRC_ALIGN 0 11106 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_EN_VSR_FRC_BITS 1 11107 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_EN_VSR_FRC_SHIFT 12 11108 11109 /* vsr40_tx_pll :: control2 :: susm_tx_en_VSR [11:11] */ 11110 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_EN_VSR_MASK 0x0800 11111 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_EN_VSR_ALIGN 0 11112 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_EN_VSR_BITS 1 11113 #define VSR40_TX_PLL_CONTROL2_SUSM_TX_EN_VSR_SHIFT 11 11114 11115 /* vsr40_tx_pll :: control2 :: Tx_test_tx1_sel [10:10] */ 11116 #define VSR40_TX_PLL_CONTROL2_TX_TEST_TX1_SEL_MASK 0x0400 11117 #define VSR40_TX_PLL_CONTROL2_TX_TEST_TX1_SEL_ALIGN 0 11118 #define VSR40_TX_PLL_CONTROL2_TX_TEST_TX1_SEL_BITS 1 11119 #define VSR40_TX_PLL_CONTROL2_TX_TEST_TX1_SEL_SHIFT 10 11120 11121 /* vsr40_tx_pll :: control2 :: Tx_test_tx_clk [09:09] */ 11122 #define VSR40_TX_PLL_CONTROL2_TX_TEST_TX_CLK_MASK 0x0200 11123 #define VSR40_TX_PLL_CONTROL2_TX_TEST_TX_CLK_ALIGN 0 11124 #define VSR40_TX_PLL_CONTROL2_TX_TEST_TX_CLK_BITS 1 11125 #define VSR40_TX_PLL_CONTROL2_TX_TEST_TX_CLK_SHIFT 9 11126 11127 /* vsr40_tx_pll :: control2 :: Txpll_rescal_frc [08:08] */ 11128 #define VSR40_TX_PLL_CONTROL2_TXPLL_RESCAL_FRC_MASK 0x0100 11129 #define VSR40_TX_PLL_CONTROL2_TXPLL_RESCAL_FRC_ALIGN 0 11130 #define VSR40_TX_PLL_CONTROL2_TXPLL_RESCAL_FRC_BITS 1 11131 #define VSR40_TX_PLL_CONTROL2_TXPLL_RESCAL_FRC_SHIFT 8 11132 11133 /* vsr40_tx_pll :: control2 :: Txpll_rescal [07:05] */ 11134 #define VSR40_TX_PLL_CONTROL2_TXPLL_RESCAL_MASK 0x00e0 11135 #define VSR40_TX_PLL_CONTROL2_TXPLL_RESCAL_ALIGN 0 11136 #define VSR40_TX_PLL_CONTROL2_TXPLL_RESCAL_BITS 3 11137 #define VSR40_TX_PLL_CONTROL2_TXPLL_RESCAL_SHIFT 5 11138 11139 /* vsr40_tx_pll :: control2 :: Tx_1Tbuf1_band_frc [04:04] */ 11140 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_BAND_FRC_MASK 0x0010 11141 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_BAND_FRC_ALIGN 0 11142 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_BAND_FRC_BITS 1 11143 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_BAND_FRC_SHIFT 4 11144 11145 /* vsr40_tx_pll :: control2 :: Tx_1Tbuf1_band [03:02] */ 11146 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_BAND_MASK 0x000c 11147 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_BAND_ALIGN 0 11148 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_BAND_BITS 2 11149 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_BAND_SHIFT 2 11150 11151 /* vsr40_tx_pll :: control2 :: Tx_1Tbuf1_cur [01:00] */ 11152 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_CUR_MASK 0x0003 11153 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_CUR_ALIGN 0 11154 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_CUR_BITS 2 11155 #define VSR40_TX_PLL_CONTROL2_TX_1TBUF1_CUR_SHIFT 0 11156 11157 11158 /**************************************************************************** 11159 * vsr40_tx_pll :: control1 11160 */ 11161 /* vsr40_tx_pll :: control1 :: reserved_for_eco0 [15:15] */ 11162 #define VSR40_TX_PLL_CONTROL1_RESERVED_FOR_ECO0_MASK 0x8000 11163 #define VSR40_TX_PLL_CONTROL1_RESERVED_FOR_ECO0_ALIGN 0 11164 #define VSR40_TX_PLL_CONTROL1_RESERVED_FOR_ECO0_BITS 1 11165 #define VSR40_TX_PLL_CONTROL1_RESERVED_FOR_ECO0_SHIFT 15 11166 11167 /* vsr40_tx_pll :: control1 :: Tx_capctrl_IQbuf [14:11] */ 11168 #define VSR40_TX_PLL_CONTROL1_TX_CAPCTRL_IQBUF_MASK 0x7800 11169 #define VSR40_TX_PLL_CONTROL1_TX_CAPCTRL_IQBUF_ALIGN 0 11170 #define VSR40_TX_PLL_CONTROL1_TX_CAPCTRL_IQBUF_BITS 4 11171 #define VSR40_TX_PLL_CONTROL1_TX_CAPCTRL_IQBUF_SHIFT 11 11172 11173 /* vsr40_tx_pll :: control1 :: Tx_encurrent_IQbuf_frc [10:10] */ 11174 #define VSR40_TX_PLL_CONTROL1_TX_ENCURRENT_IQBUF_FRC_MASK 0x0400 11175 #define VSR40_TX_PLL_CONTROL1_TX_ENCURRENT_IQBUF_FRC_ALIGN 0 11176 #define VSR40_TX_PLL_CONTROL1_TX_ENCURRENT_IQBUF_FRC_BITS 1 11177 #define VSR40_TX_PLL_CONTROL1_TX_ENCURRENT_IQBUF_FRC_SHIFT 10 11178 11179 /* vsr40_tx_pll :: control1 :: Tx_encurrent_IQbuf [09:09] */ 11180 #define VSR40_TX_PLL_CONTROL1_TX_ENCURRENT_IQBUF_MASK 0x0200 11181 #define VSR40_TX_PLL_CONTROL1_TX_ENCURRENT_IQBUF_ALIGN 0 11182 #define VSR40_TX_PLL_CONTROL1_TX_ENCURRENT_IQBUF_BITS 1 11183 #define VSR40_TX_PLL_CONTROL1_TX_ENCURRENT_IQBUF_SHIFT 9 11184 11185 /* vsr40_tx_pll :: control1 :: Tx_1Tdiv_cur [08:06] */ 11186 #define VSR40_TX_PLL_CONTROL1_TX_1TDIV_CUR_MASK 0x01c0 11187 #define VSR40_TX_PLL_CONTROL1_TX_1TDIV_CUR_ALIGN 0 11188 #define VSR40_TX_PLL_CONTROL1_TX_1TDIV_CUR_BITS 3 11189 #define VSR40_TX_PLL_CONTROL1_TX_1TDIV_CUR_SHIFT 6 11190 11191 /* vsr40_tx_pll :: control1 :: susm_tx_ref_div_frc [05:05] */ 11192 #define VSR40_TX_PLL_CONTROL1_SUSM_TX_REF_DIV_FRC_MASK 0x0020 11193 #define VSR40_TX_PLL_CONTROL1_SUSM_TX_REF_DIV_FRC_ALIGN 0 11194 #define VSR40_TX_PLL_CONTROL1_SUSM_TX_REF_DIV_FRC_BITS 1 11195 #define VSR40_TX_PLL_CONTROL1_SUSM_TX_REF_DIV_FRC_SHIFT 5 11196 11197 /* vsr40_tx_pll :: control1 :: susm_tx_ref_div [04:03] */ 11198 #define VSR40_TX_PLL_CONTROL1_SUSM_TX_REF_DIV_MASK 0x0018 11199 #define VSR40_TX_PLL_CONTROL1_SUSM_TX_REF_DIV_ALIGN 0 11200 #define VSR40_TX_PLL_CONTROL1_SUSM_TX_REF_DIV_BITS 2 11201 #define VSR40_TX_PLL_CONTROL1_SUSM_TX_REF_DIV_SHIFT 3 11202 11203 /* vsr40_tx_pll :: control1 :: Tx_2Tbufdiv_cur [02:00] */ 11204 #define VSR40_TX_PLL_CONTROL1_TX_2TBUFDIV_CUR_MASK 0x0007 11205 #define VSR40_TX_PLL_CONTROL1_TX_2TBUFDIV_CUR_ALIGN 0 11206 #define VSR40_TX_PLL_CONTROL1_TX_2TBUFDIV_CUR_BITS 3 11207 #define VSR40_TX_PLL_CONTROL1_TX_2TBUFDIV_CUR_SHIFT 0 11208 11209 11210 /**************************************************************************** 11211 * vsr40_tx_pll :: control0 11212 */ 11213 /* vsr40_tx_pll :: control0 :: reserved_for_eco0 [15:14] */ 11214 #define VSR40_TX_PLL_CONTROL0_RESERVED_FOR_ECO0_MASK 0xc000 11215 #define VSR40_TX_PLL_CONTROL0_RESERVED_FOR_ECO0_ALIGN 0 11216 #define VSR40_TX_PLL_CONTROL0_RESERVED_FOR_ECO0_BITS 2 11217 #define VSR40_TX_PLL_CONTROL0_RESERVED_FOR_ECO0_SHIFT 14 11218 11219 /* vsr40_tx_pll :: control0 :: Tx_tport_hicur [13:13] */ 11220 #define VSR40_TX_PLL_CONTROL0_TX_TPORT_HICUR_MASK 0x2000 11221 #define VSR40_TX_PLL_CONTROL0_TX_TPORT_HICUR_ALIGN 0 11222 #define VSR40_TX_PLL_CONTROL0_TX_TPORT_HICUR_BITS 1 11223 #define VSR40_TX_PLL_CONTROL0_TX_TPORT_HICUR_SHIFT 13 11224 11225 /* vsr40_tx_pll :: control0 :: ana_rsrvd_12 [12:12] */ 11226 #define VSR40_TX_PLL_CONTROL0_ANA_RSRVD_12_MASK 0x1000 11227 #define VSR40_TX_PLL_CONTROL0_ANA_RSRVD_12_ALIGN 0 11228 #define VSR40_TX_PLL_CONTROL0_ANA_RSRVD_12_BITS 1 11229 #define VSR40_TX_PLL_CONTROL0_ANA_RSRVD_12_SHIFT 12 11230 11231 /* vsr40_tx_pll :: control0 :: ana_rsrvd_11 [11:11] */ 11232 #define VSR40_TX_PLL_CONTROL0_ANA_RSRVD_11_MASK 0x0800 11233 #define VSR40_TX_PLL_CONTROL0_ANA_RSRVD_11_ALIGN 0 11234 #define VSR40_TX_PLL_CONTROL0_ANA_RSRVD_11_BITS 1 11235 #define VSR40_TX_PLL_CONTROL0_ANA_RSRVD_11_SHIFT 11 11236 11237 /* vsr40_tx_pll :: control0 :: Tx_cp [10:09] */ 11238 #define VSR40_TX_PLL_CONTROL0_TX_CP_MASK 0x0600 11239 #define VSR40_TX_PLL_CONTROL0_TX_CP_ALIGN 0 11240 #define VSR40_TX_PLL_CONTROL0_TX_CP_BITS 2 11241 #define VSR40_TX_PLL_CONTROL0_TX_CP_SHIFT 9 11242 11243 /* vsr40_tx_pll :: control0 :: Tx_rz [08:06] */ 11244 #define VSR40_TX_PLL_CONTROL0_TX_RZ_MASK 0x01c0 11245 #define VSR40_TX_PLL_CONTROL0_TX_RZ_ALIGN 0 11246 #define VSR40_TX_PLL_CONTROL0_TX_RZ_BITS 3 11247 #define VSR40_TX_PLL_CONTROL0_TX_RZ_SHIFT 6 11248 11249 /* vsr40_tx_pll :: control0 :: Tx_qp_cur [05:02] */ 11250 #define VSR40_TX_PLL_CONTROL0_TX_QP_CUR_MASK 0x003c 11251 #define VSR40_TX_PLL_CONTROL0_TX_QP_CUR_ALIGN 0 11252 #define VSR40_TX_PLL_CONTROL0_TX_QP_CUR_BITS 4 11253 #define VSR40_TX_PLL_CONTROL0_TX_QP_CUR_SHIFT 2 11254 11255 /* vsr40_tx_pll :: control0 :: Tx_qp_VDD_BGb [01:01] */ 11256 #define VSR40_TX_PLL_CONTROL0_TX_QP_VDD_BGB_MASK 0x0002 11257 #define VSR40_TX_PLL_CONTROL0_TX_QP_VDD_BGB_ALIGN 0 11258 #define VSR40_TX_PLL_CONTROL0_TX_QP_VDD_BGB_BITS 1 11259 #define VSR40_TX_PLL_CONTROL0_TX_QP_VDD_BGB_SHIFT 1 11260 11261 /* vsr40_tx_pll :: control0 :: Tx_tport_sel_ana_n [00:00] */ 11262 #define VSR40_TX_PLL_CONTROL0_TX_TPORT_SEL_ANA_N_MASK 0x0001 11263 #define VSR40_TX_PLL_CONTROL0_TX_TPORT_SEL_ANA_N_ALIGN 0 11264 #define VSR40_TX_PLL_CONTROL0_TX_TPORT_SEL_ANA_N_BITS 1 11265 #define VSR40_TX_PLL_CONTROL0_TX_TPORT_SEL_ANA_N_SHIFT 0 11266 11267 11268 /**************************************************************************** 11269 * Datatype Definitions. 11270 */ 11271 #endif /* #ifndef PHY84793_H__ */ 11272 11273 /* End of File */ 11274