phy84756_fcmap_int.h (104205B)
1 2 /* 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 9 #ifndef _PHY84756_INT_H 10 #define _PHY84756_INT_H 11 12 /**************************************************************************** 13 * Firmware related: 14 */ 15 #define BFCMAP_PHY84756_FW_CHECKSUM 0x600D 16 #define BFCMAP_PHY84756_FW_NUM_ITER 5 17 18 #define BFCMAP_PHY84756_FW_DWNLD_DONE_MSG 0x4321 19 #define BFCMAP_PHY84756_FW_TOTAL_WR_BYTE 0x4000 20 21 #define BFCMAP_PHY84756_PMAD_M8051_MSGIN_REG 0xca12 22 #define BFCMAP_PHY84756_PMAD_M8051_MSGOUT_REG 0xca13 23 24 #define BFCMAP_PHY84756_IS_10G_CHANNEL(dev_port) \ 25 ((dev_port == 0) || (dev_port ==1)) 26 27 #define BFCMAP_PHY84756_IS_GIG_ONLY_CHANNEL(dev_port) \ 28 ((dev_port == 2) || (dev_port ==3)) 29 30 31 /* Channel 2 and 3 Device 1 SGMII : */ 32 33 /* 34 * MII Link Advertisment (Clause 37) 35 */ 36 #define BFCMAP_PHY84756_DEV1_1000X_ANA_C37_FD (1 << 5) 37 #define BFCMAP_PHY84756_DEV1_1000X_ANA_C37_HD (1 << 6) 38 #define BFCMAP_PHY84756_DEV1_1000X_ANA_C37_PAUSE (1 << 7) 39 #define BFCMAP_PHY84756_DEV1_1000X_ANA_C37_ASYM_PAUSE (1 << 8) 40 41 42 43 /* MII Control register definations */ 44 #define BFCMAP_PHY84756_SGMII_MII_CTRL_SS_MSB (1 << 6) /* Speed select, MSb */ 45 #define BFCMAP_PHY84756_SGMII_MII_CTRL_FD (1 << 8) /* Full Duplex */ 46 #define BFCMAP_PHY84756_SGMII_MII_CTRL_RAN (1 << 9) /* Restart Autoneg*/ 47 #define BFCMAP_PHY84756_SGMII_MII_CTRL_PD (1 << 11) /* Power Down */ 48 #define BFCMAP_PHY84756_SGMII_MII_CTRL_AE (1 << 12) /* Autoneg enable */ 49 #define BFCMAP_PHY84756_SGMII_MII_CTRL_SS_LSB (1 << 13) /* Speed select, LSb */ 50 #define BFCMAP_PHY84756_SGMII_MII_CTRL_LE (1 << 14) /* Loopback enable */ 51 #define BFCMAP_PHY84756_SGMII_MII_CTRL_RESET (1 << 15) /* PHY reset */ 52 53 #define BFCMAP_PHY84756_SGMII_MII_CTRL_SS(_x) ((_x) & \ 54 (BFCMAP_PHY84756_SGMII_MII_CTRL_SS_LSB | \ 55 BFCMAP_PHY84756_SGMII_MII_CTRL_SS_MSB)) 56 #define BFCMAP_PHY84756_SGMII_MII_CTRL_SS_10 0 57 #define BFCMAP_PHY84756_SGMII_MII_CTRL_SS_100 \ 58 (BFCMAP_PHY84756_SGMII_MII_CTRL_SS_LSB) 59 #define BFCMAP_PHY84756_SGMII_MII_CTRL_SS_1000 \ 60 (BFCMAP_PHY84756_SGMII_MII_CTRL_SS_MSB) 61 #define BFCMAP_PHY84756_SGMII_MII_CTRL_SS_INVALID \ 62 (BFCMAP_PHY84756_SGMII_MII_CTRL_SS_LSB | \ 63 BFCMAP_PHY84756_SGMII_MII_CTRL_SS_MSB) 64 #define BFCMAP_PHY84756_SGMII_MII_CTRL_SS_MASK \ 65 (BFCMAP_PHY84756_SGMII_MII_CTRL_SS_LSB | \ 66 BFCMAP_PHY84756_SGMII_MII_CTRL_SS_MSB) 67 68 /* MII Status register definations */ 69 #define BFCMAP_PHY84756_SGMII_MII_STAT_LINK_STATUS (1 << 2) 70 #define BFCMAP_PHY84756_SGMII_MII_STAT_AN_DONE (1 << 5) 71 72 73 /* 1000x Control1 Register definations */ 74 #define BFCMAP_PHY84756_SGMII_BASE1000X_CTRL1r_FIBER_MODE (1 << 0) 75 #define BFCMAP_PHY84756_SGMII_BASE1000X_CTRL1r_TBI_INT (1 << 1) 76 #define BFCMAP_PHY84756_SGMII_BASE1000X_CTRL1r_SD_ENABLE (1 << 2) 77 #define BFCMAP_PHY84756_SGMII_BASE1000X_CTRL1r_INVERT_SD (1 << 3) 78 #define BFCMAP_PHY84756_SGMII_BASE1000X_CTRL1r_AUTODETECT_EN (1 << 4) 79 #define BFCMAP_PHY84756_SGMII_BASE1000X_CTRL1r_SGMII_MASTER (1 << 5) 80 #define BFCMAP_PHY84756_SGMII_BASE1000X_CTRL1r_DIS_PLL_PWRDN (1 << 6) 81 82 83 /* 1000x Status1 Register definations */ 84 #define BFCMAP_PHY84756_SGMII_BASE1000X_STAT1r_FIBER_MODE (1 << 0) 85 #define BFCMAP_PHY84756_SGMII_BASE1000X_STAT1r_LINK_STATUS (1 << 1) 86 #define BFCMAP_PHY84756_SGMII_BASE1000X_STAT1r_DUPLEX_STATUS (1 << 2) 87 #define BFCMAP_PHY84756_SGMII_BASE1000X_STAT1r_SPEED_STATUS ((1 << 3) | \ 88 (1 << 4)) 89 #define BFCMAP_PHY84756_SGMII_BASE1000X_STAT1r_PAUSE_TX (1 << 5) 90 #define BFCMAP_PHY84756_SGMII_BASE1000X_STAT1r_PAUSE_RX (1 << 6) 91 92 93 /* Speed Link status register defination */ 94 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_LN_PDM_SPEED_10M (1 << 0) 95 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_LN_PDM_SPEED_100M (1 << 1) 96 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_LN_PDM_SPEED_1G (1 << 2) 97 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_LN_AN_COMPLETE (1 << 6) 98 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_LN_RX_SD (1 << 7) 99 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_SYS_PDM_SPEED_10M (1 << 8) 100 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_SYS_PDM_SPEED_100M (1 << 9) 101 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_SYS_PDM_SPEED_1G (1 << 10) 102 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_SYS_AN_COMPLETE (1 << 14) 103 #define BFCMAP_PHY84756_SGMII_SPEED_LD_STATr_SYS_RX_SD (1 << 15) 104 105 /* SGMII MACSEC Control register defination */ 106 #define BFCMAP_PHY84756_SGMII_MACSEC_CTRL_BYPASS_MODE (1 << 0) 107 #define BFCMAP_PHY84756_SGMII_MACSEC_CTRL_ENABLE_PWRDN_MACSEC (1 << 8) 108 #define BFCMAP_PHY84756_SGMII_MACSEC_CTRL_UDSW_PWRDW_MACSEC (1 << 11) 109 #define BFCMAP_PHY84756_SGMII_MACSEC_CTRL_UDSW_RESET_MACSEC (1 << 15) 110 111 112 113 /************************************************************************ 114 * 115 * Channel 0 and 1 : LINE : Device 1 (PMA/PMD) 116 */ 117 118 /* Speed Link status register defination */ 119 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_10M (1 << 0) 120 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_100M (1 << 1) 121 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_1G (1 << 2) 122 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_2P5G (1 << 3) 123 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_10G (1 << 4) 124 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_AN_COMPLETE (1 << 6) 125 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_RX_SD (1 << 7) 126 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_10M (1 << 8) 127 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_100M (1 << 9) 128 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_1G (1 << 10) 129 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_2P5G (1 << 11) 130 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_10G (1 << 12) 131 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_AN_COMPLETE (1 << 14) 132 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_RX_SD (1 << 15) 133 134 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_MASK \ 135 (BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_10M | \ 136 BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_100M | \ 137 BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_1G | \ 138 BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_2P5G | \ 139 BFCMAP_PHY84756_PMD_SPEED_LD_STATr_LN_PDM_SPEED_10G) 140 141 #define BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_MASK \ 142 (BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_10M | \ 143 BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_100M | \ 144 BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_1G | \ 145 BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_2P5G | \ 146 BFCMAP_PHY84756_PMD_SPEED_LD_STATr_SYS_PDM_SPEED_10G) 147 148 149 /* DEV1 MACSEC Control register defination */ 150 #define BFCMAP_PHY84756_LN_DEV1_MACSEC_CTRL_BYPASS_MODE (1 << 0) 151 #define BFCMAP_PHY84756_LN_DEV1_MACSEC_CTRL_ENABLE_PWRDN_MACSEC (1 << 8) 152 #define BFCMAP_PHY84756_LN_DEV1_MACSEC_CTRL_UDSW_PWRDW_MACSEC (1 << 11) 153 #define BFCMAP_PHY84756_LN_DEV1_MACSEC_CTRL_UDSW_RESET_MACSEC (1 << 15) 154 155 156 157 /* PMD Control Register definations */ 158 #define BFCMAP_PHY84756_PMD_CTRL_PMS_LOOPBACK (1 << 0) /* Loopback */ 159 #define BFCMAP_PHY84756_PMD_CTRL_SS_MSB (1 << 6) /* Speed select, MSb */ 160 #define BFCMAP_PHY84756_PMD_CTRL_PD (1 << 11) /* Power Down */ 161 #define BFCMAP_PHY84756_PMD_CTRL_SS_LSB (1 << 13) /* Speed select, LSb */ 162 #define BFCMAP_PHY84756_PMD_CTRL_RESET (1 << 15) /* PHY reset */ 163 164 #define BFCMAP_PHY84756_PMD_CTRL_SS_SPEED_SEL \ 165 (BFCMAP_PHY84756_PMD_CTRL_SS_LSB | \ 166 BFCMAP_PHY84756_PMD_CTRL_SS_MSB) 167 #define BFCMAP_PHY84756_PMD_CTRL_SS_MASK \ 168 (BFCMAP_PHY84756_PMD_CTRL_SS_LSB | \ 169 BFCMAP_PHY84756_PMD_CTRL_SS_MSB) 170 171 #define BFCMAP_PHY84756_PMD_CTRL_10GSS_MASK \ 172 (BFCMAP_PHY84756_PMD_CTRL_SS_LSB | \ 173 BFCMAP_PHY84756_PMD_CTRL_SS_MSB | \ 174 (1 << 2) | \ 175 (1 << 3) | \ 176 (1 << 4) | \ 177 (1 << 5)) 178 179 #define BFCMAP_PHY84756_PMD_CTRL_SS_10 0 180 #define BFCMAP_PHY84756_PMD_CTRL_SS_100 \ 181 (BFCMAP_PHY84756_PMD_CTRL_SS_LSB) 182 #define BFCMAP_PHY84756_PMD_CTRL_SS_1000 (BFCMAP_PHY84756_PMD_CTRL_SS_MSB) 183 #define BFCMAP_PHY84756_PMD_CTRL_SS_10000 \ 184 (BFCMAP_PHY84756_PMD_CTRL_SS_SPEED_SEL | \ 185 (0x0000)) 186 187 188 #define BFCMAP_PHY84756_PMD_CTRL_SS(_x) \ 189 ((_x) & \ 190 (BFCMAP_PHY84756_PMD_CTRL_SS_LSB | \ 191 BFCMAP_PHY84756_PMD_CTRL_SS_MSB)) 192 193 194 195 /* PMD Status Register defination */ 196 #define BFCMAP_PHY84756_PMD_STAT_RX_LINK_STATUS (1 << 2) 197 198 199 200 /* PMD Control2 Resister definations */ 201 #define BFCMAP_PHY84756_PMD_CTRL2_PMA_1GTPMD_TYPE (0xc) 202 #define BFCMAP_PHY84756_PMD_CTRL2_PMA_10GLRMPMD_TYPE (0x8) 203 204 #define BFCMAP_PHY84756_PMD_CTRL2_PMA_SELECT_MASK (0xf) 205 206 /************************************************************************ 207 * 208 * LINE : Device 3 (PCS) 209 */ 210 /*PCS Control register definations */ 211 #define BFCMAP_PHY84756_PCS_PCS_CTRL_PD (1 << 11) 212 213 214 /*PCS Status register definations */ 215 #define BFCMAP_PHY84756_PCS_PCS_STAT_RX_LINK_STATUS (1 << 2) 216 217 218 219 /************************************************************************ 220 * 221 * LINE : Device 7 (AN) 222 */ 223 224 /* 225 * MII Link Advertisment (Clause 37) 226 */ 227 #define BFCMAP_PHY84756_DEV7_1000X_ANA_C37_FD (1 << 5) 228 #define BFCMAP_PHY84756_DEV7_1000X_ANA_C37_HD (1 << 6) 229 #define BFCMAP_PHY84756_DEV7_1000X_ANA_C37_PAUSE (1 << 7) 230 #define BFCMAP_PHY84756_DEV7_1000X_ANA_C37_ASYM_PAUSE (1 << 8) 231 232 233 /* 234 * MII Link Partner Advertisment (Clause 37) 235 */ 236 #define BFCMAP_PHY84756_SGMII_ANP_SGMII_MODE (1 << 0) 237 #define BFCMAP_PHY84756_SGMII_ANP_FD (1 << 5) 238 #define BFCMAP_PHY84756_SGMII_ANP_HD (1 << 6) 239 #define BFCMAP_PHY84756_SGMII_ANP_C37_PAUSE (1 << 7) 240 #define BFCMAP_PHY84756_SGMII_ANPC37_ASYM_PAUSE (1 << 8) 241 242 243 244 245 /*AN MII control register definations */ 246 #define BFCMAP_PHY84756_AN_MII_CTRL_SS_MSB (1 << 6) /* Speed select, MSb */ 247 #define BFCMAP_PHY84756_AN_MII_CTRL_FD (1 << 8) /* Full Duplex */ 248 #define BFCMAP_PHY84756_AN_MII_CTRL_RAN (1 << 9) /* Restart Autoneg `*/ 249 #define BFCMAP_PHY84756_AN_MII_CTRL_PD (1 << 11) /* Power Down */ 250 #define BFCMAP_PHY84756_AN_MII_CTRL_AE (1 << 12) /* Autoneg enable */ 251 #define BFCMAP_PHY84756_AN_MII_CTRL_SS_LSB (1 << 13) /* Speed select, LSb */ 252 #define BFCMAP_PHY84756_AN_MII_CTRL_LE (1 << 14) /* Loopback enable */ 253 #define BFCMAP_PHY84756_AN_MII_CTRL_RESET (1 << 15) /* PHY reset */ 254 255 #define BFCMAP_PHY84756_AN_MII_CTRL_SS(_x) \ 256 ((_x) & \ 257 (BFCMAP_PHY84756_AN_MII_CTRL_SS_LSB | \ 258 BFCMAP_PHY84756_AN_MII_CTRL_SS_MSB)) 259 #define BFCMAP_PHY84756_AN_MII_CTRL_SS_10 0 260 #define BFCMAP_PHY84756_AN_MII_CTRL_SS_100 (BFCMAP_PHY84756_AN_MII_CTRL_SS_LSB) 261 #define BFCMAP_PHY84756_AN_MII_CTRL_SS_1000 (BFCMAP_PHY84756_AN_MII_CTRL_SS_MSB) 262 #define BFCMAP_PHY84756_AN_MII_CTRL_SS_INVALID \ 263 (BFCMAP_PHY84756_AN_MII_CTRL_SS_LSB | \ 264 BFCMAP_PHY84756_AN_MII_CTRL_SS_MSB) 265 #define BFCMAP_PHY84756_AN_MII_CTRL_SS_MASK \ 266 (BFCMAP_PHY84756_AN_MII_CTRL_SS_LSB | \ 267 BFCMAP_PHY84756_AN_MII_CTRL_SS_MSB) 268 269 /* AN MII Status register definations */ 270 #define BFCMAP_PHY84756_AN_MII_STAT_LINK_STATUS (1 << 2) 271 #define BFCMAP_PHY84756_AN_MII_STAT_AN_DONE (1 << 5) 272 273 274 /* AN 1000x Control1 Register definations */ 275 #define BFCMAP_PHY84756_AN_BASE1000X_CTRL1r_FIBER_MODE (1 << 0) 276 #define BFCMAP_PHY84756_AN_BASE1000X_CTRL1r_TBI_INT (1 << 1) 277 #define BFCMAP_PHY84756_AN_BASE1000X_CTRL1r_SD_ENABLE (1 << 2) 278 #define BFCMAP_PHY84756_AN_BASE1000X_CTRL1r_INVERT_SD (1 << 3) 279 #define BFCMAP_PHY84756_AN_BASE1000X_CTRL1r_AUTODETECT_EN (1 << 4) 280 #define BFCMAP_PHY84756_AN_BASE1000X_CTRL1r_SGMII_MASTER (1 << 5) 281 #define BFCMAP_PHY84756_AN_BASE1000X_CTRL1r_DIS_PLL_PWRDN (1 << 6) 282 283 284 /* 1000x Status1 Register definations */ 285 #define BFCMAP_PHY84756_AN_BASE1000X_STAT1r_SGMII_MODE (1 << 0) 286 #define BFCMAP_PHY84756_AN_BASE1000X_STAT1r_LINK_STATUS (1 << 1) 287 #define BFCMAP_PHY84756_AN_BASE1000X_STAT1r_DUPLEX_STATUS (1 << 2) 288 #define BFCMAP_PHY84756_AN_BASE1000X_STAT1r_SPEED_STATUS ((1 << 3) | \ 289 (1 << 4)) 290 #define BFCMAP_PHY84756_AN_BASE1000X_STAT1r_PAUSE_TX (1 << 5) 291 #define BFCMAP_PHY84756_AN_BASE1000X_STAT1r_PAUSE_RX (1 << 6) 292 293 294 295 296 /* AN Control Register */ 297 #define BFCMAP_PHY84756_AN_AN_CTRL_RAN (1 << 9) /* Restart AutoNeg */ 298 #define BFCMAP_PHY84756_AN_AN_CTRL_AE (1 << 12) /* Enable AutoNegn */ 299 #define BFCMAP_PHY84756_AN_AN_CTRL_RESET (1 << 15) /* Reset AutoNeg */ 300 301 /* AN Status Register */ 302 #define BFCMAP_PHY84756_AN_AN_STAT_AN_DONE (1 << 5) 303 304 305 306 307 308 extern int 309 bfcmap_phy84756_reg_read(phy_ctrl_t * pc, buint32_t flags, buint8_t reg_bank, 310 buint16_t reg_addr, buint16_t *data); 311 extern int 312 bfcmap_phy84756_reg_write(phy_ctrl_t * pc, buint32_t flags, buint8_t reg_bank, 313 buint16_t reg_addr, buint16_t data); 314 extern int 315 bfcmap_phy84756_reg_modify(phy_ctrl_t * pc, buint32_t flags, buint8_t reg_bank, 316 buint16_t reg_addr, buint16_t data, buint16_t mask); 317 318 /* Flag indicating that Line side Access or System side access */ 319 #define BFCMAP_PHY84756_LINE_SIDE 0 320 #define BFCMAP_PHY84756_SYS_SIDE 1 321 322 323 #if 0 324 #define BFCMAP_READ_PHY54XX_MII_PHY_ID0r(_pctrl, _val) \ 325 BFCMAP_PHY54XX_REG_READ((_pctrl), 0x00, 0x0001, 0x02, (_val)) 326 #define BFCMAP_WRITE_PHY54XX_MII_PHY_ID0r(_pctrl, _val) \ 327 BFCMAP_PHY54XX_REG_WRITE((_pctrl), 0x00, 0x0001, 0x02, (_val)) 328 #define BFCMAP_MODIFY_PHY54XX_MII_PHY_ID0r(_pctrl, _val, _mask) \ 329 BFCMAP_PHY54XX_REG_MODIFY((_pctrl), 0x00, 0x0001, 0x02, \ 330 (_val), (_mask)) 331 #endif 332 333 #undef READ_PHY_REG 334 #define READ_PHY_REG(_unit, _pc, _addr, _value) \ 335 ((_pc->read)((_pc->unit), (_pc->phy_id), (_addr), (_value))) 336 337 #undef WRITE_PHY_REG 338 339 #if defined (BCM_WARM_BOOT_SUPPORT) /* */ 340 #define WRITE_PHY_REG(_unit, _pc, _addr, _value) \ 341 ((SOC_WARM_BOOT((_pc)->unit) || SOC_IS_RELOADING((_pc)->unit)) ? \ 342 SOC_E_NONE : \ 343 ((_pc->write)((_pc->unit), (_pc->phy_id), (_addr), (_value)))) 344 #else /* BCM_WARM_BOOT_SUPPORT */ 345 #define WRITE_PHY_REG(_unit, _pc, _addr, _value) \ 346 ((_pc->write)((_pc->unit), (_pc->phy_id), (_addr), (_value))) 347 #endif /* BCM_WARM_BOOT_SUPPORT */ 348 349 #define BFCMAP_PHY84756_IO_MDIO_READ(_phy_ctrl, _addr, _val) \ 350 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 351 352 #define BFCMAP_PHY84756_IO_MDIO_WRITE(_phy_ctrl, _addr, _val) \ 353 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 354 355 /* General - PHY register access */ 356 #define BFCMAP_PHY84756_REG_RD(_pctrl, _flags, _reg_bank, _reg_addr, _val) \ 357 bfcmap_phy84756_reg_read((_pctrl), (_flags), (_reg_bank), \ 358 (_reg_addr), (_val)) 359 360 #define BFCMAP_PHY84756_REG_WR(_pctrl, _flags, _reg_bank, _reg_addr, _val) \ 361 bfcmap_phy84756_reg_write((_pctrl), (_flags), (_reg_bank), \ 362 (_reg_addr), (_val)) 363 364 #define BFCMAP_PHY84756_REG_MOD(_pctrl, _flags, _reg_bank, _reg_addr, \ 365 _val, _mask) \ 366 bfcmap_phy84756_reg_modify((_pctrl), (_flags), (_reg_bank), \ 367 (_reg_addr), (_val), (_mask)) 368 369 370 371 /* 372 * SGMII DEVICE 1 Line Side Registers 373 */ 374 375 /* 376 * PMD Standard Registers 377 */ 378 /* PMD Control Register */ 379 #define BFCMAP_RD_PHY84756_SGMII_DEV1_PMD_CTRLr(_pctrl, _val) \ 380 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0000, (_val)) 381 #define BFCMAP_WR_PHY84756_SGMII_DEV1_PMD_CTRLr(_pctrl, _val) \ 382 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0000, (_val)) 383 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_PMD_CTRLr(_pctrl, _val, _mask) \ 384 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0000, \ 385 (_val), (_mask)) 386 387 /* PMD Status Register */ 388 #define BFCMAP_RD_PHY84756_SGMII_DEV1_PMD_STATr(_pctrl, _val) \ 389 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0001, (_val)) 390 #define BFCMAP_WR_PHY84756_SGMII_DEV1_PMD_STATr(_pctrl, _val) \ 391 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0001, (_val)) 392 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_PMD_STATr(_pctrl, _val, _mask) \ 393 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0001, \ 394 (_val), (_mask)) 395 396 /* PMD ID0 Register */ 397 #define BFCMAP_RD_PHY84756_SGMII_DEV1_PMD_ID0r(_pctrl, _val) \ 398 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0002, (_val)) 399 #define BFCMAP_WR_PHY84756_SGMII_DEV1_PMD_ID0r(_pctrl, _val) \ 400 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0002, (_val)) 401 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_PMD_ID0r(_pctrl, _val, _mask) \ 402 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0002, \ 403 (_val), (_mask)) 404 405 /* PMD ID1 Register */ 406 #define BFCMAP_RD_PHY84756_SGMII_DEV1_PMD_ID1r(_pctrl, _val) \ 407 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0003, (_val)) 408 #define BFCMAP_WR_PHY84756_SGMII_DEV1_PMD_ID1r(_pctrl, _val) \ 409 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0003, (_val)) 410 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_PMD_ID1r(_pctrl, _val, _mask) \ 411 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0003, \ 412 (_val), (_mask)) 413 414 415 /* 416 * PMD User registers 417 */ 418 /* 1000X Control1 Register */ 419 #define BFCMAP_RD_PHY84756_SGMII_DEV1_BASE1000X_CTRL1r(_pctrl, _val) \ 420 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x8300, (_val)) 421 #define BFCMAP_WR_PHY84756_SGMII_DEV1_BASE1000X_CTRL1r(_pctrl, _val) \ 422 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x8300, (_val)) 423 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_BASE1000X_CTRL1r(_pctrl, _val, _mask) \ 424 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x8300, \ 425 (_val), (_mask)) 426 427 /* 1000X Control2 Register */ 428 #define BFCMAP_RD_PHY84756_SGMII_DEV1_BASE1000X_CTRL2r(_pctrl, _val) \ 429 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x8301, (_val)) 430 #define BFCMAP_WR_PHY84756_SGMII_DEV1_BASE1000X_CTRL2r(_pctrl, _val) \ 431 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x8301, (_val)) 432 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_BASE1000X_CTRL2r(_pctrl, _val, _mask) \ 433 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x8301, \ 434 (_val), (_mask)) 435 436 /* 1000X Control3 Register */ 437 #define BFCMAP_RD_PHY84756_SGMII_DEV1_BASE1000X_CTRL3r(_pctrl, _val) \ 438 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x8302, (_val)) 439 #define BFCMAP_WR_PHY84756_SGMII_DEV1_BASE1000X_CTRL3r(_pctrl, _val) \ 440 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x8302, (_val)) 441 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_BASE1000X_CTRL3r(_pctrl, _val, _mask) \ 442 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x8302, \ 443 (_val), (_mask)) 444 445 /* 1000X Control4 Register */ 446 #define BFCMAP_RD_PHY84756_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val) \ 447 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x8303, (_val)) 448 #define BFCMAP_WR_PHY84756_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val) \ 449 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x8303, (_val)) 450 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val, _mask) \ 451 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x8303, \ 452 (_val), (_mask)) 453 454 /* 1000X Status1 Register */ 455 #define BFCMAP_RD_PHY84756_SGMII_DEV1_BASE1000X_STAT1r(_pctrl, _val) \ 456 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x8304, (_val)) 457 458 /* 1000X Status2 Register */ 459 #define BFCMAP_RD_PHY84756_SGMII_DEV1_BASE1000X_STAT2r(_pctrl, _val) \ 460 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x8305, (_val)) 461 462 /* 1000X Status3 Register */ 463 #define BFCMAP_RD_PHY84756_SGMII_DEV1_BASE1000X_STAT3r(_pctrl, _val) \ 464 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x8306, (_val)) 465 466 /* 1000X Control4 Register */ 467 #define BFCMAP_RD_PHY84756_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val) \ 468 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x8303, (_val)) 469 #define BFCMAP_WR_PHY84756_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val) \ 470 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x8303, (_val)) 471 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val, _mask) \ 472 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x8303, \ 473 (_val), (_mask)) 474 475 /* Speed Link Detect Status Register */ 476 #define BFCMAP_RD_PHY84756_SGMII_DEV1_SPEED_LINK_DETECT_STATr(_pctrl, _val) \ 477 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc81f, (_val)) 478 479 /* SGMII MACSEC Control Bypass Register */ 480 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MACSEC_BYPASS_CTRLr(_pctrl, _val) \ 481 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc8f0, (_val)) 482 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MACSEC_BYPASS_CTRLr(_pctrl, _val) \ 483 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xc8f0, (_val)) 484 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MACSEC_BYPASS_CTRLr(_pctrl, _val, _mask) \ 485 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xc8f0,(_val), (_mask)) 486 487 /* System Side Select Register */ 488 #define BFCMAP_RD_PHY84756_SGMII_DEV1_SYS_PMB_SELr(_pctrl, _val) \ 489 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc8ff, (_val)) 490 #define BFCMAP_WR_PHY84756_SGMII_DEV1_SYS_PMB_SELr(_pctrl, _val) \ 491 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xc8ff, (_val)) 492 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_SYS_PMB_SELr(_pctrl, _val, _mask) \ 493 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xc8ff, \ 494 (_val), (_mask)) 495 496 497 /* MII Control Resister (Addr 0xffe0) */ 498 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MII_CTRLr(_pctrl, _val) \ 499 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xffe0, (_val)) 500 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MII_CTRLr(_pctrl, _val) \ 501 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xffe0, (_val)) 502 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MII_CTRLr(_pctrl, _val, _mask) \ 503 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xffe0, \ 504 (_val), (_mask)) 505 506 /* MII Status Resister (Addr 0xffe1) */ 507 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MII_STATr(_pctrl, _val) \ 508 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xffe1, (_val)) 509 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MII_STATr(_pctrl, _val) \ 510 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xffe1, (_val)) 511 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MII_STATr(_pctrl, _val, _mask) \ 512 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xffe1, \ 513 (_val), (_mask)) 514 515 /* MII ID0 Resister (Addr 0xffe2) */ 516 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MII_ID0r(_pctrl, _val) \ 517 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xffe2, (_val)) 518 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MII_ID0r(_pctrl, _val) \ 519 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xffe2, (_val)) 520 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MII_ID0r(_pctrl, _val, _mask) \ 521 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xffe2, \ 522 (_val), (_mask)) 523 /* MII ID1 Resister (Addr 0x0003) */ 524 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MII_ID1r(_pctrl, _val) \ 525 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xffe3, (_val)) 526 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MII_ID1r(_pctrl, _val) \ 527 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xffe3, (_val)) 528 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MII_ID1r(_pctrl, _val, _mask) \ 529 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xffe3, \ 530 (_val), (_mask)) 531 532 /* Auto Neg Adv Resister (Addr 0xffe4) */ 533 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MII_ANAr(_pctrl, _val) \ 534 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xffe4, (_val)) 535 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MII_ANAr(_pctrl, _val) \ 536 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xffe4, (_val)) 537 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MII_ANAr(_pctrl, _val, _mask) \ 538 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xffe4, \ 539 (_val), (_mask)) 540 541 /* Auto Neg Link Partner Ability Register (Addr 0xffe5) */ 542 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MII_ANPr(_pctrl, _val) \ 543 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xffe5, (_val)) 544 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MII_ANPr(_pctrl, _val) \ 545 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xffe5, (_val)) 546 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MII_ANPr(_pctrl, _val, _mask) \ 547 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xffe5, \ 548 (_val), (_mask)) 549 550 /* Auto Neg Expansion Resister (Addr 0xffe6) */ 551 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MII_AN_EXPr(_pctrl, _val) \ 552 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xffe6, (_val)) 553 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MII_AN_EXPr(_pctrl, _val) \ 554 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xffe6, (_val)) 555 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MII_AN_EXPr(_pctrl, _val, _mask) \ 556 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xffe6, \ 557 (_val), (_mask)) 558 559 /* Extended Status Resister (Addr 0xffef) */ 560 #define BFCMAP_RD_PHY84756_SGMII_DEV1_MII_ESRr(_pctrl, _val) \ 561 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xffef, (_val)) 562 #define BFCMAP_WR_PHY84756_SGMII_DEV1_MII_ESRr(_pctrl, _val) \ 563 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xffef, (_val)) 564 #define BFCMAP_MOD_PHY84756_SGMII_DEV1_MII_ESRr(_pctrl, _val, _mask) \ 565 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xffef, \ 566 (_val), (_mask)) 567 568 569 /* 570 * SGMII DEVICE 1 System Side Registers 571 */ 572 573 /* 1000X Control1 Register */ 574 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL1r(_pctrl, _val) \ 575 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x8300, (_val)) 576 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL1r(_pctrl, _val) \ 577 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x8300, (_val)) 578 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL1r(_pctrl, _val, _mask) \ 579 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x8300, \ 580 (_val), (_mask)) 581 582 /* 1000X Control2 Register */ 583 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL2r(_pctrl, _val) \ 584 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x8301, (_val)) 585 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL2r(_pctrl, _val) \ 586 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x8301, (_val)) 587 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL2r(_pctrl, _val, _mask) \ 588 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x8301, \ 589 (_val), (_mask)) 590 591 /* 1000X Control3 Register */ 592 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL3r(_pctrl, _val) \ 593 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x8302, (_val)) 594 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL3r(_pctrl, _val) \ 595 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x8302, (_val)) 596 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL3r(_pctrl, _val, _mask) \ 597 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x8302, \ 598 (_val), (_mask)) 599 600 /* 1000X Control4 Register */ 601 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val) \ 602 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x8303, (_val)) 603 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val) \ 604 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x8303, (_val)) 605 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_BASE1000X_CTRL4r(_pctrl, _val, _mask) \ 606 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x8303, \ 607 (_val), (_mask)) 608 609 /* 1000X Status1 Register */ 610 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_BASE1000X_STAT1r(_pctrl, _val) \ 611 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x8304, (_val)) 612 613 /* 1000X Status2 Register */ 614 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_BASE1000X_STAT2r(_pctrl, _val) \ 615 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x8305, (_val)) 616 617 /* 1000X Status3 Register */ 618 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_BASE1000X_STAT3r(_pctrl, _val) \ 619 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x8306, (_val)) 620 621 /* Speed Link Detect Status Register */ 622 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_SPEED_LINK_DETECT_STATr(_pctrl, _val) \ 623 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0xc81f, (_val)) 624 625 /* MII Control Resister (Addr 0xffe0) */ 626 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_MII_CTRLr(_pctrl, _val) \ 627 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0xffe0, (_val)) 628 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_MII_CTRLr(_pctrl, _val) \ 629 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0xffe0, (_val)) 630 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_MII_CTRLr(_pctrl, _val, _mask) \ 631 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0xffe0, \ 632 (_val), (_mask)) 633 634 /* MII Status Resister (Addr 0xffe1) */ 635 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_MII_STATr(_pctrl, _val) \ 636 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0xffe1, (_val)) 637 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_MII_STATr(_pctrl, _val) \ 638 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0xffe1, (_val)) 639 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_MII_STATr(_pctrl, _val, _mask) \ 640 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0xffe1, \ 641 (_val), (_mask)) 642 643 /* Auto Neg Adv Resister (Addr 0xffe4) */ 644 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_MII_ANAr(_pctrl, _val) \ 645 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0xffe4, (_val)) 646 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_MII_ANAr(_pctrl, _val) \ 647 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0xffe4, (_val)) 648 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_MII_ANAr(_pctrl, _val, _mask) \ 649 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0xffe4, \ 650 (_val), (_mask)) 651 652 /* Auto Neg Link Partner Ability Register (Addr 0xffe5) */ 653 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_MII_ANPr(_pctrl, _val) \ 654 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0xffe5, (_val)) 655 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_MII_ANPr(_pctrl, _val) \ 656 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0xffe5, (_val)) 657 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_MII_ANPr(_pctrl, _val, _mask) \ 658 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0xffe5, \ 659 (_val), (_mask)) 660 661 /* Auto Neg Expansion Resister (Addr 0xffe6) */ 662 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_MII_AN_EXPr(_pctrl, _val) \ 663 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0xffe6, (_val)) 664 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_MII_AN_EXPr(_pctrl, _val) \ 665 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0xffe6, (_val)) 666 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_MII_AN_EXPr(_pctrl, _val, _mask) \ 667 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0xffe6, \ 668 (_val), (_mask)) 669 670 /* Extended Status Resister (Addr 0xffef) */ 671 #define BFCMAP_RD_PHY84756_SYS_SGMII_DEV1_MII_ESRr(_pctrl, _val) \ 672 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0xffef, (_val)) 673 #define BFCMAP_WR_PHY84756_SYS_SGMII_DEV1_MII_ESRr(_pctrl, _val) \ 674 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0xffef, (_val)) 675 #define BFCMAP_MOD_PHY84756_SYS_SGMII_DEV1_MII_ESRr(_pctrl, _val, _mask) \ 676 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0xffef, \ 677 (_val), (_mask)) 678 679 680 681 682 /* 683 * 10G/1G : Line Side PHY registers 684 */ 685 686 /* Device 1 */ 687 /* PCS User Defined Registers */ 688 689 /* Chip Revision Resister (Addr 0xc801) */ 690 #define BFCMAP_RD_PHY84756_LN_DEV1_CHIP_REVr(_pctrl, _val) \ 691 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc801, (_val)) 692 693 /* Chip ID Resister (Addr 0xc802) */ 694 #define BFCMAP_RD_PHY84756_LN_DEV1_CHIP_IDr(_pctrl, _val) \ 695 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc802, (_val)) 696 697 /* Speed Link detect Status Resister (Addr 0xc81f) */ 698 #define BFCMAP_RD_PHY84756_LN_DEV1_SPEED_LINK_DETECT_STATr(_pctrl, _val) \ 699 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc81f, (_val)) 700 701 /* Chip Mode Resister (Addr 0xc805) */ 702 #define BFCMAP_RD_PHY84756_LN_DEV1_CHIP_MODEr(_pctrl, _val) \ 703 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc805, (_val)) 704 #define BFCMAP_WR_PHY84756_LN_DEV1_CHIP_MODEr(_pctrl, _val) \ 705 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xc805, (_val)) 706 #define BFCMAP_MOD_PHY84756_LN_DEV1_CHIP_MODEr(_pctrl, _val, _mask)\ 707 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xc805, \ 708 (_val), (_mask)) 709 710 /* MACSEC Bypass Control Resister (Addr 0xc8f0) */ 711 #define BFCMAP_RD_PHY84756_LN_DEV1_MACSEC_BYPASS_CTLRr(_pctrl, _val) \ 712 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc8f0, (_val)) 713 #define BFCMAP_WR_PHY84756_LN_DEV1_MACSEC_BYPASS_CTLRr(_pctrl, _val) \ 714 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xc8f0, (_val)) 715 #define BFCMAP_MOD_PHY84756_LN_DEV1_MACSEC_BYPASS_CTLRr(_pctrl, _val, _mask)\ 716 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xc8f0, \ 717 (_val), (_mask)) 718 719 /* XPMD system Select Resister (Addr 0xc8f1) */ 720 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_SYS_SELr(_pctrl, _val) \ 721 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xc8f1, (_val)) 722 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_SYS_SELr(_pctrl, _val) \ 723 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xc8f1, (_val)) 724 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_SYS_SELr(_pctrl, _val, _mask) \ 725 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xc8f1, \ 726 (_val), (_mask)) 727 728 729 730 /* PMD Standard Registers */ 731 732 /* PMD Control Resister (Addr 0x0000) */ 733 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_CTRLr(_pctrl, _val) \ 734 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0000, (_val)) 735 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_CTRLr(_pctrl, _val) \ 736 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0000, (_val)) 737 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_CTRLr(_pctrl, _val, _mask) \ 738 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0000, \ 739 (_val), (_mask)) 740 741 /* PMD Status Resister (Addr 0x0001) */ 742 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_STATr(_pctrl, _val) \ 743 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0001, (_val)) 744 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_STATr(_pctrl, _val) \ 745 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0001, (_val)) 746 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_STATr(_pctrl, _val, _mask) \ 747 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0001, \ 748 (_val), (_mask)) 749 750 /* PMD ID0 Resister (Addr 0x0002) */ 751 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_ID0r(_pctrl, _val) \ 752 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0002, (_val)) 753 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_ID0r(_pctrl, _val) \ 754 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0002, (_val)) 755 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_ID0r(_pctrl, _val, _mask) \ 756 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0002, \ 757 (_val), (_mask)) 758 /* PMD ID1 Resister (Addr 0x0003) */ 759 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_ID1r(_pctrl, _val) \ 760 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0003, (_val)) 761 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_ID1r(_pctrl, _val) \ 762 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0003, (_val)) 763 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_ID1r(_pctrl, _val, _mask) \ 764 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0003, \ 765 (_val), (_mask)) 766 767 /* PMD Speed Ability Resister (Addr 0x0004) */ 768 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val) \ 769 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0004, (_val)) 770 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val) \ 771 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0004, (_val)) 772 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val, _mask) \ 773 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0004, \ 774 (_val), (_mask)) 775 776 /* PMD Devices in Package1 Resister (Addr 0x0005) */ 777 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val) \ 778 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0005, (_val)) 779 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val) \ 780 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0005, (_val)) 781 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 782 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0005, \ 783 (_val), (_mask)) 784 785 /* PMD Devices in Package2 Resister (Addr 0x0006) */ 786 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val) \ 787 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0006, (_val)) 788 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val) \ 789 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0006, (_val)) 790 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 791 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0006, \ 792 (_val), (_mask)) 793 794 /* PMD Control2 Resister (Addr 0x0007) */ 795 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_CTRL2r(_pctrl, _val) \ 796 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0007, (_val)) 797 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_CTRL2r(_pctrl, _val) \ 798 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0007, (_val)) 799 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_CTRL2r(_pctrl, _val, _mask) \ 800 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0007, \ 801 (_val), (_mask)) 802 803 /* PMD Status2 Resister (Addr 0x0008) */ 804 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_STAT2r(_pctrl, _val) \ 805 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0008, (_val)) 806 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_STAT2r(_pctrl, _val) \ 807 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0008, (_val)) 808 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_STAT2r(_pctrl, _val, _mask) \ 809 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0008, \ 810 (_val), (_mask)) 811 812 /* PMD Transmit Disable Resister (Addr 0x0009) */ 813 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val) \ 814 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x0009, (_val)) 815 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val) \ 816 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x0009, (_val)) 817 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val, _mask) \ 818 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x0009, \ 819 (_val), (_mask)) 820 821 /* PMD Receive Signal Detect Resister (Addr 0x000a) */ 822 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_RX_SDr(_pctrl, _val) \ 823 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x000a, (_val)) 824 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_RX_SDr(_pctrl, _val) \ 825 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x000a, (_val)) 826 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_RX_SDr(_pctrl, _val, _mask) \ 827 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x000a, \ 828 (_val), (_mask)) 829 830 /* PMD Extended Ability Resister (Addr 0x000b) */ 831 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_EXT_ABILITYr(_pctrl, _val) \ 832 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x000b, (_val)) 833 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_EXT_ABILITYr(_pctrl, _val) \ 834 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x000b, (_val)) 835 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_EXT_ABILITYr(_pctrl, _val, _mask) \ 836 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x000b, \ 837 (_val), (_mask)) 838 839 /* PMD OUI ID0 Resister (Addr 0x000e) */ 840 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_OUI_ID0r(_pctrl, _val) \ 841 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x000e, (_val)) 842 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_OUI_ID0r(_pctrl, _val) \ 843 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x000e, (_val)) 844 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_OUI_ID0r(_pctrl, _val, _mask) \ 845 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x000e, \ 846 (_val), (_mask)) 847 /* PMD OUI ID1 Resister (Addr 0x000e) */ 848 #define BFCMAP_RD_PHY84756_LN_DEV1_PMD_OUI_ID1r(_pctrl, _val) \ 849 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x000f, (_val)) 850 #define BFCMAP_WR_PHY84756_LN_DEV1_PMD_OUI_ID1r(_pctrl, _val) \ 851 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x000f, (_val)) 852 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMD_OUI_ID1r(_pctrl, _val, _mask) \ 853 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x000f, \ 854 (_val), (_mask)) 855 856 857 858 /* 859 * Device 3 registers 860 */ 861 /* PCS Registers */ 862 863 /* PCS Control Resister (Addr 0x0000) */ 864 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_CTRLr(_pctrl, _val) \ 865 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0000, (_val)) 866 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_CTRLr(_pctrl, _val) \ 867 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0000, (_val)) 868 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_CTRLr(_pctrl, _val, _mask) \ 869 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0000, \ 870 (_val), (_mask)) 871 872 /* PCS Status Resister (Addr 0x0001) */ 873 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_STATr(_pctrl, _val) \ 874 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0001, (_val)) 875 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_STATr(_pctrl, _val) \ 876 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0001, (_val)) 877 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_STATr(_pctrl, _val, _mask) \ 878 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0001, \ 879 (_val), (_mask)) 880 881 /* PCS ID0 Resister (Addr 0x0002) */ 882 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_ID0r(_pctrl, _val) \ 883 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0002, (_val)) 884 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_ID0r(_pctrl, _val) \ 885 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0002, (_val)) 886 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_ID0r(_pctrl, _val, _mask) \ 887 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0002, \ 888 (_val), (_mask)) 889 /* PCS ID1 Resister (Addr 0x0003) */ 890 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_ID1r(_pctrl, _val) \ 891 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0003, (_val)) 892 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_ID1r(_pctrl, _val) \ 893 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0003, (_val)) 894 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_ID1r(_pctrl, _val, _mask) \ 895 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0003, \ 896 (_val), (_mask)) 897 898 /* PCS Speed Ability Resister (Addr 0x0004) */ 899 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val) \ 900 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0004, (_val)) 901 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val) \ 902 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0004, (_val)) 903 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val, _mask) \ 904 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0004, \ 905 (_val), (_mask)) 906 907 /* PCS Devices in Package1 Resister (Addr 0x0005) */ 908 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val) \ 909 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0005, (_val)) 910 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val) \ 911 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0005, (_val)) 912 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 913 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0005, \ 914 (_val), (_mask)) 915 916 /* PCS Devices in Package2 Resister (Addr 0x0006) */ 917 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val) \ 918 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0006, (_val)) 919 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val) \ 920 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0006, (_val)) 921 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 922 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0006, \ 923 (_val), (_mask)) 924 925 /* PCS Control2 Resister (Addr 0x0007) */ 926 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_CTRL2r(_pctrl, _val) \ 927 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0007, (_val)) 928 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_CTRL2r(_pctrl, _val) \ 929 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0007, (_val)) 930 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_CTRL2r(_pctrl, _val, _mask) \ 931 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0007, \ 932 (_val), (_mask)) 933 934 /* PCS Status2 Resister (Addr 0x0008) */ 935 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_STAT2r(_pctrl, _val) \ 936 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0008, (_val)) 937 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_STAT2r(_pctrl, _val) \ 938 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0008, (_val)) 939 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_STAT2r(_pctrl, _val, _mask) \ 940 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0008, \ 941 (_val), (_mask)) 942 943 /* PCS TenGBASE-X Status Register Resister (Addr 0x0018) */ 944 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val) \ 945 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0018, (_val)) 946 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val) \ 947 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0018, (_val)) 948 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val, _mask) \ 949 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0018, \ 950 (_val), (_mask)) 951 952 /* PCS TenGBASE-R Status Register Resister (Addr 0x0020) */ 953 #define BFCMAP_RD_PHY84756_LN_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val) \ 954 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, 0x0020, (_val)) 955 #define BFCMAP_WR_PHY84756_LN_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val) \ 956 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, 0x0020, (_val)) 957 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val, _mask) \ 958 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, 0x0020, \ 959 (_val), (_mask)) 960 961 962 /* 963 * Device 7 Registers 964 */ 965 966 /* AN User Defined registers */ 967 968 /* 1000X Control1 Register */ 969 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 970 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x8300, (_val)) 971 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 972 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x8300, (_val)) 973 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val, _mask) \ 974 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x8300, \ 975 (_val), (_mask)) 976 977 /* 1000X Control2 Register */ 978 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val) \ 979 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x8301, (_val)) 980 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val) \ 981 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x8301, (_val)) 982 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val, _mask) \ 983 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x8301, \ 984 (_val), (_mask)) 985 986 /* 1000X Control3 Register */ 987 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val) \ 988 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x8302, (_val)) 989 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val) \ 990 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x8302, (_val)) 991 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val, _mask) \ 992 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x8302, \ 993 (_val), (_mask)) 994 995 /* 1000X Control4 Register */ 996 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val) \ 997 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x8303, (_val)) 998 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val) \ 999 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x8303, (_val)) 1000 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val, _mask) \ 1001 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x8303, \ 1002 (_val), (_mask)) 1003 1004 /* MISC2 Register */ 1005 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_MSIC2r(_pctrl, _val) \ 1006 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x8309, (_val)) 1007 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_MSIC2r(_pctrl, _val) \ 1008 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x8309, (_val)) 1009 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_MSIC2r(_pctrl, _val, _mask) \ 1010 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x8309, \ 1011 (_val), (_mask)) 1012 1013 /* 1000X Status1 Register */ 1014 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_BASE1000X_STAT1r(_pctrl, _val) \ 1015 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x8304, (_val)) 1016 1017 /* 1000X Status2 Register */ 1018 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_BASE1000X_STAT2r(_pctrl, _val) \ 1019 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x8305, (_val)) 1020 1021 1022 /* MII Control Register */ 1023 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_MII_CTRLr(_pctrl, _val) \ 1024 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0xffe0, (_val)) 1025 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_MII_CTRLr(_pctrl, _val) \ 1026 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0xffe0, (_val)) 1027 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_MII_CTRLr(_pctrl, _val, _mask) \ 1028 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe0, \ 1029 (_val), (_mask)) 1030 1031 /* MII Status Register */ 1032 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_MII_STATr(_pctrl, _val) \ 1033 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0xffe1, (_val)) 1034 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_MII_STATr(_pctrl, _val) \ 1035 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0xffe1, (_val)) 1036 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_MII_STATr(_pctrl, _val, _mask) \ 1037 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe1, \ 1038 (_val), (_mask)) 1039 1040 /* AutoNeg Adv Register */ 1041 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_ANAr(_pctrl, _val) \ 1042 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0xffe4, (_val)) 1043 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_ANAr(_pctrl, _val) \ 1044 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0xffe4, (_val)) 1045 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_ANAr(_pctrl, _val, _mask) \ 1046 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe4, \ 1047 (_val), (_mask)) 1048 /* Auto Neg Link Partner Register */ 1049 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_ANPr(_pctrl, _val) \ 1050 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0xffe5, (_val)) 1051 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_ANPr(_pctrl, _val) \ 1052 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0xffe5, (_val)) 1053 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_ANPr(_pctrl, _val, _mask) \ 1054 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe5, \ 1055 (_val), (_mask)) 1056 1057 /* Auto Neg Expansion Register */ 1058 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_EXRr(_pctrl, _val) \ 1059 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0xffe6, (_val)) 1060 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_EXRr(_pctrl, _val) \ 1061 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0xffe6, (_val)) 1062 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_EXRr(_pctrl, _val, _mask) \ 1063 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe6, \ 1064 (_val), (_mask)) 1065 1066 /* Auto Neg Next Page Register */ 1067 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_NEXT_PAGEr(_pctrl, _val) \ 1068 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0xffe7, (_val)) 1069 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_NEXT_PAGEr(_pctrl, _val) \ 1070 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0xffe7, (_val)) 1071 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_NEXT_PAGEr(_pctrl, _val, _mask) \ 1072 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe7, \ 1073 (_val), (_mask)) 1074 1075 /* Auto Neg Link Partner Ability 2 Register */ 1076 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_ANP2r(_pctrl, _val) \ 1077 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0xffe8, (_val)) 1078 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_ANP2r(_pctrl, _val) \ 1079 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0xffe8, (_val)) 1080 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_ANP2r(_pctrl, _val, _mask) \ 1081 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe8, \ 1082 (_val), (_mask)) 1083 1084 /* Extended Status 2 Register */ 1085 #define BFCMAP_RD_PHY84756_LN_DEV7_ESPr(_pctrl, _val) \ 1086 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0xffef, (_val)) 1087 #define BFCMAP_WR_PHY84756_LN_DEV7_ESPr(_pctrl, _val) \ 1088 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0xffef, (_val)) 1089 #define BFCMAP_MOD_PHY84756_LN_DEV7_ESPr(_pctrl, _val, _mask) \ 1090 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0xffef, \ 1091 (_val), (_mask)) 1092 1093 1094 /* AN Standard registers */ 1095 1096 /* AN Control Resister (Addr 0x0000) */ 1097 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_CTRLr(_pctrl, _val) \ 1098 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0000, (_val)) 1099 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_CTRLr(_pctrl, _val) \ 1100 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0000, (_val)) 1101 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_CTRLr(_pctrl, _val, _mask) \ 1102 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0000, \ 1103 (_val), (_mask)) 1104 1105 /* AN Status Resister (Addr 0x0001) */ 1106 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_STATr(_pctrl, _val) \ 1107 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0001, (_val)) 1108 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_STATr(_pctrl, _val) \ 1109 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0001, (_val)) 1110 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_STATr(_pctrl, _val, _mask) \ 1111 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0001, \ 1112 (_val), (_mask)) 1113 1114 /* AN ID0 Resister (Addr 0x0002) */ 1115 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_ID0r(_pctrl, _val) \ 1116 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0002, (_val)) 1117 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_ID0r(_pctrl, _val) \ 1118 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0002, (_val)) 1119 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_ID0r(_pctrl, _val, _mask) \ 1120 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0002, \ 1121 (_val), (_mask)) 1122 /* AN ID1 Resister (Addr 0x0003) */ 1123 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_ID1r(_pctrl, _val) \ 1124 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0003, (_val)) 1125 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_ID1r(_pctrl, _val) \ 1126 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0003, (_val)) 1127 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_ID1r(_pctrl, _val, _mask) \ 1128 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0003, \ 1129 (_val), (_mask)) 1130 1131 /* AN Speed Ability Resister (Addr 0x0004) */ 1132 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_SPEED_ABILITYr(_pctrl, _val) \ 1133 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0004, (_val)) 1134 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_SPEED_ABILITYr(_pctrl, _val) \ 1135 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0004, (_val)) 1136 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_SPEED_ABILITYr(_pctrl, _val, _mask) \ 1137 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0004, \ 1138 (_val), (_mask)) 1139 1140 /* AN Devices in Package1 Resister (Addr 0x0005) */ 1141 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val) \ 1142 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0005, (_val)) 1143 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val) \ 1144 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0005, (_val)) 1145 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 1146 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0005, \ 1147 (_val), (_mask)) 1148 1149 /* AN Devices in Package2 Resister (Addr 0x0006) */ 1150 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val) \ 1151 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0006, (_val)) 1152 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val) \ 1153 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0006, (_val)) 1154 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 1155 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0006, \ 1156 (_val), (_mask)) 1157 1158 /* AN Advertisement 1 Resister (Addr 0x0010) */ 1159 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_ADV1r(_pctrl, _val) \ 1160 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0010, (_val)) 1161 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_ADV1r(_pctrl, _val) \ 1162 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0010, (_val)) 1163 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_ADV1r(_pctrl, _val, _mask) \ 1164 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0010, \ 1165 (_val), (_mask)) 1166 1167 /* AN Advertisement 2 Resister (Addr 0x0011) */ 1168 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_ADV2r(_pctrl, _val) \ 1169 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0011, (_val)) 1170 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_ADV2r(_pctrl, _val) \ 1171 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0011, (_val)) 1172 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_ADV2r(_pctrl, _val, _mask) \ 1173 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0011, \ 1174 (_val), (_mask)) 1175 1176 /* AN Advertisement 3 Resister (Addr 0x0012) */ 1177 #define BFCMAP_RD_PHY84756_LN_DEV7_AN_ADV3r(_pctrl, _val) \ 1178 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, 0x0012, (_val)) 1179 #define BFCMAP_WR_PHY84756_LN_DEV7_AN_ADV3r(_pctrl, _val) \ 1180 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, 0x0012, (_val)) 1181 #define BFCMAP_MOD_PHY84756_LN_DEV7_AN_ADV3r(_pctrl, _val, _mask) \ 1182 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, 0x0012, \ 1183 (_val), (_mask)) 1184 1185 #define BFCMAP_RD_PHY84756_LN_DEV1_PMDr(_pctrl, _reg, _val) \ 1186 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, (_reg), (_val)) 1187 #define BFCMAP_WR_PHY84756_LN_DEV1_PMDr(_pctrl, _reg, _val) \ 1188 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, (_reg), (_val)) 1189 #define BFCMAP_MOD_PHY84756_LN_DEV1_PMDr(_pctrl, _reg, _val, _mask) \ 1190 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, (_reg), \ 1191 (_val), (_mask)) 1192 1193 #define BFCMAP_RD_PHY84756_LN_DEV3_PCSr(_pctrl, _reg, _val) \ 1194 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0003, (_reg), (_val)) 1195 #define BFCMAP_WR_PHY84756_LN_DEV3_PCSr(_pctrl, _reg, _val) \ 1196 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0003, (_reg), (_val)) 1197 #define BFCMAP_MOD_PHY84756_LN_DEV3_PCSr(_pctrl, _reg, _val, _mask) \ 1198 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0003, (_reg), \ 1199 (_val), (_mask)) 1200 1201 #define BFCMAP_RD_PHY84756_LN_DEV7_ANr(_pctrl, _reg, _val) \ 1202 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0007, (_reg), (_val)) 1203 #define BFCMAP_WR_PHY84756_LN_DEV7_ANr(_pctrl, _reg, _val) \ 1204 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0007, (_reg), (_val)) 1205 #define BFCMAP_MOD_PHY84756_LN_DEV7_ANr(_pctrl, _reg, _val, _mask) \ 1206 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0007, (_reg), \ 1207 1208 /* 1209 * 10G/1G : System Side PHY registers 1210 */ 1211 1212 /* Device 1 */ 1213 /* PMD Control Resister (Addr 0x0000) */ 1214 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_CTRLr(_pctrl, _val) \ 1215 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0000, (_val)) 1216 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_CTRLr(_pctrl, _val) \ 1217 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0000, (_val)) 1218 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_CTRLr(_pctrl, _val, _mask) \ 1219 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0000, \ 1220 (_val), (_mask)) 1221 1222 /* PMD Status Resister (Addr 0x0001) */ 1223 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_STATr(_pctrl, _val) \ 1224 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0001, (_val)) 1225 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_STATr(_pctrl, _val) \ 1226 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0001, (_val)) 1227 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_STATr(_pctrl, _val, _mask) \ 1228 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0001, \ 1229 (_val), (_mask)) 1230 1231 /* PMD ID0 Resister (Addr 0x0002) */ 1232 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_ID0r(_pctrl, _val) \ 1233 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0002, (_val)) 1234 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_ID0r(_pctrl, _val) \ 1235 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0002, (_val)) 1236 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_ID0r(_pctrl, _val, _mask) \ 1237 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0002, \ 1238 (_val), (_mask)) 1239 /* PMD ID1 Resister (Addr 0x0003) */ 1240 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_ID1r(_pctrl, _val) \ 1241 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0003, (_val)) 1242 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_ID1r(_pctrl, _val) \ 1243 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0003, (_val)) 1244 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_ID1r(_pctrl, _val, _mask) \ 1245 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0003, \ 1246 (_val), (_mask)) 1247 1248 /* PMD Speed Ability Resister (Addr 0x0004) */ 1249 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val) \ 1250 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0004, (_val)) 1251 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val) \ 1252 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0004, (_val)) 1253 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val, _mask) \ 1254 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0004, \ 1255 (_val), (_mask)) 1256 1257 /* PMD Devices in Package1 Resister (Addr 0x0005) */ 1258 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val) \ 1259 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0005, (_val)) 1260 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val) \ 1261 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0005, (_val)) 1262 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 1263 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0005, \ 1264 (_val), (_mask)) 1265 1266 /* PMD Devices in Package2 Resister (Addr 0x0006) */ 1267 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val) \ 1268 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0006, (_val)) 1269 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val) \ 1270 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0006, (_val)) 1271 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 1272 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0006, \ 1273 (_val), (_mask)) 1274 1275 /* PMD Control 2 Resister (Addr 0x0007) */ 1276 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_CTRL2r(_pctrl, _val) \ 1277 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0007, (_val)) 1278 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_CTRL2r(_pctrl, _val) \ 1279 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0007, (_val)) 1280 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_CTRL2r(_pctrl, _val, _mask) \ 1281 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0007, \ 1282 (_val), (_mask)) 1283 /* PMD Status 2 Resister (Addr 0x0007) */ 1284 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_STAT2r(_pctrl, _val) \ 1285 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0008, (_val)) 1286 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_STAT2r(_pctrl, _val) \ 1287 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0008, (_val)) 1288 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_STAT2r(_pctrl, _val, _mask) \ 1289 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0008, \ 1290 (_val), (_mask)) 1291 1292 /* PMD Transmit Disable Resister (Addr 0x0009) */ 1293 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val) \ 1294 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x0009, (_val)) 1295 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val) \ 1296 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x0009, (_val)) 1297 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val, _mask) \ 1298 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x0009, \ 1299 (_val), (_mask)) 1300 1301 /* PMD Receive Signal Detect Resister (Addr 0x000a) */ 1302 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_RX_SDr(_pctrl, _val) \ 1303 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x000a, (_val)) 1304 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_RX_SDr(_pctrl, _val) \ 1305 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x000a, (_val)) 1306 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_RX_SDr(_pctrl, _val, _mask) \ 1307 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x000a, \ 1308 (_val), (_mask)) 1309 1310 /* PMD Extended Ability Resister (Addr 0x000b) */ 1311 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_EXT_ABILITYr(_pctrl, _val) \ 1312 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x000b, (_val)) 1313 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_EXT_ABILITYr(_pctrl, _val) \ 1314 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x000b, (_val)) 1315 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_EXT_ABILITYr(_pctrl, _val, _mask) \ 1316 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x000b, \ 1317 (_val), (_mask)) 1318 1319 /* PMD OUI ID0 Resister (Addr 0x000e) */ 1320 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_OUI_ID0r(_pctrl, _val) \ 1321 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x000e, (_val)) 1322 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_OUI_ID0r(_pctrl, _val) \ 1323 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x000e, (_val)) 1324 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_OUI_ID0r(_pctrl, _val, _mask) \ 1325 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x000e, \ 1326 (_val), (_mask)) 1327 /* PMD OUI ID1 Resister (Addr 0x000e) */ 1328 #define BFCMAP_RD_PHY84756_SYS_DEV1_PMD_OUI_ID1r(_pctrl, _val) \ 1329 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0001, 0x000f, (_val)) 1330 #define BFCMAP_WR_PHY84756_SYS_DEV1_PMD_OUI_ID1r(_pctrl, _val) \ 1331 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0001, 0x000f, (_val)) 1332 #define BFCMAP_MOD_PHY84756_SYS_DEV1_PMD_OUI_ID1r(_pctrl, _val, _mask) \ 1333 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0001, 0x000f, \ 1334 (_val), (_mask)) 1335 1336 1337 /* 1338 * Device 3 registers 1339 */ 1340 /* XFI PCS Registers */ 1341 1342 /* PCS Control Resister (Addr 0x0000) */ 1343 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_CTRLr(_pctrl, _val) \ 1344 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0000, (_val)) 1345 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_CTRLr(_pctrl, _val) \ 1346 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0000, (_val)) 1347 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_CTRLr(_pctrl, _val, _mask) \ 1348 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0000, \ 1349 (_val), (_mask)) 1350 1351 /* PCS Status Resister (Addr 0x0001) */ 1352 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_STATr(_pctrl, _val) \ 1353 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0001, (_val)) 1354 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_STATr(_pctrl, _val) \ 1355 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0001, (_val)) 1356 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_STATr(_pctrl, _val, _mask) \ 1357 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0001, \ 1358 (_val), (_mask)) 1359 1360 /* PCS ID0 Resister (Addr 0x0002) */ 1361 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_ID0r(_pctrl, _val) \ 1362 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0002, (_val)) 1363 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_ID0r(_pctrl, _val) \ 1364 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0002, (_val)) 1365 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_ID0r(_pctrl, _val, _mask) \ 1366 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0002, \ 1367 (_val), (_mask)) 1368 /* PCS ID1 Resister (Addr 0x0003) */ 1369 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_ID1r(_pctrl, _val) \ 1370 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0003, (_val)) 1371 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_ID1r(_pctrl, _val) \ 1372 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0003, (_val)) 1373 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_ID1r(_pctrl, _val, _mask) \ 1374 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0003, \ 1375 (_val), (_mask)) 1376 1377 /* PCS Speed Ability Resister (Addr 0x0004) */ 1378 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val) \ 1379 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0004, (_val)) 1380 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val) \ 1381 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0004, (_val)) 1382 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val, _mask) \ 1383 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0004, \ 1384 (_val), (_mask)) 1385 1386 /* PCS Devices in Package1 Resister (Addr 0x0005) */ 1387 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val) \ 1388 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0005, (_val)) 1389 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val) \ 1390 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0005, (_val)) 1391 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 1392 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0005, \ 1393 (_val), (_mask)) 1394 1395 /* PCS Devices in Package2 Resister (Addr 0x0006) */ 1396 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val) \ 1397 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0006, (_val)) 1398 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val) \ 1399 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0006, (_val)) 1400 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 1401 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0006, \ 1402 (_val), (_mask)) 1403 1404 /* PCS Control2 Resister (Addr 0x0007) */ 1405 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_CTRL2r(_pctrl, _val) \ 1406 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0007, (_val)) 1407 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_CTRL2r(_pctrl, _val) \ 1408 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0007, (_val)) 1409 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_CTRL2r(_pctrl, _val, _mask) \ 1410 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0007, \ 1411 (_val), (_mask)) 1412 1413 /* PCS Status2 Resister (Addr 0x0008) */ 1414 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_STAT2r(_pctrl, _val) \ 1415 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0008, (_val)) 1416 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_STAT2r(_pctrl, _val) \ 1417 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0008, (_val)) 1418 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_STAT2r(_pctrl, _val, _mask) \ 1419 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0008, \ 1420 (_val), (_mask)) 1421 1422 /* PCS TenGBASE-X Status Register Resister (Addr 0x0018) */ 1423 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val) \ 1424 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0018, (_val)) 1425 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val) \ 1426 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0018, (_val)) 1427 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val, _mask) \ 1428 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0018, \ 1429 (_val), (_mask)) 1430 1431 /* PCS TenGBASE-R Status Register Resister (Addr 0x0020) */ 1432 #define BFCMAP_RD_PHY84756_XFI_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val) \ 1433 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0003, 0x0020, (_val)) 1434 #define BFCMAP_WR_PHY84756_XFI_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val) \ 1435 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0003, 0x0020, (_val)) 1436 #define BFCMAP_MOD_PHY84756_XFI_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val, _mask) \ 1437 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0003, 0x0020, \ 1438 (_val), (_mask)) 1439 1440 1441 1442 /* 1443 * Device 7 Registers 1444 */ 1445 1446 /* AN User Defined registers */ 1447 1448 /* 1000X Control1 Register */ 1449 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 1450 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x8300, (_val)) 1451 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 1452 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x8300, (_val)) 1453 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val, _mask) \ 1454 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x8300, \ 1455 (_val), (_mask)) 1456 1457 /* 1000X Control2 Register */ 1458 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val) \ 1459 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x8301, (_val)) 1460 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val) \ 1461 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x8301, (_val)) 1462 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val, _mask) \ 1463 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x8301, \ 1464 (_val), (_mask)) 1465 1466 /* 1000X Control3 Register */ 1467 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val) \ 1468 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x8302, (_val)) 1469 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val) \ 1470 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x8302, (_val)) 1471 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val, _mask) \ 1472 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x8302, \ 1473 (_val), (_mask)) 1474 1475 /* 1000X Control4 Register */ 1476 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val) \ 1477 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x8303, (_val)) 1478 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val) \ 1479 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x8303, (_val)) 1480 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val, _mask) \ 1481 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x8303, \ 1482 (_val), (_mask)) 1483 1484 /* PRBS Generator Register */ 1485 #define BFCMAP_RD_PHY84756_XFI_DEV7_PRBS_GEN(_pctrl, _val) \ 1486 BFCMAP_PHY84756_REG_RD((_pctrl), 0x0, 0x0007, 0x8019, (_val)) 1487 #define BFCMAP_WR_PHY84756_XFI_DEV7_PRBS_GEN(_pctrl, _val) \ 1488 BFCMAP_PHY84756_REG_WR((_pctrl), 0x0, 0x0007, 0x8019, (_val)) 1489 #define BFCMAP_MOD_PHY84756_XFI_DEV7_PRBS_GEN(_pctrl, _val, _mask) \ 1490 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x0, 0x0007, 0x8019, \ 1491 (_val), (_mask)) 1492 1493 /* Lane Control 0 Register */ 1494 #define BFCMAP_RD_PHY84756_XFI_DEV7_LANE_CTRL0(_pctrl, _val) \ 1495 BFCMAP_PHY84756_REG_RD((_pctrl), 0x0, 0x0007, 0x8015, (_val)) 1496 #define BFCMAP_WR_PHY84756_XFI_DEV7_LANE_CTRL0(_pctrl, _val) \ 1497 BFCMAP_PHY84756_REG_WR((_pctrl), 0x0, 0x0007, 0x8015, (_val)) 1498 #define BFCMAP_MOD_PHY84756_XFI_DEV7_LANE_CTRL0(_pctrl, _val, _mask) \ 1499 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x0, 0x0007, 0x8015, \ 1500 (_val), (_mask)) 1501 1502 /* Lane Control 2 Register */ 1503 #define BFCMAP_RD_PHY84756_XFI_DEV7_LANE_CTRL2(_pctrl, _val) \ 1504 BFCMAP_PHY84756_REG_RD((_pctrl), 0x0, 0x0007, 0x8017, (_val)) 1505 #define BFCMAP_WR_PHY84756_XFI_DEV7_LANE_CTRL2(_pctrl, _val) \ 1506 BFCMAP_PHY84756_REG_WR((_pctrl), 0x0, 0x0007, 0x8017, (_val)) 1507 #define BFCMAP_MOD_PHY84756_XFI_DEV7_LANE_CTRL2(_pctrl, _val, _mask) \ 1508 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x0, 0x0007, 0x8017, \ 1509 (_val), (_mask)) 1510 1511 /* XGXS Status Register */ 1512 #define BFCMAP_RD_PHY84756_XFI_DEV7_XGXS_CTRL(_pctrl, _val) \ 1513 BFCMAP_PHY84756_REG_RD((_pctrl), 0x0, 0x0007, 0x8000, (_val)) 1514 #define BFCMAP_WR_PHY84756_XFI_DEV7_XGXS_CTRL(_pctrl, _val) \ 1515 BFCMAP_PHY84756_REG_WR((_pctrl), 0x0, 0x0007, 0x8000, (_val)) 1516 #define BFCMAP_MOD_PHY84756_XFI_DEV7_XGXS_CTRL(_pctrl, _val, _mask) \ 1517 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x0, 0x0007, 0x8000, \ 1518 (_val), (_mask)) 1519 1520 /* PRBS Checker Register */ 1521 #define BFCMAP_RD_PHY84756_XFI_DEV7_PRBS_CHK(_pctrl, _val) \ 1522 BFCMAP_PHY84756_REG_RD((_pctrl), 0x0, 0x0007, 0x80B0, (_val)) 1523 #define BFCMAP_WR_PHY84756_XFI_DEV7_PRBS_CHK(_pctrl, _val) \ 1524 BFCMAP_PHY84756_REG_WR((_pctrl), 0x0, 0x0007, 0x80B0, (_val)) 1525 #define BFCMAP_MOD_PHY84756_XFI_DEV7_PRBS_CHK(_pctrl, _val, _mask) \ 1526 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x0, 0x0007, 0x80B0, \ 1527 (_val), (_mask)) 1528 /* PRBS Checker Lock Err Register */ 1529 #define BFCMAP_RD_PHY84756_XFI_DEV7_PRBS_LOCK_ERR(_pctrl, _val) \ 1530 BFCMAP_PHY84756_REG_RD((_pctrl), 0x0, 0x0007, 0x80B1, (_val)) 1531 #define BFCMAP_WR_PHY84756_XFI_DEV7_PRBS_LOCK_ERR(_pctrl, _val) \ 1532 BFCMAP_PHY84756_REG_WR((_pctrl), 0x0, 0x0007, 0x80B1, (_val)) 1533 #define BFCMAP_MOD_PHY84756_XFI_DEV7_PRBS_LOCK_ERR(_pctrl, _val, _mask) \ 1534 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x0, 0x0007, 0x80B1, \ 1535 (_val), (_mask)) 1536 1537 /* MISC2 Register */ 1538 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_MISC2r(_pctrl, _val) \ 1539 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x8309, (_val)) 1540 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_MISC2r(_pctrl, _val) \ 1541 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x8309, (_val)) 1542 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_MISC2r(_pctrl, _val, _mask) \ 1543 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x8309, \ 1544 (_val), (_mask)) 1545 1546 /* 1000X Status1 Register */ 1547 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_BASE1000X_STAT1r(_pctrl, _val) \ 1548 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x8304, (_val)) 1549 1550 /* 1000X Status2 Register */ 1551 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_BASE1000X_STAT2r(_pctrl, _val) \ 1552 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x8305, (_val)) 1553 1554 /* MII Control Register */ 1555 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_MII_CTRLr(_pctrl, _val) \ 1556 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0xffe0, (_val)) 1557 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_MII_CTRLr(_pctrl, _val) \ 1558 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0xffe0, (_val)) 1559 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_MII_CTRLr(_pctrl, _val, _mask) \ 1560 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe0, \ 1561 (_val), (_mask)) 1562 1563 /* MII Status Register */ 1564 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_MII_STATr(_pctrl, _val) \ 1565 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0xffe1, (_val)) 1566 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_MII_STATr(_pctrl, _val) \ 1567 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0xffe1, (_val)) 1568 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_MII_STATr(_pctrl, _val, _mask) \ 1569 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe1, \ 1570 (_val), (_mask)) 1571 1572 /* AutoNeg Adv Register */ 1573 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_ANAr(_pctrl, _val) \ 1574 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0xffe4, (_val)) 1575 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_ANAr(_pctrl, _val) \ 1576 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0xffe4, (_val)) 1577 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_ANAr(_pctrl, _val, _mask) \ 1578 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe4, \ 1579 (_val), (_mask)) 1580 /* Auto Neg Link Partner Register */ 1581 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_ANPr(_pctrl, _val) \ 1582 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0xffe5, (_val)) 1583 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_ANPr(_pctrl, _val) \ 1584 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0xffe5, (_val)) 1585 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_ANPr(_pctrl, _val, _mask) \ 1586 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe5, \ 1587 (_val), (_mask)) 1588 1589 /* Auto Neg Expansion Register */ 1590 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_EXRr(_pctrl, _val) \ 1591 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0xffe6, (_val)) 1592 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_EXRr(_pctrl, _val) \ 1593 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0xffe6, (_val)) 1594 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_EXRr(_pctrl, _val, _mask) \ 1595 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe6, \ 1596 (_val), (_mask)) 1597 1598 /* Auto Neg Next Page Register */ 1599 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_NEXT_PAGEr(_pctrl, _val) \ 1600 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0xffe7, (_val)) 1601 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_NEXT_PAGEr(_pctrl, _val) \ 1602 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0xffe7, (_val)) 1603 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_NEXT_PAGEr(_pctrl, _val, _mask) \ 1604 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe7, \ 1605 (_val), (_mask)) 1606 1607 /* Auto Neg Link Partner Ability 2 Register */ 1608 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_ANP2r(_pctrl, _val) \ 1609 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0xffe8, (_val)) 1610 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_ANP2r(_pctrl, _val) \ 1611 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0xffe8, (_val)) 1612 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_ANP2r(_pctrl, _val, _mask) \ 1613 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe8, \ 1614 (_val), (_mask)) 1615 1616 /* Extended Status 2 Register */ 1617 #define BFCMAP_RD_PHY84756_XFI_DEV7_ESPr(_pctrl, _val) \ 1618 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0xffef, (_val)) 1619 #define BFCMAP_WR_PHY84756_XFI_DEV7_ESPr(_pctrl, _val) \ 1620 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0xffef, (_val)) 1621 #define BFCMAP_MOD_PHY84756_XFI_DEV7_ESPr(_pctrl, _val, _mask) \ 1622 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0xffef, \ 1623 (_val), (_mask)) 1624 1625 1626 /* AN Standard registers */ 1627 1628 /* AN Control Resister (Addr 0x0000) */ 1629 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_CTRLr(_pctrl, _val) \ 1630 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0000, (_val)) 1631 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_CTRLr(_pctrl, _val) \ 1632 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0000, (_val)) 1633 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_CTRLr(_pctrl, _val, _mask) \ 1634 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0000, \ 1635 (_val), (_mask)) 1636 1637 /* AN Status Resister (Addr 0x0001) */ 1638 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_STATr(_pctrl, _val) \ 1639 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0001, (_val)) 1640 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_STATr(_pctrl, _val) \ 1641 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0001, (_val)) 1642 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_STATr(_pctrl, _val, _mask) \ 1643 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0001, \ 1644 (_val), (_mask)) 1645 1646 /* AN ID0 Resister (Addr 0x0002) */ 1647 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_ID0r(_pctrl, _val) \ 1648 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0002, (_val)) 1649 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_ID0r(_pctrl, _val) \ 1650 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0002, (_val)) 1651 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_ID0r(_pctrl, _val, _mask) \ 1652 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0002, \ 1653 (_val), (_mask)) 1654 /* AN ID1 Resister (Addr 0x0003) */ 1655 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_ID1r(_pctrl, _val) \ 1656 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0003, (_val)) 1657 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_ID1r(_pctrl, _val) \ 1658 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0003, (_val)) 1659 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_ID1r(_pctrl, _val, _mask) \ 1660 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0003, \ 1661 (_val), (_mask)) 1662 1663 /* AN Speed Ability Resister (Addr 0x0004) */ 1664 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_SPEED_ABILITYr(_pctrl, _val) \ 1665 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0004, (_val)) 1666 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_SPEED_ABILITYr(_pctrl, _val) \ 1667 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0004, (_val)) 1668 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_SPEED_ABILITYr(_pctrl, _val, _mask) \ 1669 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0004, \ 1670 (_val), (_mask)) 1671 1672 /* AN Devices in Package1 Resister (Addr 0x0005) */ 1673 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val) \ 1674 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0005, (_val)) 1675 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val) \ 1676 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0005, (_val)) 1677 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 1678 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0005, \ 1679 (_val), (_mask)) 1680 1681 /* AN Devices in Package2 Resister (Addr 0x0006) */ 1682 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val) \ 1683 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0006, (_val)) 1684 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val) \ 1685 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0006, (_val)) 1686 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 1687 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0006, \ 1688 (_val), (_mask)) 1689 1690 /* AN Advertisement 1 Resister (Addr 0x0010) */ 1691 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_ADV1r(_pctrl, _val) \ 1692 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0010, (_val)) 1693 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_ADV1r(_pctrl, _val) \ 1694 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0010, (_val)) 1695 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_ADV1r(_pctrl, _val, _mask) \ 1696 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0010, \ 1697 (_val), (_mask)) 1698 1699 /* AN Advertisement 2 Resister (Addr 0x0011) */ 1700 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_ADV2r(_pctrl, _val) \ 1701 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0011, (_val)) 1702 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_ADV2r(_pctrl, _val) \ 1703 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0011, (_val)) 1704 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_ADV2r(_pctrl, _val, _mask) \ 1705 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0011, \ 1706 (_val), (_mask)) 1707 1708 /* AN Advertisement 3 Resister (Addr 0x0012) */ 1709 #define BFCMAP_RD_PHY84756_XFI_DEV7_AN_ADV3r(_pctrl, _val) \ 1710 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x0012, (_val)) 1711 #define BFCMAP_WR_PHY84756_XFI_DEV7_AN_ADV3r(_pctrl, _val) \ 1712 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x0012, (_val)) 1713 #define BFCMAP_MOD_PHY84756_XFI_DEV7_AN_ADV3r(_pctrl, _val, _mask) \ 1714 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x0012, \ 1715 (_val), (_mask)) 1716 1717 1718 /* 1719 * Firmware Download related registers 1720 */ 1721 1722 /* M8051 Message IN Resister (Addr 0xCA12) */ 1723 #define BFCMAP_RD_PHY84756_LN_DEV1_M8501_MSGINr(_pctrl, _val) \ 1724 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xCA12, (_val)) 1725 #define BFCMAP_WR_PHY84756_LN_DEV1_M8501_MSGINr(_pctrl, _val) \ 1726 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xCA12, (_val)) 1727 #define BFCMAP_MOD_PHY84756_LN_DEV1_M8501_MSGINr(_pctrl, _val, _mask) \ 1728 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xCA12, \ 1729 (_val), (_mask)) 1730 1731 /* M8051 Message OUT Resister (Addr 0xCA13) */ 1732 #define BFCMAP_RD_PHY84756_LN_DEV1_M8501_MSGOUTr(_pctrl, _val) \ 1733 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xCA13, (_val)) 1734 #define BFCMAP_WR_PHY84756_LN_DEV1_M8501_MSGOUTr(_pctrl, _val) \ 1735 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xCA13, (_val)) 1736 #define BFCMAP_MOD_PHY84756_LN_DEV1_M8501_MSGOUTr(_pctrl, _val, _mask) \ 1737 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xCA13, \ 1738 (_val), (_mask)) 1739 1740 /* RX Alarm Resister (Addr 0x9003) */ 1741 #define BFCMAP_RD_PHY84756_LN_DEV1_RX_ALARMr(_pctrl, _val) \ 1742 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x9003, (_val)) 1743 #define BFCMAP_WR_PHY84756_LN_DEV1_RX_ALARMr(_pctrl, _val) \ 1744 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x9003, (_val)) 1745 #define BFCMAP_MOD_PHY84756_LN_DEV1_RX_ALARMr(_pctrl, _val, _mask) \ 1746 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x9003, \ 1747 (_val), (_mask)) 1748 1749 /* SPA Control and Status Resister (Addr 0xC848) */ 1750 #define BFCMAP_RD_PHY84756_LN_DEV1_SPI_CTRL_STATr(_pctrl, _val) \ 1751 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xC848, (_val)) 1752 #define BFCMAP_WR_PHY84756_LN_DEV1_SPI_CTRL_STATr(_pctrl, _val) \ 1753 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xC848, (_val)) 1754 #define BFCMAP_MOD_PHY84756_LN_DEV1_SPI_CTRL_STATr(_pctrl, _val, _mask) \ 1755 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xC848, \ 1756 (_val), (_mask)) 1757 1758 /* SPA Control and Status Resister (Addr 0xCA1C) */ 1759 #define BFCMAP_RD_PHY84756_LN_DEV1_CHECKSUMr(_pctrl, _val) \ 1760 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xCA1C, (_val)) 1761 1762 1763 /* SPI ROM Firmware update related */ 1764 1765 /* 1766 * SPI-ROM Program related defs 1767 */ 1768 #define BFCMAP_SPI_CTRL_1_L 0xC000 1769 #define BFCMAP_SPI_CTRL_1_H 0xC002 1770 #define BFCMAP_SPI_CTRL_2_L 0xC400 1771 #define BFCMAP_SPI_CTRL_2_H 0xC402 1772 #define BFCMAP_SPI_TXFIFO 0xD000 1773 #define BFCMAP_SPI_RXFIFO 0xD400 1774 #define BFCMAP_WR_CPU_CTRL_REGS 0x11 1775 #define BFCMAP_RD_CPU_CTRL_REGS 0xEE 1776 #define BFCMAP_WR_CPU_CTRL_FIFO 0x66 1777 1778 /* 1779 * SPI Controller Commands(Messages). 1780 */ 1781 #define BFCMAP_MSGTYPE_HWR 0x40 1782 #define BFCMAP_MSGTYPE_HRD 0x80 1783 #define BFCMAP_WRSR_OPCODE 0x01 1784 #define BFCMAP_WR_OPCODE 0x02 1785 #define BFCMAP_WRDI_OPCODE 0x04 1786 #define BFCMAP_RDSR_OPCODE 0x05 1787 #define BFCMAP_WREN_OPCODE 0x06 1788 #define BFCMAP_WR_BLOCK_SIZE 0x40 1789 #define BFCMAP_TOTAL_WR_BYTE 0x4000 1790 1791 #define BFCMAP_WR_TIMEOUT 100 1792 #define BFCMAP_WR_ITERATIONS 10000 1793 1794 1795 /* Misc Control 2 Resister(SPI ROM FW Upload control) (Addr 0xCA85) */ 1796 #define BFCMAP_RD_PHY84756_LN_DEV1_MISC_CNTL2r(_pctrl, _val) \ 1797 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0xCA85, (_val)) 1798 #define BFCMAP_WR_PHY84756_LN_DEV1_MISC_CNTL2r(_pctrl, _val) \ 1799 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0xCA85, (_val)) 1800 #define BFCMAP_MOD_PHY84756_LN_DEV1_MISC_CNTL2r(_pctrl, _val, _mask) \ 1801 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0xCA85, \ 1802 (_val), (_mask)) 1803 1804 /* RX Alarm Control Resister (Addr 0x9000) */ 1805 #define BFCMAP_RD_PHY84756_LN_DEV1_RX_ALARM_CNTLr(_pctrl, _val) \ 1806 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x9000, (_val)) 1807 #define BFCMAP_WR_PHY84756_LN_DEV1_RX_ALARM_CNTLr(_pctrl, _val) \ 1808 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x9000, (_val)) 1809 #define BFCMAP_MOD_PHY84756_LN_DEV1_RX_ALARM_CNTLr(_pctrl, _val, _mask) \ 1810 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x9000, \ 1811 (_val), (_mask)) 1812 1813 /* TX Alarm Control Resister (Addr 0x9001) */ 1814 #define BFCMAP_RD_PHY84756_LN_DEV1_TX_ALARM_CNTLr(_pctrl, _val) \ 1815 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x9001, (_val)) 1816 #define BFCMAP_WR_PHY84756_LN_DEV1_TX_ALARM_CNTLr(_pctrl, _val) \ 1817 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x9001, (_val)) 1818 #define BFCMAP_MOD_PHY84756_LN_DEV1_TX_ALARM_CNTLr(_pctrl, _val, _mask) \ 1819 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x9001, \ 1820 (_val), (_mask)) 1821 1822 /* LASI Control Resister (Addr 0x9002) */ 1823 #define BFCMAP_RD_PHY84756_LN_DEV1_LASI_CNTLr(_pctrl, _val) \ 1824 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x9002, (_val)) 1825 #define BFCMAP_WR_PHY84756_LN_DEV1_LASI_CNTLr(_pctrl, _val) \ 1826 BFCMAP_PHY84756_REG_WR((_pctrl), 0x00, 0x0001, 0x9002, (_val)) 1827 #define BFCMAP_MOD_PHY84756_LN_DEV1_LASI_CNTLr(_pctrl, _val, _mask) \ 1828 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x00, 0x0001, 0x9002, \ 1829 (_val), (_mask)) 1830 1831 /* RX Alarm Status Register (Addr 0x9003) */ 1832 #define BFCMAP_RD_PHY84756_LN_DEV1_RX_ALARM_STATr(_pctrl, _val) \ 1833 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x9003, (_val)) 1834 1835 /* TX Alarm Status Register (Addr 0x9003) */ 1836 #define BFCMAP_RD_PHY84756_LN_DEV1_TX_ALARM_STATr(_pctrl, _val) \ 1837 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x9004, (_val)) 1838 1839 /* LASI Status Register (Addr 0x9003) */ 1840 #define BFCMAP_RD_PHY84756_LN_DEV1_LASI_STATr(_pctrl, _val) \ 1841 BFCMAP_PHY84756_REG_RD((_pctrl), 0x00, 0x0001, 0x9005, (_val)) 1842 1843 /* XGXS clause 45 registers */ 1844 1845 /* AN User Defined registers */ 1846 1847 /* 1000X Control1 Register */ 1848 #define BFCMAP_RD_PHY84756_XGXS_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 1849 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0007, 0x8300, (_val)) 1850 #define BFCMAP_WR_PHY84756_XGXS_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 1851 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0007, 0x8300, (_val)) 1852 #define BFCMAP_MOD_PHY84756_XGXS_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val, _mask) \ 1853 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0007, 0x8300, \ 1854 (_val), (_mask)) 1855 1856 /* XGXS control Register */ 1857 #define BFCMAP_RD_PHY84756_XGXS_CTRLr(_pctrl, _val) \ 1858 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x4, 0x8000, (_val)) 1859 #define BFCMAP_WR_PHY84756_XGXS_CTRLr(_pctrl, _val) \ 1860 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x4, 0x8000, (_val)) 1861 #define BFCMAP_MOD_PHY84756_XGXS_CTRLr(_pctrl, _val, _mask) \ 1862 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x4, 0x8000, \ 1863 (_val), (_mask)) 1864 1865 /* XGXS Lane status Register */ 1866 #define BFCMAP_RD_PHY84756_XGXS_DEV4_XS_LANE_STATr(_pctrl, _val) \ 1867 BFCMAP_PHY84756_REG_RD((_pctrl), 0x01, 0x0004, 0x18, (_val)) 1868 #define BFCMAP_WR_PHY84756_XGXS_DEV4_XS_LANE_STATr(_pctrl, _val) \ 1869 BFCMAP_PHY84756_REG_WR((_pctrl), 0x01, 0x0004, 0x18, (_val)) 1870 #define BFCMAP_MOD_PHY84756_XGXS_DEV4_XS_LANE_STATr(_pctrl, _val, _mask) \ 1871 BFCMAP_PHY84756_REG_MOD((_pctrl), 0x01, 0x0004, 0x18, \ 1872 (_val), (_mask)) 1873 1874 #endif /* _PHY84756_INT_H */