phy84756_fcmap.h (24905B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 9 #ifndef _bfcmap_phy84756_H_ 10 #define _bfcmap_phy84756_H_ 11 12 13 #define BFCMAP_PHY84756_BRCM_OUI3 0x1be9 /* Broadcom OUI */ 14 #define BFCMAP_PHY84756_BRCM_OUI1 0x1018 /* Broadcom OUI */ 15 16 /* 17 * Supported PHYs 18 */ 19 20 #if 0 21 #define BFCMAP_PHY_BCM84756_MODEL 0x3d 22 #endif 23 #define BFCMAP_PHY_BCM84756_MODEL 0x27 24 25 typedef enum bfcmap_phy84756_speed_s { 26 BFCMAP_PHY84756_SPEED_10 = 0, 27 BFCMAP_PHY84756_SPEED_100, 28 BFCMAP_PHY84756_SPEED_1000, 29 BFCMAP_PHY84756_SPEED_10000 30 }bfcmap_phy84756_speed_t; 31 32 typedef enum bfcmap_phy84756_duplex_s { 33 BFCMAP_PHY84756_HALF_DUPLEX = 0, 34 BFCMAP_PHY84756_FULL_DUPLEX 35 }bfcmap_phy84756_duplex_t; 36 37 typedef enum bfcmap_phy84756_intf_s { 38 BFCMAP_PHY84756_INTF_SGMII = 0, 39 BFCMAP_PHY84756_INTF_1000X, 40 BFCMAP_PHY84756_INTF_SFI, 41 BFCMAP_PHY84756_INTF_XFI, 42 BFCMAP_PHY84756_INTF_XAUI 43 }bfcmap_phy84756_intf_t; 44 45 /* 46 * Switch MAC speed and duplex policies 47 */ 48 typedef enum bfcmap_phy84756_mac_policy_s { 49 BFCMAP_BCM84756_SWITCH_FIXED = 0, 50 BFCMAP_BCM84756_SWITCH_FOLLOWS_LINE 51 }bfcmap_phy84756_mac_policy_t; 52 53 54 typedef enum bfcmap_phy84756_port_mdix_s { 55 BFCMAP_PHY84756_PORT_MDIX_AUTO, 56 BFCMAP_PHY84756_PORT_MDIX_FORCE_AUTO, 57 BFCMAP_PHY84756_PORT_MDIX_NORMAL, 58 BFCMAP_PHY84756_PORT_MDIX_XOVER 59 }bfcmap_phy84756_port_mdix_t; 60 61 typedef enum bfcmap_phy84756_port_mdix_status_s { 62 BFCMAP_PHY84756_PORT_MDIX_STATUS_NORMAL, 63 BFCMAP_PHY84756_PORT_MDIX_STATUS_XOVER 64 }bfcmap_phy84756_port_mdix_status_t; 65 66 67 typedef enum bfcmap_phy84756_master_s { 68 BFCMAP_PHY84756_PORT_MS_SLAVE =0, 69 BFCMAP_PHY84756_PORT_MS_MASTER, 70 BFCMAP_PHY84756_PORT_MS_AUTO, 71 BFCMAP_PHY84756_PORT_MS_NONE 72 }bfcmap_phy84756_master_t; 73 74 typedef enum bfcmap_phy84756_fcmap_dir_s { 75 BFCMAP_PHY84756_FCMAP_DIR_EGRESS = 0, 76 BFCMAP_PHY84756_FCMAP_DIR_INGRESS 77 } bfcmap_phy84756_fcmap_dir_t; 78 79 typedef enum bfcmap_phy84756_fcmap_port_mode_s { 80 BFCMAP_PHY84756_FCMAP_FCOE_TO_FC_MODE = 0, 81 BFCMAP_PHY84756_FCMAP_FCOE_TO_FCOE_MODE 82 } bfcmap_phy84756_fcmap_port_mode_t; 83 84 typedef enum bfcmap_phy84756_fcmap_port_speed_s { 85 BFCMAP_PHY84756_FCMAP_PORT_SPEED_2GBPS = 0, 86 BFCMAP_PHY84756_FCMAP_PORT_SPEED_4GBPS = 1, 87 BFCMAP_PHY84756_FCMAP_PORT_SPEED_8GBPS = 2, 88 BFCMAP_PHY84756_FCMAP_PORT_SPEED_16GBPS = 3, 89 BFCMAP_PHY84756_FCMAP_PORT_SPEED_MAX_COUNT 90 } bfcmap_phy84756_fcmap_port_speed_t; 91 92 typedef enum bfcmap_phy84756_fcmap_port_state_s { 93 BFCMAP_PHY84756_FCMAP_PORT_STATE_INIT = 0, 94 BFCMAP_PHY84756_FCMAP_PORT_STATE_RESET = 1, 95 BFCMAP_PHY84756_FCMAP_PORT_STATE_ACTIVE = 2, 96 BFCMAP_PHY84756_FCMAP_PORT_STATE_LINKDOWN = 3, 97 BFCMAP_PHY84756_FCMAP_PORT_STATE_DISABLE = 4, 98 BFCMAP_PHY84756_FCMAP_PORT_STATE_MAX_COUNT 99 } bfcmap_phy84756_fcmap_port_state_t; 100 101 typedef unsigned int bfcmap_phy84756_port_mode_t; 102 typedef unsigned int bfcmap_phy84756_port_ability_t; 103 104 /* 105 * Port modes. 106 */ 107 108 #define BFCMAP_PHY84756_PM_10MB_HD (1 << 0) 109 #define BFCMAP_PHY84756_PM_10MB_FD (1 << 1) 110 #define BFCMAP_PHY84756_PM_100MB_HD (1 << 2) 111 #define BFCMAP_PHY84756_PM_100MB_FD (1 << 3) 112 #define BFCMAP_PHY84756_PM_1000MB_HD (1 << 4) 113 #define BFCMAP_PHY84756_PM_1000MB_FD (1 << 5) 114 #define BFCMAP_PHY84756_PM_PAUSE_TX (1 << 6) 115 #define BFCMAP_PHY84756_PM_PAUSE_RX (1 << 7) 116 #define BFCMAP_PHY84756_PM_PAUSE_ASYMM (1 << 8) 117 #define BFCMAP_PHY84756_PM_TBI (1 << 9) 118 #define BFCMAP_PHY84756_PM_MII (1 << 10) 119 #define BFCMAP_PHY84756_PM_GMII (1 << 11) 120 #define BFCMAP_PHY84756_PM_SGMII (1 << 12) 121 #define BFCMAP_PHY84756_PM_LB_MAC (1 << 13) 122 #define BFCMAP_PHY84756_PM_LB_NONE (1 << 14) 123 #define BFCMAP_PHY84756_PM_LB_PHY (1 << 15) 124 #define BFCMAP_PHY84756_PM_AN (1 << 16) 125 126 #define BFCMAP_PHY84756_PM_PAUSE (BFCMAP_PHY84756_PM_PAUSE_TX | \ 127 BFCMAP_PHY84756_PM_PAUSE_RX) 128 #define BFCMAP_PHY84756_PM_10MB (BFCMAP_PHY84756_PM_10MB_HD | \ 129 BFCMAP_PHY84756_PM_10MB_FD) 130 #define BFCMAP_PHY84756_PM_100MB (BFCMAP_PHY84756_PM_100MB_HD | \ 131 BFCMAP_PHY84756_PM_100MB_FD) 132 #define BFCMAP_PHY84756_PM_1000MB (BFCMAP_PHY84756_PM_1000MB_HD | \ 133 BFCMAP_PHY84756_PM_1000MB_FD) 134 135 #define BFCMAP_PHY84756_PM_SPEED_ALL (BFCMAP_PHY84756_PM_1000MB | \ 136 BFCMAP_PHY84756_PM_100MB | \ 137 BFCMAP_PHY84756_PM_10MB) 138 139 #define BFCMAP_PHY84756_PM_FD (BFCMAP_PHY84756_PM_1000MB_FD | \ 140 BFCMAP_PHY84756_PM_100MB_FD | \ 141 BFCMAP_PHY84756_PM_10MB_FD) 142 143 #define BFCMAP_PHY84756_PM_HD (BFCMAP_PHY84756_PM_1000MB_HD | \ 144 BFCMAP_PHY84756_PM_100MB_HD | \ 145 BFCMAP_PHY84756_PM_10MB_HD) 146 147 /* 148 * Port ability 149 */ 150 #define BFCMAP_PHY84756_PA_10MB_HD (1 << 0) 151 #define BFCMAP_PHY84756_PA_10MB_FD (1 << 1) 152 #define BFCMAP_PHY84756_PA_100MB_HD (1 << 2) 153 #define BFCMAP_PHY84756_PA_100MB_FD (1 << 3) 154 #define BFCMAP_PHY84756_PA_1000MB_HD (1 << 4) 155 #define BFCMAP_PHY84756_PA_1000MB_FD (1 << 5) 156 #define BFCMAP_PHY84756_PA_10000MB_FD (1 << 6) 157 #define BFCMAP_PHY84756_PA_PAUSE_TX (1 << 7) 158 #define BFCMAP_PHY84756_PA_PAUSE_RX (1 << 8) 159 #define BFCMAP_PHY84756_PA_PAUSE_ASYMM (1 << 9) 160 #define BFCMAP_PHY84756_PA_SGMII (1 << 10) 161 #define BFCMAP_PHY84756_PA_XSGMII (1 << 11) 162 #define BFCMAP_PHY84756_PA_LB_MAC (1 << 12) 163 #define BFCMAP_PHY84756_PA_LB_NONE (1 << 13) 164 #define BFCMAP_PHY84756_PA_LB_PHY (1 << 14) 165 #define BFCMAP_PHY84756_PA_AN (1 << 15) 166 167 #define BFCMAP_PHY84756_PA_PAUSE (BFCMAP_PHY84756_PA_PAUSE_TX | \ 168 BFCMAP_PHY84756_PA_PAUSE_RX) 169 #define BFCMAP_PHY84756_PA_10MB (BFCMAP_PHY84756_PA_10MB_HD | \ 170 BFCMAP_PHY84756_PA_10MB_FD) 171 #define BFCMAP_PHY84756_PA_100MB (BFCMAP_PHY84756_PA_100MB_HD | \ 172 BFCMAP_PHY84756_PA_100MB_FD) 173 #define BFCMAP_PHY84756_PA_1000MB (BFCMAP_PHY84756_PA_1000MB_HD | \ 174 BFCMAP_PHY84756_PA_1000MB_FD) 175 176 #define BFCMAP_PHY84756_PA_SPEED_ALL (BFCMAP_PHY84756_PA_1000MB | \ 177 BFCMAP_PHY84756_PA_100MB | \ 178 BFCMAP_PHY84756_PA_10MB) 179 180 #define BFCMAP_PHY84756_PA_FD (BFCMAP_PA_PHY84756_1000MB_FD | \ 181 BFCMAP_PHY84756_PA_100MB_FD | \ 182 BFCMAPPHY84756__PA_10MB_FD) 183 184 #define BFCMAP_PHY84756_PA_HD (BFCMAP_PHY84756_PA_1000MB_HD | \ 185 BFCMAP_PHY84756_PA_100MB_HD | \ 186 BFCMAP_PHY84756_PA_10MB_HD) 187 188 #define BFCMAP_PHY84756_PA_FCMAP (1 << 0) 189 #define BFCMAP_PHY84756_PA_FCMAP_FCMAC_LOOPBACK (1 << 1) 190 #define BFCMAP_PHY84756_PA_FCMAP_AUTONEG (1 << 2) 191 #define BFCMAP_PHY84756_PA_FCMAP_2GB (1 << 3) 192 #define BFCMAP_PHY84756_PA_FCMAP_4GB (1 << 4) 193 #define BFCMAP_PHY84756_PA_FCMAP_8GB (1 << 5) 194 #define BFCMAP_PHY84756_PA_FCMAP_16GB (1 << 6) 195 196 /* 197 * Port mode 198 */ 199 #define BFCMAP_PHY84756_MODE_FCMAP (1 << 0) 200 201 /* 202 * Standalone PHY driver functions 203 */ 204 extern int 205 bfcmap_phy84756_phy_mac_driver_attach(phy_ctrl_t *pc, 206 blmi_dev_addr_t fcmap_dev_addr, 207 int dev_port, blmi_dev_io_f mmi_cbf); 208 extern int 209 bfcmap_phy84756_phy_mac_driver_detach(phy_ctrl_t *pc); 210 211 212 /* Init PHY with MDIO address phy_id */ 213 extern int 214 bfcmap_phy84756_init(phy_ctrl_t *pc, buint8_t reset, int line_mode, 215 int fcmap_enable, int phy_ext_boot); 216 217 /* Reset PHY with MDIO address phy_id */ 218 extern int 219 bfcmap_phy84756_reset(phy_ctrl_t *pc); 220 221 /* Post Reset PHY setup with MDIO address phy_id */ 222 extern int 223 bfcmap_phy84756_no_reset_setup(phy_ctrl_t *pc, int line_mode, 224 int phy_ext_boot); 225 226 /* Enable/Disable PHY */ 227 extern int 228 bfcmap_phy84756_enable_set(phy_ctrl_t *pc, int enable); 229 230 /* Set Speed of PHY and (Line and Switch) UNIMACs */ 231 extern int 232 bfcmap_phy84756_speed_set(phy_ctrl_t *pc, int speed); 233 234 /* Get Speed of PHY and (Line and Switch) UNIMACs */ 235 extern int 236 bfcmap_phy84756_speed_get(phy_ctrl_t *pc, int *speed); 237 238 /* Set duplex of PHY and (Line and Switch) UNIMACs */ 239 extern int 240 bfcmap_phy84756_duplex_set(phy_ctrl_t *pc, bfcmap_phy84756_duplex_t duplex); 241 242 /* Get duplex of PHY and (Line and Switch) UNIMACs */ 243 extern int 244 bfcmap_phy84756_duplex_get(phy_ctrl_t *pc, bfcmap_phy84756_duplex_t *duplex); 245 246 /* Set AUTO negotiation Attributes */ 247 extern int 248 bfcmap_phy84756_an_set(phy_ctrl_t *pc, int an, int autoneg_advert); 249 250 /* Get AUTO negotiation Attributes */ 251 extern int 252 bfcmap_phy84756_an_get(phy_ctrl_t *pc, int *an, int *an_done); 253 254 /* Set MDIX */ 255 extern int 256 bfcmap_phy84756_mdix_set(phy_ctrl_t *pc, bfcmap_phy84756_port_mdix_t mdix_mode); 257 258 /* MDIX Status Get */ 259 extern int 260 bfcmap_phy84756_mdix_status_get(phy_ctrl_t *pc, 261 bfcmap_phy84756_port_mdix_status_t *status); 262 /* Set Loopback */ 263 extern int 264 bfcmap_phy84756_loopback_set(phy_ctrl_t *pc, int loopback); 265 266 /* Get loopback settings of the PHY */ 267 extern int 268 bfcmap_phy84756_loopback_get(phy_ctrl_t *pc, int *loopback); 269 270 /* Set master */ 271 extern int 272 bfcmap_phy84756_master_set(phy_ctrl_t *pc, bfcmap_phy84756_master_t master); 273 274 /* Get Master */ 275 extern int 276 bfcmap_phy84756_master_get(phy_ctrl_t *pc, int *master); 277 278 /* Set local autoneg advertising parameters */ 279 extern int 280 bfcmap_phy84756_ability_advert_set(phy_ctrl_t *pc, 281 bfcmap_phy84756_port_ability_t ability); 282 283 /* Get local autoneg advertising parameters */ 284 extern int 285 bfcmap_phy84756_ability_advert_get(phy_ctrl_t *pc, 286 bfcmap_phy84756_port_ability_t *ability); 287 288 /* Get Remote autoneg advertising parameters */ 289 extern int 290 bfcmap_phy84756_remote_ability_advert_get(phy_ctrl_t *pc, 291 bfcmap_phy84756_port_ability_t *ability); 292 293 /* Get Link status */ 294 extern int 295 bfcmap_phy84756_link_get(phy_ctrl_t *pc, int *link); 296 297 /* Get Link fault status */ 298 extern int 299 bfcmap_phy84756_linkfault_get(phy_ctrl_t *pc, int *fault); 300 301 /* Get Link fault trigger and reason code */ 302 extern int 303 bfcmap_phy84756_linkfault_trigger_rc_get(phy_ctrl_t *pc, uint32 *lf_trigger, uint32 *lf_rc); 304 305 306 /* Gets the Ability of the PHY */ 307 extern int 308 bfcmap_phy84756_ability_local_get(phy_ctrl_t *pc, 309 bfcmap_phy84756_port_ability_t *ability); 310 311 /* Download the firmware */ 312 extern int 313 bfcmap_phy84756_mdio_firmware_download(phy_ctrl_t *pc, 314 buint8_t *new_fw, buint32_t fw_length); 315 /* Firmware Update */ 316 extern int 317 bfcmap_phy84756_spi_firmware_update(phy_ctrl_t *pc, 318 buint8_t *array, buint32_t datalen); 319 /* Get Interface of side */ 320 extern int 321 bfcmap_phy84756_line_intf_get(phy_ctrl_t *pc, int dev_port, 322 bfcmap_phy84756_intf_t *mode); 323 /* Set Interface of side */ 324 extern int 325 bfcmap_phy84756_line_intf_set(phy_ctrl_t *pc, int dev_port, 326 bfcmap_phy84756_intf_t mode); 327 328 329 /* 1588 related */ 330 331 #define BFCMAP_PORT_PHY_TIMESYNC_ETHERNET_CAPABLE (1U<<0) 332 #define BFCMAP_PORT_PHY_TIMESYNC_MPLS_CAPABLE (1U<<1) 333 #define BFCMAP_PORT_PHY_TIMESYNC_BEH_CAPABLE (1U<<2) 334 335 extern int 336 bfcmap_port_phy_timesync_capability_get(blmi_dev_addr_t phy_id, buint32_t *cap); 337 338 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_FLAGS (1U << 0) 339 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_ITPID (1U << 1) 340 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_OTPID (1U << 2) 341 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_OTPID2 (1U << 3) 342 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_GMODE (1U << 4) 343 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE (1U << 5) 344 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE (1U << 6) 345 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER (1U << 7) 346 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE (1U << 8) 347 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET (1U << 9) 348 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET (1U << 10) 349 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE (1U << 11) 350 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE (1U << 12) 351 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE (1U << 13) 352 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE (1U << 14) 353 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE (1U << 15) 354 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE (1U << 16) 355 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE (1U << 17) 356 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE (1U << 18) 357 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL (1U << 19) 358 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY (1U << 20) 359 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 (1U << 21) 360 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 (1U << 22) 361 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 (1U << 23) 362 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER (1U << 24) 363 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE (1U << 25) 364 #define BFCMAP_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA (1U << 26) 365 366 #define BFCMAP_PORT_PHY_TIMESYNC_ENABLE (1U<<0) 367 #define BFCMAP_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE (1U<<1) /* per port */ 368 #define BFCMAP_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE (1U<<2) 369 #define BFCMAP_PORT_PHY_TIMESYNC_RX_CRC_ENABLE (1U<<3) 370 #define BFCMAP_PORT_PHY_TIMESYNC_8021AS_ENABLE (1U<<4) 371 #define BFCMAP_PORT_PHY_TIMESYNC_L2_ENABLE (1U<<5) 372 #define BFCMAP_PORT_PHY_TIMESYNC_IP4_ENABLE (1U<<6) 373 #define BFCMAP_PORT_PHY_TIMESYNC_IP6_ENABLE (1U<<7) 374 #define BFCMAP_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT (1U<<8) /* 0 - NCO FREQ CTRL REG, 1 - DPLL */ 375 #define BFCMAP_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT_MODE (1U<<9) /* DPLL 0 - phase, 1 - freq lock */ 376 377 /* Base time structure. */ 378 typedef struct bfcmap_time_spec_s { 379 buint8_t isnegative; /* Sign identifier. */ 380 buint64_t seconds; /* Seconds absolute value. */ 381 buint32_t nanoseconds; /* Nanoseconds absolute value. */ 382 } bfcmap_time_spec_t; 383 384 /* Actions on Egress event messages */ 385 typedef enum bfcmap_port_phy_timesync_event_message_egress_mode_e { 386 BFCMAP_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE, 387 BFCMAP_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD, 388 BFCMAP_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN, 389 BFCMAP_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP 390 } bfcmap_port_phy_timesync_event_message_egress_mode_t; 391 392 /* Actions on ingress event messages */ 393 typedef enum bfcmap_port_phy_timesync_event_message_ingress_mode_e { 394 BFCMAP_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE, 395 BFCMAP_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD, 396 BFCMAP_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP, 397 BFCMAP_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME 398 } bfcmap_port_phy_timesync_event_message_ingress_mode_t; 399 400 /* Global mode actions */ 401 typedef enum bfcmap_port_phy_timesync_global_mode_e { 402 BFCMAP_PORT_PHY_TIMESYNC_MODE_FREE, 403 BFCMAP_PORT_PHY_TIMESYNC_MODE_SYNCIN, 404 BFCMAP_PORT_PHY_TIMESYNC_MODE_CPU 405 } bfcmap_port_phy_timesync_global_mode_t; 406 407 /* framesync mode */ 408 typedef enum bfcmap_port_phy_timesync_framesync_mode_e { 409 BFCMAP_PORT_PHY_TIMESYNC_FRAMESYNC_NONE, /* Do nothing */ 410 BFCMAP_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN0, /* Use syncin as the source */ 411 BFCMAP_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN1, /* CPU based framesync */ 412 BFCMAP_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCOUT, /* CPU based framesync */ 413 BFCMAP_PORT_PHY_TIMESYNC_FRAMESYNC_CPU /* CPU based framesync */ 414 } bfcmap_port_phy_timesync_framesync_mode_t; 415 416 /* framesync configuration type. */ 417 typedef struct bfcmap_port_phy_timesync_framesync_s { 418 bfcmap_port_phy_timesync_framesync_mode_t mode; /* framesync mode */ 419 buint16_t length_threshold; /* syncin threshold for framesync */ 420 buint16_t event_offset; /* event offset for framesync */ 421 } bfcmap_port_phy_timesync_framesync_t; 422 423 typedef enum bfcmap_port_phy_timesync_syncout_mode_s 424 { 425 BFCMAP_PORT_PHY_TIMESYNC_SYNCOUT_DISABLE, 426 BFCMAP_PORT_PHY_TIMESYNC_SYNCOUT_ONE_TIME, 427 BFCMAP_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN, 428 BFCMAP_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN_WITH_SYNC 429 } bfcmap_port_phy_timesync_syncout_mode_t; 430 431 typedef struct bfcmap_port_phy_timesync_syncout_s { 432 433 bfcmap_port_phy_timesync_syncout_mode_t mode; 434 buint16_t pulse_1_length; /* in nanoseconds */ 435 buint16_t pulse_2_length; /* in nanoseconds */ 436 buint16_t interval; /* in nanoseconds */ 437 buint64_t syncout_ts; 438 439 } bfcmap_port_phy_timesync_syncout_t; 440 441 /* mpls_label_flags */ 442 #define BFCMAP_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT (1U<<1) 443 #define BFCMAP_PORT_PHY_TIMESYNC_MPLS_LABEL_IN (1U<<0) 444 445 typedef struct bfcmap_port_phy_timesync_mpls_label_s { 446 447 buint32_t label_value; /* bits [19:0] */ 448 buint32_t label_mask; /* bits [19:0] */ 449 buint32_t label_flags; /* label flags */ 450 451 } bfcmap_port_phy_timesync_mpls_label_t; 452 453 /* mpls_flags */ 454 #define BFCMAP_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE (1U<<3) 455 #define BFCMAP_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE (1U<<2) 456 #define BFCMAP_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE (1U<<1) 457 #define BFCMAP_PORT_PHY_TIMESYNC_MPLS_ENABLE (1U<<0) 458 459 typedef struct bfcmap_port_phy_timesync_mpls_control_s { 460 461 buint32_t flags; 462 buint32_t special_label; /* bits [19:0] */ 463 bfcmap_port_phy_timesync_mpls_label_t labels[10]; /* label */ 464 465 } bfcmap_port_phy_timesync_mpls_control_t; 466 467 /* Base timesync configuration type. */ 468 typedef struct bfcmap_port_phy_timesync_config_s { 469 buint32_t validity_mask; /* Flags BCM_PORT_PHY_TIMESYNC_VALID_* */ 470 buint32_t flags; /* Flags BFCMAP_PORT_TIMESYNC_* */ 471 buint16_t itpid; /* 1588 inner tag */ 472 buint16_t otpid; /* 1588 outer tag */ 473 buint16_t otpid2; /* 1588 outer tag 2 */ 474 bfcmap_port_phy_timesync_global_mode_t gmode; /* Global mode */ 475 bfcmap_port_phy_timesync_framesync_t framesync; 476 bfcmap_port_phy_timesync_syncout_t syncout; 477 buint16_t ts_divider; /* TS divider */ 478 bfcmap_time_spec_t original_timecode; /* Original timecode to be inserted */ 479 buint32_t tx_timestamp_offset; /* TX AFE delay in ns - per port */ 480 buint32_t rx_timestamp_offset; /* RX AFE delay in ns - per port */ 481 buint32_t rx_link_delay; /* RX link delay */ 482 bfcmap_port_phy_timesync_event_message_egress_mode_t tx_sync_mode; /* sync */ 483 bfcmap_port_phy_timesync_event_message_egress_mode_t tx_delay_request_mode; /* delay request */ 484 bfcmap_port_phy_timesync_event_message_egress_mode_t tx_pdelay_request_mode; /* pdelay request */ 485 bfcmap_port_phy_timesync_event_message_egress_mode_t tx_pdelay_response_mode; /* pdelay response */ 486 bfcmap_port_phy_timesync_event_message_ingress_mode_t rx_sync_mode; /* sync */ 487 bfcmap_port_phy_timesync_event_message_ingress_mode_t rx_delay_request_mode; /* delay request */ 488 bfcmap_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_request_mode; /* pdelay request */ 489 bfcmap_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_response_mode; /* pdelay response */ 490 491 bfcmap_port_phy_timesync_mpls_control_t mpls_control; 492 493 buint16_t phy_1588_dpll_k1; 494 buint16_t phy_1588_dpll_k2; 495 buint16_t phy_1588_dpll_k3; 496 buint64_t phy_1588_dpll_loop_filter; /* DPLL loop filter */ 497 buint64_t phy_1588_dpll_ref_phase; /* DPLL ref phase */ 498 buint32_t phy_1588_dpll_ref_phase_delta; /* DPLL ref phase delta */ 499 500 } bfcmap_port_phy_timesync_config_t; 501 502 /* bfcmap_port_phy_timesync_config_set */ 503 extern int 504 bfcmap_port_phy_timesync_config_set( 505 blmi_dev_addr_t phy_id, 506 bfcmap_port_phy_timesync_config_t *conf); 507 508 /* bfcmap_port_phy_timesync_config_get */ 509 extern int 510 bfcmap_port_phy_timesync_config_get( 511 blmi_dev_addr_t phy_id, 512 bfcmap_port_phy_timesync_config_t *conf); 513 514 /* Fast call actions */ 515 typedef enum bfcmap_port_phy_control_timesync_e { 516 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_CAPTURE_TIMESTAMP, 517 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_HEARTBEAT_TIMESTAMP, 518 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_NCOADDEND, 519 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_FRAMESYNC, 520 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_LOCAL_TIME, 521 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_LOAD_CONTROL, 522 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT, 523 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT_MASK, 524 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_TX_TIMESTAMP_OFFSET, 525 BFCMAP_PORT_CONTROL_PHY_TIMESYNC_RX_TIMESTAMP_OFFSET 526 } bfcmap_port_control_phy_timesync_t; 527 528 #define BFCMAP_PORT_PHY_TIMESYNC_TN_LOAD (1U<<23) 529 #define BFCMAP_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD (1U<<22) 530 #define BFCMAP_PORT_PHY_TIMESYNC_TIMECODE_LOAD (1U<<21) 531 #define BFCMAP_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD (1U<<20) 532 #define BFCMAP_PORT_PHY_TIMESYNC_SYNCOUT_LOAD (1U<<19) 533 #define BFCMAP_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD (1U<<18) 534 #define BFCMAP_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD (1U<<17) 535 #define BFCMAP_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD (1U<<16) 536 #define BFCMAP_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD (1U<<15) 537 #define BFCMAP_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD (1U<<14) 538 #define BFCMAP_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD (1U<<13) 539 #define BFCMAP_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD (1U<<12) 540 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD (1U<<11) 541 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD (1U<<10) 542 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD (1U<<9) 543 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD (1U<<8) 544 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD (1U<<7) 545 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD (1U<<6) 546 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_K3_LOAD (1U<<5) 547 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD (1U<<4) 548 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_K2_LOAD (1U<<3) 549 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD (1U<<2) 550 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_K1_LOAD (1U<<1) 551 #define BFCMAP_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD (1U<<0) 552 553 #define BFCMAP_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT (1U<<1) 554 #define BFCMAP_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT (1U<<0) 555 556 #define BFCMAP_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK (1U<<1) 557 #define BFCMAP_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK (1U<<0) 558 559 /* bfcmap_port_control_phy_timesync_set */ 560 extern int 561 bfcmap_port_control_phy_timesync_set( 562 blmi_dev_addr_t phy_id, 563 bfcmap_port_control_phy_timesync_t type, 564 buint64_t value); 565 566 /* bfcmap_port_control_phy_timesync_get */ 567 extern int 568 bfcmap_port_control_phy_timesync_get( 569 blmi_dev_addr_t phy_id, 570 bfcmap_port_control_phy_timesync_t type, 571 buint64_t *value); 572 573 574 #endif /* _bfcmap_phy84756_H_ */