phy84740.h (15522B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy84740.h 8 */ 9 10 #ifndef _PHY84740_H_ 11 #define _PHY84740_H_ 12 13 #include <soc/phy.h> 14 15 16 /* 84740 Devices */ 17 #define PHY84740_C45_DEV_PMA_PMD 0x01 18 #define PHY84740_C45_DEV_PCS 0x03 19 #define PHY84740_C45_DEV_AN 0x07 20 21 #define PHY84740_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 22 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 23 #define PHY84740_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 24 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 25 #define PHY84740_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 26 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 27 28 #define PHY84740_XFI(_unit, _phy_ctrl) \ 29 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 30 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, (0xffff)), 1, 1) 31 32 #define PHY84740_MMF(_unit, _phy_ctrl) \ 33 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 34 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, (0xffff)), 0,1) 35 36 #define PHY84740_XFI_IF_INTF(unit, _phy_ctrl, intf, interface) {\ 37 if(intf == interface) {\ 38 SOC_IF_ERROR_RETURN \ 39 (PHY84740_XFI(unit, _phy_ctrl));}} 40 41 #define PHY84740_MMF_IF_INTF(unit, _phy_ctrl, intf, interface) {\ 42 if(intf == interface) {\ 43 SOC_IF_ERROR_RETURN \ 44 (PHY84740_MMF(unit, _phy_ctrl));}} 45 46 /* 47 * Line side 48 */ 49 /* PMA/PMD Device (Dev Addr 1) */ 50 #define READ_PHY84740_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 51 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 52 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, (_reg)), (_val)) 53 #define WRITE_PHY84740_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 54 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 55 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, (_reg)), (_val)) 56 #define MODIFY_PHY84740_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 57 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 58 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask)) 59 60 /* PCS Device (Dev Addr 3) */ 61 #define READ_PHY84740_MMF_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 62 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 63 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val)) 64 #define WRITE_PHY84740_MMF_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 65 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 66 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val)) 67 #define MODIFY_PHY84740_MMF_PCS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 68 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 69 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val), (_mask)) 70 71 /* AN Device (Dev Addr 7) */ 72 #define READ_PHY84740_MMF_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 73 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 74 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_AN, (_reg)), (_val)) 75 #define WRITE_PHY84740_MMF_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 76 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 77 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_AN, (_reg)), (_val)) 78 #define MODIFY_PHY84740_MMF_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 79 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 80 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_AN, (_reg)), (_val), (_mask)) 81 82 83 /* 84 * XFI Side 85 */ 86 /* PMA Device (Dev Addr 1) */ 87 #define READ_PHY84740_XFI_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 88 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 89 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, (_reg)), (_val)) \ 90 91 #define WRITE_PHY84740_XFI_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 92 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 93 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, (_reg)), (_val)) \ 94 95 #define MODIFY_PHY84740_XFI_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 96 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 97 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask))\ 98 99 /* PCS Device (Dev Addr 3) */ 100 #define READ_PHY84740_XFI_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 101 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 102 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val)) \ 103 104 #define WRITE_PHY84740_XFI_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 105 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 106 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val)) \ 107 108 #define MODIFY_PHY84740_XFI_PCS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 109 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 110 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val), (_mask))\ 111 112 113 /* AN Device (Dev Addr 1) */ 114 #define READ_PHY84740_XFI_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 115 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 116 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_AN, (_reg)), (_val)) \ 117 118 #define WRITE_PHY84740_XFI_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 119 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 120 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_AN, (_reg)), (_val)) \ 121 122 #define MODIFY_PHY84740_XFI_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 123 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 124 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_AN, (_reg)), (_val), (_mask))\ 125 126 127 128 /* PMA/PMD registers */ 129 #define PHY84740_PMAD_CTRL_REG 0x00 130 #define PHY84740_PMAD_STAT_REG 0x01 131 #define PHY84740_PMAD_ID0_REG 0x02 132 #define PHY84740_PMAD_ID1_REG 0x03 133 #define PHY84740_PMAD_CTRL2_REG 0x07 134 #define PHY84740_PMAD_STAT2_REG 0x08 135 136 #define PHY84740_SPEED_LINK_DETECT_STAT_REG 0xc820 137 #define PHY84740_PMAD_BCST_REG 0xc8fe 138 #define PHY84740_PMAD_CHIP_MODE_REG 0xc805 139 #define PHY84740_PMAD_SPA_CTRL_REG 0xc848 140 #define PHY84740_PMAD_MISC_CTRL1_REG 0xca85 141 #define PHY84740_PMAD_M8051_MSGIN_REG 0xca12 142 #define PHY84740_PMAD_M8051_MSGOUT_REG 0xca13 143 #define PHY84740_PMAD_AER_ADDR_REG 0xc702 144 #define PHY84740_PMAD_CHIP_MODE_MASK 0x3 145 #define PHY84740_PMAD_DAC_MODE_MASK (1 << 3) 146 #define PHY84740_PMAD_BKPLANE_MODE_MASK (1 << 2) 147 #define PHY84740_PMAD_DAC_MODE 0x8 148 #define PHY84740_PMAD_MODE_40G 0x1 149 150 /* logical lane0 to physical lane mapping register */ 151 #define PHY84740_PMAD_LANE0_L2P_REG 0xc701 152 #define PHY84740_L2P_PHYSICAL_LANE_MASK 0x7 153 154 /* chip intr value register */ 155 #define PHY84740_PMAD_INTR_VALUE_REG 0xc878 156 #define PHY84740_AUTONEG_COMPLETE (1 << 11) 157 158 /* Optical Configuration Register */ 159 #define PHY84740_PMAD_OPTICAL_CFG_REG 0xc8e4 160 #define PHY84740_RXLOS_OVERRIDE_MASK 0xc0c0 161 #define PHY84740_MOD_ABS_OVERRIDE_MASK 0x0808 162 163 /* Optical signal active level configuration */ 164 #define PHY84740_PMAD_OPTICAL_SIG_LVL_REG 0xc800 165 #define PHY84740_RXLOS_LVL_MASK (1 << 9) 166 #define PHY84740_MOD_ABS_LVL_MASK (1 << 8) 167 168 /* Recovery clock enable control */ 169 #define PHY84740_PMAD_RECOVERY_CLK_REG 0xcb27 170 #define PHY84740_PMAD_RECOVERY_CLK_FREQ_REG 0xcb26 171 172 #define PHY84740_RECOVERY_CLK_ENABLE_MASK (1 << 0) 173 #define PHY84740_RECOVERY_CLK_FREQ_SHIFT 13 174 #define PHY84740_RECOVERY_CLK_FREQf(_f) ((_f) << PHY84740_RECOVERY_CLK_FREQ_SHIFT) 175 #define PHY84740_RECOVERY_CLK_FREQ_MASK (0x3 << PHY84740_RECOVERY_CLK_FREQ_SHIFT) 176 177 /* Optics digital control register */ 178 #define PHY84740_DIG_CTRL_REG 0xcd08 179 #define PHY84740_TX_POLARITY_FLIP_MASK (1 << 10) 180 #define PHY84740_RX_POLARITY_FLIP_MASK (1 << 9) 181 182 183 /* PCS registers */ 184 #define PHY84740_PCS_CTRL_REG 0x00 185 #define PHY84740_PCS_STAT_REG 0x01 186 #define PHY84740_PCS_ID0_REG 0x02 187 #define PHY84740_PCS_ID1_REG 0x03 188 #define PHY84740_PCS_CTRL2_REG 0x07 189 #define PHY84740_PCS_STAT2_REG 0x08 190 191 /* AN Registers */ 192 #define PHY84740_AN_CTRL_REG 0xffe0 193 #define PHY84740_AN_STAT_REG 0xffe1 194 195 196 /* PMA/PMD Standard registers definations */ 197 /* Control Register */ 198 #define PHY84740_MII_CTRL_PMA_LOOPBACK (1 << 0) 199 200 /* PMA/PMD User define registers definations */ 201 /* Speed Link Detect status register definations */ 202 #define PHY84740_1G_MODE 0x0021 203 204 205 /* AN registers definations */ 206 /* AN Status Register definations */ 207 #define PHY84740_AN_STAT_LA 0x0004 208 209 210 211 /* Chip ID register */ 212 #define READ_PHY84740_PMA_PMD_CHIPIDr(_unit, _phy_ctrl, _val) \ 213 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 214 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 0xc802), (_val)) 215 216 /* Chip Revision register */ 217 #define READ_PHY84740_PMA_PMD_CHIPREVr(_unit, _phy_ctrl, _val) \ 218 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 219 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 0xc801), (_val)) 220 221 /* Control Register (Addr 0000h) */ 222 #define READ_PHY84740_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 223 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 224 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 0), (_val)) 225 #define WRITE_PHY84740_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 226 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 227 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 0), (_val)) 228 #define MODIFY_PHY84740_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 229 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 230 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 0), (_val), (_mask)) 231 232 /* Status Register (Addr 0001h) */ 233 #define READ_PHY84740_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 234 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 235 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 1), (_val)) 236 #define WRITE_PHY84740_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 237 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 238 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 1), (_val)) 239 #define MODIFY_PHY84740_PMA_PMD_STATr(_unit, _phy_ctrl, _val, _mask) \ 240 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 241 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 1), (_val), (_mask)) 242 243 /* ID0 Register (Addr 0002h) */ 244 /* ID1 Register (Addr 0003h) */ 245 /* Speed Ability Register (Addr 0004h) */ 246 /* Devices in Package 1 Register (Addr 0005h) */ 247 /* Devices in Package 2 Register (Addr 0006h) */ 248 /* Control 2 Register (Addr 0007h) */ 249 250 #define PHY84740_PMAD_CTRL2r_PMA_TYPE_MASK 0xF 251 #define PHY84740_PMAD_CTRL2r_PMA_TYPE_1G_KX 0xD 252 #define PHY84740_PMAD_CTRL2r_PMA_TYPE_10G_KR 0xB 253 #define PHY84740_PMAD_CTRL2r_PMA_TYPE_10G_LRM 0x8 254 255 /* Status 2 Register (Addr 0008h) */ 256 257 /* Transmit Disable Register (Addr 0009h) */ 258 #define READ_PHY84740_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 259 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 260 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 9), (_val)) 261 #define WRITE_PHY84740_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 262 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 263 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 9), (_val)) 264 #define MODIFY_PHY84740_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 265 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 266 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PMA_PMD, 9), (_val), (_mask)) 267 268 269 /* Receive Signal Detect Register (Addr 000Ah) */ 270 /* Organizationlly Unique Identifier 0 Register (Addr 000Eh) */ 271 /* Organizationlly Unique Identifier 1 Register (Addr 000Fh) */ 272 273 /* PCS Device (Dev Addr 3) */ 274 #define READ_PHY84740_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 275 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 276 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val)) 277 #define WRITE_PHY84740_PCS_REG(_unit, _phy_ctrl, _reg,_val) \ 278 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 279 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val)) 280 #define MODIFY_PHY84740_PCS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 281 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 282 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, (_reg)), (_val), (_mask)) 283 284 /* Control 1 Register (Addr 0000h) */ 285 #define READ_PHY84740_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 286 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 287 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, 0), (_val)) 288 #define WRITE_PHY84740_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 289 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 290 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, 0), (_val)) 291 #define MODIFY_PHY84740_PCS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 292 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 293 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, 0), (_val), (_mask)) 294 295 /* Status 1 Register (Addr 0001h) */ 296 #define READ_PHY84740_PCS_STATr(_unit, _phy_ctrl, _val) \ 297 PHY84740_REG_READ((_unit), (_phy_ctrl), \ 298 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, 1), (_val)) 299 #define WRITE_PHY84740_PCS_STATr(_unit, _phy_ctrl, _val) \ 300 PHY84740_REG_WRITE((_unit), (_phy_ctrl), \ 301 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, 1), (_val)) 302 #define MODIFY_PHY84740_PCS_STATr(_unit, _phy_ctrl, _val, _mask) \ 303 PHY84740_REG_MODIFY((_unit), (_phy_ctrl), \ 304 SOC_PHY_CLAUSE45_ADDR(PHY84740_C45_DEV_PCS, 1), (_val), (_mask)) 305 306 /* CL73 autoneg control register */ 307 308 #define AN_CTRL_REG 0 309 #define AN_EXT_NXT_PAGE (1 << 13) 310 #define AN_ENABLE (1 << 12) 311 #define AN_RESTART (1 << 9) 312 313 /* autoneg status register */ 314 315 #define AN_STATUS_REG 1 316 #define AN_LP_AN_ABILITY (1 << 0) 317 #define AN_LINK (1 << 2) 318 #define AN_DONE (1 << 5) 319 320 /* autoneg advertisement register 0 */ 321 #define AN_ADVERT_0_REG 0x10 322 #define AN_ADVERT_PAUSE (1 << 10) 323 #define AN_ADVERT_PAUSE_ASYM (1 << 11) 324 325 /* autoneg advertisement register 1 */ 326 327 #define AN_ADVERT_1_REG 0x11 328 #define AN_ADVERT_10G (1 << 7) 329 #define AN_ADVERT_1G (1 << 5) 330 331 /* autoneg advertisement register 2 */ 332 333 #define AN_ADVERT_2_REG 0x12 334 #define AN_ADVERT_FEC (1 << 15) 335 336 /* Link Partner base ability page 0 */ 337 338 #define AN_LP_ABILITY_0_REG 0x13 339 340 /* Link Partner base ability page 1 */ 341 342 #define AN_LP_ABILITY_1_REG 0x14 343 344 /* Link Partner base ability page 2 */ 345 346 #define AN_LP_ABILITY_2_REG 0x15 347 348 /* autoneg control register */ 349 #define PHY84740_AN_EXT_NXT_PAGE (1 << 13) 350 #define PHY84740_AN_ENABLE (1 << 12) 351 #define PHY84740_AN_RESTART (1 << 9) 352 353 /* autoneg status register */ 354 #define PHY84740_AN_STATUS_REG 1 355 #define PHY84740_AN_LINK (1 << 2) 356 #define PHY84740_AN_DONE (1 << 5) 357 358 /* 1G status register for both autoneg mode and forced mode */ 359 #define AN_1G_STATUS_REG 0x8304 360 #define AN_1G_LINKUP 0x2 361 #define AN_1G_LINK_CHANGE 0x80 362 363 #endif /* _phy84740_H_ */