phy84728_int.h (90741B)
1 2 /* 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 9 #ifndef _PHY84728_INT_H 10 #define _PHY84728_INT_H 11 12 /**************************************************************************** 13 * Firmware related: 14 */ 15 #define BSDK_PHY84728_FW_CHECKSUM 0x600D 16 #define BSDK_PHY84728_FW_NUM_ITER 5 17 18 #define BSDK_PHY84728_FW_DWNLD_DONE_MSG 0x4321 19 #define BSDK_PHY84728_FW_TOTAL_WR_BYTE 0x4000 20 21 #define BSDK_PHY84728_PMAD_M8051_MSGIN_REG 0xca12 22 #define BSDK_PHY84728_PMAD_M8051_MSGOUT_REG 0xca13 23 24 /************************************************************************ 25 * 26 * Channel 0 and 1 : LINE : Device 1 (PMA/PMD) 27 */ 28 29 /* Speed Link status register defination */ 30 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_10M (1 << 0) 31 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_100M (1 << 1) 32 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_1G (1 << 2) 33 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_10G (1 << 4) 34 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_AN_COMPLETE (1 << 6) 35 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_RX_SD (1 << 7) 36 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_10M (1 << 8) 37 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_100M (1 << 9) 38 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_1G (1 << 10) 39 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_10G (1 << 12) 40 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_AN_COMPLETE (1 << 14) 41 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_RX_SD (1 << 15) 42 43 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_MASK \ 44 (BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_10M | \ 45 BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_100M | \ 46 BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_1G | \ 47 BSDK_PHY84728_PMD_SPEED_LD_STAT_LN_PDM_SPEED_10G) 48 49 #define BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_MASK \ 50 (BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_10M | \ 51 BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_100M | \ 52 BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_1G | \ 53 BSDK_PHY84728_PMD_SPEED_LD_STAT_SYS_PDM_SPEED_10G) 54 55 56 /* DEV1 MACSEC Control register defination */ 57 #define BSDK_PHY84728_LN_DEV1_MACSEC_CTRL_BYPASS_MODE (1 << 0) 58 #define BSDK_PHY84728_LN_DEV1_MACSEC_CTRL_ENABLE_PWRDN_MACSEC (1 << 8) 59 #define BSDK_PHY84728_LN_DEV1_MACSEC_CTRL_UDSW_PWRDW_MACSEC (1 << 11) 60 #define BSDK_PHY84728_LN_DEV1_MACSEC_CTRL_UDSW_RESET_MACSEC (1 << 15) 61 62 /* Chip Mode Resister (Addr 0xc805) */ 63 #define BSDK_PHY84728_LN_DEV1_CHIP_MODE_DAC_MASK (1 << 3) 64 #define BSDK_PHY84728_LN_DEV1_CHIP_MODE_BKPLANE_MASK (1 << 2) 65 66 67 68 /* PMD Control Register definations */ 69 #define BSDK_PHY84728_PMD_CTRL_PMS_LOOPBACK (1 << 0) /* Loopback */ 70 #define BSDK_PHY84728_PMD_CTRL_SS_MSB (1 << 6) /* Speed select, MSb */ 71 #define BSDK_PHY84728_PMD_CTRL_PD (1 << 11) /* Power Down */ 72 #define BSDK_PHY84728_PMD_CTRL_SS_LSB (1 << 13) /* Speed select, LSb */ 73 #define BSDK_PHY84728_PMD_CTRL_RESET (1 << 15) /* PHY reset */ 74 75 #define BSDK_PHY84728_PMD_CTRL_SS_SPEED_SEL \ 76 (BSDK_PHY84728_PMD_CTRL_SS_LSB | \ 77 BSDK_PHY84728_PMD_CTRL_SS_MSB) 78 #define BSDK_PHY84728_PMD_CTRL_SS_MASK \ 79 (BSDK_PHY84728_PMD_CTRL_SS_LSB | \ 80 BSDK_PHY84728_PMD_CTRL_SS_MSB) 81 82 #define BSDK_PHY84728_PMD_CTRL_10GSS_MASK \ 83 (BSDK_PHY84728_PMD_CTRL_SS_LSB | \ 84 BSDK_PHY84728_PMD_CTRL_SS_MSB | \ 85 (1 << 2) | \ 86 (1 << 3) | \ 87 (1 << 4) | \ 88 (1 << 5)) 89 90 #define BSDK_PHY84728_PMD_CTRL_SS_10 0 91 #define BSDK_PHY84728_PMD_CTRL_SS_100 \ 92 (BSDK_PHY84728_PMD_CTRL_SS_LSB) 93 #define BSDK_PHY84728_PMD_CTRL_SS_1000 (BSDK_PHY84728_PMD_CTRL_SS_MSB) 94 #define BSDK_PHY84728_PMD_CTRL_SS_10000 \ 95 (BSDK_PHY84728_PMD_CTRL_SS_SPEED_SEL | \ 96 (0x0000)) 97 98 99 #define BSDK_PHY84728_PMD_CTRL_SS(_x) \ 100 ((_x) & \ 101 (BSDK_PHY84728_PMD_CTRL_SS_LSB | \ 102 BSDK_PHY84728_PMD_CTRL_SS_MSB)) 103 104 105 106 /* PMD Status Register defination */ 107 #define BSDK_PHY84728_PMD_STAT_RX_LINK_STATUS (1 << 2) 108 109 110 111 /* PMD Control2 Resister definations */ 112 #define BSDK_PHY84728_PMD_CTRL2_PMA_1GTPMD_TYPE (0xc) 113 #define BSDK_PHY84728_PMD_CTRL2_PMA_10GLRMPMD_TYPE (0x8) 114 115 #define BSDK_PHY84728_PMD_CTRL2_PMA_SELECT_MASK (0xf) 116 117 /************************************************************************ 118 * 119 * LINE : Device 3 (PCS) 120 */ 121 /*PCS Control register definations */ 122 #define BSDK_PHY84728_PCS_PCS_CTRL_PD (1 << 11) 123 124 125 /*PCS Status register definations */ 126 #define BSDK_PHY84728_PCS_PCS_STAT_RX_LINK_STATUS (1 << 2) 127 128 129 130 /************************************************************************ 131 * 132 * LINE : Device 7 (AN) 133 */ 134 135 /* 136 * MII Link Advertisment (Clause 37) 137 */ 138 #define BSDK_PHY84728_DEV7_1000X_ANA_C37_FD (1 << 5) 139 #define BSDK_PHY84728_DEV7_1000X_ANA_C37_HD (1 << 6) 140 #define BSDK_PHY84728_DEV7_1000X_ANA_C37_PAUSE (1 << 7) 141 #define BSDK_PHY84728_DEV7_1000X_ANA_C37_ASYM_PAUSE (1 << 8) 142 143 144 /* 145 * MII Link Partner Advertisment (Clause 37) 146 */ 147 #define BSDK_PHY84728_SGMII_ANP_SGMII_MODE (1 << 0) 148 #define BSDK_PHY84728_SGMII_ANP_FD (1 << 5) 149 #define BSDK_PHY84728_SGMII_ANP_HD (1 << 6) 150 #define BSDK_PHY84728_SGMII_ANP_C37_PAUSE (1 << 7) 151 #define BSDK_PHY84728_SGMII_ANPC37_ASYM_PAUSE (1 << 8) 152 153 154 155 156 /*AN MII control register definations */ 157 #define BSDK_PHY84728_AN_MII_CTRL_SS_MSB (1 << 6) /* Speed select, MSb */ 158 #define BSDK_PHY84728_AN_MII_CTRL_FD (1 << 8) /* Full Duplex */ 159 #define BSDK_PHY84728_AN_MII_CTRL_RAN (1 << 9) /* Restart Autoneg `*/ 160 #define BSDK_PHY84728_AN_MII_CTRL_PD (1 << 11) /* Power Down */ 161 #define BSDK_PHY84728_AN_MII_CTRL_AE (1 << 12) /* Autoneg enable */ 162 #define BSDK_PHY84728_AN_MII_CTRL_SS_LSB (1 << 13) /* Speed select, LSb */ 163 #define BSDK_PHY84728_AN_MII_CTRL_LE (1 << 14) /* Loopback enable */ 164 #define BSDK_PHY84728_AN_MII_CTRL_RESET (1 << 15) /* PHY reset */ 165 166 #define BSDK_PHY84728_AN_MII_CTRL_SS(_x) \ 167 ((_x) & \ 168 (BSDK_PHY84728_AN_MII_CTRL_SS_LSB | \ 169 BSDK_PHY84728_AN_MII_CTRL_SS_MSB)) 170 #define BSDK_PHY84728_AN_MII_CTRL_SS_10 0 171 #define BSDK_PHY84728_AN_MII_CTRL_SS_100 (BSDK_PHY84728_AN_MII_CTRL_SS_LSB) 172 #define BSDK_PHY84728_AN_MII_CTRL_SS_1000 (BSDK_PHY84728_AN_MII_CTRL_SS_MSB) 173 #define BSDK_PHY84728_AN_MII_CTRL_SS_INVALID \ 174 (BSDK_PHY84728_AN_MII_CTRL_SS_LSB | \ 175 BSDK_PHY84728_AN_MII_CTRL_SS_MSB) 176 #define BSDK_PHY84728_AN_MII_CTRL_SS_MASK \ 177 (BSDK_PHY84728_AN_MII_CTRL_SS_LSB | \ 178 BSDK_PHY84728_AN_MII_CTRL_SS_MSB) 179 180 /* AN MII Status register definations */ 181 #define BSDK_PHY84728_AN_MII_STAT_LINK_STATUS (1 << 2) 182 #define BSDK_PHY84728_AN_MII_STAT_AN_DONE (1 << 5) 183 184 185 /* AN 1000x Control1 Register definations */ 186 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_FIBER_MODE (1 << 0) 187 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_TBI_INT (1 << 1) 188 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_SD_ENABLE (1 << 2) 189 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_INVERT_SD (1 << 3) 190 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_AUTODETECT_EN (1 << 4) 191 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_SGMII_MASTER (1 << 5) 192 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_DIS_PLL_PWRDN (1 << 6) 193 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_CRC_CHK_DIS (1 << 7) 194 #define BSDK_PHY84728_AN_BASE1000X_CTRL1_COMMA_DET_EN (1 << 8) 195 196 /* 1000x Status1 Register definations */ 197 #define BSDK_PHY84728_AN_BASE1000X_STAT1_SGMII_MODE (1 << 0) 198 #define BSDK_PHY84728_AN_BASE1000X_STAT1_LINK_STATUS (1 << 1) 199 #define BSDK_PHY84728_AN_BASE1000X_STAT1_DUPLEX_STATUS (1 << 2) 200 #define BSDK_PHY84728_AN_BASE1000X_STAT1_SPEED_STATUS ((1 << 3) | \ 201 (1 << 4)) 202 #define BSDK_PHY84728_AN_BASE1000X_STAT1_PAUSE_TX (1 << 5) 203 #define BSDK_PHY84728_AN_BASE1000X_STAT1_PAUSE_RX (1 << 6) 204 205 206 #define BSDK_PHY84728_AN_MISC2_RX_MII_GEN_SEL (1 << 13) 207 #define BSDK_PHY84728_AN_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN (1 << 5) 208 209 #define BSDK_PHY84728_AN_XGXS_CTRL_START_SEQ (1 << 13) 210 211 /* AN Control Register */ 212 #define BSDK_PHY84728_AN_AN_CTRL_RAN (1 << 9) /* Restart AutoNeg */ 213 #define BSDK_PHY84728_AN_AN_CTRL_AE (1 << 12) /* Enable AutoNegn */ 214 #define BSDK_PHY84728_AN_AN_CTRL_RESET (1 << 15) /* Reset AutoNeg */ 215 216 /* AN Status Register */ 217 #define BSDK_PHY84728_AN_AN_STAT_AN_DONE (1 << 5) 218 219 220 extern int 221 bsdk_phy84728_reg_read(phy_ctrl_t * pc, uint32 flags, uint8 reg_bank, 222 uint16 reg_addr, uint16 *data); 223 extern int 224 bsdk_phy84728_reg_write(phy_ctrl_t * pc, uint32 flags, uint8 reg_bank, 225 uint16 reg_addr, uint16 data); 226 extern int 227 bsdk_phy84728_reg_modify(phy_ctrl_t * pc, uint32 flags, uint8 reg_bank, 228 uint16 reg_addr, uint16 data, uint16 mask); 229 230 /* Flag indicating that Line side Access or System side access */ 231 #define BSDK_PHY84728_LINE_SIDE 0 232 #define BSDK_PHY84728_SYS_SIDE 1 233 234 235 #undef READ_PHY_REG 236 #define READ_PHY_REG(_unit, _pc, _addr, _value) \ 237 ((_pc->read)((_pc->unit), (_pc->phy_id), (_addr), (_value))) 238 #undef WRITE_PHY_REG 239 #define WRITE_PHY_REG(_unit, _pc, _addr, _value) \ 240 ((_pc->write)((_pc->unit), (_pc->phy_id), (_addr), (_value))) 241 242 243 #define BSDK_PHY84728_IO_MDIO_READ(_phy_ctrl, _addr, _val) \ 244 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 245 246 #define BSDK_PHY84728_IO_MDIO_WRITE(_phy_ctrl, _addr, _val) \ 247 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 248 249 /* General - PHY register access */ 250 #define BSDK_PHY84728_REG_RD(_pctrl, _flags, _reg_bank, _reg_addr, _val) \ 251 bsdk_phy84728_reg_read((_pctrl), (_flags), (_reg_bank), \ 252 (_reg_addr), (_val)) 253 254 #define BSDK_PHY84728_REG_WR(_pctrl, _flags, _reg_bank, _reg_addr, _val) \ 255 bsdk_phy84728_reg_write((_pctrl), (_flags), (_reg_bank), \ 256 (_reg_addr), (_val)) 257 258 #define BSDK_PHY84728_REG_MOD(_pctrl, _flags, _reg_bank, _reg_addr, \ 259 _val, _mask) \ 260 bsdk_phy84728_reg_modify((_pctrl), (_flags), (_reg_bank), \ 261 (_reg_addr), (_val), (_mask)) 262 263 264 /* 265 * 10G/1G : Line Side PHY registers 266 */ 267 268 /* Device 1 */ 269 /* PCS User Defined Registers */ 270 271 /* Chip Revision Resister (Addr 0xc801) */ 272 #define BSDK_RD_PHY84728_LN_DEV1_CHIP_REVr(_pctrl, _val) \ 273 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xc801, (_val)) 274 275 /* Chip ID Resister (Addr 0xc802) */ 276 #define BSDK_RD_PHY84728_LN_DEV1_CHIP_IDr(_pctrl, _val) \ 277 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xc802, (_val)) 278 279 /* Speed Link detect Status Resister (Addr 0xc81f) */ 280 #define BSDK_RD_PHY84728_LN_DEV1_SPEED_LINK_DETECT_STATr(_pctrl, _val) \ 281 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xc81f, (_val)) 282 283 /* Chip Mode Resister (Addr 0xc805) */ 284 #define BSDK_RD_PHY84728_LN_DEV1_CHIP_MODEr(_pctrl, _val) \ 285 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xc805, (_val)) 286 #define BSDK_WR_PHY84728_LN_DEV1_CHIP_MODEr(_pctrl, _val) \ 287 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0xc805, (_val)) 288 #define BSDK_MOD_PHY84728_LN_DEV1_CHIP_MODEr(_pctrl, _val, _mask)\ 289 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0xc805, \ 290 (_val), (_mask)) 291 292 /* MACSEC Bypass Control Resister (Addr 0xc8f0) */ 293 #define BSDK_RD_PHY84728_LN_DEV1_MACSEC_BYPASS_CTLRr(_pctrl, _val) \ 294 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xc8f0, (_val)) 295 #define BSDK_WR_PHY84728_LN_DEV1_MACSEC_BYPASS_CTLRr(_pctrl, _val) \ 296 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0xc8f0, (_val)) 297 #define BSDK_MOD_PHY84728_LN_DEV1_MACSEC_BYPASS_CTLRr(_pctrl, _val, _mask)\ 298 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0xc8f0, \ 299 (_val), (_mask)) 300 301 /* XPMD system Select Resister (Addr 0xc8f1) */ 302 #define BSDK_RD_PHY84728_LN_DEV1_PMD_SYS_SELr(_pctrl, _val) \ 303 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xc8f1, (_val)) 304 #define BSDK_WR_PHY84728_LN_DEV1_PMD_SYS_SELr(_pctrl, _val) \ 305 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0xc8f1, (_val)) 306 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_SYS_SELr(_pctrl, _val, _mask) \ 307 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0xc8f1, \ 308 (_val), (_mask)) 309 310 311 312 /* PMD Standard Registers */ 313 314 /* PMD Control Resister (Addr 0x0000) */ 315 #define BSDK_RD_PHY84728_LN_DEV1_PMD_CTRLr(_pctrl, _val) \ 316 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0000, (_val)) 317 #define BSDK_WR_PHY84728_LN_DEV1_PMD_CTRLr(_pctrl, _val) \ 318 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0000, (_val)) 319 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_CTRLr(_pctrl, _val, _mask) \ 320 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0000, \ 321 (_val), (_mask)) 322 323 /* PMD Status Resister (Addr 0x0001) */ 324 #define BSDK_RD_PHY84728_LN_DEV1_PMD_STATr(_pctrl, _val) \ 325 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0001, (_val)) 326 #define BSDK_WR_PHY84728_LN_DEV1_PMD_STATr(_pctrl, _val) \ 327 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0001, (_val)) 328 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_STATr(_pctrl, _val, _mask) \ 329 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0001, \ 330 (_val), (_mask)) 331 332 /* PMD ID0 Resister (Addr 0x0002) */ 333 #define BSDK_RD_PHY84728_LN_DEV1_PMD_ID0r(_pctrl, _val) \ 334 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0002, (_val)) 335 #define BSDK_WR_PHY84728_LN_DEV1_PMD_ID0r(_pctrl, _val) \ 336 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0002, (_val)) 337 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_ID0r(_pctrl, _val, _mask) \ 338 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0002, \ 339 (_val), (_mask)) 340 /* PMD ID1 Resister (Addr 0x0003) */ 341 #define BSDK_RD_PHY84728_LN_DEV1_PMD_ID1r(_pctrl, _val) \ 342 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0003, (_val)) 343 #define BSDK_WR_PHY84728_LN_DEV1_PMD_ID1r(_pctrl, _val) \ 344 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0003, (_val)) 345 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_ID1r(_pctrl, _val, _mask) \ 346 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0003, \ 347 (_val), (_mask)) 348 349 /* PMD Speed Ability Resister (Addr 0x0004) */ 350 #define BSDK_RD_PHY84728_LN_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val) \ 351 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0004, (_val)) 352 #define BSDK_WR_PHY84728_LN_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val) \ 353 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0004, (_val)) 354 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val, _mask) \ 355 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0004, \ 356 (_val), (_mask)) 357 358 /* PMD Devices in Package1 Resister (Addr 0x0005) */ 359 #define BSDK_RD_PHY84728_LN_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val) \ 360 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0005, (_val)) 361 #define BSDK_WR_PHY84728_LN_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val) \ 362 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0005, (_val)) 363 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 364 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0005, \ 365 (_val), (_mask)) 366 367 /* PMD Devices in Package2 Resister (Addr 0x0006) */ 368 #define BSDK_RD_PHY84728_LN_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val) \ 369 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0006, (_val)) 370 #define BSDK_WR_PHY84728_LN_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val) \ 371 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0006, (_val)) 372 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 373 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0006, \ 374 (_val), (_mask)) 375 376 /* PMD Control2 Resister (Addr 0x0007) */ 377 #define BSDK_RD_PHY84728_LN_DEV1_PMD_CTRL2r(_pctrl, _val) \ 378 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0007, (_val)) 379 #define BSDK_WR_PHY84728_LN_DEV1_PMD_CTRL2r(_pctrl, _val) \ 380 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0007, (_val)) 381 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_CTRL2r(_pctrl, _val, _mask) \ 382 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0007, \ 383 (_val), (_mask)) 384 385 /* PMD Status2 Resister (Addr 0x0008) */ 386 #define BSDK_RD_PHY84728_LN_DEV1_PMD_STAT2r(_pctrl, _val) \ 387 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0008, (_val)) 388 #define BSDK_WR_PHY84728_LN_DEV1_PMD_STAT2r(_pctrl, _val) \ 389 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0008, (_val)) 390 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_STAT2r(_pctrl, _val, _mask) \ 391 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0008, \ 392 (_val), (_mask)) 393 394 /* PMD Transmit Disable Resister (Addr 0x0009) */ 395 #define BSDK_RD_PHY84728_LN_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val) \ 396 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x0009, (_val)) 397 #define BSDK_WR_PHY84728_LN_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val) \ 398 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x0009, (_val)) 399 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val, _mask) \ 400 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x0009, \ 401 (_val), (_mask)) 402 403 /* PMD Receive Signal Detect Resister (Addr 0x000a) */ 404 #define BSDK_RD_PHY84728_LN_DEV1_PMD_RX_SDr(_pctrl, _val) \ 405 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x000a, (_val)) 406 #define BSDK_WR_PHY84728_LN_DEV1_PMD_RX_SDr(_pctrl, _val) \ 407 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x000a, (_val)) 408 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_RX_SDr(_pctrl, _val, _mask) \ 409 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x000a, \ 410 (_val), (_mask)) 411 412 /* PMD Extended Ability Resister (Addr 0x000b) */ 413 #define BSDK_RD_PHY84728_LN_DEV1_PMD_EXT_ABILITYr(_pctrl, _val) \ 414 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x000b, (_val)) 415 #define BSDK_WR_PHY84728_LN_DEV1_PMD_EXT_ABILITYr(_pctrl, _val) \ 416 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x000b, (_val)) 417 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_EXT_ABILITYr(_pctrl, _val, _mask) \ 418 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x000b, \ 419 (_val), (_mask)) 420 421 /* PMD OUI ID0 Resister (Addr 0x000e) */ 422 #define BSDK_RD_PHY84728_LN_DEV1_PMD_OUI_ID0r(_pctrl, _val) \ 423 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x000e, (_val)) 424 #define BSDK_WR_PHY84728_LN_DEV1_PMD_OUI_ID0r(_pctrl, _val) \ 425 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x000e, (_val)) 426 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_OUI_ID0r(_pctrl, _val, _mask) \ 427 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x000e, \ 428 (_val), (_mask)) 429 /* PMD OUI ID1 Resister (Addr 0x000e) */ 430 #define BSDK_RD_PHY84728_LN_DEV1_PMD_OUI_ID1r(_pctrl, _val) \ 431 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x000f, (_val)) 432 #define BSDK_WR_PHY84728_LN_DEV1_PMD_OUI_ID1r(_pctrl, _val) \ 433 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x000f, (_val)) 434 #define BSDK_MOD_PHY84728_LN_DEV1_PMD_OUI_ID1r(_pctrl, _val, _mask) \ 435 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x000f, \ 436 (_val), (_mask)) 437 438 439 440 /* 441 * Device 3 registers 442 */ 443 /* PCS Registers */ 444 445 /* PCS Control Resister (Addr 0x0000) */ 446 #define BSDK_RD_PHY84728_LN_DEV3_PCS_CTRLr(_pctrl, _val) \ 447 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0000, (_val)) 448 #define BSDK_WR_PHY84728_LN_DEV3_PCS_CTRLr(_pctrl, _val) \ 449 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0000, (_val)) 450 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_CTRLr(_pctrl, _val, _mask) \ 451 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0000, \ 452 (_val), (_mask)) 453 454 /* PCS Status Resister (Addr 0x0001) */ 455 #define BSDK_RD_PHY84728_LN_DEV3_PCS_STATr(_pctrl, _val) \ 456 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0001, (_val)) 457 #define BSDK_WR_PHY84728_LN_DEV3_PCS_STATr(_pctrl, _val) \ 458 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0001, (_val)) 459 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_STATr(_pctrl, _val, _mask) \ 460 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0001, \ 461 (_val), (_mask)) 462 463 /* PCS ID0 Resister (Addr 0x0002) */ 464 #define BSDK_RD_PHY84728_LN_DEV3_PCS_ID0r(_pctrl, _val) \ 465 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0002, (_val)) 466 #define BSDK_WR_PHY84728_LN_DEV3_PCS_ID0r(_pctrl, _val) \ 467 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0002, (_val)) 468 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_ID0r(_pctrl, _val, _mask) \ 469 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0002, \ 470 (_val), (_mask)) 471 /* PCS ID1 Resister (Addr 0x0003) */ 472 #define BSDK_RD_PHY84728_LN_DEV3_PCS_ID1r(_pctrl, _val) \ 473 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0003, (_val)) 474 #define BSDK_WR_PHY84728_LN_DEV3_PCS_ID1r(_pctrl, _val) \ 475 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0003, (_val)) 476 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_ID1r(_pctrl, _val, _mask) \ 477 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0003, \ 478 (_val), (_mask)) 479 480 /* PCS Speed Ability Resister (Addr 0x0004) */ 481 #define BSDK_RD_PHY84728_LN_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val) \ 482 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0004, (_val)) 483 #define BSDK_WR_PHY84728_LN_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val) \ 484 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0004, (_val)) 485 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val, _mask) \ 486 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0004, \ 487 (_val), (_mask)) 488 489 /* PCS Devices in Package1 Resister (Addr 0x0005) */ 490 #define BSDK_RD_PHY84728_LN_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val) \ 491 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0005, (_val)) 492 #define BSDK_WR_PHY84728_LN_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val) \ 493 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0005, (_val)) 494 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 495 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0005, \ 496 (_val), (_mask)) 497 498 /* PCS Devices in Package2 Resister (Addr 0x0006) */ 499 #define BSDK_RD_PHY84728_LN_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val) \ 500 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0006, (_val)) 501 #define BSDK_WR_PHY84728_LN_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val) \ 502 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0006, (_val)) 503 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 504 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0006, \ 505 (_val), (_mask)) 506 507 /* PCS Control2 Resister (Addr 0x0007) */ 508 #define BSDK_RD_PHY84728_LN_DEV3_PCS_CTRL2r(_pctrl, _val) \ 509 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0007, (_val)) 510 #define BSDK_WR_PHY84728_LN_DEV3_PCS_CTRL2r(_pctrl, _val) \ 511 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0007, (_val)) 512 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_CTRL2r(_pctrl, _val, _mask) \ 513 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0007, \ 514 (_val), (_mask)) 515 516 /* PCS Status2 Resister (Addr 0x0008) */ 517 #define BSDK_RD_PHY84728_LN_DEV3_PCS_STAT2r(_pctrl, _val) \ 518 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0008, (_val)) 519 #define BSDK_WR_PHY84728_LN_DEV3_PCS_STAT2r(_pctrl, _val) \ 520 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0008, (_val)) 521 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_STAT2r(_pctrl, _val, _mask) \ 522 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0008, \ 523 (_val), (_mask)) 524 525 /* PCS TenGBASE-X Status Register Resister (Addr 0x0018) */ 526 #define BSDK_RD_PHY84728_LN_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val) \ 527 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0018, (_val)) 528 #define BSDK_WR_PHY84728_LN_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val) \ 529 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0018, (_val)) 530 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val, _mask) \ 531 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0018, \ 532 (_val), (_mask)) 533 534 /* PCS TenGBASE-R Status Register Resister (Addr 0x0020) */ 535 #define BSDK_RD_PHY84728_LN_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val) \ 536 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, 0x0020, (_val)) 537 #define BSDK_WR_PHY84728_LN_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val) \ 538 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, 0x0020, (_val)) 539 #define BSDK_MOD_PHY84728_LN_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val, _mask) \ 540 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, 0x0020, \ 541 (_val), (_mask)) 542 543 544 /* 545 * Device 7 Registers 546 */ 547 548 /* AN User Defined registers */ 549 550 /* XGXS control Register */ 551 #define BSDK_RD_PHY84728_LN_DEV7_XGXS_CTRLr(_pctrl, _val) \ 552 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x7, 0x8000, (_val)) 553 #define BSDK_WR_PHY84728_LN_DEV7_XGXS_CTRLr(_pctrl, _val) \ 554 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x7, 0x8000, (_val)) 555 #define BSDK_MOD_PHY84728_LN_DEV7_XGXS_CTRLr(_pctrl, _val, _mask) \ 556 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x7, 0x8000, \ 557 (_val), (_mask)) 558 559 /* 1000X Control1 Register */ 560 #define BSDK_RD_PHY84728_LN_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 561 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x8300, (_val)) 562 #define BSDK_WR_PHY84728_LN_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 563 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x8300, (_val)) 564 #define BSDK_MOD_PHY84728_LN_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val, _mask) \ 565 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x8300, \ 566 (_val), (_mask)) 567 568 /* 1000X Control2 Register */ 569 #define BSDK_RD_PHY84728_LN_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val) \ 570 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x8301, (_val)) 571 #define BSDK_WR_PHY84728_LN_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val) \ 572 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x8301, (_val)) 573 #define BSDK_MOD_PHY84728_LN_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val, _mask) \ 574 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x8301, \ 575 (_val), (_mask)) 576 577 /* 1000X Control3 Register */ 578 #define BSDK_RD_PHY84728_LN_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val) \ 579 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x8302, (_val)) 580 #define BSDK_WR_PHY84728_LN_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val) \ 581 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x8302, (_val)) 582 #define BSDK_MOD_PHY84728_LN_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val, _mask) \ 583 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x8302, \ 584 (_val), (_mask)) 585 586 /* 1000X Control4 Register */ 587 #define BSDK_RD_PHY84728_LN_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val) \ 588 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x8303, (_val)) 589 #define BSDK_WR_PHY84728_LN_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val) \ 590 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x8303, (_val)) 591 #define BSDK_MOD_PHY84728_LN_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val, _mask) \ 592 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x8303, \ 593 (_val), (_mask)) 594 595 /* 1000X Status1 Register */ 596 #define BSDK_RD_PHY84728_LN_DEV7_AN_BASE1000X_STAT1r(_pctrl, _val) \ 597 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x8304, (_val)) 598 599 /* 1000X Status2 Register */ 600 #define BSDK_RD_PHY84728_LN_DEV7_AN_BASE1000X_STAT2r(_pctrl, _val) \ 601 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x8305, (_val)) 602 603 /* MISC1 Register */ 604 #define BSDK_RD_PHY84728_LN_DEV7_AN_MISC1r(_pctrl, _val) \ 605 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x8308, (_val)) 606 #define BSDK_WR_PHY84728_LN_DEV7_AN_MISC1r(_pctrl, _val) \ 607 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x8308, (_val)) 608 #define BSDK_MOD_PHY84728_LN_DEV7_AN_MISC1r(_pctrl, _val, _mask) \ 609 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x8308, \ 610 (_val), (_mask)) 611 612 /* MISC2 Register */ 613 #define BSDK_RD_PHY84728_LN_DEV7_AN_MSIC2r(_pctrl, _val) \ 614 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x8309, (_val)) 615 #define BSDK_WR_PHY84728_LN_DEV7_AN_MSIC2r(_pctrl, _val) \ 616 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x8309, (_val)) 617 #define BSDK_MOD_PHY84728_LN_DEV7_AN_MSIC2r(_pctrl, _val, _mask) \ 618 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x8309, \ 619 (_val), (_mask)) 620 621 /* SGMII BASEPAGE Register */ 622 #define BSDK_RD_PHY84728_LN_DEV7_AN_SGMII_BASEPAGEr(_pctrl, _val) \ 623 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x835c, (_val)) 624 #define BSDK_WR_PHY84728_LN_DEV7_AN_SGMII_BASEPAGEr(_pctrl, _val) \ 625 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x835c, (_val)) 626 #define BSDK_MOD_PHY84728_LN_DEV7_AN_SGMII_BASEPAGEr(_pctrl, _val, _mask) \ 627 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x835c, \ 628 (_val), (_mask)) 629 630 631 /* MII Control Register */ 632 633 /* MII Control Register */ 634 #define BSDK_RD_PHY84728_LN_DEV7_AN_MII_CTRLr(_pctrl, _val) \ 635 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0xffe0, (_val)) 636 #define BSDK_WR_PHY84728_LN_DEV7_AN_MII_CTRLr(_pctrl, _val) \ 637 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0xffe0, (_val)) 638 #define BSDK_MOD_PHY84728_LN_DEV7_AN_MII_CTRLr(_pctrl, _val, _mask) \ 639 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe0, \ 640 (_val), (_mask)) 641 642 /* MII Status Register */ 643 #define BSDK_RD_PHY84728_LN_DEV7_AN_MII_STATr(_pctrl, _val) \ 644 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0xffe1, (_val)) 645 #define BSDK_WR_PHY84728_LN_DEV7_AN_MII_STATr(_pctrl, _val) \ 646 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0xffe1, (_val)) 647 #define BSDK_MOD_PHY84728_LN_DEV7_AN_MII_STATr(_pctrl, _val, _mask) \ 648 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe1, \ 649 (_val), (_mask)) 650 651 /* AutoNeg Adv Register */ 652 #define BSDK_RD_PHY84728_LN_DEV7_AN_ANAr(_pctrl, _val) \ 653 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0xffe4, (_val)) 654 #define BSDK_WR_PHY84728_LN_DEV7_AN_ANAr(_pctrl, _val) \ 655 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0xffe4, (_val)) 656 #define BSDK_MOD_PHY84728_LN_DEV7_AN_ANAr(_pctrl, _val, _mask) \ 657 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe4, \ 658 (_val), (_mask)) 659 /* Auto Neg Link Partner Register */ 660 #define BSDK_RD_PHY84728_LN_DEV7_AN_ANPr(_pctrl, _val) \ 661 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0xffe5, (_val)) 662 #define BSDK_WR_PHY84728_LN_DEV7_AN_ANPr(_pctrl, _val) \ 663 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0xffe5, (_val)) 664 #define BSDK_MOD_PHY84728_LN_DEV7_AN_ANPr(_pctrl, _val, _mask) \ 665 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe5, \ 666 (_val), (_mask)) 667 668 /* Auto Neg Expansion Register */ 669 #define BSDK_RD_PHY84728_LN_DEV7_AN_EXRr(_pctrl, _val) \ 670 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0xffe6, (_val)) 671 #define BSDK_WR_PHY84728_LN_DEV7_AN_EXRr(_pctrl, _val) \ 672 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0xffe6, (_val)) 673 #define BSDK_MOD_PHY84728_LN_DEV7_AN_EXRr(_pctrl, _val, _mask) \ 674 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe6, \ 675 (_val), (_mask)) 676 677 /* Auto Neg Next Page Register */ 678 #define BSDK_RD_PHY84728_LN_DEV7_AN_NEXT_PAGEr(_pctrl, _val) \ 679 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0xffe7, (_val)) 680 #define BSDK_WR_PHY84728_LN_DEV7_AN_NEXT_PAGEr(_pctrl, _val) \ 681 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0xffe7, (_val)) 682 #define BSDK_MOD_PHY84728_LN_DEV7_AN_NEXT_PAGEr(_pctrl, _val, _mask) \ 683 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe7, \ 684 (_val), (_mask)) 685 686 /* Auto Neg Link Partner Ability 2 Register */ 687 #define BSDK_RD_PHY84728_LN_DEV7_AN_ANP2r(_pctrl, _val) \ 688 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0xffe8, (_val)) 689 #define BSDK_WR_PHY84728_LN_DEV7_AN_ANP2r(_pctrl, _val) \ 690 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0xffe8, (_val)) 691 #define BSDK_MOD_PHY84728_LN_DEV7_AN_ANP2r(_pctrl, _val, _mask) \ 692 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0xffe8, \ 693 (_val), (_mask)) 694 695 /* Extended Status 2 Register */ 696 #define BSDK_RD_PHY84728_LN_DEV7_ESPr(_pctrl, _val) \ 697 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0xffef, (_val)) 698 #define BSDK_WR_PHY84728_LN_DEV7_ESPr(_pctrl, _val) \ 699 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0xffef, (_val)) 700 #define BSDK_MOD_PHY84728_LN_DEV7_ESPr(_pctrl, _val, _mask) \ 701 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0xffef, \ 702 (_val), (_mask)) 703 704 705 /* AN Standard registers */ 706 707 /* AN Control Resister (Addr 0x0000) */ 708 #define BSDK_RD_PHY84728_LN_DEV7_AN_CTRLr(_pctrl, _val) \ 709 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0000, (_val)) 710 #define BSDK_WR_PHY84728_LN_DEV7_AN_CTRLr(_pctrl, _val) \ 711 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0000, (_val)) 712 #define BSDK_MOD_PHY84728_LN_DEV7_AN_CTRLr(_pctrl, _val, _mask) \ 713 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0000, \ 714 (_val), (_mask)) 715 716 /* AN Status Resister (Addr 0x0001) */ 717 #define BSDK_RD_PHY84728_LN_DEV7_AN_STATr(_pctrl, _val) \ 718 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0001, (_val)) 719 #define BSDK_WR_PHY84728_LN_DEV7_AN_STATr(_pctrl, _val) \ 720 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0001, (_val)) 721 #define BSDK_MOD_PHY84728_LN_DEV7_AN_STATr(_pctrl, _val, _mask) \ 722 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0001, \ 723 (_val), (_mask)) 724 725 /* AN ID0 Resister (Addr 0x0002) */ 726 #define BSDK_RD_PHY84728_LN_DEV7_AN_ID0r(_pctrl, _val) \ 727 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0002, (_val)) 728 #define BSDK_WR_PHY84728_LN_DEV7_AN_ID0r(_pctrl, _val) \ 729 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0002, (_val)) 730 #define BSDK_MOD_PHY84728_LN_DEV7_AN_ID0r(_pctrl, _val, _mask) \ 731 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0002, \ 732 (_val), (_mask)) 733 /* AN ID1 Resister (Addr 0x0003) */ 734 #define BSDK_RD_PHY84728_LN_DEV7_AN_ID1r(_pctrl, _val) \ 735 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0003, (_val)) 736 #define BSDK_WR_PHY84728_LN_DEV7_AN_ID1r(_pctrl, _val) \ 737 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0003, (_val)) 738 #define BSDK_MOD_PHY84728_LN_DEV7_AN_ID1r(_pctrl, _val, _mask) \ 739 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0003, \ 740 (_val), (_mask)) 741 742 /* AN Speed Ability Resister (Addr 0x0004) */ 743 #define BSDK_RD_PHY84728_LN_DEV7_AN_SPEED_ABILITYr(_pctrl, _val) \ 744 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0004, (_val)) 745 #define BSDK_WR_PHY84728_LN_DEV7_AN_SPEED_ABILITYr(_pctrl, _val) \ 746 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0004, (_val)) 747 #define BSDK_MOD_PHY84728_LN_DEV7_AN_SPEED_ABILITYr(_pctrl, _val, _mask) \ 748 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0004, \ 749 (_val), (_mask)) 750 751 /* AN Devices in Package1 Resister (Addr 0x0005) */ 752 #define BSDK_RD_PHY84728_LN_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val) \ 753 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0005, (_val)) 754 #define BSDK_WR_PHY84728_LN_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val) \ 755 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0005, (_val)) 756 #define BSDK_MOD_PHY84728_LN_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 757 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0005, \ 758 (_val), (_mask)) 759 760 /* AN Devices in Package2 Resister (Addr 0x0006) */ 761 #define BSDK_RD_PHY84728_LN_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val) \ 762 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0006, (_val)) 763 #define BSDK_WR_PHY84728_LN_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val) \ 764 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0006, (_val)) 765 #define BSDK_MOD_PHY84728_LN_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 766 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0006, \ 767 (_val), (_mask)) 768 769 /* AN Advertisement 1 Resister (Addr 0x0010) */ 770 #define BSDK_RD_PHY84728_LN_DEV7_AN_ADV1r(_pctrl, _val) \ 771 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0010, (_val)) 772 #define BSDK_WR_PHY84728_LN_DEV7_AN_ADV1r(_pctrl, _val) \ 773 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0010, (_val)) 774 #define BSDK_MOD_PHY84728_LN_DEV7_AN_ADV1r(_pctrl, _val, _mask) \ 775 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0010, \ 776 (_val), (_mask)) 777 778 /* AN Advertisement 2 Resister (Addr 0x0011) */ 779 #define BSDK_RD_PHY84728_LN_DEV7_AN_ADV2r(_pctrl, _val) \ 780 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0011, (_val)) 781 #define BSDK_WR_PHY84728_LN_DEV7_AN_ADV2r(_pctrl, _val) \ 782 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0011, (_val)) 783 #define BSDK_MOD_PHY84728_LN_DEV7_AN_ADV2r(_pctrl, _val, _mask) \ 784 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0011, \ 785 (_val), (_mask)) 786 787 /* AN Advertisement 3 Resister (Addr 0x0012) */ 788 #define BSDK_RD_PHY84728_LN_DEV7_AN_ADV3r(_pctrl, _val) \ 789 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, 0x0012, (_val)) 790 #define BSDK_WR_PHY84728_LN_DEV7_AN_ADV3r(_pctrl, _val) \ 791 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, 0x0012, (_val)) 792 #define BSDK_MOD_PHY84728_LN_DEV7_AN_ADV3r(_pctrl, _val, _mask) \ 793 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, 0x0012, \ 794 (_val), (_mask)) 795 796 #define BSDK_RD_PHY84728_LN_DEV1_PMDr(_pctrl, _reg, _val) \ 797 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, (_reg), (_val)) 798 #define BSDK_WR_PHY84728_LN_DEV1_PMDr(_pctrl, _reg, _val) \ 799 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, (_reg), (_val)) 800 #define BSDK_MOD_PHY84728_LN_DEV1_PMDr(_pctrl, _reg, _val, _mask) \ 801 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, (_reg), \ 802 (_val), (_mask)) 803 804 #define BSDK_RD_PHY84728_LN_DEV3_PCSr(_pctrl, _reg, _val) \ 805 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0003, (_reg), (_val)) 806 #define BSDK_WR_PHY84728_LN_DEV3_PCSr(_pctrl, _reg, _val) \ 807 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0003, (_reg), (_val)) 808 #define BSDK_MOD_PHY84728_LN_DEV3_PCSr(_pctrl, _reg, _val, _mask) \ 809 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0003, (_reg), \ 810 (_val), (_mask)) 811 812 #define BSDK_RD_PHY84728_LN_DEV7_ANr(_pctrl, _reg, _val) \ 813 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0007, (_reg), (_val)) 814 #define BSDK_WR_PHY84728_LN_DEV7_ANr(_pctrl, _reg, _val) \ 815 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0007, (_reg), (_val)) 816 #define BSDK_MOD_PHY84728_LN_DEV7_ANr(_pctrl, _reg, _val, _mask) \ 817 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0007, (_reg), \ 818 (_val), (_mask)) 819 820 /* 821 * 10G/1G : System Side PHY registers 822 */ 823 824 /* Device 1 */ 825 /* PMD Control Resister (Addr 0x0000) */ 826 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_CTRLr(_pctrl, _val) \ 827 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0000, (_val)) 828 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_CTRLr(_pctrl, _val) \ 829 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0000, (_val)) 830 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_CTRLr(_pctrl, _val, _mask) \ 831 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0000, \ 832 (_val), (_mask)) 833 834 /* PMD Status Resister (Addr 0x0001) */ 835 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_STATr(_pctrl, _val) \ 836 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0001, (_val)) 837 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_STATr(_pctrl, _val) \ 838 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0001, (_val)) 839 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_STATr(_pctrl, _val, _mask) \ 840 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0001, \ 841 (_val), (_mask)) 842 843 /* PMD ID0 Resister (Addr 0x0002) */ 844 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_ID0r(_pctrl, _val) \ 845 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0002, (_val)) 846 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_ID0r(_pctrl, _val) \ 847 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0002, (_val)) 848 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_ID0r(_pctrl, _val, _mask) \ 849 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0002, \ 850 (_val), (_mask)) 851 /* PMD ID1 Resister (Addr 0x0003) */ 852 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_ID1r(_pctrl, _val) \ 853 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0003, (_val)) 854 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_ID1r(_pctrl, _val) \ 855 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0003, (_val)) 856 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_ID1r(_pctrl, _val, _mask) \ 857 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0003, \ 858 (_val), (_mask)) 859 860 /* PMD Speed Ability Resister (Addr 0x0004) */ 861 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val) \ 862 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0004, (_val)) 863 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val) \ 864 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0004, (_val)) 865 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_SPEED_ABILITYr(_pctrl, _val, _mask) \ 866 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0004, \ 867 (_val), (_mask)) 868 869 /* PMD Devices in Package1 Resister (Addr 0x0005) */ 870 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val) \ 871 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0005, (_val)) 872 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val) \ 873 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0005, (_val)) 874 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 875 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0005, \ 876 (_val), (_mask)) 877 878 /* PMD Devices in Package2 Resister (Addr 0x0006) */ 879 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val) \ 880 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0006, (_val)) 881 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val) \ 882 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0006, (_val)) 883 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 884 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0006, \ 885 (_val), (_mask)) 886 887 /* PMD Control 2 Resister (Addr 0x0007) */ 888 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_CTRL2r(_pctrl, _val) \ 889 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0007, (_val)) 890 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_CTRL2r(_pctrl, _val) \ 891 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0007, (_val)) 892 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_CTRL2r(_pctrl, _val, _mask) \ 893 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0007, \ 894 (_val), (_mask)) 895 /* PMD Status 2 Resister (Addr 0x0007) */ 896 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_STAT2r(_pctrl, _val) \ 897 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0008, (_val)) 898 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_STAT2r(_pctrl, _val) \ 899 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0008, (_val)) 900 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_STAT2r(_pctrl, _val, _mask) \ 901 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0008, \ 902 (_val), (_mask)) 903 904 /* PMD Transmit Disable Resister (Addr 0x0009) */ 905 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val) \ 906 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x0009, (_val)) 907 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val) \ 908 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x0009, (_val)) 909 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_XMIT_DISABLEr(_pctrl, _val, _mask) \ 910 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x0009, \ 911 (_val), (_mask)) 912 913 /* PMD Receive Signal Detect Resister (Addr 0x000a) */ 914 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_RX_SDr(_pctrl, _val) \ 915 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x000a, (_val)) 916 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_RX_SDr(_pctrl, _val) \ 917 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x000a, (_val)) 918 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_RX_SDr(_pctrl, _val, _mask) \ 919 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x000a, \ 920 (_val), (_mask)) 921 922 /* PMD Extended Ability Resister (Addr 0x000b) */ 923 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_EXT_ABILITYr(_pctrl, _val) \ 924 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x000b, (_val)) 925 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_EXT_ABILITYr(_pctrl, _val) \ 926 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x000b, (_val)) 927 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_EXT_ABILITYr(_pctrl, _val, _mask) \ 928 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x000b, \ 929 (_val), (_mask)) 930 931 /* PMD OUI ID0 Resister (Addr 0x000e) */ 932 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_OUI_ID0r(_pctrl, _val) \ 933 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x000e, (_val)) 934 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_OUI_ID0r(_pctrl, _val) \ 935 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x000e, (_val)) 936 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_OUI_ID0r(_pctrl, _val, _mask) \ 937 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x000e, \ 938 (_val), (_mask)) 939 /* PMD OUI ID1 Resister (Addr 0x000e) */ 940 #define BSDK_RD_PHY84728_SYS_DEV1_PMD_OUI_ID1r(_pctrl, _val) \ 941 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0x000f, (_val)) 942 #define BSDK_WR_PHY84728_SYS_DEV1_PMD_OUI_ID1r(_pctrl, _val) \ 943 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0x000f, (_val)) 944 #define BSDK_MOD_PHY84728_SYS_DEV1_PMD_OUI_ID1r(_pctrl, _val, _mask) \ 945 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0x000f, \ 946 (_val), (_mask)) 947 948 949 #define BSDK_RD_PHY84728_PMD_MISC2_CTRLr(_pctrl, _val) \ 950 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0xca08, (_val)) 951 #define BSDK_WR_PHY84728_PMD_MISC2_CTRLr(_pctrl, _val) \ 952 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0xca08, (_val)) 953 #define BSDK_MOD_PHY84728_PMD_MISC2_CTRLr(_pctrl, _val, _mask) \ 954 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0xca08, \ 955 (_val), (_mask)) 956 957 #define PMD_MISC_CTRL_WAN_MODE (1 << 0) 958 #define BSDK_RD_PHY84728_PMD_MISC_CTRLr(_pctrl, _val) \ 959 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0xc812, (_val)) 960 #define BSDK_WR_PHY84728_PMD_MISC_CTRLr(_pctrl, _val) \ 961 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0xc812, (_val)) 962 #define BSDK_MOD_PHY84728_PMD_MISC_CTRLr(_pctrl, _val, _mask) \ 963 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0xc812, \ 964 (_val), (_mask)) 965 966 #define BSDK_RD_PHY84728_IDENTIFIERr(_pctrl, _val) \ 967 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0001, 0xc800, (_val)) 968 #define BSDK_WR_PHY84728_IDENTIFIERr(_pctrl, _val) \ 969 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0001, 0xc800, (_val)) 970 #define BSDK_MOD_PHY84728_IDENTIFIERr(_pctrl, _val, _mask) \ 971 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0001, 0xc800, \ 972 (_val), (_mask)) 973 974 /* WIS Device (Dev Addr 2) */ 975 /* Control 1 Register (Addr 0000h) */ 976 #define BSDK_PHY84728_WIS_CTRL_RESET (1 << 15) /* PHY reset */ 977 #define BSDK_RD_PHY84728_WIS_CTRLr(_pctrl, _val) \ 978 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0002, 0x0000, (_val)) 979 #define BSDK_WR_PHY84728_WIS_CTRLr(_pctrl, _val) \ 980 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0002, 0x0000, (_val)) 981 #define BSDK_MOD_PHY84728_WIS_CTRLr(_pctrl, _val, _mask) \ 982 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0002, 0x0000, \ 983 (_val), (_mask)) 984 985 /* Status 1 Register (Addr 0001h) */ 986 #define BSDK_RD_PHY84728_WIS_STATr(_pctrl, _val) \ 987 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0002, 0x0001, (_val)) 988 #define BSDK_WR_PHY84728_WIS_STATr(_pctrl, _val) \ 989 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0002, 0x0001, (_val)) 990 #define BSDK_MOD_PHY84728_WIS_STATr(_pctrl, _val, _mask) \ 991 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0002, 0x0001, \ 992 (_val), (_mask)) 993 /* ID0 Register (Addr 0002h) */ 994 /* ID1 Register (Addr 0003h) */ 995 /* Speed Ability Register (Addr 0004h) */ 996 997 /* Devices in Package 1 Register (Addr 0005h) */ 998 #define BSDK_RD_PHY84728_WIS_DEV_IN_PKGr(_pctrl, _val) \ 999 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0002, 0x0005, (_val)) 1000 #define BSDK_WR_PHY84728_WIS_DEV_IN_PKGr(_pctrl, _val) \ 1001 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0002, 0x0005, (_val)) 1002 #define BSDK_MOD_PHY84728_WIS_DEV_IN_PKGr(_pctrl, _val, _mask) \ 1003 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0002, 0x0005, \ 1004 (_val), (_mask)) 1005 1006 /* 1007 * Device 3 registers 1008 */ 1009 /* XFI PCS Registers */ 1010 1011 /* PCS Control Resister (Addr 0x0000) */ 1012 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_CTRLr(_pctrl, _val) \ 1013 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0000, (_val)) 1014 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_CTRLr(_pctrl, _val) \ 1015 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0000, (_val)) 1016 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_CTRLr(_pctrl, _val, _mask) \ 1017 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0000, \ 1018 (_val), (_mask)) 1019 1020 /* PCS Status Resister (Addr 0x0001) */ 1021 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_STATr(_pctrl, _val) \ 1022 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0001, (_val)) 1023 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_STATr(_pctrl, _val) \ 1024 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0001, (_val)) 1025 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_STATr(_pctrl, _val, _mask) \ 1026 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0001, \ 1027 (_val), (_mask)) 1028 1029 /* PCS ID0 Resister (Addr 0x0002) */ 1030 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_ID0r(_pctrl, _val) \ 1031 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0002, (_val)) 1032 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_ID0r(_pctrl, _val) \ 1033 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0002, (_val)) 1034 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_ID0r(_pctrl, _val, _mask) \ 1035 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0002, \ 1036 (_val), (_mask)) 1037 /* PCS ID1 Resister (Addr 0x0003) */ 1038 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_ID1r(_pctrl, _val) \ 1039 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0003, (_val)) 1040 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_ID1r(_pctrl, _val) \ 1041 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0003, (_val)) 1042 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_ID1r(_pctrl, _val, _mask) \ 1043 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0003, \ 1044 (_val), (_mask)) 1045 1046 /* PCS Speed Ability Resister (Addr 0x0004) */ 1047 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val) \ 1048 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0004, (_val)) 1049 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val) \ 1050 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0004, (_val)) 1051 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_SPEED_ABILITYr(_pctrl, _val, _mask) \ 1052 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0004, \ 1053 (_val), (_mask)) 1054 1055 /* PCS Devices in Package1 Resister (Addr 0x0005) */ 1056 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val) \ 1057 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0005, (_val)) 1058 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val) \ 1059 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0005, (_val)) 1060 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 1061 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0005, \ 1062 (_val), (_mask)) 1063 1064 /* PCS Devices in Package2 Resister (Addr 0x0006) */ 1065 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val) \ 1066 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0006, (_val)) 1067 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val) \ 1068 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0006, (_val)) 1069 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 1070 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0006, \ 1071 (_val), (_mask)) 1072 1073 /* PCS Control2 Resister (Addr 0x0007) */ 1074 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_CTRL2r(_pctrl, _val) \ 1075 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0007, (_val)) 1076 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_CTRL2r(_pctrl, _val) \ 1077 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0007, (_val)) 1078 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_CTRL2r(_pctrl, _val, _mask) \ 1079 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0007, \ 1080 (_val), (_mask)) 1081 1082 /* PCS Status2 Resister (Addr 0x0008) */ 1083 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_STAT2r(_pctrl, _val) \ 1084 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0008, (_val)) 1085 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_STAT2r(_pctrl, _val) \ 1086 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0008, (_val)) 1087 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_STAT2r(_pctrl, _val, _mask) \ 1088 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0008, \ 1089 (_val), (_mask)) 1090 1091 /* PCS TenGBASE-X Status Register Resister (Addr 0x0018) */ 1092 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val) \ 1093 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0018, (_val)) 1094 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val) \ 1095 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0018, (_val)) 1096 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_10GBASE_X_STATr(_pctrl, _val, _mask) \ 1097 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0018, \ 1098 (_val), (_mask)) 1099 1100 /* PCS TenGBASE-R Status Register Resister (Addr 0x0020) */ 1101 #define BSDK_RD_PHY84728_XFI_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val) \ 1102 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0003, 0x0020, (_val)) 1103 #define BSDK_WR_PHY84728_XFI_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val) \ 1104 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0003, 0x0020, (_val)) 1105 #define BSDK_MOD_PHY84728_XFI_DEV3_PCS_10GBASE_R_STATr(_pctrl, _val, _mask) \ 1106 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0003, 0x0020, \ 1107 (_val), (_mask)) 1108 1109 1110 1111 /* 1112 * Device 7 Registers 1113 */ 1114 1115 /* AN User Defined registers */ 1116 1117 /* 1000X Control1 Register */ 1118 #define BSDK_RD_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 1119 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x8300, (_val)) 1120 #define BSDK_WR_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val) \ 1121 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x8300, (_val)) 1122 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL1r(_pctrl, _val, _mask) \ 1123 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x8300, \ 1124 (_val), (_mask)) 1125 1126 /* 1000X Control2 Register */ 1127 #define BSDK_RD_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val) \ 1128 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x8301, (_val)) 1129 #define BSDK_WR_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val) \ 1130 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x8301, (_val)) 1131 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL2r(_pctrl, _val, _mask) \ 1132 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x8301, \ 1133 (_val), (_mask)) 1134 1135 /* 1000X Control3 Register */ 1136 #define BSDK_RD_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val) \ 1137 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x8302, (_val)) 1138 #define BSDK_WR_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val) \ 1139 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x8302, (_val)) 1140 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL3r(_pctrl, _val, _mask) \ 1141 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x8302, \ 1142 (_val), (_mask)) 1143 1144 /* 1000X Control4 Register */ 1145 #define BSDK_RD_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val) \ 1146 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x8303, (_val)) 1147 #define BSDK_WR_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val) \ 1148 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x8303, (_val)) 1149 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_BASE1000X_CTRL4r(_pctrl, _val, _mask) \ 1150 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x8303, \ 1151 (_val), (_mask)) 1152 /* MISC2 Register */ 1153 #define BSDK_RD_PHY84728_XFI_DEV7_AN_MISC2r(_pctrl, _val) \ 1154 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x8309, (_val)) 1155 #define BSDK_WR_PHY84728_XFI_DEV7_AN_MISC2r(_pctrl, _val) \ 1156 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x8309, (_val)) 1157 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_MISC2r(_pctrl, _val, _mask) \ 1158 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x8309, \ 1159 (_val), (_mask)) 1160 1161 /* 1000X Status1 Register */ 1162 #define BSDK_RD_PHY84728_XFI_DEV7_AN_BASE1000X_STAT1r(_pctrl, _val) \ 1163 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x8304, (_val)) 1164 1165 /* 1000X Status2 Register */ 1166 #define BSDK_RD_PHY84728_XFI_DEV7_AN_BASE1000X_STAT2r(_pctrl, _val) \ 1167 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x8305, (_val)) 1168 1169 /* MII Control Register */ 1170 #define BSDK_RD_PHY84728_XFI_DEV7_AN_MII_CTRLr(_pctrl, _val) \ 1171 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0xffe0, (_val)) 1172 #define BSDK_WR_PHY84728_XFI_DEV7_AN_MII_CTRLr(_pctrl, _val) \ 1173 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0xffe0, (_val)) 1174 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_MII_CTRLr(_pctrl, _val, _mask) \ 1175 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe0, \ 1176 (_val), (_mask)) 1177 1178 /* MII Status Register */ 1179 #define BSDK_RD_PHY84728_XFI_DEV7_AN_MII_STATr(_pctrl, _val) \ 1180 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0xffe1, (_val)) 1181 #define BSDK_WR_PHY84728_XFI_DEV7_AN_MII_STATr(_pctrl, _val) \ 1182 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0xffe1, (_val)) 1183 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_MII_STATr(_pctrl, _val, _mask) \ 1184 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe1, \ 1185 (_val), (_mask)) 1186 1187 /* AutoNeg Adv Register */ 1188 #define BSDK_RD_PHY84728_XFI_DEV7_AN_ANAr(_pctrl, _val) \ 1189 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0xffe4, (_val)) 1190 #define BSDK_WR_PHY84728_XFI_DEV7_AN_ANAr(_pctrl, _val) \ 1191 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0xffe4, (_val)) 1192 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_ANAr(_pctrl, _val, _mask) \ 1193 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe4, \ 1194 (_val), (_mask)) 1195 /* Auto Neg Link Partner Register */ 1196 #define BSDK_RD_PHY84728_XFI_DEV7_AN_ANPr(_pctrl, _val) \ 1197 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0xffe5, (_val)) 1198 #define BSDK_WR_PHY84728_XFI_DEV7_AN_ANPr(_pctrl, _val) \ 1199 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0xffe5, (_val)) 1200 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_ANPr(_pctrl, _val, _mask) \ 1201 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe5, \ 1202 (_val), (_mask)) 1203 1204 /* Auto Neg Expansion Register */ 1205 #define BSDK_RD_PHY84728_XFI_DEV7_AN_EXRr(_pctrl, _val) \ 1206 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0xffe6, (_val)) 1207 #define BSDK_WR_PHY84728_XFI_DEV7_AN_EXRr(_pctrl, _val) \ 1208 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0xffe6, (_val)) 1209 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_EXRr(_pctrl, _val, _mask) \ 1210 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe6, \ 1211 (_val), (_mask)) 1212 1213 /* Auto Neg Next Page Register */ 1214 #define BSDK_RD_PHY84728_XFI_DEV7_AN_NEXT_PAGEr(_pctrl, _val) \ 1215 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0xffe7, (_val)) 1216 #define BSDK_WR_PHY84728_XFI_DEV7_AN_NEXT_PAGEr(_pctrl, _val) \ 1217 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0xffe7, (_val)) 1218 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_NEXT_PAGEr(_pctrl, _val, _mask) \ 1219 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe7, \ 1220 (_val), (_mask)) 1221 1222 /* Auto Neg Link Partner Ability 2 Register */ 1223 #define BSDK_RD_PHY84728_XFI_DEV7_AN_ANP2r(_pctrl, _val) \ 1224 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0xffe8, (_val)) 1225 #define BSDK_WR_PHY84728_XFI_DEV7_AN_ANP2r(_pctrl, _val) \ 1226 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0xffe8, (_val)) 1227 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_ANP2r(_pctrl, _val, _mask) \ 1228 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0xffe8, \ 1229 (_val), (_mask)) 1230 1231 /* Extended Status 2 Register */ 1232 #define BSDK_RD_PHY84728_XFI_DEV7_ESPr(_pctrl, _val) \ 1233 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0xffef, (_val)) 1234 #define BSDK_WR_PHY84728_XFI_DEV7_ESPr(_pctrl, _val) \ 1235 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0xffef, (_val)) 1236 #define BSDK_MOD_PHY84728_XFI_DEV7_ESPr(_pctrl, _val, _mask) \ 1237 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0xffef, \ 1238 (_val), (_mask)) 1239 1240 1241 /* AN Standard registers */ 1242 1243 /* AN Control Resister (Addr 0x0000) */ 1244 #define BSDK_RD_PHY84728_XFI_DEV7_AN_CTRLr(_pctrl, _val) \ 1245 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0000, (_val)) 1246 #define BSDK_WR_PHY84728_XFI_DEV7_AN_CTRLr(_pctrl, _val) \ 1247 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0000, (_val)) 1248 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_CTRLr(_pctrl, _val, _mask) \ 1249 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0000, \ 1250 (_val), (_mask)) 1251 1252 /* AN Status Resister (Addr 0x0001) */ 1253 #define BSDK_RD_PHY84728_XFI_DEV7_AN_STATr(_pctrl, _val) \ 1254 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0001, (_val)) 1255 #define BSDK_WR_PHY84728_XFI_DEV7_AN_STATr(_pctrl, _val) \ 1256 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0001, (_val)) 1257 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_STATr(_pctrl, _val, _mask) \ 1258 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0001, \ 1259 (_val), (_mask)) 1260 1261 /* AN ID0 Resister (Addr 0x0002) */ 1262 #define BSDK_RD_PHY84728_XFI_DEV7_AN_ID0r(_pctrl, _val) \ 1263 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0002, (_val)) 1264 #define BSDK_WR_PHY84728_XFI_DEV7_AN_ID0r(_pctrl, _val) \ 1265 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0002, (_val)) 1266 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_ID0r(_pctrl, _val, _mask) \ 1267 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0002, \ 1268 (_val), (_mask)) 1269 /* AN ID1 Resister (Addr 0x0003) */ 1270 #define BSDK_RD_PHY84728_XFI_DEV7_AN_ID1r(_pctrl, _val) \ 1271 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0003, (_val)) 1272 #define BSDK_WR_PHY84728_XFI_DEV7_AN_ID1r(_pctrl, _val) \ 1273 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0003, (_val)) 1274 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_ID1r(_pctrl, _val, _mask) \ 1275 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0003, \ 1276 (_val), (_mask)) 1277 1278 /* AN Speed Ability Resister (Addr 0x0004) */ 1279 #define BSDK_RD_PHY84728_XFI_DEV7_AN_SPEED_ABILITYr(_pctrl, _val) \ 1280 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0004, (_val)) 1281 #define BSDK_WR_PHY84728_XFI_DEV7_AN_SPEED_ABILITYr(_pctrl, _val) \ 1282 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0004, (_val)) 1283 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_SPEED_ABILITYr(_pctrl, _val, _mask) \ 1284 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0004, \ 1285 (_val), (_mask)) 1286 1287 /* AN Devices in Package1 Resister (Addr 0x0005) */ 1288 #define BSDK_RD_PHY84728_XFI_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val) \ 1289 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0005, (_val)) 1290 #define BSDK_WR_PHY84728_XFI_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val) \ 1291 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0005, (_val)) 1292 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_DEV_IN_PKG1r(_pctrl, _val, _mask) \ 1293 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0005, \ 1294 (_val), (_mask)) 1295 1296 /* AN Devices in Package2 Resister (Addr 0x0006) */ 1297 #define BSDK_RD_PHY84728_XFI_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val) \ 1298 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0006, (_val)) 1299 #define BSDK_WR_PHY84728_XFI_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val) \ 1300 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0006, (_val)) 1301 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_DEV_IN_PKG2r(_pctrl, _val, _mask) \ 1302 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0006, \ 1303 (_val), (_mask)) 1304 1305 /* AN Advertisement 1 Resister (Addr 0x0010) */ 1306 #define BSDK_RD_PHY84728_XFI_DEV7_AN_ADV1r(_pctrl, _val) \ 1307 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0010, (_val)) 1308 #define BSDK_WR_PHY84728_XFI_DEV7_AN_ADV1r(_pctrl, _val) \ 1309 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0010, (_val)) 1310 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_ADV1r(_pctrl, _val, _mask) \ 1311 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0010, \ 1312 (_val), (_mask)) 1313 1314 /* AN Advertisement 2 Resister (Addr 0x0011) */ 1315 #define BSDK_RD_PHY84728_XFI_DEV7_AN_ADV2r(_pctrl, _val) \ 1316 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0011, (_val)) 1317 #define BSDK_WR_PHY84728_XFI_DEV7_AN_ADV2r(_pctrl, _val) \ 1318 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0011, (_val)) 1319 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_ADV2r(_pctrl, _val, _mask) \ 1320 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0011, \ 1321 (_val), (_mask)) 1322 1323 /* AN Advertisement 3 Resister (Addr 0x0012) */ 1324 #define BSDK_RD_PHY84728_XFI_DEV7_AN_ADV3r(_pctrl, _val) \ 1325 BSDK_PHY84728_REG_RD((_pctrl), 0x01, 0x0007, 0x0012, (_val)) 1326 #define BSDK_WR_PHY84728_XFI_DEV7_AN_ADV3r(_pctrl, _val) \ 1327 BSDK_PHY84728_REG_WR((_pctrl), 0x01, 0x0007, 0x0012, (_val)) 1328 #define BSDK_MOD_PHY84728_XFI_DEV7_AN_ADV3r(_pctrl, _val, _mask) \ 1329 BSDK_PHY84728_REG_MOD((_pctrl), 0x01, 0x0007, 0x0012, \ 1330 (_val), (_mask)) 1331 1332 1333 /* System side DEV4 XGXS registers */ 1334 1335 1336 /* 1000X Control1 Register */ 1337 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL1r(_pctrl, _val) \ 1338 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x8300, (_val)) 1339 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL1r(_pctrl, _val) \ 1340 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0x8300, (_val)) 1341 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL1r(_pctrl, _val, _mask) \ 1342 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0x8300, \ 1343 (_val), (_mask)) 1344 1345 /* 1000X Control2 Register */ 1346 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL2r(_pctrl, _val) \ 1347 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x8301, (_val)) 1348 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL2r(_pctrl, _val) \ 1349 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0x8301, (_val)) 1350 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL2r(_pctrl, _val, _mask) \ 1351 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0x8301, \ 1352 (_val), (_mask)) 1353 1354 /* 1000X Control3 Register */ 1355 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL3r(_pctrl, _val) \ 1356 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x8302, (_val)) 1357 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL3r(_pctrl, _val) \ 1358 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0x8302, (_val)) 1359 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL3r(_pctrl, _val, _mask) \ 1360 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0x8302, \ 1361 (_val), (_mask)) 1362 1363 /* 1000X Control4 Register */ 1364 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL4r(_pctrl, _val) \ 1365 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x8303, (_val)) 1366 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL4r(_pctrl, _val) \ 1367 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0x8303, (_val)) 1368 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_BASE1000X_CTRL4r(_pctrl, _val, _mask) \ 1369 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0x8303, \ 1370 (_val), (_mask)) 1371 /* 1000X Status1 Register */ 1372 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_BASE1000X_STAT1r(_pctrl, _val) \ 1373 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x8304, (_val)) 1374 1375 /* 1000X Status2 Register */ 1376 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_BASE1000X_STAT2r(_pctrl, _val) \ 1377 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x8305, (_val)) 1378 1379 /* MISC1 Register */ 1380 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_MISC1r(_pctrl, _val) \ 1381 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x8308, (_val)) 1382 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_MISC1r(_pctrl, _val) \ 1383 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0x8308, (_val)) 1384 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_MISC1r(_pctrl, _val, _mask) \ 1385 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0x8308, \ 1386 (_val), (_mask)) 1387 1388 /* MISC2 Register */ 1389 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_MISC2r(_pctrl, _val) \ 1390 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x8309, (_val)) 1391 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_MISC2r(_pctrl, _val) \ 1392 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0x8309, (_val)) 1393 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_MISC2r(_pctrl, _val, _mask) \ 1394 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0x8309, \ 1395 (_val), (_mask)) 1396 1397 /* SGMII BASEPAGE Register */ 1398 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_SGMII_BASEPAGEr(_pctrl, _val) \ 1399 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x835c, (_val)) 1400 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_SGMII_BASEPAGEr(_pctrl, _val) \ 1401 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0x835c, (_val)) 1402 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_SGMII_BASEPAGEr(_pctrl, _val, _mask) \ 1403 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0x835c, \ 1404 (_val), (_mask)) 1405 1406 /* XGXS Status1 Register */ 1407 #define BSDK_RD_PHY84728_SYS_DEV4_XGXSSTATUS1r(_pctrl, _val) \ 1408 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x0001, (_val)) 1409 1410 /* MII Control Register */ 1411 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_MII_CTRLr(_pctrl, _val) \ 1412 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0xffe0, (_val)) 1413 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_MII_CTRLr(_pctrl, _val) \ 1414 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0xffe0, (_val)) 1415 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_MII_CTRLr(_pctrl, _val, _mask) \ 1416 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0xffe0, \ 1417 (_val), (_mask)) 1418 1419 /* MII Status Register */ 1420 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_MII_STATr(_pctrl, _val) \ 1421 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0xffe1, (_val)) 1422 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_MII_STATr(_pctrl, _val) \ 1423 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0xffe1, (_val)) 1424 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_MII_STATr(_pctrl, _val, _mask) \ 1425 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0xffe1, \ 1426 (_val), (_mask)) 1427 1428 /* AutoNeg Adv Register */ 1429 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_ANAr(_pctrl, _val) \ 1430 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0xffe4, (_val)) 1431 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_ANAr(_pctrl, _val) \ 1432 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0xffe4, (_val)) 1433 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_ANAr(_pctrl, _val, _mask) \ 1434 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0xffe4, \ 1435 (_val), (_mask)) 1436 /* Auto Neg Link Partner Register */ 1437 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_ANPr(_pctrl, _val) \ 1438 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0xffe5, (_val)) 1439 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_ANPr(_pctrl, _val) \ 1440 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0xffe5, (_val)) 1441 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_ANPr(_pctrl, _val, _mask) \ 1442 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0xffe5, \ 1443 (_val), (_mask)) 1444 1445 /* Auto Neg Expansion Register */ 1446 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_EXRr(_pctrl, _val) \ 1447 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0xffe6, (_val)) 1448 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_EXRr(_pctrl, _val) \ 1449 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0xffe6, (_val)) 1450 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_EXRr(_pctrl, _val, _mask) \ 1451 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0xffe6, \ 1452 (_val), (_mask)) 1453 1454 /* Auto Neg Next Page Register */ 1455 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_NEXT_PAGEr(_pctrl, _val) \ 1456 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0xffe7, (_val)) 1457 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_NEXT_PAGEr(_pctrl, _val) \ 1458 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0xffe7, (_val)) 1459 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_NEXT_PAGEr(_pctrl, _val, _mask) \ 1460 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0xffe7, \ 1461 (_val), (_mask)) 1462 1463 /* Auto Neg Link Partner Ability 2 Register */ 1464 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_ANP2r(_pctrl, _val) \ 1465 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0xffe8, (_val)) 1466 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_ANP2r(_pctrl, _val) \ 1467 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0xffe8, (_val)) 1468 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_ANP2r(_pctrl, _val, _mask) \ 1469 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0xffe8, \ 1470 (_val), (_mask)) 1471 1472 /* Extended Status 2 Register */ 1473 #define BSDK_RD_PHY84728_XGXS_DEV4_ESPr(_pctrl, _val) \ 1474 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0xffef, (_val)) 1475 #define BSDK_WR_PHY84728_XGXS_DEV4_ESPr(_pctrl, _val) \ 1476 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0xffef, (_val)) 1477 #define BSDK_MOD_PHY84728_XGXS_DEV4_ESPr(_pctrl, _val, _mask) \ 1478 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0xffef, \ 1479 (_val), (_mask)) 1480 1481 1482 /* 1483 * Firmware Download related registers 1484 */ 1485 1486 /* M8051 Message IN Resister (Addr 0xCA12) */ 1487 #define BSDK_RD_PHY84728_LN_DEV1_M8501_MSGINr(_pctrl, _val) \ 1488 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xCA12, (_val)) 1489 #define BSDK_WR_PHY84728_LN_DEV1_M8501_MSGINr(_pctrl, _val) \ 1490 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0xCA12, (_val)) 1491 #define BSDK_MOD_PHY84728_LN_DEV1_M8501_MSGINr(_pctrl, _val, _mask) \ 1492 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0xCA12, \ 1493 (_val), (_mask)) 1494 1495 /* M8051 Message OUT Resister (Addr 0xCA13) */ 1496 #define BSDK_RD_PHY84728_LN_DEV1_M8501_MSGOUTr(_pctrl, _val) \ 1497 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xCA13, (_val)) 1498 #define BSDK_WR_PHY84728_LN_DEV1_M8501_MSGOUTr(_pctrl, _val) \ 1499 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0xCA13, (_val)) 1500 #define BSDK_MOD_PHY84728_LN_DEV1_M8501_MSGOUTr(_pctrl, _val, _mask) \ 1501 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0xCA13, \ 1502 (_val), (_mask)) 1503 1504 /* RX Alarm Resister (Addr 0x9003) */ 1505 #define BSDK_RD_PHY84728_LN_DEV1_RX_ALARMr(_pctrl, _val) \ 1506 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x9003, (_val)) 1507 #define BSDK_WR_PHY84728_LN_DEV1_RX_ALARMr(_pctrl, _val) \ 1508 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x9003, (_val)) 1509 #define BSDK_MOD_PHY84728_LN_DEV1_RX_ALARMr(_pctrl, _val, _mask) \ 1510 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x9003, \ 1511 (_val), (_mask)) 1512 1513 /* SPA Control and Status Resister (Addr 0xC848) */ 1514 #define BSDK_RD_PHY84728_LN_DEV1_SPI_CTRL_STATr(_pctrl, _val) \ 1515 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xC848, (_val)) 1516 #define BSDK_WR_PHY84728_LN_DEV1_SPI_CTRL_STATr(_pctrl, _val) \ 1517 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0xC848, (_val)) 1518 #define BSDK_MOD_PHY84728_LN_DEV1_SPI_CTRL_STATr(_pctrl, _val, _mask) \ 1519 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0xC848, \ 1520 (_val), (_mask)) 1521 1522 /* SPA Control and Status Resister (Addr 0xCA1C) */ 1523 #define BSDK_RD_PHY84728_LN_DEV1_CHECKSUMr(_pctrl, _val) \ 1524 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xCA1C, (_val)) 1525 1526 1527 /* SPI ROM Firmware update related */ 1528 1529 /* 1530 * SPI-ROM Program related defs 1531 */ 1532 #define BSDK_SPI_CTRL_1_L 0xC000 1533 #define BSDK_SPI_CTRL_1_H 0xC002 1534 #define BSDK_SPI_CTRL_2_L 0xC400 1535 #define BSDK_SPI_CTRL_2_H 0xC402 1536 #define BSDK_SPI_TXFIFO 0xD000 1537 #define BSDK_SPI_RXFIFO 0xD400 1538 #define BSDK_WR_CPU_CTRL_REGS 0x11 1539 #define BSDK_RD_CPU_CTRL_REGS 0xEE 1540 #define BSDK_WR_CPU_CTRL_FIFO 0x66 1541 1542 /* 1543 * SPI Controller Commands(Messages). 1544 */ 1545 #define BSDK_MSGTYPE_HWR 0x40 1546 #define BSDK_MSGTYPE_HRD 0x80 1547 #define BSDK_WRSR_OPCODE 0x01 1548 #define BSDK_WR_OPCODE 0x02 1549 #define BSDK_WRDI_OPCODE 0x04 1550 #define BSDK_RDSR_OPCODE 0x05 1551 #define BSDK_WREN_OPCODE 0x06 1552 #define BSDK_WR_BLOCK_SIZE 0x40 1553 #define BSDK_TOTAL_WR_BYTE 0x4000 1554 1555 #define BSDK_WR_TIMEOUT 100 1556 #define BSDK_WR_ITERATIONS 10000 1557 1558 1559 /* Misc Control 2 Resister(SPI ROM FW Upload control) (Addr 0xCA85) */ 1560 #define BSDK_RD_PHY84728_LN_DEV1_MISC_CNTL2r(_pctrl, _val) \ 1561 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0xCA85, (_val)) 1562 #define BSDK_WR_PHY84728_LN_DEV1_MISC_CNTL2r(_pctrl, _val) \ 1563 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0xCA85, (_val)) 1564 #define BSDK_MOD_PHY84728_LN_DEV1_MISC_CNTL2r(_pctrl, _val, _mask) \ 1565 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0xCA85, \ 1566 (_val), (_mask)) 1567 1568 /* RX Alarm Control Resister (Addr 0x9000) */ 1569 #define BSDK_RD_PHY84728_LN_DEV1_RX_ALARM_CNTLr(_pctrl, _val) \ 1570 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x9000, (_val)) 1571 #define BSDK_WR_PHY84728_LN_DEV1_RX_ALARM_CNTLr(_pctrl, _val) \ 1572 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x9000, (_val)) 1573 #define BSDK_MOD_PHY84728_LN_DEV1_RX_ALARM_CNTLr(_pctrl, _val, _mask) \ 1574 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x9000, \ 1575 (_val), (_mask)) 1576 1577 /* TX Alarm Control Resister (Addr 0x9001) */ 1578 #define BSDK_RD_PHY84728_LN_DEV1_TX_ALARM_CNTLr(_pctrl, _val) \ 1579 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x9001, (_val)) 1580 #define BSDK_WR_PHY84728_LN_DEV1_TX_ALARM_CNTLr(_pctrl, _val) \ 1581 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x9001, (_val)) 1582 #define BSDK_MOD_PHY84728_LN_DEV1_TX_ALARM_CNTLr(_pctrl, _val, _mask) \ 1583 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x9001, \ 1584 (_val), (_mask)) 1585 1586 /* LASI Control Resister (Addr 0x9002) */ 1587 #define BSDK_RD_PHY84728_LN_DEV1_LASI_CNTLr(_pctrl, _val) \ 1588 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x9002, (_val)) 1589 #define BSDK_WR_PHY84728_LN_DEV1_LASI_CNTLr(_pctrl, _val) \ 1590 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0001, 0x9002, (_val)) 1591 #define BSDK_MOD_PHY84728_LN_DEV1_LASI_CNTLr(_pctrl, _val, _mask) \ 1592 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0001, 0x9002, \ 1593 (_val), (_mask)) 1594 1595 /* RX Alarm Status Register (Addr 0x9003) */ 1596 #define BSDK_RD_PHY84728_LN_DEV1_RX_ALARM_STATr(_pctrl, _val) \ 1597 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x9003, (_val)) 1598 1599 /* TX Alarm Status Register (Addr 0x9003) */ 1600 #define BSDK_RD_PHY84728_LN_DEV1_TX_ALARM_STATr(_pctrl, _val) \ 1601 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x9004, (_val)) 1602 1603 /* LASI Status Register (Addr 0x9003) */ 1604 #define BSDK_RD_PHY84728_LN_DEV1_LASI_STATr(_pctrl, _val) \ 1605 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0001, 0x9005, (_val)) 1606 1607 /* XGXS clause 45 registers */ 1608 1609 /* XGXS control Register */ 1610 #define BSDK_RD_PHY84728_SYS_DEV4_XGXS_CTRLr(_pctrl, _val) \ 1611 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x4, 0x8000, (_val)) 1612 #define BSDK_WR_PHY84728_SYS_DEV4_XGXS_CTRLr(_pctrl, _val) \ 1613 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x4, 0x8000, (_val)) 1614 #define BSDK_MOD_PHY84728_SYS_DEV4_XGXS_CTRLr(_pctrl, _val, _mask) \ 1615 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x4, 0x8000, \ 1616 (_val), (_mask)) 1617 1618 /* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 1619 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 1620 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 1621 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 1622 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 1623 /* XGXS control Register */ 1624 #define BSDK_RD_PHY84728_XGXSBLK0_MISCCONTROL1r(_pctrl, _val) \ 1625 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x4, 0x800e, (_val)) 1626 #define BSDK_WR_PHY84728_XGXSBLK0_MISCCONTROL1r(_pctrl, _val) \ 1627 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x4, 0x800e, (_val)) 1628 #define BSDK_MOD_PHY84728_XGXSBLK0_MISCCONTROL1r(_pctrl, _val, _mask) \ 1629 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x4, 0x800e, \ 1630 (_val), (_mask)) 1631 1632 1633 /* XGXS Lane status Register */ 1634 #define BSDK_RD_PHY84728_XGXS_DEV4_XS_LANE_STATr(_pctrl, _val) \ 1635 BSDK_PHY84728_REG_RD((_pctrl), 0x00, 0x0004, 0x18, (_val)) 1636 #define BSDK_WR_PHY84728_XGXS_DEV4_XS_LANE_STATr(_pctrl, _val) \ 1637 BSDK_PHY84728_REG_WR((_pctrl), 0x00, 0x0004, 0x18, (_val)) 1638 #define BSDK_MOD_PHY84728_XGXS_DEV4_XS_LANE_STATr(_pctrl, _val, _mask) \ 1639 BSDK_PHY84728_REG_MOD((_pctrl), 0x00, 0x0004, 0x18, \ 1640 (_val), (_mask)) 1641 1642 /* I2C related defines */ 1643 #define BSDK_PHY84728_BSC_XFER_MAX 0x1F9 1644 #define BSDK_PHY84728_BSC_WR_MAX 16 1645 #define BSDK_PHY84728_WRITE_START_ADDR 0x8007 1646 #define BSDK_PHY84728_READ_START_ADDR 0x8007 1647 #define BSDK_PHY84728_WR_FREQ_400KHZ 0x0100 1648 #define BSDK_PHY84728_2W_STAT 0x000C 1649 #define BSDK_PHY84728_2W_STAT_IDLE 0x0000 1650 #define BSDK_PHY84728_2W_STAT_COMPLETE 0x0004 1651 #define BSDK_PHY84728_2W_STAT_IN_PRG 0x0008 1652 #define BSDK_PHY84728_2W_STAT_FAIL 0x000C 1653 #define BSDK_PHY84728_BSC_WRITE_OP 0x22 1654 #define BSDK_PHY84728_BSC_READ_OP 0x2 1655 #define BSDK_PHY84728_I2CDEV_WRITE 0x1 1656 #define BSDK_PHY84728_I2CDEV_READ 0x0 1657 #define BSDK_PHY84728_I2C_8BIT 0 1658 #define BSDK_PHY84728_I2C_16BIT 1 1659 #define BSDK_PHY84728_I2C_TEMP_RAM 0xE 1660 #define BSDK_PHY84728_I2C_OP_TYPE(access_type,data_type) \ 1661 ((access_type) | ((data_type) << 8)) 1662 #define BSDK_PHY84728_I2C_ACCESS_TYPE(op_type) ((op_type) & 0xff) 1663 #define BSDK_PHY84728_I2C_DATA_TYPE(op_type) (((op_type) >> 8) & 0xff) 1664 1665 #endif /* _PHY84728_INT_H */