phy84728.h (11556B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 */ 8 9 #ifndef _bsdk_phy84728_H_ 10 #define _bsdk_phy84728_H_ 11 12 13 #define BSDK_PHY84728_BRCM_OUI3 0x1be9 /* Broadcom OUI */ 14 #define BSDK_PHY84728_BRCM_OUI1 0x1018 /* Broadcom OUI */ 15 16 /* 17 * Supported PHYs 18 */ 19 20 #if 0 21 #define BSDK_PHY_BCM84728_MODEL 0x3d 22 #endif 23 #define BSDK_PHY_BCM84728_MODEL 0x27 24 25 typedef enum bsdk_phy84728_speed_s { 26 BSDK_PHY84728_SPEED_10 = 0, 27 BSDK_PHY84728_SPEED_100, 28 BSDK_PHY84728_SPEED_1000, 29 BSDK_PHY84728_SPEED_10000 30 }bsdk_phy84728_speed_t; 31 32 typedef enum bsdk_phy84728_duplex_s { 33 BSDK_PHY84728_HALF_DUPLEX = 0, 34 BSDK_PHY84728_FULL_DUPLEX 35 }bsdk_phy84728_duplex_t; 36 37 typedef enum bsdk_phy84728_intf_s { 38 BSDK_PHY84728_INTF_SGMII = 0, 39 BSDK_PHY84728_INTF_1000X, 40 BSDK_PHY84728_INTF_SFI, 41 BSDK_PHY84728_INTF_XFI, 42 BSDK_PHY84728_INTF_XAUI 43 }bsdk_phy84728_intf_t; 44 45 /* 46 * Switch MAC speed and duplex policies 47 */ 48 typedef enum bsdk_phy84728_mac_policy_s { 49 BSDK_BCM84728_SWITCH_FIXED = 0, 50 BSDK_BCM84728_SWITCH_FOLLOWS_LINE 51 }bsdk_phy84728_mac_policy_t; 52 53 54 typedef enum bsdk_phy84728_port_mdix_s { 55 BSDK_PHY84728_PORT_MDIX_AUTO, 56 BSDK_PHY84728_PORT_MDIX_FORCE_AUTO, 57 BSDK_PHY84728_PORT_MDIX_NORMAL, 58 BSDK_PHY84728_PORT_MDIX_XOVER 59 }bsdk_phy84728_port_mdix_t; 60 61 typedef enum bsdk_phy84728_port_mdix_status_s { 62 BSDK_PHY84728_PORT_MDIX_STATUS_NORMAL, 63 BSDK_PHY84728_PORT_MDIX_STATUS_XOVER 64 }bsdk_phy84728_port_mdix_status_t; 65 66 67 typedef enum bsdk_phy84728_master_s { 68 BSDK_PHY84728_PORT_MS_SLAVE =0, 69 BSDK_PHY84728_PORT_MS_MASTER, 70 BSDK_PHY84728_PORT_MS_AUTO, 71 BSDK_PHY84728_PORT_MS_NONE 72 }bsdk_phy84728_master_t; 73 74 typedef enum bsdk_phy84728_fcmap_dir_s { 75 BSDK_PHY84728_FCMAP_DIR_EGRESS = 0, 76 BSDK_PHY84728_FCMAP_DIR_INGRESS 77 } bsdk_phy84728_fcmap_dir_t; 78 79 typedef enum bsdk_phy84728_fcmap_port_mode_s { 80 BSDK_PHY84728_FCMAP_FCOE_TO_FC_MODE = 0, 81 BSDK_PHY84728_FCMAP_FCOE_TO_FCOE_MODE 82 } bsdk_phy84728_fcmap_port_mode_t; 83 84 typedef enum bsdk_phy84728_fcmap_port_speed_s { 85 BSDK_PHY84728_FCMAP_PORT_SPEED_2GBPS = 0, 86 BSDK_PHY84728_FCMAP_PORT_SPEED_4GBPS = 1, 87 BSDK_PHY84728_FCMAP_PORT_SPEED_8GBPS = 2, 88 BSDK_PHY84728_FCMAP_PORT_SPEED_16GBPS = 3, 89 BSDK_PHY84728_FCMAP_PORT_SPEED_MAX_COUNT 90 } bsdk_phy84728_fcmap_port_speed_t; 91 92 typedef enum bsdk_phy84728_fcmap_port_state_s { 93 BSDK_PHY84728_FCMAP_PORT_STATE_INIT = 0, 94 BSDK_PHY84728_FCMAP_PORT_STATE_RESET = 1, 95 BSDK_PHY84728_FCMAP_PORT_STATE_ACTIVE = 2, 96 BSDK_PHY84728_FCMAP_PORT_STATE_LINKDOWN = 3, 97 BSDK_PHY84728_FCMAP_PORT_STATE_DISABLE = 4, 98 BSDK_PHY84728_FCMAP_PORT_STATE_MAX_COUNT 99 } bsdk_phy84728_fcmap_port_state_t; 100 101 typedef unsigned int bsdk_phy84728_port_mode_t; 102 typedef unsigned int bsdk_phy84728_port_ability_t; 103 104 /* 105 * Port modes. 106 */ 107 108 #define BSDK_PHY84728_PM_10MB_HD (1 << 0) 109 #define BSDK_PHY84728_PM_10MB_FD (1 << 1) 110 #define BSDK_PHY84728_PM_100MB_HD (1 << 2) 111 #define BSDK_PHY84728_PM_100MB_FD (1 << 3) 112 #define BSDK_PHY84728_PM_1000MB_HD (1 << 4) 113 #define BSDK_PHY84728_PM_1000MB_FD (1 << 5) 114 #define BSDK_PHY84728_PM_PAUSE_TX (1 << 6) 115 #define BSDK_PHY84728_PM_PAUSE_RX (1 << 7) 116 #define BSDK_PHY84728_PM_PAUSE_ASYMM (1 << 8) 117 #define BSDK_PHY84728_PM_TBI (1 << 9) 118 #define BSDK_PHY84728_PM_MII (1 << 10) 119 #define BSDK_PHY84728_PM_GMII (1 << 11) 120 #define BSDK_PHY84728_PM_SGMII (1 << 12) 121 #define BSDK_PHY84728_PM_LB_MAC (1 << 13) 122 #define BSDK_PHY84728_PM_LB_NONE (1 << 14) 123 #define BSDK_PHY84728_PM_LB_PHY (1 << 15) 124 #define BSDK_PHY84728_PM_AN (1 << 16) 125 126 #define BSDK_PHY84728_PM_PAUSE (BSDK_PHY84728_PM_PAUSE_TX | \ 127 BSDK_PHY84728_PM_PAUSE_RX) 128 #define BSDK_PHY84728_PM_10MB (BSDK_PHY84728_PM_10MB_HD | \ 129 BSDK_PHY84728_PM_10MB_FD) 130 #define BSDK_PHY84728_PM_100MB (BSDK_PHY84728_PM_100MB_HD | \ 131 BSDK_PHY84728_PM_100MB_FD) 132 #define BSDK_PHY84728_PM_1000MB (BSDK_PHY84728_PM_1000MB_HD | \ 133 BSDK_PHY84728_PM_1000MB_FD) 134 135 #define BSDK_PHY84728_PM_SPEED_ALL (BSDK_PHY84728_PM_1000MB | \ 136 BSDK_PHY84728_PM_100MB | \ 137 BSDK_PHY84728_PM_10MB) 138 139 #define BSDK_PHY84728_PM_FD (BSDK_PHY84728_PM_1000MB_FD | \ 140 BSDK_PHY84728_PM_100MB_FD | \ 141 BSDK_PHY84728_PM_10MB_FD) 142 143 #define BSDK_PHY84728_PM_HD (BSDK_PHY84728_PM_1000MB_HD | \ 144 BSDK_PHY84728_PM_100MB_HD | \ 145 BSDK_PHY84728_PM_10MB_HD) 146 147 /* 148 * Port ability 149 */ 150 #define BSDK_PHY84728_PA_10MB_HD (1 << 0) 151 #define BSDK_PHY84728_PA_10MB_FD (1 << 1) 152 #define BSDK_PHY84728_PA_100MB_HD (1 << 2) 153 #define BSDK_PHY84728_PA_100MB_FD (1 << 3) 154 #define BSDK_PHY84728_PA_1000MB_HD (1 << 4) 155 #define BSDK_PHY84728_PA_1000MB_FD (1 << 5) 156 #define BSDK_PHY84728_PA_10000MB_FD (1 << 6) 157 #define BSDK_PHY84728_PA_PAUSE_TX (1 << 7) 158 #define BSDK_PHY84728_PA_PAUSE_RX (1 << 8) 159 #define BSDK_PHY84728_PA_PAUSE_ASYMM (1 << 9) 160 #define BSDK_PHY84728_PA_SGMII (1 << 10) 161 #define BSDK_PHY84728_PA_XSGMII (1 << 11) 162 #define BSDK_PHY84728_PA_LB_MAC (1 << 12) 163 #define BSDK_PHY84728_PA_LB_NONE (1 << 13) 164 #define BSDK_PHY84728_PA_LB_PHY (1 << 14) 165 #define BSDK_PHY84728_PA_AN (1 << 15) 166 167 #define BSDK_PHY84728_PA_PAUSE (BSDK_PHY84728_PA_PAUSE_TX | \ 168 BSDK_PHY84728_PA_PAUSE_RX) 169 #define BSDK_PHY84728_PA_10MB (BSDK_PHY84728_PA_10MB_HD | \ 170 BSDK_PHY84728_PA_10MB_FD) 171 #define BSDK_PHY84728_PA_100MB (BSDK_PHY84728_PA_100MB_HD | \ 172 BSDK_PHY84728_PA_100MB_FD) 173 #define BSDK_PHY84728_PA_1000MB (BSDK_PHY84728_PA_1000MB_HD | \ 174 BSDK_PHY84728_PA_1000MB_FD) 175 176 #define BSDK_PHY84728_PA_SPEED_ALL (BSDK_PHY84728_PA_1000MB | \ 177 BSDK_PHY84728_PA_100MB | \ 178 BSDK_PHY84728_PA_10MB) 179 180 #define BSDK_PHY84728_PA_FD (BSDK_PA_PHY84728_1000MB_FD | \ 181 BSDK_PHY84728_PA_100MB_FD | \ 182 BSDKPHY84728__PA_10MB_FD) 183 184 #define BSDK_PHY84728_PA_HD (BSDK_PHY84728_PA_1000MB_HD | \ 185 BSDK_PHY84728_PA_100MB_HD | \ 186 BSDK_PHY84728_PA_10MB_HD) 187 188 #define BSDK_PHY84728_PA_FCMAP (1 << 0) 189 #define BSDK_PHY84728_PA_FCMAP_FCMAC_LOOPBACK (1 << 1) 190 #define BSDK_PHY84728_PA_FCMAP_AUTONEG (1 << 2) 191 #define BSDK_PHY84728_PA_FCMAP_2GB (1 << 3) 192 #define BSDK_PHY84728_PA_FCMAP_4GB (1 << 4) 193 #define BSDK_PHY84728_PA_FCMAP_8GB (1 << 5) 194 #define BSDK_PHY84728_PA_FCMAP_16GB (1 << 6) 195 196 /* 197 * Port mode 198 */ 199 #define BSDK_PHY84728_MODE_FCMAP (1 << 0) 200 201 /* 202 * Standalone PHY driver functions 203 */ 204 extern int 205 bsdk_phy84728_phy_mac_driver_detach(phy_ctrl_t *pc); 206 207 208 /* Init PHY with MDIO address phy_id */ 209 extern int 210 bsdk_phy84728_init(phy_ctrl_t *pc, uint8 reset, int line_mode, 211 int fcmap_enable, int phy_ext_boot); 212 213 /* Reset PHY with MDIO address phy_id */ 214 extern int 215 bsdk_phy84728_reset(phy_ctrl_t *pc); 216 217 /* Post Reset PHY setup with MDIO address phy_id */ 218 extern int 219 bsdk_phy84728_no_reset_setup(phy_ctrl_t *pc, int line_mode, 220 int phy_ext_boot); 221 222 /* Enable/Disable PHY */ 223 extern int 224 bsdk_phy84728_enable_set(phy_ctrl_t *pc, int enable); 225 226 /* Set Lane Map of PHY */ 227 extern int 228 bsdk_phy84728_lane_map(phy_ctrl_t *pc); 229 230 /* Set Speed of PHY and (Line and Switch) UNIMACs */ 231 extern int 232 bsdk_phy84728_speed_set(phy_ctrl_t *pc, int speed); 233 234 /* Get Speed of PHY and (Line and Switch) UNIMACs */ 235 extern int 236 bsdk_phy84728_speed_get(phy_ctrl_t *pc, int *speed); 237 238 /* Set duplex of PHY and (Line and Switch) UNIMACs */ 239 extern int 240 bsdk_phy84728_duplex_set(phy_ctrl_t *pc, bsdk_phy84728_duplex_t duplex); 241 242 /* Get duplex of PHY and (Line and Switch) UNIMACs */ 243 extern int 244 bsdk_phy84728_duplex_get(phy_ctrl_t *pc, bsdk_phy84728_duplex_t *duplex); 245 246 /* Set AUTO negotiation Attributes */ 247 extern int 248 bsdk_phy84728_an_set(phy_ctrl_t *pc, int an, int autoneg_advert); 249 250 /* Get AUTO negotiation Attributes */ 251 extern int 252 bsdk_phy84728_an_get(phy_ctrl_t *pc, int *an, int *an_done); 253 254 /* Set MDIX */ 255 extern int 256 bsdk_phy84728_mdix_set(phy_ctrl_t *pc, bsdk_phy84728_port_mdix_t mdix_mode); 257 258 /* MDIX Status Get */ 259 extern int 260 bsdk_phy84728_mdix_status_get(phy_ctrl_t *pc, 261 bsdk_phy84728_port_mdix_status_t *status); 262 /* Set Loopback */ 263 extern int 264 bsdk_phy84728_loopback_set(phy_ctrl_t *pc, int loopback); 265 266 /* Get loopback settings of the PHY */ 267 extern int 268 bsdk_phy84728_loopback_get(phy_ctrl_t *pc, int *loopback); 269 270 /* Set master */ 271 extern int 272 bsdk_phy84728_master_set(phy_ctrl_t *pc, bsdk_phy84728_master_t master); 273 274 /* Get Master */ 275 extern int 276 bsdk_phy84728_master_get(phy_ctrl_t *pc, int *master); 277 278 /* Set local autoneg advertising parameters */ 279 extern int 280 bsdk_phy84728_ability_advert_set(phy_ctrl_t *pc, 281 bsdk_phy84728_port_ability_t ability); 282 283 /* Get local autoneg advertising parameters */ 284 extern int 285 bsdk_phy84728_ability_advert_get(phy_ctrl_t *pc, 286 bsdk_phy84728_port_ability_t *ability); 287 288 /* Get Remote autoneg advertising parameters */ 289 extern int 290 bsdk_phy84728_remote_ability_advert_get(phy_ctrl_t *pc, 291 bsdk_phy84728_port_ability_t *ability); 292 293 /* Get Link status */ 294 extern int 295 bsdk_phy84728_link_get(phy_ctrl_t *pc, int *link); 296 297 /* Gets the Ability of the PHY */ 298 extern int 299 bsdk_phy84728_ability_local_get(phy_ctrl_t *pc, 300 bsdk_phy84728_port_ability_t *ability); 301 302 /* Download the firmware */ 303 extern int 304 bsdk_phy84728_mdio_firmware_download(phy_ctrl_t *pc, 305 uint8 *new_fw, uint32 fw_length); 306 /* Firmware Update */ 307 extern int 308 bsdk_phy84728_spi_firmware_update(phy_ctrl_t *pc, 309 uint8 *array, uint32 datalen); 310 /* Get Interface of side */ 311 extern int 312 bsdk_phy84728_line_intf_get(phy_ctrl_t *pc, int dev_port, 313 bsdk_phy84728_intf_t *mode); 314 /* Set Interface of side */ 315 extern int 316 bsdk_phy84728_line_intf_set(phy_ctrl_t *pc, int dev_port, 317 bsdk_phy84728_intf_t mode); 318 319 /* I2C related */ 320 extern int 321 bsdk_phy_84740_i2cdev_read(phy_ctrl_t *pc, 322 int dev_addr, 323 int offset, 324 int nbytes, 325 uint8 *read_array); 326 327 extern int 328 bsdk_phy_84740_i2cdev_write(phy_ctrl_t *pc, 329 int dev_addr, 330 int offset, 331 int nbytes, 332 uint8 *write_array); 333 334 #endif /* _bsdk_phy84728_H_ */