phy84328.h (1425313B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy84328.h 8 * Purpose: Phys Driver support for Broadcom 84328 40G phy 9 * Note: 10 */ 11 12 13 14 /** 15 * m = memory, c = core, r = register, f = field, d = data. 16 */ 17 #if !defined(GET_FIELD) && !defined(SET_FIELD) 18 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 19 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 20 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 21 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 22 23 #define GET_FIELD(m,c,r,f) \ 24 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 25 26 #define SET_FIELD(m,c,r,f,d) \ 27 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 28 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 29 ) 30 31 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 32 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 33 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 34 35 #endif /* GET & SET */ 36 37 38 /* 84328 Devices */ 39 #define PHY84328_C45_DEV_PMA_PMD 0x01 40 #define PHY84328_C45_DEV_AN 0x07 41 42 #define PHY84328_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 43 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 44 #define PHY84328_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 45 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 46 #define PHY84328_REG_ADRR_WRITE(_unit, _phy_ctrl, _addr, _val) \ 47 WRITE_ADDR_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 48 #define PHY84328_REG_DATA_WRITE(_unit, _phy_ctrl, _addr, _val) \ 49 WRITE_DATA_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 50 #define PHY84328_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 51 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 52 53 #define PHY84328_XFI(_unit, _phy_ctrl) \ 54 PHY84328_REG_MODIFY((_unit), (_phy_ctrl), \ 55 SOC_PHY_CLAUSE45_ADDR(PHY84328_C45_DEV_PMA_PMD, (0xffff)), 1, 1) 56 57 #define PHY84328_MMF(_unit, _phy_ctrl) \ 58 PHY84328_REG_MODIFY((_unit), (_phy_ctrl), \ 59 SOC_PHY_CLAUSE45_ADDR(PHY84328_C45_DEV_PMA_PMD, (0xffff)), 0,1) 60 61 /* 62 * Line side 63 */ 64 /* PMA/PMD Device (Dev Addr 1) */ 65 #define READ_PHY84328_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 66 PHY84328_REG_READ((_unit), (_phy_ctrl), \ 67 SOC_PHY_CLAUSE45_ADDR(PHY84328_C45_DEV_PMA_PMD, (_reg)), (_val)) 68 #define WRITE_PHY84328_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 69 PHY84328_REG_WRITE((_unit), (_phy_ctrl), \ 70 SOC_PHY_CLAUSE45_ADDR(PHY84328_C45_DEV_PMA_PMD, (_reg)), (_val)) 71 #define WRITE_ADDR_PHY84328_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 72 PHY84328_REG_ADRR_WRITE((_unit), (_phy_ctrl), \ 73 (_reg), (_val)) 74 #define WRITE_DATA_PHY84328_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 75 PHY84328_REG_DATA_WRITE((_unit), (_phy_ctrl), \ 76 (_reg), (_val)) 77 #define MODIFY_PHY84328_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 78 PHY84328_REG_MODIFY((_unit), (_phy_ctrl), \ 79 SOC_PHY_CLAUSE45_ADDR(PHY84328_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask)) 80 81 /* AN Device (Dev Addr 7) */ 82 #define READ_PHY84328_MMF_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 83 PHY84328_REG_READ((_unit), (_phy_ctrl), \ 84 SOC_PHY_CLAUSE45_ADDR(PHY84328_C45_DEV_AN, (_reg)), (_val)) 85 #define WRITE_PHY84328_MMF_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 86 PHY84328_REG_WRITE((_unit), (_phy_ctrl), \ 87 SOC_PHY_CLAUSE45_ADDR(PHY84328_C45_DEV_AN, (_reg)), (_val)) 88 #define MODIFY_PHY84328_MMF_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 89 PHY84328_REG_MODIFY((_unit), (_phy_ctrl), \ 90 SOC_PHY_CLAUSE45_ADDR(PHY84328_C45_DEV_AN, (_reg)), (_val), (_mask)) 91 92 93 94 95 96 97 /**************************************************************************** 98 * Core Enums. 99 */ 100 /**************************************************************************** 101 * ln_device1_Common_Controller 102 */ 103 #define PHY84328_DEV1_REGUALTOR_CTRL 0x0000c850 /* Regulator_control */ 104 #define PHY84328_DEV1_GEN_CTRL 0x0000ca10 /* GEN_CTRL */ 105 #define PHY84328_DEV1_RAM_LWPR_CTRL 0x0000ca11 /* RAM_LWPR_CTRL */ 106 #define PHY84328_DEV1_MSG_IN 0x0000ca12 /* MSG_IN */ 107 #define PHY84328_DEV1_MSG_OUT 0x0000ca13 /* MSG_OUT */ 108 #define PHY84328_DEV1_ERRORED_SRAM_ADDRESS 0x0000ca14 /* SRAM_ADDRESS_WITH_ERROR */ 109 #define PHY84328_DEV1_ERRORED_SRAM_DATA 0x0000ca15 /* SRAM_ERROR_STATUS */ 110 #define PHY84328_DEV1_GP_REG_0 0x0000ca18 /* GP_REG_0 */ 111 #define PHY84328_DEV1_GP_REG_1 0x0000ca19 /* GP_REG_1 */ 112 #define PHY84328_DEV1_GP_REG_2 0x0000ca1a /* GP_REG_2 */ 113 #define PHY84328_DEV1_GP_REG_3 0x0000ca1b /* GP_REG_3 */ 114 #define PHY84328_DEV1_GP_REG_4 0x0000ca1c /* GP_REG_4 */ 115 #define PHY84328_DEV1_LOGAD_CTRL 0x0000ca7b /* LOG_CTRL */ 116 #define PHY84328_DEV1_SW_RESET_CTRL 0x0000ca82 /* SW_RESET_CTRL */ 117 #define PHY84328_DEV1_MISC_CTRL 0x0000ca85 /* MISC_CTRL */ 118 #define PHY84328_DEV1_SINGLE_PMD_CTRL 0x0000ca86 /* SINGLE_PMD_CTRL */ 119 #define PHY84328_DEV1_GP_REG_5 0x0000ca88 /* GP_REG_5 */ 120 #define PHY84328_DEV1_GP_REG_6 0x0000ca89 /* GP_REG_6 */ 121 #define PHY84328_DEV1_GP_REG_7 0x0000ca8a /* GP_REG_7 */ 122 #define PHY84328_DEV1_GP_REG_8 0x0000ca8b /* GP_REG_8 */ 123 #define PHY84328_DEV1_GP_REG_9 0x0000ca8c /* GP_REG_9 */ 124 #define PHY84328_DEV1_VTMON_CTRL_0 0x0000cbf0 /* VTMON_CTRL_0 */ 125 #define PHY84328_DEV1_VTMON_CTRL_1 0x0000cbf1 /* VTMON_CTRL_1 */ 126 #define PHY84328_DEV1_VTMON_STATUS 0x0000cbf2 /* VTMON_STATUS */ 127 #define PHY84328_DEV1_VTMON_CTRL_2 0x0000cbf3 /* VTMON_CTRL_2 */ 128 129 130 /**************************************************************************** 131 * ln_device1_DSC_regs 132 */ 133 #define PHY84328_DEV1_CDR_CTRL0 0x0000c200 /* CDR_Control_0_Register */ 134 #define PHY84328_DEV1_CDR_CTRL1 0x0000c201 /* CDR Control_1_Register */ 135 #define PHY84328_DEV1_CDR_CTRL2 0x0000c202 /* CDR Control_2_Register */ 136 #define PHY84328_DEV1_PI_CTRL0 0x0000c203 /* Phase_Interpolator_Control_0_Register */ 137 #define PHY84328_DEV1_PI_CTRL1 0x0000c204 /* Phase_Interpolator_Control_1_Register */ 138 #define PHY84328_DEV1_DFE_VGA_CTRL0 0x0000c205 /* DFE_VGA_Control_0_Register */ 139 #define PHY84328_DEV1_DFE_VGA_CTRL1 0x0000c206 /* DFE_VGA_Control_1_Register */ 140 #define PHY84328_DEV1_DFE_VGA_CTRL2 0x0000c207 /* DFE_VGA_Control_2_Register */ 141 #define PHY84328_DEV1_DFE_VGA_CTRL3 0x0000c208 /* DFE_VGA_Control_3_Register */ 142 #define PHY84328_DEV1_DFE_VGA_CTRL4 0x0000c209 /* DFE_VGA_Control_4_Register */ 143 #define PHY84328_DEV1_DFE_VGA_CTRL5 0x0000c20a /* DFE_VGA_Control_5_Register */ 144 #define PHY84328_DEV1_DFE_VGA_CTRL6 0x0000c20b /* DFE_VGA_Control_6_Register */ 145 #define PHY84328_DEV1_DFE_VGA_CTRL7 0x0000c20c /* DFE_VGA_Control_7_Register */ 146 #define PHY84328_DEV1_DSC_DIAG_CTRL0 0x0000c20d /* DSC_Diagnostics_Control_0_Register */ 147 #define PHY84328_DEV1_UC_CTRL 0x0000c20e /* DSC_to_uController_Control_Register */ 148 #define PHY84328_DEV1_ACQ_SM_CTRL0 0x0000c210 /* DSC State Machine Control 0 Register */ 149 #define PHY84328_DEV1_ACQ_SM_CTRL1 0x0000c211 /* DSC State Machine Control 1 Register */ 150 #define PHY84328_DEV1_ACQ_SM_CTRL2 0x0000c212 /* DSC State Machine Control 2 Register */ 151 #define PHY84328_DEV1_ACQ_SM_CTRL3 0x0000c213 /* DSC State Machine Control 3 Register */ 152 #define PHY84328_DEV1_ACQ_SM_CTRL4 0x0000c214 /* DSC State Machine Control 4 Register */ 153 #define PHY84328_DEV1_ACQ_SM_CTRL5 0x0000c215 /* DSC State Machine Control 5 Register */ 154 #define PHY84328_DEV1_ACQ_SM_CTRL6 0x0000c216 /* DSC State Machine Control 6 Register */ 155 #define PHY84328_DEV1_ACQ_SM_CTRL7 0x0000c217 /* DSC State Machine Control 7 Register */ 156 #define PHY84328_DEV1_ACQ_SM_CTRL8 0x0000c218 /* DSC State Machine Control 8 Register */ 157 #define PHY84328_DEV1_DSC_ANA_CTRL0 0x0000c219 /* DSC Analog Control 0 Register */ 158 #define PHY84328_DEV1_DSC_ANA_CTRL1 0x0000c21a /* DSC Analog Control 1 Register */ 159 #define PHY84328_DEV1_DSC_ANA_CTRL2 0x0000c21b /* DSC Analog Control 2 Register */ 160 #define PHY84328_DEV1_DSC_ANA_CTRL3 0x0000c21c /* DSC Analog Control 3 Register */ 161 #define PHY84328_DEV1_DSC_ANA_CTRL4 0x0000c21d /* DSC Analog Control 4 Register */ 162 #define PHY84328_DEV1_DSC_MISC_CTRL0 0x0000c21e /* DSC Misc Control 0 Register */ 163 #define PHY84328_DEV1_CDR_LM_CTRL_0 0x0000c250 /* CDR Lock Monitor Control 0 Register */ 164 165 166 /**************************************************************************** 167 * ln_device1_I2C_Registers 168 */ 169 #define PHY84328_DEV1_I2C_CONTROL_REGISTER 0x00008000 /* I2C Control Register */ 170 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER 0x00008001 /* I2C Check Sum Register */ 171 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER 0x00008002 /* I2C Transfer Size Register */ 172 #define PHY84328_DEV1_I2C_EXTERNAL_NVM_ADDRESS_REGISTER 0x00008003 /* I2C External NVM Address Register */ 173 #define PHY84328_DEV1_I2C_INTERNAL_ADDRESS_REGISTER 0x00008004 /* I2C Internal Address Register */ 174 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER 0x00008005 /* I2C Slave ID Address Register */ 175 176 177 /**************************************************************************** 178 * ln_device1_Micro_regs 179 */ 180 #define PHY84328_DEV1_STATE_DEBUG_LN0 0x0000c1e0 /* Micro-controller_Tuning_State_Debug_for_LN0 */ 181 #define PHY84328_DEV1_STATE_DEBUG_LN1 0x0000c1e1 /* Micro-controller_Tuning_State_Debug_for_LN1 */ 182 #define PHY84328_DEV1_STATE_DEBUG_LN2 0x0000c1e2 /* Micro-controller_Tuning_State_Debug_for_LN2 */ 183 #define PHY84328_DEV1_STATE_DEBUG_LN3 0x0000c1e3 /* Micro-controller_Tuning_State_Debug_for_LN3 */ 184 #define PHY84328_DEV1_SPEED_DEBUG_LN0 0x0000c1e4 /* Micro-controller_Speed/Mode_Debug_for_LN0 */ 185 #define PHY84328_DEV1_SPEED_DEBUG_LN1 0x0000c1e5 /* Micro-controller_Speed/Mode_Debug_for_LN1 */ 186 #define PHY84328_DEV1_SPEED_DEBUG_LN2 0x0000c1e6 /* Micro-controller_Speed/Mode_Debug_for_LN2 */ 187 #define PHY84328_DEV1_SPEED_DEBUG_LN3 0x0000c1e7 /* Micro-controller_Speed/Mode_Debug_for_LN3 */ 188 #define PHY84328_DEV1_CL72_STATUS_LN0 0x0000c1e8 /* Micro-controller_CL72_Status_for_LN0 */ 189 #define PHY84328_DEV1_CL72_STATUS_LN1 0x0000c1e9 /* Micro-controller_CL72_Status_for_LN1 */ 190 #define PHY84328_DEV1_CL72_STATUS_LN2 0x0000c1ea /* Micro-controller_CL72_Status_for_LN2 */ 191 #define PHY84328_DEV1_CL72_STATUS_LN3 0x0000c1eb /* Micro-controller_CL72_Status_for_LN3 */ 192 #define PHY84328_DEV1_VERSION 0x0000c1f0 /* Micro-controller Version Register */ 193 #define PHY84328_DEV1_TARGET 0x0000c1f1 /* Micro-controller Target Register */ 194 #define PHY84328_DEV1_FIRMWARE_MODE 0x0000c1f2 /* Micro-controller firmware_mode 2_2 Register */ 195 #define PHY84328_DEV1_GPIO_CTRL_LN0 0x0000c1f3 /* Micro-controller LN0 GPIO Control Register */ 196 #define PHY84328_DEV1_GPIO_CTRL_LN1 0x0000c1f4 /* Micro-controller LN1 GPIO Control Register */ 197 #define PHY84328_DEV1_GPIO_CTRL_LN2 0x0000c1f5 /* Micro-controller LN2 GPIO Control Register */ 198 #define PHY84328_DEV1_GPIO_CTRL_LN3 0x0000c1f6 /* Micro-controller LN3 GPIO Control Register */ 199 #define PHY84328_DEV1_GPIO_STS_LN0 0x0000c1f7 /* Micro-controller LN0 GPIO Status Register */ 200 #define PHY84328_DEV1_GPIO_STS_LN1 0x0000c1f8 /* Micro-controller LN1 GPIO Status Register */ 201 #define PHY84328_DEV1_GPIO_STS_LN2 0x0000c1f9 /* Micro-controller LN2 GPIO Status Register */ 202 #define PHY84328_DEV1_GPIO_STS_LN3 0x0000c1fa /* Micro-controller LN3 GPIO Status Register */ 203 #define PHY84328_DEV1_REGB 0x0000c1fb /* Micro Temp 2_B Register */ 204 #define PHY84328_DEV1_TUNING_STATE_BYPASS 0x0000c1fc /* Micro Tuning states Bypass Register */ 205 #define PHY84328_DEV1_TEMPERATURE 0x0000c1fd /* Die-Temperature Register */ 206 #define PHY84328_DEV1_CRC 0x0000c1fe /* Micro-controller code-ram crc Register */ 207 208 209 /**************************************************************************** 210 * ln_device1_PMD_User_Defined_Registers 211 */ 212 #define PHY84328_DEV1_PWR_RAMP 0x0000c800 /* PHY Identifier */ 213 #define PHY84328_DEV1_CHIP_REV_REGISTER 0x0000c801 /* Chip REV Register */ 214 #define PHY84328_DEV1_CHIP_ID0_REGISTER 0x0000c802 /* Chip ID 0 Register */ 215 #define PHY84328_DEV1_CHIP_ID1_REGISTER 0x0000c803 /* Chip ID 1 Register */ 216 #define PHY84328_DEV1_PMD_STATUS_REGISTER 0x0000c804 /* PMD Status Register */ 217 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER 0x0000c808 /* GPIO Control Register */ 218 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER 0x0000c80a /* Ring Oscillator Control Register */ 219 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER 0x0000c80e /* General Purpose IO Control Register */ 220 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS 0x0000c81f /* Speed Link Detect Status */ 221 #define PHY84328_DEV1_CH_RESET_CONTROL 0x0000c822 /* Channel SW Reset Control */ 222 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT 0x0000c828 /* Cl-73 Parallel Port Address Port */ 223 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT 0x0000c82c /* XCl-73 Parallel Port Address Port */ 224 #define PHY84328_DEV1_PAD_CTRL_REGISTER 0x0000c82f /* I2C RxLos And MOD-ABS PAD Control */ 225 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER 0x0000c830 /* Interrupt Register */ 226 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER 0x0000c831 /* Interrupt Enable Register */ 227 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER 0x0000c832 /* Interrupt Status Register */ 228 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER 0x0000c833 /* Interrupt Polarity Register */ 229 #define PHY84328_DEV1_GP_REGISTER_0 0x0000c840 /* General Purpose Register-0 */ 230 #define PHY84328_DEV1_GP_REGISTER_1 0x0000c841 /* General Purpose Register-1 */ 231 #define PHY84328_DEV1_GP_REGISTER_2 0x0000c842 /* General Purpose Register-2 */ 232 #define PHY84328_DEV1_GP_REGISTER_3 0x0000c843 /* General Purpose Register-3 */ 233 #define PHY84328_DEV1_GP_STATUS_REGISTER_0 0x0000c844 /* GP Misc. Status Register-0 */ 234 #define PHY84328_DEV1_GP_STATUS_REGISTER_1 0x0000c845 /* GP Misc. Status Register-1 */ 235 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER 0x0000c848 /* SPI Port Control/Status Register */ 236 #define PHY84328_DEV1_OTP_MISC_SIG1_REGISTER 0x0000c858 /* OTP MISC Signal1 Register */ 237 #define PHY84328_DEV1_OTP_MISC_SIG2_REGISTER 0x0000c859 /* OTP MISC Signal2 Register */ 238 #define PHY84328_DEV1_OTP_MISC_SIG3_REGISTER 0x0000c85a /* OTP MISC Signal3 Register */ 239 #define PHY84328_DEV1_OTP_MISC_SIG4_REGISTER 0x0000c85b /* OTP MISC Signal4 Register */ 240 #define PHY84328_DEV1_OTP_MISC_SIG5_REGISTER 0x0000c85c /* OTP MISC Signal5 Register */ 241 #define PHY84328_DEV1_OTP_MISC_SIG6_REGISTER 0x0000c85d /* OTP MISC Signal6 Register */ 242 #define PHY84328_DEV1_GP_REG_C870_REGISTER 0x0000c870 /* GP Reg @C870 Register */ 243 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER 0x0000c872 /* m8051 Watchdog Control Register */ 244 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER 0x0000c873 /* m8051 Watchdog Status Register */ 245 #define PHY84328_DEV1_CHIP_INTR_STAT 0x0000c874 /* Chip interrupt status register */ 246 #define PHY84328_DEV1_CHIP_INTR_EN 0x0000c876 /* Interrupt Enable register */ 247 #define PHY84328_DEV1_CHIP_INTR_VALUE 0x0000c878 /* Chip interrupt value register */ 248 #define PHY84328_DEV1_CHIP_INTR_CTRL 0x0000c87a /* Chip interrupt control register */ 249 #define PHY84328_DEV1_CH_INTR_CTRL 0x0000c87c /* Chip global interrupt control register */ 250 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER 0x0000c88b /* OTP_OVR_REV_ID_REG */ 251 #define PHY84328_DEV1_OTP_OVR_CHP_ID0_REGISTER 0x0000c88c /* OTP_OVR_REV_ID0_REG */ 252 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER 0x0000c88d /* OTP_OVR_REV_ID1_REG */ 253 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG 0x0000c88e /* OTP_RDY_CNT_STAT_REG */ 254 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0 0x0000c890 /* OTP Override Device ID 0. */ 255 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_1 0x0000c891 /* OTP Override Device ID 1. */ 256 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL 0x0000c892 /* OTP Override Control for Device id0 and id1. */ 257 #define PHY84328_DEV1_DIE_ID 0x0000c899 /* Die ID register */ 258 #define PHY84328_DEV1_OPTICAL_CONFIGURATION 0x0000c8e4 /* Optical Configuration */ 259 #define PHY84328_DEV1_BROADCAST_CTRL 0x0000c8fe /* Select Broadcast Mechanism for MDIO ADDR/Write Operations. */ 260 #define PHY84328_DEV1_XPMD_REGS_SEL 0x0000ffff /* Select System Side Registers For MDIO OP. */ 261 262 263 /**************************************************************************** 264 * ln_device1_PMD_standard_Registers 265 */ 266 #define PHY84328_DEV1_PMD_CONTROL_REGISTER 0x00000000 /* PMD Control Register */ 267 #define PHY84328_DEV1_STATUS_REGISTER 0x00000001 /* Status Register */ 268 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_0 0x00000002 /* PMD Identifier Register 0 */ 269 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_1 0x00000003 /* PMD Identifier Register 1 */ 270 #define PHY84328_DEV1_PMD_SPEED_ABILITY 0x00000004 /* PMD Speed Ability */ 271 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1 0x00000005 /* Devices in Package1 */ 272 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2 0x00000006 /* Devices in package 2 */ 273 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER 0x00000007 /* PMD Control 2 Register */ 274 #define PHY84328_DEV1_STATUS_REGISTER_2 0x00000008 /* Status Register 2 */ 275 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER 0x00000009 /* PMD transmit disable Register */ 276 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER 0x0000000a /* PMD receive signal detect Register */ 277 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER 0x0000000b /* PMD extended ability Register */ 278 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER 0x0000000d /* Fortyg PMD extended ability Register */ 279 #define PHY84328_DEV1_PMD_OUI_ID0_REGISTER 0x0000000e /* PMD OUI ID0 Register */ 280 #define PHY84328_DEV1_PMD_OUI_ID1_REG 0x0000000f /* PMD OUI ID1 Reg */ 281 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER 0x00000096 /* R PMD Control Register */ 282 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER 0x00000097 /* R PMD Status Register */ 283 #define PHY84328_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152 0x00000098 /* TenGBASE_KR LP coefficient upd 152 */ 284 #define PHY84328_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153 0x00000099 /* TenGBASE_KR LP status report reg 153 */ 285 #define PHY84328_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154 0x0000009a /* TenGBASE_KR LD coefficient upd 154 */ 286 #define PHY84328_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155 0x0000009b /* TenGBASE_KR LD status report reg 155 */ 287 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER 0x000000a0 /* TenGBASE_KX Control register */ 288 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER 0x000000a1 /* TenGBASE_KX Status register */ 289 290 291 /**************************************************************************** 292 * ln_device1_QSFI_AFE_Registers 293 */ 294 #define PHY84328_DEV1_ANAPLLASTATUS 0x0000c050 /* PLL_ana_status */ 295 #define PHY84328_DEV1_ANAPLLACONTROL 0x0000c051 /* PLL_ana_controls */ 296 #define PHY84328_DEV1_ANAPLLATIMER1 0x0000c052 /* PLL_ana_timer1 */ 297 #define PHY84328_DEV1_ANAPLLATIMER2 0x0000c053 /* PLL_ana_timer2 */ 298 #define PHY84328_DEV1_ANAPLLATIMER3 0x0000c054 /* PLL_ana_timer3 */ 299 #define PHY84328_DEV1_ANAPLLCAPCTRL 0x0000c055 /* PLL_ana_CapCtrl */ 300 #define PHY84328_DEV1_ANAPLLAMPCTRL 0x0000c056 /* PLL_ana_AmpCtrl */ 301 #define PHY84328_DEV1_ANAPLLASTATUS1 0x0000c058 /* PLL_ana_status1 */ 302 #define PHY84328_DEV1_ANAPLLACONTROL0 0x0000c059 /* PLL_ana_control0 */ 303 #define PHY84328_DEV1_ANAPLLACONTROL1 0x0000c05a /* PLL_ana_control1 */ 304 #define PHY84328_DEV1_ANAPLLACONTROL2 0x0000c05b /* PLL_ana_control2 */ 305 #define PHY84328_DEV1_ANAPLLACONTROL3 0x0000c05c /* PLL_ana_control3 */ 306 #define PHY84328_DEV1_ANAPLLACONTROL4 0x0000c05d /* PLL_ana_control4 */ 307 #define PHY84328_DEV1_ANAPLLACONTROL5 0x0000c05e /* PLL_ana_control5 */ 308 #define PHY84328_DEV1_ANAPLLACONTROL6 0x0000c05f /* PLL_ana_control6 */ 309 #define PHY84328_DEV1_ANATXASTATUS 0x0000c060 /* Tx_ana_status */ 310 #define PHY84328_DEV1_ANATXACONTROL 0x0000c061 /* Tx_ana_controls */ 311 #define PHY84328_DEV1_ANATXASTATUS1 0x0000c064 /* Tx_ana_status1 */ 312 #define PHY84328_DEV1_ANATXACONTROL1 0x0000c065 /* Tx_ana_control1 */ 313 #define PHY84328_DEV1_ANATXACONTROL2 0x0000c066 /* Tx_ana_control2 */ 314 #define PHY84328_DEV1_ANATXACONTROL3 0x0000c067 /* Tx_ana_control3 */ 315 #define PHY84328_DEV1_ANATXACONTROL4 0x0000c068 /* Tx_ana_control4 */ 316 #define PHY84328_DEV1_ANATXACONTROL5 0x0000c069 /* Tx_ana_control5 */ 317 #define PHY84328_DEV1_ANATXACONTROL6 0x0000c06a /* Tx_ana_control6 */ 318 #define PHY84328_DEV1_ANATXACONTROL7 0x0000c06b /* Tx_ana_control7 */ 319 #define PHY84328_DEV1_ANARXSTATUS 0x0000c0b0 /* Rx lane status register */ 320 #define PHY84328_DEV1_ANARXCONTROL 0x0000c0b1 /* Rx lane control register */ 321 #define PHY84328_DEV1_ANARXSIGDET 0x0000c0b4 /* Rx Sigdet Control */ 322 #define PHY84328_DEV1_ANARXACONTROL4 0x0000c0b5 /* Rx_analog_control_register */ 323 #define PHY84328_DEV1_ANARXCONTROL2 0x0000c0b6 /* Rx 1G Control2 register */ 324 #define PHY84328_DEV1_ANARXCONTROL1 0x0000c0b9 /* Rx 1G Control register */ 325 #define PHY84328_DEV1_ANARXACONTROL1 0x0000c0bc /* Rx_analog_control_register */ 326 #define PHY84328_DEV1_ANARXACONTROL2 0x0000c0bd /* Rx_analog_control_register */ 327 #define PHY84328_DEV1_ANARXACONTROL3 0x0000c0be /* Rx_analog_control_register */ 328 329 330 /**************************************************************************** 331 * ln_device1_QSFI_TXPI_registers 332 */ 333 #define PHY84328_DEV1_TX_PI_CONTROL1 0x0000c460 /* TX_Phase_interpolator_Control_1 Register */ 334 #define PHY84328_DEV1_TX_PI_CONTROL2 0x0000c461 /* TX_Phase_interpolator_Control_2 Register */ 335 #define PHY84328_DEV1_TX_PI_CONTROL3 0x0000c462 /* TX_Phase_interpolator_Control_3 Register */ 336 #define PHY84328_DEV1_TX_PI_CONTROL4 0x0000c463 /* TX_Phase_interpolator_Control_4 Register */ 337 #define PHY84328_DEV1_TX_PI_CONTROL5 0x0000c464 /* TX_Phase_interpolator_Control_5 Register */ 338 #define PHY84328_DEV1_TX_PI_STATUS1 0x0000c465 /* TX_Phase_interpolator_Status_1 Register */ 339 #define PHY84328_DEV1_TX_PI_STATUS2 0x0000c466 /* TX_Phase_interpolator_Status_2 Register */ 340 #define PHY84328_DEV1_TX_PI_STATUS3 0x0000c467 /* TX_Phase_interpolator_Status_3 Register */ 341 #define PHY84328_DEV1_TX_PI_STATUS4 0x0000c468 /* TX_Phase_interpolator_Status_4 Register */ 342 #define PHY84328_DEV1_LLPE_FIFO_CTL 0x0000c469 /* Low_Latency_Phase_Error_FIFO_Control_Register */ 343 #define PHY84328_DEV1_LLPE_FIFO_STS 0x0000c46a /* Low_Latency_Phase_Error_FIFO_Status_Register */ 344 345 346 /**************************************************************************** 347 * ln_device1_QSFI_gpregs 348 */ 349 #define PHY84328_DEV1_GP2_0 0x0000c1d0 /* PLL_Status_register */ 350 #define PHY84328_DEV1_GP2_1 0x0000c1d1 /* Link_status_register */ 351 #define PHY84328_DEV1_GP2_2 0x0000c1d2 /* speed_lane_0_1_register */ 352 #define PHY84328_DEV1_GP2_3 0x0000c1d3 /* speed_lane_2_3_register */ 353 #define PHY84328_DEV1_GP2_4 0x0000c1d4 /* autoneg_status_register */ 354 #define PHY84328_DEV1_GP2_5 0x0000c1d5 /* CL73_BAMStat1_register */ 355 #define PHY84328_DEV1_GP2_6 0x0000c1d6 /* CL73_BAMStat2_register */ 356 #define PHY84328_DEV1_GP2_7 0x0000c1d7 /* CL73_BAMStat3_register */ 357 #define PHY84328_DEV1_GP2_9 0x0000c1d9 /* PRBS_lock_ln0_register */ 358 #define PHY84328_DEV1_GP2_A 0x0000c1da /* PRBS_lock_ln1_register */ 359 #define PHY84328_DEV1_GP2_B 0x0000c1db /* PRBS_lock_ln2_register */ 360 #define PHY84328_DEV1_GP2_C 0x0000c1dc /* PRBS_lock_ln3_register */ 361 362 363 /**************************************************************************** 364 * ln_device1_cl72_user_regs 365 */ 366 #define PHY84328_DEV1_CL72_XMT_CONTROL_REGISTER 0x0000c2e0 /* CL72_TX_Coefficient_Update_Register */ 367 #define PHY84328_DEV1_CL72_RCVD_STATUS_REGISTER 0x0000c2e1 /* CL72_Status_Report_Register */ 368 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER 0x0000c2e2 /* CL72_TX_FIR_Tap_Register */ 369 #define PHY84328_DEV1_CL72_MISC1_CONTROL 0x0000c2e3 /* CL72_Miscellaneous_1_Control_Register */ 370 #define PHY84328_DEV1_CL72_MISC2_CONTROL 0x0000c2e4 /* CL72_Miscellaneous_2_Control_Register */ 371 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL 0x0000c2e5 /* CL7_ KR_Default_Control_Register */ 372 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL 0x0000c2e6 /* CL72_OS_Default_Control_Register */ 373 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL 0x0000c2e7 /* CL72_BR_Defaul_Control_Register */ 374 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL 0x0000c2e9 /* CL72_Tap_Limit_Control_Register */ 375 #define PHY84328_DEV1_CL72_MISC3_CONTROL 0x0000c2ea /* CL72_Miscellaneous_3_Control_Register */ 376 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL 0x0000c2eb /* CL72_Tap_Present_Control_Register */ 377 #define PHY84328_DEV1_CL72_MISC4_CONTROL 0x0000c2ec /* CL72_Miscellaneous_4_Control_Register */ 378 #define PHY84328_DEV1_CL72_FAULT_REGISTER 0x0000c2f9 /* CL72_Fault_Register */ 379 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER 0x0000c2fb /* CL72_Debug_1_Register */ 380 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER 0x0000c2fc /* CL72_Debug_2_Register */ 381 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER 0x0000c2fd /* CL72_Debug_3_Register */ 382 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER 0x0000c2fe /* CL72_Debug_4_Register */ 383 384 385 /**************************************************************************** 386 * ln_device1_userLanesCtrl_Registers 387 */ 388 #define PHY84328_DEV1_XGXSCONTROL 0x0000c000 /* XGXS control register */ 389 #define PHY84328_DEV1_XGXSSTATUS 0x0000c001 /* XGXS status register */ 390 #define PHY84328_DEV1_MISCCONTROL1 0x0000c00e /* Miscellaneous control 1 register */ 391 #define PHY84328_DEV1_LANECTRL2 0x0000c017 /* Lane control 2 register */ 392 #define PHY84328_DEV1_LANECTRL3 0x0000c018 /* Lane control 3 register */ 393 #define PHY84328_DEV1_LANEPRBS 0x0000c019 /* Lane PRBS control register */ 394 #define PHY84328_DEV1_LANECTRL 0x0000c01a /* Lane control register */ 395 #define PHY84328_DEV1_TESTMODELANE 0x0000c106 /* Test_mode_lane_select_register */ 396 #define PHY84328_DEV1_LANERESET 0x0000c10a /* Lane reset register */ 397 #define PHY84328_DEV1_XFICONTROL 0x0000c10c /* XFI Control register */ 398 #define PHY84328_DEV1_CL73CONTROL7 0x0000c160 /* CL73 Control 7 Register */ 399 #define PHY84328_DEV1_CL73CONTROL8 0x0000c161 /* CL73 Control 8 Register */ 400 #define PHY84328_DEV1_CL73CONTROL9 0x0000c162 /* CL73 Control 9 Register */ 401 #define PHY84328_DEV1_CL73CONTROL10 0x0000c163 /* CL73 Control 10 Register */ 402 #define PHY84328_DEV1_XFI_AFE_CTL1 0x0000c191 /* XFI AFE Control1 Register */ 403 #define PHY84328_DEV1_XFI_AFE_CTL2 0x0000c192 /* XFI AFE Control2 Registe */ 404 405 406 /**************************************************************************** 407 * ln_device1_Common_Controller 408 */ 409 /**************************************************************************** 410 * ln_device1 :: regualtor_ctrl 411 */ 412 /* ln_device1 :: regualtor_ctrl :: reserved0 [15:15] */ 413 #define PHY84328_DEV1_REGUALTOR_CTRL_RESERVED0_MASK 0x8000 414 #define PHY84328_DEV1_REGUALTOR_CTRL_RESERVED0_ALIGN 0 415 #define PHY84328_DEV1_REGUALTOR_CTRL_RESERVED0_BITS 1 416 #define PHY84328_DEV1_REGUALTOR_CTRL_RESERVED0_SHIFT 15 417 418 /* ln_device1 :: regualtor_ctrl :: vregcntl_en [14:14] */ 419 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCNTL_EN_MASK 0x4000 420 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCNTL_EN_ALIGN 0 421 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCNTL_EN_BITS 1 422 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCNTL_EN_SHIFT 14 423 424 /* ln_device1 :: regualtor_ctrl :: pwrdn [13:13] */ 425 #define PHY84328_DEV1_REGUALTOR_CTRL_PWRDN_MASK 0x2000 426 #define PHY84328_DEV1_REGUALTOR_CTRL_PWRDN_ALIGN 0 427 #define PHY84328_DEV1_REGUALTOR_CTRL_PWRDN_BITS 1 428 #define PHY84328_DEV1_REGUALTOR_CTRL_PWRDN_SHIFT 13 429 430 /* ln_device1 :: regualtor_ctrl :: vregctl_100kohm [12:12] */ 431 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_100KOHM_MASK 0x1000 432 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_100KOHM_ALIGN 0 433 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_100KOHM_BITS 1 434 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_100KOHM_SHIFT 12 435 436 /* ln_device1 :: regualtor_ctrl :: vregctl_Rpole_tuning [11:10] */ 437 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_RPOLE_TUNING_MASK 0x0c00 438 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_RPOLE_TUNING_ALIGN 0 439 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_RPOLE_TUNING_BITS 2 440 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_RPOLE_TUNING_SHIFT 10 441 442 /* ln_device1 :: regualtor_ctrl :: vregctl_output_voltage_ctrl [09:09] */ 443 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_OUTPUT_VOLTAGE_CTRL_MASK 0x0200 444 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_OUTPUT_VOLTAGE_CTRL_ALIGN 0 445 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_OUTPUT_VOLTAGE_CTRL_BITS 1 446 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_OUTPUT_VOLTAGE_CTRL_SHIFT 9 447 448 /* ln_device1 :: regualtor_ctrl :: reserved1 [08:08] */ 449 #define PHY84328_DEV1_REGUALTOR_CTRL_RESERVED1_MASK 0x0100 450 #define PHY84328_DEV1_REGUALTOR_CTRL_RESERVED1_ALIGN 0 451 #define PHY84328_DEV1_REGUALTOR_CTRL_RESERVED1_BITS 1 452 #define PHY84328_DEV1_REGUALTOR_CTRL_RESERVED1_SHIFT 8 453 454 /* ln_device1 :: regualtor_ctrl :: vregctl_Ovolt_tuning [07:04] */ 455 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_OVOLT_TUNING_MASK 0x00f0 456 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_OVOLT_TUNING_ALIGN 0 457 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_OVOLT_TUNING_BITS 4 458 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_OVOLT_TUNING_SHIFT 4 459 460 /* ln_device1 :: regualtor_ctrl :: vregctl_Bg_tuning [03:00] */ 461 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_BG_TUNING_MASK 0x000f 462 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_BG_TUNING_ALIGN 0 463 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_BG_TUNING_BITS 4 464 #define PHY84328_DEV1_REGUALTOR_CTRL_VREGCTL_BG_TUNING_SHIFT 0 465 466 467 /**************************************************************************** 468 * ln_device1 :: gen_ctrl 469 */ 470 /* ln_device1 :: gen_ctrl :: m51_i2c_wr_ctrl [15:12] */ 471 #define PHY84328_DEV1_GEN_CTRL_M51_I2C_WR_CTRL_MASK 0xf000 472 #define PHY84328_DEV1_GEN_CTRL_M51_I2C_WR_CTRL_ALIGN 0 473 #define PHY84328_DEV1_GEN_CTRL_M51_I2C_WR_CTRL_BITS 4 474 #define PHY84328_DEV1_GEN_CTRL_M51_I2C_WR_CTRL_SHIFT 12 475 476 /* ln_device1 :: gen_ctrl :: reserved0 [11:09] */ 477 #define PHY84328_DEV1_GEN_CTRL_RESERVED0_MASK 0x0e00 478 #define PHY84328_DEV1_GEN_CTRL_RESERVED0_ALIGN 0 479 #define PHY84328_DEV1_GEN_CTRL_RESERVED0_BITS 3 480 #define PHY84328_DEV1_GEN_CTRL_RESERVED0_SHIFT 9 481 482 /* ln_device1 :: gen_ctrl :: uc_refclk_sel [08:08] */ 483 #define PHY84328_DEV1_GEN_CTRL_UC_REFCLK_SEL_MASK 0x0100 484 #define PHY84328_DEV1_GEN_CTRL_UC_REFCLK_SEL_ALIGN 0 485 #define PHY84328_DEV1_GEN_CTRL_UC_REFCLK_SEL_BITS 1 486 #define PHY84328_DEV1_GEN_CTRL_UC_REFCLK_SEL_SHIFT 8 487 488 /* ln_device1 :: gen_ctrl :: reserved1 [07:07] */ 489 #define PHY84328_DEV1_GEN_CTRL_RESERVED1_MASK 0x0080 490 #define PHY84328_DEV1_GEN_CTRL_RESERVED1_ALIGN 0 491 #define PHY84328_DEV1_GEN_CTRL_RESERVED1_BITS 1 492 #define PHY84328_DEV1_GEN_CTRL_RESERVED1_SHIFT 7 493 494 /* ln_device1 :: gen_ctrl :: ucclksel_speed_sel [06:06] */ 495 #define PHY84328_DEV1_GEN_CTRL_UCCLKSEL_SPEED_SEL_MASK 0x0040 496 #define PHY84328_DEV1_GEN_CTRL_UCCLKSEL_SPEED_SEL_ALIGN 0 497 #define PHY84328_DEV1_GEN_CTRL_UCCLKSEL_SPEED_SEL_BITS 1 498 #define PHY84328_DEV1_GEN_CTRL_UCCLKSEL_SPEED_SEL_SHIFT 6 499 500 /* ln_device1 :: gen_ctrl :: reserved2 [05:03] */ 501 #define PHY84328_DEV1_GEN_CTRL_RESERVED2_MASK 0x0038 502 #define PHY84328_DEV1_GEN_CTRL_RESERVED2_ALIGN 0 503 #define PHY84328_DEV1_GEN_CTRL_RESERVED2_BITS 3 504 #define PHY84328_DEV1_GEN_CTRL_RESERVED2_SHIFT 3 505 506 /* ln_device1 :: gen_ctrl :: ucrst [02:02] */ 507 #define PHY84328_DEV1_GEN_CTRL_UCRST_MASK 0x0004 508 #define PHY84328_DEV1_GEN_CTRL_UCRST_ALIGN 0 509 #define PHY84328_DEV1_GEN_CTRL_UCRST_BITS 1 510 #define PHY84328_DEV1_GEN_CTRL_UCRST_SHIFT 2 511 512 /* ln_device1 :: gen_ctrl :: reserved3 [01:00] */ 513 #define PHY84328_DEV1_GEN_CTRL_RESERVED3_MASK 0x0003 514 #define PHY84328_DEV1_GEN_CTRL_RESERVED3_ALIGN 0 515 #define PHY84328_DEV1_GEN_CTRL_RESERVED3_BITS 2 516 #define PHY84328_DEV1_GEN_CTRL_RESERVED3_SHIFT 0 517 518 519 /**************************************************************************** 520 * ln_device1 :: ram_lwpr_ctrl 521 */ 522 /* ln_device1 :: ram_lwpr_ctrl :: RAM_LWPR_CTRL [15:08] */ 523 #define PHY84328_DEV1_RAM_LWPR_CTRL_RAM_LWPR_CTRL_MASK 0xff00 524 #define PHY84328_DEV1_RAM_LWPR_CTRL_RAM_LWPR_CTRL_ALIGN 0 525 #define PHY84328_DEV1_RAM_LWPR_CTRL_RAM_LWPR_CTRL_BITS 8 526 #define PHY84328_DEV1_RAM_LWPR_CTRL_RAM_LWPR_CTRL_SHIFT 8 527 528 /* ln_device1 :: ram_lwpr_ctrl :: reserved0 [07:00] */ 529 #define PHY84328_DEV1_RAM_LWPR_CTRL_RESERVED0_MASK 0x00ff 530 #define PHY84328_DEV1_RAM_LWPR_CTRL_RESERVED0_ALIGN 0 531 #define PHY84328_DEV1_RAM_LWPR_CTRL_RESERVED0_BITS 8 532 #define PHY84328_DEV1_RAM_LWPR_CTRL_RESERVED0_SHIFT 0 533 534 535 /**************************************************************************** 536 * ln_device1 :: msg_in 537 */ 538 /* ln_device1 :: msg_in :: message_in [15:00] */ 539 #define PHY84328_DEV1_MSG_IN_MESSAGE_IN_MASK 0xffff 540 #define PHY84328_DEV1_MSG_IN_MESSAGE_IN_ALIGN 0 541 #define PHY84328_DEV1_MSG_IN_MESSAGE_IN_BITS 16 542 #define PHY84328_DEV1_MSG_IN_MESSAGE_IN_SHIFT 0 543 544 545 /**************************************************************************** 546 * ln_device1 :: msg_out 547 */ 548 /* ln_device1 :: msg_out :: message_out [15:00] */ 549 #define PHY84328_DEV1_MSG_OUT_MESSAGE_OUT_MASK 0xffff 550 #define PHY84328_DEV1_MSG_OUT_MESSAGE_OUT_ALIGN 0 551 #define PHY84328_DEV1_MSG_OUT_MESSAGE_OUT_BITS 16 552 #define PHY84328_DEV1_MSG_OUT_MESSAGE_OUT_SHIFT 0 553 554 555 /**************************************************************************** 556 * ln_device1 :: errored_sram_address 557 */ 558 /* ln_device1 :: errored_sram_address :: current_sram_address [15:00] */ 559 #define PHY84328_DEV1_ERRORED_SRAM_ADDRESS_CURRENT_SRAM_ADDRESS_MASK 0xffff 560 #define PHY84328_DEV1_ERRORED_SRAM_ADDRESS_CURRENT_SRAM_ADDRESS_ALIGN 0 561 #define PHY84328_DEV1_ERRORED_SRAM_ADDRESS_CURRENT_SRAM_ADDRESS_BITS 16 562 #define PHY84328_DEV1_ERRORED_SRAM_ADDRESS_CURRENT_SRAM_ADDRESS_SHIFT 0 563 564 565 /**************************************************************************** 566 * ln_device1 :: errored_sram_data 567 */ 568 /* ln_device1 :: errored_sram_data :: Uncorrectable_Low_Mem_Error [15:15] */ 569 #define PHY84328_DEV1_ERRORED_SRAM_DATA_UNCORRECTABLE_LOW_MEM_ERROR_MASK 0x8000 570 #define PHY84328_DEV1_ERRORED_SRAM_DATA_UNCORRECTABLE_LOW_MEM_ERROR_ALIGN 0 571 #define PHY84328_DEV1_ERRORED_SRAM_DATA_UNCORRECTABLE_LOW_MEM_ERROR_BITS 1 572 #define PHY84328_DEV1_ERRORED_SRAM_DATA_UNCORRECTABLE_LOW_MEM_ERROR_SHIFT 15 573 574 /* ln_device1 :: errored_sram_data :: Low_Mem_Error_Corrected [14:14] */ 575 #define PHY84328_DEV1_ERRORED_SRAM_DATA_LOW_MEM_ERROR_CORRECTED_MASK 0x4000 576 #define PHY84328_DEV1_ERRORED_SRAM_DATA_LOW_MEM_ERROR_CORRECTED_ALIGN 0 577 #define PHY84328_DEV1_ERRORED_SRAM_DATA_LOW_MEM_ERROR_CORRECTED_BITS 1 578 #define PHY84328_DEV1_ERRORED_SRAM_DATA_LOW_MEM_ERROR_CORRECTED_SHIFT 14 579 580 /* ln_device1 :: errored_sram_data :: Uncorrectable_High_Mem_Error [13:13] */ 581 #define PHY84328_DEV1_ERRORED_SRAM_DATA_UNCORRECTABLE_HIGH_MEM_ERROR_MASK 0x2000 582 #define PHY84328_DEV1_ERRORED_SRAM_DATA_UNCORRECTABLE_HIGH_MEM_ERROR_ALIGN 0 583 #define PHY84328_DEV1_ERRORED_SRAM_DATA_UNCORRECTABLE_HIGH_MEM_ERROR_BITS 1 584 #define PHY84328_DEV1_ERRORED_SRAM_DATA_UNCORRECTABLE_HIGH_MEM_ERROR_SHIFT 13 585 586 /* ln_device1 :: errored_sram_data :: High_Mem_Error_Corrected [12:12] */ 587 #define PHY84328_DEV1_ERRORED_SRAM_DATA_HIGH_MEM_ERROR_CORRECTED_MASK 0x1000 588 #define PHY84328_DEV1_ERRORED_SRAM_DATA_HIGH_MEM_ERROR_CORRECTED_ALIGN 0 589 #define PHY84328_DEV1_ERRORED_SRAM_DATA_HIGH_MEM_ERROR_CORRECTED_BITS 1 590 #define PHY84328_DEV1_ERRORED_SRAM_DATA_HIGH_MEM_ERROR_CORRECTED_SHIFT 12 591 592 /* ln_device1 :: errored_sram_data :: reserved0 [11:10] */ 593 #define PHY84328_DEV1_ERRORED_SRAM_DATA_RESERVED0_MASK 0x0c00 594 #define PHY84328_DEV1_ERRORED_SRAM_DATA_RESERVED0_ALIGN 0 595 #define PHY84328_DEV1_ERRORED_SRAM_DATA_RESERVED0_BITS 2 596 #define PHY84328_DEV1_ERRORED_SRAM_DATA_RESERVED0_SHIFT 10 597 598 /* ln_device1 :: errored_sram_data :: Mem_Error_Corrected_8051_interrupt_mask [09:09] */ 599 #define PHY84328_DEV1_ERRORED_SRAM_DATA_MEM_ERROR_CORRECTED_8051_INTERRUPT_MASK_MASK 0x0200 600 #define PHY84328_DEV1_ERRORED_SRAM_DATA_MEM_ERROR_CORRECTED_8051_INTERRUPT_MASK_ALIGN 0 601 #define PHY84328_DEV1_ERRORED_SRAM_DATA_MEM_ERROR_CORRECTED_8051_INTERRUPT_MASK_BITS 1 602 #define PHY84328_DEV1_ERRORED_SRAM_DATA_MEM_ERROR_CORRECTED_8051_INTERRUPT_MASK_SHIFT 9 603 604 /* ln_device1 :: errored_sram_data :: Mem_Error_Uncorrected_8051_interrupt_mask [08:08] */ 605 #define PHY84328_DEV1_ERRORED_SRAM_DATA_MEM_ERROR_UNCORRECTED_8051_INTERRUPT_MASK_MASK 0x0100 606 #define PHY84328_DEV1_ERRORED_SRAM_DATA_MEM_ERROR_UNCORRECTED_8051_INTERRUPT_MASK_ALIGN 0 607 #define PHY84328_DEV1_ERRORED_SRAM_DATA_MEM_ERROR_UNCORRECTED_8051_INTERRUPT_MASK_BITS 1 608 #define PHY84328_DEV1_ERRORED_SRAM_DATA_MEM_ERROR_UNCORRECTED_8051_INTERRUPT_MASK_SHIFT 8 609 610 /* ln_device1 :: errored_sram_data :: current_sram_data [07:00] */ 611 #define PHY84328_DEV1_ERRORED_SRAM_DATA_CURRENT_SRAM_DATA_MASK 0x00ff 612 #define PHY84328_DEV1_ERRORED_SRAM_DATA_CURRENT_SRAM_DATA_ALIGN 0 613 #define PHY84328_DEV1_ERRORED_SRAM_DATA_CURRENT_SRAM_DATA_BITS 8 614 #define PHY84328_DEV1_ERRORED_SRAM_DATA_CURRENT_SRAM_DATA_SHIFT 0 615 616 617 /**************************************************************************** 618 * ln_device1 :: gp_reg_0 619 */ 620 /* ln_device1 :: gp_reg_0 :: Enable_line_3_0 [15:12] */ 621 #define PHY84328_DEV1_GP_REG_0_ENABLE_LINE_3_0_MASK 0xf000 622 #define PHY84328_DEV1_GP_REG_0_ENABLE_LINE_3_0_ALIGN 0 623 #define PHY84328_DEV1_GP_REG_0_ENABLE_LINE_3_0_BITS 4 624 #define PHY84328_DEV1_GP_REG_0_ENABLE_LINE_3_0_SHIFT 12 625 626 /* ln_device1 :: gp_reg_0 :: Enable_system_3_0 [11:08] */ 627 #define PHY84328_DEV1_GP_REG_0_ENABLE_SYSTEM_3_0_MASK 0x0f00 628 #define PHY84328_DEV1_GP_REG_0_ENABLE_SYSTEM_3_0_ALIGN 0 629 #define PHY84328_DEV1_GP_REG_0_ENABLE_SYSTEM_3_0_BITS 4 630 #define PHY84328_DEV1_GP_REG_0_ENABLE_SYSTEM_3_0_SHIFT 8 631 632 /* ln_device1 :: gp_reg_0 :: gpreg0_data_7_5 [07:05] */ 633 #define PHY84328_DEV1_GP_REG_0_GPREG0_DATA_7_5_MASK 0x00e0 634 #define PHY84328_DEV1_GP_REG_0_GPREG0_DATA_7_5_ALIGN 0 635 #define PHY84328_DEV1_GP_REG_0_GPREG0_DATA_7_5_BITS 3 636 #define PHY84328_DEV1_GP_REG_0_GPREG0_DATA_7_5_SHIFT 5 637 638 /* ln_device1 :: gp_reg_0 :: ULL_datapath_latency [04:04] */ 639 #define PHY84328_DEV1_GP_REG_0_ULL_DATAPATH_LATENCY_MASK 0x0010 640 #define PHY84328_DEV1_GP_REG_0_ULL_DATAPATH_LATENCY_ALIGN 0 641 #define PHY84328_DEV1_GP_REG_0_ULL_DATAPATH_LATENCY_BITS 1 642 #define PHY84328_DEV1_GP_REG_0_ULL_DATAPATH_LATENCY_SHIFT 4 643 644 /* ln_device1 :: gp_reg_0 :: Enable_ultra_low_latency_datapath [03:03] */ 645 #define PHY84328_DEV1_GP_REG_0_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_MASK 0x0008 646 #define PHY84328_DEV1_GP_REG_0_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_ALIGN 0 647 #define PHY84328_DEV1_GP_REG_0_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_BITS 1 648 #define PHY84328_DEV1_GP_REG_0_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_SHIFT 3 649 650 /* ln_device1 :: gp_reg_0 :: i2c_operation_in_progress [02:02] */ 651 #define PHY84328_DEV1_GP_REG_0_I2C_OPERATION_IN_PROGRESS_MASK 0x0004 652 #define PHY84328_DEV1_GP_REG_0_I2C_OPERATION_IN_PROGRESS_ALIGN 0 653 #define PHY84328_DEV1_GP_REG_0_I2C_OPERATION_IN_PROGRESS_BITS 1 654 #define PHY84328_DEV1_GP_REG_0_I2C_OPERATION_IN_PROGRESS_SHIFT 2 655 656 /* ln_device1 :: gp_reg_0 :: Enable_QSFP_Mod_detect [01:01] */ 657 #define PHY84328_DEV1_GP_REG_0_ENABLE_QSFP_MOD_DETECT_MASK 0x0002 658 #define PHY84328_DEV1_GP_REG_0_ENABLE_QSFP_MOD_DETECT_ALIGN 0 659 #define PHY84328_DEV1_GP_REG_0_ENABLE_QSFP_MOD_DETECT_BITS 1 660 #define PHY84328_DEV1_GP_REG_0_ENABLE_QSFP_MOD_DETECT_SHIFT 1 661 662 /* ln_device1 :: gp_reg_0 :: Enable_SFP_Mod_detect [00:00] */ 663 #define PHY84328_DEV1_GP_REG_0_ENABLE_SFP_MOD_DETECT_MASK 0x0001 664 #define PHY84328_DEV1_GP_REG_0_ENABLE_SFP_MOD_DETECT_ALIGN 0 665 #define PHY84328_DEV1_GP_REG_0_ENABLE_SFP_MOD_DETECT_BITS 1 666 #define PHY84328_DEV1_GP_REG_0_ENABLE_SFP_MOD_DETECT_SHIFT 0 667 668 669 /**************************************************************************** 670 * ln_device1 :: gp_reg_1 671 */ 672 /* ln_device1 :: gp_reg_1 :: System_LR_mode [15:15] */ 673 #define PHY84328_DEV1_GP_REG_1_SYSTEM_LR_MODE_MASK 0x8000 674 #define PHY84328_DEV1_GP_REG_1_SYSTEM_LR_MODE_ALIGN 0 675 #define PHY84328_DEV1_GP_REG_1_SYSTEM_LR_MODE_BITS 1 676 #define PHY84328_DEV1_GP_REG_1_SYSTEM_LR_MODE_SHIFT 15 677 678 /* ln_device1 :: gp_reg_1 :: Line_LR_mode [14:14] */ 679 #define PHY84328_DEV1_GP_REG_1_LINE_LR_MODE_MASK 0x4000 680 #define PHY84328_DEV1_GP_REG_1_LINE_LR_MODE_ALIGN 0 681 #define PHY84328_DEV1_GP_REG_1_LINE_LR_MODE_BITS 1 682 #define PHY84328_DEV1_GP_REG_1_LINE_LR_MODE_SHIFT 14 683 684 /* ln_device1 :: gp_reg_1 :: System_Forced_CL72_mode [13:13] */ 685 #define PHY84328_DEV1_GP_REG_1_SYSTEM_FORCED_CL72_MODE_MASK 0x2000 686 #define PHY84328_DEV1_GP_REG_1_SYSTEM_FORCED_CL72_MODE_ALIGN 0 687 #define PHY84328_DEV1_GP_REG_1_SYSTEM_FORCED_CL72_MODE_BITS 1 688 #define PHY84328_DEV1_GP_REG_1_SYSTEM_FORCED_CL72_MODE_SHIFT 13 689 690 /* ln_device1 :: gp_reg_1 :: Line_Forced_CL72_mode [12:12] */ 691 #define PHY84328_DEV1_GP_REG_1_LINE_FORCED_CL72_MODE_MASK 0x1000 692 #define PHY84328_DEV1_GP_REG_1_LINE_FORCED_CL72_MODE_ALIGN 0 693 #define PHY84328_DEV1_GP_REG_1_LINE_FORCED_CL72_MODE_BITS 1 694 #define PHY84328_DEV1_GP_REG_1_LINE_FORCED_CL72_MODE_SHIFT 12 695 696 /* ln_device1 :: gp_reg_1 :: System_Cu_Type [11:11] */ 697 #define PHY84328_DEV1_GP_REG_1_SYSTEM_CU_TYPE_MASK 0x0800 698 #define PHY84328_DEV1_GP_REG_1_SYSTEM_CU_TYPE_ALIGN 0 699 #define PHY84328_DEV1_GP_REG_1_SYSTEM_CU_TYPE_BITS 1 700 #define PHY84328_DEV1_GP_REG_1_SYSTEM_CU_TYPE_SHIFT 11 701 702 /* ln_device1 :: gp_reg_1 :: System_Type [10:10] */ 703 #define PHY84328_DEV1_GP_REG_1_SYSTEM_TYPE_MASK 0x0400 704 #define PHY84328_DEV1_GP_REG_1_SYSTEM_TYPE_ALIGN 0 705 #define PHY84328_DEV1_GP_REG_1_SYSTEM_TYPE_BITS 1 706 #define PHY84328_DEV1_GP_REG_1_SYSTEM_TYPE_SHIFT 10 707 708 /* ln_device1 :: gp_reg_1 :: Line_Cu_Type [09:09] */ 709 #define PHY84328_DEV1_GP_REG_1_LINE_CU_TYPE_MASK 0x0200 710 #define PHY84328_DEV1_GP_REG_1_LINE_CU_TYPE_ALIGN 0 711 #define PHY84328_DEV1_GP_REG_1_LINE_CU_TYPE_BITS 1 712 #define PHY84328_DEV1_GP_REG_1_LINE_CU_TYPE_SHIFT 9 713 714 /* ln_device1 :: gp_reg_1 :: Line_Type [08:08] */ 715 #define PHY84328_DEV1_GP_REG_1_LINE_TYPE_MASK 0x0100 716 #define PHY84328_DEV1_GP_REG_1_LINE_TYPE_ALIGN 0 717 #define PHY84328_DEV1_GP_REG_1_LINE_TYPE_BITS 1 718 #define PHY84328_DEV1_GP_REG_1_LINE_TYPE_SHIFT 8 719 720 /* ln_device1 :: gp_reg_1 :: finish_change [07:07] */ 721 #define PHY84328_DEV1_GP_REG_1_FINISH_CHANGE_MASK 0x0080 722 #define PHY84328_DEV1_GP_REG_1_FINISH_CHANGE_ALIGN 0 723 #define PHY84328_DEV1_GP_REG_1_FINISH_CHANGE_BITS 1 724 #define PHY84328_DEV1_GP_REG_1_FINISH_CHANGE_SHIFT 7 725 726 /* ln_device1 :: gp_reg_1 :: Type_change [06:06] */ 727 #define PHY84328_DEV1_GP_REG_1_TYPE_CHANGE_MASK 0x0040 728 #define PHY84328_DEV1_GP_REG_1_TYPE_CHANGE_ALIGN 0 729 #define PHY84328_DEV1_GP_REG_1_TYPE_CHANGE_BITS 1 730 #define PHY84328_DEV1_GP_REG_1_TYPE_CHANGE_SHIFT 6 731 732 /* ln_device1 :: gp_reg_1 :: Speed_change [05:05] */ 733 #define PHY84328_DEV1_GP_REG_1_SPEED_CHANGE_MASK 0x0020 734 #define PHY84328_DEV1_GP_REG_1_SPEED_CHANGE_ALIGN 0 735 #define PHY84328_DEV1_GP_REG_1_SPEED_CHANGE_BITS 1 736 #define PHY84328_DEV1_GP_REG_1_SPEED_CHANGE_SHIFT 5 737 738 /* ln_device1 :: gp_reg_1 :: Speed_or_Type_change [04:04] */ 739 #define PHY84328_DEV1_GP_REG_1_SPEED_OR_TYPE_CHANGE_MASK 0x0010 740 #define PHY84328_DEV1_GP_REG_1_SPEED_OR_TYPE_CHANGE_ALIGN 0 741 #define PHY84328_DEV1_GP_REG_1_SPEED_OR_TYPE_CHANGE_BITS 1 742 #define PHY84328_DEV1_GP_REG_1_SPEED_OR_TYPE_CHANGE_SHIFT 4 743 744 /* ln_device1 :: gp_reg_1 :: Speed_100G [03:03] */ 745 #define PHY84328_DEV1_GP_REG_1_SPEED_100G_MASK 0x0008 746 #define PHY84328_DEV1_GP_REG_1_SPEED_100G_ALIGN 0 747 #define PHY84328_DEV1_GP_REG_1_SPEED_100G_BITS 1 748 #define PHY84328_DEV1_GP_REG_1_SPEED_100G_SHIFT 3 749 750 /* ln_device1 :: gp_reg_1 :: Speed_40G [02:02] */ 751 #define PHY84328_DEV1_GP_REG_1_SPEED_40G_MASK 0x0004 752 #define PHY84328_DEV1_GP_REG_1_SPEED_40G_ALIGN 0 753 #define PHY84328_DEV1_GP_REG_1_SPEED_40G_BITS 1 754 #define PHY84328_DEV1_GP_REG_1_SPEED_40G_SHIFT 2 755 756 /* ln_device1 :: gp_reg_1 :: Speed_10G [01:01] */ 757 #define PHY84328_DEV1_GP_REG_1_SPEED_10G_MASK 0x0002 758 #define PHY84328_DEV1_GP_REG_1_SPEED_10G_ALIGN 0 759 #define PHY84328_DEV1_GP_REG_1_SPEED_10G_BITS 1 760 #define PHY84328_DEV1_GP_REG_1_SPEED_10G_SHIFT 1 761 762 /* ln_device1 :: gp_reg_1 :: Speed_1G [00:00] */ 763 #define PHY84328_DEV1_GP_REG_1_SPEED_1G_MASK 0x0001 764 #define PHY84328_DEV1_GP_REG_1_SPEED_1G_ALIGN 0 765 #define PHY84328_DEV1_GP_REG_1_SPEED_1G_BITS 1 766 #define PHY84328_DEV1_GP_REG_1_SPEED_1G_SHIFT 0 767 768 769 /**************************************************************************** 770 * ln_device1 :: gp_reg_2 771 */ 772 /* ln_device1 :: gp_reg_2 :: gpreg2_data [15:00] */ 773 #define PHY84328_DEV1_GP_REG_2_GPREG2_DATA_MASK 0xffff 774 #define PHY84328_DEV1_GP_REG_2_GPREG2_DATA_ALIGN 0 775 #define PHY84328_DEV1_GP_REG_2_GPREG2_DATA_BITS 16 776 #define PHY84328_DEV1_GP_REG_2_GPREG2_DATA_SHIFT 0 777 778 779 /**************************************************************************** 780 * ln_device1 :: gp_reg_3 781 */ 782 /* ln_device1 :: gp_reg_3 :: gpreg3_data [15:00] */ 783 #define PHY84328_DEV1_GP_REG_3_GPREG3_DATA_MASK 0xffff 784 #define PHY84328_DEV1_GP_REG_3_GPREG3_DATA_ALIGN 0 785 #define PHY84328_DEV1_GP_REG_3_GPREG3_DATA_BITS 16 786 #define PHY84328_DEV1_GP_REG_3_GPREG3_DATA_SHIFT 0 787 788 789 /**************************************************************************** 790 * ln_device1 :: gp_reg_4 791 */ 792 /* ln_device1 :: gp_reg_4 :: gpreg4_data [15:00] */ 793 #define PHY84328_DEV1_GP_REG_4_GPREG4_DATA_MASK 0xffff 794 #define PHY84328_DEV1_GP_REG_4_GPREG4_DATA_ALIGN 0 795 #define PHY84328_DEV1_GP_REG_4_GPREG4_DATA_BITS 16 796 #define PHY84328_DEV1_GP_REG_4_GPREG4_DATA_SHIFT 0 797 798 799 /**************************************************************************** 800 * ln_device1 :: logad_ctrl 801 */ 802 /* ln_device1 :: logad_ctrl :: reserved0 [15:08] */ 803 #define PHY84328_DEV1_LOGAD_CTRL_RESERVED0_MASK 0xff00 804 #define PHY84328_DEV1_LOGAD_CTRL_RESERVED0_ALIGN 0 805 #define PHY84328_DEV1_LOGAD_CTRL_RESERVED0_BITS 8 806 #define PHY84328_DEV1_LOGAD_CTRL_RESERVED0_SHIFT 8 807 808 /* ln_device1 :: logad_ctrl :: Logical_ch_numbering_4_physical_ch3 [07:06] */ 809 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH3_MASK 0x00c0 810 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH3_ALIGN 0 811 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH3_BITS 2 812 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH3_SHIFT 6 813 814 /* ln_device1 :: logad_ctrl :: Logical_ch_numbering_4_physical_ch2 [05:04] */ 815 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH2_MASK 0x0030 816 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH2_ALIGN 0 817 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH2_BITS 2 818 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH2_SHIFT 4 819 820 /* ln_device1 :: logad_ctrl :: Logical_ch_numbering_4_physical_ch1 [03:02] */ 821 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH1_MASK 0x000c 822 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH1_ALIGN 0 823 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH1_BITS 2 824 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH1_SHIFT 2 825 826 /* ln_device1 :: logad_ctrl :: Logical_ch_numbering_4_physical_ch0 [01:00] */ 827 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH0_MASK 0x0003 828 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH0_ALIGN 0 829 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH0_BITS 2 830 #define PHY84328_DEV1_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH0_SHIFT 0 831 832 833 /**************************************************************************** 834 * ln_device1 :: sw_reset_ctrl 835 */ 836 /* ln_device1 :: sw_reset_ctrl :: reserved0 [15:03] */ 837 #define PHY84328_DEV1_SW_RESET_CTRL_RESERVED0_MASK 0xfff8 838 #define PHY84328_DEV1_SW_RESET_CTRL_RESERVED0_ALIGN 0 839 #define PHY84328_DEV1_SW_RESET_CTRL_RESERVED0_BITS 13 840 #define PHY84328_DEV1_SW_RESET_CTRL_RESERVED0_SHIFT 3 841 842 /* ln_device1 :: sw_reset_ctrl :: i2c_master_blk_sw_rst [02:02] */ 843 #define PHY84328_DEV1_SW_RESET_CTRL_I2C_MASTER_BLK_SW_RST_MASK 0x0004 844 #define PHY84328_DEV1_SW_RESET_CTRL_I2C_MASTER_BLK_SW_RST_ALIGN 0 845 #define PHY84328_DEV1_SW_RESET_CTRL_I2C_MASTER_BLK_SW_RST_BITS 1 846 #define PHY84328_DEV1_SW_RESET_CTRL_I2C_MASTER_BLK_SW_RST_SHIFT 2 847 848 /* ln_device1 :: sw_reset_ctrl :: i2c_slave_blk_sw_rst [01:01] */ 849 #define PHY84328_DEV1_SW_RESET_CTRL_I2C_SLAVE_BLK_SW_RST_MASK 0x0002 850 #define PHY84328_DEV1_SW_RESET_CTRL_I2C_SLAVE_BLK_SW_RST_ALIGN 0 851 #define PHY84328_DEV1_SW_RESET_CTRL_I2C_SLAVE_BLK_SW_RST_BITS 1 852 #define PHY84328_DEV1_SW_RESET_CTRL_I2C_SLAVE_BLK_SW_RST_SHIFT 1 853 854 /* ln_device1 :: sw_reset_ctrl :: reserved1 [00:00] */ 855 #define PHY84328_DEV1_SW_RESET_CTRL_RESERVED1_MASK 0x0001 856 #define PHY84328_DEV1_SW_RESET_CTRL_RESERVED1_ALIGN 0 857 #define PHY84328_DEV1_SW_RESET_CTRL_RESERVED1_BITS 1 858 #define PHY84328_DEV1_SW_RESET_CTRL_RESERVED1_SHIFT 0 859 860 861 /**************************************************************************** 862 * ln_device1 :: misc_ctrl 863 */ 864 /* ln_device1 :: misc_ctrl :: Serial_broadcast_Mode [15:15] */ 865 #define PHY84328_DEV1_MISC_CTRL_SERIAL_BROADCAST_MODE_MASK 0x8000 866 #define PHY84328_DEV1_MISC_CTRL_SERIAL_BROADCAST_MODE_ALIGN 0 867 #define PHY84328_DEV1_MISC_CTRL_SERIAL_BROADCAST_MODE_BITS 1 868 #define PHY84328_DEV1_MISC_CTRL_SERIAL_BROADCAST_MODE_SHIFT 15 869 870 /* ln_device1 :: misc_ctrl :: reserved0 [14:14] */ 871 #define PHY84328_DEV1_MISC_CTRL_RESERVED0_MASK 0x4000 872 #define PHY84328_DEV1_MISC_CTRL_RESERVED0_ALIGN 0 873 #define PHY84328_DEV1_MISC_CTRL_RESERVED0_BITS 1 874 #define PHY84328_DEV1_MISC_CTRL_RESERVED0_SHIFT 14 875 876 /* ln_device1 :: misc_ctrl :: rxd_oen [13:13] */ 877 #define PHY84328_DEV1_MISC_CTRL_RXD_OEN_MASK 0x2000 878 #define PHY84328_DEV1_MISC_CTRL_RXD_OEN_ALIGN 0 879 #define PHY84328_DEV1_MISC_CTRL_RXD_OEN_BITS 1 880 #define PHY84328_DEV1_MISC_CTRL_RXD_OEN_SHIFT 13 881 882 /* ln_device1 :: misc_ctrl :: txd_oen [12:12] */ 883 #define PHY84328_DEV1_MISC_CTRL_TXD_OEN_MASK 0x1000 884 #define PHY84328_DEV1_MISC_CTRL_TXD_OEN_ALIGN 0 885 #define PHY84328_DEV1_MISC_CTRL_TXD_OEN_BITS 1 886 #define PHY84328_DEV1_MISC_CTRL_TXD_OEN_SHIFT 12 887 888 /* ln_device1 :: misc_ctrl :: rescal_done_stat [11:11] */ 889 #define PHY84328_DEV1_MISC_CTRL_RESCAL_DONE_STAT_MASK 0x0800 890 #define PHY84328_DEV1_MISC_CTRL_RESCAL_DONE_STAT_ALIGN 0 891 #define PHY84328_DEV1_MISC_CTRL_RESCAL_DONE_STAT_BITS 1 892 #define PHY84328_DEV1_MISC_CTRL_RESCAL_DONE_STAT_SHIFT 11 893 894 /* ln_device1 :: misc_ctrl :: rescal [10:08] */ 895 #define PHY84328_DEV1_MISC_CTRL_RESCAL_MASK 0x0700 896 #define PHY84328_DEV1_MISC_CTRL_RESCAL_ALIGN 0 897 #define PHY84328_DEV1_MISC_CTRL_RESCAL_BITS 3 898 #define PHY84328_DEV1_MISC_CTRL_RESCAL_SHIFT 8 899 900 /* ln_device1 :: misc_ctrl :: global_chip_intr_en [07:07] */ 901 #define PHY84328_DEV1_MISC_CTRL_GLOBAL_CHIP_INTR_EN_MASK 0x0080 902 #define PHY84328_DEV1_MISC_CTRL_GLOBAL_CHIP_INTR_EN_ALIGN 0 903 #define PHY84328_DEV1_MISC_CTRL_GLOBAL_CHIP_INTR_EN_BITS 1 904 #define PHY84328_DEV1_MISC_CTRL_GLOBAL_CHIP_INTR_EN_SHIFT 7 905 906 /* ln_device1 :: misc_ctrl :: reserved1 [06:05] */ 907 #define PHY84328_DEV1_MISC_CTRL_RESERVED1_MASK 0x0060 908 #define PHY84328_DEV1_MISC_CTRL_RESERVED1_ALIGN 0 909 #define PHY84328_DEV1_MISC_CTRL_RESERVED1_BITS 2 910 #define PHY84328_DEV1_MISC_CTRL_RESERVED1_SHIFT 5 911 912 /* ln_device1 :: misc_ctrl :: message_out_status [04:04] */ 913 #define PHY84328_DEV1_MISC_CTRL_MESSAGE_OUT_STATUS_MASK 0x0010 914 #define PHY84328_DEV1_MISC_CTRL_MESSAGE_OUT_STATUS_ALIGN 0 915 #define PHY84328_DEV1_MISC_CTRL_MESSAGE_OUT_STATUS_BITS 1 916 #define PHY84328_DEV1_MISC_CTRL_MESSAGE_OUT_STATUS_SHIFT 4 917 918 /* ln_device1 :: misc_ctrl :: spi_download_size [03:03] */ 919 #define PHY84328_DEV1_MISC_CTRL_SPI_DOWNLOAD_SIZE_MASK 0x0008 920 #define PHY84328_DEV1_MISC_CTRL_SPI_DOWNLOAD_SIZE_ALIGN 0 921 #define PHY84328_DEV1_MISC_CTRL_SPI_DOWNLOAD_SIZE_BITS 1 922 #define PHY84328_DEV1_MISC_CTRL_SPI_DOWNLOAD_SIZE_SHIFT 3 923 924 /* ln_device1 :: misc_ctrl :: spi_download_clock_speed [02:02] */ 925 #define PHY84328_DEV1_MISC_CTRL_SPI_DOWNLOAD_CLOCK_SPEED_MASK 0x0004 926 #define PHY84328_DEV1_MISC_CTRL_SPI_DOWNLOAD_CLOCK_SPEED_ALIGN 0 927 #define PHY84328_DEV1_MISC_CTRL_SPI_DOWNLOAD_CLOCK_SPEED_BITS 1 928 #define PHY84328_DEV1_MISC_CTRL_SPI_DOWNLOAD_CLOCK_SPEED_SHIFT 2 929 930 /* ln_device1 :: misc_ctrl :: i2c_port_sel [01:00] */ 931 #define PHY84328_DEV1_MISC_CTRL_I2C_PORT_SEL_MASK 0x0003 932 #define PHY84328_DEV1_MISC_CTRL_I2C_PORT_SEL_ALIGN 0 933 #define PHY84328_DEV1_MISC_CTRL_I2C_PORT_SEL_BITS 2 934 #define PHY84328_DEV1_MISC_CTRL_I2C_PORT_SEL_SHIFT 0 935 936 937 /**************************************************************************** 938 * ln_device1 :: single_pmd_ctrl 939 */ 940 /* ln_device1 :: single_pmd_ctrl :: reserved0 [15:08] */ 941 #define PHY84328_DEV1_SINGLE_PMD_CTRL_RESERVED0_MASK 0xff00 942 #define PHY84328_DEV1_SINGLE_PMD_CTRL_RESERVED0_ALIGN 0 943 #define PHY84328_DEV1_SINGLE_PMD_CTRL_RESERVED0_BITS 8 944 #define PHY84328_DEV1_SINGLE_PMD_CTRL_RESERVED0_SHIFT 8 945 946 /* ln_device1 :: single_pmd_ctrl :: Single_pmd_mode [07:07] */ 947 #define PHY84328_DEV1_SINGLE_PMD_CTRL_SINGLE_PMD_MODE_MASK 0x0080 948 #define PHY84328_DEV1_SINGLE_PMD_CTRL_SINGLE_PMD_MODE_ALIGN 0 949 #define PHY84328_DEV1_SINGLE_PMD_CTRL_SINGLE_PMD_MODE_BITS 1 950 #define PHY84328_DEV1_SINGLE_PMD_CTRL_SINGLE_PMD_MODE_SHIFT 7 951 952 /* ln_device1 :: single_pmd_ctrl :: reserved1 [06:06] */ 953 #define PHY84328_DEV1_SINGLE_PMD_CTRL_RESERVED1_MASK 0x0040 954 #define PHY84328_DEV1_SINGLE_PMD_CTRL_RESERVED1_ALIGN 0 955 #define PHY84328_DEV1_SINGLE_PMD_CTRL_RESERVED1_BITS 1 956 #define PHY84328_DEV1_SINGLE_PMD_CTRL_RESERVED1_SHIFT 6 957 958 /* ln_device1 :: single_pmd_ctrl :: phy_ch_to_access_in_single_pmd [05:04] */ 959 #define PHY84328_DEV1_SINGLE_PMD_CTRL_PHY_CH_TO_ACCESS_IN_SINGLE_PMD_MASK 0x0030 960 #define PHY84328_DEV1_SINGLE_PMD_CTRL_PHY_CH_TO_ACCESS_IN_SINGLE_PMD_ALIGN 0 961 #define PHY84328_DEV1_SINGLE_PMD_CTRL_PHY_CH_TO_ACCESS_IN_SINGLE_PMD_BITS 2 962 #define PHY84328_DEV1_SINGLE_PMD_CTRL_PHY_CH_TO_ACCESS_IN_SINGLE_PMD_SHIFT 4 963 964 /* ln_device1 :: single_pmd_ctrl :: phy_ch_to_be_disable_in_single_pmd [03:00] */ 965 #define PHY84328_DEV1_SINGLE_PMD_CTRL_PHY_CH_TO_BE_DISABLE_IN_SINGLE_PMD_MASK 0x000f 966 #define PHY84328_DEV1_SINGLE_PMD_CTRL_PHY_CH_TO_BE_DISABLE_IN_SINGLE_PMD_ALIGN 0 967 #define PHY84328_DEV1_SINGLE_PMD_CTRL_PHY_CH_TO_BE_DISABLE_IN_SINGLE_PMD_BITS 4 968 #define PHY84328_DEV1_SINGLE_PMD_CTRL_PHY_CH_TO_BE_DISABLE_IN_SINGLE_PMD_SHIFT 0 969 970 971 /**************************************************************************** 972 * ln_device1 :: gp_reg_5 973 */ 974 /* ln_device1 :: gp_reg_5 :: gpreg5_data [15:00] */ 975 #define PHY84328_DEV1_GP_REG_5_GPREG5_DATA_MASK 0xffff 976 #define PHY84328_DEV1_GP_REG_5_GPREG5_DATA_ALIGN 0 977 #define PHY84328_DEV1_GP_REG_5_GPREG5_DATA_BITS 16 978 #define PHY84328_DEV1_GP_REG_5_GPREG5_DATA_SHIFT 0 979 980 981 /**************************************************************************** 982 * ln_device1 :: gp_reg_6 983 */ 984 /* ln_device1 :: gp_reg_6 :: gpreg6_data [15:00] */ 985 #define PHY84328_DEV1_GP_REG_6_GPREG6_DATA_MASK 0xffff 986 #define PHY84328_DEV1_GP_REG_6_GPREG6_DATA_ALIGN 0 987 #define PHY84328_DEV1_GP_REG_6_GPREG6_DATA_BITS 16 988 #define PHY84328_DEV1_GP_REG_6_GPREG6_DATA_SHIFT 0 989 990 991 /**************************************************************************** 992 * ln_device1 :: gp_reg_7 993 */ 994 /* ln_device1 :: gp_reg_7 :: gpreg7_data [15:00] */ 995 #define PHY84328_DEV1_GP_REG_7_GPREG7_DATA_MASK 0xffff 996 #define PHY84328_DEV1_GP_REG_7_GPREG7_DATA_ALIGN 0 997 #define PHY84328_DEV1_GP_REG_7_GPREG7_DATA_BITS 16 998 #define PHY84328_DEV1_GP_REG_7_GPREG7_DATA_SHIFT 0 999 1000 1001 /**************************************************************************** 1002 * ln_device1 :: gp_reg_8 1003 */ 1004 /* ln_device1 :: gp_reg_8 :: gpreg8_data [15:00] */ 1005 #define PHY84328_DEV1_GP_REG_8_GPREG8_DATA_MASK 0xffff 1006 #define PHY84328_DEV1_GP_REG_8_GPREG8_DATA_ALIGN 0 1007 #define PHY84328_DEV1_GP_REG_8_GPREG8_DATA_BITS 16 1008 #define PHY84328_DEV1_GP_REG_8_GPREG8_DATA_SHIFT 0 1009 1010 1011 /**************************************************************************** 1012 * ln_device1 :: gp_reg_9 1013 */ 1014 /* ln_device1 :: gp_reg_9 :: gpreg9_data [15:00] */ 1015 #define PHY84328_DEV1_GP_REG_9_GPREG9_DATA_MASK 0xffff 1016 #define PHY84328_DEV1_GP_REG_9_GPREG9_DATA_ALIGN 0 1017 #define PHY84328_DEV1_GP_REG_9_GPREG9_DATA_BITS 16 1018 #define PHY84328_DEV1_GP_REG_9_GPREG9_DATA_SHIFT 0 1019 1020 1021 /**************************************************************************** 1022 * ln_device1 :: vtmon_ctrl_0 1023 */ 1024 /* ln_device1 :: vtmon_ctrl_0 :: reserved0 [15:07] */ 1025 #define PHY84328_DEV1_VTMON_CTRL_0_RESERVED0_MASK 0xff80 1026 #define PHY84328_DEV1_VTMON_CTRL_0_RESERVED0_ALIGN 0 1027 #define PHY84328_DEV1_VTMON_CTRL_0_RESERVED0_BITS 9 1028 #define PHY84328_DEV1_VTMON_CTRL_0_RESERVED0_SHIFT 7 1029 1030 /* ln_device1 :: vtmon_ctrl_0 :: vtmon_test_sel [06:03] */ 1031 #define PHY84328_DEV1_VTMON_CTRL_0_VTMON_TEST_SEL_MASK 0x0078 1032 #define PHY84328_DEV1_VTMON_CTRL_0_VTMON_TEST_SEL_ALIGN 0 1033 #define PHY84328_DEV1_VTMON_CTRL_0_VTMON_TEST_SEL_BITS 4 1034 #define PHY84328_DEV1_VTMON_CTRL_0_VTMON_TEST_SEL_SHIFT 3 1035 1036 /* ln_device1 :: vtmon_ctrl_0 :: vtmon_bg_adj [02:00] */ 1037 #define PHY84328_DEV1_VTMON_CTRL_0_VTMON_BG_ADJ_MASK 0x0007 1038 #define PHY84328_DEV1_VTMON_CTRL_0_VTMON_BG_ADJ_ALIGN 0 1039 #define PHY84328_DEV1_VTMON_CTRL_0_VTMON_BG_ADJ_BITS 3 1040 #define PHY84328_DEV1_VTMON_CTRL_0_VTMON_BG_ADJ_SHIFT 0 1041 1042 1043 /**************************************************************************** 1044 * ln_device1 :: vtmon_ctrl_1 1045 */ 1046 /* ln_device1 :: vtmon_ctrl_1 :: reserved0 [15:08] */ 1047 #define PHY84328_DEV1_VTMON_CTRL_1_RESERVED0_MASK 0xff00 1048 #define PHY84328_DEV1_VTMON_CTRL_1_RESERVED0_ALIGN 0 1049 #define PHY84328_DEV1_VTMON_CTRL_1_RESERVED0_BITS 8 1050 #define PHY84328_DEV1_VTMON_CTRL_1_RESERVED0_SHIFT 8 1051 1052 /* ln_device1 :: vtmon_ctrl_1 :: pvtmon_idoffmon_pwrdn [07:07] */ 1053 #define PHY84328_DEV1_VTMON_CTRL_1_PVTMON_IDOFFMON_PWRDN_MASK 0x0080 1054 #define PHY84328_DEV1_VTMON_CTRL_1_PVTMON_IDOFFMON_PWRDN_ALIGN 0 1055 #define PHY84328_DEV1_VTMON_CTRL_1_PVTMON_IDOFFMON_PWRDN_BITS 1 1056 #define PHY84328_DEV1_VTMON_CTRL_1_PVTMON_IDOFFMON_PWRDN_SHIFT 7 1057 1058 /* ln_device1 :: vtmon_ctrl_1 :: vtmon_strb [06:06] */ 1059 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_STRB_MASK 0x0040 1060 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_STRB_ALIGN 0 1061 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_STRB_BITS 1 1062 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_STRB_SHIFT 6 1063 1064 /* ln_device1 :: vtmon_ctrl_1 :: vtmon_pwrdn [05:05] */ 1065 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_PWRDN_MASK 0x0020 1066 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_PWRDN_ALIGN 0 1067 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_PWRDN_BITS 1 1068 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_PWRDN_SHIFT 5 1069 1070 /* ln_device1 :: vtmon_ctrl_1 :: vtmon_rstb [04:04] */ 1071 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_RSTB_MASK 0x0010 1072 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_RSTB_ALIGN 0 1073 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_RSTB_BITS 1 1074 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_RSTB_SHIFT 4 1075 1076 /* ln_device1 :: vtmon_ctrl_1 :: reserved1 [03:03] */ 1077 #define PHY84328_DEV1_VTMON_CTRL_1_RESERVED1_MASK 0x0008 1078 #define PHY84328_DEV1_VTMON_CTRL_1_RESERVED1_ALIGN 0 1079 #define PHY84328_DEV1_VTMON_CTRL_1_RESERVED1_BITS 1 1080 #define PHY84328_DEV1_VTMON_CTRL_1_RESERVED1_SHIFT 3 1081 1082 /* ln_device1 :: vtmon_ctrl_1 :: vtmon_mode_sel [02:00] */ 1083 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_MODE_SEL_MASK 0x0007 1084 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_MODE_SEL_ALIGN 0 1085 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_MODE_SEL_BITS 3 1086 #define PHY84328_DEV1_VTMON_CTRL_1_VTMON_MODE_SEL_SHIFT 0 1087 1088 1089 /**************************************************************************** 1090 * ln_device1 :: vtmon_status 1091 */ 1092 /* ln_device1 :: vtmon_status :: reserved0 [15:10] */ 1093 #define PHY84328_DEV1_VTMON_STATUS_RESERVED0_MASK 0xfc00 1094 #define PHY84328_DEV1_VTMON_STATUS_RESERVED0_ALIGN 0 1095 #define PHY84328_DEV1_VTMON_STATUS_RESERVED0_BITS 6 1096 #define PHY84328_DEV1_VTMON_STATUS_RESERVED0_SHIFT 10 1097 1098 /* ln_device1 :: vtmon_status :: vtmon_data [09:00] */ 1099 #define PHY84328_DEV1_VTMON_STATUS_VTMON_DATA_MASK 0x03ff 1100 #define PHY84328_DEV1_VTMON_STATUS_VTMON_DATA_ALIGN 0 1101 #define PHY84328_DEV1_VTMON_STATUS_VTMON_DATA_BITS 10 1102 #define PHY84328_DEV1_VTMON_STATUS_VTMON_DATA_SHIFT 0 1103 1104 1105 /**************************************************************************** 1106 * ln_device1 :: vtmon_ctrl_2 1107 */ 1108 /* ln_device1 :: vtmon_ctrl_2 :: reserved0 [15:07] */ 1109 #define PHY84328_DEV1_VTMON_CTRL_2_RESERVED0_MASK 0xff80 1110 #define PHY84328_DEV1_VTMON_CTRL_2_RESERVED0_ALIGN 0 1111 #define PHY84328_DEV1_VTMON_CTRL_2_RESERVED0_BITS 9 1112 #define PHY84328_DEV1_VTMON_CTRL_2_RESERVED0_SHIFT 7 1113 1114 /* ln_device1 :: vtmon_ctrl_2 :: pvtmon_prog_resistor [06:03] */ 1115 #define PHY84328_DEV1_VTMON_CTRL_2_PVTMON_PROG_RESISTOR_MASK 0x0078 1116 #define PHY84328_DEV1_VTMON_CTRL_2_PVTMON_PROG_RESISTOR_ALIGN 0 1117 #define PHY84328_DEV1_VTMON_CTRL_2_PVTMON_PROG_RESISTOR_BITS 4 1118 #define PHY84328_DEV1_VTMON_CTRL_2_PVTMON_PROG_RESISTOR_SHIFT 3 1119 1120 /* ln_device1 :: vtmon_ctrl_2 :: pvtmon_mode [02:00] */ 1121 #define PHY84328_DEV1_VTMON_CTRL_2_PVTMON_MODE_MASK 0x0007 1122 #define PHY84328_DEV1_VTMON_CTRL_2_PVTMON_MODE_ALIGN 0 1123 #define PHY84328_DEV1_VTMON_CTRL_2_PVTMON_MODE_BITS 3 1124 #define PHY84328_DEV1_VTMON_CTRL_2_PVTMON_MODE_SHIFT 0 1125 1126 1127 /**************************************************************************** 1128 * ln_device1_DSC_regs 1129 */ 1130 /**************************************************************************** 1131 * ln_device1 :: cdr_ctrl0 1132 */ 1133 /* ln_device1 :: cdr_ctrl0 :: cdros_xfi_integ_sat_sel [15:15] */ 1134 #define PHY84328_DEV1_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_MASK 0x8000 1135 #define PHY84328_DEV1_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_ALIGN 0 1136 #define PHY84328_DEV1_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_BITS 1 1137 #define PHY84328_DEV1_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_SHIFT 15 1138 1139 /* ln_device1 :: cdr_ctrl0 :: cdrbr_m1_slicer_only [14:14] */ 1140 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_MASK 0x4000 1141 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_ALIGN 0 1142 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_BITS 1 1143 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_SHIFT 14 1144 1145 /* ln_device1 :: cdr_ctrl0 :: cdrbr_p1_slicer_only [13:13] */ 1146 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_MASK 0x2000 1147 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_ALIGN 0 1148 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_BITS 1 1149 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_SHIFT 13 1150 1151 /* ln_device1 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 1152 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 1153 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 1154 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_POLARITY_BITS 1 1155 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 1156 1157 /* ln_device1 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 1158 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 1159 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 1160 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 1161 #define PHY84328_DEV1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 1162 1163 /* ln_device1 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 1164 #define PHY84328_DEV1_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 1165 #define PHY84328_DEV1_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 1166 #define PHY84328_DEV1_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 1167 #define PHY84328_DEV1_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 1168 1169 /* ln_device1 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 1170 #define PHY84328_DEV1_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 1171 #define PHY84328_DEV1_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 1172 #define PHY84328_DEV1_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 1173 #define PHY84328_DEV1_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 1174 1175 /* ln_device1 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 1176 #define PHY84328_DEV1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 1177 #define PHY84328_DEV1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 1178 #define PHY84328_DEV1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 1179 #define PHY84328_DEV1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 1180 1181 /* ln_device1 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 1182 #define PHY84328_DEV1_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 1183 #define PHY84328_DEV1_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 1184 #define PHY84328_DEV1_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 1185 #define PHY84328_DEV1_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 1186 1187 /* ln_device1 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 1188 #define PHY84328_DEV1_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 1189 #define PHY84328_DEV1_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 1190 #define PHY84328_DEV1_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 1191 #define PHY84328_DEV1_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 1192 1193 /* ln_device1 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 1194 #define PHY84328_DEV1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 1195 #define PHY84328_DEV1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 1196 #define PHY84328_DEV1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 1197 #define PHY84328_DEV1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 1198 1199 /* ln_device1 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 1200 #define PHY84328_DEV1_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 1201 #define PHY84328_DEV1_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 1202 #define PHY84328_DEV1_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 1203 #define PHY84328_DEV1_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 1204 1205 /* ln_device1 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 1206 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 1207 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 1208 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 1209 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 1210 1211 /* ln_device1 :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 1212 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 1213 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 1214 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_EN_BITS 1 1215 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 1216 1217 /* ln_device1 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 1218 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 1219 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 1220 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 1221 #define PHY84328_DEV1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 1222 1223 1224 /**************************************************************************** 1225 * ln_device1 :: cdr_ctrl1 1226 */ 1227 /* ln_device1 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 1228 #define PHY84328_DEV1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 1229 #define PHY84328_DEV1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 1230 #define PHY84328_DEV1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 1231 #define PHY84328_DEV1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 1232 1233 1234 /**************************************************************************** 1235 * ln_device1 :: cdr_ctrl2 1236 */ 1237 /* ln_device1 :: cdr_ctrl2 :: rsvd_for_eco [15:10] */ 1238 #define PHY84328_DEV1_CDR_CTRL2_RSVD_FOR_ECO_MASK 0xfc00 1239 #define PHY84328_DEV1_CDR_CTRL2_RSVD_FOR_ECO_ALIGN 0 1240 #define PHY84328_DEV1_CDR_CTRL2_RSVD_FOR_ECO_BITS 6 1241 #define PHY84328_DEV1_CDR_CTRL2_RSVD_FOR_ECO_SHIFT 10 1242 1243 /* ln_device1 :: cdr_ctrl2 :: cdros_phase_err_offset [09:06] */ 1244 #define PHY84328_DEV1_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_MASK 0x03c0 1245 #define PHY84328_DEV1_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_ALIGN 0 1246 #define PHY84328_DEV1_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_BITS 4 1247 #define PHY84328_DEV1_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_SHIFT 6 1248 1249 /* ln_device1 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 1250 #define PHY84328_DEV1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 1251 #define PHY84328_DEV1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 1252 #define PHY84328_DEV1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 1253 #define PHY84328_DEV1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 1254 1255 1256 /**************************************************************************** 1257 * ln_device1 :: pi_ctrl0 1258 */ 1259 /* ln_device1 :: pi_ctrl0 :: pi_cw_rst [15:15] */ 1260 #define PHY84328_DEV1_PI_CTRL0_PI_CW_RST_MASK 0x8000 1261 #define PHY84328_DEV1_PI_CTRL0_PI_CW_RST_ALIGN 0 1262 #define PHY84328_DEV1_PI_CTRL0_PI_CW_RST_BITS 1 1263 #define PHY84328_DEV1_PI_CTRL0_PI_CW_RST_SHIFT 15 1264 1265 /* ln_device1 :: pi_ctrl0 :: interp_ctrl_dsel [14:12] */ 1266 #define PHY84328_DEV1_PI_CTRL0_INTERP_CTRL_DSEL_MASK 0x7000 1267 #define PHY84328_DEV1_PI_CTRL0_INTERP_CTRL_DSEL_ALIGN 0 1268 #define PHY84328_DEV1_PI_CTRL0_INTERP_CTRL_DSEL_BITS 3 1269 #define PHY84328_DEV1_PI_CTRL0_INTERP_CTRL_DSEL_SHIFT 12 1270 1271 /* ln_device1 :: pi_ctrl0 :: interp_ctrl_cap [11:11] */ 1272 #define PHY84328_DEV1_PI_CTRL0_INTERP_CTRL_CAP_MASK 0x0800 1273 #define PHY84328_DEV1_PI_CTRL0_INTERP_CTRL_CAP_ALIGN 0 1274 #define PHY84328_DEV1_PI_CTRL0_INTERP_CTRL_CAP_BITS 1 1275 #define PHY84328_DEV1_PI_CTRL0_INTERP_CTRL_CAP_SHIFT 11 1276 1277 /* ln_device1 :: pi_ctrl0 :: reserved_for_eco0 [10:06] */ 1278 #define PHY84328_DEV1_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0x07c0 1279 #define PHY84328_DEV1_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 1280 #define PHY84328_DEV1_PI_CTRL0_RESERVED_FOR_ECO0_BITS 5 1281 #define PHY84328_DEV1_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 6 1282 1283 /* ln_device1 :: pi_ctrl0 :: pi_phase_step_mult_os8 [05:05] */ 1284 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_MASK 0x0020 1285 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_ALIGN 0 1286 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_BITS 1 1287 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_SHIFT 5 1288 1289 /* ln_device1 :: pi_ctrl0 :: pi_phase_step_mult_os4 [04:04] */ 1290 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_MASK 0x0010 1291 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_ALIGN 0 1292 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_BITS 1 1293 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_SHIFT 4 1294 1295 /* ln_device1 :: pi_ctrl0 :: pi_phase_step_mult_os3 [03:03] */ 1296 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_MASK 0x0008 1297 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_ALIGN 0 1298 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_BITS 1 1299 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_SHIFT 3 1300 1301 /* ln_device1 :: pi_ctrl0 :: pi_phase_step_mult_os2 [02:02] */ 1302 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_MASK 0x0004 1303 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_ALIGN 0 1304 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_BITS 1 1305 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_SHIFT 2 1306 1307 /* ln_device1 :: pi_ctrl0 :: pi_phase_invert [01:01] */ 1308 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0002 1309 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 1310 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_INVERT_BITS 1 1311 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_INVERT_SHIFT 1 1312 1313 /* ln_device1 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 1314 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 1315 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 1316 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 1317 #define PHY84328_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 1318 1319 1320 /**************************************************************************** 1321 * ln_device1 :: pi_ctrl1 1322 */ 1323 /* ln_device1 :: pi_ctrl1 :: reserved_for_eco0 [15:12] */ 1324 #define PHY84328_DEV1_PI_CTRL1_RESERVED_FOR_ECO0_MASK 0xf000 1325 #define PHY84328_DEV1_PI_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 1326 #define PHY84328_DEV1_PI_CTRL1_RESERVED_FOR_ECO0_BITS 4 1327 #define PHY84328_DEV1_PI_CTRL1_RESERVED_FOR_ECO0_SHIFT 12 1328 1329 /* ln_device1 :: pi_ctrl1 :: pi_phase_step_dir [11:11] */ 1330 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STEP_DIR_MASK 0x0800 1331 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STEP_DIR_ALIGN 0 1332 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STEP_DIR_BITS 1 1333 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STEP_DIR_SHIFT 11 1334 1335 /* ln_device1 :: pi_ctrl1 :: pi_phase_step [10:09] */ 1336 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STEP_MASK 0x0600 1337 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STEP_ALIGN 0 1338 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STEP_BITS 2 1339 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STEP_SHIFT 9 1340 1341 /* ln_device1 :: pi_ctrl1 :: pi_phase_delta [08:04] */ 1342 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_DELTA_MASK 0x01f0 1343 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_DELTA_ALIGN 0 1344 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_DELTA_BITS 5 1345 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_DELTA_SHIFT 4 1346 1347 /* ln_device1 :: pi_ctrl1 :: pi_phase_strobe [03:03] */ 1348 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STROBE_MASK 0x0008 1349 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STROBE_ALIGN 0 1350 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STROBE_BITS 1 1351 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_STROBE_SHIFT 3 1352 1353 /* ln_device1 :: pi_ctrl1 :: pi_phase_rotate_override [02:02] */ 1354 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_MASK 0x0004 1355 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_ALIGN 0 1356 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_BITS 1 1357 #define PHY84328_DEV1_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_SHIFT 2 1358 1359 /* ln_device1 :: pi_ctrl1 :: pi_clk90_offset_override [01:01] */ 1360 #define PHY84328_DEV1_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0002 1361 #define PHY84328_DEV1_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 1362 #define PHY84328_DEV1_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_BITS 1 1363 #define PHY84328_DEV1_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_SHIFT 1 1364 1365 /* ln_device1 :: pi_ctrl1 :: pi_dual_phase_override [00:00] */ 1366 #define PHY84328_DEV1_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_MASK 0x0001 1367 #define PHY84328_DEV1_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 1368 #define PHY84328_DEV1_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_BITS 1 1369 #define PHY84328_DEV1_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_SHIFT 0 1370 1371 1372 /**************************************************************************** 1373 * ln_device1 :: dfe_vga_ctrl0 1374 */ 1375 /* ln_device1 :: dfe_vga_ctrl0 :: dfe_abs_sum_max [15:09] */ 1376 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_MASK 0xfe00 1377 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_ALIGN 0 1378 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_BITS 7 1379 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_SHIFT 9 1380 1381 /* ln_device1 :: dfe_vga_ctrl0 :: random_tapsel_disable [08:08] */ 1382 #define PHY84328_DEV1_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_MASK 0x0100 1383 #define PHY84328_DEV1_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_ALIGN 0 1384 #define PHY84328_DEV1_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_BITS 1 1385 #define PHY84328_DEV1_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_SHIFT 8 1386 1387 /* ln_device1 :: dfe_vga_ctrl0 :: cor_neg2_en [07:07] */ 1388 #define PHY84328_DEV1_DFE_VGA_CTRL0_COR_NEG2_EN_MASK 0x0080 1389 #define PHY84328_DEV1_DFE_VGA_CTRL0_COR_NEG2_EN_ALIGN 0 1390 #define PHY84328_DEV1_DFE_VGA_CTRL0_COR_NEG2_EN_BITS 1 1391 #define PHY84328_DEV1_DFE_VGA_CTRL0_COR_NEG2_EN_SHIFT 7 1392 1393 /* ln_device1 :: dfe_vga_ctrl0 :: cor_neg1_en [06:06] */ 1394 #define PHY84328_DEV1_DFE_VGA_CTRL0_COR_NEG1_EN_MASK 0x0040 1395 #define PHY84328_DEV1_DFE_VGA_CTRL0_COR_NEG1_EN_ALIGN 0 1396 #define PHY84328_DEV1_DFE_VGA_CTRL0_COR_NEG1_EN_BITS 1 1397 #define PHY84328_DEV1_DFE_VGA_CTRL0_COR_NEG1_EN_SHIFT 6 1398 1399 /* ln_device1 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 1400 #define PHY84328_DEV1_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 1401 #define PHY84328_DEV1_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 1402 #define PHY84328_DEV1_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 1403 #define PHY84328_DEV1_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 1404 1405 /* ln_device1 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 1406 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 1407 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 1408 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 1409 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 1410 1411 /* ln_device1 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 1412 #define PHY84328_DEV1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 1413 #define PHY84328_DEV1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 1414 #define PHY84328_DEV1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 1415 #define PHY84328_DEV1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 1416 1417 /* ln_device1 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 1418 #define PHY84328_DEV1_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 1419 #define PHY84328_DEV1_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 1420 #define PHY84328_DEV1_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 1421 #define PHY84328_DEV1_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 1422 1423 /* ln_device1 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 1424 #define PHY84328_DEV1_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 1425 #define PHY84328_DEV1_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 1426 #define PHY84328_DEV1_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 1427 #define PHY84328_DEV1_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 1428 1429 /* ln_device1 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 1430 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 1431 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 1432 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 1433 #define PHY84328_DEV1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 1434 1435 1436 /**************************************************************************** 1437 * ln_device1 :: dfe_vga_ctrl1 1438 */ 1439 /* ln_device1 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:14] */ 1440 #define PHY84328_DEV1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0xc000 1441 #define PHY84328_DEV1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 1442 #define PHY84328_DEV1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 2 1443 #define PHY84328_DEV1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 14 1444 1445 /* ln_device1 :: dfe_vga_ctrl1 :: dfe_llms_update_count_sel [13:12] */ 1446 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_MASK 0x3000 1447 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_ALIGN 0 1448 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_BITS 2 1449 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_SHIFT 12 1450 1451 /* ln_device1 :: dfe_vga_ctrl1 :: dfe_llms_en [11:11] */ 1452 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_LLMS_EN_MASK 0x0800 1453 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_LLMS_EN_ALIGN 0 1454 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_LLMS_EN_BITS 1 1455 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_LLMS_EN_SHIFT 11 1456 1457 /* ln_device1 :: dfe_vga_ctrl1 :: dfe_cdros_qphase_mult_en [10:10] */ 1458 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_MASK 0x0400 1459 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_ALIGN 0 1460 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_BITS 1 1461 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_SHIFT 10 1462 1463 /* ln_device1 :: dfe_vga_ctrl1 :: dfe_tap_2_dcd [09:06] */ 1464 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_2_DCD_MASK 0x03c0 1465 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_2_DCD_ALIGN 0 1466 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_2_DCD_BITS 4 1467 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_2_DCD_SHIFT 6 1468 1469 /* ln_device1 :: dfe_vga_ctrl1 :: dfe_tap_1_do [05:03] */ 1470 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DO_MASK 0x0038 1471 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DO_ALIGN 0 1472 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DO_BITS 3 1473 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DO_SHIFT 3 1474 1475 /* ln_device1 :: dfe_vga_ctrl1 :: dfe_tap_1_de [02:00] */ 1476 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DE_MASK 0x0007 1477 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DE_ALIGN 0 1478 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DE_BITS 3 1479 #define PHY84328_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DE_SHIFT 0 1480 1481 1482 /**************************************************************************** 1483 * ln_device1 :: dfe_vga_ctrl2 1484 */ 1485 /* ln_device1 :: dfe_vga_ctrl2 :: vga3_override_val [15:12] */ 1486 #define PHY84328_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_MASK 0xf000 1487 #define PHY84328_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_ALIGN 0 1488 #define PHY84328_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_BITS 4 1489 #define PHY84328_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_SHIFT 12 1490 1491 /* ln_device1 :: dfe_vga_ctrl2 :: vga3_override_en [11:11] */ 1492 #define PHY84328_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_MASK 0x0800 1493 #define PHY84328_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_ALIGN 0 1494 #define PHY84328_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_BITS 1 1495 #define PHY84328_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_SHIFT 11 1496 1497 /* ln_device1 :: dfe_vga_ctrl2 :: reserved_for_eco0 [10:10] */ 1498 #define PHY84328_DEV1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK 0x0400 1499 #define PHY84328_DEV1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 1500 #define PHY84328_DEV1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS 1 1501 #define PHY84328_DEV1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT 10 1502 1503 /* ln_device1 :: dfe_vga_ctrl2 :: dfe_vga_write_tapsel [09:07] */ 1504 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_MASK 0x0380 1505 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_ALIGN 0 1506 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_BITS 3 1507 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_SHIFT 7 1508 1509 /* ln_device1 :: dfe_vga_ctrl2 :: dfe_vga_write_val [06:01] */ 1510 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_MASK 0x007e 1511 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_ALIGN 0 1512 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_BITS 6 1513 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_SHIFT 1 1514 1515 /* ln_device1 :: dfe_vga_ctrl2 :: dfe_vga_write_en [00:00] */ 1516 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_MASK 0x0001 1517 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_ALIGN 0 1518 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_BITS 1 1519 #define PHY84328_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_SHIFT 0 1520 1521 1522 /**************************************************************************** 1523 * ln_device1 :: dfe_vga_ctrl3 1524 */ 1525 /* ln_device1 :: dfe_vga_ctrl3 :: trnsum_otap_en [15:08] */ 1526 #define PHY84328_DEV1_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_MASK 0xff00 1527 #define PHY84328_DEV1_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_ALIGN 0 1528 #define PHY84328_DEV1_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_BITS 8 1529 #define PHY84328_DEV1_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_SHIFT 8 1530 1531 /* ln_device1 :: dfe_vga_ctrl3 :: trnsum_etap_en [07:00] */ 1532 #define PHY84328_DEV1_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_MASK 0x00ff 1533 #define PHY84328_DEV1_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_ALIGN 0 1534 #define PHY84328_DEV1_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_BITS 8 1535 #define PHY84328_DEV1_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_SHIFT 0 1536 1537 1538 /**************************************************************************** 1539 * ln_device1 :: dfe_vga_ctrl4 1540 */ 1541 /* ln_device1 :: dfe_vga_ctrl4 :: trnsum_otap_sign [15:08] */ 1542 #define PHY84328_DEV1_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_MASK 0xff00 1543 #define PHY84328_DEV1_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_ALIGN 0 1544 #define PHY84328_DEV1_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_BITS 8 1545 #define PHY84328_DEV1_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_SHIFT 8 1546 1547 /* ln_device1 :: dfe_vga_ctrl4 :: trnsum_etap_sign [07:00] */ 1548 #define PHY84328_DEV1_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_MASK 0x00ff 1549 #define PHY84328_DEV1_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_ALIGN 0 1550 #define PHY84328_DEV1_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_BITS 8 1551 #define PHY84328_DEV1_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_SHIFT 0 1552 1553 1554 /**************************************************************************** 1555 * ln_device1 :: dfe_vga_ctrl5 1556 */ 1557 /* ln_device1 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */ 1558 #define PHY84328_DEV1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK 0xfc00 1559 #define PHY84328_DEV1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 1560 #define PHY84328_DEV1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS 6 1561 #define PHY84328_DEV1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT 10 1562 1563 /* ln_device1 :: dfe_vga_ctrl5 :: vga_cor_sel_e [09:05] */ 1564 #define PHY84328_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_E_MASK 0x03e0 1565 #define PHY84328_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_E_ALIGN 0 1566 #define PHY84328_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_E_BITS 5 1567 #define PHY84328_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_E_SHIFT 5 1568 1569 /* ln_device1 :: dfe_vga_ctrl5 :: vga_cor_sel_o [04:00] */ 1570 #define PHY84328_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_O_MASK 0x001f 1571 #define PHY84328_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_O_ALIGN 0 1572 #define PHY84328_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_O_BITS 5 1573 #define PHY84328_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_O_SHIFT 0 1574 1575 1576 /**************************************************************************** 1577 * ln_device1 :: dfe_vga_ctrl6 1578 */ 1579 /* ln_device1 :: dfe_vga_ctrl6 :: reserved_for_eco0 [15:10] */ 1580 #define PHY84328_DEV1_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_MASK 0xfc00 1581 #define PHY84328_DEV1_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 1582 #define PHY84328_DEV1_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_BITS 6 1583 #define PHY84328_DEV1_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_SHIFT 10 1584 1585 /* ln_device1 :: dfe_vga_ctrl6 :: dfe_cor_sel_e [09:05] */ 1586 #define PHY84328_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_E_MASK 0x03e0 1587 #define PHY84328_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_E_ALIGN 0 1588 #define PHY84328_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_E_BITS 5 1589 #define PHY84328_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_E_SHIFT 5 1590 1591 /* ln_device1 :: dfe_vga_ctrl6 :: dfe_cor_sel_o [04:00] */ 1592 #define PHY84328_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_O_MASK 0x001f 1593 #define PHY84328_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_O_ALIGN 0 1594 #define PHY84328_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_O_BITS 5 1595 #define PHY84328_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_O_SHIFT 0 1596 1597 1598 /**************************************************************************** 1599 * ln_device1 :: dfe_vga_ctrl7 1600 */ 1601 /* ln_device1 :: dfe_vga_ctrl7 :: disable_cl72_rcving_ctrl_frame [15:15] */ 1602 #define PHY84328_DEV1_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_MASK 0x8000 1603 #define PHY84328_DEV1_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_ALIGN 0 1604 #define PHY84328_DEV1_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_BITS 1 1605 #define PHY84328_DEV1_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_SHIFT 15 1606 1607 /* ln_device1 :: dfe_vga_ctrl7 :: pattern [14:08] */ 1608 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_MASK 0x7f00 1609 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_ALIGN 0 1610 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_BITS 7 1611 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_SHIFT 8 1612 1613 /* ln_device1 :: dfe_vga_ctrl7 :: pattern_bit_en [07:01] */ 1614 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_BIT_EN_MASK 0x00fe 1615 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_BIT_EN_ALIGN 0 1616 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_BIT_EN_BITS 7 1617 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_BIT_EN_SHIFT 1 1618 1619 /* ln_device1 :: dfe_vga_ctrl7 :: pattern_en [00:00] */ 1620 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_EN_MASK 0x0001 1621 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_EN_ALIGN 0 1622 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_EN_BITS 1 1623 #define PHY84328_DEV1_DFE_VGA_CTRL7_PATTERN_EN_SHIFT 0 1624 1625 1626 /**************************************************************************** 1627 * ln_device1 :: dsc_diag_ctrl0 1628 */ 1629 /* ln_device1 :: dsc_diag_ctrl0 :: rsvd_for_eco [15:12] */ 1630 #define PHY84328_DEV1_DSC_DIAG_CTRL0_RSVD_FOR_ECO_MASK 0xf000 1631 #define PHY84328_DEV1_DSC_DIAG_CTRL0_RSVD_FOR_ECO_ALIGN 0 1632 #define PHY84328_DEV1_DSC_DIAG_CTRL0_RSVD_FOR_ECO_BITS 4 1633 #define PHY84328_DEV1_DSC_DIAG_CTRL0_RSVD_FOR_ECO_SHIFT 12 1634 1635 /* ln_device1 :: dsc_diag_ctrl0 :: osx2_diag_ctrl [11:11] */ 1636 #define PHY84328_DEV1_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_MASK 0x0800 1637 #define PHY84328_DEV1_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_ALIGN 0 1638 #define PHY84328_DEV1_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_BITS 1 1639 #define PHY84328_DEV1_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_SHIFT 11 1640 1641 /* ln_device1 :: dsc_diag_ctrl0 :: voffset [10:07] */ 1642 #define PHY84328_DEV1_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 1643 #define PHY84328_DEV1_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 1644 #define PHY84328_DEV1_DSC_DIAG_CTRL0_VOFFSET_BITS 4 1645 #define PHY84328_DEV1_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 1646 1647 /* ln_device1 :: dsc_diag_ctrl0 :: hoffset [06:01] */ 1648 #define PHY84328_DEV1_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 1649 #define PHY84328_DEV1_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 1650 #define PHY84328_DEV1_DSC_DIAG_CTRL0_HOFFSET_BITS 6 1651 #define PHY84328_DEV1_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 1652 1653 /* ln_device1 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 1654 #define PHY84328_DEV1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 1655 #define PHY84328_DEV1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 1656 #define PHY84328_DEV1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 1657 #define PHY84328_DEV1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 1658 1659 1660 /**************************************************************************** 1661 * ln_device1 :: uC_ctrl 1662 */ 1663 /* ln_device1 :: uC_ctrl :: supplement_info [15:08] */ 1664 #define PHY84328_DEV1_UC_CTRL_SUPPLEMENT_INFO_MASK 0xff00 1665 #define PHY84328_DEV1_UC_CTRL_SUPPLEMENT_INFO_ALIGN 0 1666 #define PHY84328_DEV1_UC_CTRL_SUPPLEMENT_INFO_BITS 8 1667 #define PHY84328_DEV1_UC_CTRL_SUPPLEMENT_INFO_SHIFT 8 1668 1669 /* ln_device1 :: uC_ctrl :: ready_for_cmd [07:07] */ 1670 #define PHY84328_DEV1_UC_CTRL_READY_FOR_CMD_MASK 0x0080 1671 #define PHY84328_DEV1_UC_CTRL_READY_FOR_CMD_ALIGN 0 1672 #define PHY84328_DEV1_UC_CTRL_READY_FOR_CMD_BITS 1 1673 #define PHY84328_DEV1_UC_CTRL_READY_FOR_CMD_SHIFT 7 1674 1675 /* ln_device1 :: uC_ctrl :: error_found [06:06] */ 1676 #define PHY84328_DEV1_UC_CTRL_ERROR_FOUND_MASK 0x0040 1677 #define PHY84328_DEV1_UC_CTRL_ERROR_FOUND_ALIGN 0 1678 #define PHY84328_DEV1_UC_CTRL_ERROR_FOUND_BITS 1 1679 #define PHY84328_DEV1_UC_CTRL_ERROR_FOUND_SHIFT 6 1680 1681 /* ln_device1 :: uC_ctrl :: cmd_info [05:04] */ 1682 #define PHY84328_DEV1_UC_CTRL_CMD_INFO_MASK 0x0030 1683 #define PHY84328_DEV1_UC_CTRL_CMD_INFO_ALIGN 0 1684 #define PHY84328_DEV1_UC_CTRL_CMD_INFO_BITS 2 1685 #define PHY84328_DEV1_UC_CTRL_CMD_INFO_SHIFT 4 1686 1687 /* ln_device1 :: uC_ctrl :: gp_uC_req [03:00] */ 1688 #define PHY84328_DEV1_UC_CTRL_GP_UC_REQ_MASK 0x000f 1689 #define PHY84328_DEV1_UC_CTRL_GP_UC_REQ_ALIGN 0 1690 #define PHY84328_DEV1_UC_CTRL_GP_UC_REQ_BITS 4 1691 #define PHY84328_DEV1_UC_CTRL_GP_UC_REQ_SHIFT 0 1692 1693 1694 /**************************************************************************** 1695 * ln_device1 :: acq_sm_ctrl0 1696 */ 1697 /* ln_device1 :: acq_sm_ctrl0 :: cl72_timer_en [15:15] */ 1698 #define PHY84328_DEV1_ACQ_SM_CTRL0_CL72_TIMER_EN_MASK 0x8000 1699 #define PHY84328_DEV1_ACQ_SM_CTRL0_CL72_TIMER_EN_ALIGN 0 1700 #define PHY84328_DEV1_ACQ_SM_CTRL0_CL72_TIMER_EN_BITS 1 1701 #define PHY84328_DEV1_ACQ_SM_CTRL0_CL72_TIMER_EN_SHIFT 15 1702 1703 /* ln_device1 :: acq_sm_ctrl0 :: acq2_timeout [14:10] */ 1704 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQ2_TIMEOUT_MASK 0x7c00 1705 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQ2_TIMEOUT_ALIGN 0 1706 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQ2_TIMEOUT_BITS 5 1707 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQ2_TIMEOUT_SHIFT 10 1708 1709 /* ln_device1 :: acq_sm_ctrl0 :: acq1_timeout [09:05] */ 1710 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQ1_TIMEOUT_MASK 0x03e0 1711 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQ1_TIMEOUT_ALIGN 0 1712 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQ1_TIMEOUT_BITS 5 1713 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQ1_TIMEOUT_SHIFT 5 1714 1715 /* ln_device1 :: acq_sm_ctrl0 :: acqcdr_timeout [04:00] */ 1716 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_MASK 0x001f 1717 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_ALIGN 0 1718 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_BITS 5 1719 #define PHY84328_DEV1_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_SHIFT 0 1720 1721 1722 /**************************************************************************** 1723 * ln_device1 :: acq_sm_ctrl1 1724 */ 1725 /* ln_device1 :: acq_sm_ctrl1 :: acqvga_timeout [15:11] */ 1726 #define PHY84328_DEV1_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_MASK 0xf800 1727 #define PHY84328_DEV1_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_ALIGN 0 1728 #define PHY84328_DEV1_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_BITS 5 1729 #define PHY84328_DEV1_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_SHIFT 11 1730 1731 /* ln_device1 :: acq_sm_ctrl1 :: bypass_os_integ_xfer [10:10] */ 1732 #define PHY84328_DEV1_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_MASK 0x0400 1733 #define PHY84328_DEV1_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_ALIGN 0 1734 #define PHY84328_DEV1_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_BITS 1 1735 #define PHY84328_DEV1_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_SHIFT 10 1736 1737 /* ln_device1 :: acq_sm_ctrl1 :: dfe_frzval [09:05] */ 1738 #define PHY84328_DEV1_ACQ_SM_CTRL1_DFE_FRZVAL_MASK 0x03e0 1739 #define PHY84328_DEV1_ACQ_SM_CTRL1_DFE_FRZVAL_ALIGN 0 1740 #define PHY84328_DEV1_ACQ_SM_CTRL1_DFE_FRZVAL_BITS 5 1741 #define PHY84328_DEV1_ACQ_SM_CTRL1_DFE_FRZVAL_SHIFT 5 1742 1743 /* ln_device1 :: acq_sm_ctrl1 :: dfe_frcfrz [04:04] */ 1744 #define PHY84328_DEV1_ACQ_SM_CTRL1_DFE_FRCFRZ_MASK 0x0010 1745 #define PHY84328_DEV1_ACQ_SM_CTRL1_DFE_FRCFRZ_ALIGN 0 1746 #define PHY84328_DEV1_ACQ_SM_CTRL1_DFE_FRCFRZ_BITS 1 1747 #define PHY84328_DEV1_ACQ_SM_CTRL1_DFE_FRCFRZ_SHIFT 4 1748 1749 /* ln_device1 :: acq_sm_ctrl1 :: vga_frzval [03:03] */ 1750 #define PHY84328_DEV1_ACQ_SM_CTRL1_VGA_FRZVAL_MASK 0x0008 1751 #define PHY84328_DEV1_ACQ_SM_CTRL1_VGA_FRZVAL_ALIGN 0 1752 #define PHY84328_DEV1_ACQ_SM_CTRL1_VGA_FRZVAL_BITS 1 1753 #define PHY84328_DEV1_ACQ_SM_CTRL1_VGA_FRZVAL_SHIFT 3 1754 1755 /* ln_device1 :: acq_sm_ctrl1 :: vga_frcfrz [02:02] */ 1756 #define PHY84328_DEV1_ACQ_SM_CTRL1_VGA_FRCFRZ_MASK 0x0004 1757 #define PHY84328_DEV1_ACQ_SM_CTRL1_VGA_FRCFRZ_ALIGN 0 1758 #define PHY84328_DEV1_ACQ_SM_CTRL1_VGA_FRCFRZ_BITS 1 1759 #define PHY84328_DEV1_ACQ_SM_CTRL1_VGA_FRCFRZ_SHIFT 2 1760 1761 /* ln_device1 :: acq_sm_ctrl1 :: dsc_clr_val [01:01] */ 1762 #define PHY84328_DEV1_ACQ_SM_CTRL1_DSC_CLR_VAL_MASK 0x0002 1763 #define PHY84328_DEV1_ACQ_SM_CTRL1_DSC_CLR_VAL_ALIGN 0 1764 #define PHY84328_DEV1_ACQ_SM_CTRL1_DSC_CLR_VAL_BITS 1 1765 #define PHY84328_DEV1_ACQ_SM_CTRL1_DSC_CLR_VAL_SHIFT 1 1766 1767 /* ln_device1 :: acq_sm_ctrl1 :: dsc_clr_frc [00:00] */ 1768 #define PHY84328_DEV1_ACQ_SM_CTRL1_DSC_CLR_FRC_MASK 0x0001 1769 #define PHY84328_DEV1_ACQ_SM_CTRL1_DSC_CLR_FRC_ALIGN 0 1770 #define PHY84328_DEV1_ACQ_SM_CTRL1_DSC_CLR_FRC_BITS 1 1771 #define PHY84328_DEV1_ACQ_SM_CTRL1_DSC_CLR_FRC_SHIFT 0 1772 1773 1774 /**************************************************************************** 1775 * ln_device1 :: acq_sm_ctrl2 1776 */ 1777 /* ln_device1 :: acq_sm_ctrl2 :: sw_handover [15:15] */ 1778 #define PHY84328_DEV1_ACQ_SM_CTRL2_SW_HANDOVER_MASK 0x8000 1779 #define PHY84328_DEV1_ACQ_SM_CTRL2_SW_HANDOVER_ALIGN 0 1780 #define PHY84328_DEV1_ACQ_SM_CTRL2_SW_HANDOVER_BITS 1 1781 #define PHY84328_DEV1_ACQ_SM_CTRL2_SW_HANDOVER_SHIFT 15 1782 1783 /* ln_device1 :: acq_sm_ctrl2 :: eee_acq_2_timeout [14:10] */ 1784 #define PHY84328_DEV1_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_MASK 0x7c00 1785 #define PHY84328_DEV1_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_ALIGN 0 1786 #define PHY84328_DEV1_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_BITS 5 1787 #define PHY84328_DEV1_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_SHIFT 10 1788 1789 /* ln_device1 :: acq_sm_ctrl2 :: eee_acq_phase_timeout [09:05] */ 1790 #define PHY84328_DEV1_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_MASK 0x03e0 1791 #define PHY84328_DEV1_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_ALIGN 0 1792 #define PHY84328_DEV1_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_BITS 5 1793 #define PHY84328_DEV1_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_SHIFT 5 1794 1795 /* ln_device1 :: acq_sm_ctrl2 :: skip_acq [04:04] */ 1796 #define PHY84328_DEV1_ACQ_SM_CTRL2_SKIP_ACQ_MASK 0x0010 1797 #define PHY84328_DEV1_ACQ_SM_CTRL2_SKIP_ACQ_ALIGN 0 1798 #define PHY84328_DEV1_ACQ_SM_CTRL2_SKIP_ACQ_BITS 1 1799 #define PHY84328_DEV1_ACQ_SM_CTRL2_SKIP_ACQ_SHIFT 4 1800 1801 /* ln_device1 :: acq_sm_ctrl2 :: train2_req [03:03] */ 1802 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 1803 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN2_REQ_ALIGN 0 1804 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN2_REQ_BITS 1 1805 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN2_REQ_SHIFT 3 1806 1807 /* ln_device1 :: acq_sm_ctrl2 :: train1_req [02:02] */ 1808 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 1809 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN1_REQ_ALIGN 0 1810 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN1_REQ_BITS 1 1811 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN1_REQ_SHIFT 2 1812 1813 /* ln_device1 :: acq_sm_ctrl2 :: soft_ack [01:01] */ 1814 #define PHY84328_DEV1_ACQ_SM_CTRL2_SOFT_ACK_MASK 0x0002 1815 #define PHY84328_DEV1_ACQ_SM_CTRL2_SOFT_ACK_ALIGN 0 1816 #define PHY84328_DEV1_ACQ_SM_CTRL2_SOFT_ACK_BITS 1 1817 #define PHY84328_DEV1_ACQ_SM_CTRL2_SOFT_ACK_SHIFT 1 1818 1819 /* ln_device1 :: acq_sm_ctrl2 :: train_mode_en [00:00] */ 1820 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 1821 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 1822 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN_MODE_EN_BITS 1 1823 #define PHY84328_DEV1_ACQ_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 1824 1825 1826 /**************************************************************************** 1827 * ln_device1 :: acq_sm_ctrl3 1828 */ 1829 /* ln_device1 :: acq_sm_ctrl3 :: pause_level_trigger_en [15:15] */ 1830 #define PHY84328_DEV1_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_MASK 0x8000 1831 #define PHY84328_DEV1_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_ALIGN 0 1832 #define PHY84328_DEV1_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_BITS 1 1833 #define PHY84328_DEV1_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_SHIFT 15 1834 1835 /* ln_device1 :: acq_sm_ctrl3 :: reserved_for_eco0 [14:14] */ 1836 #define PHY84328_DEV1_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0x4000 1837 #define PHY84328_DEV1_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 1838 #define PHY84328_DEV1_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_BITS 1 1839 #define PHY84328_DEV1_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 14 1840 1841 /* ln_device1 :: acq_sm_ctrl3 :: os_dfe_en [13:13] */ 1842 #define PHY84328_DEV1_ACQ_SM_CTRL3_OS_DFE_EN_MASK 0x2000 1843 #define PHY84328_DEV1_ACQ_SM_CTRL3_OS_DFE_EN_ALIGN 0 1844 #define PHY84328_DEV1_ACQ_SM_CTRL3_OS_DFE_EN_BITS 1 1845 #define PHY84328_DEV1_ACQ_SM_CTRL3_OS_DFE_EN_SHIFT 13 1846 1847 /* ln_device1 :: acq_sm_ctrl3 :: dfe_taps2_5_en [12:12] */ 1848 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_MASK 0x1000 1849 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_ALIGN 0 1850 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_BITS 1 1851 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_SHIFT 12 1852 1853 /* ln_device1 :: acq_sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 1854 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 1855 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 1856 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 1857 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 1858 1859 /* ln_device1 :: acq_sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 1860 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 1861 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 1862 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 1863 #define PHY84328_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 1864 1865 /* ln_device1 :: acq_sm_ctrl3 :: vga_gain_acq2 [07:06] */ 1866 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 1867 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 1868 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 1869 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 1870 1871 /* ln_device1 :: acq_sm_ctrl3 :: vga_gain_acq1 [05:04] */ 1872 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 1873 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 1874 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 1875 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 1876 1877 /* ln_device1 :: acq_sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 1878 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 1879 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 1880 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 1881 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 1882 1883 /* ln_device1 :: acq_sm_ctrl3 :: vga_gain_acqvga [01:00] */ 1884 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 1885 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 1886 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 1887 #define PHY84328_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 1888 1889 1890 /**************************************************************************** 1891 * ln_device1 :: acq_sm_ctrl4 1892 */ 1893 /* ln_device1 :: acq_sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 1894 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 1895 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 1896 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 1897 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 1898 1899 /* ln_device1 :: acq_sm_ctrl4 :: cdros38_bwsel_prop_offset [13:12] */ 1900 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_MASK 0x3000 1901 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_ALIGN 0 1902 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_BITS 2 1903 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_SHIFT 12 1904 1905 /* ln_device1 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [11:08] */ 1906 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x0f00 1907 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 1908 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 1909 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 8 1910 1911 /* ln_device1 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqcdr [07:04] */ 1912 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x00f0 1913 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 1914 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 1915 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 4 1916 1917 /* ln_device1 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqvga [03:00] */ 1918 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 1919 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 1920 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_BITS 4 1921 #define PHY84328_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 1922 1923 1924 /**************************************************************************** 1925 * ln_device1 :: acq_sm_ctrl5 1926 */ 1927 /* ln_device1 :: acq_sm_ctrl5 :: cdros_bwsel_integ_eee_acq2 [15:12] */ 1928 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_MASK 0xf000 1929 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_ALIGN 0 1930 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_BITS 4 1931 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_SHIFT 12 1932 1933 /* ln_device1 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [11:08] */ 1934 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0x0f00 1935 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 1936 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 1937 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 8 1938 1939 /* ln_device1 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqcdr [07:04] */ 1940 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x00f0 1941 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 1942 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 1943 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 4 1944 1945 /* ln_device1 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqvga [03:00] */ 1946 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x000f 1947 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 1948 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 1949 #define PHY84328_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 0 1950 1951 1952 /**************************************************************************** 1953 * ln_device1 :: acq_sm_ctrl6 1954 */ 1955 /* ln_device1 :: acq_sm_ctrl6 :: reserved_for_eco0 [15:12] */ 1956 #define PHY84328_DEV1_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xf000 1957 #define PHY84328_DEV1_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 1958 #define PHY84328_DEV1_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_BITS 4 1959 #define PHY84328_DEV1_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 12 1960 1961 /* ln_device1 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq2 [11:09] */ 1962 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0e00 1963 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 1964 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_BITS 3 1965 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_SHIFT 9 1966 1967 /* ln_device1 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq1 [08:06] */ 1968 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_MASK 0x01c0 1969 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 1970 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_BITS 3 1971 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_SHIFT 6 1972 1973 /* ln_device1 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqcdr [05:03] */ 1974 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x0038 1975 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 1976 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 1977 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 3 1978 1979 /* ln_device1 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [02:00] */ 1980 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0007 1981 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 1982 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 1983 #define PHY84328_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 0 1984 1985 1986 /**************************************************************************** 1987 * ln_device1 :: acq_sm_ctrl7 1988 */ 1989 /* ln_device1 :: acq_sm_ctrl7 :: reserved_for_eco0 [15:12] */ 1990 #define PHY84328_DEV1_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_MASK 0xf000 1991 #define PHY84328_DEV1_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN 0 1992 #define PHY84328_DEV1_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_BITS 4 1993 #define PHY84328_DEV1_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT 12 1994 1995 /* ln_device1 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq2 [11:09] */ 1996 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0e00 1997 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 1998 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_BITS 3 1999 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 9 2000 2001 /* ln_device1 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq1 [08:06] */ 2002 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x01c0 2003 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 2004 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_BITS 3 2005 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 6 2006 2007 /* ln_device1 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqcdr [05:03] */ 2008 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x0038 2009 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 2010 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_BITS 3 2011 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 3 2012 2013 /* ln_device1 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqphase [02:00] */ 2014 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x0007 2015 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 2016 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 3 2017 #define PHY84328_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 0 2018 2019 2020 /**************************************************************************** 2021 * ln_device1 :: acq_sm_ctrl8 2022 */ 2023 /* ln_device1 :: acq_sm_ctrl8 :: reserved_for_eco0 [15:15] */ 2024 #define PHY84328_DEV1_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_MASK 0x8000 2025 #define PHY84328_DEV1_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN 0 2026 #define PHY84328_DEV1_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_BITS 1 2027 #define PHY84328_DEV1_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT 15 2028 2029 /* ln_device1 :: acq_sm_ctrl8 :: cdros_bwsel_prop_eee_acqphase [14:11] */ 2030 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_MASK 0x7800 2031 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_ALIGN 0 2032 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_BITS 4 2033 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_SHIFT 11 2034 2035 /* ln_device1 :: acq_sm_ctrl8 :: phase_sat_ctrl_100fx [10:09] */ 2036 #define PHY84328_DEV1_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_MASK 0x0600 2037 #define PHY84328_DEV1_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_ALIGN 0 2038 #define PHY84328_DEV1_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_BITS 2 2039 #define PHY84328_DEV1_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_SHIFT 9 2040 2041 /* ln_device1 :: acq_sm_ctrl8 :: pi_phase_step_mult_100fx [08:08] */ 2042 #define PHY84328_DEV1_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 2043 #define PHY84328_DEV1_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_ALIGN 0 2044 #define PHY84328_DEV1_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_BITS 1 2045 #define PHY84328_DEV1_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_SHIFT 8 2046 2047 /* ln_device1 :: acq_sm_ctrl8 :: cdros_bwsel_integ_100fx [07:04] */ 2048 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 2049 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_ALIGN 0 2050 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_BITS 4 2051 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_SHIFT 4 2052 2053 /* ln_device1 :: acq_sm_ctrl8 :: cdros_bwsel_prop_100fx [03:00] */ 2054 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_MASK 0x000f 2055 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_ALIGN 0 2056 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_BITS 4 2057 #define PHY84328_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_SHIFT 0 2058 2059 2060 /**************************************************************************** 2061 * ln_device1 :: dsc_ana_ctrl0 2062 */ 2063 /* ln_device1 :: dsc_ana_ctrl0 :: reserved_for_eco0 [15:15] */ 2064 #define PHY84328_DEV1_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 2065 #define PHY84328_DEV1_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 2066 #define PHY84328_DEV1_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_BITS 1 2067 #define PHY84328_DEV1_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 2068 2069 /* ln_device1 :: dsc_ana_ctrl0 :: force_p1_ctrl_strobe [14:14] */ 2070 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_MASK 0x4000 2071 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_ALIGN 0 2072 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_BITS 1 2073 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_SHIFT 14 2074 2075 /* ln_device1 :: dsc_ana_ctrl0 :: force_p1_odd_ctrl [13:13] */ 2076 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_MASK 0x2000 2077 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_ALIGN 0 2078 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_BITS 1 2079 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_SHIFT 13 2080 2081 /* ln_device1 :: dsc_ana_ctrl0 :: force_p1_evn_ctrl [12:12] */ 2082 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_MASK 0x1000 2083 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_ALIGN 0 2084 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_BITS 1 2085 #define PHY84328_DEV1_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_SHIFT 12 2086 2087 /* ln_device1 :: dsc_ana_ctrl0 :: p1_odd_ctrl [11:06] */ 2088 #define PHY84328_DEV1_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x0fc0 2089 #define PHY84328_DEV1_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 2090 #define PHY84328_DEV1_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 6 2091 #define PHY84328_DEV1_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 6 2092 2093 /* ln_device1 :: dsc_ana_ctrl0 :: p1_evn_ctrl [05:00] */ 2094 #define PHY84328_DEV1_DSC_ANA_CTRL0_P1_EVN_CTRL_MASK 0x003f 2095 #define PHY84328_DEV1_DSC_ANA_CTRL0_P1_EVN_CTRL_ALIGN 0 2096 #define PHY84328_DEV1_DSC_ANA_CTRL0_P1_EVN_CTRL_BITS 6 2097 #define PHY84328_DEV1_DSC_ANA_CTRL0_P1_EVN_CTRL_SHIFT 0 2098 2099 2100 /**************************************************************************** 2101 * ln_device1 :: dsc_ana_ctrl1 2102 */ 2103 /* ln_device1 :: dsc_ana_ctrl1 :: reserved_for_eco0 [15:15] */ 2104 #define PHY84328_DEV1_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 2105 #define PHY84328_DEV1_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 2106 #define PHY84328_DEV1_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_BITS 1 2107 #define PHY84328_DEV1_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 2108 2109 /* ln_device1 :: dsc_ana_ctrl1 :: force_d_ctrl_strobe [14:14] */ 2110 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_MASK 0x4000 2111 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_ALIGN 0 2112 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_BITS 1 2113 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_SHIFT 14 2114 2115 /* ln_device1 :: dsc_ana_ctrl1 :: force_d_odd_ctrl [13:13] */ 2116 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_MASK 0x2000 2117 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_ALIGN 0 2118 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_BITS 1 2119 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_SHIFT 13 2120 2121 /* ln_device1 :: dsc_ana_ctrl1 :: force_d_evn_ctrl [12:12] */ 2122 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_MASK 0x1000 2123 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_ALIGN 0 2124 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_BITS 1 2125 #define PHY84328_DEV1_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_SHIFT 12 2126 2127 /* ln_device1 :: dsc_ana_ctrl1 :: d_odd_ctrl [11:06] */ 2128 #define PHY84328_DEV1_DSC_ANA_CTRL1_D_ODD_CTRL_MASK 0x0fc0 2129 #define PHY84328_DEV1_DSC_ANA_CTRL1_D_ODD_CTRL_ALIGN 0 2130 #define PHY84328_DEV1_DSC_ANA_CTRL1_D_ODD_CTRL_BITS 6 2131 #define PHY84328_DEV1_DSC_ANA_CTRL1_D_ODD_CTRL_SHIFT 6 2132 2133 /* ln_device1 :: dsc_ana_ctrl1 :: d_evn_ctrl [05:00] */ 2134 #define PHY84328_DEV1_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x003f 2135 #define PHY84328_DEV1_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 2136 #define PHY84328_DEV1_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 6 2137 #define PHY84328_DEV1_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 0 2138 2139 2140 /**************************************************************************** 2141 * ln_device1 :: dsc_ana_ctrl2 2142 */ 2143 /* ln_device1 :: dsc_ana_ctrl2 :: reserved_for_eco0 [15:15] */ 2144 #define PHY84328_DEV1_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 2145 #define PHY84328_DEV1_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 2146 #define PHY84328_DEV1_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_BITS 1 2147 #define PHY84328_DEV1_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 2148 2149 /* ln_device1 :: dsc_ana_ctrl2 :: force_m1_ctrl_strobe [14:14] */ 2150 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_MASK 0x4000 2151 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_ALIGN 0 2152 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_BITS 1 2153 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_SHIFT 14 2154 2155 /* ln_device1 :: dsc_ana_ctrl2 :: force_m1_odd_ctrl [13:13] */ 2156 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_MASK 0x2000 2157 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_ALIGN 0 2158 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_BITS 1 2159 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_SHIFT 13 2160 2161 /* ln_device1 :: dsc_ana_ctrl2 :: force_m1_evn_ctrl [12:12] */ 2162 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_MASK 0x1000 2163 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_ALIGN 0 2164 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_BITS 1 2165 #define PHY84328_DEV1_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_SHIFT 12 2166 2167 /* ln_device1 :: dsc_ana_ctrl2 :: m1_odd_ctrl [11:06] */ 2168 #define PHY84328_DEV1_DSC_ANA_CTRL2_M1_ODD_CTRL_MASK 0x0fc0 2169 #define PHY84328_DEV1_DSC_ANA_CTRL2_M1_ODD_CTRL_ALIGN 0 2170 #define PHY84328_DEV1_DSC_ANA_CTRL2_M1_ODD_CTRL_BITS 6 2171 #define PHY84328_DEV1_DSC_ANA_CTRL2_M1_ODD_CTRL_SHIFT 6 2172 2173 /* ln_device1 :: dsc_ana_ctrl2 :: m1_evn_ctrl [05:00] */ 2174 #define PHY84328_DEV1_DSC_ANA_CTRL2_M1_EVN_CTRL_MASK 0x003f 2175 #define PHY84328_DEV1_DSC_ANA_CTRL2_M1_EVN_CTRL_ALIGN 0 2176 #define PHY84328_DEV1_DSC_ANA_CTRL2_M1_EVN_CTRL_BITS 6 2177 #define PHY84328_DEV1_DSC_ANA_CTRL2_M1_EVN_CTRL_SHIFT 0 2178 2179 2180 /**************************************************************************** 2181 * ln_device1 :: dsc_ana_ctrl3 2182 */ 2183 /* ln_device1 :: dsc_ana_ctrl3 :: rsvd_for_eco [15:10] */ 2184 #define PHY84328_DEV1_DSC_ANA_CTRL3_RSVD_FOR_ECO_MASK 0xfc00 2185 #define PHY84328_DEV1_DSC_ANA_CTRL3_RSVD_FOR_ECO_ALIGN 0 2186 #define PHY84328_DEV1_DSC_ANA_CTRL3_RSVD_FOR_ECO_BITS 6 2187 #define PHY84328_DEV1_DSC_ANA_CTRL3_RSVD_FOR_ECO_SHIFT 10 2188 2189 /* ln_device1 :: dsc_ana_ctrl3 :: rx_pf_hiz [09:09] */ 2190 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_PF_HIZ_MASK 0x0200 2191 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_PF_HIZ_ALIGN 0 2192 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_PF_HIZ_BITS 1 2193 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_PF_HIZ_SHIFT 9 2194 2195 /* ln_device1 :: dsc_ana_ctrl3 :: force_rx_m1_thresh_zero [08:08] */ 2196 #define PHY84328_DEV1_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_MASK 0x0100 2197 #define PHY84328_DEV1_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 2198 #define PHY84328_DEV1_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_BITS 1 2199 #define PHY84328_DEV1_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_SHIFT 8 2200 2201 /* ln_device1 :: dsc_ana_ctrl3 :: rx_m1_thresh_zero [07:07] */ 2202 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_MASK 0x0080 2203 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_ALIGN 0 2204 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_BITS 1 2205 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_SHIFT 7 2206 2207 /* ln_device1 :: dsc_ana_ctrl3 :: rx_thresh_sel [06:05] */ 2208 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_THRESH_SEL_MASK 0x0060 2209 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_THRESH_SEL_ALIGN 0 2210 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_THRESH_SEL_BITS 2 2211 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_THRESH_SEL_SHIFT 5 2212 2213 /* ln_device1 :: dsc_ana_ctrl3 :: force_rx_pf_ctrl [04:04] */ 2214 #define PHY84328_DEV1_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_MASK 0x0010 2215 #define PHY84328_DEV1_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_ALIGN 0 2216 #define PHY84328_DEV1_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_BITS 1 2217 #define PHY84328_DEV1_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_SHIFT 4 2218 2219 /* ln_device1 :: dsc_ana_ctrl3 :: rx_pf_ctrl [03:00] */ 2220 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_PF_CTRL_MASK 0x000f 2221 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_PF_CTRL_ALIGN 0 2222 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_PF_CTRL_BITS 4 2223 #define PHY84328_DEV1_DSC_ANA_CTRL3_RX_PF_CTRL_SHIFT 0 2224 2225 2226 /**************************************************************************** 2227 * ln_device1 :: dsc_ana_ctrl4 2228 */ 2229 /* ln_device1 :: dsc_ana_ctrl4 :: reserved_for_eco0 [15:08] */ 2230 #define PHY84328_DEV1_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_MASK 0xff00 2231 #define PHY84328_DEV1_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 2232 #define PHY84328_DEV1_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_BITS 8 2233 #define PHY84328_DEV1_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_SHIFT 8 2234 2235 /* ln_device1 :: dsc_ana_ctrl4 :: br_offset_pd [07:07] */ 2236 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_OFFSET_PD_MASK 0x0080 2237 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_OFFSET_PD_ALIGN 0 2238 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_OFFSET_PD_BITS 1 2239 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_OFFSET_PD_SHIFT 7 2240 2241 /* ln_device1 :: dsc_ana_ctrl4 :: br_en_hgain [06:06] */ 2242 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_EN_HGAIN_MASK 0x0040 2243 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_EN_HGAIN_ALIGN 0 2244 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_EN_HGAIN_BITS 1 2245 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_EN_HGAIN_SHIFT 6 2246 2247 /* ln_device1 :: dsc_ana_ctrl4 :: br_en_dfe_clk [05:05] */ 2248 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_EN_DFE_CLK_MASK 0x0020 2249 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_EN_DFE_CLK_ALIGN 0 2250 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_EN_DFE_CLK_BITS 1 2251 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_EN_DFE_CLK_SHIFT 5 2252 2253 /* ln_device1 :: dsc_ana_ctrl4 :: br_pd_ch_p1 [04:04] */ 2254 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_PD_CH_P1_MASK 0x0010 2255 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_PD_CH_P1_ALIGN 0 2256 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_PD_CH_P1_BITS 1 2257 #define PHY84328_DEV1_DSC_ANA_CTRL4_BR_PD_CH_P1_SHIFT 4 2258 2259 /* ln_device1 :: dsc_ana_ctrl4 :: osr_offset_pd [03:03] */ 2260 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_OFFSET_PD_MASK 0x0008 2261 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_OFFSET_PD_ALIGN 0 2262 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_OFFSET_PD_BITS 1 2263 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_OFFSET_PD_SHIFT 3 2264 2265 /* ln_device1 :: dsc_ana_ctrl4 :: osr_en_hgain [02:02] */ 2266 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_EN_HGAIN_MASK 0x0004 2267 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_EN_HGAIN_ALIGN 0 2268 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_EN_HGAIN_BITS 1 2269 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_EN_HGAIN_SHIFT 2 2270 2271 /* ln_device1 :: dsc_ana_ctrl4 :: osr_en_dfe_clk [01:01] */ 2272 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_MASK 0x0002 2273 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_ALIGN 0 2274 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_BITS 1 2275 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_SHIFT 1 2276 2277 /* ln_device1 :: dsc_ana_ctrl4 :: osr_pd_ch_p1 [00:00] */ 2278 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_PD_CH_P1_MASK 0x0001 2279 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_PD_CH_P1_ALIGN 0 2280 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_PD_CH_P1_BITS 1 2281 #define PHY84328_DEV1_DSC_ANA_CTRL4_OSR_PD_CH_P1_SHIFT 0 2282 2283 2284 /**************************************************************************** 2285 * ln_device1 :: dsc_misc_ctrl0 2286 */ 2287 /* ln_device1 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 2288 #define PHY84328_DEV1_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 2289 #define PHY84328_DEV1_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 2290 #define PHY84328_DEV1_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 2291 #define PHY84328_DEV1_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 2292 2293 /* ln_device1 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 2294 #define PHY84328_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 2295 #define PHY84328_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 2296 #define PHY84328_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 2297 #define PHY84328_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 2298 2299 /* ln_device1 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */ 2300 #define PHY84328_DEV1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK 0x2000 2301 #define PHY84328_DEV1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN 0 2302 #define PHY84328_DEV1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS 1 2303 #define PHY84328_DEV1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT 13 2304 2305 /* ln_device1 :: dsc_misc_ctrl0 :: forceRxSeqDone_val [12:12] */ 2306 #define PHY84328_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_MASK 0x1000 2307 #define PHY84328_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_ALIGN 0 2308 #define PHY84328_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_BITS 1 2309 #define PHY84328_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_SHIFT 12 2310 2311 /* ln_device1 :: dsc_misc_ctrl0 :: rxSeqStart_AN_disable [11:11] */ 2312 #define PHY84328_DEV1_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_MASK 0x0800 2313 #define PHY84328_DEV1_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_ALIGN 0 2314 #define PHY84328_DEV1_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_BITS 1 2315 #define PHY84328_DEV1_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_SHIFT 11 2316 2317 /* ln_device1 :: dsc_misc_ctrl0 :: test_bus_sel_bit4 [10:10] */ 2318 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_MASK 0x0400 2319 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_ALIGN 0 2320 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_BITS 1 2321 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_SHIFT 10 2322 2323 /* ln_device1 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 2324 #define PHY84328_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 2325 #define PHY84328_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 2326 #define PHY84328_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 2327 #define PHY84328_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 2328 2329 /* ln_device1 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 2330 #define PHY84328_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 2331 #define PHY84328_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 2332 #define PHY84328_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 2333 #define PHY84328_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 2334 2335 /* ln_device1 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 2336 #define PHY84328_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 2337 #define PHY84328_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 2338 #define PHY84328_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 2339 #define PHY84328_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 2340 2341 /* ln_device1 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 2342 #define PHY84328_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 2343 #define PHY84328_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 2344 #define PHY84328_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 2345 #define PHY84328_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 2346 2347 /* ln_device1 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 2348 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 2349 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 2350 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 2351 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 2352 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 2353 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 2354 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 2355 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 2356 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 2357 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 2358 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 2359 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 2360 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 2361 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 2362 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe1 12 2363 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe2 13 2364 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe3 14 2365 #define PHY84328_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe4 15 2366 2367 2368 /**************************************************************************** 2369 * ln_device1 :: cdr_lm_ctrl_0 2370 */ 2371 /* ln_device1 :: cdr_lm_ctrl_0 :: reserved_for_eco0 [15:10] */ 2372 #define PHY84328_DEV1_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_MASK 0xfc00 2373 #define PHY84328_DEV1_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_ALIGN 0 2374 #define PHY84328_DEV1_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_BITS 6 2375 #define PHY84328_DEV1_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_SHIFT 10 2376 2377 /* ln_device1 :: cdr_lm_ctrl_0 :: refclk_frc_sel [09:09] */ 2378 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_SEL_MASK 0x0200 2379 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_SEL_ALIGN 0 2380 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_SEL_BITS 1 2381 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_SEL_SHIFT 9 2382 2383 /* ln_device1 :: cdr_lm_ctrl_0 :: refclk_frc_val [08:08] */ 2384 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_VAL_MASK 0x0100 2385 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_VAL_ALIGN 0 2386 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_VAL_BITS 1 2387 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_VAL_SHIFT 8 2388 2389 /* ln_device1 :: cdr_lm_ctrl_0 :: refclk_async_sel [07:07] */ 2390 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_ASYNC_SEL_MASK 0x0080 2391 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_ASYNC_SEL_ALIGN 0 2392 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_ASYNC_SEL_BITS 1 2393 #define PHY84328_DEV1_CDR_LM_CTRL_0_REFCLK_ASYNC_SEL_SHIFT 7 2394 2395 /* ln_device1 :: cdr_lm_ctrl_0 :: pf_ctrl_strobe [06:06] */ 2396 #define PHY84328_DEV1_CDR_LM_CTRL_0_PF_CTRL_STROBE_MASK 0x0040 2397 #define PHY84328_DEV1_CDR_LM_CTRL_0_PF_CTRL_STROBE_ALIGN 0 2398 #define PHY84328_DEV1_CDR_LM_CTRL_0_PF_CTRL_STROBE_BITS 1 2399 #define PHY84328_DEV1_CDR_LM_CTRL_0_PF_CTRL_STROBE_SHIFT 6 2400 2401 /* ln_device1 :: cdr_lm_ctrl_0 :: force_pcs_clken [05:05] */ 2402 #define PHY84328_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_MASK 0x0020 2403 #define PHY84328_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_ALIGN 0 2404 #define PHY84328_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_BITS 1 2405 #define PHY84328_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_SHIFT 5 2406 2407 /* ln_device1 :: cdr_lm_ctrl_0 :: force_pcs_clken_val [04:04] */ 2408 #define PHY84328_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_MASK 0x0010 2409 #define PHY84328_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_ALIGN 0 2410 #define PHY84328_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_BITS 1 2411 #define PHY84328_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_SHIFT 4 2412 2413 /* ln_device1 :: cdr_lm_ctrl_0 :: cdr_lm_thr_sel [03:01] */ 2414 #define PHY84328_DEV1_CDR_LM_CTRL_0_CDR_LM_THR_SEL_MASK 0x000e 2415 #define PHY84328_DEV1_CDR_LM_CTRL_0_CDR_LM_THR_SEL_ALIGN 0 2416 #define PHY84328_DEV1_CDR_LM_CTRL_0_CDR_LM_THR_SEL_BITS 3 2417 #define PHY84328_DEV1_CDR_LM_CTRL_0_CDR_LM_THR_SEL_SHIFT 1 2418 2419 /* ln_device1 :: cdr_lm_ctrl_0 :: cdr_lm_en [00:00] */ 2420 #define PHY84328_DEV1_CDR_LM_CTRL_0_CDR_LM_EN_MASK 0x0001 2421 #define PHY84328_DEV1_CDR_LM_CTRL_0_CDR_LM_EN_ALIGN 0 2422 #define PHY84328_DEV1_CDR_LM_CTRL_0_CDR_LM_EN_BITS 1 2423 #define PHY84328_DEV1_CDR_LM_CTRL_0_CDR_LM_EN_SHIFT 0 2424 2425 2426 /**************************************************************************** 2427 * ln_device1_I2C_Registers 2428 */ 2429 /**************************************************************************** 2430 * ln_device1 :: i2c_control_register 2431 */ 2432 /* ln_device1 :: i2c_control_register :: i2c_master_enable [15:15] */ 2433 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_I2C_MASTER_ENABLE_MASK 0x8000 2434 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_I2C_MASTER_ENABLE_ALIGN 0 2435 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_I2C_MASTER_ENABLE_BITS 1 2436 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_I2C_MASTER_ENABLE_SHIFT 15 2437 2438 /* ln_device1 :: i2c_control_register :: regs_imc_i2cflush [14:14] */ 2439 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_REGS_IMC_I2CFLUSH_MASK 0x4000 2440 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_REGS_IMC_I2CFLUSH_ALIGN 0 2441 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_REGS_IMC_I2CFLUSH_BITS 1 2442 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_REGS_IMC_I2CFLUSH_SHIFT 14 2443 2444 /* ln_device1 :: i2c_control_register :: imc_sl_add_cnt [13:13] */ 2445 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_SL_ADD_CNT_MASK 0x2000 2446 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_SL_ADD_CNT_ALIGN 0 2447 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_SL_ADD_CNT_BITS 1 2448 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_SL_ADD_CNT_SHIFT 13 2449 2450 /* ln_device1 :: i2c_control_register :: imc_sl_dat_cnt [12:12] */ 2451 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_SL_DAT_CNT_MASK 0x1000 2452 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_SL_DAT_CNT_ALIGN 0 2453 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_SL_DAT_CNT_BITS 1 2454 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_SL_DAT_CNT_SHIFT 12 2455 2456 /* ln_device1 :: i2c_control_register :: nvm_chsum_ok [11:11] */ 2457 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_NVM_CHSUM_OK_MASK 0x0800 2458 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_NVM_CHSUM_OK_ALIGN 0 2459 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_NVM_CHSUM_OK_BITS 1 2460 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_NVM_CHSUM_OK_SHIFT 11 2461 2462 /* ln_device1 :: i2c_control_register :: imc_regs_xfer_stat [10:09] */ 2463 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_REGS_XFER_STAT_MASK 0x0600 2464 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_REGS_XFER_STAT_ALIGN 0 2465 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_REGS_XFER_STAT_BITS 2 2466 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_IMC_REGS_XFER_STAT_SHIFT 9 2467 2468 /* ln_device1 :: i2c_control_register :: reserved0 [08:06] */ 2469 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_RESERVED0_MASK 0x01c0 2470 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_RESERVED0_ALIGN 0 2471 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_RESERVED0_BITS 3 2472 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_RESERVED0_SHIFT 6 2473 2474 /* ln_device1 :: i2c_control_register :: slave_cmd [05:05] */ 2475 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_SLAVE_CMD_MASK 0x0020 2476 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_SLAVE_CMD_ALIGN 0 2477 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_SLAVE_CMD_BITS 1 2478 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_SLAVE_CMD_SHIFT 5 2479 2480 /* ln_device1 :: i2c_control_register :: reserved1 [04:04] */ 2481 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_RESERVED1_MASK 0x0010 2482 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_RESERVED1_ALIGN 0 2483 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_RESERVED1_BITS 1 2484 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_RESERVED1_SHIFT 4 2485 2486 /* ln_device1 :: i2c_control_register :: i2c_status [03:02] */ 2487 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_I2C_STATUS_MASK 0x000c 2488 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_I2C_STATUS_ALIGN 0 2489 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_I2C_STATUS_BITS 2 2490 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_I2C_STATUS_SHIFT 2 2491 2492 /* ln_device1 :: i2c_control_register :: extended_r_w [01:00] */ 2493 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_EXTENDED_R_W_MASK 0x0003 2494 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_EXTENDED_R_W_ALIGN 0 2495 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_EXTENDED_R_W_BITS 2 2496 #define PHY84328_DEV1_I2C_CONTROL_REGISTER_EXTENDED_R_W_SHIFT 0 2497 2498 2499 /**************************************************************************** 2500 * ln_device1 :: i2c_check_sum_register 2501 */ 2502 /* ln_device1 :: i2c_check_sum_register :: reserved0 [15:08] */ 2503 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER_RESERVED0_MASK 0xff00 2504 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER_RESERVED0_ALIGN 0 2505 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER_RESERVED0_BITS 8 2506 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER_RESERVED0_SHIFT 8 2507 2508 /* ln_device1 :: i2c_check_sum_register :: i2c_csum [07:00] */ 2509 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER_I2C_CSUM_MASK 0x00ff 2510 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER_I2C_CSUM_ALIGN 0 2511 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER_I2C_CSUM_BITS 8 2512 #define PHY84328_DEV1_I2C_CHECK_SUM_REGISTER_I2C_CSUM_SHIFT 0 2513 2514 2515 /**************************************************************************** 2516 * ln_device1 :: i2c_transfer_size_register 2517 */ 2518 /* ln_device1 :: i2c_transfer_size_register :: i2c_config_status [15:14] */ 2519 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER_I2C_CONFIG_STATUS_MASK 0xc000 2520 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER_I2C_CONFIG_STATUS_ALIGN 0 2521 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER_I2C_CONFIG_STATUS_BITS 2 2522 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER_I2C_CONFIG_STATUS_SHIFT 14 2523 2524 /* ln_device1 :: i2c_transfer_size_register :: imc_xfer_cnt [13:00] */ 2525 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER_IMC_XFER_CNT_MASK 0x3fff 2526 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER_IMC_XFER_CNT_ALIGN 0 2527 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER_IMC_XFER_CNT_BITS 14 2528 #define PHY84328_DEV1_I2C_TRANSFER_SIZE_REGISTER_IMC_XFER_CNT_SHIFT 0 2529 2530 2531 /**************************************************************************** 2532 * ln_device1 :: i2c_external_nvm_address_register 2533 */ 2534 /* ln_device1 :: i2c_external_nvm_address_register :: imc_slave_addr [15:00] */ 2535 #define PHY84328_DEV1_I2C_EXTERNAL_NVM_ADDRESS_REGISTER_IMC_SLAVE_ADDR_MASK 0xffff 2536 #define PHY84328_DEV1_I2C_EXTERNAL_NVM_ADDRESS_REGISTER_IMC_SLAVE_ADDR_ALIGN 0 2537 #define PHY84328_DEV1_I2C_EXTERNAL_NVM_ADDRESS_REGISTER_IMC_SLAVE_ADDR_BITS 16 2538 #define PHY84328_DEV1_I2C_EXTERNAL_NVM_ADDRESS_REGISTER_IMC_SLAVE_ADDR_SHIFT 0 2539 2540 2541 /**************************************************************************** 2542 * ln_device1 :: i2c_internal_address_register 2543 */ 2544 /* ln_device1 :: i2c_internal_address_register :: imc_xfer_addr_15_0 [15:00] */ 2545 #define PHY84328_DEV1_I2C_INTERNAL_ADDRESS_REGISTER_IMC_XFER_ADDR_15_0_MASK 0xffff 2546 #define PHY84328_DEV1_I2C_INTERNAL_ADDRESS_REGISTER_IMC_XFER_ADDR_15_0_ALIGN 0 2547 #define PHY84328_DEV1_I2C_INTERNAL_ADDRESS_REGISTER_IMC_XFER_ADDR_15_0_BITS 16 2548 #define PHY84328_DEV1_I2C_INTERNAL_ADDRESS_REGISTER_IMC_XFER_ADDR_15_0_SHIFT 0 2549 2550 2551 /**************************************************************************** 2552 * ln_device1 :: i2c_slave_id_address_register 2553 */ 2554 /* ln_device1 :: i2c_slave_id_address_register :: imc_sl_dev_add [15:09] */ 2555 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_SL_DEV_ADD_MASK 0xfe00 2556 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_SL_DEV_ADD_ALIGN 0 2557 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_SL_DEV_ADD_BITS 7 2558 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_SL_DEV_ADD_SHIFT 9 2559 2560 /* ln_device1 :: i2c_slave_id_address_register :: imc_i2c_speed [08:08] */ 2561 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_I2C_SPEED_MASK 0x0100 2562 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_I2C_SPEED_ALIGN 0 2563 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_I2C_SPEED_BITS 1 2564 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_I2C_SPEED_SHIFT 8 2565 2566 /* ln_device1 :: i2c_slave_id_address_register :: imc_xfer_addr_23_16 [07:00] */ 2567 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_XFER_ADDR_23_16_MASK 0x00ff 2568 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_XFER_ADDR_23_16_ALIGN 0 2569 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_XFER_ADDR_23_16_BITS 8 2570 #define PHY84328_DEV1_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_XFER_ADDR_23_16_SHIFT 0 2571 2572 2573 /**************************************************************************** 2574 * ln_device1_Micro_regs 2575 */ 2576 /**************************************************************************** 2577 * ln_device1 :: state_debug_ln0 2578 */ 2579 /* ln_device1 :: state_debug_ln0 :: CDR_LOCK_CORR [15:15] */ 2580 #define PHY84328_DEV1_STATE_DEBUG_LN0_CDR_LOCK_CORR_MASK 0x8000 2581 #define PHY84328_DEV1_STATE_DEBUG_LN0_CDR_LOCK_CORR_ALIGN 0 2582 #define PHY84328_DEV1_STATE_DEBUG_LN0_CDR_LOCK_CORR_BITS 1 2583 #define PHY84328_DEV1_STATE_DEBUG_LN0_CDR_LOCK_CORR_SHIFT 15 2584 2585 /* ln_device1 :: state_debug_ln0 :: DSC_DONE [14:14] */ 2586 #define PHY84328_DEV1_STATE_DEBUG_LN0_DSC_DONE_MASK 0x4000 2587 #define PHY84328_DEV1_STATE_DEBUG_LN0_DSC_DONE_ALIGN 0 2588 #define PHY84328_DEV1_STATE_DEBUG_LN0_DSC_DONE_BITS 1 2589 #define PHY84328_DEV1_STATE_DEBUG_LN0_DSC_DONE_SHIFT 14 2590 2591 /* ln_device1 :: state_debug_ln0 :: TUNING_DONE [13:13] */ 2592 #define PHY84328_DEV1_STATE_DEBUG_LN0_TUNING_DONE_MASK 0x2000 2593 #define PHY84328_DEV1_STATE_DEBUG_LN0_TUNING_DONE_ALIGN 0 2594 #define PHY84328_DEV1_STATE_DEBUG_LN0_TUNING_DONE_BITS 1 2595 #define PHY84328_DEV1_STATE_DEBUG_LN0_TUNING_DONE_SHIFT 13 2596 2597 /* ln_device1 :: state_debug_ln0 :: KR4_DIV16CK_BCST [12:12] */ 2598 #define PHY84328_DEV1_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_MASK 0x1000 2599 #define PHY84328_DEV1_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_ALIGN 0 2600 #define PHY84328_DEV1_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_BITS 1 2601 #define PHY84328_DEV1_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_SHIFT 12 2602 2603 /* ln_device1 :: state_debug_ln0 :: DCD_DFE_TUNING [11:11] */ 2604 #define PHY84328_DEV1_STATE_DEBUG_LN0_DCD_DFE_TUNING_MASK 0x0800 2605 #define PHY84328_DEV1_STATE_DEBUG_LN0_DCD_DFE_TUNING_ALIGN 0 2606 #define PHY84328_DEV1_STATE_DEBUG_LN0_DCD_DFE_TUNING_BITS 1 2607 #define PHY84328_DEV1_STATE_DEBUG_LN0_DCD_DFE_TUNING_SHIFT 11 2608 2609 /* ln_device1 :: state_debug_ln0 :: OSDFE_P1_TUNING [10:10] */ 2610 #define PHY84328_DEV1_STATE_DEBUG_LN0_OSDFE_P1_TUNING_MASK 0x0400 2611 #define PHY84328_DEV1_STATE_DEBUG_LN0_OSDFE_P1_TUNING_ALIGN 0 2612 #define PHY84328_DEV1_STATE_DEBUG_LN0_OSDFE_P1_TUNING_BITS 1 2613 #define PHY84328_DEV1_STATE_DEBUG_LN0_OSDFE_P1_TUNING_SHIFT 10 2614 2615 /* ln_device1 :: state_debug_ln0 :: SLICER_OFFSET_TUNING [09:09] */ 2616 #define PHY84328_DEV1_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_MASK 0x0200 2617 #define PHY84328_DEV1_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_ALIGN 0 2618 #define PHY84328_DEV1_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_BITS 1 2619 #define PHY84328_DEV1_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_SHIFT 9 2620 2621 /* ln_device1 :: state_debug_ln0 :: CL72_REMOTE_TUNING [08:08] */ 2622 #define PHY84328_DEV1_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_MASK 0x0100 2623 #define PHY84328_DEV1_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_ALIGN 0 2624 #define PHY84328_DEV1_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_BITS 1 2625 #define PHY84328_DEV1_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_SHIFT 8 2626 2627 /* ln_device1 :: state_debug_ln0 :: CL72_TUNING [07:07] */ 2628 #define PHY84328_DEV1_STATE_DEBUG_LN0_CL72_TUNING_MASK 0x0080 2629 #define PHY84328_DEV1_STATE_DEBUG_LN0_CL72_TUNING_ALIGN 0 2630 #define PHY84328_DEV1_STATE_DEBUG_LN0_CL72_TUNING_BITS 1 2631 #define PHY84328_DEV1_STATE_DEBUG_LN0_CL72_TUNING_SHIFT 7 2632 2633 /* ln_device1 :: state_debug_ln0 :: SLICER_TARGET_TUNING [06:06] */ 2634 #define PHY84328_DEV1_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_MASK 0x0040 2635 #define PHY84328_DEV1_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_ALIGN 0 2636 #define PHY84328_DEV1_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_BITS 1 2637 #define PHY84328_DEV1_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_SHIFT 6 2638 2639 /* ln_device1 :: state_debug_ln0 :: VGA_BIAS_TUNING [05:05] */ 2640 #define PHY84328_DEV1_STATE_DEBUG_LN0_VGA_BIAS_TUNING_MASK 0x0020 2641 #define PHY84328_DEV1_STATE_DEBUG_LN0_VGA_BIAS_TUNING_ALIGN 0 2642 #define PHY84328_DEV1_STATE_DEBUG_LN0_VGA_BIAS_TUNING_BITS 1 2643 #define PHY84328_DEV1_STATE_DEBUG_LN0_VGA_BIAS_TUNING_SHIFT 5 2644 2645 /* ln_device1 :: state_debug_ln0 :: PF_TUNING [04:04] */ 2646 #define PHY84328_DEV1_STATE_DEBUG_LN0_PF_TUNING_MASK 0x0010 2647 #define PHY84328_DEV1_STATE_DEBUG_LN0_PF_TUNING_ALIGN 0 2648 #define PHY84328_DEV1_STATE_DEBUG_LN0_PF_TUNING_BITS 1 2649 #define PHY84328_DEV1_STATE_DEBUG_LN0_PF_TUNING_SHIFT 4 2650 2651 /* ln_device1 :: state_debug_ln0 :: CLK90_OFFSET_TUNING [03:03] */ 2652 #define PHY84328_DEV1_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_MASK 0x0008 2653 #define PHY84328_DEV1_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_ALIGN 0 2654 #define PHY84328_DEV1_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_BITS 1 2655 #define PHY84328_DEV1_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_SHIFT 3 2656 2657 /* ln_device1 :: state_debug_ln0 :: OS_VGA_TUNING [02:02] */ 2658 #define PHY84328_DEV1_STATE_DEBUG_LN0_OS_VGA_TUNING_MASK 0x0004 2659 #define PHY84328_DEV1_STATE_DEBUG_LN0_OS_VGA_TUNING_ALIGN 0 2660 #define PHY84328_DEV1_STATE_DEBUG_LN0_OS_VGA_TUNING_BITS 1 2661 #define PHY84328_DEV1_STATE_DEBUG_LN0_OS_VGA_TUNING_SHIFT 2 2662 2663 /* ln_device1 :: state_debug_ln0 :: DFE_TAPS_2_5_EN [01:01] */ 2664 #define PHY84328_DEV1_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_MASK 0x0002 2665 #define PHY84328_DEV1_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_ALIGN 0 2666 #define PHY84328_DEV1_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_BITS 1 2667 #define PHY84328_DEV1_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_SHIFT 1 2668 2669 /* ln_device1 :: state_debug_ln0 :: CDR_LOCK [00:00] */ 2670 #define PHY84328_DEV1_STATE_DEBUG_LN0_CDR_LOCK_MASK 0x0001 2671 #define PHY84328_DEV1_STATE_DEBUG_LN0_CDR_LOCK_ALIGN 0 2672 #define PHY84328_DEV1_STATE_DEBUG_LN0_CDR_LOCK_BITS 1 2673 #define PHY84328_DEV1_STATE_DEBUG_LN0_CDR_LOCK_SHIFT 0 2674 2675 2676 /**************************************************************************** 2677 * ln_device1 :: state_debug_ln1 2678 */ 2679 /* ln_device1 :: state_debug_ln1 :: CDR_LOCK_CORR [15:15] */ 2680 #define PHY84328_DEV1_STATE_DEBUG_LN1_CDR_LOCK_CORR_MASK 0x8000 2681 #define PHY84328_DEV1_STATE_DEBUG_LN1_CDR_LOCK_CORR_ALIGN 0 2682 #define PHY84328_DEV1_STATE_DEBUG_LN1_CDR_LOCK_CORR_BITS 1 2683 #define PHY84328_DEV1_STATE_DEBUG_LN1_CDR_LOCK_CORR_SHIFT 15 2684 2685 /* ln_device1 :: state_debug_ln1 :: DSC_DONE [14:14] */ 2686 #define PHY84328_DEV1_STATE_DEBUG_LN1_DSC_DONE_MASK 0x4000 2687 #define PHY84328_DEV1_STATE_DEBUG_LN1_DSC_DONE_ALIGN 0 2688 #define PHY84328_DEV1_STATE_DEBUG_LN1_DSC_DONE_BITS 1 2689 #define PHY84328_DEV1_STATE_DEBUG_LN1_DSC_DONE_SHIFT 14 2690 2691 /* ln_device1 :: state_debug_ln1 :: TUNING_DONE [13:13] */ 2692 #define PHY84328_DEV1_STATE_DEBUG_LN1_TUNING_DONE_MASK 0x2000 2693 #define PHY84328_DEV1_STATE_DEBUG_LN1_TUNING_DONE_ALIGN 0 2694 #define PHY84328_DEV1_STATE_DEBUG_LN1_TUNING_DONE_BITS 1 2695 #define PHY84328_DEV1_STATE_DEBUG_LN1_TUNING_DONE_SHIFT 13 2696 2697 /* ln_device1 :: state_debug_ln1 :: KR4_DIV16CK_BCST [12:12] */ 2698 #define PHY84328_DEV1_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_MASK 0x1000 2699 #define PHY84328_DEV1_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_ALIGN 0 2700 #define PHY84328_DEV1_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_BITS 1 2701 #define PHY84328_DEV1_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_SHIFT 12 2702 2703 /* ln_device1 :: state_debug_ln1 :: DCD_DFE_TUNING [11:11] */ 2704 #define PHY84328_DEV1_STATE_DEBUG_LN1_DCD_DFE_TUNING_MASK 0x0800 2705 #define PHY84328_DEV1_STATE_DEBUG_LN1_DCD_DFE_TUNING_ALIGN 0 2706 #define PHY84328_DEV1_STATE_DEBUG_LN1_DCD_DFE_TUNING_BITS 1 2707 #define PHY84328_DEV1_STATE_DEBUG_LN1_DCD_DFE_TUNING_SHIFT 11 2708 2709 /* ln_device1 :: state_debug_ln1 :: OSDFE_P1_TUNING [10:10] */ 2710 #define PHY84328_DEV1_STATE_DEBUG_LN1_OSDFE_P1_TUNING_MASK 0x0400 2711 #define PHY84328_DEV1_STATE_DEBUG_LN1_OSDFE_P1_TUNING_ALIGN 0 2712 #define PHY84328_DEV1_STATE_DEBUG_LN1_OSDFE_P1_TUNING_BITS 1 2713 #define PHY84328_DEV1_STATE_DEBUG_LN1_OSDFE_P1_TUNING_SHIFT 10 2714 2715 /* ln_device1 :: state_debug_ln1 :: SLICER_OFFSET_TUNING [09:09] */ 2716 #define PHY84328_DEV1_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_MASK 0x0200 2717 #define PHY84328_DEV1_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_ALIGN 0 2718 #define PHY84328_DEV1_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_BITS 1 2719 #define PHY84328_DEV1_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_SHIFT 9 2720 2721 /* ln_device1 :: state_debug_ln1 :: CL72_REMOTE_TUNING [08:08] */ 2722 #define PHY84328_DEV1_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_MASK 0x0100 2723 #define PHY84328_DEV1_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_ALIGN 0 2724 #define PHY84328_DEV1_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_BITS 1 2725 #define PHY84328_DEV1_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_SHIFT 8 2726 2727 /* ln_device1 :: state_debug_ln1 :: CL72_TUNING [07:07] */ 2728 #define PHY84328_DEV1_STATE_DEBUG_LN1_CL72_TUNING_MASK 0x0080 2729 #define PHY84328_DEV1_STATE_DEBUG_LN1_CL72_TUNING_ALIGN 0 2730 #define PHY84328_DEV1_STATE_DEBUG_LN1_CL72_TUNING_BITS 1 2731 #define PHY84328_DEV1_STATE_DEBUG_LN1_CL72_TUNING_SHIFT 7 2732 2733 /* ln_device1 :: state_debug_ln1 :: SLICER_TARGET_TUNING [06:06] */ 2734 #define PHY84328_DEV1_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_MASK 0x0040 2735 #define PHY84328_DEV1_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_ALIGN 0 2736 #define PHY84328_DEV1_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_BITS 1 2737 #define PHY84328_DEV1_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_SHIFT 6 2738 2739 /* ln_device1 :: state_debug_ln1 :: VGA_BIAS_TUNING [05:05] */ 2740 #define PHY84328_DEV1_STATE_DEBUG_LN1_VGA_BIAS_TUNING_MASK 0x0020 2741 #define PHY84328_DEV1_STATE_DEBUG_LN1_VGA_BIAS_TUNING_ALIGN 0 2742 #define PHY84328_DEV1_STATE_DEBUG_LN1_VGA_BIAS_TUNING_BITS 1 2743 #define PHY84328_DEV1_STATE_DEBUG_LN1_VGA_BIAS_TUNING_SHIFT 5 2744 2745 /* ln_device1 :: state_debug_ln1 :: PF_TUNING [04:04] */ 2746 #define PHY84328_DEV1_STATE_DEBUG_LN1_PF_TUNING_MASK 0x0010 2747 #define PHY84328_DEV1_STATE_DEBUG_LN1_PF_TUNING_ALIGN 0 2748 #define PHY84328_DEV1_STATE_DEBUG_LN1_PF_TUNING_BITS 1 2749 #define PHY84328_DEV1_STATE_DEBUG_LN1_PF_TUNING_SHIFT 4 2750 2751 /* ln_device1 :: state_debug_ln1 :: CLK90_OFFSET_TUNING [03:03] */ 2752 #define PHY84328_DEV1_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_MASK 0x0008 2753 #define PHY84328_DEV1_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_ALIGN 0 2754 #define PHY84328_DEV1_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_BITS 1 2755 #define PHY84328_DEV1_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_SHIFT 3 2756 2757 /* ln_device1 :: state_debug_ln1 :: OS_VGA_TUNING [02:02] */ 2758 #define PHY84328_DEV1_STATE_DEBUG_LN1_OS_VGA_TUNING_MASK 0x0004 2759 #define PHY84328_DEV1_STATE_DEBUG_LN1_OS_VGA_TUNING_ALIGN 0 2760 #define PHY84328_DEV1_STATE_DEBUG_LN1_OS_VGA_TUNING_BITS 1 2761 #define PHY84328_DEV1_STATE_DEBUG_LN1_OS_VGA_TUNING_SHIFT 2 2762 2763 /* ln_device1 :: state_debug_ln1 :: DFE_TAPS_2_5_EN [01:01] */ 2764 #define PHY84328_DEV1_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_MASK 0x0002 2765 #define PHY84328_DEV1_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_ALIGN 0 2766 #define PHY84328_DEV1_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_BITS 1 2767 #define PHY84328_DEV1_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_SHIFT 1 2768 2769 /* ln_device1 :: state_debug_ln1 :: CDR_LOCK [00:00] */ 2770 #define PHY84328_DEV1_STATE_DEBUG_LN1_CDR_LOCK_MASK 0x0001 2771 #define PHY84328_DEV1_STATE_DEBUG_LN1_CDR_LOCK_ALIGN 0 2772 #define PHY84328_DEV1_STATE_DEBUG_LN1_CDR_LOCK_BITS 1 2773 #define PHY84328_DEV1_STATE_DEBUG_LN1_CDR_LOCK_SHIFT 0 2774 2775 2776 /**************************************************************************** 2777 * ln_device1 :: state_debug_ln2 2778 */ 2779 /* ln_device1 :: state_debug_ln2 :: CDR_LOCK_CORR [15:15] */ 2780 #define PHY84328_DEV1_STATE_DEBUG_LN2_CDR_LOCK_CORR_MASK 0x8000 2781 #define PHY84328_DEV1_STATE_DEBUG_LN2_CDR_LOCK_CORR_ALIGN 0 2782 #define PHY84328_DEV1_STATE_DEBUG_LN2_CDR_LOCK_CORR_BITS 1 2783 #define PHY84328_DEV1_STATE_DEBUG_LN2_CDR_LOCK_CORR_SHIFT 15 2784 2785 /* ln_device1 :: state_debug_ln2 :: DSC_DONE [14:14] */ 2786 #define PHY84328_DEV1_STATE_DEBUG_LN2_DSC_DONE_MASK 0x4000 2787 #define PHY84328_DEV1_STATE_DEBUG_LN2_DSC_DONE_ALIGN 0 2788 #define PHY84328_DEV1_STATE_DEBUG_LN2_DSC_DONE_BITS 1 2789 #define PHY84328_DEV1_STATE_DEBUG_LN2_DSC_DONE_SHIFT 14 2790 2791 /* ln_device1 :: state_debug_ln2 :: TUNING_DONE [13:13] */ 2792 #define PHY84328_DEV1_STATE_DEBUG_LN2_TUNING_DONE_MASK 0x2000 2793 #define PHY84328_DEV1_STATE_DEBUG_LN2_TUNING_DONE_ALIGN 0 2794 #define PHY84328_DEV1_STATE_DEBUG_LN2_TUNING_DONE_BITS 1 2795 #define PHY84328_DEV1_STATE_DEBUG_LN2_TUNING_DONE_SHIFT 13 2796 2797 /* ln_device1 :: state_debug_ln2 :: KR4_DIV16CK_BCST [12:12] */ 2798 #define PHY84328_DEV1_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_MASK 0x1000 2799 #define PHY84328_DEV1_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_ALIGN 0 2800 #define PHY84328_DEV1_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_BITS 1 2801 #define PHY84328_DEV1_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_SHIFT 12 2802 2803 /* ln_device1 :: state_debug_ln2 :: DCD_DFE_TUNING [11:11] */ 2804 #define PHY84328_DEV1_STATE_DEBUG_LN2_DCD_DFE_TUNING_MASK 0x0800 2805 #define PHY84328_DEV1_STATE_DEBUG_LN2_DCD_DFE_TUNING_ALIGN 0 2806 #define PHY84328_DEV1_STATE_DEBUG_LN2_DCD_DFE_TUNING_BITS 1 2807 #define PHY84328_DEV1_STATE_DEBUG_LN2_DCD_DFE_TUNING_SHIFT 11 2808 2809 /* ln_device1 :: state_debug_ln2 :: OSDFE_P1_TUNING [10:10] */ 2810 #define PHY84328_DEV1_STATE_DEBUG_LN2_OSDFE_P1_TUNING_MASK 0x0400 2811 #define PHY84328_DEV1_STATE_DEBUG_LN2_OSDFE_P1_TUNING_ALIGN 0 2812 #define PHY84328_DEV1_STATE_DEBUG_LN2_OSDFE_P1_TUNING_BITS 1 2813 #define PHY84328_DEV1_STATE_DEBUG_LN2_OSDFE_P1_TUNING_SHIFT 10 2814 2815 /* ln_device1 :: state_debug_ln2 :: SLICER_OFFSET_TUNING [09:09] */ 2816 #define PHY84328_DEV1_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_MASK 0x0200 2817 #define PHY84328_DEV1_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_ALIGN 0 2818 #define PHY84328_DEV1_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_BITS 1 2819 #define PHY84328_DEV1_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_SHIFT 9 2820 2821 /* ln_device1 :: state_debug_ln2 :: CL72_REMOTE_TUNING [08:08] */ 2822 #define PHY84328_DEV1_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_MASK 0x0100 2823 #define PHY84328_DEV1_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_ALIGN 0 2824 #define PHY84328_DEV1_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_BITS 1 2825 #define PHY84328_DEV1_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_SHIFT 8 2826 2827 /* ln_device1 :: state_debug_ln2 :: CL72_TUNING [07:07] */ 2828 #define PHY84328_DEV1_STATE_DEBUG_LN2_CL72_TUNING_MASK 0x0080 2829 #define PHY84328_DEV1_STATE_DEBUG_LN2_CL72_TUNING_ALIGN 0 2830 #define PHY84328_DEV1_STATE_DEBUG_LN2_CL72_TUNING_BITS 1 2831 #define PHY84328_DEV1_STATE_DEBUG_LN2_CL72_TUNING_SHIFT 7 2832 2833 /* ln_device1 :: state_debug_ln2 :: SLICER_TARGET_TUNING [06:06] */ 2834 #define PHY84328_DEV1_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_MASK 0x0040 2835 #define PHY84328_DEV1_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_ALIGN 0 2836 #define PHY84328_DEV1_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_BITS 1 2837 #define PHY84328_DEV1_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_SHIFT 6 2838 2839 /* ln_device1 :: state_debug_ln2 :: VGA_BIAS_TUNING [05:05] */ 2840 #define PHY84328_DEV1_STATE_DEBUG_LN2_VGA_BIAS_TUNING_MASK 0x0020 2841 #define PHY84328_DEV1_STATE_DEBUG_LN2_VGA_BIAS_TUNING_ALIGN 0 2842 #define PHY84328_DEV1_STATE_DEBUG_LN2_VGA_BIAS_TUNING_BITS 1 2843 #define PHY84328_DEV1_STATE_DEBUG_LN2_VGA_BIAS_TUNING_SHIFT 5 2844 2845 /* ln_device1 :: state_debug_ln2 :: PF_TUNING [04:04] */ 2846 #define PHY84328_DEV1_STATE_DEBUG_LN2_PF_TUNING_MASK 0x0010 2847 #define PHY84328_DEV1_STATE_DEBUG_LN2_PF_TUNING_ALIGN 0 2848 #define PHY84328_DEV1_STATE_DEBUG_LN2_PF_TUNING_BITS 1 2849 #define PHY84328_DEV1_STATE_DEBUG_LN2_PF_TUNING_SHIFT 4 2850 2851 /* ln_device1 :: state_debug_ln2 :: CLK90_OFFSET_TUNING [03:03] */ 2852 #define PHY84328_DEV1_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_MASK 0x0008 2853 #define PHY84328_DEV1_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_ALIGN 0 2854 #define PHY84328_DEV1_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_BITS 1 2855 #define PHY84328_DEV1_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_SHIFT 3 2856 2857 /* ln_device1 :: state_debug_ln2 :: OS_VGA_TUNING [02:02] */ 2858 #define PHY84328_DEV1_STATE_DEBUG_LN2_OS_VGA_TUNING_MASK 0x0004 2859 #define PHY84328_DEV1_STATE_DEBUG_LN2_OS_VGA_TUNING_ALIGN 0 2860 #define PHY84328_DEV1_STATE_DEBUG_LN2_OS_VGA_TUNING_BITS 1 2861 #define PHY84328_DEV1_STATE_DEBUG_LN2_OS_VGA_TUNING_SHIFT 2 2862 2863 /* ln_device1 :: state_debug_ln2 :: DFE_TAPS_2_5_EN [01:01] */ 2864 #define PHY84328_DEV1_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_MASK 0x0002 2865 #define PHY84328_DEV1_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_ALIGN 0 2866 #define PHY84328_DEV1_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_BITS 1 2867 #define PHY84328_DEV1_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_SHIFT 1 2868 2869 /* ln_device1 :: state_debug_ln2 :: CDR_LOCK [00:00] */ 2870 #define PHY84328_DEV1_STATE_DEBUG_LN2_CDR_LOCK_MASK 0x0001 2871 #define PHY84328_DEV1_STATE_DEBUG_LN2_CDR_LOCK_ALIGN 0 2872 #define PHY84328_DEV1_STATE_DEBUG_LN2_CDR_LOCK_BITS 1 2873 #define PHY84328_DEV1_STATE_DEBUG_LN2_CDR_LOCK_SHIFT 0 2874 2875 2876 /**************************************************************************** 2877 * ln_device1 :: state_debug_ln3 2878 */ 2879 /* ln_device1 :: state_debug_ln3 :: CDR_LOCK_CORR [15:15] */ 2880 #define PHY84328_DEV1_STATE_DEBUG_LN3_CDR_LOCK_CORR_MASK 0x8000 2881 #define PHY84328_DEV1_STATE_DEBUG_LN3_CDR_LOCK_CORR_ALIGN 0 2882 #define PHY84328_DEV1_STATE_DEBUG_LN3_CDR_LOCK_CORR_BITS 1 2883 #define PHY84328_DEV1_STATE_DEBUG_LN3_CDR_LOCK_CORR_SHIFT 15 2884 2885 /* ln_device1 :: state_debug_ln3 :: DSC_DONE [14:14] */ 2886 #define PHY84328_DEV1_STATE_DEBUG_LN3_DSC_DONE_MASK 0x4000 2887 #define PHY84328_DEV1_STATE_DEBUG_LN3_DSC_DONE_ALIGN 0 2888 #define PHY84328_DEV1_STATE_DEBUG_LN3_DSC_DONE_BITS 1 2889 #define PHY84328_DEV1_STATE_DEBUG_LN3_DSC_DONE_SHIFT 14 2890 2891 /* ln_device1 :: state_debug_ln3 :: TUNING_DONE [13:13] */ 2892 #define PHY84328_DEV1_STATE_DEBUG_LN3_TUNING_DONE_MASK 0x2000 2893 #define PHY84328_DEV1_STATE_DEBUG_LN3_TUNING_DONE_ALIGN 0 2894 #define PHY84328_DEV1_STATE_DEBUG_LN3_TUNING_DONE_BITS 1 2895 #define PHY84328_DEV1_STATE_DEBUG_LN3_TUNING_DONE_SHIFT 13 2896 2897 /* ln_device1 :: state_debug_ln3 :: KR4_DIV16CK_BCST [12:12] */ 2898 #define PHY84328_DEV1_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_MASK 0x1000 2899 #define PHY84328_DEV1_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_ALIGN 0 2900 #define PHY84328_DEV1_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_BITS 1 2901 #define PHY84328_DEV1_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_SHIFT 12 2902 2903 /* ln_device1 :: state_debug_ln3 :: DCD_DFE_TUNING [11:11] */ 2904 #define PHY84328_DEV1_STATE_DEBUG_LN3_DCD_DFE_TUNING_MASK 0x0800 2905 #define PHY84328_DEV1_STATE_DEBUG_LN3_DCD_DFE_TUNING_ALIGN 0 2906 #define PHY84328_DEV1_STATE_DEBUG_LN3_DCD_DFE_TUNING_BITS 1 2907 #define PHY84328_DEV1_STATE_DEBUG_LN3_DCD_DFE_TUNING_SHIFT 11 2908 2909 /* ln_device1 :: state_debug_ln3 :: OSDFE_P1_TUNING [10:10] */ 2910 #define PHY84328_DEV1_STATE_DEBUG_LN3_OSDFE_P1_TUNING_MASK 0x0400 2911 #define PHY84328_DEV1_STATE_DEBUG_LN3_OSDFE_P1_TUNING_ALIGN 0 2912 #define PHY84328_DEV1_STATE_DEBUG_LN3_OSDFE_P1_TUNING_BITS 1 2913 #define PHY84328_DEV1_STATE_DEBUG_LN3_OSDFE_P1_TUNING_SHIFT 10 2914 2915 /* ln_device1 :: state_debug_ln3 :: SLICER_OFFSET_TUNING [09:09] */ 2916 #define PHY84328_DEV1_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_MASK 0x0200 2917 #define PHY84328_DEV1_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_ALIGN 0 2918 #define PHY84328_DEV1_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_BITS 1 2919 #define PHY84328_DEV1_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_SHIFT 9 2920 2921 /* ln_device1 :: state_debug_ln3 :: CL72_REMOTE_TUNING [08:08] */ 2922 #define PHY84328_DEV1_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_MASK 0x0100 2923 #define PHY84328_DEV1_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_ALIGN 0 2924 #define PHY84328_DEV1_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_BITS 1 2925 #define PHY84328_DEV1_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_SHIFT 8 2926 2927 /* ln_device1 :: state_debug_ln3 :: CL72_TUNING [07:07] */ 2928 #define PHY84328_DEV1_STATE_DEBUG_LN3_CL72_TUNING_MASK 0x0080 2929 #define PHY84328_DEV1_STATE_DEBUG_LN3_CL72_TUNING_ALIGN 0 2930 #define PHY84328_DEV1_STATE_DEBUG_LN3_CL72_TUNING_BITS 1 2931 #define PHY84328_DEV1_STATE_DEBUG_LN3_CL72_TUNING_SHIFT 7 2932 2933 /* ln_device1 :: state_debug_ln3 :: SLICER_TARGET_TUNING [06:06] */ 2934 #define PHY84328_DEV1_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_MASK 0x0040 2935 #define PHY84328_DEV1_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_ALIGN 0 2936 #define PHY84328_DEV1_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_BITS 1 2937 #define PHY84328_DEV1_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_SHIFT 6 2938 2939 /* ln_device1 :: state_debug_ln3 :: VGA_BIAS_TUNING [05:05] */ 2940 #define PHY84328_DEV1_STATE_DEBUG_LN3_VGA_BIAS_TUNING_MASK 0x0020 2941 #define PHY84328_DEV1_STATE_DEBUG_LN3_VGA_BIAS_TUNING_ALIGN 0 2942 #define PHY84328_DEV1_STATE_DEBUG_LN3_VGA_BIAS_TUNING_BITS 1 2943 #define PHY84328_DEV1_STATE_DEBUG_LN3_VGA_BIAS_TUNING_SHIFT 5 2944 2945 /* ln_device1 :: state_debug_ln3 :: PF_TUNING [04:04] */ 2946 #define PHY84328_DEV1_STATE_DEBUG_LN3_PF_TUNING_MASK 0x0010 2947 #define PHY84328_DEV1_STATE_DEBUG_LN3_PF_TUNING_ALIGN 0 2948 #define PHY84328_DEV1_STATE_DEBUG_LN3_PF_TUNING_BITS 1 2949 #define PHY84328_DEV1_STATE_DEBUG_LN3_PF_TUNING_SHIFT 4 2950 2951 /* ln_device1 :: state_debug_ln3 :: CLK90_OFFSET_TUNING [03:03] */ 2952 #define PHY84328_DEV1_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_MASK 0x0008 2953 #define PHY84328_DEV1_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_ALIGN 0 2954 #define PHY84328_DEV1_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_BITS 1 2955 #define PHY84328_DEV1_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_SHIFT 3 2956 2957 /* ln_device1 :: state_debug_ln3 :: OS_VGA_TUNING [02:02] */ 2958 #define PHY84328_DEV1_STATE_DEBUG_LN3_OS_VGA_TUNING_MASK 0x0004 2959 #define PHY84328_DEV1_STATE_DEBUG_LN3_OS_VGA_TUNING_ALIGN 0 2960 #define PHY84328_DEV1_STATE_DEBUG_LN3_OS_VGA_TUNING_BITS 1 2961 #define PHY84328_DEV1_STATE_DEBUG_LN3_OS_VGA_TUNING_SHIFT 2 2962 2963 /* ln_device1 :: state_debug_ln3 :: DFE_TAPS_2_5_EN [01:01] */ 2964 #define PHY84328_DEV1_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_MASK 0x0002 2965 #define PHY84328_DEV1_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_ALIGN 0 2966 #define PHY84328_DEV1_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_BITS 1 2967 #define PHY84328_DEV1_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_SHIFT 1 2968 2969 /* ln_device1 :: state_debug_ln3 :: CDR_LOCK [00:00] */ 2970 #define PHY84328_DEV1_STATE_DEBUG_LN3_CDR_LOCK_MASK 0x0001 2971 #define PHY84328_DEV1_STATE_DEBUG_LN3_CDR_LOCK_ALIGN 0 2972 #define PHY84328_DEV1_STATE_DEBUG_LN3_CDR_LOCK_BITS 1 2973 #define PHY84328_DEV1_STATE_DEBUG_LN3_CDR_LOCK_SHIFT 0 2974 2975 2976 /**************************************************************************** 2977 * ln_device1 :: speed_debug_ln0 2978 */ 2979 /* ln_device1 :: speed_debug_ln0 :: LOS_counter [15:12] */ 2980 #define PHY84328_DEV1_SPEED_DEBUG_LN0_LOS_COUNTER_MASK 0xf000 2981 #define PHY84328_DEV1_SPEED_DEBUG_LN0_LOS_COUNTER_ALIGN 0 2982 #define PHY84328_DEV1_SPEED_DEBUG_LN0_LOS_COUNTER_BITS 4 2983 #define PHY84328_DEV1_SPEED_DEBUG_LN0_LOS_COUNTER_SHIFT 12 2984 2985 /* ln_device1 :: speed_debug_ln0 :: need_br_dfe [11:11] */ 2986 #define PHY84328_DEV1_SPEED_DEBUG_LN0_NEED_BR_DFE_MASK 0x0800 2987 #define PHY84328_DEV1_SPEED_DEBUG_LN0_NEED_BR_DFE_ALIGN 0 2988 #define PHY84328_DEV1_SPEED_DEBUG_LN0_NEED_BR_DFE_BITS 1 2989 #define PHY84328_DEV1_SPEED_DEBUG_LN0_NEED_BR_DFE_SHIFT 11 2990 2991 /* ln_device1 :: speed_debug_ln0 :: br_dfe_enabled [10:10] */ 2992 #define PHY84328_DEV1_SPEED_DEBUG_LN0_BR_DFE_ENABLED_MASK 0x0400 2993 #define PHY84328_DEV1_SPEED_DEBUG_LN0_BR_DFE_ENABLED_ALIGN 0 2994 #define PHY84328_DEV1_SPEED_DEBUG_LN0_BR_DFE_ENABLED_BITS 1 2995 #define PHY84328_DEV1_SPEED_DEBUG_LN0_BR_DFE_ENABLED_SHIFT 10 2996 2997 /* ln_device1 :: speed_debug_ln0 :: os_dfe_enabled [09:09] */ 2998 #define PHY84328_DEV1_SPEED_DEBUG_LN0_OS_DFE_ENABLED_MASK 0x0200 2999 #define PHY84328_DEV1_SPEED_DEBUG_LN0_OS_DFE_ENABLED_ALIGN 0 3000 #define PHY84328_DEV1_SPEED_DEBUG_LN0_OS_DFE_ENABLED_BITS 1 3001 #define PHY84328_DEV1_SPEED_DEBUG_LN0_OS_DFE_ENABLED_SHIFT 9 3002 3003 /* ln_device1 :: speed_debug_ln0 :: os_enabled [08:08] */ 3004 #define PHY84328_DEV1_SPEED_DEBUG_LN0_OS_ENABLED_MASK 0x0100 3005 #define PHY84328_DEV1_SPEED_DEBUG_LN0_OS_ENABLED_ALIGN 0 3006 #define PHY84328_DEV1_SPEED_DEBUG_LN0_OS_ENABLED_BITS 1 3007 #define PHY84328_DEV1_SPEED_DEBUG_LN0_OS_ENABLED_SHIFT 8 3008 3009 /* ln_device1 :: speed_debug_ln0 :: actual_speed [07:00] */ 3010 #define PHY84328_DEV1_SPEED_DEBUG_LN0_ACTUAL_SPEED_MASK 0x00ff 3011 #define PHY84328_DEV1_SPEED_DEBUG_LN0_ACTUAL_SPEED_ALIGN 0 3012 #define PHY84328_DEV1_SPEED_DEBUG_LN0_ACTUAL_SPEED_BITS 8 3013 #define PHY84328_DEV1_SPEED_DEBUG_LN0_ACTUAL_SPEED_SHIFT 0 3014 3015 3016 /**************************************************************************** 3017 * ln_device1 :: speed_debug_ln1 3018 */ 3019 /* ln_device1 :: speed_debug_ln1 :: LOS_counter [15:12] */ 3020 #define PHY84328_DEV1_SPEED_DEBUG_LN1_LOS_COUNTER_MASK 0xf000 3021 #define PHY84328_DEV1_SPEED_DEBUG_LN1_LOS_COUNTER_ALIGN 0 3022 #define PHY84328_DEV1_SPEED_DEBUG_LN1_LOS_COUNTER_BITS 4 3023 #define PHY84328_DEV1_SPEED_DEBUG_LN1_LOS_COUNTER_SHIFT 12 3024 3025 /* ln_device1 :: speed_debug_ln1 :: need_br_dfe [11:11] */ 3026 #define PHY84328_DEV1_SPEED_DEBUG_LN1_NEED_BR_DFE_MASK 0x0800 3027 #define PHY84328_DEV1_SPEED_DEBUG_LN1_NEED_BR_DFE_ALIGN 0 3028 #define PHY84328_DEV1_SPEED_DEBUG_LN1_NEED_BR_DFE_BITS 1 3029 #define PHY84328_DEV1_SPEED_DEBUG_LN1_NEED_BR_DFE_SHIFT 11 3030 3031 /* ln_device1 :: speed_debug_ln1 :: br_dfe_enabled [10:10] */ 3032 #define PHY84328_DEV1_SPEED_DEBUG_LN1_BR_DFE_ENABLED_MASK 0x0400 3033 #define PHY84328_DEV1_SPEED_DEBUG_LN1_BR_DFE_ENABLED_ALIGN 0 3034 #define PHY84328_DEV1_SPEED_DEBUG_LN1_BR_DFE_ENABLED_BITS 1 3035 #define PHY84328_DEV1_SPEED_DEBUG_LN1_BR_DFE_ENABLED_SHIFT 10 3036 3037 /* ln_device1 :: speed_debug_ln1 :: os_dfe_enabled [09:09] */ 3038 #define PHY84328_DEV1_SPEED_DEBUG_LN1_OS_DFE_ENABLED_MASK 0x0200 3039 #define PHY84328_DEV1_SPEED_DEBUG_LN1_OS_DFE_ENABLED_ALIGN 0 3040 #define PHY84328_DEV1_SPEED_DEBUG_LN1_OS_DFE_ENABLED_BITS 1 3041 #define PHY84328_DEV1_SPEED_DEBUG_LN1_OS_DFE_ENABLED_SHIFT 9 3042 3043 /* ln_device1 :: speed_debug_ln1 :: os_enabled [08:08] */ 3044 #define PHY84328_DEV1_SPEED_DEBUG_LN1_OS_ENABLED_MASK 0x0100 3045 #define PHY84328_DEV1_SPEED_DEBUG_LN1_OS_ENABLED_ALIGN 0 3046 #define PHY84328_DEV1_SPEED_DEBUG_LN1_OS_ENABLED_BITS 1 3047 #define PHY84328_DEV1_SPEED_DEBUG_LN1_OS_ENABLED_SHIFT 8 3048 3049 /* ln_device1 :: speed_debug_ln1 :: actual_speed [07:00] */ 3050 #define PHY84328_DEV1_SPEED_DEBUG_LN1_ACTUAL_SPEED_MASK 0x00ff 3051 #define PHY84328_DEV1_SPEED_DEBUG_LN1_ACTUAL_SPEED_ALIGN 0 3052 #define PHY84328_DEV1_SPEED_DEBUG_LN1_ACTUAL_SPEED_BITS 8 3053 #define PHY84328_DEV1_SPEED_DEBUG_LN1_ACTUAL_SPEED_SHIFT 0 3054 3055 3056 /**************************************************************************** 3057 * ln_device1 :: speed_debug_ln2 3058 */ 3059 /* ln_device1 :: speed_debug_ln2 :: LOS_counter [15:12] */ 3060 #define PHY84328_DEV1_SPEED_DEBUG_LN2_LOS_COUNTER_MASK 0xf000 3061 #define PHY84328_DEV1_SPEED_DEBUG_LN2_LOS_COUNTER_ALIGN 0 3062 #define PHY84328_DEV1_SPEED_DEBUG_LN2_LOS_COUNTER_BITS 4 3063 #define PHY84328_DEV1_SPEED_DEBUG_LN2_LOS_COUNTER_SHIFT 12 3064 3065 /* ln_device1 :: speed_debug_ln2 :: need_br_dfe [11:11] */ 3066 #define PHY84328_DEV1_SPEED_DEBUG_LN2_NEED_BR_DFE_MASK 0x0800 3067 #define PHY84328_DEV1_SPEED_DEBUG_LN2_NEED_BR_DFE_ALIGN 0 3068 #define PHY84328_DEV1_SPEED_DEBUG_LN2_NEED_BR_DFE_BITS 1 3069 #define PHY84328_DEV1_SPEED_DEBUG_LN2_NEED_BR_DFE_SHIFT 11 3070 3071 /* ln_device1 :: speed_debug_ln2 :: br_dfe_enabled [10:10] */ 3072 #define PHY84328_DEV1_SPEED_DEBUG_LN2_BR_DFE_ENABLED_MASK 0x0400 3073 #define PHY84328_DEV1_SPEED_DEBUG_LN2_BR_DFE_ENABLED_ALIGN 0 3074 #define PHY84328_DEV1_SPEED_DEBUG_LN2_BR_DFE_ENABLED_BITS 1 3075 #define PHY84328_DEV1_SPEED_DEBUG_LN2_BR_DFE_ENABLED_SHIFT 10 3076 3077 /* ln_device1 :: speed_debug_ln2 :: os_dfe_enabled [09:09] */ 3078 #define PHY84328_DEV1_SPEED_DEBUG_LN2_OS_DFE_ENABLED_MASK 0x0200 3079 #define PHY84328_DEV1_SPEED_DEBUG_LN2_OS_DFE_ENABLED_ALIGN 0 3080 #define PHY84328_DEV1_SPEED_DEBUG_LN2_OS_DFE_ENABLED_BITS 1 3081 #define PHY84328_DEV1_SPEED_DEBUG_LN2_OS_DFE_ENABLED_SHIFT 9 3082 3083 /* ln_device1 :: speed_debug_ln2 :: os_enabled [08:08] */ 3084 #define PHY84328_DEV1_SPEED_DEBUG_LN2_OS_ENABLED_MASK 0x0100 3085 #define PHY84328_DEV1_SPEED_DEBUG_LN2_OS_ENABLED_ALIGN 0 3086 #define PHY84328_DEV1_SPEED_DEBUG_LN2_OS_ENABLED_BITS 1 3087 #define PHY84328_DEV1_SPEED_DEBUG_LN2_OS_ENABLED_SHIFT 8 3088 3089 /* ln_device1 :: speed_debug_ln2 :: actual_speed [07:00] */ 3090 #define PHY84328_DEV1_SPEED_DEBUG_LN2_ACTUAL_SPEED_MASK 0x00ff 3091 #define PHY84328_DEV1_SPEED_DEBUG_LN2_ACTUAL_SPEED_ALIGN 0 3092 #define PHY84328_DEV1_SPEED_DEBUG_LN2_ACTUAL_SPEED_BITS 8 3093 #define PHY84328_DEV1_SPEED_DEBUG_LN2_ACTUAL_SPEED_SHIFT 0 3094 3095 3096 /**************************************************************************** 3097 * ln_device1 :: speed_debug_ln3 3098 */ 3099 /* ln_device1 :: speed_debug_ln3 :: LOS_counter [15:12] */ 3100 #define PHY84328_DEV1_SPEED_DEBUG_LN3_LOS_COUNTER_MASK 0xf000 3101 #define PHY84328_DEV1_SPEED_DEBUG_LN3_LOS_COUNTER_ALIGN 0 3102 #define PHY84328_DEV1_SPEED_DEBUG_LN3_LOS_COUNTER_BITS 4 3103 #define PHY84328_DEV1_SPEED_DEBUG_LN3_LOS_COUNTER_SHIFT 12 3104 3105 /* ln_device1 :: speed_debug_ln3 :: need_br_dfe [11:11] */ 3106 #define PHY84328_DEV1_SPEED_DEBUG_LN3_NEED_BR_DFE_MASK 0x0800 3107 #define PHY84328_DEV1_SPEED_DEBUG_LN3_NEED_BR_DFE_ALIGN 0 3108 #define PHY84328_DEV1_SPEED_DEBUG_LN3_NEED_BR_DFE_BITS 1 3109 #define PHY84328_DEV1_SPEED_DEBUG_LN3_NEED_BR_DFE_SHIFT 11 3110 3111 /* ln_device1 :: speed_debug_ln3 :: br_dfe_enabled [10:10] */ 3112 #define PHY84328_DEV1_SPEED_DEBUG_LN3_BR_DFE_ENABLED_MASK 0x0400 3113 #define PHY84328_DEV1_SPEED_DEBUG_LN3_BR_DFE_ENABLED_ALIGN 0 3114 #define PHY84328_DEV1_SPEED_DEBUG_LN3_BR_DFE_ENABLED_BITS 1 3115 #define PHY84328_DEV1_SPEED_DEBUG_LN3_BR_DFE_ENABLED_SHIFT 10 3116 3117 /* ln_device1 :: speed_debug_ln3 :: os_dfe_enabled [09:09] */ 3118 #define PHY84328_DEV1_SPEED_DEBUG_LN3_OS_DFE_ENABLED_MASK 0x0200 3119 #define PHY84328_DEV1_SPEED_DEBUG_LN3_OS_DFE_ENABLED_ALIGN 0 3120 #define PHY84328_DEV1_SPEED_DEBUG_LN3_OS_DFE_ENABLED_BITS 1 3121 #define PHY84328_DEV1_SPEED_DEBUG_LN3_OS_DFE_ENABLED_SHIFT 9 3122 3123 /* ln_device1 :: speed_debug_ln3 :: os_enabled [08:08] */ 3124 #define PHY84328_DEV1_SPEED_DEBUG_LN3_OS_ENABLED_MASK 0x0100 3125 #define PHY84328_DEV1_SPEED_DEBUG_LN3_OS_ENABLED_ALIGN 0 3126 #define PHY84328_DEV1_SPEED_DEBUG_LN3_OS_ENABLED_BITS 1 3127 #define PHY84328_DEV1_SPEED_DEBUG_LN3_OS_ENABLED_SHIFT 8 3128 3129 /* ln_device1 :: speed_debug_ln3 :: actual_speed [07:00] */ 3130 #define PHY84328_DEV1_SPEED_DEBUG_LN3_ACTUAL_SPEED_MASK 0x00ff 3131 #define PHY84328_DEV1_SPEED_DEBUG_LN3_ACTUAL_SPEED_ALIGN 0 3132 #define PHY84328_DEV1_SPEED_DEBUG_LN3_ACTUAL_SPEED_BITS 8 3133 #define PHY84328_DEV1_SPEED_DEBUG_LN3_ACTUAL_SPEED_SHIFT 0 3134 3135 3136 /**************************************************************************** 3137 * ln_device1 :: cl72_status_ln0 3138 */ 3139 /* ln_device1 :: cl72_status_ln0 :: temp_idx [15:12] */ 3140 #define PHY84328_DEV1_CL72_STATUS_LN0_TEMP_IDX_MASK 0xf000 3141 #define PHY84328_DEV1_CL72_STATUS_LN0_TEMP_IDX_ALIGN 0 3142 #define PHY84328_DEV1_CL72_STATUS_LN0_TEMP_IDX_BITS 4 3143 #define PHY84328_DEV1_CL72_STATUS_LN0_TEMP_IDX_SHIFT 12 3144 3145 /* ln_device1 :: cl72_status_ln0 :: dfe_tap1 [11:06] */ 3146 #define PHY84328_DEV1_CL72_STATUS_LN0_DFE_TAP1_MASK 0x0fc0 3147 #define PHY84328_DEV1_CL72_STATUS_LN0_DFE_TAP1_ALIGN 0 3148 #define PHY84328_DEV1_CL72_STATUS_LN0_DFE_TAP1_BITS 6 3149 #define PHY84328_DEV1_CL72_STATUS_LN0_DFE_TAP1_SHIFT 6 3150 3151 /* ln_device1 :: cl72_status_ln0 :: vga [05:00] */ 3152 #define PHY84328_DEV1_CL72_STATUS_LN0_VGA_MASK 0x003f 3153 #define PHY84328_DEV1_CL72_STATUS_LN0_VGA_ALIGN 0 3154 #define PHY84328_DEV1_CL72_STATUS_LN0_VGA_BITS 6 3155 #define PHY84328_DEV1_CL72_STATUS_LN0_VGA_SHIFT 0 3156 3157 3158 /**************************************************************************** 3159 * ln_device1 :: cl72_status_ln1 3160 */ 3161 /* ln_device1 :: cl72_status_ln1 :: temp_idx [15:12] */ 3162 #define PHY84328_DEV1_CL72_STATUS_LN1_TEMP_IDX_MASK 0xf000 3163 #define PHY84328_DEV1_CL72_STATUS_LN1_TEMP_IDX_ALIGN 0 3164 #define PHY84328_DEV1_CL72_STATUS_LN1_TEMP_IDX_BITS 4 3165 #define PHY84328_DEV1_CL72_STATUS_LN1_TEMP_IDX_SHIFT 12 3166 3167 /* ln_device1 :: cl72_status_ln1 :: dfe_tap1 [11:06] */ 3168 #define PHY84328_DEV1_CL72_STATUS_LN1_DFE_TAP1_MASK 0x0fc0 3169 #define PHY84328_DEV1_CL72_STATUS_LN1_DFE_TAP1_ALIGN 0 3170 #define PHY84328_DEV1_CL72_STATUS_LN1_DFE_TAP1_BITS 6 3171 #define PHY84328_DEV1_CL72_STATUS_LN1_DFE_TAP1_SHIFT 6 3172 3173 /* ln_device1 :: cl72_status_ln1 :: vga [05:00] */ 3174 #define PHY84328_DEV1_CL72_STATUS_LN1_VGA_MASK 0x003f 3175 #define PHY84328_DEV1_CL72_STATUS_LN1_VGA_ALIGN 0 3176 #define PHY84328_DEV1_CL72_STATUS_LN1_VGA_BITS 6 3177 #define PHY84328_DEV1_CL72_STATUS_LN1_VGA_SHIFT 0 3178 3179 3180 /**************************************************************************** 3181 * ln_device1 :: cl72_status_ln2 3182 */ 3183 /* ln_device1 :: cl72_status_ln2 :: temp_idx [15:12] */ 3184 #define PHY84328_DEV1_CL72_STATUS_LN2_TEMP_IDX_MASK 0xf000 3185 #define PHY84328_DEV1_CL72_STATUS_LN2_TEMP_IDX_ALIGN 0 3186 #define PHY84328_DEV1_CL72_STATUS_LN2_TEMP_IDX_BITS 4 3187 #define PHY84328_DEV1_CL72_STATUS_LN2_TEMP_IDX_SHIFT 12 3188 3189 /* ln_device1 :: cl72_status_ln2 :: dfe_tap1 [11:06] */ 3190 #define PHY84328_DEV1_CL72_STATUS_LN2_DFE_TAP1_MASK 0x0fc0 3191 #define PHY84328_DEV1_CL72_STATUS_LN2_DFE_TAP1_ALIGN 0 3192 #define PHY84328_DEV1_CL72_STATUS_LN2_DFE_TAP1_BITS 6 3193 #define PHY84328_DEV1_CL72_STATUS_LN2_DFE_TAP1_SHIFT 6 3194 3195 /* ln_device1 :: cl72_status_ln2 :: vga [05:00] */ 3196 #define PHY84328_DEV1_CL72_STATUS_LN2_VGA_MASK 0x003f 3197 #define PHY84328_DEV1_CL72_STATUS_LN2_VGA_ALIGN 0 3198 #define PHY84328_DEV1_CL72_STATUS_LN2_VGA_BITS 6 3199 #define PHY84328_DEV1_CL72_STATUS_LN2_VGA_SHIFT 0 3200 3201 3202 /**************************************************************************** 3203 * ln_device1 :: cl72_status_ln3 3204 */ 3205 /* ln_device1 :: cl72_status_ln3 :: temp_idx [15:12] */ 3206 #define PHY84328_DEV1_CL72_STATUS_LN3_TEMP_IDX_MASK 0xf000 3207 #define PHY84328_DEV1_CL72_STATUS_LN3_TEMP_IDX_ALIGN 0 3208 #define PHY84328_DEV1_CL72_STATUS_LN3_TEMP_IDX_BITS 4 3209 #define PHY84328_DEV1_CL72_STATUS_LN3_TEMP_IDX_SHIFT 12 3210 3211 /* ln_device1 :: cl72_status_ln3 :: dfe_tap1 [11:06] */ 3212 #define PHY84328_DEV1_CL72_STATUS_LN3_DFE_TAP1_MASK 0x0fc0 3213 #define PHY84328_DEV1_CL72_STATUS_LN3_DFE_TAP1_ALIGN 0 3214 #define PHY84328_DEV1_CL72_STATUS_LN3_DFE_TAP1_BITS 6 3215 #define PHY84328_DEV1_CL72_STATUS_LN3_DFE_TAP1_SHIFT 6 3216 3217 /* ln_device1 :: cl72_status_ln3 :: vga [05:00] */ 3218 #define PHY84328_DEV1_CL72_STATUS_LN3_VGA_MASK 0x003f 3219 #define PHY84328_DEV1_CL72_STATUS_LN3_VGA_ALIGN 0 3220 #define PHY84328_DEV1_CL72_STATUS_LN3_VGA_BITS 6 3221 #define PHY84328_DEV1_CL72_STATUS_LN3_VGA_SHIFT 0 3222 3223 3224 /**************************************************************************** 3225 * ln_device1 :: version 3226 */ 3227 /* ln_device1 :: version :: version [15:00] */ 3228 #define PHY84328_DEV1_VERSION_VERSION_MASK 0xffff 3229 #define PHY84328_DEV1_VERSION_VERSION_ALIGN 0 3230 #define PHY84328_DEV1_VERSION_VERSION_BITS 16 3231 #define PHY84328_DEV1_VERSION_VERSION_SHIFT 0 3232 3233 3234 /**************************************************************************** 3235 * ln_device1 :: target 3236 */ 3237 /* ln_device1 :: target :: target [15:00] */ 3238 #define PHY84328_DEV1_TARGET_TARGET_MASK 0xffff 3239 #define PHY84328_DEV1_TARGET_TARGET_ALIGN 0 3240 #define PHY84328_DEV1_TARGET_TARGET_BITS 16 3241 #define PHY84328_DEV1_TARGET_TARGET_SHIFT 0 3242 3243 3244 /**************************************************************************** 3245 * ln_device1 :: firmware_mode 3246 */ 3247 /* ln_device1 :: firmware_mode :: LN3_mode [15:12] */ 3248 #define PHY84328_DEV1_FIRMWARE_MODE_LN3_MODE_MASK 0xf000 3249 #define PHY84328_DEV1_FIRMWARE_MODE_LN3_MODE_ALIGN 0 3250 #define PHY84328_DEV1_FIRMWARE_MODE_LN3_MODE_BITS 4 3251 #define PHY84328_DEV1_FIRMWARE_MODE_LN3_MODE_SHIFT 12 3252 3253 /* ln_device1 :: firmware_mode :: LN2_mode [11:08] */ 3254 #define PHY84328_DEV1_FIRMWARE_MODE_LN2_MODE_MASK 0x0f00 3255 #define PHY84328_DEV1_FIRMWARE_MODE_LN2_MODE_ALIGN 0 3256 #define PHY84328_DEV1_FIRMWARE_MODE_LN2_MODE_BITS 4 3257 #define PHY84328_DEV1_FIRMWARE_MODE_LN2_MODE_SHIFT 8 3258 3259 /* ln_device1 :: firmware_mode :: LN1_mode [07:04] */ 3260 #define PHY84328_DEV1_FIRMWARE_MODE_LN1_MODE_MASK 0x00f0 3261 #define PHY84328_DEV1_FIRMWARE_MODE_LN1_MODE_ALIGN 0 3262 #define PHY84328_DEV1_FIRMWARE_MODE_LN1_MODE_BITS 4 3263 #define PHY84328_DEV1_FIRMWARE_MODE_LN1_MODE_SHIFT 4 3264 3265 /* ln_device1 :: firmware_mode :: LN0_mode [03:00] */ 3266 #define PHY84328_DEV1_FIRMWARE_MODE_LN0_MODE_MASK 0x000f 3267 #define PHY84328_DEV1_FIRMWARE_MODE_LN0_MODE_ALIGN 0 3268 #define PHY84328_DEV1_FIRMWARE_MODE_LN0_MODE_BITS 4 3269 #define PHY84328_DEV1_FIRMWARE_MODE_LN0_MODE_SHIFT 0 3270 3271 3272 /**************************************************************************** 3273 * ln_device1 :: gpio_ctrl_ln0 3274 */ 3275 /* ln_device1 :: gpio_ctrl_ln0 :: GPIO_CTRL_LN0 [15:00] */ 3276 #define PHY84328_DEV1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_MASK 0xffff 3277 #define PHY84328_DEV1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_ALIGN 0 3278 #define PHY84328_DEV1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_BITS 16 3279 #define PHY84328_DEV1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_SHIFT 0 3280 3281 3282 /**************************************************************************** 3283 * ln_device1 :: gpio_ctrl_ln1 3284 */ 3285 /* ln_device1 :: gpio_ctrl_ln1 :: GPIO_CTRL_LN1 [15:00] */ 3286 #define PHY84328_DEV1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_MASK 0xffff 3287 #define PHY84328_DEV1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_ALIGN 0 3288 #define PHY84328_DEV1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_BITS 16 3289 #define PHY84328_DEV1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_SHIFT 0 3290 3291 3292 /**************************************************************************** 3293 * ln_device1 :: gpio_ctrl_ln2 3294 */ 3295 /* ln_device1 :: gpio_ctrl_ln2 :: GPIO_CTRL_LN2 [15:00] */ 3296 #define PHY84328_DEV1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_MASK 0xffff 3297 #define PHY84328_DEV1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_ALIGN 0 3298 #define PHY84328_DEV1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_BITS 16 3299 #define PHY84328_DEV1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_SHIFT 0 3300 3301 3302 /**************************************************************************** 3303 * ln_device1 :: gpio_ctrl_ln3 3304 */ 3305 /* ln_device1 :: gpio_ctrl_ln3 :: GPIO_CTRL_LN3 [15:00] */ 3306 #define PHY84328_DEV1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_MASK 0xffff 3307 #define PHY84328_DEV1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_ALIGN 0 3308 #define PHY84328_DEV1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_BITS 16 3309 #define PHY84328_DEV1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_SHIFT 0 3310 3311 3312 /**************************************************************************** 3313 * ln_device1 :: gpio_sts_ln0 3314 */ 3315 /* ln_device1 :: gpio_sts_ln0 :: GPIO_STS_LN0 [15:00] */ 3316 #define PHY84328_DEV1_GPIO_STS_LN0_GPIO_STS_LN0_MASK 0xffff 3317 #define PHY84328_DEV1_GPIO_STS_LN0_GPIO_STS_LN0_ALIGN 0 3318 #define PHY84328_DEV1_GPIO_STS_LN0_GPIO_STS_LN0_BITS 16 3319 #define PHY84328_DEV1_GPIO_STS_LN0_GPIO_STS_LN0_SHIFT 0 3320 3321 3322 /**************************************************************************** 3323 * ln_device1 :: gpio_sts_ln1 3324 */ 3325 /* ln_device1 :: gpio_sts_ln1 :: GPIO_STS_LN1 [15:00] */ 3326 #define PHY84328_DEV1_GPIO_STS_LN1_GPIO_STS_LN1_MASK 0xffff 3327 #define PHY84328_DEV1_GPIO_STS_LN1_GPIO_STS_LN1_ALIGN 0 3328 #define PHY84328_DEV1_GPIO_STS_LN1_GPIO_STS_LN1_BITS 16 3329 #define PHY84328_DEV1_GPIO_STS_LN1_GPIO_STS_LN1_SHIFT 0 3330 3331 3332 /**************************************************************************** 3333 * ln_device1 :: gpio_sts_ln2 3334 */ 3335 /* ln_device1 :: gpio_sts_ln2 :: GPIO_STS_LN2 [15:00] */ 3336 #define PHY84328_DEV1_GPIO_STS_LN2_GPIO_STS_LN2_MASK 0xffff 3337 #define PHY84328_DEV1_GPIO_STS_LN2_GPIO_STS_LN2_ALIGN 0 3338 #define PHY84328_DEV1_GPIO_STS_LN2_GPIO_STS_LN2_BITS 16 3339 #define PHY84328_DEV1_GPIO_STS_LN2_GPIO_STS_LN2_SHIFT 0 3340 3341 3342 /**************************************************************************** 3343 * ln_device1 :: gpio_sts_ln3 3344 */ 3345 /* ln_device1 :: gpio_sts_ln3 :: GPIO_STS_LN3 [15:00] */ 3346 #define PHY84328_DEV1_GPIO_STS_LN3_GPIO_STS_LN3_MASK 0xffff 3347 #define PHY84328_DEV1_GPIO_STS_LN3_GPIO_STS_LN3_ALIGN 0 3348 #define PHY84328_DEV1_GPIO_STS_LN3_GPIO_STS_LN3_BITS 16 3349 #define PHY84328_DEV1_GPIO_STS_LN3_GPIO_STS_LN3_SHIFT 0 3350 3351 3352 /**************************************************************************** 3353 * ln_device1 :: regB 3354 */ 3355 /* ln_device1 :: regB :: reserved_for_eco0 [15:00] */ 3356 #define PHY84328_DEV1_REGB_RESERVED_FOR_ECO0_MASK 0xffff 3357 #define PHY84328_DEV1_REGB_RESERVED_FOR_ECO0_ALIGN 0 3358 #define PHY84328_DEV1_REGB_RESERVED_FOR_ECO0_BITS 16 3359 #define PHY84328_DEV1_REGB_RESERVED_FOR_ECO0_SHIFT 0 3360 3361 3362 /**************************************************************************** 3363 * ln_device1 :: tuning_state_bypass 3364 */ 3365 /* ln_device1 :: tuning_state_bypass :: reserved_for_eco0 [15:09] */ 3366 #define PHY84328_DEV1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_MASK 0xfe00 3367 #define PHY84328_DEV1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_ALIGN 0 3368 #define PHY84328_DEV1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_BITS 7 3369 #define PHY84328_DEV1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_SHIFT 9 3370 3371 /* ln_device1 :: tuning_state_bypass :: bypass_steady_state_tuning [08:08] */ 3372 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_MASK 0x0100 3373 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_ALIGN 0 3374 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_BITS 1 3375 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_SHIFT 8 3376 3377 /* ln_device1 :: tuning_state_bypass :: bypass_cdr_lock_monitor [07:07] */ 3378 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_MASK 0x0080 3379 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_ALIGN 0 3380 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_BITS 1 3381 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_SHIFT 7 3382 3383 /* ln_device1 :: tuning_state_bypass :: bypass_dcd_tuning [06:06] */ 3384 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_MASK 0x0040 3385 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_ALIGN 0 3386 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_BITS 1 3387 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_SHIFT 6 3388 3389 /* ln_device1 :: tuning_state_bypass :: bypass_slicer_offset_tuning [05:05] */ 3390 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_MASK 0x0020 3391 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_ALIGN 0 3392 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_BITS 1 3393 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_SHIFT 5 3394 3395 /* ln_device1 :: tuning_state_bypass :: bypass_slicer_target_tuning [04:04] */ 3396 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_MASK 0x0010 3397 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_ALIGN 0 3398 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_BITS 1 3399 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_SHIFT 4 3400 3401 /* ln_device1 :: tuning_state_bypass :: bypass_vga_bias_tuning [03:03] */ 3402 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_MASK 0x0008 3403 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_ALIGN 0 3404 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_BITS 1 3405 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_SHIFT 3 3406 3407 /* ln_device1 :: tuning_state_bypass :: bypass_pf_tuning [02:02] */ 3408 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_MASK 0x0004 3409 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_ALIGN 0 3410 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_BITS 1 3411 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_SHIFT 2 3412 3413 /* ln_device1 :: tuning_state_bypass :: bypass_clk90_tuning [01:01] */ 3414 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_MASK 0x0002 3415 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_ALIGN 0 3416 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_BITS 1 3417 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_SHIFT 1 3418 3419 /* ln_device1 :: tuning_state_bypass :: bypass_os_vga_tuning [00:00] */ 3420 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_MASK 0x0001 3421 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_ALIGN 0 3422 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_BITS 1 3423 #define PHY84328_DEV1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_SHIFT 0 3424 3425 3426 /**************************************************************************** 3427 * ln_device1 :: temperature 3428 */ 3429 /* ln_device1 :: temperature :: force_temperature [15:15] */ 3430 #define PHY84328_DEV1_TEMPERATURE_FORCE_TEMPERATURE_MASK 0x8000 3431 #define PHY84328_DEV1_TEMPERATURE_FORCE_TEMPERATURE_ALIGN 0 3432 #define PHY84328_DEV1_TEMPERATURE_FORCE_TEMPERATURE_BITS 1 3433 #define PHY84328_DEV1_TEMPERATURE_FORCE_TEMPERATURE_SHIFT 15 3434 3435 /* ln_device1 :: temperature :: reserved_for_eco0 [14:14] */ 3436 #define PHY84328_DEV1_TEMPERATURE_RESERVED_FOR_ECO0_MASK 0x4000 3437 #define PHY84328_DEV1_TEMPERATURE_RESERVED_FOR_ECO0_ALIGN 0 3438 #define PHY84328_DEV1_TEMPERATURE_RESERVED_FOR_ECO0_BITS 1 3439 #define PHY84328_DEV1_TEMPERATURE_RESERVED_FOR_ECO0_SHIFT 14 3440 3441 /* ln_device1 :: temperature :: temp_idx [13:10] */ 3442 #define PHY84328_DEV1_TEMPERATURE_TEMP_IDX_MASK 0x3c00 3443 #define PHY84328_DEV1_TEMPERATURE_TEMP_IDX_ALIGN 0 3444 #define PHY84328_DEV1_TEMPERATURE_TEMP_IDX_BITS 4 3445 #define PHY84328_DEV1_TEMPERATURE_TEMP_IDX_SHIFT 10 3446 3447 /* ln_device1 :: temperature :: temperature [09:00] */ 3448 #define PHY84328_DEV1_TEMPERATURE_TEMPERATURE_MASK 0x03ff 3449 #define PHY84328_DEV1_TEMPERATURE_TEMPERATURE_ALIGN 0 3450 #define PHY84328_DEV1_TEMPERATURE_TEMPERATURE_BITS 10 3451 #define PHY84328_DEV1_TEMPERATURE_TEMPERATURE_SHIFT 0 3452 3453 3454 /**************************************************************************** 3455 * ln_device1 :: crc 3456 */ 3457 /* ln_device1 :: crc :: crc [15:00] */ 3458 #define PHY84328_DEV1_CRC_CRC_MASK 0xffff 3459 #define PHY84328_DEV1_CRC_CRC_ALIGN 0 3460 #define PHY84328_DEV1_CRC_CRC_BITS 16 3461 #define PHY84328_DEV1_CRC_CRC_SHIFT 0 3462 3463 3464 /**************************************************************************** 3465 * ln_device1_PMD_User_Defined_Registers 3466 */ 3467 /**************************************************************************** 3468 * ln_device1 :: pwr_ramp 3469 */ 3470 /* ln_device1 :: pwr_ramp :: pwr_on_en15_0 [15:00] */ 3471 #define PHY84328_DEV1_PWR_RAMP_PWR_ON_EN15_0_MASK 0xffff 3472 #define PHY84328_DEV1_PWR_RAMP_PWR_ON_EN15_0_ALIGN 0 3473 #define PHY84328_DEV1_PWR_RAMP_PWR_ON_EN15_0_BITS 16 3474 #define PHY84328_DEV1_PWR_RAMP_PWR_ON_EN15_0_SHIFT 0 3475 3476 3477 /**************************************************************************** 3478 * ln_device1 :: chip_rev_register 3479 */ 3480 /* ln_device1 :: chip_rev_register :: reserved0 [15:08] */ 3481 #define PHY84328_DEV1_CHIP_REV_REGISTER_RESERVED0_MASK 0xff00 3482 #define PHY84328_DEV1_CHIP_REV_REGISTER_RESERVED0_ALIGN 0 3483 #define PHY84328_DEV1_CHIP_REV_REGISTER_RESERVED0_BITS 8 3484 #define PHY84328_DEV1_CHIP_REV_REGISTER_RESERVED0_SHIFT 8 3485 3486 /* ln_device1 :: chip_rev_register :: rev [07:00] */ 3487 #define PHY84328_DEV1_CHIP_REV_REGISTER_REV_MASK 0x00ff 3488 #define PHY84328_DEV1_CHIP_REV_REGISTER_REV_ALIGN 0 3489 #define PHY84328_DEV1_CHIP_REV_REGISTER_REV_BITS 8 3490 #define PHY84328_DEV1_CHIP_REV_REGISTER_REV_SHIFT 0 3491 3492 3493 /**************************************************************************** 3494 * ln_device1 :: chip_id0_register 3495 */ 3496 /* ln_device1 :: chip_id0_register :: chip_id_lower [15:00] */ 3497 #define PHY84328_DEV1_CHIP_ID0_REGISTER_CHIP_ID_LOWER_MASK 0xffff 3498 #define PHY84328_DEV1_CHIP_ID0_REGISTER_CHIP_ID_LOWER_ALIGN 0 3499 #define PHY84328_DEV1_CHIP_ID0_REGISTER_CHIP_ID_LOWER_BITS 16 3500 #define PHY84328_DEV1_CHIP_ID0_REGISTER_CHIP_ID_LOWER_SHIFT 0 3501 3502 3503 /**************************************************************************** 3504 * ln_device1 :: chip_id1_register 3505 */ 3506 /* ln_device1 :: chip_id1_register :: reserved0 [15:04] */ 3507 #define PHY84328_DEV1_CHIP_ID1_REGISTER_RESERVED0_MASK 0xfff0 3508 #define PHY84328_DEV1_CHIP_ID1_REGISTER_RESERVED0_ALIGN 0 3509 #define PHY84328_DEV1_CHIP_ID1_REGISTER_RESERVED0_BITS 12 3510 #define PHY84328_DEV1_CHIP_ID1_REGISTER_RESERVED0_SHIFT 4 3511 3512 /* ln_device1 :: chip_id1_register :: chip_id_upper [03:00] */ 3513 #define PHY84328_DEV1_CHIP_ID1_REGISTER_CHIP_ID_UPPER_MASK 0x000f 3514 #define PHY84328_DEV1_CHIP_ID1_REGISTER_CHIP_ID_UPPER_ALIGN 0 3515 #define PHY84328_DEV1_CHIP_ID1_REGISTER_CHIP_ID_UPPER_BITS 4 3516 #define PHY84328_DEV1_CHIP_ID1_REGISTER_CHIP_ID_UPPER_SHIFT 0 3517 3518 3519 /**************************************************************************** 3520 * ln_device1 :: pmd_status_register 3521 */ 3522 /* ln_device1 :: pmd_status_register :: reserved0 [15:08] */ 3523 #define PHY84328_DEV1_PMD_STATUS_REGISTER_RESERVED0_MASK 0xff00 3524 #define PHY84328_DEV1_PMD_STATUS_REGISTER_RESERVED0_ALIGN 0 3525 #define PHY84328_DEV1_PMD_STATUS_REGISTER_RESERVED0_BITS 8 3526 #define PHY84328_DEV1_PMD_STATUS_REGISTER_RESERVED0_SHIFT 8 3527 3528 /* ln_device1 :: pmd_status_register :: sys_lkdtcmu [07:07] */ 3529 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LKDTCMU_MASK 0x0080 3530 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LKDTCMU_ALIGN 0 3531 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LKDTCMU_BITS 1 3532 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LKDTCMU_SHIFT 7 3533 3534 /* ln_device1 :: pmd_status_register :: sys_lkdtcdr [06:06] */ 3535 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LKDTCDR_MASK 0x0040 3536 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LKDTCDR_ALIGN 0 3537 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LKDTCDR_BITS 1 3538 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LKDTCDR_SHIFT 6 3539 3540 /* ln_device1 :: pmd_status_register :: reserved1 [05:05] */ 3541 #define PHY84328_DEV1_PMD_STATUS_REGISTER_RESERVED1_MASK 0x0020 3542 #define PHY84328_DEV1_PMD_STATUS_REGISTER_RESERVED1_ALIGN 0 3543 #define PHY84328_DEV1_PMD_STATUS_REGISTER_RESERVED1_BITS 1 3544 #define PHY84328_DEV1_PMD_STATUS_REGISTER_RESERVED1_SHIFT 5 3545 3546 /* ln_device1 :: pmd_status_register :: sys_los [04:04] */ 3547 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LOS_MASK 0x0010 3548 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LOS_ALIGN 0 3549 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LOS_BITS 1 3550 #define PHY84328_DEV1_PMD_STATUS_REGISTER_SYS_LOS_SHIFT 4 3551 3552 /* ln_device1 :: pmd_status_register :: ln_lkdtcmu [03:03] */ 3553 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LKDTCMU_MASK 0x0008 3554 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LKDTCMU_ALIGN 0 3555 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LKDTCMU_BITS 1 3556 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LKDTCMU_SHIFT 3 3557 3558 /* ln_device1 :: pmd_status_register :: ln_lkdtcdr [02:02] */ 3559 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LKDTCDR_MASK 0x0004 3560 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LKDTCDR_ALIGN 0 3561 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LKDTCDR_BITS 1 3562 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LKDTCDR_SHIFT 2 3563 3564 /* ln_device1 :: pmd_status_register :: oplosb [01:01] */ 3565 #define PHY84328_DEV1_PMD_STATUS_REGISTER_OPLOSB_MASK 0x0002 3566 #define PHY84328_DEV1_PMD_STATUS_REGISTER_OPLOSB_ALIGN 0 3567 #define PHY84328_DEV1_PMD_STATUS_REGISTER_OPLOSB_BITS 1 3568 #define PHY84328_DEV1_PMD_STATUS_REGISTER_OPLOSB_SHIFT 1 3569 3570 /* ln_device1 :: pmd_status_register :: ln_los [00:00] */ 3571 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LOS_MASK 0x0001 3572 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LOS_ALIGN 0 3573 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LOS_BITS 1 3574 #define PHY84328_DEV1_PMD_STATUS_REGISTER_LN_LOS_SHIFT 0 3575 3576 3577 /**************************************************************************** 3578 * ln_device1 :: gpio_control_register 3579 */ 3580 /* ln_device1 :: gpio_control_register :: reserved0 [15:07] */ 3581 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_RESERVED0_MASK 0xff80 3582 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_RESERVED0_ALIGN 0 3583 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_RESERVED0_BITS 9 3584 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_RESERVED0_SHIFT 7 3585 3586 /* ln_device1 :: gpio_control_register :: gpio_sel [06:04] */ 3587 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_GPIO_SEL_MASK 0x0070 3588 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_GPIO_SEL_ALIGN 0 3589 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_GPIO_SEL_BITS 3 3590 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_GPIO_SEL_SHIFT 4 3591 3592 /* ln_device1 :: gpio_control_register :: reserved1 [03:02] */ 3593 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_RESERVED1_MASK 0x000c 3594 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_RESERVED1_ALIGN 0 3595 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_RESERVED1_BITS 2 3596 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_RESERVED1_SHIFT 2 3597 3598 /* ln_device1 :: gpio_control_register :: sel_txdis_as_gpio1 [01:01] */ 3599 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_SEL_TXDIS_AS_GPIO1_MASK 0x0002 3600 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_SEL_TXDIS_AS_GPIO1_ALIGN 0 3601 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_SEL_TXDIS_AS_GPIO1_BITS 1 3602 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_SEL_TXDIS_AS_GPIO1_SHIFT 1 3603 3604 /* ln_device1 :: gpio_control_register :: sel_txon_as_gpio0 [00:00] */ 3605 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_SEL_TXON_AS_GPIO0_MASK 0x0001 3606 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_SEL_TXON_AS_GPIO0_ALIGN 0 3607 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_SEL_TXON_AS_GPIO0_BITS 1 3608 #define PHY84328_DEV1_GPIO_CONTROL_REGISTER_SEL_TXON_AS_GPIO0_SHIFT 0 3609 3610 3611 /**************************************************************************** 3612 * ln_device1 :: ring_osc_control_register 3613 */ 3614 /* ln_device1 :: ring_osc_control_register :: osc_sel1 [15:12] */ 3615 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_SEL1_MASK 0xf000 3616 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_SEL1_ALIGN 0 3617 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_SEL1_BITS 4 3618 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_SEL1_SHIFT 12 3619 3620 /* ln_device1 :: ring_osc_control_register :: osc_sel0 [11:08] */ 3621 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_SEL0_MASK 0x0f00 3622 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_SEL0_ALIGN 0 3623 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_SEL0_BITS 4 3624 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_SEL0_SHIFT 8 3625 3626 /* ln_device1 :: ring_osc_control_register :: osc_pwenb [07:04] */ 3627 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_PWENB_MASK 0x00f0 3628 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_PWENB_ALIGN 0 3629 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_PWENB_BITS 4 3630 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_PWENB_SHIFT 4 3631 3632 /* ln_device1 :: ring_osc_control_register :: osc_ent [03:00] */ 3633 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_ENT_MASK 0x000f 3634 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_ENT_ALIGN 0 3635 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_ENT_BITS 4 3636 #define PHY84328_DEV1_RING_OSC_CONTROL_REGISTER_OSC_ENT_SHIFT 0 3637 3638 3639 /**************************************************************************** 3640 * ln_device1 :: gp_io_control_register 3641 */ 3642 /* ln_device1 :: gp_io_control_register :: reserved0 [15:10] */ 3643 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED0_MASK 0xfc00 3644 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED0_ALIGN 0 3645 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED0_BITS 6 3646 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED0_SHIFT 10 3647 3648 /* ln_device1 :: gp_io_control_register :: in_gp_dat [09:08] */ 3649 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_IN_GP_DAT_MASK 0x0300 3650 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_IN_GP_DAT_ALIGN 0 3651 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_IN_GP_DAT_BITS 2 3652 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_IN_GP_DAT_SHIFT 8 3653 3654 /* ln_device1 :: gp_io_control_register :: reserved1 [07:06] */ 3655 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED1_MASK 0x00c0 3656 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED1_ALIGN 0 3657 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED1_BITS 2 3658 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED1_SHIFT 6 3659 3660 /* ln_device1 :: gp_io_control_register :: out_gp_dis [05:04] */ 3661 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_OUT_GP_DIS_MASK 0x0030 3662 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_OUT_GP_DIS_ALIGN 0 3663 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_OUT_GP_DIS_BITS 2 3664 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_OUT_GP_DIS_SHIFT 4 3665 3666 /* ln_device1 :: gp_io_control_register :: reserved2 [03:02] */ 3667 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED2_MASK 0x000c 3668 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED2_ALIGN 0 3669 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED2_BITS 2 3670 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_RESERVED2_SHIFT 2 3671 3672 /* ln_device1 :: gp_io_control_register :: out_gp_dat [01:00] */ 3673 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_OUT_GP_DAT_MASK 0x0003 3674 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_OUT_GP_DAT_ALIGN 0 3675 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_OUT_GP_DAT_BITS 2 3676 #define PHY84328_DEV1_GP_IO_CONTROL_REGISTER_OUT_GP_DAT_SHIFT 0 3677 3678 3679 /**************************************************************************** 3680 * ln_device1 :: speed_link_detect_status 3681 */ 3682 /* ln_device1 :: speed_link_detect_status :: sys_rx_sigdet [15:15] */ 3683 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_RX_SIGDET_MASK 0x8000 3684 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_RX_SIGDET_ALIGN 0 3685 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_RX_SIGDET_BITS 1 3686 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_RX_SIGDET_SHIFT 15 3687 3688 /* ln_device1 :: speed_link_detect_status :: sys_an_complete [14:14] */ 3689 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_AN_COMPLETE_MASK 0x4000 3690 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_AN_COMPLETE_ALIGN 0 3691 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_AN_COMPLETE_BITS 1 3692 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_AN_COMPLETE_SHIFT 14 3693 3694 /* ln_device1 :: speed_link_detect_status :: sys_pmd_speed40G [13:13] */ 3695 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED40G_MASK 0x2000 3696 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED40G_ALIGN 0 3697 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED40G_BITS 1 3698 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED40G_SHIFT 13 3699 3700 /* ln_device1 :: speed_link_detect_status :: sys_pmd_speed10G [12:12] */ 3701 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10G_MASK 0x1000 3702 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10G_ALIGN 0 3703 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10G_BITS 1 3704 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10G_SHIFT 12 3705 3706 /* ln_device1 :: speed_link_detect_status :: reserved0 [11:11] */ 3707 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_RESERVED0_MASK 0x0800 3708 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_RESERVED0_ALIGN 0 3709 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_RESERVED0_BITS 1 3710 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_RESERVED0_SHIFT 11 3711 3712 /* ln_device1 :: speed_link_detect_status :: sys_pmd_speed1G [10:10] */ 3713 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED1G_MASK 0x0400 3714 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED1G_ALIGN 0 3715 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED1G_BITS 1 3716 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED1G_SHIFT 10 3717 3718 /* ln_device1 :: speed_link_detect_status :: sys_pmd_speed100M [09:09] */ 3719 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED100M_MASK 0x0200 3720 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED100M_ALIGN 0 3721 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED100M_BITS 1 3722 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED100M_SHIFT 9 3723 3724 /* ln_device1 :: speed_link_detect_status :: sys_pmd_speed10M [08:08] */ 3725 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10M_MASK 0x0100 3726 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10M_ALIGN 0 3727 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10M_BITS 1 3728 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10M_SHIFT 8 3729 3730 /* ln_device1 :: speed_link_detect_status :: ln_rx_sigdet [07:07] */ 3731 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_RX_SIGDET_MASK 0x0080 3732 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_RX_SIGDET_ALIGN 0 3733 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_RX_SIGDET_BITS 1 3734 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_RX_SIGDET_SHIFT 7 3735 3736 /* ln_device1 :: speed_link_detect_status :: ln_an_complete [06:06] */ 3737 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_AN_COMPLETE_MASK 0x0040 3738 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_AN_COMPLETE_ALIGN 0 3739 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_AN_COMPLETE_BITS 1 3740 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_AN_COMPLETE_SHIFT 6 3741 3742 /* ln_device1 :: speed_link_detect_status :: ln_pmd_speed40g [05:05] */ 3743 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED40G_MASK 0x0020 3744 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED40G_ALIGN 0 3745 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED40G_BITS 1 3746 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED40G_SHIFT 5 3747 3748 /* ln_device1 :: speed_link_detect_status :: ln_pmd_speed10G [04:04] */ 3749 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10G_MASK 0x0010 3750 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10G_ALIGN 0 3751 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10G_BITS 1 3752 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10G_SHIFT 4 3753 3754 /* ln_device1 :: speed_link_detect_status :: reserved1 [03:03] */ 3755 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_RESERVED1_MASK 0x0008 3756 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_RESERVED1_ALIGN 0 3757 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_RESERVED1_BITS 1 3758 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_RESERVED1_SHIFT 3 3759 3760 /* ln_device1 :: speed_link_detect_status :: ln_pmd_speed1G [02:02] */ 3761 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED1G_MASK 0x0004 3762 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED1G_ALIGN 0 3763 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED1G_BITS 1 3764 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED1G_SHIFT 2 3765 3766 /* ln_device1 :: speed_link_detect_status :: ln_pmd_speed100M [01:01] */ 3767 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED100M_MASK 0x0002 3768 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED100M_ALIGN 0 3769 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED100M_BITS 1 3770 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED100M_SHIFT 1 3771 3772 /* ln_device1 :: speed_link_detect_status :: ln_pmd_speed10M [00:00] */ 3773 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10M_MASK 0x0001 3774 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10M_ALIGN 0 3775 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10M_BITS 1 3776 #define PHY84328_DEV1_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10M_SHIFT 0 3777 3778 3779 /**************************************************************************** 3780 * ln_device1 :: ch_reset_control 3781 */ 3782 /* ln_device1 :: ch_reset_control :: cl73_manhw_rst_n [15:12] */ 3783 #define PHY84328_DEV1_CH_RESET_CONTROL_CL73_MANHW_RST_N_MASK 0xf000 3784 #define PHY84328_DEV1_CH_RESET_CONTROL_CL73_MANHW_RST_N_ALIGN 0 3785 #define PHY84328_DEV1_CH_RESET_CONTROL_CL73_MANHW_RST_N_BITS 4 3786 #define PHY84328_DEV1_CH_RESET_CONTROL_CL73_MANHW_RST_N_SHIFT 12 3787 3788 /* ln_device1 :: ch_reset_control :: cl73_mandp_rst_n [11:08] */ 3789 #define PHY84328_DEV1_CH_RESET_CONTROL_CL73_MANDP_RST_N_MASK 0x0f00 3790 #define PHY84328_DEV1_CH_RESET_CONTROL_CL73_MANDP_RST_N_ALIGN 0 3791 #define PHY84328_DEV1_CH_RESET_CONTROL_CL73_MANDP_RST_N_BITS 4 3792 #define PHY84328_DEV1_CH_RESET_CONTROL_CL73_MANDP_RST_N_SHIFT 8 3793 3794 /* ln_device1 :: ch_reset_control :: xcl73_manhw_rst_n [07:04] */ 3795 #define PHY84328_DEV1_CH_RESET_CONTROL_XCL73_MANHW_RST_N_MASK 0x00f0 3796 #define PHY84328_DEV1_CH_RESET_CONTROL_XCL73_MANHW_RST_N_ALIGN 0 3797 #define PHY84328_DEV1_CH_RESET_CONTROL_XCL73_MANHW_RST_N_BITS 4 3798 #define PHY84328_DEV1_CH_RESET_CONTROL_XCL73_MANHW_RST_N_SHIFT 4 3799 3800 /* ln_device1 :: ch_reset_control :: xcl73_mandp_rst_n [03:00] */ 3801 #define PHY84328_DEV1_CH_RESET_CONTROL_XCL73_MANDP_RST_N_MASK 0x000f 3802 #define PHY84328_DEV1_CH_RESET_CONTROL_XCL73_MANDP_RST_N_ALIGN 0 3803 #define PHY84328_DEV1_CH_RESET_CONTROL_XCL73_MANDP_RST_N_BITS 4 3804 #define PHY84328_DEV1_CH_RESET_CONTROL_XCL73_MANDP_RST_N_SHIFT 0 3805 3806 3807 /**************************************************************************** 3808 * ln_device1 :: cl73_parallel_port_address_port 3809 */ 3810 /* ln_device1 :: cl73_parallel_port_address_port :: reserved0 [15:13] */ 3811 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_MASK 0xe000 3812 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_ALIGN 0 3813 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_BITS 3 3814 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_SHIFT 13 3815 3816 /* ln_device1 :: cl73_parallel_port_address_port :: cl73_pmd_aer [12:08] */ 3817 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_MASK 0x1f00 3818 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_ALIGN 0 3819 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_BITS 5 3820 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_SHIFT 8 3821 3822 /* ln_device1 :: cl73_parallel_port_address_port :: reserved1 [07:05] */ 3823 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_MASK 0x00e0 3824 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_ALIGN 0 3825 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_BITS 3 3826 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_SHIFT 5 3827 3828 /* ln_device1 :: cl73_parallel_port_address_port :: cl73_ang_aer [04:00] */ 3829 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_MASK 0x001f 3830 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_ALIGN 0 3831 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_BITS 5 3832 #define PHY84328_DEV1_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_SHIFT 0 3833 3834 3835 /**************************************************************************** 3836 * ln_device1 :: xcl73_parallel_port_address_port 3837 */ 3838 /* ln_device1 :: xcl73_parallel_port_address_port :: reserved0 [15:13] */ 3839 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_MASK 0xe000 3840 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_ALIGN 0 3841 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_BITS 3 3842 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_SHIFT 13 3843 3844 /* ln_device1 :: xcl73_parallel_port_address_port :: cl73_pmd_aer [12:08] */ 3845 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_MASK 0x1f00 3846 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_ALIGN 0 3847 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_BITS 5 3848 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_SHIFT 8 3849 3850 /* ln_device1 :: xcl73_parallel_port_address_port :: reserved1 [07:05] */ 3851 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_MASK 0x00e0 3852 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_ALIGN 0 3853 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_BITS 3 3854 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_SHIFT 5 3855 3856 /* ln_device1 :: xcl73_parallel_port_address_port :: cl73_ang_aer [04:00] */ 3857 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_MASK 0x001f 3858 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_ALIGN 0 3859 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_BITS 5 3860 #define PHY84328_DEV1_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_SHIFT 0 3861 3862 3863 /**************************************************************************** 3864 * ln_device1 :: pad_ctrl_register 3865 */ 3866 /* ln_device1 :: pad_ctrl_register :: i2c_pad_func_ctrl [15:15] */ 3867 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_PAD_FUNC_CTRL_MASK 0x8000 3868 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_PAD_FUNC_CTRL_ALIGN 0 3869 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_PAD_FUNC_CTRL_BITS 1 3870 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_PAD_FUNC_CTRL_SHIFT 15 3871 3872 /* ln_device1 :: pad_ctrl_register :: i2c_scl_pad_input [14:14] */ 3873 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_PAD_INPUT_MASK 0x4000 3874 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_PAD_INPUT_ALIGN 0 3875 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_PAD_INPUT_BITS 1 3876 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_PAD_INPUT_SHIFT 14 3877 3878 /* ln_device1 :: pad_ctrl_register :: i2c_scl_dir_ctrl [13:13] */ 3879 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_DIR_CTRL_MASK 0x2000 3880 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_DIR_CTRL_ALIGN 0 3881 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_DIR_CTRL_BITS 1 3882 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_DIR_CTRL_SHIFT 13 3883 3884 /* ln_device1 :: pad_ctrl_register :: i2c_scl_output [12:12] */ 3885 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_OUTPUT_MASK 0x1000 3886 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_OUTPUT_ALIGN 0 3887 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_OUTPUT_BITS 1 3888 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SCL_OUTPUT_SHIFT 12 3889 3890 /* ln_device1 :: pad_ctrl_register :: reserved0 [11:11] */ 3891 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED0_MASK 0x0800 3892 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED0_ALIGN 0 3893 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED0_BITS 1 3894 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED0_SHIFT 11 3895 3896 /* ln_device1 :: pad_ctrl_register :: i2c_sda_pad_input [10:10] */ 3897 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_PAD_INPUT_MASK 0x0400 3898 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_PAD_INPUT_ALIGN 0 3899 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_PAD_INPUT_BITS 1 3900 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_PAD_INPUT_SHIFT 10 3901 3902 /* ln_device1 :: pad_ctrl_register :: i2c_sda_dir_ctrl [09:09] */ 3903 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_DIR_CTRL_MASK 0x0200 3904 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_DIR_CTRL_ALIGN 0 3905 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_DIR_CTRL_BITS 1 3906 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_DIR_CTRL_SHIFT 9 3907 3908 /* ln_device1 :: pad_ctrl_register :: i2c_sda_output [08:08] */ 3909 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_OUTPUT_MASK 0x0100 3910 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_OUTPUT_ALIGN 0 3911 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_OUTPUT_BITS 1 3912 #define PHY84328_DEV1_PAD_CTRL_REGISTER_I2C_SDA_OUTPUT_SHIFT 8 3913 3914 /* ln_device1 :: pad_ctrl_register :: reserved1 [07:07] */ 3915 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED1_MASK 0x0080 3916 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED1_ALIGN 0 3917 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED1_BITS 1 3918 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED1_SHIFT 7 3919 3920 /* ln_device1 :: pad_ctrl_register :: mod_abs_pad_input [06:06] */ 3921 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_PAD_INPUT_MASK 0x0040 3922 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_PAD_INPUT_ALIGN 0 3923 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_PAD_INPUT_BITS 1 3924 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_PAD_INPUT_SHIFT 6 3925 3926 /* ln_device1 :: pad_ctrl_register :: mod_abs_ctrl [05:05] */ 3927 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_CTRL_MASK 0x0020 3928 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_CTRL_ALIGN 0 3929 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_CTRL_BITS 1 3930 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_CTRL_SHIFT 5 3931 3932 /* ln_device1 :: pad_ctrl_register :: mod_abs_output [04:04] */ 3933 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_OUTPUT_MASK 0x0010 3934 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_OUTPUT_ALIGN 0 3935 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_OUTPUT_BITS 1 3936 #define PHY84328_DEV1_PAD_CTRL_REGISTER_MOD_ABS_OUTPUT_SHIFT 4 3937 3938 /* ln_device1 :: pad_ctrl_register :: reserved2 [03:03] */ 3939 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED2_MASK 0x0008 3940 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED2_ALIGN 0 3941 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED2_BITS 1 3942 #define PHY84328_DEV1_PAD_CTRL_REGISTER_RESERVED2_SHIFT 3 3943 3944 /* ln_device1 :: pad_ctrl_register :: oprxlos_pad_input [02:02] */ 3945 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_PAD_INPUT_MASK 0x0004 3946 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_PAD_INPUT_ALIGN 0 3947 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_PAD_INPUT_BITS 1 3948 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_PAD_INPUT_SHIFT 2 3949 3950 /* ln_device1 :: pad_ctrl_register :: oprxlos_ctrl [01:01] */ 3951 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_CTRL_MASK 0x0002 3952 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_CTRL_ALIGN 0 3953 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_CTRL_BITS 1 3954 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_CTRL_SHIFT 1 3955 3956 /* ln_device1 :: pad_ctrl_register :: oprxlos_output [00:00] */ 3957 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_OUTPUT_MASK 0x0001 3958 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_OUTPUT_ALIGN 0 3959 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_OUTPUT_BITS 1 3960 #define PHY84328_DEV1_PAD_CTRL_REGISTER_OPRXLOS_OUTPUT_SHIFT 0 3961 3962 3963 /**************************************************************************** 3964 * ln_device1 :: interrupt_m8051_register 3965 */ 3966 /* ln_device1 :: interrupt_m8051_register :: QSFI_ch_interrupt_TBD [15:14] */ 3967 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_QSFI_CH_INTERRUPT_TBD_MASK 0xc000 3968 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_QSFI_CH_INTERRUPT_TBD_ALIGN 0 3969 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_QSFI_CH_INTERRUPT_TBD_BITS 2 3970 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_QSFI_CH_INTERRUPT_TBD_SHIFT 14 3971 3972 /* ln_device1 :: interrupt_m8051_register :: External_PCS_Linkup [13:13] */ 3973 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKUP_MASK 0x2000 3974 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKUP_ALIGN 0 3975 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKUP_BITS 1 3976 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKUP_SHIFT 13 3977 3978 /* ln_device1 :: interrupt_m8051_register :: External_PCS_Linkdown [12:12] */ 3979 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKDOWN_MASK 0x1000 3980 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKDOWN_ALIGN 0 3981 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKDOWN_BITS 1 3982 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKDOWN_SHIFT 12 3983 3984 /* ln_device1 :: interrupt_m8051_register :: loss_of_optical_rxsignal_interrupt [11:08] */ 3985 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_MASK 0x0f00 3986 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_ALIGN 0 3987 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_BITS 4 3988 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_SHIFT 8 3989 3990 /* ln_device1 :: interrupt_m8051_register :: gpio_1_interrupt [07:04] */ 3991 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_GPIO_1_INTERRUPT_MASK 0x00f0 3992 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_GPIO_1_INTERRUPT_ALIGN 0 3993 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_GPIO_1_INTERRUPT_BITS 4 3994 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_GPIO_1_INTERRUPT_SHIFT 4 3995 3996 /* ln_device1 :: interrupt_m8051_register :: gpio_0_interrupt [03:00] */ 3997 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_GPIO_0_INTERRUPT_MASK 0x000f 3998 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_GPIO_0_INTERRUPT_ALIGN 0 3999 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_GPIO_0_INTERRUPT_BITS 4 4000 #define PHY84328_DEV1_INTERRUPT_M8051_REGISTER_GPIO_0_INTERRUPT_SHIFT 0 4001 4002 4003 /**************************************************************************** 4004 * ln_device1 :: interrupt_m8051_enable_register 4005 */ 4006 /* ln_device1 :: interrupt_m8051_enable_register :: QSFI_ch_interrupt_enable [15:14] */ 4007 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_QSFI_CH_INTERRUPT_ENABLE_MASK 0xc000 4008 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_QSFI_CH_INTERRUPT_ENABLE_ALIGN 0 4009 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_QSFI_CH_INTERRUPT_ENABLE_BITS 2 4010 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_QSFI_CH_INTERRUPT_ENABLE_SHIFT 14 4011 4012 /* ln_device1 :: interrupt_m8051_enable_register :: External_PCS_Linkup_enable [13:13] */ 4013 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKUP_ENABLE_MASK 0x2000 4014 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKUP_ENABLE_ALIGN 0 4015 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKUP_ENABLE_BITS 1 4016 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKUP_ENABLE_SHIFT 13 4017 4018 /* ln_device1 :: interrupt_m8051_enable_register :: External_PCS_Linkdown_enable [12:12] */ 4019 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKDOWN_ENABLE_MASK 0x1000 4020 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKDOWN_ENABLE_ALIGN 0 4021 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKDOWN_ENABLE_BITS 1 4022 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKDOWN_ENABLE_SHIFT 12 4023 4024 /* ln_device1 :: interrupt_m8051_enable_register :: loss_of_opt_rx_interrupt_enable [11:08] */ 4025 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_LOSS_OF_OPT_RX_INTERRUPT_ENABLE_MASK 0x0f00 4026 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_LOSS_OF_OPT_RX_INTERRUPT_ENABLE_ALIGN 0 4027 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_LOSS_OF_OPT_RX_INTERRUPT_ENABLE_BITS 4 4028 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_LOSS_OF_OPT_RX_INTERRUPT_ENABLE_SHIFT 8 4029 4030 /* ln_device1 :: interrupt_m8051_enable_register :: gpio_1_interrupt [07:04] */ 4031 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_1_INTERRUPT_MASK 0x00f0 4032 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_1_INTERRUPT_ALIGN 0 4033 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_1_INTERRUPT_BITS 4 4034 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_1_INTERRUPT_SHIFT 4 4035 4036 /* ln_device1 :: interrupt_m8051_enable_register :: gpio_0_interrupt [03:00] */ 4037 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_0_INTERRUPT_MASK 0x000f 4038 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_0_INTERRUPT_ALIGN 0 4039 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_0_INTERRUPT_BITS 4 4040 #define PHY84328_DEV1_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_0_INTERRUPT_SHIFT 0 4041 4042 4043 /**************************************************************************** 4044 * ln_device1 :: interrupt_m8051_status_register 4045 */ 4046 /* ln_device1 :: interrupt_m8051_status_register :: QSFI_ch_interrupt_status [15:14] */ 4047 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_QSFI_CH_INTERRUPT_STATUS_MASK 0xc000 4048 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_QSFI_CH_INTERRUPT_STATUS_ALIGN 0 4049 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_QSFI_CH_INTERRUPT_STATUS_BITS 2 4050 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_QSFI_CH_INTERRUPT_STATUS_SHIFT 14 4051 4052 /* ln_device1 :: interrupt_m8051_status_register :: External_PCS_Linkup_status [13:13] */ 4053 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKUP_STATUS_MASK 0x2000 4054 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKUP_STATUS_ALIGN 0 4055 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKUP_STATUS_BITS 1 4056 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKUP_STATUS_SHIFT 13 4057 4058 /* ln_device1 :: interrupt_m8051_status_register :: External_PCS_Linkdown_status [12:12] */ 4059 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKDOWN_STATUS_MASK 0x1000 4060 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKDOWN_STATUS_ALIGN 0 4061 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKDOWN_STATUS_BITS 1 4062 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKDOWN_STATUS_SHIFT 12 4063 4064 /* ln_device1 :: interrupt_m8051_status_register :: loss_of_optical_rxsignal_interrupt [11:08] */ 4065 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_MASK 0x0f00 4066 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_ALIGN 0 4067 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_BITS 4 4068 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_SHIFT 8 4069 4070 /* ln_device1 :: interrupt_m8051_status_register :: gpio_1_interrupt [07:04] */ 4071 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_GPIO_1_INTERRUPT_MASK 0x00f0 4072 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_GPIO_1_INTERRUPT_ALIGN 0 4073 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_GPIO_1_INTERRUPT_BITS 4 4074 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_GPIO_1_INTERRUPT_SHIFT 4 4075 4076 /* ln_device1 :: interrupt_m8051_status_register :: gpio_0_interrupt [03:00] */ 4077 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_GPIO_0_INTERRUPT_MASK 0x000f 4078 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_GPIO_0_INTERRUPT_ALIGN 0 4079 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_GPIO_0_INTERRUPT_BITS 4 4080 #define PHY84328_DEV1_INTERRUPT_M8051_STATUS_REGISTER_GPIO_0_INTERRUPT_SHIFT 0 4081 4082 4083 /**************************************************************************** 4084 * ln_device1 :: interrupt_m8051_polarity_register 4085 */ 4086 /* ln_device1 :: interrupt_m8051_polarity_register :: assertion_level_for_QSFI_ch_interrupt [15:12] */ 4087 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_QSFI_CH_INTERRUPT_MASK 0xf000 4088 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_QSFI_CH_INTERRUPT_ALIGN 0 4089 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_QSFI_CH_INTERRUPT_BITS 4 4090 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_QSFI_CH_INTERRUPT_SHIFT 12 4091 4092 /* ln_device1 :: interrupt_m8051_polarity_register :: assertion_level_for_opt_Rx_los_interrupt [11:08] */ 4093 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_OPT_RX_LOS_INTERRUPT_MASK 0x0f00 4094 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_OPT_RX_LOS_INTERRUPT_ALIGN 0 4095 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_OPT_RX_LOS_INTERRUPT_BITS 4 4096 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_OPT_RX_LOS_INTERRUPT_SHIFT 8 4097 4098 /* ln_device1 :: interrupt_m8051_polarity_register :: assertion_level_for_GPIO1_interrupt [07:04] */ 4099 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO1_INTERRUPT_MASK 0x00f0 4100 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO1_INTERRUPT_ALIGN 0 4101 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO1_INTERRUPT_BITS 4 4102 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO1_INTERRUPT_SHIFT 4 4103 4104 /* ln_device1 :: interrupt_m8051_polarity_register :: assertion_level_for_GPIO0_interrupt [03:00] */ 4105 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO0_INTERRUPT_MASK 0x000f 4106 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO0_INTERRUPT_ALIGN 0 4107 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO0_INTERRUPT_BITS 4 4108 #define PHY84328_DEV1_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO0_INTERRUPT_SHIFT 0 4109 4110 4111 /**************************************************************************** 4112 * ln_device1 :: gp_register_0 4113 */ 4114 /* ln_device1 :: gp_register_0 :: gp_register_0 [15:08] */ 4115 #define PHY84328_DEV1_GP_REGISTER_0_GP_REGISTER_0_MASK 0xff00 4116 #define PHY84328_DEV1_GP_REGISTER_0_GP_REGISTER_0_ALIGN 0 4117 #define PHY84328_DEV1_GP_REGISTER_0_GP_REGISTER_0_BITS 8 4118 #define PHY84328_DEV1_GP_REGISTER_0_GP_REGISTER_0_SHIFT 8 4119 4120 /* ln_device1 :: gp_register_0 :: module_resolution_failure [07:07] */ 4121 #define PHY84328_DEV1_GP_REGISTER_0_MODULE_RESOLUTION_FAILURE_MASK 0x0080 4122 #define PHY84328_DEV1_GP_REGISTER_0_MODULE_RESOLUTION_FAILURE_ALIGN 0 4123 #define PHY84328_DEV1_GP_REGISTER_0_MODULE_RESOLUTION_FAILURE_BITS 1 4124 #define PHY84328_DEV1_GP_REGISTER_0_MODULE_RESOLUTION_FAILURE_SHIFT 7 4125 4126 /* ln_device1 :: gp_register_0 :: i2c_data_failure [06:06] */ 4127 #define PHY84328_DEV1_GP_REGISTER_0_I2C_DATA_FAILURE_MASK 0x0040 4128 #define PHY84328_DEV1_GP_REGISTER_0_I2C_DATA_FAILURE_ALIGN 0 4129 #define PHY84328_DEV1_GP_REGISTER_0_I2C_DATA_FAILURE_BITS 1 4130 #define PHY84328_DEV1_GP_REGISTER_0_I2C_DATA_FAILURE_SHIFT 6 4131 4132 /* ln_device1 :: gp_register_0 :: Restart_i2c_access [05:05] */ 4133 #define PHY84328_DEV1_GP_REGISTER_0_RESTART_I2C_ACCESS_MASK 0x0020 4134 #define PHY84328_DEV1_GP_REGISTER_0_RESTART_I2C_ACCESS_ALIGN 0 4135 #define PHY84328_DEV1_GP_REGISTER_0_RESTART_I2C_ACCESS_BITS 1 4136 #define PHY84328_DEV1_GP_REGISTER_0_RESTART_I2C_ACCESS_SHIFT 5 4137 4138 /* ln_device1 :: gp_register_0 :: i2c_access_failure [04:04] */ 4139 #define PHY84328_DEV1_GP_REGISTER_0_I2C_ACCESS_FAILURE_MASK 0x0010 4140 #define PHY84328_DEV1_GP_REGISTER_0_I2C_ACCESS_FAILURE_ALIGN 0 4141 #define PHY84328_DEV1_GP_REGISTER_0_I2C_ACCESS_FAILURE_BITS 1 4142 #define PHY84328_DEV1_GP_REGISTER_0_I2C_ACCESS_FAILURE_SHIFT 4 4143 4144 /* ln_device1 :: gp_register_0 :: Enable_i2c_dynamic_reset [03:03] */ 4145 #define PHY84328_DEV1_GP_REGISTER_0_ENABLE_I2C_DYNAMIC_RESET_MASK 0x0008 4146 #define PHY84328_DEV1_GP_REGISTER_0_ENABLE_I2C_DYNAMIC_RESET_ALIGN 0 4147 #define PHY84328_DEV1_GP_REGISTER_0_ENABLE_I2C_DYNAMIC_RESET_BITS 1 4148 #define PHY84328_DEV1_GP_REGISTER_0_ENABLE_I2C_DYNAMIC_RESET_SHIFT 3 4149 4150 /* ln_device1 :: gp_register_0 :: gp_register_0_bit_2 [02:02] */ 4151 #define PHY84328_DEV1_GP_REGISTER_0_GP_REGISTER_0_BIT_2_MASK 0x0004 4152 #define PHY84328_DEV1_GP_REGISTER_0_GP_REGISTER_0_BIT_2_ALIGN 0 4153 #define PHY84328_DEV1_GP_REGISTER_0_GP_REGISTER_0_BIT_2_BITS 1 4154 #define PHY84328_DEV1_GP_REGISTER_0_GP_REGISTER_0_BIT_2_SHIFT 2 4155 4156 /* ln_device1 :: gp_register_0 :: Micro_timeout_4_i2c_access [01:01] */ 4157 #define PHY84328_DEV1_GP_REGISTER_0_MICRO_TIMEOUT_4_I2C_ACCESS_MASK 0x0002 4158 #define PHY84328_DEV1_GP_REGISTER_0_MICRO_TIMEOUT_4_I2C_ACCESS_ALIGN 0 4159 #define PHY84328_DEV1_GP_REGISTER_0_MICRO_TIMEOUT_4_I2C_ACCESS_BITS 1 4160 #define PHY84328_DEV1_GP_REGISTER_0_MICRO_TIMEOUT_4_I2C_ACCESS_SHIFT 1 4161 4162 /* ln_device1 :: gp_register_0 :: Mod_ABS_asserted [00:00] */ 4163 #define PHY84328_DEV1_GP_REGISTER_0_MOD_ABS_ASSERTED_MASK 0x0001 4164 #define PHY84328_DEV1_GP_REGISTER_0_MOD_ABS_ASSERTED_ALIGN 0 4165 #define PHY84328_DEV1_GP_REGISTER_0_MOD_ABS_ASSERTED_BITS 1 4166 #define PHY84328_DEV1_GP_REGISTER_0_MOD_ABS_ASSERTED_SHIFT 0 4167 4168 4169 /**************************************************************************** 4170 * ln_device1 :: gp_register_1 4171 */ 4172 /* ln_device1 :: gp_register_1 :: System_LR_mode [15:15] */ 4173 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_LR_MODE_MASK 0x8000 4174 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_LR_MODE_ALIGN 0 4175 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_LR_MODE_BITS 1 4176 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_LR_MODE_SHIFT 15 4177 4178 /* ln_device1 :: gp_register_1 :: Line_LR_mode [14:14] */ 4179 #define PHY84328_DEV1_GP_REGISTER_1_LINE_LR_MODE_MASK 0x4000 4180 #define PHY84328_DEV1_GP_REGISTER_1_LINE_LR_MODE_ALIGN 0 4181 #define PHY84328_DEV1_GP_REGISTER_1_LINE_LR_MODE_BITS 1 4182 #define PHY84328_DEV1_GP_REGISTER_1_LINE_LR_MODE_SHIFT 14 4183 4184 /* ln_device1 :: gp_register_1 :: System_Forced_CL72_mode [13:13] */ 4185 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_FORCED_CL72_MODE_MASK 0x2000 4186 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_FORCED_CL72_MODE_ALIGN 0 4187 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_FORCED_CL72_MODE_BITS 1 4188 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_FORCED_CL72_MODE_SHIFT 13 4189 4190 /* ln_device1 :: gp_register_1 :: Line_Forced_CL72_mode [12:12] */ 4191 #define PHY84328_DEV1_GP_REGISTER_1_LINE_FORCED_CL72_MODE_MASK 0x1000 4192 #define PHY84328_DEV1_GP_REGISTER_1_LINE_FORCED_CL72_MODE_ALIGN 0 4193 #define PHY84328_DEV1_GP_REGISTER_1_LINE_FORCED_CL72_MODE_BITS 1 4194 #define PHY84328_DEV1_GP_REGISTER_1_LINE_FORCED_CL72_MODE_SHIFT 12 4195 4196 /* ln_device1 :: gp_register_1 :: System_Cu_Type [11:11] */ 4197 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_CU_TYPE_MASK 0x0800 4198 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_CU_TYPE_ALIGN 0 4199 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_CU_TYPE_BITS 1 4200 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_CU_TYPE_SHIFT 11 4201 4202 /* ln_device1 :: gp_register_1 :: System_Type [10:10] */ 4203 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_TYPE_MASK 0x0400 4204 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_TYPE_ALIGN 0 4205 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_TYPE_BITS 1 4206 #define PHY84328_DEV1_GP_REGISTER_1_SYSTEM_TYPE_SHIFT 10 4207 4208 /* ln_device1 :: gp_register_1 :: Line_Cu_Type [09:09] */ 4209 #define PHY84328_DEV1_GP_REGISTER_1_LINE_CU_TYPE_MASK 0x0200 4210 #define PHY84328_DEV1_GP_REGISTER_1_LINE_CU_TYPE_ALIGN 0 4211 #define PHY84328_DEV1_GP_REGISTER_1_LINE_CU_TYPE_BITS 1 4212 #define PHY84328_DEV1_GP_REGISTER_1_LINE_CU_TYPE_SHIFT 9 4213 4214 /* ln_device1 :: gp_register_1 :: Line_Type [08:08] */ 4215 #define PHY84328_DEV1_GP_REGISTER_1_LINE_TYPE_MASK 0x0100 4216 #define PHY84328_DEV1_GP_REGISTER_1_LINE_TYPE_ALIGN 0 4217 #define PHY84328_DEV1_GP_REGISTER_1_LINE_TYPE_BITS 1 4218 #define PHY84328_DEV1_GP_REGISTER_1_LINE_TYPE_SHIFT 8 4219 4220 /* ln_device1 :: gp_register_1 :: finish_change [07:07] */ 4221 #define PHY84328_DEV1_GP_REGISTER_1_FINISH_CHANGE_MASK 0x0080 4222 #define PHY84328_DEV1_GP_REGISTER_1_FINISH_CHANGE_ALIGN 0 4223 #define PHY84328_DEV1_GP_REGISTER_1_FINISH_CHANGE_BITS 1 4224 #define PHY84328_DEV1_GP_REGISTER_1_FINISH_CHANGE_SHIFT 7 4225 4226 /* ln_device1 :: gp_register_1 :: Type_change [06:06] */ 4227 #define PHY84328_DEV1_GP_REGISTER_1_TYPE_CHANGE_MASK 0x0040 4228 #define PHY84328_DEV1_GP_REGISTER_1_TYPE_CHANGE_ALIGN 0 4229 #define PHY84328_DEV1_GP_REGISTER_1_TYPE_CHANGE_BITS 1 4230 #define PHY84328_DEV1_GP_REGISTER_1_TYPE_CHANGE_SHIFT 6 4231 4232 /* ln_device1 :: gp_register_1 :: Speed_change [05:05] */ 4233 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_CHANGE_MASK 0x0020 4234 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_CHANGE_ALIGN 0 4235 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_CHANGE_BITS 1 4236 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_CHANGE_SHIFT 5 4237 4238 /* ln_device1 :: gp_register_1 :: Speed_or_Type_change [04:04] */ 4239 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_OR_TYPE_CHANGE_MASK 0x0010 4240 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_OR_TYPE_CHANGE_ALIGN 0 4241 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_OR_TYPE_CHANGE_BITS 1 4242 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_OR_TYPE_CHANGE_SHIFT 4 4243 4244 /* ln_device1 :: gp_register_1 :: Speed_100G [03:03] */ 4245 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_100G_MASK 0x0008 4246 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_100G_ALIGN 0 4247 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_100G_BITS 1 4248 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_100G_SHIFT 3 4249 4250 /* ln_device1 :: gp_register_1 :: Speed_40G [02:02] */ 4251 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_40G_MASK 0x0004 4252 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_40G_ALIGN 0 4253 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_40G_BITS 1 4254 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_40G_SHIFT 2 4255 4256 /* ln_device1 :: gp_register_1 :: Speed_10G [01:01] */ 4257 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_10G_MASK 0x0002 4258 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_10G_ALIGN 0 4259 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_10G_BITS 1 4260 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_10G_SHIFT 1 4261 4262 /* ln_device1 :: gp_register_1 :: Speed_1G [00:00] */ 4263 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_1G_MASK 0x0001 4264 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_1G_ALIGN 0 4265 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_1G_BITS 1 4266 #define PHY84328_DEV1_GP_REGISTER_1_SPEED_1G_SHIFT 0 4267 4268 4269 /**************************************************************************** 4270 * ln_device1 :: gp_register_2 4271 */ 4272 /* ln_device1 :: gp_register_2 :: gp_register_2 [15:00] */ 4273 #define PHY84328_DEV1_GP_REGISTER_2_GP_REGISTER_2_MASK 0xffff 4274 #define PHY84328_DEV1_GP_REGISTER_2_GP_REGISTER_2_ALIGN 0 4275 #define PHY84328_DEV1_GP_REGISTER_2_GP_REGISTER_2_BITS 16 4276 #define PHY84328_DEV1_GP_REGISTER_2_GP_REGISTER_2_SHIFT 0 4277 4278 4279 /**************************************************************************** 4280 * ln_device1 :: gp_register_3 4281 */ 4282 /* ln_device1 :: gp_register_3 :: gp_register_3 [15:00] */ 4283 #define PHY84328_DEV1_GP_REGISTER_3_GP_REGISTER_3_MASK 0xffff 4284 #define PHY84328_DEV1_GP_REGISTER_3_GP_REGISTER_3_ALIGN 0 4285 #define PHY84328_DEV1_GP_REGISTER_3_GP_REGISTER_3_BITS 16 4286 #define PHY84328_DEV1_GP_REGISTER_3_GP_REGISTER_3_SHIFT 0 4287 4288 4289 /**************************************************************************** 4290 * ln_device1 :: gp_status_register_0 4291 */ 4292 /* ln_device1 :: gp_status_register_0 :: misc_status_15_0 [15:00] */ 4293 #define PHY84328_DEV1_GP_STATUS_REGISTER_0_MISC_STATUS_15_0_MASK 0xffff 4294 #define PHY84328_DEV1_GP_STATUS_REGISTER_0_MISC_STATUS_15_0_ALIGN 0 4295 #define PHY84328_DEV1_GP_STATUS_REGISTER_0_MISC_STATUS_15_0_BITS 16 4296 #define PHY84328_DEV1_GP_STATUS_REGISTER_0_MISC_STATUS_15_0_SHIFT 0 4297 4298 4299 /**************************************************************************** 4300 * ln_device1 :: gp_status_register_1 4301 */ 4302 /* ln_device1 :: gp_status_register_1 :: misc_status_31_16 [15:00] */ 4303 #define PHY84328_DEV1_GP_STATUS_REGISTER_1_MISC_STATUS_31_16_MASK 0xffff 4304 #define PHY84328_DEV1_GP_STATUS_REGISTER_1_MISC_STATUS_31_16_ALIGN 0 4305 #define PHY84328_DEV1_GP_STATUS_REGISTER_1_MISC_STATUS_31_16_BITS 16 4306 #define PHY84328_DEV1_GP_STATUS_REGISTER_1_MISC_STATUS_31_16_SHIFT 0 4307 4308 4309 /**************************************************************************** 4310 * ln_device1 :: spa_control_status_register 4311 */ 4312 /* ln_device1 :: spa_control_status_register :: spi_port_used [15:15] */ 4313 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_PORT_USED_MASK 0x8000 4314 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_PORT_USED_ALIGN 0 4315 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_PORT_USED_BITS 1 4316 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_PORT_USED_SHIFT 15 4317 4318 /* ln_device1 :: spa_control_status_register :: spi_boot [14:14] */ 4319 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_BOOT_MASK 0x4000 4320 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_BOOT_ALIGN 0 4321 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_BOOT_BITS 1 4322 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_BOOT_SHIFT 14 4323 4324 /* ln_device1 :: spa_control_status_register :: spi_dwld_done [13:13] */ 4325 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_DWLD_DONE_MASK 0x2000 4326 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_DWLD_DONE_ALIGN 0 4327 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_DWLD_DONE_BITS 1 4328 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_DWLD_DONE_SHIFT 13 4329 4330 /* ln_device1 :: spa_control_status_register :: spa_en [12:12] */ 4331 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPA_EN_MASK 0x1000 4332 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPA_EN_ALIGN 0 4333 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPA_EN_BITS 1 4334 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPA_EN_SHIFT 12 4335 4336 /* ln_device1 :: spa_control_status_register :: gp_por_ctl [11:04] */ 4337 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_GP_POR_CTL_MASK 0x0ff0 4338 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_GP_POR_CTL_ALIGN 0 4339 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_GP_POR_CTL_BITS 8 4340 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_GP_POR_CTL_SHIFT 4 4341 4342 /* ln_device1 :: spa_control_status_register :: use_irom_isr [03:03] */ 4343 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_USE_IROM_ISR_MASK 0x0008 4344 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_USE_IROM_ISR_ALIGN 0 4345 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_USE_IROM_ISR_BITS 1 4346 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_USE_IROM_ISR_SHIFT 3 4347 4348 /* ln_device1 :: spa_control_status_register :: reserved0 [02:01] */ 4349 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_RESERVED0_MASK 0x0006 4350 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_RESERVED0_ALIGN 0 4351 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_RESERVED0_BITS 2 4352 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_RESERVED0_SHIFT 1 4353 4354 /* ln_device1 :: spa_control_status_register :: spi_ports_enable [00:00] */ 4355 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_PORTS_ENABLE_MASK 0x0001 4356 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_PORTS_ENABLE_ALIGN 0 4357 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_PORTS_ENABLE_BITS 1 4358 #define PHY84328_DEV1_SPA_CONTROL_STATUS_REGISTER_SPI_PORTS_ENABLE_SHIFT 0 4359 4360 4361 /**************************************************************************** 4362 * ln_device1 :: otp_misc_sig1_register 4363 */ 4364 /* ln_device1 :: otp_misc_sig1_register :: otp_misc_sig1 [15:00] */ 4365 #define PHY84328_DEV1_OTP_MISC_SIG1_REGISTER_OTP_MISC_SIG1_MASK 0xffff 4366 #define PHY84328_DEV1_OTP_MISC_SIG1_REGISTER_OTP_MISC_SIG1_ALIGN 0 4367 #define PHY84328_DEV1_OTP_MISC_SIG1_REGISTER_OTP_MISC_SIG1_BITS 16 4368 #define PHY84328_DEV1_OTP_MISC_SIG1_REGISTER_OTP_MISC_SIG1_SHIFT 0 4369 4370 4371 /**************************************************************************** 4372 * ln_device1 :: otp_misc_sig2_register 4373 */ 4374 /* ln_device1 :: otp_misc_sig2_register :: otp_misc_sig2 [15:00] */ 4375 #define PHY84328_DEV1_OTP_MISC_SIG2_REGISTER_OTP_MISC_SIG2_MASK 0xffff 4376 #define PHY84328_DEV1_OTP_MISC_SIG2_REGISTER_OTP_MISC_SIG2_ALIGN 0 4377 #define PHY84328_DEV1_OTP_MISC_SIG2_REGISTER_OTP_MISC_SIG2_BITS 16 4378 #define PHY84328_DEV1_OTP_MISC_SIG2_REGISTER_OTP_MISC_SIG2_SHIFT 0 4379 4380 4381 /**************************************************************************** 4382 * ln_device1 :: otp_misc_sig3_register 4383 */ 4384 /* ln_device1 :: otp_misc_sig3_register :: otp_misc_sig3 [15:00] */ 4385 #define PHY84328_DEV1_OTP_MISC_SIG3_REGISTER_OTP_MISC_SIG3_MASK 0xffff 4386 #define PHY84328_DEV1_OTP_MISC_SIG3_REGISTER_OTP_MISC_SIG3_ALIGN 0 4387 #define PHY84328_DEV1_OTP_MISC_SIG3_REGISTER_OTP_MISC_SIG3_BITS 16 4388 #define PHY84328_DEV1_OTP_MISC_SIG3_REGISTER_OTP_MISC_SIG3_SHIFT 0 4389 4390 4391 /**************************************************************************** 4392 * ln_device1 :: otp_misc_sig4_register 4393 */ 4394 /* ln_device1 :: otp_misc_sig4_register :: otp_misc_sig4 [15:00] */ 4395 #define PHY84328_DEV1_OTP_MISC_SIG4_REGISTER_OTP_MISC_SIG4_MASK 0xffff 4396 #define PHY84328_DEV1_OTP_MISC_SIG4_REGISTER_OTP_MISC_SIG4_ALIGN 0 4397 #define PHY84328_DEV1_OTP_MISC_SIG4_REGISTER_OTP_MISC_SIG4_BITS 16 4398 #define PHY84328_DEV1_OTP_MISC_SIG4_REGISTER_OTP_MISC_SIG4_SHIFT 0 4399 4400 4401 /**************************************************************************** 4402 * ln_device1 :: otp_misc_sig5_register 4403 */ 4404 /* ln_device1 :: otp_misc_sig5_register :: otp_misc_sig5 [15:00] */ 4405 #define PHY84328_DEV1_OTP_MISC_SIG5_REGISTER_OTP_MISC_SIG5_MASK 0xffff 4406 #define PHY84328_DEV1_OTP_MISC_SIG5_REGISTER_OTP_MISC_SIG5_ALIGN 0 4407 #define PHY84328_DEV1_OTP_MISC_SIG5_REGISTER_OTP_MISC_SIG5_BITS 16 4408 #define PHY84328_DEV1_OTP_MISC_SIG5_REGISTER_OTP_MISC_SIG5_SHIFT 0 4409 4410 4411 /**************************************************************************** 4412 * ln_device1 :: otp_misc_sig6_register 4413 */ 4414 /* ln_device1 :: otp_misc_sig6_register :: otp_misc_sig6 [15:00] */ 4415 #define PHY84328_DEV1_OTP_MISC_SIG6_REGISTER_OTP_MISC_SIG6_MASK 0xffff 4416 #define PHY84328_DEV1_OTP_MISC_SIG6_REGISTER_OTP_MISC_SIG6_ALIGN 0 4417 #define PHY84328_DEV1_OTP_MISC_SIG6_REGISTER_OTP_MISC_SIG6_BITS 16 4418 #define PHY84328_DEV1_OTP_MISC_SIG6_REGISTER_OTP_MISC_SIG6_SHIFT 0 4419 4420 4421 /**************************************************************************** 4422 * ln_device1 :: gp_reg_c870_register 4423 */ 4424 /* ln_device1 :: gp_reg_c870_register :: reserved0 [15:11] */ 4425 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RESERVED0_MASK 0xf800 4426 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RESERVED0_ALIGN 0 4427 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RESERVED0_BITS 5 4428 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RESERVED0_SHIFT 11 4429 4430 /* ln_device1 :: gp_reg_c870_register :: cdr_lkdt_manual_value [10:10] */ 4431 #define PHY84328_DEV1_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_VALUE_MASK 0x0400 4432 #define PHY84328_DEV1_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_VALUE_ALIGN 0 4433 #define PHY84328_DEV1_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_VALUE_BITS 1 4434 #define PHY84328_DEV1_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_VALUE_SHIFT 10 4435 4436 /* ln_device1 :: gp_reg_c870_register :: cdr_lkdt_manual_en [09:09] */ 4437 #define PHY84328_DEV1_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_EN_MASK 0x0200 4438 #define PHY84328_DEV1_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_EN_ALIGN 0 4439 #define PHY84328_DEV1_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_EN_BITS 1 4440 #define PHY84328_DEV1_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_EN_SHIFT 9 4441 4442 /* ln_device1 :: gp_reg_c870_register :: rx_los_manual_value [08:08] */ 4443 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RX_LOS_MANUAL_VALUE_MASK 0x0100 4444 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RX_LOS_MANUAL_VALUE_ALIGN 0 4445 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RX_LOS_MANUAL_VALUE_BITS 1 4446 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RX_LOS_MANUAL_VALUE_SHIFT 8 4447 4448 /* ln_device1 :: gp_reg_c870_register :: rx_los_manual_en [07:07] */ 4449 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RX_LOS_MANUAL_EN_MASK 0x0080 4450 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RX_LOS_MANUAL_EN_ALIGN 0 4451 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RX_LOS_MANUAL_EN_BITS 1 4452 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RX_LOS_MANUAL_EN_SHIFT 7 4453 4454 /* ln_device1 :: gp_reg_c870_register :: sys_cdr_lkdt_manual_value [06:06] */ 4455 #define PHY84328_DEV1_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_VALUE_MASK 0x0040 4456 #define PHY84328_DEV1_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_VALUE_ALIGN 0 4457 #define PHY84328_DEV1_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_VALUE_BITS 1 4458 #define PHY84328_DEV1_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_VALUE_SHIFT 6 4459 4460 /* ln_device1 :: gp_reg_c870_register :: sys_cdr_lkdt_manual_en [05:05] */ 4461 #define PHY84328_DEV1_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_EN_MASK 0x0020 4462 #define PHY84328_DEV1_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_EN_ALIGN 0 4463 #define PHY84328_DEV1_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_EN_BITS 1 4464 #define PHY84328_DEV1_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_EN_SHIFT 5 4465 4466 /* ln_device1 :: gp_reg_c870_register :: reserved1 [04:00] */ 4467 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RESERVED1_MASK 0x001f 4468 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RESERVED1_ALIGN 0 4469 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RESERVED1_BITS 5 4470 #define PHY84328_DEV1_GP_REG_C870_REGISTER_RESERVED1_SHIFT 0 4471 4472 4473 /**************************************************************************** 4474 * ln_device1 :: m8051_watchdog_control_register 4475 */ 4476 /* ln_device1 :: m8051_watchdog_control_register :: m8051_wdog_freeze [15:15] */ 4477 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_FREEZE_MASK 0x8000 4478 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_FREEZE_ALIGN 0 4479 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_FREEZE_BITS 1 4480 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_FREEZE_SHIFT 15 4481 4482 /* ln_device1 :: m8051_watchdog_control_register :: reserved0 [14:12] */ 4483 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_RESERVED0_MASK 0x7000 4484 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_RESERVED0_ALIGN 0 4485 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_RESERVED0_BITS 3 4486 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_RESERVED0_SHIFT 12 4487 4488 /* ln_device1 :: m8051_watchdog_control_register :: m8051_wdog_init [11:00] */ 4489 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_INIT_MASK 0x0fff 4490 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_INIT_ALIGN 0 4491 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_INIT_BITS 12 4492 #define PHY84328_DEV1_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_INIT_SHIFT 0 4493 4494 4495 /**************************************************************************** 4496 * ln_device1 :: m8051_watchdog_status_register 4497 */ 4498 /* ln_device1 :: m8051_watchdog_status_register :: reserved0 [15:12] */ 4499 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER_RESERVED0_MASK 0xf000 4500 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER_RESERVED0_ALIGN 0 4501 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER_RESERVED0_BITS 4 4502 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER_RESERVED0_SHIFT 12 4503 4504 /* ln_device1 :: m8051_watchdog_status_register :: m8051_wdog_cnt [11:00] */ 4505 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER_M8051_WDOG_CNT_MASK 0x0fff 4506 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER_M8051_WDOG_CNT_ALIGN 0 4507 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER_M8051_WDOG_CNT_BITS 12 4508 #define PHY84328_DEV1_M8051_WATCHDOG_STATUS_REGISTER_M8051_WDOG_CNT_SHIFT 0 4509 4510 4511 /**************************************************************************** 4512 * ln_device1 :: chip_intr_stat 4513 */ 4514 /* ln_device1 :: chip_intr_stat :: uncorrectable_error_det_sram_stat [15:15] */ 4515 #define PHY84328_DEV1_CHIP_INTR_STAT_UNCORRECTABLE_ERROR_DET_SRAM_STAT_MASK 0x8000 4516 #define PHY84328_DEV1_CHIP_INTR_STAT_UNCORRECTABLE_ERROR_DET_SRAM_STAT_ALIGN 0 4517 #define PHY84328_DEV1_CHIP_INTR_STAT_UNCORRECTABLE_ERROR_DET_SRAM_STAT_BITS 1 4518 #define PHY84328_DEV1_CHIP_INTR_STAT_UNCORRECTABLE_ERROR_DET_SRAM_STAT_SHIFT 15 4519 4520 /* ln_device1 :: chip_intr_stat :: correctable_error_det_sram_stat [14:14] */ 4521 #define PHY84328_DEV1_CHIP_INTR_STAT_CORRECTABLE_ERROR_DET_SRAM_STAT_MASK 0x4000 4522 #define PHY84328_DEV1_CHIP_INTR_STAT_CORRECTABLE_ERROR_DET_SRAM_STAT_ALIGN 0 4523 #define PHY84328_DEV1_CHIP_INTR_STAT_CORRECTABLE_ERROR_DET_SRAM_STAT_BITS 1 4524 #define PHY84328_DEV1_CHIP_INTR_STAT_CORRECTABLE_ERROR_DET_SRAM_STAT_SHIFT 14 4525 4526 /* ln_device1 :: chip_intr_stat :: Micro_generated_attention_stat [13:13] */ 4527 #define PHY84328_DEV1_CHIP_INTR_STAT_MICRO_GENERATED_ATTENTION_STAT_MASK 0x2000 4528 #define PHY84328_DEV1_CHIP_INTR_STAT_MICRO_GENERATED_ATTENTION_STAT_ALIGN 0 4529 #define PHY84328_DEV1_CHIP_INTR_STAT_MICRO_GENERATED_ATTENTION_STAT_BITS 1 4530 #define PHY84328_DEV1_CHIP_INTR_STAT_MICRO_GENERATED_ATTENTION_STAT_SHIFT 13 4531 4532 /* ln_device1 :: chip_intr_stat :: watch_dog_timer_expired_stat [12:12] */ 4533 #define PHY84328_DEV1_CHIP_INTR_STAT_WATCH_DOG_TIMER_EXPIRED_STAT_MASK 0x1000 4534 #define PHY84328_DEV1_CHIP_INTR_STAT_WATCH_DOG_TIMER_EXPIRED_STAT_ALIGN 0 4535 #define PHY84328_DEV1_CHIP_INTR_STAT_WATCH_DOG_TIMER_EXPIRED_STAT_BITS 1 4536 #define PHY84328_DEV1_CHIP_INTR_STAT_WATCH_DOG_TIMER_EXPIRED_STAT_SHIFT 12 4537 4538 /* ln_device1 :: chip_intr_stat :: ln_autoneg_completed_stat [11:11] */ 4539 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_AUTONEG_COMPLETED_STAT_MASK 0x0800 4540 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_AUTONEG_COMPLETED_STAT_ALIGN 0 4541 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_AUTONEG_COMPLETED_STAT_BITS 1 4542 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_AUTONEG_COMPLETED_STAT_SHIFT 11 4543 4544 /* ln_device1 :: chip_intr_stat :: sys_autoneg_completed_stat [10:10] */ 4545 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_AUTONEG_COMPLETED_STAT_MASK 0x0400 4546 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_AUTONEG_COMPLETED_STAT_ALIGN 0 4547 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_AUTONEG_COMPLETED_STAT_BITS 1 4548 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_AUTONEG_COMPLETED_STAT_SHIFT 10 4549 4550 /* ln_device1 :: chip_intr_stat :: Micro_message_stat [09:09] */ 4551 #define PHY84328_DEV1_CHIP_INTR_STAT_MICRO_MESSAGE_STAT_MASK 0x0200 4552 #define PHY84328_DEV1_CHIP_INTR_STAT_MICRO_MESSAGE_STAT_ALIGN 0 4553 #define PHY84328_DEV1_CHIP_INTR_STAT_MICRO_MESSAGE_STAT_BITS 1 4554 #define PHY84328_DEV1_CHIP_INTR_STAT_MICRO_MESSAGE_STAT_SHIFT 9 4555 4556 /* ln_device1 :: chip_intr_stat :: pad_gp_in_1 [08:08] */ 4557 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_GP_IN_1_MASK 0x0100 4558 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_GP_IN_1_ALIGN 0 4559 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_GP_IN_1_BITS 1 4560 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_GP_IN_1_SHIFT 8 4561 4562 /* ln_device1 :: chip_intr_stat :: pad_gp_in_0 [07:07] */ 4563 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_GP_IN_0_MASK 0x0080 4564 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_GP_IN_0_ALIGN 0 4565 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_GP_IN_0_BITS 1 4566 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_GP_IN_0_SHIFT 7 4567 4568 /* ln_device1 :: chip_intr_stat :: pad_extPCS_Link [06:06] */ 4569 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_EXTPCS_LINK_MASK 0x0040 4570 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_EXTPCS_LINK_ALIGN 0 4571 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_EXTPCS_LINK_BITS 1 4572 #define PHY84328_DEV1_CHIP_INTR_STAT_PAD_EXTPCS_LINK_SHIFT 6 4573 4574 /* ln_device1 :: chip_intr_stat :: sys_cmu_lkdt_stat [05:05] */ 4575 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_CMU_LKDT_STAT_MASK 0x0020 4576 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_CMU_LKDT_STAT_ALIGN 0 4577 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_CMU_LKDT_STAT_BITS 1 4578 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_CMU_LKDT_STAT_SHIFT 5 4579 4580 /* ln_device1 :: chip_intr_stat :: ln_cmu_lkdt_stat [04:04] */ 4581 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_CMU_LKDT_STAT_MASK 0x0010 4582 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_CMU_LKDT_STAT_ALIGN 0 4583 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_CMU_LKDT_STAT_BITS 1 4584 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_CMU_LKDT_STAT_SHIFT 4 4585 4586 /* ln_device1 :: chip_intr_stat :: ln_cdr_lkdt_stat [03:03] */ 4587 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_CDR_LKDT_STAT_MASK 0x0008 4588 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_CDR_LKDT_STAT_ALIGN 0 4589 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_CDR_LKDT_STAT_BITS 1 4590 #define PHY84328_DEV1_CHIP_INTR_STAT_LN_CDR_LKDT_STAT_SHIFT 3 4591 4592 /* ln_device1 :: chip_intr_stat :: opt_los_stat [02:02] */ 4593 #define PHY84328_DEV1_CHIP_INTR_STAT_OPT_LOS_STAT_MASK 0x0004 4594 #define PHY84328_DEV1_CHIP_INTR_STAT_OPT_LOS_STAT_ALIGN 0 4595 #define PHY84328_DEV1_CHIP_INTR_STAT_OPT_LOS_STAT_BITS 1 4596 #define PHY84328_DEV1_CHIP_INTR_STAT_OPT_LOS_STAT_SHIFT 2 4597 4598 /* ln_device1 :: chip_intr_stat :: sys_cdr_lkdt_stat [01:01] */ 4599 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_CDR_LKDT_STAT_MASK 0x0002 4600 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_CDR_LKDT_STAT_ALIGN 0 4601 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_CDR_LKDT_STAT_BITS 1 4602 #define PHY84328_DEV1_CHIP_INTR_STAT_SYS_CDR_LKDT_STAT_SHIFT 1 4603 4604 /* ln_device1 :: chip_intr_stat :: mod_abs_stat [00:00] */ 4605 #define PHY84328_DEV1_CHIP_INTR_STAT_MOD_ABS_STAT_MASK 0x0001 4606 #define PHY84328_DEV1_CHIP_INTR_STAT_MOD_ABS_STAT_ALIGN 0 4607 #define PHY84328_DEV1_CHIP_INTR_STAT_MOD_ABS_STAT_BITS 1 4608 #define PHY84328_DEV1_CHIP_INTR_STAT_MOD_ABS_STAT_SHIFT 0 4609 4610 4611 /**************************************************************************** 4612 * ln_device1 :: chip_intr_en 4613 */ 4614 /* ln_device1 :: chip_intr_en :: Micro_intr_en [15:14] */ 4615 #define PHY84328_DEV1_CHIP_INTR_EN_MICRO_INTR_EN_MASK 0xc000 4616 #define PHY84328_DEV1_CHIP_INTR_EN_MICRO_INTR_EN_ALIGN 0 4617 #define PHY84328_DEV1_CHIP_INTR_EN_MICRO_INTR_EN_BITS 2 4618 #define PHY84328_DEV1_CHIP_INTR_EN_MICRO_INTR_EN_SHIFT 14 4619 4620 /* ln_device1 :: chip_intr_en :: sw_intr_en [13:13] */ 4621 #define PHY84328_DEV1_CHIP_INTR_EN_SW_INTR_EN_MASK 0x2000 4622 #define PHY84328_DEV1_CHIP_INTR_EN_SW_INTR_EN_ALIGN 0 4623 #define PHY84328_DEV1_CHIP_INTR_EN_SW_INTR_EN_BITS 1 4624 #define PHY84328_DEV1_CHIP_INTR_EN_SW_INTR_EN_SHIFT 13 4625 4626 /* ln_device1 :: chip_intr_en :: watchdog_timer_expiry_intr_en [12:12] */ 4627 #define PHY84328_DEV1_CHIP_INTR_EN_WATCHDOG_TIMER_EXPIRY_INTR_EN_MASK 0x1000 4628 #define PHY84328_DEV1_CHIP_INTR_EN_WATCHDOG_TIMER_EXPIRY_INTR_EN_ALIGN 0 4629 #define PHY84328_DEV1_CHIP_INTR_EN_WATCHDOG_TIMER_EXPIRY_INTR_EN_BITS 1 4630 #define PHY84328_DEV1_CHIP_INTR_EN_WATCHDOG_TIMER_EXPIRY_INTR_EN_SHIFT 12 4631 4632 /* ln_device1 :: chip_intr_en :: ln_autoneg_completed_intr_en [11:11] */ 4633 #define PHY84328_DEV1_CHIP_INTR_EN_LN_AUTONEG_COMPLETED_INTR_EN_MASK 0x0800 4634 #define PHY84328_DEV1_CHIP_INTR_EN_LN_AUTONEG_COMPLETED_INTR_EN_ALIGN 0 4635 #define PHY84328_DEV1_CHIP_INTR_EN_LN_AUTONEG_COMPLETED_INTR_EN_BITS 1 4636 #define PHY84328_DEV1_CHIP_INTR_EN_LN_AUTONEG_COMPLETED_INTR_EN_SHIFT 11 4637 4638 /* ln_device1 :: chip_intr_en :: sys_autoneg_completed_intr_en [10:10] */ 4639 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_AUTONEG_COMPLETED_INTR_EN_MASK 0x0400 4640 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_AUTONEG_COMPLETED_INTR_EN_ALIGN 0 4641 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_AUTONEG_COMPLETED_INTR_EN_BITS 1 4642 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_AUTONEG_COMPLETED_INTR_EN_SHIFT 10 4643 4644 /* ln_device1 :: chip_intr_en :: Micro_message_out_intr_en [09:09] */ 4645 #define PHY84328_DEV1_CHIP_INTR_EN_MICRO_MESSAGE_OUT_INTR_EN_MASK 0x0200 4646 #define PHY84328_DEV1_CHIP_INTR_EN_MICRO_MESSAGE_OUT_INTR_EN_ALIGN 0 4647 #define PHY84328_DEV1_CHIP_INTR_EN_MICRO_MESSAGE_OUT_INTR_EN_BITS 1 4648 #define PHY84328_DEV1_CHIP_INTR_EN_MICRO_MESSAGE_OUT_INTR_EN_SHIFT 9 4649 4650 /* ln_device1 :: chip_intr_en :: GPIO_IN_1_intr_en [08:08] */ 4651 #define PHY84328_DEV1_CHIP_INTR_EN_GPIO_IN_1_INTR_EN_MASK 0x0100 4652 #define PHY84328_DEV1_CHIP_INTR_EN_GPIO_IN_1_INTR_EN_ALIGN 0 4653 #define PHY84328_DEV1_CHIP_INTR_EN_GPIO_IN_1_INTR_EN_BITS 1 4654 #define PHY84328_DEV1_CHIP_INTR_EN_GPIO_IN_1_INTR_EN_SHIFT 8 4655 4656 /* ln_device1 :: chip_intr_en :: GPIO_IN_0_intr_en [07:07] */ 4657 #define PHY84328_DEV1_CHIP_INTR_EN_GPIO_IN_0_INTR_EN_MASK 0x0080 4658 #define PHY84328_DEV1_CHIP_INTR_EN_GPIO_IN_0_INTR_EN_ALIGN 0 4659 #define PHY84328_DEV1_CHIP_INTR_EN_GPIO_IN_0_INTR_EN_BITS 1 4660 #define PHY84328_DEV1_CHIP_INTR_EN_GPIO_IN_0_INTR_EN_SHIFT 7 4661 4662 /* ln_device1 :: chip_intr_en :: pad_extPCS_Link [06:06] */ 4663 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_EXTPCS_LINK_MASK 0x0040 4664 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_EXTPCS_LINK_ALIGN 0 4665 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_EXTPCS_LINK_BITS 1 4666 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_EXTPCS_LINK_SHIFT 6 4667 4668 /* ln_device1 :: chip_intr_en :: sys_cmu_lkdt_en [05:05] */ 4669 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_CMU_LKDT_EN_MASK 0x0020 4670 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_CMU_LKDT_EN_ALIGN 0 4671 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_CMU_LKDT_EN_BITS 1 4672 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_CMU_LKDT_EN_SHIFT 5 4673 4674 /* ln_device1 :: chip_intr_en :: ln_cmu_lkdt_en [04:04] */ 4675 #define PHY84328_DEV1_CHIP_INTR_EN_LN_CMU_LKDT_EN_MASK 0x0010 4676 #define PHY84328_DEV1_CHIP_INTR_EN_LN_CMU_LKDT_EN_ALIGN 0 4677 #define PHY84328_DEV1_CHIP_INTR_EN_LN_CMU_LKDT_EN_BITS 1 4678 #define PHY84328_DEV1_CHIP_INTR_EN_LN_CMU_LKDT_EN_SHIFT 4 4679 4680 /* ln_device1 :: chip_intr_en :: ln_cdr_lkdt_en [03:03] */ 4681 #define PHY84328_DEV1_CHIP_INTR_EN_LN_CDR_LKDT_EN_MASK 0x0008 4682 #define PHY84328_DEV1_CHIP_INTR_EN_LN_CDR_LKDT_EN_ALIGN 0 4683 #define PHY84328_DEV1_CHIP_INTR_EN_LN_CDR_LKDT_EN_BITS 1 4684 #define PHY84328_DEV1_CHIP_INTR_EN_LN_CDR_LKDT_EN_SHIFT 3 4685 4686 /* ln_device1 :: chip_intr_en :: pad_opt_los_en [02:02] */ 4687 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_OPT_LOS_EN_MASK 0x0004 4688 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_OPT_LOS_EN_ALIGN 0 4689 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_OPT_LOS_EN_BITS 1 4690 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_OPT_LOS_EN_SHIFT 2 4691 4692 /* ln_device1 :: chip_intr_en :: sys_cdr_lkdt_en [01:01] */ 4693 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_CDR_LKDT_EN_MASK 0x0002 4694 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_CDR_LKDT_EN_ALIGN 0 4695 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_CDR_LKDT_EN_BITS 1 4696 #define PHY84328_DEV1_CHIP_INTR_EN_SYS_CDR_LKDT_EN_SHIFT 1 4697 4698 /* ln_device1 :: chip_intr_en :: pad_mod_abs_en [00:00] */ 4699 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_MOD_ABS_EN_MASK 0x0001 4700 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_MOD_ABS_EN_ALIGN 0 4701 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_MOD_ABS_EN_BITS 1 4702 #define PHY84328_DEV1_CHIP_INTR_EN_PAD_MOD_ABS_EN_SHIFT 0 4703 4704 4705 /**************************************************************************** 4706 * ln_device1 :: chip_intr_value 4707 */ 4708 /* ln_device1 :: chip_intr_value :: micro_intr_value [15:14] */ 4709 #define PHY84328_DEV1_CHIP_INTR_VALUE_MICRO_INTR_VALUE_MASK 0xc000 4710 #define PHY84328_DEV1_CHIP_INTR_VALUE_MICRO_INTR_VALUE_ALIGN 0 4711 #define PHY84328_DEV1_CHIP_INTR_VALUE_MICRO_INTR_VALUE_BITS 2 4712 #define PHY84328_DEV1_CHIP_INTR_VALUE_MICRO_INTR_VALUE_SHIFT 14 4713 4714 /* ln_device1 :: chip_intr_value :: sw_intr_value [13:13] */ 4715 #define PHY84328_DEV1_CHIP_INTR_VALUE_SW_INTR_VALUE_MASK 0x2000 4716 #define PHY84328_DEV1_CHIP_INTR_VALUE_SW_INTR_VALUE_ALIGN 0 4717 #define PHY84328_DEV1_CHIP_INTR_VALUE_SW_INTR_VALUE_BITS 1 4718 #define PHY84328_DEV1_CHIP_INTR_VALUE_SW_INTR_VALUE_SHIFT 13 4719 4720 /* ln_device1 :: chip_intr_value :: watchdog_timer_expiry [12:12] */ 4721 #define PHY84328_DEV1_CHIP_INTR_VALUE_WATCHDOG_TIMER_EXPIRY_MASK 0x1000 4722 #define PHY84328_DEV1_CHIP_INTR_VALUE_WATCHDOG_TIMER_EXPIRY_ALIGN 0 4723 #define PHY84328_DEV1_CHIP_INTR_VALUE_WATCHDOG_TIMER_EXPIRY_BITS 1 4724 #define PHY84328_DEV1_CHIP_INTR_VALUE_WATCHDOG_TIMER_EXPIRY_SHIFT 12 4725 4726 /* ln_device1 :: chip_intr_value :: ln_autoneg_completed_value [11:11] */ 4727 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_AUTONEG_COMPLETED_VALUE_MASK 0x0800 4728 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_AUTONEG_COMPLETED_VALUE_ALIGN 0 4729 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_AUTONEG_COMPLETED_VALUE_BITS 1 4730 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_AUTONEG_COMPLETED_VALUE_SHIFT 11 4731 4732 /* ln_device1 :: chip_intr_value :: sys_autoneg_completed_value [10:10] */ 4733 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_AUTONEG_COMPLETED_VALUE_MASK 0x0400 4734 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_AUTONEG_COMPLETED_VALUE_ALIGN 0 4735 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_AUTONEG_COMPLETED_VALUE_BITS 1 4736 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_AUTONEG_COMPLETED_VALUE_SHIFT 10 4737 4738 /* ln_device1 :: chip_intr_value :: message_out_intr_value [09:09] */ 4739 #define PHY84328_DEV1_CHIP_INTR_VALUE_MESSAGE_OUT_INTR_VALUE_MASK 0x0200 4740 #define PHY84328_DEV1_CHIP_INTR_VALUE_MESSAGE_OUT_INTR_VALUE_ALIGN 0 4741 #define PHY84328_DEV1_CHIP_INTR_VALUE_MESSAGE_OUT_INTR_VALUE_BITS 1 4742 #define PHY84328_DEV1_CHIP_INTR_VALUE_MESSAGE_OUT_INTR_VALUE_SHIFT 9 4743 4744 /* ln_device1 :: chip_intr_value :: gpio_in_1_value [08:08] */ 4745 #define PHY84328_DEV1_CHIP_INTR_VALUE_GPIO_IN_1_VALUE_MASK 0x0100 4746 #define PHY84328_DEV1_CHIP_INTR_VALUE_GPIO_IN_1_VALUE_ALIGN 0 4747 #define PHY84328_DEV1_CHIP_INTR_VALUE_GPIO_IN_1_VALUE_BITS 1 4748 #define PHY84328_DEV1_CHIP_INTR_VALUE_GPIO_IN_1_VALUE_SHIFT 8 4749 4750 /* ln_device1 :: chip_intr_value :: gpio_in_0_value [07:07] */ 4751 #define PHY84328_DEV1_CHIP_INTR_VALUE_GPIO_IN_0_VALUE_MASK 0x0080 4752 #define PHY84328_DEV1_CHIP_INTR_VALUE_GPIO_IN_0_VALUE_ALIGN 0 4753 #define PHY84328_DEV1_CHIP_INTR_VALUE_GPIO_IN_0_VALUE_BITS 1 4754 #define PHY84328_DEV1_CHIP_INTR_VALUE_GPIO_IN_0_VALUE_SHIFT 7 4755 4756 /* ln_device1 :: chip_intr_value :: extPCS_Link_value [06:06] */ 4757 #define PHY84328_DEV1_CHIP_INTR_VALUE_EXTPCS_LINK_VALUE_MASK 0x0040 4758 #define PHY84328_DEV1_CHIP_INTR_VALUE_EXTPCS_LINK_VALUE_ALIGN 0 4759 #define PHY84328_DEV1_CHIP_INTR_VALUE_EXTPCS_LINK_VALUE_BITS 1 4760 #define PHY84328_DEV1_CHIP_INTR_VALUE_EXTPCS_LINK_VALUE_SHIFT 6 4761 4762 /* ln_device1 :: chip_intr_value :: sys_cmu_lkdt_value [05:05] */ 4763 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_CMU_LKDT_VALUE_MASK 0x0020 4764 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_CMU_LKDT_VALUE_ALIGN 0 4765 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_CMU_LKDT_VALUE_BITS 1 4766 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_CMU_LKDT_VALUE_SHIFT 5 4767 4768 /* ln_device1 :: chip_intr_value :: ln_cmu_lkdt_value [04:04] */ 4769 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_CMU_LKDT_VALUE_MASK 0x0010 4770 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_CMU_LKDT_VALUE_ALIGN 0 4771 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_CMU_LKDT_VALUE_BITS 1 4772 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_CMU_LKDT_VALUE_SHIFT 4 4773 4774 /* ln_device1 :: chip_intr_value :: ln_cdr_lkdt_value [03:03] */ 4775 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_CDR_LKDT_VALUE_MASK 0x0008 4776 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_CDR_LKDT_VALUE_ALIGN 0 4777 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_CDR_LKDT_VALUE_BITS 1 4778 #define PHY84328_DEV1_CHIP_INTR_VALUE_LN_CDR_LKDT_VALUE_SHIFT 3 4779 4780 /* ln_device1 :: chip_intr_value :: pad_rx__los_value [02:02] */ 4781 #define PHY84328_DEV1_CHIP_INTR_VALUE_PAD_RX__LOS_VALUE_MASK 0x0004 4782 #define PHY84328_DEV1_CHIP_INTR_VALUE_PAD_RX__LOS_VALUE_ALIGN 0 4783 #define PHY84328_DEV1_CHIP_INTR_VALUE_PAD_RX__LOS_VALUE_BITS 1 4784 #define PHY84328_DEV1_CHIP_INTR_VALUE_PAD_RX__LOS_VALUE_SHIFT 2 4785 4786 /* ln_device1 :: chip_intr_value :: sys_cdr_lkdt_value [01:01] */ 4787 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_CDR_LKDT_VALUE_MASK 0x0002 4788 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_CDR_LKDT_VALUE_ALIGN 0 4789 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_CDR_LKDT_VALUE_BITS 1 4790 #define PHY84328_DEV1_CHIP_INTR_VALUE_SYS_CDR_LKDT_VALUE_SHIFT 1 4791 4792 /* ln_device1 :: chip_intr_value :: pad_mod_abs_value [00:00] */ 4793 #define PHY84328_DEV1_CHIP_INTR_VALUE_PAD_MOD_ABS_VALUE_MASK 0x0001 4794 #define PHY84328_DEV1_CHIP_INTR_VALUE_PAD_MOD_ABS_VALUE_ALIGN 0 4795 #define PHY84328_DEV1_CHIP_INTR_VALUE_PAD_MOD_ABS_VALUE_BITS 1 4796 #define PHY84328_DEV1_CHIP_INTR_VALUE_PAD_MOD_ABS_VALUE_SHIFT 0 4797 4798 4799 /**************************************************************************** 4800 * ln_device1 :: chip_intr_ctrl 4801 */ 4802 /* ln_device1 :: chip_intr_ctrl :: uncorrectable_sram_error_ctrl [15:15] */ 4803 #define PHY84328_DEV1_CHIP_INTR_CTRL_UNCORRECTABLE_SRAM_ERROR_CTRL_MASK 0x8000 4804 #define PHY84328_DEV1_CHIP_INTR_CTRL_UNCORRECTABLE_SRAM_ERROR_CTRL_ALIGN 0 4805 #define PHY84328_DEV1_CHIP_INTR_CTRL_UNCORRECTABLE_SRAM_ERROR_CTRL_BITS 1 4806 #define PHY84328_DEV1_CHIP_INTR_CTRL_UNCORRECTABLE_SRAM_ERROR_CTRL_SHIFT 15 4807 4808 /* ln_device1 :: chip_intr_ctrl :: correctable_sram_error_ctrl [14:14] */ 4809 #define PHY84328_DEV1_CHIP_INTR_CTRL_CORRECTABLE_SRAM_ERROR_CTRL_MASK 0x4000 4810 #define PHY84328_DEV1_CHIP_INTR_CTRL_CORRECTABLE_SRAM_ERROR_CTRL_ALIGN 0 4811 #define PHY84328_DEV1_CHIP_INTR_CTRL_CORRECTABLE_SRAM_ERROR_CTRL_BITS 1 4812 #define PHY84328_DEV1_CHIP_INTR_CTRL_CORRECTABLE_SRAM_ERROR_CTRL_SHIFT 14 4813 4814 /* ln_device1 :: chip_intr_ctrl :: sw_attention_ctrl [13:13] */ 4815 #define PHY84328_DEV1_CHIP_INTR_CTRL_SW_ATTENTION_CTRL_MASK 0x2000 4816 #define PHY84328_DEV1_CHIP_INTR_CTRL_SW_ATTENTION_CTRL_ALIGN 0 4817 #define PHY84328_DEV1_CHIP_INTR_CTRL_SW_ATTENTION_CTRL_BITS 1 4818 #define PHY84328_DEV1_CHIP_INTR_CTRL_SW_ATTENTION_CTRL_SHIFT 13 4819 4820 /* ln_device1 :: chip_intr_ctrl :: wdog_timer_expire_ctrl [12:12] */ 4821 #define PHY84328_DEV1_CHIP_INTR_CTRL_WDOG_TIMER_EXPIRE_CTRL_MASK 0x1000 4822 #define PHY84328_DEV1_CHIP_INTR_CTRL_WDOG_TIMER_EXPIRE_CTRL_ALIGN 0 4823 #define PHY84328_DEV1_CHIP_INTR_CTRL_WDOG_TIMER_EXPIRE_CTRL_BITS 1 4824 #define PHY84328_DEV1_CHIP_INTR_CTRL_WDOG_TIMER_EXPIRE_CTRL_SHIFT 12 4825 4826 /* ln_device1 :: chip_intr_ctrl :: ln_autoneg_completed_ctrl [11:11] */ 4827 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_AUTONEG_COMPLETED_CTRL_MASK 0x0800 4828 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_AUTONEG_COMPLETED_CTRL_ALIGN 0 4829 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_AUTONEG_COMPLETED_CTRL_BITS 1 4830 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_AUTONEG_COMPLETED_CTRL_SHIFT 11 4831 4832 /* ln_device1 :: chip_intr_ctrl :: sys_autoneg_completed_ctrl [10:10] */ 4833 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_AUTONEG_COMPLETED_CTRL_MASK 0x0400 4834 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_AUTONEG_COMPLETED_CTRL_ALIGN 0 4835 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_AUTONEG_COMPLETED_CTRL_BITS 1 4836 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_AUTONEG_COMPLETED_CTRL_SHIFT 10 4837 4838 /* ln_device1 :: chip_intr_ctrl :: message_out_status_ctrl [09:09] */ 4839 #define PHY84328_DEV1_CHIP_INTR_CTRL_MESSAGE_OUT_STATUS_CTRL_MASK 0x0200 4840 #define PHY84328_DEV1_CHIP_INTR_CTRL_MESSAGE_OUT_STATUS_CTRL_ALIGN 0 4841 #define PHY84328_DEV1_CHIP_INTR_CTRL_MESSAGE_OUT_STATUS_CTRL_BITS 1 4842 #define PHY84328_DEV1_CHIP_INTR_CTRL_MESSAGE_OUT_STATUS_CTRL_SHIFT 9 4843 4844 /* ln_device1 :: chip_intr_ctrl :: pad_gp_in_1_ctrl [08:08] */ 4845 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_GP_IN_1_CTRL_MASK 0x0100 4846 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_GP_IN_1_CTRL_ALIGN 0 4847 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_GP_IN_1_CTRL_BITS 1 4848 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_GP_IN_1_CTRL_SHIFT 8 4849 4850 /* ln_device1 :: chip_intr_ctrl :: pad_gp_in_0_ctrl [07:07] */ 4851 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_GP_IN_0_CTRL_MASK 0x0080 4852 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_GP_IN_0_CTRL_ALIGN 0 4853 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_GP_IN_0_CTRL_BITS 1 4854 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_GP_IN_0_CTRL_SHIFT 7 4855 4856 /* ln_device1 :: chip_intr_ctrl :: pad_extPCS_link_ctrl [06:06] */ 4857 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_EXTPCS_LINK_CTRL_MASK 0x0040 4858 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_EXTPCS_LINK_CTRL_ALIGN 0 4859 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_EXTPCS_LINK_CTRL_BITS 1 4860 #define PHY84328_DEV1_CHIP_INTR_CTRL_PAD_EXTPCS_LINK_CTRL_SHIFT 6 4861 4862 /* ln_device1 :: chip_intr_ctrl :: sys_cmu_lkdt_ctrl [05:05] */ 4863 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_CMU_LKDT_CTRL_MASK 0x0020 4864 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_CMU_LKDT_CTRL_ALIGN 0 4865 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_CMU_LKDT_CTRL_BITS 1 4866 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_CMU_LKDT_CTRL_SHIFT 5 4867 4868 /* ln_device1 :: chip_intr_ctrl :: ln_cmu_lkdt_ctrl [04:04] */ 4869 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_CMU_LKDT_CTRL_MASK 0x0010 4870 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_CMU_LKDT_CTRL_ALIGN 0 4871 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_CMU_LKDT_CTRL_BITS 1 4872 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_CMU_LKDT_CTRL_SHIFT 4 4873 4874 /* ln_device1 :: chip_intr_ctrl :: ln_cdr_lkdt_ctrl [03:03] */ 4875 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_CDR_LKDT_CTRL_MASK 0x0008 4876 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_CDR_LKDT_CTRL_ALIGN 0 4877 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_CDR_LKDT_CTRL_BITS 1 4878 #define PHY84328_DEV1_CHIP_INTR_CTRL_LN_CDR_LKDT_CTRL_SHIFT 3 4879 4880 /* ln_device1 :: chip_intr_ctrl :: opt_los_ctrl [02:02] */ 4881 #define PHY84328_DEV1_CHIP_INTR_CTRL_OPT_LOS_CTRL_MASK 0x0004 4882 #define PHY84328_DEV1_CHIP_INTR_CTRL_OPT_LOS_CTRL_ALIGN 0 4883 #define PHY84328_DEV1_CHIP_INTR_CTRL_OPT_LOS_CTRL_BITS 1 4884 #define PHY84328_DEV1_CHIP_INTR_CTRL_OPT_LOS_CTRL_SHIFT 2 4885 4886 /* ln_device1 :: chip_intr_ctrl :: sys_cdr_lkdt_ctrl [01:01] */ 4887 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_CDR_LKDT_CTRL_MASK 0x0002 4888 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_CDR_LKDT_CTRL_ALIGN 0 4889 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_CDR_LKDT_CTRL_BITS 1 4890 #define PHY84328_DEV1_CHIP_INTR_CTRL_SYS_CDR_LKDT_CTRL_SHIFT 1 4891 4892 /* ln_device1 :: chip_intr_ctrl :: mod_abs_ctrl [00:00] */ 4893 #define PHY84328_DEV1_CHIP_INTR_CTRL_MOD_ABS_CTRL_MASK 0x0001 4894 #define PHY84328_DEV1_CHIP_INTR_CTRL_MOD_ABS_CTRL_ALIGN 0 4895 #define PHY84328_DEV1_CHIP_INTR_CTRL_MOD_ABS_CTRL_BITS 1 4896 #define PHY84328_DEV1_CHIP_INTR_CTRL_MOD_ABS_CTRL_SHIFT 0 4897 4898 4899 /**************************************************************************** 4900 * ln_device1 :: ch_intr_ctrl 4901 */ 4902 /* ln_device1 :: ch_intr_ctrl :: reserved0 [15:14] */ 4903 #define PHY84328_DEV1_CH_INTR_CTRL_RESERVED0_MASK 0xc000 4904 #define PHY84328_DEV1_CH_INTR_CTRL_RESERVED0_ALIGN 0 4905 #define PHY84328_DEV1_CH_INTR_CTRL_RESERVED0_BITS 2 4906 #define PHY84328_DEV1_CH_INTR_CTRL_RESERVED0_SHIFT 14 4907 4908 /* ln_device1 :: ch_intr_ctrl :: edc_interrupt_pad_control [13:06] */ 4909 #define PHY84328_DEV1_CH_INTR_CTRL_EDC_INTERRUPT_PAD_CONTROL_MASK 0x3fc0 4910 #define PHY84328_DEV1_CH_INTR_CTRL_EDC_INTERRUPT_PAD_CONTROL_ALIGN 0 4911 #define PHY84328_DEV1_CH_INTR_CTRL_EDC_INTERRUPT_PAD_CONTROL_BITS 8 4912 #define PHY84328_DEV1_CH_INTR_CTRL_EDC_INTERRUPT_PAD_CONTROL_SHIFT 6 4913 4914 /* ln_device1 :: ch_intr_ctrl :: interrupt_clear_sel [05:05] */ 4915 #define PHY84328_DEV1_CH_INTR_CTRL_INTERRUPT_CLEAR_SEL_MASK 0x0020 4916 #define PHY84328_DEV1_CH_INTR_CTRL_INTERRUPT_CLEAR_SEL_ALIGN 0 4917 #define PHY84328_DEV1_CH_INTR_CTRL_INTERRUPT_CLEAR_SEL_BITS 1 4918 #define PHY84328_DEV1_CH_INTR_CTRL_INTERRUPT_CLEAR_SEL_SHIFT 5 4919 4920 /* ln_device1 :: ch_intr_ctrl :: ch_intr_en [04:04] */ 4921 #define PHY84328_DEV1_CH_INTR_CTRL_CH_INTR_EN_MASK 0x0010 4922 #define PHY84328_DEV1_CH_INTR_CTRL_CH_INTR_EN_ALIGN 0 4923 #define PHY84328_DEV1_CH_INTR_CTRL_CH_INTR_EN_BITS 1 4924 #define PHY84328_DEV1_CH_INTR_CTRL_CH_INTR_EN_SHIFT 4 4925 4926 /* ln_device1 :: ch_intr_ctrl :: chip_intr_ctr [03:00] */ 4927 #define PHY84328_DEV1_CH_INTR_CTRL_CHIP_INTR_CTR_MASK 0x000f 4928 #define PHY84328_DEV1_CH_INTR_CTRL_CHIP_INTR_CTR_ALIGN 0 4929 #define PHY84328_DEV1_CH_INTR_CTRL_CHIP_INTR_CTR_BITS 4 4930 #define PHY84328_DEV1_CH_INTR_CTRL_CHIP_INTR_CTR_SHIFT 0 4931 4932 4933 /**************************************************************************** 4934 * ln_device1 :: otp_ovr_rev_id_register 4935 */ 4936 /* ln_device1 :: otp_ovr_rev_id_register :: otp_revid_override_ctl [15:15] */ 4937 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_OTP_REVID_OVERRIDE_CTL_MASK 0x8000 4938 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_OTP_REVID_OVERRIDE_CTL_ALIGN 0 4939 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_OTP_REVID_OVERRIDE_CTL_BITS 1 4940 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_OTP_REVID_OVERRIDE_CTL_SHIFT 15 4941 4942 /* ln_device1 :: otp_ovr_rev_id_register :: reserved0 [14:08] */ 4943 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_RESERVED0_MASK 0x7f00 4944 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_RESERVED0_ALIGN 0 4945 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_RESERVED0_BITS 7 4946 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_RESERVED0_SHIFT 8 4947 4948 /* ln_device1 :: otp_ovr_rev_id_register :: reg_chip_rev_id [07:00] */ 4949 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_REG_CHIP_REV_ID_MASK 0x00ff 4950 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_REG_CHIP_REV_ID_ALIGN 0 4951 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_REG_CHIP_REV_ID_BITS 8 4952 #define PHY84328_DEV1_OTP_OVR_REV_ID_REGISTER_REG_CHIP_REV_ID_SHIFT 0 4953 4954 4955 /**************************************************************************** 4956 * ln_device1 :: otp_ovr_chp_id0_register 4957 */ 4958 /* ln_device1 :: otp_ovr_chp_id0_register :: otp_ovr_chp_id0 [15:00] */ 4959 #define PHY84328_DEV1_OTP_OVR_CHP_ID0_REGISTER_OTP_OVR_CHP_ID0_MASK 0xffff 4960 #define PHY84328_DEV1_OTP_OVR_CHP_ID0_REGISTER_OTP_OVR_CHP_ID0_ALIGN 0 4961 #define PHY84328_DEV1_OTP_OVR_CHP_ID0_REGISTER_OTP_OVR_CHP_ID0_BITS 16 4962 #define PHY84328_DEV1_OTP_OVR_CHP_ID0_REGISTER_OTP_OVR_CHP_ID0_SHIFT 0 4963 4964 4965 /**************************************************************************** 4966 * ln_device1 :: otp_ovr_chp_id1_register 4967 */ 4968 /* ln_device1 :: otp_ovr_chp_id1_register :: otp_chipid_override_ctl [15:15] */ 4969 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_OTP_CHIPID_OVERRIDE_CTL_MASK 0x8000 4970 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_OTP_CHIPID_OVERRIDE_CTL_ALIGN 0 4971 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_OTP_CHIPID_OVERRIDE_CTL_BITS 1 4972 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_OTP_CHIPID_OVERRIDE_CTL_SHIFT 15 4973 4974 /* ln_device1 :: otp_ovr_chp_id1_register :: reserved0 [14:04] */ 4975 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_RESERVED0_MASK 0x7ff0 4976 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_RESERVED0_ALIGN 0 4977 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_RESERVED0_BITS 11 4978 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_RESERVED0_SHIFT 4 4979 4980 /* ln_device1 :: otp_ovr_chp_id1_register :: otp_ovr_chp_id1 [03:00] */ 4981 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_OTP_OVR_CHP_ID1_MASK 0x000f 4982 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_OTP_OVR_CHP_ID1_ALIGN 0 4983 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_OTP_OVR_CHP_ID1_BITS 4 4984 #define PHY84328_DEV1_OTP_OVR_CHP_ID1_REGISTER_OTP_OVR_CHP_ID1_SHIFT 0 4985 4986 4987 /**************************************************************************** 4988 * ln_device1 :: otp_rdy_cnt_stat_reg 4989 */ 4990 /* ln_device1 :: otp_rdy_cnt_stat_reg :: reserved0 [15:13] */ 4991 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_RESERVED0_MASK 0xe000 4992 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_RESERVED0_ALIGN 0 4993 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_RESERVED0_BITS 3 4994 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_RESERVED0_SHIFT 13 4995 4996 /* ln_device1 :: otp_rdy_cnt_stat_reg :: otp_rdy_cnt_status [12:08] */ 4997 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_RDY_CNT_STATUS_MASK 0x1f00 4998 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_RDY_CNT_STATUS_ALIGN 0 4999 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_RDY_CNT_STATUS_BITS 5 5000 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_RDY_CNT_STATUS_SHIFT 8 5001 5002 /* ln_device1 :: otp_rdy_cnt_stat_reg :: reserved1 [07:02] */ 5003 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_RESERVED1_MASK 0x00fc 5004 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_RESERVED1_ALIGN 0 5005 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_RESERVED1_BITS 6 5006 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_RESERVED1_SHIFT 2 5007 5008 /* ln_device1 :: otp_rdy_cnt_stat_reg :: otp_ready_sample_val [01:01] */ 5009 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_READY_SAMPLE_VAL_MASK 0x0002 5010 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_READY_SAMPLE_VAL_ALIGN 0 5011 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_READY_SAMPLE_VAL_BITS 1 5012 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_READY_SAMPLE_VAL_SHIFT 1 5013 5014 /* ln_device1 :: otp_rdy_cnt_stat_reg :: otp_ready_raw_val [00:00] */ 5015 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_READY_RAW_VAL_MASK 0x0001 5016 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_READY_RAW_VAL_ALIGN 0 5017 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_READY_RAW_VAL_BITS 1 5018 #define PHY84328_DEV1_OTP_RDY_CNT_STAT_REG_OTP_READY_RAW_VAL_SHIFT 0 5019 5020 5021 /**************************************************************************** 5022 * ln_device1 :: otp_ovr_device_id_0 5023 */ 5024 /* ln_device1 :: otp_ovr_device_id_0 :: otp_ovr_device_id_0 [15:00] */ 5025 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_OTP_OVR_DEVICE_ID_0_MASK 0xffff 5026 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_OTP_OVR_DEVICE_ID_0_ALIGN 0 5027 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_OTP_OVR_DEVICE_ID_0_BITS 16 5028 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_OTP_OVR_DEVICE_ID_0_SHIFT 0 5029 5030 5031 /**************************************************************************** 5032 * ln_device1 :: otp_ovr_device_id_1 5033 */ 5034 /* ln_device1 :: otp_ovr_device_id_1 :: otp_ovr_device_id_1 [15:00] */ 5035 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_1_OTP_OVR_DEVICE_ID_1_MASK 0xffff 5036 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_1_OTP_OVR_DEVICE_ID_1_ALIGN 0 5037 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_1_OTP_OVR_DEVICE_ID_1_BITS 16 5038 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_1_OTP_OVR_DEVICE_ID_1_SHIFT 0 5039 5040 5041 /**************************************************************************** 5042 * ln_device1 :: otp_ovr_device_id_0_1_cntl 5043 */ 5044 /* ln_device1 :: otp_ovr_device_id_0_1_cntl :: reserved0 [15:02] */ 5045 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_RESERVED0_MASK 0xfffc 5046 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_RESERVED0_ALIGN 0 5047 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_RESERVED0_BITS 14 5048 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_RESERVED0_SHIFT 2 5049 5050 /* ln_device1 :: otp_ovr_device_id_0_1_cntl :: otp_ovr_device_id_1_cntl [01:01] */ 5051 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_1_CNTL_MASK 0x0002 5052 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_1_CNTL_ALIGN 0 5053 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_1_CNTL_BITS 1 5054 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_1_CNTL_SHIFT 1 5055 5056 /* ln_device1 :: otp_ovr_device_id_0_1_cntl :: otp_ovr_device_id_0_cntl [00:00] */ 5057 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_0_CNTL_MASK 0x0001 5058 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_0_CNTL_ALIGN 0 5059 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_0_CNTL_BITS 1 5060 #define PHY84328_DEV1_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_0_CNTL_SHIFT 0 5061 5062 5063 /**************************************************************************** 5064 * ln_device1 :: die_id 5065 */ 5066 /* ln_device1 :: die_id :: reserved0 [15:08] */ 5067 #define PHY84328_DEV1_DIE_ID_RESERVED0_MASK 0xff00 5068 #define PHY84328_DEV1_DIE_ID_RESERVED0_ALIGN 0 5069 #define PHY84328_DEV1_DIE_ID_RESERVED0_BITS 8 5070 #define PHY84328_DEV1_DIE_ID_RESERVED0_SHIFT 8 5071 5072 /* ln_device1 :: die_id :: die_id [07:00] */ 5073 #define PHY84328_DEV1_DIE_ID_DIE_ID_MASK 0x00ff 5074 #define PHY84328_DEV1_DIE_ID_DIE_ID_ALIGN 0 5075 #define PHY84328_DEV1_DIE_ID_DIE_ID_BITS 8 5076 #define PHY84328_DEV1_DIE_ID_DIE_ID_SHIFT 0 5077 5078 5079 /**************************************************************************** 5080 * ln_device1 :: optical_configuration 5081 */ 5082 /* ln_device1 :: optical_configuration :: optxenb_lvl [15:15] */ 5083 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTXENB_LVL_MASK 0x8000 5084 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTXENB_LVL_ALIGN 0 5085 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTXENB_LVL_BITS 1 5086 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTXENB_LVL_SHIFT 15 5087 5088 /* ln_device1 :: optical_configuration :: man_oplosb_en [14:14] */ 5089 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_OPLOSB_EN_MASK 0x4000 5090 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_OPLOSB_EN_ALIGN 0 5091 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_OPLOSB_EN_BITS 1 5092 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_OPLOSB_EN_SHIFT 14 5093 5094 /* ln_device1 :: optical_configuration :: man_extPCS_Link [13:13] */ 5095 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_EXTPCS_LINK_MASK 0x2000 5096 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_EXTPCS_LINK_ALIGN 0 5097 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_EXTPCS_LINK_BITS 1 5098 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_EXTPCS_LINK_SHIFT 13 5099 5100 /* ln_device1 :: optical_configuration :: man_txon_en [12:12] */ 5101 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_TXON_EN_MASK 0x1000 5102 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_TXON_EN_ALIGN 0 5103 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_TXON_EN_BITS 1 5104 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MAN_TXON_EN_SHIFT 12 5105 5106 /* ln_device1 :: optical_configuration :: optrxlos_lvl [11:11] */ 5107 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTRXLOS_LVL_MASK 0x0800 5108 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTRXLOS_LVL_ALIGN 0 5109 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTRXLOS_LVL_BITS 1 5110 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTRXLOS_LVL_SHIFT 11 5111 5112 /* ln_device1 :: optical_configuration :: optxon_lvl [10:10] */ 5113 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTXON_LVL_MASK 0x0400 5114 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTXON_LVL_ALIGN 0 5115 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTXON_LVL_BITS 1 5116 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_OPTXON_LVL_SHIFT 10 5117 5118 /* ln_device1 :: optical_configuration :: Enable_extPCS_Link_for_Line [09:09] */ 5119 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_LINE_MASK 0x0200 5120 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_LINE_ALIGN 0 5121 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_LINE_BITS 1 5122 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_LINE_SHIFT 9 5123 5124 /* ln_device1 :: optical_configuration :: Enable_extPCS_Link_for_Sys [08:08] */ 5125 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_SYS_MASK 0x0100 5126 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_SYS_ALIGN 0 5127 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_SYS_BITS 1 5128 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_SYS_SHIFT 8 5129 5130 /* ln_device1 :: optical_configuration :: txenb [07:07] */ 5131 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXENB_MASK 0x0080 5132 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXENB_ALIGN 0 5133 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXENB_BITS 1 5134 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXENB_SHIFT 7 5135 5136 /* ln_device1 :: optical_configuration :: md_opt_losb [06:06] */ 5137 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MD_OPT_LOSB_MASK 0x0040 5138 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MD_OPT_LOSB_ALIGN 0 5139 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MD_OPT_LOSB_BITS 1 5140 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_MD_OPT_LOSB_SHIFT 6 5141 5142 /* ln_device1 :: optical_configuration :: extPCS_Link [05:05] */ 5143 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EXTPCS_LINK_MASK 0x0020 5144 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EXTPCS_LINK_ALIGN 0 5145 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EXTPCS_LINK_BITS 1 5146 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EXTPCS_LINK_SHIFT 5 5147 5148 /* ln_device1 :: optical_configuration :: txofft [04:04] */ 5149 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXOFFT_MASK 0x0010 5150 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXOFFT_ALIGN 0 5151 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXOFFT_BITS 1 5152 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXOFFT_SHIFT 4 5153 5154 /* ln_device1 :: optical_configuration :: txenb_oen [03:03] */ 5155 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXENB_OEN_MASK 0x0008 5156 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXENB_OEN_ALIGN 0 5157 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXENB_OEN_BITS 1 5158 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_TXENB_OEN_SHIFT 3 5159 5160 /* ln_device1 :: optical_configuration :: reserved_txon_oen [02:02] */ 5161 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_RESERVED_TXON_OEN_MASK 0x0004 5162 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_RESERVED_TXON_OEN_ALIGN 0 5163 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_RESERVED_TXON_OEN_BITS 1 5164 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_RESERVED_TXON_OEN_SHIFT 2 5165 5166 /* ln_device1 :: optical_configuration :: en_txenb_int [01:01] */ 5167 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EN_TXENB_INT_MASK 0x0002 5168 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EN_TXENB_INT_ALIGN 0 5169 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EN_TXENB_INT_BITS 1 5170 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EN_TXENB_INT_SHIFT 1 5171 5172 /* ln_device1 :: optical_configuration :: en_txonb_int [00:00] */ 5173 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EN_TXONB_INT_MASK 0x0001 5174 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EN_TXONB_INT_ALIGN 0 5175 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EN_TXONB_INT_BITS 1 5176 #define PHY84328_DEV1_OPTICAL_CONFIGURATION_EN_TXONB_INT_SHIFT 0 5177 5178 5179 /**************************************************************************** 5180 * ln_device1 :: broadcast_ctrl 5181 */ 5182 /* ln_device1 :: broadcast_ctrl :: reserved0 [15:07] */ 5183 #define PHY84328_DEV1_BROADCAST_CTRL_RESERVED0_MASK 0xff80 5184 #define PHY84328_DEV1_BROADCAST_CTRL_RESERVED0_ALIGN 0 5185 #define PHY84328_DEV1_BROADCAST_CTRL_RESERVED0_BITS 9 5186 #define PHY84328_DEV1_BROADCAST_CTRL_RESERVED0_SHIFT 7 5187 5188 /* ln_device1 :: broadcast_ctrl :: multiport_address [06:02] */ 5189 #define PHY84328_DEV1_BROADCAST_CTRL_MULTIPORT_ADDRESS_MASK 0x007c 5190 #define PHY84328_DEV1_BROADCAST_CTRL_MULTIPORT_ADDRESS_ALIGN 0 5191 #define PHY84328_DEV1_BROADCAST_CTRL_MULTIPORT_ADDRESS_BITS 5 5192 #define PHY84328_DEV1_BROADCAST_CTRL_MULTIPORT_ADDRESS_SHIFT 2 5193 5194 /* ln_device1 :: broadcast_ctrl :: multiport_addressing_enable [01:01] */ 5195 #define PHY84328_DEV1_BROADCAST_CTRL_MULTIPORT_ADDRESSING_ENABLE_MASK 0x0002 5196 #define PHY84328_DEV1_BROADCAST_CTRL_MULTIPORT_ADDRESSING_ENABLE_ALIGN 0 5197 #define PHY84328_DEV1_BROADCAST_CTRL_MULTIPORT_ADDRESSING_ENABLE_BITS 1 5198 #define PHY84328_DEV1_BROADCAST_CTRL_MULTIPORT_ADDRESSING_ENABLE_SHIFT 1 5199 5200 /* ln_device1 :: broadcast_ctrl :: broadcast_mode_enable [00:00] */ 5201 #define PHY84328_DEV1_BROADCAST_CTRL_BROADCAST_MODE_ENABLE_MASK 0x0001 5202 #define PHY84328_DEV1_BROADCAST_CTRL_BROADCAST_MODE_ENABLE_ALIGN 0 5203 #define PHY84328_DEV1_BROADCAST_CTRL_BROADCAST_MODE_ENABLE_BITS 1 5204 #define PHY84328_DEV1_BROADCAST_CTRL_BROADCAST_MODE_ENABLE_SHIFT 0 5205 5206 5207 /**************************************************************************** 5208 * ln_device1 :: xpmd_regs_sel 5209 */ 5210 /* ln_device1 :: xpmd_regs_sel :: reserved0 [15:01] */ 5211 #define PHY84328_DEV1_XPMD_REGS_SEL_RESERVED0_MASK 0xfffe 5212 #define PHY84328_DEV1_XPMD_REGS_SEL_RESERVED0_ALIGN 0 5213 #define PHY84328_DEV1_XPMD_REGS_SEL_RESERVED0_BITS 15 5214 #define PHY84328_DEV1_XPMD_REGS_SEL_RESERVED0_SHIFT 1 5215 5216 /* ln_device1 :: xpmd_regs_sel :: select_sys_registers [00:00] */ 5217 #define PHY84328_DEV1_XPMD_REGS_SEL_SELECT_SYS_REGISTERS_MASK 0x0001 5218 #define PHY84328_DEV1_XPMD_REGS_SEL_SELECT_SYS_REGISTERS_ALIGN 0 5219 #define PHY84328_DEV1_XPMD_REGS_SEL_SELECT_SYS_REGISTERS_BITS 1 5220 #define PHY84328_DEV1_XPMD_REGS_SEL_SELECT_SYS_REGISTERS_SHIFT 0 5221 5222 5223 /**************************************************************************** 5224 * ln_device1_PMD_standard_Registers 5225 */ 5226 /**************************************************************************** 5227 * ln_device1 :: pmd_control_register 5228 */ 5229 /* ln_device1 :: pmd_control_register :: reset [15:15] */ 5230 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESET_MASK 0x8000 5231 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESET_ALIGN 0 5232 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESET_BITS 1 5233 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESET_SHIFT 15 5234 5235 /* ln_device1 :: pmd_control_register :: reserved0 [14:14] */ 5236 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED0_MASK 0x4000 5237 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED0_ALIGN 0 5238 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED0_BITS 1 5239 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED0_SHIFT 14 5240 5241 /* ln_device1 :: pmd_control_register :: speed_selectionlsb [13:13] */ 5242 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_MASK 0x2000 5243 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_ALIGN 0 5244 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_BITS 1 5245 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_SHIFT 13 5246 5247 /* ln_device1 :: pmd_control_register :: reserved1 [12:12] */ 5248 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED1_MASK 0x1000 5249 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED1_ALIGN 0 5250 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED1_BITS 1 5251 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED1_SHIFT 12 5252 5253 /* ln_device1 :: pmd_control_register :: power_down [11:11] */ 5254 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_POWER_DOWN_MASK 0x0800 5255 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_POWER_DOWN_ALIGN 0 5256 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_POWER_DOWN_BITS 1 5257 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_POWER_DOWN_SHIFT 11 5258 5259 /* ln_device1 :: pmd_control_register :: reserved2 [10:07] */ 5260 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED2_MASK 0x0780 5261 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED2_ALIGN 0 5262 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED2_BITS 4 5263 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED2_SHIFT 7 5264 5265 /* ln_device1 :: pmd_control_register :: speed_selectionmsb [06:06] */ 5266 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_MASK 0x0040 5267 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_ALIGN 0 5268 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_BITS 1 5269 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_SHIFT 6 5270 5271 /* ln_device1 :: pmd_control_register :: speed_selection [05:02] */ 5272 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTION_MASK 0x003c 5273 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTION_ALIGN 0 5274 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTION_BITS 4 5275 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTION_SHIFT 2 5276 5277 /* ln_device1 :: pmd_control_register :: reserved3 [01:01] */ 5278 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED3_MASK 0x0002 5279 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED3_ALIGN 0 5280 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED3_BITS 1 5281 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_RESERVED3_SHIFT 1 5282 5283 /* ln_device1 :: pmd_control_register :: pma_loopback [00:00] */ 5284 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_PMA_LOOPBACK_MASK 0x0001 5285 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_PMA_LOOPBACK_ALIGN 0 5286 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_PMA_LOOPBACK_BITS 1 5287 #define PHY84328_DEV1_PMD_CONTROL_REGISTER_PMA_LOOPBACK_SHIFT 0 5288 5289 5290 /**************************************************************************** 5291 * ln_device1 :: status_register 5292 */ 5293 /* ln_device1 :: status_register :: reserved0 [15:08] */ 5294 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED0_MASK 0xff00 5295 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED0_ALIGN 0 5296 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED0_BITS 8 5297 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED0_SHIFT 8 5298 5299 /* ln_device1 :: status_register :: fault [07:07] */ 5300 #define PHY84328_DEV1_STATUS_REGISTER_FAULT_MASK 0x0080 5301 #define PHY84328_DEV1_STATUS_REGISTER_FAULT_ALIGN 0 5302 #define PHY84328_DEV1_STATUS_REGISTER_FAULT_BITS 1 5303 #define PHY84328_DEV1_STATUS_REGISTER_FAULT_SHIFT 7 5304 5305 /* ln_device1 :: status_register :: reserved1 [06:03] */ 5306 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED1_MASK 0x0078 5307 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED1_ALIGN 0 5308 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED1_BITS 4 5309 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED1_SHIFT 3 5310 5311 /* ln_device1 :: status_register :: receive_link_status [02:02] */ 5312 #define PHY84328_DEV1_STATUS_REGISTER_RECEIVE_LINK_STATUS_MASK 0x0004 5313 #define PHY84328_DEV1_STATUS_REGISTER_RECEIVE_LINK_STATUS_ALIGN 0 5314 #define PHY84328_DEV1_STATUS_REGISTER_RECEIVE_LINK_STATUS_BITS 1 5315 #define PHY84328_DEV1_STATUS_REGISTER_RECEIVE_LINK_STATUS_SHIFT 2 5316 5317 /* ln_device1 :: status_register :: low_power_ability [01:01] */ 5318 #define PHY84328_DEV1_STATUS_REGISTER_LOW_POWER_ABILITY_MASK 0x0002 5319 #define PHY84328_DEV1_STATUS_REGISTER_LOW_POWER_ABILITY_ALIGN 0 5320 #define PHY84328_DEV1_STATUS_REGISTER_LOW_POWER_ABILITY_BITS 1 5321 #define PHY84328_DEV1_STATUS_REGISTER_LOW_POWER_ABILITY_SHIFT 1 5322 5323 /* ln_device1 :: status_register :: reserved2 [00:00] */ 5324 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED2_MASK 0x0001 5325 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED2_ALIGN 0 5326 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED2_BITS 1 5327 #define PHY84328_DEV1_STATUS_REGISTER_RESERVED2_SHIFT 0 5328 5329 5330 /**************************************************************************** 5331 * ln_device1 :: pmd_identifier_register_0 5332 */ 5333 /* ln_device1 :: pmd_identifier_register_0 :: device_id_0 [15:00] */ 5334 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_MASK 0xffff 5335 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_ALIGN 0 5336 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_BITS 16 5337 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_SHIFT 0 5338 5339 5340 /**************************************************************************** 5341 * ln_device1 :: pmd_identifier_register_1 5342 */ 5343 /* ln_device1 :: pmd_identifier_register_1 :: device_id_1 [15:00] */ 5344 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_MASK 0xffff 5345 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_ALIGN 0 5346 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_BITS 16 5347 #define PHY84328_DEV1_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_SHIFT 0 5348 5349 5350 /**************************************************************************** 5351 * ln_device1 :: pmd_speed_ability 5352 */ 5353 /* ln_device1 :: pmd_speed_ability :: reserved0 [15:09] */ 5354 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED0_MASK 0xfe00 5355 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED0_ALIGN 0 5356 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED0_BITS 7 5357 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED0_SHIFT 9 5358 5359 /* ln_device1 :: pmd_speed_ability :: fortyG_capable [08:08] */ 5360 #define PHY84328_DEV1_PMD_SPEED_ABILITY_FORTYG_CAPABLE_MASK 0x0100 5361 #define PHY84328_DEV1_PMD_SPEED_ABILITY_FORTYG_CAPABLE_ALIGN 0 5362 #define PHY84328_DEV1_PMD_SPEED_ABILITY_FORTYG_CAPABLE_BITS 1 5363 #define PHY84328_DEV1_PMD_SPEED_ABILITY_FORTYG_CAPABLE_SHIFT 8 5364 5365 /* ln_device1 :: pmd_speed_ability :: reserved1 [07:05] */ 5366 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED1_MASK 0x00e0 5367 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED1_ALIGN 0 5368 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED1_BITS 3 5369 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED1_SHIFT 5 5370 5371 /* ln_device1 :: pmd_speed_ability :: oneG_capable [04:04] */ 5372 #define PHY84328_DEV1_PMD_SPEED_ABILITY_ONEG_CAPABLE_MASK 0x0010 5373 #define PHY84328_DEV1_PMD_SPEED_ABILITY_ONEG_CAPABLE_ALIGN 0 5374 #define PHY84328_DEV1_PMD_SPEED_ABILITY_ONEG_CAPABLE_BITS 1 5375 #define PHY84328_DEV1_PMD_SPEED_ABILITY_ONEG_CAPABLE_SHIFT 4 5376 5377 /* ln_device1 :: pmd_speed_ability :: reserved2 [03:01] */ 5378 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED2_MASK 0x000e 5379 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED2_ALIGN 0 5380 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED2_BITS 3 5381 #define PHY84328_DEV1_PMD_SPEED_ABILITY_RESERVED2_SHIFT 1 5382 5383 /* ln_device1 :: pmd_speed_ability :: tenG_capable [00:00] */ 5384 #define PHY84328_DEV1_PMD_SPEED_ABILITY_TENG_CAPABLE_MASK 0x0001 5385 #define PHY84328_DEV1_PMD_SPEED_ABILITY_TENG_CAPABLE_ALIGN 0 5386 #define PHY84328_DEV1_PMD_SPEED_ABILITY_TENG_CAPABLE_BITS 1 5387 #define PHY84328_DEV1_PMD_SPEED_ABILITY_TENG_CAPABLE_SHIFT 0 5388 5389 5390 /**************************************************************************** 5391 * ln_device1 :: devices_in_package_1 5392 */ 5393 /* ln_device1 :: devices_in_package_1 :: reserved0 [15:12] */ 5394 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_RESERVED0_MASK 0xf000 5395 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_RESERVED0_ALIGN 0 5396 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_RESERVED0_BITS 4 5397 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_RESERVED0_SHIFT 12 5398 5399 /* ln_device1 :: devices_in_package_1 :: Seperate_PMA_4_Present [11:11] */ 5400 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_4_PRESENT_MASK 0x0800 5401 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_4_PRESENT_ALIGN 0 5402 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_4_PRESENT_BITS 1 5403 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_4_PRESENT_SHIFT 11 5404 5405 /* ln_device1 :: devices_in_package_1 :: Seperate_PMA_3_Present [10:10] */ 5406 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_3_PRESENT_MASK 0x0400 5407 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_3_PRESENT_ALIGN 0 5408 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_3_PRESENT_BITS 1 5409 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_3_PRESENT_SHIFT 10 5410 5411 /* ln_device1 :: devices_in_package_1 :: Seperate_PMA_2_Present [09:09] */ 5412 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_2_PRESENT_MASK 0x0200 5413 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_2_PRESENT_ALIGN 0 5414 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_2_PRESENT_BITS 1 5415 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_2_PRESENT_SHIFT 9 5416 5417 /* ln_device1 :: devices_in_package_1 :: Seperate_PMA_1_Present [08:08] */ 5418 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_1_PRESENT_MASK 0x0100 5419 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_1_PRESENT_ALIGN 0 5420 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_1_PRESENT_BITS 1 5421 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_1_PRESENT_SHIFT 8 5422 5423 /* ln_device1 :: devices_in_package_1 :: ang_present [07:07] */ 5424 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_ANG_PRESENT_MASK 0x0080 5425 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_ANG_PRESENT_ALIGN 0 5426 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_ANG_PRESENT_BITS 1 5427 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_ANG_PRESENT_SHIFT 7 5428 5429 /* ln_device1 :: devices_in_package_1 :: tc_present [06:06] */ 5430 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_TC_PRESENT_MASK 0x0040 5431 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_TC_PRESENT_ALIGN 0 5432 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_TC_PRESENT_BITS 1 5433 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_TC_PRESENT_SHIFT 6 5434 5435 /* ln_device1 :: devices_in_package_1 :: dte_xs_present [05:05] */ 5436 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_DTE_XS_PRESENT_MASK 0x0020 5437 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_DTE_XS_PRESENT_ALIGN 0 5438 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_DTE_XS_PRESENT_BITS 1 5439 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_DTE_XS_PRESENT_SHIFT 5 5440 5441 /* ln_device1 :: devices_in_package_1 :: phy_xs_present [04:04] */ 5442 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PHY_XS_PRESENT_MASK 0x0010 5443 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PHY_XS_PRESENT_ALIGN 0 5444 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PHY_XS_PRESENT_BITS 1 5445 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PHY_XS_PRESENT_SHIFT 4 5446 5447 /* ln_device1 :: devices_in_package_1 :: pcs_present [03:03] */ 5448 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PCS_PRESENT_MASK 0x0008 5449 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PCS_PRESENT_ALIGN 0 5450 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PCS_PRESENT_BITS 1 5451 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PCS_PRESENT_SHIFT 3 5452 5453 /* ln_device1 :: devices_in_package_1 :: wis_present [02:02] */ 5454 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_WIS_PRESENT_MASK 0x0004 5455 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_WIS_PRESENT_ALIGN 0 5456 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_WIS_PRESENT_BITS 1 5457 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_WIS_PRESENT_SHIFT 2 5458 5459 /* ln_device1 :: devices_in_package_1 :: pmd_pmapresent [01:01] */ 5460 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PMD_PMAPRESENT_MASK 0x0002 5461 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PMD_PMAPRESENT_ALIGN 0 5462 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PMD_PMAPRESENT_BITS 1 5463 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_PMD_PMAPRESENT_SHIFT 1 5464 5465 /* ln_device1 :: devices_in_package_1 :: clause_22registers_present [00:00] */ 5466 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_CLAUSE_22REGISTERS_PRESENT_MASK 0x0001 5467 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_CLAUSE_22REGISTERS_PRESENT_ALIGN 0 5468 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_CLAUSE_22REGISTERS_PRESENT_BITS 1 5469 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_1_CLAUSE_22REGISTERS_PRESENT_SHIFT 0 5470 5471 5472 /**************************************************************************** 5473 * ln_device1 :: devices_in_package_2 5474 */ 5475 /* ln_device1 :: devices_in_package_2 :: vendor_specificdevice_2_present [15:15] */ 5476 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_MASK 0x8000 5477 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_ALIGN 0 5478 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_BITS 1 5479 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_SHIFT 15 5480 5481 /* ln_device1 :: devices_in_package_2 :: vendor_specificdevice_1_present [14:14] */ 5482 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_MASK 0x4000 5483 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_ALIGN 0 5484 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_BITS 1 5485 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_SHIFT 14 5486 5487 /* ln_device1 :: devices_in_package_2 :: clause_22extension_present [13:13] */ 5488 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_MASK 0x2000 5489 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_ALIGN 0 5490 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_BITS 1 5491 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_SHIFT 13 5492 5493 /* ln_device1 :: devices_in_package_2 :: reserved0 [12:00] */ 5494 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_RESERVED0_MASK 0x1fff 5495 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_RESERVED0_ALIGN 0 5496 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_RESERVED0_BITS 13 5497 #define PHY84328_DEV1_DEVICES_IN_PACKAGE_2_RESERVED0_SHIFT 0 5498 5499 5500 /**************************************************************************** 5501 * ln_device1 :: pmd_control_2_register 5502 */ 5503 /* ln_device1 :: pmd_control_2_register :: reserved0 [15:06] */ 5504 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER_RESERVED0_MASK 0xffc0 5505 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER_RESERVED0_ALIGN 0 5506 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER_RESERVED0_BITS 10 5507 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER_RESERVED0_SHIFT 6 5508 5509 /* ln_device1 :: pmd_control_2_register :: pma_typeselection [05:00] */ 5510 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_MASK 0x003f 5511 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_ALIGN 0 5512 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_BITS 6 5513 #define PHY84328_DEV1_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_SHIFT 0 5514 5515 5516 /**************************************************************************** 5517 * ln_device1 :: status_register_2 5518 */ 5519 /* ln_device1 :: status_register_2 :: device_present [15:14] */ 5520 #define PHY84328_DEV1_STATUS_REGISTER_2_DEVICE_PRESENT_MASK 0xc000 5521 #define PHY84328_DEV1_STATUS_REGISTER_2_DEVICE_PRESENT_ALIGN 0 5522 #define PHY84328_DEV1_STATUS_REGISTER_2_DEVICE_PRESENT_BITS 2 5523 #define PHY84328_DEV1_STATUS_REGISTER_2_DEVICE_PRESENT_SHIFT 14 5524 5525 /* ln_device1 :: status_register_2 :: transmit_localfault_ability [13:13] */ 5526 #define PHY84328_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_MASK 0x2000 5527 #define PHY84328_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_ALIGN 0 5528 #define PHY84328_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_BITS 1 5529 #define PHY84328_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_SHIFT 13 5530 5531 /* ln_device1 :: status_register_2 :: receive_localfault_ability [12:12] */ 5532 #define PHY84328_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_MASK 0x1000 5533 #define PHY84328_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_ALIGN 0 5534 #define PHY84328_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_BITS 1 5535 #define PHY84328_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_SHIFT 12 5536 5537 /* ln_device1 :: status_register_2 :: transmit_localfault [11:11] */ 5538 #define PHY84328_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_MASK 0x0800 5539 #define PHY84328_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ALIGN 0 5540 #define PHY84328_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_BITS 1 5541 #define PHY84328_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_SHIFT 11 5542 5543 /* ln_device1 :: status_register_2 :: receive_localfault [10:10] */ 5544 #define PHY84328_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_MASK 0x0400 5545 #define PHY84328_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ALIGN 0 5546 #define PHY84328_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_BITS 1 5547 #define PHY84328_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_SHIFT 10 5548 5549 /* ln_device1 :: status_register_2 :: extended_abilities [09:09] */ 5550 #define PHY84328_DEV1_STATUS_REGISTER_2_EXTENDED_ABILITIES_MASK 0x0200 5551 #define PHY84328_DEV1_STATUS_REGISTER_2_EXTENDED_ABILITIES_ALIGN 0 5552 #define PHY84328_DEV1_STATUS_REGISTER_2_EXTENDED_ABILITIES_BITS 1 5553 #define PHY84328_DEV1_STATUS_REGISTER_2_EXTENDED_ABILITIES_SHIFT 9 5554 5555 /* ln_device1 :: status_register_2 :: pmd_transmitdisable_ability [08:08] */ 5556 #define PHY84328_DEV1_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_MASK 0x0100 5557 #define PHY84328_DEV1_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_ALIGN 0 5558 #define PHY84328_DEV1_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_BITS 1 5559 #define PHY84328_DEV1_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_SHIFT 8 5560 5561 /* ln_device1 :: status_register_2 :: tengbase_srability [07:07] */ 5562 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_SRABILITY_MASK 0x0080 5563 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_SRABILITY_ALIGN 0 5564 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_SRABILITY_BITS 1 5565 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_SRABILITY_SHIFT 7 5566 5567 /* ln_device1 :: status_register_2 :: tengbase_lrability [06:06] */ 5568 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LRABILITY_MASK 0x0040 5569 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LRABILITY_ALIGN 0 5570 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LRABILITY_BITS 1 5571 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LRABILITY_SHIFT 6 5572 5573 /* ln_device1 :: status_register_2 :: tengbase_erability [05:05] */ 5574 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_ERABILITY_MASK 0x0020 5575 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_ERABILITY_ALIGN 0 5576 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_ERABILITY_BITS 1 5577 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_ERABILITY_SHIFT 5 5578 5579 /* ln_device1 :: status_register_2 :: tengbase_lx4ability [04:04] */ 5580 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LX4ABILITY_MASK 0x0010 5581 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LX4ABILITY_ALIGN 0 5582 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LX4ABILITY_BITS 1 5583 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LX4ABILITY_SHIFT 4 5584 5585 /* ln_device1 :: status_register_2 :: tengbase_swability [03:03] */ 5586 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_SWABILITY_MASK 0x0008 5587 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_SWABILITY_ALIGN 0 5588 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_SWABILITY_BITS 1 5589 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_SWABILITY_SHIFT 3 5590 5591 /* ln_device1 :: status_register_2 :: tengbase_lwability [02:02] */ 5592 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LWABILITY_MASK 0x0004 5593 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LWABILITY_ALIGN 0 5594 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LWABILITY_BITS 1 5595 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_LWABILITY_SHIFT 2 5596 5597 /* ln_device1 :: status_register_2 :: tengbase_ewability [01:01] */ 5598 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_EWABILITY_MASK 0x0002 5599 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_EWABILITY_ALIGN 0 5600 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_EWABILITY_BITS 1 5601 #define PHY84328_DEV1_STATUS_REGISTER_2_TENGBASE_EWABILITY_SHIFT 1 5602 5603 /* ln_device1 :: status_register_2 :: pma_local_loopbackability [00:00] */ 5604 #define PHY84328_DEV1_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACKABILITY_MASK 0x0001 5605 #define PHY84328_DEV1_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACKABILITY_ALIGN 0 5606 #define PHY84328_DEV1_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACKABILITY_BITS 1 5607 #define PHY84328_DEV1_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACKABILITY_SHIFT 0 5608 5609 5610 /**************************************************************************** 5611 * ln_device1 :: pmd_transmit_disable_register 5612 */ 5613 /* ln_device1 :: pmd_transmit_disable_register :: reserved0 [15:05] */ 5614 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_RESERVED0_MASK 0xffe0 5615 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_RESERVED0_ALIGN 0 5616 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_RESERVED0_BITS 11 5617 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_RESERVED0_SHIFT 5 5618 5619 /* ln_device1 :: pmd_transmit_disable_register :: pmd_transmitdisable_3 [04:04] */ 5620 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_3_MASK 0x0010 5621 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_3_ALIGN 0 5622 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_3_BITS 1 5623 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_3_SHIFT 4 5624 5625 /* ln_device1 :: pmd_transmit_disable_register :: pmd_transmitdisable_2 [03:03] */ 5626 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_2_MASK 0x0008 5627 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_2_ALIGN 0 5628 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_2_BITS 1 5629 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_2_SHIFT 3 5630 5631 /* ln_device1 :: pmd_transmit_disable_register :: pmd_transmitdisable_1 [02:02] */ 5632 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_1_MASK 0x0004 5633 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_1_ALIGN 0 5634 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_1_BITS 1 5635 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_1_SHIFT 2 5636 5637 /* ln_device1 :: pmd_transmit_disable_register :: pmd_transmitdisable_0 [01:01] */ 5638 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_0_MASK 0x0002 5639 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_0_ALIGN 0 5640 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_0_BITS 1 5641 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_0_SHIFT 1 5642 5643 /* ln_device1 :: pmd_transmit_disable_register :: global_pmdtransmit_disable [00:00] */ 5644 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_GLOBAL_PMDTRANSMIT_DISABLE_MASK 0x0001 5645 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_GLOBAL_PMDTRANSMIT_DISABLE_ALIGN 0 5646 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_GLOBAL_PMDTRANSMIT_DISABLE_BITS 1 5647 #define PHY84328_DEV1_PMD_TRANSMIT_DISABLE_REGISTER_GLOBAL_PMDTRANSMIT_DISABLE_SHIFT 0 5648 5649 5650 /**************************************************************************** 5651 * ln_device1 :: pmd_receive_signal_detect_register 5652 */ 5653 /* ln_device1 :: pmd_receive_signal_detect_register :: reserved0 [15:05] */ 5654 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_MASK 0xffe0 5655 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_ALIGN 0 5656 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_BITS 11 5657 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_SHIFT 5 5658 5659 /* ln_device1 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_3 [04:04] */ 5660 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_MASK 0x0010 5661 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_ALIGN 0 5662 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_BITS 1 5663 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_SHIFT 4 5664 5665 /* ln_device1 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_2 [03:03] */ 5666 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_MASK 0x0008 5667 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_ALIGN 0 5668 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_BITS 1 5669 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_SHIFT 3 5670 5671 /* ln_device1 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_1 [02:02] */ 5672 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_MASK 0x0004 5673 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_ALIGN 0 5674 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_BITS 1 5675 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_SHIFT 2 5676 5677 /* ln_device1 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_0 [01:01] */ 5678 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_MASK 0x0002 5679 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_ALIGN 0 5680 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_BITS 1 5681 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_SHIFT 1 5682 5683 /* ln_device1 :: pmd_receive_signal_detect_register :: global_pmdreceive_signal_ok [00:00] */ 5684 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_MASK 0x0001 5685 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_ALIGN 0 5686 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_BITS 1 5687 #define PHY84328_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_SHIFT 0 5688 5689 5690 /**************************************************************************** 5691 * ln_device1 :: pmd_extended_ability_register 5692 */ 5693 /* ln_device1 :: pmd_extended_ability_register :: reserved0 [15:11] */ 5694 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_MASK 0xf800 5695 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_ALIGN 0 5696 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_BITS 5 5697 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_SHIFT 11 5698 5699 /* ln_device1 :: pmd_extended_ability_register :: fortygbase_tability [10:10] */ 5700 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_TABILITY_MASK 0x0400 5701 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_TABILITY_ALIGN 0 5702 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_TABILITY_BITS 1 5703 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_TABILITY_SHIFT 10 5704 5705 /* ln_device1 :: pmd_extended_ability_register :: reserved1 [09:09] */ 5706 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_MASK 0x0200 5707 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_ALIGN 0 5708 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_BITS 1 5709 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_SHIFT 9 5710 5711 /* ln_device1 :: pmd_extended_ability_register :: tenbase_tability [08:08] */ 5712 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_TABILITY_MASK 0x0100 5713 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_TABILITY_ALIGN 0 5714 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_TABILITY_BITS 1 5715 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_TABILITY_SHIFT 8 5716 5717 /* ln_device1 :: pmd_extended_ability_register :: hundredbase_tx_ability [07:07] */ 5718 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_MASK 0x0080 5719 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_ALIGN 0 5720 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_BITS 1 5721 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_SHIFT 7 5722 5723 /* ln_device1 :: pmd_extended_ability_register :: gigbase_kxability [06:06] */ 5724 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KXABILITY_MASK 0x0040 5725 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KXABILITY_ALIGN 0 5726 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KXABILITY_BITS 1 5727 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KXABILITY_SHIFT 6 5728 5729 /* ln_device1 :: pmd_extended_ability_register :: gigbase_tability [05:05] */ 5730 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_TABILITY_MASK 0x0020 5731 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_TABILITY_ALIGN 0 5732 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_TABILITY_BITS 1 5733 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_TABILITY_SHIFT 5 5734 5735 /* ln_device1 :: pmd_extended_ability_register :: tengbase_krability [04:04] */ 5736 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KRABILITY_MASK 0x0010 5737 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KRABILITY_ALIGN 0 5738 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KRABILITY_BITS 1 5739 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KRABILITY_SHIFT 4 5740 5741 /* ln_device1 :: pmd_extended_ability_register :: tengbase_kx4ability [03:03] */ 5742 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4ABILITY_MASK 0x0008 5743 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4ABILITY_ALIGN 0 5744 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4ABILITY_BITS 1 5745 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4ABILITY_SHIFT 3 5746 5747 /* ln_device1 :: pmd_extended_ability_register :: tengbase_tability [02:02] */ 5748 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_TABILITY_MASK 0x0004 5749 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_TABILITY_ALIGN 0 5750 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_TABILITY_BITS 1 5751 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_TABILITY_SHIFT 2 5752 5753 /* ln_device1 :: pmd_extended_ability_register :: tengbase_lrmability [01:01] */ 5754 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRMABILITY_MASK 0x0002 5755 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRMABILITY_ALIGN 0 5756 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRMABILITY_BITS 1 5757 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRMABILITY_SHIFT 1 5758 5759 /* ln_device1 :: pmd_extended_ability_register :: tengbase_cx4ability [00:00] */ 5760 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4ABILITY_MASK 0x0001 5761 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4ABILITY_ALIGN 0 5762 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4ABILITY_BITS 1 5763 #define PHY84328_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4ABILITY_SHIFT 0 5764 5765 5766 /**************************************************************************** 5767 * ln_device1 :: fortyg_pmd_extended_ability_register 5768 */ 5769 /* ln_device1 :: fortyg_pmd_extended_ability_register :: fortgy_PMA_remote_loopback_Ability [15:15] */ 5770 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTGY_PMA_REMOTE_LOOPBACK_ABILITY_MASK 0x8000 5771 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTGY_PMA_REMOTE_LOOPBACK_ABILITY_ALIGN 0 5772 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTGY_PMA_REMOTE_LOOPBACK_ABILITY_BITS 1 5773 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTGY_PMA_REMOTE_LOOPBACK_ABILITY_SHIFT 15 5774 5775 /* ln_device1 :: fortyg_pmd_extended_ability_register :: reserved0 [14:04] */ 5776 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_MASK 0x7ff0 5777 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_ALIGN 0 5778 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_BITS 11 5779 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_SHIFT 4 5780 5781 /* ln_device1 :: fortyg_pmd_extended_ability_register :: fortygbase_LR4_ability [03:03] */ 5782 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_LR4_ABILITY_MASK 0x0008 5783 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_LR4_ABILITY_ALIGN 0 5784 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_LR4_ABILITY_BITS 1 5785 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_LR4_ABILITY_SHIFT 3 5786 5787 /* ln_device1 :: fortyg_pmd_extended_ability_register :: fortygbase_SR4_ability [02:02] */ 5788 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_SR4_ABILITY_MASK 0x0004 5789 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_SR4_ABILITY_ALIGN 0 5790 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_SR4_ABILITY_BITS 1 5791 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_SR4_ABILITY_SHIFT 2 5792 5793 /* ln_device1 :: fortyg_pmd_extended_ability_register :: fortygbase_CR4_ability [01:01] */ 5794 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_CR4_ABILITY_MASK 0x0002 5795 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_CR4_ABILITY_ALIGN 0 5796 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_CR4_ABILITY_BITS 1 5797 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_CR4_ABILITY_SHIFT 1 5798 5799 /* ln_device1 :: fortyg_pmd_extended_ability_register :: fortygbase_KR4_ability [00:00] */ 5800 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_KR4_ABILITY_MASK 0x0001 5801 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_KR4_ABILITY_ALIGN 0 5802 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_KR4_ABILITY_BITS 1 5803 #define PHY84328_DEV1_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_KR4_ABILITY_SHIFT 0 5804 5805 5806 /**************************************************************************** 5807 * ln_device1 :: pmd_oui_id0_register 5808 */ 5809 /* ln_device1 :: pmd_oui_id0_register :: pmd_form_id_0 [15:00] */ 5810 #define PHY84328_DEV1_PMD_OUI_ID0_REGISTER_PMD_FORM_ID_0_MASK 0xffff 5811 #define PHY84328_DEV1_PMD_OUI_ID0_REGISTER_PMD_FORM_ID_0_ALIGN 0 5812 #define PHY84328_DEV1_PMD_OUI_ID0_REGISTER_PMD_FORM_ID_0_BITS 16 5813 #define PHY84328_DEV1_PMD_OUI_ID0_REGISTER_PMD_FORM_ID_0_SHIFT 0 5814 5815 5816 /**************************************************************************** 5817 * ln_device1 :: pmd_oui_id1_reg 5818 */ 5819 /* ln_device1 :: pmd_oui_id1_reg :: pmd_form_id_1 [15:00] */ 5820 #define PHY84328_DEV1_PMD_OUI_ID1_REG_PMD_FORM_ID_1_MASK 0xffff 5821 #define PHY84328_DEV1_PMD_OUI_ID1_REG_PMD_FORM_ID_1_ALIGN 0 5822 #define PHY84328_DEV1_PMD_OUI_ID1_REG_PMD_FORM_ID_1_BITS 16 5823 #define PHY84328_DEV1_PMD_OUI_ID1_REG_PMD_FORM_ID_1_SHIFT 0 5824 5825 5826 /**************************************************************************** 5827 * ln_device1 :: base_r_pmd_control_register 5828 */ 5829 /* ln_device1 :: base_r_pmd_control_register :: reserved0 [15:02] */ 5830 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESERVED0_MASK 0xfffc 5831 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESERVED0_ALIGN 0 5832 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESERVED0_BITS 14 5833 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESERVED0_SHIFT 2 5834 5835 /* ln_device1 :: base_r_pmd_control_register :: training_enable [01:01] */ 5836 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_TRAINING_ENABLE_MASK 0x0002 5837 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_TRAINING_ENABLE_ALIGN 0 5838 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_TRAINING_ENABLE_BITS 1 5839 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_TRAINING_ENABLE_SHIFT 1 5840 5841 /* ln_device1 :: base_r_pmd_control_register :: restart_training [00:00] */ 5842 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESTART_TRAINING_MASK 0x0001 5843 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESTART_TRAINING_ALIGN 0 5844 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESTART_TRAINING_BITS 1 5845 #define PHY84328_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESTART_TRAINING_SHIFT 0 5846 5847 5848 /**************************************************************************** 5849 * ln_device1 :: base_r_pmd_status_register 5850 */ 5851 /* ln_device1 :: base_r_pmd_status_register :: reserved0 [15:04] */ 5852 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_RESERVED0_MASK 0xfff0 5853 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_RESERVED0_ALIGN 0 5854 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_RESERVED0_BITS 12 5855 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_RESERVED0_SHIFT 4 5856 5857 /* ln_device1 :: base_r_pmd_status_register :: training_failure_lane [03:03] */ 5858 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_TRAINING_FAILURE_LANE_MASK 0x0008 5859 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_TRAINING_FAILURE_LANE_ALIGN 0 5860 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_TRAINING_FAILURE_LANE_BITS 1 5861 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_TRAINING_FAILURE_LANE_SHIFT 3 5862 5863 /* ln_device1 :: base_r_pmd_status_register :: start_up_protocol_status_lane [02:02] */ 5864 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_START_UP_PROTOCOL_STATUS_LANE_MASK 0x0004 5865 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_START_UP_PROTOCOL_STATUS_LANE_ALIGN 0 5866 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_START_UP_PROTOCOL_STATUS_LANE_BITS 1 5867 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_START_UP_PROTOCOL_STATUS_LANE_SHIFT 2 5868 5869 /* ln_device1 :: base_r_pmd_status_register :: frame_lock_lane [01:01] */ 5870 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_FRAME_LOCK_LANE_MASK 0x0002 5871 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_FRAME_LOCK_LANE_ALIGN 0 5872 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_FRAME_LOCK_LANE_BITS 1 5873 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_FRAME_LOCK_LANE_SHIFT 1 5874 5875 /* ln_device1 :: base_r_pmd_status_register :: receiver_status_lane [00:00] */ 5876 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_RECEIVER_STATUS_LANE_MASK 0x0001 5877 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_RECEIVER_STATUS_LANE_ALIGN 0 5878 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_RECEIVER_STATUS_LANE_BITS 1 5879 #define PHY84328_DEV1_BASE_R_PMD_STATUS_REGISTER_RECEIVER_STATUS_LANE_SHIFT 0 5880 5881 5882 /**************************************************************************** 5883 * ln_device1 :: tengbase_kr_lp_coefficient_upd_152 5884 */ 5885 /* ln_device1 :: tengbase_kr_lp_coefficient_upd_152 :: lp_coeff_upd_reg [15:00] */ 5886 #define PHY84328_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_MASK 0xffff 5887 #define PHY84328_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_ALIGN 0 5888 #define PHY84328_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_BITS 16 5889 #define PHY84328_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_SHIFT 0 5890 5891 5892 /**************************************************************************** 5893 * ln_device1 :: tengbase_kr_lp_status_report_reg_153 5894 */ 5895 /* ln_device1 :: tengbase_kr_lp_status_report_reg_153 :: lp_coeff_status_reg [15:00] */ 5896 #define PHY84328_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_MASK 0xffff 5897 #define PHY84328_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_ALIGN 0 5898 #define PHY84328_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_BITS 16 5899 #define PHY84328_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_SHIFT 0 5900 5901 5902 /**************************************************************************** 5903 * ln_device1 :: tengbase_kr_ld_coefficient_upd_154 5904 */ 5905 /* ln_device1 :: tengbase_kr_ld_coefficient_upd_154 :: ld_coeff_upd_reg [15:00] */ 5906 #define PHY84328_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_MASK 0xffff 5907 #define PHY84328_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_ALIGN 0 5908 #define PHY84328_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_BITS 16 5909 #define PHY84328_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_SHIFT 0 5910 5911 5912 /**************************************************************************** 5913 * ln_device1 :: tengbase_kr_ld_status_report_reg_155 5914 */ 5915 /* ln_device1 :: tengbase_kr_ld_status_report_reg_155 :: ld_coeff_status_reg [15:00] */ 5916 #define PHY84328_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_MASK 0xffff 5917 #define PHY84328_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_ALIGN 0 5918 #define PHY84328_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_BITS 16 5919 #define PHY84328_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_SHIFT 0 5920 5921 5922 /**************************************************************************** 5923 * ln_device1 :: tengbase_kx_control_register 5924 */ 5925 /* ln_device1 :: tengbase_kx_control_register :: reserved0 [15:01] */ 5926 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_MASK 0xfffe 5927 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_ALIGN 0 5928 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_BITS 15 5929 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_SHIFT 1 5930 5931 /* ln_device1 :: tengbase_kx_control_register :: pmd_transmit_disable [00:00] */ 5932 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_MASK 0x0001 5933 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_ALIGN 0 5934 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_BITS 1 5935 #define PHY84328_DEV1_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_SHIFT 0 5936 5937 5938 /**************************************************************************** 5939 * ln_device1 :: tengbase_kx_status_register 5940 */ 5941 /* ln_device1 :: tengbase_kx_status_register :: reserved0 [15:14] */ 5942 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED0_MASK 0xc000 5943 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED0_ALIGN 0 5944 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED0_BITS 2 5945 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED0_SHIFT 14 5946 5947 /* ln_device1 :: tengbase_kx_status_register :: transmit_faultability [13:13] */ 5948 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_MASK 0x2000 5949 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_ALIGN 0 5950 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_BITS 1 5951 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_SHIFT 13 5952 5953 /* ln_device1 :: tengbase_kx_status_register :: receive_faultability [12:12] */ 5954 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_MASK 0x1000 5955 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_ALIGN 0 5956 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_BITS 1 5957 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_SHIFT 12 5958 5959 /* ln_device1 :: tengbase_kx_status_register :: transmit_fault [11:11] */ 5960 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_MASK 0x0800 5961 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_ALIGN 0 5962 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_BITS 1 5963 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_SHIFT 11 5964 5965 /* ln_device1 :: tengbase_kx_status_register :: receive_fault [10:10] */ 5966 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_MASK 0x0400 5967 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_ALIGN 0 5968 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_BITS 1 5969 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_SHIFT 10 5970 5971 /* ln_device1 :: tengbase_kx_status_register :: reserved1 [09:09] */ 5972 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED1_MASK 0x0200 5973 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED1_ALIGN 0 5974 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED1_BITS 1 5975 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED1_SHIFT 9 5976 5977 /* ln_device1 :: tengbase_kx_status_register :: pmd_transmitdisable_ability [08:08] */ 5978 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_MASK 0x0100 5979 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_ALIGN 0 5980 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_BITS 1 5981 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_SHIFT 8 5982 5983 /* ln_device1 :: tengbase_kx_status_register :: reserved2 [07:01] */ 5984 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED2_MASK 0x00fe 5985 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED2_ALIGN 0 5986 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED2_BITS 7 5987 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED2_SHIFT 1 5988 5989 /* ln_device1 :: tengbase_kx_status_register :: signal_detectfrom_pmd [00:00] */ 5990 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_MASK 0x0001 5991 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_ALIGN 0 5992 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_BITS 1 5993 #define PHY84328_DEV1_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_SHIFT 0 5994 5995 5996 /**************************************************************************** 5997 * ln_device1_QSFI_AFE_Registers 5998 */ 5999 /**************************************************************************** 6000 * ln_device1 :: anaPllAStatus 6001 */ 6002 /* ln_device1 :: anaPllAStatus :: PLL_lock_detect [15:15] */ 6003 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_LOCK_DETECT_MASK 0x8000 6004 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_LOCK_DETECT_ALIGN 0 6005 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_LOCK_DETECT_BITS 1 6006 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_LOCK_DETECT_SHIFT 15 6007 6008 /* ln_device1 :: anaPllAStatus :: PLL_cal_valid [14:14] */ 6009 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_CAL_VALID_MASK 0x4000 6010 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_CAL_VALID_ALIGN 0 6011 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_CAL_VALID_BITS 1 6012 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_CAL_VALID_SHIFT 14 6013 6014 /* ln_device1 :: anaPllAStatus :: cal_state [13:11] */ 6015 #define PHY84328_DEV1_ANAPLLASTATUS_CAL_STATE_MASK 0x3800 6016 #define PHY84328_DEV1_ANAPLLASTATUS_CAL_STATE_ALIGN 0 6017 #define PHY84328_DEV1_ANAPLLASTATUS_CAL_STATE_BITS 3 6018 #define PHY84328_DEV1_ANAPLLASTATUS_CAL_STATE_SHIFT 11 6019 6020 /* ln_device1 :: anaPllAStatus :: PLL_lock_bar [10:10] */ 6021 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_LOCK_BAR_MASK 0x0400 6022 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_LOCK_BAR_ALIGN 0 6023 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_LOCK_BAR_BITS 1 6024 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_LOCK_BAR_SHIFT 10 6025 6026 /* ln_device1 :: anaPllAStatus :: reserved0 [09:08] */ 6027 #define PHY84328_DEV1_ANAPLLASTATUS_RESERVED0_MASK 0x0300 6028 #define PHY84328_DEV1_ANAPLLASTATUS_RESERVED0_ALIGN 0 6029 #define PHY84328_DEV1_ANAPLLASTATUS_RESERVED0_BITS 2 6030 #define PHY84328_DEV1_ANAPLLASTATUS_RESERVED0_SHIFT 8 6031 6032 /* ln_device1 :: anaPllAStatus :: pll_rescal [07:05] */ 6033 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_RESCAL_MASK 0x00e0 6034 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_RESCAL_ALIGN 0 6035 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_RESCAL_BITS 3 6036 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_RESCAL_SHIFT 5 6037 6038 /* ln_device1 :: anaPllAStatus :: pll_pwrdn [04:04] */ 6039 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_PWRDN_MASK 0x0010 6040 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_PWRDN_ALIGN 0 6041 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_PWRDN_BITS 1 6042 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_PWRDN_SHIFT 4 6043 6044 /* ln_device1 :: anaPllAStatus :: pll_mode_afe [03:00] */ 6045 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_MODE_AFE_MASK 0x000f 6046 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_MODE_AFE_ALIGN 0 6047 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_MODE_AFE_BITS 4 6048 #define PHY84328_DEV1_ANAPLLASTATUS_PLL_MODE_AFE_SHIFT 0 6049 6050 6051 /**************************************************************************** 6052 * ln_device1 :: anaPllAControl 6053 */ 6054 /* ln_device1 :: anaPllAControl :: start_sequencer [15:15] */ 6055 #define PHY84328_DEV1_ANAPLLACONTROL_START_SEQUENCER_MASK 0x8000 6056 #define PHY84328_DEV1_ANAPLLACONTROL_START_SEQUENCER_ALIGN 0 6057 #define PHY84328_DEV1_ANAPLLACONTROL_START_SEQUENCER_BITS 1 6058 #define PHY84328_DEV1_ANAPLLACONTROL_START_SEQUENCER_SHIFT 15 6059 6060 /* ln_device1 :: anaPllAControl :: cal_th [14:13] */ 6061 #define PHY84328_DEV1_ANAPLLACONTROL_CAL_TH_MASK 0x6000 6062 #define PHY84328_DEV1_ANAPLLACONTROL_CAL_TH_ALIGN 0 6063 #define PHY84328_DEV1_ANAPLLACONTROL_CAL_TH_BITS 2 6064 #define PHY84328_DEV1_ANAPLLACONTROL_CAL_TH_SHIFT 13 6065 6066 /* ln_device1 :: anaPllAControl :: cap_delay [12:12] */ 6067 #define PHY84328_DEV1_ANAPLLACONTROL_CAP_DELAY_MASK 0x1000 6068 #define PHY84328_DEV1_ANAPLLACONTROL_CAP_DELAY_ALIGN 0 6069 #define PHY84328_DEV1_ANAPLLACONTROL_CAP_DELAY_BITS 1 6070 #define PHY84328_DEV1_ANAPLLACONTROL_CAP_DELAY_SHIFT 12 6071 6072 /* ln_device1 :: anaPllAControl :: pll_lkdt_byp [11:11] */ 6073 #define PHY84328_DEV1_ANAPLLACONTROL_PLL_LKDT_BYP_MASK 0x0800 6074 #define PHY84328_DEV1_ANAPLLACONTROL_PLL_LKDT_BYP_ALIGN 0 6075 #define PHY84328_DEV1_ANAPLLACONTROL_PLL_LKDT_BYP_BITS 1 6076 #define PHY84328_DEV1_ANAPLLACONTROL_PLL_LKDT_BYP_SHIFT 11 6077 6078 /* ln_device1 :: anaPllAControl :: pll_clk_dis [10:10] */ 6079 #define PHY84328_DEV1_ANAPLLACONTROL_PLL_CLK_DIS_MASK 0x0400 6080 #define PHY84328_DEV1_ANAPLLACONTROL_PLL_CLK_DIS_ALIGN 0 6081 #define PHY84328_DEV1_ANAPLLACONTROL_PLL_CLK_DIS_BITS 1 6082 #define PHY84328_DEV1_ANAPLLACONTROL_PLL_CLK_DIS_SHIFT 10 6083 6084 /* ln_device1 :: anaPllAControl :: reserved0 [09:08] */ 6085 #define PHY84328_DEV1_ANAPLLACONTROL_RESERVED0_MASK 0x0300 6086 #define PHY84328_DEV1_ANAPLLACONTROL_RESERVED0_ALIGN 0 6087 #define PHY84328_DEV1_ANAPLLACONTROL_RESERVED0_BITS 2 6088 #define PHY84328_DEV1_ANAPLLACONTROL_RESERVED0_SHIFT 8 6089 6090 /* ln_device1 :: anaPllAControl :: PllForceDone_en [07:07] */ 6091 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEDONE_EN_MASK 0x0080 6092 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEDONE_EN_ALIGN 0 6093 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEDONE_EN_BITS 1 6094 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEDONE_EN_SHIFT 7 6095 6096 /* ln_device1 :: anaPllAControl :: PllForceDone [06:06] */ 6097 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEDONE_MASK 0x0040 6098 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEDONE_ALIGN 0 6099 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEDONE_BITS 1 6100 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEDONE_SHIFT 6 6101 6102 /* ln_device1 :: anaPllAControl :: PllForcePass [05:05] */ 6103 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEPASS_MASK 0x0020 6104 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEPASS_ALIGN 0 6105 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEPASS_BITS 1 6106 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEPASS_SHIFT 5 6107 6108 /* ln_device1 :: anaPllAControl :: reserved1 [04:03] */ 6109 #define PHY84328_DEV1_ANAPLLACONTROL_RESERVED1_MASK 0x0018 6110 #define PHY84328_DEV1_ANAPLLACONTROL_RESERVED1_ALIGN 0 6111 #define PHY84328_DEV1_ANAPLLACONTROL_RESERVED1_BITS 2 6112 #define PHY84328_DEV1_ANAPLLACONTROL_RESERVED1_SHIFT 3 6113 6114 /* ln_device1 :: anaPllAControl :: PllForceVcoPass_en [02:02] */ 6115 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_EN_MASK 0x0004 6116 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_EN_ALIGN 0 6117 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_EN_BITS 1 6118 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_EN_SHIFT 2 6119 6120 /* ln_device1 :: anaPllAControl :: PllForceVcoPass [01:01] */ 6121 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_MASK 0x0002 6122 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_ALIGN 0 6123 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_BITS 1 6124 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_SHIFT 1 6125 6126 /* ln_device1 :: anaPllAControl :: PllForcePllLock [00:00] */ 6127 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEPLLLOCK_MASK 0x0001 6128 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEPLLLOCK_ALIGN 0 6129 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEPLLLOCK_BITS 1 6130 #define PHY84328_DEV1_ANAPLLACONTROL_PLLFORCEPLLLOCK_SHIFT 0 6131 6132 6133 /**************************************************************************** 6134 * ln_device1 :: anaPllATimer1 6135 */ 6136 /* ln_device1 :: anaPllATimer1 :: reserved0 [15:13] */ 6137 #define PHY84328_DEV1_ANAPLLATIMER1_RESERVED0_MASK 0xe000 6138 #define PHY84328_DEV1_ANAPLLATIMER1_RESERVED0_ALIGN 0 6139 #define PHY84328_DEV1_ANAPLLATIMER1_RESERVED0_BITS 3 6140 #define PHY84328_DEV1_ANAPLLATIMER1_RESERVED0_SHIFT 13 6141 6142 /* ln_device1 :: anaPllATimer1 :: Vco_calibration_StepTime [12:00] */ 6143 #define PHY84328_DEV1_ANAPLLATIMER1_VCO_CALIBRATION_STEPTIME_MASK 0x1fff 6144 #define PHY84328_DEV1_ANAPLLATIMER1_VCO_CALIBRATION_STEPTIME_ALIGN 0 6145 #define PHY84328_DEV1_ANAPLLATIMER1_VCO_CALIBRATION_STEPTIME_BITS 13 6146 #define PHY84328_DEV1_ANAPLLATIMER1_VCO_CALIBRATION_STEPTIME_SHIFT 0 6147 6148 6149 /**************************************************************************** 6150 * ln_device1 :: anaPllATimer2 6151 */ 6152 /* ln_device1 :: anaPllATimer2 :: reserved0 [15:14] */ 6153 #define PHY84328_DEV1_ANAPLLATIMER2_RESERVED0_MASK 0xc000 6154 #define PHY84328_DEV1_ANAPLLATIMER2_RESERVED0_ALIGN 0 6155 #define PHY84328_DEV1_ANAPLLATIMER2_RESERVED0_BITS 2 6156 #define PHY84328_DEV1_ANAPLLATIMER2_RESERVED0_SHIFT 14 6157 6158 /* ln_device1 :: anaPllATimer2 :: freqDetTime [13:13] */ 6159 #define PHY84328_DEV1_ANAPLLATIMER2_FREQDETTIME_MASK 0x2000 6160 #define PHY84328_DEV1_ANAPLLATIMER2_FREQDETTIME_ALIGN 0 6161 #define PHY84328_DEV1_ANAPLLATIMER2_FREQDETTIME_BITS 1 6162 #define PHY84328_DEV1_ANAPLLATIMER2_FREQDETTIME_SHIFT 13 6163 6164 /* ln_device1 :: anaPllATimer2 :: reserved1 [12:08] */ 6165 #define PHY84328_DEV1_ANAPLLATIMER2_RESERVED1_MASK 0x1f00 6166 #define PHY84328_DEV1_ANAPLLATIMER2_RESERVED1_ALIGN 0 6167 #define PHY84328_DEV1_ANAPLLATIMER2_RESERVED1_BITS 5 6168 #define PHY84328_DEV1_ANAPLLATIMER2_RESERVED1_SHIFT 8 6169 6170 /* ln_device1 :: anaPllATimer2 :: retryTime [07:00] */ 6171 #define PHY84328_DEV1_ANAPLLATIMER2_RETRYTIME_MASK 0x00ff 6172 #define PHY84328_DEV1_ANAPLLATIMER2_RETRYTIME_ALIGN 0 6173 #define PHY84328_DEV1_ANAPLLATIMER2_RETRYTIME_BITS 8 6174 #define PHY84328_DEV1_ANAPLLATIMER2_RETRYTIME_SHIFT 0 6175 6176 6177 /**************************************************************************** 6178 * ln_device1 :: anaPllATimer3 6179 */ 6180 /* ln_device1 :: anaPllATimer3 :: freqDetTime [15:00] */ 6181 #define PHY84328_DEV1_ANAPLLATIMER3_FREQDETTIME_MASK 0xffff 6182 #define PHY84328_DEV1_ANAPLLATIMER3_FREQDETTIME_ALIGN 0 6183 #define PHY84328_DEV1_ANAPLLATIMER3_FREQDETTIME_BITS 16 6184 #define PHY84328_DEV1_ANAPLLATIMER3_FREQDETTIME_SHIFT 0 6185 6186 6187 /**************************************************************************** 6188 * ln_device1 :: anaPllcapCtrl 6189 */ 6190 /* ln_device1 :: anaPllcapCtrl :: vcoSeqCYA [15:15] */ 6191 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSEQCYA_MASK 0x8000 6192 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSEQCYA_ALIGN 0 6193 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSEQCYA_BITS 1 6194 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSEQCYA_SHIFT 15 6195 6196 /* ln_device1 :: anaPllcapCtrl :: vcoRestart [14:14] */ 6197 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCORESTART_MASK 0x4000 6198 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCORESTART_ALIGN 0 6199 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCORESTART_BITS 1 6200 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCORESTART_SHIFT 14 6201 6202 /* ln_device1 :: anaPllcapCtrl :: vcoSelectM_en [13:13] */ 6203 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSELECTM_EN_MASK 0x2000 6204 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSELECTM_EN_ALIGN 0 6205 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSELECTM_EN_BITS 1 6206 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSELECTM_EN_SHIFT 13 6207 6208 /* ln_device1 :: anaPllcapCtrl :: vcoForceSlowdn_en [12:12] */ 6209 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDN_EN_MASK 0x1000 6210 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDN_EN_ALIGN 0 6211 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDN_EN_BITS 1 6212 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDN_EN_SHIFT 12 6213 6214 /* ln_device1 :: anaPllcapCtrl :: vcoRstEn [11:11] */ 6215 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCORSTEN_MASK 0x0800 6216 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCORSTEN_ALIGN 0 6217 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCORSTEN_BITS 1 6218 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCORSTEN_SHIFT 11 6219 6220 /* ln_device1 :: anaPllcapCtrl :: vcoCntMask_en [10:10] */ 6221 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOCNTMASK_EN_MASK 0x0400 6222 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOCNTMASK_EN_ALIGN 0 6223 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOCNTMASK_EN_BITS 1 6224 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOCNTMASK_EN_SHIFT 10 6225 6226 /* ln_device1 :: anaPllcapCtrl :: slowdn_xor [09:09] */ 6227 #define PHY84328_DEV1_ANAPLLCAPCTRL_SLOWDN_XOR_MASK 0x0200 6228 #define PHY84328_DEV1_ANAPLLCAPCTRL_SLOWDN_XOR_ALIGN 0 6229 #define PHY84328_DEV1_ANAPLLCAPCTRL_SLOWDN_XOR_BITS 1 6230 #define PHY84328_DEV1_ANAPLLCAPCTRL_SLOWDN_XOR_SHIFT 9 6231 6232 /* ln_device1 :: anaPllcapCtrl :: vcoForceSlowDown [08:08] */ 6233 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDOWN_MASK 0x0100 6234 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDOWN_ALIGN 0 6235 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDOWN_BITS 1 6236 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDOWN_SHIFT 8 6237 6238 /* ln_device1 :: anaPllcapCtrl :: vcoSelectM [07:00] */ 6239 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSELECTM_MASK 0x00ff 6240 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSELECTM_ALIGN 0 6241 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSELECTM_BITS 8 6242 #define PHY84328_DEV1_ANAPLLCAPCTRL_VCOSELECTM_SHIFT 0 6243 6244 6245 /**************************************************************************** 6246 * ln_device1 :: anaPllampCtrl 6247 */ 6248 /* ln_device1 :: anaPllampCtrl :: pll_rescal_manual_en [15:15] */ 6249 #define PHY84328_DEV1_ANAPLLAMPCTRL_PLL_RESCAL_MANUAL_EN_MASK 0x8000 6250 #define PHY84328_DEV1_ANAPLLAMPCTRL_PLL_RESCAL_MANUAL_EN_ALIGN 0 6251 #define PHY84328_DEV1_ANAPLLAMPCTRL_PLL_RESCAL_MANUAL_EN_BITS 1 6252 #define PHY84328_DEV1_ANAPLLAMPCTRL_PLL_RESCAL_MANUAL_EN_SHIFT 15 6253 6254 /* ln_device1 :: anaPllampCtrl :: reserved0 [14:00] */ 6255 #define PHY84328_DEV1_ANAPLLAMPCTRL_RESERVED0_MASK 0x7fff 6256 #define PHY84328_DEV1_ANAPLLAMPCTRL_RESERVED0_ALIGN 0 6257 #define PHY84328_DEV1_ANAPLLAMPCTRL_RESERVED0_BITS 15 6258 #define PHY84328_DEV1_ANAPLLAMPCTRL_RESERVED0_SHIFT 0 6259 6260 6261 /**************************************************************************** 6262 * ln_device1 :: anaPllAStatus1 6263 */ 6264 /* ln_device1 :: anaPllAStatus1 :: reserved0 [15:03] */ 6265 #define PHY84328_DEV1_ANAPLLASTATUS1_RESERVED0_MASK 0xfff8 6266 #define PHY84328_DEV1_ANAPLLASTATUS1_RESERVED0_ALIGN 0 6267 #define PHY84328_DEV1_ANAPLLASTATUS1_RESERVED0_BITS 13 6268 #define PHY84328_DEV1_ANAPLLASTATUS1_RESERVED0_SHIFT 3 6269 6270 /* ln_device1 :: anaPllAStatus1 :: pll_rescal [02:00] */ 6271 #define PHY84328_DEV1_ANAPLLASTATUS1_PLL_RESCAL_MASK 0x0007 6272 #define PHY84328_DEV1_ANAPLLASTATUS1_PLL_RESCAL_ALIGN 0 6273 #define PHY84328_DEV1_ANAPLLASTATUS1_PLL_RESCAL_BITS 3 6274 #define PHY84328_DEV1_ANAPLLASTATUS1_PLL_RESCAL_SHIFT 0 6275 6276 6277 /**************************************************************************** 6278 * ln_device1 :: anaPllAControl0 6279 */ 6280 /* ln_device1 :: anaPllAControl0 :: buf10g_ctr_b0 [15:15] */ 6281 #define PHY84328_DEV1_ANAPLLACONTROL0_BUF10G_CTR_B0_MASK 0x8000 6282 #define PHY84328_DEV1_ANAPLLACONTROL0_BUF10G_CTR_B0_ALIGN 0 6283 #define PHY84328_DEV1_ANAPLLACONTROL0_BUF10G_CTR_B0_BITS 1 6284 #define PHY84328_DEV1_ANAPLLACONTROL0_BUF10G_CTR_B0_SHIFT 15 6285 6286 /* ln_device1 :: anaPllAControl0 :: reserved0 [14:12] */ 6287 #define PHY84328_DEV1_ANAPLLACONTROL0_RESERVED0_MASK 0x7000 6288 #define PHY84328_DEV1_ANAPLLACONTROL0_RESERVED0_ALIGN 0 6289 #define PHY84328_DEV1_ANAPLLACONTROL0_RESERVED0_BITS 3 6290 #define PHY84328_DEV1_ANAPLLACONTROL0_RESERVED0_SHIFT 12 6291 6292 /* ln_device1 :: anaPllAControl0 :: en_test_pllclk [11:11] */ 6293 #define PHY84328_DEV1_ANAPLLACONTROL0_EN_TEST_PLLCLK_MASK 0x0800 6294 #define PHY84328_DEV1_ANAPLLACONTROL0_EN_TEST_PLLCLK_ALIGN 0 6295 #define PHY84328_DEV1_ANAPLLACONTROL0_EN_TEST_PLLCLK_BITS 1 6296 #define PHY84328_DEV1_ANAPLLACONTROL0_EN_TEST_PLLCLK_SHIFT 11 6297 6298 /* ln_device1 :: anaPllAControl0 :: cpar [10:09] */ 6299 #define PHY84328_DEV1_ANAPLLACONTROL0_CPAR_MASK 0x0600 6300 #define PHY84328_DEV1_ANAPLLACONTROL0_CPAR_ALIGN 0 6301 #define PHY84328_DEV1_ANAPLLACONTROL0_CPAR_BITS 2 6302 #define PHY84328_DEV1_ANAPLLACONTROL0_CPAR_SHIFT 9 6303 6304 /* ln_device1 :: anaPllAControl0 :: rpar [08:06] */ 6305 #define PHY84328_DEV1_ANAPLLACONTROL0_RPAR_MASK 0x01c0 6306 #define PHY84328_DEV1_ANAPLLACONTROL0_RPAR_ALIGN 0 6307 #define PHY84328_DEV1_ANAPLLACONTROL0_RPAR_BITS 3 6308 #define PHY84328_DEV1_ANAPLLACONTROL0_RPAR_SHIFT 6 6309 6310 /* ln_device1 :: anaPllAControl0 :: curr_sel [05:02] */ 6311 #define PHY84328_DEV1_ANAPLLACONTROL0_CURR_SEL_MASK 0x003c 6312 #define PHY84328_DEV1_ANAPLLACONTROL0_CURR_SEL_ALIGN 0 6313 #define PHY84328_DEV1_ANAPLLACONTROL0_CURR_SEL_BITS 4 6314 #define PHY84328_DEV1_ANAPLLACONTROL0_CURR_SEL_SHIFT 2 6315 6316 /* ln_device1 :: anaPllAControl0 :: test_bg [01:01] */ 6317 #define PHY84328_DEV1_ANAPLLACONTROL0_TEST_BG_MASK 0x0002 6318 #define PHY84328_DEV1_ANAPLLACONTROL0_TEST_BG_ALIGN 0 6319 #define PHY84328_DEV1_ANAPLLACONTROL0_TEST_BG_BITS 1 6320 #define PHY84328_DEV1_ANAPLLACONTROL0_TEST_BG_SHIFT 1 6321 6322 /* ln_device1 :: anaPllAControl0 :: test_vc [00:00] */ 6323 #define PHY84328_DEV1_ANAPLLACONTROL0_TEST_VC_MASK 0x0001 6324 #define PHY84328_DEV1_ANAPLLACONTROL0_TEST_VC_ALIGN 0 6325 #define PHY84328_DEV1_ANAPLLACONTROL0_TEST_VC_BITS 1 6326 #define PHY84328_DEV1_ANAPLLACONTROL0_TEST_VC_SHIFT 0 6327 6328 6329 /**************************************************************************** 6330 * ln_device1 :: anaPllAControl1 6331 */ 6332 /* ln_device1 :: anaPllAControl1 :: vco_range_b4_b0 [15:11] */ 6333 #define PHY84328_DEV1_ANAPLLACONTROL1_VCO_RANGE_B4_B0_MASK 0xf800 6334 #define PHY84328_DEV1_ANAPLLACONTROL1_VCO_RANGE_B4_B0_ALIGN 0 6335 #define PHY84328_DEV1_ANAPLLACONTROL1_VCO_RANGE_B4_B0_BITS 5 6336 #define PHY84328_DEV1_ANAPLLACONTROL1_VCO_RANGE_B4_B0_SHIFT 11 6337 6338 /* ln_device1 :: anaPllAControl1 :: sel_xaui [10:10] */ 6339 #define PHY84328_DEV1_ANAPLLACONTROL1_SEL_XAUI_MASK 0x0400 6340 #define PHY84328_DEV1_ANAPLLACONTROL1_SEL_XAUI_ALIGN 0 6341 #define PHY84328_DEV1_ANAPLLACONTROL1_SEL_XAUI_BITS 1 6342 #define PHY84328_DEV1_ANAPLLACONTROL1_SEL_XAUI_SHIFT 10 6343 6344 /* ln_device1 :: anaPllAControl1 :: en_e10g [09:09] */ 6345 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_E10G_MASK 0x0200 6346 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_E10G_ALIGN 0 6347 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_E10G_BITS 1 6348 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_E10G_SHIFT 9 6349 6350 /* ln_device1 :: anaPllAControl1 :: pllclksel [08:08] */ 6351 #define PHY84328_DEV1_ANAPLLACONTROL1_PLLCLKSEL_MASK 0x0100 6352 #define PHY84328_DEV1_ANAPLLACONTROL1_PLLCLKSEL_ALIGN 0 6353 #define PHY84328_DEV1_ANAPLLACONTROL1_PLLCLKSEL_BITS 1 6354 #define PHY84328_DEV1_ANAPLLACONTROL1_PLLCLKSEL_SHIFT 8 6355 6356 /* ln_device1 :: anaPllAControl1 :: en_rclk_refout [07:07] */ 6357 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_RCLK_REFOUT_MASK 0x0080 6358 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_RCLK_REFOUT_ALIGN 0 6359 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_RCLK_REFOUT_BITS 1 6360 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_RCLK_REFOUT_SHIFT 7 6361 6362 /* ln_device1 :: anaPllAControl1 :: pll_clkvco_cal_invert [06:06] */ 6363 #define PHY84328_DEV1_ANAPLLACONTROL1_PLL_CLKVCO_CAL_INVERT_MASK 0x0040 6364 #define PHY84328_DEV1_ANAPLLACONTROL1_PLL_CLKVCO_CAL_INVERT_ALIGN 0 6365 #define PHY84328_DEV1_ANAPLLACONTROL1_PLL_CLKVCO_CAL_INVERT_BITS 1 6366 #define PHY84328_DEV1_ANAPLLACONTROL1_PLL_CLKVCO_CAL_INVERT_SHIFT 6 6367 6368 /* ln_device1 :: anaPllAControl1 :: en_i4buf10g [05:04] */ 6369 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_I4BUF10G_MASK 0x0030 6370 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_I4BUF10G_ALIGN 0 6371 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_I4BUF10G_BITS 2 6372 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_I4BUF10G_SHIFT 4 6373 6374 /* ln_device1 :: anaPllAControl1 :: en_i4drv5g [03:02] */ 6375 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_I4DRV5G_MASK 0x000c 6376 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_I4DRV5G_ALIGN 0 6377 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_I4DRV5G_BITS 2 6378 #define PHY84328_DEV1_ANAPLLACONTROL1_EN_I4DRV5G_SHIFT 2 6379 6380 /* ln_device1 :: anaPllAControl1 :: buf10g_ctr_b2_b1 [01:00] */ 6381 #define PHY84328_DEV1_ANAPLLACONTROL1_BUF10G_CTR_B2_B1_MASK 0x0003 6382 #define PHY84328_DEV1_ANAPLLACONTROL1_BUF10G_CTR_B2_B1_ALIGN 0 6383 #define PHY84328_DEV1_ANAPLLACONTROL1_BUF10G_CTR_B2_B1_BITS 2 6384 #define PHY84328_DEV1_ANAPLLACONTROL1_BUF10G_CTR_B2_B1_SHIFT 0 6385 6386 6387 /**************************************************************************** 6388 * ln_device1 :: anaPllAControl2 6389 */ 6390 /* ln_device1 :: anaPllAControl2 :: reserved0 [15:14] */ 6391 #define PHY84328_DEV1_ANAPLLACONTROL2_RESERVED0_MASK 0xc000 6392 #define PHY84328_DEV1_ANAPLLACONTROL2_RESERVED0_ALIGN 0 6393 #define PHY84328_DEV1_ANAPLLACONTROL2_RESERVED0_BITS 2 6394 #define PHY84328_DEV1_ANAPLLACONTROL2_RESERVED0_SHIFT 14 6395 6396 /* ln_device1 :: anaPllAControl2 :: clk_test_sel [13:11] */ 6397 #define PHY84328_DEV1_ANAPLLACONTROL2_CLK_TEST_SEL_MASK 0x3800 6398 #define PHY84328_DEV1_ANAPLLACONTROL2_CLK_TEST_SEL_ALIGN 0 6399 #define PHY84328_DEV1_ANAPLLACONTROL2_CLK_TEST_SEL_BITS 3 6400 #define PHY84328_DEV1_ANAPLLACONTROL2_CLK_TEST_SEL_SHIFT 11 6401 6402 /* ln_device1 :: anaPllAControl2 :: bg_pwrdn [10:10] */ 6403 #define PHY84328_DEV1_ANAPLLACONTROL2_BG_PWRDN_MASK 0x0400 6404 #define PHY84328_DEV1_ANAPLLACONTROL2_BG_PWRDN_ALIGN 0 6405 #define PHY84328_DEV1_ANAPLLACONTROL2_BG_PWRDN_BITS 1 6406 #define PHY84328_DEV1_ANAPLLACONTROL2_BG_PWRDN_SHIFT 10 6407 6408 /* ln_device1 :: anaPllAControl2 :: pll_pwrdn [09:09] */ 6409 #define PHY84328_DEV1_ANAPLLACONTROL2_PLL_PWRDN_MASK 0x0200 6410 #define PHY84328_DEV1_ANAPLLACONTROL2_PLL_PWRDN_ALIGN 0 6411 #define PHY84328_DEV1_ANAPLLACONTROL2_PLL_PWRDN_BITS 1 6412 #define PHY84328_DEV1_ANAPLLACONTROL2_PLL_PWRDN_SHIFT 9 6413 6414 /* ln_device1 :: anaPllAControl2 :: en_cmos_refout [08:08] */ 6415 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_CMOS_REFOUT_MASK 0x0100 6416 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_CMOS_REFOUT_ALIGN 0 6417 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_CMOS_REFOUT_BITS 1 6418 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_CMOS_REFOUT_SHIFT 8 6419 6420 /* ln_device1 :: anaPllAControl2 :: en_cml_refout [07:07] */ 6421 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_CML_REFOUT_MASK 0x0080 6422 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_CML_REFOUT_ALIGN 0 6423 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_CML_REFOUT_BITS 1 6424 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_CML_REFOUT_SHIFT 7 6425 6426 /* ln_device1 :: anaPllAControl2 :: vdd_bgb [06:06] */ 6427 #define PHY84328_DEV1_ANAPLLACONTROL2_VDD_BGB_MASK 0x0040 6428 #define PHY84328_DEV1_ANAPLLACONTROL2_VDD_BGB_ALIGN 0 6429 #define PHY84328_DEV1_ANAPLLACONTROL2_VDD_BGB_BITS 1 6430 #define PHY84328_DEV1_ANAPLLACONTROL2_VDD_BGB_SHIFT 6 6431 6432 /* ln_device1 :: anaPllAControl2 :: terminal_sel [05:05] */ 6433 #define PHY84328_DEV1_ANAPLLACONTROL2_TERMINAL_SEL_MASK 0x0020 6434 #define PHY84328_DEV1_ANAPLLACONTROL2_TERMINAL_SEL_ALIGN 0 6435 #define PHY84328_DEV1_ANAPLLACONTROL2_TERMINAL_SEL_BITS 1 6436 #define PHY84328_DEV1_ANAPLLACONTROL2_TERMINAL_SEL_SHIFT 5 6437 6438 /* ln_device1 :: anaPllAControl2 :: vco_bias [04:03] */ 6439 #define PHY84328_DEV1_ANAPLLACONTROL2_VCO_BIAS_MASK 0x0018 6440 #define PHY84328_DEV1_ANAPLLACONTROL2_VCO_BIAS_ALIGN 0 6441 #define PHY84328_DEV1_ANAPLLACONTROL2_VCO_BIAS_BITS 2 6442 #define PHY84328_DEV1_ANAPLLACONTROL2_VCO_BIAS_SHIFT 3 6443 6444 /* ln_device1 :: anaPllAControl2 :: en_kvh [02:02] */ 6445 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_KVH_MASK 0x0004 6446 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_KVH_ALIGN 0 6447 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_KVH_BITS 1 6448 #define PHY84328_DEV1_ANAPLLACONTROL2_EN_KVH_SHIFT 2 6449 6450 /* ln_device1 :: anaPllAControl2 :: vco_range_b6_b5 [01:00] */ 6451 #define PHY84328_DEV1_ANAPLLACONTROL2_VCO_RANGE_B6_B5_MASK 0x0003 6452 #define PHY84328_DEV1_ANAPLLACONTROL2_VCO_RANGE_B6_B5_ALIGN 0 6453 #define PHY84328_DEV1_ANAPLLACONTROL2_VCO_RANGE_B6_B5_BITS 2 6454 #define PHY84328_DEV1_ANAPLLACONTROL2_VCO_RANGE_B6_B5_SHIFT 0 6455 6456 6457 /**************************************************************************** 6458 * ln_device1 :: anaPllAControl3 6459 */ 6460 /* ln_device1 :: anaPllAControl3 :: bg_ptatadj [15:12] */ 6461 #define PHY84328_DEV1_ANAPLLACONTROL3_BG_PTATADJ_MASK 0xf000 6462 #define PHY84328_DEV1_ANAPLLACONTROL3_BG_PTATADJ_ALIGN 0 6463 #define PHY84328_DEV1_ANAPLLACONTROL3_BG_PTATADJ_BITS 4 6464 #define PHY84328_DEV1_ANAPLLACONTROL3_BG_PTATADJ_SHIFT 12 6465 6466 /* ln_device1 :: anaPllAControl3 :: bg_ctatadj [11:08] */ 6467 #define PHY84328_DEV1_ANAPLLACONTROL3_BG_CTATADJ_MASK 0x0f00 6468 #define PHY84328_DEV1_ANAPLLACONTROL3_BG_CTATADJ_ALIGN 0 6469 #define PHY84328_DEV1_ANAPLLACONTROL3_BG_CTATADJ_BITS 4 6470 #define PHY84328_DEV1_ANAPLLACONTROL3_BG_CTATADJ_SHIFT 8 6471 6472 /* ln_device1 :: anaPllAControl3 :: adc_ptat_ctrl [07:06] */ 6473 #define PHY84328_DEV1_ANAPLLACONTROL3_ADC_PTAT_CTRL_MASK 0x00c0 6474 #define PHY84328_DEV1_ANAPLLACONTROL3_ADC_PTAT_CTRL_ALIGN 0 6475 #define PHY84328_DEV1_ANAPLLACONTROL3_ADC_PTAT_CTRL_BITS 2 6476 #define PHY84328_DEV1_ANAPLLACONTROL3_ADC_PTAT_CTRL_SHIFT 6 6477 6478 /* ln_device1 :: anaPllAControl3 :: reserved0 [05:04] */ 6479 #define PHY84328_DEV1_ANAPLLACONTROL3_RESERVED0_MASK 0x0030 6480 #define PHY84328_DEV1_ANAPLLACONTROL3_RESERVED0_ALIGN 0 6481 #define PHY84328_DEV1_ANAPLLACONTROL3_RESERVED0_BITS 2 6482 #define PHY84328_DEV1_ANAPLLACONTROL3_RESERVED0_SHIFT 4 6483 6484 /* ln_device1 :: anaPllAControl3 :: pll_mode [03:03] */ 6485 #define PHY84328_DEV1_ANAPLLACONTROL3_PLL_MODE_MASK 0x0008 6486 #define PHY84328_DEV1_ANAPLLACONTROL3_PLL_MODE_ALIGN 0 6487 #define PHY84328_DEV1_ANAPLLACONTROL3_PLL_MODE_BITS 1 6488 #define PHY84328_DEV1_ANAPLLACONTROL3_PLL_MODE_SHIFT 3 6489 6490 /* ln_device1 :: anaPllAControl3 :: pll_pon [02:00] */ 6491 #define PHY84328_DEV1_ANAPLLACONTROL3_PLL_PON_MASK 0x0007 6492 #define PHY84328_DEV1_ANAPLLACONTROL3_PLL_PON_ALIGN 0 6493 #define PHY84328_DEV1_ANAPLLACONTROL3_PLL_PON_BITS 3 6494 #define PHY84328_DEV1_ANAPLLACONTROL3_PLL_PON_SHIFT 0 6495 6496 6497 /**************************************************************************** 6498 * ln_device1 :: anaPllAControl4 6499 */ 6500 /* ln_device1 :: anaPllAControl4 :: i_ndiv_frac_lsb [15:02] */ 6501 #define PHY84328_DEV1_ANAPLLACONTROL4_I_NDIV_FRAC_LSB_MASK 0xfffc 6502 #define PHY84328_DEV1_ANAPLLACONTROL4_I_NDIV_FRAC_LSB_ALIGN 0 6503 #define PHY84328_DEV1_ANAPLLACONTROL4_I_NDIV_FRAC_LSB_BITS 14 6504 #define PHY84328_DEV1_ANAPLLACONTROL4_I_NDIV_FRAC_LSB_SHIFT 2 6505 6506 /* ln_device1 :: anaPllAControl4 :: dac_ctat_ctl [01:00] */ 6507 #define PHY84328_DEV1_ANAPLLACONTROL4_DAC_CTAT_CTL_MASK 0x0003 6508 #define PHY84328_DEV1_ANAPLLACONTROL4_DAC_CTAT_CTL_ALIGN 0 6509 #define PHY84328_DEV1_ANAPLLACONTROL4_DAC_CTAT_CTL_BITS 2 6510 #define PHY84328_DEV1_ANAPLLACONTROL4_DAC_CTAT_CTL_SHIFT 0 6511 6512 6513 /**************************************************************************** 6514 * ln_device1 :: anaPllAControl5 6515 */ 6516 /* ln_device1 :: anaPllAControl5 :: i_dsm_resetb [15:15] */ 6517 #define PHY84328_DEV1_ANAPLLACONTROL5_I_DSM_RESETB_MASK 0x8000 6518 #define PHY84328_DEV1_ANAPLLACONTROL5_I_DSM_RESETB_ALIGN 0 6519 #define PHY84328_DEV1_ANAPLLACONTROL5_I_DSM_RESETB_BITS 1 6520 #define PHY84328_DEV1_ANAPLLACONTROL5_I_DSM_RESETB_SHIFT 15 6521 6522 /* ln_device1 :: anaPllAControl5 :: i_ndiv_dither_en [14:14] */ 6523 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_DITHER_EN_MASK 0x4000 6524 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_DITHER_EN_ALIGN 0 6525 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_DITHER_EN_BITS 1 6526 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_DITHER_EN_SHIFT 14 6527 6528 /* ln_device1 :: anaPllAControl5 :: i_pll_wis_mode [13:13] */ 6529 #define PHY84328_DEV1_ANAPLLACONTROL5_I_PLL_WIS_MODE_MASK 0x2000 6530 #define PHY84328_DEV1_ANAPLLACONTROL5_I_PLL_WIS_MODE_ALIGN 0 6531 #define PHY84328_DEV1_ANAPLLACONTROL5_I_PLL_WIS_MODE_BITS 1 6532 #define PHY84328_DEV1_ANAPLLACONTROL5_I_PLL_WIS_MODE_SHIFT 13 6533 6534 /* ln_device1 :: anaPllAControl5 :: i_div7_bypass_wis [12:12] */ 6535 #define PHY84328_DEV1_ANAPLLACONTROL5_I_DIV7_BYPASS_WIS_MASK 0x1000 6536 #define PHY84328_DEV1_ANAPLLACONTROL5_I_DIV7_BYPASS_WIS_ALIGN 0 6537 #define PHY84328_DEV1_ANAPLLACONTROL5_I_DIV7_BYPASS_WIS_BITS 1 6538 #define PHY84328_DEV1_ANAPLLACONTROL5_I_DIV7_BYPASS_WIS_SHIFT 12 6539 6540 /* ln_device1 :: anaPllAControl5 :: i_ndiv_int [11:04] */ 6541 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_INT_MASK 0x0ff0 6542 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_INT_ALIGN 0 6543 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_INT_BITS 8 6544 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_INT_SHIFT 4 6545 6546 /* ln_device1 :: anaPllAControl5 :: i_ndiv_frac_msb [03:00] */ 6547 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_FRAC_MSB_MASK 0x000f 6548 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_FRAC_MSB_ALIGN 0 6549 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_FRAC_MSB_BITS 4 6550 #define PHY84328_DEV1_ANAPLLACONTROL5_I_NDIV_FRAC_MSB_SHIFT 0 6551 6552 6553 /**************************************************************************** 6554 * ln_device1 :: anaPllAControl6 6555 */ 6556 /* ln_device1 :: anaPllAControl6 :: reserved0 [15:06] */ 6557 #define PHY84328_DEV1_ANAPLLACONTROL6_RESERVED0_MASK 0xffc0 6558 #define PHY84328_DEV1_ANAPLLACONTROL6_RESERVED0_ALIGN 0 6559 #define PHY84328_DEV1_ANAPLLACONTROL6_RESERVED0_BITS 10 6560 #define PHY84328_DEV1_ANAPLLACONTROL6_RESERVED0_SHIFT 6 6561 6562 /* ln_device1 :: anaPllAControl6 :: sel_fp3cap [05:01] */ 6563 #define PHY84328_DEV1_ANAPLLACONTROL6_SEL_FP3CAP_MASK 0x003e 6564 #define PHY84328_DEV1_ANAPLLACONTROL6_SEL_FP3CAP_ALIGN 0 6565 #define PHY84328_DEV1_ANAPLLACONTROL6_SEL_FP3CAP_BITS 5 6566 #define PHY84328_DEV1_ANAPLLACONTROL6_SEL_FP3CAP_SHIFT 1 6567 6568 /* ln_device1 :: anaPllAControl6 :: i_pll_wis_frac_en [00:00] */ 6569 #define PHY84328_DEV1_ANAPLLACONTROL6_I_PLL_WIS_FRAC_EN_MASK 0x0001 6570 #define PHY84328_DEV1_ANAPLLACONTROL6_I_PLL_WIS_FRAC_EN_ALIGN 0 6571 #define PHY84328_DEV1_ANAPLLACONTROL6_I_PLL_WIS_FRAC_EN_BITS 1 6572 #define PHY84328_DEV1_ANAPLLACONTROL6_I_PLL_WIS_FRAC_EN_SHIFT 0 6573 6574 6575 /**************************************************************************** 6576 * ln_device1 :: anaTxAStatus 6577 */ 6578 /* ln_device1 :: anaTxAStatus :: reserved0 [15:11] */ 6579 #define PHY84328_DEV1_ANATXASTATUS_RESERVED0_MASK 0xf800 6580 #define PHY84328_DEV1_ANATXASTATUS_RESERVED0_ALIGN 0 6581 #define PHY84328_DEV1_ANATXASTATUS_RESERVED0_BITS 5 6582 #define PHY84328_DEV1_ANATXASTATUS_RESERVED0_SHIFT 11 6583 6584 /* ln_device1 :: anaTxAStatus :: os_mode [10:07] */ 6585 #define PHY84328_DEV1_ANATXASTATUS_OS_MODE_MASK 0x0780 6586 #define PHY84328_DEV1_ANATXASTATUS_OS_MODE_ALIGN 0 6587 #define PHY84328_DEV1_ANATXASTATUS_OS_MODE_BITS 4 6588 #define PHY84328_DEV1_ANATXASTATUS_OS_MODE_SHIFT 7 6589 6590 /* ln_device1 :: anaTxAStatus :: txdisable_ln [06:06] */ 6591 #define PHY84328_DEV1_ANATXASTATUS_TXDISABLE_LN_MASK 0x0040 6592 #define PHY84328_DEV1_ANATXASTATUS_TXDISABLE_LN_ALIGN 0 6593 #define PHY84328_DEV1_ANATXASTATUS_TXDISABLE_LN_BITS 1 6594 #define PHY84328_DEV1_ANATXASTATUS_TXDISABLE_LN_SHIFT 6 6595 6596 /* ln_device1 :: anaTxAStatus :: txferr_stky [05:05] */ 6597 #define PHY84328_DEV1_ANATXASTATUS_TXFERR_STKY_MASK 0x0020 6598 #define PHY84328_DEV1_ANATXASTATUS_TXFERR_STKY_ALIGN 0 6599 #define PHY84328_DEV1_ANATXASTATUS_TXFERR_STKY_BITS 1 6600 #define PHY84328_DEV1_ANATXASTATUS_TXFERR_STKY_SHIFT 5 6601 6602 /* ln_device1 :: anaTxAStatus :: tbi_mode [04:04] */ 6603 #define PHY84328_DEV1_ANATXASTATUS_TBI_MODE_MASK 0x0010 6604 #define PHY84328_DEV1_ANATXASTATUS_TBI_MODE_ALIGN 0 6605 #define PHY84328_DEV1_ANATXASTATUS_TBI_MODE_BITS 1 6606 #define PHY84328_DEV1_ANATXASTATUS_TBI_MODE_SHIFT 4 6607 6608 /* ln_device1 :: anaTxAStatus :: tx_reset [03:03] */ 6609 #define PHY84328_DEV1_ANATXASTATUS_TX_RESET_MASK 0x0008 6610 #define PHY84328_DEV1_ANATXASTATUS_TX_RESET_ALIGN 0 6611 #define PHY84328_DEV1_ANATXASTATUS_TX_RESET_BITS 1 6612 #define PHY84328_DEV1_ANATXASTATUS_TX_RESET_SHIFT 3 6613 6614 /* ln_device1 :: anaTxAStatus :: tx_pwrdn [02:02] */ 6615 #define PHY84328_DEV1_ANATXASTATUS_TX_PWRDN_MASK 0x0004 6616 #define PHY84328_DEV1_ANATXASTATUS_TX_PWRDN_ALIGN 0 6617 #define PHY84328_DEV1_ANATXASTATUS_TX_PWRDN_BITS 1 6618 #define PHY84328_DEV1_ANATXASTATUS_TX_PWRDN_SHIFT 2 6619 6620 /* ln_device1 :: anaTxAStatus :: rltxferr_stky [01:01] */ 6621 #define PHY84328_DEV1_ANATXASTATUS_RLTXFERR_STKY_MASK 0x0002 6622 #define PHY84328_DEV1_ANATXASTATUS_RLTXFERR_STKY_ALIGN 0 6623 #define PHY84328_DEV1_ANATXASTATUS_RLTXFERR_STKY_BITS 1 6624 #define PHY84328_DEV1_ANATXASTATUS_RLTXFERR_STKY_SHIFT 1 6625 6626 /* ln_device1 :: anaTxAStatus :: txpll_lock [00:00] */ 6627 #define PHY84328_DEV1_ANATXASTATUS_TXPLL_LOCK_MASK 0x0001 6628 #define PHY84328_DEV1_ANATXASTATUS_TXPLL_LOCK_ALIGN 0 6629 #define PHY84328_DEV1_ANATXASTATUS_TXPLL_LOCK_BITS 1 6630 #define PHY84328_DEV1_ANATXASTATUS_TXPLL_LOCK_SHIFT 0 6631 6632 6633 /**************************************************************************** 6634 * ln_device1 :: anaTxAControl 6635 */ 6636 /* ln_device1 :: anaTxAControl :: reserved0 [15:15] */ 6637 #define PHY84328_DEV1_ANATXACONTROL_RESERVED0_MASK 0x8000 6638 #define PHY84328_DEV1_ANATXACONTROL_RESERVED0_ALIGN 0 6639 #define PHY84328_DEV1_ANATXACONTROL_RESERVED0_BITS 1 6640 #define PHY84328_DEV1_ANATXACONTROL_RESERVED0_SHIFT 15 6641 6642 /* ln_device1 :: anaTxAControl :: force_txclk [14:14] */ 6643 #define PHY84328_DEV1_ANATXACONTROL_FORCE_TXCLK_MASK 0x4000 6644 #define PHY84328_DEV1_ANATXACONTROL_FORCE_TXCLK_ALIGN 0 6645 #define PHY84328_DEV1_ANATXACONTROL_FORCE_TXCLK_BITS 1 6646 #define PHY84328_DEV1_ANATXACONTROL_FORCE_TXCLK_SHIFT 14 6647 6648 /* ln_device1 :: anaTxAControl :: tx_fifo_rst [13:13] */ 6649 #define PHY84328_DEV1_ANATXACONTROL_TX_FIFO_RST_MASK 0x2000 6650 #define PHY84328_DEV1_ANATXACONTROL_TX_FIFO_RST_ALIGN 0 6651 #define PHY84328_DEV1_ANATXACONTROL_TX_FIFO_RST_BITS 1 6652 #define PHY84328_DEV1_ANATXACONTROL_TX_FIFO_RST_SHIFT 13 6653 6654 /* ln_device1 :: anaTxAControl :: reserved1 [12:10] */ 6655 #define PHY84328_DEV1_ANATXACONTROL_RESERVED1_MASK 0x1c00 6656 #define PHY84328_DEV1_ANATXACONTROL_RESERVED1_ALIGN 0 6657 #define PHY84328_DEV1_ANATXACONTROL_RESERVED1_BITS 3 6658 #define PHY84328_DEV1_ANATXACONTROL_RESERVED1_SHIFT 10 6659 6660 /* ln_device1 :: anaTxAControl :: gloopOutEn [09:09] */ 6661 #define PHY84328_DEV1_ANATXACONTROL_GLOOPOUTEN_MASK 0x0200 6662 #define PHY84328_DEV1_ANATXACONTROL_GLOOPOUTEN_ALIGN 0 6663 #define PHY84328_DEV1_ANATXACONTROL_GLOOPOUTEN_BITS 1 6664 #define PHY84328_DEV1_ANATXACONTROL_GLOOPOUTEN_SHIFT 9 6665 6666 /* ln_device1 :: anaTxAControl :: prbs_en [08:08] */ 6667 #define PHY84328_DEV1_ANATXACONTROL_PRBS_EN_MASK 0x0100 6668 #define PHY84328_DEV1_ANATXACONTROL_PRBS_EN_ALIGN 0 6669 #define PHY84328_DEV1_ANATXACONTROL_PRBS_EN_BITS 1 6670 #define PHY84328_DEV1_ANATXACONTROL_PRBS_EN_SHIFT 8 6671 6672 /* ln_device1 :: anaTxAControl :: pckt_en [07:07] */ 6673 #define PHY84328_DEV1_ANATXACONTROL_PCKT_EN_MASK 0x0080 6674 #define PHY84328_DEV1_ANATXACONTROL_PCKT_EN_ALIGN 0 6675 #define PHY84328_DEV1_ANATXACONTROL_PCKT_EN_BITS 1 6676 #define PHY84328_DEV1_ANATXACONTROL_PCKT_EN_SHIFT 7 6677 6678 /* ln_device1 :: anaTxAControl :: pckt_strt [06:06] */ 6679 #define PHY84328_DEV1_ANATXACONTROL_PCKT_STRT_MASK 0x0040 6680 #define PHY84328_DEV1_ANATXACONTROL_PCKT_STRT_ALIGN 0 6681 #define PHY84328_DEV1_ANATXACONTROL_PCKT_STRT_BITS 1 6682 #define PHY84328_DEV1_ANATXACONTROL_PCKT_STRT_SHIFT 6 6683 6684 /* ln_device1 :: anaTxAControl :: txpol_flip [05:05] */ 6685 #define PHY84328_DEV1_ANATXACONTROL_TXPOL_FLIP_MASK 0x0020 6686 #define PHY84328_DEV1_ANATXACONTROL_TXPOL_FLIP_ALIGN 0 6687 #define PHY84328_DEV1_ANATXACONTROL_TXPOL_FLIP_BITS 1 6688 #define PHY84328_DEV1_ANATXACONTROL_TXPOL_FLIP_SHIFT 5 6689 6690 /* ln_device1 :: anaTxAControl :: rtbi_flip [04:04] */ 6691 #define PHY84328_DEV1_ANATXACONTROL_RTBI_FLIP_MASK 0x0010 6692 #define PHY84328_DEV1_ANATXACONTROL_RTBI_FLIP_ALIGN 0 6693 #define PHY84328_DEV1_ANATXACONTROL_RTBI_FLIP_BITS 1 6694 #define PHY84328_DEV1_ANATXACONTROL_RTBI_FLIP_SHIFT 4 6695 6696 /* ln_device1 :: anaTxAControl :: eden_r [03:03] */ 6697 #define PHY84328_DEV1_ANATXACONTROL_EDEN_R_MASK 0x0008 6698 #define PHY84328_DEV1_ANATXACONTROL_EDEN_R_ALIGN 0 6699 #define PHY84328_DEV1_ANATXACONTROL_EDEN_R_BITS 1 6700 #define PHY84328_DEV1_ANATXACONTROL_EDEN_R_SHIFT 3 6701 6702 /* ln_device1 :: anaTxAControl :: eden_force_r [02:02] */ 6703 #define PHY84328_DEV1_ANATXACONTROL_EDEN_FORCE_R_MASK 0x0004 6704 #define PHY84328_DEV1_ANATXACONTROL_EDEN_FORCE_R_ALIGN 0 6705 #define PHY84328_DEV1_ANATXACONTROL_EDEN_FORCE_R_BITS 1 6706 #define PHY84328_DEV1_ANATXACONTROL_EDEN_FORCE_R_SHIFT 2 6707 6708 /* ln_device1 :: anaTxAControl :: txpat_en [01:01] */ 6709 #define PHY84328_DEV1_ANATXACONTROL_TXPAT_EN_MASK 0x0002 6710 #define PHY84328_DEV1_ANATXACONTROL_TXPAT_EN_ALIGN 0 6711 #define PHY84328_DEV1_ANATXACONTROL_TXPAT_EN_BITS 1 6712 #define PHY84328_DEV1_ANATXACONTROL_TXPAT_EN_SHIFT 1 6713 6714 /* ln_device1 :: anaTxAControl :: tx_mdata_en [00:00] */ 6715 #define PHY84328_DEV1_ANATXACONTROL_TX_MDATA_EN_MASK 0x0001 6716 #define PHY84328_DEV1_ANATXACONTROL_TX_MDATA_EN_ALIGN 0 6717 #define PHY84328_DEV1_ANATXACONTROL_TX_MDATA_EN_BITS 1 6718 #define PHY84328_DEV1_ANATXACONTROL_TX_MDATA_EN_SHIFT 0 6719 6720 6721 /**************************************************************************** 6722 * ln_device1 :: anaTxAStatus1 6723 */ 6724 /* ln_device1 :: anaTxAStatus1 :: reserved0 [15:04] */ 6725 #define PHY84328_DEV1_ANATXASTATUS1_RESERVED0_MASK 0xfff0 6726 #define PHY84328_DEV1_ANATXASTATUS1_RESERVED0_ALIGN 0 6727 #define PHY84328_DEV1_ANATXASTATUS1_RESERVED0_BITS 12 6728 #define PHY84328_DEV1_ANATXASTATUS1_RESERVED0_SHIFT 4 6729 6730 /* ln_device1 :: anaTxAStatus1 :: Tx_rescal [03:01] */ 6731 #define PHY84328_DEV1_ANATXASTATUS1_TX_RESCAL_MASK 0x000e 6732 #define PHY84328_DEV1_ANATXASTATUS1_TX_RESCAL_ALIGN 0 6733 #define PHY84328_DEV1_ANATXASTATUS1_TX_RESCAL_BITS 3 6734 #define PHY84328_DEV1_ANATXASTATUS1_TX_RESCAL_SHIFT 1 6735 6736 /* ln_device1 :: anaTxAStatus1 :: reserved1 [00:00] */ 6737 #define PHY84328_DEV1_ANATXASTATUS1_RESERVED1_MASK 0x0001 6738 #define PHY84328_DEV1_ANATXASTATUS1_RESERVED1_ALIGN 0 6739 #define PHY84328_DEV1_ANATXASTATUS1_RESERVED1_BITS 1 6740 #define PHY84328_DEV1_ANATXASTATUS1_RESERVED1_SHIFT 0 6741 6742 6743 /**************************************************************************** 6744 * ln_device1 :: anaTxAControl1 6745 */ 6746 /* ln_device1 :: anaTxAControl1 :: idriver [15:12] */ 6747 #define PHY84328_DEV1_ANATXACONTROL1_IDRIVER_MASK 0xf000 6748 #define PHY84328_DEV1_ANATXACONTROL1_IDRIVER_ALIGN 0 6749 #define PHY84328_DEV1_ANATXACONTROL1_IDRIVER_BITS 4 6750 #define PHY84328_DEV1_ANATXACONTROL1_IDRIVER_SHIFT 12 6751 6752 /* ln_device1 :: anaTxAControl1 :: ipredriver [11:08] */ 6753 #define PHY84328_DEV1_ANATXACONTROL1_IPREDRIVER_MASK 0x0f00 6754 #define PHY84328_DEV1_ANATXACONTROL1_IPREDRIVER_ALIGN 0 6755 #define PHY84328_DEV1_ANATXACONTROL1_IPREDRIVER_BITS 4 6756 #define PHY84328_DEV1_ANATXACONTROL1_IPREDRIVER_SHIFT 8 6757 6758 /* ln_device1 :: anaTxAControl1 :: sl_ctrl [07:04] */ 6759 #define PHY84328_DEV1_ANATXACONTROL1_SL_CTRL_MASK 0x00f0 6760 #define PHY84328_DEV1_ANATXACONTROL1_SL_CTRL_ALIGN 0 6761 #define PHY84328_DEV1_ANATXACONTROL1_SL_CTRL_BITS 4 6762 #define PHY84328_DEV1_ANATXACONTROL1_SL_CTRL_SHIFT 4 6763 6764 /* ln_device1 :: anaTxAControl1 :: ena_prot [03:03] */ 6765 #define PHY84328_DEV1_ANATXACONTROL1_ENA_PROT_MASK 0x0008 6766 #define PHY84328_DEV1_ANATXACONTROL1_ENA_PROT_ALIGN 0 6767 #define PHY84328_DEV1_ANATXACONTROL1_ENA_PROT_BITS 1 6768 #define PHY84328_DEV1_ANATXACONTROL1_ENA_PROT_SHIFT 3 6769 6770 /* ln_device1 :: anaTxAControl1 :: tx_bmode [02:02] */ 6771 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMODE_MASK 0x0004 6772 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMODE_ALIGN 0 6773 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMODE_BITS 1 6774 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMODE_SHIFT 2 6775 6776 /* ln_device1 :: anaTxAControl1 :: tx_bmax [01:01] */ 6777 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMAX_MASK 0x0002 6778 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMAX_ALIGN 0 6779 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMAX_BITS 1 6780 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMAX_SHIFT 1 6781 6782 /* ln_device1 :: anaTxAControl1 :: tx_bmin [00:00] */ 6783 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMIN_MASK 0x0001 6784 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMIN_ALIGN 0 6785 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMIN_BITS 1 6786 #define PHY84328_DEV1_ANATXACONTROL1_TX_BMIN_SHIFT 0 6787 6788 6789 /**************************************************************************** 6790 * ln_device1 :: anaTxAControl2 6791 */ 6792 /* ln_device1 :: anaTxAControl2 :: main_tap [15:11] */ 6793 #define PHY84328_DEV1_ANATXACONTROL2_MAIN_TAP_MASK 0xf800 6794 #define PHY84328_DEV1_ANATXACONTROL2_MAIN_TAP_ALIGN 0 6795 #define PHY84328_DEV1_ANATXACONTROL2_MAIN_TAP_BITS 5 6796 #define PHY84328_DEV1_ANATXACONTROL2_MAIN_TAP_SHIFT 11 6797 6798 /* ln_device1 :: anaTxAControl2 :: tx_pwrdn [10:10] */ 6799 #define PHY84328_DEV1_ANATXACONTROL2_TX_PWRDN_MASK 0x0400 6800 #define PHY84328_DEV1_ANATXACONTROL2_TX_PWRDN_ALIGN 0 6801 #define PHY84328_DEV1_ANATXACONTROL2_TX_PWRDN_BITS 1 6802 #define PHY84328_DEV1_ANATXACONTROL2_TX_PWRDN_SHIFT 10 6803 6804 /* ln_device1 :: anaTxAControl2 :: tx_modeselect [09:07] */ 6805 #define PHY84328_DEV1_ANATXACONTROL2_TX_MODESELECT_MASK 0x0380 6806 #define PHY84328_DEV1_ANATXACONTROL2_TX_MODESELECT_ALIGN 0 6807 #define PHY84328_DEV1_ANATXACONTROL2_TX_MODESELECT_BITS 3 6808 #define PHY84328_DEV1_ANATXACONTROL2_TX_MODESELECT_SHIFT 7 6809 6810 /* ln_device1 :: anaTxAControl2 :: imux [06:04] */ 6811 #define PHY84328_DEV1_ANATXACONTROL2_IMUX_MASK 0x0070 6812 #define PHY84328_DEV1_ANATXACONTROL2_IMUX_ALIGN 0 6813 #define PHY84328_DEV1_ANATXACONTROL2_IMUX_BITS 3 6814 #define PHY84328_DEV1_ANATXACONTROL2_IMUX_SHIFT 4 6815 6816 /* ln_device1 :: anaTxAControl2 :: imux_latch [03:01] */ 6817 #define PHY84328_DEV1_ANATXACONTROL2_IMUX_LATCH_MASK 0x000e 6818 #define PHY84328_DEV1_ANATXACONTROL2_IMUX_LATCH_ALIGN 0 6819 #define PHY84328_DEV1_ANATXACONTROL2_IMUX_LATCH_BITS 3 6820 #define PHY84328_DEV1_ANATXACONTROL2_IMUX_LATCH_SHIFT 1 6821 6822 /* ln_device1 :: anaTxAControl2 :: test_drv [00:00] */ 6823 #define PHY84328_DEV1_ANATXACONTROL2_TEST_DRV_MASK 0x0001 6824 #define PHY84328_DEV1_ANATXACONTROL2_TEST_DRV_ALIGN 0 6825 #define PHY84328_DEV1_ANATXACONTROL2_TEST_DRV_BITS 1 6826 #define PHY84328_DEV1_ANATXACONTROL2_TEST_DRV_SHIFT 0 6827 6828 6829 /**************************************************************************** 6830 * ln_device1 :: anaTxAControl3 6831 */ 6832 /* ln_device1 :: anaTxAControl3 :: tx_pi_bias [15:14] */ 6833 #define PHY84328_DEV1_ANATXACONTROL3_TX_PI_BIAS_MASK 0xc000 6834 #define PHY84328_DEV1_ANATXACONTROL3_TX_PI_BIAS_ALIGN 0 6835 #define PHY84328_DEV1_ANATXACONTROL3_TX_PI_BIAS_BITS 2 6836 #define PHY84328_DEV1_ANATXACONTROL3_TX_PI_BIAS_SHIFT 14 6837 6838 /* ln_device1 :: anaTxAControl3 :: ticksel [13:12] */ 6839 #define PHY84328_DEV1_ANATXACONTROL3_TICKSEL_MASK 0x3000 6840 #define PHY84328_DEV1_ANATXACONTROL3_TICKSEL_ALIGN 0 6841 #define PHY84328_DEV1_ANATXACONTROL3_TICKSEL_BITS 2 6842 #define PHY84328_DEV1_ANATXACONTROL3_TICKSEL_SHIFT 12 6843 6844 /* ln_device1 :: anaTxAControl3 :: iclkgen [11:09] */ 6845 #define PHY84328_DEV1_ANATXACONTROL3_ICLKGEN_MASK 0x0e00 6846 #define PHY84328_DEV1_ANATXACONTROL3_ICLKGEN_ALIGN 0 6847 #define PHY84328_DEV1_ANATXACONTROL3_ICLKGEN_BITS 3 6848 #define PHY84328_DEV1_ANATXACONTROL3_ICLKGEN_SHIFT 9 6849 6850 /* ln_device1 :: anaTxAControl3 :: postcursor_tap_fine [08:08] */ 6851 #define PHY84328_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_FINE_MASK 0x0100 6852 #define PHY84328_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_FINE_ALIGN 0 6853 #define PHY84328_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_FINE_BITS 1 6854 #define PHY84328_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_FINE_SHIFT 8 6855 6856 /* ln_device1 :: anaTxAControl3 :: postcursor_tap [07:04] */ 6857 #define PHY84328_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_MASK 0x00f0 6858 #define PHY84328_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_ALIGN 0 6859 #define PHY84328_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_BITS 4 6860 #define PHY84328_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_SHIFT 4 6861 6862 /* ln_device1 :: anaTxAControl3 :: i_en_8p5G [03:03] */ 6863 #define PHY84328_DEV1_ANATXACONTROL3_I_EN_8P5G_MASK 0x0008 6864 #define PHY84328_DEV1_ANATXACONTROL3_I_EN_8P5G_ALIGN 0 6865 #define PHY84328_DEV1_ANATXACONTROL3_I_EN_8P5G_BITS 1 6866 #define PHY84328_DEV1_ANATXACONTROL3_I_EN_8P5G_SHIFT 3 6867 6868 /* ln_device1 :: anaTxAControl3 :: precursor_tap [02:00] */ 6869 #define PHY84328_DEV1_ANATXACONTROL3_PRECURSOR_TAP_MASK 0x0007 6870 #define PHY84328_DEV1_ANATXACONTROL3_PRECURSOR_TAP_ALIGN 0 6871 #define PHY84328_DEV1_ANATXACONTROL3_PRECURSOR_TAP_BITS 3 6872 #define PHY84328_DEV1_ANATXACONTROL3_PRECURSOR_TAP_SHIFT 0 6873 6874 6875 /**************************************************************************** 6876 * ln_device1 :: anaTxAControl4 6877 */ 6878 /* ln_device1 :: anaTxAControl4 :: xfi_lowlatency_fifo_ctrl [15:14] */ 6879 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_CTRL_MASK 0xc000 6880 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_CTRL_ALIGN 0 6881 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_CTRL_BITS 2 6882 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_CTRL_SHIFT 14 6883 6884 /* ln_device1 :: anaTxAControl4 :: xfi_lowlatency_fifo_zero_out [13:13] */ 6885 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_ZERO_OUT_MASK 0x2000 6886 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_ZERO_OUT_ALIGN 0 6887 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_ZERO_OUT_BITS 1 6888 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_ZERO_OUT_SHIFT 13 6889 6890 /* ln_device1 :: anaTxAControl4 :: xfi_lowlatency_polarity_flip [12:12] */ 6891 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_POLARITY_FLIP_MASK 0x1000 6892 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_POLARITY_FLIP_ALIGN 0 6893 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_POLARITY_FLIP_BITS 1 6894 #define PHY84328_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_POLARITY_FLIP_SHIFT 12 6895 6896 /* ln_device1 :: anaTxAControl4 :: lowlatency_selectpath_tx [11:11] */ 6897 #define PHY84328_DEV1_ANATXACONTROL4_LOWLATENCY_SELECTPATH_TX_MASK 0x0800 6898 #define PHY84328_DEV1_ANATXACONTROL4_LOWLATENCY_SELECTPATH_TX_ALIGN 0 6899 #define PHY84328_DEV1_ANATXACONTROL4_LOWLATENCY_SELECTPATH_TX_BITS 1 6900 #define PHY84328_DEV1_ANATXACONTROL4_LOWLATENCY_SELECTPATH_TX_SHIFT 11 6901 6902 /* ln_device1 :: anaTxAControl4 :: postcursor2_tap [10:08] */ 6903 #define PHY84328_DEV1_ANATXACONTROL4_POSTCURSOR2_TAP_MASK 0x0700 6904 #define PHY84328_DEV1_ANATXACONTROL4_POSTCURSOR2_TAP_ALIGN 0 6905 #define PHY84328_DEV1_ANATXACONTROL4_POSTCURSOR2_TAP_BITS 3 6906 #define PHY84328_DEV1_ANATXACONTROL4_POSTCURSOR2_TAP_SHIFT 8 6907 6908 /* ln_device1 :: anaTxAControl4 :: drv_bias_en [07:07] */ 6909 #define PHY84328_DEV1_ANATXACONTROL4_DRV_BIAS_EN_MASK 0x0080 6910 #define PHY84328_DEV1_ANATXACONTROL4_DRV_BIAS_EN_ALIGN 0 6911 #define PHY84328_DEV1_ANATXACONTROL4_DRV_BIAS_EN_BITS 1 6912 #define PHY84328_DEV1_ANATXACONTROL4_DRV_BIAS_EN_SHIFT 7 6913 6914 /* ln_device1 :: anaTxAControl4 :: i_tuneb [06:06] */ 6915 #define PHY84328_DEV1_ANATXACONTROL4_I_TUNEB_MASK 0x0040 6916 #define PHY84328_DEV1_ANATXACONTROL4_I_TUNEB_ALIGN 0 6917 #define PHY84328_DEV1_ANATXACONTROL4_I_TUNEB_BITS 1 6918 #define PHY84328_DEV1_ANATXACONTROL4_I_TUNEB_SHIFT 6 6919 6920 /* ln_device1 :: anaTxAControl4 :: test_bias_sel [05:04] */ 6921 #define PHY84328_DEV1_ANATXACONTROL4_TEST_BIAS_SEL_MASK 0x0030 6922 #define PHY84328_DEV1_ANATXACONTROL4_TEST_BIAS_SEL_ALIGN 0 6923 #define PHY84328_DEV1_ANATXACONTROL4_TEST_BIAS_SEL_BITS 2 6924 #define PHY84328_DEV1_ANATXACONTROL4_TEST_BIAS_SEL_SHIFT 4 6925 6926 /* ln_device1 :: anaTxAControl4 :: tx_pon [03:01] */ 6927 #define PHY84328_DEV1_ANATXACONTROL4_TX_PON_MASK 0x000e 6928 #define PHY84328_DEV1_ANATXACONTROL4_TX_PON_ALIGN 0 6929 #define PHY84328_DEV1_ANATXACONTROL4_TX_PON_BITS 3 6930 #define PHY84328_DEV1_ANATXACONTROL4_TX_PON_SHIFT 1 6931 6932 /* ln_device1 :: anaTxAControl4 :: tx_pi_bias [00:00] */ 6933 #define PHY84328_DEV1_ANATXACONTROL4_TX_PI_BIAS_MASK 0x0001 6934 #define PHY84328_DEV1_ANATXACONTROL4_TX_PI_BIAS_ALIGN 0 6935 #define PHY84328_DEV1_ANATXACONTROL4_TX_PI_BIAS_BITS 1 6936 #define PHY84328_DEV1_ANATXACONTROL4_TX_PI_BIAS_SHIFT 0 6937 6938 6939 /**************************************************************************** 6940 * ln_device1 :: anaTxAControl5 6941 */ 6942 /* ln_device1 :: anaTxAControl5 :: reserved0 [15:04] */ 6943 #define PHY84328_DEV1_ANATXACONTROL5_RESERVED0_MASK 0xfff0 6944 #define PHY84328_DEV1_ANATXACONTROL5_RESERVED0_ALIGN 0 6945 #define PHY84328_DEV1_ANATXACONTROL5_RESERVED0_BITS 12 6946 #define PHY84328_DEV1_ANATXACONTROL5_RESERVED0_SHIFT 4 6947 6948 /* ln_device1 :: anaTxAControl5 :: clamp_enb [03:03] */ 6949 #define PHY84328_DEV1_ANATXACONTROL5_CLAMP_ENB_MASK 0x0008 6950 #define PHY84328_DEV1_ANATXACONTROL5_CLAMP_ENB_ALIGN 0 6951 #define PHY84328_DEV1_ANATXACONTROL5_CLAMP_ENB_BITS 1 6952 #define PHY84328_DEV1_ANATXACONTROL5_CLAMP_ENB_SHIFT 3 6953 6954 /* ln_device1 :: anaTxAControl5 :: testport_low_curr [02:02] */ 6955 #define PHY84328_DEV1_ANATXACONTROL5_TESTPORT_LOW_CURR_MASK 0x0004 6956 #define PHY84328_DEV1_ANATXACONTROL5_TESTPORT_LOW_CURR_ALIGN 0 6957 #define PHY84328_DEV1_ANATXACONTROL5_TESTPORT_LOW_CURR_BITS 1 6958 #define PHY84328_DEV1_ANATXACONTROL5_TESTPORT_LOW_CURR_SHIFT 2 6959 6960 /* ln_device1 :: anaTxAControl5 :: xfi_lowlatency_pdb [01:01] */ 6961 #define PHY84328_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_PDB_MASK 0x0002 6962 #define PHY84328_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_PDB_ALIGN 0 6963 #define PHY84328_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_PDB_BITS 1 6964 #define PHY84328_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_PDB_SHIFT 1 6965 6966 /* ln_device1 :: anaTxAControl5 :: xfi_lowlatency_fifo_resetb [00:00] */ 6967 #define PHY84328_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_FIFO_RESETB_MASK 0x0001 6968 #define PHY84328_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_FIFO_RESETB_ALIGN 0 6969 #define PHY84328_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_FIFO_RESETB_BITS 1 6970 #define PHY84328_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_FIFO_RESETB_SHIFT 0 6971 6972 6973 /**************************************************************************** 6974 * ln_device1 :: anaTxAControl6 6975 */ 6976 /* ln_device1 :: anaTxAControl6 :: reserved0 [15:10] */ 6977 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED0_MASK 0xfc00 6978 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED0_ALIGN 0 6979 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED0_BITS 6 6980 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED0_SHIFT 10 6981 6982 /* ln_device1 :: anaTxAControl6 :: lowlatency_fifo_resetb [09:09] */ 6983 #define PHY84328_DEV1_ANATXACONTROL6_LOWLATENCY_FIFO_RESETB_MASK 0x0200 6984 #define PHY84328_DEV1_ANATXACONTROL6_LOWLATENCY_FIFO_RESETB_ALIGN 0 6985 #define PHY84328_DEV1_ANATXACONTROL6_LOWLATENCY_FIFO_RESETB_BITS 1 6986 #define PHY84328_DEV1_ANATXACONTROL6_LOWLATENCY_FIFO_RESETB_SHIFT 9 6987 6988 /* ln_device1 :: anaTxAControl6 :: lowlatency_path_select [08:08] */ 6989 #define PHY84328_DEV1_ANATXACONTROL6_LOWLATENCY_PATH_SELECT_MASK 0x0100 6990 #define PHY84328_DEV1_ANATXACONTROL6_LOWLATENCY_PATH_SELECT_ALIGN 0 6991 #define PHY84328_DEV1_ANATXACONTROL6_LOWLATENCY_PATH_SELECT_BITS 1 6992 #define PHY84328_DEV1_ANATXACONTROL6_LOWLATENCY_PATH_SELECT_SHIFT 8 6993 6994 /* ln_device1 :: anaTxAControl6 :: reserved1 [07:03] */ 6995 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED1_MASK 0x00f8 6996 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED1_ALIGN 0 6997 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED1_BITS 5 6998 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED1_SHIFT 3 6999 7000 /* ln_device1 :: anaTxAControl6 :: rloop [02:02] */ 7001 #define PHY84328_DEV1_ANATXACONTROL6_RLOOP_MASK 0x0004 7002 #define PHY84328_DEV1_ANATXACONTROL6_RLOOP_ALIGN 0 7003 #define PHY84328_DEV1_ANATXACONTROL6_RLOOP_BITS 1 7004 #define PHY84328_DEV1_ANATXACONTROL6_RLOOP_SHIFT 2 7005 7006 /* ln_device1 :: anaTxAControl6 :: reserved2 [01:01] */ 7007 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED2_MASK 0x0002 7008 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED2_ALIGN 0 7009 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED2_BITS 1 7010 #define PHY84328_DEV1_ANATXACONTROL6_RESERVED2_SHIFT 1 7011 7012 /* ln_device1 :: anaTxAControl6 :: disable_transmit [00:00] */ 7013 #define PHY84328_DEV1_ANATXACONTROL6_DISABLE_TRANSMIT_MASK 0x0001 7014 #define PHY84328_DEV1_ANATXACONTROL6_DISABLE_TRANSMIT_ALIGN 0 7015 #define PHY84328_DEV1_ANATXACONTROL6_DISABLE_TRANSMIT_BITS 1 7016 #define PHY84328_DEV1_ANATXACONTROL6_DISABLE_TRANSMIT_SHIFT 0 7017 7018 7019 /**************************************************************************** 7020 * ln_device1 :: anaTxAControl7 7021 */ 7022 /* ln_device1 :: anaTxAControl7 :: reserved0 [15:15] */ 7023 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED0_MASK 0x8000 7024 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED0_ALIGN 0 7025 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED0_BITS 1 7026 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED0_SHIFT 15 7027 7028 /* ln_device1 :: anaTxAControl7 :: PRBS_20_manual_width_value [14:14] */ 7029 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_VALUE_MASK 0x4000 7030 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_VALUE_ALIGN 0 7031 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_VALUE_BITS 1 7032 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_VALUE_SHIFT 14 7033 7034 /* ln_device1 :: anaTxAControl7 :: PRBS_20_manual_width_select_enable [13:13] */ 7035 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_SELECT_ENABLE_MASK 0x2000 7036 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_SELECT_ENABLE_ALIGN 0 7037 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_SELECT_ENABLE_BITS 1 7038 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_SELECT_ENABLE_SHIFT 13 7039 7040 /* ln_device1 :: anaTxAControl7 :: PRBS_Bit_order_swap [12:12] */ 7041 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_BIT_ORDER_SWAP_MASK 0x1000 7042 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_BIT_ORDER_SWAP_ALIGN 0 7043 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_BIT_ORDER_SWAP_BITS 1 7044 #define PHY84328_DEV1_ANATXACONTROL7_PRBS_BIT_ORDER_SWAP_SHIFT 12 7045 7046 /* ln_device1 :: anaTxAControl7 :: Tx_Bit_order_swap [11:11] */ 7047 #define PHY84328_DEV1_ANATXACONTROL7_TX_BIT_ORDER_SWAP_MASK 0x0800 7048 #define PHY84328_DEV1_ANATXACONTROL7_TX_BIT_ORDER_SWAP_ALIGN 0 7049 #define PHY84328_DEV1_ANATXACONTROL7_TX_BIT_ORDER_SWAP_BITS 1 7050 #define PHY84328_DEV1_ANATXACONTROL7_TX_BIT_ORDER_SWAP_SHIFT 11 7051 7052 /* ln_device1 :: anaTxAControl7 :: tx_reset [10:10] */ 7053 #define PHY84328_DEV1_ANATXACONTROL7_TX_RESET_MASK 0x0400 7054 #define PHY84328_DEV1_ANATXACONTROL7_TX_RESET_ALIGN 0 7055 #define PHY84328_DEV1_ANATXACONTROL7_TX_RESET_BITS 1 7056 #define PHY84328_DEV1_ANATXACONTROL7_TX_RESET_SHIFT 10 7057 7058 /* ln_device1 :: anaTxAControl7 :: tx_power_down [09:09] */ 7059 #define PHY84328_DEV1_ANATXACONTROL7_TX_POWER_DOWN_MASK 0x0200 7060 #define PHY84328_DEV1_ANATXACONTROL7_TX_POWER_DOWN_ALIGN 0 7061 #define PHY84328_DEV1_ANATXACONTROL7_TX_POWER_DOWN_BITS 1 7062 #define PHY84328_DEV1_ANATXACONTROL7_TX_POWER_DOWN_SHIFT 9 7063 7064 /* ln_device1 :: anaTxAControl7 :: Lane_PRBS_order_new_b2 [08:08] */ 7065 #define PHY84328_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B2_MASK 0x0100 7066 #define PHY84328_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B2_ALIGN 0 7067 #define PHY84328_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B2_BITS 1 7068 #define PHY84328_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B2_SHIFT 8 7069 7070 /* ln_device1 :: anaTxAControl7 :: reserved1 [07:07] */ 7071 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED1_MASK 0x0080 7072 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED1_ALIGN 0 7073 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED1_BITS 1 7074 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED1_SHIFT 7 7075 7076 /* ln_device1 :: anaTxAControl7 :: select_new_prbs [06:06] */ 7077 #define PHY84328_DEV1_ANATXACONTROL7_SELECT_NEW_PRBS_MASK 0x0040 7078 #define PHY84328_DEV1_ANATXACONTROL7_SELECT_NEW_PRBS_ALIGN 0 7079 #define PHY84328_DEV1_ANATXACONTROL7_SELECT_NEW_PRBS_BITS 1 7080 #define PHY84328_DEV1_ANATXACONTROL7_SELECT_NEW_PRBS_SHIFT 6 7081 7082 /* ln_device1 :: anaTxAControl7 :: new_prbs_en [05:05] */ 7083 #define PHY84328_DEV1_ANATXACONTROL7_NEW_PRBS_EN_MASK 0x0020 7084 #define PHY84328_DEV1_ANATXACONTROL7_NEW_PRBS_EN_ALIGN 0 7085 #define PHY84328_DEV1_ANATXACONTROL7_NEW_PRBS_EN_BITS 1 7086 #define PHY84328_DEV1_ANATXACONTROL7_NEW_PRBS_EN_SHIFT 5 7087 7088 /* ln_device1 :: anaTxAControl7 :: new_prbs_inv [04:04] */ 7089 #define PHY84328_DEV1_ANATXACONTROL7_NEW_PRBS_INV_MASK 0x0010 7090 #define PHY84328_DEV1_ANATXACONTROL7_NEW_PRBS_INV_ALIGN 0 7091 #define PHY84328_DEV1_ANATXACONTROL7_NEW_PRBS_INV_BITS 1 7092 #define PHY84328_DEV1_ANATXACONTROL7_NEW_PRBS_INV_SHIFT 4 7093 7094 /* ln_device1 :: anaTxAControl7 :: Lane_PRBS_order_new_b1_0 [03:02] */ 7095 #define PHY84328_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B1_0_MASK 0x000c 7096 #define PHY84328_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B1_0_ALIGN 0 7097 #define PHY84328_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B1_0_BITS 2 7098 #define PHY84328_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B1_0_SHIFT 2 7099 7100 /* ln_device1 :: anaTxAControl7 :: reserved2 [01:00] */ 7101 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED2_MASK 0x0003 7102 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED2_ALIGN 0 7103 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED2_BITS 2 7104 #define PHY84328_DEV1_ANATXACONTROL7_RESERVED2_SHIFT 0 7105 7106 7107 /**************************************************************************** 7108 * ln_device1 :: anaRxStatus 7109 */ 7110 /* ln_device1 :: anaRxStatus :: rxStatus [15:00] */ 7111 #define PHY84328_DEV1_ANARXSTATUS_RXSTATUS_MASK 0xffff 7112 #define PHY84328_DEV1_ANARXSTATUS_RXSTATUS_ALIGN 0 7113 #define PHY84328_DEV1_ANARXSTATUS_RXSTATUS_BITS 16 7114 #define PHY84328_DEV1_ANARXSTATUS_RXSTATUS_SHIFT 0 7115 7116 7117 /**************************************************************************** 7118 * ln_device1 :: anaRxControl 7119 */ 7120 /* ln_device1 :: anaRxControl :: reserved0 [15:13] */ 7121 #define PHY84328_DEV1_ANARXCONTROL_RESERVED0_MASK 0xe000 7122 #define PHY84328_DEV1_ANARXCONTROL_RESERVED0_ALIGN 0 7123 #define PHY84328_DEV1_ANARXCONTROL_RESERVED0_BITS 3 7124 #define PHY84328_DEV1_ANARXCONTROL_RESERVED0_SHIFT 13 7125 7126 /* ln_device1 :: anaRxControl :: reserved_SigDetect [12:10] */ 7127 #define PHY84328_DEV1_ANARXCONTROL_RESERVED_SIGDETECT_MASK 0x1c00 7128 #define PHY84328_DEV1_ANARXCONTROL_RESERVED_SIGDETECT_ALIGN 0 7129 #define PHY84328_DEV1_ANARXCONTROL_RESERVED_SIGDETECT_BITS 3 7130 #define PHY84328_DEV1_ANARXCONTROL_RESERVED_SIGDETECT_SHIFT 10 7131 7132 /* ln_device1 :: anaRxControl :: override_sigdet_en [09:09] */ 7133 #define PHY84328_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 7134 #define PHY84328_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 7135 #define PHY84328_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 7136 #define PHY84328_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 7137 7138 /* ln_device1 :: anaRxControl :: override_sigdet_val [08:08] */ 7139 #define PHY84328_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 7140 #define PHY84328_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 7141 #define PHY84328_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 7142 #define PHY84328_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 7143 7144 /* ln_device1 :: anaRxControl :: reserved1 [07:07] */ 7145 #define PHY84328_DEV1_ANARXCONTROL_RESERVED1_MASK 0x0080 7146 #define PHY84328_DEV1_ANARXCONTROL_RESERVED1_ALIGN 0 7147 #define PHY84328_DEV1_ANARXCONTROL_RESERVED1_BITS 1 7148 #define PHY84328_DEV1_ANARXCONTROL_RESERVED1_SHIFT 7 7149 7150 /* ln_device1 :: anaRxControl :: reserved_phfreq_rst_dis_fst_SM [06:06] */ 7151 #define PHY84328_DEV1_ANARXCONTROL_RESERVED_PHFREQ_RST_DIS_FST_SM_MASK 0x0040 7152 #define PHY84328_DEV1_ANARXCONTROL_RESERVED_PHFREQ_RST_DIS_FST_SM_ALIGN 0 7153 #define PHY84328_DEV1_ANARXCONTROL_RESERVED_PHFREQ_RST_DIS_FST_SM_BITS 1 7154 #define PHY84328_DEV1_ANARXCONTROL_RESERVED_PHFREQ_RST_DIS_FST_SM_SHIFT 6 7155 7156 /* ln_device1 :: anaRxControl :: reserved2 [05:03] */ 7157 #define PHY84328_DEV1_ANARXCONTROL_RESERVED2_MASK 0x0038 7158 #define PHY84328_DEV1_ANARXCONTROL_RESERVED2_ALIGN 0 7159 #define PHY84328_DEV1_ANARXCONTROL_RESERVED2_BITS 3 7160 #define PHY84328_DEV1_ANARXCONTROL_RESERVED2_SHIFT 3 7161 7162 /* ln_device1 :: anaRxControl :: status_sel [02:00] */ 7163 #define PHY84328_DEV1_ANARXCONTROL_STATUS_SEL_MASK 0x0007 7164 #define PHY84328_DEV1_ANARXCONTROL_STATUS_SEL_ALIGN 0 7165 #define PHY84328_DEV1_ANARXCONTROL_STATUS_SEL_BITS 3 7166 #define PHY84328_DEV1_ANARXCONTROL_STATUS_SEL_SHIFT 0 7167 7168 7169 /**************************************************************************** 7170 * ln_device1 :: anaRxSigdet 7171 */ 7172 /* ln_device1 :: anaRxSigdet :: sigdetTime_SM [15:08] */ 7173 #define PHY84328_DEV1_ANARXSIGDET_SIGDETTIME_SM_MASK 0xff00 7174 #define PHY84328_DEV1_ANARXSIGDET_SIGDETTIME_SM_ALIGN 0 7175 #define PHY84328_DEV1_ANARXSIGDET_SIGDETTIME_SM_BITS 8 7176 #define PHY84328_DEV1_ANARXSIGDET_SIGDETTIME_SM_SHIFT 8 7177 7178 /* ln_device1 :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */ 7179 #define PHY84328_DEV1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK 0x0080 7180 #define PHY84328_DEV1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN 0 7181 #define PHY84328_DEV1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS 1 7182 #define PHY84328_DEV1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT 7 7183 7184 /* ln_device1 :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */ 7185 #define PHY84328_DEV1_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK 0x0040 7186 #define PHY84328_DEV1_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN 0 7187 #define PHY84328_DEV1_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS 1 7188 #define PHY84328_DEV1_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT 6 7189 7190 /* ln_device1 :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */ 7191 #define PHY84328_DEV1_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK 0x0020 7192 #define PHY84328_DEV1_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN 0 7193 #define PHY84328_DEV1_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS 1 7194 #define PHY84328_DEV1_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT 5 7195 7196 /* ln_device1 :: anaRxSigdet :: rx_sigdet_r [04:04] */ 7197 #define PHY84328_DEV1_ANARXSIGDET_RX_SIGDET_R_MASK 0x0010 7198 #define PHY84328_DEV1_ANARXSIGDET_RX_SIGDET_R_ALIGN 0 7199 #define PHY84328_DEV1_ANARXSIGDET_RX_SIGDET_R_BITS 1 7200 #define PHY84328_DEV1_ANARXSIGDET_RX_SIGDET_R_SHIFT 4 7201 7202 /* ln_device1 :: anaRxSigdet :: rx_sigdet_force_r [03:03] */ 7203 #define PHY84328_DEV1_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK 0x0008 7204 #define PHY84328_DEV1_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN 0 7205 #define PHY84328_DEV1_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS 1 7206 #define PHY84328_DEV1_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT 3 7207 7208 /* ln_device1 :: anaRxSigdet :: invert_rx_sigdet [02:02] */ 7209 #define PHY84328_DEV1_ANARXSIGDET_INVERT_RX_SIGDET_MASK 0x0004 7210 #define PHY84328_DEV1_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN 0 7211 #define PHY84328_DEV1_ANARXSIGDET_INVERT_RX_SIGDET_BITS 1 7212 #define PHY84328_DEV1_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT 2 7213 7214 /* ln_device1 :: anaRxSigdet :: reserved0 [01:00] */ 7215 #define PHY84328_DEV1_ANARXSIGDET_RESERVED0_MASK 0x0003 7216 #define PHY84328_DEV1_ANARXSIGDET_RESERVED0_ALIGN 0 7217 #define PHY84328_DEV1_ANARXSIGDET_RESERVED0_BITS 2 7218 #define PHY84328_DEV1_ANARXSIGDET_RESERVED0_SHIFT 0 7219 7220 7221 /**************************************************************************** 7222 * ln_device1 :: anaRxAControl4 7223 */ 7224 /* ln_device1 :: anaRxAControl4 :: low_latency_mode [15:15] */ 7225 #define PHY84328_DEV1_ANARXACONTROL4_LOW_LATENCY_MODE_MASK 0x8000 7226 #define PHY84328_DEV1_ANARXACONTROL4_LOW_LATENCY_MODE_ALIGN 0 7227 #define PHY84328_DEV1_ANARXACONTROL4_LOW_LATENCY_MODE_BITS 1 7228 #define PHY84328_DEV1_ANARXACONTROL4_LOW_LATENCY_MODE_SHIFT 15 7229 7230 /* ln_device1 :: anaRxAControl4 :: fastacq_pf [14:14] */ 7231 #define PHY84328_DEV1_ANARXACONTROL4_FASTACQ_PF_MASK 0x4000 7232 #define PHY84328_DEV1_ANARXACONTROL4_FASTACQ_PF_ALIGN 0 7233 #define PHY84328_DEV1_ANARXACONTROL4_FASTACQ_PF_BITS 1 7234 #define PHY84328_DEV1_ANARXACONTROL4_FASTACQ_PF_SHIFT 14 7235 7236 /* ln_device1 :: anaRxAControl4 :: i1p25dfe [13:13] */ 7237 #define PHY84328_DEV1_ANARXACONTROL4_I1P25DFE_MASK 0x2000 7238 #define PHY84328_DEV1_ANARXACONTROL4_I1P25DFE_ALIGN 0 7239 #define PHY84328_DEV1_ANARXACONTROL4_I1P25DFE_BITS 1 7240 #define PHY84328_DEV1_ANARXACONTROL4_I1P25DFE_SHIFT 13 7241 7242 /* ln_device1 :: anaRxAControl4 :: i4deadzone [12:12] */ 7243 #define PHY84328_DEV1_ANARXACONTROL4_I4DEADZONE_MASK 0x1000 7244 #define PHY84328_DEV1_ANARXACONTROL4_I4DEADZONE_ALIGN 0 7245 #define PHY84328_DEV1_ANARXACONTROL4_I4DEADZONE_BITS 1 7246 #define PHY84328_DEV1_ANARXACONTROL4_I4DEADZONE_SHIFT 12 7247 7248 /* ln_device1 :: anaRxAControl4 :: imax_sigdet [11:11] */ 7249 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_SIGDET_MASK 0x0800 7250 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_SIGDET_ALIGN 0 7251 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_SIGDET_BITS 1 7252 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_SIGDET_SHIFT 11 7253 7254 /* ln_device1 :: anaRxAControl4 :: imode_sigdet [10:10] */ 7255 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_SIGDET_MASK 0x0400 7256 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_SIGDET_ALIGN 0 7257 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_SIGDET_BITS 1 7258 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_SIGDET_SHIFT 10 7259 7260 /* ln_device1 :: anaRxAControl4 :: imin_sigdet [09:09] */ 7261 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_SIGDET_MASK 0x0200 7262 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_SIGDET_ALIGN 0 7263 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_SIGDET_BITS 1 7264 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_SIGDET_SHIFT 9 7265 7266 /* ln_device1 :: anaRxAControl4 :: imax_yp_eyediag [08:08] */ 7267 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_YP_EYEDIAG_MASK 0x0100 7268 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_YP_EYEDIAG_ALIGN 0 7269 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_YP_EYEDIAG_BITS 1 7270 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_YP_EYEDIAG_SHIFT 8 7271 7272 /* ln_device1 :: anaRxAControl4 :: imode_yp_eyediag [07:07] */ 7273 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_YP_EYEDIAG_MASK 0x0080 7274 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_YP_EYEDIAG_ALIGN 0 7275 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_YP_EYEDIAG_BITS 1 7276 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_YP_EYEDIAG_SHIFT 7 7277 7278 /* ln_device1 :: anaRxAControl4 :: imin_yp_eyediag [06:06] */ 7279 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_YP_EYEDIAG_MASK 0x0040 7280 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_YP_EYEDIAG_ALIGN 0 7281 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_YP_EYEDIAG_BITS 1 7282 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_YP_EYEDIAG_SHIFT 6 7283 7284 /* ln_device1 :: anaRxAControl4 :: imax_interp [05:05] */ 7285 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_INTERP_MASK 0x0020 7286 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_INTERP_ALIGN 0 7287 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_INTERP_BITS 1 7288 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_INTERP_SHIFT 5 7289 7290 /* ln_device1 :: anaRxAControl4 :: imode_interp [04:04] */ 7291 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_INTERP_MASK 0x0010 7292 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_INTERP_ALIGN 0 7293 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_INTERP_BITS 1 7294 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_INTERP_SHIFT 4 7295 7296 /* ln_device1 :: anaRxAControl4 :: imin_interp [03:03] */ 7297 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_INTERP_MASK 0x0008 7298 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_INTERP_ALIGN 0 7299 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_INTERP_BITS 1 7300 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_INTERP_SHIFT 3 7301 7302 /* ln_device1 :: anaRxAControl4 :: imax_pf [02:02] */ 7303 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_PF_MASK 0x0004 7304 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_PF_ALIGN 0 7305 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_PF_BITS 1 7306 #define PHY84328_DEV1_ANARXACONTROL4_IMAX_PF_SHIFT 2 7307 7308 /* ln_device1 :: anaRxAControl4 :: imode_pf [01:01] */ 7309 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_PF_MASK 0x0002 7310 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_PF_ALIGN 0 7311 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_PF_BITS 1 7312 #define PHY84328_DEV1_ANARXACONTROL4_IMODE_PF_SHIFT 1 7313 7314 /* ln_device1 :: anaRxAControl4 :: imin_pf [00:00] */ 7315 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_PF_MASK 0x0001 7316 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_PF_ALIGN 0 7317 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_PF_BITS 1 7318 #define PHY84328_DEV1_ANARXACONTROL4_IMIN_PF_SHIFT 0 7319 7320 7321 /**************************************************************************** 7322 * ln_device1 :: anaRxControl2 7323 */ 7324 /* ln_device1 :: anaRxControl2 :: reserved0 [15:15] */ 7325 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED0_MASK 0x8000 7326 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED0_ALIGN 0 7327 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED0_BITS 1 7328 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED0_SHIFT 15 7329 7330 /* ln_device1 :: anaRxControl2 :: rx_prbs_w_val [14:14] */ 7331 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_W_VAL_MASK 0x4000 7332 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_W_VAL_ALIGN 0 7333 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_W_VAL_BITS 1 7334 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_W_VAL_SHIFT 14 7335 7336 /* ln_device1 :: anaRxControl2 :: rx_prbs_w_force [13:13] */ 7337 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_W_FORCE_MASK 0x2000 7338 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_W_FORCE_ALIGN 0 7339 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_W_FORCE_BITS 1 7340 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_W_FORCE_SHIFT 13 7341 7342 /* ln_device1 :: anaRxControl2 :: rx_prbs_bswap [12:12] */ 7343 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_BSWAP_MASK 0x1000 7344 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_BSWAP_ALIGN 0 7345 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_BSWAP_BITS 1 7346 #define PHY84328_DEV1_ANARXCONTROL2_RX_PRBS_BSWAP_SHIFT 12 7347 7348 /* ln_device1 :: anaRxControl2 :: rx_bitswap [11:11] */ 7349 #define PHY84328_DEV1_ANARXCONTROL2_RX_BITSWAP_MASK 0x0800 7350 #define PHY84328_DEV1_ANARXCONTROL2_RX_BITSWAP_ALIGN 0 7351 #define PHY84328_DEV1_ANARXCONTROL2_RX_BITSWAP_BITS 1 7352 #define PHY84328_DEV1_ANARXCONTROL2_RX_BITSWAP_SHIFT 11 7353 7354 /* ln_device1 :: anaRxControl2 :: rst_rx_r [10:10] */ 7355 #define PHY84328_DEV1_ANARXCONTROL2_RST_RX_R_MASK 0x0400 7356 #define PHY84328_DEV1_ANARXCONTROL2_RST_RX_R_ALIGN 0 7357 #define PHY84328_DEV1_ANARXCONTROL2_RST_RX_R_BITS 1 7358 #define PHY84328_DEV1_ANARXCONTROL2_RST_RX_R_SHIFT 10 7359 7360 /* ln_device1 :: anaRxControl2 :: pwdwn_rx_r [09:09] */ 7361 #define PHY84328_DEV1_ANARXCONTROL2_PWDWN_RX_R_MASK 0x0200 7362 #define PHY84328_DEV1_ANARXCONTROL2_PWDWN_RX_R_ALIGN 0 7363 #define PHY84328_DEV1_ANARXCONTROL2_PWDWN_RX_R_BITS 1 7364 #define PHY84328_DEV1_ANARXCONTROL2_PWDWN_RX_R_SHIFT 9 7365 7366 /* ln_device1 :: anaRxControl2 :: prbs_order_rx_r_2 [08:08] */ 7367 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_2_MASK 0x0100 7368 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_2_ALIGN 0 7369 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_2_BITS 1 7370 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_2_SHIFT 8 7371 7372 /* ln_device1 :: anaRxControl2 :: reserved1 [07:07] */ 7373 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED1_MASK 0x0080 7374 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED1_ALIGN 0 7375 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED1_BITS 1 7376 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED1_SHIFT 7 7377 7378 /* ln_device1 :: anaRxControl2 :: prbs_sel_rx_r [06:06] */ 7379 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_SEL_RX_R_MASK 0x0040 7380 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_SEL_RX_R_ALIGN 0 7381 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_SEL_RX_R_BITS 1 7382 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_SEL_RX_R_SHIFT 6 7383 7384 /* ln_device1 :: anaRxControl2 :: prbs_en_rx_r [05:05] */ 7385 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_EN_RX_R_MASK 0x0020 7386 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_EN_RX_R_ALIGN 0 7387 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_EN_RX_R_BITS 1 7388 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_EN_RX_R_SHIFT 5 7389 7390 /* ln_device1 :: anaRxControl2 :: prbs_inv_rx_r [04:04] */ 7391 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_INV_RX_R_MASK 0x0010 7392 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_INV_RX_R_ALIGN 0 7393 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_INV_RX_R_BITS 1 7394 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_INV_RX_R_SHIFT 4 7395 7396 /* ln_device1 :: anaRxControl2 :: prbs_order_rx_r [03:02] */ 7397 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_MASK 0x000c 7398 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_ALIGN 0 7399 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_BITS 2 7400 #define PHY84328_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_SHIFT 2 7401 7402 /* ln_device1 :: anaRxControl2 :: reserved2 [01:01] */ 7403 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED2_MASK 0x0002 7404 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED2_ALIGN 0 7405 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED2_BITS 1 7406 #define PHY84328_DEV1_ANARXCONTROL2_RESERVED2_SHIFT 1 7407 7408 /* ln_device1 :: anaRxControl2 :: errcnt_15 [00:00] */ 7409 #define PHY84328_DEV1_ANARXCONTROL2_ERRCNT_15_MASK 0x0001 7410 #define PHY84328_DEV1_ANARXCONTROL2_ERRCNT_15_ALIGN 0 7411 #define PHY84328_DEV1_ANARXCONTROL2_ERRCNT_15_BITS 1 7412 #define PHY84328_DEV1_ANARXCONTROL2_ERRCNT_15_SHIFT 0 7413 7414 7415 /**************************************************************************** 7416 * ln_device1 :: anaRxControl1 7417 */ 7418 /* ln_device1 :: anaRxControl1 :: fpat_md [15:15] */ 7419 #define PHY84328_DEV1_ANARXCONTROL1_FPAT_MD_MASK 0x8000 7420 #define PHY84328_DEV1_ANARXCONTROL1_FPAT_MD_ALIGN 0 7421 #define PHY84328_DEV1_ANARXCONTROL1_FPAT_MD_BITS 1 7422 #define PHY84328_DEV1_ANARXCONTROL1_FPAT_MD_SHIFT 15 7423 7424 /* ln_device1 :: anaRxControl1 :: pkt_count_en [14:14] */ 7425 #define PHY84328_DEV1_ANARXCONTROL1_PKT_COUNT_EN_MASK 0x4000 7426 #define PHY84328_DEV1_ANARXCONTROL1_PKT_COUNT_EN_ALIGN 0 7427 #define PHY84328_DEV1_ANARXCONTROL1_PKT_COUNT_EN_BITS 1 7428 #define PHY84328_DEV1_ANARXCONTROL1_PKT_COUNT_EN_SHIFT 14 7429 7430 /* ln_device1 :: anaRxControl1 :: staMuxRegDis [13:13] */ 7431 #define PHY84328_DEV1_ANARXCONTROL1_STAMUXREGDIS_MASK 0x2000 7432 #define PHY84328_DEV1_ANARXCONTROL1_STAMUXREGDIS_ALIGN 0 7433 #define PHY84328_DEV1_ANARXCONTROL1_STAMUXREGDIS_BITS 1 7434 #define PHY84328_DEV1_ANARXCONTROL1_STAMUXREGDIS_SHIFT 13 7435 7436 /* ln_device1 :: anaRxControl1 :: prbs_clr_dis [12:12] */ 7437 #define PHY84328_DEV1_ANARXCONTROL1_PRBS_CLR_DIS_MASK 0x1000 7438 #define PHY84328_DEV1_ANARXCONTROL1_PRBS_CLR_DIS_ALIGN 0 7439 #define PHY84328_DEV1_ANARXCONTROL1_PRBS_CLR_DIS_BITS 1 7440 #define PHY84328_DEV1_ANARXCONTROL1_PRBS_CLR_DIS_SHIFT 12 7441 7442 /* ln_device1 :: anaRxControl1 :: rxd_dec_sel [11:11] */ 7443 #define PHY84328_DEV1_ANARXCONTROL1_RXD_DEC_SEL_MASK 0x0800 7444 #define PHY84328_DEV1_ANARXCONTROL1_RXD_DEC_SEL_ALIGN 0 7445 #define PHY84328_DEV1_ANARXCONTROL1_RXD_DEC_SEL_BITS 1 7446 #define PHY84328_DEV1_ANARXCONTROL1_RXD_DEC_SEL_SHIFT 11 7447 7448 /* ln_device1 :: anaRxControl1 :: cgbad_tst [10:10] */ 7449 #define PHY84328_DEV1_ANARXCONTROL1_CGBAD_TST_MASK 0x0400 7450 #define PHY84328_DEV1_ANARXCONTROL1_CGBAD_TST_ALIGN 0 7451 #define PHY84328_DEV1_ANARXCONTROL1_CGBAD_TST_BITS 1 7452 #define PHY84328_DEV1_ANARXCONTROL1_CGBAD_TST_SHIFT 10 7453 7454 /* ln_device1 :: anaRxControl1 :: Emon_en [09:09] */ 7455 #define PHY84328_DEV1_ANARXCONTROL1_EMON_EN_MASK 0x0200 7456 #define PHY84328_DEV1_ANARXCONTROL1_EMON_EN_ALIGN 0 7457 #define PHY84328_DEV1_ANARXCONTROL1_EMON_EN_BITS 1 7458 #define PHY84328_DEV1_ANARXCONTROL1_EMON_EN_SHIFT 9 7459 7460 /* ln_device1 :: anaRxControl1 :: prbs_en [08:08] */ 7461 #define PHY84328_DEV1_ANARXCONTROL1_PRBS_EN_MASK 0x0100 7462 #define PHY84328_DEV1_ANARXCONTROL1_PRBS_EN_ALIGN 0 7463 #define PHY84328_DEV1_ANARXCONTROL1_PRBS_EN_BITS 1 7464 #define PHY84328_DEV1_ANARXCONTROL1_PRBS_EN_SHIFT 8 7465 7466 /* ln_device1 :: anaRxControl1 :: cgbad_en [07:07] */ 7467 #define PHY84328_DEV1_ANARXCONTROL1_CGBAD_EN_MASK 0x0080 7468 #define PHY84328_DEV1_ANARXCONTROL1_CGBAD_EN_ALIGN 0 7469 #define PHY84328_DEV1_ANARXCONTROL1_CGBAD_EN_BITS 1 7470 #define PHY84328_DEV1_ANARXCONTROL1_CGBAD_EN_SHIFT 7 7471 7472 /* ln_device1 :: anaRxControl1 :: cstretch [06:06] */ 7473 #define PHY84328_DEV1_ANARXCONTROL1_CSTRETCH_MASK 0x0040 7474 #define PHY84328_DEV1_ANARXCONTROL1_CSTRETCH_ALIGN 0 7475 #define PHY84328_DEV1_ANARXCONTROL1_CSTRETCH_BITS 1 7476 #define PHY84328_DEV1_ANARXCONTROL1_CSTRETCH_SHIFT 6 7477 7478 /* ln_device1 :: anaRxControl1 :: comma_low_byte_SM [05:05] */ 7479 #define PHY84328_DEV1_ANARXCONTROL1_COMMA_LOW_BYTE_SM_MASK 0x0020 7480 #define PHY84328_DEV1_ANARXCONTROL1_COMMA_LOW_BYTE_SM_ALIGN 0 7481 #define PHY84328_DEV1_ANARXCONTROL1_COMMA_LOW_BYTE_SM_BITS 1 7482 #define PHY84328_DEV1_ANARXCONTROL1_COMMA_LOW_BYTE_SM_SHIFT 5 7483 7484 /* ln_device1 :: anaRxControl1 :: comma_byte_adj_en_SM [04:04] */ 7485 #define PHY84328_DEV1_ANARXCONTROL1_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 7486 #define PHY84328_DEV1_ANARXCONTROL1_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 7487 #define PHY84328_DEV1_ANARXCONTROL1_COMMA_BYTE_ADJ_EN_SM_BITS 1 7488 #define PHY84328_DEV1_ANARXCONTROL1_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 7489 7490 /* ln_device1 :: anaRxControl1 :: reserved0 [03:02] */ 7491 #define PHY84328_DEV1_ANARXCONTROL1_RESERVED0_MASK 0x000c 7492 #define PHY84328_DEV1_ANARXCONTROL1_RESERVED0_ALIGN 0 7493 #define PHY84328_DEV1_ANARXCONTROL1_RESERVED0_BITS 2 7494 #define PHY84328_DEV1_ANARXCONTROL1_RESERVED0_SHIFT 2 7495 7496 /* ln_device1 :: anaRxControl1 :: freq_sel_force [01:01] */ 7497 #define PHY84328_DEV1_ANARXCONTROL1_FREQ_SEL_FORCE_MASK 0x0002 7498 #define PHY84328_DEV1_ANARXCONTROL1_FREQ_SEL_FORCE_ALIGN 0 7499 #define PHY84328_DEV1_ANARXCONTROL1_FREQ_SEL_FORCE_BITS 1 7500 #define PHY84328_DEV1_ANARXCONTROL1_FREQ_SEL_FORCE_SHIFT 1 7501 7502 /* ln_device1 :: anaRxControl1 :: freq_sel [00:00] */ 7503 #define PHY84328_DEV1_ANARXCONTROL1_FREQ_SEL_MASK 0x0001 7504 #define PHY84328_DEV1_ANARXCONTROL1_FREQ_SEL_ALIGN 0 7505 #define PHY84328_DEV1_ANARXCONTROL1_FREQ_SEL_BITS 1 7506 #define PHY84328_DEV1_ANARXCONTROL1_FREQ_SEL_SHIFT 0 7507 7508 7509 /**************************************************************************** 7510 * ln_device1 :: anaRxAControl1 7511 */ 7512 /* ln_device1 :: anaRxAControl1 :: imode_cmd [15:15] */ 7513 #define PHY84328_DEV1_ANARXACONTROL1_IMODE_CMD_MASK 0x8000 7514 #define PHY84328_DEV1_ANARXACONTROL1_IMODE_CMD_ALIGN 0 7515 #define PHY84328_DEV1_ANARXACONTROL1_IMODE_CMD_BITS 1 7516 #define PHY84328_DEV1_ANARXACONTROL1_IMODE_CMD_SHIFT 15 7517 7518 /* ln_device1 :: anaRxAControl1 :: imin_cmd [14:14] */ 7519 #define PHY84328_DEV1_ANARXACONTROL1_IMIN_CMD_MASK 0x4000 7520 #define PHY84328_DEV1_ANARXACONTROL1_IMIN_CMD_ALIGN 0 7521 #define PHY84328_DEV1_ANARXACONTROL1_IMIN_CMD_BITS 1 7522 #define PHY84328_DEV1_ANARXACONTROL1_IMIN_CMD_SHIFT 14 7523 7524 /* ln_device1 :: anaRxAControl1 :: en_10gmode [13:13] */ 7525 #define PHY84328_DEV1_ANARXACONTROL1_EN_10GMODE_MASK 0x2000 7526 #define PHY84328_DEV1_ANARXACONTROL1_EN_10GMODE_ALIGN 0 7527 #define PHY84328_DEV1_ANARXACONTROL1_EN_10GMODE_BITS 1 7528 #define PHY84328_DEV1_ANARXACONTROL1_EN_10GMODE_SHIFT 13 7529 7530 /* ln_device1 :: anaRxAControl1 :: dc_mode [12:12] */ 7531 #define PHY84328_DEV1_ANARXACONTROL1_DC_MODE_MASK 0x1000 7532 #define PHY84328_DEV1_ANARXACONTROL1_DC_MODE_ALIGN 0 7533 #define PHY84328_DEV1_ANARXACONTROL1_DC_MODE_BITS 1 7534 #define PHY84328_DEV1_ANARXACONTROL1_DC_MODE_SHIFT 12 7535 7536 /* ln_device1 :: anaRxAControl1 :: vga_bw_extension [11:11] */ 7537 #define PHY84328_DEV1_ANARXACONTROL1_VGA_BW_EXTENSION_MASK 0x0800 7538 #define PHY84328_DEV1_ANARXACONTROL1_VGA_BW_EXTENSION_ALIGN 0 7539 #define PHY84328_DEV1_ANARXACONTROL1_VGA_BW_EXTENSION_BITS 1 7540 #define PHY84328_DEV1_ANARXACONTROL1_VGA_BW_EXTENSION_SHIFT 11 7541 7542 /* ln_device1 :: anaRxAControl1 :: refh_rx [10:10] */ 7543 #define PHY84328_DEV1_ANARXACONTROL1_REFH_RX_MASK 0x0400 7544 #define PHY84328_DEV1_ANARXACONTROL1_REFH_RX_ALIGN 0 7545 #define PHY84328_DEV1_ANARXACONTROL1_REFH_RX_BITS 1 7546 #define PHY84328_DEV1_ANARXACONTROL1_REFH_RX_SHIFT 10 7547 7548 /* ln_device1 :: anaRxAControl1 :: refl_rx [09:09] */ 7549 #define PHY84328_DEV1_ANARXACONTROL1_REFL_RX_MASK 0x0200 7550 #define PHY84328_DEV1_ANARXACONTROL1_REFL_RX_ALIGN 0 7551 #define PHY84328_DEV1_ANARXACONTROL1_REFL_RX_BITS 1 7552 #define PHY84328_DEV1_ANARXACONTROL1_REFL_RX_SHIFT 9 7553 7554 /* ln_device1 :: anaRxAControl1 :: tport_en [08:08] */ 7555 #define PHY84328_DEV1_ANARXACONTROL1_TPORT_EN_MASK 0x0100 7556 #define PHY84328_DEV1_ANARXACONTROL1_TPORT_EN_ALIGN 0 7557 #define PHY84328_DEV1_ANARXACONTROL1_TPORT_EN_BITS 1 7558 #define PHY84328_DEV1_ANARXACONTROL1_TPORT_EN_SHIFT 8 7559 7560 /* ln_device1 :: anaRxAControl1 :: vddrb_bgb [07:07] */ 7561 #define PHY84328_DEV1_ANARXACONTROL1_VDDRB_BGB_MASK 0x0080 7562 #define PHY84328_DEV1_ANARXACONTROL1_VDDRB_BGB_ALIGN 0 7563 #define PHY84328_DEV1_ANARXACONTROL1_VDDRB_BGB_BITS 1 7564 #define PHY84328_DEV1_ANARXACONTROL1_VDDRB_BGB_SHIFT 7 7565 7566 /* ln_device1 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 7567 #define PHY84328_DEV1_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 7568 #define PHY84328_DEV1_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 7569 #define PHY84328_DEV1_ANARXACONTROL1_SIG_PWRDN_BITS 1 7570 #define PHY84328_DEV1_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 7571 7572 /* ln_device1 :: anaRxAControl1 :: offset_ctrl [05:03] */ 7573 #define PHY84328_DEV1_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 7574 #define PHY84328_DEV1_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 7575 #define PHY84328_DEV1_ANARXACONTROL1_OFFSET_CTRL_BITS 3 7576 #define PHY84328_DEV1_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 7577 7578 /* ln_device1 :: anaRxAControl1 :: offset_sel [02:02] */ 7579 #define PHY84328_DEV1_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 7580 #define PHY84328_DEV1_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 7581 #define PHY84328_DEV1_ANARXACONTROL1_OFFSET_SEL_BITS 1 7582 #define PHY84328_DEV1_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 7583 7584 /* ln_device1 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */ 7585 #define PHY84328_DEV1_ANARXACONTROL1_SEL_DFECKDELAY1_MASK 0x0002 7586 #define PHY84328_DEV1_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN 0 7587 #define PHY84328_DEV1_ANARXACONTROL1_SEL_DFECKDELAY1_BITS 1 7588 #define PHY84328_DEV1_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT 1 7589 7590 /* ln_device1 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */ 7591 #define PHY84328_DEV1_ANARXACONTROL1_SEL_DFECKDELAY0_MASK 0x0001 7592 #define PHY84328_DEV1_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN 0 7593 #define PHY84328_DEV1_ANARXACONTROL1_SEL_DFECKDELAY0_BITS 1 7594 #define PHY84328_DEV1_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT 0 7595 7596 7597 /**************************************************************************** 7598 * ln_device1 :: anaRxAControl2 7599 */ 7600 /* ln_device1 :: anaRxAControl2 :: imax_ctat [15:15] */ 7601 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_CTAT_MASK 0x8000 7602 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_CTAT_ALIGN 0 7603 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_CTAT_BITS 1 7604 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_CTAT_SHIFT 15 7605 7606 /* ln_device1 :: anaRxAControl2 :: imode_ctat [14:14] */ 7607 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_CTAT_MASK 0x4000 7608 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_CTAT_ALIGN 0 7609 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_CTAT_BITS 1 7610 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_CTAT_SHIFT 14 7611 7612 /* ln_device1 :: anaRxAControl2 :: imin_ctat [13:13] */ 7613 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_CTAT_MASK 0x2000 7614 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_CTAT_ALIGN 0 7615 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_CTAT_BITS 1 7616 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_CTAT_SHIFT 13 7617 7618 /* ln_device1 :: anaRxAControl2 :: imax_peaking [12:12] */ 7619 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_PEAKING_MASK 0x1000 7620 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_PEAKING_ALIGN 0 7621 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_PEAKING_BITS 1 7622 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_PEAKING_SHIFT 12 7623 7624 /* ln_device1 :: anaRxAControl2 :: imode_peaking [11:11] */ 7625 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_PEAKING_MASK 0x0800 7626 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_PEAKING_ALIGN 0 7627 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_PEAKING_BITS 1 7628 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_PEAKING_SHIFT 11 7629 7630 /* ln_device1 :: anaRxAControl2 :: imin_peaking [10:10] */ 7631 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_PEAKING_MASK 0x0400 7632 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_PEAKING_ALIGN 0 7633 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_PEAKING_BITS 1 7634 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_PEAKING_SHIFT 10 7635 7636 /* ln_device1 :: anaRxAControl2 :: imax_dfesum [09:09] */ 7637 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 7638 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 7639 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_DFESUM_BITS 1 7640 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 7641 7642 /* ln_device1 :: anaRxAControl2 :: imode_dfesum [08:08] */ 7643 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 7644 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 7645 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_DFESUM_BITS 1 7646 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 7647 7648 /* ln_device1 :: anaRxAControl2 :: imin_dfesum [07:07] */ 7649 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 7650 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 7651 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_DFESUM_BITS 1 7652 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 7653 7654 /* ln_device1 :: anaRxAControl2 :: imax_vga [06:06] */ 7655 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 7656 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_VGA_ALIGN 0 7657 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_VGA_BITS 1 7658 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_VGA_SHIFT 6 7659 7660 /* ln_device1 :: anaRxAControl2 :: imode_vga [05:05] */ 7661 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 7662 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_VGA_ALIGN 0 7663 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_VGA_BITS 1 7664 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_VGA_SHIFT 5 7665 7666 /* ln_device1 :: anaRxAControl2 :: imin_vga [04:04] */ 7667 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 7668 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_VGA_ALIGN 0 7669 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_VGA_BITS 1 7670 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_VGA_SHIFT 4 7671 7672 /* ln_device1 :: anaRxAControl2 :: imax_interp [03:03] */ 7673 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 7674 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 7675 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_INTERP_BITS 1 7676 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 7677 7678 /* ln_device1 :: anaRxAControl2 :: imode_interp [02:02] */ 7679 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 7680 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 7681 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_INTERP_BITS 1 7682 #define PHY84328_DEV1_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 7683 7684 /* ln_device1 :: anaRxAControl2 :: imin_interp [01:01] */ 7685 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 7686 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 7687 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_INTERP_BITS 1 7688 #define PHY84328_DEV1_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 7689 7690 /* ln_device1 :: anaRxAControl2 :: imax_cmd [00:00] */ 7691 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_CMD_MASK 0x0001 7692 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_CMD_ALIGN 0 7693 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_CMD_BITS 1 7694 #define PHY84328_DEV1_ANARXACONTROL2_IMAX_CMD_SHIFT 0 7695 7696 7697 /**************************************************************************** 7698 * ln_device1 :: anaRxAControl3 7699 */ 7700 /* ln_device1 :: anaRxAControl3 :: en_clk16 [15:15] */ 7701 #define PHY84328_DEV1_ANARXACONTROL3_EN_CLK16_MASK 0x8000 7702 #define PHY84328_DEV1_ANARXACONTROL3_EN_CLK16_ALIGN 0 7703 #define PHY84328_DEV1_ANARXACONTROL3_EN_CLK16_BITS 1 7704 #define PHY84328_DEV1_ANARXACONTROL3_EN_CLK16_SHIFT 15 7705 7706 /* ln_device1 :: anaRxAControl3 :: en_clk33 [14:14] */ 7707 #define PHY84328_DEV1_ANARXACONTROL3_EN_CLK33_MASK 0x4000 7708 #define PHY84328_DEV1_ANARXACONTROL3_EN_CLK33_ALIGN 0 7709 #define PHY84328_DEV1_ANARXACONTROL3_EN_CLK33_BITS 1 7710 #define PHY84328_DEV1_ANARXACONTROL3_EN_CLK33_SHIFT 14 7711 7712 /* ln_device1 :: anaRxAControl3 :: en_vcctrl [13:13] */ 7713 #define PHY84328_DEV1_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 7714 #define PHY84328_DEV1_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 7715 #define PHY84328_DEV1_ANARXACONTROL3_EN_VCCTRL_BITS 1 7716 #define PHY84328_DEV1_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 7717 7718 /* ln_device1 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */ 7719 #define PHY84328_DEV1_ANARXACONTROL3_SEL_TH4DFE1_MASK 0x1000 7720 #define PHY84328_DEV1_ANARXACONTROL3_SEL_TH4DFE1_ALIGN 0 7721 #define PHY84328_DEV1_ANARXACONTROL3_SEL_TH4DFE1_BITS 1 7722 #define PHY84328_DEV1_ANARXACONTROL3_SEL_TH4DFE1_SHIFT 12 7723 7724 /* ln_device1 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */ 7725 #define PHY84328_DEV1_ANARXACONTROL3_SEL_TH4DFE0_MASK 0x0800 7726 #define PHY84328_DEV1_ANARXACONTROL3_SEL_TH4DFE0_ALIGN 0 7727 #define PHY84328_DEV1_ANARXACONTROL3_SEL_TH4DFE0_BITS 1 7728 #define PHY84328_DEV1_ANARXACONTROL3_SEL_TH4DFE0_SHIFT 11 7729 7730 /* ln_device1 :: anaRxAControl3 :: selugbw1 [10:10] */ 7731 #define PHY84328_DEV1_ANARXACONTROL3_SELUGBW1_MASK 0x0400 7732 #define PHY84328_DEV1_ANARXACONTROL3_SELUGBW1_ALIGN 0 7733 #define PHY84328_DEV1_ANARXACONTROL3_SELUGBW1_BITS 1 7734 #define PHY84328_DEV1_ANARXACONTROL3_SELUGBW1_SHIFT 10 7735 7736 /* ln_device1 :: anaRxAControl3 :: selugbw0 [09:09] */ 7737 #define PHY84328_DEV1_ANARXACONTROL3_SELUGBW0_MASK 0x0200 7738 #define PHY84328_DEV1_ANARXACONTROL3_SELUGBW0_ALIGN 0 7739 #define PHY84328_DEV1_ANARXACONTROL3_SELUGBW0_BITS 1 7740 #define PHY84328_DEV1_ANARXACONTROL3_SELUGBW0_SHIFT 9 7741 7742 /* ln_device1 :: anaRxAControl3 :: imax_dfetap [08:08] */ 7743 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 7744 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 7745 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_DFETAP_BITS 1 7746 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 7747 7748 /* ln_device1 :: anaRxAControl3 :: imode_dfetap [07:07] */ 7749 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 7750 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 7751 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_DFETAP_BITS 1 7752 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 7753 7754 /* ln_device1 :: anaRxAControl3 :: imin_dfetap [06:06] */ 7755 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 7756 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 7757 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_DFETAP_BITS 1 7758 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 7759 7760 /* ln_device1 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 7761 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 7762 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 7763 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 7764 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 7765 7766 /* ln_device1 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 7767 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 7768 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 7769 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 7770 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 7771 7772 /* ln_device1 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 7773 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 7774 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 7775 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 7776 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 7777 7778 /* ln_device1 :: anaRxAControl3 :: imax_dfevref [02:02] */ 7779 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 7780 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 7781 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 7782 #define PHY84328_DEV1_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 7783 7784 /* ln_device1 :: anaRxAControl3 :: imode_dfevref [01:01] */ 7785 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 7786 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 7787 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 7788 #define PHY84328_DEV1_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 7789 7790 /* ln_device1 :: anaRxAControl3 :: imin_dfevref [00:00] */ 7791 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 7792 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 7793 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 7794 #define PHY84328_DEV1_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 7795 7796 7797 /**************************************************************************** 7798 * ln_device1_QSFI_TXPI_registers 7799 */ 7800 /**************************************************************************** 7801 * ln_device1 :: tx_pi_control1 7802 */ 7803 /* ln_device1 :: tx_pi_control1 :: tx_pi_integ_sat_sel [15:15] */ 7804 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_MASK 0x8000 7805 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_ALIGN 0 7806 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_BITS 1 7807 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_SHIFT 15 7808 7809 /* ln_device1 :: tx_pi_control1 :: tx_pi_integ_sat_1_or_2 [14:14] */ 7810 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_MASK 0x4000 7811 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_ALIGN 0 7812 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_BITS 1 7813 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_SHIFT 14 7814 7815 /* ln_device1 :: tx_pi_control1 :: tx_pi_phase_invert [13:13] */ 7816 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_MASK 0x2000 7817 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_ALIGN 0 7818 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_BITS 1 7819 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_SHIFT 13 7820 7821 /* ln_device1 :: tx_pi_control1 :: tx_pi_phase_step_mult [12:12] */ 7822 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_MASK 0x1000 7823 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_ALIGN 0 7824 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_BITS 1 7825 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_SHIFT 12 7826 7827 /* ln_device1 :: tx_pi_control1 :: tx_pi_phase_step_dir [11:11] */ 7828 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_MASK 0x0800 7829 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_ALIGN 0 7830 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_BITS 1 7831 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_SHIFT 11 7832 7833 /* ln_device1 :: tx_pi_control1 :: tx_pi_phase_step [10:09] */ 7834 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MASK 0x0600 7835 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_ALIGN 0 7836 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_BITS 2 7837 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_SHIFT 9 7838 7839 /* ln_device1 :: tx_pi_control1 :: tx_pi_phase_delta [08:04] */ 7840 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_MASK 0x01f0 7841 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_ALIGN 0 7842 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_BITS 5 7843 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_SHIFT 4 7844 7845 /* ln_device1 :: tx_pi_control1 :: tx_pi_phase_strobe [03:03] */ 7846 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_MASK 0x0008 7847 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_ALIGN 0 7848 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_BITS 1 7849 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_SHIFT 3 7850 7851 /* ln_device1 :: tx_pi_control1 :: tx_pi_phase_override [02:02] */ 7852 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_MASK 0x0004 7853 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_ALIGN 0 7854 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_BITS 1 7855 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_SHIFT 2 7856 7857 /* ln_device1 :: tx_pi_control1 :: tx_pi_bypass_mode [01:01] */ 7858 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_MASK 0x0002 7859 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_ALIGN 0 7860 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_BITS 1 7861 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_SHIFT 1 7862 7863 /* ln_device1 :: tx_pi_control1 :: tx_pi_en [00:00] */ 7864 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_EN_MASK 0x0001 7865 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_EN_ALIGN 0 7866 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_EN_BITS 1 7867 #define PHY84328_DEV1_TX_PI_CONTROL1_TX_PI_EN_SHIFT 0 7868 7869 7870 /**************************************************************************** 7871 * ln_device1 :: tx_pi_control2 7872 */ 7873 /* ln_device1 :: tx_pi_control2 :: tx_pi_sm_timer_sel [15:14] */ 7874 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_MASK 0xc000 7875 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_ALIGN 0 7876 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_BITS 2 7877 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_SHIFT 14 7878 7879 /* ln_device1 :: tx_pi_control2 :: tx_pi_sm_done_override [13:13] */ 7880 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_MASK 0x2000 7881 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_ALIGN 0 7882 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_BITS 1 7883 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_SHIFT 13 7884 7885 /* ln_device1 :: tx_pi_control2 :: tx_pi_sm_en_override [12:12] */ 7886 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_MASK 0x1000 7887 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_ALIGN 0 7888 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_BITS 1 7889 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_SHIFT 12 7890 7891 /* ln_device1 :: tx_pi_control2 :: reserved0 [11:08] */ 7892 #define PHY84328_DEV1_TX_PI_CONTROL2_RESERVED0_MASK 0x0f00 7893 #define PHY84328_DEV1_TX_PI_CONTROL2_RESERVED0_ALIGN 0 7894 #define PHY84328_DEV1_TX_PI_CONTROL2_RESERVED0_BITS 4 7895 #define PHY84328_DEV1_TX_PI_CONTROL2_RESERVED0_SHIFT 8 7896 7897 /* ln_device1 :: tx_pi_control2 :: tx_pi_loopback_mode [07:07] */ 7898 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_MASK 0x0080 7899 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_ALIGN 0 7900 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_BITS 1 7901 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_SHIFT 7 7902 7903 /* ln_device1 :: tx_pi_control2 :: tx_pi_sm_bypass [06:06] */ 7904 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_BYPASS_MASK 0x0040 7905 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_BYPASS_ALIGN 0 7906 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_BYPASS_BITS 1 7907 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_SM_BYPASS_SHIFT 6 7908 7909 /* ln_device1 :: tx_pi_control2 :: tx_pi_integ_reg_clr [05:05] */ 7910 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_MASK 0x0020 7911 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_ALIGN 0 7912 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_BITS 1 7913 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_SHIFT 5 7914 7915 /* ln_device1 :: tx_pi_control2 :: tx_pi_bwsel_integ [04:02] */ 7916 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_MASK 0x001c 7917 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_ALIGN 0 7918 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_BITS 3 7919 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_SHIFT 2 7920 7921 /* ln_device1 :: tx_pi_control2 :: tx_pi_rx_lane_sel [01:00] */ 7922 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_MASK 0x0003 7923 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_ALIGN 0 7924 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_BITS 2 7925 #define PHY84328_DEV1_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_SHIFT 0 7926 7927 7928 /**************************************************************************** 7929 * ln_device1 :: tx_pi_control3 7930 */ 7931 /* ln_device1 :: tx_pi_control3 :: tx_pi_freq_override_val [15:01] */ 7932 #define PHY84328_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_MASK 0xfffe 7933 #define PHY84328_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_ALIGN 0 7934 #define PHY84328_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_BITS 15 7935 #define PHY84328_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_SHIFT 1 7936 7937 /* ln_device1 :: tx_pi_control3 :: tx_pi_freq_override_en [00:00] */ 7938 #define PHY84328_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_MASK 0x0001 7939 #define PHY84328_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_ALIGN 0 7940 #define PHY84328_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_BITS 1 7941 #define PHY84328_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_SHIFT 0 7942 7943 7944 /**************************************************************************** 7945 * ln_device1 :: tx_pi_control4 7946 */ 7947 /* ln_device1 :: tx_pi_control4 :: tx_pi_sm_enable_override [15:15] */ 7948 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_MASK 0x8000 7949 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_ALIGN 0 7950 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_BITS 1 7951 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_SHIFT 15 7952 7953 /* ln_device1 :: tx_pi_control4 :: tx_pi_sm_enable_override_value [14:14] */ 7954 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_MASK 0x4000 7955 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_ALIGN 0 7956 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_BITS 1 7957 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_SHIFT 14 7958 7959 /* ln_device1 :: tx_pi_control4 :: tx_pi_cdr_lkdt_override [13:13] */ 7960 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_MASK 0x2000 7961 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_ALIGN 0 7962 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_BITS 1 7963 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_SHIFT 13 7964 7965 /* ln_device1 :: tx_pi_control4 :: tx_pi_cdr_lkdt_override_value [12:12] */ 7966 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_MASK 0x1000 7967 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_ALIGN 0 7968 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_BITS 1 7969 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_SHIFT 12 7970 7971 /* ln_device1 :: tx_pi_control4 :: tx_pi_halfSpd_override_ctl [11:11] */ 7972 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_MASK 0x0800 7973 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_ALIGN 0 7974 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_BITS 1 7975 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_SHIFT 11 7976 7977 /* ln_device1 :: tx_pi_control4 :: tx_pi_halfSpd_ctl [10:10] */ 7978 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_MASK 0x0400 7979 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_ALIGN 0 7980 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_BITS 1 7981 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_SHIFT 10 7982 7983 /* ln_device1 :: tx_pi_control4 :: tx_pi_loopback_mode_override_ctl [09:09] */ 7984 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_MASK 0x0200 7985 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_ALIGN 0 7986 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_BITS 1 7987 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_SHIFT 9 7988 7989 /* ln_device1 :: tx_pi_control4 :: tx_pi_loopback_mode_ctl [08:08] */ 7990 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_MASK 0x0100 7991 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_ALIGN 0 7992 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_BITS 1 7993 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_SHIFT 8 7994 7995 /* ln_device1 :: tx_pi_control4 :: tx_pi_status3_mux_sel [07:06] */ 7996 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_MASK 0x00c0 7997 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_ALIGN 0 7998 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_BITS 2 7999 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_SHIFT 6 8000 8001 /* ln_device1 :: tx_pi_control4 :: tx_pi_status_latch [05:05] */ 8002 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_MASK 0x0020 8003 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_ALIGN 0 8004 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_BITS 1 8005 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_SHIFT 5 8006 8007 /* ln_device1 :: tx_pi_control4 :: tx_pi_prop_bypass [04:04] */ 8008 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_MASK 0x0010 8009 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_ALIGN 0 8010 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_BITS 1 8011 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_SHIFT 4 8012 8013 /* ln_device1 :: tx_pi_control4 :: tx_pi_prop_gain [03:01] */ 8014 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_GAIN_MASK 0x000e 8015 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_GAIN_ALIGN 0 8016 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_GAIN_BITS 3 8017 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_GAIN_SHIFT 1 8018 8019 /* ln_device1 :: tx_pi_control4 :: tx_pi_prop_acq [00:00] */ 8020 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_ACQ_MASK 0x0001 8021 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_ACQ_ALIGN 0 8022 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_ACQ_BITS 1 8023 #define PHY84328_DEV1_TX_PI_CONTROL4_TX_PI_PROP_ACQ_SHIFT 0 8024 8025 8026 /**************************************************************************** 8027 * ln_device1 :: tx_pi_control5 8028 */ 8029 /* ln_device1 :: tx_pi_control5 :: reserved0 [15:01] */ 8030 #define PHY84328_DEV1_TX_PI_CONTROL5_RESERVED0_MASK 0xfffe 8031 #define PHY84328_DEV1_TX_PI_CONTROL5_RESERVED0_ALIGN 0 8032 #define PHY84328_DEV1_TX_PI_CONTROL5_RESERVED0_BITS 15 8033 #define PHY84328_DEV1_TX_PI_CONTROL5_RESERVED0_SHIFT 1 8034 8035 /* ln_device1 :: tx_pi_control5 :: tx_pi_sm_rst [00:00] */ 8036 #define PHY84328_DEV1_TX_PI_CONTROL5_TX_PI_SM_RST_MASK 0x0001 8037 #define PHY84328_DEV1_TX_PI_CONTROL5_TX_PI_SM_RST_ALIGN 0 8038 #define PHY84328_DEV1_TX_PI_CONTROL5_TX_PI_SM_RST_BITS 1 8039 #define PHY84328_DEV1_TX_PI_CONTROL5_TX_PI_SM_RST_SHIFT 0 8040 8041 8042 /**************************************************************************** 8043 * ln_device1 :: tx_pi_status1 8044 */ 8045 /* ln_device1 :: tx_pi_status1 :: reserved0 [15:15] */ 8046 #define PHY84328_DEV1_TX_PI_STATUS1_RESERVED0_MASK 0x8000 8047 #define PHY84328_DEV1_TX_PI_STATUS1_RESERVED0_ALIGN 0 8048 #define PHY84328_DEV1_TX_PI_STATUS1_RESERVED0_BITS 1 8049 #define PHY84328_DEV1_TX_PI_STATUS1_RESERVED0_SHIFT 15 8050 8051 /* ln_device1 :: tx_pi_status1 :: tx_pi_integ_reg [14:00] */ 8052 #define PHY84328_DEV1_TX_PI_STATUS1_TX_PI_INTEG_REG_MASK 0x7fff 8053 #define PHY84328_DEV1_TX_PI_STATUS1_TX_PI_INTEG_REG_ALIGN 0 8054 #define PHY84328_DEV1_TX_PI_STATUS1_TX_PI_INTEG_REG_BITS 15 8055 #define PHY84328_DEV1_TX_PI_STATUS1_TX_PI_INTEG_REG_SHIFT 0 8056 8057 8058 /**************************************************************************** 8059 * ln_device1 :: tx_pi_status2 8060 */ 8061 /* ln_device1 :: tx_pi_status2 :: reserved0 [15:07] */ 8062 #define PHY84328_DEV1_TX_PI_STATUS2_RESERVED0_MASK 0xff80 8063 #define PHY84328_DEV1_TX_PI_STATUS2_RESERVED0_ALIGN 0 8064 #define PHY84328_DEV1_TX_PI_STATUS2_RESERVED0_BITS 9 8065 #define PHY84328_DEV1_TX_PI_STATUS2_RESERVED0_SHIFT 7 8066 8067 /* ln_device1 :: tx_pi_status2 :: tx_pi_phase_cntr [06:00] */ 8068 #define PHY84328_DEV1_TX_PI_STATUS2_TX_PI_PHASE_CNTR_MASK 0x007f 8069 #define PHY84328_DEV1_TX_PI_STATUS2_TX_PI_PHASE_CNTR_ALIGN 0 8070 #define PHY84328_DEV1_TX_PI_STATUS2_TX_PI_PHASE_CNTR_BITS 7 8071 #define PHY84328_DEV1_TX_PI_STATUS2_TX_PI_PHASE_CNTR_SHIFT 0 8072 8073 8074 /**************************************************************************** 8075 * ln_device1 :: tx_pi_status3 8076 */ 8077 /* ln_device1 :: tx_pi_status3 :: tx_pi_phase_ctrl [15:00] */ 8078 #define PHY84328_DEV1_TX_PI_STATUS3_TX_PI_PHASE_CTRL_MASK 0xffff 8079 #define PHY84328_DEV1_TX_PI_STATUS3_TX_PI_PHASE_CTRL_ALIGN 0 8080 #define PHY84328_DEV1_TX_PI_STATUS3_TX_PI_PHASE_CTRL_BITS 16 8081 #define PHY84328_DEV1_TX_PI_STATUS3_TX_PI_PHASE_CTRL_SHIFT 0 8082 8083 8084 /**************************************************************************** 8085 * ln_device1 :: tx_pi_status4 8086 */ 8087 /* ln_device1 :: tx_pi_status4 :: reserved0 [15:02] */ 8088 #define PHY84328_DEV1_TX_PI_STATUS4_RESERVED0_MASK 0xfffc 8089 #define PHY84328_DEV1_TX_PI_STATUS4_RESERVED0_ALIGN 0 8090 #define PHY84328_DEV1_TX_PI_STATUS4_RESERVED0_BITS 14 8091 #define PHY84328_DEV1_TX_PI_STATUS4_RESERVED0_SHIFT 2 8092 8093 /* ln_device1 :: tx_pi_status4 :: tx_pi_sm_en [01:01] */ 8094 #define PHY84328_DEV1_TX_PI_STATUS4_TX_PI_SM_EN_MASK 0x0002 8095 #define PHY84328_DEV1_TX_PI_STATUS4_TX_PI_SM_EN_ALIGN 0 8096 #define PHY84328_DEV1_TX_PI_STATUS4_TX_PI_SM_EN_BITS 1 8097 #define PHY84328_DEV1_TX_PI_STATUS4_TX_PI_SM_EN_SHIFT 1 8098 8099 /* ln_device1 :: tx_pi_status4 :: tx_pi_sm_done [00:00] */ 8100 #define PHY84328_DEV1_TX_PI_STATUS4_TX_PI_SM_DONE_MASK 0x0001 8101 #define PHY84328_DEV1_TX_PI_STATUS4_TX_PI_SM_DONE_ALIGN 0 8102 #define PHY84328_DEV1_TX_PI_STATUS4_TX_PI_SM_DONE_BITS 1 8103 #define PHY84328_DEV1_TX_PI_STATUS4_TX_PI_SM_DONE_SHIFT 0 8104 8105 8106 /**************************************************************************** 8107 * ln_device1 :: llpe_fifo_ctl 8108 */ 8109 /* ln_device1 :: llpe_fifo_ctl :: rel_level [15:11] */ 8110 #define PHY84328_DEV1_LLPE_FIFO_CTL_REL_LEVEL_MASK 0xf800 8111 #define PHY84328_DEV1_LLPE_FIFO_CTL_REL_LEVEL_ALIGN 0 8112 #define PHY84328_DEV1_LLPE_FIFO_CTL_REL_LEVEL_BITS 5 8113 #define PHY84328_DEV1_LLPE_FIFO_CTL_REL_LEVEL_SHIFT 11 8114 8115 /* ln_device1 :: llpe_fifo_ctl :: rel_4cycles [10:10] */ 8116 #define PHY84328_DEV1_LLPE_FIFO_CTL_REL_4CYCLES_MASK 0x0400 8117 #define PHY84328_DEV1_LLPE_FIFO_CTL_REL_4CYCLES_ALIGN 0 8118 #define PHY84328_DEV1_LLPE_FIFO_CTL_REL_4CYCLES_BITS 1 8119 #define PHY84328_DEV1_LLPE_FIFO_CTL_REL_4CYCLES_SHIFT 10 8120 8121 /* ln_device1 :: llpe_fifo_ctl :: lowlat_fifo_rstb_rel_sel [09:09] */ 8122 #define PHY84328_DEV1_LLPE_FIFO_CTL_LOWLAT_FIFO_RSTB_REL_SEL_MASK 0x0200 8123 #define PHY84328_DEV1_LLPE_FIFO_CTL_LOWLAT_FIFO_RSTB_REL_SEL_ALIGN 0 8124 #define PHY84328_DEV1_LLPE_FIFO_CTL_LOWLAT_FIFO_RSTB_REL_SEL_BITS 1 8125 #define PHY84328_DEV1_LLPE_FIFO_CTL_LOWLAT_FIFO_RSTB_REL_SEL_SHIFT 9 8126 8127 /* ln_device1 :: llpe_fifo_ctl :: phase_error_sel [08:08] */ 8128 #define PHY84328_DEV1_LLPE_FIFO_CTL_PHASE_ERROR_SEL_MASK 0x0100 8129 #define PHY84328_DEV1_LLPE_FIFO_CTL_PHASE_ERROR_SEL_ALIGN 0 8130 #define PHY84328_DEV1_LLPE_FIFO_CTL_PHASE_ERROR_SEL_BITS 1 8131 #define PHY84328_DEV1_LLPE_FIFO_CTL_PHASE_ERROR_SEL_SHIFT 8 8132 8133 /* ln_device1 :: llpe_fifo_ctl :: cap_prop_pe [07:07] */ 8134 #define PHY84328_DEV1_LLPE_FIFO_CTL_CAP_PROP_PE_MASK 0x0080 8135 #define PHY84328_DEV1_LLPE_FIFO_CTL_CAP_PROP_PE_ALIGN 0 8136 #define PHY84328_DEV1_LLPE_FIFO_CTL_CAP_PROP_PE_BITS 1 8137 #define PHY84328_DEV1_LLPE_FIFO_CTL_CAP_PROP_PE_SHIFT 7 8138 8139 /* ln_device1 :: llpe_fifo_ctl :: llm_fifo_status_clear [06:06] */ 8140 #define PHY84328_DEV1_LLPE_FIFO_CTL_LLM_FIFO_STATUS_CLEAR_MASK 0x0040 8141 #define PHY84328_DEV1_LLPE_FIFO_CTL_LLM_FIFO_STATUS_CLEAR_ALIGN 0 8142 #define PHY84328_DEV1_LLPE_FIFO_CTL_LLM_FIFO_STATUS_CLEAR_BITS 1 8143 #define PHY84328_DEV1_LLPE_FIFO_CTL_LLM_FIFO_STATUS_CLEAR_SHIFT 6 8144 8145 /* ln_device1 :: llpe_fifo_ctl :: hold_fifo_ptr_enable [05:05] */ 8146 #define PHY84328_DEV1_LLPE_FIFO_CTL_HOLD_FIFO_PTR_ENABLE_MASK 0x0020 8147 #define PHY84328_DEV1_LLPE_FIFO_CTL_HOLD_FIFO_PTR_ENABLE_ALIGN 0 8148 #define PHY84328_DEV1_LLPE_FIFO_CTL_HOLD_FIFO_PTR_ENABLE_BITS 1 8149 #define PHY84328_DEV1_LLPE_FIFO_CTL_HOLD_FIFO_PTR_ENABLE_SHIFT 5 8150 8151 /* ln_device1 :: llpe_fifo_ctl :: fifo_auto_reset_enable [04:04] */ 8152 #define PHY84328_DEV1_LLPE_FIFO_CTL_FIFO_AUTO_RESET_ENABLE_MASK 0x0010 8153 #define PHY84328_DEV1_LLPE_FIFO_CTL_FIFO_AUTO_RESET_ENABLE_ALIGN 0 8154 #define PHY84328_DEV1_LLPE_FIFO_CTL_FIFO_AUTO_RESET_ENABLE_BITS 1 8155 #define PHY84328_DEV1_LLPE_FIFO_CTL_FIFO_AUTO_RESET_ENABLE_SHIFT 4 8156 8157 /* ln_device1 :: llpe_fifo_ctl :: llpe_fifo_enable [03:03] */ 8158 #define PHY84328_DEV1_LLPE_FIFO_CTL_LLPE_FIFO_ENABLE_MASK 0x0008 8159 #define PHY84328_DEV1_LLPE_FIFO_CTL_LLPE_FIFO_ENABLE_ALIGN 0 8160 #define PHY84328_DEV1_LLPE_FIFO_CTL_LLPE_FIFO_ENABLE_BITS 1 8161 #define PHY84328_DEV1_LLPE_FIFO_CTL_LLPE_FIFO_ENABLE_SHIFT 3 8162 8163 /* ln_device1 :: llpe_fifo_ctl :: fifo_initial_distance [02:00] */ 8164 #define PHY84328_DEV1_LLPE_FIFO_CTL_FIFO_INITIAL_DISTANCE_MASK 0x0007 8165 #define PHY84328_DEV1_LLPE_FIFO_CTL_FIFO_INITIAL_DISTANCE_ALIGN 0 8166 #define PHY84328_DEV1_LLPE_FIFO_CTL_FIFO_INITIAL_DISTANCE_BITS 3 8167 #define PHY84328_DEV1_LLPE_FIFO_CTL_FIFO_INITIAL_DISTANCE_SHIFT 0 8168 8169 8170 /**************************************************************************** 8171 * ln_device1 :: llpe_fifo_sts 8172 */ 8173 /* ln_device1 :: llpe_fifo_sts :: fifo_rstb [15:15] */ 8174 #define PHY84328_DEV1_LLPE_FIFO_STS_FIFO_RSTB_MASK 0x8000 8175 #define PHY84328_DEV1_LLPE_FIFO_STS_FIFO_RSTB_ALIGN 0 8176 #define PHY84328_DEV1_LLPE_FIFO_STS_FIFO_RSTB_BITS 1 8177 #define PHY84328_DEV1_LLPE_FIFO_STS_FIFO_RSTB_SHIFT 15 8178 8179 /* ln_device1 :: llpe_fifo_sts :: prop_sum [14:10] */ 8180 #define PHY84328_DEV1_LLPE_FIFO_STS_PROP_SUM_MASK 0x7c00 8181 #define PHY84328_DEV1_LLPE_FIFO_STS_PROP_SUM_ALIGN 0 8182 #define PHY84328_DEV1_LLPE_FIFO_STS_PROP_SUM_BITS 5 8183 #define PHY84328_DEV1_LLPE_FIFO_STS_PROP_SUM_SHIFT 10 8184 8185 /* ln_device1 :: llpe_fifo_sts :: pe_cap_value [09:05] */ 8186 #define PHY84328_DEV1_LLPE_FIFO_STS_PE_CAP_VALUE_MASK 0x03e0 8187 #define PHY84328_DEV1_LLPE_FIFO_STS_PE_CAP_VALUE_ALIGN 0 8188 #define PHY84328_DEV1_LLPE_FIFO_STS_PE_CAP_VALUE_BITS 5 8189 #define PHY84328_DEV1_LLPE_FIFO_STS_PE_CAP_VALUE_SHIFT 5 8190 8191 /* ln_device1 :: llpe_fifo_sts :: llpe_fifo_full [04:04] */ 8192 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_MASK 0x0010 8193 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_ALIGN 0 8194 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_BITS 1 8195 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_SHIFT 4 8196 8197 /* ln_device1 :: llpe_fifo_sts :: llpe_fifo_full_sticky [03:03] */ 8198 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_STICKY_MASK 0x0008 8199 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_STICKY_ALIGN 0 8200 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_STICKY_BITS 1 8201 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_STICKY_SHIFT 3 8202 8203 /* ln_device1 :: llpe_fifo_sts :: llpe_fifo_empty [02:02] */ 8204 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_MASK 0x0004 8205 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_ALIGN 0 8206 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_BITS 1 8207 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_SHIFT 2 8208 8209 /* ln_device1 :: llpe_fifo_sts :: llpe_fifo_empty_sticky [01:01] */ 8210 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_STICKY_MASK 0x0002 8211 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_STICKY_ALIGN 0 8212 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_STICKY_BITS 1 8213 #define PHY84328_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_STICKY_SHIFT 1 8214 8215 /* ln_device1 :: llpe_fifo_sts :: ll_analog_fifo_ovfb [00:00] */ 8216 #define PHY84328_DEV1_LLPE_FIFO_STS_LL_ANALOG_FIFO_OVFB_MASK 0x0001 8217 #define PHY84328_DEV1_LLPE_FIFO_STS_LL_ANALOG_FIFO_OVFB_ALIGN 0 8218 #define PHY84328_DEV1_LLPE_FIFO_STS_LL_ANALOG_FIFO_OVFB_BITS 1 8219 #define PHY84328_DEV1_LLPE_FIFO_STS_LL_ANALOG_FIFO_OVFB_SHIFT 0 8220 8221 8222 /**************************************************************************** 8223 * ln_device1_QSFI_gpregs 8224 */ 8225 /**************************************************************************** 8226 * ln_device1 :: GP2_0 8227 */ 8228 /* ln_device1 :: GP2_0 :: pll_mode [15:12] */ 8229 #define PHY84328_DEV1_GP2_0_PLL_MODE_MASK 0xf000 8230 #define PHY84328_DEV1_GP2_0_PLL_MODE_ALIGN 0 8231 #define PHY84328_DEV1_GP2_0_PLL_MODE_BITS 4 8232 #define PHY84328_DEV1_GP2_0_PLL_MODE_SHIFT 12 8233 8234 /* ln_device1 :: GP2_0 :: sigdet [11:08] */ 8235 #define PHY84328_DEV1_GP2_0_SIGDET_MASK 0x0f00 8236 #define PHY84328_DEV1_GP2_0_SIGDET_ALIGN 0 8237 #define PHY84328_DEV1_GP2_0_SIGDET_BITS 4 8238 #define PHY84328_DEV1_GP2_0_SIGDET_SHIFT 8 8239 8240 /* ln_device1 :: GP2_0 :: pll_lock_1g [07:04] */ 8241 #define PHY84328_DEV1_GP2_0_PLL_LOCK_1G_MASK 0x00f0 8242 #define PHY84328_DEV1_GP2_0_PLL_LOCK_1G_ALIGN 0 8243 #define PHY84328_DEV1_GP2_0_PLL_LOCK_1G_BITS 4 8244 #define PHY84328_DEV1_GP2_0_PLL_LOCK_1G_SHIFT 4 8245 8246 /* ln_device1 :: GP2_0 :: sync_status_combo [03:00] */ 8247 #define PHY84328_DEV1_GP2_0_SYNC_STATUS_COMBO_MASK 0x000f 8248 #define PHY84328_DEV1_GP2_0_SYNC_STATUS_COMBO_ALIGN 0 8249 #define PHY84328_DEV1_GP2_0_SYNC_STATUS_COMBO_BITS 4 8250 #define PHY84328_DEV1_GP2_0_SYNC_STATUS_COMBO_SHIFT 0 8251 8252 8253 /**************************************************************************** 8254 * ln_device1 :: GP2_1 8255 */ 8256 /* ln_device1 :: GP2_1 :: link_KR [15:12] */ 8257 #define PHY84328_DEV1_GP2_1_LINK_KR_MASK 0xf000 8258 #define PHY84328_DEV1_GP2_1_LINK_KR_ALIGN 0 8259 #define PHY84328_DEV1_GP2_1_LINK_KR_BITS 4 8260 #define PHY84328_DEV1_GP2_1_LINK_KR_SHIFT 12 8261 8262 /* ln_device1 :: GP2_1 :: link_status [11:08] */ 8263 #define PHY84328_DEV1_GP2_1_LINK_STATUS_MASK 0x0f00 8264 #define PHY84328_DEV1_GP2_1_LINK_STATUS_ALIGN 0 8265 #define PHY84328_DEV1_GP2_1_LINK_STATUS_BITS 4 8266 #define PHY84328_DEV1_GP2_1_LINK_STATUS_SHIFT 8 8267 8268 /* ln_device1 :: GP2_1 :: link_100fx [07:04] */ 8269 #define PHY84328_DEV1_GP2_1_LINK_100FX_MASK 0x00f0 8270 #define PHY84328_DEV1_GP2_1_LINK_100FX_ALIGN 0 8271 #define PHY84328_DEV1_GP2_1_LINK_100FX_BITS 4 8272 #define PHY84328_DEV1_GP2_1_LINK_100FX_SHIFT 4 8273 8274 /* ln_device1 :: GP2_1 :: link_an [03:00] */ 8275 #define PHY84328_DEV1_GP2_1_LINK_AN_MASK 0x000f 8276 #define PHY84328_DEV1_GP2_1_LINK_AN_ALIGN 0 8277 #define PHY84328_DEV1_GP2_1_LINK_AN_BITS 4 8278 #define PHY84328_DEV1_GP2_1_LINK_AN_SHIFT 0 8279 8280 8281 /**************************************************************************** 8282 * ln_device1 :: GP2_2 8283 */ 8284 /* ln_device1 :: GP2_2 :: reserved0 [15:14] */ 8285 #define PHY84328_DEV1_GP2_2_RESERVED0_MASK 0xc000 8286 #define PHY84328_DEV1_GP2_2_RESERVED0_ALIGN 0 8287 #define PHY84328_DEV1_GP2_2_RESERVED0_BITS 2 8288 #define PHY84328_DEV1_GP2_2_RESERVED0_SHIFT 14 8289 8290 /* ln_device1 :: GP2_2 :: actual_speed_ln1 [13:08] */ 8291 #define PHY84328_DEV1_GP2_2_ACTUAL_SPEED_LN1_MASK 0x3f00 8292 #define PHY84328_DEV1_GP2_2_ACTUAL_SPEED_LN1_ALIGN 0 8293 #define PHY84328_DEV1_GP2_2_ACTUAL_SPEED_LN1_BITS 6 8294 #define PHY84328_DEV1_GP2_2_ACTUAL_SPEED_LN1_SHIFT 8 8295 8296 /* ln_device1 :: GP2_2 :: reserved1 [07:06] */ 8297 #define PHY84328_DEV1_GP2_2_RESERVED1_MASK 0x00c0 8298 #define PHY84328_DEV1_GP2_2_RESERVED1_ALIGN 0 8299 #define PHY84328_DEV1_GP2_2_RESERVED1_BITS 2 8300 #define PHY84328_DEV1_GP2_2_RESERVED1_SHIFT 6 8301 8302 /* ln_device1 :: GP2_2 :: actual_speed_ln0 [05:00] */ 8303 #define PHY84328_DEV1_GP2_2_ACTUAL_SPEED_LN0_MASK 0x003f 8304 #define PHY84328_DEV1_GP2_2_ACTUAL_SPEED_LN0_ALIGN 0 8305 #define PHY84328_DEV1_GP2_2_ACTUAL_SPEED_LN0_BITS 6 8306 #define PHY84328_DEV1_GP2_2_ACTUAL_SPEED_LN0_SHIFT 0 8307 8308 8309 /**************************************************************************** 8310 * ln_device1 :: GP2_3 8311 */ 8312 /* ln_device1 :: GP2_3 :: reserved0 [15:14] */ 8313 #define PHY84328_DEV1_GP2_3_RESERVED0_MASK 0xc000 8314 #define PHY84328_DEV1_GP2_3_RESERVED0_ALIGN 0 8315 #define PHY84328_DEV1_GP2_3_RESERVED0_BITS 2 8316 #define PHY84328_DEV1_GP2_3_RESERVED0_SHIFT 14 8317 8318 /* ln_device1 :: GP2_3 :: actual_speed_ln3 [13:08] */ 8319 #define PHY84328_DEV1_GP2_3_ACTUAL_SPEED_LN3_MASK 0x3f00 8320 #define PHY84328_DEV1_GP2_3_ACTUAL_SPEED_LN3_ALIGN 0 8321 #define PHY84328_DEV1_GP2_3_ACTUAL_SPEED_LN3_BITS 6 8322 #define PHY84328_DEV1_GP2_3_ACTUAL_SPEED_LN3_SHIFT 8 8323 8324 /* ln_device1 :: GP2_3 :: reserved1 [07:06] */ 8325 #define PHY84328_DEV1_GP2_3_RESERVED1_MASK 0x00c0 8326 #define PHY84328_DEV1_GP2_3_RESERVED1_ALIGN 0 8327 #define PHY84328_DEV1_GP2_3_RESERVED1_BITS 2 8328 #define PHY84328_DEV1_GP2_3_RESERVED1_SHIFT 6 8329 8330 /* ln_device1 :: GP2_3 :: actual_speed_ln2 [05:00] */ 8331 #define PHY84328_DEV1_GP2_3_ACTUAL_SPEED_LN2_MASK 0x003f 8332 #define PHY84328_DEV1_GP2_3_ACTUAL_SPEED_LN2_ALIGN 0 8333 #define PHY84328_DEV1_GP2_3_ACTUAL_SPEED_LN2_BITS 6 8334 #define PHY84328_DEV1_GP2_3_ACTUAL_SPEED_LN2_SHIFT 0 8335 8336 8337 /**************************************************************************** 8338 * ln_device1 :: GP2_4 8339 */ 8340 /* ln_device1 :: GP2_4 :: cl73_autoneg_complete [15:12] */ 8341 #define PHY84328_DEV1_GP2_4_CL73_AUTONEG_COMPLETE_MASK 0xf000 8342 #define PHY84328_DEV1_GP2_4_CL73_AUTONEG_COMPLETE_ALIGN 0 8343 #define PHY84328_DEV1_GP2_4_CL73_AUTONEG_COMPLETE_BITS 4 8344 #define PHY84328_DEV1_GP2_4_CL73_AUTONEG_COMPLETE_SHIFT 12 8345 8346 /* ln_device1 :: GP2_4 :: autoneg_complete [11:08] */ 8347 #define PHY84328_DEV1_GP2_4_AUTONEG_COMPLETE_MASK 0x0f00 8348 #define PHY84328_DEV1_GP2_4_AUTONEG_COMPLETE_ALIGN 0 8349 #define PHY84328_DEV1_GP2_4_AUTONEG_COMPLETE_BITS 4 8350 #define PHY84328_DEV1_GP2_4_AUTONEG_COMPLETE_SHIFT 8 8351 8352 /* ln_device1 :: GP2_4 :: cl73_mr_lp_autoneg_able [07:04] */ 8353 #define PHY84328_DEV1_GP2_4_CL73_MR_LP_AUTONEG_ABLE_MASK 0x00f0 8354 #define PHY84328_DEV1_GP2_4_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 8355 #define PHY84328_DEV1_GP2_4_CL73_MR_LP_AUTONEG_ABLE_BITS 4 8356 #define PHY84328_DEV1_GP2_4_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 8357 8358 /* ln_device1 :: GP2_4 :: cl73_mr_autoneg_able [03:00] */ 8359 #define PHY84328_DEV1_GP2_4_CL73_MR_AUTONEG_ABLE_MASK 0x000f 8360 #define PHY84328_DEV1_GP2_4_CL73_MR_AUTONEG_ABLE_ALIGN 0 8361 #define PHY84328_DEV1_GP2_4_CL73_MR_AUTONEG_ABLE_BITS 4 8362 #define PHY84328_DEV1_GP2_4_CL73_MR_AUTONEG_ABLE_SHIFT 0 8363 8364 8365 /**************************************************************************** 8366 * ln_device1 :: GP2_5 8367 */ 8368 /* ln_device1 :: GP2_5 :: Cl73_BAMStat1_ln0 [15:00] */ 8369 #define PHY84328_DEV1_GP2_5_CL73_BAMSTAT1_LN0_MASK 0xffff 8370 #define PHY84328_DEV1_GP2_5_CL73_BAMSTAT1_LN0_ALIGN 0 8371 #define PHY84328_DEV1_GP2_5_CL73_BAMSTAT1_LN0_BITS 16 8372 #define PHY84328_DEV1_GP2_5_CL73_BAMSTAT1_LN0_SHIFT 0 8373 8374 8375 /**************************************************************************** 8376 * ln_device1 :: GP2_6 8377 */ 8378 /* ln_device1 :: GP2_6 :: Cl73_BAMStat2_ln0 [15:00] */ 8379 #define PHY84328_DEV1_GP2_6_CL73_BAMSTAT2_LN0_MASK 0xffff 8380 #define PHY84328_DEV1_GP2_6_CL73_BAMSTAT2_LN0_ALIGN 0 8381 #define PHY84328_DEV1_GP2_6_CL73_BAMSTAT2_LN0_BITS 16 8382 #define PHY84328_DEV1_GP2_6_CL73_BAMSTAT2_LN0_SHIFT 0 8383 8384 8385 /**************************************************************************** 8386 * ln_device1 :: GP2_7 8387 */ 8388 /* ln_device1 :: GP2_7 :: Cl73_BAMStat3_ln0 [15:00] */ 8389 #define PHY84328_DEV1_GP2_7_CL73_BAMSTAT3_LN0_MASK 0xffff 8390 #define PHY84328_DEV1_GP2_7_CL73_BAMSTAT3_LN0_ALIGN 0 8391 #define PHY84328_DEV1_GP2_7_CL73_BAMSTAT3_LN0_BITS 16 8392 #define PHY84328_DEV1_GP2_7_CL73_BAMSTAT3_LN0_SHIFT 0 8393 8394 8395 /**************************************************************************** 8396 * ln_device1 :: GP2_9 8397 */ 8398 /* ln_device1 :: GP2_9 :: prbs_lock_ln0 [15:15] */ 8399 #define PHY84328_DEV1_GP2_9_PRBS_LOCK_LN0_MASK 0x8000 8400 #define PHY84328_DEV1_GP2_9_PRBS_LOCK_LN0_ALIGN 0 8401 #define PHY84328_DEV1_GP2_9_PRBS_LOCK_LN0_BITS 1 8402 #define PHY84328_DEV1_GP2_9_PRBS_LOCK_LN0_SHIFT 15 8403 8404 /* ln_device1 :: GP2_9 :: tx0_fir_tap_main [14:09] */ 8405 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_MAIN_MASK 0x7e00 8406 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_MAIN_ALIGN 0 8407 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_MAIN_BITS 6 8408 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_MAIN_SHIFT 9 8409 8410 /* ln_device1 :: GP2_9 :: tx0_fir_tap_pre [08:05] */ 8411 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_PRE_MASK 0x01e0 8412 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_PRE_ALIGN 0 8413 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_PRE_BITS 4 8414 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_PRE_SHIFT 5 8415 8416 /* ln_device1 :: GP2_9 :: tx0_fir_tap_post [04:00] */ 8417 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_POST_MASK 0x001f 8418 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_POST_ALIGN 0 8419 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_POST_BITS 5 8420 #define PHY84328_DEV1_GP2_9_TX0_FIR_TAP_POST_SHIFT 0 8421 8422 8423 /**************************************************************************** 8424 * ln_device1 :: GP2_A 8425 */ 8426 /* ln_device1 :: GP2_A :: prbs_lock_ln1 [15:15] */ 8427 #define PHY84328_DEV1_GP2_A_PRBS_LOCK_LN1_MASK 0x8000 8428 #define PHY84328_DEV1_GP2_A_PRBS_LOCK_LN1_ALIGN 0 8429 #define PHY84328_DEV1_GP2_A_PRBS_LOCK_LN1_BITS 1 8430 #define PHY84328_DEV1_GP2_A_PRBS_LOCK_LN1_SHIFT 15 8431 8432 /* ln_device1 :: GP2_A :: tx1_fir_tap_main [14:09] */ 8433 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_MAIN_MASK 0x7e00 8434 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_MAIN_ALIGN 0 8435 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_MAIN_BITS 6 8436 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_MAIN_SHIFT 9 8437 8438 /* ln_device1 :: GP2_A :: tx1_fir_tap_pre [08:05] */ 8439 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_PRE_MASK 0x01e0 8440 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_PRE_ALIGN 0 8441 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_PRE_BITS 4 8442 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_PRE_SHIFT 5 8443 8444 /* ln_device1 :: GP2_A :: tx1_fir_tap_post [04:00] */ 8445 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_POST_MASK 0x001f 8446 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_POST_ALIGN 0 8447 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_POST_BITS 5 8448 #define PHY84328_DEV1_GP2_A_TX1_FIR_TAP_POST_SHIFT 0 8449 8450 8451 /**************************************************************************** 8452 * ln_device1 :: GP2_B 8453 */ 8454 /* ln_device1 :: GP2_B :: prbs_lock_ln2 [15:15] */ 8455 #define PHY84328_DEV1_GP2_B_PRBS_LOCK_LN2_MASK 0x8000 8456 #define PHY84328_DEV1_GP2_B_PRBS_LOCK_LN2_ALIGN 0 8457 #define PHY84328_DEV1_GP2_B_PRBS_LOCK_LN2_BITS 1 8458 #define PHY84328_DEV1_GP2_B_PRBS_LOCK_LN2_SHIFT 15 8459 8460 /* ln_device1 :: GP2_B :: tx2_fir_tap_main [14:09] */ 8461 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_MAIN_MASK 0x7e00 8462 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_MAIN_ALIGN 0 8463 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_MAIN_BITS 6 8464 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_MAIN_SHIFT 9 8465 8466 /* ln_device1 :: GP2_B :: tx2_fir_tap_pre [08:05] */ 8467 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_PRE_MASK 0x01e0 8468 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_PRE_ALIGN 0 8469 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_PRE_BITS 4 8470 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_PRE_SHIFT 5 8471 8472 /* ln_device1 :: GP2_B :: tx2_fir_tap_post [04:00] */ 8473 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_POST_MASK 0x001f 8474 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_POST_ALIGN 0 8475 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_POST_BITS 5 8476 #define PHY84328_DEV1_GP2_B_TX2_FIR_TAP_POST_SHIFT 0 8477 8478 8479 /**************************************************************************** 8480 * ln_device1 :: GP2_C 8481 */ 8482 /* ln_device1 :: GP2_C :: prbs_lock_ln3 [15:15] */ 8483 #define PHY84328_DEV1_GP2_C_PRBS_LOCK_LN3_MASK 0x8000 8484 #define PHY84328_DEV1_GP2_C_PRBS_LOCK_LN3_ALIGN 0 8485 #define PHY84328_DEV1_GP2_C_PRBS_LOCK_LN3_BITS 1 8486 #define PHY84328_DEV1_GP2_C_PRBS_LOCK_LN3_SHIFT 15 8487 8488 /* ln_device1 :: GP2_C :: tx3_fir_tap_main [14:09] */ 8489 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_MAIN_MASK 0x7e00 8490 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_MAIN_ALIGN 0 8491 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_MAIN_BITS 6 8492 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_MAIN_SHIFT 9 8493 8494 /* ln_device1 :: GP2_C :: tx3_fir_tap_pre [08:05] */ 8495 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_PRE_MASK 0x01e0 8496 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_PRE_ALIGN 0 8497 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_PRE_BITS 4 8498 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_PRE_SHIFT 5 8499 8500 /* ln_device1 :: GP2_C :: tx3_fir_tap_post [04:00] */ 8501 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_POST_MASK 0x001f 8502 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_POST_ALIGN 0 8503 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_POST_BITS 5 8504 #define PHY84328_DEV1_GP2_C_TX3_FIR_TAP_POST_SHIFT 0 8505 8506 8507 /**************************************************************************** 8508 * ln_device1_cl72_user_regs 8509 */ 8510 /**************************************************************************** 8511 * ln_device1 :: cl72_xmt_control_register 8512 */ 8513 /* ln_device1 :: cl72_xmt_control_register :: xmt_control_page [15:00] */ 8514 #define PHY84328_DEV1_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_MASK 0xffff 8515 #define PHY84328_DEV1_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_ALIGN 0 8516 #define PHY84328_DEV1_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_BITS 16 8517 #define PHY84328_DEV1_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_SHIFT 0 8518 8519 8520 /**************************************************************************** 8521 * ln_device1 :: cl72_rcvd_status_register 8522 */ 8523 /* ln_device1 :: cl72_rcvd_status_register :: rcvd_status_page [15:00] */ 8524 #define PHY84328_DEV1_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_MASK 0xffff 8525 #define PHY84328_DEV1_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_ALIGN 0 8526 #define PHY84328_DEV1_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_BITS 16 8527 #define PHY84328_DEV1_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_SHIFT 0 8528 8529 8530 /**************************************************************************** 8531 * ln_device1 :: cl72_tx_fir_tap_register 8532 */ 8533 /* ln_device1 :: cl72_tx_fir_tap_register :: tx_fir_tap_force [15:15] */ 8534 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_MASK 0x8000 8535 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_ALIGN 0 8536 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_BITS 1 8537 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_SHIFT 15 8538 8539 /* ln_device1 :: cl72_tx_fir_tap_register :: tx_fir_tap_post [14:10] */ 8540 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_MASK 0x7c00 8541 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_ALIGN 0 8542 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_BITS 5 8543 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_SHIFT 10 8544 8545 /* ln_device1 :: cl72_tx_fir_tap_register :: tx_fir_tap_main [09:04] */ 8546 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_MASK 0x03f0 8547 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_ALIGN 0 8548 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_BITS 6 8549 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_SHIFT 4 8550 8551 /* ln_device1 :: cl72_tx_fir_tap_register :: tx_fir_tap_pre [03:00] */ 8552 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_MASK 0x000f 8553 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_ALIGN 0 8554 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_BITS 4 8555 #define PHY84328_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_SHIFT 0 8556 8557 8558 /**************************************************************************** 8559 * ln_device1 :: cl72_misc1_control 8560 */ 8561 /* ln_device1 :: cl72_misc1_control :: link_control_force [15:15] */ 8562 #define PHY84328_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_MASK 0x8000 8563 #define PHY84328_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_ALIGN 0 8564 #define PHY84328_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_BITS 1 8565 #define PHY84328_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_SHIFT 15 8566 8567 /* ln_device1 :: cl72_misc1_control :: link_control_forceval [14:14] */ 8568 #define PHY84328_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_MASK 0x4000 8569 #define PHY84328_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_ALIGN 0 8570 #define PHY84328_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_BITS 1 8571 #define PHY84328_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_SHIFT 14 8572 8573 /* ln_device1 :: cl72_misc1_control :: tx_fir_tap_main_kx_init_val [13:08] */ 8574 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_MASK 0x3f00 8575 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_ALIGN 0 8576 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_BITS 6 8577 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_SHIFT 8 8578 8579 /* ln_device1 :: cl72_misc1_control :: tap_default_muxsel_force [07:07] */ 8580 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_MASK 0x0080 8581 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_ALIGN 0 8582 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_BITS 1 8583 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_SHIFT 7 8584 8585 /* ln_device1 :: cl72_misc1_control :: tap_default_muxsel_forceval [06:04] */ 8586 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_MASK 0x0070 8587 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_ALIGN 0 8588 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_BITS 3 8589 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_SHIFT 4 8590 8591 /* ln_device1 :: cl72_misc1_control :: reserved0 [03:02] */ 8592 #define PHY84328_DEV1_CL72_MISC1_CONTROL_RESERVED0_MASK 0x000c 8593 #define PHY84328_DEV1_CL72_MISC1_CONTROL_RESERVED0_ALIGN 0 8594 #define PHY84328_DEV1_CL72_MISC1_CONTROL_RESERVED0_BITS 2 8595 #define PHY84328_DEV1_CL72_MISC1_CONTROL_RESERVED0_SHIFT 2 8596 8597 /* ln_device1 :: cl72_misc1_control :: tr_coarse_lock [01:01] */ 8598 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TR_COARSE_LOCK_MASK 0x0002 8599 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TR_COARSE_LOCK_ALIGN 0 8600 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TR_COARSE_LOCK_BITS 1 8601 #define PHY84328_DEV1_CL72_MISC1_CONTROL_TR_COARSE_LOCK_SHIFT 1 8602 8603 /* ln_device1 :: cl72_misc1_control :: rx_trained [00:00] */ 8604 #define PHY84328_DEV1_CL72_MISC1_CONTROL_RX_TRAINED_MASK 0x0001 8605 #define PHY84328_DEV1_CL72_MISC1_CONTROL_RX_TRAINED_ALIGN 0 8606 #define PHY84328_DEV1_CL72_MISC1_CONTROL_RX_TRAINED_BITS 1 8607 #define PHY84328_DEV1_CL72_MISC1_CONTROL_RX_TRAINED_SHIFT 0 8608 8609 8610 /**************************************************************************** 8611 * ln_device1 :: cl72_misc2_control 8612 */ 8613 /* ln_device1 :: cl72_misc2_control :: reserved0 [15:14] */ 8614 #define PHY84328_DEV1_CL72_MISC2_CONTROL_RESERVED0_MASK 0xc000 8615 #define PHY84328_DEV1_CL72_MISC2_CONTROL_RESERVED0_ALIGN 0 8616 #define PHY84328_DEV1_CL72_MISC2_CONTROL_RESERVED0_BITS 2 8617 #define PHY84328_DEV1_CL72_MISC2_CONTROL_RESERVED0_SHIFT 14 8618 8619 /* ln_device1 :: cl72_misc2_control :: rxfifo_data_swap_r20clk [13:13] */ 8620 #define PHY84328_DEV1_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_MASK 0x2000 8621 #define PHY84328_DEV1_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_ALIGN 0 8622 #define PHY84328_DEV1_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_BITS 1 8623 #define PHY84328_DEV1_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_SHIFT 13 8624 8625 /* ln_device1 :: cl72_misc2_control :: txfifo_data_swap_t20clk [12:12] */ 8626 #define PHY84328_DEV1_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_MASK 0x1000 8627 #define PHY84328_DEV1_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_ALIGN 0 8628 #define PHY84328_DEV1_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_BITS 1 8629 #define PHY84328_DEV1_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_SHIFT 12 8630 8631 /* ln_device1 :: cl72_misc2_control :: signal_detect_fec_sel [11:11] */ 8632 #define PHY84328_DEV1_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_MASK 0x0800 8633 #define PHY84328_DEV1_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_ALIGN 0 8634 #define PHY84328_DEV1_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_BITS 1 8635 #define PHY84328_DEV1_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_SHIFT 11 8636 8637 /* ln_device1 :: cl72_misc2_control :: wait_timer_frame_inc_en [10:10] */ 8638 #define PHY84328_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_MASK 0x0400 8639 #define PHY84328_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_ALIGN 0 8640 #define PHY84328_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_BITS 1 8641 #define PHY84328_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_SHIFT 10 8642 8643 /* ln_device1 :: cl72_misc2_control :: wait_timer_frame_cnt_init_sel [09:08] */ 8644 #define PHY84328_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_MASK 0x0300 8645 #define PHY84328_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_ALIGN 0 8646 #define PHY84328_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_BITS 2 8647 #define PHY84328_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_SHIFT 8 8648 8649 /* ln_device1 :: cl72_misc2_control :: main_tap_adjust_force [07:07] */ 8650 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_MASK 0x0080 8651 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_ALIGN 0 8652 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_BITS 1 8653 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_SHIFT 7 8654 8655 /* ln_device1 :: cl72_misc2_control :: main_tap_adjust_forceval [06:06] */ 8656 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_MASK 0x0040 8657 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_ALIGN 0 8658 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_BITS 1 8659 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_SHIFT 6 8660 8661 /* ln_device1 :: cl72_misc2_control :: main_tap_adjust_en [05:05] */ 8662 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_MASK 0x0020 8663 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_ALIGN 0 8664 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_BITS 1 8665 #define PHY84328_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_SHIFT 5 8666 8667 /* ln_device1 :: cl72_misc2_control :: newpg_rcvd_override [04:04] */ 8668 #define PHY84328_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_MASK 0x0010 8669 #define PHY84328_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_ALIGN 0 8670 #define PHY84328_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_BITS 1 8671 #define PHY84328_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_SHIFT 4 8672 8673 /* ln_device1 :: cl72_misc2_control :: newpg_rcvd_load [03:03] */ 8674 #define PHY84328_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_MASK 0x0008 8675 #define PHY84328_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_ALIGN 0 8676 #define PHY84328_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_BITS 1 8677 #define PHY84328_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_SHIFT 3 8678 8679 /* ln_device1 :: cl72_misc2_control :: inc_dec_val_sel [02:02] */ 8680 #define PHY84328_DEV1_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_MASK 0x0004 8681 #define PHY84328_DEV1_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_ALIGN 0 8682 #define PHY84328_DEV1_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_BITS 1 8683 #define PHY84328_DEV1_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_SHIFT 2 8684 8685 /* ln_device1 :: cl72_misc2_control :: dis_max_wait_timer_force [01:01] */ 8686 #define PHY84328_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_MASK 0x0002 8687 #define PHY84328_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_ALIGN 0 8688 #define PHY84328_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_BITS 1 8689 #define PHY84328_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_SHIFT 1 8690 8691 /* ln_device1 :: cl72_misc2_control :: dis_max_wait_timer_forceval [00:00] */ 8692 #define PHY84328_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_MASK 0x0001 8693 #define PHY84328_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_ALIGN 0 8694 #define PHY84328_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_BITS 1 8695 #define PHY84328_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_SHIFT 0 8696 8697 8698 /**************************************************************************** 8699 * ln_device1 :: cl72_kr_default_control 8700 */ 8701 /* ln_device1 :: cl72_kr_default_control :: reserved0 [15:15] */ 8702 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 8703 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_RESERVED0_ALIGN 0 8704 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_RESERVED0_BITS 1 8705 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_RESERVED0_SHIFT 15 8706 8707 /* ln_device1 :: cl72_kr_default_control :: tx_fir_tap_post_kr_init_val [14:10] */ 8708 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_MASK 0x7c00 8709 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_ALIGN 0 8710 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_BITS 5 8711 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_SHIFT 10 8712 8713 /* ln_device1 :: cl72_kr_default_control :: tx_fir_tap_main_kr_init_val [09:04] */ 8714 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_MASK 0x03f0 8715 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_ALIGN 0 8716 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_BITS 6 8717 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_SHIFT 4 8718 8719 /* ln_device1 :: cl72_kr_default_control :: tx_fir_tap_pre_kr_init_val [03:00] */ 8720 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_MASK 0x000f 8721 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_ALIGN 0 8722 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_BITS 4 8723 #define PHY84328_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_SHIFT 0 8724 8725 8726 /**************************************************************************** 8727 * ln_device1 :: cl72_os_default_control 8728 */ 8729 /* ln_device1 :: cl72_os_default_control :: reserved0 [15:15] */ 8730 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 8731 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_RESERVED0_ALIGN 0 8732 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_RESERVED0_BITS 1 8733 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_RESERVED0_SHIFT 15 8734 8735 /* ln_device1 :: cl72_os_default_control :: tx_fir_tap_post_os_init_val [14:10] */ 8736 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_MASK 0x7c00 8737 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_ALIGN 0 8738 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_BITS 5 8739 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_SHIFT 10 8740 8741 /* ln_device1 :: cl72_os_default_control :: tx_fir_tap_main_os_init_val [09:04] */ 8742 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_MASK 0x03f0 8743 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_ALIGN 0 8744 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_BITS 6 8745 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_SHIFT 4 8746 8747 /* ln_device1 :: cl72_os_default_control :: tx_fir_tap_pre_os_init_val [03:00] */ 8748 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_MASK 0x000f 8749 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_ALIGN 0 8750 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_BITS 4 8751 #define PHY84328_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_SHIFT 0 8752 8753 8754 /**************************************************************************** 8755 * ln_device1 :: cl72_br_default_control 8756 */ 8757 /* ln_device1 :: cl72_br_default_control :: reserved0 [15:15] */ 8758 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 8759 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_RESERVED0_ALIGN 0 8760 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_RESERVED0_BITS 1 8761 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_RESERVED0_SHIFT 15 8762 8763 /* ln_device1 :: cl72_br_default_control :: tx_fir_tap_post_br_init_val [14:10] */ 8764 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_MASK 0x7c00 8765 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_ALIGN 0 8766 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_BITS 5 8767 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_SHIFT 10 8768 8769 /* ln_device1 :: cl72_br_default_control :: tx_fir_tap_main_br_init_val [09:04] */ 8770 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_MASK 0x03f0 8771 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_ALIGN 0 8772 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_BITS 6 8773 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_SHIFT 4 8774 8775 /* ln_device1 :: cl72_br_default_control :: tx_fir_tap_pre_br_init_val [03:00] */ 8776 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_MASK 0x000f 8777 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_ALIGN 0 8778 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_BITS 4 8779 #define PHY84328_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_SHIFT 0 8780 8781 8782 /**************************************************************************** 8783 * ln_device1 :: cl72_tap_limit_control 8784 */ 8785 /* ln_device1 :: cl72_tap_limit_control :: reserved0 [15:15] */ 8786 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_RESERVED0_MASK 0x8000 8787 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_RESERVED0_ALIGN 0 8788 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_RESERVED0_BITS 1 8789 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_RESERVED0_SHIFT 15 8790 8791 /* ln_device1 :: cl72_tap_limit_control :: post_tap_limit [14:10] */ 8792 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_MASK 0x7c00 8793 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_ALIGN 0 8794 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_BITS 5 8795 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_SHIFT 10 8796 8797 /* ln_device1 :: cl72_tap_limit_control :: main_tap_limit [09:04] */ 8798 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_MASK 0x03f0 8799 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_ALIGN 0 8800 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_BITS 6 8801 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_SHIFT 4 8802 8803 /* ln_device1 :: cl72_tap_limit_control :: pre_tap_limit [03:00] */ 8804 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_MASK 0x000f 8805 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_ALIGN 0 8806 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_BITS 4 8807 #define PHY84328_DEV1_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_SHIFT 0 8808 8809 8810 /**************************************************************************** 8811 * ln_device1 :: cl72_misc3_control 8812 */ 8813 /* ln_device1 :: cl72_misc3_control :: cl72_en_mask [15:00] */ 8814 #define PHY84328_DEV1_CL72_MISC3_CONTROL_CL72_EN_MASK_MASK 0xffff 8815 #define PHY84328_DEV1_CL72_MISC3_CONTROL_CL72_EN_MASK_ALIGN 0 8816 #define PHY84328_DEV1_CL72_MISC3_CONTROL_CL72_EN_MASK_BITS 16 8817 #define PHY84328_DEV1_CL72_MISC3_CONTROL_CL72_EN_MASK_SHIFT 0 8818 8819 8820 /**************************************************************************** 8821 * ln_device1 :: cl72_tap_preset_control 8822 */ 8823 /* ln_device1 :: cl72_tap_preset_control :: reserved0 [15:09] */ 8824 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_RESERVED0_MASK 0xfe00 8825 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_RESERVED0_ALIGN 0 8826 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_RESERVED0_BITS 7 8827 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_RESERVED0_SHIFT 9 8828 8829 /* ln_device1 :: cl72_tap_preset_control :: pre_init_val [08:05] */ 8830 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_MASK 0x01e0 8831 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_ALIGN 0 8832 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_BITS 4 8833 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_SHIFT 5 8834 8835 /* ln_device1 :: cl72_tap_preset_control :: post_init_val [04:00] */ 8836 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_MASK 0x001f 8837 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_ALIGN 0 8838 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_BITS 5 8839 #define PHY84328_DEV1_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_SHIFT 0 8840 8841 8842 /**************************************************************************** 8843 * ln_device1 :: cl72_misc4_control 8844 */ 8845 /* ln_device1 :: cl72_misc4_control :: reserved0 [15:12] */ 8846 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RESERVED0_MASK 0xf000 8847 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RESERVED0_ALIGN 0 8848 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RESERVED0_BITS 4 8849 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RESERVED0_SHIFT 12 8850 8851 /* ln_device1 :: cl72_misc4_control :: rx_wclk_20_mode_sel [11:10] */ 8852 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_MASK 0x0c00 8853 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_ALIGN 0 8854 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_BITS 2 8855 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_SHIFT 10 8856 8857 /* ln_device1 :: cl72_misc4_control :: rx_wclk16_ckgate_off [09:09] */ 8858 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_MASK 0x0200 8859 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_ALIGN 0 8860 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_BITS 1 8861 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_SHIFT 9 8862 8863 /* ln_device1 :: cl72_misc4_control :: rx_wclk16_legacy_clkmode [08:08] */ 8864 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_MASK 0x0100 8865 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_ALIGN 0 8866 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_BITS 1 8867 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_SHIFT 8 8868 8869 /* ln_device1 :: cl72_misc4_control :: rx_wclk16_wclk20_per_lane [07:07] */ 8870 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_MASK 0x0080 8871 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_ALIGN 0 8872 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_BITS 1 8873 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_SHIFT 7 8874 8875 /* ln_device1 :: cl72_misc4_control :: rx_wclk_16_mode_sel [06:05] */ 8876 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_MASK 0x0060 8877 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_ALIGN 0 8878 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_BITS 2 8879 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_SHIFT 5 8880 8881 /* ln_device1 :: cl72_misc4_control :: rx_wclk33_mode_sel [04:03] */ 8882 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_MASK 0x0018 8883 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_ALIGN 0 8884 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_BITS 2 8885 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_SHIFT 3 8886 8887 /* ln_device1 :: cl72_misc4_control :: rx_wclk_cl72_rst_sw [02:02] */ 8888 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_MASK 0x0004 8889 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_ALIGN 0 8890 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_BITS 1 8891 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_SHIFT 2 8892 8893 /* ln_device1 :: cl72_misc4_control :: rx_wclk_cl72_ckgate_sw [01:01] */ 8894 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_MASK 0x0002 8895 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_ALIGN 0 8896 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_BITS 1 8897 #define PHY84328_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_SHIFT 1 8898 8899 /* ln_device1 :: cl72_misc4_control :: cl72_en_mask [00:00] */ 8900 #define PHY84328_DEV1_CL72_MISC4_CONTROL_CL72_EN_MASK_MASK 0x0001 8901 #define PHY84328_DEV1_CL72_MISC4_CONTROL_CL72_EN_MASK_ALIGN 0 8902 #define PHY84328_DEV1_CL72_MISC4_CONTROL_CL72_EN_MASK_BITS 1 8903 #define PHY84328_DEV1_CL72_MISC4_CONTROL_CL72_EN_MASK_SHIFT 0 8904 8905 8906 /**************************************************************************** 8907 * ln_device1 :: cl72_fault_register 8908 */ 8909 /* ln_device1 :: cl72_fault_register :: reserved0 [15:04] */ 8910 #define PHY84328_DEV1_CL72_FAULT_REGISTER_RESERVED0_MASK 0xfff0 8911 #define PHY84328_DEV1_CL72_FAULT_REGISTER_RESERVED0_ALIGN 0 8912 #define PHY84328_DEV1_CL72_FAULT_REGISTER_RESERVED0_BITS 12 8913 #define PHY84328_DEV1_CL72_FAULT_REGISTER_RESERVED0_SHIFT 4 8914 8915 /* ln_device1 :: cl72_fault_register :: cl72_frame_lock [03:03] */ 8916 #define PHY84328_DEV1_CL72_FAULT_REGISTER_CL72_FRAME_LOCK_MASK 0x0008 8917 #define PHY84328_DEV1_CL72_FAULT_REGISTER_CL72_FRAME_LOCK_ALIGN 0 8918 #define PHY84328_DEV1_CL72_FAULT_REGISTER_CL72_FRAME_LOCK_BITS 1 8919 #define PHY84328_DEV1_CL72_FAULT_REGISTER_CL72_FRAME_LOCK_SHIFT 3 8920 8921 /* ln_device1 :: cl72_fault_register :: micro_status_bit2 [02:02] */ 8922 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT2_MASK 0x0004 8923 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT2_ALIGN 0 8924 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT2_BITS 1 8925 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT2_SHIFT 2 8926 8927 /* ln_device1 :: cl72_fault_register :: micro_status_bit1 [01:01] */ 8928 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT1_MASK 0x0002 8929 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT1_ALIGN 0 8930 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT1_BITS 1 8931 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT1_SHIFT 1 8932 8933 /* ln_device1 :: cl72_fault_register :: micro_status_bit0 [00:00] */ 8934 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT0_MASK 0x0001 8935 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT0_ALIGN 0 8936 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT0_BITS 1 8937 #define PHY84328_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT0_SHIFT 0 8938 8939 8940 /**************************************************************************** 8941 * ln_device1 :: cl72_debug_1_register 8942 */ 8943 /* ln_device1 :: cl72_debug_1_register :: reserved0 [15:12] */ 8944 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_RESERVED0_MASK 0xf000 8945 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_RESERVED0_ALIGN 0 8946 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_RESERVED0_BITS 4 8947 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_RESERVED0_SHIFT 12 8948 8949 /* ln_device1 :: cl72_debug_1_register :: tap_max_val [11:06] */ 8950 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_MASK 0x0fc0 8951 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_ALIGN 0 8952 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_BITS 6 8953 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_SHIFT 6 8954 8955 /* ln_device1 :: cl72_debug_1_register :: tap_min_val [05:00] */ 8956 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_MASK 0x003f 8957 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_ALIGN 0 8958 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_BITS 6 8959 #define PHY84328_DEV1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_SHIFT 0 8960 8961 8962 /**************************************************************************** 8963 * ln_device1 :: cl72_debug_2_register 8964 */ 8965 /* ln_device1 :: cl72_debug_2_register :: pmd_data_swap [15:15] */ 8966 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_MASK 0x8000 8967 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_ALIGN 0 8968 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_BITS 1 8969 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_SHIFT 15 8970 8971 /* ln_device1 :: cl72_debug_2_register :: brk_ring_osc [14:14] */ 8972 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC_MASK 0x4000 8973 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC_ALIGN 0 8974 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC_BITS 1 8975 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC_SHIFT 14 8976 8977 /* ln_device1 :: cl72_debug_2_register :: strict_marker_chk [13:13] */ 8978 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_MASK 0x2000 8979 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_ALIGN 0 8980 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_BITS 1 8981 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_SHIFT 13 8982 8983 /* ln_device1 :: cl72_debug_2_register :: strict_dme_chk [12:12] */ 8984 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_MASK 0x1000 8985 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_ALIGN 0 8986 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_BITS 1 8987 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_SHIFT 12 8988 8989 /* ln_device1 :: cl72_debug_2_register :: dis_max_wait_timer [11:11] */ 8990 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_MASK 0x0800 8991 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_ALIGN 0 8992 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_BITS 1 8993 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_SHIFT 11 8994 8995 /* ln_device1 :: cl72_debug_2_register :: max_wait_timer_val [10:09] */ 8996 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_MASK 0x0600 8997 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_ALIGN 0 8998 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_BITS 2 8999 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_SHIFT 9 9000 9001 /* ln_device1 :: cl72_debug_2_register :: signal_det_force [08:08] */ 9002 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_MASK 0x0100 9003 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_ALIGN 0 9004 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_BITS 1 9005 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_SHIFT 8 9006 9007 /* ln_device1 :: cl72_debug_2_register :: tr_coarse_lock_force [07:07] */ 9008 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_MASK 0x0080 9009 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_ALIGN 0 9010 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_BITS 1 9011 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_SHIFT 7 9012 9013 /* ln_device1 :: cl72_debug_2_register :: clk_gate_force_ [06:06] */ 9014 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__MASK 0x0040 9015 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__ALIGN 0 9016 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__BITS 1 9017 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__SHIFT 6 9018 9019 /* ln_device1 :: cl72_debug_2_register :: clk_gate_forceval [05:05] */ 9020 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_MASK 0x0020 9021 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_ALIGN 0 9022 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_BITS 1 9023 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_SHIFT 5 9024 9025 /* ln_device1 :: cl72_debug_2_register :: bad_marker_cnt [04:02] */ 9026 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_MASK 0x001c 9027 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_ALIGN 0 9028 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_BITS 3 9029 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_SHIFT 2 9030 9031 /* ln_device1 :: cl72_debug_2_register :: good_marker_cnt [01:00] */ 9032 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_MASK 0x0003 9033 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_ALIGN 0 9034 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_BITS 2 9035 #define PHY84328_DEV1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_SHIFT 0 9036 9037 9038 /**************************************************************************** 9039 * ln_device1 :: cl72_debug_3_register 9040 */ 9041 /* ln_device1 :: cl72_debug_3_register :: signal_ok_force [15:15] */ 9042 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_MASK 0x8000 9043 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_ALIGN 0 9044 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_BITS 1 9045 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_SHIFT 15 9046 9047 /* ln_device1 :: cl72_debug_3_register :: ctrl_frame_dly [14:11] */ 9048 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_MASK 0x7800 9049 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_ALIGN 0 9050 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_BITS 4 9051 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_SHIFT 11 9052 9053 /* ln_device1 :: cl72_debug_3_register :: random_seed [10:00] */ 9054 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_MASK 0x07ff 9055 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_ALIGN 0 9056 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_BITS 11 9057 #define PHY84328_DEV1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_SHIFT 0 9058 9059 9060 /**************************************************************************** 9061 * ln_device1 :: cl72_debug_4_register 9062 */ 9063 /* ln_device1 :: cl72_debug_4_register :: reserved0 [15:14] */ 9064 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_RESERVED0_MASK 0xc000 9065 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_RESERVED0_ALIGN 0 9066 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_RESERVED0_BITS 2 9067 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_RESERVED0_SHIFT 14 9068 9069 /* ln_device1 :: cl72_debug_4_register :: brcm_mode_force [13:13] */ 9070 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_MASK 0x2000 9071 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_ALIGN 0 9072 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_BITS 1 9073 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_SHIFT 13 9074 9075 /* ln_device1 :: cl72_debug_4_register :: brcm_mode_forceval [12:12] */ 9076 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_MASK 0x1000 9077 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_ALIGN 0 9078 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_BITS 1 9079 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_SHIFT 12 9080 9081 /* ln_device1 :: cl72_debug_4_register :: v2_constraint_dis [11:11] */ 9082 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_MASK 0x0800 9083 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_ALIGN 0 9084 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_BITS 1 9085 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_SHIFT 11 9086 9087 /* ln_device1 :: cl72_debug_4_register :: tap_v2_val [10:06] */ 9088 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_MASK 0x07c0 9089 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_ALIGN 0 9090 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_BITS 5 9091 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_SHIFT 6 9092 9093 /* ln_device1 :: cl72_debug_4_register :: micro_reg_reset [05:05] */ 9094 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_MASK 0x0020 9095 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_ALIGN 0 9096 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_BITS 1 9097 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_SHIFT 5 9098 9099 /* ln_device1 :: cl72_debug_4_register :: sigdet_forceval [04:04] */ 9100 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_MASK 0x0010 9101 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_ALIGN 0 9102 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_BITS 1 9103 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_SHIFT 4 9104 9105 /* ln_device1 :: cl72_debug_4_register :: sigdet_force [03:03] */ 9106 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_MASK 0x0008 9107 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_ALIGN 0 9108 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_BITS 1 9109 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_SHIFT 3 9110 9111 /* ln_device1 :: cl72_debug_4_register :: trnpat_en_forceval [02:02] */ 9112 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_MASK 0x0004 9113 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_ALIGN 0 9114 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_BITS 1 9115 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_SHIFT 2 9116 9117 /* ln_device1 :: cl72_debug_4_register :: trnpat_en_force [01:01] */ 9118 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_MASK 0x0002 9119 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_ALIGN 0 9120 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_BITS 1 9121 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_SHIFT 1 9122 9123 /* ln_device1 :: cl72_debug_4_register :: ppm_offset_en [00:00] */ 9124 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_MASK 0x0001 9125 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_ALIGN 0 9126 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_BITS 1 9127 #define PHY84328_DEV1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_SHIFT 0 9128 9129 9130 /**************************************************************************** 9131 * ln_device1_userLanesCtrl_Registers 9132 */ 9133 /**************************************************************************** 9134 * ln_device1 :: xgxsControl 9135 */ 9136 /* ln_device1 :: xgxsControl :: pgen_en [15:15] */ 9137 #define PHY84328_DEV1_XGXSCONTROL_PGEN_EN_MASK 0x8000 9138 #define PHY84328_DEV1_XGXSCONTROL_PGEN_EN_ALIGN 0 9139 #define PHY84328_DEV1_XGXSCONTROL_PGEN_EN_BITS 1 9140 #define PHY84328_DEV1_XGXSCONTROL_PGEN_EN_SHIFT 15 9141 9142 /* ln_device1 :: xgxsControl :: pcmp_en [14:14] */ 9143 #define PHY84328_DEV1_XGXSCONTROL_PCMP_EN_MASK 0x4000 9144 #define PHY84328_DEV1_XGXSCONTROL_PCMP_EN_ALIGN 0 9145 #define PHY84328_DEV1_XGXSCONTROL_PCMP_EN_BITS 1 9146 #define PHY84328_DEV1_XGXSCONTROL_PCMP_EN_SHIFT 14 9147 9148 /* ln_device1 :: xgxsControl :: start_sequencer [13:13] */ 9149 #define PHY84328_DEV1_XGXSCONTROL_START_SEQUENCER_MASK 0x2000 9150 #define PHY84328_DEV1_XGXSCONTROL_START_SEQUENCER_ALIGN 0 9151 #define PHY84328_DEV1_XGXSCONTROL_START_SEQUENCER_BITS 1 9152 #define PHY84328_DEV1_XGXSCONTROL_START_SEQUENCER_SHIFT 13 9153 9154 /* ln_device1 :: xgxsControl :: reset_anlg [12:12] */ 9155 #define PHY84328_DEV1_XGXSCONTROL_RESET_ANLG_MASK 0x1000 9156 #define PHY84328_DEV1_XGXSCONTROL_RESET_ANLG_ALIGN 0 9157 #define PHY84328_DEV1_XGXSCONTROL_RESET_ANLG_BITS 1 9158 #define PHY84328_DEV1_XGXSCONTROL_RESET_ANLG_SHIFT 12 9159 9160 /* ln_device1 :: xgxsControl :: mode_10g [11:08] */ 9161 #define PHY84328_DEV1_XGXSCONTROL_MODE_10G_MASK 0x0f00 9162 #define PHY84328_DEV1_XGXSCONTROL_MODE_10G_ALIGN 0 9163 #define PHY84328_DEV1_XGXSCONTROL_MODE_10G_BITS 4 9164 #define PHY84328_DEV1_XGXSCONTROL_MODE_10G_SHIFT 8 9165 9166 /* ln_device1 :: xgxsControl :: pll_bypass [07:07] */ 9167 #define PHY84328_DEV1_XGXSCONTROL_PLL_BYPASS_MASK 0x0080 9168 #define PHY84328_DEV1_XGXSCONTROL_PLL_BYPASS_ALIGN 0 9169 #define PHY84328_DEV1_XGXSCONTROL_PLL_BYPASS_BITS 1 9170 #define PHY84328_DEV1_XGXSCONTROL_PLL_BYPASS_SHIFT 7 9171 9172 /* ln_device1 :: xgxsControl :: rloop [06:06] */ 9173 #define PHY84328_DEV1_XGXSCONTROL_RLOOP_MASK 0x0040 9174 #define PHY84328_DEV1_XGXSCONTROL_RLOOP_ALIGN 0 9175 #define PHY84328_DEV1_XGXSCONTROL_RLOOP_BITS 1 9176 #define PHY84328_DEV1_XGXSCONTROL_RLOOP_SHIFT 6 9177 9178 /* ln_device1 :: xgxsControl :: reserved0 [05:05] */ 9179 #define PHY84328_DEV1_XGXSCONTROL_RESERVED0_MASK 0x0020 9180 #define PHY84328_DEV1_XGXSCONTROL_RESERVED0_ALIGN 0 9181 #define PHY84328_DEV1_XGXSCONTROL_RESERVED0_BITS 1 9182 #define PHY84328_DEV1_XGXSCONTROL_RESERVED0_SHIFT 5 9183 9184 /* ln_device1 :: xgxsControl :: mdio_cont_en [04:04] */ 9185 #define PHY84328_DEV1_XGXSCONTROL_MDIO_CONT_EN_MASK 0x0010 9186 #define PHY84328_DEV1_XGXSCONTROL_MDIO_CONT_EN_ALIGN 0 9187 #define PHY84328_DEV1_XGXSCONTROL_MDIO_CONT_EN_BITS 1 9188 #define PHY84328_DEV1_XGXSCONTROL_MDIO_CONT_EN_SHIFT 4 9189 9190 /* ln_device1 :: xgxsControl :: cdet_en [03:03] */ 9191 #define PHY84328_DEV1_XGXSCONTROL_CDET_EN_MASK 0x0008 9192 #define PHY84328_DEV1_XGXSCONTROL_CDET_EN_ALIGN 0 9193 #define PHY84328_DEV1_XGXSCONTROL_CDET_EN_BITS 1 9194 #define PHY84328_DEV1_XGXSCONTROL_CDET_EN_SHIFT 3 9195 9196 /* ln_device1 :: xgxsControl :: eden [02:02] */ 9197 #define PHY84328_DEV1_XGXSCONTROL_EDEN_MASK 0x0004 9198 #define PHY84328_DEV1_XGXSCONTROL_EDEN_ALIGN 0 9199 #define PHY84328_DEV1_XGXSCONTROL_EDEN_BITS 1 9200 #define PHY84328_DEV1_XGXSCONTROL_EDEN_SHIFT 2 9201 9202 /* ln_device1 :: xgxsControl :: afrst_en [01:01] */ 9203 #define PHY84328_DEV1_XGXSCONTROL_AFRST_EN_MASK 0x0002 9204 #define PHY84328_DEV1_XGXSCONTROL_AFRST_EN_ALIGN 0 9205 #define PHY84328_DEV1_XGXSCONTROL_AFRST_EN_BITS 1 9206 #define PHY84328_DEV1_XGXSCONTROL_AFRST_EN_SHIFT 1 9207 9208 /* ln_device1 :: xgxsControl :: txcko_div [00:00] */ 9209 #define PHY84328_DEV1_XGXSCONTROL_TXCKO_DIV_MASK 0x0001 9210 #define PHY84328_DEV1_XGXSCONTROL_TXCKO_DIV_ALIGN 0 9211 #define PHY84328_DEV1_XGXSCONTROL_TXCKO_DIV_BITS 1 9212 #define PHY84328_DEV1_XGXSCONTROL_TXCKO_DIV_SHIFT 0 9213 9214 9215 /**************************************************************************** 9216 * ln_device1 :: xgxsStatus 9217 */ 9218 /* ln_device1 :: xgxsStatus :: status_en [15:15] */ 9219 #define PHY84328_DEV1_XGXSSTATUS_STATUS_EN_MASK 0x8000 9220 #define PHY84328_DEV1_XGXSSTATUS_STATUS_EN_ALIGN 0 9221 #define PHY84328_DEV1_XGXSSTATUS_STATUS_EN_BITS 1 9222 #define PHY84328_DEV1_XGXSSTATUS_STATUS_EN_SHIFT 15 9223 9224 /* ln_device1 :: xgxsStatus :: reserved0 [14:12] */ 9225 #define PHY84328_DEV1_XGXSSTATUS_RESERVED0_MASK 0x7000 9226 #define PHY84328_DEV1_XGXSSTATUS_RESERVED0_ALIGN 0 9227 #define PHY84328_DEV1_XGXSSTATUS_RESERVED0_BITS 3 9228 #define PHY84328_DEV1_XGXSSTATUS_RESERVED0_SHIFT 12 9229 9230 /* ln_device1 :: xgxsStatus :: txpll_lock [11:11] */ 9231 #define PHY84328_DEV1_XGXSSTATUS_TXPLL_LOCK_MASK 0x0800 9232 #define PHY84328_DEV1_XGXSSTATUS_TXPLL_LOCK_ALIGN 0 9233 #define PHY84328_DEV1_XGXSSTATUS_TXPLL_LOCK_BITS 1 9234 #define PHY84328_DEV1_XGXSSTATUS_TXPLL_LOCK_SHIFT 11 9235 9236 /* ln_device1 :: xgxsStatus :: reserved1 [10:04] */ 9237 #define PHY84328_DEV1_XGXSSTATUS_RESERVED1_MASK 0x07f0 9238 #define PHY84328_DEV1_XGXSSTATUS_RESERVED1_ALIGN 0 9239 #define PHY84328_DEV1_XGXSSTATUS_RESERVED1_BITS 7 9240 #define PHY84328_DEV1_XGXSSTATUS_RESERVED1_SHIFT 4 9241 9242 /* ln_device1 :: xgxsStatus :: pll_mode_afe [03:03] */ 9243 #define PHY84328_DEV1_XGXSSTATUS_PLL_MODE_AFE_MASK 0x0008 9244 #define PHY84328_DEV1_XGXSSTATUS_PLL_MODE_AFE_ALIGN 0 9245 #define PHY84328_DEV1_XGXSSTATUS_PLL_MODE_AFE_BITS 1 9246 #define PHY84328_DEV1_XGXSSTATUS_PLL_MODE_AFE_SHIFT 3 9247 9248 /* ln_device1 :: xgxsStatus :: reserved2 [02:00] */ 9249 #define PHY84328_DEV1_XGXSSTATUS_RESERVED2_MASK 0x0007 9250 #define PHY84328_DEV1_XGXSSTATUS_RESERVED2_ALIGN 0 9251 #define PHY84328_DEV1_XGXSSTATUS_RESERVED2_BITS 3 9252 #define PHY84328_DEV1_XGXSSTATUS_RESERVED2_SHIFT 0 9253 9254 9255 /**************************************************************************** 9256 * ln_device1 :: miscControl1 9257 */ 9258 /* ln_device1 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */ 9259 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK 0x8000 9260 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN 0 9261 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS 1 9262 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT 15 9263 9264 /* ln_device1 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */ 9265 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK 0x4000 9266 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN 0 9267 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS 1 9268 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT 14 9269 9270 /* ln_device1 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */ 9271 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK 0x2000 9272 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN 0 9273 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS 1 9274 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT 13 9275 9276 /* ln_device1 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */ 9277 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK 0x1000 9278 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN 0 9279 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS 1 9280 #define PHY84328_DEV1_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT 12 9281 9282 /* ln_device1 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 9283 #define PHY84328_DEV1_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 9284 #define PHY84328_DEV1_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 9285 #define PHY84328_DEV1_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 9286 #define PHY84328_DEV1_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 9287 9288 /* ln_device1 :: miscControl1 :: reserved0 [10:05] */ 9289 #define PHY84328_DEV1_MISCCONTROL1_RESERVED0_MASK 0x07e0 9290 #define PHY84328_DEV1_MISCCONTROL1_RESERVED0_ALIGN 0 9291 #define PHY84328_DEV1_MISCCONTROL1_RESERVED0_BITS 6 9292 #define PHY84328_DEV1_MISCCONTROL1_RESERVED0_SHIFT 5 9293 9294 /* ln_device1 :: miscControl1 :: force_div5_for_lxck25 [04:04] */ 9295 #define PHY84328_DEV1_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK 0x0010 9296 #define PHY84328_DEV1_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN 0 9297 #define PHY84328_DEV1_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS 1 9298 #define PHY84328_DEV1_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT 4 9299 9300 /* ln_device1 :: miscControl1 :: reserved1 [03:03] */ 9301 #define PHY84328_DEV1_MISCCONTROL1_RESERVED1_MASK 0x0008 9302 #define PHY84328_DEV1_MISCCONTROL1_RESERVED1_ALIGN 0 9303 #define PHY84328_DEV1_MISCCONTROL1_RESERVED1_BITS 1 9304 #define PHY84328_DEV1_MISCCONTROL1_RESERVED1_SHIFT 3 9305 9306 /* ln_device1 :: miscControl1 :: invert_rx_sigdet [02:02] */ 9307 #define PHY84328_DEV1_MISCCONTROL1_INVERT_RX_SIGDET_MASK 0x0004 9308 #define PHY84328_DEV1_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN 0 9309 #define PHY84328_DEV1_MISCCONTROL1_INVERT_RX_SIGDET_BITS 1 9310 #define PHY84328_DEV1_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT 2 9311 9312 /* ln_device1 :: miscControl1 :: ieee_blksel_autodet [01:01] */ 9313 #define PHY84328_DEV1_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK 0x0002 9314 #define PHY84328_DEV1_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN 0 9315 #define PHY84328_DEV1_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS 1 9316 #define PHY84328_DEV1_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT 1 9317 9318 /* ln_device1 :: miscControl1 :: ieee_blksel_val [00:00] */ 9319 #define PHY84328_DEV1_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK 0x0001 9320 #define PHY84328_DEV1_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN 0 9321 #define PHY84328_DEV1_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS 1 9322 #define PHY84328_DEV1_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT 0 9323 9324 9325 /**************************************************************************** 9326 * ln_device1 :: laneCtrl2 9327 */ 9328 /* ln_device1 :: laneCtrl2 :: reserved0 [15:08] */ 9329 #define PHY84328_DEV1_LANECTRL2_RESERVED0_MASK 0xff00 9330 #define PHY84328_DEV1_LANECTRL2_RESERVED0_ALIGN 0 9331 #define PHY84328_DEV1_LANECTRL2_RESERVED0_BITS 8 9332 #define PHY84328_DEV1_LANECTRL2_RESERVED0_SHIFT 8 9333 9334 /* ln_device1 :: laneCtrl2 :: rloop1g [07:04] */ 9335 #define PHY84328_DEV1_LANECTRL2_RLOOP1G_MASK 0x00f0 9336 #define PHY84328_DEV1_LANECTRL2_RLOOP1G_ALIGN 0 9337 #define PHY84328_DEV1_LANECTRL2_RLOOP1G_BITS 4 9338 #define PHY84328_DEV1_LANECTRL2_RLOOP1G_SHIFT 4 9339 9340 /* ln_device1 :: laneCtrl2 :: reserved1 [03:00] */ 9341 #define PHY84328_DEV1_LANECTRL2_RESERVED1_MASK 0x000f 9342 #define PHY84328_DEV1_LANECTRL2_RESERVED1_ALIGN 0 9343 #define PHY84328_DEV1_LANECTRL2_RESERVED1_BITS 4 9344 #define PHY84328_DEV1_LANECTRL2_RESERVED1_SHIFT 0 9345 9346 9347 /**************************************************************************** 9348 * ln_device1 :: laneCtrl3 9349 */ 9350 /* ln_device1 :: laneCtrl3 :: lock_ref [15:12] */ 9351 #define PHY84328_DEV1_LANECTRL3_LOCK_REF_MASK 0xf000 9352 #define PHY84328_DEV1_LANECTRL3_LOCK_REF_ALIGN 0 9353 #define PHY84328_DEV1_LANECTRL3_LOCK_REF_BITS 4 9354 #define PHY84328_DEV1_LANECTRL3_LOCK_REF_SHIFT 12 9355 9356 /* ln_device1 :: laneCtrl3 :: pwrdwn_force [11:11] */ 9357 #define PHY84328_DEV1_LANECTRL3_PWRDWN_FORCE_MASK 0x0800 9358 #define PHY84328_DEV1_LANECTRL3_PWRDWN_FORCE_ALIGN 0 9359 #define PHY84328_DEV1_LANECTRL3_PWRDWN_FORCE_BITS 1 9360 #define PHY84328_DEV1_LANECTRL3_PWRDWN_FORCE_SHIFT 11 9361 9362 /* ln_device1 :: laneCtrl3 :: lock_ref_en [10:10] */ 9363 #define PHY84328_DEV1_LANECTRL3_LOCK_REF_EN_MASK 0x0400 9364 #define PHY84328_DEV1_LANECTRL3_LOCK_REF_EN_ALIGN 0 9365 #define PHY84328_DEV1_LANECTRL3_LOCK_REF_EN_BITS 1 9366 #define PHY84328_DEV1_LANECTRL3_LOCK_REF_EN_SHIFT 10 9367 9368 /* ln_device1 :: laneCtrl3 :: pwrdwn10g_pll_dis [09:09] */ 9369 #define PHY84328_DEV1_LANECTRL3_PWRDWN10G_PLL_DIS_MASK 0x0200 9370 #define PHY84328_DEV1_LANECTRL3_PWRDWN10G_PLL_DIS_ALIGN 0 9371 #define PHY84328_DEV1_LANECTRL3_PWRDWN10G_PLL_DIS_BITS 1 9372 #define PHY84328_DEV1_LANECTRL3_PWRDWN10G_PLL_DIS_SHIFT 9 9373 9374 /* ln_device1 :: laneCtrl3 :: pwrdwn_pll [08:08] */ 9375 #define PHY84328_DEV1_LANECTRL3_PWRDWN_PLL_MASK 0x0100 9376 #define PHY84328_DEV1_LANECTRL3_PWRDWN_PLL_ALIGN 0 9377 #define PHY84328_DEV1_LANECTRL3_PWRDWN_PLL_BITS 1 9378 #define PHY84328_DEV1_LANECTRL3_PWRDWN_PLL_SHIFT 8 9379 9380 /* ln_device1 :: laneCtrl3 :: pwrdn_tx [07:04] */ 9381 #define PHY84328_DEV1_LANECTRL3_PWRDN_TX_MASK 0x00f0 9382 #define PHY84328_DEV1_LANECTRL3_PWRDN_TX_ALIGN 0 9383 #define PHY84328_DEV1_LANECTRL3_PWRDN_TX_BITS 4 9384 #define PHY84328_DEV1_LANECTRL3_PWRDN_TX_SHIFT 4 9385 9386 /* ln_device1 :: laneCtrl3 :: pwrdn_rx [03:00] */ 9387 #define PHY84328_DEV1_LANECTRL3_PWRDN_RX_MASK 0x000f 9388 #define PHY84328_DEV1_LANECTRL3_PWRDN_RX_ALIGN 0 9389 #define PHY84328_DEV1_LANECTRL3_PWRDN_RX_BITS 4 9390 #define PHY84328_DEV1_LANECTRL3_PWRDN_RX_SHIFT 0 9391 9392 9393 /**************************************************************************** 9394 * ln_device1 :: lanePrbs 9395 */ 9396 /* ln_device1 :: lanePrbs :: prbs_en3 [15:15] */ 9397 #define PHY84328_DEV1_LANEPRBS_PRBS_EN3_MASK 0x8000 9398 #define PHY84328_DEV1_LANEPRBS_PRBS_EN3_ALIGN 0 9399 #define PHY84328_DEV1_LANEPRBS_PRBS_EN3_BITS 1 9400 #define PHY84328_DEV1_LANEPRBS_PRBS_EN3_SHIFT 15 9401 9402 /* ln_device1 :: lanePrbs :: prbs_inv3 [14:14] */ 9403 #define PHY84328_DEV1_LANEPRBS_PRBS_INV3_MASK 0x4000 9404 #define PHY84328_DEV1_LANEPRBS_PRBS_INV3_ALIGN 0 9405 #define PHY84328_DEV1_LANEPRBS_PRBS_INV3_BITS 1 9406 #define PHY84328_DEV1_LANEPRBS_PRBS_INV3_SHIFT 14 9407 9408 /* ln_device1 :: lanePrbs :: prbs_order3 [13:12] */ 9409 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER3_MASK 0x3000 9410 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER3_ALIGN 0 9411 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER3_BITS 2 9412 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER3_SHIFT 12 9413 9414 /* ln_device1 :: lanePrbs :: prbs_en2 [11:11] */ 9415 #define PHY84328_DEV1_LANEPRBS_PRBS_EN2_MASK 0x0800 9416 #define PHY84328_DEV1_LANEPRBS_PRBS_EN2_ALIGN 0 9417 #define PHY84328_DEV1_LANEPRBS_PRBS_EN2_BITS 1 9418 #define PHY84328_DEV1_LANEPRBS_PRBS_EN2_SHIFT 11 9419 9420 /* ln_device1 :: lanePrbs :: prbs_inv2 [10:10] */ 9421 #define PHY84328_DEV1_LANEPRBS_PRBS_INV2_MASK 0x0400 9422 #define PHY84328_DEV1_LANEPRBS_PRBS_INV2_ALIGN 0 9423 #define PHY84328_DEV1_LANEPRBS_PRBS_INV2_BITS 1 9424 #define PHY84328_DEV1_LANEPRBS_PRBS_INV2_SHIFT 10 9425 9426 /* ln_device1 :: lanePrbs :: prbs_order2 [09:08] */ 9427 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER2_MASK 0x0300 9428 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER2_ALIGN 0 9429 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER2_BITS 2 9430 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER2_SHIFT 8 9431 9432 /* ln_device1 :: lanePrbs :: prbs_en1 [07:07] */ 9433 #define PHY84328_DEV1_LANEPRBS_PRBS_EN1_MASK 0x0080 9434 #define PHY84328_DEV1_LANEPRBS_PRBS_EN1_ALIGN 0 9435 #define PHY84328_DEV1_LANEPRBS_PRBS_EN1_BITS 1 9436 #define PHY84328_DEV1_LANEPRBS_PRBS_EN1_SHIFT 7 9437 9438 /* ln_device1 :: lanePrbs :: prbs_inv1 [06:06] */ 9439 #define PHY84328_DEV1_LANEPRBS_PRBS_INV1_MASK 0x0040 9440 #define PHY84328_DEV1_LANEPRBS_PRBS_INV1_ALIGN 0 9441 #define PHY84328_DEV1_LANEPRBS_PRBS_INV1_BITS 1 9442 #define PHY84328_DEV1_LANEPRBS_PRBS_INV1_SHIFT 6 9443 9444 /* ln_device1 :: lanePrbs :: prbs_order1 [05:04] */ 9445 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER1_MASK 0x0030 9446 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER1_ALIGN 0 9447 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER1_BITS 2 9448 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER1_SHIFT 4 9449 9450 /* ln_device1 :: lanePrbs :: prbs_en0 [03:03] */ 9451 #define PHY84328_DEV1_LANEPRBS_PRBS_EN0_MASK 0x0008 9452 #define PHY84328_DEV1_LANEPRBS_PRBS_EN0_ALIGN 0 9453 #define PHY84328_DEV1_LANEPRBS_PRBS_EN0_BITS 1 9454 #define PHY84328_DEV1_LANEPRBS_PRBS_EN0_SHIFT 3 9455 9456 /* ln_device1 :: lanePrbs :: prbs_inv0 [02:02] */ 9457 #define PHY84328_DEV1_LANEPRBS_PRBS_INV0_MASK 0x0004 9458 #define PHY84328_DEV1_LANEPRBS_PRBS_INV0_ALIGN 0 9459 #define PHY84328_DEV1_LANEPRBS_PRBS_INV0_BITS 1 9460 #define PHY84328_DEV1_LANEPRBS_PRBS_INV0_SHIFT 2 9461 9462 /* ln_device1 :: lanePrbs :: prbs_order0 [01:00] */ 9463 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER0_MASK 0x0003 9464 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER0_ALIGN 0 9465 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER0_BITS 2 9466 #define PHY84328_DEV1_LANEPRBS_PRBS_ORDER0_SHIFT 0 9467 9468 9469 /**************************************************************************** 9470 * ln_device1 :: laneCtrl 9471 */ 9472 /* ln_device1 :: laneCtrl :: reserved0 [15:11] */ 9473 #define PHY84328_DEV1_LANECTRL_RESERVED0_MASK 0xf800 9474 #define PHY84328_DEV1_LANECTRL_RESERVED0_ALIGN 0 9475 #define PHY84328_DEV1_LANECTRL_RESERVED0_BITS 5 9476 #define PHY84328_DEV1_LANECTRL_RESERVED0_SHIFT 11 9477 9478 /* ln_device1 :: laneCtrl :: pwrdn_ext_dis [10:10] */ 9479 #define PHY84328_DEV1_LANECTRL_PWRDN_EXT_DIS_MASK 0x0400 9480 #define PHY84328_DEV1_LANECTRL_PWRDN_EXT_DIS_ALIGN 0 9481 #define PHY84328_DEV1_LANECTRL_PWRDN_EXT_DIS_BITS 1 9482 #define PHY84328_DEV1_LANECTRL_PWRDN_EXT_DIS_SHIFT 10 9483 9484 /* ln_device1 :: laneCtrl :: pwrdn_safe_dis [09:09] */ 9485 #define PHY84328_DEV1_LANECTRL_PWRDN_SAFE_DIS_MASK 0x0200 9486 #define PHY84328_DEV1_LANECTRL_PWRDN_SAFE_DIS_ALIGN 0 9487 #define PHY84328_DEV1_LANECTRL_PWRDN_SAFE_DIS_BITS 1 9488 #define PHY84328_DEV1_LANECTRL_PWRDN_SAFE_DIS_SHIFT 9 9489 9490 /* ln_device1 :: laneCtrl :: pwrdwn_clks_en [08:08] */ 9491 #define PHY84328_DEV1_LANECTRL_PWRDWN_CLKS_EN_MASK 0x0100 9492 #define PHY84328_DEV1_LANECTRL_PWRDWN_CLKS_EN_ALIGN 0 9493 #define PHY84328_DEV1_LANECTRL_PWRDWN_CLKS_EN_BITS 1 9494 #define PHY84328_DEV1_LANECTRL_PWRDWN_CLKS_EN_SHIFT 8 9495 9496 /* ln_device1 :: laneCtrl :: rxSeqStart_ext_dis [07:07] */ 9497 #define PHY84328_DEV1_LANECTRL_RXSEQSTART_EXT_DIS_MASK 0x0080 9498 #define PHY84328_DEV1_LANECTRL_RXSEQSTART_EXT_DIS_ALIGN 0 9499 #define PHY84328_DEV1_LANECTRL_RXSEQSTART_EXT_DIS_BITS 1 9500 #define PHY84328_DEV1_LANECTRL_RXSEQSTART_EXT_DIS_SHIFT 7 9501 9502 /* ln_device1 :: laneCtrl :: pll_lock_rstb_r [06:06] */ 9503 #define PHY84328_DEV1_LANECTRL_PLL_LOCK_RSTB_R_MASK 0x0040 9504 #define PHY84328_DEV1_LANECTRL_PLL_LOCK_RSTB_R_ALIGN 0 9505 #define PHY84328_DEV1_LANECTRL_PLL_LOCK_RSTB_R_BITS 1 9506 #define PHY84328_DEV1_LANECTRL_PLL_LOCK_RSTB_R_SHIFT 6 9507 9508 /* ln_device1 :: laneCtrl :: lfck_bypass [05:05] */ 9509 #define PHY84328_DEV1_LANECTRL_LFCK_BYPASS_MASK 0x0020 9510 #define PHY84328_DEV1_LANECTRL_LFCK_BYPASS_ALIGN 0 9511 #define PHY84328_DEV1_LANECTRL_LFCK_BYPASS_BITS 1 9512 #define PHY84328_DEV1_LANECTRL_LFCK_BYPASS_SHIFT 5 9513 9514 /* ln_device1 :: laneCtrl :: rx_snoop_en [04:04] */ 9515 #define PHY84328_DEV1_LANECTRL_RX_SNOOP_EN_MASK 0x0010 9516 #define PHY84328_DEV1_LANECTRL_RX_SNOOP_EN_ALIGN 0 9517 #define PHY84328_DEV1_LANECTRL_RX_SNOOP_EN_BITS 1 9518 #define PHY84328_DEV1_LANECTRL_RX_SNOOP_EN_SHIFT 4 9519 9520 /* ln_device1 :: laneCtrl :: mode_10g_snoop [03:00] */ 9521 #define PHY84328_DEV1_LANECTRL_MODE_10G_SNOOP_MASK 0x000f 9522 #define PHY84328_DEV1_LANECTRL_MODE_10G_SNOOP_ALIGN 0 9523 #define PHY84328_DEV1_LANECTRL_MODE_10G_SNOOP_BITS 4 9524 #define PHY84328_DEV1_LANECTRL_MODE_10G_SNOOP_SHIFT 0 9525 9526 9527 /**************************************************************************** 9528 * ln_device1 :: TestModeLane 9529 */ 9530 /* ln_device1 :: TestModeLane :: eee_fast_timer_en [15:15] */ 9531 #define PHY84328_DEV1_TESTMODELANE_EEE_FAST_TIMER_EN_MASK 0x8000 9532 #define PHY84328_DEV1_TESTMODELANE_EEE_FAST_TIMER_EN_ALIGN 0 9533 #define PHY84328_DEV1_TESTMODELANE_EEE_FAST_TIMER_EN_BITS 1 9534 #define PHY84328_DEV1_TESTMODELANE_EEE_FAST_TIMER_EN_SHIFT 15 9535 9536 /* ln_device1 :: TestModeLane :: eee_gateclk_en [14:14] */ 9537 #define PHY84328_DEV1_TESTMODELANE_EEE_GATECLK_EN_MASK 0x4000 9538 #define PHY84328_DEV1_TESTMODELANE_EEE_GATECLK_EN_ALIGN 0 9539 #define PHY84328_DEV1_TESTMODELANE_EEE_GATECLK_EN_BITS 1 9540 #define PHY84328_DEV1_TESTMODELANE_EEE_GATECLK_EN_SHIFT 14 9541 9542 /* ln_device1 :: TestModeLane :: eee_gateoutclk_en [13:13] */ 9543 #define PHY84328_DEV1_TESTMODELANE_EEE_GATEOUTCLK_EN_MASK 0x2000 9544 #define PHY84328_DEV1_TESTMODELANE_EEE_GATEOUTCLK_EN_ALIGN 0 9545 #define PHY84328_DEV1_TESTMODELANE_EEE_GATEOUTCLK_EN_BITS 1 9546 #define PHY84328_DEV1_TESTMODELANE_EEE_GATEOUTCLK_EN_SHIFT 13 9547 9548 /* ln_device1 :: TestModeLane :: reserved0 [12:11] */ 9549 #define PHY84328_DEV1_TESTMODELANE_RESERVED0_MASK 0x1800 9550 #define PHY84328_DEV1_TESTMODELANE_RESERVED0_ALIGN 0 9551 #define PHY84328_DEV1_TESTMODELANE_RESERVED0_BITS 2 9552 #define PHY84328_DEV1_TESTMODELANE_RESERVED0_SHIFT 11 9553 9554 /* ln_device1 :: TestModeLane :: indck_mode_en_rx_force [10:10] */ 9555 #define PHY84328_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_MASK 0x0400 9556 #define PHY84328_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_ALIGN 0 9557 #define PHY84328_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_BITS 1 9558 #define PHY84328_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_SHIFT 10 9559 9560 /* ln_device1 :: TestModeLane :: indck_mode_en_rx_val [09:09] */ 9561 #define PHY84328_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_VAL_MASK 0x0200 9562 #define PHY84328_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_VAL_ALIGN 0 9563 #define PHY84328_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_VAL_BITS 1 9564 #define PHY84328_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_VAL_SHIFT 9 9565 9566 /* ln_device1 :: TestModeLane :: use_cl82en_cya [08:08] */ 9567 #define PHY84328_DEV1_TESTMODELANE_USE_CL82EN_CYA_MASK 0x0100 9568 #define PHY84328_DEV1_TESTMODELANE_USE_CL82EN_CYA_ALIGN 0 9569 #define PHY84328_DEV1_TESTMODELANE_USE_CL82EN_CYA_BITS 1 9570 #define PHY84328_DEV1_TESTMODELANE_USE_CL82EN_CYA_SHIFT 8 9571 9572 /* ln_device1 :: TestModeLane :: txfifo_bypass [07:07] */ 9573 #define PHY84328_DEV1_TESTMODELANE_TXFIFO_BYPASS_MASK 0x0080 9574 #define PHY84328_DEV1_TESTMODELANE_TXFIFO_BYPASS_ALIGN 0 9575 #define PHY84328_DEV1_TESTMODELANE_TXFIFO_BYPASS_BITS 1 9576 #define PHY84328_DEV1_TESTMODELANE_TXFIFO_BYPASS_SHIFT 7 9577 9578 /* ln_device1 :: TestModeLane :: reserved1 [06:06] */ 9579 #define PHY84328_DEV1_TESTMODELANE_RESERVED1_MASK 0x0040 9580 #define PHY84328_DEV1_TESTMODELANE_RESERVED1_ALIGN 0 9581 #define PHY84328_DEV1_TESTMODELANE_RESERVED1_BITS 1 9582 #define PHY84328_DEV1_TESTMODELANE_RESERVED1_SHIFT 6 9583 9584 /* ln_device1 :: TestModeLane :: mode_change_rst_disable_for_tx [05:05] */ 9585 #define PHY84328_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_TX_MASK 0x0020 9586 #define PHY84328_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_TX_ALIGN 0 9587 #define PHY84328_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_TX_BITS 1 9588 #define PHY84328_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_TX_SHIFT 5 9589 9590 /* ln_device1 :: TestModeLane :: mode_change_rst_disable_for_rx [04:04] */ 9591 #define PHY84328_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_RX_MASK 0x0010 9592 #define PHY84328_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_RX_ALIGN 0 9593 #define PHY84328_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_RX_BITS 1 9594 #define PHY84328_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_RX_SHIFT 4 9595 9596 /* ln_device1 :: TestModeLane :: reserved2 [03:00] */ 9597 #define PHY84328_DEV1_TESTMODELANE_RESERVED2_MASK 0x000f 9598 #define PHY84328_DEV1_TESTMODELANE_RESERVED2_ALIGN 0 9599 #define PHY84328_DEV1_TESTMODELANE_RESERVED2_BITS 4 9600 #define PHY84328_DEV1_TESTMODELANE_RESERVED2_SHIFT 0 9601 9602 9603 /**************************************************************************** 9604 * ln_device1 :: laneReset 9605 */ 9606 /* ln_device1 :: laneReset :: reset_mdio [15:15] */ 9607 #define PHY84328_DEV1_LANERESET_RESET_MDIO_MASK 0x8000 9608 #define PHY84328_DEV1_LANERESET_RESET_MDIO_ALIGN 0 9609 #define PHY84328_DEV1_LANERESET_RESET_MDIO_BITS 1 9610 #define PHY84328_DEV1_LANERESET_RESET_MDIO_SHIFT 15 9611 9612 /* ln_device1 :: laneReset :: reserved0 [14:09] */ 9613 #define PHY84328_DEV1_LANERESET_RESERVED0_MASK 0x7e00 9614 #define PHY84328_DEV1_LANERESET_RESERVED0_ALIGN 0 9615 #define PHY84328_DEV1_LANERESET_RESERVED0_BITS 6 9616 #define PHY84328_DEV1_LANERESET_RESERVED0_SHIFT 9 9617 9618 /* ln_device1 :: laneReset :: reset_pll [08:08] */ 9619 #define PHY84328_DEV1_LANERESET_RESET_PLL_MASK 0x0100 9620 #define PHY84328_DEV1_LANERESET_RESET_PLL_ALIGN 0 9621 #define PHY84328_DEV1_LANERESET_RESET_PLL_BITS 1 9622 #define PHY84328_DEV1_LANERESET_RESET_PLL_SHIFT 8 9623 9624 /* ln_device1 :: laneReset :: reset_tx [07:04] */ 9625 #define PHY84328_DEV1_LANERESET_RESET_TX_MASK 0x00f0 9626 #define PHY84328_DEV1_LANERESET_RESET_TX_ALIGN 0 9627 #define PHY84328_DEV1_LANERESET_RESET_TX_BITS 4 9628 #define PHY84328_DEV1_LANERESET_RESET_TX_SHIFT 4 9629 9630 /* ln_device1 :: laneReset :: reset_rx [03:00] */ 9631 #define PHY84328_DEV1_LANERESET_RESET_RX_MASK 0x000f 9632 #define PHY84328_DEV1_LANERESET_RESET_RX_ALIGN 0 9633 #define PHY84328_DEV1_LANERESET_RESET_RX_BITS 4 9634 #define PHY84328_DEV1_LANERESET_RESET_RX_SHIFT 0 9635 9636 9637 /**************************************************************************** 9638 * ln_device1 :: XFIcontrol 9639 */ 9640 /* ln_device1 :: XFIcontrol :: reserved0 [15:06] */ 9641 #define PHY84328_DEV1_XFICONTROL_RESERVED0_MASK 0xffc0 9642 #define PHY84328_DEV1_XFICONTROL_RESERVED0_ALIGN 0 9643 #define PHY84328_DEV1_XFICONTROL_RESERVED0_BITS 10 9644 #define PHY84328_DEV1_XFICONTROL_RESERVED0_SHIFT 6 9645 9646 /* ln_device1 :: XFIcontrol :: fc_mode_disable [05:05] */ 9647 #define PHY84328_DEV1_XFICONTROL_FC_MODE_DISABLE_MASK 0x0020 9648 #define PHY84328_DEV1_XFICONTROL_FC_MODE_DISABLE_ALIGN 0 9649 #define PHY84328_DEV1_XFICONTROL_FC_MODE_DISABLE_BITS 1 9650 #define PHY84328_DEV1_XFICONTROL_FC_MODE_DISABLE_SHIFT 5 9651 9652 /* ln_device1 :: XFIcontrol :: xfipcs_pwrdown [04:04] */ 9653 #define PHY84328_DEV1_XFICONTROL_XFIPCS_PWRDOWN_MASK 0x0010 9654 #define PHY84328_DEV1_XFICONTROL_XFIPCS_PWRDOWN_ALIGN 0 9655 #define PHY84328_DEV1_XFICONTROL_XFIPCS_PWRDOWN_BITS 1 9656 #define PHY84328_DEV1_XFICONTROL_XFIPCS_PWRDOWN_SHIFT 4 9657 9658 /* ln_device1 :: XFIcontrol :: xfi_rx_bypass_val [03:03] */ 9659 #define PHY84328_DEV1_XFICONTROL_XFI_RX_BYPASS_VAL_MASK 0x0008 9660 #define PHY84328_DEV1_XFICONTROL_XFI_RX_BYPASS_VAL_ALIGN 0 9661 #define PHY84328_DEV1_XFICONTROL_XFI_RX_BYPASS_VAL_BITS 1 9662 #define PHY84328_DEV1_XFICONTROL_XFI_RX_BYPASS_VAL_SHIFT 3 9663 9664 /* ln_device1 :: XFIcontrol :: xfi_rx_bypass_force [02:02] */ 9665 #define PHY84328_DEV1_XFICONTROL_XFI_RX_BYPASS_FORCE_MASK 0x0004 9666 #define PHY84328_DEV1_XFICONTROL_XFI_RX_BYPASS_FORCE_ALIGN 0 9667 #define PHY84328_DEV1_XFICONTROL_XFI_RX_BYPASS_FORCE_BITS 1 9668 #define PHY84328_DEV1_XFICONTROL_XFI_RX_BYPASS_FORCE_SHIFT 2 9669 9670 /* ln_device1 :: XFIcontrol :: xfi_tx_bypass_val [01:01] */ 9671 #define PHY84328_DEV1_XFICONTROL_XFI_TX_BYPASS_VAL_MASK 0x0002 9672 #define PHY84328_DEV1_XFICONTROL_XFI_TX_BYPASS_VAL_ALIGN 0 9673 #define PHY84328_DEV1_XFICONTROL_XFI_TX_BYPASS_VAL_BITS 1 9674 #define PHY84328_DEV1_XFICONTROL_XFI_TX_BYPASS_VAL_SHIFT 1 9675 9676 /* ln_device1 :: XFIcontrol :: xfi_tx_bypass_force [00:00] */ 9677 #define PHY84328_DEV1_XFICONTROL_XFI_TX_BYPASS_FORCE_MASK 0x0001 9678 #define PHY84328_DEV1_XFICONTROL_XFI_TX_BYPASS_FORCE_ALIGN 0 9679 #define PHY84328_DEV1_XFICONTROL_XFI_TX_BYPASS_FORCE_BITS 1 9680 #define PHY84328_DEV1_XFICONTROL_XFI_TX_BYPASS_FORCE_SHIFT 0 9681 9682 9683 /**************************************************************************** 9684 * ln_device1 :: cl73Control7 9685 */ 9686 /* ln_device1 :: cl73Control7 :: cl73_an_switch_cntL [15:00] */ 9687 #define PHY84328_DEV1_CL73CONTROL7_CL73_AN_SWITCH_CNTL_MASK 0xffff 9688 #define PHY84328_DEV1_CL73CONTROL7_CL73_AN_SWITCH_CNTL_ALIGN 0 9689 #define PHY84328_DEV1_CL73CONTROL7_CL73_AN_SWITCH_CNTL_BITS 16 9690 #define PHY84328_DEV1_CL73CONTROL7_CL73_AN_SWITCH_CNTL_SHIFT 0 9691 9692 9693 /**************************************************************************** 9694 * ln_device1 :: cl73Control8 9695 */ 9696 /* ln_device1 :: cl73Control8 :: cl73_refclk_161_offset_cnt [15:08] */ 9697 #define PHY84328_DEV1_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_MASK 0xff00 9698 #define PHY84328_DEV1_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_ALIGN 0 9699 #define PHY84328_DEV1_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_BITS 8 9700 #define PHY84328_DEV1_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_SHIFT 8 9701 9702 /* ln_device1 :: cl73Control8 :: cl73_an_switch_cntH [07:00] */ 9703 #define PHY84328_DEV1_CL73CONTROL8_CL73_AN_SWITCH_CNTH_MASK 0x00ff 9704 #define PHY84328_DEV1_CL73CONTROL8_CL73_AN_SWITCH_CNTH_ALIGN 0 9705 #define PHY84328_DEV1_CL73CONTROL8_CL73_AN_SWITCH_CNTH_BITS 8 9706 #define PHY84328_DEV1_CL73CONTROL8_CL73_AN_SWITCH_CNTH_SHIFT 0 9707 9708 9709 /**************************************************************************** 9710 * ln_device1 :: cl73Control9 9711 */ 9712 /* ln_device1 :: cl73Control9 :: reserved0 [15:15] */ 9713 #define PHY84328_DEV1_CL73CONTROL9_RESERVED0_MASK 0x8000 9714 #define PHY84328_DEV1_CL73CONTROL9_RESERVED0_ALIGN 0 9715 #define PHY84328_DEV1_CL73CONTROL9_RESERVED0_BITS 1 9716 #define PHY84328_DEV1_CL73CONTROL9_RESERVED0_SHIFT 15 9717 9718 /* ln_device1 :: cl73Control9 :: rxSeqDone_cya [14:14] */ 9719 #define PHY84328_DEV1_CL73CONTROL9_RXSEQDONE_CYA_MASK 0x4000 9720 #define PHY84328_DEV1_CL73CONTROL9_RXSEQDONE_CYA_ALIGN 0 9721 #define PHY84328_DEV1_CL73CONTROL9_RXSEQDONE_CYA_BITS 1 9722 #define PHY84328_DEV1_CL73CONTROL9_RXSEQDONE_CYA_SHIFT 14 9723 9724 /* ln_device1 :: cl73Control9 :: cl73_link_fail_inhibit_timer_kr_val [13:00] */ 9725 #define PHY84328_DEV1_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_MASK 0x3fff 9726 #define PHY84328_DEV1_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_ALIGN 0 9727 #define PHY84328_DEV1_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_BITS 14 9728 #define PHY84328_DEV1_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_SHIFT 0 9729 9730 9731 /**************************************************************************** 9732 * ln_device1 :: cl73Control10 9733 */ 9734 /* ln_device1 :: cl73Control10 :: reserved0 [15:14] */ 9735 #define PHY84328_DEV1_CL73CONTROL10_RESERVED0_MASK 0xc000 9736 #define PHY84328_DEV1_CL73CONTROL10_RESERVED0_ALIGN 0 9737 #define PHY84328_DEV1_CL73CONTROL10_RESERVED0_BITS 2 9738 #define PHY84328_DEV1_CL73CONTROL10_RESERVED0_SHIFT 14 9739 9740 /* ln_device1 :: cl73Control10 :: cl73_link_fail_inhibit_timer_cl72_val [13:00] */ 9741 #define PHY84328_DEV1_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_MASK 0x3fff 9742 #define PHY84328_DEV1_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_ALIGN 0 9743 #define PHY84328_DEV1_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_BITS 14 9744 #define PHY84328_DEV1_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_SHIFT 0 9745 9746 9747 /**************************************************************************** 9748 * ln_device1 :: xfi_afe_ctl1 9749 */ 9750 /* ln_device1 :: xfi_afe_ctl1 :: refclk_val [15:15] */ 9751 #define PHY84328_DEV1_XFI_AFE_CTL1_REFCLK_VAL_MASK 0x8000 9752 #define PHY84328_DEV1_XFI_AFE_CTL1_REFCLK_VAL_ALIGN 0 9753 #define PHY84328_DEV1_XFI_AFE_CTL1_REFCLK_VAL_BITS 1 9754 #define PHY84328_DEV1_XFI_AFE_CTL1_REFCLK_VAL_SHIFT 15 9755 9756 /* ln_device1 :: xfi_afe_ctl1 :: refclk_sel [14:14] */ 9757 #define PHY84328_DEV1_XFI_AFE_CTL1_REFCLK_SEL_MASK 0x4000 9758 #define PHY84328_DEV1_XFI_AFE_CTL1_REFCLK_SEL_ALIGN 0 9759 #define PHY84328_DEV1_XFI_AFE_CTL1_REFCLK_SEL_BITS 1 9760 #define PHY84328_DEV1_XFI_AFE_CTL1_REFCLK_SEL_SHIFT 14 9761 9762 /* ln_device1 :: xfi_afe_ctl1 :: tx_fir_sel [13:13] */ 9763 #define PHY84328_DEV1_XFI_AFE_CTL1_TX_FIR_SEL_MASK 0x2000 9764 #define PHY84328_DEV1_XFI_AFE_CTL1_TX_FIR_SEL_ALIGN 0 9765 #define PHY84328_DEV1_XFI_AFE_CTL1_TX_FIR_SEL_BITS 1 9766 #define PHY84328_DEV1_XFI_AFE_CTL1_TX_FIR_SEL_SHIFT 13 9767 9768 /* ln_device1 :: xfi_afe_ctl1 :: cal_valid_value [12:12] */ 9769 #define PHY84328_DEV1_XFI_AFE_CTL1_CAL_VALID_VALUE_MASK 0x1000 9770 #define PHY84328_DEV1_XFI_AFE_CTL1_CAL_VALID_VALUE_ALIGN 0 9771 #define PHY84328_DEV1_XFI_AFE_CTL1_CAL_VALID_VALUE_BITS 1 9772 #define PHY84328_DEV1_XFI_AFE_CTL1_CAL_VALID_VALUE_SHIFT 12 9773 9774 /* ln_device1 :: xfi_afe_ctl1 :: calibration_valid [11:11] */ 9775 #define PHY84328_DEV1_XFI_AFE_CTL1_CALIBRATION_VALID_MASK 0x0800 9776 #define PHY84328_DEV1_XFI_AFE_CTL1_CALIBRATION_VALID_ALIGN 0 9777 #define PHY84328_DEV1_XFI_AFE_CTL1_CALIBRATION_VALID_BITS 1 9778 #define PHY84328_DEV1_XFI_AFE_CTL1_CALIBRATION_VALID_SHIFT 11 9779 9780 /* ln_device1 :: xfi_afe_ctl1 :: Status_Select [10:08] */ 9781 #define PHY84328_DEV1_XFI_AFE_CTL1_STATUS_SELECT_MASK 0x0700 9782 #define PHY84328_DEV1_XFI_AFE_CTL1_STATUS_SELECT_ALIGN 0 9783 #define PHY84328_DEV1_XFI_AFE_CTL1_STATUS_SELECT_BITS 3 9784 #define PHY84328_DEV1_XFI_AFE_CTL1_STATUS_SELECT_SHIFT 8 9785 9786 /* ln_device1 :: xfi_afe_ctl1 :: drv5g_sel [07:07] */ 9787 #define PHY84328_DEV1_XFI_AFE_CTL1_DRV5G_SEL_MASK 0x0080 9788 #define PHY84328_DEV1_XFI_AFE_CTL1_DRV5G_SEL_ALIGN 0 9789 #define PHY84328_DEV1_XFI_AFE_CTL1_DRV5G_SEL_BITS 1 9790 #define PHY84328_DEV1_XFI_AFE_CTL1_DRV5G_SEL_SHIFT 7 9791 9792 /* ln_device1 :: xfi_afe_ctl1 :: buf10g_sel [06:06] */ 9793 #define PHY84328_DEV1_XFI_AFE_CTL1_BUF10G_SEL_MASK 0x0040 9794 #define PHY84328_DEV1_XFI_AFE_CTL1_BUF10G_SEL_ALIGN 0 9795 #define PHY84328_DEV1_XFI_AFE_CTL1_BUF10G_SEL_BITS 1 9796 #define PHY84328_DEV1_XFI_AFE_CTL1_BUF10G_SEL_SHIFT 6 9797 9798 /* ln_device1 :: xfi_afe_ctl1 :: pll_range_sel [05:05] */ 9799 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RANGE_SEL_MASK 0x0020 9800 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RANGE_SEL_ALIGN 0 9801 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RANGE_SEL_BITS 1 9802 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RANGE_SEL_SHIFT 5 9803 9804 /* ln_device1 :: xfi_afe_ctl1 :: pll_rescal_sel [04:04] */ 9805 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_SEL_MASK 0x0010 9806 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_SEL_ALIGN 0 9807 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_SEL_BITS 1 9808 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_SEL_SHIFT 4 9809 9810 /* ln_device1 :: xfi_afe_ctl1 :: pll_rescal_offset_sel [03:03] */ 9811 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SEL_MASK 0x0008 9812 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SEL_ALIGN 0 9813 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SEL_BITS 1 9814 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SEL_SHIFT 3 9815 9816 /* ln_device1 :: xfi_afe_ctl1 :: pll_rescal_offset [02:00] */ 9817 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_MASK 0x0007 9818 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_ALIGN 0 9819 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_BITS 3 9820 #define PHY84328_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SHIFT 0 9821 9822 9823 /**************************************************************************** 9824 * ln_device1 :: xfi_afe_ctl2 9825 */ 9826 /* ln_device1 :: xfi_afe_ctl2 :: reserved0 [15:14] */ 9827 #define PHY84328_DEV1_XFI_AFE_CTL2_RESERVED0_MASK 0xc000 9828 #define PHY84328_DEV1_XFI_AFE_CTL2_RESERVED0_ALIGN 0 9829 #define PHY84328_DEV1_XFI_AFE_CTL2_RESERVED0_BITS 2 9830 #define PHY84328_DEV1_XFI_AFE_CTL2_RESERVED0_SHIFT 14 9831 9832 /* ln_device1 :: xfi_afe_ctl2 :: pll_mode_sel [13:13] */ 9833 #define PHY84328_DEV1_XFI_AFE_CTL2_PLL_MODE_SEL_MASK 0x2000 9834 #define PHY84328_DEV1_XFI_AFE_CTL2_PLL_MODE_SEL_ALIGN 0 9835 #define PHY84328_DEV1_XFI_AFE_CTL2_PLL_MODE_SEL_BITS 1 9836 #define PHY84328_DEV1_XFI_AFE_CTL2_PLL_MODE_SEL_SHIFT 13 9837 9838 /* ln_device1 :: xfi_afe_ctl2 :: pll_sts_sel [12:12] */ 9839 #define PHY84328_DEV1_XFI_AFE_CTL2_PLL_STS_SEL_MASK 0x1000 9840 #define PHY84328_DEV1_XFI_AFE_CTL2_PLL_STS_SEL_ALIGN 0 9841 #define PHY84328_DEV1_XFI_AFE_CTL2_PLL_STS_SEL_BITS 1 9842 #define PHY84328_DEV1_XFI_AFE_CTL2_PLL_STS_SEL_SHIFT 12 9843 9844 /* ln_device1 :: xfi_afe_ctl2 :: Ge50sel_val [11:11] */ 9845 #define PHY84328_DEV1_XFI_AFE_CTL2_GE50SEL_VAL_MASK 0x0800 9846 #define PHY84328_DEV1_XFI_AFE_CTL2_GE50SEL_VAL_ALIGN 0 9847 #define PHY84328_DEV1_XFI_AFE_CTL2_GE50SEL_VAL_BITS 1 9848 #define PHY84328_DEV1_XFI_AFE_CTL2_GE50SEL_VAL_SHIFT 11 9849 9850 /* ln_device1 :: xfi_afe_ctl2 :: Ge50sel [10:10] */ 9851 #define PHY84328_DEV1_XFI_AFE_CTL2_GE50SEL_MASK 0x0400 9852 #define PHY84328_DEV1_XFI_AFE_CTL2_GE50SEL_ALIGN 0 9853 #define PHY84328_DEV1_XFI_AFE_CTL2_GE50SEL_BITS 1 9854 #define PHY84328_DEV1_XFI_AFE_CTL2_GE50SEL_SHIFT 10 9855 9856 /* ln_device1 :: xfi_afe_ctl2 :: Fc156sel_val [09:09] */ 9857 #define PHY84328_DEV1_XFI_AFE_CTL2_FC156SEL_VAL_MASK 0x0200 9858 #define PHY84328_DEV1_XFI_AFE_CTL2_FC156SEL_VAL_ALIGN 0 9859 #define PHY84328_DEV1_XFI_AFE_CTL2_FC156SEL_VAL_BITS 1 9860 #define PHY84328_DEV1_XFI_AFE_CTL2_FC156SEL_VAL_SHIFT 9 9861 9862 /* ln_device1 :: xfi_afe_ctl2 :: Fc156sel [08:08] */ 9863 #define PHY84328_DEV1_XFI_AFE_CTL2_FC156SEL_MASK 0x0100 9864 #define PHY84328_DEV1_XFI_AFE_CTL2_FC156SEL_ALIGN 0 9865 #define PHY84328_DEV1_XFI_AFE_CTL2_FC156SEL_BITS 1 9866 #define PHY84328_DEV1_XFI_AFE_CTL2_FC156SEL_SHIFT 8 9867 9868 /* ln_device1 :: xfi_afe_ctl2 :: tx_rescal_sel [07:04] */ 9869 #define PHY84328_DEV1_XFI_AFE_CTL2_TX_RESCAL_SEL_MASK 0x00f0 9870 #define PHY84328_DEV1_XFI_AFE_CTL2_TX_RESCAL_SEL_ALIGN 0 9871 #define PHY84328_DEV1_XFI_AFE_CTL2_TX_RESCAL_SEL_BITS 4 9872 #define PHY84328_DEV1_XFI_AFE_CTL2_TX_RESCAL_SEL_SHIFT 4 9873 9874 /* ln_device1 :: xfi_afe_ctl2 :: tx_fir_sel [03:00] */ 9875 #define PHY84328_DEV1_XFI_AFE_CTL2_TX_FIR_SEL_MASK 0x000f 9876 #define PHY84328_DEV1_XFI_AFE_CTL2_TX_FIR_SEL_ALIGN 0 9877 #define PHY84328_DEV1_XFI_AFE_CTL2_TX_FIR_SEL_BITS 4 9878 #define PHY84328_DEV1_XFI_AFE_CTL2_TX_FIR_SEL_SHIFT 0 9879 9880 9881 /**************************************************************************** 9882 **************************************************************************** 9883 **************************************************************************** 9884 **************************************************************************** 9885 **************************************************************************** 9886 **************************************************************************** 9887 * ln_device7_AN_Standard_Registers 9888 */ 9889 9890 9891 #define PHY84328_DEV7_AN_CONTROL_REGISTER 0x00000000 /* AN Control Register */ 9892 #define PHY84328_DEV7_AN_STATUS_REGISTER 0x00000001 /* AN Status Register */ 9893 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_0 0x00000002 /* AN Identifier Register 0 */ 9894 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_1 0x00000003 /* AN Identifier Register 1 */ 9895 #define PHY84328_DEV7_AN_OUI_ID0_REGISTER 0x0000000e /* AN OUI ID0 Register */ 9896 #define PHY84328_DEV7_AN_OUI_ID1_REG 0x0000000f /* AN OUI ID1 Reg */ 9897 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER 0x00000010 /* AN Advertisement 1 Register */ 9898 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER 0x00000011 /* AN Advertisement 2 Register */ 9899 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER 0x00000012 /* AN Advertisement 3 Register */ 9900 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG 0x00000013 /* AN LP Base Page Ability 1 Register */ 9901 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG 0x00000014 /* AN LP Base Page Ability 2 Register */ 9902 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG 0x00000015 /* AN LP Base Page Ability 3 Register */ 9903 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER 0x00000016 /* AN XNP transmit 1 Register */ 9904 #define PHY84328_DEV7_AN_XNP_TRANSMIT_2_REGISTER 0x00000017 /* AN XNP transmit 2 Register */ 9905 #define PHY84328_DEV7_AN_XNP_TRANSMIT_3_REGISTER 0x00000018 /* AN XNP transmit 3 Register */ 9906 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER 0x00000019 /* AN LP XNP transmit 1 Register */ 9907 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER 0x0000001a /* AN LP XNP transmit 2 Register */ 9908 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER 0x0000001b /* AN LP XNP transmit 3 Register */ 9909 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER 0x00000030 /* Backplane Ethernet Status Register */ 9910 #define PHY84328_DEV7_EEE_ADV 0x0000003c /* EEE_adv_type */ 9911 #define PHY84328_DEV7_EEE_LP_ADV 0x0000003d /* EEE_lp_adv_type */ 9912 9913 9914 /**************************************************************************** 9915 * ln_device7_cl73_userb0 9916 */ 9917 #define PHY84328_DEV7_CL73_UCTRL1 0x0000c370 /* CL73_UCtrl1_type */ 9918 #define PHY84328_DEV7_CL73_USTAT1 0x0000c371 /* CL73_UStat1_type */ 9919 #define PHY84328_DEV7_CL73_BAMCTRL1 0x0000c372 /* CL73_BAMCtrl1_type */ 9920 #define PHY84328_DEV7_CL73_BAMCTRL2 0x0000c373 /* CL73_BAMCtrl2_type */ 9921 #define PHY84328_DEV7_CL73_BAMCTRL3 0x0000c374 /* CL73_BAMCtrl3_type */ 9922 #define PHY84328_DEV7_CL73_BAMSTAT1 0x0000c375 /* CL73_BAMStat1_type */ 9923 #define PHY84328_DEV7_CL73_BAMSTAT2 0x0000c376 /* CL73_BAMStat2_type */ 9924 #define PHY84328_DEV7_CL73_BAMSTAT3 0x0000c377 /* CL73_BAMStat3_type */ 9925 #define PHY84328_DEV7_CL73_UCTRL2 0x0000c378 /* CL73_UCtrl2_type */ 9926 #define PHY84328_DEV7_CL73_EEECTRL_TYPE 0x0000c37e /* CL73_EEECtrl_type */ 9927 9928 9929 /**************************************************************************** 9930 * ln_device7_gp_status 9931 */ 9932 #define PHY84328_DEV7_MISCRXSTATUS 0x0000c120 /* MiscRxStatus_Reg */ 9933 #define PHY84328_DEV7_X2500STATUS1 0x0000c12a /* basex2500Status1_Reg */ 9934 #define PHY84328_DEV7_TOPANSTATUS1 0x0000c12b /* topANStatus1_Reg */ 9935 #define PHY84328_DEV7_LP_UP1 0x0000c12c /* LP_UP1_Reg */ 9936 #define PHY84328_DEV7_LP_UP2 0x0000c12d /* LP_UP2_Reg */ 9937 #define PHY84328_DEV7_LP_UP3 0x0000c12e /* LP_UP3_Reg */ 9938 9939 9940 /**************************************************************************** 9941 * ln_device7_userPerLnCtrl_Registers 9942 */ 9943 #define PHY84328_DEV7_CL73CONTROL1 0x0000c135 /* Clause 73 auto-negotiation control register 1 */ 9944 #define PHY84328_DEV7_CL73CONTROL2 0x0000c136 /* Clause 73 auto-negotiation control register 2 */ 9945 #define PHY84328_DEV7_CL73CONTROL3 0x0000c137 /* Clause 73 auto-negotiation control register 3 */ 9946 #define PHY84328_DEV7_CL73CONTROL4 0x0000c138 /* Clause 73 auto-negotiation control register 4 */ 9947 #define PHY84328_DEV7_CL73CONTROL5 0x0000c139 /* Clause 73 auto-negotiation control register 5 */ 9948 #define PHY84328_DEV7_CL73CONTROL6 0x0000c13a /* Clause 73 auto-negotiation control register 6 */ 9949 #define PHY84328_DEV7_CL73DMETMRS 0x0000c13b /* Clause 73 auto-negotiation DME Timers Register */ 9950 #define PHY84328_DEV7_CONTROL1000X1 0x0000c300 /* 1000X control 1 register */ 9951 #define PHY84328_DEV7_CONTROL1000X2 0x0000c301 /* 1000X control 2 register */ 9952 #define PHY84328_DEV7_CONTROL1000X3 0x0000c302 /* 1000X control 3 register */ 9953 #define PHY84328_DEV7_CONTROL1000X4 0x0000c303 /* 1000X control 4 register */ 9954 #define PHY84328_DEV7_STATUS1000X1 0x0000c304 /* 1000X status 1 register */ 9955 #define PHY84328_DEV7_STATUS1000X2 0x0000c305 /* 1000X status 2 register */ 9956 #define PHY84328_DEV7_STATUS1000X3 0x0000c306 /* 1000X status 3 register */ 9957 #define PHY84328_DEV7_BADCODEGROUP 0x0000c307 /* Invalid code group count register */ 9958 #define PHY84328_DEV7_MISC1 0x0000c308 /* Miscellaneous 1 control register */ 9959 #define PHY84328_DEV7_MISC2 0x0000c309 /* Miscellaneous 2 control register */ 9960 #define PHY84328_DEV7_PATGENCTRL 0x0000c30a /* Pattern generator control register */ 9961 #define PHY84328_DEV7_PATGENSTAT 0x0000c30b /* Pattern generator status register */ 9962 #define PHY84328_DEV7_TESTMODE 0x0000c30c /* Test mode register */ 9963 #define PHY84328_DEV7_TXPKTCNT 0x0000c30d /* Tx packet count register */ 9964 #define PHY84328_DEV7_RXPKTCNT 0x0000c30e /* Rx packet count register */ 9965 #define PHY84328_DEV7_DIGCTL_3_0 0x0000c320 /* AN lost link count time, bits 15:0 */ 9966 #define PHY84328_DEV7_DIGCTL_3_1 0x0000c321 /* AN switch count time, bits 15:0 */ 9967 #define PHY84328_DEV7_DIGCTL_3_2 0x0000c322 /* AN link count time, bits 15:0 */ 9968 #define PHY84328_DEV7_DIGCTL_3_3 0x0000c323 /* AN switch count & link count time, bits 23:16 */ 9969 #define PHY84328_DEV7_DIGCTL_3_4 0x0000c324 /* Over 1G message page number & AN fail count timer */ 9970 #define PHY84328_DEV7_DIGCTL_3_5 0x0000c325 /* AN ignore link count time, bits 15:0 */ 9971 #define PHY84328_DEV7_DIGCTL_3_6 0x0000c326 /* AN lost link count & ignore link count time, bits 23:16 */ 9972 #define PHY84328_DEV7_UP1 0x0000c329 /* AN local device user page 1 */ 9973 #define PHY84328_DEV7_UP2 0x0000c32a /* AN local device user page 2 */ 9974 #define PHY84328_DEV7_UP3 0x0000c32b /* AN local device user page 3 */ 9975 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1 0x0000c32c /* AN link partner user page 1 */ 9976 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2 0x0000c32d /* AN link partner user page 2 */ 9977 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3 0x0000c32e /* AN link partner user page 3 */ 9978 #define PHY84328_DEV7_RPHYMISCRXSTATUS 0x0000c330 /* Dig 4 Miscellaneous Rx status register */ 9979 #define PHY84328_DEV7_LP_BASEPAGE 0x0000c331 /* Dig 4 Link partner basepage register */ 9980 #define PHY84328_DEV7_LP_NEXTPAGE_0 0x0000c332 /* Dig 4 Link partner nextpage 0 register */ 9981 #define PHY84328_DEV7_LP_NEXTPAGE_1 0x0000c333 /* Dig 4 Link partner nextpage 1 register */ 9982 #define PHY84328_DEV7_LP_NEXTPAGE_2 0x0000c334 /* Dig 4 Link partner nextpage 2 register */ 9983 #define PHY84328_DEV7_LP_NEXTPAGE_3 0x0000c335 /* Dig 4 Link partner nextpage 3 register */ 9984 #define PHY84328_DEV7_LP_NEXTPAGE_4 0x0000c336 /* Dig 4 Link partner nextpage 4 register */ 9985 #define PHY84328_DEV7_RP_NEXTPAGE_0 0x0000c337 /* Remote phy nextpage 0 register */ 9986 #define PHY84328_DEV7_RP_NEXTPAGE_1 0x0000c338 /* Dig 4 Remote phy nextpage 1 register */ 9987 #define PHY84328_DEV7_RP_NEXTPAGE_2 0x0000c339 /* Dig 4 Remote phy nextpage 2 register */ 9988 #define PHY84328_DEV7_RP_NEXTPAGE_3 0x0000c33a /* Dig 4 Remote phy nextpage 3 register */ 9989 #define PHY84328_DEV7_RP_NEXTPAGE_4 0x0000c33b /* Dig 4 Remote phy nextpage 4 register */ 9990 #define PHY84328_DEV7_MISC3 0x0000c33c /* Dig 4 Miscellaneous 3 control register */ 9991 #define PHY84328_DEV7_MISC4 0x0000c33d /* Dig 4 Miscelaneous 4 control register */ 9992 #define PHY84328_DEV7_MISC5 0x0000c33e /* Dig 4 Miscelaneous 5 control register */ 9993 #define PHY84328_DEV7_LINKCNT_CL72_MSB 0x0000c340 /* CL72 Link counter MSB [23:16] */ 9994 #define PHY84328_DEV7_LINKCNT_CL72_LSB 0x0000c341 /* CL72 Link counter LSB [15:0] */ 9995 #define PHY84328_DEV7_LP_UP4 0x0000c342 /* Link Partner's UP4 page */ 9996 #define PHY84328_DEV7_LP_UP5 0x0000c343 /* Link Partner's UP5 page */ 9997 #define PHY84328_DEV7_MISC6 0x0000c345 /* Misc6 */ 9998 #define PHY84328_DEV7_MISC7 0x0000c349 /* Misc7 */ 9999 #define PHY84328_DEV7_MISC8 0x0000c34a /* Misc8 */ 10000 #define PHY84328_DEV7_LINK_STATUS 0x0000c34d /* link_status */ 10001 #define PHY84328_DEV7_ACTUAL_SPEED 0x0000c34e /* Actual Speed status */ 10002 #define PHY84328_DEV7_MP5_NEXTPAGECTRL 0x0000c350 /* MP5, Message Page 5, next page control register */ 10003 #define PHY84328_DEV7_LINK_TIMER_OFFSET1 0x0000c351 /* sgmii & max timer offsets */ 10004 #define PHY84328_DEV7_LINK_TIMER_OFFSET2 0x0000c352 /* link up & link down timer offsets */ 10005 #define PHY84328_DEV7_LINK_TIMER_OFFSET3 0x0000c353 /* break link & next page link timer offsets */ 10006 #define PHY84328_DEV7_OUI_MSB_FIELD 0x0000c354 /* 11 MSbits of the oui, oui[23:13] */ 10007 #define PHY84328_DEV7_OUI_LSB_FIELD 0x0000c355 /* 11 middle bits of the oui, oui[12:2] */ 10008 #define PHY84328_DEV7_UD_FIELD 0x0000c357 /* User defined field of MP5 */ 10009 #define PHY84328_DEV7_LP_UD_FIELD 0x0000c35b /* Link partner's User defined field of MP5 */ 10010 #define PHY84328_DEV7_SGMIIBASEPAGE 0x0000c35c /* sgmii_basepage */ 10011 #define PHY84328_DEV7_UP5 0x0000c35e /* AN local device user page 5 */ 10012 10013 10014 /**************************************************************************** 10015 * ln_device7_AN_Standard_Registers 10016 */ 10017 /**************************************************************************** 10018 * ln_device7 :: an_control_register 10019 */ 10020 /* ln_device7 :: an_control_register :: an_reset [15:15] */ 10021 #define PHY84328_DEV7_AN_CONTROL_REGISTER_AN_RESET_MASK 0x8000 10022 #define PHY84328_DEV7_AN_CONTROL_REGISTER_AN_RESET_ALIGN 0 10023 #define PHY84328_DEV7_AN_CONTROL_REGISTER_AN_RESET_BITS 1 10024 #define PHY84328_DEV7_AN_CONTROL_REGISTER_AN_RESET_SHIFT 15 10025 10026 /* ln_device7 :: an_control_register :: reserved0 [14:13] */ 10027 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED0_MASK 0x6000 10028 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED0_ALIGN 0 10029 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED0_BITS 2 10030 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED0_SHIFT 13 10031 10032 /* ln_device7 :: an_control_register :: auto_negotiationenable [12:12] */ 10033 #define PHY84328_DEV7_AN_CONTROL_REGISTER_AUTO_NEGOTIATIONENABLE_MASK 0x1000 10034 #define PHY84328_DEV7_AN_CONTROL_REGISTER_AUTO_NEGOTIATIONENABLE_ALIGN 0 10035 #define PHY84328_DEV7_AN_CONTROL_REGISTER_AUTO_NEGOTIATIONENABLE_BITS 1 10036 #define PHY84328_DEV7_AN_CONTROL_REGISTER_AUTO_NEGOTIATIONENABLE_SHIFT 12 10037 10038 /* ln_device7 :: an_control_register :: reserved1 [11:10] */ 10039 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED1_MASK 0x0c00 10040 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED1_ALIGN 0 10041 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED1_BITS 2 10042 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED1_SHIFT 10 10043 10044 /* ln_device7 :: an_control_register :: restart_auto_negotiation [09:09] */ 10045 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESTART_AUTO_NEGOTIATION_MASK 0x0200 10046 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESTART_AUTO_NEGOTIATION_ALIGN 0 10047 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESTART_AUTO_NEGOTIATION_BITS 1 10048 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESTART_AUTO_NEGOTIATION_SHIFT 9 10049 10050 /* ln_device7 :: an_control_register :: reserved2 [08:00] */ 10051 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED2_MASK 0x01ff 10052 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED2_ALIGN 0 10053 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED2_BITS 9 10054 #define PHY84328_DEV7_AN_CONTROL_REGISTER_RESERVED2_SHIFT 0 10055 10056 10057 /**************************************************************************** 10058 * ln_device7 :: an_status_register 10059 */ 10060 /* ln_device7 :: an_status_register :: reserved0 [15:10] */ 10061 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED0_MASK 0xfc00 10062 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED0_ALIGN 0 10063 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED0_BITS 6 10064 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED0_SHIFT 10 10065 10066 /* ln_device7 :: an_status_register :: parallel_detection_fault [09:09] */ 10067 #define PHY84328_DEV7_AN_STATUS_REGISTER_PARALLEL_DETECTION_FAULT_MASK 0x0200 10068 #define PHY84328_DEV7_AN_STATUS_REGISTER_PARALLEL_DETECTION_FAULT_ALIGN 0 10069 #define PHY84328_DEV7_AN_STATUS_REGISTER_PARALLEL_DETECTION_FAULT_BITS 1 10070 #define PHY84328_DEV7_AN_STATUS_REGISTER_PARALLEL_DETECTION_FAULT_SHIFT 9 10071 10072 /* ln_device7 :: an_status_register :: reserved1 [08:08] */ 10073 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED1_MASK 0x0100 10074 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED1_ALIGN 0 10075 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED1_BITS 1 10076 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED1_SHIFT 8 10077 10078 /* ln_device7 :: an_status_register :: extended_next_pagestatus [07:07] */ 10079 #define PHY84328_DEV7_AN_STATUS_REGISTER_EXTENDED_NEXT_PAGESTATUS_MASK 0x0080 10080 #define PHY84328_DEV7_AN_STATUS_REGISTER_EXTENDED_NEXT_PAGESTATUS_ALIGN 0 10081 #define PHY84328_DEV7_AN_STATUS_REGISTER_EXTENDED_NEXT_PAGESTATUS_BITS 1 10082 #define PHY84328_DEV7_AN_STATUS_REGISTER_EXTENDED_NEXT_PAGESTATUS_SHIFT 7 10083 10084 /* ln_device7 :: an_status_register :: page_received [06:06] */ 10085 #define PHY84328_DEV7_AN_STATUS_REGISTER_PAGE_RECEIVED_MASK 0x0040 10086 #define PHY84328_DEV7_AN_STATUS_REGISTER_PAGE_RECEIVED_ALIGN 0 10087 #define PHY84328_DEV7_AN_STATUS_REGISTER_PAGE_RECEIVED_BITS 1 10088 #define PHY84328_DEV7_AN_STATUS_REGISTER_PAGE_RECEIVED_SHIFT 6 10089 10090 /* ln_device7 :: an_status_register :: auto_negotiationcomplete [05:05] */ 10091 #define PHY84328_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONCOMPLETE_MASK 0x0020 10092 #define PHY84328_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONCOMPLETE_ALIGN 0 10093 #define PHY84328_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONCOMPLETE_BITS 1 10094 #define PHY84328_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONCOMPLETE_SHIFT 5 10095 10096 /* ln_device7 :: an_status_register :: remote_fault [04:04] */ 10097 #define PHY84328_DEV7_AN_STATUS_REGISTER_REMOTE_FAULT_MASK 0x0010 10098 #define PHY84328_DEV7_AN_STATUS_REGISTER_REMOTE_FAULT_ALIGN 0 10099 #define PHY84328_DEV7_AN_STATUS_REGISTER_REMOTE_FAULT_BITS 1 10100 #define PHY84328_DEV7_AN_STATUS_REGISTER_REMOTE_FAULT_SHIFT 4 10101 10102 /* ln_device7 :: an_status_register :: auto_negotiationability [03:03] */ 10103 #define PHY84328_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONABILITY_MASK 0x0008 10104 #define PHY84328_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONABILITY_ALIGN 0 10105 #define PHY84328_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONABILITY_BITS 1 10106 #define PHY84328_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONABILITY_SHIFT 3 10107 10108 /* ln_device7 :: an_status_register :: link_status [02:02] */ 10109 #define PHY84328_DEV7_AN_STATUS_REGISTER_LINK_STATUS_MASK 0x0004 10110 #define PHY84328_DEV7_AN_STATUS_REGISTER_LINK_STATUS_ALIGN 0 10111 #define PHY84328_DEV7_AN_STATUS_REGISTER_LINK_STATUS_BITS 1 10112 #define PHY84328_DEV7_AN_STATUS_REGISTER_LINK_STATUS_SHIFT 2 10113 10114 /* ln_device7 :: an_status_register :: reserved2 [01:01] */ 10115 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED2_MASK 0x0002 10116 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED2_ALIGN 0 10117 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED2_BITS 1 10118 #define PHY84328_DEV7_AN_STATUS_REGISTER_RESERVED2_SHIFT 1 10119 10120 /* ln_device7 :: an_status_register :: link_partner_auto_negotiationability [00:00] */ 10121 #define PHY84328_DEV7_AN_STATUS_REGISTER_LINK_PARTNER_AUTO_NEGOTIATIONABILITY_MASK 0x0001 10122 #define PHY84328_DEV7_AN_STATUS_REGISTER_LINK_PARTNER_AUTO_NEGOTIATIONABILITY_ALIGN 0 10123 #define PHY84328_DEV7_AN_STATUS_REGISTER_LINK_PARTNER_AUTO_NEGOTIATIONABILITY_BITS 1 10124 #define PHY84328_DEV7_AN_STATUS_REGISTER_LINK_PARTNER_AUTO_NEGOTIATIONABILITY_SHIFT 0 10125 10126 10127 /**************************************************************************** 10128 * ln_device7 :: an_identifier_register_0 10129 */ 10130 /* ln_device7 :: an_identifier_register_0 :: device_id_0 [15:00] */ 10131 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_0_DEVICE_ID_0_MASK 0xffff 10132 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_0_DEVICE_ID_0_ALIGN 0 10133 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_0_DEVICE_ID_0_BITS 16 10134 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_0_DEVICE_ID_0_SHIFT 0 10135 10136 10137 /**************************************************************************** 10138 * ln_device7 :: an_identifier_register_1 10139 */ 10140 /* ln_device7 :: an_identifier_register_1 :: device_id_1 [15:00] */ 10141 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_1_DEVICE_ID_1_MASK 0xffff 10142 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_1_DEVICE_ID_1_ALIGN 0 10143 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_1_DEVICE_ID_1_BITS 16 10144 #define PHY84328_DEV7_AN_IDENTIFIER_REGISTER_1_DEVICE_ID_1_SHIFT 0 10145 10146 10147 /**************************************************************************** 10148 * ln_device7 :: an_oui_id0_register 10149 */ 10150 /* ln_device7 :: an_oui_id0_register :: device_id_0 [15:00] */ 10151 #define PHY84328_DEV7_AN_OUI_ID0_REGISTER_DEVICE_ID_0_MASK 0xffff 10152 #define PHY84328_DEV7_AN_OUI_ID0_REGISTER_DEVICE_ID_0_ALIGN 0 10153 #define PHY84328_DEV7_AN_OUI_ID0_REGISTER_DEVICE_ID_0_BITS 16 10154 #define PHY84328_DEV7_AN_OUI_ID0_REGISTER_DEVICE_ID_0_SHIFT 0 10155 10156 10157 /**************************************************************************** 10158 * ln_device7 :: an_oui_id1_reg 10159 */ 10160 /* ln_device7 :: an_oui_id1_reg :: device_id_1 [15:00] */ 10161 #define PHY84328_DEV7_AN_OUI_ID1_REG_DEVICE_ID_1_MASK 0xffff 10162 #define PHY84328_DEV7_AN_OUI_ID1_REG_DEVICE_ID_1_ALIGN 0 10163 #define PHY84328_DEV7_AN_OUI_ID1_REG_DEVICE_ID_1_BITS 16 10164 #define PHY84328_DEV7_AN_OUI_ID1_REG_DEVICE_ID_1_SHIFT 0 10165 10166 10167 /**************************************************************************** 10168 * ln_device7 :: an_advertisement_1_register 10169 */ 10170 /* ln_device7 :: an_advertisement_1_register :: next_page [15:15] */ 10171 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_MASK 0x8000 10172 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_ALIGN 0 10173 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_BITS 1 10174 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_SHIFT 15 10175 10176 /* ln_device7 :: an_advertisement_1_register :: acknowledge [14:14] */ 10177 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_MASK 0x4000 10178 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_ALIGN 0 10179 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_BITS 1 10180 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_SHIFT 14 10181 10182 /* ln_device7 :: an_advertisement_1_register :: remote_fault [13:13] */ 10183 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_MASK 0x2000 10184 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_ALIGN 0 10185 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_BITS 1 10186 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_SHIFT 13 10187 10188 /* ln_device7 :: an_advertisement_1_register :: pause [12:10] */ 10189 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_PAUSE_MASK 0x1c00 10190 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_PAUSE_ALIGN 0 10191 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_PAUSE_BITS 3 10192 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_PAUSE_SHIFT 10 10193 10194 /* ln_device7 :: an_advertisement_1_register :: echoed_nonce [09:05] */ 10195 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_MASK 0x03e0 10196 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_ALIGN 0 10197 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_BITS 5 10198 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_SHIFT 5 10199 10200 /* ln_device7 :: an_advertisement_1_register :: selector_field [04:00] */ 10201 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_MASK 0x001f 10202 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_ALIGN 0 10203 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_BITS 5 10204 #define PHY84328_DEV7_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_SHIFT 0 10205 10206 10207 /**************************************************************************** 10208 * ln_device7 :: an_advertisement_2_register 10209 */ 10210 /* ln_device7 :: an_advertisement_2_register :: techAbility [15:05] */ 10211 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_MASK 0xffe0 10212 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_ALIGN 0 10213 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_BITS 11 10214 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_SHIFT 5 10215 10216 /* ln_device7 :: an_advertisement_2_register :: transmitted_nonce [04:00] */ 10217 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_MASK 0x001f 10218 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_ALIGN 0 10219 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_BITS 5 10220 #define PHY84328_DEV7_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_SHIFT 0 10221 10222 10223 /**************************************************************************** 10224 * ln_device7 :: an_advertisement_3_register 10225 */ 10226 /* ln_device7 :: an_advertisement_3_register :: fec_requested [15:14] */ 10227 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_MASK 0xc000 10228 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_ALIGN 0 10229 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_BITS 2 10230 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_SHIFT 14 10231 10232 /* ln_device7 :: an_advertisement_3_register :: reserved0 [13:00] */ 10233 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER_RESERVED0_MASK 0x3fff 10234 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER_RESERVED0_ALIGN 0 10235 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER_RESERVED0_BITS 14 10236 #define PHY84328_DEV7_AN_ADVERTISEMENT_3_REGISTER_RESERVED0_SHIFT 0 10237 10238 10239 /**************************************************************************** 10240 * ln_device7 :: an_lp_base_page_ability_1_reg 10241 */ 10242 /* ln_device7 :: an_lp_base_page_ability_1_reg :: d15_d0 [15:00] */ 10243 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_MASK 0xffff 10244 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_ALIGN 0 10245 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_BITS 16 10246 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_SHIFT 0 10247 10248 10249 /**************************************************************************** 10250 * ln_device7 :: an_lp_base_page_ability_2_reg 10251 */ 10252 /* ln_device7 :: an_lp_base_page_ability_2_reg :: d31_16 [15:00] */ 10253 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_MASK 0xffff 10254 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_ALIGN 0 10255 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_BITS 16 10256 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_SHIFT 0 10257 10258 10259 /**************************************************************************** 10260 * ln_device7 :: an_lp_base_page_ability_3_reg 10261 */ 10262 /* ln_device7 :: an_lp_base_page_ability_3_reg :: d47_32 [15:00] */ 10263 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_MASK 0xffff 10264 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_ALIGN 0 10265 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_BITS 16 10266 #define PHY84328_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_SHIFT 0 10267 10268 10269 /**************************************************************************** 10270 * ln_device7 :: an_xnp_transmit_1_register 10271 */ 10272 /* ln_device7 :: an_xnp_transmit_1_register :: next_page [15:15] */ 10273 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_MASK 0x8000 10274 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_ALIGN 0 10275 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_BITS 1 10276 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_SHIFT 15 10277 10278 /* ln_device7 :: an_xnp_transmit_1_register :: reserved0 [14:14] */ 10279 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_MASK 0x4000 10280 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_ALIGN 0 10281 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_BITS 1 10282 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_SHIFT 14 10283 10284 /* ln_device7 :: an_xnp_transmit_1_register :: message_page [13:13] */ 10285 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_MASK 0x2000 10286 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_ALIGN 0 10287 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_BITS 1 10288 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_SHIFT 13 10289 10290 /* ln_device7 :: an_xnp_transmit_1_register :: acknowledge_2 [12:12] */ 10291 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_MASK 0x1000 10292 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_ALIGN 0 10293 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_BITS 1 10294 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_SHIFT 12 10295 10296 /* ln_device7 :: an_xnp_transmit_1_register :: toggle [11:11] */ 10297 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_MASK 0x0800 10298 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_ALIGN 0 10299 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_BITS 1 10300 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_SHIFT 11 10301 10302 /* ln_device7 :: an_xnp_transmit_1_register :: message_unformatedcode_field [10:00] */ 10303 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_MASK 0x07ff 10304 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_ALIGN 0 10305 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_BITS 11 10306 #define PHY84328_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_SHIFT 0 10307 10308 10309 /**************************************************************************** 10310 * ln_device7 :: an_xnp_transmit_2_register 10311 */ 10312 /* ln_device7 :: an_xnp_transmit_2_register :: unformated_codefield_1 [15:00] */ 10313 #define PHY84328_DEV7_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_MASK 0xffff 10314 #define PHY84328_DEV7_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_ALIGN 0 10315 #define PHY84328_DEV7_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_BITS 16 10316 #define PHY84328_DEV7_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_SHIFT 0 10317 10318 10319 /**************************************************************************** 10320 * ln_device7 :: an_xnp_transmit_3_register 10321 */ 10322 /* ln_device7 :: an_xnp_transmit_3_register :: unformated_codefield_3 [15:00] */ 10323 #define PHY84328_DEV7_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_MASK 0xffff 10324 #define PHY84328_DEV7_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_ALIGN 0 10325 #define PHY84328_DEV7_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_BITS 16 10326 #define PHY84328_DEV7_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_SHIFT 0 10327 10328 10329 /**************************************************************************** 10330 * ln_device7 :: an_lp_xnp_transmit_1_register 10331 */ 10332 /* ln_device7 :: an_lp_xnp_transmit_1_register :: next_page [15:15] */ 10333 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_MASK 0x8000 10334 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_ALIGN 0 10335 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_BITS 1 10336 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_SHIFT 15 10337 10338 /* ln_device7 :: an_lp_xnp_transmit_1_register :: acknowledge [14:14] */ 10339 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_MASK 0x4000 10340 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_ALIGN 0 10341 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_BITS 1 10342 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_SHIFT 14 10343 10344 /* ln_device7 :: an_lp_xnp_transmit_1_register :: message_page [13:13] */ 10345 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_MASK 0x2000 10346 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_ALIGN 0 10347 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_BITS 1 10348 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_SHIFT 13 10349 10350 /* ln_device7 :: an_lp_xnp_transmit_1_register :: acknowledge_2 [12:12] */ 10351 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_MASK 0x1000 10352 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_ALIGN 0 10353 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_BITS 1 10354 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_SHIFT 12 10355 10356 /* ln_device7 :: an_lp_xnp_transmit_1_register :: toggle [11:11] */ 10357 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_MASK 0x0800 10358 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_ALIGN 0 10359 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_BITS 1 10360 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_SHIFT 11 10361 10362 /* ln_device7 :: an_lp_xnp_transmit_1_register :: message_unformatedcode_field [10:00] */ 10363 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_MASK 0x07ff 10364 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_ALIGN 0 10365 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_BITS 11 10366 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_SHIFT 0 10367 10368 10369 /**************************************************************************** 10370 * ln_device7 :: an_lp_xnp_transmit_2_register 10371 */ 10372 /* ln_device7 :: an_lp_xnp_transmit_2_register :: unformated_codefield_1 [15:00] */ 10373 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_MASK 0xffff 10374 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_ALIGN 0 10375 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_BITS 16 10376 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_SHIFT 0 10377 10378 10379 /**************************************************************************** 10380 * ln_device7 :: an_lp_xnp_transmit_3_register 10381 */ 10382 /* ln_device7 :: an_lp_xnp_transmit_3_register :: unformated_codefield_3 [15:00] */ 10383 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_MASK 0xffff 10384 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_ALIGN 0 10385 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_BITS 16 10386 #define PHY84328_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_SHIFT 0 10387 10388 10389 /**************************************************************************** 10390 * ln_device7 :: backplane_ethernet_status_register 10391 */ 10392 /* ln_device7 :: backplane_ethernet_status_register :: reserved0 [15:07] */ 10393 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_MASK 0xff80 10394 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_ALIGN 0 10395 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_BITS 9 10396 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_SHIFT 7 10397 10398 /* ln_device7 :: backplane_ethernet_status_register :: fortygbase_cr4 [06:06] */ 10399 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_MASK 0x0040 10400 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_ALIGN 0 10401 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_BITS 1 10402 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_SHIFT 6 10403 10404 /* ln_device7 :: backplane_ethernet_status_register :: fortygbase_kr [05:05] */ 10405 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR_MASK 0x0020 10406 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR_ALIGN 0 10407 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR_BITS 1 10408 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR_SHIFT 5 10409 10410 /* ln_device7 :: backplane_ethernet_status_register :: tengbase_kr_fecnegotiated [04:04] */ 10411 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_FECNEGOTIATED_MASK 0x0010 10412 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_FECNEGOTIATED_ALIGN 0 10413 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_FECNEGOTIATED_BITS 1 10414 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_FECNEGOTIATED_SHIFT 4 10415 10416 /* ln_device7 :: backplane_ethernet_status_register :: tengbase_kr [03:03] */ 10417 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_MASK 0x0008 10418 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_ALIGN 0 10419 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_BITS 1 10420 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_SHIFT 3 10421 10422 /* ln_device7 :: backplane_ethernet_status_register :: tengbase_kx4 [02:02] */ 10423 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_MASK 0x0004 10424 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_ALIGN 0 10425 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_BITS 1 10426 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_SHIFT 2 10427 10428 /* ln_device7 :: backplane_ethernet_status_register :: gigbase_kx [01:01] */ 10429 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_MASK 0x0002 10430 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_ALIGN 0 10431 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_BITS 1 10432 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_SHIFT 1 10433 10434 /* ln_device7 :: backplane_ethernet_status_register :: bp_an_ability [00:00] */ 10435 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_MASK 0x0001 10436 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_ALIGN 0 10437 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_BITS 1 10438 #define PHY84328_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_SHIFT 0 10439 10440 10441 /**************************************************************************** 10442 * ln_device7 :: EEE_adv 10443 */ 10444 /* ln_device7 :: EEE_adv :: reserved0 [15:07] */ 10445 #define PHY84328_DEV7_EEE_ADV_RESERVED0_MASK 0xff80 10446 #define PHY84328_DEV7_EEE_ADV_RESERVED0_ALIGN 0 10447 #define PHY84328_DEV7_EEE_ADV_RESERVED0_BITS 9 10448 #define PHY84328_DEV7_EEE_ADV_RESERVED0_SHIFT 7 10449 10450 /* ln_device7 :: EEE_adv :: EEE_10G_KR [06:06] */ 10451 #define PHY84328_DEV7_EEE_ADV_EEE_10G_KR_MASK 0x0040 10452 #define PHY84328_DEV7_EEE_ADV_EEE_10G_KR_ALIGN 0 10453 #define PHY84328_DEV7_EEE_ADV_EEE_10G_KR_BITS 1 10454 #define PHY84328_DEV7_EEE_ADV_EEE_10G_KR_SHIFT 6 10455 10456 /* ln_device7 :: EEE_adv :: EEE_10G_KX4 [05:05] */ 10457 #define PHY84328_DEV7_EEE_ADV_EEE_10G_KX4_MASK 0x0020 10458 #define PHY84328_DEV7_EEE_ADV_EEE_10G_KX4_ALIGN 0 10459 #define PHY84328_DEV7_EEE_ADV_EEE_10G_KX4_BITS 1 10460 #define PHY84328_DEV7_EEE_ADV_EEE_10G_KX4_SHIFT 5 10461 10462 /* ln_device7 :: EEE_adv :: EEE_1G_KX [04:04] */ 10463 #define PHY84328_DEV7_EEE_ADV_EEE_1G_KX_MASK 0x0010 10464 #define PHY84328_DEV7_EEE_ADV_EEE_1G_KX_ALIGN 0 10465 #define PHY84328_DEV7_EEE_ADV_EEE_1G_KX_BITS 1 10466 #define PHY84328_DEV7_EEE_ADV_EEE_1G_KX_SHIFT 4 10467 10468 /* ln_device7 :: EEE_adv :: reserved1 [03:00] */ 10469 #define PHY84328_DEV7_EEE_ADV_RESERVED1_MASK 0x000f 10470 #define PHY84328_DEV7_EEE_ADV_RESERVED1_ALIGN 0 10471 #define PHY84328_DEV7_EEE_ADV_RESERVED1_BITS 4 10472 #define PHY84328_DEV7_EEE_ADV_RESERVED1_SHIFT 0 10473 10474 10475 /**************************************************************************** 10476 * ln_device7 :: EEE_lp_adv 10477 */ 10478 /* ln_device7 :: EEE_lp_adv :: reserved0 [15:07] */ 10479 #define PHY84328_DEV7_EEE_LP_ADV_RESERVED0_MASK 0xff80 10480 #define PHY84328_DEV7_EEE_LP_ADV_RESERVED0_ALIGN 0 10481 #define PHY84328_DEV7_EEE_LP_ADV_RESERVED0_BITS 9 10482 #define PHY84328_DEV7_EEE_LP_ADV_RESERVED0_SHIFT 7 10483 10484 /* ln_device7 :: EEE_lp_adv :: EEE_10G_KR [06:06] */ 10485 #define PHY84328_DEV7_EEE_LP_ADV_EEE_10G_KR_MASK 0x0040 10486 #define PHY84328_DEV7_EEE_LP_ADV_EEE_10G_KR_ALIGN 0 10487 #define PHY84328_DEV7_EEE_LP_ADV_EEE_10G_KR_BITS 1 10488 #define PHY84328_DEV7_EEE_LP_ADV_EEE_10G_KR_SHIFT 6 10489 10490 /* ln_device7 :: EEE_lp_adv :: EEE_10G_KX4 [05:05] */ 10491 #define PHY84328_DEV7_EEE_LP_ADV_EEE_10G_KX4_MASK 0x0020 10492 #define PHY84328_DEV7_EEE_LP_ADV_EEE_10G_KX4_ALIGN 0 10493 #define PHY84328_DEV7_EEE_LP_ADV_EEE_10G_KX4_BITS 1 10494 #define PHY84328_DEV7_EEE_LP_ADV_EEE_10G_KX4_SHIFT 5 10495 10496 /* ln_device7 :: EEE_lp_adv :: EEE_1G_KX [04:04] */ 10497 #define PHY84328_DEV7_EEE_LP_ADV_EEE_1G_KX_MASK 0x0010 10498 #define PHY84328_DEV7_EEE_LP_ADV_EEE_1G_KX_ALIGN 0 10499 #define PHY84328_DEV7_EEE_LP_ADV_EEE_1G_KX_BITS 1 10500 #define PHY84328_DEV7_EEE_LP_ADV_EEE_1G_KX_SHIFT 4 10501 10502 /* ln_device7 :: EEE_lp_adv :: reserved1 [03:00] */ 10503 #define PHY84328_DEV7_EEE_LP_ADV_RESERVED1_MASK 0x000f 10504 #define PHY84328_DEV7_EEE_LP_ADV_RESERVED1_ALIGN 0 10505 #define PHY84328_DEV7_EEE_LP_ADV_RESERVED1_BITS 4 10506 #define PHY84328_DEV7_EEE_LP_ADV_RESERVED1_SHIFT 0 10507 10508 10509 /**************************************************************************** 10510 * ln_device7_cl73_userb0 10511 */ 10512 /**************************************************************************** 10513 * ln_device7 :: CL73_UCtrl1 10514 */ 10515 /* ln_device7 :: CL73_UCtrl1 :: cl73_fast_timers [15:15] */ 10516 #define PHY84328_DEV7_CL73_UCTRL1_CL73_FAST_TIMERS_MASK 0x8000 10517 #define PHY84328_DEV7_CL73_UCTRL1_CL73_FAST_TIMERS_ALIGN 0 10518 #define PHY84328_DEV7_CL73_UCTRL1_CL73_FAST_TIMERS_BITS 1 10519 #define PHY84328_DEV7_CL73_UCTRL1_CL73_FAST_TIMERS_SHIFT 15 10520 10521 /* ln_device7 :: CL73_UCtrl1 :: txDisableBam_en_over [14:14] */ 10522 #define PHY84328_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_OVER_MASK 0x4000 10523 #define PHY84328_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_OVER_ALIGN 0 10524 #define PHY84328_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_OVER_BITS 1 10525 #define PHY84328_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_OVER_SHIFT 14 10526 10527 /* ln_device7 :: CL73_UCtrl1 :: txDisableBam_en_val [13:13] */ 10528 #define PHY84328_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_VAL_MASK 0x2000 10529 #define PHY84328_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_VAL_ALIGN 0 10530 #define PHY84328_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_VAL_BITS 1 10531 #define PHY84328_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_VAL_SHIFT 13 10532 10533 /* ln_device7 :: CL73_UCtrl1 :: cl73_lossOfSyncFail_en [12:12] */ 10534 #define PHY84328_DEV7_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_MASK 0x1000 10535 #define PHY84328_DEV7_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_ALIGN 0 10536 #define PHY84328_DEV7_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_BITS 1 10537 #define PHY84328_DEV7_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_SHIFT 12 10538 10539 /* ln_device7 :: CL73_UCtrl1 :: cl73_parDet_dis [11:11] */ 10540 #define PHY84328_DEV7_CL73_UCTRL1_CL73_PARDET_DIS_MASK 0x0800 10541 #define PHY84328_DEV7_CL73_UCTRL1_CL73_PARDET_DIS_ALIGN 0 10542 #define PHY84328_DEV7_CL73_UCTRL1_CL73_PARDET_DIS_BITS 1 10543 #define PHY84328_DEV7_CL73_UCTRL1_CL73_PARDET_DIS_SHIFT 11 10544 10545 /* ln_device7 :: CL73_UCtrl1 :: cl73_allowCl37AN [10:10] */ 10546 #define PHY84328_DEV7_CL73_UCTRL1_CL73_ALLOWCL37AN_MASK 0x0400 10547 #define PHY84328_DEV7_CL73_UCTRL1_CL73_ALLOWCL37AN_ALIGN 0 10548 #define PHY84328_DEV7_CL73_UCTRL1_CL73_ALLOWCL37AN_BITS 1 10549 #define PHY84328_DEV7_CL73_UCTRL1_CL73_ALLOWCL37AN_SHIFT 10 10550 10551 /* ln_device7 :: CL73_UCtrl1 :: longParDetTimer_dis [09:09] */ 10552 #define PHY84328_DEV7_CL73_UCTRL1_LONGPARDETTIMER_DIS_MASK 0x0200 10553 #define PHY84328_DEV7_CL73_UCTRL1_LONGPARDETTIMER_DIS_ALIGN 0 10554 #define PHY84328_DEV7_CL73_UCTRL1_LONGPARDETTIMER_DIS_BITS 1 10555 #define PHY84328_DEV7_CL73_UCTRL1_LONGPARDETTIMER_DIS_SHIFT 9 10556 10557 /* ln_device7 :: CL73_UCtrl1 :: linkFailTimer_dis [08:08] */ 10558 #define PHY84328_DEV7_CL73_UCTRL1_LINKFAILTIMER_DIS_MASK 0x0100 10559 #define PHY84328_DEV7_CL73_UCTRL1_LINKFAILTIMER_DIS_ALIGN 0 10560 #define PHY84328_DEV7_CL73_UCTRL1_LINKFAILTIMER_DIS_BITS 1 10561 #define PHY84328_DEV7_CL73_UCTRL1_LINKFAILTIMER_DIS_SHIFT 8 10562 10563 /* ln_device7 :: CL73_UCtrl1 :: linkFailTimerQual_en [07:07] */ 10564 #define PHY84328_DEV7_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_MASK 0x0080 10565 #define PHY84328_DEV7_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_ALIGN 0 10566 #define PHY84328_DEV7_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_BITS 1 10567 #define PHY84328_DEV7_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_SHIFT 7 10568 10569 /* ln_device7 :: CL73_UCtrl1 :: cl73_nonce_match_over [06:06] */ 10570 #define PHY84328_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK 0x0040 10571 #define PHY84328_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN 0 10572 #define PHY84328_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS 1 10573 #define PHY84328_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT 6 10574 10575 /* ln_device7 :: CL73_UCtrl1 :: cl73_nonce_match_val [05:05] */ 10576 #define PHY84328_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK 0x0020 10577 #define PHY84328_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN 0 10578 #define PHY84328_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS 1 10579 #define PHY84328_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT 5 10580 10581 /* ln_device7 :: CL73_UCtrl1 :: couple_w_cl73_restart_wo_link_fail [04:04] */ 10582 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_MASK 0x0010 10583 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_ALIGN 0 10584 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_BITS 1 10585 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_SHIFT 4 10586 10587 /* ln_device7 :: CL73_UCtrl1 :: couple_w_cl73_restart [03:03] */ 10588 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_MASK 0x0008 10589 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_ALIGN 0 10590 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_BITS 1 10591 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_SHIFT 3 10592 10593 /* ln_device7 :: CL73_UCtrl1 :: couple_w_cl37_restart [02:02] */ 10594 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL37_RESTART_MASK 0x0004 10595 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL37_RESTART_ALIGN 0 10596 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL37_RESTART_BITS 1 10597 #define PHY84328_DEV7_CL73_UCTRL1_COUPLE_W_CL37_RESTART_SHIFT 2 10598 10599 /* ln_device7 :: CL73_UCtrl1 :: CL73_UStat1_muxsel [01:01] */ 10600 #define PHY84328_DEV7_CL73_UCTRL1_CL73_USTAT1_MUXSEL_MASK 0x0002 10601 #define PHY84328_DEV7_CL73_UCTRL1_CL73_USTAT1_MUXSEL_ALIGN 0 10602 #define PHY84328_DEV7_CL73_UCTRL1_CL73_USTAT1_MUXSEL_BITS 1 10603 #define PHY84328_DEV7_CL73_UCTRL1_CL73_USTAT1_MUXSEL_SHIFT 1 10604 10605 /* ln_device7 :: CL73_UCtrl1 :: force_cl73_tx_omux_en [00:00] */ 10606 #define PHY84328_DEV7_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_MASK 0x0001 10607 #define PHY84328_DEV7_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_ALIGN 0 10608 #define PHY84328_DEV7_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_BITS 1 10609 #define PHY84328_DEV7_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_SHIFT 0 10610 10611 10612 /**************************************************************************** 10613 * ln_device7 :: CL73_UStat1 10614 */ 10615 /* ln_device7 :: CL73_UStat1 :: reserved0 [15:10] */ 10616 #define PHY84328_DEV7_CL73_USTAT1_RESERVED0_MASK 0xfc00 10617 #define PHY84328_DEV7_CL73_USTAT1_RESERVED0_ALIGN 0 10618 #define PHY84328_DEV7_CL73_USTAT1_RESERVED0_BITS 6 10619 #define PHY84328_DEV7_CL73_USTAT1_RESERVED0_SHIFT 10 10620 10621 /* ln_device7 :: CL73_UStat1 :: arb_fsm [09:00] */ 10622 #define PHY84328_DEV7_CL73_USTAT1_ARB_FSM_MASK 0x03ff 10623 #define PHY84328_DEV7_CL73_USTAT1_ARB_FSM_ALIGN 0 10624 #define PHY84328_DEV7_CL73_USTAT1_ARB_FSM_BITS 10 10625 #define PHY84328_DEV7_CL73_USTAT1_ARB_FSM_SHIFT 0 10626 10627 10628 /**************************************************************************** 10629 * ln_device7 :: CL73_BAMCtrl1 10630 */ 10631 /* ln_device7 :: CL73_BAMCtrl1 :: CL73_bamEn [15:15] */ 10632 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAMEN_MASK 0x8000 10633 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAMEN_ALIGN 0 10634 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAMEN_BITS 1 10635 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAMEN_SHIFT 15 10636 10637 /* ln_device7 :: CL73_BAMCtrl1 :: CL73_bam_station_mngr_en [14:14] */ 10638 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_MASK 0x4000 10639 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_ALIGN 0 10640 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_BITS 1 10641 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_SHIFT 14 10642 10643 /* ln_device7 :: CL73_BAMCtrl1 :: CL73_bamNP_after_bp_en [13:13] */ 10644 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_MASK 0x2000 10645 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_ALIGN 0 10646 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_BITS 1 10647 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_SHIFT 13 10648 10649 /* ln_device7 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_en [12:12] */ 10650 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_MASK 0x1000 10651 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_ALIGN 0 10652 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_BITS 1 10653 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_SHIFT 12 10654 10655 /* ln_device7 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_step [11:11] */ 10656 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_MASK 0x0800 10657 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_ALIGN 0 10658 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_BITS 1 10659 #define PHY84328_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_SHIFT 11 10660 10661 /* ln_device7 :: CL73_BAMCtrl1 :: reserved0 [10:10] */ 10662 #define PHY84328_DEV7_CL73_BAMCTRL1_RESERVED0_MASK 0x0400 10663 #define PHY84328_DEV7_CL73_BAMCTRL1_RESERVED0_ALIGN 0 10664 #define PHY84328_DEV7_CL73_BAMCTRL1_RESERVED0_BITS 1 10665 #define PHY84328_DEV7_CL73_BAMCTRL1_RESERVED0_SHIFT 10 10666 10667 /* ln_device7 :: CL73_BAMCtrl1 :: UD_code_field_41_32 [09:00] */ 10668 #define PHY84328_DEV7_CL73_BAMCTRL1_UD_CODE_FIELD_41_32_MASK 0x03ff 10669 #define PHY84328_DEV7_CL73_BAMCTRL1_UD_CODE_FIELD_41_32_ALIGN 0 10670 #define PHY84328_DEV7_CL73_BAMCTRL1_UD_CODE_FIELD_41_32_BITS 10 10671 #define PHY84328_DEV7_CL73_BAMCTRL1_UD_CODE_FIELD_41_32_SHIFT 0 10672 10673 10674 /**************************************************************************** 10675 * ln_device7 :: CL73_BAMCtrl2 10676 */ 10677 /* ln_device7 :: CL73_BAMCtrl2 :: UD_code_field_31_16 [15:00] */ 10678 #define PHY84328_DEV7_CL73_BAMCTRL2_UD_CODE_FIELD_31_16_MASK 0xffff 10679 #define PHY84328_DEV7_CL73_BAMCTRL2_UD_CODE_FIELD_31_16_ALIGN 0 10680 #define PHY84328_DEV7_CL73_BAMCTRL2_UD_CODE_FIELD_31_16_BITS 16 10681 #define PHY84328_DEV7_CL73_BAMCTRL2_UD_CODE_FIELD_31_16_SHIFT 0 10682 10683 10684 /**************************************************************************** 10685 * ln_device7 :: CL73_BAMCtrl3 10686 */ 10687 /* ln_device7 :: CL73_BAMCtrl3 :: UD_code_field_15_0 [15:00] */ 10688 #define PHY84328_DEV7_CL73_BAMCTRL3_UD_CODE_FIELD_15_0_MASK 0xffff 10689 #define PHY84328_DEV7_CL73_BAMCTRL3_UD_CODE_FIELD_15_0_ALIGN 0 10690 #define PHY84328_DEV7_CL73_BAMCTRL3_UD_CODE_FIELD_15_0_BITS 16 10691 #define PHY84328_DEV7_CL73_BAMCTRL3_UD_CODE_FIELD_15_0_SHIFT 0 10692 10693 10694 /**************************************************************************** 10695 * ln_device7 :: CL73_BAMStat1 10696 */ 10697 /* ln_device7 :: CL73_BAMStat1 :: reserved0 [15:10] */ 10698 #define PHY84328_DEV7_CL73_BAMSTAT1_RESERVED0_MASK 0xfc00 10699 #define PHY84328_DEV7_CL73_BAMSTAT1_RESERVED0_ALIGN 0 10700 #define PHY84328_DEV7_CL73_BAMSTAT1_RESERVED0_BITS 6 10701 #define PHY84328_DEV7_CL73_BAMSTAT1_RESERVED0_SHIFT 10 10702 10703 /* ln_device7 :: CL73_BAMStat1 :: LP_UD_code_field_41_32 [09:00] */ 10704 #define PHY84328_DEV7_CL73_BAMSTAT1_LP_UD_CODE_FIELD_41_32_MASK 0x03ff 10705 #define PHY84328_DEV7_CL73_BAMSTAT1_LP_UD_CODE_FIELD_41_32_ALIGN 0 10706 #define PHY84328_DEV7_CL73_BAMSTAT1_LP_UD_CODE_FIELD_41_32_BITS 10 10707 #define PHY84328_DEV7_CL73_BAMSTAT1_LP_UD_CODE_FIELD_41_32_SHIFT 0 10708 10709 10710 /**************************************************************************** 10711 * ln_device7 :: CL73_BAMStat2 10712 */ 10713 /* ln_device7 :: CL73_BAMStat2 :: LP_UD_code_field_31_16 [15:00] */ 10714 #define PHY84328_DEV7_CL73_BAMSTAT2_LP_UD_CODE_FIELD_31_16_MASK 0xffff 10715 #define PHY84328_DEV7_CL73_BAMSTAT2_LP_UD_CODE_FIELD_31_16_ALIGN 0 10716 #define PHY84328_DEV7_CL73_BAMSTAT2_LP_UD_CODE_FIELD_31_16_BITS 16 10717 #define PHY84328_DEV7_CL73_BAMSTAT2_LP_UD_CODE_FIELD_31_16_SHIFT 0 10718 10719 10720 /**************************************************************************** 10721 * ln_device7 :: CL73_BAMStat3 10722 */ 10723 /* ln_device7 :: CL73_BAMStat3 :: LP_UD_code_field_15_0 [15:00] */ 10724 #define PHY84328_DEV7_CL73_BAMSTAT3_LP_UD_CODE_FIELD_15_0_MASK 0xffff 10725 #define PHY84328_DEV7_CL73_BAMSTAT3_LP_UD_CODE_FIELD_15_0_ALIGN 0 10726 #define PHY84328_DEV7_CL73_BAMSTAT3_LP_UD_CODE_FIELD_15_0_BITS 16 10727 #define PHY84328_DEV7_CL73_BAMSTAT3_LP_UD_CODE_FIELD_15_0_SHIFT 0 10728 10729 10730 /**************************************************************************** 10731 * ln_device7 :: CL73_UCtrl2 10732 */ 10733 /* ln_device7 :: CL73_UCtrl2 :: reserved0 [15:15] */ 10734 #define PHY84328_DEV7_CL73_UCTRL2_RESERVED0_MASK 0x8000 10735 #define PHY84328_DEV7_CL73_UCTRL2_RESERVED0_ALIGN 0 10736 #define PHY84328_DEV7_CL73_UCTRL2_RESERVED0_BITS 1 10737 #define PHY84328_DEV7_CL73_UCTRL2_RESERVED0_SHIFT 15 10738 10739 /* ln_device7 :: CL73_UCtrl2 :: Disable_Wait4_DME_RxSeqDone_4_AN_START [14:14] */ 10740 #define PHY84328_DEV7_CL73_UCTRL2_DISABLE_WAIT4_DME_RXSEQDONE_4_AN_START_MASK 0x4000 10741 #define PHY84328_DEV7_CL73_UCTRL2_DISABLE_WAIT4_DME_RXSEQDONE_4_AN_START_ALIGN 0 10742 #define PHY84328_DEV7_CL73_UCTRL2_DISABLE_WAIT4_DME_RXSEQDONE_4_AN_START_BITS 1 10743 #define PHY84328_DEV7_CL73_UCTRL2_DISABLE_WAIT4_DME_RXSEQDONE_4_AN_START_SHIFT 14 10744 10745 /* ln_device7 :: CL73_UCtrl2 :: an_good_trap [13:13] */ 10746 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_TRAP_MASK 0x2000 10747 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_TRAP_ALIGN 0 10748 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_TRAP_BITS 1 10749 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_TRAP_SHIFT 13 10750 10751 /* ln_device7 :: CL73_UCtrl2 :: an_good_checkTrap [12:12] */ 10752 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_CHECKTRAP_MASK 0x1000 10753 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_CHECKTRAP_ALIGN 0 10754 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_CHECKTRAP_BITS 1 10755 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_CHECKTRAP_SHIFT 12 10756 10757 /* ln_device7 :: CL73_UCtrl2 :: uselink [11:11] */ 10758 #define PHY84328_DEV7_CL73_UCTRL2_USELINK_MASK 0x0800 10759 #define PHY84328_DEV7_CL73_UCTRL2_USELINK_ALIGN 0 10760 #define PHY84328_DEV7_CL73_UCTRL2_USELINK_BITS 1 10761 #define PHY84328_DEV7_CL73_UCTRL2_USELINK_SHIFT 11 10762 10763 /* ln_device7 :: CL73_UCtrl2 :: rx_dme_status_sel [10:09] */ 10764 #define PHY84328_DEV7_CL73_UCTRL2_RX_DME_STATUS_SEL_MASK 0x0600 10765 #define PHY84328_DEV7_CL73_UCTRL2_RX_DME_STATUS_SEL_ALIGN 0 10766 #define PHY84328_DEV7_CL73_UCTRL2_RX_DME_STATUS_SEL_BITS 2 10767 #define PHY84328_DEV7_CL73_UCTRL2_RX_DME_STATUS_SEL_SHIFT 9 10768 10769 /* ln_device7 :: CL73_UCtrl2 :: cl73_suppress_mr_page_rx_dis [08:08] */ 10770 #define PHY84328_DEV7_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_MASK 0x0100 10771 #define PHY84328_DEV7_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_ALIGN 0 10772 #define PHY84328_DEV7_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_BITS 1 10773 #define PHY84328_DEV7_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_SHIFT 8 10774 10775 /* ln_device7 :: CL73_UCtrl2 :: cl73_record_2NP_after_BP_en [07:07] */ 10776 #define PHY84328_DEV7_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_MASK 0x0080 10777 #define PHY84328_DEV7_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_ALIGN 0 10778 #define PHY84328_DEV7_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_BITS 1 10779 #define PHY84328_DEV7_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_SHIFT 7 10780 10781 /* ln_device7 :: CL73_UCtrl2 :: cl73_BAMStat123_sel [06:04] */ 10782 #define PHY84328_DEV7_CL73_UCTRL2_CL73_BAMSTAT123_SEL_MASK 0x0070 10783 #define PHY84328_DEV7_CL73_UCTRL2_CL73_BAMSTAT123_SEL_ALIGN 0 10784 #define PHY84328_DEV7_CL73_UCTRL2_CL73_BAMSTAT123_SEL_BITS 3 10785 #define PHY84328_DEV7_CL73_UCTRL2_CL73_BAMSTAT123_SEL_SHIFT 4 10786 10787 /* ln_device7 :: CL73_UCtrl2 :: sigdet_timer_dis [03:03] */ 10788 #define PHY84328_DEV7_CL73_UCTRL2_SIGDET_TIMER_DIS_MASK 0x0008 10789 #define PHY84328_DEV7_CL73_UCTRL2_SIGDET_TIMER_DIS_ALIGN 0 10790 #define PHY84328_DEV7_CL73_UCTRL2_SIGDET_TIMER_DIS_BITS 1 10791 #define PHY84328_DEV7_CL73_UCTRL2_SIGDET_TIMER_DIS_SHIFT 3 10792 10793 /* ln_device7 :: CL73_UCtrl2 :: an_good_check_bam37_dis [02:02] */ 10794 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_MASK 0x0004 10795 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_ALIGN 0 10796 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_BITS 1 10797 #define PHY84328_DEV7_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_SHIFT 2 10798 10799 /* ln_device7 :: CL73_UCtrl2 :: config_match_dis [01:01] */ 10800 #define PHY84328_DEV7_CL73_UCTRL2_CONFIG_MATCH_DIS_MASK 0x0002 10801 #define PHY84328_DEV7_CL73_UCTRL2_CONFIG_MATCH_DIS_ALIGN 0 10802 #define PHY84328_DEV7_CL73_UCTRL2_CONFIG_MATCH_DIS_BITS 1 10803 #define PHY84328_DEV7_CL73_UCTRL2_CONFIG_MATCH_DIS_SHIFT 1 10804 10805 /* ln_device7 :: CL73_UCtrl2 :: hold_lp_ability [00:00] */ 10806 #define PHY84328_DEV7_CL73_UCTRL2_HOLD_LP_ABILITY_MASK 0x0001 10807 #define PHY84328_DEV7_CL73_UCTRL2_HOLD_LP_ABILITY_ALIGN 0 10808 #define PHY84328_DEV7_CL73_UCTRL2_HOLD_LP_ABILITY_BITS 1 10809 #define PHY84328_DEV7_CL73_UCTRL2_HOLD_LP_ABILITY_SHIFT 0 10810 10811 10812 /**************************************************************************** 10813 * ln_device7 :: CL73_EEECtrl_type 10814 */ 10815 /* ln_device7 :: CL73_EEECtrl_type :: CL73_eeeEn [15:15] */ 10816 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_CL73_EEEEN_MASK 0x8000 10817 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_CL73_EEEEN_ALIGN 0 10818 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_CL73_EEEEN_BITS 1 10819 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_CL73_EEEEN_SHIFT 15 10820 10821 /* ln_device7 :: CL73_EEECtrl_type :: CL73_eeeNP_after_bp_en [14:14] */ 10822 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_CL73_EEENP_AFTER_BP_EN_MASK 0x4000 10823 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_CL73_EEENP_AFTER_BP_EN_ALIGN 0 10824 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_CL73_EEENP_AFTER_BP_EN_BITS 1 10825 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_CL73_EEENP_AFTER_BP_EN_SHIFT 14 10826 10827 /* ln_device7 :: CL73_EEECtrl_type :: hold_eee_lp_ability [13:13] */ 10828 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_HOLD_EEE_LP_ABILITY_MASK 0x2000 10829 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_HOLD_EEE_LP_ABILITY_ALIGN 0 10830 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_HOLD_EEE_LP_ABILITY_BITS 1 10831 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_HOLD_EEE_LP_ABILITY_SHIFT 13 10832 10833 /* ln_device7 :: CL73_EEECtrl_type :: reserved0 [12:00] */ 10834 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_RESERVED0_MASK 0x1fff 10835 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_RESERVED0_ALIGN 0 10836 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_RESERVED0_BITS 13 10837 #define PHY84328_DEV7_CL73_EEECTRL_TYPE_RESERVED0_SHIFT 0 10838 10839 10840 /**************************************************************************** 10841 * ln_device7_gp_status 10842 */ 10843 /**************************************************************************** 10844 * ln_device7 :: miscrxstatus 10845 */ 10846 /* ln_device7 :: miscrxstatus :: capture_NP_lh [15:15] */ 10847 #define PHY84328_DEV7_MISCRXSTATUS_CAPTURE_NP_LH_MASK 0x8000 10848 #define PHY84328_DEV7_MISCRXSTATUS_CAPTURE_NP_LH_ALIGN 0 10849 #define PHY84328_DEV7_MISCRXSTATUS_CAPTURE_NP_LH_BITS 1 10850 #define PHY84328_DEV7_MISCRXSTATUS_CAPTURE_NP_LH_SHIFT 15 10851 10852 /* ln_device7 :: miscrxstatus :: teton_brk_link_lh [14:14] */ 10853 #define PHY84328_DEV7_MISCRXSTATUS_TETON_BRK_LINK_LH_MASK 0x4000 10854 #define PHY84328_DEV7_MISCRXSTATUS_TETON_BRK_LINK_LH_ALIGN 0 10855 #define PHY84328_DEV7_MISCRXSTATUS_TETON_BRK_LINK_LH_BITS 1 10856 #define PHY84328_DEV7_MISCRXSTATUS_TETON_BRK_LINK_LH_SHIFT 14 10857 10858 /* ln_device7 :: miscrxstatus :: UP3_lh [13:13] */ 10859 #define PHY84328_DEV7_MISCRXSTATUS_UP3_LH_MASK 0x2000 10860 #define PHY84328_DEV7_MISCRXSTATUS_UP3_LH_ALIGN 0 10861 #define PHY84328_DEV7_MISCRXSTATUS_UP3_LH_BITS 1 10862 #define PHY84328_DEV7_MISCRXSTATUS_UP3_LH_SHIFT 13 10863 10864 /* ln_device7 :: miscrxstatus :: MP5_lh [12:12] */ 10865 #define PHY84328_DEV7_MISCRXSTATUS_MP5_LH_MASK 0x1000 10866 #define PHY84328_DEV7_MISCRXSTATUS_MP5_LH_ALIGN 0 10867 #define PHY84328_DEV7_MISCRXSTATUS_MP5_LH_BITS 1 10868 #define PHY84328_DEV7_MISCRXSTATUS_MP5_LH_SHIFT 12 10869 10870 /* ln_device7 :: miscrxstatus :: nonMatchingOUI_lh [11:11] */ 10871 #define PHY84328_DEV7_MISCRXSTATUS_NONMATCHINGOUI_LH_MASK 0x0800 10872 #define PHY84328_DEV7_MISCRXSTATUS_NONMATCHINGOUI_LH_ALIGN 0 10873 #define PHY84328_DEV7_MISCRXSTATUS_NONMATCHINGOUI_LH_BITS 1 10874 #define PHY84328_DEV7_MISCRXSTATUS_NONMATCHINGOUI_LH_SHIFT 11 10875 10876 /* ln_device7 :: miscrxstatus :: matchingOUI_msb_lh [10:10] */ 10877 #define PHY84328_DEV7_MISCRXSTATUS_MATCHINGOUI_MSB_LH_MASK 0x0400 10878 #define PHY84328_DEV7_MISCRXSTATUS_MATCHINGOUI_MSB_LH_ALIGN 0 10879 #define PHY84328_DEV7_MISCRXSTATUS_MATCHINGOUI_MSB_LH_BITS 1 10880 #define PHY84328_DEV7_MISCRXSTATUS_MATCHINGOUI_MSB_LH_SHIFT 10 10881 10882 /* ln_device7 :: miscrxstatus :: matchingOUI_lsb_lh [09:09] */ 10883 #define PHY84328_DEV7_MISCRXSTATUS_MATCHINGOUI_LSB_LH_MASK 0x0200 10884 #define PHY84328_DEV7_MISCRXSTATUS_MATCHINGOUI_LSB_LH_ALIGN 0 10885 #define PHY84328_DEV7_MISCRXSTATUS_MATCHINGOUI_LSB_LH_BITS 1 10886 #define PHY84328_DEV7_MISCRXSTATUS_MATCHINGOUI_LSB_LH_SHIFT 9 10887 10888 /* ln_device7 :: miscrxstatus :: invalidSeq_lh [08:08] */ 10889 #define PHY84328_DEV7_MISCRXSTATUS_INVALIDSEQ_LH_MASK 0x0100 10890 #define PHY84328_DEV7_MISCRXSTATUS_INVALIDSEQ_LH_ALIGN 0 10891 #define PHY84328_DEV7_MISCRXSTATUS_INVALIDSEQ_LH_BITS 1 10892 #define PHY84328_DEV7_MISCRXSTATUS_INVALIDSEQ_LH_SHIFT 8 10893 10894 /* ln_device7 :: miscrxstatus :: nullMP_lh [07:07] */ 10895 #define PHY84328_DEV7_MISCRXSTATUS_NULLMP_LH_MASK 0x0080 10896 #define PHY84328_DEV7_MISCRXSTATUS_NULLMP_LH_ALIGN 0 10897 #define PHY84328_DEV7_MISCRXSTATUS_NULLMP_LH_BITS 1 10898 #define PHY84328_DEV7_MISCRXSTATUS_NULLMP_LH_SHIFT 7 10899 10900 /* ln_device7 :: miscrxstatus :: remotePhyMP_lh [06:06] */ 10901 #define PHY84328_DEV7_MISCRXSTATUS_REMOTEPHYMP_LH_MASK 0x0040 10902 #define PHY84328_DEV7_MISCRXSTATUS_REMOTEPHYMP_LH_ALIGN 0 10903 #define PHY84328_DEV7_MISCRXSTATUS_REMOTEPHYMP_LH_BITS 1 10904 #define PHY84328_DEV7_MISCRXSTATUS_REMOTEPHYMP_LH_SHIFT 6 10905 10906 /* ln_device7 :: miscrxstatus :: nonMatchingMP_lh [05:05] */ 10907 #define PHY84328_DEV7_MISCRXSTATUS_NONMATCHINGMP_LH_MASK 0x0020 10908 #define PHY84328_DEV7_MISCRXSTATUS_NONMATCHINGMP_LH_ALIGN 0 10909 #define PHY84328_DEV7_MISCRXSTATUS_NONMATCHINGMP_LH_BITS 1 10910 #define PHY84328_DEV7_MISCRXSTATUS_NONMATCHINGMP_LH_SHIFT 5 10911 10912 /* ln_device7 :: miscrxstatus :: over1gMP_lh [04:04] */ 10913 #define PHY84328_DEV7_MISCRXSTATUS_OVER1GMP_LH_MASK 0x0010 10914 #define PHY84328_DEV7_MISCRXSTATUS_OVER1GMP_LH_ALIGN 0 10915 #define PHY84328_DEV7_MISCRXSTATUS_OVER1GMP_LH_BITS 1 10916 #define PHY84328_DEV7_MISCRXSTATUS_OVER1GMP_LH_SHIFT 4 10917 10918 /* ln_device7 :: miscrxstatus :: rx_config_is_0_lh [03:03] */ 10919 #define PHY84328_DEV7_MISCRXSTATUS_RX_CONFIG_IS_0_LH_MASK 0x0008 10920 #define PHY84328_DEV7_MISCRXSTATUS_RX_CONFIG_IS_0_LH_ALIGN 0 10921 #define PHY84328_DEV7_MISCRXSTATUS_RX_CONFIG_IS_0_LH_BITS 1 10922 #define PHY84328_DEV7_MISCRXSTATUS_RX_CONFIG_IS_0_LH_SHIFT 3 10923 10924 /* ln_device7 :: miscrxstatus :: np_toggle_err_lh [02:02] */ 10925 #define PHY84328_DEV7_MISCRXSTATUS_NP_TOGGLE_ERR_LH_MASK 0x0004 10926 #define PHY84328_DEV7_MISCRXSTATUS_NP_TOGGLE_ERR_LH_ALIGN 0 10927 #define PHY84328_DEV7_MISCRXSTATUS_NP_TOGGLE_ERR_LH_BITS 1 10928 #define PHY84328_DEV7_MISCRXSTATUS_NP_TOGGLE_ERR_LH_SHIFT 2 10929 10930 /* ln_device7 :: miscrxstatus :: mr_np_lh [01:01] */ 10931 #define PHY84328_DEV7_MISCRXSTATUS_MR_NP_LH_MASK 0x0002 10932 #define PHY84328_DEV7_MISCRXSTATUS_MR_NP_LH_ALIGN 0 10933 #define PHY84328_DEV7_MISCRXSTATUS_MR_NP_LH_BITS 1 10934 #define PHY84328_DEV7_MISCRXSTATUS_MR_NP_LH_SHIFT 1 10935 10936 /* ln_device7 :: miscrxstatus :: mr_bp_lh [00:00] */ 10937 #define PHY84328_DEV7_MISCRXSTATUS_MR_BP_LH_MASK 0x0001 10938 #define PHY84328_DEV7_MISCRXSTATUS_MR_BP_LH_ALIGN 0 10939 #define PHY84328_DEV7_MISCRXSTATUS_MR_BP_LH_BITS 1 10940 #define PHY84328_DEV7_MISCRXSTATUS_MR_BP_LH_SHIFT 0 10941 10942 10943 /**************************************************************************** 10944 * ln_device7 :: x2500status1 10945 */ 10946 /* ln_device7 :: x2500status1 :: hcd_over_1g_or [15:15] */ 10947 #define PHY84328_DEV7_X2500STATUS1_HCD_OVER_1G_OR_MASK 0x8000 10948 #define PHY84328_DEV7_X2500STATUS1_HCD_OVER_1G_OR_ALIGN 0 10949 #define PHY84328_DEV7_X2500STATUS1_HCD_OVER_1G_OR_BITS 1 10950 #define PHY84328_DEV7_X2500STATUS1_HCD_OVER_1G_OR_SHIFT 15 10951 10952 /* ln_device7 :: x2500status1 :: latch_hcd_over_1g [14:14] */ 10953 #define PHY84328_DEV7_X2500STATUS1_LATCH_HCD_OVER_1G_MASK 0x4000 10954 #define PHY84328_DEV7_X2500STATUS1_LATCH_HCD_OVER_1G_ALIGN 0 10955 #define PHY84328_DEV7_X2500STATUS1_LATCH_HCD_OVER_1G_BITS 1 10956 #define PHY84328_DEV7_X2500STATUS1_LATCH_HCD_OVER_1G_SHIFT 14 10957 10958 /* ln_device7 :: x2500status1 :: latchmdio [13:13] */ 10959 #define PHY84328_DEV7_X2500STATUS1_LATCHMDIO_MASK 0x2000 10960 #define PHY84328_DEV7_X2500STATUS1_LATCHMDIO_ALIGN 0 10961 #define PHY84328_DEV7_X2500STATUS1_LATCHMDIO_BITS 1 10962 #define PHY84328_DEV7_X2500STATUS1_LATCHMDIO_SHIFT 13 10963 10964 /* ln_device7 :: x2500status1 :: s_bc_reg_rst [12:12] */ 10965 #define PHY84328_DEV7_X2500STATUS1_S_BC_REG_RST_MASK 0x1000 10966 #define PHY84328_DEV7_X2500STATUS1_S_BC_REG_RST_ALIGN 0 10967 #define PHY84328_DEV7_X2500STATUS1_S_BC_REG_RST_BITS 1 10968 #define PHY84328_DEV7_X2500STATUS1_S_BC_REG_RST_SHIFT 12 10969 10970 /* ln_device7 :: x2500status1 :: s_wait2res [11:11] */ 10971 #define PHY84328_DEV7_X2500STATUS1_S_WAIT2RES_MASK 0x0800 10972 #define PHY84328_DEV7_X2500STATUS1_S_WAIT2RES_ALIGN 0 10973 #define PHY84328_DEV7_X2500STATUS1_S_WAIT2RES_BITS 1 10974 #define PHY84328_DEV7_X2500STATUS1_S_WAIT2RES_SHIFT 11 10975 10976 /* ln_device7 :: x2500status1 :: s_wait30ms [10:10] */ 10977 #define PHY84328_DEV7_X2500STATUS1_S_WAIT30MS_MASK 0x0400 10978 #define PHY84328_DEV7_X2500STATUS1_S_WAIT30MS_ALIGN 0 10979 #define PHY84328_DEV7_X2500STATUS1_S_WAIT30MS_BITS 1 10980 #define PHY84328_DEV7_X2500STATUS1_S_WAIT30MS_SHIFT 10 10981 10982 /* ln_device7 :: x2500status1 :: s_clockswit [09:09] */ 10983 #define PHY84328_DEV7_X2500STATUS1_S_CLOCKSWIT_MASK 0x0200 10984 #define PHY84328_DEV7_X2500STATUS1_S_CLOCKSWIT_ALIGN 0 10985 #define PHY84328_DEV7_X2500STATUS1_S_CLOCKSWIT_BITS 1 10986 #define PHY84328_DEV7_X2500STATUS1_S_CLOCKSWIT_SHIFT 9 10987 10988 /* ln_device7 :: x2500status1 :: s_pllswit [08:08] */ 10989 #define PHY84328_DEV7_X2500STATUS1_S_PLLSWIT_MASK 0x0100 10990 #define PHY84328_DEV7_X2500STATUS1_S_PLLSWIT_ALIGN 0 10991 #define PHY84328_DEV7_X2500STATUS1_S_PLLSWIT_BITS 1 10992 #define PHY84328_DEV7_X2500STATUS1_S_PLLSWIT_SHIFT 8 10993 10994 /* ln_device7 :: x2500status1 :: s_wait4link [07:07] */ 10995 #define PHY84328_DEV7_X2500STATUS1_S_WAIT4LINK_MASK 0x0080 10996 #define PHY84328_DEV7_X2500STATUS1_S_WAIT4LINK_ALIGN 0 10997 #define PHY84328_DEV7_X2500STATUS1_S_WAIT4LINK_BITS 1 10998 #define PHY84328_DEV7_X2500STATUS1_S_WAIT4LINK_SHIFT 7 10999 11000 /* ln_device7 :: x2500status1 :: s_complete [06:06] */ 11001 #define PHY84328_DEV7_X2500STATUS1_S_COMPLETE_MASK 0x0040 11002 #define PHY84328_DEV7_X2500STATUS1_S_COMPLETE_ALIGN 0 11003 #define PHY84328_DEV7_X2500STATUS1_S_COMPLETE_BITS 1 11004 #define PHY84328_DEV7_X2500STATUS1_S_COMPLETE_SHIFT 6 11005 11006 /* ln_device7 :: x2500status1 :: s_lostlink [05:05] */ 11007 #define PHY84328_DEV7_X2500STATUS1_S_LOSTLINK_MASK 0x0020 11008 #define PHY84328_DEV7_X2500STATUS1_S_LOSTLINK_ALIGN 0 11009 #define PHY84328_DEV7_X2500STATUS1_S_LOSTLINK_BITS 1 11010 #define PHY84328_DEV7_X2500STATUS1_S_LOSTLINK_SHIFT 5 11011 11012 /* ln_device7 :: x2500status1 :: s_dead [04:04] */ 11013 #define PHY84328_DEV7_X2500STATUS1_S_DEAD_MASK 0x0010 11014 #define PHY84328_DEV7_X2500STATUS1_S_DEAD_ALIGN 0 11015 #define PHY84328_DEV7_X2500STATUS1_S_DEAD_BITS 1 11016 #define PHY84328_DEV7_X2500STATUS1_S_DEAD_SHIFT 4 11017 11018 /* ln_device7 :: x2500status1 :: fail_cnt [03:00] */ 11019 #define PHY84328_DEV7_X2500STATUS1_FAIL_CNT_MASK 0x000f 11020 #define PHY84328_DEV7_X2500STATUS1_FAIL_CNT_ALIGN 0 11021 #define PHY84328_DEV7_X2500STATUS1_FAIL_CNT_BITS 4 11022 #define PHY84328_DEV7_X2500STATUS1_FAIL_CNT_SHIFT 0 11023 11024 11025 /**************************************************************************** 11026 * ln_device7 :: topanstatus1 11027 */ 11028 /* ln_device7 :: topanstatus1 :: reserved0 [15:14] */ 11029 #define PHY84328_DEV7_TOPANSTATUS1_RESERVED0_MASK 0xc000 11030 #define PHY84328_DEV7_TOPANSTATUS1_RESERVED0_ALIGN 0 11031 #define PHY84328_DEV7_TOPANSTATUS1_RESERVED0_BITS 2 11032 #define PHY84328_DEV7_TOPANSTATUS1_RESERVED0_SHIFT 14 11033 11034 /* ln_device7 :: topanstatus1 :: actual_speed [13:08] */ 11035 #define PHY84328_DEV7_TOPANSTATUS1_ACTUAL_SPEED_MASK 0x3f00 11036 #define PHY84328_DEV7_TOPANSTATUS1_ACTUAL_SPEED_ALIGN 0 11037 #define PHY84328_DEV7_TOPANSTATUS1_ACTUAL_SPEED_BITS 6 11038 #define PHY84328_DEV7_TOPANSTATUS1_ACTUAL_SPEED_SHIFT 8 11039 11040 /* ln_device7 :: topanstatus1 :: pause_resolution_rxside [07:07] */ 11041 #define PHY84328_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0080 11042 #define PHY84328_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 11043 #define PHY84328_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_BITS 1 11044 #define PHY84328_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_SHIFT 7 11045 11046 /* ln_device7 :: topanstatus1 :: pause_resolution_txside [06:06] */ 11047 #define PHY84328_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0040 11048 #define PHY84328_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 11049 #define PHY84328_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_BITS 1 11050 #define PHY84328_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_SHIFT 6 11051 11052 /* ln_device7 :: topanstatus1 :: cl73_lp_np_BAM_able [05:05] */ 11053 #define PHY84328_DEV7_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_MASK 0x0020 11054 #define PHY84328_DEV7_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_ALIGN 0 11055 #define PHY84328_DEV7_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_BITS 1 11056 #define PHY84328_DEV7_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_SHIFT 5 11057 11058 /* ln_device7 :: topanstatus1 :: cl73_mr_lp_autoneg_able [04:04] */ 11059 #define PHY84328_DEV7_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_MASK 0x0010 11060 #define PHY84328_DEV7_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 11061 #define PHY84328_DEV7_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_BITS 1 11062 #define PHY84328_DEV7_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 11063 11064 /* ln_device7 :: topanstatus1 :: duplex_status [03:03] */ 11065 #define PHY84328_DEV7_TOPANSTATUS1_DUPLEX_STATUS_MASK 0x0008 11066 #define PHY84328_DEV7_TOPANSTATUS1_DUPLEX_STATUS_ALIGN 0 11067 #define PHY84328_DEV7_TOPANSTATUS1_DUPLEX_STATUS_BITS 1 11068 #define PHY84328_DEV7_TOPANSTATUS1_DUPLEX_STATUS_SHIFT 3 11069 11070 /* ln_device7 :: topanstatus1 :: link_status [02:02] */ 11071 #define PHY84328_DEV7_TOPANSTATUS1_LINK_STATUS_MASK 0x0004 11072 #define PHY84328_DEV7_TOPANSTATUS1_LINK_STATUS_ALIGN 0 11073 #define PHY84328_DEV7_TOPANSTATUS1_LINK_STATUS_BITS 1 11074 #define PHY84328_DEV7_TOPANSTATUS1_LINK_STATUS_SHIFT 2 11075 11076 /* ln_device7 :: topanstatus1 :: cl37_autoneg_complete [01:01] */ 11077 #define PHY84328_DEV7_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK 0x0002 11078 #define PHY84328_DEV7_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN 0 11079 #define PHY84328_DEV7_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS 1 11080 #define PHY84328_DEV7_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT 1 11081 11082 /* ln_device7 :: topanstatus1 :: cl73_autoneg_complete [00:00] */ 11083 #define PHY84328_DEV7_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK 0x0001 11084 #define PHY84328_DEV7_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN 0 11085 #define PHY84328_DEV7_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS 1 11086 #define PHY84328_DEV7_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT 0 11087 11088 11089 /**************************************************************************** 11090 * ln_device7 :: lp_up1 11091 */ 11092 /* ln_device7 :: lp_up1 :: reserved0 [15:11] */ 11093 #define PHY84328_DEV7_LP_UP1_RESERVED0_MASK 0xf800 11094 #define PHY84328_DEV7_LP_UP1_RESERVED0_ALIGN 0 11095 #define PHY84328_DEV7_LP_UP1_RESERVED0_BITS 5 11096 #define PHY84328_DEV7_LP_UP1_RESERVED0_SHIFT 11 11097 11098 /* ln_device7 :: lp_up1 :: lp_adv_over_1g [10:00] */ 11099 #define PHY84328_DEV7_LP_UP1_LP_ADV_OVER_1G_MASK 0x07ff 11100 #define PHY84328_DEV7_LP_UP1_LP_ADV_OVER_1G_ALIGN 0 11101 #define PHY84328_DEV7_LP_UP1_LP_ADV_OVER_1G_BITS 11 11102 #define PHY84328_DEV7_LP_UP1_LP_ADV_OVER_1G_SHIFT 0 11103 11104 11105 /**************************************************************************** 11106 * ln_device7 :: lp_up2 11107 */ 11108 /* ln_device7 :: lp_up2 :: reserved0 [15:11] */ 11109 #define PHY84328_DEV7_LP_UP2_RESERVED0_MASK 0xf800 11110 #define PHY84328_DEV7_LP_UP2_RESERVED0_ALIGN 0 11111 #define PHY84328_DEV7_LP_UP2_RESERVED0_BITS 5 11112 #define PHY84328_DEV7_LP_UP2_RESERVED0_SHIFT 11 11113 11114 /* ln_device7 :: lp_up2 :: lp_adv_over_1g [10:00] */ 11115 #define PHY84328_DEV7_LP_UP2_LP_ADV_OVER_1G_MASK 0x07ff 11116 #define PHY84328_DEV7_LP_UP2_LP_ADV_OVER_1G_ALIGN 0 11117 #define PHY84328_DEV7_LP_UP2_LP_ADV_OVER_1G_BITS 11 11118 #define PHY84328_DEV7_LP_UP2_LP_ADV_OVER_1G_SHIFT 0 11119 11120 11121 /**************************************************************************** 11122 * ln_device7 :: lp_up3 11123 */ 11124 /* ln_device7 :: lp_up3 :: reserved0 [15:11] */ 11125 #define PHY84328_DEV7_LP_UP3_RESERVED0_MASK 0xf800 11126 #define PHY84328_DEV7_LP_UP3_RESERVED0_ALIGN 0 11127 #define PHY84328_DEV7_LP_UP3_RESERVED0_BITS 5 11128 #define PHY84328_DEV7_LP_UP3_RESERVED0_SHIFT 11 11129 11130 /* ln_device7 :: lp_up3 :: lp_adv_over_1g [10:00] */ 11131 #define PHY84328_DEV7_LP_UP3_LP_ADV_OVER_1G_MASK 0x07ff 11132 #define PHY84328_DEV7_LP_UP3_LP_ADV_OVER_1G_ALIGN 0 11133 #define PHY84328_DEV7_LP_UP3_LP_ADV_OVER_1G_BITS 11 11134 #define PHY84328_DEV7_LP_UP3_LP_ADV_OVER_1G_SHIFT 0 11135 11136 11137 /**************************************************************************** 11138 * ln_device7_userPerLnCtrl_Registers 11139 */ 11140 /**************************************************************************** 11141 * ln_device7 :: cl73Control1 11142 */ 11143 /* ln_device7 :: cl73Control1 :: reserved0 [15:08] */ 11144 #define PHY84328_DEV7_CL73CONTROL1_RESERVED0_MASK 0xff00 11145 #define PHY84328_DEV7_CL73CONTROL1_RESERVED0_ALIGN 0 11146 #define PHY84328_DEV7_CL73CONTROL1_RESERVED0_BITS 8 11147 #define PHY84328_DEV7_CL73CONTROL1_RESERVED0_SHIFT 8 11148 11149 /* ln_device7 :: cl73Control1 :: cl73_internal_10us_timer_val [07:00] */ 11150 #define PHY84328_DEV7_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_MASK 0x00ff 11151 #define PHY84328_DEV7_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_ALIGN 0 11152 #define PHY84328_DEV7_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_BITS 8 11153 #define PHY84328_DEV7_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_SHIFT 0 11154 11155 11156 /**************************************************************************** 11157 * ln_device7 :: cl73Control2 11158 */ 11159 /* ln_device7 :: cl73Control2 :: reserved0 [15:13] */ 11160 #define PHY84328_DEV7_CL73CONTROL2_RESERVED0_MASK 0xe000 11161 #define PHY84328_DEV7_CL73CONTROL2_RESERVED0_ALIGN 0 11162 #define PHY84328_DEV7_CL73CONTROL2_RESERVED0_BITS 3 11163 #define PHY84328_DEV7_CL73CONTROL2_RESERVED0_SHIFT 13 11164 11165 /* ln_device7 :: cl73Control2 :: cl73_link_fail_inhibit_timer_val [12:00] */ 11166 #define PHY84328_DEV7_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_MASK 0x1fff 11167 #define PHY84328_DEV7_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_ALIGN 0 11168 #define PHY84328_DEV7_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_BITS 13 11169 #define PHY84328_DEV7_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_SHIFT 0 11170 11171 11172 /**************************************************************************** 11173 * ln_device7 :: cl73Control3 11174 */ 11175 /* ln_device7 :: cl73Control3 :: reserved0 [15:13] */ 11176 #define PHY84328_DEV7_CL73CONTROL3_RESERVED0_MASK 0xe000 11177 #define PHY84328_DEV7_CL73CONTROL3_RESERVED0_ALIGN 0 11178 #define PHY84328_DEV7_CL73CONTROL3_RESERVED0_BITS 3 11179 #define PHY84328_DEV7_CL73CONTROL3_RESERVED0_SHIFT 13 11180 11181 /* ln_device7 :: cl73Control3 :: cl73_an_wait_timer_val [12:00] */ 11182 #define PHY84328_DEV7_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_MASK 0x1fff 11183 #define PHY84328_DEV7_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_ALIGN 0 11184 #define PHY84328_DEV7_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_BITS 13 11185 #define PHY84328_DEV7_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_SHIFT 0 11186 11187 11188 /**************************************************************************** 11189 * ln_device7 :: cl73Control4 11190 */ 11191 /* ln_device7 :: cl73Control4 :: reserved0 [15:13] */ 11192 #define PHY84328_DEV7_CL73CONTROL4_RESERVED0_MASK 0xe000 11193 #define PHY84328_DEV7_CL73CONTROL4_RESERVED0_ALIGN 0 11194 #define PHY84328_DEV7_CL73CONTROL4_RESERVED0_BITS 3 11195 #define PHY84328_DEV7_CL73CONTROL4_RESERVED0_SHIFT 13 11196 11197 /* ln_device7 :: cl73Control4 :: cl73_break_link_timer_val [12:00] */ 11198 #define PHY84328_DEV7_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_MASK 0x1fff 11199 #define PHY84328_DEV7_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_ALIGN 0 11200 #define PHY84328_DEV7_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_BITS 13 11201 #define PHY84328_DEV7_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_SHIFT 0 11202 11203 11204 /**************************************************************************** 11205 * ln_device7 :: cl73Control5 11206 */ 11207 /* ln_device7 :: cl73Control5 :: reserved0 [15:13] */ 11208 #define PHY84328_DEV7_CL73CONTROL5_RESERVED0_MASK 0xe000 11209 #define PHY84328_DEV7_CL73CONTROL5_RESERVED0_ALIGN 0 11210 #define PHY84328_DEV7_CL73CONTROL5_RESERVED0_BITS 3 11211 #define PHY84328_DEV7_CL73CONTROL5_RESERVED0_SHIFT 13 11212 11213 /* ln_device7 :: cl73Control5 :: cl73_break_link_timer_bam_val [12:00] */ 11214 #define PHY84328_DEV7_CL73CONTROL5_CL73_BREAK_LINK_TIMER_BAM_VAL_MASK 0x1fff 11215 #define PHY84328_DEV7_CL73CONTROL5_CL73_BREAK_LINK_TIMER_BAM_VAL_ALIGN 0 11216 #define PHY84328_DEV7_CL73CONTROL5_CL73_BREAK_LINK_TIMER_BAM_VAL_BITS 13 11217 #define PHY84328_DEV7_CL73CONTROL5_CL73_BREAK_LINK_TIMER_BAM_VAL_SHIFT 0 11218 11219 11220 /**************************************************************************** 11221 * ln_device7 :: cl73Control6 11222 */ 11223 /* ln_device7 :: cl73Control6 :: reserved0 [15:13] */ 11224 #define PHY84328_DEV7_CL73CONTROL6_RESERVED0_MASK 0xe000 11225 #define PHY84328_DEV7_CL73CONTROL6_RESERVED0_ALIGN 0 11226 #define PHY84328_DEV7_CL73CONTROL6_RESERVED0_BITS 3 11227 #define PHY84328_DEV7_CL73CONTROL6_RESERVED0_SHIFT 13 11228 11229 /* ln_device7 :: cl73Control6 :: cl73_ignore_link_timer_val [12:00] */ 11230 #define PHY84328_DEV7_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_MASK 0x1fff 11231 #define PHY84328_DEV7_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_ALIGN 0 11232 #define PHY84328_DEV7_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_BITS 13 11233 #define PHY84328_DEV7_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_SHIFT 0 11234 11235 11236 /**************************************************************************** 11237 * ln_device7 :: cl73DmeTmrs 11238 */ 11239 /* ln_device7 :: cl73DmeTmrs :: cl73_dme_page_test_max_cnt_val [15:08] */ 11240 #define PHY84328_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_MASK 0xff00 11241 #define PHY84328_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_ALIGN 0 11242 #define PHY84328_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_BITS 8 11243 #define PHY84328_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_SHIFT 8 11244 11245 /* ln_device7 :: cl73DmeTmrs :: cl73_dme_page_test_min_cnt_val [07:00] */ 11246 #define PHY84328_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_MASK 0x00ff 11247 #define PHY84328_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_ALIGN 0 11248 #define PHY84328_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_BITS 8 11249 #define PHY84328_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_SHIFT 0 11250 11251 11252 /**************************************************************************** 11253 * ln_device7 :: Control1000X1 11254 */ 11255 /* ln_device7 :: Control1000X1 :: reserved0 [15:15] */ 11256 #define PHY84328_DEV7_CONTROL1000X1_RESERVED0_MASK 0x8000 11257 #define PHY84328_DEV7_CONTROL1000X1_RESERVED0_ALIGN 0 11258 #define PHY84328_DEV7_CONTROL1000X1_RESERVED0_BITS 1 11259 #define PHY84328_DEV7_CONTROL1000X1_RESERVED0_SHIFT 15 11260 11261 /* ln_device7 :: Control1000X1 :: disable_signal_detect_filter [14:14] */ 11262 #define PHY84328_DEV7_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000 11263 #define PHY84328_DEV7_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0 11264 #define PHY84328_DEV7_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1 11265 #define PHY84328_DEV7_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14 11266 11267 /* ln_device7 :: Control1000X1 :: reserved1 [13:12] */ 11268 #define PHY84328_DEV7_CONTROL1000X1_RESERVED1_MASK 0x3000 11269 #define PHY84328_DEV7_CONTROL1000X1_RESERVED1_ALIGN 0 11270 #define PHY84328_DEV7_CONTROL1000X1_RESERVED1_BITS 2 11271 #define PHY84328_DEV7_CONTROL1000X1_RESERVED1_SHIFT 12 11272 11273 /* ln_device7 :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */ 11274 #define PHY84328_DEV7_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK 0x0800 11275 #define PHY84328_DEV7_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN 0 11276 #define PHY84328_DEV7_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS 1 11277 #define PHY84328_DEV7_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT 11 11278 11279 /* ln_device7 :: Control1000X1 :: remote_loopback [10:10] */ 11280 #define PHY84328_DEV7_CONTROL1000X1_REMOTE_LOOPBACK_MASK 0x0400 11281 #define PHY84328_DEV7_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN 0 11282 #define PHY84328_DEV7_CONTROL1000X1_REMOTE_LOOPBACK_BITS 1 11283 #define PHY84328_DEV7_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT 10 11284 11285 /* ln_device7 :: Control1000X1 :: zero_comma_detector_phase [09:09] */ 11286 #define PHY84328_DEV7_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200 11287 #define PHY84328_DEV7_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0 11288 #define PHY84328_DEV7_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1 11289 #define PHY84328_DEV7_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9 11290 11291 /* ln_device7 :: Control1000X1 :: comma_det_en [08:08] */ 11292 #define PHY84328_DEV7_CONTROL1000X1_COMMA_DET_EN_MASK 0x0100 11293 #define PHY84328_DEV7_CONTROL1000X1_COMMA_DET_EN_ALIGN 0 11294 #define PHY84328_DEV7_CONTROL1000X1_COMMA_DET_EN_BITS 1 11295 #define PHY84328_DEV7_CONTROL1000X1_COMMA_DET_EN_SHIFT 8 11296 11297 /* ln_device7 :: Control1000X1 :: crc_checker_disable [07:07] */ 11298 #define PHY84328_DEV7_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK 0x0080 11299 #define PHY84328_DEV7_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN 0 11300 #define PHY84328_DEV7_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS 1 11301 #define PHY84328_DEV7_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT 7 11302 11303 /* ln_device7 :: Control1000X1 :: disable_pll_pwrdwn [06:06] */ 11304 #define PHY84328_DEV7_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK 0x0040 11305 #define PHY84328_DEV7_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN 0 11306 #define PHY84328_DEV7_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS 1 11307 #define PHY84328_DEV7_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT 6 11308 11309 /* ln_device7 :: Control1000X1 :: sgmii_master_mode [05:05] */ 11310 #define PHY84328_DEV7_CONTROL1000X1_SGMII_MASTER_MODE_MASK 0x0020 11311 #define PHY84328_DEV7_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN 0 11312 #define PHY84328_DEV7_CONTROL1000X1_SGMII_MASTER_MODE_BITS 1 11313 #define PHY84328_DEV7_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT 5 11314 11315 /* ln_device7 :: Control1000X1 :: autodet_en [04:04] */ 11316 #define PHY84328_DEV7_CONTROL1000X1_AUTODET_EN_MASK 0x0010 11317 #define PHY84328_DEV7_CONTROL1000X1_AUTODET_EN_ALIGN 0 11318 #define PHY84328_DEV7_CONTROL1000X1_AUTODET_EN_BITS 1 11319 #define PHY84328_DEV7_CONTROL1000X1_AUTODET_EN_SHIFT 4 11320 11321 /* ln_device7 :: Control1000X1 :: invert_signal_detect [03:03] */ 11322 #define PHY84328_DEV7_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK 0x0008 11323 #define PHY84328_DEV7_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN 0 11324 #define PHY84328_DEV7_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS 1 11325 #define PHY84328_DEV7_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT 3 11326 11327 /* ln_device7 :: Control1000X1 :: signal_detect_en [02:02] */ 11328 #define PHY84328_DEV7_CONTROL1000X1_SIGNAL_DETECT_EN_MASK 0x0004 11329 #define PHY84328_DEV7_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN 0 11330 #define PHY84328_DEV7_CONTROL1000X1_SIGNAL_DETECT_EN_BITS 1 11331 #define PHY84328_DEV7_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT 2 11332 11333 /* ln_device7 :: Control1000X1 :: tbi_interface [01:01] */ 11334 #define PHY84328_DEV7_CONTROL1000X1_TBI_INTERFACE_MASK 0x0002 11335 #define PHY84328_DEV7_CONTROL1000X1_TBI_INTERFACE_ALIGN 0 11336 #define PHY84328_DEV7_CONTROL1000X1_TBI_INTERFACE_BITS 1 11337 #define PHY84328_DEV7_CONTROL1000X1_TBI_INTERFACE_SHIFT 1 11338 11339 /* ln_device7 :: Control1000X1 :: fiber_mode_1000X [00:00] */ 11340 #define PHY84328_DEV7_CONTROL1000X1_FIBER_MODE_1000X_MASK 0x0001 11341 #define PHY84328_DEV7_CONTROL1000X1_FIBER_MODE_1000X_ALIGN 0 11342 #define PHY84328_DEV7_CONTROL1000X1_FIBER_MODE_1000X_BITS 1 11343 #define PHY84328_DEV7_CONTROL1000X1_FIBER_MODE_1000X_SHIFT 0 11344 11345 11346 /**************************************************************************** 11347 * ln_device7 :: Control1000X2 11348 */ 11349 /* ln_device7 :: Control1000X2 :: disable_extend_fdx_only [15:15] */ 11350 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK 0x8000 11351 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0 11352 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS 1 11353 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15 11354 11355 /* ln_device7 :: Control1000X2 :: clear_ber_counter [14:14] */ 11356 #define PHY84328_DEV7_CONTROL1000X2_CLEAR_BER_COUNTER_MASK 0x4000 11357 #define PHY84328_DEV7_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN 0 11358 #define PHY84328_DEV7_CONTROL1000X2_CLEAR_BER_COUNTER_BITS 1 11359 #define PHY84328_DEV7_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT 14 11360 11361 /* ln_device7 :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */ 11362 #define PHY84328_DEV7_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000 11363 #define PHY84328_DEV7_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0 11364 #define PHY84328_DEV7_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1 11365 #define PHY84328_DEV7_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13 11366 11367 /* ln_device7 :: Control1000X2 :: transmit_packet_seq_test [12:12] */ 11368 #define PHY84328_DEV7_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK 0x1000 11369 #define PHY84328_DEV7_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0 11370 #define PHY84328_DEV7_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS 1 11371 #define PHY84328_DEV7_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12 11372 11373 /* ln_device7 :: Control1000X2 :: test_cntr [11:11] */ 11374 #define PHY84328_DEV7_CONTROL1000X2_TEST_CNTR_MASK 0x0800 11375 #define PHY84328_DEV7_CONTROL1000X2_TEST_CNTR_ALIGN 0 11376 #define PHY84328_DEV7_CONTROL1000X2_TEST_CNTR_BITS 1 11377 #define PHY84328_DEV7_CONTROL1000X2_TEST_CNTR_SHIFT 11 11378 11379 /* ln_device7 :: Control1000X2 :: bypass_pcs_tx [10:10] */ 11380 #define PHY84328_DEV7_CONTROL1000X2_BYPASS_PCS_TX_MASK 0x0400 11381 #define PHY84328_DEV7_CONTROL1000X2_BYPASS_PCS_TX_ALIGN 0 11382 #define PHY84328_DEV7_CONTROL1000X2_BYPASS_PCS_TX_BITS 1 11383 #define PHY84328_DEV7_CONTROL1000X2_BYPASS_PCS_TX_SHIFT 10 11384 11385 /* ln_device7 :: Control1000X2 :: bypass_pcs_rx [09:09] */ 11386 #define PHY84328_DEV7_CONTROL1000X2_BYPASS_PCS_RX_MASK 0x0200 11387 #define PHY84328_DEV7_CONTROL1000X2_BYPASS_PCS_RX_ALIGN 0 11388 #define PHY84328_DEV7_CONTROL1000X2_BYPASS_PCS_RX_BITS 1 11389 #define PHY84328_DEV7_CONTROL1000X2_BYPASS_PCS_RX_SHIFT 9 11390 11391 /* ln_device7 :: Control1000X2 :: disable_TRRR_generation [08:08] */ 11392 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK 0x0100 11393 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0 11394 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS 1 11395 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8 11396 11397 /* ln_device7 :: Control1000X2 :: disable_carrier_extend [07:07] */ 11398 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK 0x0080 11399 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN 0 11400 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS 1 11401 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT 7 11402 11403 /* ln_device7 :: Control1000X2 :: autoneg_fast_timers [06:06] */ 11404 #define PHY84328_DEV7_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK 0x0040 11405 #define PHY84328_DEV7_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN 0 11406 #define PHY84328_DEV7_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS 1 11407 #define PHY84328_DEV7_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT 6 11408 11409 /* ln_device7 :: Control1000X2 :: force_xmit_data_on_txside [05:05] */ 11410 #define PHY84328_DEV7_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020 11411 #define PHY84328_DEV7_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0 11412 #define PHY84328_DEV7_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1 11413 #define PHY84328_DEV7_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5 11414 11415 /* ln_device7 :: Control1000X2 :: disable_remote_fault_sensing [04:04] */ 11416 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010 11417 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0 11418 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1 11419 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4 11420 11421 /* ln_device7 :: Control1000X2 :: enable_autoneg_err_timer [03:03] */ 11422 #define PHY84328_DEV7_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008 11423 #define PHY84328_DEV7_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0 11424 #define PHY84328_DEV7_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1 11425 #define PHY84328_DEV7_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3 11426 11427 /* ln_device7 :: Control1000X2 :: filter_force_link [02:02] */ 11428 #define PHY84328_DEV7_CONTROL1000X2_FILTER_FORCE_LINK_MASK 0x0004 11429 #define PHY84328_DEV7_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN 0 11430 #define PHY84328_DEV7_CONTROL1000X2_FILTER_FORCE_LINK_BITS 1 11431 #define PHY84328_DEV7_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT 2 11432 11433 /* ln_device7 :: Control1000X2 :: disable_false_link [01:01] */ 11434 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_FALSE_LINK_MASK 0x0002 11435 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN 0 11436 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_FALSE_LINK_BITS 1 11437 #define PHY84328_DEV7_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT 1 11438 11439 /* ln_device7 :: Control1000X2 :: enable_parallel_detection [00:00] */ 11440 #define PHY84328_DEV7_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK 0x0001 11441 #define PHY84328_DEV7_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN 0 11442 #define PHY84328_DEV7_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS 1 11443 #define PHY84328_DEV7_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT 0 11444 11445 11446 /**************************************************************************** 11447 * ln_device7 :: Control1000X3 11448 */ 11449 /* ln_device7 :: Control1000X3 :: disable_packet_misalign [15:15] */ 11450 #define PHY84328_DEV7_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK 0x8000 11451 #define PHY84328_DEV7_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN 0 11452 #define PHY84328_DEV7_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS 1 11453 #define PHY84328_DEV7_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT 15 11454 11455 /* ln_device7 :: Control1000X3 :: rxfifo_gmii_reset [14:14] */ 11456 #define PHY84328_DEV7_CONTROL1000X3_RXFIFO_GMII_RESET_MASK 0x4000 11457 #define PHY84328_DEV7_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN 0 11458 #define PHY84328_DEV7_CONTROL1000X3_RXFIFO_GMII_RESET_BITS 1 11459 #define PHY84328_DEV7_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT 14 11460 11461 /* ln_device7 :: Control1000X3 :: disable_tx_crs [13:13] */ 11462 #define PHY84328_DEV7_CONTROL1000X3_DISABLE_TX_CRS_MASK 0x2000 11463 #define PHY84328_DEV7_CONTROL1000X3_DISABLE_TX_CRS_ALIGN 0 11464 #define PHY84328_DEV7_CONTROL1000X3_DISABLE_TX_CRS_BITS 1 11465 #define PHY84328_DEV7_CONTROL1000X3_DISABLE_TX_CRS_SHIFT 13 11466 11467 /* ln_device7 :: Control1000X3 :: invert_ext_phy_crs [12:12] */ 11468 #define PHY84328_DEV7_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK 0x1000 11469 #define PHY84328_DEV7_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN 0 11470 #define PHY84328_DEV7_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS 1 11471 #define PHY84328_DEV7_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT 12 11472 11473 /* ln_device7 :: Control1000X3 :: ext_phy_crs_mode [11:11] */ 11474 #define PHY84328_DEV7_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK 0x0800 11475 #define PHY84328_DEV7_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN 0 11476 #define PHY84328_DEV7_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS 1 11477 #define PHY84328_DEV7_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT 11 11478 11479 /* ln_device7 :: Control1000X3 :: jam_false_carrier_mode [10:10] */ 11480 #define PHY84328_DEV7_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK 0x0400 11481 #define PHY84328_DEV7_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN 0 11482 #define PHY84328_DEV7_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS 1 11483 #define PHY84328_DEV7_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT 10 11484 11485 /* ln_device7 :: Control1000X3 :: block_txen_mode [09:09] */ 11486 #define PHY84328_DEV7_CONTROL1000X3_BLOCK_TXEN_MODE_MASK 0x0200 11487 #define PHY84328_DEV7_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN 0 11488 #define PHY84328_DEV7_CONTROL1000X3_BLOCK_TXEN_MODE_BITS 1 11489 #define PHY84328_DEV7_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT 9 11490 11491 /* ln_device7 :: Control1000X3 :: force_txfifo_on [08:08] */ 11492 #define PHY84328_DEV7_CONTROL1000X3_FORCE_TXFIFO_ON_MASK 0x0100 11493 #define PHY84328_DEV7_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN 0 11494 #define PHY84328_DEV7_CONTROL1000X3_FORCE_TXFIFO_ON_BITS 1 11495 #define PHY84328_DEV7_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT 8 11496 11497 /* ln_device7 :: Control1000X3 :: bypass_txfifo1000 [07:07] */ 11498 #define PHY84328_DEV7_CONTROL1000X3_BYPASS_TXFIFO1000_MASK 0x0080 11499 #define PHY84328_DEV7_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN 0 11500 #define PHY84328_DEV7_CONTROL1000X3_BYPASS_TXFIFO1000_BITS 1 11501 #define PHY84328_DEV7_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT 7 11502 11503 /* ln_device7 :: Control1000X3 :: freq_lock_elasticity_tx [06:06] */ 11504 #define PHY84328_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_MASK 0x0040 11505 #define PHY84328_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_ALIGN 0 11506 #define PHY84328_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_BITS 1 11507 #define PHY84328_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_SHIFT 6 11508 11509 /* ln_device7 :: Control1000X3 :: freq_lock_elasticity_rx [05:05] */ 11510 #define PHY84328_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_MASK 0x0020 11511 #define PHY84328_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_ALIGN 0 11512 #define PHY84328_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_BITS 1 11513 #define PHY84328_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_SHIFT 5 11514 11515 /* ln_device7 :: Control1000X3 :: early_preamble_rx [04:04] */ 11516 #define PHY84328_DEV7_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK 0x0010 11517 #define PHY84328_DEV7_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN 0 11518 #define PHY84328_DEV7_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS 1 11519 #define PHY84328_DEV7_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT 4 11520 11521 /* ln_device7 :: Control1000X3 :: early_preamble_tx [03:03] */ 11522 #define PHY84328_DEV7_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK 0x0008 11523 #define PHY84328_DEV7_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN 0 11524 #define PHY84328_DEV7_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS 1 11525 #define PHY84328_DEV7_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT 3 11526 11527 /* ln_device7 :: Control1000X3 :: fifo_elasicity_tx [02:01] */ 11528 #define PHY84328_DEV7_CONTROL1000X3_FIFO_ELASICITY_TX_MASK 0x0006 11529 #define PHY84328_DEV7_CONTROL1000X3_FIFO_ELASICITY_TX_ALIGN 0 11530 #define PHY84328_DEV7_CONTROL1000X3_FIFO_ELASICITY_TX_BITS 2 11531 #define PHY84328_DEV7_CONTROL1000X3_FIFO_ELASICITY_TX_SHIFT 1 11532 11533 /* ln_device7 :: Control1000X3 :: tx_fifo_rst [00:00] */ 11534 #define PHY84328_DEV7_CONTROL1000X3_TX_FIFO_RST_MASK 0x0001 11535 #define PHY84328_DEV7_CONTROL1000X3_TX_FIFO_RST_ALIGN 0 11536 #define PHY84328_DEV7_CONTROL1000X3_TX_FIFO_RST_BITS 1 11537 #define PHY84328_DEV7_CONTROL1000X3_TX_FIFO_RST_SHIFT 0 11538 11539 11540 /**************************************************************************** 11541 * ln_device7 :: Control1000X4 11542 */ 11543 /* ln_device7 :: Control1000X4 :: reserved0 [15:14] */ 11544 #define PHY84328_DEV7_CONTROL1000X4_RESERVED0_MASK 0xc000 11545 #define PHY84328_DEV7_CONTROL1000X4_RESERVED0_ALIGN 0 11546 #define PHY84328_DEV7_CONTROL1000X4_RESERVED0_BITS 2 11547 #define PHY84328_DEV7_CONTROL1000X4_RESERVED0_SHIFT 14 11548 11549 /* ln_device7 :: Control1000X4 :: disable_resolution_err_restart [13:13] */ 11550 #define PHY84328_DEV7_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000 11551 #define PHY84328_DEV7_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0 11552 #define PHY84328_DEV7_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1 11553 #define PHY84328_DEV7_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13 11554 11555 /* ln_device7 :: Control1000X4 :: enable_last_resolution_err [12:12] */ 11556 #define PHY84328_DEV7_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000 11557 #define PHY84328_DEV7_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0 11558 #define PHY84328_DEV7_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1 11559 #define PHY84328_DEV7_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12 11560 11561 /* ln_device7 :: Control1000X4 :: tx_config_reg_sel [11:11] */ 11562 #define PHY84328_DEV7_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK 0x0800 11563 #define PHY84328_DEV7_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN 0 11564 #define PHY84328_DEV7_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS 1 11565 #define PHY84328_DEV7_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT 11 11566 11567 /* ln_device7 :: Control1000X4 :: zero_rxdgmii [10:10] */ 11568 #define PHY84328_DEV7_CONTROL1000X4_ZERO_RXDGMII_MASK 0x0400 11569 #define PHY84328_DEV7_CONTROL1000X4_ZERO_RXDGMII_ALIGN 0 11570 #define PHY84328_DEV7_CONTROL1000X4_ZERO_RXDGMII_BITS 1 11571 #define PHY84328_DEV7_CONTROL1000X4_ZERO_RXDGMII_SHIFT 10 11572 11573 /* ln_device7 :: Control1000X4 :: clear_linkdown [09:09] */ 11574 #define PHY84328_DEV7_CONTROL1000X4_CLEAR_LINKDOWN_MASK 0x0200 11575 #define PHY84328_DEV7_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN 0 11576 #define PHY84328_DEV7_CONTROL1000X4_CLEAR_LINKDOWN_BITS 1 11577 #define PHY84328_DEV7_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT 9 11578 11579 /* ln_device7 :: Control1000X4 :: latch_linkdown_enable [08:08] */ 11580 #define PHY84328_DEV7_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK 0x0100 11581 #define PHY84328_DEV7_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN 0 11582 #define PHY84328_DEV7_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS 1 11583 #define PHY84328_DEV7_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT 8 11584 11585 /* ln_device7 :: Control1000X4 :: link_force [07:07] */ 11586 #define PHY84328_DEV7_CONTROL1000X4_LINK_FORCE_MASK 0x0080 11587 #define PHY84328_DEV7_CONTROL1000X4_LINK_FORCE_ALIGN 0 11588 #define PHY84328_DEV7_CONTROL1000X4_LINK_FORCE_BITS 1 11589 #define PHY84328_DEV7_CONTROL1000X4_LINK_FORCE_SHIFT 7 11590 11591 /* ln_device7 :: Control1000X4 :: reserved1 [06:06] */ 11592 #define PHY84328_DEV7_CONTROL1000X4_RESERVED1_MASK 0x0040 11593 #define PHY84328_DEV7_CONTROL1000X4_RESERVED1_ALIGN 0 11594 #define PHY84328_DEV7_CONTROL1000X4_RESERVED1_BITS 1 11595 #define PHY84328_DEV7_CONTROL1000X4_RESERVED1_SHIFT 6 11596 11597 /* ln_device7 :: Control1000X4 :: lp_next_page_sel [05:05] */ 11598 #define PHY84328_DEV7_CONTROL1000X4_LP_NEXT_PAGE_SEL_MASK 0x0020 11599 #define PHY84328_DEV7_CONTROL1000X4_LP_NEXT_PAGE_SEL_ALIGN 0 11600 #define PHY84328_DEV7_CONTROL1000X4_LP_NEXT_PAGE_SEL_BITS 1 11601 #define PHY84328_DEV7_CONTROL1000X4_LP_NEXT_PAGE_SEL_SHIFT 5 11602 11603 /* ln_device7 :: Control1000X4 :: np_count_ClrnBp [04:04] */ 11604 #define PHY84328_DEV7_CONTROL1000X4_NP_COUNT_CLRNBP_MASK 0x0010 11605 #define PHY84328_DEV7_CONTROL1000X4_NP_COUNT_CLRNBP_ALIGN 0 11606 #define PHY84328_DEV7_CONTROL1000X4_NP_COUNT_CLRNBP_BITS 1 11607 #define PHY84328_DEV7_CONTROL1000X4_NP_COUNT_CLRNBP_SHIFT 4 11608 11609 /* ln_device7 :: Control1000X4 :: np_count_ClrnRd [03:03] */ 11610 #define PHY84328_DEV7_CONTROL1000X4_NP_COUNT_CLRNRD_MASK 0x0008 11611 #define PHY84328_DEV7_CONTROL1000X4_NP_COUNT_CLRNRD_ALIGN 0 11612 #define PHY84328_DEV7_CONTROL1000X4_NP_COUNT_CLRNRD_BITS 1 11613 #define PHY84328_DEV7_CONTROL1000X4_NP_COUNT_CLRNRD_SHIFT 3 11614 11615 /* ln_device7 :: Control1000X4 :: MiscRxStatus_sel [02:00] */ 11616 #define PHY84328_DEV7_CONTROL1000X4_MISCRXSTATUS_SEL_MASK 0x0007 11617 #define PHY84328_DEV7_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN 0 11618 #define PHY84328_DEV7_CONTROL1000X4_MISCRXSTATUS_SEL_BITS 3 11619 #define PHY84328_DEV7_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT 0 11620 11621 11622 /**************************************************************************** 11623 * ln_device7 :: Status1000X1 11624 */ 11625 /* ln_device7 :: Status1000X1 :: txfifo_err_detected [15:15] */ 11626 #define PHY84328_DEV7_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK 0x8000 11627 #define PHY84328_DEV7_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN 0 11628 #define PHY84328_DEV7_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS 1 11629 #define PHY84328_DEV7_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT 15 11630 11631 /* ln_device7 :: Status1000X1 :: rxfifo_err_detected [14:14] */ 11632 #define PHY84328_DEV7_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK 0x4000 11633 #define PHY84328_DEV7_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN 0 11634 #define PHY84328_DEV7_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS 1 11635 #define PHY84328_DEV7_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT 14 11636 11637 /* ln_device7 :: Status1000X1 :: false_carrier_detected [13:13] */ 11638 #define PHY84328_DEV7_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK 0x2000 11639 #define PHY84328_DEV7_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN 0 11640 #define PHY84328_DEV7_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS 1 11641 #define PHY84328_DEV7_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT 13 11642 11643 /* ln_device7 :: Status1000X1 :: crc_err_detected [12:12] */ 11644 #define PHY84328_DEV7_STATUS1000X1_CRC_ERR_DETECTED_MASK 0x1000 11645 #define PHY84328_DEV7_STATUS1000X1_CRC_ERR_DETECTED_ALIGN 0 11646 #define PHY84328_DEV7_STATUS1000X1_CRC_ERR_DETECTED_BITS 1 11647 #define PHY84328_DEV7_STATUS1000X1_CRC_ERR_DETECTED_SHIFT 12 11648 11649 /* ln_device7 :: Status1000X1 :: tx_err_detected [11:11] */ 11650 #define PHY84328_DEV7_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 11651 #define PHY84328_DEV7_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 11652 #define PHY84328_DEV7_STATUS1000X1_TX_ERR_DETECTED_BITS 1 11653 #define PHY84328_DEV7_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 11654 11655 /* ln_device7 :: Status1000X1 :: rx_err_detected [10:10] */ 11656 #define PHY84328_DEV7_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 11657 #define PHY84328_DEV7_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 11658 #define PHY84328_DEV7_STATUS1000X1_RX_ERR_DETECTED_BITS 1 11659 #define PHY84328_DEV7_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 11660 11661 /* ln_device7 :: Status1000X1 :: carrier_extend_err_detected [09:09] */ 11662 #define PHY84328_DEV7_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200 11663 #define PHY84328_DEV7_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0 11664 #define PHY84328_DEV7_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1 11665 #define PHY84328_DEV7_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9 11666 11667 /* ln_device7 :: Status1000X1 :: early_end_extension_detected [08:08] */ 11668 #define PHY84328_DEV7_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100 11669 #define PHY84328_DEV7_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0 11670 #define PHY84328_DEV7_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1 11671 #define PHY84328_DEV7_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8 11672 11673 /* ln_device7 :: Status1000X1 :: link_status_change [07:07] */ 11674 #define PHY84328_DEV7_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 11675 #define PHY84328_DEV7_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 11676 #define PHY84328_DEV7_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 11677 #define PHY84328_DEV7_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 11678 11679 /* ln_device7 :: Status1000X1 :: pause_resolution_rxside [06:06] */ 11680 #define PHY84328_DEV7_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0040 11681 #define PHY84328_DEV7_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 11682 #define PHY84328_DEV7_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS 1 11683 #define PHY84328_DEV7_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT 6 11684 11685 /* ln_device7 :: Status1000X1 :: pause_resolution_txside [05:05] */ 11686 #define PHY84328_DEV7_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0020 11687 #define PHY84328_DEV7_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 11688 #define PHY84328_DEV7_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS 1 11689 #define PHY84328_DEV7_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT 5 11690 11691 /* ln_device7 :: Status1000X1 :: speed_status [04:03] */ 11692 #define PHY84328_DEV7_STATUS1000X1_SPEED_STATUS_MASK 0x0018 11693 #define PHY84328_DEV7_STATUS1000X1_SPEED_STATUS_ALIGN 0 11694 #define PHY84328_DEV7_STATUS1000X1_SPEED_STATUS_BITS 2 11695 #define PHY84328_DEV7_STATUS1000X1_SPEED_STATUS_SHIFT 3 11696 11697 /* ln_device7 :: Status1000X1 :: duplex_status [02:02] */ 11698 #define PHY84328_DEV7_STATUS1000X1_DUPLEX_STATUS_MASK 0x0004 11699 #define PHY84328_DEV7_STATUS1000X1_DUPLEX_STATUS_ALIGN 0 11700 #define PHY84328_DEV7_STATUS1000X1_DUPLEX_STATUS_BITS 1 11701 #define PHY84328_DEV7_STATUS1000X1_DUPLEX_STATUS_SHIFT 2 11702 11703 /* ln_device7 :: Status1000X1 :: link_status [01:01] */ 11704 #define PHY84328_DEV7_STATUS1000X1_LINK_STATUS_MASK 0x0002 11705 #define PHY84328_DEV7_STATUS1000X1_LINK_STATUS_ALIGN 0 11706 #define PHY84328_DEV7_STATUS1000X1_LINK_STATUS_BITS 1 11707 #define PHY84328_DEV7_STATUS1000X1_LINK_STATUS_SHIFT 1 11708 11709 /* ln_device7 :: Status1000X1 :: sgmii_mode [00:00] */ 11710 #define PHY84328_DEV7_STATUS1000X1_SGMII_MODE_MASK 0x0001 11711 #define PHY84328_DEV7_STATUS1000X1_SGMII_MODE_ALIGN 0 11712 #define PHY84328_DEV7_STATUS1000X1_SGMII_MODE_BITS 1 11713 #define PHY84328_DEV7_STATUS1000X1_SGMII_MODE_SHIFT 0 11714 11715 11716 /**************************************************************************** 11717 * ln_device7 :: Status1000X2 11718 */ 11719 /* ln_device7 :: Status1000X2 :: sgmii_mode_change [15:15] */ 11720 #define PHY84328_DEV7_STATUS1000X2_SGMII_MODE_CHANGE_MASK 0x8000 11721 #define PHY84328_DEV7_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN 0 11722 #define PHY84328_DEV7_STATUS1000X2_SGMII_MODE_CHANGE_BITS 1 11723 #define PHY84328_DEV7_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT 15 11724 11725 /* ln_device7 :: Status1000X2 :: consistency_mismatch [14:14] */ 11726 #define PHY84328_DEV7_STATUS1000X2_CONSISTENCY_MISMATCH_MASK 0x4000 11727 #define PHY84328_DEV7_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN 0 11728 #define PHY84328_DEV7_STATUS1000X2_CONSISTENCY_MISMATCH_BITS 1 11729 #define PHY84328_DEV7_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT 14 11730 11731 /* ln_device7 :: Status1000X2 :: autoneg_resolution_err [13:13] */ 11732 #define PHY84328_DEV7_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK 0x2000 11733 #define PHY84328_DEV7_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN 0 11734 #define PHY84328_DEV7_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS 1 11735 #define PHY84328_DEV7_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT 13 11736 11737 /* ln_device7 :: Status1000X2 :: sgmii_selector_mismatch [12:12] */ 11738 #define PHY84328_DEV7_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK 0x1000 11739 #define PHY84328_DEV7_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN 0 11740 #define PHY84328_DEV7_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS 1 11741 #define PHY84328_DEV7_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT 12 11742 11743 /* ln_device7 :: Status1000X2 :: sync_status_fail [11:11] */ 11744 #define PHY84328_DEV7_STATUS1000X2_SYNC_STATUS_FAIL_MASK 0x0800 11745 #define PHY84328_DEV7_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN 0 11746 #define PHY84328_DEV7_STATUS1000X2_SYNC_STATUS_FAIL_BITS 1 11747 #define PHY84328_DEV7_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT 11 11748 11749 /* ln_device7 :: Status1000X2 :: sync_status_ok [10:10] */ 11750 #define PHY84328_DEV7_STATUS1000X2_SYNC_STATUS_OK_MASK 0x0400 11751 #define PHY84328_DEV7_STATUS1000X2_SYNC_STATUS_OK_ALIGN 0 11752 #define PHY84328_DEV7_STATUS1000X2_SYNC_STATUS_OK_BITS 1 11753 #define PHY84328_DEV7_STATUS1000X2_SYNC_STATUS_OK_SHIFT 10 11754 11755 /* ln_device7 :: Status1000X2 :: rudi_c [09:09] */ 11756 #define PHY84328_DEV7_STATUS1000X2_RUDI_C_MASK 0x0200 11757 #define PHY84328_DEV7_STATUS1000X2_RUDI_C_ALIGN 0 11758 #define PHY84328_DEV7_STATUS1000X2_RUDI_C_BITS 1 11759 #define PHY84328_DEV7_STATUS1000X2_RUDI_C_SHIFT 9 11760 11761 /* ln_device7 :: Status1000X2 :: rudi_I [08:08] */ 11762 #define PHY84328_DEV7_STATUS1000X2_RUDI_I_MASK 0x0100 11763 #define PHY84328_DEV7_STATUS1000X2_RUDI_I_ALIGN 0 11764 #define PHY84328_DEV7_STATUS1000X2_RUDI_I_BITS 1 11765 #define PHY84328_DEV7_STATUS1000X2_RUDI_I_SHIFT 8 11766 11767 /* ln_device7 :: Status1000X2 :: rudi_invalid [07:07] */ 11768 #define PHY84328_DEV7_STATUS1000X2_RUDI_INVALID_MASK 0x0080 11769 #define PHY84328_DEV7_STATUS1000X2_RUDI_INVALID_ALIGN 0 11770 #define PHY84328_DEV7_STATUS1000X2_RUDI_INVALID_BITS 1 11771 #define PHY84328_DEV7_STATUS1000X2_RUDI_INVALID_SHIFT 7 11772 11773 /* ln_device7 :: Status1000X2 :: linkDown_syncLoss [06:06] */ 11774 #define PHY84328_DEV7_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK 0x0040 11775 #define PHY84328_DEV7_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN 0 11776 #define PHY84328_DEV7_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS 1 11777 #define PHY84328_DEV7_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT 6 11778 11779 /* ln_device7 :: Status1000X2 :: idle_detect_state [05:05] */ 11780 #define PHY84328_DEV7_STATUS1000X2_IDLE_DETECT_STATE_MASK 0x0020 11781 #define PHY84328_DEV7_STATUS1000X2_IDLE_DETECT_STATE_ALIGN 0 11782 #define PHY84328_DEV7_STATUS1000X2_IDLE_DETECT_STATE_BITS 1 11783 #define PHY84328_DEV7_STATUS1000X2_IDLE_DETECT_STATE_SHIFT 5 11784 11785 /* ln_device7 :: Status1000X2 :: complete_acknowledge_state [04:04] */ 11786 #define PHY84328_DEV7_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010 11787 #define PHY84328_DEV7_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0 11788 #define PHY84328_DEV7_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1 11789 #define PHY84328_DEV7_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4 11790 11791 /* ln_device7 :: Status1000X2 :: acknowledge_detect_state [03:03] */ 11792 #define PHY84328_DEV7_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK 0x0008 11793 #define PHY84328_DEV7_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0 11794 #define PHY84328_DEV7_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS 1 11795 #define PHY84328_DEV7_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3 11796 11797 /* ln_device7 :: Status1000X2 :: ability_detect_state [02:02] */ 11798 #define PHY84328_DEV7_STATUS1000X2_ABILITY_DETECT_STATE_MASK 0x0004 11799 #define PHY84328_DEV7_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN 0 11800 #define PHY84328_DEV7_STATUS1000X2_ABILITY_DETECT_STATE_BITS 1 11801 #define PHY84328_DEV7_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT 2 11802 11803 /* ln_device7 :: Status1000X2 :: reserved0 [01:01] */ 11804 #define PHY84328_DEV7_STATUS1000X2_RESERVED0_MASK 0x0002 11805 #define PHY84328_DEV7_STATUS1000X2_RESERVED0_ALIGN 0 11806 #define PHY84328_DEV7_STATUS1000X2_RESERVED0_BITS 1 11807 #define PHY84328_DEV7_STATUS1000X2_RESERVED0_SHIFT 1 11808 11809 /* ln_device7 :: Status1000X2 :: an_enable_state [00:00] */ 11810 #define PHY84328_DEV7_STATUS1000X2_AN_ENABLE_STATE_MASK 0x0001 11811 #define PHY84328_DEV7_STATUS1000X2_AN_ENABLE_STATE_ALIGN 0 11812 #define PHY84328_DEV7_STATUS1000X2_AN_ENABLE_STATE_BITS 1 11813 #define PHY84328_DEV7_STATUS1000X2_AN_ENABLE_STATE_SHIFT 0 11814 11815 11816 /**************************************************************************** 11817 * ln_device7 :: Status1000X3 11818 */ 11819 /* ln_device7 :: Status1000X3 :: reserved0 [15:14] */ 11820 #define PHY84328_DEV7_STATUS1000X3_RESERVED0_MASK 0xc000 11821 #define PHY84328_DEV7_STATUS1000X3_RESERVED0_ALIGN 0 11822 #define PHY84328_DEV7_STATUS1000X3_RESERVED0_BITS 2 11823 #define PHY84328_DEV7_STATUS1000X3_RESERVED0_SHIFT 14 11824 11825 /* ln_device7 :: Status1000X3 :: tx_os_fifo_error [13:13] */ 11826 #define PHY84328_DEV7_STATUS1000X3_TX_OS_FIFO_ERROR_MASK 0x2000 11827 #define PHY84328_DEV7_STATUS1000X3_TX_OS_FIFO_ERROR_ALIGN 0 11828 #define PHY84328_DEV7_STATUS1000X3_TX_OS_FIFO_ERROR_BITS 1 11829 #define PHY84328_DEV7_STATUS1000X3_TX_OS_FIFO_ERROR_SHIFT 13 11830 11831 /* ln_device7 :: Status1000X3 :: pd_park_an [12:12] */ 11832 #define PHY84328_DEV7_STATUS1000X3_PD_PARK_AN_MASK 0x1000 11833 #define PHY84328_DEV7_STATUS1000X3_PD_PARK_AN_ALIGN 0 11834 #define PHY84328_DEV7_STATUS1000X3_PD_PARK_AN_BITS 1 11835 #define PHY84328_DEV7_STATUS1000X3_PD_PARK_AN_SHIFT 12 11836 11837 /* ln_device7 :: Status1000X3 :: remotePhy_autosel [11:11] */ 11838 #define PHY84328_DEV7_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK 0x0800 11839 #define PHY84328_DEV7_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN 0 11840 #define PHY84328_DEV7_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS 1 11841 #define PHY84328_DEV7_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT 11 11842 11843 /* ln_device7 :: Status1000X3 :: latch_linkdown [10:10] */ 11844 #define PHY84328_DEV7_STATUS1000X3_LATCH_LINKDOWN_MASK 0x0400 11845 #define PHY84328_DEV7_STATUS1000X3_LATCH_LINKDOWN_ALIGN 0 11846 #define PHY84328_DEV7_STATUS1000X3_LATCH_LINKDOWN_BITS 1 11847 #define PHY84328_DEV7_STATUS1000X3_LATCH_LINKDOWN_SHIFT 10 11848 11849 /* ln_device7 :: Status1000X3 :: sd_filter [09:09] */ 11850 #define PHY84328_DEV7_STATUS1000X3_SD_FILTER_MASK 0x0200 11851 #define PHY84328_DEV7_STATUS1000X3_SD_FILTER_ALIGN 0 11852 #define PHY84328_DEV7_STATUS1000X3_SD_FILTER_BITS 1 11853 #define PHY84328_DEV7_STATUS1000X3_SD_FILTER_SHIFT 9 11854 11855 /* ln_device7 :: Status1000X3 :: sd_mux [08:08] */ 11856 #define PHY84328_DEV7_STATUS1000X3_SD_MUX_MASK 0x0100 11857 #define PHY84328_DEV7_STATUS1000X3_SD_MUX_ALIGN 0 11858 #define PHY84328_DEV7_STATUS1000X3_SD_MUX_BITS 1 11859 #define PHY84328_DEV7_STATUS1000X3_SD_MUX_SHIFT 8 11860 11861 /* ln_device7 :: Status1000X3 :: sd_filter_chg [07:07] */ 11862 #define PHY84328_DEV7_STATUS1000X3_SD_FILTER_CHG_MASK 0x0080 11863 #define PHY84328_DEV7_STATUS1000X3_SD_FILTER_CHG_ALIGN 0 11864 #define PHY84328_DEV7_STATUS1000X3_SD_FILTER_CHG_BITS 1 11865 #define PHY84328_DEV7_STATUS1000X3_SD_FILTER_CHG_SHIFT 7 11866 11867 /* ln_device7 :: Status1000X3 :: reserved1 [06:00] */ 11868 #define PHY84328_DEV7_STATUS1000X3_RESERVED1_MASK 0x007f 11869 #define PHY84328_DEV7_STATUS1000X3_RESERVED1_ALIGN 0 11870 #define PHY84328_DEV7_STATUS1000X3_RESERVED1_BITS 7 11871 #define PHY84328_DEV7_STATUS1000X3_RESERVED1_SHIFT 0 11872 11873 11874 /**************************************************************************** 11875 * ln_device7 :: BadCodeGroup 11876 */ 11877 /* ln_device7 :: BadCodeGroup :: badCodeGroups [15:08] */ 11878 #define PHY84328_DEV7_BADCODEGROUP_BADCODEGROUPS_MASK 0xff00 11879 #define PHY84328_DEV7_BADCODEGROUP_BADCODEGROUPS_ALIGN 0 11880 #define PHY84328_DEV7_BADCODEGROUP_BADCODEGROUPS_BITS 8 11881 #define PHY84328_DEV7_BADCODEGROUP_BADCODEGROUPS_SHIFT 8 11882 11883 /* ln_device7 :: BadCodeGroup :: reserved0 [07:00] */ 11884 #define PHY84328_DEV7_BADCODEGROUP_RESERVED0_MASK 0x00ff 11885 #define PHY84328_DEV7_BADCODEGROUP_RESERVED0_ALIGN 0 11886 #define PHY84328_DEV7_BADCODEGROUP_RESERVED0_BITS 8 11887 #define PHY84328_DEV7_BADCODEGROUP_RESERVED0_SHIFT 0 11888 11889 11890 /**************************************************************************** 11891 * ln_device7 :: Misc1 11892 */ 11893 /* ln_device7 :: Misc1 :: refclk_sel [15:13] */ 11894 #define PHY84328_DEV7_MISC1_REFCLK_SEL_MASK 0xe000 11895 #define PHY84328_DEV7_MISC1_REFCLK_SEL_ALIGN 0 11896 #define PHY84328_DEV7_MISC1_REFCLK_SEL_BITS 3 11897 #define PHY84328_DEV7_MISC1_REFCLK_SEL_SHIFT 13 11898 11899 /* ln_device7 :: Misc1 :: force_pll_mode_afe_sel [12:12] */ 11900 #define PHY84328_DEV7_MISC1_FORCE_PLL_MODE_AFE_SEL_MASK 0x1000 11901 #define PHY84328_DEV7_MISC1_FORCE_PLL_MODE_AFE_SEL_ALIGN 0 11902 #define PHY84328_DEV7_MISC1_FORCE_PLL_MODE_AFE_SEL_BITS 1 11903 #define PHY84328_DEV7_MISC1_FORCE_PLL_MODE_AFE_SEL_SHIFT 12 11904 11905 /* ln_device7 :: Misc1 :: force_pll_mode_afe [11:08] */ 11906 #define PHY84328_DEV7_MISC1_FORCE_PLL_MODE_AFE_MASK 0x0f00 11907 #define PHY84328_DEV7_MISC1_FORCE_PLL_MODE_AFE_ALIGN 0 11908 #define PHY84328_DEV7_MISC1_FORCE_PLL_MODE_AFE_BITS 4 11909 #define PHY84328_DEV7_MISC1_FORCE_PLL_MODE_AFE_SHIFT 8 11910 11911 /* ln_device7 :: Misc1 :: force_tick0_sw2 [07:07] */ 11912 #define PHY84328_DEV7_MISC1_FORCE_TICK0_SW2_MASK 0x0080 11913 #define PHY84328_DEV7_MISC1_FORCE_TICK0_SW2_ALIGN 0 11914 #define PHY84328_DEV7_MISC1_FORCE_TICK0_SW2_BITS 1 11915 #define PHY84328_DEV7_MISC1_FORCE_TICK0_SW2_SHIFT 7 11916 11917 /* ln_device7 :: Misc1 :: tx_underrun_1000_dis [06:06] */ 11918 #define PHY84328_DEV7_MISC1_TX_UNDERRUN_1000_DIS_MASK 0x0040 11919 #define PHY84328_DEV7_MISC1_TX_UNDERRUN_1000_DIS_ALIGN 0 11920 #define PHY84328_DEV7_MISC1_TX_UNDERRUN_1000_DIS_BITS 1 11921 #define PHY84328_DEV7_MISC1_TX_UNDERRUN_1000_DIS_SHIFT 6 11922 11923 /* ln_device7 :: Misc1 :: force_ln_mode [05:05] */ 11924 #define PHY84328_DEV7_MISC1_FORCE_LN_MODE_MASK 0x0020 11925 #define PHY84328_DEV7_MISC1_FORCE_LN_MODE_ALIGN 0 11926 #define PHY84328_DEV7_MISC1_FORCE_LN_MODE_BITS 1 11927 #define PHY84328_DEV7_MISC1_FORCE_LN_MODE_SHIFT 5 11928 11929 /* ln_device7 :: Misc1 :: force_speed [04:00] */ 11930 #define PHY84328_DEV7_MISC1_FORCE_SPEED_MASK 0x001f 11931 #define PHY84328_DEV7_MISC1_FORCE_SPEED_ALIGN 0 11932 #define PHY84328_DEV7_MISC1_FORCE_SPEED_BITS 5 11933 #define PHY84328_DEV7_MISC1_FORCE_SPEED_SHIFT 0 11934 11935 11936 /**************************************************************************** 11937 * ln_device7 :: Misc2 11938 */ 11939 /* ln_device7 :: Misc2 :: rxckpl_sel_combo [15:15] */ 11940 #define PHY84328_DEV7_MISC2_RXCKPL_SEL_COMBO_MASK 0x8000 11941 #define PHY84328_DEV7_MISC2_RXCKPL_SEL_COMBO_ALIGN 0 11942 #define PHY84328_DEV7_MISC2_RXCKPL_SEL_COMBO_BITS 1 11943 #define PHY84328_DEV7_MISC2_RXCKPL_SEL_COMBO_SHIFT 15 11944 11945 /* ln_device7 :: Misc2 :: rxck_mii_gen_sel_force [14:14] */ 11946 #define PHY84328_DEV7_MISC2_RXCK_MII_GEN_SEL_FORCE_MASK 0x4000 11947 #define PHY84328_DEV7_MISC2_RXCK_MII_GEN_SEL_FORCE_ALIGN 0 11948 #define PHY84328_DEV7_MISC2_RXCK_MII_GEN_SEL_FORCE_BITS 1 11949 #define PHY84328_DEV7_MISC2_RXCK_MII_GEN_SEL_FORCE_SHIFT 14 11950 11951 /* ln_device7 :: Misc2 :: rxck_mii_gen_sel_val [13:13] */ 11952 #define PHY84328_DEV7_MISC2_RXCK_MII_GEN_SEL_VAL_MASK 0x2000 11953 #define PHY84328_DEV7_MISC2_RXCK_MII_GEN_SEL_VAL_ALIGN 0 11954 #define PHY84328_DEV7_MISC2_RXCK_MII_GEN_SEL_VAL_BITS 1 11955 #define PHY84328_DEV7_MISC2_RXCK_MII_GEN_SEL_VAL_SHIFT 13 11956 11957 /* ln_device7 :: Misc2 :: rlpbk_sw_force [12:12] */ 11958 #define PHY84328_DEV7_MISC2_RLPBK_SW_FORCE_MASK 0x1000 11959 #define PHY84328_DEV7_MISC2_RLPBK_SW_FORCE_ALIGN 0 11960 #define PHY84328_DEV7_MISC2_RLPBK_SW_FORCE_BITS 1 11961 #define PHY84328_DEV7_MISC2_RLPBK_SW_FORCE_SHIFT 12 11962 11963 /* ln_device7 :: Misc2 :: rlpbk_RxRst_en [11:11] */ 11964 #define PHY84328_DEV7_MISC2_RLPBK_RXRST_EN_MASK 0x0800 11965 #define PHY84328_DEV7_MISC2_RLPBK_RXRST_EN_ALIGN 0 11966 #define PHY84328_DEV7_MISC2_RLPBK_RXRST_EN_BITS 1 11967 #define PHY84328_DEV7_MISC2_RLPBK_RXRST_EN_SHIFT 11 11968 11969 /* ln_device7 :: Misc2 :: clkSigdet_bypass [10:10] */ 11970 #define PHY84328_DEV7_MISC2_CLKSIGDET_BYPASS_MASK 0x0400 11971 #define PHY84328_DEV7_MISC2_CLKSIGDET_BYPASS_ALIGN 0 11972 #define PHY84328_DEV7_MISC2_CLKSIGDET_BYPASS_BITS 1 11973 #define PHY84328_DEV7_MISC2_CLKSIGDET_BYPASS_SHIFT 10 11974 11975 /* ln_device7 :: Misc2 :: clk41_bypass [09:09] */ 11976 #define PHY84328_DEV7_MISC2_CLK41_BYPASS_MASK 0x0200 11977 #define PHY84328_DEV7_MISC2_CLK41_BYPASS_ALIGN 0 11978 #define PHY84328_DEV7_MISC2_CLK41_BYPASS_BITS 1 11979 #define PHY84328_DEV7_MISC2_CLK41_BYPASS_SHIFT 9 11980 11981 /* ln_device7 :: Misc2 :: miiGmiiDly_en [08:08] */ 11982 #define PHY84328_DEV7_MISC2_MIIGMIIDLY_EN_MASK 0x0100 11983 #define PHY84328_DEV7_MISC2_MIIGMIIDLY_EN_ALIGN 0 11984 #define PHY84328_DEV7_MISC2_MIIGMIIDLY_EN_BITS 1 11985 #define PHY84328_DEV7_MISC2_MIIGMIIDLY_EN_SHIFT 8 11986 11987 /* ln_device7 :: Misc2 :: miiGmiiMux_en [07:07] */ 11988 #define PHY84328_DEV7_MISC2_MIIGMIIMUX_EN_MASK 0x0080 11989 #define PHY84328_DEV7_MISC2_MIIGMIIMUX_EN_ALIGN 0 11990 #define PHY84328_DEV7_MISC2_MIIGMIIMUX_EN_BITS 1 11991 #define PHY84328_DEV7_MISC2_MIIGMIIMUX_EN_SHIFT 7 11992 11993 /* ln_device7 :: Misc2 :: KX_cl73_an_en [06:06] */ 11994 #define PHY84328_DEV7_MISC2_KX_CL73_AN_EN_MASK 0x0040 11995 #define PHY84328_DEV7_MISC2_KX_CL73_AN_EN_ALIGN 0 11996 #define PHY84328_DEV7_MISC2_KX_CL73_AN_EN_BITS 1 11997 #define PHY84328_DEV7_MISC2_KX_CL73_AN_EN_SHIFT 6 11998 11999 /* ln_device7 :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */ 12000 #define PHY84328_DEV7_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK 0x0020 12001 #define PHY84328_DEV7_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN 0 12002 #define PHY84328_DEV7_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS 1 12003 #define PHY84328_DEV7_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT 5 12004 12005 /* ln_device7 :: Misc2 :: fifo_err_cya [04:04] */ 12006 #define PHY84328_DEV7_MISC2_FIFO_ERR_CYA_MASK 0x0010 12007 #define PHY84328_DEV7_MISC2_FIFO_ERR_CYA_ALIGN 0 12008 #define PHY84328_DEV7_MISC2_FIFO_ERR_CYA_BITS 1 12009 #define PHY84328_DEV7_MISC2_FIFO_ERR_CYA_SHIFT 4 12010 12011 /* ln_device7 :: Misc2 :: an_txdisablePhase [03:03] */ 12012 #define PHY84328_DEV7_MISC2_AN_TXDISABLEPHASE_MASK 0x0008 12013 #define PHY84328_DEV7_MISC2_AN_TXDISABLEPHASE_ALIGN 0 12014 #define PHY84328_DEV7_MISC2_AN_TXDISABLEPHASE_BITS 1 12015 #define PHY84328_DEV7_MISC2_AN_TXDISABLEPHASE_SHIFT 3 12016 12017 /* ln_device7 :: Misc2 :: an_rxSeqStartDis [02:02] */ 12018 #define PHY84328_DEV7_MISC2_AN_RXSEQSTARTDIS_MASK 0x0004 12019 #define PHY84328_DEV7_MISC2_AN_RXSEQSTARTDIS_ALIGN 0 12020 #define PHY84328_DEV7_MISC2_AN_RXSEQSTARTDIS_BITS 1 12021 #define PHY84328_DEV7_MISC2_AN_RXSEQSTARTDIS_SHIFT 2 12022 12023 /* ln_device7 :: Misc2 :: an_txdisable_ln [01:01] */ 12024 #define PHY84328_DEV7_MISC2_AN_TXDISABLE_LN_MASK 0x0002 12025 #define PHY84328_DEV7_MISC2_AN_TXDISABLE_LN_ALIGN 0 12026 #define PHY84328_DEV7_MISC2_AN_TXDISABLE_LN_BITS 1 12027 #define PHY84328_DEV7_MISC2_AN_TXDISABLE_LN_SHIFT 1 12028 12029 /* ln_device7 :: Misc2 :: an_deadTrap [00:00] */ 12030 #define PHY84328_DEV7_MISC2_AN_DEADTRAP_MASK 0x0001 12031 #define PHY84328_DEV7_MISC2_AN_DEADTRAP_ALIGN 0 12032 #define PHY84328_DEV7_MISC2_AN_DEADTRAP_BITS 1 12033 #define PHY84328_DEV7_MISC2_AN_DEADTRAP_SHIFT 0 12034 12035 12036 /**************************************************************************** 12037 * ln_device7 :: PatGenCtrl 12038 */ 12039 /* ln_device7 :: PatGenCtrl :: patgen_lpi_en [15:15] */ 12040 #define PHY84328_DEV7_PATGENCTRL_PATGEN_LPI_EN_MASK 0x8000 12041 #define PHY84328_DEV7_PATGENCTRL_PATGEN_LPI_EN_ALIGN 0 12042 #define PHY84328_DEV7_PATGENCTRL_PATGEN_LPI_EN_BITS 1 12043 #define PHY84328_DEV7_PATGENCTRL_PATGEN_LPI_EN_SHIFT 15 12044 12045 /* ln_device7 :: PatGenCtrl :: tx_err [14:14] */ 12046 #define PHY84328_DEV7_PATGENCTRL_TX_ERR_MASK 0x4000 12047 #define PHY84328_DEV7_PATGENCTRL_TX_ERR_ALIGN 0 12048 #define PHY84328_DEV7_PATGENCTRL_TX_ERR_BITS 1 12049 #define PHY84328_DEV7_PATGENCTRL_TX_ERR_SHIFT 14 12050 12051 /* ln_device7 :: PatGenCtrl :: skip_crc [13:13] */ 12052 #define PHY84328_DEV7_PATGENCTRL_SKIP_CRC_MASK 0x2000 12053 #define PHY84328_DEV7_PATGENCTRL_SKIP_CRC_ALIGN 0 12054 #define PHY84328_DEV7_PATGENCTRL_SKIP_CRC_BITS 1 12055 #define PHY84328_DEV7_PATGENCTRL_SKIP_CRC_SHIFT 13 12056 12057 /* ln_device7 :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */ 12058 #define PHY84328_DEV7_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000 12059 #define PHY84328_DEV7_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0 12060 #define PHY84328_DEV7_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1 12061 #define PHY84328_DEV7_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12 12062 12063 /* ln_device7 :: PatGenCtrl :: ipg_select [11:09] */ 12064 #define PHY84328_DEV7_PATGENCTRL_IPG_SELECT_MASK 0x0e00 12065 #define PHY84328_DEV7_PATGENCTRL_IPG_SELECT_ALIGN 0 12066 #define PHY84328_DEV7_PATGENCTRL_IPG_SELECT_BITS 3 12067 #define PHY84328_DEV7_PATGENCTRL_IPG_SELECT_SHIFT 9 12068 12069 /* ln_device7 :: PatGenCtrl :: pkt_size [08:03] */ 12070 #define PHY84328_DEV7_PATGENCTRL_PKT_SIZE_MASK 0x01f8 12071 #define PHY84328_DEV7_PATGENCTRL_PKT_SIZE_ALIGN 0 12072 #define PHY84328_DEV7_PATGENCTRL_PKT_SIZE_BITS 6 12073 #define PHY84328_DEV7_PATGENCTRL_PKT_SIZE_SHIFT 3 12074 12075 /* ln_device7 :: PatGenCtrl :: single_pass_mode [02:02] */ 12076 #define PHY84328_DEV7_PATGENCTRL_SINGLE_PASS_MODE_MASK 0x0004 12077 #define PHY84328_DEV7_PATGENCTRL_SINGLE_PASS_MODE_ALIGN 0 12078 #define PHY84328_DEV7_PATGENCTRL_SINGLE_PASS_MODE_BITS 1 12079 #define PHY84328_DEV7_PATGENCTRL_SINGLE_PASS_MODE_SHIFT 2 12080 12081 /* ln_device7 :: PatGenCtrl :: run_pattern_gen [01:01] */ 12082 #define PHY84328_DEV7_PATGENCTRL_RUN_PATTERN_GEN_MASK 0x0002 12083 #define PHY84328_DEV7_PATGENCTRL_RUN_PATTERN_GEN_ALIGN 0 12084 #define PHY84328_DEV7_PATGENCTRL_RUN_PATTERN_GEN_BITS 1 12085 #define PHY84328_DEV7_PATGENCTRL_RUN_PATTERN_GEN_SHIFT 1 12086 12087 /* ln_device7 :: PatGenCtrl :: sel_pattern_gen_data [00:00] */ 12088 #define PHY84328_DEV7_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK 0x0001 12089 #define PHY84328_DEV7_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN 0 12090 #define PHY84328_DEV7_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS 1 12091 #define PHY84328_DEV7_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT 0 12092 12093 12094 /**************************************************************************** 12095 * ln_device7 :: PatGenStat 12096 */ 12097 /* ln_device7 :: PatGenStat :: reserved0 [15:04] */ 12098 #define PHY84328_DEV7_PATGENSTAT_RESERVED0_MASK 0xfff0 12099 #define PHY84328_DEV7_PATGENSTAT_RESERVED0_ALIGN 0 12100 #define PHY84328_DEV7_PATGENSTAT_RESERVED0_BITS 12 12101 #define PHY84328_DEV7_PATGENSTAT_RESERVED0_SHIFT 4 12102 12103 /* ln_device7 :: PatGenStat :: pattern_gen_active [03:03] */ 12104 #define PHY84328_DEV7_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK 0x0008 12105 #define PHY84328_DEV7_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN 0 12106 #define PHY84328_DEV7_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS 1 12107 #define PHY84328_DEV7_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT 3 12108 12109 /* ln_device7 :: PatGenStat :: pattern_gen_fsm [02:00] */ 12110 #define PHY84328_DEV7_PATGENSTAT_PATTERN_GEN_FSM_MASK 0x0007 12111 #define PHY84328_DEV7_PATGENSTAT_PATTERN_GEN_FSM_ALIGN 0 12112 #define PHY84328_DEV7_PATGENSTAT_PATTERN_GEN_FSM_BITS 3 12113 #define PHY84328_DEV7_PATGENSTAT_PATTERN_GEN_FSM_SHIFT 0 12114 12115 12116 /**************************************************************************** 12117 * ln_device7 :: TestMode 12118 */ 12119 /* ln_device7 :: TestMode :: disable_reset_cnt [15:15] */ 12120 #define PHY84328_DEV7_TESTMODE_DISABLE_RESET_CNT_MASK 0x8000 12121 #define PHY84328_DEV7_TESTMODE_DISABLE_RESET_CNT_ALIGN 0 12122 #define PHY84328_DEV7_TESTMODE_DISABLE_RESET_CNT_BITS 1 12123 #define PHY84328_DEV7_TESTMODE_DISABLE_RESET_CNT_SHIFT 15 12124 12125 /* ln_device7 :: TestMode :: clear_packet_counters [14:14] */ 12126 #define PHY84328_DEV7_TESTMODE_CLEAR_PACKET_COUNTERS_MASK 0x4000 12127 #define PHY84328_DEV7_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN 0 12128 #define PHY84328_DEV7_TESTMODE_CLEAR_PACKET_COUNTERS_BITS 1 12129 #define PHY84328_DEV7_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT 14 12130 12131 /* ln_device7 :: TestMode :: reserved0 [13:05] */ 12132 #define PHY84328_DEV7_TESTMODE_RESERVED0_MASK 0x3fe0 12133 #define PHY84328_DEV7_TESTMODE_RESERVED0_ALIGN 0 12134 #define PHY84328_DEV7_TESTMODE_RESERVED0_BITS 9 12135 #define PHY84328_DEV7_TESTMODE_RESERVED0_SHIFT 5 12136 12137 /* ln_device7 :: TestMode :: fifo_fsm_cya_rx [04:04] */ 12138 #define PHY84328_DEV7_TESTMODE_FIFO_FSM_CYA_RX_MASK 0x0010 12139 #define PHY84328_DEV7_TESTMODE_FIFO_FSM_CYA_RX_ALIGN 0 12140 #define PHY84328_DEV7_TESTMODE_FIFO_FSM_CYA_RX_BITS 1 12141 #define PHY84328_DEV7_TESTMODE_FIFO_FSM_CYA_RX_SHIFT 4 12142 12143 /* ln_device7 :: TestMode :: dig1000x_afrst_cya [03:03] */ 12144 #define PHY84328_DEV7_TESTMODE_DIG1000X_AFRST_CYA_MASK 0x0008 12145 #define PHY84328_DEV7_TESTMODE_DIG1000X_AFRST_CYA_ALIGN 0 12146 #define PHY84328_DEV7_TESTMODE_DIG1000X_AFRST_CYA_BITS 1 12147 #define PHY84328_DEV7_TESTMODE_DIG1000X_AFRST_CYA_SHIFT 3 12148 12149 /* ln_device7 :: TestMode :: fifo_elasicity_rx [02:01] */ 12150 #define PHY84328_DEV7_TESTMODE_FIFO_ELASICITY_RX_MASK 0x0006 12151 #define PHY84328_DEV7_TESTMODE_FIFO_ELASICITY_RX_ALIGN 0 12152 #define PHY84328_DEV7_TESTMODE_FIFO_ELASICITY_RX_BITS 2 12153 #define PHY84328_DEV7_TESTMODE_FIFO_ELASICITY_RX_SHIFT 1 12154 12155 /* ln_device7 :: TestMode :: fifo_ipg_rx_cya [00:00] */ 12156 #define PHY84328_DEV7_TESTMODE_FIFO_IPG_RX_CYA_MASK 0x0001 12157 #define PHY84328_DEV7_TESTMODE_FIFO_IPG_RX_CYA_ALIGN 0 12158 #define PHY84328_DEV7_TESTMODE_FIFO_IPG_RX_CYA_BITS 1 12159 #define PHY84328_DEV7_TESTMODE_FIFO_IPG_RX_CYA_SHIFT 0 12160 12161 12162 /**************************************************************************** 12163 * ln_device7 :: TxPktCnt 12164 */ 12165 /* ln_device7 :: TxPktCnt :: TxPktCnt [15:00] */ 12166 #define PHY84328_DEV7_TXPKTCNT_TXPKTCNT_MASK 0xffff 12167 #define PHY84328_DEV7_TXPKTCNT_TXPKTCNT_ALIGN 0 12168 #define PHY84328_DEV7_TXPKTCNT_TXPKTCNT_BITS 16 12169 #define PHY84328_DEV7_TXPKTCNT_TXPKTCNT_SHIFT 0 12170 12171 12172 /**************************************************************************** 12173 * ln_device7 :: RxPktCnt 12174 */ 12175 /* ln_device7 :: RxPktCnt :: RxPktCnt [15:00] */ 12176 #define PHY84328_DEV7_RXPKTCNT_RXPKTCNT_MASK 0xffff 12177 #define PHY84328_DEV7_RXPKTCNT_RXPKTCNT_ALIGN 0 12178 #define PHY84328_DEV7_RXPKTCNT_RXPKTCNT_BITS 16 12179 #define PHY84328_DEV7_RXPKTCNT_RXPKTCNT_SHIFT 0 12180 12181 12182 /**************************************************************************** 12183 * ln_device7 :: digctl_3_0 12184 */ 12185 /* ln_device7 :: digctl_3_0 :: an_lostLink_cnt [15:00] */ 12186 #define PHY84328_DEV7_DIGCTL_3_0_AN_LOSTLINK_CNT_MASK 0xffff 12187 #define PHY84328_DEV7_DIGCTL_3_0_AN_LOSTLINK_CNT_ALIGN 0 12188 #define PHY84328_DEV7_DIGCTL_3_0_AN_LOSTLINK_CNT_BITS 16 12189 #define PHY84328_DEV7_DIGCTL_3_0_AN_LOSTLINK_CNT_SHIFT 0 12190 12191 12192 /**************************************************************************** 12193 * ln_device7 :: digctl_3_1 12194 */ 12195 /* ln_device7 :: digctl_3_1 :: an_switch_cnt [15:00] */ 12196 #define PHY84328_DEV7_DIGCTL_3_1_AN_SWITCH_CNT_MASK 0xffff 12197 #define PHY84328_DEV7_DIGCTL_3_1_AN_SWITCH_CNT_ALIGN 0 12198 #define PHY84328_DEV7_DIGCTL_3_1_AN_SWITCH_CNT_BITS 16 12199 #define PHY84328_DEV7_DIGCTL_3_1_AN_SWITCH_CNT_SHIFT 0 12200 12201 12202 /**************************************************************************** 12203 * ln_device7 :: digctl_3_2 12204 */ 12205 /* ln_device7 :: digctl_3_2 :: an_link_cnt [15:00] */ 12206 #define PHY84328_DEV7_DIGCTL_3_2_AN_LINK_CNT_MASK 0xffff 12207 #define PHY84328_DEV7_DIGCTL_3_2_AN_LINK_CNT_ALIGN 0 12208 #define PHY84328_DEV7_DIGCTL_3_2_AN_LINK_CNT_BITS 16 12209 #define PHY84328_DEV7_DIGCTL_3_2_AN_LINK_CNT_SHIFT 0 12210 12211 12212 /**************************************************************************** 12213 * ln_device7 :: digctl_3_3 12214 */ 12215 /* ln_device7 :: digctl_3_3 :: an_switch_cnt2 [15:08] */ 12216 #define PHY84328_DEV7_DIGCTL_3_3_AN_SWITCH_CNT2_MASK 0xff00 12217 #define PHY84328_DEV7_DIGCTL_3_3_AN_SWITCH_CNT2_ALIGN 0 12218 #define PHY84328_DEV7_DIGCTL_3_3_AN_SWITCH_CNT2_BITS 8 12219 #define PHY84328_DEV7_DIGCTL_3_3_AN_SWITCH_CNT2_SHIFT 8 12220 12221 /* ln_device7 :: digctl_3_3 :: an_link_cnt2 [07:00] */ 12222 #define PHY84328_DEV7_DIGCTL_3_3_AN_LINK_CNT2_MASK 0x00ff 12223 #define PHY84328_DEV7_DIGCTL_3_3_AN_LINK_CNT2_ALIGN 0 12224 #define PHY84328_DEV7_DIGCTL_3_3_AN_LINK_CNT2_BITS 8 12225 #define PHY84328_DEV7_DIGCTL_3_3_AN_LINK_CNT2_SHIFT 0 12226 12227 12228 /**************************************************************************** 12229 * ln_device7 :: digctl_3_4 12230 */ 12231 /* ln_device7 :: digctl_3_4 :: mp_number [15:05] */ 12232 #define PHY84328_DEV7_DIGCTL_3_4_MP_NUMBER_MASK 0xffe0 12233 #define PHY84328_DEV7_DIGCTL_3_4_MP_NUMBER_ALIGN 0 12234 #define PHY84328_DEV7_DIGCTL_3_4_MP_NUMBER_BITS 11 12235 #define PHY84328_DEV7_DIGCTL_3_4_MP_NUMBER_SHIFT 5 12236 12237 /* ln_device7 :: digctl_3_4 :: no_fail_cnt [04:04] */ 12238 #define PHY84328_DEV7_DIGCTL_3_4_NO_FAIL_CNT_MASK 0x0010 12239 #define PHY84328_DEV7_DIGCTL_3_4_NO_FAIL_CNT_ALIGN 0 12240 #define PHY84328_DEV7_DIGCTL_3_4_NO_FAIL_CNT_BITS 1 12241 #define PHY84328_DEV7_DIGCTL_3_4_NO_FAIL_CNT_SHIFT 4 12242 12243 /* ln_device7 :: digctl_3_4 :: an_fail_cnt [03:00] */ 12244 #define PHY84328_DEV7_DIGCTL_3_4_AN_FAIL_CNT_MASK 0x000f 12245 #define PHY84328_DEV7_DIGCTL_3_4_AN_FAIL_CNT_ALIGN 0 12246 #define PHY84328_DEV7_DIGCTL_3_4_AN_FAIL_CNT_BITS 4 12247 #define PHY84328_DEV7_DIGCTL_3_4_AN_FAIL_CNT_SHIFT 0 12248 12249 12250 /**************************************************************************** 12251 * ln_device7 :: digctl_3_5 12252 */ 12253 /* ln_device7 :: digctl_3_5 :: an_ignoreLink_cnt [15:00] */ 12254 #define PHY84328_DEV7_DIGCTL_3_5_AN_IGNORELINK_CNT_MASK 0xffff 12255 #define PHY84328_DEV7_DIGCTL_3_5_AN_IGNORELINK_CNT_ALIGN 0 12256 #define PHY84328_DEV7_DIGCTL_3_5_AN_IGNORELINK_CNT_BITS 16 12257 #define PHY84328_DEV7_DIGCTL_3_5_AN_IGNORELINK_CNT_SHIFT 0 12258 12259 12260 /**************************************************************************** 12261 * ln_device7 :: digctl_3_6 12262 */ 12263 /* ln_device7 :: digctl_3_6 :: an_lostLink_cnt2 [15:08] */ 12264 #define PHY84328_DEV7_DIGCTL_3_6_AN_LOSTLINK_CNT2_MASK 0xff00 12265 #define PHY84328_DEV7_DIGCTL_3_6_AN_LOSTLINK_CNT2_ALIGN 0 12266 #define PHY84328_DEV7_DIGCTL_3_6_AN_LOSTLINK_CNT2_BITS 8 12267 #define PHY84328_DEV7_DIGCTL_3_6_AN_LOSTLINK_CNT2_SHIFT 8 12268 12269 /* ln_device7 :: digctl_3_6 :: an_ingoreLink_cnt2 [07:00] */ 12270 #define PHY84328_DEV7_DIGCTL_3_6_AN_INGORELINK_CNT2_MASK 0x00ff 12271 #define PHY84328_DEV7_DIGCTL_3_6_AN_INGORELINK_CNT2_ALIGN 0 12272 #define PHY84328_DEV7_DIGCTL_3_6_AN_INGORELINK_CNT2_BITS 8 12273 #define PHY84328_DEV7_DIGCTL_3_6_AN_INGORELINK_CNT2_SHIFT 0 12274 12275 12276 /**************************************************************************** 12277 * ln_device7 :: UP1 12278 */ 12279 /* ln_device7 :: UP1 :: reserved0 [15:11] */ 12280 #define PHY84328_DEV7_UP1_RESERVED0_MASK 0xf800 12281 #define PHY84328_DEV7_UP1_RESERVED0_ALIGN 0 12282 #define PHY84328_DEV7_UP1_RESERVED0_BITS 5 12283 #define PHY84328_DEV7_UP1_RESERVED0_SHIFT 11 12284 12285 /* ln_device7 :: UP1 :: dataRate_20GX4 [10:10] */ 12286 #define PHY84328_DEV7_UP1_DATARATE_20GX4_MASK 0x0400 12287 #define PHY84328_DEV7_UP1_DATARATE_20GX4_ALIGN 0 12288 #define PHY84328_DEV7_UP1_DATARATE_20GX4_BITS 1 12289 #define PHY84328_DEV7_UP1_DATARATE_20GX4_SHIFT 10 12290 12291 /* ln_device7 :: UP1 :: dataRate_16GX4 [09:09] */ 12292 #define PHY84328_DEV7_UP1_DATARATE_16GX4_MASK 0x0200 12293 #define PHY84328_DEV7_UP1_DATARATE_16GX4_ALIGN 0 12294 #define PHY84328_DEV7_UP1_DATARATE_16GX4_BITS 1 12295 #define PHY84328_DEV7_UP1_DATARATE_16GX4_SHIFT 9 12296 12297 /* ln_device7 :: UP1 :: dataRate_15GX4 [08:08] */ 12298 #define PHY84328_DEV7_UP1_DATARATE_15GX4_MASK 0x0100 12299 #define PHY84328_DEV7_UP1_DATARATE_15GX4_ALIGN 0 12300 #define PHY84328_DEV7_UP1_DATARATE_15GX4_BITS 1 12301 #define PHY84328_DEV7_UP1_DATARATE_15GX4_SHIFT 8 12302 12303 /* ln_device7 :: UP1 :: dataRate_13GX4 [07:07] */ 12304 #define PHY84328_DEV7_UP1_DATARATE_13GX4_MASK 0x0080 12305 #define PHY84328_DEV7_UP1_DATARATE_13GX4_ALIGN 0 12306 #define PHY84328_DEV7_UP1_DATARATE_13GX4_BITS 1 12307 #define PHY84328_DEV7_UP1_DATARATE_13GX4_SHIFT 7 12308 12309 /* ln_device7 :: UP1 :: dataRate_12p5GX4 [06:06] */ 12310 #define PHY84328_DEV7_UP1_DATARATE_12P5GX4_MASK 0x0040 12311 #define PHY84328_DEV7_UP1_DATARATE_12P5GX4_ALIGN 0 12312 #define PHY84328_DEV7_UP1_DATARATE_12P5GX4_BITS 1 12313 #define PHY84328_DEV7_UP1_DATARATE_12P5GX4_SHIFT 6 12314 12315 /* ln_device7 :: UP1 :: dataRate_12GX4 [05:05] */ 12316 #define PHY84328_DEV7_UP1_DATARATE_12GX4_MASK 0x0020 12317 #define PHY84328_DEV7_UP1_DATARATE_12GX4_ALIGN 0 12318 #define PHY84328_DEV7_UP1_DATARATE_12GX4_BITS 1 12319 #define PHY84328_DEV7_UP1_DATARATE_12GX4_SHIFT 5 12320 12321 /* ln_device7 :: UP1 :: dataRate_10GCX4 [04:04] */ 12322 #define PHY84328_DEV7_UP1_DATARATE_10GCX4_MASK 0x0010 12323 #define PHY84328_DEV7_UP1_DATARATE_10GCX4_ALIGN 0 12324 #define PHY84328_DEV7_UP1_DATARATE_10GCX4_BITS 1 12325 #define PHY84328_DEV7_UP1_DATARATE_10GCX4_SHIFT 4 12326 12327 /* ln_device7 :: UP1 :: dataRate_10GX4 [03:03] */ 12328 #define PHY84328_DEV7_UP1_DATARATE_10GX4_MASK 0x0008 12329 #define PHY84328_DEV7_UP1_DATARATE_10GX4_ALIGN 0 12330 #define PHY84328_DEV7_UP1_DATARATE_10GX4_BITS 1 12331 #define PHY84328_DEV7_UP1_DATARATE_10GX4_SHIFT 3 12332 12333 /* ln_device7 :: UP1 :: dataRate_6GX4 [02:02] */ 12334 #define PHY84328_DEV7_UP1_DATARATE_6GX4_MASK 0x0004 12335 #define PHY84328_DEV7_UP1_DATARATE_6GX4_ALIGN 0 12336 #define PHY84328_DEV7_UP1_DATARATE_6GX4_BITS 1 12337 #define PHY84328_DEV7_UP1_DATARATE_6GX4_SHIFT 2 12338 12339 /* ln_device7 :: UP1 :: dataRate_5GX4 [01:01] */ 12340 #define PHY84328_DEV7_UP1_DATARATE_5GX4_MASK 0x0002 12341 #define PHY84328_DEV7_UP1_DATARATE_5GX4_ALIGN 0 12342 #define PHY84328_DEV7_UP1_DATARATE_5GX4_BITS 1 12343 #define PHY84328_DEV7_UP1_DATARATE_5GX4_SHIFT 1 12344 12345 /* ln_device7 :: UP1 :: dataRate_2p5GX1 [00:00] */ 12346 #define PHY84328_DEV7_UP1_DATARATE_2P5GX1_MASK 0x0001 12347 #define PHY84328_DEV7_UP1_DATARATE_2P5GX1_ALIGN 0 12348 #define PHY84328_DEV7_UP1_DATARATE_2P5GX1_BITS 1 12349 #define PHY84328_DEV7_UP1_DATARATE_2P5GX1_SHIFT 0 12350 12351 12352 /**************************************************************************** 12353 * ln_device7 :: UP2 12354 */ 12355 /* ln_device7 :: UP2 :: reserved0 [15:11] */ 12356 #define PHY84328_DEV7_UP2_RESERVED0_MASK 0xf800 12357 #define PHY84328_DEV7_UP2_RESERVED0_ALIGN 0 12358 #define PHY84328_DEV7_UP2_RESERVED0_BITS 5 12359 #define PHY84328_DEV7_UP2_RESERVED0_SHIFT 11 12360 12361 /* ln_device7 :: UP2 :: valid [10:10] */ 12362 #define PHY84328_DEV7_UP2_VALID_MASK 0x0400 12363 #define PHY84328_DEV7_UP2_VALID_ALIGN 0 12364 #define PHY84328_DEV7_UP2_VALID_BITS 1 12365 #define PHY84328_DEV7_UP2_VALID_SHIFT 10 12366 12367 /* ln_device7 :: UP2 :: preemphasis [09:06] */ 12368 #define PHY84328_DEV7_UP2_PREEMPHASIS_MASK 0x03c0 12369 #define PHY84328_DEV7_UP2_PREEMPHASIS_ALIGN 0 12370 #define PHY84328_DEV7_UP2_PREEMPHASIS_BITS 4 12371 #define PHY84328_DEV7_UP2_PREEMPHASIS_SHIFT 6 12372 12373 /* ln_device7 :: UP2 :: idriver [05:03] */ 12374 #define PHY84328_DEV7_UP2_IDRIVER_MASK 0x0038 12375 #define PHY84328_DEV7_UP2_IDRIVER_ALIGN 0 12376 #define PHY84328_DEV7_UP2_IDRIVER_BITS 3 12377 #define PHY84328_DEV7_UP2_IDRIVER_SHIFT 3 12378 12379 /* ln_device7 :: UP2 :: ipredriver [02:00] */ 12380 #define PHY84328_DEV7_UP2_IPREDRIVER_MASK 0x0007 12381 #define PHY84328_DEV7_UP2_IPREDRIVER_ALIGN 0 12382 #define PHY84328_DEV7_UP2_IPREDRIVER_BITS 3 12383 #define PHY84328_DEV7_UP2_IPREDRIVER_SHIFT 0 12384 12385 12386 /**************************************************************************** 12387 * ln_device7 :: UP3 12388 */ 12389 /* ln_device7 :: UP3 :: reserved0 [15:11] */ 12390 #define PHY84328_DEV7_UP3_RESERVED0_MASK 0xf800 12391 #define PHY84328_DEV7_UP3_RESERVED0_ALIGN 0 12392 #define PHY84328_DEV7_UP3_RESERVED0_BITS 5 12393 #define PHY84328_DEV7_UP3_RESERVED0_SHIFT 11 12394 12395 /* ln_device7 :: UP3 :: last [10:10] */ 12396 #define PHY84328_DEV7_UP3_LAST_MASK 0x0400 12397 #define PHY84328_DEV7_UP3_LAST_ALIGN 0 12398 #define PHY84328_DEV7_UP3_LAST_BITS 1 12399 #define PHY84328_DEV7_UP3_LAST_SHIFT 10 12400 12401 /* ln_device7 :: UP3 :: dataRate_21GX4 [09:09] */ 12402 #define PHY84328_DEV7_UP3_DATARATE_21GX4_MASK 0x0200 12403 #define PHY84328_DEV7_UP3_DATARATE_21GX4_ALIGN 0 12404 #define PHY84328_DEV7_UP3_DATARATE_21GX4_BITS 1 12405 #define PHY84328_DEV7_UP3_DATARATE_21GX4_SHIFT 9 12406 12407 /* ln_device7 :: UP3 :: dataRate_25p45GX4 [08:08] */ 12408 #define PHY84328_DEV7_UP3_DATARATE_25P45GX4_MASK 0x0100 12409 #define PHY84328_DEV7_UP3_DATARATE_25P45GX4_ALIGN 0 12410 #define PHY84328_DEV7_UP3_DATARATE_25P45GX4_BITS 1 12411 #define PHY84328_DEV7_UP3_DATARATE_25P45GX4_SHIFT 8 12412 12413 /* ln_device7 :: UP3 :: dataRate_31p5G [07:07] */ 12414 #define PHY84328_DEV7_UP3_DATARATE_31P5G_MASK 0x0080 12415 #define PHY84328_DEV7_UP3_DATARATE_31P5G_ALIGN 0 12416 #define PHY84328_DEV7_UP3_DATARATE_31P5G_BITS 1 12417 #define PHY84328_DEV7_UP3_DATARATE_31P5G_SHIFT 7 12418 12419 /* ln_device7 :: UP3 :: reserved1 [06:06] */ 12420 #define PHY84328_DEV7_UP3_RESERVED1_MASK 0x0040 12421 #define PHY84328_DEV7_UP3_RESERVED1_ALIGN 0 12422 #define PHY84328_DEV7_UP3_RESERVED1_BITS 1 12423 #define PHY84328_DEV7_UP3_RESERVED1_SHIFT 6 12424 12425 /* ln_device7 :: UP3 :: dataRate_40G [05:05] */ 12426 #define PHY84328_DEV7_UP3_DATARATE_40G_MASK 0x0020 12427 #define PHY84328_DEV7_UP3_DATARATE_40G_ALIGN 0 12428 #define PHY84328_DEV7_UP3_DATARATE_40G_BITS 1 12429 #define PHY84328_DEV7_UP3_DATARATE_40G_SHIFT 5 12430 12431 /* ln_device7 :: UP3 :: reserved2 [04:03] */ 12432 #define PHY84328_DEV7_UP3_RESERVED2_MASK 0x0018 12433 #define PHY84328_DEV7_UP3_RESERVED2_ALIGN 0 12434 #define PHY84328_DEV7_UP3_RESERVED2_BITS 2 12435 #define PHY84328_DEV7_UP3_RESERVED2_SHIFT 3 12436 12437 /* ln_device7 :: UP3 :: Cl72 [02:02] */ 12438 #define PHY84328_DEV7_UP3_CL72_MASK 0x0004 12439 #define PHY84328_DEV7_UP3_CL72_ALIGN 0 12440 #define PHY84328_DEV7_UP3_CL72_BITS 1 12441 #define PHY84328_DEV7_UP3_CL72_SHIFT 2 12442 12443 /* ln_device7 :: UP3 :: FEC [01:01] */ 12444 #define PHY84328_DEV7_UP3_FEC_MASK 0x0002 12445 #define PHY84328_DEV7_UP3_FEC_ALIGN 0 12446 #define PHY84328_DEV7_UP3_FEC_BITS 1 12447 #define PHY84328_DEV7_UP3_FEC_SHIFT 1 12448 12449 /* ln_device7 :: UP3 :: HiGig2 [00:00] */ 12450 #define PHY84328_DEV7_UP3_HIGIG2_MASK 0x0001 12451 #define PHY84328_DEV7_UP3_HIGIG2_ALIGN 0 12452 #define PHY84328_DEV7_UP3_HIGIG2_BITS 1 12453 #define PHY84328_DEV7_UP3_HIGIG2_SHIFT 0 12454 12455 12456 /**************************************************************************** 12457 * ln_device7 :: xgxsblock4LP_UP1 12458 */ 12459 /* ln_device7 :: xgxsblock4LP_UP1 :: reserved0 [15:11] */ 12460 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_RESERVED0_MASK 0xf800 12461 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_RESERVED0_ALIGN 0 12462 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_RESERVED0_BITS 5 12463 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_RESERVED0_SHIFT 11 12464 12465 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_20GX4 [10:10] */ 12466 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_20GX4_MASK 0x0400 12467 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_20GX4_ALIGN 0 12468 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_20GX4_BITS 1 12469 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_20GX4_SHIFT 10 12470 12471 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_16GX4 [09:09] */ 12472 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_16GX4_MASK 0x0200 12473 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_16GX4_ALIGN 0 12474 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_16GX4_BITS 1 12475 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_16GX4_SHIFT 9 12476 12477 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_15GX4 [08:08] */ 12478 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_15GX4_MASK 0x0100 12479 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_15GX4_ALIGN 0 12480 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_15GX4_BITS 1 12481 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_15GX4_SHIFT 8 12482 12483 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_13GX4 [07:07] */ 12484 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_13GX4_MASK 0x0080 12485 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_13GX4_ALIGN 0 12486 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_13GX4_BITS 1 12487 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_13GX4_SHIFT 7 12488 12489 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_12p5GX4 [06:06] */ 12490 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12P5GX4_MASK 0x0040 12491 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12P5GX4_ALIGN 0 12492 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12P5GX4_BITS 1 12493 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12P5GX4_SHIFT 6 12494 12495 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_12GX4 [05:05] */ 12496 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12GX4_MASK 0x0020 12497 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12GX4_ALIGN 0 12498 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12GX4_BITS 1 12499 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12GX4_SHIFT 5 12500 12501 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_10GCX4 [04:04] */ 12502 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GCX4_MASK 0x0010 12503 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GCX4_ALIGN 0 12504 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GCX4_BITS 1 12505 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GCX4_SHIFT 4 12506 12507 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_10GX4 [03:03] */ 12508 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GX4_MASK 0x0008 12509 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GX4_ALIGN 0 12510 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GX4_BITS 1 12511 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GX4_SHIFT 3 12512 12513 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_6GX4 [02:02] */ 12514 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_6GX4_MASK 0x0004 12515 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_6GX4_ALIGN 0 12516 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_6GX4_BITS 1 12517 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_6GX4_SHIFT 2 12518 12519 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_5GX4 [01:01] */ 12520 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_5GX4_MASK 0x0002 12521 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_5GX4_ALIGN 0 12522 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_5GX4_BITS 1 12523 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_5GX4_SHIFT 1 12524 12525 /* ln_device7 :: xgxsblock4LP_UP1 :: dataRate_2p5GX1 [00:00] */ 12526 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_2P5GX1_MASK 0x0001 12527 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_2P5GX1_ALIGN 0 12528 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_2P5GX1_BITS 1 12529 #define PHY84328_DEV7_XGXSBLOCK4LP_UP1_DATARATE_2P5GX1_SHIFT 0 12530 12531 12532 /**************************************************************************** 12533 * ln_device7 :: xgxsblock4LP_UP2 12534 */ 12535 /* ln_device7 :: xgxsblock4LP_UP2 :: reserved0 [15:11] */ 12536 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_RESERVED0_MASK 0xf800 12537 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_RESERVED0_ALIGN 0 12538 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_RESERVED0_BITS 5 12539 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_RESERVED0_SHIFT 11 12540 12541 /* ln_device7 :: xgxsblock4LP_UP2 :: valid [10:10] */ 12542 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_VALID_MASK 0x0400 12543 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_VALID_ALIGN 0 12544 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_VALID_BITS 1 12545 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_VALID_SHIFT 10 12546 12547 /* ln_device7 :: xgxsblock4LP_UP2 :: preemphasis [09:06] */ 12548 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_PREEMPHASIS_MASK 0x03c0 12549 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_PREEMPHASIS_ALIGN 0 12550 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_PREEMPHASIS_BITS 4 12551 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_PREEMPHASIS_SHIFT 6 12552 12553 /* ln_device7 :: xgxsblock4LP_UP2 :: idriver [05:03] */ 12554 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_IDRIVER_MASK 0x0038 12555 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_IDRIVER_ALIGN 0 12556 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_IDRIVER_BITS 3 12557 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_IDRIVER_SHIFT 3 12558 12559 /* ln_device7 :: xgxsblock4LP_UP2 :: ipredriver [02:00] */ 12560 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_IPREDRIVER_MASK 0x0007 12561 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_IPREDRIVER_ALIGN 0 12562 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_IPREDRIVER_BITS 3 12563 #define PHY84328_DEV7_XGXSBLOCK4LP_UP2_IPREDRIVER_SHIFT 0 12564 12565 12566 /**************************************************************************** 12567 * ln_device7 :: xgxsblock4LP_UP3 12568 */ 12569 /* ln_device7 :: xgxsblock4LP_UP3 :: reserved0 [15:11] */ 12570 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED0_MASK 0xf800 12571 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED0_ALIGN 0 12572 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED0_BITS 5 12573 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED0_SHIFT 11 12574 12575 /* ln_device7 :: xgxsblock4LP_UP3 :: last [10:10] */ 12576 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_LAST_MASK 0x0400 12577 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_LAST_ALIGN 0 12578 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_LAST_BITS 1 12579 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_LAST_SHIFT 10 12580 12581 /* ln_device7 :: xgxsblock4LP_UP3 :: dataRate_21GX4 [09:09] */ 12582 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_21GX4_MASK 0x0200 12583 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_21GX4_ALIGN 0 12584 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_21GX4_BITS 1 12585 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_21GX4_SHIFT 9 12586 12587 /* ln_device7 :: xgxsblock4LP_UP3 :: dataRate_25p45GX4 [08:08] */ 12588 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_25P45GX4_MASK 0x0100 12589 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_25P45GX4_ALIGN 0 12590 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_25P45GX4_BITS 1 12591 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_25P45GX4_SHIFT 8 12592 12593 /* ln_device7 :: xgxsblock4LP_UP3 :: dataRate_31p5G [07:07] */ 12594 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_31P5G_MASK 0x0080 12595 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_31P5G_ALIGN 0 12596 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_31P5G_BITS 1 12597 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_31P5G_SHIFT 7 12598 12599 /* ln_device7 :: xgxsblock4LP_UP3 :: reserved1 [06:06] */ 12600 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED1_MASK 0x0040 12601 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED1_ALIGN 0 12602 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED1_BITS 1 12603 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED1_SHIFT 6 12604 12605 /* ln_device7 :: xgxsblock4LP_UP3 :: dataRate_40G [05:05] */ 12606 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_40G_MASK 0x0020 12607 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_40G_ALIGN 0 12608 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_40G_BITS 1 12609 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_DATARATE_40G_SHIFT 5 12610 12611 /* ln_device7 :: xgxsblock4LP_UP3 :: reserved2 [04:03] */ 12612 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED2_MASK 0x0018 12613 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED2_ALIGN 0 12614 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED2_BITS 2 12615 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_RESERVED2_SHIFT 3 12616 12617 /* ln_device7 :: xgxsblock4LP_UP3 :: Cl72 [02:02] */ 12618 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_CL72_MASK 0x0004 12619 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_CL72_ALIGN 0 12620 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_CL72_BITS 1 12621 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_CL72_SHIFT 2 12622 12623 /* ln_device7 :: xgxsblock4LP_UP3 :: FEC [01:01] */ 12624 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_FEC_MASK 0x0002 12625 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_FEC_ALIGN 0 12626 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_FEC_BITS 1 12627 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_FEC_SHIFT 1 12628 12629 /* ln_device7 :: xgxsblock4LP_UP3 :: HiGig2 [00:00] */ 12630 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_HIGIG2_MASK 0x0001 12631 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_HIGIG2_ALIGN 0 12632 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_HIGIG2_BITS 1 12633 #define PHY84328_DEV7_XGXSBLOCK4LP_UP3_HIGIG2_SHIFT 0 12634 12635 12636 /**************************************************************************** 12637 * ln_device7 :: rphyMiscRxStatus 12638 */ 12639 /* ln_device7 :: rphyMiscRxStatus :: capture_NP_lh [15:15] */ 12640 #define PHY84328_DEV7_RPHYMISCRXSTATUS_CAPTURE_NP_LH_MASK 0x8000 12641 #define PHY84328_DEV7_RPHYMISCRXSTATUS_CAPTURE_NP_LH_ALIGN 0 12642 #define PHY84328_DEV7_RPHYMISCRXSTATUS_CAPTURE_NP_LH_BITS 1 12643 #define PHY84328_DEV7_RPHYMISCRXSTATUS_CAPTURE_NP_LH_SHIFT 15 12644 12645 /* ln_device7 :: rphyMiscRxStatus :: teton_brk_link_lh [14:14] */ 12646 #define PHY84328_DEV7_RPHYMISCRXSTATUS_TETON_BRK_LINK_LH_MASK 0x4000 12647 #define PHY84328_DEV7_RPHYMISCRXSTATUS_TETON_BRK_LINK_LH_ALIGN 0 12648 #define PHY84328_DEV7_RPHYMISCRXSTATUS_TETON_BRK_LINK_LH_BITS 1 12649 #define PHY84328_DEV7_RPHYMISCRXSTATUS_TETON_BRK_LINK_LH_SHIFT 14 12650 12651 /* ln_device7 :: rphyMiscRxStatus :: UP3_lh [13:13] */ 12652 #define PHY84328_DEV7_RPHYMISCRXSTATUS_UP3_LH_MASK 0x2000 12653 #define PHY84328_DEV7_RPHYMISCRXSTATUS_UP3_LH_ALIGN 0 12654 #define PHY84328_DEV7_RPHYMISCRXSTATUS_UP3_LH_BITS 1 12655 #define PHY84328_DEV7_RPHYMISCRXSTATUS_UP3_LH_SHIFT 13 12656 12657 /* ln_device7 :: rphyMiscRxStatus :: MP5_lh [12:12] */ 12658 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MP5_LH_MASK 0x1000 12659 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MP5_LH_ALIGN 0 12660 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MP5_LH_BITS 1 12661 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MP5_LH_SHIFT 12 12662 12663 /* ln_device7 :: rphyMiscRxStatus :: nonMatchingOUI_lh [11:11] */ 12664 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NONMATCHINGOUI_LH_MASK 0x0800 12665 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NONMATCHINGOUI_LH_ALIGN 0 12666 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NONMATCHINGOUI_LH_BITS 1 12667 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NONMATCHINGOUI_LH_SHIFT 11 12668 12669 /* ln_device7 :: rphyMiscRxStatus :: matchingOUI_msb_lh [10:10] */ 12670 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_MSB_LH_MASK 0x0400 12671 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_MSB_LH_ALIGN 0 12672 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_MSB_LH_BITS 1 12673 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_MSB_LH_SHIFT 10 12674 12675 /* ln_device7 :: rphyMiscRxStatus :: matchingOUI_lsb_lh [09:09] */ 12676 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_LSB_LH_MASK 0x0200 12677 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_LSB_LH_ALIGN 0 12678 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_LSB_LH_BITS 1 12679 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_LSB_LH_SHIFT 9 12680 12681 /* ln_device7 :: rphyMiscRxStatus :: invalidSeq_lh [08:08] */ 12682 #define PHY84328_DEV7_RPHYMISCRXSTATUS_INVALIDSEQ_LH_MASK 0x0100 12683 #define PHY84328_DEV7_RPHYMISCRXSTATUS_INVALIDSEQ_LH_ALIGN 0 12684 #define PHY84328_DEV7_RPHYMISCRXSTATUS_INVALIDSEQ_LH_BITS 1 12685 #define PHY84328_DEV7_RPHYMISCRXSTATUS_INVALIDSEQ_LH_SHIFT 8 12686 12687 /* ln_device7 :: rphyMiscRxStatus :: nullMP_lh [07:07] */ 12688 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NULLMP_LH_MASK 0x0080 12689 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NULLMP_LH_ALIGN 0 12690 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NULLMP_LH_BITS 1 12691 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NULLMP_LH_SHIFT 7 12692 12693 /* ln_device7 :: rphyMiscRxStatus :: remotePhyMP_lh [06:06] */ 12694 #define PHY84328_DEV7_RPHYMISCRXSTATUS_REMOTEPHYMP_LH_MASK 0x0040 12695 #define PHY84328_DEV7_RPHYMISCRXSTATUS_REMOTEPHYMP_LH_ALIGN 0 12696 #define PHY84328_DEV7_RPHYMISCRXSTATUS_REMOTEPHYMP_LH_BITS 1 12697 #define PHY84328_DEV7_RPHYMISCRXSTATUS_REMOTEPHYMP_LH_SHIFT 6 12698 12699 /* ln_device7 :: rphyMiscRxStatus :: nonMatchingMP_lh [05:05] */ 12700 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NONMATCHINGMP_LH_MASK 0x0020 12701 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NONMATCHINGMP_LH_ALIGN 0 12702 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NONMATCHINGMP_LH_BITS 1 12703 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NONMATCHINGMP_LH_SHIFT 5 12704 12705 /* ln_device7 :: rphyMiscRxStatus :: over1gMP_lh [04:04] */ 12706 #define PHY84328_DEV7_RPHYMISCRXSTATUS_OVER1GMP_LH_MASK 0x0010 12707 #define PHY84328_DEV7_RPHYMISCRXSTATUS_OVER1GMP_LH_ALIGN 0 12708 #define PHY84328_DEV7_RPHYMISCRXSTATUS_OVER1GMP_LH_BITS 1 12709 #define PHY84328_DEV7_RPHYMISCRXSTATUS_OVER1GMP_LH_SHIFT 4 12710 12711 /* ln_device7 :: rphyMiscRxStatus :: rx_config_is_0_lh [03:03] */ 12712 #define PHY84328_DEV7_RPHYMISCRXSTATUS_RX_CONFIG_IS_0_LH_MASK 0x0008 12713 #define PHY84328_DEV7_RPHYMISCRXSTATUS_RX_CONFIG_IS_0_LH_ALIGN 0 12714 #define PHY84328_DEV7_RPHYMISCRXSTATUS_RX_CONFIG_IS_0_LH_BITS 1 12715 #define PHY84328_DEV7_RPHYMISCRXSTATUS_RX_CONFIG_IS_0_LH_SHIFT 3 12716 12717 /* ln_device7 :: rphyMiscRxStatus :: np_toggle_err_lh [02:02] */ 12718 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NP_TOGGLE_ERR_LH_MASK 0x0004 12719 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NP_TOGGLE_ERR_LH_ALIGN 0 12720 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NP_TOGGLE_ERR_LH_BITS 1 12721 #define PHY84328_DEV7_RPHYMISCRXSTATUS_NP_TOGGLE_ERR_LH_SHIFT 2 12722 12723 /* ln_device7 :: rphyMiscRxStatus :: mr_np_lh [01:01] */ 12724 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MR_NP_LH_MASK 0x0002 12725 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MR_NP_LH_ALIGN 0 12726 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MR_NP_LH_BITS 1 12727 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MR_NP_LH_SHIFT 1 12728 12729 /* ln_device7 :: rphyMiscRxStatus :: mr_bp_lh [00:00] */ 12730 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MR_BP_LH_MASK 0x0001 12731 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MR_BP_LH_ALIGN 0 12732 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MR_BP_LH_BITS 1 12733 #define PHY84328_DEV7_RPHYMISCRXSTATUS_MR_BP_LH_SHIFT 0 12734 12735 12736 /**************************************************************************** 12737 * ln_device7 :: lp_basePage 12738 */ 12739 /* ln_device7 :: lp_basePage :: lp_basePage [15:00] */ 12740 #define PHY84328_DEV7_LP_BASEPAGE_LP_BASEPAGE_MASK 0xffff 12741 #define PHY84328_DEV7_LP_BASEPAGE_LP_BASEPAGE_ALIGN 0 12742 #define PHY84328_DEV7_LP_BASEPAGE_LP_BASEPAGE_BITS 16 12743 #define PHY84328_DEV7_LP_BASEPAGE_LP_BASEPAGE_SHIFT 0 12744 12745 12746 /**************************************************************************** 12747 * ln_device7 :: lp_nextPage_0 12748 */ 12749 /* ln_device7 :: lp_nextPage_0 :: lp_nextPage_0 [15:00] */ 12750 #define PHY84328_DEV7_LP_NEXTPAGE_0_LP_NEXTPAGE_0_MASK 0xffff 12751 #define PHY84328_DEV7_LP_NEXTPAGE_0_LP_NEXTPAGE_0_ALIGN 0 12752 #define PHY84328_DEV7_LP_NEXTPAGE_0_LP_NEXTPAGE_0_BITS 16 12753 #define PHY84328_DEV7_LP_NEXTPAGE_0_LP_NEXTPAGE_0_SHIFT 0 12754 12755 12756 /**************************************************************************** 12757 * ln_device7 :: lp_nextPage_1 12758 */ 12759 /* ln_device7 :: lp_nextPage_1 :: lp_nextPage_1 [15:00] */ 12760 #define PHY84328_DEV7_LP_NEXTPAGE_1_LP_NEXTPAGE_1_MASK 0xffff 12761 #define PHY84328_DEV7_LP_NEXTPAGE_1_LP_NEXTPAGE_1_ALIGN 0 12762 #define PHY84328_DEV7_LP_NEXTPAGE_1_LP_NEXTPAGE_1_BITS 16 12763 #define PHY84328_DEV7_LP_NEXTPAGE_1_LP_NEXTPAGE_1_SHIFT 0 12764 12765 12766 /**************************************************************************** 12767 * ln_device7 :: lp_nextPage_2 12768 */ 12769 /* ln_device7 :: lp_nextPage_2 :: lp_nextPage_2 [15:00] */ 12770 #define PHY84328_DEV7_LP_NEXTPAGE_2_LP_NEXTPAGE_2_MASK 0xffff 12771 #define PHY84328_DEV7_LP_NEXTPAGE_2_LP_NEXTPAGE_2_ALIGN 0 12772 #define PHY84328_DEV7_LP_NEXTPAGE_2_LP_NEXTPAGE_2_BITS 16 12773 #define PHY84328_DEV7_LP_NEXTPAGE_2_LP_NEXTPAGE_2_SHIFT 0 12774 12775 12776 /**************************************************************************** 12777 * ln_device7 :: lp_nextPage_3 12778 */ 12779 /* ln_device7 :: lp_nextPage_3 :: lp_nextPage_3 [15:00] */ 12780 #define PHY84328_DEV7_LP_NEXTPAGE_3_LP_NEXTPAGE_3_MASK 0xffff 12781 #define PHY84328_DEV7_LP_NEXTPAGE_3_LP_NEXTPAGE_3_ALIGN 0 12782 #define PHY84328_DEV7_LP_NEXTPAGE_3_LP_NEXTPAGE_3_BITS 16 12783 #define PHY84328_DEV7_LP_NEXTPAGE_3_LP_NEXTPAGE_3_SHIFT 0 12784 12785 12786 /**************************************************************************** 12787 * ln_device7 :: lp_nextPage_4 12788 */ 12789 /* ln_device7 :: lp_nextPage_4 :: lp_nextPage_4 [15:00] */ 12790 #define PHY84328_DEV7_LP_NEXTPAGE_4_LP_NEXTPAGE_4_MASK 0xffff 12791 #define PHY84328_DEV7_LP_NEXTPAGE_4_LP_NEXTPAGE_4_ALIGN 0 12792 #define PHY84328_DEV7_LP_NEXTPAGE_4_LP_NEXTPAGE_4_BITS 16 12793 #define PHY84328_DEV7_LP_NEXTPAGE_4_LP_NEXTPAGE_4_SHIFT 0 12794 12795 12796 /**************************************************************************** 12797 * ln_device7 :: rp_nextPage_0 12798 */ 12799 /* ln_device7 :: rp_nextPage_0 :: reserved0 [15:15] */ 12800 #define PHY84328_DEV7_RP_NEXTPAGE_0_RESERVED0_MASK 0x8000 12801 #define PHY84328_DEV7_RP_NEXTPAGE_0_RESERVED0_ALIGN 0 12802 #define PHY84328_DEV7_RP_NEXTPAGE_0_RESERVED0_BITS 1 12803 #define PHY84328_DEV7_RP_NEXTPAGE_0_RESERVED0_SHIFT 15 12804 12805 /* ln_device7 :: rp_nextPage_0 :: extra_page_disable [14:14] */ 12806 #define PHY84328_DEV7_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_MASK 0x4000 12807 #define PHY84328_DEV7_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_ALIGN 0 12808 #define PHY84328_DEV7_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_BITS 1 12809 #define PHY84328_DEV7_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_SHIFT 14 12810 12811 /* ln_device7 :: rp_nextPage_0 :: null_page_enable [13:13] */ 12812 #define PHY84328_DEV7_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_MASK 0x2000 12813 #define PHY84328_DEV7_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_ALIGN 0 12814 #define PHY84328_DEV7_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_BITS 1 12815 #define PHY84328_DEV7_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_SHIFT 13 12816 12817 /* ln_device7 :: rp_nextPage_0 :: over_1g_disable [12:12] */ 12818 #define PHY84328_DEV7_RP_NEXTPAGE_0_OVER_1G_DISABLE_MASK 0x1000 12819 #define PHY84328_DEV7_RP_NEXTPAGE_0_OVER_1G_DISABLE_ALIGN 0 12820 #define PHY84328_DEV7_RP_NEXTPAGE_0_OVER_1G_DISABLE_BITS 1 12821 #define PHY84328_DEV7_RP_NEXTPAGE_0_OVER_1G_DISABLE_SHIFT 12 12822 12823 /* ln_device7 :: rp_nextPage_0 :: remote_phy_enable [11:11] */ 12824 #define PHY84328_DEV7_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_MASK 0x0800 12825 #define PHY84328_DEV7_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_ALIGN 0 12826 #define PHY84328_DEV7_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_BITS 1 12827 #define PHY84328_DEV7_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_SHIFT 11 12828 12829 /* ln_device7 :: rp_nextPage_0 :: rp_nextPage_0 [10:00] */ 12830 #define PHY84328_DEV7_RP_NEXTPAGE_0_RP_NEXTPAGE_0_MASK 0x07ff 12831 #define PHY84328_DEV7_RP_NEXTPAGE_0_RP_NEXTPAGE_0_ALIGN 0 12832 #define PHY84328_DEV7_RP_NEXTPAGE_0_RP_NEXTPAGE_0_BITS 11 12833 #define PHY84328_DEV7_RP_NEXTPAGE_0_RP_NEXTPAGE_0_SHIFT 0 12834 12835 12836 /**************************************************************************** 12837 * ln_device7 :: rp_nextPage_1 12838 */ 12839 /* ln_device7 :: rp_nextPage_1 :: reserved0 [15:15] */ 12840 #define PHY84328_DEV7_RP_NEXTPAGE_1_RESERVED0_MASK 0x8000 12841 #define PHY84328_DEV7_RP_NEXTPAGE_1_RESERVED0_ALIGN 0 12842 #define PHY84328_DEV7_RP_NEXTPAGE_1_RESERVED0_BITS 1 12843 #define PHY84328_DEV7_RP_NEXTPAGE_1_RESERVED0_SHIFT 15 12844 12845 /* ln_device7 :: rp_nextPage_1 :: remotePhy_linkDown_rstrt_disable [14:14] */ 12846 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_MASK 0x4000 12847 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_ALIGN 0 12848 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_BITS 1 12849 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_SHIFT 14 12850 12851 /* ln_device7 :: rp_nextPage_1 :: remotePhy_rsltn_err_rstrt_disable [13:13] */ 12852 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_MASK 0x2000 12853 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_ALIGN 0 12854 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_BITS 1 12855 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_SHIFT 13 12856 12857 /* ln_device7 :: rp_nextPage_1 :: remotePhy_resolution_disable [12:12] */ 12858 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_MASK 0x1000 12859 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_ALIGN 0 12860 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_BITS 1 12861 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_SHIFT 12 12862 12863 /* ln_device7 :: rp_nextPage_1 :: remotePhy_decode_enable [11:11] */ 12864 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_MASK 0x0800 12865 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_ALIGN 0 12866 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_BITS 1 12867 #define PHY84328_DEV7_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_SHIFT 11 12868 12869 /* ln_device7 :: rp_nextPage_1 :: rp_nextPage_1 [10:00] */ 12870 #define PHY84328_DEV7_RP_NEXTPAGE_1_RP_NEXTPAGE_1_MASK 0x07ff 12871 #define PHY84328_DEV7_RP_NEXTPAGE_1_RP_NEXTPAGE_1_ALIGN 0 12872 #define PHY84328_DEV7_RP_NEXTPAGE_1_RP_NEXTPAGE_1_BITS 11 12873 #define PHY84328_DEV7_RP_NEXTPAGE_1_RP_NEXTPAGE_1_SHIFT 0 12874 12875 12876 /**************************************************************************** 12877 * ln_device7 :: rp_nextPage_2 12878 */ 12879 /* ln_device7 :: rp_nextPage_2 :: reserved0 [15:12] */ 12880 #define PHY84328_DEV7_RP_NEXTPAGE_2_RESERVED0_MASK 0xf000 12881 #define PHY84328_DEV7_RP_NEXTPAGE_2_RESERVED0_ALIGN 0 12882 #define PHY84328_DEV7_RP_NEXTPAGE_2_RESERVED0_BITS 4 12883 #define PHY84328_DEV7_RP_NEXTPAGE_2_RESERVED0_SHIFT 12 12884 12885 /* ln_device7 :: rp_nextPage_2 :: remPhy_NP_clr_disable [11:11] */ 12886 #define PHY84328_DEV7_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_MASK 0x0800 12887 #define PHY84328_DEV7_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_ALIGN 0 12888 #define PHY84328_DEV7_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_BITS 1 12889 #define PHY84328_DEV7_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_SHIFT 11 12890 12891 /* ln_device7 :: rp_nextPage_2 :: rp_nextPage_2 [10:00] */ 12892 #define PHY84328_DEV7_RP_NEXTPAGE_2_RP_NEXTPAGE_2_MASK 0x07ff 12893 #define PHY84328_DEV7_RP_NEXTPAGE_2_RP_NEXTPAGE_2_ALIGN 0 12894 #define PHY84328_DEV7_RP_NEXTPAGE_2_RP_NEXTPAGE_2_BITS 11 12895 #define PHY84328_DEV7_RP_NEXTPAGE_2_RP_NEXTPAGE_2_SHIFT 0 12896 12897 12898 /**************************************************************************** 12899 * ln_device7 :: rp_nextPage_3 12900 */ 12901 /* ln_device7 :: rp_nextPage_3 :: reserved0 [15:11] */ 12902 #define PHY84328_DEV7_RP_NEXTPAGE_3_RESERVED0_MASK 0xf800 12903 #define PHY84328_DEV7_RP_NEXTPAGE_3_RESERVED0_ALIGN 0 12904 #define PHY84328_DEV7_RP_NEXTPAGE_3_RESERVED0_BITS 5 12905 #define PHY84328_DEV7_RP_NEXTPAGE_3_RESERVED0_SHIFT 11 12906 12907 /* ln_device7 :: rp_nextPage_3 :: rp_nextPage_3 [10:00] */ 12908 #define PHY84328_DEV7_RP_NEXTPAGE_3_RP_NEXTPAGE_3_MASK 0x07ff 12909 #define PHY84328_DEV7_RP_NEXTPAGE_3_RP_NEXTPAGE_3_ALIGN 0 12910 #define PHY84328_DEV7_RP_NEXTPAGE_3_RP_NEXTPAGE_3_BITS 11 12911 #define PHY84328_DEV7_RP_NEXTPAGE_3_RP_NEXTPAGE_3_SHIFT 0 12912 12913 12914 /**************************************************************************** 12915 * ln_device7 :: rp_nextPage_4 12916 */ 12917 /* ln_device7 :: rp_nextPage_4 :: reserved0 [15:11] */ 12918 #define PHY84328_DEV7_RP_NEXTPAGE_4_RESERVED0_MASK 0xf800 12919 #define PHY84328_DEV7_RP_NEXTPAGE_4_RESERVED0_ALIGN 0 12920 #define PHY84328_DEV7_RP_NEXTPAGE_4_RESERVED0_BITS 5 12921 #define PHY84328_DEV7_RP_NEXTPAGE_4_RESERVED0_SHIFT 11 12922 12923 /* ln_device7 :: rp_nextPage_4 :: rp_nextPage_4 [10:00] */ 12924 #define PHY84328_DEV7_RP_NEXTPAGE_4_RP_NEXTPAGE_4_MASK 0x07ff 12925 #define PHY84328_DEV7_RP_NEXTPAGE_4_RP_NEXTPAGE_4_ALIGN 0 12926 #define PHY84328_DEV7_RP_NEXTPAGE_4_RP_NEXTPAGE_4_BITS 11 12927 #define PHY84328_DEV7_RP_NEXTPAGE_4_RP_NEXTPAGE_4_SHIFT 0 12928 12929 12930 /**************************************************************************** 12931 * ln_device7 :: Misc3 12932 */ 12933 /* ln_device7 :: Misc3 :: ind_40bitif [15:15] */ 12934 #define PHY84328_DEV7_MISC3_IND_40BITIF_MASK 0x8000 12935 #define PHY84328_DEV7_MISC3_IND_40BITIF_ALIGN 0 12936 #define PHY84328_DEV7_MISC3_IND_40BITIF_BITS 1 12937 #define PHY84328_DEV7_MISC3_IND_40BITIF_SHIFT 15 12938 12939 /* ln_device7 :: Misc3 :: cl49_ed66_en_override [14:14] */ 12940 #define PHY84328_DEV7_MISC3_CL49_ED66_EN_OVERRIDE_MASK 0x4000 12941 #define PHY84328_DEV7_MISC3_CL49_ED66_EN_OVERRIDE_ALIGN 0 12942 #define PHY84328_DEV7_MISC3_CL49_ED66_EN_OVERRIDE_BITS 1 12943 #define PHY84328_DEV7_MISC3_CL49_ED66_EN_OVERRIDE_SHIFT 14 12944 12945 /* ln_device7 :: Misc3 :: cl49_ed66_en_val [13:13] */ 12946 #define PHY84328_DEV7_MISC3_CL49_ED66_EN_VAL_MASK 0x2000 12947 #define PHY84328_DEV7_MISC3_CL49_ED66_EN_VAL_ALIGN 0 12948 #define PHY84328_DEV7_MISC3_CL49_ED66_EN_VAL_BITS 1 12949 #define PHY84328_DEV7_MISC3_CL49_ED66_EN_VAL_SHIFT 13 12950 12951 /* ln_device7 :: Misc3 :: fifo_fsm_cya [12:12] */ 12952 #define PHY84328_DEV7_MISC3_FIFO_FSM_CYA_MASK 0x1000 12953 #define PHY84328_DEV7_MISC3_FIFO_FSM_CYA_ALIGN 0 12954 #define PHY84328_DEV7_MISC3_FIFO_FSM_CYA_BITS 1 12955 #define PHY84328_DEV7_MISC3_FIFO_FSM_CYA_SHIFT 12 12956 12957 /* ln_device7 :: Misc3 :: rxck_mii_override_val [11:11] */ 12958 #define PHY84328_DEV7_MISC3_RXCK_MII_OVERRIDE_VAL_MASK 0x0800 12959 #define PHY84328_DEV7_MISC3_RXCK_MII_OVERRIDE_VAL_ALIGN 0 12960 #define PHY84328_DEV7_MISC3_RXCK_MII_OVERRIDE_VAL_BITS 1 12961 #define PHY84328_DEV7_MISC3_RXCK_MII_OVERRIDE_VAL_SHIFT 11 12962 12963 /* ln_device7 :: Misc3 :: rxck_mii_override [10:10] */ 12964 #define PHY84328_DEV7_MISC3_RXCK_MII_OVERRIDE_MASK 0x0400 12965 #define PHY84328_DEV7_MISC3_RXCK_MII_OVERRIDE_ALIGN 0 12966 #define PHY84328_DEV7_MISC3_RXCK_MII_OVERRIDE_BITS 1 12967 #define PHY84328_DEV7_MISC3_RXCK_MII_OVERRIDE_SHIFT 10 12968 12969 /* ln_device7 :: Misc3 :: fifo_ipg_cya [09:09] */ 12970 #define PHY84328_DEV7_MISC3_FIFO_IPG_CYA_MASK 0x0200 12971 #define PHY84328_DEV7_MISC3_FIFO_IPG_CYA_ALIGN 0 12972 #define PHY84328_DEV7_MISC3_FIFO_IPG_CYA_BITS 1 12973 #define PHY84328_DEV7_MISC3_FIFO_IPG_CYA_SHIFT 9 12974 12975 /* ln_device7 :: Misc3 :: scr_en_per_lane [08:08] */ 12976 #define PHY84328_DEV7_MISC3_SCR_EN_PER_LANE_MASK 0x0100 12977 #define PHY84328_DEV7_MISC3_SCR_EN_PER_LANE_ALIGN 0 12978 #define PHY84328_DEV7_MISC3_SCR_EN_PER_LANE_BITS 1 12979 #define PHY84328_DEV7_MISC3_SCR_EN_PER_LANE_SHIFT 8 12980 12981 /* ln_device7 :: Misc3 :: force_speed_b5 [07:07] */ 12982 #define PHY84328_DEV7_MISC3_FORCE_SPEED_B5_MASK 0x0080 12983 #define PHY84328_DEV7_MISC3_FORCE_SPEED_B5_ALIGN 0 12984 #define PHY84328_DEV7_MISC3_FORCE_SPEED_B5_BITS 1 12985 #define PHY84328_DEV7_MISC3_FORCE_SPEED_B5_SHIFT 7 12986 12987 /* ln_device7 :: Misc3 :: laneDisable [06:06] */ 12988 #define PHY84328_DEV7_MISC3_LANEDISABLE_MASK 0x0040 12989 #define PHY84328_DEV7_MISC3_LANEDISABLE_ALIGN 0 12990 #define PHY84328_DEV7_MISC3_LANEDISABLE_BITS 1 12991 #define PHY84328_DEV7_MISC3_LANEDISABLE_SHIFT 6 12992 12993 /* ln_device7 :: Misc3 :: fifo_err_cya2 [05:05] */ 12994 #define PHY84328_DEV7_MISC3_FIFO_ERR_CYA2_MASK 0x0020 12995 #define PHY84328_DEV7_MISC3_FIFO_ERR_CYA2_ALIGN 0 12996 #define PHY84328_DEV7_MISC3_FIFO_ERR_CYA2_BITS 1 12997 #define PHY84328_DEV7_MISC3_FIFO_ERR_CYA2_SHIFT 5 12998 12999 /* ln_device7 :: Misc3 :: disable_pcs_tx_r [04:04] */ 13000 #define PHY84328_DEV7_MISC3_DISABLE_PCS_TX_R_MASK 0x0010 13001 #define PHY84328_DEV7_MISC3_DISABLE_PCS_TX_R_ALIGN 0 13002 #define PHY84328_DEV7_MISC3_DISABLE_PCS_TX_R_BITS 1 13003 #define PHY84328_DEV7_MISC3_DISABLE_PCS_TX_R_SHIFT 4 13004 13005 /* ln_device7 :: Misc3 :: disable_pcs_tx_force_r [03:03] */ 13006 #define PHY84328_DEV7_MISC3_DISABLE_PCS_TX_FORCE_R_MASK 0x0008 13007 #define PHY84328_DEV7_MISC3_DISABLE_PCS_TX_FORCE_R_ALIGN 0 13008 #define PHY84328_DEV7_MISC3_DISABLE_PCS_TX_FORCE_R_BITS 1 13009 #define PHY84328_DEV7_MISC3_DISABLE_PCS_TX_FORCE_R_SHIFT 3 13010 13011 /* ln_device7 :: Misc3 :: tbi_mode_force_r [02:02] */ 13012 #define PHY84328_DEV7_MISC3_TBI_MODE_FORCE_R_MASK 0x0004 13013 #define PHY84328_DEV7_MISC3_TBI_MODE_FORCE_R_ALIGN 0 13014 #define PHY84328_DEV7_MISC3_TBI_MODE_FORCE_R_BITS 1 13015 #define PHY84328_DEV7_MISC3_TBI_MODE_FORCE_R_SHIFT 2 13016 13017 /* ln_device7 :: Misc3 :: rxSigdetPwrdn_override_val [01:01] */ 13018 #define PHY84328_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_MASK 0x0002 13019 #define PHY84328_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_ALIGN 0 13020 #define PHY84328_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_BITS 1 13021 #define PHY84328_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_SHIFT 1 13022 13023 /* ln_device7 :: Misc3 :: rxSigdetPwrdn_override [00:00] */ 13024 #define PHY84328_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_MASK 0x0001 13025 #define PHY84328_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_ALIGN 0 13026 #define PHY84328_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_BITS 1 13027 #define PHY84328_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_SHIFT 0 13028 13029 13030 /**************************************************************************** 13031 * ln_device7 :: Misc4 13032 */ 13033 /* ln_device7 :: Misc4 :: reserved0 [15:15] */ 13034 #define PHY84328_DEV7_MISC4_RESERVED0_MASK 0x8000 13035 #define PHY84328_DEV7_MISC4_RESERVED0_ALIGN 0 13036 #define PHY84328_DEV7_MISC4_RESERVED0_BITS 1 13037 #define PHY84328_DEV7_MISC4_RESERVED0_SHIFT 15 13038 13039 /* ln_device7 :: Misc4 :: scr_en_over [14:14] */ 13040 #define PHY84328_DEV7_MISC4_SCR_EN_OVER_MASK 0x4000 13041 #define PHY84328_DEV7_MISC4_SCR_EN_OVER_ALIGN 0 13042 #define PHY84328_DEV7_MISC4_SCR_EN_OVER_BITS 1 13043 #define PHY84328_DEV7_MISC4_SCR_EN_OVER_SHIFT 14 13044 13045 /* ln_device7 :: Misc4 :: div33_clk_use_cya [13:13] */ 13046 #define PHY84328_DEV7_MISC4_DIV33_CLK_USE_CYA_MASK 0x2000 13047 #define PHY84328_DEV7_MISC4_DIV33_CLK_USE_CYA_ALIGN 0 13048 #define PHY84328_DEV7_MISC4_DIV33_CLK_USE_CYA_BITS 1 13049 #define PHY84328_DEV7_MISC4_DIV33_CLK_USE_CYA_SHIFT 13 13050 13051 /* ln_device7 :: Misc4 :: os3_en_val [12:12] */ 13052 #define PHY84328_DEV7_MISC4_OS3_EN_VAL_MASK 0x1000 13053 #define PHY84328_DEV7_MISC4_OS3_EN_VAL_ALIGN 0 13054 #define PHY84328_DEV7_MISC4_OS3_EN_VAL_BITS 1 13055 #define PHY84328_DEV7_MISC4_OS3_EN_VAL_SHIFT 12 13056 13057 /* ln_device7 :: Misc4 :: os3_en_override [11:11] */ 13058 #define PHY84328_DEV7_MISC4_OS3_EN_OVERRIDE_MASK 0x0800 13059 #define PHY84328_DEV7_MISC4_OS3_EN_OVERRIDE_ALIGN 0 13060 #define PHY84328_DEV7_MISC4_OS3_EN_OVERRIDE_BITS 1 13061 #define PHY84328_DEV7_MISC4_OS3_EN_OVERRIDE_SHIFT 11 13062 13063 /* ln_device7 :: Misc4 :: decouple_actual_speed [10:10] */ 13064 #define PHY84328_DEV7_MISC4_DECOUPLE_ACTUAL_SPEED_MASK 0x0400 13065 #define PHY84328_DEV7_MISC4_DECOUPLE_ACTUAL_SPEED_ALIGN 0 13066 #define PHY84328_DEV7_MISC4_DECOUPLE_ACTUAL_SPEED_BITS 1 13067 #define PHY84328_DEV7_MISC4_DECOUPLE_ACTUAL_SPEED_SHIFT 10 13068 13069 /* ln_device7 :: Misc4 :: fx_mode_rx_pre [09:09] */ 13070 #define PHY84328_DEV7_MISC4_FX_MODE_RX_PRE_MASK 0x0200 13071 #define PHY84328_DEV7_MISC4_FX_MODE_RX_PRE_ALIGN 0 13072 #define PHY84328_DEV7_MISC4_FX_MODE_RX_PRE_BITS 1 13073 #define PHY84328_DEV7_MISC4_FX_MODE_RX_PRE_SHIFT 9 13074 13075 /* ln_device7 :: Misc4 :: fiber_select_rx_pre [08:08] */ 13076 #define PHY84328_DEV7_MISC4_FIBER_SELECT_RX_PRE_MASK 0x0100 13077 #define PHY84328_DEV7_MISC4_FIBER_SELECT_RX_PRE_ALIGN 0 13078 #define PHY84328_DEV7_MISC4_FIBER_SELECT_RX_PRE_BITS 1 13079 #define PHY84328_DEV7_MISC4_FIBER_SELECT_RX_PRE_SHIFT 8 13080 13081 /* ln_device7 :: Misc4 :: force_speed_rx_pre [07:02] */ 13082 #define PHY84328_DEV7_MISC4_FORCE_SPEED_RX_PRE_MASK 0x00fc 13083 #define PHY84328_DEV7_MISC4_FORCE_SPEED_RX_PRE_ALIGN 0 13084 #define PHY84328_DEV7_MISC4_FORCE_SPEED_RX_PRE_BITS 6 13085 #define PHY84328_DEV7_MISC4_FORCE_SPEED_RX_PRE_SHIFT 2 13086 13087 /* ln_device7 :: Misc4 :: reg0_forced_speed_rx_pre [01:00] */ 13088 #define PHY84328_DEV7_MISC4_REG0_FORCED_SPEED_RX_PRE_MASK 0x0003 13089 #define PHY84328_DEV7_MISC4_REG0_FORCED_SPEED_RX_PRE_ALIGN 0 13090 #define PHY84328_DEV7_MISC4_REG0_FORCED_SPEED_RX_PRE_BITS 2 13091 #define PHY84328_DEV7_MISC4_REG0_FORCED_SPEED_RX_PRE_SHIFT 0 13092 13093 13094 /**************************************************************************** 13095 * ln_device7 :: Misc5 13096 */ 13097 /* ln_device7 :: Misc5 :: LPI_en_rx [15:15] */ 13098 #define PHY84328_DEV7_MISC5_LPI_EN_RX_MASK 0x8000 13099 #define PHY84328_DEV7_MISC5_LPI_EN_RX_ALIGN 0 13100 #define PHY84328_DEV7_MISC5_LPI_EN_RX_BITS 1 13101 #define PHY84328_DEV7_MISC5_LPI_EN_RX_SHIFT 15 13102 13103 /* ln_device7 :: Misc5 :: LPI_en_tx [14:14] */ 13104 #define PHY84328_DEV7_MISC5_LPI_EN_TX_MASK 0x4000 13105 #define PHY84328_DEV7_MISC5_LPI_EN_TX_ALIGN 0 13106 #define PHY84328_DEV7_MISC5_LPI_EN_TX_BITS 1 13107 #define PHY84328_DEV7_MISC5_LPI_EN_TX_SHIFT 14 13108 13109 /* ln_device7 :: Misc5 :: tgen_data_sel [13:13] */ 13110 #define PHY84328_DEV7_MISC5_TGEN_DATA_SEL_MASK 0x2000 13111 #define PHY84328_DEV7_MISC5_TGEN_DATA_SEL_ALIGN 0 13112 #define PHY84328_DEV7_MISC5_TGEN_DATA_SEL_BITS 1 13113 #define PHY84328_DEV7_MISC5_TGEN_DATA_SEL_SHIFT 13 13114 13115 /* ln_device7 :: Misc5 :: tgen_cx4 [12:12] */ 13116 #define PHY84328_DEV7_MISC5_TGEN_CX4_MASK 0x1000 13117 #define PHY84328_DEV7_MISC5_TGEN_CX4_ALIGN 0 13118 #define PHY84328_DEV7_MISC5_TGEN_CX4_BITS 1 13119 #define PHY84328_DEV7_MISC5_TGEN_CX4_SHIFT 12 13120 13121 /* ln_device7 :: Misc5 :: tgen_link [11:11] */ 13122 #define PHY84328_DEV7_MISC5_TGEN_LINK_MASK 0x0800 13123 #define PHY84328_DEV7_MISC5_TGEN_LINK_ALIGN 0 13124 #define PHY84328_DEV7_MISC5_TGEN_LINK_BITS 1 13125 #define PHY84328_DEV7_MISC5_TGEN_LINK_SHIFT 11 13126 13127 /* ln_device7 :: Misc5 :: tgen_tmsel [10:08] */ 13128 #define PHY84328_DEV7_MISC5_TGEN_TMSEL_MASK 0x0700 13129 #define PHY84328_DEV7_MISC5_TGEN_TMSEL_ALIGN 0 13130 #define PHY84328_DEV7_MISC5_TGEN_TMSEL_BITS 3 13131 #define PHY84328_DEV7_MISC5_TGEN_TMSEL_SHIFT 8 13132 13133 /* ln_device7 :: Misc5 :: reserved0 [07:04] */ 13134 #define PHY84328_DEV7_MISC5_RESERVED0_MASK 0x00f0 13135 #define PHY84328_DEV7_MISC5_RESERVED0_ALIGN 0 13136 #define PHY84328_DEV7_MISC5_RESERVED0_BITS 4 13137 #define PHY84328_DEV7_MISC5_RESERVED0_SHIFT 4 13138 13139 /* ln_device7 :: Misc5 :: rchk_en [03:03] */ 13140 #define PHY84328_DEV7_MISC5_RCHK_EN_MASK 0x0008 13141 #define PHY84328_DEV7_MISC5_RCHK_EN_ALIGN 0 13142 #define PHY84328_DEV7_MISC5_RCHK_EN_BITS 1 13143 #define PHY84328_DEV7_MISC5_RCHK_EN_SHIFT 3 13144 13145 /* ln_device7 :: Misc5 :: rchk_tmsel [02:00] */ 13146 #define PHY84328_DEV7_MISC5_RCHK_TMSEL_MASK 0x0007 13147 #define PHY84328_DEV7_MISC5_RCHK_TMSEL_ALIGN 0 13148 #define PHY84328_DEV7_MISC5_RCHK_TMSEL_BITS 3 13149 #define PHY84328_DEV7_MISC5_RCHK_TMSEL_SHIFT 0 13150 13151 13152 /**************************************************************************** 13153 * ln_device7 :: linkcnt_cl72_msb 13154 */ 13155 /* ln_device7 :: linkcnt_cl72_msb :: reserved_for_eco0 [15:08] */ 13156 #define PHY84328_DEV7_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_MASK 0xff00 13157 #define PHY84328_DEV7_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_ALIGN 0 13158 #define PHY84328_DEV7_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_BITS 8 13159 #define PHY84328_DEV7_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_SHIFT 8 13160 13161 /* ln_device7 :: linkcnt_cl72_msb :: link_cnt_cl72_msbB [07:00] */ 13162 #define PHY84328_DEV7_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_MASK 0x00ff 13163 #define PHY84328_DEV7_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_ALIGN 0 13164 #define PHY84328_DEV7_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_BITS 8 13165 #define PHY84328_DEV7_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_SHIFT 0 13166 13167 13168 /**************************************************************************** 13169 * ln_device7 :: linkcnt_cl72_lsb 13170 */ 13171 /* ln_device7 :: linkcnt_cl72_lsb :: link_cnt_cl72_lsbB [15:00] */ 13172 #define PHY84328_DEV7_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_MASK 0xffff 13173 #define PHY84328_DEV7_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_ALIGN 0 13174 #define PHY84328_DEV7_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_BITS 16 13175 #define PHY84328_DEV7_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_SHIFT 0 13176 13177 13178 /**************************************************************************** 13179 * ln_device7 :: LP_UP4 13180 */ 13181 /* ln_device7 :: LP_UP4 :: reserved0 [15:11] */ 13182 #define PHY84328_DEV7_LP_UP4_RESERVED0_MASK 0xf800 13183 #define PHY84328_DEV7_LP_UP4_RESERVED0_ALIGN 0 13184 #define PHY84328_DEV7_LP_UP4_RESERVED0_BITS 5 13185 #define PHY84328_DEV7_LP_UP4_RESERVED0_SHIFT 11 13186 13187 /* ln_device7 :: LP_UP4 :: last [10:10] */ 13188 #define PHY84328_DEV7_LP_UP4_LAST_MASK 0x0400 13189 #define PHY84328_DEV7_LP_UP4_LAST_ALIGN 0 13190 #define PHY84328_DEV7_LP_UP4_LAST_BITS 1 13191 #define PHY84328_DEV7_LP_UP4_LAST_SHIFT 10 13192 13193 /* ln_device7 :: LP_UP4 :: dataRate_1GCX1 [09:09] */ 13194 #define PHY84328_DEV7_LP_UP4_DATARATE_1GCX1_MASK 0x0200 13195 #define PHY84328_DEV7_LP_UP4_DATARATE_1GCX1_ALIGN 0 13196 #define PHY84328_DEV7_LP_UP4_DATARATE_1GCX1_BITS 1 13197 #define PHY84328_DEV7_LP_UP4_DATARATE_1GCX1_SHIFT 9 13198 13199 /* ln_device7 :: LP_UP4 :: dataRate_10GCX1 [08:08] */ 13200 #define PHY84328_DEV7_LP_UP4_DATARATE_10GCX1_MASK 0x0100 13201 #define PHY84328_DEV7_LP_UP4_DATARATE_10GCX1_ALIGN 0 13202 #define PHY84328_DEV7_LP_UP4_DATARATE_10GCX1_BITS 1 13203 #define PHY84328_DEV7_LP_UP4_DATARATE_10GCX1_SHIFT 8 13204 13205 /* ln_device7 :: LP_UP4 :: dataRate_15p75G_dxgxs [07:07] */ 13206 #define PHY84328_DEV7_LP_UP4_DATARATE_15P75G_DXGXS_MASK 0x0080 13207 #define PHY84328_DEV7_LP_UP4_DATARATE_15P75G_DXGXS_ALIGN 0 13208 #define PHY84328_DEV7_LP_UP4_DATARATE_15P75G_DXGXS_BITS 1 13209 #define PHY84328_DEV7_LP_UP4_DATARATE_15P75G_DXGXS_SHIFT 7 13210 13211 /* ln_device7 :: LP_UP4 :: dataRate_20G_dxgxs [06:06] */ 13212 #define PHY84328_DEV7_LP_UP4_DATARATE_20G_DXGXS_MASK 0x0040 13213 #define PHY84328_DEV7_LP_UP4_DATARATE_20G_DXGXS_ALIGN 0 13214 #define PHY84328_DEV7_LP_UP4_DATARATE_20G_DXGXS_BITS 1 13215 #define PHY84328_DEV7_LP_UP4_DATARATE_20G_DXGXS_SHIFT 6 13216 13217 /* ln_device7 :: LP_UP4 :: dataRate_20Gh_dxgxs [05:05] */ 13218 #define PHY84328_DEV7_LP_UP4_DATARATE_20GH_DXGXS_MASK 0x0020 13219 #define PHY84328_DEV7_LP_UP4_DATARATE_20GH_DXGXS_ALIGN 0 13220 #define PHY84328_DEV7_LP_UP4_DATARATE_20GH_DXGXS_BITS 1 13221 #define PHY84328_DEV7_LP_UP4_DATARATE_20GH_DXGXS_SHIFT 5 13222 13223 /* ln_device7 :: LP_UP4 :: dataRate_12p7G_dxgxs [04:04] */ 13224 #define PHY84328_DEV7_LP_UP4_DATARATE_12P7G_DXGXS_MASK 0x0010 13225 #define PHY84328_DEV7_LP_UP4_DATARATE_12P7G_DXGXS_ALIGN 0 13226 #define PHY84328_DEV7_LP_UP4_DATARATE_12P7G_DXGXS_BITS 1 13227 #define PHY84328_DEV7_LP_UP4_DATARATE_12P7G_DXGXS_SHIFT 4 13228 13229 /* ln_device7 :: LP_UP4 :: dataRate_10p5G_dxgxs [03:03] */ 13230 #define PHY84328_DEV7_LP_UP4_DATARATE_10P5G_DXGXS_MASK 0x0008 13231 #define PHY84328_DEV7_LP_UP4_DATARATE_10P5G_DXGXS_ALIGN 0 13232 #define PHY84328_DEV7_LP_UP4_DATARATE_10P5G_DXGXS_BITS 1 13233 #define PHY84328_DEV7_LP_UP4_DATARATE_10P5G_DXGXS_SHIFT 3 13234 13235 /* ln_device7 :: LP_UP4 :: dataRate_10G_dxgxs [02:02] */ 13236 #define PHY84328_DEV7_LP_UP4_DATARATE_10G_DXGXS_MASK 0x0004 13237 #define PHY84328_DEV7_LP_UP4_DATARATE_10G_DXGXS_ALIGN 0 13238 #define PHY84328_DEV7_LP_UP4_DATARATE_10G_DXGXS_BITS 1 13239 #define PHY84328_DEV7_LP_UP4_DATARATE_10G_DXGXS_SHIFT 2 13240 13241 /* ln_device7 :: LP_UP4 :: dataRate_10Gh_dxgxs [01:01] */ 13242 #define PHY84328_DEV7_LP_UP4_DATARATE_10GH_DXGXS_MASK 0x0002 13243 #define PHY84328_DEV7_LP_UP4_DATARATE_10GH_DXGXS_ALIGN 0 13244 #define PHY84328_DEV7_LP_UP4_DATARATE_10GH_DXGXS_BITS 1 13245 #define PHY84328_DEV7_LP_UP4_DATARATE_10GH_DXGXS_SHIFT 1 13246 13247 /* ln_device7 :: LP_UP4 :: dataRate_20G [00:00] */ 13248 #define PHY84328_DEV7_LP_UP4_DATARATE_20G_MASK 0x0001 13249 #define PHY84328_DEV7_LP_UP4_DATARATE_20G_ALIGN 0 13250 #define PHY84328_DEV7_LP_UP4_DATARATE_20G_BITS 1 13251 #define PHY84328_DEV7_LP_UP4_DATARATE_20G_SHIFT 0 13252 13253 13254 /**************************************************************************** 13255 * ln_device7 :: LP_UP5 13256 */ 13257 /* ln_device7 :: LP_UP5 :: reserved0 [15:11] */ 13258 #define PHY84328_DEV7_LP_UP5_RESERVED0_MASK 0xf800 13259 #define PHY84328_DEV7_LP_UP5_RESERVED0_ALIGN 0 13260 #define PHY84328_DEV7_LP_UP5_RESERVED0_BITS 5 13261 #define PHY84328_DEV7_LP_UP5_RESERVED0_SHIFT 11 13262 13263 /* ln_device7 :: LP_UP5 :: last [10:10] */ 13264 #define PHY84328_DEV7_LP_UP5_LAST_MASK 0x0400 13265 #define PHY84328_DEV7_LP_UP5_LAST_ALIGN 0 13266 #define PHY84328_DEV7_LP_UP5_LAST_BITS 1 13267 #define PHY84328_DEV7_LP_UP5_LAST_SHIFT 10 13268 13269 /* ln_device7 :: LP_UP5 :: reserved1 [09:00] */ 13270 #define PHY84328_DEV7_LP_UP5_RESERVED1_MASK 0x03ff 13271 #define PHY84328_DEV7_LP_UP5_RESERVED1_ALIGN 0 13272 #define PHY84328_DEV7_LP_UP5_RESERVED1_BITS 10 13273 #define PHY84328_DEV7_LP_UP5_RESERVED1_SHIFT 0 13274 13275 13276 /**************************************************************************** 13277 * ln_device7 :: Misc6 13278 */ 13279 /* ln_device7 :: Misc6 :: reset_rx_asic [15:15] */ 13280 #define PHY84328_DEV7_MISC6_RESET_RX_ASIC_MASK 0x8000 13281 #define PHY84328_DEV7_MISC6_RESET_RX_ASIC_ALIGN 0 13282 #define PHY84328_DEV7_MISC6_RESET_RX_ASIC_BITS 1 13283 #define PHY84328_DEV7_MISC6_RESET_RX_ASIC_SHIFT 15 13284 13285 /* ln_device7 :: Misc6 :: reset_tx_asic [14:14] */ 13286 #define PHY84328_DEV7_MISC6_RESET_TX_ASIC_MASK 0x4000 13287 #define PHY84328_DEV7_MISC6_RESET_TX_ASIC_ALIGN 0 13288 #define PHY84328_DEV7_MISC6_RESET_TX_ASIC_BITS 1 13289 #define PHY84328_DEV7_MISC6_RESET_TX_ASIC_SHIFT 14 13290 13291 /* ln_device7 :: Misc6 :: reserved0 [13:09] */ 13292 #define PHY84328_DEV7_MISC6_RESERVED0_MASK 0x3e00 13293 #define PHY84328_DEV7_MISC6_RESERVED0_ALIGN 0 13294 #define PHY84328_DEV7_MISC6_RESERVED0_BITS 5 13295 #define PHY84328_DEV7_MISC6_RESERVED0_SHIFT 9 13296 13297 /* ln_device7 :: Misc6 :: rx_os8_frst_SM [08:08] */ 13298 #define PHY84328_DEV7_MISC6_RX_OS8_FRST_SM_MASK 0x0100 13299 #define PHY84328_DEV7_MISC6_RX_OS8_FRST_SM_ALIGN 0 13300 #define PHY84328_DEV7_MISC6_RX_OS8_FRST_SM_BITS 1 13301 #define PHY84328_DEV7_MISC6_RX_OS8_FRST_SM_SHIFT 8 13302 13303 /* ln_device7 :: Misc6 :: use_brcm6466_31500_cya [07:07] */ 13304 #define PHY84328_DEV7_MISC6_USE_BRCM6466_31500_CYA_MASK 0x0080 13305 #define PHY84328_DEV7_MISC6_USE_BRCM6466_31500_CYA_ALIGN 0 13306 #define PHY84328_DEV7_MISC6_USE_BRCM6466_31500_CYA_BITS 1 13307 #define PHY84328_DEV7_MISC6_USE_BRCM6466_31500_CYA_SHIFT 7 13308 13309 /* ln_device7 :: Misc6 :: cx4_sigdet_filt_all_speed [06:06] */ 13310 #define PHY84328_DEV7_MISC6_CX4_SIGDET_FILT_ALL_SPEED_MASK 0x0040 13311 #define PHY84328_DEV7_MISC6_CX4_SIGDET_FILT_ALL_SPEED_ALIGN 0 13312 #define PHY84328_DEV7_MISC6_CX4_SIGDET_FILT_ALL_SPEED_BITS 1 13313 #define PHY84328_DEV7_MISC6_CX4_SIGDET_FILT_ALL_SPEED_SHIFT 6 13314 13315 /* ln_device7 :: Misc6 :: pcs_type_sel_1000x_cya [05:05] */ 13316 #define PHY84328_DEV7_MISC6_PCS_TYPE_SEL_1000X_CYA_MASK 0x0020 13317 #define PHY84328_DEV7_MISC6_PCS_TYPE_SEL_1000X_CYA_ALIGN 0 13318 #define PHY84328_DEV7_MISC6_PCS_TYPE_SEL_1000X_CYA_BITS 1 13319 #define PHY84328_DEV7_MISC6_PCS_TYPE_SEL_1000X_CYA_SHIFT 5 13320 13321 /* ln_device7 :: Misc6 :: rx_os8_os3_alt_bits_cya [04:04] */ 13322 #define PHY84328_DEV7_MISC6_RX_OS8_OS3_ALT_BITS_CYA_MASK 0x0010 13323 #define PHY84328_DEV7_MISC6_RX_OS8_OS3_ALT_BITS_CYA_ALIGN 0 13324 #define PHY84328_DEV7_MISC6_RX_OS8_OS3_ALT_BITS_CYA_BITS 1 13325 #define PHY84328_DEV7_MISC6_RX_OS8_OS3_ALT_BITS_CYA_SHIFT 4 13326 13327 /* ln_device7 :: Misc6 :: reserved1 [03:02] */ 13328 #define PHY84328_DEV7_MISC6_RESERVED1_MASK 0x000c 13329 #define PHY84328_DEV7_MISC6_RESERVED1_ALIGN 0 13330 #define PHY84328_DEV7_MISC6_RESERVED1_BITS 2 13331 #define PHY84328_DEV7_MISC6_RESERVED1_SHIFT 2 13332 13333 /* ln_device7 :: Misc6 :: tx_os8_afrst_en [01:01] */ 13334 #define PHY84328_DEV7_MISC6_TX_OS8_AFRST_EN_MASK 0x0002 13335 #define PHY84328_DEV7_MISC6_TX_OS8_AFRST_EN_ALIGN 0 13336 #define PHY84328_DEV7_MISC6_TX_OS8_AFRST_EN_BITS 1 13337 #define PHY84328_DEV7_MISC6_TX_OS8_AFRST_EN_SHIFT 1 13338 13339 /* ln_device7 :: Misc6 :: tx_os8_frst_SM [00:00] */ 13340 #define PHY84328_DEV7_MISC6_TX_OS8_FRST_SM_MASK 0x0001 13341 #define PHY84328_DEV7_MISC6_TX_OS8_FRST_SM_ALIGN 0 13342 #define PHY84328_DEV7_MISC6_TX_OS8_FRST_SM_BITS 1 13343 #define PHY84328_DEV7_MISC6_TX_OS8_FRST_SM_SHIFT 0 13344 13345 13346 /**************************************************************************** 13347 * ln_device7 :: Misc7 13348 */ 13349 /* ln_device7 :: Misc7 :: reserved0 [15:14] */ 13350 #define PHY84328_DEV7_MISC7_RESERVED0_MASK 0xc000 13351 #define PHY84328_DEV7_MISC7_RESERVED0_ALIGN 0 13352 #define PHY84328_DEV7_MISC7_RESERVED0_BITS 2 13353 #define PHY84328_DEV7_MISC7_RESERVED0_SHIFT 14 13354 13355 /* ln_device7 :: Misc7 :: force_oscdr_mode_val [13:10] */ 13356 #define PHY84328_DEV7_MISC7_FORCE_OSCDR_MODE_VAL_MASK 0x3c00 13357 #define PHY84328_DEV7_MISC7_FORCE_OSCDR_MODE_VAL_ALIGN 0 13358 #define PHY84328_DEV7_MISC7_FORCE_OSCDR_MODE_VAL_BITS 4 13359 #define PHY84328_DEV7_MISC7_FORCE_OSCDR_MODE_VAL_SHIFT 10 13360 13361 /* ln_device7 :: Misc7 :: force_oscdr_mode_en [09:09] */ 13362 #define PHY84328_DEV7_MISC7_FORCE_OSCDR_MODE_EN_MASK 0x0200 13363 #define PHY84328_DEV7_MISC7_FORCE_OSCDR_MODE_EN_ALIGN 0 13364 #define PHY84328_DEV7_MISC7_FORCE_OSCDR_MODE_EN_BITS 1 13365 #define PHY84328_DEV7_MISC7_FORCE_OSCDR_MODE_EN_SHIFT 9 13366 13367 /* ln_device7 :: Misc7 :: reserved1 [08:08] */ 13368 #define PHY84328_DEV7_MISC7_RESERVED1_MASK 0x0100 13369 #define PHY84328_DEV7_MISC7_RESERVED1_ALIGN 0 13370 #define PHY84328_DEV7_MISC7_RESERVED1_BITS 1 13371 #define PHY84328_DEV7_MISC7_RESERVED1_SHIFT 8 13372 13373 /* ln_device7 :: Misc7 :: force_speed_rx_pre_7_6 [07:06] */ 13374 #define PHY84328_DEV7_MISC7_FORCE_SPEED_RX_PRE_7_6_MASK 0x00c0 13375 #define PHY84328_DEV7_MISC7_FORCE_SPEED_RX_PRE_7_6_ALIGN 0 13376 #define PHY84328_DEV7_MISC7_FORCE_SPEED_RX_PRE_7_6_BITS 2 13377 #define PHY84328_DEV7_MISC7_FORCE_SPEED_RX_PRE_7_6_SHIFT 6 13378 13379 /* ln_device7 :: Misc7 :: brcm6466_cl49_in_all_mode_cya [05:05] */ 13380 #define PHY84328_DEV7_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_MASK 0x0020 13381 #define PHY84328_DEV7_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_ALIGN 0 13382 #define PHY84328_DEV7_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_BITS 1 13383 #define PHY84328_DEV7_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_SHIFT 5 13384 13385 /* ln_device7 :: Misc7 :: xfi_txfault_pll_cya [04:04] */ 13386 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_PLL_CYA_MASK 0x0010 13387 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_PLL_CYA_ALIGN 0 13388 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_PLL_CYA_BITS 1 13389 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_PLL_CYA_SHIFT 4 13390 13391 /* ln_device7 :: Misc7 :: xfi_txfault_ext_cya [03:03] */ 13392 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_EXT_CYA_MASK 0x0008 13393 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_EXT_CYA_ALIGN 0 13394 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_EXT_CYA_BITS 1 13395 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_EXT_CYA_SHIFT 3 13396 13397 /* ln_device7 :: Misc7 :: xfi_txfault_det_cya [02:02] */ 13398 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_DET_CYA_MASK 0x0004 13399 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_DET_CYA_ALIGN 0 13400 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_DET_CYA_BITS 1 13401 #define PHY84328_DEV7_MISC7_XFI_TXFAULT_DET_CYA_SHIFT 2 13402 13403 /* ln_device7 :: Misc7 :: xfi_rxfault_link_cya [01:01] */ 13404 #define PHY84328_DEV7_MISC7_XFI_RXFAULT_LINK_CYA_MASK 0x0002 13405 #define PHY84328_DEV7_MISC7_XFI_RXFAULT_LINK_CYA_ALIGN 0 13406 #define PHY84328_DEV7_MISC7_XFI_RXFAULT_LINK_CYA_BITS 1 13407 #define PHY84328_DEV7_MISC7_XFI_RXFAULT_LINK_CYA_SHIFT 1 13408 13409 /* ln_device7 :: Misc7 :: xfi_rxfault_det_cya [00:00] */ 13410 #define PHY84328_DEV7_MISC7_XFI_RXFAULT_DET_CYA_MASK 0x0001 13411 #define PHY84328_DEV7_MISC7_XFI_RXFAULT_DET_CYA_ALIGN 0 13412 #define PHY84328_DEV7_MISC7_XFI_RXFAULT_DET_CYA_BITS 1 13413 #define PHY84328_DEV7_MISC7_XFI_RXFAULT_DET_CYA_SHIFT 0 13414 13415 13416 /**************************************************************************** 13417 * ln_device7 :: Misc8 13418 */ 13419 /* ln_device7 :: Misc8 :: reserved0 [15:05] */ 13420 #define PHY84328_DEV7_MISC8_RESERVED0_MASK 0xffe0 13421 #define PHY84328_DEV7_MISC8_RESERVED0_ALIGN 0 13422 #define PHY84328_DEV7_MISC8_RESERVED0_BITS 11 13423 #define PHY84328_DEV7_MISC8_RESERVED0_SHIFT 5 13424 13425 /* ln_device7 :: Misc8 :: force_oscdr_mode_en_rx [04:04] */ 13426 #define PHY84328_DEV7_MISC8_FORCE_OSCDR_MODE_EN_RX_MASK 0x0010 13427 #define PHY84328_DEV7_MISC8_FORCE_OSCDR_MODE_EN_RX_ALIGN 0 13428 #define PHY84328_DEV7_MISC8_FORCE_OSCDR_MODE_EN_RX_BITS 1 13429 #define PHY84328_DEV7_MISC8_FORCE_OSCDR_MODE_EN_RX_SHIFT 4 13430 13431 /* ln_device7 :: Misc8 :: force_oscdr_mode_val [03:00] */ 13432 #define PHY84328_DEV7_MISC8_FORCE_OSCDR_MODE_VAL_MASK 0x000f 13433 #define PHY84328_DEV7_MISC8_FORCE_OSCDR_MODE_VAL_ALIGN 0 13434 #define PHY84328_DEV7_MISC8_FORCE_OSCDR_MODE_VAL_BITS 4 13435 #define PHY84328_DEV7_MISC8_FORCE_OSCDR_MODE_VAL_SHIFT 0 13436 13437 13438 /**************************************************************************** 13439 * ln_device7 :: link_status 13440 */ 13441 /* ln_device7 :: link_status :: reserved0 [15:06] */ 13442 #define PHY84328_DEV7_LINK_STATUS_RESERVED0_MASK 0xffc0 13443 #define PHY84328_DEV7_LINK_STATUS_RESERVED0_ALIGN 0 13444 #define PHY84328_DEV7_LINK_STATUS_RESERVED0_BITS 10 13445 #define PHY84328_DEV7_LINK_STATUS_RESERVED0_SHIFT 6 13446 13447 /* ln_device7 :: link_status :: ll_link [05:05] */ 13448 #define PHY84328_DEV7_LINK_STATUS_LL_LINK_MASK 0x0020 13449 #define PHY84328_DEV7_LINK_STATUS_LL_LINK_ALIGN 0 13450 #define PHY84328_DEV7_LINK_STATUS_LL_LINK_BITS 1 13451 #define PHY84328_DEV7_LINK_STATUS_LL_LINK_SHIFT 5 13452 13453 /* ln_device7 :: link_status :: l_an_link [04:04] */ 13454 #define PHY84328_DEV7_LINK_STATUS_L_AN_LINK_MASK 0x0010 13455 #define PHY84328_DEV7_LINK_STATUS_L_AN_LINK_ALIGN 0 13456 #define PHY84328_DEV7_LINK_STATUS_L_AN_LINK_BITS 1 13457 #define PHY84328_DEV7_LINK_STATUS_L_AN_LINK_SHIFT 4 13458 13459 /* ln_device7 :: link_status :: l_link_kr [03:03] */ 13460 #define PHY84328_DEV7_LINK_STATUS_L_LINK_KR_MASK 0x0008 13461 #define PHY84328_DEV7_LINK_STATUS_L_LINK_KR_ALIGN 0 13462 #define PHY84328_DEV7_LINK_STATUS_L_LINK_KR_BITS 1 13463 #define PHY84328_DEV7_LINK_STATUS_L_LINK_KR_SHIFT 3 13464 13465 /* ln_device7 :: link_status :: l_link10g [02:02] */ 13466 #define PHY84328_DEV7_LINK_STATUS_L_LINK10G_MASK 0x0004 13467 #define PHY84328_DEV7_LINK_STATUS_L_LINK10G_ALIGN 0 13468 #define PHY84328_DEV7_LINK_STATUS_L_LINK10G_BITS 1 13469 #define PHY84328_DEV7_LINK_STATUS_L_LINK10G_SHIFT 2 13470 13471 /* ln_device7 :: link_status :: l_link_status [01:01] */ 13472 #define PHY84328_DEV7_LINK_STATUS_L_LINK_STATUS_MASK 0x0002 13473 #define PHY84328_DEV7_LINK_STATUS_L_LINK_STATUS_ALIGN 0 13474 #define PHY84328_DEV7_LINK_STATUS_L_LINK_STATUS_BITS 1 13475 #define PHY84328_DEV7_LINK_STATUS_L_LINK_STATUS_SHIFT 1 13476 13477 /* ln_device7 :: link_status :: l_link [00:00] */ 13478 #define PHY84328_DEV7_LINK_STATUS_L_LINK_MASK 0x0001 13479 #define PHY84328_DEV7_LINK_STATUS_L_LINK_ALIGN 0 13480 #define PHY84328_DEV7_LINK_STATUS_L_LINK_BITS 1 13481 #define PHY84328_DEV7_LINK_STATUS_L_LINK_SHIFT 0 13482 13483 13484 /**************************************************************************** 13485 * ln_device7 :: actual_speed 13486 */ 13487 /* ln_device7 :: actual_speed :: reserved0 [15:14] */ 13488 #define PHY84328_DEV7_ACTUAL_SPEED_RESERVED0_MASK 0xc000 13489 #define PHY84328_DEV7_ACTUAL_SPEED_RESERVED0_ALIGN 0 13490 #define PHY84328_DEV7_ACTUAL_SPEED_RESERVED0_BITS 2 13491 #define PHY84328_DEV7_ACTUAL_SPEED_RESERVED0_SHIFT 14 13492 13493 /* ln_device7 :: actual_speed :: actual_speed_rx [13:08] */ 13494 #define PHY84328_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_RX_MASK 0x3f00 13495 #define PHY84328_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_RX_ALIGN 0 13496 #define PHY84328_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_RX_BITS 6 13497 #define PHY84328_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_RX_SHIFT 8 13498 13499 /* ln_device7 :: actual_speed :: reserved1 [07:06] */ 13500 #define PHY84328_DEV7_ACTUAL_SPEED_RESERVED1_MASK 0x00c0 13501 #define PHY84328_DEV7_ACTUAL_SPEED_RESERVED1_ALIGN 0 13502 #define PHY84328_DEV7_ACTUAL_SPEED_RESERVED1_BITS 2 13503 #define PHY84328_DEV7_ACTUAL_SPEED_RESERVED1_SHIFT 6 13504 13505 /* ln_device7 :: actual_speed :: actual_speed_tx [05:00] */ 13506 #define PHY84328_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_TX_MASK 0x003f 13507 #define PHY84328_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_TX_ALIGN 0 13508 #define PHY84328_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_TX_BITS 6 13509 #define PHY84328_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_TX_SHIFT 0 13510 13511 13512 /**************************************************************************** 13513 * ln_device7 :: mp5_NextPageCtrl 13514 */ 13515 /* ln_device7 :: mp5_NextPageCtrl :: reserved0 [15:04] */ 13516 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_RESERVED0_MASK 0xfff0 13517 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_RESERVED0_ALIGN 0 13518 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_RESERVED0_BITS 12 13519 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_RESERVED0_SHIFT 4 13520 13521 /* ln_device7 :: mp5_NextPageCtrl :: np_sw_overRide_en [03:03] */ 13522 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_MASK 0x0008 13523 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_ALIGN 0 13524 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_BITS 1 13525 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_SHIFT 3 13526 13527 /* ln_device7 :: mp5_NextPageCtrl :: teton_mode_up3_en [02:02] */ 13528 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_MASK 0x0004 13529 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_ALIGN 0 13530 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_BITS 1 13531 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_SHIFT 2 13532 13533 /* ln_device7 :: mp5_NextPageCtrl :: teton_mode [01:01] */ 13534 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_MASK 0x0002 13535 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_ALIGN 0 13536 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_BITS 1 13537 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_SHIFT 1 13538 13539 /* ln_device7 :: mp5_NextPageCtrl :: bam_mode [00:00] */ 13540 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_BAM_MODE_MASK 0x0001 13541 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_BAM_MODE_ALIGN 0 13542 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_BAM_MODE_BITS 1 13543 #define PHY84328_DEV7_MP5_NEXTPAGECTRL_BAM_MODE_SHIFT 0 13544 13545 13546 /**************************************************************************** 13547 * ln_device7 :: link_timer_offset1 13548 */ 13549 /* ln_device7 :: link_timer_offset1 :: sgmii_offset [15:08] */ 13550 #define PHY84328_DEV7_LINK_TIMER_OFFSET1_SGMII_OFFSET_MASK 0xff00 13551 #define PHY84328_DEV7_LINK_TIMER_OFFSET1_SGMII_OFFSET_ALIGN 0 13552 #define PHY84328_DEV7_LINK_TIMER_OFFSET1_SGMII_OFFSET_BITS 8 13553 #define PHY84328_DEV7_LINK_TIMER_OFFSET1_SGMII_OFFSET_SHIFT 8 13554 13555 /* ln_device7 :: link_timer_offset1 :: max_offset [07:00] */ 13556 #define PHY84328_DEV7_LINK_TIMER_OFFSET1_MAX_OFFSET_MASK 0x00ff 13557 #define PHY84328_DEV7_LINK_TIMER_OFFSET1_MAX_OFFSET_ALIGN 0 13558 #define PHY84328_DEV7_LINK_TIMER_OFFSET1_MAX_OFFSET_BITS 8 13559 #define PHY84328_DEV7_LINK_TIMER_OFFSET1_MAX_OFFSET_SHIFT 0 13560 13561 13562 /**************************************************************************** 13563 * ln_device7 :: link_timer_offset2 13564 */ 13565 /* ln_device7 :: link_timer_offset2 :: link_up_offset [15:08] */ 13566 #define PHY84328_DEV7_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_MASK 0xff00 13567 #define PHY84328_DEV7_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_ALIGN 0 13568 #define PHY84328_DEV7_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_BITS 8 13569 #define PHY84328_DEV7_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_SHIFT 8 13570 13571 /* ln_device7 :: link_timer_offset2 :: link_down_offset [07:00] */ 13572 #define PHY84328_DEV7_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_MASK 0x00ff 13573 #define PHY84328_DEV7_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_ALIGN 0 13574 #define PHY84328_DEV7_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_BITS 8 13575 #define PHY84328_DEV7_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_SHIFT 0 13576 13577 13578 /**************************************************************************** 13579 * ln_device7 :: link_timer_offset3 13580 */ 13581 /* ln_device7 :: link_timer_offset3 :: break_link_offset [15:08] */ 13582 #define PHY84328_DEV7_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_MASK 0xff00 13583 #define PHY84328_DEV7_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_ALIGN 0 13584 #define PHY84328_DEV7_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_BITS 8 13585 #define PHY84328_DEV7_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_SHIFT 8 13586 13587 /* ln_device7 :: link_timer_offset3 :: np_link_offset [07:00] */ 13588 #define PHY84328_DEV7_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_MASK 0x00ff 13589 #define PHY84328_DEV7_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_ALIGN 0 13590 #define PHY84328_DEV7_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_BITS 8 13591 #define PHY84328_DEV7_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_SHIFT 0 13592 13593 13594 /**************************************************************************** 13595 * ln_device7 :: oui_msb_field 13596 */ 13597 /* ln_device7 :: oui_msb_field :: reserved0 [15:11] */ 13598 #define PHY84328_DEV7_OUI_MSB_FIELD_RESERVED0_MASK 0xf800 13599 #define PHY84328_DEV7_OUI_MSB_FIELD_RESERVED0_ALIGN 0 13600 #define PHY84328_DEV7_OUI_MSB_FIELD_RESERVED0_BITS 5 13601 #define PHY84328_DEV7_OUI_MSB_FIELD_RESERVED0_SHIFT 11 13602 13603 /* ln_device7 :: oui_msb_field :: oui_msb_field [10:00] */ 13604 #define PHY84328_DEV7_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK 0x07ff 13605 #define PHY84328_DEV7_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN 0 13606 #define PHY84328_DEV7_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS 11 13607 #define PHY84328_DEV7_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT 0 13608 13609 13610 /**************************************************************************** 13611 * ln_device7 :: oui_lsb_field 13612 */ 13613 /* ln_device7 :: oui_lsb_field :: reserved0 [15:11] */ 13614 #define PHY84328_DEV7_OUI_LSB_FIELD_RESERVED0_MASK 0xf800 13615 #define PHY84328_DEV7_OUI_LSB_FIELD_RESERVED0_ALIGN 0 13616 #define PHY84328_DEV7_OUI_LSB_FIELD_RESERVED0_BITS 5 13617 #define PHY84328_DEV7_OUI_LSB_FIELD_RESERVED0_SHIFT 11 13618 13619 /* ln_device7 :: oui_lsb_field :: oui_lsb_field [10:00] */ 13620 #define PHY84328_DEV7_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK 0x07ff 13621 #define PHY84328_DEV7_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN 0 13622 #define PHY84328_DEV7_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS 11 13623 #define PHY84328_DEV7_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT 0 13624 13625 13626 /**************************************************************************** 13627 * ln_device7 :: ud_field 13628 */ 13629 /* ln_device7 :: ud_field :: reserved0 [15:11] */ 13630 #define PHY84328_DEV7_UD_FIELD_RESERVED0_MASK 0xf800 13631 #define PHY84328_DEV7_UD_FIELD_RESERVED0_ALIGN 0 13632 #define PHY84328_DEV7_UD_FIELD_RESERVED0_BITS 5 13633 #define PHY84328_DEV7_UD_FIELD_RESERVED0_SHIFT 11 13634 13635 /* ln_device7 :: ud_field :: ud_reserved [10:06] */ 13636 #define PHY84328_DEV7_UD_FIELD_UD_RESERVED_MASK 0x07c0 13637 #define PHY84328_DEV7_UD_FIELD_UD_RESERVED_ALIGN 0 13638 #define PHY84328_DEV7_UD_FIELD_UD_RESERVED_BITS 5 13639 #define PHY84328_DEV7_UD_FIELD_UD_RESERVED_SHIFT 6 13640 13641 /* ln_device7 :: ud_field :: remote_BN_page [05:05] */ 13642 #define PHY84328_DEV7_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 13643 #define PHY84328_DEV7_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 13644 #define PHY84328_DEV7_UD_FIELD_REMOTE_BN_PAGE_BITS 1 13645 #define PHY84328_DEV7_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 13646 13647 /* ln_device7 :: ud_field :: inband_MDIO [04:04] */ 13648 #define PHY84328_DEV7_UD_FIELD_INBAND_MDIO_MASK 0x0010 13649 #define PHY84328_DEV7_UD_FIELD_INBAND_MDIO_ALIGN 0 13650 #define PHY84328_DEV7_UD_FIELD_INBAND_MDIO_BITS 1 13651 #define PHY84328_DEV7_UD_FIELD_INBAND_MDIO_SHIFT 4 13652 13653 /* ln_device7 :: ud_field :: autoneg_MDIO [03:03] */ 13654 #define PHY84328_DEV7_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 13655 #define PHY84328_DEV7_UD_FIELD_AUTONEG_MDIO_ALIGN 0 13656 #define PHY84328_DEV7_UD_FIELD_AUTONEG_MDIO_BITS 1 13657 #define PHY84328_DEV7_UD_FIELD_AUTONEG_MDIO_SHIFT 3 13658 13659 /* ln_device7 :: ud_field :: remote_serdes_phy [02:02] */ 13660 #define PHY84328_DEV7_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 13661 #define PHY84328_DEV7_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 13662 #define PHY84328_DEV7_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 13663 #define PHY84328_DEV7_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 13664 13665 /* ln_device7 :: ud_field :: remote_cu_phy [01:01] */ 13666 #define PHY84328_DEV7_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 13667 #define PHY84328_DEV7_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 13668 #define PHY84328_DEV7_UD_FIELD_REMOTE_CU_PHY_BITS 1 13669 #define PHY84328_DEV7_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 13670 13671 /* ln_device7 :: ud_field :: over1g [00:00] */ 13672 #define PHY84328_DEV7_UD_FIELD_OVER1G_MASK 0x0001 13673 #define PHY84328_DEV7_UD_FIELD_OVER1G_ALIGN 0 13674 #define PHY84328_DEV7_UD_FIELD_OVER1G_BITS 1 13675 #define PHY84328_DEV7_UD_FIELD_OVER1G_SHIFT 0 13676 13677 13678 /**************************************************************************** 13679 * ln_device7 :: lp_ud_field 13680 */ 13681 /* ln_device7 :: lp_ud_field :: reserved0 [15:11] */ 13682 #define PHY84328_DEV7_LP_UD_FIELD_RESERVED0_MASK 0xf800 13683 #define PHY84328_DEV7_LP_UD_FIELD_RESERVED0_ALIGN 0 13684 #define PHY84328_DEV7_LP_UD_FIELD_RESERVED0_BITS 5 13685 #define PHY84328_DEV7_LP_UD_FIELD_RESERVED0_SHIFT 11 13686 13687 /* ln_device7 :: lp_ud_field :: ud_reserved [10:06] */ 13688 #define PHY84328_DEV7_LP_UD_FIELD_UD_RESERVED_MASK 0x07c0 13689 #define PHY84328_DEV7_LP_UD_FIELD_UD_RESERVED_ALIGN 0 13690 #define PHY84328_DEV7_LP_UD_FIELD_UD_RESERVED_BITS 5 13691 #define PHY84328_DEV7_LP_UD_FIELD_UD_RESERVED_SHIFT 6 13692 13693 /* ln_device7 :: lp_ud_field :: remote_BN_page [05:05] */ 13694 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 13695 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 13696 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_BN_PAGE_BITS 1 13697 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 13698 13699 /* ln_device7 :: lp_ud_field :: inband_MDIO [04:04] */ 13700 #define PHY84328_DEV7_LP_UD_FIELD_INBAND_MDIO_MASK 0x0010 13701 #define PHY84328_DEV7_LP_UD_FIELD_INBAND_MDIO_ALIGN 0 13702 #define PHY84328_DEV7_LP_UD_FIELD_INBAND_MDIO_BITS 1 13703 #define PHY84328_DEV7_LP_UD_FIELD_INBAND_MDIO_SHIFT 4 13704 13705 /* ln_device7 :: lp_ud_field :: autoneg_MDIO [03:03] */ 13706 #define PHY84328_DEV7_LP_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 13707 #define PHY84328_DEV7_LP_UD_FIELD_AUTONEG_MDIO_ALIGN 0 13708 #define PHY84328_DEV7_LP_UD_FIELD_AUTONEG_MDIO_BITS 1 13709 #define PHY84328_DEV7_LP_UD_FIELD_AUTONEG_MDIO_SHIFT 3 13710 13711 /* ln_device7 :: lp_ud_field :: remote_serdes_phy [02:02] */ 13712 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 13713 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 13714 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 13715 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 13716 13717 /* ln_device7 :: lp_ud_field :: remote_cu_phy [01:01] */ 13718 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 13719 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 13720 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_CU_PHY_BITS 1 13721 #define PHY84328_DEV7_LP_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 13722 13723 /* ln_device7 :: lp_ud_field :: over1g [00:00] */ 13724 #define PHY84328_DEV7_LP_UD_FIELD_OVER1G_MASK 0x0001 13725 #define PHY84328_DEV7_LP_UD_FIELD_OVER1G_ALIGN 0 13726 #define PHY84328_DEV7_LP_UD_FIELD_OVER1G_BITS 1 13727 #define PHY84328_DEV7_LP_UD_FIELD_OVER1G_SHIFT 0 13728 13729 13730 /**************************************************************************** 13731 * ln_device7 :: SGMIIbasepage 13732 */ 13733 /* ln_device7 :: SGMIIbasepage :: reserved0 [15:12] */ 13734 #define PHY84328_DEV7_SGMIIBASEPAGE_RESERVED0_MASK 0xf000 13735 #define PHY84328_DEV7_SGMIIBASEPAGE_RESERVED0_ALIGN 0 13736 #define PHY84328_DEV7_SGMIIBASEPAGE_RESERVED0_BITS 4 13737 #define PHY84328_DEV7_SGMIIBASEPAGE_RESERVED0_SHIFT 12 13738 13739 /* ln_device7 :: SGMIIbasepage :: sgmii_basepage [11:00] */ 13740 #define PHY84328_DEV7_SGMIIBASEPAGE_SGMII_BASEPAGE_MASK 0x0fff 13741 #define PHY84328_DEV7_SGMIIBASEPAGE_SGMII_BASEPAGE_ALIGN 0 13742 #define PHY84328_DEV7_SGMIIBASEPAGE_SGMII_BASEPAGE_BITS 12 13743 #define PHY84328_DEV7_SGMIIBASEPAGE_SGMII_BASEPAGE_SHIFT 0 13744 13745 13746 /**************************************************************************** 13747 * ln_device7 :: UP5 13748 */ 13749 /* ln_device7 :: UP5 :: reserved0 [15:11] */ 13750 #define PHY84328_DEV7_UP5_RESERVED0_MASK 0xf800 13751 #define PHY84328_DEV7_UP5_RESERVED0_ALIGN 0 13752 #define PHY84328_DEV7_UP5_RESERVED0_BITS 5 13753 #define PHY84328_DEV7_UP5_RESERVED0_SHIFT 11 13754 13755 /* ln_device7 :: UP5 :: last [10:10] */ 13756 #define PHY84328_DEV7_UP5_LAST_MASK 0x0400 13757 #define PHY84328_DEV7_UP5_LAST_ALIGN 0 13758 #define PHY84328_DEV7_UP5_LAST_BITS 1 13759 #define PHY84328_DEV7_UP5_LAST_SHIFT 10 13760 13761 /* ln_device7 :: UP5 :: reserved1 [09:00] */ 13762 #define PHY84328_DEV7_UP5_RESERVED1_MASK 0x03ff 13763 #define PHY84328_DEV7_UP5_RESERVED1_ALIGN 0 13764 #define PHY84328_DEV7_UP5_RESERVED1_BITS 10 13765 #define PHY84328_DEV7_UP5_RESERVED1_SHIFT 0 13766 13767 13768 13769 /**************************************************************************** 13770 * sys_device1_DSC_regs 13771 */ 13772 #define PHY84328_SYS_DEV1_CDR_CTRL0 0x0000c200 /* CDR_Control_0_Register */ 13773 #define PHY84328_SYS_DEV1_CDR_CTRL1 0x0000c201 /* CDR Control_1_Register */ 13774 #define PHY84328_SYS_DEV1_CDR_CTRL2 0x0000c202 /* CDR Control_2_Register */ 13775 #define PHY84328_SYS_DEV1_PI_CTRL0 0x0000c203 /* Phase_Interpolator_Control_0_Register */ 13776 #define PHY84328_SYS_DEV1_PI_CTRL1 0x0000c204 /* Phase_Interpolator_Control_1_Register */ 13777 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0 0x0000c205 /* DFE_VGA_Control_0_Register */ 13778 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1 0x0000c206 /* DFE_VGA_Control_1_Register */ 13779 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2 0x0000c207 /* DFE_VGA_Control_2_Register */ 13780 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3 0x0000c208 /* DFE_VGA_Control_3_Register */ 13781 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4 0x0000c209 /* DFE_VGA_Control_4_Register */ 13782 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5 0x0000c20a /* DFE_VGA_Control_5_Register */ 13783 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6 0x0000c20b /* DFE_VGA_Control_6_Register */ 13784 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7 0x0000c20c /* DFE_VGA_Control_7_Register */ 13785 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0 0x0000c20d /* DSC_Diagnostics_Control_0_Register */ 13786 #define PHY84328_SYS_DEV1_UC_CTRL 0x0000c20e /* DSC_to_uController_Control_Register */ 13787 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0 0x0000c210 /* DSC State Machine Control 0 Register */ 13788 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1 0x0000c211 /* DSC State Machine Control 1 Register */ 13789 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2 0x0000c212 /* DSC State Machine Control 2 Register */ 13790 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3 0x0000c213 /* DSC State Machine Control 3 Register */ 13791 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4 0x0000c214 /* DSC State Machine Control 4 Register */ 13792 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5 0x0000c215 /* DSC State Machine Control 5 Register */ 13793 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6 0x0000c216 /* DSC State Machine Control 6 Register */ 13794 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7 0x0000c217 /* DSC State Machine Control 7 Register */ 13795 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8 0x0000c218 /* DSC State Machine Control 8 Register */ 13796 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0 0x0000c219 /* DSC Analog Control 0 Register */ 13797 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1 0x0000c21a /* DSC Analog Control 1 Register */ 13798 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2 0x0000c21b /* DSC Analog Control 2 Register */ 13799 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3 0x0000c21c /* DSC Analog Control 3 Register */ 13800 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4 0x0000c21d /* DSC Analog Control 4 Register */ 13801 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0 0x0000c21e /* DSC Misc Control 0 Register */ 13802 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0 0x0000c250 /* CDR Lock Monitor Control 0 Register */ 13803 13804 13805 /**************************************************************************** 13806 * sys_device1_Micro_regs 13807 */ 13808 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0 0x0000c1e0 /* Micro-controller_Tuning_State_Debug_for_LN0 */ 13809 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1 0x0000c1e1 /* Micro-controller_Tuning_State_Debug_for_LN1 */ 13810 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2 0x0000c1e2 /* Micro-controller_Tuning_State_Debug_for_LN2 */ 13811 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3 0x0000c1e3 /* Micro-controller_Tuning_State_Debug_for_LN3 */ 13812 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0 0x0000c1e4 /* Micro-controller_Speed/Mode_Debug_for_LN0 */ 13813 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1 0x0000c1e5 /* Micro-controller_Speed/Mode_Debug_for_LN1 */ 13814 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2 0x0000c1e6 /* Micro-controller_Speed/Mode_Debug_for_LN2 */ 13815 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3 0x0000c1e7 /* Micro-controller_Speed/Mode_Debug_for_LN3 */ 13816 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0 0x0000c1e8 /* Micro-controller_CL72_Status_for_LN0 */ 13817 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1 0x0000c1e9 /* Micro-controller_CL72_Status_for_LN1 */ 13818 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2 0x0000c1ea /* Micro-controller_CL72_Status_for_LN2 */ 13819 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3 0x0000c1eb /* Micro-controller_CL72_Status_for_LN3 */ 13820 #define PHY84328_SYS_DEV1_VERSION 0x0000c1f0 /* Micro-controller Version Register */ 13821 #define PHY84328_SYS_DEV1_TARGET 0x0000c1f1 /* Micro-controller Target Register */ 13822 #define PHY84328_SYS_DEV1_FIRMWARE_MODE 0x0000c1f2 /* Micro-controller firmware_mode 2_2 Register */ 13823 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN0 0x0000c1f3 /* Micro-controller LN0 GPIO Control Register */ 13824 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN1 0x0000c1f4 /* Micro-controller LN1 GPIO Control Register */ 13825 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN2 0x0000c1f5 /* Micro-controller LN2 GPIO Control Register */ 13826 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN3 0x0000c1f6 /* Micro-controller LN3 GPIO Control Register */ 13827 #define PHY84328_SYS_DEV1_GPIO_STS_LN0 0x0000c1f7 /* Micro-controller LN0 GPIO Status Register */ 13828 #define PHY84328_SYS_DEV1_GPIO_STS_LN1 0x0000c1f8 /* Micro-controller LN1 GPIO Status Register */ 13829 #define PHY84328_SYS_DEV1_GPIO_STS_LN2 0x0000c1f9 /* Micro-controller LN2 GPIO Status Register */ 13830 #define PHY84328_SYS_DEV1_GPIO_STS_LN3 0x0000c1fa /* Micro-controller LN3 GPIO Status Register */ 13831 #define PHY84328_SYS_DEV1_REGB 0x0000c1fb /* Micro Temp 2_B Register */ 13832 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS 0x0000c1fc /* Micro Tuning states Bypass Register */ 13833 #define PHY84328_SYS_DEV1_TEMPERATURE 0x0000c1fd /* Die-Temperature Register */ 13834 #define PHY84328_SYS_DEV1_CRC 0x0000c1fe /* Micro-controller code-ram crc Register */ 13835 13836 13837 /**************************************************************************** 13838 * sys_device1_PMD_Standard_Registers 13839 */ 13840 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER 0x00000000 /* PMD Control Register */ 13841 #define PHY84328_SYS_DEV1_STATUS_REGISTER 0x00000001 /* Status Register */ 13842 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_0 0x00000002 /* PMD Identifier Register 0 */ 13843 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_1 0x00000003 /* PMD Identifier Register 1 */ 13844 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY 0x00000004 /* PMD Speed Ability */ 13845 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1 0x00000005 /* Devices in Package1 */ 13846 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2 0x00000006 /* Devices in package 2 */ 13847 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER 0x00000007 /* PMD Control 2 Register */ 13848 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2 0x00000008 /* Status Register 2 */ 13849 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER 0x0000000a /* PMD receive signal detect Register */ 13850 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER 0x0000000b /* PMD extended ability Register */ 13851 #define PHY84328_SYS_DEV1_PMD_OUI_ID0_REGISTER 0x0000000e /* PMD OUI ID0 Register */ 13852 #define PHY84328_SYS_DEV1_PMD_OUI_ID1_REG 0x0000000f /* PMD OUI ID1 Reg */ 13853 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER 0x00000096 /* R PMD Control Register */ 13854 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER 0x00000097 /* R PMD Status Register */ 13855 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152 0x00000098 /* TenGBASE_KR LP coefficient upd 152 */ 13856 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153 0x00000099 /* TenGBASE_KR LP status report reg 153 */ 13857 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154 0x0000009a /* TenGBASE_KR LD coefficient upd 154 */ 13858 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155 0x0000009b /* TenGBASE_KR LD status report reg 155 */ 13859 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER 0x000000a0 /* TenGBASE_KX Control register */ 13860 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER 0x000000a1 /* TenGBASE_KX Status register */ 13861 13862 13863 /**************************************************************************** 13864 * sys_device1_QSFI_AFE_Registers 13865 */ 13866 #define PHY84328_SYS_DEV1_ANAPLLASTATUS 0x0000c050 /* PLL_ana_status */ 13867 #define PHY84328_SYS_DEV1_ANAPLLACONTROL 0x0000c051 /* PLL_ana_controls */ 13868 #define PHY84328_SYS_DEV1_ANAPLLATIMER1 0x0000c052 /* PLL_ana_timer1 */ 13869 #define PHY84328_SYS_DEV1_ANAPLLATIMER2 0x0000c053 /* PLL_ana_timer2 */ 13870 #define PHY84328_SYS_DEV1_ANAPLLATIMER3 0x0000c054 /* PLL_ana_timer3 */ 13871 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL 0x0000c055 /* PLL_ana_CapCtrl */ 13872 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL 0x0000c056 /* PLL_ana_AmpCtrl */ 13873 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1 0x0000c058 /* PLL_ana_status1 */ 13874 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0 0x0000c059 /* PLL_ana_control0 */ 13875 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1 0x0000c05a /* PLL_ana_control1 */ 13876 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2 0x0000c05b /* PLL_ana_control2 */ 13877 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3 0x0000c05c /* PLL_ana_control3 */ 13878 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4 0x0000c05d /* PLL_ana_control4 */ 13879 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5 0x0000c05e /* PLL_ana_control5 */ 13880 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6 0x0000c05f /* PLL_ana_control6 */ 13881 #define PHY84328_SYS_DEV1_ANATXASTATUS 0x0000c060 /* Tx_ana_status */ 13882 #define PHY84328_SYS_DEV1_ANATXACONTROL 0x0000c061 /* Tx_ana_controls */ 13883 #define PHY84328_SYS_DEV1_ANATXASTATUS1 0x0000c064 /* Tx_ana_status1 */ 13884 #define PHY84328_SYS_DEV1_ANATXACONTROL1 0x0000c065 /* Tx_ana_control1 */ 13885 #define PHY84328_SYS_DEV1_ANATXACONTROL2 0x0000c066 /* Tx_ana_control2 */ 13886 #define PHY84328_SYS_DEV1_ANATXACONTROL3 0x0000c067 /* Tx_ana_control3 */ 13887 #define PHY84328_SYS_DEV1_ANATXACONTROL4 0x0000c068 /* Tx_ana_control4 */ 13888 #define PHY84328_SYS_DEV1_ANATXACONTROL5 0x0000c069 /* Tx_ana_control5 */ 13889 #define PHY84328_SYS_DEV1_ANATXACONTROL6 0x0000c06a /* Tx_ana_control6 */ 13890 #define PHY84328_SYS_DEV1_ANATXACONTROL7 0x0000c06b /* Tx_ana_control7 */ 13891 #define PHY84328_SYS_DEV1_ANARXSTATUS 0x0000c0b0 /* Rx lane status register */ 13892 #define PHY84328_SYS_DEV1_ANARXCONTROL 0x0000c0b1 /* Rx lane control register */ 13893 #define PHY84328_SYS_DEV1_ANARXSIGDET 0x0000c0b4 /* Rx Sigdet Control */ 13894 #define PHY84328_SYS_DEV1_ANARXACONTROL4 0x0000c0b5 /* Rx_analog_control_register */ 13895 #define PHY84328_SYS_DEV1_ANARXCONTROL2 0x0000c0b6 /* Rx 1G Control2 register */ 13896 #define PHY84328_SYS_DEV1_ANARXCONTROL1 0x0000c0b9 /* Rx 1G Control register */ 13897 #define PHY84328_SYS_DEV1_ANARXACONTROL1 0x0000c0bc /* Rx_analog_control_register */ 13898 #define PHY84328_SYS_DEV1_ANARXACONTROL2 0x0000c0bd /* Rx_analog_control_register */ 13899 #define PHY84328_SYS_DEV1_ANARXACONTROL3 0x0000c0be /* Rx_analog_control_register */ 13900 13901 13902 /**************************************************************************** 13903 * sys_device1_QSFI_TXPI_registers 13904 */ 13905 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1 0x0000c460 /* TX_Phase_interpolator_Control_1 Register */ 13906 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2 0x0000c461 /* TX_Phase_interpolator_Control_2 Register */ 13907 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3 0x0000c462 /* TX_Phase_interpolator_Control_3 Register */ 13908 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4 0x0000c463 /* TX_Phase_interpolator_Control_4 Register */ 13909 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5 0x0000c464 /* TX_Phase_interpolator_Control_5 Register */ 13910 #define PHY84328_SYS_DEV1_TX_PI_STATUS1 0x0000c465 /* TX_Phase_interpolator_Status_1 Register */ 13911 #define PHY84328_SYS_DEV1_TX_PI_STATUS2 0x0000c466 /* TX_Phase_interpolator_Status_2 Register */ 13912 #define PHY84328_SYS_DEV1_TX_PI_STATUS3 0x0000c467 /* TX_Phase_interpolator_Status_3 Register */ 13913 #define PHY84328_SYS_DEV1_TX_PI_STATUS4 0x0000c468 /* TX_Phase_interpolator_Status_4 Register */ 13914 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL 0x0000c469 /* Low_Latency_Phase_Error_FIFO_Control_Register */ 13915 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS 0x0000c46a /* Low_Latency_Phase_Error_FIFO_Status_Register */ 13916 #define PHY84328_SYS_DEV1_PMD_REGS_SEL 0x0000ffff /* Select System Side Registers For MDIO OP. */ 13917 13918 13919 /**************************************************************************** 13920 * sys_device1_QSFI_gpregs 13921 */ 13922 #define PHY84328_SYS_DEV1_GP2_0 0x0000c1d0 /* PLL_Status_register */ 13923 #define PHY84328_SYS_DEV1_GP2_1 0x0000c1d1 /* Link_status_register */ 13924 #define PHY84328_SYS_DEV1_GP2_2 0x0000c1d2 /* speed_lane_0_1_register */ 13925 #define PHY84328_SYS_DEV1_GP2_3 0x0000c1d3 /* speed_lane_2_3_register */ 13926 #define PHY84328_SYS_DEV1_GP2_4 0x0000c1d4 /* autoneg_status_register */ 13927 #define PHY84328_SYS_DEV1_GP2_5 0x0000c1d5 /* CL73_BAMStat1_register */ 13928 #define PHY84328_SYS_DEV1_GP2_6 0x0000c1d6 /* CL73_BAMStat2_register */ 13929 #define PHY84328_SYS_DEV1_GP2_7 0x0000c1d7 /* CL73_BAMStat3_register */ 13930 #define PHY84328_SYS_DEV1_GP2_9 0x0000c1d9 /* PRBS_lock_ln0_register */ 13931 #define PHY84328_SYS_DEV1_GP2_A 0x0000c1da /* PRBS_lock_ln1_register */ 13932 #define PHY84328_SYS_DEV1_GP2_B 0x0000c1db /* PRBS_lock_ln2_register */ 13933 #define PHY84328_SYS_DEV1_GP2_C 0x0000c1dc /* PRBS_lock_ln3_register */ 13934 13935 13936 /**************************************************************************** 13937 * sys_device1_cl72_user_regs 13938 */ 13939 #define PHY84328_SYS_DEV1_CL72_XMT_CONTROL_REGISTER 0x0000c2e0 /* CL72_TX_Coefficient_Update_Register */ 13940 #define PHY84328_SYS_DEV1_CL72_RCVD_STATUS_REGISTER 0x0000c2e1 /* CL72_Status_Report_Register */ 13941 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER 0x0000c2e2 /* CL72_TX_FIR_Tap_Register */ 13942 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL 0x0000c2e3 /* CL72_Miscellaneous_1_Control_Register */ 13943 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL 0x0000c2e4 /* CL72_Miscellaneous_2_Control_Register */ 13944 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL 0x0000c2e5 /* CL7_ KR_Default_Control_Register */ 13945 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL 0x0000c2e6 /* CL72_OS_Default_Control_Register */ 13946 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL 0x0000c2e7 /* CL72_BR_Defaul_Control_Register */ 13947 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL 0x0000c2e9 /* CL72_Tap_Limit_Control_Register */ 13948 #define PHY84328_SYS_DEV1_CL72_MISC3_CONTROL 0x0000c2ea /* CL72_Miscellaneous_3_Control_Register */ 13949 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL 0x0000c2eb /* CL72_Tap_Present_Control_Register */ 13950 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL 0x0000c2ec /* CL72_Miscellaneous_4_Control_Register */ 13951 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER 0x0000c2f9 /* CL72_Fault_Register */ 13952 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER 0x0000c2fb /* CL72_Debug_1_Register */ 13953 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER 0x0000c2fc /* CL72_Debug_2_Register */ 13954 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER 0x0000c2fd /* CL72_Debug_3_Register */ 13955 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER 0x0000c2fe /* CL72_Debug_4_Register */ 13956 13957 13958 /**************************************************************************** 13959 * sys_device1_userLanesCtrl_Registers 13960 */ 13961 #define PHY84328_SYS_DEV1_XGXSCONTROL 0x0000c000 /* XGXS control register */ 13962 #define PHY84328_SYS_DEV1_XGXSSTATUS 0x0000c001 /* XGXS status register */ 13963 #define PHY84328_SYS_DEV1_MISCCONTROL1 0x0000c00e /* Miscellaneous control 1 register */ 13964 #define PHY84328_SYS_DEV1_LANECTRL2 0x0000c017 /* Lane control 2 register */ 13965 #define PHY84328_SYS_DEV1_LANECTRL3 0x0000c018 /* Lane control 3 register */ 13966 #define PHY84328_SYS_DEV1_LANEPRBS 0x0000c019 /* Lane PRBS control register */ 13967 #define PHY84328_SYS_DEV1_LANECTRL 0x0000c01a /* Lane control register */ 13968 #define PHY84328_SYS_DEV1_TESTMODELANE 0x0000c106 /* Test_mode_lane_select_register */ 13969 #define PHY84328_SYS_DEV1_LANERESET 0x0000c10a /* Lane reset register */ 13970 #define PHY84328_SYS_DEV1_XFICONTROL 0x0000c10c /* XFI Control register */ 13971 #define PHY84328_SYS_DEV1_CL73CONTROL7 0x0000c160 /* CL73 Control 7 Register */ 13972 #define PHY84328_SYS_DEV1_CL73CONTROL8 0x0000c161 /* CL73 Control 8 Register */ 13973 #define PHY84328_SYS_DEV1_CL73CONTROL9 0x0000c162 /* CL73 Control 9 Register */ 13974 #define PHY84328_SYS_DEV1_CL73CONTROL10 0x0000c163 /* CL73 Control 10 Register */ 13975 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1 0x0000c191 /* XFI AFE Control1 Register */ 13976 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2 0x0000c192 /* XFI AFE Control2 Registe */ 13977 13978 13979 /**************************************************************************** 13980 * sys_device1_DSC_regs 13981 */ 13982 /**************************************************************************** 13983 * sys_device1 :: cdr_ctrl0 13984 */ 13985 /* sys_device1 :: cdr_ctrl0 :: cdros_xfi_integ_sat_sel [15:15] */ 13986 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_MASK 0x8000 13987 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_ALIGN 0 13988 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_BITS 1 13989 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_XFI_INTEG_SAT_SEL_SHIFT 15 13990 13991 /* sys_device1 :: cdr_ctrl0 :: cdrbr_m1_slicer_only [14:14] */ 13992 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_MASK 0x4000 13993 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_ALIGN 0 13994 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_BITS 1 13995 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_M1_SLICER_ONLY_SHIFT 14 13996 13997 /* sys_device1 :: cdr_ctrl0 :: cdrbr_p1_slicer_only [13:13] */ 13998 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_MASK 0x2000 13999 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_ALIGN 0 14000 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_BITS 1 14001 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_P1_SLICER_ONLY_SHIFT 13 14002 14003 /* sys_device1 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 14004 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 14005 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 14006 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_POLARITY_BITS 1 14007 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 14008 14009 /* sys_device1 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 14010 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 14011 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 14012 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 14013 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 14014 14015 /* sys_device1 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 14016 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 14017 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 14018 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 14019 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 14020 14021 /* sys_device1 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 14022 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 14023 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 14024 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 14025 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 14026 14027 /* sys_device1 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 14028 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 14029 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 14030 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 14031 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 14032 14033 /* sys_device1 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 14034 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 14035 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 14036 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 14037 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 14038 14039 /* sys_device1 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 14040 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 14041 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 14042 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 14043 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 14044 14045 /* sys_device1 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 14046 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 14047 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 14048 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 14049 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 14050 14051 /* sys_device1 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 14052 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 14053 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 14054 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 14055 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 14056 14057 /* sys_device1 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 14058 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 14059 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 14060 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 14061 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 14062 14063 /* sys_device1 :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 14064 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 14065 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 14066 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_EN_BITS 1 14067 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 14068 14069 /* sys_device1 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 14070 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 14071 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 14072 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 14073 #define PHY84328_SYS_DEV1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 14074 14075 14076 /**************************************************************************** 14077 * sys_device1 :: cdr_ctrl1 14078 */ 14079 /* sys_device1 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 14080 #define PHY84328_SYS_DEV1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 14081 #define PHY84328_SYS_DEV1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 14082 #define PHY84328_SYS_DEV1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 14083 #define PHY84328_SYS_DEV1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 14084 14085 14086 /**************************************************************************** 14087 * sys_device1 :: cdr_ctrl2 14088 */ 14089 /* sys_device1 :: cdr_ctrl2 :: rsvd_for_eco [15:10] */ 14090 #define PHY84328_SYS_DEV1_CDR_CTRL2_RSVD_FOR_ECO_MASK 0xfc00 14091 #define PHY84328_SYS_DEV1_CDR_CTRL2_RSVD_FOR_ECO_ALIGN 0 14092 #define PHY84328_SYS_DEV1_CDR_CTRL2_RSVD_FOR_ECO_BITS 6 14093 #define PHY84328_SYS_DEV1_CDR_CTRL2_RSVD_FOR_ECO_SHIFT 10 14094 14095 /* sys_device1 :: cdr_ctrl2 :: cdros_phase_err_offset [09:06] */ 14096 #define PHY84328_SYS_DEV1_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_MASK 0x03c0 14097 #define PHY84328_SYS_DEV1_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_ALIGN 0 14098 #define PHY84328_SYS_DEV1_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_BITS 4 14099 #define PHY84328_SYS_DEV1_CDR_CTRL2_CDROS_PHASE_ERR_OFFSET_SHIFT 6 14100 14101 /* sys_device1 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 14102 #define PHY84328_SYS_DEV1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 14103 #define PHY84328_SYS_DEV1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 14104 #define PHY84328_SYS_DEV1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 14105 #define PHY84328_SYS_DEV1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 14106 14107 14108 /**************************************************************************** 14109 * sys_device1 :: pi_ctrl0 14110 */ 14111 /* sys_device1 :: pi_ctrl0 :: pi_cw_rst [15:15] */ 14112 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_CW_RST_MASK 0x8000 14113 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_CW_RST_ALIGN 0 14114 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_CW_RST_BITS 1 14115 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_CW_RST_SHIFT 15 14116 14117 /* sys_device1 :: pi_ctrl0 :: interp_ctrl_dsel [14:12] */ 14118 #define PHY84328_SYS_DEV1_PI_CTRL0_INTERP_CTRL_DSEL_MASK 0x7000 14119 #define PHY84328_SYS_DEV1_PI_CTRL0_INTERP_CTRL_DSEL_ALIGN 0 14120 #define PHY84328_SYS_DEV1_PI_CTRL0_INTERP_CTRL_DSEL_BITS 3 14121 #define PHY84328_SYS_DEV1_PI_CTRL0_INTERP_CTRL_DSEL_SHIFT 12 14122 14123 /* sys_device1 :: pi_ctrl0 :: interp_ctrl_cap [11:11] */ 14124 #define PHY84328_SYS_DEV1_PI_CTRL0_INTERP_CTRL_CAP_MASK 0x0800 14125 #define PHY84328_SYS_DEV1_PI_CTRL0_INTERP_CTRL_CAP_ALIGN 0 14126 #define PHY84328_SYS_DEV1_PI_CTRL0_INTERP_CTRL_CAP_BITS 1 14127 #define PHY84328_SYS_DEV1_PI_CTRL0_INTERP_CTRL_CAP_SHIFT 11 14128 14129 /* sys_device1 :: pi_ctrl0 :: reserved_for_eco0 [10:06] */ 14130 #define PHY84328_SYS_DEV1_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0x07c0 14131 #define PHY84328_SYS_DEV1_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 14132 #define PHY84328_SYS_DEV1_PI_CTRL0_RESERVED_FOR_ECO0_BITS 5 14133 #define PHY84328_SYS_DEV1_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 6 14134 14135 /* sys_device1 :: pi_ctrl0 :: pi_phase_step_mult_os8 [05:05] */ 14136 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_MASK 0x0020 14137 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_ALIGN 0 14138 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_BITS 1 14139 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS8_SHIFT 5 14140 14141 /* sys_device1 :: pi_ctrl0 :: pi_phase_step_mult_os4 [04:04] */ 14142 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_MASK 0x0010 14143 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_ALIGN 0 14144 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_BITS 1 14145 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS4_SHIFT 4 14146 14147 /* sys_device1 :: pi_ctrl0 :: pi_phase_step_mult_os3 [03:03] */ 14148 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_MASK 0x0008 14149 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_ALIGN 0 14150 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_BITS 1 14151 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS3_SHIFT 3 14152 14153 /* sys_device1 :: pi_ctrl0 :: pi_phase_step_mult_os2 [02:02] */ 14154 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_MASK 0x0004 14155 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_ALIGN 0 14156 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_BITS 1 14157 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_OS2_SHIFT 2 14158 14159 /* sys_device1 :: pi_ctrl0 :: pi_phase_invert [01:01] */ 14160 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0002 14161 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 14162 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_INVERT_BITS 1 14163 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_INVERT_SHIFT 1 14164 14165 /* sys_device1 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 14166 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 14167 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 14168 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 14169 #define PHY84328_SYS_DEV1_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 14170 14171 14172 /**************************************************************************** 14173 * sys_device1 :: pi_ctrl1 14174 */ 14175 /* sys_device1 :: pi_ctrl1 :: reserved_for_eco0 [15:12] */ 14176 #define PHY84328_SYS_DEV1_PI_CTRL1_RESERVED_FOR_ECO0_MASK 0xf000 14177 #define PHY84328_SYS_DEV1_PI_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 14178 #define PHY84328_SYS_DEV1_PI_CTRL1_RESERVED_FOR_ECO0_BITS 4 14179 #define PHY84328_SYS_DEV1_PI_CTRL1_RESERVED_FOR_ECO0_SHIFT 12 14180 14181 /* sys_device1 :: pi_ctrl1 :: pi_phase_step_dir [11:11] */ 14182 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STEP_DIR_MASK 0x0800 14183 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STEP_DIR_ALIGN 0 14184 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STEP_DIR_BITS 1 14185 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STEP_DIR_SHIFT 11 14186 14187 /* sys_device1 :: pi_ctrl1 :: pi_phase_step [10:09] */ 14188 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STEP_MASK 0x0600 14189 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STEP_ALIGN 0 14190 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STEP_BITS 2 14191 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STEP_SHIFT 9 14192 14193 /* sys_device1 :: pi_ctrl1 :: pi_phase_delta [08:04] */ 14194 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_DELTA_MASK 0x01f0 14195 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_DELTA_ALIGN 0 14196 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_DELTA_BITS 5 14197 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_DELTA_SHIFT 4 14198 14199 /* sys_device1 :: pi_ctrl1 :: pi_phase_strobe [03:03] */ 14200 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STROBE_MASK 0x0008 14201 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STROBE_ALIGN 0 14202 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STROBE_BITS 1 14203 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_STROBE_SHIFT 3 14204 14205 /* sys_device1 :: pi_ctrl1 :: pi_phase_rotate_override [02:02] */ 14206 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_MASK 0x0004 14207 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_ALIGN 0 14208 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_BITS 1 14209 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_PHASE_ROTATE_OVERRIDE_SHIFT 2 14210 14211 /* sys_device1 :: pi_ctrl1 :: pi_clk90_offset_override [01:01] */ 14212 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0002 14213 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 14214 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_BITS 1 14215 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_CLK90_OFFSET_OVERRIDE_SHIFT 1 14216 14217 /* sys_device1 :: pi_ctrl1 :: pi_dual_phase_override [00:00] */ 14218 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_MASK 0x0001 14219 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 14220 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_BITS 1 14221 #define PHY84328_SYS_DEV1_PI_CTRL1_PI_DUAL_PHASE_OVERRIDE_SHIFT 0 14222 14223 14224 /**************************************************************************** 14225 * sys_device1 :: dfe_vga_ctrl0 14226 */ 14227 /* sys_device1 :: dfe_vga_ctrl0 :: dfe_abs_sum_max [15:09] */ 14228 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_MASK 0xfe00 14229 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_ALIGN 0 14230 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_BITS 7 14231 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_ABS_SUM_MAX_SHIFT 9 14232 14233 /* sys_device1 :: dfe_vga_ctrl0 :: random_tapsel_disable [08:08] */ 14234 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_MASK 0x0100 14235 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_ALIGN 0 14236 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_BITS 1 14237 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_RANDOM_TAPSEL_DISABLE_SHIFT 8 14238 14239 /* sys_device1 :: dfe_vga_ctrl0 :: cor_neg2_en [07:07] */ 14240 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_COR_NEG2_EN_MASK 0x0080 14241 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_COR_NEG2_EN_ALIGN 0 14242 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_COR_NEG2_EN_BITS 1 14243 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_COR_NEG2_EN_SHIFT 7 14244 14245 /* sys_device1 :: dfe_vga_ctrl0 :: cor_neg1_en [06:06] */ 14246 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_COR_NEG1_EN_MASK 0x0040 14247 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_COR_NEG1_EN_ALIGN 0 14248 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_COR_NEG1_EN_BITS 1 14249 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_COR_NEG1_EN_SHIFT 6 14250 14251 /* sys_device1 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 14252 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 14253 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 14254 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 14255 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 14256 14257 /* sys_device1 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 14258 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 14259 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 14260 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 14261 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 14262 14263 /* sys_device1 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 14264 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 14265 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 14266 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 14267 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 14268 14269 /* sys_device1 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 14270 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 14271 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 14272 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 14273 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 14274 14275 /* sys_device1 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 14276 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 14277 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 14278 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 14279 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 14280 14281 /* sys_device1 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 14282 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 14283 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 14284 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 14285 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 14286 14287 14288 /**************************************************************************** 14289 * sys_device1 :: dfe_vga_ctrl1 14290 */ 14291 /* sys_device1 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:14] */ 14292 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0xc000 14293 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 14294 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 2 14295 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 14 14296 14297 /* sys_device1 :: dfe_vga_ctrl1 :: dfe_llms_update_count_sel [13:12] */ 14298 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_MASK 0x3000 14299 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_ALIGN 0 14300 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_BITS 2 14301 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_LLMS_UPDATE_COUNT_SEL_SHIFT 12 14302 14303 /* sys_device1 :: dfe_vga_ctrl1 :: dfe_llms_en [11:11] */ 14304 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_LLMS_EN_MASK 0x0800 14305 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_LLMS_EN_ALIGN 0 14306 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_LLMS_EN_BITS 1 14307 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_LLMS_EN_SHIFT 11 14308 14309 /* sys_device1 :: dfe_vga_ctrl1 :: dfe_cdros_qphase_mult_en [10:10] */ 14310 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_MASK 0x0400 14311 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_ALIGN 0 14312 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_BITS 1 14313 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_CDROS_QPHASE_MULT_EN_SHIFT 10 14314 14315 /* sys_device1 :: dfe_vga_ctrl1 :: dfe_tap_2_dcd [09:06] */ 14316 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_2_DCD_MASK 0x03c0 14317 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_2_DCD_ALIGN 0 14318 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_2_DCD_BITS 4 14319 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_2_DCD_SHIFT 6 14320 14321 /* sys_device1 :: dfe_vga_ctrl1 :: dfe_tap_1_do [05:03] */ 14322 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DO_MASK 0x0038 14323 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DO_ALIGN 0 14324 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DO_BITS 3 14325 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DO_SHIFT 3 14326 14327 /* sys_device1 :: dfe_vga_ctrl1 :: dfe_tap_1_de [02:00] */ 14328 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DE_MASK 0x0007 14329 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DE_ALIGN 0 14330 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DE_BITS 3 14331 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL1_DFE_TAP_1_DE_SHIFT 0 14332 14333 14334 /**************************************************************************** 14335 * sys_device1 :: dfe_vga_ctrl2 14336 */ 14337 /* sys_device1 :: dfe_vga_ctrl2 :: vga3_override_val [15:12] */ 14338 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_MASK 0xf000 14339 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_ALIGN 0 14340 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_BITS 4 14341 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_VAL_SHIFT 12 14342 14343 /* sys_device1 :: dfe_vga_ctrl2 :: vga3_override_en [11:11] */ 14344 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_MASK 0x0800 14345 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_ALIGN 0 14346 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_BITS 1 14347 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_VGA3_OVERRIDE_EN_SHIFT 11 14348 14349 /* sys_device1 :: dfe_vga_ctrl2 :: reserved_for_eco0 [10:10] */ 14350 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK 0x0400 14351 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 14352 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS 1 14353 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT 10 14354 14355 /* sys_device1 :: dfe_vga_ctrl2 :: dfe_vga_write_tapsel [09:07] */ 14356 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_MASK 0x0380 14357 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_ALIGN 0 14358 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_BITS 3 14359 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_TAPSEL_SHIFT 7 14360 14361 /* sys_device1 :: dfe_vga_ctrl2 :: dfe_vga_write_val [06:01] */ 14362 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_MASK 0x007e 14363 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_ALIGN 0 14364 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_BITS 6 14365 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_VAL_SHIFT 1 14366 14367 /* sys_device1 :: dfe_vga_ctrl2 :: dfe_vga_write_en [00:00] */ 14368 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_MASK 0x0001 14369 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_ALIGN 0 14370 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_BITS 1 14371 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL2_DFE_VGA_WRITE_EN_SHIFT 0 14372 14373 14374 /**************************************************************************** 14375 * sys_device1 :: dfe_vga_ctrl3 14376 */ 14377 /* sys_device1 :: dfe_vga_ctrl3 :: trnsum_otap_en [15:08] */ 14378 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_MASK 0xff00 14379 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_ALIGN 0 14380 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_BITS 8 14381 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3_TRNSUM_OTAP_EN_SHIFT 8 14382 14383 /* sys_device1 :: dfe_vga_ctrl3 :: trnsum_etap_en [07:00] */ 14384 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_MASK 0x00ff 14385 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_ALIGN 0 14386 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_BITS 8 14387 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL3_TRNSUM_ETAP_EN_SHIFT 0 14388 14389 14390 /**************************************************************************** 14391 * sys_device1 :: dfe_vga_ctrl4 14392 */ 14393 /* sys_device1 :: dfe_vga_ctrl4 :: trnsum_otap_sign [15:08] */ 14394 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_MASK 0xff00 14395 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_ALIGN 0 14396 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_BITS 8 14397 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4_TRNSUM_OTAP_SIGN_SHIFT 8 14398 14399 /* sys_device1 :: dfe_vga_ctrl4 :: trnsum_etap_sign [07:00] */ 14400 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_MASK 0x00ff 14401 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_ALIGN 0 14402 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_BITS 8 14403 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL4_TRNSUM_ETAP_SIGN_SHIFT 0 14404 14405 14406 /**************************************************************************** 14407 * sys_device1 :: dfe_vga_ctrl5 14408 */ 14409 /* sys_device1 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */ 14410 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK 0xfc00 14411 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 14412 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS 6 14413 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT 10 14414 14415 /* sys_device1 :: dfe_vga_ctrl5 :: vga_cor_sel_e [09:05] */ 14416 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_E_MASK 0x03e0 14417 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_E_ALIGN 0 14418 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_E_BITS 5 14419 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_E_SHIFT 5 14420 14421 /* sys_device1 :: dfe_vga_ctrl5 :: vga_cor_sel_o [04:00] */ 14422 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_O_MASK 0x001f 14423 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_O_ALIGN 0 14424 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_O_BITS 5 14425 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL5_VGA_COR_SEL_O_SHIFT 0 14426 14427 14428 /**************************************************************************** 14429 * sys_device1 :: dfe_vga_ctrl6 14430 */ 14431 /* sys_device1 :: dfe_vga_ctrl6 :: reserved_for_eco0 [15:10] */ 14432 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_MASK 0xfc00 14433 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 14434 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_BITS 6 14435 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_RESERVED_FOR_ECO0_SHIFT 10 14436 14437 /* sys_device1 :: dfe_vga_ctrl6 :: dfe_cor_sel_e [09:05] */ 14438 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_E_MASK 0x03e0 14439 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_E_ALIGN 0 14440 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_E_BITS 5 14441 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_E_SHIFT 5 14442 14443 /* sys_device1 :: dfe_vga_ctrl6 :: dfe_cor_sel_o [04:00] */ 14444 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_O_MASK 0x001f 14445 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_O_ALIGN 0 14446 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_O_BITS 5 14447 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL6_DFE_COR_SEL_O_SHIFT 0 14448 14449 14450 /**************************************************************************** 14451 * sys_device1 :: dfe_vga_ctrl7 14452 */ 14453 /* sys_device1 :: dfe_vga_ctrl7 :: disable_cl72_rcving_ctrl_frame [15:15] */ 14454 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_MASK 0x8000 14455 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_ALIGN 0 14456 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_BITS 1 14457 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_DISABLE_CL72_RCVING_CTRL_FRAME_SHIFT 15 14458 14459 /* sys_device1 :: dfe_vga_ctrl7 :: pattern [14:08] */ 14460 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_MASK 0x7f00 14461 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_ALIGN 0 14462 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_BITS 7 14463 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_SHIFT 8 14464 14465 /* sys_device1 :: dfe_vga_ctrl7 :: pattern_bit_en [07:01] */ 14466 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_BIT_EN_MASK 0x00fe 14467 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_BIT_EN_ALIGN 0 14468 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_BIT_EN_BITS 7 14469 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_BIT_EN_SHIFT 1 14470 14471 /* sys_device1 :: dfe_vga_ctrl7 :: pattern_en [00:00] */ 14472 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_EN_MASK 0x0001 14473 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_EN_ALIGN 0 14474 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_EN_BITS 1 14475 #define PHY84328_SYS_DEV1_DFE_VGA_CTRL7_PATTERN_EN_SHIFT 0 14476 14477 14478 /**************************************************************************** 14479 * sys_device1 :: dsc_diag_ctrl0 14480 */ 14481 /* sys_device1 :: dsc_diag_ctrl0 :: rsvd_for_eco [15:12] */ 14482 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_RSVD_FOR_ECO_MASK 0xf000 14483 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_RSVD_FOR_ECO_ALIGN 0 14484 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_RSVD_FOR_ECO_BITS 4 14485 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_RSVD_FOR_ECO_SHIFT 12 14486 14487 /* sys_device1 :: dsc_diag_ctrl0 :: osx2_diag_ctrl [11:11] */ 14488 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_MASK 0x0800 14489 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_ALIGN 0 14490 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_BITS 1 14491 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_OSX2_DIAG_CTRL_SHIFT 11 14492 14493 /* sys_device1 :: dsc_diag_ctrl0 :: voffset [10:07] */ 14494 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 14495 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 14496 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_VOFFSET_BITS 4 14497 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 14498 14499 /* sys_device1 :: dsc_diag_ctrl0 :: hoffset [06:01] */ 14500 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 14501 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 14502 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_HOFFSET_BITS 6 14503 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 14504 14505 /* sys_device1 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 14506 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 14507 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 14508 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 14509 #define PHY84328_SYS_DEV1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 14510 14511 14512 /**************************************************************************** 14513 * sys_device1 :: uC_ctrl 14514 */ 14515 /* sys_device1 :: uC_ctrl :: supplement_info [15:08] */ 14516 #define PHY84328_SYS_DEV1_UC_CTRL_SUPPLEMENT_INFO_MASK 0xff00 14517 #define PHY84328_SYS_DEV1_UC_CTRL_SUPPLEMENT_INFO_ALIGN 0 14518 #define PHY84328_SYS_DEV1_UC_CTRL_SUPPLEMENT_INFO_BITS 8 14519 #define PHY84328_SYS_DEV1_UC_CTRL_SUPPLEMENT_INFO_SHIFT 8 14520 14521 /* sys_device1 :: uC_ctrl :: ready_for_cmd [07:07] */ 14522 #define PHY84328_SYS_DEV1_UC_CTRL_READY_FOR_CMD_MASK 0x0080 14523 #define PHY84328_SYS_DEV1_UC_CTRL_READY_FOR_CMD_ALIGN 0 14524 #define PHY84328_SYS_DEV1_UC_CTRL_READY_FOR_CMD_BITS 1 14525 #define PHY84328_SYS_DEV1_UC_CTRL_READY_FOR_CMD_SHIFT 7 14526 14527 /* sys_device1 :: uC_ctrl :: error_found [06:06] */ 14528 #define PHY84328_SYS_DEV1_UC_CTRL_ERROR_FOUND_MASK 0x0040 14529 #define PHY84328_SYS_DEV1_UC_CTRL_ERROR_FOUND_ALIGN 0 14530 #define PHY84328_SYS_DEV1_UC_CTRL_ERROR_FOUND_BITS 1 14531 #define PHY84328_SYS_DEV1_UC_CTRL_ERROR_FOUND_SHIFT 6 14532 14533 /* sys_device1 :: uC_ctrl :: cmd_info [05:04] */ 14534 #define PHY84328_SYS_DEV1_UC_CTRL_CMD_INFO_MASK 0x0030 14535 #define PHY84328_SYS_DEV1_UC_CTRL_CMD_INFO_ALIGN 0 14536 #define PHY84328_SYS_DEV1_UC_CTRL_CMD_INFO_BITS 2 14537 #define PHY84328_SYS_DEV1_UC_CTRL_CMD_INFO_SHIFT 4 14538 14539 /* sys_device1 :: uC_ctrl :: gp_uC_req [03:00] */ 14540 #define PHY84328_SYS_DEV1_UC_CTRL_GP_UC_REQ_MASK 0x000f 14541 #define PHY84328_SYS_DEV1_UC_CTRL_GP_UC_REQ_ALIGN 0 14542 #define PHY84328_SYS_DEV1_UC_CTRL_GP_UC_REQ_BITS 4 14543 #define PHY84328_SYS_DEV1_UC_CTRL_GP_UC_REQ_SHIFT 0 14544 14545 14546 /**************************************************************************** 14547 * sys_device1 :: acq_sm_ctrl0 14548 */ 14549 /* sys_device1 :: acq_sm_ctrl0 :: cl72_timer_en [15:15] */ 14550 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_CL72_TIMER_EN_MASK 0x8000 14551 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_CL72_TIMER_EN_ALIGN 0 14552 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_CL72_TIMER_EN_BITS 1 14553 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_CL72_TIMER_EN_SHIFT 15 14554 14555 /* sys_device1 :: acq_sm_ctrl0 :: acq2_timeout [14:10] */ 14556 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQ2_TIMEOUT_MASK 0x7c00 14557 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQ2_TIMEOUT_ALIGN 0 14558 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQ2_TIMEOUT_BITS 5 14559 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQ2_TIMEOUT_SHIFT 10 14560 14561 /* sys_device1 :: acq_sm_ctrl0 :: acq1_timeout [09:05] */ 14562 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQ1_TIMEOUT_MASK 0x03e0 14563 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQ1_TIMEOUT_ALIGN 0 14564 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQ1_TIMEOUT_BITS 5 14565 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQ1_TIMEOUT_SHIFT 5 14566 14567 /* sys_device1 :: acq_sm_ctrl0 :: acqcdr_timeout [04:00] */ 14568 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_MASK 0x001f 14569 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_ALIGN 0 14570 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_BITS 5 14571 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL0_ACQCDR_TIMEOUT_SHIFT 0 14572 14573 14574 /**************************************************************************** 14575 * sys_device1 :: acq_sm_ctrl1 14576 */ 14577 /* sys_device1 :: acq_sm_ctrl1 :: acqvga_timeout [15:11] */ 14578 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_MASK 0xf800 14579 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_ALIGN 0 14580 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_BITS 5 14581 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_ACQVGA_TIMEOUT_SHIFT 11 14582 14583 /* sys_device1 :: acq_sm_ctrl1 :: bypass_os_integ_xfer [10:10] */ 14584 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_MASK 0x0400 14585 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_ALIGN 0 14586 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_BITS 1 14587 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_BYPASS_OS_INTEG_XFER_SHIFT 10 14588 14589 /* sys_device1 :: acq_sm_ctrl1 :: dfe_frzval [09:05] */ 14590 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DFE_FRZVAL_MASK 0x03e0 14591 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DFE_FRZVAL_ALIGN 0 14592 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DFE_FRZVAL_BITS 5 14593 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DFE_FRZVAL_SHIFT 5 14594 14595 /* sys_device1 :: acq_sm_ctrl1 :: dfe_frcfrz [04:04] */ 14596 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DFE_FRCFRZ_MASK 0x0010 14597 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DFE_FRCFRZ_ALIGN 0 14598 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DFE_FRCFRZ_BITS 1 14599 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DFE_FRCFRZ_SHIFT 4 14600 14601 /* sys_device1 :: acq_sm_ctrl1 :: vga_frzval [03:03] */ 14602 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_VGA_FRZVAL_MASK 0x0008 14603 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_VGA_FRZVAL_ALIGN 0 14604 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_VGA_FRZVAL_BITS 1 14605 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_VGA_FRZVAL_SHIFT 3 14606 14607 /* sys_device1 :: acq_sm_ctrl1 :: vga_frcfrz [02:02] */ 14608 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_VGA_FRCFRZ_MASK 0x0004 14609 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_VGA_FRCFRZ_ALIGN 0 14610 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_VGA_FRCFRZ_BITS 1 14611 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_VGA_FRCFRZ_SHIFT 2 14612 14613 /* sys_device1 :: acq_sm_ctrl1 :: dsc_clr_val [01:01] */ 14614 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DSC_CLR_VAL_MASK 0x0002 14615 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DSC_CLR_VAL_ALIGN 0 14616 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DSC_CLR_VAL_BITS 1 14617 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DSC_CLR_VAL_SHIFT 1 14618 14619 /* sys_device1 :: acq_sm_ctrl1 :: dsc_clr_frc [00:00] */ 14620 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DSC_CLR_FRC_MASK 0x0001 14621 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DSC_CLR_FRC_ALIGN 0 14622 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DSC_CLR_FRC_BITS 1 14623 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL1_DSC_CLR_FRC_SHIFT 0 14624 14625 14626 /**************************************************************************** 14627 * sys_device1 :: acq_sm_ctrl2 14628 */ 14629 /* sys_device1 :: acq_sm_ctrl2 :: sw_handover [15:15] */ 14630 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SW_HANDOVER_MASK 0x8000 14631 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SW_HANDOVER_ALIGN 0 14632 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SW_HANDOVER_BITS 1 14633 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SW_HANDOVER_SHIFT 15 14634 14635 /* sys_device1 :: acq_sm_ctrl2 :: eee_acq_2_timeout [14:10] */ 14636 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_MASK 0x7c00 14637 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_ALIGN 0 14638 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_BITS 5 14639 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_EEE_ACQ_2_TIMEOUT_SHIFT 10 14640 14641 /* sys_device1 :: acq_sm_ctrl2 :: eee_acq_phase_timeout [09:05] */ 14642 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_MASK 0x03e0 14643 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_ALIGN 0 14644 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_BITS 5 14645 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_EEE_ACQ_PHASE_TIMEOUT_SHIFT 5 14646 14647 /* sys_device1 :: acq_sm_ctrl2 :: skip_acq [04:04] */ 14648 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SKIP_ACQ_MASK 0x0010 14649 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SKIP_ACQ_ALIGN 0 14650 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SKIP_ACQ_BITS 1 14651 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SKIP_ACQ_SHIFT 4 14652 14653 /* sys_device1 :: acq_sm_ctrl2 :: train2_req [03:03] */ 14654 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 14655 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN2_REQ_ALIGN 0 14656 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN2_REQ_BITS 1 14657 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN2_REQ_SHIFT 3 14658 14659 /* sys_device1 :: acq_sm_ctrl2 :: train1_req [02:02] */ 14660 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 14661 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN1_REQ_ALIGN 0 14662 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN1_REQ_BITS 1 14663 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN1_REQ_SHIFT 2 14664 14665 /* sys_device1 :: acq_sm_ctrl2 :: soft_ack [01:01] */ 14666 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SOFT_ACK_MASK 0x0002 14667 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SOFT_ACK_ALIGN 0 14668 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SOFT_ACK_BITS 1 14669 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_SOFT_ACK_SHIFT 1 14670 14671 /* sys_device1 :: acq_sm_ctrl2 :: train_mode_en [00:00] */ 14672 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 14673 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 14674 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN_MODE_EN_BITS 1 14675 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 14676 14677 14678 /**************************************************************************** 14679 * sys_device1 :: acq_sm_ctrl3 14680 */ 14681 /* sys_device1 :: acq_sm_ctrl3 :: pause_level_trigger_en [15:15] */ 14682 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_MASK 0x8000 14683 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_ALIGN 0 14684 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_BITS 1 14685 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_PAUSE_LEVEL_TRIGGER_EN_SHIFT 15 14686 14687 /* sys_device1 :: acq_sm_ctrl3 :: reserved_for_eco0 [14:14] */ 14688 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0x4000 14689 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 14690 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_BITS 1 14691 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 14 14692 14693 /* sys_device1 :: acq_sm_ctrl3 :: os_dfe_en [13:13] */ 14694 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_OS_DFE_EN_MASK 0x2000 14695 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_OS_DFE_EN_ALIGN 0 14696 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_OS_DFE_EN_BITS 1 14697 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_OS_DFE_EN_SHIFT 13 14698 14699 /* sys_device1 :: acq_sm_ctrl3 :: dfe_taps2_5_en [12:12] */ 14700 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_MASK 0x1000 14701 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_ALIGN 0 14702 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_BITS 1 14703 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_TAPS2_5_EN_SHIFT 12 14704 14705 /* sys_device1 :: acq_sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 14706 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 14707 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 14708 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 14709 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 14710 14711 /* sys_device1 :: acq_sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 14712 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 14713 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 14714 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 14715 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 14716 14717 /* sys_device1 :: acq_sm_ctrl3 :: vga_gain_acq2 [07:06] */ 14718 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 14719 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 14720 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 14721 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 14722 14723 /* sys_device1 :: acq_sm_ctrl3 :: vga_gain_acq1 [05:04] */ 14724 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 14725 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 14726 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 14727 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 14728 14729 /* sys_device1 :: acq_sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 14730 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 14731 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 14732 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 14733 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 14734 14735 /* sys_device1 :: acq_sm_ctrl3 :: vga_gain_acqvga [01:00] */ 14736 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 14737 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 14738 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 14739 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 14740 14741 14742 /**************************************************************************** 14743 * sys_device1 :: acq_sm_ctrl4 14744 */ 14745 /* sys_device1 :: acq_sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 14746 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 14747 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 14748 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 14749 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 14750 14751 /* sys_device1 :: acq_sm_ctrl4 :: cdros38_bwsel_prop_offset [13:12] */ 14752 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_MASK 0x3000 14753 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_ALIGN 0 14754 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_BITS 2 14755 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS38_BWSEL_PROP_OFFSET_SHIFT 12 14756 14757 /* sys_device1 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acq1_2 [11:08] */ 14758 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x0f00 14759 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 14760 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 14761 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 8 14762 14763 /* sys_device1 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqcdr [07:04] */ 14764 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_MASK 0x00f0 14765 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 14766 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_BITS 4 14767 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQCDR_SHIFT 4 14768 14769 /* sys_device1 :: acq_sm_ctrl4 :: cdros_bwsel_prop_acqvga [03:00] */ 14770 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 14771 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 14772 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_BITS 4 14773 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL4_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 14774 14775 14776 /**************************************************************************** 14777 * sys_device1 :: acq_sm_ctrl5 14778 */ 14779 /* sys_device1 :: acq_sm_ctrl5 :: cdros_bwsel_integ_eee_acq2 [15:12] */ 14780 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_MASK 0xf000 14781 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_ALIGN 0 14782 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_BITS 4 14783 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_EEE_ACQ2_SHIFT 12 14784 14785 /* sys_device1 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [11:08] */ 14786 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0x0f00 14787 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 14788 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 14789 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 8 14790 14791 /* sys_device1 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqcdr [07:04] */ 14792 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x00f0 14793 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 14794 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 14795 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 4 14796 14797 /* sys_device1 :: acq_sm_ctrl5 :: cdros_bwsel_integ_acqvga [03:00] */ 14798 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x000f 14799 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 14800 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 14801 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL5_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 0 14802 14803 14804 /**************************************************************************** 14805 * sys_device1 :: acq_sm_ctrl6 14806 */ 14807 /* sys_device1 :: acq_sm_ctrl6 :: reserved_for_eco0 [15:12] */ 14808 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xf000 14809 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 14810 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_BITS 4 14811 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 12 14812 14813 /* sys_device1 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq2 [11:09] */ 14814 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0e00 14815 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 14816 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_BITS 3 14817 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ2_SHIFT 9 14818 14819 /* sys_device1 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acq1 [08:06] */ 14820 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_MASK 0x01c0 14821 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 14822 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_BITS 3 14823 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQ1_SHIFT 6 14824 14825 /* sys_device1 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqcdr [05:03] */ 14826 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x0038 14827 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 14828 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 14829 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 3 14830 14831 /* sys_device1 :: acq_sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [02:00] */ 14832 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0007 14833 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 14834 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 14835 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 0 14836 14837 14838 /**************************************************************************** 14839 * sys_device1 :: acq_sm_ctrl7 14840 */ 14841 /* sys_device1 :: acq_sm_ctrl7 :: reserved_for_eco0 [15:12] */ 14842 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_MASK 0xf000 14843 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN 0 14844 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_BITS 4 14845 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT 12 14846 14847 /* sys_device1 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq2 [11:09] */ 14848 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0e00 14849 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 14850 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_BITS 3 14851 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 9 14852 14853 /* sys_device1 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acq1 [08:06] */ 14854 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x01c0 14855 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 14856 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_BITS 3 14857 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 6 14858 14859 /* sys_device1 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqcdr [05:03] */ 14860 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x0038 14861 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 14862 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_BITS 3 14863 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 3 14864 14865 /* sys_device1 :: acq_sm_ctrl7 :: cdrbr_bwsel_integ_acqphase [02:00] */ 14866 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x0007 14867 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 14868 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 3 14869 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL7_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 0 14870 14871 14872 /**************************************************************************** 14873 * sys_device1 :: acq_sm_ctrl8 14874 */ 14875 /* sys_device1 :: acq_sm_ctrl8 :: reserved_for_eco0 [15:15] */ 14876 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_MASK 0x8000 14877 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN 0 14878 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_BITS 1 14879 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT 15 14880 14881 /* sys_device1 :: acq_sm_ctrl8 :: cdros_bwsel_prop_eee_acqphase [14:11] */ 14882 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_MASK 0x7800 14883 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_ALIGN 0 14884 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_BITS 4 14885 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_EEE_ACQPHASE_SHIFT 11 14886 14887 /* sys_device1 :: acq_sm_ctrl8 :: phase_sat_ctrl_100fx [10:09] */ 14888 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_MASK 0x0600 14889 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_ALIGN 0 14890 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_BITS 2 14891 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_PHASE_SAT_CTRL_100FX_SHIFT 9 14892 14893 /* sys_device1 :: acq_sm_ctrl8 :: pi_phase_step_mult_100fx [08:08] */ 14894 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 14895 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_ALIGN 0 14896 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_BITS 1 14897 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_PI_PHASE_STEP_MULT_100FX_SHIFT 8 14898 14899 /* sys_device1 :: acq_sm_ctrl8 :: cdros_bwsel_integ_100fx [07:04] */ 14900 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 14901 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_ALIGN 0 14902 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_BITS 4 14903 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_INTEG_100FX_SHIFT 4 14904 14905 /* sys_device1 :: acq_sm_ctrl8 :: cdros_bwsel_prop_100fx [03:00] */ 14906 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_MASK 0x000f 14907 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_ALIGN 0 14908 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_BITS 4 14909 #define PHY84328_SYS_DEV1_ACQ_SM_CTRL8_CDROS_BWSEL_PROP_100FX_SHIFT 0 14910 14911 14912 /**************************************************************************** 14913 * sys_device1 :: dsc_ana_ctrl0 14914 */ 14915 /* sys_device1 :: dsc_ana_ctrl0 :: reserved_for_eco0 [15:15] */ 14916 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 14917 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 14918 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_BITS 1 14919 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 14920 14921 /* sys_device1 :: dsc_ana_ctrl0 :: force_p1_ctrl_strobe [14:14] */ 14922 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_MASK 0x4000 14923 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_ALIGN 0 14924 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_BITS 1 14925 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_CTRL_STROBE_SHIFT 14 14926 14927 /* sys_device1 :: dsc_ana_ctrl0 :: force_p1_odd_ctrl [13:13] */ 14928 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_MASK 0x2000 14929 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_ALIGN 0 14930 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_BITS 1 14931 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_ODD_CTRL_SHIFT 13 14932 14933 /* sys_device1 :: dsc_ana_ctrl0 :: force_p1_evn_ctrl [12:12] */ 14934 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_MASK 0x1000 14935 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_ALIGN 0 14936 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_BITS 1 14937 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_FORCE_P1_EVN_CTRL_SHIFT 12 14938 14939 /* sys_device1 :: dsc_ana_ctrl0 :: p1_odd_ctrl [11:06] */ 14940 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x0fc0 14941 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 14942 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 6 14943 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 6 14944 14945 /* sys_device1 :: dsc_ana_ctrl0 :: p1_evn_ctrl [05:00] */ 14946 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_P1_EVN_CTRL_MASK 0x003f 14947 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_P1_EVN_CTRL_ALIGN 0 14948 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_P1_EVN_CTRL_BITS 6 14949 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL0_P1_EVN_CTRL_SHIFT 0 14950 14951 14952 /**************************************************************************** 14953 * sys_device1 :: dsc_ana_ctrl1 14954 */ 14955 /* sys_device1 :: dsc_ana_ctrl1 :: reserved_for_eco0 [15:15] */ 14956 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_MASK 0x8000 14957 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 14958 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_BITS 1 14959 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_RESERVED_FOR_ECO0_SHIFT 15 14960 14961 /* sys_device1 :: dsc_ana_ctrl1 :: force_d_ctrl_strobe [14:14] */ 14962 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_MASK 0x4000 14963 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_ALIGN 0 14964 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_BITS 1 14965 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_CTRL_STROBE_SHIFT 14 14966 14967 /* sys_device1 :: dsc_ana_ctrl1 :: force_d_odd_ctrl [13:13] */ 14968 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_MASK 0x2000 14969 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_ALIGN 0 14970 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_BITS 1 14971 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_ODD_CTRL_SHIFT 13 14972 14973 /* sys_device1 :: dsc_ana_ctrl1 :: force_d_evn_ctrl [12:12] */ 14974 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_MASK 0x1000 14975 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_ALIGN 0 14976 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_BITS 1 14977 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_FORCE_D_EVN_CTRL_SHIFT 12 14978 14979 /* sys_device1 :: dsc_ana_ctrl1 :: d_odd_ctrl [11:06] */ 14980 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_D_ODD_CTRL_MASK 0x0fc0 14981 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_D_ODD_CTRL_ALIGN 0 14982 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_D_ODD_CTRL_BITS 6 14983 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_D_ODD_CTRL_SHIFT 6 14984 14985 /* sys_device1 :: dsc_ana_ctrl1 :: d_evn_ctrl [05:00] */ 14986 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x003f 14987 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 14988 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 6 14989 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 0 14990 14991 14992 /**************************************************************************** 14993 * sys_device1 :: dsc_ana_ctrl2 14994 */ 14995 /* sys_device1 :: dsc_ana_ctrl2 :: reserved_for_eco0 [15:15] */ 14996 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_MASK 0x8000 14997 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 14998 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_BITS 1 14999 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_RESERVED_FOR_ECO0_SHIFT 15 15000 15001 /* sys_device1 :: dsc_ana_ctrl2 :: force_m1_ctrl_strobe [14:14] */ 15002 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_MASK 0x4000 15003 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_ALIGN 0 15004 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_BITS 1 15005 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_CTRL_STROBE_SHIFT 14 15006 15007 /* sys_device1 :: dsc_ana_ctrl2 :: force_m1_odd_ctrl [13:13] */ 15008 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_MASK 0x2000 15009 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_ALIGN 0 15010 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_BITS 1 15011 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_ODD_CTRL_SHIFT 13 15012 15013 /* sys_device1 :: dsc_ana_ctrl2 :: force_m1_evn_ctrl [12:12] */ 15014 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_MASK 0x1000 15015 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_ALIGN 0 15016 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_BITS 1 15017 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_FORCE_M1_EVN_CTRL_SHIFT 12 15018 15019 /* sys_device1 :: dsc_ana_ctrl2 :: m1_odd_ctrl [11:06] */ 15020 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_M1_ODD_CTRL_MASK 0x0fc0 15021 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_M1_ODD_CTRL_ALIGN 0 15022 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_M1_ODD_CTRL_BITS 6 15023 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_M1_ODD_CTRL_SHIFT 6 15024 15025 /* sys_device1 :: dsc_ana_ctrl2 :: m1_evn_ctrl [05:00] */ 15026 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_M1_EVN_CTRL_MASK 0x003f 15027 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_M1_EVN_CTRL_ALIGN 0 15028 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_M1_EVN_CTRL_BITS 6 15029 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL2_M1_EVN_CTRL_SHIFT 0 15030 15031 15032 /**************************************************************************** 15033 * sys_device1 :: dsc_ana_ctrl3 15034 */ 15035 /* sys_device1 :: dsc_ana_ctrl3 :: rsvd_for_eco [15:10] */ 15036 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RSVD_FOR_ECO_MASK 0xfc00 15037 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RSVD_FOR_ECO_ALIGN 0 15038 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RSVD_FOR_ECO_BITS 6 15039 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RSVD_FOR_ECO_SHIFT 10 15040 15041 /* sys_device1 :: dsc_ana_ctrl3 :: rx_pf_hiz [09:09] */ 15042 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_PF_HIZ_MASK 0x0200 15043 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_PF_HIZ_ALIGN 0 15044 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_PF_HIZ_BITS 1 15045 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_PF_HIZ_SHIFT 9 15046 15047 /* sys_device1 :: dsc_ana_ctrl3 :: force_rx_m1_thresh_zero [08:08] */ 15048 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_MASK 0x0100 15049 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 15050 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_BITS 1 15051 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_FORCE_RX_M1_THRESH_ZERO_SHIFT 8 15052 15053 /* sys_device1 :: dsc_ana_ctrl3 :: rx_m1_thresh_zero [07:07] */ 15054 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_MASK 0x0080 15055 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_ALIGN 0 15056 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_BITS 1 15057 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_M1_THRESH_ZERO_SHIFT 7 15058 15059 /* sys_device1 :: dsc_ana_ctrl3 :: rx_thresh_sel [06:05] */ 15060 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_THRESH_SEL_MASK 0x0060 15061 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_THRESH_SEL_ALIGN 0 15062 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_THRESH_SEL_BITS 2 15063 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_THRESH_SEL_SHIFT 5 15064 15065 /* sys_device1 :: dsc_ana_ctrl3 :: force_rx_pf_ctrl [04:04] */ 15066 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_MASK 0x0010 15067 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_ALIGN 0 15068 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_BITS 1 15069 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_FORCE_RX_PF_CTRL_SHIFT 4 15070 15071 /* sys_device1 :: dsc_ana_ctrl3 :: rx_pf_ctrl [03:00] */ 15072 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_PF_CTRL_MASK 0x000f 15073 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_PF_CTRL_ALIGN 0 15074 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_PF_CTRL_BITS 4 15075 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL3_RX_PF_CTRL_SHIFT 0 15076 15077 15078 /**************************************************************************** 15079 * sys_device1 :: dsc_ana_ctrl4 15080 */ 15081 /* sys_device1 :: dsc_ana_ctrl4 :: reserved_for_eco0 [15:08] */ 15082 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_MASK 0xff00 15083 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 15084 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_BITS 8 15085 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_RESERVED_FOR_ECO0_SHIFT 8 15086 15087 /* sys_device1 :: dsc_ana_ctrl4 :: br_offset_pd [07:07] */ 15088 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_OFFSET_PD_MASK 0x0080 15089 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_OFFSET_PD_ALIGN 0 15090 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_OFFSET_PD_BITS 1 15091 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_OFFSET_PD_SHIFT 7 15092 15093 /* sys_device1 :: dsc_ana_ctrl4 :: br_en_hgain [06:06] */ 15094 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_EN_HGAIN_MASK 0x0040 15095 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_EN_HGAIN_ALIGN 0 15096 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_EN_HGAIN_BITS 1 15097 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_EN_HGAIN_SHIFT 6 15098 15099 /* sys_device1 :: dsc_ana_ctrl4 :: br_en_dfe_clk [05:05] */ 15100 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_EN_DFE_CLK_MASK 0x0020 15101 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_EN_DFE_CLK_ALIGN 0 15102 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_EN_DFE_CLK_BITS 1 15103 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_EN_DFE_CLK_SHIFT 5 15104 15105 /* sys_device1 :: dsc_ana_ctrl4 :: br_pd_ch_p1 [04:04] */ 15106 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_PD_CH_P1_MASK 0x0010 15107 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_PD_CH_P1_ALIGN 0 15108 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_PD_CH_P1_BITS 1 15109 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_BR_PD_CH_P1_SHIFT 4 15110 15111 /* sys_device1 :: dsc_ana_ctrl4 :: osr_offset_pd [03:03] */ 15112 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_OFFSET_PD_MASK 0x0008 15113 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_OFFSET_PD_ALIGN 0 15114 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_OFFSET_PD_BITS 1 15115 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_OFFSET_PD_SHIFT 3 15116 15117 /* sys_device1 :: dsc_ana_ctrl4 :: osr_en_hgain [02:02] */ 15118 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_EN_HGAIN_MASK 0x0004 15119 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_EN_HGAIN_ALIGN 0 15120 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_EN_HGAIN_BITS 1 15121 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_EN_HGAIN_SHIFT 2 15122 15123 /* sys_device1 :: dsc_ana_ctrl4 :: osr_en_dfe_clk [01:01] */ 15124 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_MASK 0x0002 15125 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_ALIGN 0 15126 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_BITS 1 15127 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_EN_DFE_CLK_SHIFT 1 15128 15129 /* sys_device1 :: dsc_ana_ctrl4 :: osr_pd_ch_p1 [00:00] */ 15130 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_PD_CH_P1_MASK 0x0001 15131 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_PD_CH_P1_ALIGN 0 15132 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_PD_CH_P1_BITS 1 15133 #define PHY84328_SYS_DEV1_DSC_ANA_CTRL4_OSR_PD_CH_P1_SHIFT 0 15134 15135 15136 /**************************************************************************** 15137 * sys_device1 :: dsc_misc_ctrl0 15138 */ 15139 /* sys_device1 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 15140 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 15141 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 15142 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 15143 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 15144 15145 /* sys_device1 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 15146 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 15147 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 15148 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 15149 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 15150 15151 /* sys_device1 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */ 15152 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK 0x2000 15153 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN 0 15154 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS 1 15155 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT 13 15156 15157 /* sys_device1 :: dsc_misc_ctrl0 :: forceRxSeqDone_val [12:12] */ 15158 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_MASK 0x1000 15159 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_ALIGN 0 15160 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_BITS 1 15161 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_FORCERXSEQDONE_VAL_SHIFT 12 15162 15163 /* sys_device1 :: dsc_misc_ctrl0 :: rxSeqStart_AN_disable [11:11] */ 15164 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_MASK 0x0800 15165 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_ALIGN 0 15166 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_BITS 1 15167 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_RXSEQSTART_AN_DISABLE_SHIFT 11 15168 15169 /* sys_device1 :: dsc_misc_ctrl0 :: test_bus_sel_bit4 [10:10] */ 15170 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_MASK 0x0400 15171 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_ALIGN 0 15172 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_BITS 1 15173 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BIT4_SHIFT 10 15174 15175 /* sys_device1 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 15176 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 15177 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 15178 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 15179 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 15180 15181 /* sys_device1 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 15182 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 15183 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 15184 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 15185 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 15186 15187 /* sys_device1 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 15188 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 15189 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 15190 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 15191 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 15192 15193 /* sys_device1 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 15194 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 15195 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 15196 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 15197 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 15198 15199 /* sys_device1 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 15200 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 15201 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 15202 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 15203 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 15204 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 15205 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 15206 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 15207 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 15208 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 15209 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 15210 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 15211 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 15212 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 15213 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 15214 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe1 12 15215 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe2 13 15216 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe3 14 15217 #define PHY84328_SYS_DEV1_DSC_MISC_CTRL0_TEST_BUS_SEL_anadfe4 15 15218 15219 15220 /**************************************************************************** 15221 * sys_device1 :: cdr_lm_ctrl_0 15222 */ 15223 /* sys_device1 :: cdr_lm_ctrl_0 :: reserved_for_eco0 [15:10] */ 15224 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_MASK 0xfc00 15225 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_ALIGN 0 15226 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_BITS 6 15227 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_RESERVED_FOR_ECO0_SHIFT 10 15228 15229 /* sys_device1 :: cdr_lm_ctrl_0 :: refclk_frc_sel [09:09] */ 15230 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_SEL_MASK 0x0200 15231 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_SEL_ALIGN 0 15232 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_SEL_BITS 1 15233 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_SEL_SHIFT 9 15234 15235 /* sys_device1 :: cdr_lm_ctrl_0 :: refclk_frc_val [08:08] */ 15236 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_VAL_MASK 0x0100 15237 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_VAL_ALIGN 0 15238 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_VAL_BITS 1 15239 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_FRC_VAL_SHIFT 8 15240 15241 /* sys_device1 :: cdr_lm_ctrl_0 :: refclk_async_sel [07:07] */ 15242 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_ASYNC_SEL_MASK 0x0080 15243 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_ASYNC_SEL_ALIGN 0 15244 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_ASYNC_SEL_BITS 1 15245 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_REFCLK_ASYNC_SEL_SHIFT 7 15246 15247 /* sys_device1 :: cdr_lm_ctrl_0 :: pf_ctrl_strobe [06:06] */ 15248 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_PF_CTRL_STROBE_MASK 0x0040 15249 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_PF_CTRL_STROBE_ALIGN 0 15250 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_PF_CTRL_STROBE_BITS 1 15251 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_PF_CTRL_STROBE_SHIFT 6 15252 15253 /* sys_device1 :: cdr_lm_ctrl_0 :: force_pcs_clken [05:05] */ 15254 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_MASK 0x0020 15255 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_ALIGN 0 15256 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_BITS 1 15257 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_SHIFT 5 15258 15259 /* sys_device1 :: cdr_lm_ctrl_0 :: force_pcs_clken_val [04:04] */ 15260 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_MASK 0x0010 15261 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_ALIGN 0 15262 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_BITS 1 15263 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_FORCE_PCS_CLKEN_VAL_SHIFT 4 15264 15265 /* sys_device1 :: cdr_lm_ctrl_0 :: cdr_lm_thr_sel [03:01] */ 15266 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_CDR_LM_THR_SEL_MASK 0x000e 15267 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_CDR_LM_THR_SEL_ALIGN 0 15268 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_CDR_LM_THR_SEL_BITS 3 15269 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_CDR_LM_THR_SEL_SHIFT 1 15270 15271 /* sys_device1 :: cdr_lm_ctrl_0 :: cdr_lm_en [00:00] */ 15272 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_CDR_LM_EN_MASK 0x0001 15273 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_CDR_LM_EN_ALIGN 0 15274 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_CDR_LM_EN_BITS 1 15275 #define PHY84328_SYS_DEV1_CDR_LM_CTRL_0_CDR_LM_EN_SHIFT 0 15276 15277 15278 /**************************************************************************** 15279 * sys_device1_Micro_regs 15280 */ 15281 /**************************************************************************** 15282 * sys_device1 :: state_debug_ln0 15283 */ 15284 /* sys_device1 :: state_debug_ln0 :: CDR_LOCK_CORR [15:15] */ 15285 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CDR_LOCK_CORR_MASK 0x8000 15286 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CDR_LOCK_CORR_ALIGN 0 15287 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CDR_LOCK_CORR_BITS 1 15288 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CDR_LOCK_CORR_SHIFT 15 15289 15290 /* sys_device1 :: state_debug_ln0 :: DSC_DONE [14:14] */ 15291 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DSC_DONE_MASK 0x4000 15292 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DSC_DONE_ALIGN 0 15293 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DSC_DONE_BITS 1 15294 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DSC_DONE_SHIFT 14 15295 15296 /* sys_device1 :: state_debug_ln0 :: TUNING_DONE [13:13] */ 15297 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_TUNING_DONE_MASK 0x2000 15298 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_TUNING_DONE_ALIGN 0 15299 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_TUNING_DONE_BITS 1 15300 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_TUNING_DONE_SHIFT 13 15301 15302 /* sys_device1 :: state_debug_ln0 :: KR4_DIV16CK_BCST [12:12] */ 15303 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_MASK 0x1000 15304 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_ALIGN 0 15305 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_BITS 1 15306 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_KR4_DIV16CK_BCST_SHIFT 12 15307 15308 /* sys_device1 :: state_debug_ln0 :: DCD_DFE_TUNING [11:11] */ 15309 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DCD_DFE_TUNING_MASK 0x0800 15310 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DCD_DFE_TUNING_ALIGN 0 15311 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DCD_DFE_TUNING_BITS 1 15312 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DCD_DFE_TUNING_SHIFT 11 15313 15314 /* sys_device1 :: state_debug_ln0 :: OSDFE_P1_TUNING [10:10] */ 15315 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_OSDFE_P1_TUNING_MASK 0x0400 15316 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_OSDFE_P1_TUNING_ALIGN 0 15317 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_OSDFE_P1_TUNING_BITS 1 15318 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_OSDFE_P1_TUNING_SHIFT 10 15319 15320 /* sys_device1 :: state_debug_ln0 :: SLICER_OFFSET_TUNING [09:09] */ 15321 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_MASK 0x0200 15322 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_ALIGN 0 15323 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_BITS 1 15324 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_SLICER_OFFSET_TUNING_SHIFT 9 15325 15326 /* sys_device1 :: state_debug_ln0 :: CL72_REMOTE_TUNING [08:08] */ 15327 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_MASK 0x0100 15328 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_ALIGN 0 15329 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_BITS 1 15330 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CL72_REMOTE_TUNING_SHIFT 8 15331 15332 /* sys_device1 :: state_debug_ln0 :: CL72_TUNING [07:07] */ 15333 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CL72_TUNING_MASK 0x0080 15334 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CL72_TUNING_ALIGN 0 15335 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CL72_TUNING_BITS 1 15336 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CL72_TUNING_SHIFT 7 15337 15338 /* sys_device1 :: state_debug_ln0 :: SLICER_TARGET_TUNING [06:06] */ 15339 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_MASK 0x0040 15340 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_ALIGN 0 15341 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_BITS 1 15342 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_SLICER_TARGET_TUNING_SHIFT 6 15343 15344 /* sys_device1 :: state_debug_ln0 :: VGA_BIAS_TUNING [05:05] */ 15345 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_VGA_BIAS_TUNING_MASK 0x0020 15346 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_VGA_BIAS_TUNING_ALIGN 0 15347 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_VGA_BIAS_TUNING_BITS 1 15348 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_VGA_BIAS_TUNING_SHIFT 5 15349 15350 /* sys_device1 :: state_debug_ln0 :: PF_TUNING [04:04] */ 15351 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_PF_TUNING_MASK 0x0010 15352 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_PF_TUNING_ALIGN 0 15353 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_PF_TUNING_BITS 1 15354 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_PF_TUNING_SHIFT 4 15355 15356 /* sys_device1 :: state_debug_ln0 :: CLK90_OFFSET_TUNING [03:03] */ 15357 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_MASK 0x0008 15358 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_ALIGN 0 15359 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_BITS 1 15360 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CLK90_OFFSET_TUNING_SHIFT 3 15361 15362 /* sys_device1 :: state_debug_ln0 :: OS_VGA_TUNING [02:02] */ 15363 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_OS_VGA_TUNING_MASK 0x0004 15364 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_OS_VGA_TUNING_ALIGN 0 15365 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_OS_VGA_TUNING_BITS 1 15366 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_OS_VGA_TUNING_SHIFT 2 15367 15368 /* sys_device1 :: state_debug_ln0 :: DFE_TAPS_2_5_EN [01:01] */ 15369 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_MASK 0x0002 15370 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_ALIGN 0 15371 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_BITS 1 15372 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_DFE_TAPS_2_5_EN_SHIFT 1 15373 15374 /* sys_device1 :: state_debug_ln0 :: CDR_LOCK [00:00] */ 15375 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CDR_LOCK_MASK 0x0001 15376 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CDR_LOCK_ALIGN 0 15377 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CDR_LOCK_BITS 1 15378 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN0_CDR_LOCK_SHIFT 0 15379 15380 15381 /**************************************************************************** 15382 * sys_device1 :: state_debug_ln1 15383 */ 15384 /* sys_device1 :: state_debug_ln1 :: CDR_LOCK_CORR [15:15] */ 15385 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CDR_LOCK_CORR_MASK 0x8000 15386 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CDR_LOCK_CORR_ALIGN 0 15387 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CDR_LOCK_CORR_BITS 1 15388 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CDR_LOCK_CORR_SHIFT 15 15389 15390 /* sys_device1 :: state_debug_ln1 :: DSC_DONE [14:14] */ 15391 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DSC_DONE_MASK 0x4000 15392 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DSC_DONE_ALIGN 0 15393 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DSC_DONE_BITS 1 15394 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DSC_DONE_SHIFT 14 15395 15396 /* sys_device1 :: state_debug_ln1 :: TUNING_DONE [13:13] */ 15397 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_TUNING_DONE_MASK 0x2000 15398 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_TUNING_DONE_ALIGN 0 15399 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_TUNING_DONE_BITS 1 15400 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_TUNING_DONE_SHIFT 13 15401 15402 /* sys_device1 :: state_debug_ln1 :: KR4_DIV16CK_BCST [12:12] */ 15403 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_MASK 0x1000 15404 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_ALIGN 0 15405 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_BITS 1 15406 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_KR4_DIV16CK_BCST_SHIFT 12 15407 15408 /* sys_device1 :: state_debug_ln1 :: DCD_DFE_TUNING [11:11] */ 15409 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DCD_DFE_TUNING_MASK 0x0800 15410 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DCD_DFE_TUNING_ALIGN 0 15411 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DCD_DFE_TUNING_BITS 1 15412 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DCD_DFE_TUNING_SHIFT 11 15413 15414 /* sys_device1 :: state_debug_ln1 :: OSDFE_P1_TUNING [10:10] */ 15415 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_OSDFE_P1_TUNING_MASK 0x0400 15416 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_OSDFE_P1_TUNING_ALIGN 0 15417 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_OSDFE_P1_TUNING_BITS 1 15418 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_OSDFE_P1_TUNING_SHIFT 10 15419 15420 /* sys_device1 :: state_debug_ln1 :: SLICER_OFFSET_TUNING [09:09] */ 15421 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_MASK 0x0200 15422 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_ALIGN 0 15423 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_BITS 1 15424 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_SLICER_OFFSET_TUNING_SHIFT 9 15425 15426 /* sys_device1 :: state_debug_ln1 :: CL72_REMOTE_TUNING [08:08] */ 15427 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_MASK 0x0100 15428 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_ALIGN 0 15429 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_BITS 1 15430 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CL72_REMOTE_TUNING_SHIFT 8 15431 15432 /* sys_device1 :: state_debug_ln1 :: CL72_TUNING [07:07] */ 15433 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CL72_TUNING_MASK 0x0080 15434 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CL72_TUNING_ALIGN 0 15435 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CL72_TUNING_BITS 1 15436 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CL72_TUNING_SHIFT 7 15437 15438 /* sys_device1 :: state_debug_ln1 :: SLICER_TARGET_TUNING [06:06] */ 15439 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_MASK 0x0040 15440 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_ALIGN 0 15441 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_BITS 1 15442 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_SLICER_TARGET_TUNING_SHIFT 6 15443 15444 /* sys_device1 :: state_debug_ln1 :: VGA_BIAS_TUNING [05:05] */ 15445 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_VGA_BIAS_TUNING_MASK 0x0020 15446 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_VGA_BIAS_TUNING_ALIGN 0 15447 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_VGA_BIAS_TUNING_BITS 1 15448 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_VGA_BIAS_TUNING_SHIFT 5 15449 15450 /* sys_device1 :: state_debug_ln1 :: PF_TUNING [04:04] */ 15451 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_PF_TUNING_MASK 0x0010 15452 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_PF_TUNING_ALIGN 0 15453 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_PF_TUNING_BITS 1 15454 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_PF_TUNING_SHIFT 4 15455 15456 /* sys_device1 :: state_debug_ln1 :: CLK90_OFFSET_TUNING [03:03] */ 15457 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_MASK 0x0008 15458 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_ALIGN 0 15459 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_BITS 1 15460 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CLK90_OFFSET_TUNING_SHIFT 3 15461 15462 /* sys_device1 :: state_debug_ln1 :: OS_VGA_TUNING [02:02] */ 15463 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_OS_VGA_TUNING_MASK 0x0004 15464 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_OS_VGA_TUNING_ALIGN 0 15465 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_OS_VGA_TUNING_BITS 1 15466 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_OS_VGA_TUNING_SHIFT 2 15467 15468 /* sys_device1 :: state_debug_ln1 :: DFE_TAPS_2_5_EN [01:01] */ 15469 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_MASK 0x0002 15470 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_ALIGN 0 15471 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_BITS 1 15472 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_DFE_TAPS_2_5_EN_SHIFT 1 15473 15474 /* sys_device1 :: state_debug_ln1 :: CDR_LOCK [00:00] */ 15475 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CDR_LOCK_MASK 0x0001 15476 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CDR_LOCK_ALIGN 0 15477 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CDR_LOCK_BITS 1 15478 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN1_CDR_LOCK_SHIFT 0 15479 15480 15481 /**************************************************************************** 15482 * sys_device1 :: state_debug_ln2 15483 */ 15484 /* sys_device1 :: state_debug_ln2 :: CDR_LOCK_CORR [15:15] */ 15485 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CDR_LOCK_CORR_MASK 0x8000 15486 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CDR_LOCK_CORR_ALIGN 0 15487 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CDR_LOCK_CORR_BITS 1 15488 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CDR_LOCK_CORR_SHIFT 15 15489 15490 /* sys_device1 :: state_debug_ln2 :: DSC_DONE [14:14] */ 15491 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DSC_DONE_MASK 0x4000 15492 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DSC_DONE_ALIGN 0 15493 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DSC_DONE_BITS 1 15494 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DSC_DONE_SHIFT 14 15495 15496 /* sys_device1 :: state_debug_ln2 :: TUNING_DONE [13:13] */ 15497 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_TUNING_DONE_MASK 0x2000 15498 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_TUNING_DONE_ALIGN 0 15499 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_TUNING_DONE_BITS 1 15500 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_TUNING_DONE_SHIFT 13 15501 15502 /* sys_device1 :: state_debug_ln2 :: KR4_DIV16CK_BCST [12:12] */ 15503 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_MASK 0x1000 15504 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_ALIGN 0 15505 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_BITS 1 15506 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_KR4_DIV16CK_BCST_SHIFT 12 15507 15508 /* sys_device1 :: state_debug_ln2 :: DCD_DFE_TUNING [11:11] */ 15509 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DCD_DFE_TUNING_MASK 0x0800 15510 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DCD_DFE_TUNING_ALIGN 0 15511 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DCD_DFE_TUNING_BITS 1 15512 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DCD_DFE_TUNING_SHIFT 11 15513 15514 /* sys_device1 :: state_debug_ln2 :: OSDFE_P1_TUNING [10:10] */ 15515 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_OSDFE_P1_TUNING_MASK 0x0400 15516 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_OSDFE_P1_TUNING_ALIGN 0 15517 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_OSDFE_P1_TUNING_BITS 1 15518 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_OSDFE_P1_TUNING_SHIFT 10 15519 15520 /* sys_device1 :: state_debug_ln2 :: SLICER_OFFSET_TUNING [09:09] */ 15521 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_MASK 0x0200 15522 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_ALIGN 0 15523 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_BITS 1 15524 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_SLICER_OFFSET_TUNING_SHIFT 9 15525 15526 /* sys_device1 :: state_debug_ln2 :: CL72_REMOTE_TUNING [08:08] */ 15527 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_MASK 0x0100 15528 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_ALIGN 0 15529 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_BITS 1 15530 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CL72_REMOTE_TUNING_SHIFT 8 15531 15532 /* sys_device1 :: state_debug_ln2 :: CL72_TUNING [07:07] */ 15533 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CL72_TUNING_MASK 0x0080 15534 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CL72_TUNING_ALIGN 0 15535 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CL72_TUNING_BITS 1 15536 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CL72_TUNING_SHIFT 7 15537 15538 /* sys_device1 :: state_debug_ln2 :: SLICER_TARGET_TUNING [06:06] */ 15539 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_MASK 0x0040 15540 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_ALIGN 0 15541 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_BITS 1 15542 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_SLICER_TARGET_TUNING_SHIFT 6 15543 15544 /* sys_device1 :: state_debug_ln2 :: VGA_BIAS_TUNING [05:05] */ 15545 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_VGA_BIAS_TUNING_MASK 0x0020 15546 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_VGA_BIAS_TUNING_ALIGN 0 15547 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_VGA_BIAS_TUNING_BITS 1 15548 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_VGA_BIAS_TUNING_SHIFT 5 15549 15550 /* sys_device1 :: state_debug_ln2 :: PF_TUNING [04:04] */ 15551 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_PF_TUNING_MASK 0x0010 15552 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_PF_TUNING_ALIGN 0 15553 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_PF_TUNING_BITS 1 15554 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_PF_TUNING_SHIFT 4 15555 15556 /* sys_device1 :: state_debug_ln2 :: CLK90_OFFSET_TUNING [03:03] */ 15557 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_MASK 0x0008 15558 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_ALIGN 0 15559 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_BITS 1 15560 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CLK90_OFFSET_TUNING_SHIFT 3 15561 15562 /* sys_device1 :: state_debug_ln2 :: OS_VGA_TUNING [02:02] */ 15563 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_OS_VGA_TUNING_MASK 0x0004 15564 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_OS_VGA_TUNING_ALIGN 0 15565 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_OS_VGA_TUNING_BITS 1 15566 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_OS_VGA_TUNING_SHIFT 2 15567 15568 /* sys_device1 :: state_debug_ln2 :: DFE_TAPS_2_5_EN [01:01] */ 15569 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_MASK 0x0002 15570 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_ALIGN 0 15571 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_BITS 1 15572 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_DFE_TAPS_2_5_EN_SHIFT 1 15573 15574 /* sys_device1 :: state_debug_ln2 :: CDR_LOCK [00:00] */ 15575 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CDR_LOCK_MASK 0x0001 15576 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CDR_LOCK_ALIGN 0 15577 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CDR_LOCK_BITS 1 15578 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN2_CDR_LOCK_SHIFT 0 15579 15580 15581 /**************************************************************************** 15582 * sys_device1 :: state_debug_ln3 15583 */ 15584 /* sys_device1 :: state_debug_ln3 :: CDR_LOCK_CORR [15:15] */ 15585 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CDR_LOCK_CORR_MASK 0x8000 15586 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CDR_LOCK_CORR_ALIGN 0 15587 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CDR_LOCK_CORR_BITS 1 15588 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CDR_LOCK_CORR_SHIFT 15 15589 15590 /* sys_device1 :: state_debug_ln3 :: DSC_DONE [14:14] */ 15591 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DSC_DONE_MASK 0x4000 15592 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DSC_DONE_ALIGN 0 15593 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DSC_DONE_BITS 1 15594 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DSC_DONE_SHIFT 14 15595 15596 /* sys_device1 :: state_debug_ln3 :: TUNING_DONE [13:13] */ 15597 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_TUNING_DONE_MASK 0x2000 15598 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_TUNING_DONE_ALIGN 0 15599 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_TUNING_DONE_BITS 1 15600 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_TUNING_DONE_SHIFT 13 15601 15602 /* sys_device1 :: state_debug_ln3 :: KR4_DIV16CK_BCST [12:12] */ 15603 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_MASK 0x1000 15604 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_ALIGN 0 15605 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_BITS 1 15606 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_KR4_DIV16CK_BCST_SHIFT 12 15607 15608 /* sys_device1 :: state_debug_ln3 :: DCD_DFE_TUNING [11:11] */ 15609 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DCD_DFE_TUNING_MASK 0x0800 15610 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DCD_DFE_TUNING_ALIGN 0 15611 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DCD_DFE_TUNING_BITS 1 15612 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DCD_DFE_TUNING_SHIFT 11 15613 15614 /* sys_device1 :: state_debug_ln3 :: OSDFE_P1_TUNING [10:10] */ 15615 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_OSDFE_P1_TUNING_MASK 0x0400 15616 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_OSDFE_P1_TUNING_ALIGN 0 15617 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_OSDFE_P1_TUNING_BITS 1 15618 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_OSDFE_P1_TUNING_SHIFT 10 15619 15620 /* sys_device1 :: state_debug_ln3 :: SLICER_OFFSET_TUNING [09:09] */ 15621 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_MASK 0x0200 15622 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_ALIGN 0 15623 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_BITS 1 15624 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_SLICER_OFFSET_TUNING_SHIFT 9 15625 15626 /* sys_device1 :: state_debug_ln3 :: CL72_REMOTE_TUNING [08:08] */ 15627 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_MASK 0x0100 15628 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_ALIGN 0 15629 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_BITS 1 15630 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CL72_REMOTE_TUNING_SHIFT 8 15631 15632 /* sys_device1 :: state_debug_ln3 :: CL72_TUNING [07:07] */ 15633 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CL72_TUNING_MASK 0x0080 15634 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CL72_TUNING_ALIGN 0 15635 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CL72_TUNING_BITS 1 15636 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CL72_TUNING_SHIFT 7 15637 15638 /* sys_device1 :: state_debug_ln3 :: SLICER_TARGET_TUNING [06:06] */ 15639 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_MASK 0x0040 15640 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_ALIGN 0 15641 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_BITS 1 15642 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_SLICER_TARGET_TUNING_SHIFT 6 15643 15644 /* sys_device1 :: state_debug_ln3 :: VGA_BIAS_TUNING [05:05] */ 15645 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_VGA_BIAS_TUNING_MASK 0x0020 15646 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_VGA_BIAS_TUNING_ALIGN 0 15647 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_VGA_BIAS_TUNING_BITS 1 15648 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_VGA_BIAS_TUNING_SHIFT 5 15649 15650 /* sys_device1 :: state_debug_ln3 :: PF_TUNING [04:04] */ 15651 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_PF_TUNING_MASK 0x0010 15652 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_PF_TUNING_ALIGN 0 15653 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_PF_TUNING_BITS 1 15654 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_PF_TUNING_SHIFT 4 15655 15656 /* sys_device1 :: state_debug_ln3 :: CLK90_OFFSET_TUNING [03:03] */ 15657 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_MASK 0x0008 15658 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_ALIGN 0 15659 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_BITS 1 15660 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CLK90_OFFSET_TUNING_SHIFT 3 15661 15662 /* sys_device1 :: state_debug_ln3 :: OS_VGA_TUNING [02:02] */ 15663 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_OS_VGA_TUNING_MASK 0x0004 15664 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_OS_VGA_TUNING_ALIGN 0 15665 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_OS_VGA_TUNING_BITS 1 15666 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_OS_VGA_TUNING_SHIFT 2 15667 15668 /* sys_device1 :: state_debug_ln3 :: DFE_TAPS_2_5_EN [01:01] */ 15669 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_MASK 0x0002 15670 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_ALIGN 0 15671 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_BITS 1 15672 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_DFE_TAPS_2_5_EN_SHIFT 1 15673 15674 /* sys_device1 :: state_debug_ln3 :: CDR_LOCK [00:00] */ 15675 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CDR_LOCK_MASK 0x0001 15676 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CDR_LOCK_ALIGN 0 15677 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CDR_LOCK_BITS 1 15678 #define PHY84328_SYS_DEV1_STATE_DEBUG_LN3_CDR_LOCK_SHIFT 0 15679 15680 15681 /**************************************************************************** 15682 * sys_device1 :: speed_debug_ln0 15683 */ 15684 /* sys_device1 :: speed_debug_ln0 :: LOS_counter [15:12] */ 15685 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_LOS_COUNTER_MASK 0xf000 15686 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_LOS_COUNTER_ALIGN 0 15687 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_LOS_COUNTER_BITS 4 15688 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_LOS_COUNTER_SHIFT 12 15689 15690 /* sys_device1 :: speed_debug_ln0 :: need_br_dfe [11:11] */ 15691 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_NEED_BR_DFE_MASK 0x0800 15692 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_NEED_BR_DFE_ALIGN 0 15693 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_NEED_BR_DFE_BITS 1 15694 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_NEED_BR_DFE_SHIFT 11 15695 15696 /* sys_device1 :: speed_debug_ln0 :: br_dfe_enabled [10:10] */ 15697 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_BR_DFE_ENABLED_MASK 0x0400 15698 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_BR_DFE_ENABLED_ALIGN 0 15699 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_BR_DFE_ENABLED_BITS 1 15700 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_BR_DFE_ENABLED_SHIFT 10 15701 15702 /* sys_device1 :: speed_debug_ln0 :: os_dfe_enabled [09:09] */ 15703 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_OS_DFE_ENABLED_MASK 0x0200 15704 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_OS_DFE_ENABLED_ALIGN 0 15705 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_OS_DFE_ENABLED_BITS 1 15706 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_OS_DFE_ENABLED_SHIFT 9 15707 15708 /* sys_device1 :: speed_debug_ln0 :: os_enabled [08:08] */ 15709 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_OS_ENABLED_MASK 0x0100 15710 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_OS_ENABLED_ALIGN 0 15711 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_OS_ENABLED_BITS 1 15712 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_OS_ENABLED_SHIFT 8 15713 15714 /* sys_device1 :: speed_debug_ln0 :: actual_speed [07:00] */ 15715 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_ACTUAL_SPEED_MASK 0x00ff 15716 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_ACTUAL_SPEED_ALIGN 0 15717 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_ACTUAL_SPEED_BITS 8 15718 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN0_ACTUAL_SPEED_SHIFT 0 15719 15720 15721 /**************************************************************************** 15722 * sys_device1 :: speed_debug_ln1 15723 */ 15724 /* sys_device1 :: speed_debug_ln1 :: LOS_counter [15:12] */ 15725 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_LOS_COUNTER_MASK 0xf000 15726 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_LOS_COUNTER_ALIGN 0 15727 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_LOS_COUNTER_BITS 4 15728 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_LOS_COUNTER_SHIFT 12 15729 15730 /* sys_device1 :: speed_debug_ln1 :: need_br_dfe [11:11] */ 15731 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_NEED_BR_DFE_MASK 0x0800 15732 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_NEED_BR_DFE_ALIGN 0 15733 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_NEED_BR_DFE_BITS 1 15734 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_NEED_BR_DFE_SHIFT 11 15735 15736 /* sys_device1 :: speed_debug_ln1 :: br_dfe_enabled [10:10] */ 15737 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_BR_DFE_ENABLED_MASK 0x0400 15738 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_BR_DFE_ENABLED_ALIGN 0 15739 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_BR_DFE_ENABLED_BITS 1 15740 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_BR_DFE_ENABLED_SHIFT 10 15741 15742 /* sys_device1 :: speed_debug_ln1 :: os_dfe_enabled [09:09] */ 15743 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_OS_DFE_ENABLED_MASK 0x0200 15744 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_OS_DFE_ENABLED_ALIGN 0 15745 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_OS_DFE_ENABLED_BITS 1 15746 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_OS_DFE_ENABLED_SHIFT 9 15747 15748 /* sys_device1 :: speed_debug_ln1 :: os_enabled [08:08] */ 15749 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_OS_ENABLED_MASK 0x0100 15750 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_OS_ENABLED_ALIGN 0 15751 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_OS_ENABLED_BITS 1 15752 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_OS_ENABLED_SHIFT 8 15753 15754 /* sys_device1 :: speed_debug_ln1 :: actual_speed [07:00] */ 15755 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_ACTUAL_SPEED_MASK 0x00ff 15756 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_ACTUAL_SPEED_ALIGN 0 15757 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_ACTUAL_SPEED_BITS 8 15758 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN1_ACTUAL_SPEED_SHIFT 0 15759 15760 15761 /**************************************************************************** 15762 * sys_device1 :: speed_debug_ln2 15763 */ 15764 /* sys_device1 :: speed_debug_ln2 :: LOS_counter [15:12] */ 15765 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_LOS_COUNTER_MASK 0xf000 15766 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_LOS_COUNTER_ALIGN 0 15767 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_LOS_COUNTER_BITS 4 15768 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_LOS_COUNTER_SHIFT 12 15769 15770 /* sys_device1 :: speed_debug_ln2 :: need_br_dfe [11:11] */ 15771 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_NEED_BR_DFE_MASK 0x0800 15772 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_NEED_BR_DFE_ALIGN 0 15773 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_NEED_BR_DFE_BITS 1 15774 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_NEED_BR_DFE_SHIFT 11 15775 15776 /* sys_device1 :: speed_debug_ln2 :: br_dfe_enabled [10:10] */ 15777 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_BR_DFE_ENABLED_MASK 0x0400 15778 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_BR_DFE_ENABLED_ALIGN 0 15779 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_BR_DFE_ENABLED_BITS 1 15780 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_BR_DFE_ENABLED_SHIFT 10 15781 15782 /* sys_device1 :: speed_debug_ln2 :: os_dfe_enabled [09:09] */ 15783 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_OS_DFE_ENABLED_MASK 0x0200 15784 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_OS_DFE_ENABLED_ALIGN 0 15785 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_OS_DFE_ENABLED_BITS 1 15786 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_OS_DFE_ENABLED_SHIFT 9 15787 15788 /* sys_device1 :: speed_debug_ln2 :: os_enabled [08:08] */ 15789 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_OS_ENABLED_MASK 0x0100 15790 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_OS_ENABLED_ALIGN 0 15791 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_OS_ENABLED_BITS 1 15792 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_OS_ENABLED_SHIFT 8 15793 15794 /* sys_device1 :: speed_debug_ln2 :: actual_speed [07:00] */ 15795 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_ACTUAL_SPEED_MASK 0x00ff 15796 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_ACTUAL_SPEED_ALIGN 0 15797 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_ACTUAL_SPEED_BITS 8 15798 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN2_ACTUAL_SPEED_SHIFT 0 15799 15800 15801 /**************************************************************************** 15802 * sys_device1 :: speed_debug_ln3 15803 */ 15804 /* sys_device1 :: speed_debug_ln3 :: LOS_counter [15:12] */ 15805 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_LOS_COUNTER_MASK 0xf000 15806 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_LOS_COUNTER_ALIGN 0 15807 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_LOS_COUNTER_BITS 4 15808 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_LOS_COUNTER_SHIFT 12 15809 15810 /* sys_device1 :: speed_debug_ln3 :: need_br_dfe [11:11] */ 15811 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_NEED_BR_DFE_MASK 0x0800 15812 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_NEED_BR_DFE_ALIGN 0 15813 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_NEED_BR_DFE_BITS 1 15814 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_NEED_BR_DFE_SHIFT 11 15815 15816 /* sys_device1 :: speed_debug_ln3 :: br_dfe_enabled [10:10] */ 15817 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_BR_DFE_ENABLED_MASK 0x0400 15818 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_BR_DFE_ENABLED_ALIGN 0 15819 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_BR_DFE_ENABLED_BITS 1 15820 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_BR_DFE_ENABLED_SHIFT 10 15821 15822 /* sys_device1 :: speed_debug_ln3 :: os_dfe_enabled [09:09] */ 15823 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_OS_DFE_ENABLED_MASK 0x0200 15824 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_OS_DFE_ENABLED_ALIGN 0 15825 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_OS_DFE_ENABLED_BITS 1 15826 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_OS_DFE_ENABLED_SHIFT 9 15827 15828 /* sys_device1 :: speed_debug_ln3 :: os_enabled [08:08] */ 15829 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_OS_ENABLED_MASK 0x0100 15830 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_OS_ENABLED_ALIGN 0 15831 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_OS_ENABLED_BITS 1 15832 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_OS_ENABLED_SHIFT 8 15833 15834 /* sys_device1 :: speed_debug_ln3 :: actual_speed [07:00] */ 15835 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_ACTUAL_SPEED_MASK 0x00ff 15836 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_ACTUAL_SPEED_ALIGN 0 15837 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_ACTUAL_SPEED_BITS 8 15838 #define PHY84328_SYS_DEV1_SPEED_DEBUG_LN3_ACTUAL_SPEED_SHIFT 0 15839 15840 15841 /**************************************************************************** 15842 * sys_device1 :: cl72_status_ln0 15843 */ 15844 /* sys_device1 :: cl72_status_ln0 :: temp_idx [15:12] */ 15845 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_TEMP_IDX_MASK 0xf000 15846 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_TEMP_IDX_ALIGN 0 15847 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_TEMP_IDX_BITS 4 15848 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_TEMP_IDX_SHIFT 12 15849 15850 /* sys_device1 :: cl72_status_ln0 :: dfe_tap1 [11:06] */ 15851 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_DFE_TAP1_MASK 0x0fc0 15852 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_DFE_TAP1_ALIGN 0 15853 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_DFE_TAP1_BITS 6 15854 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_DFE_TAP1_SHIFT 6 15855 15856 /* sys_device1 :: cl72_status_ln0 :: vga [05:00] */ 15857 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_VGA_MASK 0x003f 15858 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_VGA_ALIGN 0 15859 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_VGA_BITS 6 15860 #define PHY84328_SYS_DEV1_CL72_STATUS_LN0_VGA_SHIFT 0 15861 15862 15863 /**************************************************************************** 15864 * sys_device1 :: cl72_status_ln1 15865 */ 15866 /* sys_device1 :: cl72_status_ln1 :: temp_idx [15:12] */ 15867 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_TEMP_IDX_MASK 0xf000 15868 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_TEMP_IDX_ALIGN 0 15869 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_TEMP_IDX_BITS 4 15870 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_TEMP_IDX_SHIFT 12 15871 15872 /* sys_device1 :: cl72_status_ln1 :: dfe_tap1 [11:06] */ 15873 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_DFE_TAP1_MASK 0x0fc0 15874 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_DFE_TAP1_ALIGN 0 15875 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_DFE_TAP1_BITS 6 15876 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_DFE_TAP1_SHIFT 6 15877 15878 /* sys_device1 :: cl72_status_ln1 :: vga [05:00] */ 15879 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_VGA_MASK 0x003f 15880 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_VGA_ALIGN 0 15881 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_VGA_BITS 6 15882 #define PHY84328_SYS_DEV1_CL72_STATUS_LN1_VGA_SHIFT 0 15883 15884 15885 /**************************************************************************** 15886 * sys_device1 :: cl72_status_ln2 15887 */ 15888 /* sys_device1 :: cl72_status_ln2 :: temp_idx [15:12] */ 15889 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_TEMP_IDX_MASK 0xf000 15890 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_TEMP_IDX_ALIGN 0 15891 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_TEMP_IDX_BITS 4 15892 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_TEMP_IDX_SHIFT 12 15893 15894 /* sys_device1 :: cl72_status_ln2 :: dfe_tap1 [11:06] */ 15895 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_DFE_TAP1_MASK 0x0fc0 15896 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_DFE_TAP1_ALIGN 0 15897 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_DFE_TAP1_BITS 6 15898 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_DFE_TAP1_SHIFT 6 15899 15900 /* sys_device1 :: cl72_status_ln2 :: vga [05:00] */ 15901 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_VGA_MASK 0x003f 15902 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_VGA_ALIGN 0 15903 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_VGA_BITS 6 15904 #define PHY84328_SYS_DEV1_CL72_STATUS_LN2_VGA_SHIFT 0 15905 15906 15907 /**************************************************************************** 15908 * sys_device1 :: cl72_status_ln3 15909 */ 15910 /* sys_device1 :: cl72_status_ln3 :: temp_idx [15:12] */ 15911 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_TEMP_IDX_MASK 0xf000 15912 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_TEMP_IDX_ALIGN 0 15913 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_TEMP_IDX_BITS 4 15914 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_TEMP_IDX_SHIFT 12 15915 15916 /* sys_device1 :: cl72_status_ln3 :: dfe_tap1 [11:06] */ 15917 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_DFE_TAP1_MASK 0x0fc0 15918 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_DFE_TAP1_ALIGN 0 15919 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_DFE_TAP1_BITS 6 15920 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_DFE_TAP1_SHIFT 6 15921 15922 /* sys_device1 :: cl72_status_ln3 :: vga [05:00] */ 15923 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_VGA_MASK 0x003f 15924 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_VGA_ALIGN 0 15925 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_VGA_BITS 6 15926 #define PHY84328_SYS_DEV1_CL72_STATUS_LN3_VGA_SHIFT 0 15927 15928 15929 /**************************************************************************** 15930 * sys_device1 :: version 15931 */ 15932 /* sys_device1 :: version :: version [15:00] */ 15933 #define PHY84328_SYS_DEV1_VERSION_VERSION_MASK 0xffff 15934 #define PHY84328_SYS_DEV1_VERSION_VERSION_ALIGN 0 15935 #define PHY84328_SYS_DEV1_VERSION_VERSION_BITS 16 15936 #define PHY84328_SYS_DEV1_VERSION_VERSION_SHIFT 0 15937 15938 15939 /**************************************************************************** 15940 * sys_device1 :: target 15941 */ 15942 /* sys_device1 :: target :: target [15:00] */ 15943 #define PHY84328_SYS_DEV1_TARGET_TARGET_MASK 0xffff 15944 #define PHY84328_SYS_DEV1_TARGET_TARGET_ALIGN 0 15945 #define PHY84328_SYS_DEV1_TARGET_TARGET_BITS 16 15946 #define PHY84328_SYS_DEV1_TARGET_TARGET_SHIFT 0 15947 15948 15949 /**************************************************************************** 15950 * sys_device1 :: firmware_mode 15951 */ 15952 /* sys_device1 :: firmware_mode :: LN3_mode [15:12] */ 15953 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN3_MODE_MASK 0xf000 15954 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN3_MODE_ALIGN 0 15955 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN3_MODE_BITS 4 15956 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN3_MODE_SHIFT 12 15957 15958 /* sys_device1 :: firmware_mode :: LN2_mode [11:08] */ 15959 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN2_MODE_MASK 0x0f00 15960 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN2_MODE_ALIGN 0 15961 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN2_MODE_BITS 4 15962 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN2_MODE_SHIFT 8 15963 15964 /* sys_device1 :: firmware_mode :: LN1_mode [07:04] */ 15965 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN1_MODE_MASK 0x00f0 15966 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN1_MODE_ALIGN 0 15967 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN1_MODE_BITS 4 15968 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN1_MODE_SHIFT 4 15969 15970 /* sys_device1 :: firmware_mode :: LN0_mode [03:00] */ 15971 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN0_MODE_MASK 0x000f 15972 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN0_MODE_ALIGN 0 15973 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN0_MODE_BITS 4 15974 #define PHY84328_SYS_DEV1_FIRMWARE_MODE_LN0_MODE_SHIFT 0 15975 15976 15977 /**************************************************************************** 15978 * sys_device1 :: gpio_ctrl_ln0 15979 */ 15980 /* sys_device1 :: gpio_ctrl_ln0 :: GPIO_CTRL_LN0 [15:00] */ 15981 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_MASK 0xffff 15982 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_ALIGN 0 15983 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_BITS 16 15984 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN0_GPIO_CTRL_LN0_SHIFT 0 15985 15986 15987 /**************************************************************************** 15988 * sys_device1 :: gpio_ctrl_ln1 15989 */ 15990 /* sys_device1 :: gpio_ctrl_ln1 :: GPIO_CTRL_LN1 [15:00] */ 15991 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_MASK 0xffff 15992 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_ALIGN 0 15993 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_BITS 16 15994 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN1_GPIO_CTRL_LN1_SHIFT 0 15995 15996 15997 /**************************************************************************** 15998 * sys_device1 :: gpio_ctrl_ln2 15999 */ 16000 /* sys_device1 :: gpio_ctrl_ln2 :: GPIO_CTRL_LN2 [15:00] */ 16001 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_MASK 0xffff 16002 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_ALIGN 0 16003 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_BITS 16 16004 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN2_GPIO_CTRL_LN2_SHIFT 0 16005 16006 16007 /**************************************************************************** 16008 * sys_device1 :: gpio_ctrl_ln3 16009 */ 16010 /* sys_device1 :: gpio_ctrl_ln3 :: GPIO_CTRL_LN3 [15:00] */ 16011 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_MASK 0xffff 16012 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_ALIGN 0 16013 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_BITS 16 16014 #define PHY84328_SYS_DEV1_GPIO_CTRL_LN3_GPIO_CTRL_LN3_SHIFT 0 16015 16016 16017 /**************************************************************************** 16018 * sys_device1 :: gpio_sts_ln0 16019 */ 16020 /* sys_device1 :: gpio_sts_ln0 :: GPIO_STS_LN0 [15:00] */ 16021 #define PHY84328_SYS_DEV1_GPIO_STS_LN0_GPIO_STS_LN0_MASK 0xffff 16022 #define PHY84328_SYS_DEV1_GPIO_STS_LN0_GPIO_STS_LN0_ALIGN 0 16023 #define PHY84328_SYS_DEV1_GPIO_STS_LN0_GPIO_STS_LN0_BITS 16 16024 #define PHY84328_SYS_DEV1_GPIO_STS_LN0_GPIO_STS_LN0_SHIFT 0 16025 16026 16027 /**************************************************************************** 16028 * sys_device1 :: gpio_sts_ln1 16029 */ 16030 /* sys_device1 :: gpio_sts_ln1 :: GPIO_STS_LN1 [15:00] */ 16031 #define PHY84328_SYS_DEV1_GPIO_STS_LN1_GPIO_STS_LN1_MASK 0xffff 16032 #define PHY84328_SYS_DEV1_GPIO_STS_LN1_GPIO_STS_LN1_ALIGN 0 16033 #define PHY84328_SYS_DEV1_GPIO_STS_LN1_GPIO_STS_LN1_BITS 16 16034 #define PHY84328_SYS_DEV1_GPIO_STS_LN1_GPIO_STS_LN1_SHIFT 0 16035 16036 16037 /**************************************************************************** 16038 * sys_device1 :: gpio_sts_ln2 16039 */ 16040 /* sys_device1 :: gpio_sts_ln2 :: GPIO_STS_LN2 [15:00] */ 16041 #define PHY84328_SYS_DEV1_GPIO_STS_LN2_GPIO_STS_LN2_MASK 0xffff 16042 #define PHY84328_SYS_DEV1_GPIO_STS_LN2_GPIO_STS_LN2_ALIGN 0 16043 #define PHY84328_SYS_DEV1_GPIO_STS_LN2_GPIO_STS_LN2_BITS 16 16044 #define PHY84328_SYS_DEV1_GPIO_STS_LN2_GPIO_STS_LN2_SHIFT 0 16045 16046 16047 /**************************************************************************** 16048 * sys_device1 :: gpio_sts_ln3 16049 */ 16050 /* sys_device1 :: gpio_sts_ln3 :: GPIO_STS_LN3 [15:00] */ 16051 #define PHY84328_SYS_DEV1_GPIO_STS_LN3_GPIO_STS_LN3_MASK 0xffff 16052 #define PHY84328_SYS_DEV1_GPIO_STS_LN3_GPIO_STS_LN3_ALIGN 0 16053 #define PHY84328_SYS_DEV1_GPIO_STS_LN3_GPIO_STS_LN3_BITS 16 16054 #define PHY84328_SYS_DEV1_GPIO_STS_LN3_GPIO_STS_LN3_SHIFT 0 16055 16056 16057 /**************************************************************************** 16058 * sys_device1 :: regB 16059 */ 16060 /* sys_device1 :: regB :: reserved_for_eco0 [15:00] */ 16061 #define PHY84328_SYS_DEV1_REGB_RESERVED_FOR_ECO0_MASK 0xffff 16062 #define PHY84328_SYS_DEV1_REGB_RESERVED_FOR_ECO0_ALIGN 0 16063 #define PHY84328_SYS_DEV1_REGB_RESERVED_FOR_ECO0_BITS 16 16064 #define PHY84328_SYS_DEV1_REGB_RESERVED_FOR_ECO0_SHIFT 0 16065 16066 16067 /**************************************************************************** 16068 * sys_device1 :: tuning_state_bypass 16069 */ 16070 /* sys_device1 :: tuning_state_bypass :: reserved_for_eco0 [15:09] */ 16071 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_MASK 0xfe00 16072 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_ALIGN 0 16073 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_BITS 7 16074 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_RESERVED_FOR_ECO0_SHIFT 9 16075 16076 /* sys_device1 :: tuning_state_bypass :: bypass_steady_state_tuning [08:08] */ 16077 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_MASK 0x0100 16078 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_ALIGN 0 16079 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_BITS 1 16080 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_STEADY_STATE_TUNING_SHIFT 8 16081 16082 /* sys_device1 :: tuning_state_bypass :: bypass_cdr_lock_monitor [07:07] */ 16083 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_MASK 0x0080 16084 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_ALIGN 0 16085 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_BITS 1 16086 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_CDR_LOCK_MONITOR_SHIFT 7 16087 16088 /* sys_device1 :: tuning_state_bypass :: bypass_dcd_tuning [06:06] */ 16089 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_MASK 0x0040 16090 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_ALIGN 0 16091 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_BITS 1 16092 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_DCD_TUNING_SHIFT 6 16093 16094 /* sys_device1 :: tuning_state_bypass :: bypass_slicer_offset_tuning [05:05] */ 16095 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_MASK 0x0020 16096 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_ALIGN 0 16097 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_BITS 1 16098 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_OFFSET_TUNING_SHIFT 5 16099 16100 /* sys_device1 :: tuning_state_bypass :: bypass_slicer_target_tuning [04:04] */ 16101 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_MASK 0x0010 16102 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_ALIGN 0 16103 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_BITS 1 16104 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_SLICER_TARGET_TUNING_SHIFT 4 16105 16106 /* sys_device1 :: tuning_state_bypass :: bypass_vga_bias_tuning [03:03] */ 16107 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_MASK 0x0008 16108 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_ALIGN 0 16109 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_BITS 1 16110 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_VGA_BIAS_TUNING_SHIFT 3 16111 16112 /* sys_device1 :: tuning_state_bypass :: bypass_pf_tuning [02:02] */ 16113 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_MASK 0x0004 16114 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_ALIGN 0 16115 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_BITS 1 16116 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_PF_TUNING_SHIFT 2 16117 16118 /* sys_device1 :: tuning_state_bypass :: bypass_clk90_tuning [01:01] */ 16119 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_MASK 0x0002 16120 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_ALIGN 0 16121 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_BITS 1 16122 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_CLK90_TUNING_SHIFT 1 16123 16124 /* sys_device1 :: tuning_state_bypass :: bypass_os_vga_tuning [00:00] */ 16125 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_MASK 0x0001 16126 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_ALIGN 0 16127 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_BITS 1 16128 #define PHY84328_SYS_DEV1_TUNING_STATE_BYPASS_BYPASS_OS_VGA_TUNING_SHIFT 0 16129 16130 16131 /**************************************************************************** 16132 * sys_device1 :: temperature 16133 */ 16134 /* sys_device1 :: temperature :: force_temperature [15:15] */ 16135 #define PHY84328_SYS_DEV1_TEMPERATURE_FORCE_TEMPERATURE_MASK 0x8000 16136 #define PHY84328_SYS_DEV1_TEMPERATURE_FORCE_TEMPERATURE_ALIGN 0 16137 #define PHY84328_SYS_DEV1_TEMPERATURE_FORCE_TEMPERATURE_BITS 1 16138 #define PHY84328_SYS_DEV1_TEMPERATURE_FORCE_TEMPERATURE_SHIFT 15 16139 16140 /* sys_device1 :: temperature :: reserved_for_eco0 [14:14] */ 16141 #define PHY84328_SYS_DEV1_TEMPERATURE_RESERVED_FOR_ECO0_MASK 0x4000 16142 #define PHY84328_SYS_DEV1_TEMPERATURE_RESERVED_FOR_ECO0_ALIGN 0 16143 #define PHY84328_SYS_DEV1_TEMPERATURE_RESERVED_FOR_ECO0_BITS 1 16144 #define PHY84328_SYS_DEV1_TEMPERATURE_RESERVED_FOR_ECO0_SHIFT 14 16145 16146 /* sys_device1 :: temperature :: temp_idx [13:10] */ 16147 #define PHY84328_SYS_DEV1_TEMPERATURE_TEMP_IDX_MASK 0x3c00 16148 #define PHY84328_SYS_DEV1_TEMPERATURE_TEMP_IDX_ALIGN 0 16149 #define PHY84328_SYS_DEV1_TEMPERATURE_TEMP_IDX_BITS 4 16150 #define PHY84328_SYS_DEV1_TEMPERATURE_TEMP_IDX_SHIFT 10 16151 16152 /* sys_device1 :: temperature :: temperature [09:00] */ 16153 #define PHY84328_SYS_DEV1_TEMPERATURE_TEMPERATURE_MASK 0x03ff 16154 #define PHY84328_SYS_DEV1_TEMPERATURE_TEMPERATURE_ALIGN 0 16155 #define PHY84328_SYS_DEV1_TEMPERATURE_TEMPERATURE_BITS 10 16156 #define PHY84328_SYS_DEV1_TEMPERATURE_TEMPERATURE_SHIFT 0 16157 16158 16159 /**************************************************************************** 16160 * sys_device1 :: crc 16161 */ 16162 /* sys_device1 :: crc :: crc [15:00] */ 16163 #define PHY84328_SYS_DEV1_CRC_CRC_MASK 0xffff 16164 #define PHY84328_SYS_DEV1_CRC_CRC_ALIGN 0 16165 #define PHY84328_SYS_DEV1_CRC_CRC_BITS 16 16166 #define PHY84328_SYS_DEV1_CRC_CRC_SHIFT 0 16167 16168 16169 /**************************************************************************** 16170 * sys_device1_PMD_Standard_Registers 16171 */ 16172 /**************************************************************************** 16173 * sys_device1 :: pmd_control_register 16174 */ 16175 /* sys_device1 :: pmd_control_register :: reset [15:15] */ 16176 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESET_MASK 0x8000 16177 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESET_ALIGN 0 16178 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESET_BITS 1 16179 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESET_SHIFT 15 16180 16181 /* sys_device1 :: pmd_control_register :: reserved0 [14:14] */ 16182 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED0_MASK 0x4000 16183 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED0_ALIGN 0 16184 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED0_BITS 1 16185 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED0_SHIFT 14 16186 16187 /* sys_device1 :: pmd_control_register :: speed_selectionlsb [13:13] */ 16188 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_MASK 0x2000 16189 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_ALIGN 0 16190 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_BITS 1 16191 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_SHIFT 13 16192 16193 /* sys_device1 :: pmd_control_register :: reserved1 [12:12] */ 16194 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED1_MASK 0x1000 16195 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED1_ALIGN 0 16196 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED1_BITS 1 16197 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED1_SHIFT 12 16198 16199 /* sys_device1 :: pmd_control_register :: power_down [11:11] */ 16200 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_POWER_DOWN_MASK 0x0800 16201 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_POWER_DOWN_ALIGN 0 16202 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_POWER_DOWN_BITS 1 16203 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_POWER_DOWN_SHIFT 11 16204 16205 /* sys_device1 :: pmd_control_register :: reserved2 [10:07] */ 16206 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED2_MASK 0x0780 16207 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED2_ALIGN 0 16208 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED2_BITS 4 16209 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED2_SHIFT 7 16210 16211 /* sys_device1 :: pmd_control_register :: speed_selectionmsb [06:06] */ 16212 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_MASK 0x0040 16213 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_ALIGN 0 16214 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_BITS 1 16215 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_SHIFT 6 16216 16217 /* sys_device1 :: pmd_control_register :: speed_selection [05:02] */ 16218 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTION_MASK 0x003c 16219 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTION_ALIGN 0 16220 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTION_BITS 4 16221 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_SPEED_SELECTION_SHIFT 2 16222 16223 /* sys_device1 :: pmd_control_register :: reserved3 [01:01] */ 16224 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED3_MASK 0x0002 16225 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED3_ALIGN 0 16226 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED3_BITS 1 16227 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_RESERVED3_SHIFT 1 16228 16229 /* sys_device1 :: pmd_control_register :: pma_loopback [00:00] */ 16230 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_PMA_LOOPBACK_MASK 0x0001 16231 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_PMA_LOOPBACK_ALIGN 0 16232 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_PMA_LOOPBACK_BITS 1 16233 #define PHY84328_SYS_DEV1_PMD_CONTROL_REGISTER_PMA_LOOPBACK_SHIFT 0 16234 16235 16236 /**************************************************************************** 16237 * sys_device1 :: status_register 16238 */ 16239 /* sys_device1 :: status_register :: reserved0 [15:08] */ 16240 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED0_MASK 0xff00 16241 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED0_ALIGN 0 16242 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED0_BITS 8 16243 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED0_SHIFT 8 16244 16245 /* sys_device1 :: status_register :: fault [07:07] */ 16246 #define PHY84328_SYS_DEV1_STATUS_REGISTER_FAULT_MASK 0x0080 16247 #define PHY84328_SYS_DEV1_STATUS_REGISTER_FAULT_ALIGN 0 16248 #define PHY84328_SYS_DEV1_STATUS_REGISTER_FAULT_BITS 1 16249 #define PHY84328_SYS_DEV1_STATUS_REGISTER_FAULT_SHIFT 7 16250 16251 /* sys_device1 :: status_register :: reserved1 [06:03] */ 16252 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED1_MASK 0x0078 16253 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED1_ALIGN 0 16254 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED1_BITS 4 16255 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED1_SHIFT 3 16256 16257 /* sys_device1 :: status_register :: receive_link_status [02:02] */ 16258 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RECEIVE_LINK_STATUS_MASK 0x0004 16259 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RECEIVE_LINK_STATUS_ALIGN 0 16260 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RECEIVE_LINK_STATUS_BITS 1 16261 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RECEIVE_LINK_STATUS_SHIFT 2 16262 16263 /* sys_device1 :: status_register :: low_power_ability [01:01] */ 16264 #define PHY84328_SYS_DEV1_STATUS_REGISTER_LOW_POWER_ABILITY_MASK 0x0002 16265 #define PHY84328_SYS_DEV1_STATUS_REGISTER_LOW_POWER_ABILITY_ALIGN 0 16266 #define PHY84328_SYS_DEV1_STATUS_REGISTER_LOW_POWER_ABILITY_BITS 1 16267 #define PHY84328_SYS_DEV1_STATUS_REGISTER_LOW_POWER_ABILITY_SHIFT 1 16268 16269 /* sys_device1 :: status_register :: reserved2 [00:00] */ 16270 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED2_MASK 0x0001 16271 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED2_ALIGN 0 16272 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED2_BITS 1 16273 #define PHY84328_SYS_DEV1_STATUS_REGISTER_RESERVED2_SHIFT 0 16274 16275 16276 /**************************************************************************** 16277 * sys_device1 :: pmd_identifier_register_0 16278 */ 16279 /* sys_device1 :: pmd_identifier_register_0 :: device_id_0 [15:00] */ 16280 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_MASK 0xffff 16281 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_ALIGN 0 16282 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_BITS 16 16283 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_SHIFT 0 16284 16285 16286 /**************************************************************************** 16287 * sys_device1 :: pmd_identifier_register_1 16288 */ 16289 /* sys_device1 :: pmd_identifier_register_1 :: device_id_1 [15:00] */ 16290 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_MASK 0xffff 16291 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_ALIGN 0 16292 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_BITS 16 16293 #define PHY84328_SYS_DEV1_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_SHIFT 0 16294 16295 16296 /**************************************************************************** 16297 * sys_device1 :: pmd_speed_ability 16298 */ 16299 /* sys_device1 :: pmd_speed_ability :: reserved0 [15:09] */ 16300 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED0_MASK 0xfe00 16301 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED0_ALIGN 0 16302 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED0_BITS 7 16303 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED0_SHIFT 9 16304 16305 /* sys_device1 :: pmd_speed_ability :: fortyG_capable [08:08] */ 16306 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_FORTYG_CAPABLE_MASK 0x0100 16307 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_FORTYG_CAPABLE_ALIGN 0 16308 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_FORTYG_CAPABLE_BITS 1 16309 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_FORTYG_CAPABLE_SHIFT 8 16310 16311 /* sys_device1 :: pmd_speed_ability :: reserved1 [07:05] */ 16312 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED1_MASK 0x00e0 16313 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED1_ALIGN 0 16314 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED1_BITS 3 16315 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED1_SHIFT 5 16316 16317 /* sys_device1 :: pmd_speed_ability :: oneG_capable [04:04] */ 16318 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_ONEG_CAPABLE_MASK 0x0010 16319 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_ONEG_CAPABLE_ALIGN 0 16320 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_ONEG_CAPABLE_BITS 1 16321 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_ONEG_CAPABLE_SHIFT 4 16322 16323 /* sys_device1 :: pmd_speed_ability :: reserved2 [03:01] */ 16324 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED2_MASK 0x000e 16325 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED2_ALIGN 0 16326 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED2_BITS 3 16327 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_RESERVED2_SHIFT 1 16328 16329 /* sys_device1 :: pmd_speed_ability :: tenG_capable [00:00] */ 16330 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_TENG_CAPABLE_MASK 0x0001 16331 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_TENG_CAPABLE_ALIGN 0 16332 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_TENG_CAPABLE_BITS 1 16333 #define PHY84328_SYS_DEV1_PMD_SPEED_ABILITY_TENG_CAPABLE_SHIFT 0 16334 16335 16336 /**************************************************************************** 16337 * sys_device1 :: devices_in_package1 16338 */ 16339 /* sys_device1 :: devices_in_package1 :: reserved0 [15:12] */ 16340 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_RESERVED0_MASK 0xf000 16341 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_RESERVED0_ALIGN 0 16342 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_RESERVED0_BITS 4 16343 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_RESERVED0_SHIFT 12 16344 16345 /* sys_device1 :: devices_in_package1 :: Seperate_PMA_4_Present [11:11] */ 16346 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_4_PRESENT_MASK 0x0800 16347 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_4_PRESENT_ALIGN 0 16348 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_4_PRESENT_BITS 1 16349 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_4_PRESENT_SHIFT 11 16350 16351 /* sys_device1 :: devices_in_package1 :: Seperate_PMA_3_Present [10:10] */ 16352 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_3_PRESENT_MASK 0x0400 16353 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_3_PRESENT_ALIGN 0 16354 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_3_PRESENT_BITS 1 16355 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_3_PRESENT_SHIFT 10 16356 16357 /* sys_device1 :: devices_in_package1 :: Seperate_PMA_2_Present [09:09] */ 16358 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_2_PRESENT_MASK 0x0200 16359 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_2_PRESENT_ALIGN 0 16360 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_2_PRESENT_BITS 1 16361 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_2_PRESENT_SHIFT 9 16362 16363 /* sys_device1 :: devices_in_package1 :: Seperate_PMA_1_Present [08:08] */ 16364 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_1_PRESENT_MASK 0x0100 16365 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_1_PRESENT_ALIGN 0 16366 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_1_PRESENT_BITS 1 16367 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_SEPERATE_PMA_1_PRESENT_SHIFT 8 16368 16369 /* sys_device1 :: devices_in_package1 :: ang_present [07:07] */ 16370 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_ANG_PRESENT_MASK 0x0080 16371 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_ANG_PRESENT_ALIGN 0 16372 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_ANG_PRESENT_BITS 1 16373 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_ANG_PRESENT_SHIFT 7 16374 16375 /* sys_device1 :: devices_in_package1 :: tc_present [06:06] */ 16376 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_TC_PRESENT_MASK 0x0040 16377 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_TC_PRESENT_ALIGN 0 16378 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_TC_PRESENT_BITS 1 16379 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_TC_PRESENT_SHIFT 6 16380 16381 /* sys_device1 :: devices_in_package1 :: dte_xs_present [05:05] */ 16382 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_DTE_XS_PRESENT_MASK 0x0020 16383 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_DTE_XS_PRESENT_ALIGN 0 16384 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_DTE_XS_PRESENT_BITS 1 16385 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_DTE_XS_PRESENT_SHIFT 5 16386 16387 /* sys_device1 :: devices_in_package1 :: phy_xs_present [04:04] */ 16388 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PHY_XS_PRESENT_MASK 0x0010 16389 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PHY_XS_PRESENT_ALIGN 0 16390 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PHY_XS_PRESENT_BITS 1 16391 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PHY_XS_PRESENT_SHIFT 4 16392 16393 /* sys_device1 :: devices_in_package1 :: pcs_present [03:03] */ 16394 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PCS_PRESENT_MASK 0x0008 16395 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PCS_PRESENT_ALIGN 0 16396 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PCS_PRESENT_BITS 1 16397 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PCS_PRESENT_SHIFT 3 16398 16399 /* sys_device1 :: devices_in_package1 :: wis_present [02:02] */ 16400 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_WIS_PRESENT_MASK 0x0004 16401 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_WIS_PRESENT_ALIGN 0 16402 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_WIS_PRESENT_BITS 1 16403 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_WIS_PRESENT_SHIFT 2 16404 16405 /* sys_device1 :: devices_in_package1 :: pmd_pmapresent [01:01] */ 16406 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PMD_PMAPRESENT_MASK 0x0002 16407 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PMD_PMAPRESENT_ALIGN 0 16408 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PMD_PMAPRESENT_BITS 1 16409 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_PMD_PMAPRESENT_SHIFT 1 16410 16411 /* sys_device1 :: devices_in_package1 :: clause_22registers_present [00:00] */ 16412 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_CLAUSE_22REGISTERS_PRESENT_MASK 0x0001 16413 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_CLAUSE_22REGISTERS_PRESENT_ALIGN 0 16414 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_CLAUSE_22REGISTERS_PRESENT_BITS 1 16415 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE1_CLAUSE_22REGISTERS_PRESENT_SHIFT 0 16416 16417 16418 /**************************************************************************** 16419 * sys_device1 :: devices_in_package_2 16420 */ 16421 /* sys_device1 :: devices_in_package_2 :: vendor_specificdevice_2_present [15:15] */ 16422 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_MASK 0x8000 16423 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_ALIGN 0 16424 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_BITS 1 16425 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_SHIFT 15 16426 16427 /* sys_device1 :: devices_in_package_2 :: vendor_specificdevice_1_present [14:14] */ 16428 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_MASK 0x4000 16429 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_ALIGN 0 16430 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_BITS 1 16431 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_SHIFT 14 16432 16433 /* sys_device1 :: devices_in_package_2 :: clause_22extension_present [13:13] */ 16434 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_MASK 0x2000 16435 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_ALIGN 0 16436 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_BITS 1 16437 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_SHIFT 13 16438 16439 /* sys_device1 :: devices_in_package_2 :: reserved0 [12:00] */ 16440 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_RESERVED0_MASK 0x1fff 16441 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_RESERVED0_ALIGN 0 16442 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_RESERVED0_BITS 13 16443 #define PHY84328_SYS_DEV1_DEVICES_IN_PACKAGE_2_RESERVED0_SHIFT 0 16444 16445 16446 /**************************************************************************** 16447 * sys_device1 :: pmd_control_2_register 16448 */ 16449 /* sys_device1 :: pmd_control_2_register :: reserved0 [15:06] */ 16450 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER_RESERVED0_MASK 0xffc0 16451 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER_RESERVED0_ALIGN 0 16452 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER_RESERVED0_BITS 10 16453 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER_RESERVED0_SHIFT 6 16454 16455 /* sys_device1 :: pmd_control_2_register :: pma_typeselection [05:00] */ 16456 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_MASK 0x003f 16457 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_ALIGN 0 16458 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_BITS 6 16459 #define PHY84328_SYS_DEV1_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_SHIFT 0 16460 16461 16462 /**************************************************************************** 16463 * sys_device1 :: status_register_2 16464 */ 16465 /* sys_device1 :: status_register_2 :: device_present [15:14] */ 16466 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_DEVICE_PRESENT_MASK 0xc000 16467 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_DEVICE_PRESENT_ALIGN 0 16468 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_DEVICE_PRESENT_BITS 2 16469 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_DEVICE_PRESENT_SHIFT 14 16470 16471 /* sys_device1 :: status_register_2 :: transmit_localfault_ability [13:13] */ 16472 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_MASK 0x2000 16473 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_ALIGN 0 16474 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_BITS 1 16475 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_SHIFT 13 16476 16477 /* sys_device1 :: status_register_2 :: receive_localfault_ability [12:12] */ 16478 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_MASK 0x1000 16479 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_ALIGN 0 16480 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_BITS 1 16481 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_SHIFT 12 16482 16483 /* sys_device1 :: status_register_2 :: transmit_localfault [11:11] */ 16484 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_MASK 0x0800 16485 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ALIGN 0 16486 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_BITS 1 16487 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_SHIFT 11 16488 16489 /* sys_device1 :: status_register_2 :: receive_localfault [10:10] */ 16490 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_MASK 0x0400 16491 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ALIGN 0 16492 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_BITS 1 16493 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_SHIFT 10 16494 16495 /* sys_device1 :: status_register_2 :: extended_abilities [09:09] */ 16496 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_EXTENDED_ABILITIES_MASK 0x0200 16497 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_EXTENDED_ABILITIES_ALIGN 0 16498 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_EXTENDED_ABILITIES_BITS 1 16499 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_EXTENDED_ABILITIES_SHIFT 9 16500 16501 /* sys_device1 :: status_register_2 :: pmd_transmitdisable_ability [08:08] */ 16502 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_MASK 0x0100 16503 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_ALIGN 0 16504 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_BITS 1 16505 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_SHIFT 8 16506 16507 /* sys_device1 :: status_register_2 :: tengbase_srability [07:07] */ 16508 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_SRABILITY_MASK 0x0080 16509 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_SRABILITY_ALIGN 0 16510 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_SRABILITY_BITS 1 16511 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_SRABILITY_SHIFT 7 16512 16513 /* sys_device1 :: status_register_2 :: tengbase_lrability [06:06] */ 16514 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LRABILITY_MASK 0x0040 16515 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LRABILITY_ALIGN 0 16516 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LRABILITY_BITS 1 16517 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LRABILITY_SHIFT 6 16518 16519 /* sys_device1 :: status_register_2 :: tengbase_erability [05:05] */ 16520 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_ERABILITY_MASK 0x0020 16521 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_ERABILITY_ALIGN 0 16522 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_ERABILITY_BITS 1 16523 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_ERABILITY_SHIFT 5 16524 16525 /* sys_device1 :: status_register_2 :: tengbase_lx4ability [04:04] */ 16526 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LX4ABILITY_MASK 0x0010 16527 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LX4ABILITY_ALIGN 0 16528 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LX4ABILITY_BITS 1 16529 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LX4ABILITY_SHIFT 4 16530 16531 /* sys_device1 :: status_register_2 :: tengbase_swability [03:03] */ 16532 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_SWABILITY_MASK 0x0008 16533 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_SWABILITY_ALIGN 0 16534 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_SWABILITY_BITS 1 16535 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_SWABILITY_SHIFT 3 16536 16537 /* sys_device1 :: status_register_2 :: tengbase_lwability [02:02] */ 16538 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LWABILITY_MASK 0x0004 16539 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LWABILITY_ALIGN 0 16540 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LWABILITY_BITS 1 16541 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_LWABILITY_SHIFT 2 16542 16543 /* sys_device1 :: status_register_2 :: tengbase_ewability [01:01] */ 16544 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_EWABILITY_MASK 0x0002 16545 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_EWABILITY_ALIGN 0 16546 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_EWABILITY_BITS 1 16547 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_TENGBASE_EWABILITY_SHIFT 1 16548 16549 /* sys_device1 :: status_register_2 :: pma_local_loopbackability [00:00] */ 16550 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACKABILITY_MASK 0x0001 16551 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACKABILITY_ALIGN 0 16552 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACKABILITY_BITS 1 16553 #define PHY84328_SYS_DEV1_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACKABILITY_SHIFT 0 16554 16555 16556 /**************************************************************************** 16557 * sys_device1 :: pmd_receive_signal_detect_register 16558 */ 16559 /* sys_device1 :: pmd_receive_signal_detect_register :: reserved0 [15:05] */ 16560 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_MASK 0xffe0 16561 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_ALIGN 0 16562 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_BITS 11 16563 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_SHIFT 5 16564 16565 /* sys_device1 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_3 [04:04] */ 16566 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_MASK 0x0010 16567 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_ALIGN 0 16568 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_BITS 1 16569 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_SHIFT 4 16570 16571 /* sys_device1 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_2 [03:03] */ 16572 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_MASK 0x0008 16573 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_ALIGN 0 16574 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_BITS 1 16575 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_SHIFT 3 16576 16577 /* sys_device1 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_1 [02:02] */ 16578 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_MASK 0x0004 16579 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_ALIGN 0 16580 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_BITS 1 16581 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_SHIFT 2 16582 16583 /* sys_device1 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_0 [01:01] */ 16584 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_MASK 0x0002 16585 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_ALIGN 0 16586 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_BITS 1 16587 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_SHIFT 1 16588 16589 /* sys_device1 :: pmd_receive_signal_detect_register :: global_pmdreceive_signal_ok [00:00] */ 16590 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_MASK 0x0001 16591 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_ALIGN 0 16592 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_BITS 1 16593 #define PHY84328_SYS_DEV1_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_SHIFT 0 16594 16595 16596 /**************************************************************************** 16597 * sys_device1 :: pmd_extended_ability_register 16598 */ 16599 /* sys_device1 :: pmd_extended_ability_register :: reserved0 [15:11] */ 16600 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_MASK 0xf800 16601 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_ALIGN 0 16602 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_BITS 5 16603 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_SHIFT 11 16604 16605 /* sys_device1 :: pmd_extended_ability_register :: fortygbase_tability [10:10] */ 16606 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_TABILITY_MASK 0x0400 16607 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_TABILITY_ALIGN 0 16608 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_TABILITY_BITS 1 16609 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_TABILITY_SHIFT 10 16610 16611 /* sys_device1 :: pmd_extended_ability_register :: reserved1 [09:09] */ 16612 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_MASK 0x0200 16613 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_ALIGN 0 16614 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_BITS 1 16615 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_SHIFT 9 16616 16617 /* sys_device1 :: pmd_extended_ability_register :: tenbase_tability [08:08] */ 16618 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_TABILITY_MASK 0x0100 16619 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_TABILITY_ALIGN 0 16620 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_TABILITY_BITS 1 16621 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_TABILITY_SHIFT 8 16622 16623 /* sys_device1 :: pmd_extended_ability_register :: hundredbase_tx_ability [07:07] */ 16624 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_MASK 0x0080 16625 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_ALIGN 0 16626 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_BITS 1 16627 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_SHIFT 7 16628 16629 /* sys_device1 :: pmd_extended_ability_register :: gigbase_kxability [06:06] */ 16630 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KXABILITY_MASK 0x0040 16631 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KXABILITY_ALIGN 0 16632 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KXABILITY_BITS 1 16633 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KXABILITY_SHIFT 6 16634 16635 /* sys_device1 :: pmd_extended_ability_register :: gigbase_tability [05:05] */ 16636 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_TABILITY_MASK 0x0020 16637 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_TABILITY_ALIGN 0 16638 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_TABILITY_BITS 1 16639 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_TABILITY_SHIFT 5 16640 16641 /* sys_device1 :: pmd_extended_ability_register :: tengbase_krability [04:04] */ 16642 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KRABILITY_MASK 0x0010 16643 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KRABILITY_ALIGN 0 16644 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KRABILITY_BITS 1 16645 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KRABILITY_SHIFT 4 16646 16647 /* sys_device1 :: pmd_extended_ability_register :: tengbase_kx4ability [03:03] */ 16648 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4ABILITY_MASK 0x0008 16649 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4ABILITY_ALIGN 0 16650 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4ABILITY_BITS 1 16651 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4ABILITY_SHIFT 3 16652 16653 /* sys_device1 :: pmd_extended_ability_register :: tengbase_tability [02:02] */ 16654 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_TABILITY_MASK 0x0004 16655 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_TABILITY_ALIGN 0 16656 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_TABILITY_BITS 1 16657 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_TABILITY_SHIFT 2 16658 16659 /* sys_device1 :: pmd_extended_ability_register :: tengbase_lrmability [01:01] */ 16660 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRMABILITY_MASK 0x0002 16661 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRMABILITY_ALIGN 0 16662 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRMABILITY_BITS 1 16663 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRMABILITY_SHIFT 1 16664 16665 /* sys_device1 :: pmd_extended_ability_register :: tengbase_cx4ability [00:00] */ 16666 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4ABILITY_MASK 0x0001 16667 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4ABILITY_ALIGN 0 16668 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4ABILITY_BITS 1 16669 #define PHY84328_SYS_DEV1_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4ABILITY_SHIFT 0 16670 16671 16672 /**************************************************************************** 16673 * sys_device1 :: pmd_oui_id0_register 16674 */ 16675 /* sys_device1 :: pmd_oui_id0_register :: pmd_form_id_0 [15:00] */ 16676 #define PHY84328_SYS_DEV1_PMD_OUI_ID0_REGISTER_PMD_FORM_ID_0_MASK 0xffff 16677 #define PHY84328_SYS_DEV1_PMD_OUI_ID0_REGISTER_PMD_FORM_ID_0_ALIGN 0 16678 #define PHY84328_SYS_DEV1_PMD_OUI_ID0_REGISTER_PMD_FORM_ID_0_BITS 16 16679 #define PHY84328_SYS_DEV1_PMD_OUI_ID0_REGISTER_PMD_FORM_ID_0_SHIFT 0 16680 16681 16682 /**************************************************************************** 16683 * sys_device1 :: pmd_oui_id1_reg 16684 */ 16685 /* sys_device1 :: pmd_oui_id1_reg :: pmd_form_id_1 [15:00] */ 16686 #define PHY84328_SYS_DEV1_PMD_OUI_ID1_REG_PMD_FORM_ID_1_MASK 0xffff 16687 #define PHY84328_SYS_DEV1_PMD_OUI_ID1_REG_PMD_FORM_ID_1_ALIGN 0 16688 #define PHY84328_SYS_DEV1_PMD_OUI_ID1_REG_PMD_FORM_ID_1_BITS 16 16689 #define PHY84328_SYS_DEV1_PMD_OUI_ID1_REG_PMD_FORM_ID_1_SHIFT 0 16690 16691 16692 /**************************************************************************** 16693 * sys_device1 :: base_r_pmd_control_register 16694 */ 16695 /* sys_device1 :: base_r_pmd_control_register :: reserved0 [15:02] */ 16696 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESERVED0_MASK 0xfffc 16697 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESERVED0_ALIGN 0 16698 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESERVED0_BITS 14 16699 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESERVED0_SHIFT 2 16700 16701 /* sys_device1 :: base_r_pmd_control_register :: training_enable [01:01] */ 16702 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_TRAINING_ENABLE_MASK 0x0002 16703 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_TRAINING_ENABLE_ALIGN 0 16704 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_TRAINING_ENABLE_BITS 1 16705 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_TRAINING_ENABLE_SHIFT 1 16706 16707 /* sys_device1 :: base_r_pmd_control_register :: restart_training [00:00] */ 16708 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESTART_TRAINING_MASK 0x0001 16709 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESTART_TRAINING_ALIGN 0 16710 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESTART_TRAINING_BITS 1 16711 #define PHY84328_SYS_DEV1_BASE_R_PMD_CONTROL_REGISTER_RESTART_TRAINING_SHIFT 0 16712 16713 16714 /**************************************************************************** 16715 * sys_device1 :: base_r_pmd_status_register 16716 */ 16717 /* sys_device1 :: base_r_pmd_status_register :: reserved0 [15:04] */ 16718 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_RESERVED0_MASK 0xfff0 16719 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_RESERVED0_ALIGN 0 16720 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_RESERVED0_BITS 12 16721 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_RESERVED0_SHIFT 4 16722 16723 /* sys_device1 :: base_r_pmd_status_register :: training_failure_lane [03:03] */ 16724 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_TRAINING_FAILURE_LANE_MASK 0x0008 16725 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_TRAINING_FAILURE_LANE_ALIGN 0 16726 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_TRAINING_FAILURE_LANE_BITS 1 16727 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_TRAINING_FAILURE_LANE_SHIFT 3 16728 16729 /* sys_device1 :: base_r_pmd_status_register :: start_up_protocol_status_lane [02:02] */ 16730 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_START_UP_PROTOCOL_STATUS_LANE_MASK 0x0004 16731 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_START_UP_PROTOCOL_STATUS_LANE_ALIGN 0 16732 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_START_UP_PROTOCOL_STATUS_LANE_BITS 1 16733 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_START_UP_PROTOCOL_STATUS_LANE_SHIFT 2 16734 16735 /* sys_device1 :: base_r_pmd_status_register :: frame_lock_lane [01:01] */ 16736 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_FRAME_LOCK_LANE_MASK 0x0002 16737 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_FRAME_LOCK_LANE_ALIGN 0 16738 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_FRAME_LOCK_LANE_BITS 1 16739 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_FRAME_LOCK_LANE_SHIFT 1 16740 16741 /* sys_device1 :: base_r_pmd_status_register :: receiver_status_lane [00:00] */ 16742 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_RECEIVER_STATUS_LANE_MASK 0x0001 16743 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_RECEIVER_STATUS_LANE_ALIGN 0 16744 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_RECEIVER_STATUS_LANE_BITS 1 16745 #define PHY84328_SYS_DEV1_BASE_R_PMD_STATUS_REGISTER_RECEIVER_STATUS_LANE_SHIFT 0 16746 16747 16748 /**************************************************************************** 16749 * sys_device1 :: tengbase_kr_lp_coefficient_upd_152 16750 */ 16751 /* sys_device1 :: tengbase_kr_lp_coefficient_upd_152 :: lp_coeff_upd_reg [15:00] */ 16752 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_MASK 0xffff 16753 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_ALIGN 0 16754 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_BITS 16 16755 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_COEFFICIENT_UPD_152_LP_COEFF_UPD_REG_SHIFT 0 16756 16757 16758 /**************************************************************************** 16759 * sys_device1 :: tengbase_kr_lp_status_report_reg_153 16760 */ 16761 /* sys_device1 :: tengbase_kr_lp_status_report_reg_153 :: lp_coeff_status_reg [15:00] */ 16762 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_MASK 0xffff 16763 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_ALIGN 0 16764 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_BITS 16 16765 #define PHY84328_SYS_DEV1_TENGBASE_KR_LP_STATUS_REPORT_REG_153_LP_COEFF_STATUS_REG_SHIFT 0 16766 16767 16768 /**************************************************************************** 16769 * sys_device1 :: tengbase_kr_ld_coefficient_upd_154 16770 */ 16771 /* sys_device1 :: tengbase_kr_ld_coefficient_upd_154 :: ld_coeff_upd_reg [15:00] */ 16772 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_MASK 0xffff 16773 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_ALIGN 0 16774 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_BITS 16 16775 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_COEFFICIENT_UPD_154_LD_COEFF_UPD_REG_SHIFT 0 16776 16777 16778 /**************************************************************************** 16779 * sys_device1 :: tengbase_kr_ld_status_report_reg_155 16780 */ 16781 /* sys_device1 :: tengbase_kr_ld_status_report_reg_155 :: ld_coeff_status_reg [15:00] */ 16782 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_MASK 0xffff 16783 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_ALIGN 0 16784 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_BITS 16 16785 #define PHY84328_SYS_DEV1_TENGBASE_KR_LD_STATUS_REPORT_REG_155_LD_COEFF_STATUS_REG_SHIFT 0 16786 16787 16788 /**************************************************************************** 16789 * sys_device1 :: tengbase_kx_control_register 16790 */ 16791 /* sys_device1 :: tengbase_kx_control_register :: reserved0 [15:01] */ 16792 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_MASK 0xfffe 16793 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_ALIGN 0 16794 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_BITS 15 16795 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_SHIFT 1 16796 16797 /* sys_device1 :: tengbase_kx_control_register :: pmd_transmit_disable [00:00] */ 16798 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_MASK 0x0001 16799 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_ALIGN 0 16800 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_BITS 1 16801 #define PHY84328_SYS_DEV1_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_SHIFT 0 16802 16803 16804 /**************************************************************************** 16805 * sys_device1 :: tengbase_kx_status_register 16806 */ 16807 /* sys_device1 :: tengbase_kx_status_register :: reserved0 [15:14] */ 16808 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED0_MASK 0xc000 16809 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED0_ALIGN 0 16810 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED0_BITS 2 16811 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED0_SHIFT 14 16812 16813 /* sys_device1 :: tengbase_kx_status_register :: transmit_faultability [13:13] */ 16814 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_MASK 0x2000 16815 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_ALIGN 0 16816 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_BITS 1 16817 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_SHIFT 13 16818 16819 /* sys_device1 :: tengbase_kx_status_register :: receive_faultability [12:12] */ 16820 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_MASK 0x1000 16821 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_ALIGN 0 16822 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_BITS 1 16823 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_SHIFT 12 16824 16825 /* sys_device1 :: tengbase_kx_status_register :: transmit_fault [11:11] */ 16826 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_MASK 0x0800 16827 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_ALIGN 0 16828 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_BITS 1 16829 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_SHIFT 11 16830 16831 /* sys_device1 :: tengbase_kx_status_register :: receive_fault [10:10] */ 16832 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_MASK 0x0400 16833 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_ALIGN 0 16834 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_BITS 1 16835 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_SHIFT 10 16836 16837 /* sys_device1 :: tengbase_kx_status_register :: reserved1 [09:09] */ 16838 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED1_MASK 0x0200 16839 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED1_ALIGN 0 16840 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED1_BITS 1 16841 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED1_SHIFT 9 16842 16843 /* sys_device1 :: tengbase_kx_status_register :: pmd_transmitdisable_ability [08:08] */ 16844 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_MASK 0x0100 16845 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_ALIGN 0 16846 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_BITS 1 16847 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_SHIFT 8 16848 16849 /* sys_device1 :: tengbase_kx_status_register :: reserved2 [07:01] */ 16850 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED2_MASK 0x00fe 16851 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED2_ALIGN 0 16852 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED2_BITS 7 16853 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_RESERVED2_SHIFT 1 16854 16855 /* sys_device1 :: tengbase_kx_status_register :: signal_detectfrom_pmd [00:00] */ 16856 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_MASK 0x0001 16857 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_ALIGN 0 16858 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_BITS 1 16859 #define PHY84328_SYS_DEV1_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_SHIFT 0 16860 16861 16862 /**************************************************************************** 16863 * sys_device1_QSFI_AFE_Registers 16864 */ 16865 /**************************************************************************** 16866 * sys_device1 :: anaPllAStatus 16867 */ 16868 /* sys_device1 :: anaPllAStatus :: PLL_lock_detect [15:15] */ 16869 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_LOCK_DETECT_MASK 0x8000 16870 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_LOCK_DETECT_ALIGN 0 16871 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_LOCK_DETECT_BITS 1 16872 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_LOCK_DETECT_SHIFT 15 16873 16874 /* sys_device1 :: anaPllAStatus :: PLL_cal_valid [14:14] */ 16875 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_CAL_VALID_MASK 0x4000 16876 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_CAL_VALID_ALIGN 0 16877 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_CAL_VALID_BITS 1 16878 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_CAL_VALID_SHIFT 14 16879 16880 /* sys_device1 :: anaPllAStatus :: cal_state [13:11] */ 16881 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_CAL_STATE_MASK 0x3800 16882 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_CAL_STATE_ALIGN 0 16883 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_CAL_STATE_BITS 3 16884 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_CAL_STATE_SHIFT 11 16885 16886 /* sys_device1 :: anaPllAStatus :: PLL_lock_bar [10:10] */ 16887 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_LOCK_BAR_MASK 0x0400 16888 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_LOCK_BAR_ALIGN 0 16889 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_LOCK_BAR_BITS 1 16890 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_LOCK_BAR_SHIFT 10 16891 16892 /* sys_device1 :: anaPllAStatus :: reserved0 [09:08] */ 16893 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_RESERVED0_MASK 0x0300 16894 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_RESERVED0_ALIGN 0 16895 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_RESERVED0_BITS 2 16896 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_RESERVED0_SHIFT 8 16897 16898 /* sys_device1 :: anaPllAStatus :: pll_rescal [07:05] */ 16899 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_RESCAL_MASK 0x00e0 16900 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_RESCAL_ALIGN 0 16901 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_RESCAL_BITS 3 16902 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_RESCAL_SHIFT 5 16903 16904 /* sys_device1 :: anaPllAStatus :: pll_pwrdn [04:04] */ 16905 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_PWRDN_MASK 0x0010 16906 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_PWRDN_ALIGN 0 16907 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_PWRDN_BITS 1 16908 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_PWRDN_SHIFT 4 16909 16910 /* sys_device1 :: anaPllAStatus :: pll_mode_afe [03:00] */ 16911 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_MODE_AFE_MASK 0x000f 16912 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_MODE_AFE_ALIGN 0 16913 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_MODE_AFE_BITS 4 16914 #define PHY84328_SYS_DEV1_ANAPLLASTATUS_PLL_MODE_AFE_SHIFT 0 16915 16916 16917 /**************************************************************************** 16918 * sys_device1 :: anaPllAControl 16919 */ 16920 /* sys_device1 :: anaPllAControl :: start_sequencer [15:15] */ 16921 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_START_SEQUENCER_MASK 0x8000 16922 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_START_SEQUENCER_ALIGN 0 16923 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_START_SEQUENCER_BITS 1 16924 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_START_SEQUENCER_SHIFT 15 16925 16926 /* sys_device1 :: anaPllAControl :: cal_th [14:13] */ 16927 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_CAL_TH_MASK 0x6000 16928 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_CAL_TH_ALIGN 0 16929 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_CAL_TH_BITS 2 16930 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_CAL_TH_SHIFT 13 16931 16932 /* sys_device1 :: anaPllAControl :: cap_delay [12:12] */ 16933 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_CAP_DELAY_MASK 0x1000 16934 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_CAP_DELAY_ALIGN 0 16935 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_CAP_DELAY_BITS 1 16936 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_CAP_DELAY_SHIFT 12 16937 16938 /* sys_device1 :: anaPllAControl :: pll_lkdt_byp [11:11] */ 16939 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLL_LKDT_BYP_MASK 0x0800 16940 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLL_LKDT_BYP_ALIGN 0 16941 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLL_LKDT_BYP_BITS 1 16942 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLL_LKDT_BYP_SHIFT 11 16943 16944 /* sys_device1 :: anaPllAControl :: pll_clk_dis [10:10] */ 16945 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLL_CLK_DIS_MASK 0x0400 16946 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLL_CLK_DIS_ALIGN 0 16947 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLL_CLK_DIS_BITS 1 16948 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLL_CLK_DIS_SHIFT 10 16949 16950 /* sys_device1 :: anaPllAControl :: reserved0 [09:08] */ 16951 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_RESERVED0_MASK 0x0300 16952 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_RESERVED0_ALIGN 0 16953 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_RESERVED0_BITS 2 16954 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_RESERVED0_SHIFT 8 16955 16956 /* sys_device1 :: anaPllAControl :: PllForceDone_en [07:07] */ 16957 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEDONE_EN_MASK 0x0080 16958 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEDONE_EN_ALIGN 0 16959 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEDONE_EN_BITS 1 16960 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEDONE_EN_SHIFT 7 16961 16962 /* sys_device1 :: anaPllAControl :: PllForceDone [06:06] */ 16963 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEDONE_MASK 0x0040 16964 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEDONE_ALIGN 0 16965 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEDONE_BITS 1 16966 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEDONE_SHIFT 6 16967 16968 /* sys_device1 :: anaPllAControl :: PllForcePass [05:05] */ 16969 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEPASS_MASK 0x0020 16970 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEPASS_ALIGN 0 16971 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEPASS_BITS 1 16972 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEPASS_SHIFT 5 16973 16974 /* sys_device1 :: anaPllAControl :: reserved1 [04:03] */ 16975 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_RESERVED1_MASK 0x0018 16976 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_RESERVED1_ALIGN 0 16977 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_RESERVED1_BITS 2 16978 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_RESERVED1_SHIFT 3 16979 16980 /* sys_device1 :: anaPllAControl :: PllForceVcoPass_en [02:02] */ 16981 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_EN_MASK 0x0004 16982 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_EN_ALIGN 0 16983 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_EN_BITS 1 16984 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_EN_SHIFT 2 16985 16986 /* sys_device1 :: anaPllAControl :: PllForceVcoPass [01:01] */ 16987 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_MASK 0x0002 16988 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_ALIGN 0 16989 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_BITS 1 16990 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEVCOPASS_SHIFT 1 16991 16992 /* sys_device1 :: anaPllAControl :: PllForcePllLock [00:00] */ 16993 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEPLLLOCK_MASK 0x0001 16994 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEPLLLOCK_ALIGN 0 16995 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEPLLLOCK_BITS 1 16996 #define PHY84328_SYS_DEV1_ANAPLLACONTROL_PLLFORCEPLLLOCK_SHIFT 0 16997 16998 16999 /**************************************************************************** 17000 * sys_device1 :: anaPllATimer1 17001 */ 17002 /* sys_device1 :: anaPllATimer1 :: reserved0 [15:13] */ 17003 #define PHY84328_SYS_DEV1_ANAPLLATIMER1_RESERVED0_MASK 0xe000 17004 #define PHY84328_SYS_DEV1_ANAPLLATIMER1_RESERVED0_ALIGN 0 17005 #define PHY84328_SYS_DEV1_ANAPLLATIMER1_RESERVED0_BITS 3 17006 #define PHY84328_SYS_DEV1_ANAPLLATIMER1_RESERVED0_SHIFT 13 17007 17008 /* sys_device1 :: anaPllATimer1 :: Vco_calibration_StepTime [12:00] */ 17009 #define PHY84328_SYS_DEV1_ANAPLLATIMER1_VCO_CALIBRATION_STEPTIME_MASK 0x1fff 17010 #define PHY84328_SYS_DEV1_ANAPLLATIMER1_VCO_CALIBRATION_STEPTIME_ALIGN 0 17011 #define PHY84328_SYS_DEV1_ANAPLLATIMER1_VCO_CALIBRATION_STEPTIME_BITS 13 17012 #define PHY84328_SYS_DEV1_ANAPLLATIMER1_VCO_CALIBRATION_STEPTIME_SHIFT 0 17013 17014 17015 /**************************************************************************** 17016 * sys_device1 :: anaPllATimer2 17017 */ 17018 /* sys_device1 :: anaPllATimer2 :: reserved0 [15:14] */ 17019 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RESERVED0_MASK 0xc000 17020 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RESERVED0_ALIGN 0 17021 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RESERVED0_BITS 2 17022 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RESERVED0_SHIFT 14 17023 17024 /* sys_device1 :: anaPllATimer2 :: freqDetTime [13:13] */ 17025 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_FREQDETTIME_MASK 0x2000 17026 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_FREQDETTIME_ALIGN 0 17027 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_FREQDETTIME_BITS 1 17028 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_FREQDETTIME_SHIFT 13 17029 17030 /* sys_device1 :: anaPllATimer2 :: reserved1 [12:08] */ 17031 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RESERVED1_MASK 0x1f00 17032 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RESERVED1_ALIGN 0 17033 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RESERVED1_BITS 5 17034 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RESERVED1_SHIFT 8 17035 17036 /* sys_device1 :: anaPllATimer2 :: retryTime [07:00] */ 17037 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RETRYTIME_MASK 0x00ff 17038 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RETRYTIME_ALIGN 0 17039 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RETRYTIME_BITS 8 17040 #define PHY84328_SYS_DEV1_ANAPLLATIMER2_RETRYTIME_SHIFT 0 17041 17042 17043 /**************************************************************************** 17044 * sys_device1 :: anaPllATimer3 17045 */ 17046 /* sys_device1 :: anaPllATimer3 :: freqDetTime [15:00] */ 17047 #define PHY84328_SYS_DEV1_ANAPLLATIMER3_FREQDETTIME_MASK 0xffff 17048 #define PHY84328_SYS_DEV1_ANAPLLATIMER3_FREQDETTIME_ALIGN 0 17049 #define PHY84328_SYS_DEV1_ANAPLLATIMER3_FREQDETTIME_BITS 16 17050 #define PHY84328_SYS_DEV1_ANAPLLATIMER3_FREQDETTIME_SHIFT 0 17051 17052 17053 /**************************************************************************** 17054 * sys_device1 :: anaPllcapCtrl 17055 */ 17056 /* sys_device1 :: anaPllcapCtrl :: vcoSeqCYA [15:15] */ 17057 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSEQCYA_MASK 0x8000 17058 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSEQCYA_ALIGN 0 17059 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSEQCYA_BITS 1 17060 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSEQCYA_SHIFT 15 17061 17062 /* sys_device1 :: anaPllcapCtrl :: vcoRestart [14:14] */ 17063 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCORESTART_MASK 0x4000 17064 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCORESTART_ALIGN 0 17065 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCORESTART_BITS 1 17066 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCORESTART_SHIFT 14 17067 17068 /* sys_device1 :: anaPllcapCtrl :: vcoSelectM_en [13:13] */ 17069 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSELECTM_EN_MASK 0x2000 17070 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSELECTM_EN_ALIGN 0 17071 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSELECTM_EN_BITS 1 17072 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSELECTM_EN_SHIFT 13 17073 17074 /* sys_device1 :: anaPllcapCtrl :: vcoForceSlowdn_en [12:12] */ 17075 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDN_EN_MASK 0x1000 17076 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDN_EN_ALIGN 0 17077 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDN_EN_BITS 1 17078 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDN_EN_SHIFT 12 17079 17080 /* sys_device1 :: anaPllcapCtrl :: vcoRstEn [11:11] */ 17081 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCORSTEN_MASK 0x0800 17082 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCORSTEN_ALIGN 0 17083 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCORSTEN_BITS 1 17084 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCORSTEN_SHIFT 11 17085 17086 /* sys_device1 :: anaPllcapCtrl :: vcoCntMask_en [10:10] */ 17087 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOCNTMASK_EN_MASK 0x0400 17088 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOCNTMASK_EN_ALIGN 0 17089 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOCNTMASK_EN_BITS 1 17090 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOCNTMASK_EN_SHIFT 10 17091 17092 /* sys_device1 :: anaPllcapCtrl :: slowdn_xor [09:09] */ 17093 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_SLOWDN_XOR_MASK 0x0200 17094 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_SLOWDN_XOR_ALIGN 0 17095 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_SLOWDN_XOR_BITS 1 17096 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_SLOWDN_XOR_SHIFT 9 17097 17098 /* sys_device1 :: anaPllcapCtrl :: vcoForceSlowDown [08:08] */ 17099 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDOWN_MASK 0x0100 17100 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDOWN_ALIGN 0 17101 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDOWN_BITS 1 17102 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOFORCESLOWDOWN_SHIFT 8 17103 17104 /* sys_device1 :: anaPllcapCtrl :: vcoSelectM [07:00] */ 17105 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSELECTM_MASK 0x00ff 17106 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSELECTM_ALIGN 0 17107 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSELECTM_BITS 8 17108 #define PHY84328_SYS_DEV1_ANAPLLCAPCTRL_VCOSELECTM_SHIFT 0 17109 17110 17111 /**************************************************************************** 17112 * sys_device1 :: anaPllampCtrl 17113 */ 17114 /* sys_device1 :: anaPllampCtrl :: pll_rescal_manual_en [15:15] */ 17115 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL_PLL_RESCAL_MANUAL_EN_MASK 0x8000 17116 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL_PLL_RESCAL_MANUAL_EN_ALIGN 0 17117 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL_PLL_RESCAL_MANUAL_EN_BITS 1 17118 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL_PLL_RESCAL_MANUAL_EN_SHIFT 15 17119 17120 /* sys_device1 :: anaPllampCtrl :: reserved0 [14:00] */ 17121 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL_RESERVED0_MASK 0x7fff 17122 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL_RESERVED0_ALIGN 0 17123 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL_RESERVED0_BITS 15 17124 #define PHY84328_SYS_DEV1_ANAPLLAMPCTRL_RESERVED0_SHIFT 0 17125 17126 17127 /**************************************************************************** 17128 * sys_device1 :: anaPllAStatus1 17129 */ 17130 /* sys_device1 :: anaPllAStatus1 :: reserved0 [15:03] */ 17131 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1_RESERVED0_MASK 0xfff8 17132 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1_RESERVED0_ALIGN 0 17133 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1_RESERVED0_BITS 13 17134 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1_RESERVED0_SHIFT 3 17135 17136 /* sys_device1 :: anaPllAStatus1 :: pll_rescal [02:00] */ 17137 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1_PLL_RESCAL_MASK 0x0007 17138 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1_PLL_RESCAL_ALIGN 0 17139 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1_PLL_RESCAL_BITS 3 17140 #define PHY84328_SYS_DEV1_ANAPLLASTATUS1_PLL_RESCAL_SHIFT 0 17141 17142 17143 /**************************************************************************** 17144 * sys_device1 :: anaPllAControl0 17145 */ 17146 /* sys_device1 :: anaPllAControl0 :: buf10g_ctr_b0 [15:15] */ 17147 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_BUF10G_CTR_B0_MASK 0x8000 17148 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_BUF10G_CTR_B0_ALIGN 0 17149 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_BUF10G_CTR_B0_BITS 1 17150 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_BUF10G_CTR_B0_SHIFT 15 17151 17152 /* sys_device1 :: anaPllAControl0 :: reserved0 [14:12] */ 17153 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_RESERVED0_MASK 0x7000 17154 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_RESERVED0_ALIGN 0 17155 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_RESERVED0_BITS 3 17156 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_RESERVED0_SHIFT 12 17157 17158 /* sys_device1 :: anaPllAControl0 :: en_test_pllclk [11:11] */ 17159 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_EN_TEST_PLLCLK_MASK 0x0800 17160 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_EN_TEST_PLLCLK_ALIGN 0 17161 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_EN_TEST_PLLCLK_BITS 1 17162 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_EN_TEST_PLLCLK_SHIFT 11 17163 17164 /* sys_device1 :: anaPllAControl0 :: cpar [10:09] */ 17165 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_CPAR_MASK 0x0600 17166 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_CPAR_ALIGN 0 17167 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_CPAR_BITS 2 17168 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_CPAR_SHIFT 9 17169 17170 /* sys_device1 :: anaPllAControl0 :: rpar [08:06] */ 17171 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_RPAR_MASK 0x01c0 17172 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_RPAR_ALIGN 0 17173 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_RPAR_BITS 3 17174 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_RPAR_SHIFT 6 17175 17176 /* sys_device1 :: anaPllAControl0 :: curr_sel [05:02] */ 17177 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_CURR_SEL_MASK 0x003c 17178 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_CURR_SEL_ALIGN 0 17179 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_CURR_SEL_BITS 4 17180 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_CURR_SEL_SHIFT 2 17181 17182 /* sys_device1 :: anaPllAControl0 :: test_bg [01:01] */ 17183 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_TEST_BG_MASK 0x0002 17184 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_TEST_BG_ALIGN 0 17185 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_TEST_BG_BITS 1 17186 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_TEST_BG_SHIFT 1 17187 17188 /* sys_device1 :: anaPllAControl0 :: test_vc [00:00] */ 17189 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_TEST_VC_MASK 0x0001 17190 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_TEST_VC_ALIGN 0 17191 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_TEST_VC_BITS 1 17192 #define PHY84328_SYS_DEV1_ANAPLLACONTROL0_TEST_VC_SHIFT 0 17193 17194 17195 /**************************************************************************** 17196 * sys_device1 :: anaPllAControl1 17197 */ 17198 /* sys_device1 :: anaPllAControl1 :: vco_range_b4_b0 [15:11] */ 17199 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_VCO_RANGE_B4_B0_MASK 0xf800 17200 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_VCO_RANGE_B4_B0_ALIGN 0 17201 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_VCO_RANGE_B4_B0_BITS 5 17202 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_VCO_RANGE_B4_B0_SHIFT 11 17203 17204 /* sys_device1 :: anaPllAControl1 :: sel_xaui [10:10] */ 17205 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_SEL_XAUI_MASK 0x0400 17206 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_SEL_XAUI_ALIGN 0 17207 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_SEL_XAUI_BITS 1 17208 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_SEL_XAUI_SHIFT 10 17209 17210 /* sys_device1 :: anaPllAControl1 :: en_e10g [09:09] */ 17211 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_E10G_MASK 0x0200 17212 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_E10G_ALIGN 0 17213 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_E10G_BITS 1 17214 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_E10G_SHIFT 9 17215 17216 /* sys_device1 :: anaPllAControl1 :: pllclksel [08:08] */ 17217 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_PLLCLKSEL_MASK 0x0100 17218 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_PLLCLKSEL_ALIGN 0 17219 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_PLLCLKSEL_BITS 1 17220 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_PLLCLKSEL_SHIFT 8 17221 17222 /* sys_device1 :: anaPllAControl1 :: en_rclk_refout [07:07] */ 17223 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_RCLK_REFOUT_MASK 0x0080 17224 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_RCLK_REFOUT_ALIGN 0 17225 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_RCLK_REFOUT_BITS 1 17226 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_RCLK_REFOUT_SHIFT 7 17227 17228 /* sys_device1 :: anaPllAControl1 :: pll_clkvco_cal_invert [06:06] */ 17229 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_PLL_CLKVCO_CAL_INVERT_MASK 0x0040 17230 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_PLL_CLKVCO_CAL_INVERT_ALIGN 0 17231 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_PLL_CLKVCO_CAL_INVERT_BITS 1 17232 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_PLL_CLKVCO_CAL_INVERT_SHIFT 6 17233 17234 /* sys_device1 :: anaPllAControl1 :: en_i4buf10g [05:04] */ 17235 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_I4BUF10G_MASK 0x0030 17236 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_I4BUF10G_ALIGN 0 17237 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_I4BUF10G_BITS 2 17238 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_I4BUF10G_SHIFT 4 17239 17240 /* sys_device1 :: anaPllAControl1 :: en_i4drv5g [03:02] */ 17241 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_I4DRV5G_MASK 0x000c 17242 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_I4DRV5G_ALIGN 0 17243 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_I4DRV5G_BITS 2 17244 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_EN_I4DRV5G_SHIFT 2 17245 17246 /* sys_device1 :: anaPllAControl1 :: buf10g_ctr_b2_b1 [01:00] */ 17247 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_BUF10G_CTR_B2_B1_MASK 0x0003 17248 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_BUF10G_CTR_B2_B1_ALIGN 0 17249 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_BUF10G_CTR_B2_B1_BITS 2 17250 #define PHY84328_SYS_DEV1_ANAPLLACONTROL1_BUF10G_CTR_B2_B1_SHIFT 0 17251 17252 17253 /**************************************************************************** 17254 * sys_device1 :: anaPllAControl2 17255 */ 17256 /* sys_device1 :: anaPllAControl2 :: reserved0 [15:14] */ 17257 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_RESERVED0_MASK 0xc000 17258 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_RESERVED0_ALIGN 0 17259 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_RESERVED0_BITS 2 17260 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_RESERVED0_SHIFT 14 17261 17262 /* sys_device1 :: anaPllAControl2 :: clk_test_sel [13:11] */ 17263 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_CLK_TEST_SEL_MASK 0x3800 17264 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_CLK_TEST_SEL_ALIGN 0 17265 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_CLK_TEST_SEL_BITS 3 17266 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_CLK_TEST_SEL_SHIFT 11 17267 17268 /* sys_device1 :: anaPllAControl2 :: bg_pwrdn [10:10] */ 17269 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_BG_PWRDN_MASK 0x0400 17270 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_BG_PWRDN_ALIGN 0 17271 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_BG_PWRDN_BITS 1 17272 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_BG_PWRDN_SHIFT 10 17273 17274 /* sys_device1 :: anaPllAControl2 :: pll_pwrdn [09:09] */ 17275 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_PLL_PWRDN_MASK 0x0200 17276 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_PLL_PWRDN_ALIGN 0 17277 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_PLL_PWRDN_BITS 1 17278 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_PLL_PWRDN_SHIFT 9 17279 17280 /* sys_device1 :: anaPllAControl2 :: en_cmos_refout [08:08] */ 17281 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_CMOS_REFOUT_MASK 0x0100 17282 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_CMOS_REFOUT_ALIGN 0 17283 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_CMOS_REFOUT_BITS 1 17284 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_CMOS_REFOUT_SHIFT 8 17285 17286 /* sys_device1 :: anaPllAControl2 :: en_cml_refout [07:07] */ 17287 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_CML_REFOUT_MASK 0x0080 17288 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_CML_REFOUT_ALIGN 0 17289 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_CML_REFOUT_BITS 1 17290 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_CML_REFOUT_SHIFT 7 17291 17292 /* sys_device1 :: anaPllAControl2 :: vdd_bgb [06:06] */ 17293 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VDD_BGB_MASK 0x0040 17294 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VDD_BGB_ALIGN 0 17295 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VDD_BGB_BITS 1 17296 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VDD_BGB_SHIFT 6 17297 17298 /* sys_device1 :: anaPllAControl2 :: terminal_sel [05:05] */ 17299 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_TERMINAL_SEL_MASK 0x0020 17300 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_TERMINAL_SEL_ALIGN 0 17301 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_TERMINAL_SEL_BITS 1 17302 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_TERMINAL_SEL_SHIFT 5 17303 17304 /* sys_device1 :: anaPllAControl2 :: vco_bias [04:03] */ 17305 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VCO_BIAS_MASK 0x0018 17306 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VCO_BIAS_ALIGN 0 17307 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VCO_BIAS_BITS 2 17308 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VCO_BIAS_SHIFT 3 17309 17310 /* sys_device1 :: anaPllAControl2 :: en_kvh [02:02] */ 17311 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_KVH_MASK 0x0004 17312 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_KVH_ALIGN 0 17313 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_KVH_BITS 1 17314 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_EN_KVH_SHIFT 2 17315 17316 /* sys_device1 :: anaPllAControl2 :: vco_range_b6_b5 [01:00] */ 17317 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VCO_RANGE_B6_B5_MASK 0x0003 17318 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VCO_RANGE_B6_B5_ALIGN 0 17319 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VCO_RANGE_B6_B5_BITS 2 17320 #define PHY84328_SYS_DEV1_ANAPLLACONTROL2_VCO_RANGE_B6_B5_SHIFT 0 17321 17322 17323 /**************************************************************************** 17324 * sys_device1 :: anaPllAControl3 17325 */ 17326 /* sys_device1 :: anaPllAControl3 :: bg_ptatadj [15:12] */ 17327 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_BG_PTATADJ_MASK 0xf000 17328 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_BG_PTATADJ_ALIGN 0 17329 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_BG_PTATADJ_BITS 4 17330 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_BG_PTATADJ_SHIFT 12 17331 17332 /* sys_device1 :: anaPllAControl3 :: bg_ctatadj [11:08] */ 17333 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_BG_CTATADJ_MASK 0x0f00 17334 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_BG_CTATADJ_ALIGN 0 17335 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_BG_CTATADJ_BITS 4 17336 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_BG_CTATADJ_SHIFT 8 17337 17338 /* sys_device1 :: anaPllAControl3 :: adc_ptat_ctrl [07:06] */ 17339 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_ADC_PTAT_CTRL_MASK 0x00c0 17340 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_ADC_PTAT_CTRL_ALIGN 0 17341 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_ADC_PTAT_CTRL_BITS 2 17342 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_ADC_PTAT_CTRL_SHIFT 6 17343 17344 /* sys_device1 :: anaPllAControl3 :: reserved0 [05:04] */ 17345 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_RESERVED0_MASK 0x0030 17346 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_RESERVED0_ALIGN 0 17347 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_RESERVED0_BITS 2 17348 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_RESERVED0_SHIFT 4 17349 17350 /* sys_device1 :: anaPllAControl3 :: pll_mode [03:03] */ 17351 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_PLL_MODE_MASK 0x0008 17352 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_PLL_MODE_ALIGN 0 17353 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_PLL_MODE_BITS 1 17354 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_PLL_MODE_SHIFT 3 17355 17356 /* sys_device1 :: anaPllAControl3 :: pll_pon [02:00] */ 17357 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_PLL_PON_MASK 0x0007 17358 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_PLL_PON_ALIGN 0 17359 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_PLL_PON_BITS 3 17360 #define PHY84328_SYS_DEV1_ANAPLLACONTROL3_PLL_PON_SHIFT 0 17361 17362 17363 /**************************************************************************** 17364 * sys_device1 :: anaPllAControl4 17365 */ 17366 /* sys_device1 :: anaPllAControl4 :: i_ndiv_frac_lsb [15:02] */ 17367 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4_I_NDIV_FRAC_LSB_MASK 0xfffc 17368 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4_I_NDIV_FRAC_LSB_ALIGN 0 17369 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4_I_NDIV_FRAC_LSB_BITS 14 17370 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4_I_NDIV_FRAC_LSB_SHIFT 2 17371 17372 /* sys_device1 :: anaPllAControl4 :: dac_ctat_ctl [01:00] */ 17373 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4_DAC_CTAT_CTL_MASK 0x0003 17374 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4_DAC_CTAT_CTL_ALIGN 0 17375 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4_DAC_CTAT_CTL_BITS 2 17376 #define PHY84328_SYS_DEV1_ANAPLLACONTROL4_DAC_CTAT_CTL_SHIFT 0 17377 17378 17379 /**************************************************************************** 17380 * sys_device1 :: anaPllAControl5 17381 */ 17382 /* sys_device1 :: anaPllAControl5 :: i_dsm_resetb [15:15] */ 17383 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_DSM_RESETB_MASK 0x8000 17384 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_DSM_RESETB_ALIGN 0 17385 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_DSM_RESETB_BITS 1 17386 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_DSM_RESETB_SHIFT 15 17387 17388 /* sys_device1 :: anaPllAControl5 :: i_ndiv_dither_en [14:14] */ 17389 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_DITHER_EN_MASK 0x4000 17390 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_DITHER_EN_ALIGN 0 17391 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_DITHER_EN_BITS 1 17392 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_DITHER_EN_SHIFT 14 17393 17394 /* sys_device1 :: anaPllAControl5 :: i_pll_wis_mode [13:13] */ 17395 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_PLL_WIS_MODE_MASK 0x2000 17396 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_PLL_WIS_MODE_ALIGN 0 17397 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_PLL_WIS_MODE_BITS 1 17398 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_PLL_WIS_MODE_SHIFT 13 17399 17400 /* sys_device1 :: anaPllAControl5 :: i_div7_bypass_wis [12:12] */ 17401 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_DIV7_BYPASS_WIS_MASK 0x1000 17402 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_DIV7_BYPASS_WIS_ALIGN 0 17403 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_DIV7_BYPASS_WIS_BITS 1 17404 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_DIV7_BYPASS_WIS_SHIFT 12 17405 17406 /* sys_device1 :: anaPllAControl5 :: i_ndiv_int [11:04] */ 17407 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_INT_MASK 0x0ff0 17408 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_INT_ALIGN 0 17409 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_INT_BITS 8 17410 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_INT_SHIFT 4 17411 17412 /* sys_device1 :: anaPllAControl5 :: i_ndiv_frac_msb [03:00] */ 17413 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_FRAC_MSB_MASK 0x000f 17414 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_FRAC_MSB_ALIGN 0 17415 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_FRAC_MSB_BITS 4 17416 #define PHY84328_SYS_DEV1_ANAPLLACONTROL5_I_NDIV_FRAC_MSB_SHIFT 0 17417 17418 17419 /**************************************************************************** 17420 * sys_device1 :: anaPllAControl6 17421 */ 17422 /* sys_device1 :: anaPllAControl6 :: reserved0 [15:06] */ 17423 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_RESERVED0_MASK 0xffc0 17424 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_RESERVED0_ALIGN 0 17425 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_RESERVED0_BITS 10 17426 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_RESERVED0_SHIFT 6 17427 17428 /* sys_device1 :: anaPllAControl6 :: sel_fp3cap [05:01] */ 17429 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_SEL_FP3CAP_MASK 0x003e 17430 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_SEL_FP3CAP_ALIGN 0 17431 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_SEL_FP3CAP_BITS 5 17432 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_SEL_FP3CAP_SHIFT 1 17433 17434 /* sys_device1 :: anaPllAControl6 :: i_pll_wis_frac_en [00:00] */ 17435 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_I_PLL_WIS_FRAC_EN_MASK 0x0001 17436 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_I_PLL_WIS_FRAC_EN_ALIGN 0 17437 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_I_PLL_WIS_FRAC_EN_BITS 1 17438 #define PHY84328_SYS_DEV1_ANAPLLACONTROL6_I_PLL_WIS_FRAC_EN_SHIFT 0 17439 17440 17441 /**************************************************************************** 17442 * sys_device1 :: anaTxAStatus 17443 */ 17444 /* sys_device1 :: anaTxAStatus :: reserved0 [15:11] */ 17445 #define PHY84328_SYS_DEV1_ANATXASTATUS_RESERVED0_MASK 0xf800 17446 #define PHY84328_SYS_DEV1_ANATXASTATUS_RESERVED0_ALIGN 0 17447 #define PHY84328_SYS_DEV1_ANATXASTATUS_RESERVED0_BITS 5 17448 #define PHY84328_SYS_DEV1_ANATXASTATUS_RESERVED0_SHIFT 11 17449 17450 /* sys_device1 :: anaTxAStatus :: os_mode [10:07] */ 17451 #define PHY84328_SYS_DEV1_ANATXASTATUS_OS_MODE_MASK 0x0780 17452 #define PHY84328_SYS_DEV1_ANATXASTATUS_OS_MODE_ALIGN 0 17453 #define PHY84328_SYS_DEV1_ANATXASTATUS_OS_MODE_BITS 4 17454 #define PHY84328_SYS_DEV1_ANATXASTATUS_OS_MODE_SHIFT 7 17455 17456 /* sys_device1 :: anaTxAStatus :: txdisable_ln [06:06] */ 17457 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXDISABLE_LN_MASK 0x0040 17458 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXDISABLE_LN_ALIGN 0 17459 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXDISABLE_LN_BITS 1 17460 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXDISABLE_LN_SHIFT 6 17461 17462 /* sys_device1 :: anaTxAStatus :: txferr_stky [05:05] */ 17463 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXFERR_STKY_MASK 0x0020 17464 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXFERR_STKY_ALIGN 0 17465 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXFERR_STKY_BITS 1 17466 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXFERR_STKY_SHIFT 5 17467 17468 /* sys_device1 :: anaTxAStatus :: tbi_mode [04:04] */ 17469 #define PHY84328_SYS_DEV1_ANATXASTATUS_TBI_MODE_MASK 0x0010 17470 #define PHY84328_SYS_DEV1_ANATXASTATUS_TBI_MODE_ALIGN 0 17471 #define PHY84328_SYS_DEV1_ANATXASTATUS_TBI_MODE_BITS 1 17472 #define PHY84328_SYS_DEV1_ANATXASTATUS_TBI_MODE_SHIFT 4 17473 17474 /* sys_device1 :: anaTxAStatus :: tx_reset [03:03] */ 17475 #define PHY84328_SYS_DEV1_ANATXASTATUS_TX_RESET_MASK 0x0008 17476 #define PHY84328_SYS_DEV1_ANATXASTATUS_TX_RESET_ALIGN 0 17477 #define PHY84328_SYS_DEV1_ANATXASTATUS_TX_RESET_BITS 1 17478 #define PHY84328_SYS_DEV1_ANATXASTATUS_TX_RESET_SHIFT 3 17479 17480 /* sys_device1 :: anaTxAStatus :: tx_pwrdn [02:02] */ 17481 #define PHY84328_SYS_DEV1_ANATXASTATUS_TX_PWRDN_MASK 0x0004 17482 #define PHY84328_SYS_DEV1_ANATXASTATUS_TX_PWRDN_ALIGN 0 17483 #define PHY84328_SYS_DEV1_ANATXASTATUS_TX_PWRDN_BITS 1 17484 #define PHY84328_SYS_DEV1_ANATXASTATUS_TX_PWRDN_SHIFT 2 17485 17486 /* sys_device1 :: anaTxAStatus :: rltxferr_stky [01:01] */ 17487 #define PHY84328_SYS_DEV1_ANATXASTATUS_RLTXFERR_STKY_MASK 0x0002 17488 #define PHY84328_SYS_DEV1_ANATXASTATUS_RLTXFERR_STKY_ALIGN 0 17489 #define PHY84328_SYS_DEV1_ANATXASTATUS_RLTXFERR_STKY_BITS 1 17490 #define PHY84328_SYS_DEV1_ANATXASTATUS_RLTXFERR_STKY_SHIFT 1 17491 17492 /* sys_device1 :: anaTxAStatus :: txpll_lock [00:00] */ 17493 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXPLL_LOCK_MASK 0x0001 17494 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXPLL_LOCK_ALIGN 0 17495 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXPLL_LOCK_BITS 1 17496 #define PHY84328_SYS_DEV1_ANATXASTATUS_TXPLL_LOCK_SHIFT 0 17497 17498 17499 /**************************************************************************** 17500 * sys_device1 :: anaTxAControl 17501 */ 17502 /* sys_device1 :: anaTxAControl :: reserved0 [15:15] */ 17503 #define PHY84328_SYS_DEV1_ANATXACONTROL_RESERVED0_MASK 0x8000 17504 #define PHY84328_SYS_DEV1_ANATXACONTROL_RESERVED0_ALIGN 0 17505 #define PHY84328_SYS_DEV1_ANATXACONTROL_RESERVED0_BITS 1 17506 #define PHY84328_SYS_DEV1_ANATXACONTROL_RESERVED0_SHIFT 15 17507 17508 /* sys_device1 :: anaTxAControl :: force_txclk [14:14] */ 17509 #define PHY84328_SYS_DEV1_ANATXACONTROL_FORCE_TXCLK_MASK 0x4000 17510 #define PHY84328_SYS_DEV1_ANATXACONTROL_FORCE_TXCLK_ALIGN 0 17511 #define PHY84328_SYS_DEV1_ANATXACONTROL_FORCE_TXCLK_BITS 1 17512 #define PHY84328_SYS_DEV1_ANATXACONTROL_FORCE_TXCLK_SHIFT 14 17513 17514 /* sys_device1 :: anaTxAControl :: tx_fifo_rst [13:13] */ 17515 #define PHY84328_SYS_DEV1_ANATXACONTROL_TX_FIFO_RST_MASK 0x2000 17516 #define PHY84328_SYS_DEV1_ANATXACONTROL_TX_FIFO_RST_ALIGN 0 17517 #define PHY84328_SYS_DEV1_ANATXACONTROL_TX_FIFO_RST_BITS 1 17518 #define PHY84328_SYS_DEV1_ANATXACONTROL_TX_FIFO_RST_SHIFT 13 17519 17520 /* sys_device1 :: anaTxAControl :: reserved1 [12:10] */ 17521 #define PHY84328_SYS_DEV1_ANATXACONTROL_RESERVED1_MASK 0x1c00 17522 #define PHY84328_SYS_DEV1_ANATXACONTROL_RESERVED1_ALIGN 0 17523 #define PHY84328_SYS_DEV1_ANATXACONTROL_RESERVED1_BITS 3 17524 #define PHY84328_SYS_DEV1_ANATXACONTROL_RESERVED1_SHIFT 10 17525 17526 /* sys_device1 :: anaTxAControl :: gloopOutEn [09:09] */ 17527 #define PHY84328_SYS_DEV1_ANATXACONTROL_GLOOPOUTEN_MASK 0x0200 17528 #define PHY84328_SYS_DEV1_ANATXACONTROL_GLOOPOUTEN_ALIGN 0 17529 #define PHY84328_SYS_DEV1_ANATXACONTROL_GLOOPOUTEN_BITS 1 17530 #define PHY84328_SYS_DEV1_ANATXACONTROL_GLOOPOUTEN_SHIFT 9 17531 17532 /* sys_device1 :: anaTxAControl :: prbs_en [08:08] */ 17533 #define PHY84328_SYS_DEV1_ANATXACONTROL_PRBS_EN_MASK 0x0100 17534 #define PHY84328_SYS_DEV1_ANATXACONTROL_PRBS_EN_ALIGN 0 17535 #define PHY84328_SYS_DEV1_ANATXACONTROL_PRBS_EN_BITS 1 17536 #define PHY84328_SYS_DEV1_ANATXACONTROL_PRBS_EN_SHIFT 8 17537 17538 /* sys_device1 :: anaTxAControl :: pckt_en [07:07] */ 17539 #define PHY84328_SYS_DEV1_ANATXACONTROL_PCKT_EN_MASK 0x0080 17540 #define PHY84328_SYS_DEV1_ANATXACONTROL_PCKT_EN_ALIGN 0 17541 #define PHY84328_SYS_DEV1_ANATXACONTROL_PCKT_EN_BITS 1 17542 #define PHY84328_SYS_DEV1_ANATXACONTROL_PCKT_EN_SHIFT 7 17543 17544 /* sys_device1 :: anaTxAControl :: pckt_strt [06:06] */ 17545 #define PHY84328_SYS_DEV1_ANATXACONTROL_PCKT_STRT_MASK 0x0040 17546 #define PHY84328_SYS_DEV1_ANATXACONTROL_PCKT_STRT_ALIGN 0 17547 #define PHY84328_SYS_DEV1_ANATXACONTROL_PCKT_STRT_BITS 1 17548 #define PHY84328_SYS_DEV1_ANATXACONTROL_PCKT_STRT_SHIFT 6 17549 17550 /* sys_device1 :: anaTxAControl :: txpol_flip [05:05] */ 17551 #define PHY84328_SYS_DEV1_ANATXACONTROL_TXPOL_FLIP_MASK 0x0020 17552 #define PHY84328_SYS_DEV1_ANATXACONTROL_TXPOL_FLIP_ALIGN 0 17553 #define PHY84328_SYS_DEV1_ANATXACONTROL_TXPOL_FLIP_BITS 1 17554 #define PHY84328_SYS_DEV1_ANATXACONTROL_TXPOL_FLIP_SHIFT 5 17555 17556 /* sys_device1 :: anaTxAControl :: rtbi_flip [04:04] */ 17557 #define PHY84328_SYS_DEV1_ANATXACONTROL_RTBI_FLIP_MASK 0x0010 17558 #define PHY84328_SYS_DEV1_ANATXACONTROL_RTBI_FLIP_ALIGN 0 17559 #define PHY84328_SYS_DEV1_ANATXACONTROL_RTBI_FLIP_BITS 1 17560 #define PHY84328_SYS_DEV1_ANATXACONTROL_RTBI_FLIP_SHIFT 4 17561 17562 /* sys_device1 :: anaTxAControl :: eden_r [03:03] */ 17563 #define PHY84328_SYS_DEV1_ANATXACONTROL_EDEN_R_MASK 0x0008 17564 #define PHY84328_SYS_DEV1_ANATXACONTROL_EDEN_R_ALIGN 0 17565 #define PHY84328_SYS_DEV1_ANATXACONTROL_EDEN_R_BITS 1 17566 #define PHY84328_SYS_DEV1_ANATXACONTROL_EDEN_R_SHIFT 3 17567 17568 /* sys_device1 :: anaTxAControl :: eden_force_r [02:02] */ 17569 #define PHY84328_SYS_DEV1_ANATXACONTROL_EDEN_FORCE_R_MASK 0x0004 17570 #define PHY84328_SYS_DEV1_ANATXACONTROL_EDEN_FORCE_R_ALIGN 0 17571 #define PHY84328_SYS_DEV1_ANATXACONTROL_EDEN_FORCE_R_BITS 1 17572 #define PHY84328_SYS_DEV1_ANATXACONTROL_EDEN_FORCE_R_SHIFT 2 17573 17574 /* sys_device1 :: anaTxAControl :: txpat_en [01:01] */ 17575 #define PHY84328_SYS_DEV1_ANATXACONTROL_TXPAT_EN_MASK 0x0002 17576 #define PHY84328_SYS_DEV1_ANATXACONTROL_TXPAT_EN_ALIGN 0 17577 #define PHY84328_SYS_DEV1_ANATXACONTROL_TXPAT_EN_BITS 1 17578 #define PHY84328_SYS_DEV1_ANATXACONTROL_TXPAT_EN_SHIFT 1 17579 17580 /* sys_device1 :: anaTxAControl :: tx_mdata_en [00:00] */ 17581 #define PHY84328_SYS_DEV1_ANATXACONTROL_TX_MDATA_EN_MASK 0x0001 17582 #define PHY84328_SYS_DEV1_ANATXACONTROL_TX_MDATA_EN_ALIGN 0 17583 #define PHY84328_SYS_DEV1_ANATXACONTROL_TX_MDATA_EN_BITS 1 17584 #define PHY84328_SYS_DEV1_ANATXACONTROL_TX_MDATA_EN_SHIFT 0 17585 17586 17587 /**************************************************************************** 17588 * sys_device1 :: anaTxAStatus1 17589 */ 17590 /* sys_device1 :: anaTxAStatus1 :: reserved0 [15:04] */ 17591 #define PHY84328_SYS_DEV1_ANATXASTATUS1_RESERVED0_MASK 0xfff0 17592 #define PHY84328_SYS_DEV1_ANATXASTATUS1_RESERVED0_ALIGN 0 17593 #define PHY84328_SYS_DEV1_ANATXASTATUS1_RESERVED0_BITS 12 17594 #define PHY84328_SYS_DEV1_ANATXASTATUS1_RESERVED0_SHIFT 4 17595 17596 /* sys_device1 :: anaTxAStatus1 :: Tx_rescal [03:01] */ 17597 #define PHY84328_SYS_DEV1_ANATXASTATUS1_TX_RESCAL_MASK 0x000e 17598 #define PHY84328_SYS_DEV1_ANATXASTATUS1_TX_RESCAL_ALIGN 0 17599 #define PHY84328_SYS_DEV1_ANATXASTATUS1_TX_RESCAL_BITS 3 17600 #define PHY84328_SYS_DEV1_ANATXASTATUS1_TX_RESCAL_SHIFT 1 17601 17602 /* sys_device1 :: anaTxAStatus1 :: reserved1 [00:00] */ 17603 #define PHY84328_SYS_DEV1_ANATXASTATUS1_RESERVED1_MASK 0x0001 17604 #define PHY84328_SYS_DEV1_ANATXASTATUS1_RESERVED1_ALIGN 0 17605 #define PHY84328_SYS_DEV1_ANATXASTATUS1_RESERVED1_BITS 1 17606 #define PHY84328_SYS_DEV1_ANATXASTATUS1_RESERVED1_SHIFT 0 17607 17608 17609 /**************************************************************************** 17610 * sys_device1 :: anaTxAControl1 17611 */ 17612 /* sys_device1 :: anaTxAControl1 :: idriver [15:12] */ 17613 #define PHY84328_SYS_DEV1_ANATXACONTROL1_IDRIVER_MASK 0xf000 17614 #define PHY84328_SYS_DEV1_ANATXACONTROL1_IDRIVER_ALIGN 0 17615 #define PHY84328_SYS_DEV1_ANATXACONTROL1_IDRIVER_BITS 4 17616 #define PHY84328_SYS_DEV1_ANATXACONTROL1_IDRIVER_SHIFT 12 17617 17618 /* sys_device1 :: anaTxAControl1 :: ipredriver [11:08] */ 17619 #define PHY84328_SYS_DEV1_ANATXACONTROL1_IPREDRIVER_MASK 0x0f00 17620 #define PHY84328_SYS_DEV1_ANATXACONTROL1_IPREDRIVER_ALIGN 0 17621 #define PHY84328_SYS_DEV1_ANATXACONTROL1_IPREDRIVER_BITS 4 17622 #define PHY84328_SYS_DEV1_ANATXACONTROL1_IPREDRIVER_SHIFT 8 17623 17624 /* sys_device1 :: anaTxAControl1 :: sl_ctrl [07:04] */ 17625 #define PHY84328_SYS_DEV1_ANATXACONTROL1_SL_CTRL_MASK 0x00f0 17626 #define PHY84328_SYS_DEV1_ANATXACONTROL1_SL_CTRL_ALIGN 0 17627 #define PHY84328_SYS_DEV1_ANATXACONTROL1_SL_CTRL_BITS 4 17628 #define PHY84328_SYS_DEV1_ANATXACONTROL1_SL_CTRL_SHIFT 4 17629 17630 /* sys_device1 :: anaTxAControl1 :: ena_prot [03:03] */ 17631 #define PHY84328_SYS_DEV1_ANATXACONTROL1_ENA_PROT_MASK 0x0008 17632 #define PHY84328_SYS_DEV1_ANATXACONTROL1_ENA_PROT_ALIGN 0 17633 #define PHY84328_SYS_DEV1_ANATXACONTROL1_ENA_PROT_BITS 1 17634 #define PHY84328_SYS_DEV1_ANATXACONTROL1_ENA_PROT_SHIFT 3 17635 17636 /* sys_device1 :: anaTxAControl1 :: tx_bmode [02:02] */ 17637 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMODE_MASK 0x0004 17638 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMODE_ALIGN 0 17639 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMODE_BITS 1 17640 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMODE_SHIFT 2 17641 17642 /* sys_device1 :: anaTxAControl1 :: tx_bmax [01:01] */ 17643 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMAX_MASK 0x0002 17644 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMAX_ALIGN 0 17645 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMAX_BITS 1 17646 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMAX_SHIFT 1 17647 17648 /* sys_device1 :: anaTxAControl1 :: tx_bmin [00:00] */ 17649 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMIN_MASK 0x0001 17650 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMIN_ALIGN 0 17651 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMIN_BITS 1 17652 #define PHY84328_SYS_DEV1_ANATXACONTROL1_TX_BMIN_SHIFT 0 17653 17654 17655 /**************************************************************************** 17656 * sys_device1 :: anaTxAControl2 17657 */ 17658 /* sys_device1 :: anaTxAControl2 :: main_tap [15:11] */ 17659 #define PHY84328_SYS_DEV1_ANATXACONTROL2_MAIN_TAP_MASK 0xf800 17660 #define PHY84328_SYS_DEV1_ANATXACONTROL2_MAIN_TAP_ALIGN 0 17661 #define PHY84328_SYS_DEV1_ANATXACONTROL2_MAIN_TAP_BITS 5 17662 #define PHY84328_SYS_DEV1_ANATXACONTROL2_MAIN_TAP_SHIFT 11 17663 17664 /* sys_device1 :: anaTxAControl2 :: tx_pwrdn [10:10] */ 17665 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TX_PWRDN_MASK 0x0400 17666 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TX_PWRDN_ALIGN 0 17667 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TX_PWRDN_BITS 1 17668 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TX_PWRDN_SHIFT 10 17669 17670 /* sys_device1 :: anaTxAControl2 :: tx_modeselect [09:07] */ 17671 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TX_MODESELECT_MASK 0x0380 17672 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TX_MODESELECT_ALIGN 0 17673 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TX_MODESELECT_BITS 3 17674 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TX_MODESELECT_SHIFT 7 17675 17676 /* sys_device1 :: anaTxAControl2 :: imux [06:04] */ 17677 #define PHY84328_SYS_DEV1_ANATXACONTROL2_IMUX_MASK 0x0070 17678 #define PHY84328_SYS_DEV1_ANATXACONTROL2_IMUX_ALIGN 0 17679 #define PHY84328_SYS_DEV1_ANATXACONTROL2_IMUX_BITS 3 17680 #define PHY84328_SYS_DEV1_ANATXACONTROL2_IMUX_SHIFT 4 17681 17682 /* sys_device1 :: anaTxAControl2 :: imux_latch [03:01] */ 17683 #define PHY84328_SYS_DEV1_ANATXACONTROL2_IMUX_LATCH_MASK 0x000e 17684 #define PHY84328_SYS_DEV1_ANATXACONTROL2_IMUX_LATCH_ALIGN 0 17685 #define PHY84328_SYS_DEV1_ANATXACONTROL2_IMUX_LATCH_BITS 3 17686 #define PHY84328_SYS_DEV1_ANATXACONTROL2_IMUX_LATCH_SHIFT 1 17687 17688 /* sys_device1 :: anaTxAControl2 :: test_drv [00:00] */ 17689 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TEST_DRV_MASK 0x0001 17690 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TEST_DRV_ALIGN 0 17691 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TEST_DRV_BITS 1 17692 #define PHY84328_SYS_DEV1_ANATXACONTROL2_TEST_DRV_SHIFT 0 17693 17694 17695 /**************************************************************************** 17696 * sys_device1 :: anaTxAControl3 17697 */ 17698 /* sys_device1 :: anaTxAControl3 :: tx_pi_bias [15:14] */ 17699 #define PHY84328_SYS_DEV1_ANATXACONTROL3_TX_PI_BIAS_MASK 0xc000 17700 #define PHY84328_SYS_DEV1_ANATXACONTROL3_TX_PI_BIAS_ALIGN 0 17701 #define PHY84328_SYS_DEV1_ANATXACONTROL3_TX_PI_BIAS_BITS 2 17702 #define PHY84328_SYS_DEV1_ANATXACONTROL3_TX_PI_BIAS_SHIFT 14 17703 17704 /* sys_device1 :: anaTxAControl3 :: ticksel [13:12] */ 17705 #define PHY84328_SYS_DEV1_ANATXACONTROL3_TICKSEL_MASK 0x3000 17706 #define PHY84328_SYS_DEV1_ANATXACONTROL3_TICKSEL_ALIGN 0 17707 #define PHY84328_SYS_DEV1_ANATXACONTROL3_TICKSEL_BITS 2 17708 #define PHY84328_SYS_DEV1_ANATXACONTROL3_TICKSEL_SHIFT 12 17709 17710 /* sys_device1 :: anaTxAControl3 :: iclkgen [11:09] */ 17711 #define PHY84328_SYS_DEV1_ANATXACONTROL3_ICLKGEN_MASK 0x0e00 17712 #define PHY84328_SYS_DEV1_ANATXACONTROL3_ICLKGEN_ALIGN 0 17713 #define PHY84328_SYS_DEV1_ANATXACONTROL3_ICLKGEN_BITS 3 17714 #define PHY84328_SYS_DEV1_ANATXACONTROL3_ICLKGEN_SHIFT 9 17715 17716 /* sys_device1 :: anaTxAControl3 :: postcursor_tap_fine [08:08] */ 17717 #define PHY84328_SYS_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_FINE_MASK 0x0100 17718 #define PHY84328_SYS_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_FINE_ALIGN 0 17719 #define PHY84328_SYS_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_FINE_BITS 1 17720 #define PHY84328_SYS_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_FINE_SHIFT 8 17721 17722 /* sys_device1 :: anaTxAControl3 :: postcursor_tap [07:04] */ 17723 #define PHY84328_SYS_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_MASK 0x00f0 17724 #define PHY84328_SYS_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_ALIGN 0 17725 #define PHY84328_SYS_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_BITS 4 17726 #define PHY84328_SYS_DEV1_ANATXACONTROL3_POSTCURSOR_TAP_SHIFT 4 17727 17728 /* sys_device1 :: anaTxAControl3 :: i_en_8p5G [03:03] */ 17729 #define PHY84328_SYS_DEV1_ANATXACONTROL3_I_EN_8P5G_MASK 0x0008 17730 #define PHY84328_SYS_DEV1_ANATXACONTROL3_I_EN_8P5G_ALIGN 0 17731 #define PHY84328_SYS_DEV1_ANATXACONTROL3_I_EN_8P5G_BITS 1 17732 #define PHY84328_SYS_DEV1_ANATXACONTROL3_I_EN_8P5G_SHIFT 3 17733 17734 /* sys_device1 :: anaTxAControl3 :: precursor_tap [02:00] */ 17735 #define PHY84328_SYS_DEV1_ANATXACONTROL3_PRECURSOR_TAP_MASK 0x0007 17736 #define PHY84328_SYS_DEV1_ANATXACONTROL3_PRECURSOR_TAP_ALIGN 0 17737 #define PHY84328_SYS_DEV1_ANATXACONTROL3_PRECURSOR_TAP_BITS 3 17738 #define PHY84328_SYS_DEV1_ANATXACONTROL3_PRECURSOR_TAP_SHIFT 0 17739 17740 17741 /**************************************************************************** 17742 * sys_device1 :: anaTxAControl4 17743 */ 17744 /* sys_device1 :: anaTxAControl4 :: xfi_lowlatency_fifo_ctrl [15:14] */ 17745 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_CTRL_MASK 0xc000 17746 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_CTRL_ALIGN 0 17747 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_CTRL_BITS 2 17748 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_CTRL_SHIFT 14 17749 17750 /* sys_device1 :: anaTxAControl4 :: xfi_lowlatency_fifo_zero_out [13:13] */ 17751 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_ZERO_OUT_MASK 0x2000 17752 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_ZERO_OUT_ALIGN 0 17753 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_ZERO_OUT_BITS 1 17754 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_FIFO_ZERO_OUT_SHIFT 13 17755 17756 /* sys_device1 :: anaTxAControl4 :: xfi_lowlatency_polarity_flip [12:12] */ 17757 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_POLARITY_FLIP_MASK 0x1000 17758 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_POLARITY_FLIP_ALIGN 0 17759 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_POLARITY_FLIP_BITS 1 17760 #define PHY84328_SYS_DEV1_ANATXACONTROL4_XFI_LOWLATENCY_POLARITY_FLIP_SHIFT 12 17761 17762 /* sys_device1 :: anaTxAControl4 :: lowlatency_selectpath_tx [11:11] */ 17763 #define PHY84328_SYS_DEV1_ANATXACONTROL4_LOWLATENCY_SELECTPATH_TX_MASK 0x0800 17764 #define PHY84328_SYS_DEV1_ANATXACONTROL4_LOWLATENCY_SELECTPATH_TX_ALIGN 0 17765 #define PHY84328_SYS_DEV1_ANATXACONTROL4_LOWLATENCY_SELECTPATH_TX_BITS 1 17766 #define PHY84328_SYS_DEV1_ANATXACONTROL4_LOWLATENCY_SELECTPATH_TX_SHIFT 11 17767 17768 /* sys_device1 :: anaTxAControl4 :: postcursor2_tap [10:08] */ 17769 #define PHY84328_SYS_DEV1_ANATXACONTROL4_POSTCURSOR2_TAP_MASK 0x0700 17770 #define PHY84328_SYS_DEV1_ANATXACONTROL4_POSTCURSOR2_TAP_ALIGN 0 17771 #define PHY84328_SYS_DEV1_ANATXACONTROL4_POSTCURSOR2_TAP_BITS 3 17772 #define PHY84328_SYS_DEV1_ANATXACONTROL4_POSTCURSOR2_TAP_SHIFT 8 17773 17774 /* sys_device1 :: anaTxAControl4 :: drv_bias_en [07:07] */ 17775 #define PHY84328_SYS_DEV1_ANATXACONTROL4_DRV_BIAS_EN_MASK 0x0080 17776 #define PHY84328_SYS_DEV1_ANATXACONTROL4_DRV_BIAS_EN_ALIGN 0 17777 #define PHY84328_SYS_DEV1_ANATXACONTROL4_DRV_BIAS_EN_BITS 1 17778 #define PHY84328_SYS_DEV1_ANATXACONTROL4_DRV_BIAS_EN_SHIFT 7 17779 17780 /* sys_device1 :: anaTxAControl4 :: i_tuneb [06:06] */ 17781 #define PHY84328_SYS_DEV1_ANATXACONTROL4_I_TUNEB_MASK 0x0040 17782 #define PHY84328_SYS_DEV1_ANATXACONTROL4_I_TUNEB_ALIGN 0 17783 #define PHY84328_SYS_DEV1_ANATXACONTROL4_I_TUNEB_BITS 1 17784 #define PHY84328_SYS_DEV1_ANATXACONTROL4_I_TUNEB_SHIFT 6 17785 17786 /* sys_device1 :: anaTxAControl4 :: test_bias_sel [05:04] */ 17787 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TEST_BIAS_SEL_MASK 0x0030 17788 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TEST_BIAS_SEL_ALIGN 0 17789 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TEST_BIAS_SEL_BITS 2 17790 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TEST_BIAS_SEL_SHIFT 4 17791 17792 /* sys_device1 :: anaTxAControl4 :: tx_pon [03:01] */ 17793 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TX_PON_MASK 0x000e 17794 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TX_PON_ALIGN 0 17795 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TX_PON_BITS 3 17796 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TX_PON_SHIFT 1 17797 17798 /* sys_device1 :: anaTxAControl4 :: tx_pi_bias [00:00] */ 17799 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TX_PI_BIAS_MASK 0x0001 17800 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TX_PI_BIAS_ALIGN 0 17801 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TX_PI_BIAS_BITS 1 17802 #define PHY84328_SYS_DEV1_ANATXACONTROL4_TX_PI_BIAS_SHIFT 0 17803 17804 17805 /**************************************************************************** 17806 * sys_device1 :: anaTxAControl5 17807 */ 17808 /* sys_device1 :: anaTxAControl5 :: reserved0 [15:04] */ 17809 #define PHY84328_SYS_DEV1_ANATXACONTROL5_RESERVED0_MASK 0xfff0 17810 #define PHY84328_SYS_DEV1_ANATXACONTROL5_RESERVED0_ALIGN 0 17811 #define PHY84328_SYS_DEV1_ANATXACONTROL5_RESERVED0_BITS 12 17812 #define PHY84328_SYS_DEV1_ANATXACONTROL5_RESERVED0_SHIFT 4 17813 17814 /* sys_device1 :: anaTxAControl5 :: clamp_enb [03:03] */ 17815 #define PHY84328_SYS_DEV1_ANATXACONTROL5_CLAMP_ENB_MASK 0x0008 17816 #define PHY84328_SYS_DEV1_ANATXACONTROL5_CLAMP_ENB_ALIGN 0 17817 #define PHY84328_SYS_DEV1_ANATXACONTROL5_CLAMP_ENB_BITS 1 17818 #define PHY84328_SYS_DEV1_ANATXACONTROL5_CLAMP_ENB_SHIFT 3 17819 17820 /* sys_device1 :: anaTxAControl5 :: testport_low_curr [02:02] */ 17821 #define PHY84328_SYS_DEV1_ANATXACONTROL5_TESTPORT_LOW_CURR_MASK 0x0004 17822 #define PHY84328_SYS_DEV1_ANATXACONTROL5_TESTPORT_LOW_CURR_ALIGN 0 17823 #define PHY84328_SYS_DEV1_ANATXACONTROL5_TESTPORT_LOW_CURR_BITS 1 17824 #define PHY84328_SYS_DEV1_ANATXACONTROL5_TESTPORT_LOW_CURR_SHIFT 2 17825 17826 /* sys_device1 :: anaTxAControl5 :: xfi_lowlatency_pdb [01:01] */ 17827 #define PHY84328_SYS_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_PDB_MASK 0x0002 17828 #define PHY84328_SYS_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_PDB_ALIGN 0 17829 #define PHY84328_SYS_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_PDB_BITS 1 17830 #define PHY84328_SYS_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_PDB_SHIFT 1 17831 17832 /* sys_device1 :: anaTxAControl5 :: xfi_lowlatency_fifo_resetb [00:00] */ 17833 #define PHY84328_SYS_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_FIFO_RESETB_MASK 0x0001 17834 #define PHY84328_SYS_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_FIFO_RESETB_ALIGN 0 17835 #define PHY84328_SYS_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_FIFO_RESETB_BITS 1 17836 #define PHY84328_SYS_DEV1_ANATXACONTROL5_XFI_LOWLATENCY_FIFO_RESETB_SHIFT 0 17837 17838 17839 /**************************************************************************** 17840 * sys_device1 :: anaTxAControl6 17841 */ 17842 /* sys_device1 :: anaTxAControl6 :: reserved0 [15:10] */ 17843 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED0_MASK 0xfc00 17844 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED0_ALIGN 0 17845 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED0_BITS 6 17846 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED0_SHIFT 10 17847 17848 /* sys_device1 :: anaTxAControl6 :: lowlatency_fifo_resetb [09:09] */ 17849 #define PHY84328_SYS_DEV1_ANATXACONTROL6_LOWLATENCY_FIFO_RESETB_MASK 0x0200 17850 #define PHY84328_SYS_DEV1_ANATXACONTROL6_LOWLATENCY_FIFO_RESETB_ALIGN 0 17851 #define PHY84328_SYS_DEV1_ANATXACONTROL6_LOWLATENCY_FIFO_RESETB_BITS 1 17852 #define PHY84328_SYS_DEV1_ANATXACONTROL6_LOWLATENCY_FIFO_RESETB_SHIFT 9 17853 17854 /* sys_device1 :: anaTxAControl6 :: lowlatency_path_select [08:08] */ 17855 #define PHY84328_SYS_DEV1_ANATXACONTROL6_LOWLATENCY_PATH_SELECT_MASK 0x0100 17856 #define PHY84328_SYS_DEV1_ANATXACONTROL6_LOWLATENCY_PATH_SELECT_ALIGN 0 17857 #define PHY84328_SYS_DEV1_ANATXACONTROL6_LOWLATENCY_PATH_SELECT_BITS 1 17858 #define PHY84328_SYS_DEV1_ANATXACONTROL6_LOWLATENCY_PATH_SELECT_SHIFT 8 17859 17860 /* sys_device1 :: anaTxAControl6 :: reserved1 [07:03] */ 17861 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED1_MASK 0x00f8 17862 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED1_ALIGN 0 17863 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED1_BITS 5 17864 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED1_SHIFT 3 17865 17866 /* sys_device1 :: anaTxAControl6 :: rloop [02:02] */ 17867 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RLOOP_MASK 0x0004 17868 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RLOOP_ALIGN 0 17869 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RLOOP_BITS 1 17870 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RLOOP_SHIFT 2 17871 17872 /* sys_device1 :: anaTxAControl6 :: reserved2 [01:01] */ 17873 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED2_MASK 0x0002 17874 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED2_ALIGN 0 17875 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED2_BITS 1 17876 #define PHY84328_SYS_DEV1_ANATXACONTROL6_RESERVED2_SHIFT 1 17877 17878 /* sys_device1 :: anaTxAControl6 :: disable_transmit [00:00] */ 17879 #define PHY84328_SYS_DEV1_ANATXACONTROL6_DISABLE_TRANSMIT_MASK 0x0001 17880 #define PHY84328_SYS_DEV1_ANATXACONTROL6_DISABLE_TRANSMIT_ALIGN 0 17881 #define PHY84328_SYS_DEV1_ANATXACONTROL6_DISABLE_TRANSMIT_BITS 1 17882 #define PHY84328_SYS_DEV1_ANATXACONTROL6_DISABLE_TRANSMIT_SHIFT 0 17883 17884 17885 /**************************************************************************** 17886 * sys_device1 :: anaTxAControl7 17887 */ 17888 /* sys_device1 :: anaTxAControl7 :: reserved0 [15:15] */ 17889 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED0_MASK 0x8000 17890 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED0_ALIGN 0 17891 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED0_BITS 1 17892 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED0_SHIFT 15 17893 17894 /* sys_device1 :: anaTxAControl7 :: PRBS_20_manual_width_value [14:14] */ 17895 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_VALUE_MASK 0x4000 17896 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_VALUE_ALIGN 0 17897 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_VALUE_BITS 1 17898 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_VALUE_SHIFT 14 17899 17900 /* sys_device1 :: anaTxAControl7 :: PRBS_20_manual_width_select_enable [13:13] */ 17901 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_SELECT_ENABLE_MASK 0x2000 17902 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_SELECT_ENABLE_ALIGN 0 17903 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_SELECT_ENABLE_BITS 1 17904 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_20_MANUAL_WIDTH_SELECT_ENABLE_SHIFT 13 17905 17906 /* sys_device1 :: anaTxAControl7 :: PRBS_Bit_order_swap [12:12] */ 17907 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_BIT_ORDER_SWAP_MASK 0x1000 17908 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_BIT_ORDER_SWAP_ALIGN 0 17909 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_BIT_ORDER_SWAP_BITS 1 17910 #define PHY84328_SYS_DEV1_ANATXACONTROL7_PRBS_BIT_ORDER_SWAP_SHIFT 12 17911 17912 /* sys_device1 :: anaTxAControl7 :: Tx_Bit_order_swap [11:11] */ 17913 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_BIT_ORDER_SWAP_MASK 0x0800 17914 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_BIT_ORDER_SWAP_ALIGN 0 17915 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_BIT_ORDER_SWAP_BITS 1 17916 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_BIT_ORDER_SWAP_SHIFT 11 17917 17918 /* sys_device1 :: anaTxAControl7 :: tx_reset [10:10] */ 17919 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_RESET_MASK 0x0400 17920 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_RESET_ALIGN 0 17921 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_RESET_BITS 1 17922 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_RESET_SHIFT 10 17923 17924 /* sys_device1 :: anaTxAControl7 :: tx_power_down [09:09] */ 17925 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_POWER_DOWN_MASK 0x0200 17926 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_POWER_DOWN_ALIGN 0 17927 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_POWER_DOWN_BITS 1 17928 #define PHY84328_SYS_DEV1_ANATXACONTROL7_TX_POWER_DOWN_SHIFT 9 17929 17930 /* sys_device1 :: anaTxAControl7 :: Lane_PRBS_order_new_b2 [08:08] */ 17931 #define PHY84328_SYS_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B2_MASK 0x0100 17932 #define PHY84328_SYS_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B2_ALIGN 0 17933 #define PHY84328_SYS_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B2_BITS 1 17934 #define PHY84328_SYS_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B2_SHIFT 8 17935 17936 /* sys_device1 :: anaTxAControl7 :: reserved1 [07:07] */ 17937 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED1_MASK 0x0080 17938 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED1_ALIGN 0 17939 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED1_BITS 1 17940 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED1_SHIFT 7 17941 17942 /* sys_device1 :: anaTxAControl7 :: select_new_prbs [06:06] */ 17943 #define PHY84328_SYS_DEV1_ANATXACONTROL7_SELECT_NEW_PRBS_MASK 0x0040 17944 #define PHY84328_SYS_DEV1_ANATXACONTROL7_SELECT_NEW_PRBS_ALIGN 0 17945 #define PHY84328_SYS_DEV1_ANATXACONTROL7_SELECT_NEW_PRBS_BITS 1 17946 #define PHY84328_SYS_DEV1_ANATXACONTROL7_SELECT_NEW_PRBS_SHIFT 6 17947 17948 /* sys_device1 :: anaTxAControl7 :: new_prbs_en [05:05] */ 17949 #define PHY84328_SYS_DEV1_ANATXACONTROL7_NEW_PRBS_EN_MASK 0x0020 17950 #define PHY84328_SYS_DEV1_ANATXACONTROL7_NEW_PRBS_EN_ALIGN 0 17951 #define PHY84328_SYS_DEV1_ANATXACONTROL7_NEW_PRBS_EN_BITS 1 17952 #define PHY84328_SYS_DEV1_ANATXACONTROL7_NEW_PRBS_EN_SHIFT 5 17953 17954 /* sys_device1 :: anaTxAControl7 :: new_prbs_inv [04:04] */ 17955 #define PHY84328_SYS_DEV1_ANATXACONTROL7_NEW_PRBS_INV_MASK 0x0010 17956 #define PHY84328_SYS_DEV1_ANATXACONTROL7_NEW_PRBS_INV_ALIGN 0 17957 #define PHY84328_SYS_DEV1_ANATXACONTROL7_NEW_PRBS_INV_BITS 1 17958 #define PHY84328_SYS_DEV1_ANATXACONTROL7_NEW_PRBS_INV_SHIFT 4 17959 17960 /* sys_device1 :: anaTxAControl7 :: Lane_PRBS_order_new_b1_0 [03:02] */ 17961 #define PHY84328_SYS_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B1_0_MASK 0x000c 17962 #define PHY84328_SYS_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B1_0_ALIGN 0 17963 #define PHY84328_SYS_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B1_0_BITS 2 17964 #define PHY84328_SYS_DEV1_ANATXACONTROL7_LANE_PRBS_ORDER_NEW_B1_0_SHIFT 2 17965 17966 /* sys_device1 :: anaTxAControl7 :: reserved2 [01:00] */ 17967 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED2_MASK 0x0003 17968 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED2_ALIGN 0 17969 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED2_BITS 2 17970 #define PHY84328_SYS_DEV1_ANATXACONTROL7_RESERVED2_SHIFT 0 17971 17972 17973 /**************************************************************************** 17974 * sys_device1 :: anaRxStatus 17975 */ 17976 /* sys_device1 :: anaRxStatus :: rxStatus [15:00] */ 17977 #define PHY84328_SYS_DEV1_ANARXSTATUS_RXSTATUS_MASK 0xffff 17978 #define PHY84328_SYS_DEV1_ANARXSTATUS_RXSTATUS_ALIGN 0 17979 #define PHY84328_SYS_DEV1_ANARXSTATUS_RXSTATUS_BITS 16 17980 #define PHY84328_SYS_DEV1_ANARXSTATUS_RXSTATUS_SHIFT 0 17981 17982 17983 /**************************************************************************** 17984 * sys_device1 :: anaRxControl 17985 */ 17986 /* sys_device1 :: anaRxControl :: reserved0 [15:13] */ 17987 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED0_MASK 0xe000 17988 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED0_ALIGN 0 17989 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED0_BITS 3 17990 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED0_SHIFT 13 17991 17992 /* sys_device1 :: anaRxControl :: reserved_SigDetect [12:10] */ 17993 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED_SIGDETECT_MASK 0x1c00 17994 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED_SIGDETECT_ALIGN 0 17995 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED_SIGDETECT_BITS 3 17996 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED_SIGDETECT_SHIFT 10 17997 17998 /* sys_device1 :: anaRxControl :: override_sigdet_en [09:09] */ 17999 #define PHY84328_SYS_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 18000 #define PHY84328_SYS_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 18001 #define PHY84328_SYS_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 18002 #define PHY84328_SYS_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 18003 18004 /* sys_device1 :: anaRxControl :: override_sigdet_val [08:08] */ 18005 #define PHY84328_SYS_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 18006 #define PHY84328_SYS_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 18007 #define PHY84328_SYS_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 18008 #define PHY84328_SYS_DEV1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 18009 18010 /* sys_device1 :: anaRxControl :: reserved1 [07:07] */ 18011 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED1_MASK 0x0080 18012 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED1_ALIGN 0 18013 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED1_BITS 1 18014 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED1_SHIFT 7 18015 18016 /* sys_device1 :: anaRxControl :: reserved_phfreq_rst_dis_fst_SM [06:06] */ 18017 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED_PHFREQ_RST_DIS_FST_SM_MASK 0x0040 18018 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED_PHFREQ_RST_DIS_FST_SM_ALIGN 0 18019 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED_PHFREQ_RST_DIS_FST_SM_BITS 1 18020 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED_PHFREQ_RST_DIS_FST_SM_SHIFT 6 18021 18022 /* sys_device1 :: anaRxControl :: reserved2 [05:03] */ 18023 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED2_MASK 0x0038 18024 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED2_ALIGN 0 18025 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED2_BITS 3 18026 #define PHY84328_SYS_DEV1_ANARXCONTROL_RESERVED2_SHIFT 3 18027 18028 /* sys_device1 :: anaRxControl :: status_sel [02:00] */ 18029 #define PHY84328_SYS_DEV1_ANARXCONTROL_STATUS_SEL_MASK 0x0007 18030 #define PHY84328_SYS_DEV1_ANARXCONTROL_STATUS_SEL_ALIGN 0 18031 #define PHY84328_SYS_DEV1_ANARXCONTROL_STATUS_SEL_BITS 3 18032 #define PHY84328_SYS_DEV1_ANARXCONTROL_STATUS_SEL_SHIFT 0 18033 18034 18035 /**************************************************************************** 18036 * sys_device1 :: anaRxSigdet 18037 */ 18038 /* sys_device1 :: anaRxSigdet :: sigdetTime_SM [15:08] */ 18039 #define PHY84328_SYS_DEV1_ANARXSIGDET_SIGDETTIME_SM_MASK 0xff00 18040 #define PHY84328_SYS_DEV1_ANARXSIGDET_SIGDETTIME_SM_ALIGN 0 18041 #define PHY84328_SYS_DEV1_ANARXSIGDET_SIGDETTIME_SM_BITS 8 18042 #define PHY84328_SYS_DEV1_ANARXSIGDET_SIGDETTIME_SM_SHIFT 8 18043 18044 /* sys_device1 :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */ 18045 #define PHY84328_SYS_DEV1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK 0x0080 18046 #define PHY84328_SYS_DEV1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN 0 18047 #define PHY84328_SYS_DEV1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS 1 18048 #define PHY84328_SYS_DEV1_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT 7 18049 18050 /* sys_device1 :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */ 18051 #define PHY84328_SYS_DEV1_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK 0x0040 18052 #define PHY84328_SYS_DEV1_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN 0 18053 #define PHY84328_SYS_DEV1_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS 1 18054 #define PHY84328_SYS_DEV1_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT 6 18055 18056 /* sys_device1 :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */ 18057 #define PHY84328_SYS_DEV1_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK 0x0020 18058 #define PHY84328_SYS_DEV1_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN 0 18059 #define PHY84328_SYS_DEV1_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS 1 18060 #define PHY84328_SYS_DEV1_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT 5 18061 18062 /* sys_device1 :: anaRxSigdet :: rx_sigdet_r [04:04] */ 18063 #define PHY84328_SYS_DEV1_ANARXSIGDET_RX_SIGDET_R_MASK 0x0010 18064 #define PHY84328_SYS_DEV1_ANARXSIGDET_RX_SIGDET_R_ALIGN 0 18065 #define PHY84328_SYS_DEV1_ANARXSIGDET_RX_SIGDET_R_BITS 1 18066 #define PHY84328_SYS_DEV1_ANARXSIGDET_RX_SIGDET_R_SHIFT 4 18067 18068 /* sys_device1 :: anaRxSigdet :: rx_sigdet_force_r [03:03] */ 18069 #define PHY84328_SYS_DEV1_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK 0x0008 18070 #define PHY84328_SYS_DEV1_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN 0 18071 #define PHY84328_SYS_DEV1_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS 1 18072 #define PHY84328_SYS_DEV1_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT 3 18073 18074 /* sys_device1 :: anaRxSigdet :: invert_rx_sigdet [02:02] */ 18075 #define PHY84328_SYS_DEV1_ANARXSIGDET_INVERT_RX_SIGDET_MASK 0x0004 18076 #define PHY84328_SYS_DEV1_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN 0 18077 #define PHY84328_SYS_DEV1_ANARXSIGDET_INVERT_RX_SIGDET_BITS 1 18078 #define PHY84328_SYS_DEV1_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT 2 18079 18080 /* sys_device1 :: anaRxSigdet :: reserved0 [01:00] */ 18081 #define PHY84328_SYS_DEV1_ANARXSIGDET_RESERVED0_MASK 0x0003 18082 #define PHY84328_SYS_DEV1_ANARXSIGDET_RESERVED0_ALIGN 0 18083 #define PHY84328_SYS_DEV1_ANARXSIGDET_RESERVED0_BITS 2 18084 #define PHY84328_SYS_DEV1_ANARXSIGDET_RESERVED0_SHIFT 0 18085 18086 18087 /**************************************************************************** 18088 * sys_device1 :: anaRxAControl4 18089 */ 18090 /* sys_device1 :: anaRxAControl4 :: low_latency_mode [15:15] */ 18091 #define PHY84328_SYS_DEV1_ANARXACONTROL4_LOW_LATENCY_MODE_MASK 0x8000 18092 #define PHY84328_SYS_DEV1_ANARXACONTROL4_LOW_LATENCY_MODE_ALIGN 0 18093 #define PHY84328_SYS_DEV1_ANARXACONTROL4_LOW_LATENCY_MODE_BITS 1 18094 #define PHY84328_SYS_DEV1_ANARXACONTROL4_LOW_LATENCY_MODE_SHIFT 15 18095 18096 /* sys_device1 :: anaRxAControl4 :: fastacq_pf [14:14] */ 18097 #define PHY84328_SYS_DEV1_ANARXACONTROL4_FASTACQ_PF_MASK 0x4000 18098 #define PHY84328_SYS_DEV1_ANARXACONTROL4_FASTACQ_PF_ALIGN 0 18099 #define PHY84328_SYS_DEV1_ANARXACONTROL4_FASTACQ_PF_BITS 1 18100 #define PHY84328_SYS_DEV1_ANARXACONTROL4_FASTACQ_PF_SHIFT 14 18101 18102 /* sys_device1 :: anaRxAControl4 :: i1p25dfe [13:13] */ 18103 #define PHY84328_SYS_DEV1_ANARXACONTROL4_I1P25DFE_MASK 0x2000 18104 #define PHY84328_SYS_DEV1_ANARXACONTROL4_I1P25DFE_ALIGN 0 18105 #define PHY84328_SYS_DEV1_ANARXACONTROL4_I1P25DFE_BITS 1 18106 #define PHY84328_SYS_DEV1_ANARXACONTROL4_I1P25DFE_SHIFT 13 18107 18108 /* sys_device1 :: anaRxAControl4 :: i4deadzone [12:12] */ 18109 #define PHY84328_SYS_DEV1_ANARXACONTROL4_I4DEADZONE_MASK 0x1000 18110 #define PHY84328_SYS_DEV1_ANARXACONTROL4_I4DEADZONE_ALIGN 0 18111 #define PHY84328_SYS_DEV1_ANARXACONTROL4_I4DEADZONE_BITS 1 18112 #define PHY84328_SYS_DEV1_ANARXACONTROL4_I4DEADZONE_SHIFT 12 18113 18114 /* sys_device1 :: anaRxAControl4 :: imax_sigdet [11:11] */ 18115 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_SIGDET_MASK 0x0800 18116 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_SIGDET_ALIGN 0 18117 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_SIGDET_BITS 1 18118 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_SIGDET_SHIFT 11 18119 18120 /* sys_device1 :: anaRxAControl4 :: imode_sigdet [10:10] */ 18121 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_SIGDET_MASK 0x0400 18122 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_SIGDET_ALIGN 0 18123 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_SIGDET_BITS 1 18124 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_SIGDET_SHIFT 10 18125 18126 /* sys_device1 :: anaRxAControl4 :: imin_sigdet [09:09] */ 18127 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_SIGDET_MASK 0x0200 18128 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_SIGDET_ALIGN 0 18129 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_SIGDET_BITS 1 18130 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_SIGDET_SHIFT 9 18131 18132 /* sys_device1 :: anaRxAControl4 :: imax_yp_eyediag [08:08] */ 18133 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_YP_EYEDIAG_MASK 0x0100 18134 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_YP_EYEDIAG_ALIGN 0 18135 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_YP_EYEDIAG_BITS 1 18136 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_YP_EYEDIAG_SHIFT 8 18137 18138 /* sys_device1 :: anaRxAControl4 :: imode_yp_eyediag [07:07] */ 18139 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_YP_EYEDIAG_MASK 0x0080 18140 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_YP_EYEDIAG_ALIGN 0 18141 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_YP_EYEDIAG_BITS 1 18142 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_YP_EYEDIAG_SHIFT 7 18143 18144 /* sys_device1 :: anaRxAControl4 :: imin_yp_eyediag [06:06] */ 18145 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_YP_EYEDIAG_MASK 0x0040 18146 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_YP_EYEDIAG_ALIGN 0 18147 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_YP_EYEDIAG_BITS 1 18148 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_YP_EYEDIAG_SHIFT 6 18149 18150 /* sys_device1 :: anaRxAControl4 :: imax_interp [05:05] */ 18151 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_INTERP_MASK 0x0020 18152 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_INTERP_ALIGN 0 18153 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_INTERP_BITS 1 18154 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_INTERP_SHIFT 5 18155 18156 /* sys_device1 :: anaRxAControl4 :: imode_interp [04:04] */ 18157 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_INTERP_MASK 0x0010 18158 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_INTERP_ALIGN 0 18159 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_INTERP_BITS 1 18160 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_INTERP_SHIFT 4 18161 18162 /* sys_device1 :: anaRxAControl4 :: imin_interp [03:03] */ 18163 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_INTERP_MASK 0x0008 18164 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_INTERP_ALIGN 0 18165 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_INTERP_BITS 1 18166 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_INTERP_SHIFT 3 18167 18168 /* sys_device1 :: anaRxAControl4 :: imax_pf [02:02] */ 18169 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_PF_MASK 0x0004 18170 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_PF_ALIGN 0 18171 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_PF_BITS 1 18172 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMAX_PF_SHIFT 2 18173 18174 /* sys_device1 :: anaRxAControl4 :: imode_pf [01:01] */ 18175 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_PF_MASK 0x0002 18176 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_PF_ALIGN 0 18177 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_PF_BITS 1 18178 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMODE_PF_SHIFT 1 18179 18180 /* sys_device1 :: anaRxAControl4 :: imin_pf [00:00] */ 18181 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_PF_MASK 0x0001 18182 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_PF_ALIGN 0 18183 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_PF_BITS 1 18184 #define PHY84328_SYS_DEV1_ANARXACONTROL4_IMIN_PF_SHIFT 0 18185 18186 18187 /**************************************************************************** 18188 * sys_device1 :: anaRxControl2 18189 */ 18190 /* sys_device1 :: anaRxControl2 :: reserved0 [15:15] */ 18191 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED0_MASK 0x8000 18192 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED0_ALIGN 0 18193 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED0_BITS 1 18194 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED0_SHIFT 15 18195 18196 /* sys_device1 :: anaRxControl2 :: rx_prbs_w_val [14:14] */ 18197 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_W_VAL_MASK 0x4000 18198 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_W_VAL_ALIGN 0 18199 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_W_VAL_BITS 1 18200 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_W_VAL_SHIFT 14 18201 18202 /* sys_device1 :: anaRxControl2 :: rx_prbs_w_force [13:13] */ 18203 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_W_FORCE_MASK 0x2000 18204 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_W_FORCE_ALIGN 0 18205 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_W_FORCE_BITS 1 18206 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_W_FORCE_SHIFT 13 18207 18208 /* sys_device1 :: anaRxControl2 :: rx_prbs_bswap [12:12] */ 18209 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_BSWAP_MASK 0x1000 18210 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_BSWAP_ALIGN 0 18211 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_BSWAP_BITS 1 18212 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_PRBS_BSWAP_SHIFT 12 18213 18214 /* sys_device1 :: anaRxControl2 :: rx_bitswap [11:11] */ 18215 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_BITSWAP_MASK 0x0800 18216 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_BITSWAP_ALIGN 0 18217 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_BITSWAP_BITS 1 18218 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RX_BITSWAP_SHIFT 11 18219 18220 /* sys_device1 :: anaRxControl2 :: rst_rx_r [10:10] */ 18221 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RST_RX_R_MASK 0x0400 18222 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RST_RX_R_ALIGN 0 18223 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RST_RX_R_BITS 1 18224 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RST_RX_R_SHIFT 10 18225 18226 /* sys_device1 :: anaRxControl2 :: pwdwn_rx_r [09:09] */ 18227 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PWDWN_RX_R_MASK 0x0200 18228 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PWDWN_RX_R_ALIGN 0 18229 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PWDWN_RX_R_BITS 1 18230 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PWDWN_RX_R_SHIFT 9 18231 18232 /* sys_device1 :: anaRxControl2 :: prbs_order_rx_r_2 [08:08] */ 18233 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_2_MASK 0x0100 18234 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_2_ALIGN 0 18235 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_2_BITS 1 18236 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_2_SHIFT 8 18237 18238 /* sys_device1 :: anaRxControl2 :: reserved1 [07:07] */ 18239 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED1_MASK 0x0080 18240 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED1_ALIGN 0 18241 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED1_BITS 1 18242 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED1_SHIFT 7 18243 18244 /* sys_device1 :: anaRxControl2 :: prbs_sel_rx_r [06:06] */ 18245 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_SEL_RX_R_MASK 0x0040 18246 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_SEL_RX_R_ALIGN 0 18247 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_SEL_RX_R_BITS 1 18248 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_SEL_RX_R_SHIFT 6 18249 18250 /* sys_device1 :: anaRxControl2 :: prbs_en_rx_r [05:05] */ 18251 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_EN_RX_R_MASK 0x0020 18252 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_EN_RX_R_ALIGN 0 18253 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_EN_RX_R_BITS 1 18254 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_EN_RX_R_SHIFT 5 18255 18256 /* sys_device1 :: anaRxControl2 :: prbs_inv_rx_r [04:04] */ 18257 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_INV_RX_R_MASK 0x0010 18258 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_INV_RX_R_ALIGN 0 18259 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_INV_RX_R_BITS 1 18260 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_INV_RX_R_SHIFT 4 18261 18262 /* sys_device1 :: anaRxControl2 :: prbs_order_rx_r [03:02] */ 18263 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_MASK 0x000c 18264 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_ALIGN 0 18265 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_BITS 2 18266 #define PHY84328_SYS_DEV1_ANARXCONTROL2_PRBS_ORDER_RX_R_SHIFT 2 18267 18268 /* sys_device1 :: anaRxControl2 :: reserved2 [01:01] */ 18269 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED2_MASK 0x0002 18270 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED2_ALIGN 0 18271 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED2_BITS 1 18272 #define PHY84328_SYS_DEV1_ANARXCONTROL2_RESERVED2_SHIFT 1 18273 18274 /* sys_device1 :: anaRxControl2 :: errcnt_15 [00:00] */ 18275 #define PHY84328_SYS_DEV1_ANARXCONTROL2_ERRCNT_15_MASK 0x0001 18276 #define PHY84328_SYS_DEV1_ANARXCONTROL2_ERRCNT_15_ALIGN 0 18277 #define PHY84328_SYS_DEV1_ANARXCONTROL2_ERRCNT_15_BITS 1 18278 #define PHY84328_SYS_DEV1_ANARXCONTROL2_ERRCNT_15_SHIFT 0 18279 18280 18281 /**************************************************************************** 18282 * sys_device1 :: anaRxControl1 18283 */ 18284 /* sys_device1 :: anaRxControl1 :: fpat_md [15:15] */ 18285 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FPAT_MD_MASK 0x8000 18286 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FPAT_MD_ALIGN 0 18287 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FPAT_MD_BITS 1 18288 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FPAT_MD_SHIFT 15 18289 18290 /* sys_device1 :: anaRxControl1 :: pkt_count_en [14:14] */ 18291 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PKT_COUNT_EN_MASK 0x4000 18292 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PKT_COUNT_EN_ALIGN 0 18293 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PKT_COUNT_EN_BITS 1 18294 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PKT_COUNT_EN_SHIFT 14 18295 18296 /* sys_device1 :: anaRxControl1 :: staMuxRegDis [13:13] */ 18297 #define PHY84328_SYS_DEV1_ANARXCONTROL1_STAMUXREGDIS_MASK 0x2000 18298 #define PHY84328_SYS_DEV1_ANARXCONTROL1_STAMUXREGDIS_ALIGN 0 18299 #define PHY84328_SYS_DEV1_ANARXCONTROL1_STAMUXREGDIS_BITS 1 18300 #define PHY84328_SYS_DEV1_ANARXCONTROL1_STAMUXREGDIS_SHIFT 13 18301 18302 /* sys_device1 :: anaRxControl1 :: prbs_clr_dis [12:12] */ 18303 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PRBS_CLR_DIS_MASK 0x1000 18304 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PRBS_CLR_DIS_ALIGN 0 18305 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PRBS_CLR_DIS_BITS 1 18306 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PRBS_CLR_DIS_SHIFT 12 18307 18308 /* sys_device1 :: anaRxControl1 :: rxd_dec_sel [11:11] */ 18309 #define PHY84328_SYS_DEV1_ANARXCONTROL1_RXD_DEC_SEL_MASK 0x0800 18310 #define PHY84328_SYS_DEV1_ANARXCONTROL1_RXD_DEC_SEL_ALIGN 0 18311 #define PHY84328_SYS_DEV1_ANARXCONTROL1_RXD_DEC_SEL_BITS 1 18312 #define PHY84328_SYS_DEV1_ANARXCONTROL1_RXD_DEC_SEL_SHIFT 11 18313 18314 /* sys_device1 :: anaRxControl1 :: cgbad_tst [10:10] */ 18315 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CGBAD_TST_MASK 0x0400 18316 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CGBAD_TST_ALIGN 0 18317 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CGBAD_TST_BITS 1 18318 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CGBAD_TST_SHIFT 10 18319 18320 /* sys_device1 :: anaRxControl1 :: Emon_en [09:09] */ 18321 #define PHY84328_SYS_DEV1_ANARXCONTROL1_EMON_EN_MASK 0x0200 18322 #define PHY84328_SYS_DEV1_ANARXCONTROL1_EMON_EN_ALIGN 0 18323 #define PHY84328_SYS_DEV1_ANARXCONTROL1_EMON_EN_BITS 1 18324 #define PHY84328_SYS_DEV1_ANARXCONTROL1_EMON_EN_SHIFT 9 18325 18326 /* sys_device1 :: anaRxControl1 :: prbs_en [08:08] */ 18327 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PRBS_EN_MASK 0x0100 18328 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PRBS_EN_ALIGN 0 18329 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PRBS_EN_BITS 1 18330 #define PHY84328_SYS_DEV1_ANARXCONTROL1_PRBS_EN_SHIFT 8 18331 18332 /* sys_device1 :: anaRxControl1 :: cgbad_en [07:07] */ 18333 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CGBAD_EN_MASK 0x0080 18334 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CGBAD_EN_ALIGN 0 18335 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CGBAD_EN_BITS 1 18336 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CGBAD_EN_SHIFT 7 18337 18338 /* sys_device1 :: anaRxControl1 :: cstretch [06:06] */ 18339 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CSTRETCH_MASK 0x0040 18340 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CSTRETCH_ALIGN 0 18341 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CSTRETCH_BITS 1 18342 #define PHY84328_SYS_DEV1_ANARXCONTROL1_CSTRETCH_SHIFT 6 18343 18344 /* sys_device1 :: anaRxControl1 :: comma_low_byte_SM [05:05] */ 18345 #define PHY84328_SYS_DEV1_ANARXCONTROL1_COMMA_LOW_BYTE_SM_MASK 0x0020 18346 #define PHY84328_SYS_DEV1_ANARXCONTROL1_COMMA_LOW_BYTE_SM_ALIGN 0 18347 #define PHY84328_SYS_DEV1_ANARXCONTROL1_COMMA_LOW_BYTE_SM_BITS 1 18348 #define PHY84328_SYS_DEV1_ANARXCONTROL1_COMMA_LOW_BYTE_SM_SHIFT 5 18349 18350 /* sys_device1 :: anaRxControl1 :: comma_byte_adj_en_SM [04:04] */ 18351 #define PHY84328_SYS_DEV1_ANARXCONTROL1_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 18352 #define PHY84328_SYS_DEV1_ANARXCONTROL1_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 18353 #define PHY84328_SYS_DEV1_ANARXCONTROL1_COMMA_BYTE_ADJ_EN_SM_BITS 1 18354 #define PHY84328_SYS_DEV1_ANARXCONTROL1_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 18355 18356 /* sys_device1 :: anaRxControl1 :: reserved0 [03:02] */ 18357 #define PHY84328_SYS_DEV1_ANARXCONTROL1_RESERVED0_MASK 0x000c 18358 #define PHY84328_SYS_DEV1_ANARXCONTROL1_RESERVED0_ALIGN 0 18359 #define PHY84328_SYS_DEV1_ANARXCONTROL1_RESERVED0_BITS 2 18360 #define PHY84328_SYS_DEV1_ANARXCONTROL1_RESERVED0_SHIFT 2 18361 18362 /* sys_device1 :: anaRxControl1 :: freq_sel_force [01:01] */ 18363 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FREQ_SEL_FORCE_MASK 0x0002 18364 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FREQ_SEL_FORCE_ALIGN 0 18365 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FREQ_SEL_FORCE_BITS 1 18366 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FREQ_SEL_FORCE_SHIFT 1 18367 18368 /* sys_device1 :: anaRxControl1 :: freq_sel [00:00] */ 18369 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FREQ_SEL_MASK 0x0001 18370 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FREQ_SEL_ALIGN 0 18371 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FREQ_SEL_BITS 1 18372 #define PHY84328_SYS_DEV1_ANARXCONTROL1_FREQ_SEL_SHIFT 0 18373 18374 18375 /**************************************************************************** 18376 * sys_device1 :: anaRxAControl1 18377 */ 18378 /* sys_device1 :: anaRxAControl1 :: imode_cmd [15:15] */ 18379 #define PHY84328_SYS_DEV1_ANARXACONTROL1_IMODE_CMD_MASK 0x8000 18380 #define PHY84328_SYS_DEV1_ANARXACONTROL1_IMODE_CMD_ALIGN 0 18381 #define PHY84328_SYS_DEV1_ANARXACONTROL1_IMODE_CMD_BITS 1 18382 #define PHY84328_SYS_DEV1_ANARXACONTROL1_IMODE_CMD_SHIFT 15 18383 18384 /* sys_device1 :: anaRxAControl1 :: imin_cmd [14:14] */ 18385 #define PHY84328_SYS_DEV1_ANARXACONTROL1_IMIN_CMD_MASK 0x4000 18386 #define PHY84328_SYS_DEV1_ANARXACONTROL1_IMIN_CMD_ALIGN 0 18387 #define PHY84328_SYS_DEV1_ANARXACONTROL1_IMIN_CMD_BITS 1 18388 #define PHY84328_SYS_DEV1_ANARXACONTROL1_IMIN_CMD_SHIFT 14 18389 18390 /* sys_device1 :: anaRxAControl1 :: en_10gmode [13:13] */ 18391 #define PHY84328_SYS_DEV1_ANARXACONTROL1_EN_10GMODE_MASK 0x2000 18392 #define PHY84328_SYS_DEV1_ANARXACONTROL1_EN_10GMODE_ALIGN 0 18393 #define PHY84328_SYS_DEV1_ANARXACONTROL1_EN_10GMODE_BITS 1 18394 #define PHY84328_SYS_DEV1_ANARXACONTROL1_EN_10GMODE_SHIFT 13 18395 18396 /* sys_device1 :: anaRxAControl1 :: dc_mode [12:12] */ 18397 #define PHY84328_SYS_DEV1_ANARXACONTROL1_DC_MODE_MASK 0x1000 18398 #define PHY84328_SYS_DEV1_ANARXACONTROL1_DC_MODE_ALIGN 0 18399 #define PHY84328_SYS_DEV1_ANARXACONTROL1_DC_MODE_BITS 1 18400 #define PHY84328_SYS_DEV1_ANARXACONTROL1_DC_MODE_SHIFT 12 18401 18402 /* sys_device1 :: anaRxAControl1 :: vga_bw_extension [11:11] */ 18403 #define PHY84328_SYS_DEV1_ANARXACONTROL1_VGA_BW_EXTENSION_MASK 0x0800 18404 #define PHY84328_SYS_DEV1_ANARXACONTROL1_VGA_BW_EXTENSION_ALIGN 0 18405 #define PHY84328_SYS_DEV1_ANARXACONTROL1_VGA_BW_EXTENSION_BITS 1 18406 #define PHY84328_SYS_DEV1_ANARXACONTROL1_VGA_BW_EXTENSION_SHIFT 11 18407 18408 /* sys_device1 :: anaRxAControl1 :: refh_rx [10:10] */ 18409 #define PHY84328_SYS_DEV1_ANARXACONTROL1_REFH_RX_MASK 0x0400 18410 #define PHY84328_SYS_DEV1_ANARXACONTROL1_REFH_RX_ALIGN 0 18411 #define PHY84328_SYS_DEV1_ANARXACONTROL1_REFH_RX_BITS 1 18412 #define PHY84328_SYS_DEV1_ANARXACONTROL1_REFH_RX_SHIFT 10 18413 18414 /* sys_device1 :: anaRxAControl1 :: refl_rx [09:09] */ 18415 #define PHY84328_SYS_DEV1_ANARXACONTROL1_REFL_RX_MASK 0x0200 18416 #define PHY84328_SYS_DEV1_ANARXACONTROL1_REFL_RX_ALIGN 0 18417 #define PHY84328_SYS_DEV1_ANARXACONTROL1_REFL_RX_BITS 1 18418 #define PHY84328_SYS_DEV1_ANARXACONTROL1_REFL_RX_SHIFT 9 18419 18420 /* sys_device1 :: anaRxAControl1 :: tport_en [08:08] */ 18421 #define PHY84328_SYS_DEV1_ANARXACONTROL1_TPORT_EN_MASK 0x0100 18422 #define PHY84328_SYS_DEV1_ANARXACONTROL1_TPORT_EN_ALIGN 0 18423 #define PHY84328_SYS_DEV1_ANARXACONTROL1_TPORT_EN_BITS 1 18424 #define PHY84328_SYS_DEV1_ANARXACONTROL1_TPORT_EN_SHIFT 8 18425 18426 /* sys_device1 :: anaRxAControl1 :: vddrb_bgb [07:07] */ 18427 #define PHY84328_SYS_DEV1_ANARXACONTROL1_VDDRB_BGB_MASK 0x0080 18428 #define PHY84328_SYS_DEV1_ANARXACONTROL1_VDDRB_BGB_ALIGN 0 18429 #define PHY84328_SYS_DEV1_ANARXACONTROL1_VDDRB_BGB_BITS 1 18430 #define PHY84328_SYS_DEV1_ANARXACONTROL1_VDDRB_BGB_SHIFT 7 18431 18432 /* sys_device1 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 18433 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 18434 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 18435 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SIG_PWRDN_BITS 1 18436 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 18437 18438 /* sys_device1 :: anaRxAControl1 :: offset_ctrl [05:03] */ 18439 #define PHY84328_SYS_DEV1_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 18440 #define PHY84328_SYS_DEV1_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 18441 #define PHY84328_SYS_DEV1_ANARXACONTROL1_OFFSET_CTRL_BITS 3 18442 #define PHY84328_SYS_DEV1_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 18443 18444 /* sys_device1 :: anaRxAControl1 :: offset_sel [02:02] */ 18445 #define PHY84328_SYS_DEV1_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 18446 #define PHY84328_SYS_DEV1_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 18447 #define PHY84328_SYS_DEV1_ANARXACONTROL1_OFFSET_SEL_BITS 1 18448 #define PHY84328_SYS_DEV1_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 18449 18450 /* sys_device1 :: anaRxAControl1 :: sel_dfeckdelay1 [01:01] */ 18451 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SEL_DFECKDELAY1_MASK 0x0002 18452 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SEL_DFECKDELAY1_ALIGN 0 18453 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SEL_DFECKDELAY1_BITS 1 18454 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SEL_DFECKDELAY1_SHIFT 1 18455 18456 /* sys_device1 :: anaRxAControl1 :: sel_dfeckdelay0 [00:00] */ 18457 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SEL_DFECKDELAY0_MASK 0x0001 18458 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SEL_DFECKDELAY0_ALIGN 0 18459 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SEL_DFECKDELAY0_BITS 1 18460 #define PHY84328_SYS_DEV1_ANARXACONTROL1_SEL_DFECKDELAY0_SHIFT 0 18461 18462 18463 /**************************************************************************** 18464 * sys_device1 :: anaRxAControl2 18465 */ 18466 /* sys_device1 :: anaRxAControl2 :: imax_ctat [15:15] */ 18467 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_CTAT_MASK 0x8000 18468 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_CTAT_ALIGN 0 18469 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_CTAT_BITS 1 18470 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_CTAT_SHIFT 15 18471 18472 /* sys_device1 :: anaRxAControl2 :: imode_ctat [14:14] */ 18473 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_CTAT_MASK 0x4000 18474 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_CTAT_ALIGN 0 18475 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_CTAT_BITS 1 18476 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_CTAT_SHIFT 14 18477 18478 /* sys_device1 :: anaRxAControl2 :: imin_ctat [13:13] */ 18479 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_CTAT_MASK 0x2000 18480 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_CTAT_ALIGN 0 18481 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_CTAT_BITS 1 18482 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_CTAT_SHIFT 13 18483 18484 /* sys_device1 :: anaRxAControl2 :: imax_peaking [12:12] */ 18485 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_PEAKING_MASK 0x1000 18486 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_PEAKING_ALIGN 0 18487 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_PEAKING_BITS 1 18488 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_PEAKING_SHIFT 12 18489 18490 /* sys_device1 :: anaRxAControl2 :: imode_peaking [11:11] */ 18491 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_PEAKING_MASK 0x0800 18492 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_PEAKING_ALIGN 0 18493 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_PEAKING_BITS 1 18494 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_PEAKING_SHIFT 11 18495 18496 /* sys_device1 :: anaRxAControl2 :: imin_peaking [10:10] */ 18497 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_PEAKING_MASK 0x0400 18498 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_PEAKING_ALIGN 0 18499 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_PEAKING_BITS 1 18500 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_PEAKING_SHIFT 10 18501 18502 /* sys_device1 :: anaRxAControl2 :: imax_dfesum [09:09] */ 18503 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 18504 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 18505 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_DFESUM_BITS 1 18506 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 18507 18508 /* sys_device1 :: anaRxAControl2 :: imode_dfesum [08:08] */ 18509 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 18510 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 18511 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_DFESUM_BITS 1 18512 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 18513 18514 /* sys_device1 :: anaRxAControl2 :: imin_dfesum [07:07] */ 18515 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 18516 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 18517 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_DFESUM_BITS 1 18518 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 18519 18520 /* sys_device1 :: anaRxAControl2 :: imax_vga [06:06] */ 18521 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 18522 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_VGA_ALIGN 0 18523 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_VGA_BITS 1 18524 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_VGA_SHIFT 6 18525 18526 /* sys_device1 :: anaRxAControl2 :: imode_vga [05:05] */ 18527 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 18528 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_VGA_ALIGN 0 18529 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_VGA_BITS 1 18530 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_VGA_SHIFT 5 18531 18532 /* sys_device1 :: anaRxAControl2 :: imin_vga [04:04] */ 18533 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 18534 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_VGA_ALIGN 0 18535 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_VGA_BITS 1 18536 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_VGA_SHIFT 4 18537 18538 /* sys_device1 :: anaRxAControl2 :: imax_interp [03:03] */ 18539 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 18540 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 18541 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_INTERP_BITS 1 18542 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 18543 18544 /* sys_device1 :: anaRxAControl2 :: imode_interp [02:02] */ 18545 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 18546 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 18547 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_INTERP_BITS 1 18548 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 18549 18550 /* sys_device1 :: anaRxAControl2 :: imin_interp [01:01] */ 18551 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 18552 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 18553 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_INTERP_BITS 1 18554 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 18555 18556 /* sys_device1 :: anaRxAControl2 :: imax_cmd [00:00] */ 18557 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_CMD_MASK 0x0001 18558 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_CMD_ALIGN 0 18559 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_CMD_BITS 1 18560 #define PHY84328_SYS_DEV1_ANARXACONTROL2_IMAX_CMD_SHIFT 0 18561 18562 18563 /**************************************************************************** 18564 * sys_device1 :: anaRxAControl3 18565 */ 18566 /* sys_device1 :: anaRxAControl3 :: en_clk16 [15:15] */ 18567 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_CLK16_MASK 0x8000 18568 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_CLK16_ALIGN 0 18569 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_CLK16_BITS 1 18570 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_CLK16_SHIFT 15 18571 18572 /* sys_device1 :: anaRxAControl3 :: en_clk33 [14:14] */ 18573 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_CLK33_MASK 0x4000 18574 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_CLK33_ALIGN 0 18575 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_CLK33_BITS 1 18576 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_CLK33_SHIFT 14 18577 18578 /* sys_device1 :: anaRxAControl3 :: en_vcctrl [13:13] */ 18579 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 18580 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 18581 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_VCCTRL_BITS 1 18582 #define PHY84328_SYS_DEV1_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 18583 18584 /* sys_device1 :: anaRxAControl3 :: sel_th4dfe1 [12:12] */ 18585 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SEL_TH4DFE1_MASK 0x1000 18586 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SEL_TH4DFE1_ALIGN 0 18587 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SEL_TH4DFE1_BITS 1 18588 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SEL_TH4DFE1_SHIFT 12 18589 18590 /* sys_device1 :: anaRxAControl3 :: sel_th4dfe0 [11:11] */ 18591 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SEL_TH4DFE0_MASK 0x0800 18592 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SEL_TH4DFE0_ALIGN 0 18593 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SEL_TH4DFE0_BITS 1 18594 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SEL_TH4DFE0_SHIFT 11 18595 18596 /* sys_device1 :: anaRxAControl3 :: selugbw1 [10:10] */ 18597 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SELUGBW1_MASK 0x0400 18598 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SELUGBW1_ALIGN 0 18599 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SELUGBW1_BITS 1 18600 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SELUGBW1_SHIFT 10 18601 18602 /* sys_device1 :: anaRxAControl3 :: selugbw0 [09:09] */ 18603 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SELUGBW0_MASK 0x0200 18604 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SELUGBW0_ALIGN 0 18605 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SELUGBW0_BITS 1 18606 #define PHY84328_SYS_DEV1_ANARXACONTROL3_SELUGBW0_SHIFT 9 18607 18608 /* sys_device1 :: anaRxAControl3 :: imax_dfetap [08:08] */ 18609 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 18610 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 18611 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_DFETAP_BITS 1 18612 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 18613 18614 /* sys_device1 :: anaRxAControl3 :: imode_dfetap [07:07] */ 18615 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 18616 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 18617 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_DFETAP_BITS 1 18618 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 18619 18620 /* sys_device1 :: anaRxAControl3 :: imin_dfetap [06:06] */ 18621 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 18622 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 18623 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_DFETAP_BITS 1 18624 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 18625 18626 /* sys_device1 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 18627 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 18628 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 18629 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 18630 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 18631 18632 /* sys_device1 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 18633 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 18634 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 18635 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 18636 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 18637 18638 /* sys_device1 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 18639 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 18640 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 18641 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 18642 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 18643 18644 /* sys_device1 :: anaRxAControl3 :: imax_dfevref [02:02] */ 18645 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 18646 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 18647 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 18648 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 18649 18650 /* sys_device1 :: anaRxAControl3 :: imode_dfevref [01:01] */ 18651 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 18652 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 18653 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 18654 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 18655 18656 /* sys_device1 :: anaRxAControl3 :: imin_dfevref [00:00] */ 18657 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 18658 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 18659 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 18660 #define PHY84328_SYS_DEV1_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 18661 18662 18663 /**************************************************************************** 18664 * sys_device1_QSFI_TXPI_registers 18665 */ 18666 /**************************************************************************** 18667 * sys_device1 :: tx_pi_control1 18668 */ 18669 /* sys_device1 :: tx_pi_control1 :: tx_pi_integ_sat_sel [15:15] */ 18670 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_MASK 0x8000 18671 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_ALIGN 0 18672 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_BITS 1 18673 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_SEL_SHIFT 15 18674 18675 /* sys_device1 :: tx_pi_control1 :: tx_pi_integ_sat_1_or_2 [14:14] */ 18676 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_MASK 0x4000 18677 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_ALIGN 0 18678 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_BITS 1 18679 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_INTEG_SAT_1_OR_2_SHIFT 14 18680 18681 /* sys_device1 :: tx_pi_control1 :: tx_pi_phase_invert [13:13] */ 18682 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_MASK 0x2000 18683 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_ALIGN 0 18684 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_BITS 1 18685 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_INVERT_SHIFT 13 18686 18687 /* sys_device1 :: tx_pi_control1 :: tx_pi_phase_step_mult [12:12] */ 18688 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_MASK 0x1000 18689 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_ALIGN 0 18690 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_BITS 1 18691 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MULT_SHIFT 12 18692 18693 /* sys_device1 :: tx_pi_control1 :: tx_pi_phase_step_dir [11:11] */ 18694 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_MASK 0x0800 18695 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_ALIGN 0 18696 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_BITS 1 18697 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_DIR_SHIFT 11 18698 18699 /* sys_device1 :: tx_pi_control1 :: tx_pi_phase_step [10:09] */ 18700 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_MASK 0x0600 18701 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_ALIGN 0 18702 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_BITS 2 18703 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STEP_SHIFT 9 18704 18705 /* sys_device1 :: tx_pi_control1 :: tx_pi_phase_delta [08:04] */ 18706 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_MASK 0x01f0 18707 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_ALIGN 0 18708 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_BITS 5 18709 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_DELTA_SHIFT 4 18710 18711 /* sys_device1 :: tx_pi_control1 :: tx_pi_phase_strobe [03:03] */ 18712 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_MASK 0x0008 18713 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_ALIGN 0 18714 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_BITS 1 18715 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_STROBE_SHIFT 3 18716 18717 /* sys_device1 :: tx_pi_control1 :: tx_pi_phase_override [02:02] */ 18718 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_MASK 0x0004 18719 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_ALIGN 0 18720 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_BITS 1 18721 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_PHASE_OVERRIDE_SHIFT 2 18722 18723 /* sys_device1 :: tx_pi_control1 :: tx_pi_bypass_mode [01:01] */ 18724 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_MASK 0x0002 18725 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_ALIGN 0 18726 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_BITS 1 18727 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_BYPASS_MODE_SHIFT 1 18728 18729 /* sys_device1 :: tx_pi_control1 :: tx_pi_en [00:00] */ 18730 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_EN_MASK 0x0001 18731 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_EN_ALIGN 0 18732 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_EN_BITS 1 18733 #define PHY84328_SYS_DEV1_TX_PI_CONTROL1_TX_PI_EN_SHIFT 0 18734 18735 18736 /**************************************************************************** 18737 * sys_device1 :: tx_pi_control2 18738 */ 18739 /* sys_device1 :: tx_pi_control2 :: tx_pi_sm_timer_sel [15:14] */ 18740 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_MASK 0xc000 18741 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_ALIGN 0 18742 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_BITS 2 18743 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_TIMER_SEL_SHIFT 14 18744 18745 /* sys_device1 :: tx_pi_control2 :: tx_pi_sm_done_override [13:13] */ 18746 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_MASK 0x2000 18747 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_ALIGN 0 18748 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_BITS 1 18749 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_DONE_OVERRIDE_SHIFT 13 18750 18751 /* sys_device1 :: tx_pi_control2 :: tx_pi_sm_en_override [12:12] */ 18752 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_MASK 0x1000 18753 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_ALIGN 0 18754 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_BITS 1 18755 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_EN_OVERRIDE_SHIFT 12 18756 18757 /* sys_device1 :: tx_pi_control2 :: reserved0 [11:08] */ 18758 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_RESERVED0_MASK 0x0f00 18759 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_RESERVED0_ALIGN 0 18760 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_RESERVED0_BITS 4 18761 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_RESERVED0_SHIFT 8 18762 18763 /* sys_device1 :: tx_pi_control2 :: tx_pi_loopback_mode [07:07] */ 18764 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_MASK 0x0080 18765 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_ALIGN 0 18766 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_BITS 1 18767 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_LOOPBACK_MODE_SHIFT 7 18768 18769 /* sys_device1 :: tx_pi_control2 :: tx_pi_sm_bypass [06:06] */ 18770 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_BYPASS_MASK 0x0040 18771 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_BYPASS_ALIGN 0 18772 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_BYPASS_BITS 1 18773 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_SM_BYPASS_SHIFT 6 18774 18775 /* sys_device1 :: tx_pi_control2 :: tx_pi_integ_reg_clr [05:05] */ 18776 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_MASK 0x0020 18777 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_ALIGN 0 18778 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_BITS 1 18779 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_INTEG_REG_CLR_SHIFT 5 18780 18781 /* sys_device1 :: tx_pi_control2 :: tx_pi_bwsel_integ [04:02] */ 18782 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_MASK 0x001c 18783 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_ALIGN 0 18784 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_BITS 3 18785 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_BWSEL_INTEG_SHIFT 2 18786 18787 /* sys_device1 :: tx_pi_control2 :: tx_pi_rx_lane_sel [01:00] */ 18788 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_MASK 0x0003 18789 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_ALIGN 0 18790 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_BITS 2 18791 #define PHY84328_SYS_DEV1_TX_PI_CONTROL2_TX_PI_RX_LANE_SEL_SHIFT 0 18792 18793 18794 /**************************************************************************** 18795 * sys_device1 :: tx_pi_control3 18796 */ 18797 /* sys_device1 :: tx_pi_control3 :: tx_pi_freq_override_val [15:01] */ 18798 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_MASK 0xfffe 18799 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_ALIGN 0 18800 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_BITS 15 18801 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_VAL_SHIFT 1 18802 18803 /* sys_device1 :: tx_pi_control3 :: tx_pi_freq_override_en [00:00] */ 18804 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_MASK 0x0001 18805 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_ALIGN 0 18806 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_BITS 1 18807 #define PHY84328_SYS_DEV1_TX_PI_CONTROL3_TX_PI_FREQ_OVERRIDE_EN_SHIFT 0 18808 18809 18810 /**************************************************************************** 18811 * sys_device1 :: tx_pi_control4 18812 */ 18813 /* sys_device1 :: tx_pi_control4 :: tx_pi_sm_enable_override [15:15] */ 18814 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_MASK 0x8000 18815 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_ALIGN 0 18816 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_BITS 1 18817 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_SHIFT 15 18818 18819 /* sys_device1 :: tx_pi_control4 :: tx_pi_sm_enable_override_value [14:14] */ 18820 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_MASK 0x4000 18821 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_ALIGN 0 18822 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_BITS 1 18823 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_SM_ENABLE_OVERRIDE_VALUE_SHIFT 14 18824 18825 /* sys_device1 :: tx_pi_control4 :: tx_pi_cdr_lkdt_override [13:13] */ 18826 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_MASK 0x2000 18827 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_ALIGN 0 18828 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_BITS 1 18829 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_SHIFT 13 18830 18831 /* sys_device1 :: tx_pi_control4 :: tx_pi_cdr_lkdt_override_value [12:12] */ 18832 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_MASK 0x1000 18833 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_ALIGN 0 18834 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_BITS 1 18835 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_CDR_LKDT_OVERRIDE_VALUE_SHIFT 12 18836 18837 /* sys_device1 :: tx_pi_control4 :: tx_pi_halfSpd_override_ctl [11:11] */ 18838 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_MASK 0x0800 18839 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_ALIGN 0 18840 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_BITS 1 18841 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_OVERRIDE_CTL_SHIFT 11 18842 18843 /* sys_device1 :: tx_pi_control4 :: tx_pi_halfSpd_ctl [10:10] */ 18844 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_MASK 0x0400 18845 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_ALIGN 0 18846 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_BITS 1 18847 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_HALFSPD_CTL_SHIFT 10 18848 18849 /* sys_device1 :: tx_pi_control4 :: tx_pi_loopback_mode_override_ctl [09:09] */ 18850 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_MASK 0x0200 18851 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_ALIGN 0 18852 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_BITS 1 18853 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_OVERRIDE_CTL_SHIFT 9 18854 18855 /* sys_device1 :: tx_pi_control4 :: tx_pi_loopback_mode_ctl [08:08] */ 18856 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_MASK 0x0100 18857 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_ALIGN 0 18858 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_BITS 1 18859 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_LOOPBACK_MODE_CTL_SHIFT 8 18860 18861 /* sys_device1 :: tx_pi_control4 :: tx_pi_status3_mux_sel [07:06] */ 18862 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_MASK 0x00c0 18863 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_ALIGN 0 18864 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_BITS 2 18865 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_STATUS3_MUX_SEL_SHIFT 6 18866 18867 /* sys_device1 :: tx_pi_control4 :: tx_pi_status_latch [05:05] */ 18868 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_MASK 0x0020 18869 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_ALIGN 0 18870 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_BITS 1 18871 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_STATUS_LATCH_SHIFT 5 18872 18873 /* sys_device1 :: tx_pi_control4 :: tx_pi_prop_bypass [04:04] */ 18874 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_MASK 0x0010 18875 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_ALIGN 0 18876 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_BITS 1 18877 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_BYPASS_SHIFT 4 18878 18879 /* sys_device1 :: tx_pi_control4 :: tx_pi_prop_gain [03:01] */ 18880 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_GAIN_MASK 0x000e 18881 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_GAIN_ALIGN 0 18882 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_GAIN_BITS 3 18883 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_GAIN_SHIFT 1 18884 18885 /* sys_device1 :: tx_pi_control4 :: tx_pi_prop_acq [00:00] */ 18886 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_ACQ_MASK 0x0001 18887 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_ACQ_ALIGN 0 18888 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_ACQ_BITS 1 18889 #define PHY84328_SYS_DEV1_TX_PI_CONTROL4_TX_PI_PROP_ACQ_SHIFT 0 18890 18891 18892 /**************************************************************************** 18893 * sys_device1 :: tx_pi_control5 18894 */ 18895 /* sys_device1 :: tx_pi_control5 :: reserved0 [15:01] */ 18896 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5_RESERVED0_MASK 0xfffe 18897 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5_RESERVED0_ALIGN 0 18898 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5_RESERVED0_BITS 15 18899 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5_RESERVED0_SHIFT 1 18900 18901 /* sys_device1 :: tx_pi_control5 :: tx_pi_sm_rst [00:00] */ 18902 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5_TX_PI_SM_RST_MASK 0x0001 18903 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5_TX_PI_SM_RST_ALIGN 0 18904 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5_TX_PI_SM_RST_BITS 1 18905 #define PHY84328_SYS_DEV1_TX_PI_CONTROL5_TX_PI_SM_RST_SHIFT 0 18906 18907 18908 /**************************************************************************** 18909 * sys_device1 :: tx_pi_status1 18910 */ 18911 /* sys_device1 :: tx_pi_status1 :: reserved0 [15:15] */ 18912 #define PHY84328_SYS_DEV1_TX_PI_STATUS1_RESERVED0_MASK 0x8000 18913 #define PHY84328_SYS_DEV1_TX_PI_STATUS1_RESERVED0_ALIGN 0 18914 #define PHY84328_SYS_DEV1_TX_PI_STATUS1_RESERVED0_BITS 1 18915 #define PHY84328_SYS_DEV1_TX_PI_STATUS1_RESERVED0_SHIFT 15 18916 18917 /* sys_device1 :: tx_pi_status1 :: tx_pi_integ_reg [14:00] */ 18918 #define PHY84328_SYS_DEV1_TX_PI_STATUS1_TX_PI_INTEG_REG_MASK 0x7fff 18919 #define PHY84328_SYS_DEV1_TX_PI_STATUS1_TX_PI_INTEG_REG_ALIGN 0 18920 #define PHY84328_SYS_DEV1_TX_PI_STATUS1_TX_PI_INTEG_REG_BITS 15 18921 #define PHY84328_SYS_DEV1_TX_PI_STATUS1_TX_PI_INTEG_REG_SHIFT 0 18922 18923 18924 /**************************************************************************** 18925 * sys_device1 :: tx_pi_status2 18926 */ 18927 /* sys_device1 :: tx_pi_status2 :: reserved0 [15:07] */ 18928 #define PHY84328_SYS_DEV1_TX_PI_STATUS2_RESERVED0_MASK 0xff80 18929 #define PHY84328_SYS_DEV1_TX_PI_STATUS2_RESERVED0_ALIGN 0 18930 #define PHY84328_SYS_DEV1_TX_PI_STATUS2_RESERVED0_BITS 9 18931 #define PHY84328_SYS_DEV1_TX_PI_STATUS2_RESERVED0_SHIFT 7 18932 18933 /* sys_device1 :: tx_pi_status2 :: tx_pi_phase_cntr [06:00] */ 18934 #define PHY84328_SYS_DEV1_TX_PI_STATUS2_TX_PI_PHASE_CNTR_MASK 0x007f 18935 #define PHY84328_SYS_DEV1_TX_PI_STATUS2_TX_PI_PHASE_CNTR_ALIGN 0 18936 #define PHY84328_SYS_DEV1_TX_PI_STATUS2_TX_PI_PHASE_CNTR_BITS 7 18937 #define PHY84328_SYS_DEV1_TX_PI_STATUS2_TX_PI_PHASE_CNTR_SHIFT 0 18938 18939 18940 /**************************************************************************** 18941 * sys_device1 :: tx_pi_status3 18942 */ 18943 /* sys_device1 :: tx_pi_status3 :: tx_pi_phase_ctrl [15:00] */ 18944 #define PHY84328_SYS_DEV1_TX_PI_STATUS3_TX_PI_PHASE_CTRL_MASK 0xffff 18945 #define PHY84328_SYS_DEV1_TX_PI_STATUS3_TX_PI_PHASE_CTRL_ALIGN 0 18946 #define PHY84328_SYS_DEV1_TX_PI_STATUS3_TX_PI_PHASE_CTRL_BITS 16 18947 #define PHY84328_SYS_DEV1_TX_PI_STATUS3_TX_PI_PHASE_CTRL_SHIFT 0 18948 18949 18950 /**************************************************************************** 18951 * sys_device1 :: tx_pi_status4 18952 */ 18953 /* sys_device1 :: tx_pi_status4 :: reserved0 [15:02] */ 18954 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_RESERVED0_MASK 0xfffc 18955 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_RESERVED0_ALIGN 0 18956 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_RESERVED0_BITS 14 18957 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_RESERVED0_SHIFT 2 18958 18959 /* sys_device1 :: tx_pi_status4 :: tx_pi_sm_en [01:01] */ 18960 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_TX_PI_SM_EN_MASK 0x0002 18961 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_TX_PI_SM_EN_ALIGN 0 18962 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_TX_PI_SM_EN_BITS 1 18963 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_TX_PI_SM_EN_SHIFT 1 18964 18965 /* sys_device1 :: tx_pi_status4 :: tx_pi_sm_done [00:00] */ 18966 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_TX_PI_SM_DONE_MASK 0x0001 18967 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_TX_PI_SM_DONE_ALIGN 0 18968 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_TX_PI_SM_DONE_BITS 1 18969 #define PHY84328_SYS_DEV1_TX_PI_STATUS4_TX_PI_SM_DONE_SHIFT 0 18970 18971 18972 /**************************************************************************** 18973 * sys_device1 :: llpe_fifo_ctl 18974 */ 18975 /* sys_device1 :: llpe_fifo_ctl :: rel_level [15:11] */ 18976 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_REL_LEVEL_MASK 0xf800 18977 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_REL_LEVEL_ALIGN 0 18978 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_REL_LEVEL_BITS 5 18979 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_REL_LEVEL_SHIFT 11 18980 18981 /* sys_device1 :: llpe_fifo_ctl :: rel_4cycles [10:10] */ 18982 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_REL_4CYCLES_MASK 0x0400 18983 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_REL_4CYCLES_ALIGN 0 18984 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_REL_4CYCLES_BITS 1 18985 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_REL_4CYCLES_SHIFT 10 18986 18987 /* sys_device1 :: llpe_fifo_ctl :: lowlat_fifo_rstb_rel_sel [09:09] */ 18988 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LOWLAT_FIFO_RSTB_REL_SEL_MASK 0x0200 18989 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LOWLAT_FIFO_RSTB_REL_SEL_ALIGN 0 18990 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LOWLAT_FIFO_RSTB_REL_SEL_BITS 1 18991 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LOWLAT_FIFO_RSTB_REL_SEL_SHIFT 9 18992 18993 /* sys_device1 :: llpe_fifo_ctl :: phase_error_sel [08:08] */ 18994 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_PHASE_ERROR_SEL_MASK 0x0100 18995 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_PHASE_ERROR_SEL_ALIGN 0 18996 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_PHASE_ERROR_SEL_BITS 1 18997 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_PHASE_ERROR_SEL_SHIFT 8 18998 18999 /* sys_device1 :: llpe_fifo_ctl :: cap_prop_pe [07:07] */ 19000 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_CAP_PROP_PE_MASK 0x0080 19001 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_CAP_PROP_PE_ALIGN 0 19002 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_CAP_PROP_PE_BITS 1 19003 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_CAP_PROP_PE_SHIFT 7 19004 19005 /* sys_device1 :: llpe_fifo_ctl :: llm_fifo_status_clear [06:06] */ 19006 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LLM_FIFO_STATUS_CLEAR_MASK 0x0040 19007 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LLM_FIFO_STATUS_CLEAR_ALIGN 0 19008 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LLM_FIFO_STATUS_CLEAR_BITS 1 19009 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LLM_FIFO_STATUS_CLEAR_SHIFT 6 19010 19011 /* sys_device1 :: llpe_fifo_ctl :: hold_fifo_ptr_enable [05:05] */ 19012 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_HOLD_FIFO_PTR_ENABLE_MASK 0x0020 19013 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_HOLD_FIFO_PTR_ENABLE_ALIGN 0 19014 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_HOLD_FIFO_PTR_ENABLE_BITS 1 19015 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_HOLD_FIFO_PTR_ENABLE_SHIFT 5 19016 19017 /* sys_device1 :: llpe_fifo_ctl :: fifo_auto_reset_enable [04:04] */ 19018 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_FIFO_AUTO_RESET_ENABLE_MASK 0x0010 19019 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_FIFO_AUTO_RESET_ENABLE_ALIGN 0 19020 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_FIFO_AUTO_RESET_ENABLE_BITS 1 19021 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_FIFO_AUTO_RESET_ENABLE_SHIFT 4 19022 19023 /* sys_device1 :: llpe_fifo_ctl :: llpe_fifo_enable [03:03] */ 19024 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LLPE_FIFO_ENABLE_MASK 0x0008 19025 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LLPE_FIFO_ENABLE_ALIGN 0 19026 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LLPE_FIFO_ENABLE_BITS 1 19027 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_LLPE_FIFO_ENABLE_SHIFT 3 19028 19029 /* sys_device1 :: llpe_fifo_ctl :: fifo_initial_distance [02:00] */ 19030 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_FIFO_INITIAL_DISTANCE_MASK 0x0007 19031 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_FIFO_INITIAL_DISTANCE_ALIGN 0 19032 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_FIFO_INITIAL_DISTANCE_BITS 3 19033 #define PHY84328_SYS_DEV1_LLPE_FIFO_CTL_FIFO_INITIAL_DISTANCE_SHIFT 0 19034 19035 19036 /**************************************************************************** 19037 * sys_device1 :: llpe_fifo_sts 19038 */ 19039 /* sys_device1 :: llpe_fifo_sts :: fifo_rstb [15:15] */ 19040 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_FIFO_RSTB_MASK 0x8000 19041 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_FIFO_RSTB_ALIGN 0 19042 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_FIFO_RSTB_BITS 1 19043 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_FIFO_RSTB_SHIFT 15 19044 19045 /* sys_device1 :: llpe_fifo_sts :: prop_sum [14:10] */ 19046 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_PROP_SUM_MASK 0x7c00 19047 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_PROP_SUM_ALIGN 0 19048 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_PROP_SUM_BITS 5 19049 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_PROP_SUM_SHIFT 10 19050 19051 /* sys_device1 :: llpe_fifo_sts :: pe_cap_value [09:05] */ 19052 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_PE_CAP_VALUE_MASK 0x03e0 19053 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_PE_CAP_VALUE_ALIGN 0 19054 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_PE_CAP_VALUE_BITS 5 19055 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_PE_CAP_VALUE_SHIFT 5 19056 19057 /* sys_device1 :: llpe_fifo_sts :: llpe_fifo_full [04:04] */ 19058 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_MASK 0x0010 19059 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_ALIGN 0 19060 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_BITS 1 19061 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_SHIFT 4 19062 19063 /* sys_device1 :: llpe_fifo_sts :: llpe_fifo_full_sticky [03:03] */ 19064 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_STICKY_MASK 0x0008 19065 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_STICKY_ALIGN 0 19066 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_STICKY_BITS 1 19067 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_FULL_STICKY_SHIFT 3 19068 19069 /* sys_device1 :: llpe_fifo_sts :: llpe_fifo_empty [02:02] */ 19070 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_MASK 0x0004 19071 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_ALIGN 0 19072 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_BITS 1 19073 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_SHIFT 2 19074 19075 /* sys_device1 :: llpe_fifo_sts :: llpe_fifo_empty_sticky [01:01] */ 19076 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_STICKY_MASK 0x0002 19077 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_STICKY_ALIGN 0 19078 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_STICKY_BITS 1 19079 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LLPE_FIFO_EMPTY_STICKY_SHIFT 1 19080 19081 /* sys_device1 :: llpe_fifo_sts :: ll_analog_fifo_ovfb [00:00] */ 19082 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LL_ANALOG_FIFO_OVFB_MASK 0x0001 19083 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LL_ANALOG_FIFO_OVFB_ALIGN 0 19084 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LL_ANALOG_FIFO_OVFB_BITS 1 19085 #define PHY84328_SYS_DEV1_LLPE_FIFO_STS_LL_ANALOG_FIFO_OVFB_SHIFT 0 19086 19087 19088 /**************************************************************************** 19089 * sys_device1 :: pmd_regs_sel 19090 */ 19091 /* sys_device1 :: pmd_regs_sel :: reserved0 [15:01] */ 19092 #define PHY84328_SYS_DEV1_PMD_REGS_SEL_RESERVED0_MASK 0xfffe 19093 #define PHY84328_SYS_DEV1_PMD_REGS_SEL_RESERVED0_ALIGN 0 19094 #define PHY84328_SYS_DEV1_PMD_REGS_SEL_RESERVED0_BITS 15 19095 #define PHY84328_SYS_DEV1_PMD_REGS_SEL_RESERVED0_SHIFT 1 19096 19097 /* sys_device1 :: pmd_regs_sel :: select_sys_registers [00:00] */ 19098 #define PHY84328_SYS_DEV1_PMD_REGS_SEL_SELECT_SYS_REGISTERS_MASK 0x0001 19099 #define PHY84328_SYS_DEV1_PMD_REGS_SEL_SELECT_SYS_REGISTERS_ALIGN 0 19100 #define PHY84328_SYS_DEV1_PMD_REGS_SEL_SELECT_SYS_REGISTERS_BITS 1 19101 #define PHY84328_SYS_DEV1_PMD_REGS_SEL_SELECT_SYS_REGISTERS_SHIFT 0 19102 19103 19104 /**************************************************************************** 19105 * sys_device1_QSFI_gpregs 19106 */ 19107 /**************************************************************************** 19108 * sys_device1 :: GP2_0 19109 */ 19110 /* sys_device1 :: GP2_0 :: pll_mode [15:12] */ 19111 #define PHY84328_SYS_DEV1_GP2_0_PLL_MODE_MASK 0xf000 19112 #define PHY84328_SYS_DEV1_GP2_0_PLL_MODE_ALIGN 0 19113 #define PHY84328_SYS_DEV1_GP2_0_PLL_MODE_BITS 4 19114 #define PHY84328_SYS_DEV1_GP2_0_PLL_MODE_SHIFT 12 19115 19116 /* sys_device1 :: GP2_0 :: sigdet [11:08] */ 19117 #define PHY84328_SYS_DEV1_GP2_0_SIGDET_MASK 0x0f00 19118 #define PHY84328_SYS_DEV1_GP2_0_SIGDET_ALIGN 0 19119 #define PHY84328_SYS_DEV1_GP2_0_SIGDET_BITS 4 19120 #define PHY84328_SYS_DEV1_GP2_0_SIGDET_SHIFT 8 19121 19122 /* sys_device1 :: GP2_0 :: pll_lock_1g [07:04] */ 19123 #define PHY84328_SYS_DEV1_GP2_0_PLL_LOCK_1G_MASK 0x00f0 19124 #define PHY84328_SYS_DEV1_GP2_0_PLL_LOCK_1G_ALIGN 0 19125 #define PHY84328_SYS_DEV1_GP2_0_PLL_LOCK_1G_BITS 4 19126 #define PHY84328_SYS_DEV1_GP2_0_PLL_LOCK_1G_SHIFT 4 19127 19128 /* sys_device1 :: GP2_0 :: sync_status_combo [03:00] */ 19129 #define PHY84328_SYS_DEV1_GP2_0_SYNC_STATUS_COMBO_MASK 0x000f 19130 #define PHY84328_SYS_DEV1_GP2_0_SYNC_STATUS_COMBO_ALIGN 0 19131 #define PHY84328_SYS_DEV1_GP2_0_SYNC_STATUS_COMBO_BITS 4 19132 #define PHY84328_SYS_DEV1_GP2_0_SYNC_STATUS_COMBO_SHIFT 0 19133 19134 19135 /**************************************************************************** 19136 * sys_device1 :: GP2_1 19137 */ 19138 /* sys_device1 :: GP2_1 :: link_KR [15:12] */ 19139 #define PHY84328_SYS_DEV1_GP2_1_LINK_KR_MASK 0xf000 19140 #define PHY84328_SYS_DEV1_GP2_1_LINK_KR_ALIGN 0 19141 #define PHY84328_SYS_DEV1_GP2_1_LINK_KR_BITS 4 19142 #define PHY84328_SYS_DEV1_GP2_1_LINK_KR_SHIFT 12 19143 19144 /* sys_device1 :: GP2_1 :: link_status [11:08] */ 19145 #define PHY84328_SYS_DEV1_GP2_1_LINK_STATUS_MASK 0x0f00 19146 #define PHY84328_SYS_DEV1_GP2_1_LINK_STATUS_ALIGN 0 19147 #define PHY84328_SYS_DEV1_GP2_1_LINK_STATUS_BITS 4 19148 #define PHY84328_SYS_DEV1_GP2_1_LINK_STATUS_SHIFT 8 19149 19150 /* sys_device1 :: GP2_1 :: link_100fx [07:04] */ 19151 #define PHY84328_SYS_DEV1_GP2_1_LINK_100FX_MASK 0x00f0 19152 #define PHY84328_SYS_DEV1_GP2_1_LINK_100FX_ALIGN 0 19153 #define PHY84328_SYS_DEV1_GP2_1_LINK_100FX_BITS 4 19154 #define PHY84328_SYS_DEV1_GP2_1_LINK_100FX_SHIFT 4 19155 19156 /* sys_device1 :: GP2_1 :: link_an [03:00] */ 19157 #define PHY84328_SYS_DEV1_GP2_1_LINK_AN_MASK 0x000f 19158 #define PHY84328_SYS_DEV1_GP2_1_LINK_AN_ALIGN 0 19159 #define PHY84328_SYS_DEV1_GP2_1_LINK_AN_BITS 4 19160 #define PHY84328_SYS_DEV1_GP2_1_LINK_AN_SHIFT 0 19161 19162 19163 /**************************************************************************** 19164 * sys_device1 :: GP2_2 19165 */ 19166 /* sys_device1 :: GP2_2 :: reserved0 [15:14] */ 19167 #define PHY84328_SYS_DEV1_GP2_2_RESERVED0_MASK 0xc000 19168 #define PHY84328_SYS_DEV1_GP2_2_RESERVED0_ALIGN 0 19169 #define PHY84328_SYS_DEV1_GP2_2_RESERVED0_BITS 2 19170 #define PHY84328_SYS_DEV1_GP2_2_RESERVED0_SHIFT 14 19171 19172 /* sys_device1 :: GP2_2 :: actual_speed_ln1 [13:08] */ 19173 #define PHY84328_SYS_DEV1_GP2_2_ACTUAL_SPEED_LN1_MASK 0x3f00 19174 #define PHY84328_SYS_DEV1_GP2_2_ACTUAL_SPEED_LN1_ALIGN 0 19175 #define PHY84328_SYS_DEV1_GP2_2_ACTUAL_SPEED_LN1_BITS 6 19176 #define PHY84328_SYS_DEV1_GP2_2_ACTUAL_SPEED_LN1_SHIFT 8 19177 19178 /* sys_device1 :: GP2_2 :: reserved1 [07:06] */ 19179 #define PHY84328_SYS_DEV1_GP2_2_RESERVED1_MASK 0x00c0 19180 #define PHY84328_SYS_DEV1_GP2_2_RESERVED1_ALIGN 0 19181 #define PHY84328_SYS_DEV1_GP2_2_RESERVED1_BITS 2 19182 #define PHY84328_SYS_DEV1_GP2_2_RESERVED1_SHIFT 6 19183 19184 /* sys_device1 :: GP2_2 :: actual_speed_ln0 [05:00] */ 19185 #define PHY84328_SYS_DEV1_GP2_2_ACTUAL_SPEED_LN0_MASK 0x003f 19186 #define PHY84328_SYS_DEV1_GP2_2_ACTUAL_SPEED_LN0_ALIGN 0 19187 #define PHY84328_SYS_DEV1_GP2_2_ACTUAL_SPEED_LN0_BITS 6 19188 #define PHY84328_SYS_DEV1_GP2_2_ACTUAL_SPEED_LN0_SHIFT 0 19189 19190 19191 /**************************************************************************** 19192 * sys_device1 :: GP2_3 19193 */ 19194 /* sys_device1 :: GP2_3 :: reserved0 [15:14] */ 19195 #define PHY84328_SYS_DEV1_GP2_3_RESERVED0_MASK 0xc000 19196 #define PHY84328_SYS_DEV1_GP2_3_RESERVED0_ALIGN 0 19197 #define PHY84328_SYS_DEV1_GP2_3_RESERVED0_BITS 2 19198 #define PHY84328_SYS_DEV1_GP2_3_RESERVED0_SHIFT 14 19199 19200 /* sys_device1 :: GP2_3 :: actual_speed_ln3 [13:08] */ 19201 #define PHY84328_SYS_DEV1_GP2_3_ACTUAL_SPEED_LN3_MASK 0x3f00 19202 #define PHY84328_SYS_DEV1_GP2_3_ACTUAL_SPEED_LN3_ALIGN 0 19203 #define PHY84328_SYS_DEV1_GP2_3_ACTUAL_SPEED_LN3_BITS 6 19204 #define PHY84328_SYS_DEV1_GP2_3_ACTUAL_SPEED_LN3_SHIFT 8 19205 19206 /* sys_device1 :: GP2_3 :: reserved1 [07:06] */ 19207 #define PHY84328_SYS_DEV1_GP2_3_RESERVED1_MASK 0x00c0 19208 #define PHY84328_SYS_DEV1_GP2_3_RESERVED1_ALIGN 0 19209 #define PHY84328_SYS_DEV1_GP2_3_RESERVED1_BITS 2 19210 #define PHY84328_SYS_DEV1_GP2_3_RESERVED1_SHIFT 6 19211 19212 /* sys_device1 :: GP2_3 :: actual_speed_ln2 [05:00] */ 19213 #define PHY84328_SYS_DEV1_GP2_3_ACTUAL_SPEED_LN2_MASK 0x003f 19214 #define PHY84328_SYS_DEV1_GP2_3_ACTUAL_SPEED_LN2_ALIGN 0 19215 #define PHY84328_SYS_DEV1_GP2_3_ACTUAL_SPEED_LN2_BITS 6 19216 #define PHY84328_SYS_DEV1_GP2_3_ACTUAL_SPEED_LN2_SHIFT 0 19217 19218 19219 /**************************************************************************** 19220 * sys_device1 :: GP2_4 19221 */ 19222 /* sys_device1 :: GP2_4 :: cl73_autoneg_complete [15:12] */ 19223 #define PHY84328_SYS_DEV1_GP2_4_CL73_AUTONEG_COMPLETE_MASK 0xf000 19224 #define PHY84328_SYS_DEV1_GP2_4_CL73_AUTONEG_COMPLETE_ALIGN 0 19225 #define PHY84328_SYS_DEV1_GP2_4_CL73_AUTONEG_COMPLETE_BITS 4 19226 #define PHY84328_SYS_DEV1_GP2_4_CL73_AUTONEG_COMPLETE_SHIFT 12 19227 19228 /* sys_device1 :: GP2_4 :: autoneg_complete [11:08] */ 19229 #define PHY84328_SYS_DEV1_GP2_4_AUTONEG_COMPLETE_MASK 0x0f00 19230 #define PHY84328_SYS_DEV1_GP2_4_AUTONEG_COMPLETE_ALIGN 0 19231 #define PHY84328_SYS_DEV1_GP2_4_AUTONEG_COMPLETE_BITS 4 19232 #define PHY84328_SYS_DEV1_GP2_4_AUTONEG_COMPLETE_SHIFT 8 19233 19234 /* sys_device1 :: GP2_4 :: cl73_mr_lp_autoneg_able [07:04] */ 19235 #define PHY84328_SYS_DEV1_GP2_4_CL73_MR_LP_AUTONEG_ABLE_MASK 0x00f0 19236 #define PHY84328_SYS_DEV1_GP2_4_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 19237 #define PHY84328_SYS_DEV1_GP2_4_CL73_MR_LP_AUTONEG_ABLE_BITS 4 19238 #define PHY84328_SYS_DEV1_GP2_4_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 19239 19240 /* sys_device1 :: GP2_4 :: cl73_mr_autoneg_able [03:00] */ 19241 #define PHY84328_SYS_DEV1_GP2_4_CL73_MR_AUTONEG_ABLE_MASK 0x000f 19242 #define PHY84328_SYS_DEV1_GP2_4_CL73_MR_AUTONEG_ABLE_ALIGN 0 19243 #define PHY84328_SYS_DEV1_GP2_4_CL73_MR_AUTONEG_ABLE_BITS 4 19244 #define PHY84328_SYS_DEV1_GP2_4_CL73_MR_AUTONEG_ABLE_SHIFT 0 19245 19246 19247 /**************************************************************************** 19248 * sys_device1 :: GP2_5 19249 */ 19250 /* sys_device1 :: GP2_5 :: Cl73_BAMStat1_ln0 [15:00] */ 19251 #define PHY84328_SYS_DEV1_GP2_5_CL73_BAMSTAT1_LN0_MASK 0xffff 19252 #define PHY84328_SYS_DEV1_GP2_5_CL73_BAMSTAT1_LN0_ALIGN 0 19253 #define PHY84328_SYS_DEV1_GP2_5_CL73_BAMSTAT1_LN0_BITS 16 19254 #define PHY84328_SYS_DEV1_GP2_5_CL73_BAMSTAT1_LN0_SHIFT 0 19255 19256 19257 /**************************************************************************** 19258 * sys_device1 :: GP2_6 19259 */ 19260 /* sys_device1 :: GP2_6 :: Cl73_BAMStat2_ln0 [15:00] */ 19261 #define PHY84328_SYS_DEV1_GP2_6_CL73_BAMSTAT2_LN0_MASK 0xffff 19262 #define PHY84328_SYS_DEV1_GP2_6_CL73_BAMSTAT2_LN0_ALIGN 0 19263 #define PHY84328_SYS_DEV1_GP2_6_CL73_BAMSTAT2_LN0_BITS 16 19264 #define PHY84328_SYS_DEV1_GP2_6_CL73_BAMSTAT2_LN0_SHIFT 0 19265 19266 19267 /**************************************************************************** 19268 * sys_device1 :: GP2_7 19269 */ 19270 /* sys_device1 :: GP2_7 :: Cl73_BAMStat3_ln0 [15:00] */ 19271 #define PHY84328_SYS_DEV1_GP2_7_CL73_BAMSTAT3_LN0_MASK 0xffff 19272 #define PHY84328_SYS_DEV1_GP2_7_CL73_BAMSTAT3_LN0_ALIGN 0 19273 #define PHY84328_SYS_DEV1_GP2_7_CL73_BAMSTAT3_LN0_BITS 16 19274 #define PHY84328_SYS_DEV1_GP2_7_CL73_BAMSTAT3_LN0_SHIFT 0 19275 19276 19277 /**************************************************************************** 19278 * sys_device1 :: GP2_9 19279 */ 19280 /* sys_device1 :: GP2_9 :: prbs_lock_ln0 [15:15] */ 19281 #define PHY84328_SYS_DEV1_GP2_9_PRBS_LOCK_LN0_MASK 0x8000 19282 #define PHY84328_SYS_DEV1_GP2_9_PRBS_LOCK_LN0_ALIGN 0 19283 #define PHY84328_SYS_DEV1_GP2_9_PRBS_LOCK_LN0_BITS 1 19284 #define PHY84328_SYS_DEV1_GP2_9_PRBS_LOCK_LN0_SHIFT 15 19285 19286 /* sys_device1 :: GP2_9 :: tx0_fir_tap_main [14:09] */ 19287 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_MAIN_MASK 0x7e00 19288 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_MAIN_ALIGN 0 19289 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_MAIN_BITS 6 19290 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_MAIN_SHIFT 9 19291 19292 /* sys_device1 :: GP2_9 :: tx0_fir_tap_pre [08:05] */ 19293 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_PRE_MASK 0x01e0 19294 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_PRE_ALIGN 0 19295 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_PRE_BITS 4 19296 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_PRE_SHIFT 5 19297 19298 /* sys_device1 :: GP2_9 :: tx0_fir_tap_post [04:00] */ 19299 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_POST_MASK 0x001f 19300 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_POST_ALIGN 0 19301 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_POST_BITS 5 19302 #define PHY84328_SYS_DEV1_GP2_9_TX0_FIR_TAP_POST_SHIFT 0 19303 19304 19305 /**************************************************************************** 19306 * sys_device1 :: GP2_A 19307 */ 19308 /* sys_device1 :: GP2_A :: prbs_lock_ln1 [15:15] */ 19309 #define PHY84328_SYS_DEV1_GP2_A_PRBS_LOCK_LN1_MASK 0x8000 19310 #define PHY84328_SYS_DEV1_GP2_A_PRBS_LOCK_LN1_ALIGN 0 19311 #define PHY84328_SYS_DEV1_GP2_A_PRBS_LOCK_LN1_BITS 1 19312 #define PHY84328_SYS_DEV1_GP2_A_PRBS_LOCK_LN1_SHIFT 15 19313 19314 /* sys_device1 :: GP2_A :: tx1_fir_tap_main [14:09] */ 19315 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_MAIN_MASK 0x7e00 19316 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_MAIN_ALIGN 0 19317 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_MAIN_BITS 6 19318 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_MAIN_SHIFT 9 19319 19320 /* sys_device1 :: GP2_A :: tx1_fir_tap_pre [08:05] */ 19321 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_PRE_MASK 0x01e0 19322 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_PRE_ALIGN 0 19323 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_PRE_BITS 4 19324 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_PRE_SHIFT 5 19325 19326 /* sys_device1 :: GP2_A :: tx1_fir_tap_post [04:00] */ 19327 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_POST_MASK 0x001f 19328 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_POST_ALIGN 0 19329 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_POST_BITS 5 19330 #define PHY84328_SYS_DEV1_GP2_A_TX1_FIR_TAP_POST_SHIFT 0 19331 19332 19333 /**************************************************************************** 19334 * sys_device1 :: GP2_B 19335 */ 19336 /* sys_device1 :: GP2_B :: prbs_lock_ln2 [15:15] */ 19337 #define PHY84328_SYS_DEV1_GP2_B_PRBS_LOCK_LN2_MASK 0x8000 19338 #define PHY84328_SYS_DEV1_GP2_B_PRBS_LOCK_LN2_ALIGN 0 19339 #define PHY84328_SYS_DEV1_GP2_B_PRBS_LOCK_LN2_BITS 1 19340 #define PHY84328_SYS_DEV1_GP2_B_PRBS_LOCK_LN2_SHIFT 15 19341 19342 /* sys_device1 :: GP2_B :: tx2_fir_tap_main [14:09] */ 19343 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_MAIN_MASK 0x7e00 19344 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_MAIN_ALIGN 0 19345 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_MAIN_BITS 6 19346 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_MAIN_SHIFT 9 19347 19348 /* sys_device1 :: GP2_B :: tx2_fir_tap_pre [08:05] */ 19349 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_PRE_MASK 0x01e0 19350 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_PRE_ALIGN 0 19351 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_PRE_BITS 4 19352 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_PRE_SHIFT 5 19353 19354 /* sys_device1 :: GP2_B :: tx2_fir_tap_post [04:00] */ 19355 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_POST_MASK 0x001f 19356 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_POST_ALIGN 0 19357 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_POST_BITS 5 19358 #define PHY84328_SYS_DEV1_GP2_B_TX2_FIR_TAP_POST_SHIFT 0 19359 19360 19361 /**************************************************************************** 19362 * sys_device1 :: GP2_C 19363 */ 19364 /* sys_device1 :: GP2_C :: prbs_lock_ln3 [15:15] */ 19365 #define PHY84328_SYS_DEV1_GP2_C_PRBS_LOCK_LN3_MASK 0x8000 19366 #define PHY84328_SYS_DEV1_GP2_C_PRBS_LOCK_LN3_ALIGN 0 19367 #define PHY84328_SYS_DEV1_GP2_C_PRBS_LOCK_LN3_BITS 1 19368 #define PHY84328_SYS_DEV1_GP2_C_PRBS_LOCK_LN3_SHIFT 15 19369 19370 /* sys_device1 :: GP2_C :: tx3_fir_tap_main [14:09] */ 19371 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_MAIN_MASK 0x7e00 19372 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_MAIN_ALIGN 0 19373 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_MAIN_BITS 6 19374 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_MAIN_SHIFT 9 19375 19376 /* sys_device1 :: GP2_C :: tx3_fir_tap_pre [08:05] */ 19377 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_PRE_MASK 0x01e0 19378 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_PRE_ALIGN 0 19379 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_PRE_BITS 4 19380 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_PRE_SHIFT 5 19381 19382 /* sys_device1 :: GP2_C :: tx3_fir_tap_post [04:00] */ 19383 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_POST_MASK 0x001f 19384 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_POST_ALIGN 0 19385 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_POST_BITS 5 19386 #define PHY84328_SYS_DEV1_GP2_C_TX3_FIR_TAP_POST_SHIFT 0 19387 19388 19389 /**************************************************************************** 19390 * sys_device1_cl72_user_regs 19391 */ 19392 /**************************************************************************** 19393 * sys_device1 :: cl72_xmt_control_register 19394 */ 19395 /* sys_device1 :: cl72_xmt_control_register :: xmt_control_page [15:00] */ 19396 #define PHY84328_SYS_DEV1_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_MASK 0xffff 19397 #define PHY84328_SYS_DEV1_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_ALIGN 0 19398 #define PHY84328_SYS_DEV1_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_BITS 16 19399 #define PHY84328_SYS_DEV1_CL72_XMT_CONTROL_REGISTER_XMT_CONTROL_PAGE_SHIFT 0 19400 19401 19402 /**************************************************************************** 19403 * sys_device1 :: cl72_rcvd_status_register 19404 */ 19405 /* sys_device1 :: cl72_rcvd_status_register :: rcvd_status_page [15:00] */ 19406 #define PHY84328_SYS_DEV1_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_MASK 0xffff 19407 #define PHY84328_SYS_DEV1_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_ALIGN 0 19408 #define PHY84328_SYS_DEV1_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_BITS 16 19409 #define PHY84328_SYS_DEV1_CL72_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_SHIFT 0 19410 19411 19412 /**************************************************************************** 19413 * sys_device1 :: cl72_tx_fir_tap_register 19414 */ 19415 /* sys_device1 :: cl72_tx_fir_tap_register :: tx_fir_tap_force [15:15] */ 19416 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_MASK 0x8000 19417 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_ALIGN 0 19418 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_BITS 1 19419 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_FORCE_SHIFT 15 19420 19421 /* sys_device1 :: cl72_tx_fir_tap_register :: tx_fir_tap_post [14:10] */ 19422 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_MASK 0x7c00 19423 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_ALIGN 0 19424 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_BITS 5 19425 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_POST_SHIFT 10 19426 19427 /* sys_device1 :: cl72_tx_fir_tap_register :: tx_fir_tap_main [09:04] */ 19428 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_MASK 0x03f0 19429 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_ALIGN 0 19430 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_BITS 6 19431 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_MAIN_SHIFT 4 19432 19433 /* sys_device1 :: cl72_tx_fir_tap_register :: tx_fir_tap_pre [03:00] */ 19434 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_MASK 0x000f 19435 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_ALIGN 0 19436 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_BITS 4 19437 #define PHY84328_SYS_DEV1_CL72_TX_FIR_TAP_REGISTER_TX_FIR_TAP_PRE_SHIFT 0 19438 19439 19440 /**************************************************************************** 19441 * sys_device1 :: cl72_misc1_control 19442 */ 19443 /* sys_device1 :: cl72_misc1_control :: link_control_force [15:15] */ 19444 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_MASK 0x8000 19445 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_ALIGN 0 19446 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_BITS 1 19447 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCE_SHIFT 15 19448 19449 /* sys_device1 :: cl72_misc1_control :: link_control_forceval [14:14] */ 19450 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_MASK 0x4000 19451 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_ALIGN 0 19452 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_BITS 1 19453 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_LINK_CONTROL_FORCEVAL_SHIFT 14 19454 19455 /* sys_device1 :: cl72_misc1_control :: tx_fir_tap_main_kx_init_val [13:08] */ 19456 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_MASK 0x3f00 19457 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_ALIGN 0 19458 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_BITS 6 19459 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TX_FIR_TAP_MAIN_KX_INIT_VAL_SHIFT 8 19460 19461 /* sys_device1 :: cl72_misc1_control :: tap_default_muxsel_force [07:07] */ 19462 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_MASK 0x0080 19463 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_ALIGN 0 19464 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_BITS 1 19465 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCE_SHIFT 7 19466 19467 /* sys_device1 :: cl72_misc1_control :: tap_default_muxsel_forceval [06:04] */ 19468 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_MASK 0x0070 19469 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_ALIGN 0 19470 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_BITS 3 19471 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TAP_DEFAULT_MUXSEL_FORCEVAL_SHIFT 4 19472 19473 /* sys_device1 :: cl72_misc1_control :: reserved0 [03:02] */ 19474 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_RESERVED0_MASK 0x000c 19475 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_RESERVED0_ALIGN 0 19476 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_RESERVED0_BITS 2 19477 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_RESERVED0_SHIFT 2 19478 19479 /* sys_device1 :: cl72_misc1_control :: tr_coarse_lock [01:01] */ 19480 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TR_COARSE_LOCK_MASK 0x0002 19481 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TR_COARSE_LOCK_ALIGN 0 19482 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TR_COARSE_LOCK_BITS 1 19483 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_TR_COARSE_LOCK_SHIFT 1 19484 19485 /* sys_device1 :: cl72_misc1_control :: rx_trained [00:00] */ 19486 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_RX_TRAINED_MASK 0x0001 19487 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_RX_TRAINED_ALIGN 0 19488 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_RX_TRAINED_BITS 1 19489 #define PHY84328_SYS_DEV1_CL72_MISC1_CONTROL_RX_TRAINED_SHIFT 0 19490 19491 19492 /**************************************************************************** 19493 * sys_device1 :: cl72_misc2_control 19494 */ 19495 /* sys_device1 :: cl72_misc2_control :: reserved0 [15:14] */ 19496 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_RESERVED0_MASK 0xc000 19497 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_RESERVED0_ALIGN 0 19498 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_RESERVED0_BITS 2 19499 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_RESERVED0_SHIFT 14 19500 19501 /* sys_device1 :: cl72_misc2_control :: rxfifo_data_swap_r20clk [13:13] */ 19502 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_MASK 0x2000 19503 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_ALIGN 0 19504 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_BITS 1 19505 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_RXFIFO_DATA_SWAP_R20CLK_SHIFT 13 19506 19507 /* sys_device1 :: cl72_misc2_control :: txfifo_data_swap_t20clk [12:12] */ 19508 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_MASK 0x1000 19509 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_ALIGN 0 19510 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_BITS 1 19511 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_TXFIFO_DATA_SWAP_T20CLK_SHIFT 12 19512 19513 /* sys_device1 :: cl72_misc2_control :: signal_detect_fec_sel [11:11] */ 19514 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_MASK 0x0800 19515 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_ALIGN 0 19516 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_BITS 1 19517 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_SIGNAL_DETECT_FEC_SEL_SHIFT 11 19518 19519 /* sys_device1 :: cl72_misc2_control :: wait_timer_frame_inc_en [10:10] */ 19520 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_MASK 0x0400 19521 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_ALIGN 0 19522 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_BITS 1 19523 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_INC_EN_SHIFT 10 19524 19525 /* sys_device1 :: cl72_misc2_control :: wait_timer_frame_cnt_init_sel [09:08] */ 19526 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_MASK 0x0300 19527 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_ALIGN 0 19528 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_BITS 2 19529 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_WAIT_TIMER_FRAME_CNT_INIT_SEL_SHIFT 8 19530 19531 /* sys_device1 :: cl72_misc2_control :: main_tap_adjust_force [07:07] */ 19532 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_MASK 0x0080 19533 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_ALIGN 0 19534 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_BITS 1 19535 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCE_SHIFT 7 19536 19537 /* sys_device1 :: cl72_misc2_control :: main_tap_adjust_forceval [06:06] */ 19538 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_MASK 0x0040 19539 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_ALIGN 0 19540 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_BITS 1 19541 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_FORCEVAL_SHIFT 6 19542 19543 /* sys_device1 :: cl72_misc2_control :: main_tap_adjust_en [05:05] */ 19544 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_MASK 0x0020 19545 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_ALIGN 0 19546 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_BITS 1 19547 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_MAIN_TAP_ADJUST_EN_SHIFT 5 19548 19549 /* sys_device1 :: cl72_misc2_control :: newpg_rcvd_override [04:04] */ 19550 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_MASK 0x0010 19551 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_ALIGN 0 19552 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_BITS 1 19553 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_OVERRIDE_SHIFT 4 19554 19555 /* sys_device1 :: cl72_misc2_control :: newpg_rcvd_load [03:03] */ 19556 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_MASK 0x0008 19557 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_ALIGN 0 19558 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_BITS 1 19559 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_NEWPG_RCVD_LOAD_SHIFT 3 19560 19561 /* sys_device1 :: cl72_misc2_control :: inc_dec_val_sel [02:02] */ 19562 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_MASK 0x0004 19563 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_ALIGN 0 19564 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_BITS 1 19565 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_INC_DEC_VAL_SEL_SHIFT 2 19566 19567 /* sys_device1 :: cl72_misc2_control :: dis_max_wait_timer_force [01:01] */ 19568 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_MASK 0x0002 19569 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_ALIGN 0 19570 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_BITS 1 19571 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCE_SHIFT 1 19572 19573 /* sys_device1 :: cl72_misc2_control :: dis_max_wait_timer_forceval [00:00] */ 19574 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_MASK 0x0001 19575 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_ALIGN 0 19576 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_BITS 1 19577 #define PHY84328_SYS_DEV1_CL72_MISC2_CONTROL_DIS_MAX_WAIT_TIMER_FORCEVAL_SHIFT 0 19578 19579 19580 /**************************************************************************** 19581 * sys_device1 :: cl72_kr_default_control 19582 */ 19583 /* sys_device1 :: cl72_kr_default_control :: reserved0 [15:15] */ 19584 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 19585 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_RESERVED0_ALIGN 0 19586 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_RESERVED0_BITS 1 19587 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_RESERVED0_SHIFT 15 19588 19589 /* sys_device1 :: cl72_kr_default_control :: tx_fir_tap_post_kr_init_val [14:10] */ 19590 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_MASK 0x7c00 19591 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_ALIGN 0 19592 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_BITS 5 19593 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_POST_KR_INIT_VAL_SHIFT 10 19594 19595 /* sys_device1 :: cl72_kr_default_control :: tx_fir_tap_main_kr_init_val [09:04] */ 19596 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_MASK 0x03f0 19597 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_ALIGN 0 19598 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_BITS 6 19599 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_KR_INIT_VAL_SHIFT 4 19600 19601 /* sys_device1 :: cl72_kr_default_control :: tx_fir_tap_pre_kr_init_val [03:00] */ 19602 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_MASK 0x000f 19603 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_ALIGN 0 19604 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_BITS 4 19605 #define PHY84328_SYS_DEV1_CL72_KR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_KR_INIT_VAL_SHIFT 0 19606 19607 19608 /**************************************************************************** 19609 * sys_device1 :: cl72_os_default_control 19610 */ 19611 /* sys_device1 :: cl72_os_default_control :: reserved0 [15:15] */ 19612 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 19613 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_RESERVED0_ALIGN 0 19614 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_RESERVED0_BITS 1 19615 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_RESERVED0_SHIFT 15 19616 19617 /* sys_device1 :: cl72_os_default_control :: tx_fir_tap_post_os_init_val [14:10] */ 19618 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_MASK 0x7c00 19619 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_ALIGN 0 19620 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_BITS 5 19621 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_POST_OS_INIT_VAL_SHIFT 10 19622 19623 /* sys_device1 :: cl72_os_default_control :: tx_fir_tap_main_os_init_val [09:04] */ 19624 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_MASK 0x03f0 19625 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_ALIGN 0 19626 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_BITS 6 19627 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_OS_INIT_VAL_SHIFT 4 19628 19629 /* sys_device1 :: cl72_os_default_control :: tx_fir_tap_pre_os_init_val [03:00] */ 19630 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_MASK 0x000f 19631 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_ALIGN 0 19632 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_BITS 4 19633 #define PHY84328_SYS_DEV1_CL72_OS_DEFAULT_CONTROL_TX_FIR_TAP_PRE_OS_INIT_VAL_SHIFT 0 19634 19635 19636 /**************************************************************************** 19637 * sys_device1 :: cl72_br_default_control 19638 */ 19639 /* sys_device1 :: cl72_br_default_control :: reserved0 [15:15] */ 19640 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_RESERVED0_MASK 0x8000 19641 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_RESERVED0_ALIGN 0 19642 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_RESERVED0_BITS 1 19643 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_RESERVED0_SHIFT 15 19644 19645 /* sys_device1 :: cl72_br_default_control :: tx_fir_tap_post_br_init_val [14:10] */ 19646 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_MASK 0x7c00 19647 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_ALIGN 0 19648 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_BITS 5 19649 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_POST_BR_INIT_VAL_SHIFT 10 19650 19651 /* sys_device1 :: cl72_br_default_control :: tx_fir_tap_main_br_init_val [09:04] */ 19652 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_MASK 0x03f0 19653 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_ALIGN 0 19654 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_BITS 6 19655 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_MAIN_BR_INIT_VAL_SHIFT 4 19656 19657 /* sys_device1 :: cl72_br_default_control :: tx_fir_tap_pre_br_init_val [03:00] */ 19658 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_MASK 0x000f 19659 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_ALIGN 0 19660 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_BITS 4 19661 #define PHY84328_SYS_DEV1_CL72_BR_DEFAULT_CONTROL_TX_FIR_TAP_PRE_BR_INIT_VAL_SHIFT 0 19662 19663 19664 /**************************************************************************** 19665 * sys_device1 :: cl72_tap_limit_control 19666 */ 19667 /* sys_device1 :: cl72_tap_limit_control :: reserved0 [15:15] */ 19668 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_RESERVED0_MASK 0x8000 19669 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_RESERVED0_ALIGN 0 19670 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_RESERVED0_BITS 1 19671 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_RESERVED0_SHIFT 15 19672 19673 /* sys_device1 :: cl72_tap_limit_control :: post_tap_limit [14:10] */ 19674 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_MASK 0x7c00 19675 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_ALIGN 0 19676 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_BITS 5 19677 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_POST_TAP_LIMIT_SHIFT 10 19678 19679 /* sys_device1 :: cl72_tap_limit_control :: main_tap_limit [09:04] */ 19680 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_MASK 0x03f0 19681 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_ALIGN 0 19682 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_BITS 6 19683 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_MAIN_TAP_LIMIT_SHIFT 4 19684 19685 /* sys_device1 :: cl72_tap_limit_control :: pre_tap_limit [03:00] */ 19686 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_MASK 0x000f 19687 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_ALIGN 0 19688 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_BITS 4 19689 #define PHY84328_SYS_DEV1_CL72_TAP_LIMIT_CONTROL_PRE_TAP_LIMIT_SHIFT 0 19690 19691 19692 /**************************************************************************** 19693 * sys_device1 :: cl72_misc3_control 19694 */ 19695 /* sys_device1 :: cl72_misc3_control :: cl72_en_mask [15:00] */ 19696 #define PHY84328_SYS_DEV1_CL72_MISC3_CONTROL_CL72_EN_MASK_MASK 0xffff 19697 #define PHY84328_SYS_DEV1_CL72_MISC3_CONTROL_CL72_EN_MASK_ALIGN 0 19698 #define PHY84328_SYS_DEV1_CL72_MISC3_CONTROL_CL72_EN_MASK_BITS 16 19699 #define PHY84328_SYS_DEV1_CL72_MISC3_CONTROL_CL72_EN_MASK_SHIFT 0 19700 19701 19702 /**************************************************************************** 19703 * sys_device1 :: cl72_tap_preset_control 19704 */ 19705 /* sys_device1 :: cl72_tap_preset_control :: reserved0 [15:09] */ 19706 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_RESERVED0_MASK 0xfe00 19707 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_RESERVED0_ALIGN 0 19708 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_RESERVED0_BITS 7 19709 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_RESERVED0_SHIFT 9 19710 19711 /* sys_device1 :: cl72_tap_preset_control :: pre_init_val [08:05] */ 19712 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_MASK 0x01e0 19713 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_ALIGN 0 19714 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_BITS 4 19715 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_PRE_INIT_VAL_SHIFT 5 19716 19717 /* sys_device1 :: cl72_tap_preset_control :: post_init_val [04:00] */ 19718 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_MASK 0x001f 19719 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_ALIGN 0 19720 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_BITS 5 19721 #define PHY84328_SYS_DEV1_CL72_TAP_PRESET_CONTROL_POST_INIT_VAL_SHIFT 0 19722 19723 19724 /**************************************************************************** 19725 * sys_device1 :: cl72_misc4_control 19726 */ 19727 /* sys_device1 :: cl72_misc4_control :: reserved0 [15:12] */ 19728 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RESERVED0_MASK 0xf000 19729 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RESERVED0_ALIGN 0 19730 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RESERVED0_BITS 4 19731 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RESERVED0_SHIFT 12 19732 19733 /* sys_device1 :: cl72_misc4_control :: rx_wclk_20_mode_sel [11:10] */ 19734 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_MASK 0x0c00 19735 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_ALIGN 0 19736 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_BITS 2 19737 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_20_MODE_SEL_SHIFT 10 19738 19739 /* sys_device1 :: cl72_misc4_control :: rx_wclk16_ckgate_off [09:09] */ 19740 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_MASK 0x0200 19741 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_ALIGN 0 19742 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_BITS 1 19743 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_CKGATE_OFF_SHIFT 9 19744 19745 /* sys_device1 :: cl72_misc4_control :: rx_wclk16_legacy_clkmode [08:08] */ 19746 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_MASK 0x0100 19747 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_ALIGN 0 19748 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_BITS 1 19749 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_LEGACY_CLKMODE_SHIFT 8 19750 19751 /* sys_device1 :: cl72_misc4_control :: rx_wclk16_wclk20_per_lane [07:07] */ 19752 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_MASK 0x0080 19753 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_ALIGN 0 19754 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_BITS 1 19755 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK16_WCLK20_PER_LANE_SHIFT 7 19756 19757 /* sys_device1 :: cl72_misc4_control :: rx_wclk_16_mode_sel [06:05] */ 19758 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_MASK 0x0060 19759 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_ALIGN 0 19760 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_BITS 2 19761 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_16_MODE_SEL_SHIFT 5 19762 19763 /* sys_device1 :: cl72_misc4_control :: rx_wclk33_mode_sel [04:03] */ 19764 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_MASK 0x0018 19765 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_ALIGN 0 19766 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_BITS 2 19767 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK33_MODE_SEL_SHIFT 3 19768 19769 /* sys_device1 :: cl72_misc4_control :: rx_wclk_cl72_rst_sw [02:02] */ 19770 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_MASK 0x0004 19771 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_ALIGN 0 19772 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_BITS 1 19773 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_RST_SW_SHIFT 2 19774 19775 /* sys_device1 :: cl72_misc4_control :: rx_wclk_cl72_ckgate_sw [01:01] */ 19776 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_MASK 0x0002 19777 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_ALIGN 0 19778 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_BITS 1 19779 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_RX_WCLK_CL72_CKGATE_SW_SHIFT 1 19780 19781 /* sys_device1 :: cl72_misc4_control :: cl72_en_mask [00:00] */ 19782 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_CL72_EN_MASK_MASK 0x0001 19783 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_CL72_EN_MASK_ALIGN 0 19784 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_CL72_EN_MASK_BITS 1 19785 #define PHY84328_SYS_DEV1_CL72_MISC4_CONTROL_CL72_EN_MASK_SHIFT 0 19786 19787 19788 /**************************************************************************** 19789 * sys_device1 :: cl72_fault_register 19790 */ 19791 /* sys_device1 :: cl72_fault_register :: reserved0 [15:04] */ 19792 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_RESERVED0_MASK 0xfff0 19793 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_RESERVED0_ALIGN 0 19794 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_RESERVED0_BITS 12 19795 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_RESERVED0_SHIFT 4 19796 19797 /* sys_device1 :: cl72_fault_register :: cl72_frame_lock [03:03] */ 19798 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_CL72_FRAME_LOCK_MASK 0x0008 19799 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_CL72_FRAME_LOCK_ALIGN 0 19800 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_CL72_FRAME_LOCK_BITS 1 19801 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_CL72_FRAME_LOCK_SHIFT 3 19802 19803 /* sys_device1 :: cl72_fault_register :: micro_status_bit2 [02:02] */ 19804 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT2_MASK 0x0004 19805 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT2_ALIGN 0 19806 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT2_BITS 1 19807 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT2_SHIFT 2 19808 19809 /* sys_device1 :: cl72_fault_register :: micro_status_bit1 [01:01] */ 19810 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT1_MASK 0x0002 19811 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT1_ALIGN 0 19812 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT1_BITS 1 19813 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT1_SHIFT 1 19814 19815 /* sys_device1 :: cl72_fault_register :: micro_status_bit0 [00:00] */ 19816 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT0_MASK 0x0001 19817 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT0_ALIGN 0 19818 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT0_BITS 1 19819 #define PHY84328_SYS_DEV1_CL72_FAULT_REGISTER_MICRO_STATUS_BIT0_SHIFT 0 19820 19821 19822 /**************************************************************************** 19823 * sys_device1 :: cl72_debug_1_register 19824 */ 19825 /* sys_device1 :: cl72_debug_1_register :: reserved0 [15:12] */ 19826 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_RESERVED0_MASK 0xf000 19827 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_RESERVED0_ALIGN 0 19828 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_RESERVED0_BITS 4 19829 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_RESERVED0_SHIFT 12 19830 19831 /* sys_device1 :: cl72_debug_1_register :: tap_max_val [11:06] */ 19832 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_MASK 0x0fc0 19833 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_ALIGN 0 19834 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_BITS 6 19835 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_TAP_MAX_VAL_SHIFT 6 19836 19837 /* sys_device1 :: cl72_debug_1_register :: tap_min_val [05:00] */ 19838 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_MASK 0x003f 19839 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_ALIGN 0 19840 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_BITS 6 19841 #define PHY84328_SYS_DEV1_CL72_DEBUG_1_REGISTER_TAP_MIN_VAL_SHIFT 0 19842 19843 19844 /**************************************************************************** 19845 * sys_device1 :: cl72_debug_2_register 19846 */ 19847 /* sys_device1 :: cl72_debug_2_register :: pmd_data_swap [15:15] */ 19848 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_MASK 0x8000 19849 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_ALIGN 0 19850 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_BITS 1 19851 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_PMD_DATA_SWAP_SHIFT 15 19852 19853 /* sys_device1 :: cl72_debug_2_register :: brk_ring_osc [14:14] */ 19854 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC_MASK 0x4000 19855 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC_ALIGN 0 19856 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC_BITS 1 19857 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_BRK_RING_OSC_SHIFT 14 19858 19859 /* sys_device1 :: cl72_debug_2_register :: strict_marker_chk [13:13] */ 19860 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_MASK 0x2000 19861 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_ALIGN 0 19862 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_BITS 1 19863 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_STRICT_MARKER_CHK_SHIFT 13 19864 19865 /* sys_device1 :: cl72_debug_2_register :: strict_dme_chk [12:12] */ 19866 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_MASK 0x1000 19867 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_ALIGN 0 19868 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_BITS 1 19869 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_STRICT_DME_CHK_SHIFT 12 19870 19871 /* sys_device1 :: cl72_debug_2_register :: dis_max_wait_timer [11:11] */ 19872 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_MASK 0x0800 19873 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_ALIGN 0 19874 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_BITS 1 19875 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_DIS_MAX_WAIT_TIMER_SHIFT 11 19876 19877 /* sys_device1 :: cl72_debug_2_register :: max_wait_timer_val [10:09] */ 19878 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_MASK 0x0600 19879 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_ALIGN 0 19880 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_BITS 2 19881 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_MAX_WAIT_TIMER_VAL_SHIFT 9 19882 19883 /* sys_device1 :: cl72_debug_2_register :: signal_det_force [08:08] */ 19884 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_MASK 0x0100 19885 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_ALIGN 0 19886 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_BITS 1 19887 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_SIGNAL_DET_FORCE_SHIFT 8 19888 19889 /* sys_device1 :: cl72_debug_2_register :: tr_coarse_lock_force [07:07] */ 19890 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_MASK 0x0080 19891 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_ALIGN 0 19892 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_BITS 1 19893 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_TR_COARSE_LOCK_FORCE_SHIFT 7 19894 19895 /* sys_device1 :: cl72_debug_2_register :: clk_gate_force_ [06:06] */ 19896 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__MASK 0x0040 19897 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__ALIGN 0 19898 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__BITS 1 19899 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCE__SHIFT 6 19900 19901 /* sys_device1 :: cl72_debug_2_register :: clk_gate_forceval [05:05] */ 19902 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_MASK 0x0020 19903 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_ALIGN 0 19904 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_BITS 1 19905 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_CLK_GATE_FORCEVAL_SHIFT 5 19906 19907 /* sys_device1 :: cl72_debug_2_register :: bad_marker_cnt [04:02] */ 19908 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_MASK 0x001c 19909 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_ALIGN 0 19910 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_BITS 3 19911 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_BAD_MARKER_CNT_SHIFT 2 19912 19913 /* sys_device1 :: cl72_debug_2_register :: good_marker_cnt [01:00] */ 19914 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_MASK 0x0003 19915 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_ALIGN 0 19916 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_BITS 2 19917 #define PHY84328_SYS_DEV1_CL72_DEBUG_2_REGISTER_GOOD_MARKER_CNT_SHIFT 0 19918 19919 19920 /**************************************************************************** 19921 * sys_device1 :: cl72_debug_3_register 19922 */ 19923 /* sys_device1 :: cl72_debug_3_register :: signal_ok_force [15:15] */ 19924 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_MASK 0x8000 19925 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_ALIGN 0 19926 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_BITS 1 19927 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_SIGNAL_OK_FORCE_SHIFT 15 19928 19929 /* sys_device1 :: cl72_debug_3_register :: ctrl_frame_dly [14:11] */ 19930 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_MASK 0x7800 19931 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_ALIGN 0 19932 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_BITS 4 19933 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_CTRL_FRAME_DLY_SHIFT 11 19934 19935 /* sys_device1 :: cl72_debug_3_register :: random_seed [10:00] */ 19936 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_MASK 0x07ff 19937 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_ALIGN 0 19938 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_BITS 11 19939 #define PHY84328_SYS_DEV1_CL72_DEBUG_3_REGISTER_RANDOM_SEED_SHIFT 0 19940 19941 19942 /**************************************************************************** 19943 * sys_device1 :: cl72_debug_4_register 19944 */ 19945 /* sys_device1 :: cl72_debug_4_register :: reserved0 [15:14] */ 19946 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_RESERVED0_MASK 0xc000 19947 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_RESERVED0_ALIGN 0 19948 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_RESERVED0_BITS 2 19949 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_RESERVED0_SHIFT 14 19950 19951 /* sys_device1 :: cl72_debug_4_register :: brcm_mode_force [13:13] */ 19952 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_MASK 0x2000 19953 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_ALIGN 0 19954 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_BITS 1 19955 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCE_SHIFT 13 19956 19957 /* sys_device1 :: cl72_debug_4_register :: brcm_mode_forceval [12:12] */ 19958 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_MASK 0x1000 19959 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_ALIGN 0 19960 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_BITS 1 19961 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_BRCM_MODE_FORCEVAL_SHIFT 12 19962 19963 /* sys_device1 :: cl72_debug_4_register :: v2_constraint_dis [11:11] */ 19964 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_MASK 0x0800 19965 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_ALIGN 0 19966 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_BITS 1 19967 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_V2_CONSTRAINT_DIS_SHIFT 11 19968 19969 /* sys_device1 :: cl72_debug_4_register :: tap_v2_val [10:06] */ 19970 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_MASK 0x07c0 19971 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_ALIGN 0 19972 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_BITS 5 19973 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TAP_V2_VAL_SHIFT 6 19974 19975 /* sys_device1 :: cl72_debug_4_register :: micro_reg_reset [05:05] */ 19976 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_MASK 0x0020 19977 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_ALIGN 0 19978 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_BITS 1 19979 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_MICRO_REG_RESET_SHIFT 5 19980 19981 /* sys_device1 :: cl72_debug_4_register :: sigdet_forceval [04:04] */ 19982 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_MASK 0x0010 19983 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_ALIGN 0 19984 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_BITS 1 19985 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCEVAL_SHIFT 4 19986 19987 /* sys_device1 :: cl72_debug_4_register :: sigdet_force [03:03] */ 19988 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_MASK 0x0008 19989 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_ALIGN 0 19990 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_BITS 1 19991 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_SIGDET_FORCE_SHIFT 3 19992 19993 /* sys_device1 :: cl72_debug_4_register :: trnpat_en_forceval [02:02] */ 19994 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_MASK 0x0004 19995 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_ALIGN 0 19996 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_BITS 1 19997 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCEVAL_SHIFT 2 19998 19999 /* sys_device1 :: cl72_debug_4_register :: trnpat_en_force [01:01] */ 20000 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_MASK 0x0002 20001 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_ALIGN 0 20002 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_BITS 1 20003 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_TRNPAT_EN_FORCE_SHIFT 1 20004 20005 /* sys_device1 :: cl72_debug_4_register :: ppm_offset_en [00:00] */ 20006 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_MASK 0x0001 20007 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_ALIGN 0 20008 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_BITS 1 20009 #define PHY84328_SYS_DEV1_CL72_DEBUG_4_REGISTER_PPM_OFFSET_EN_SHIFT 0 20010 20011 20012 /**************************************************************************** 20013 * sys_device1_userLanesCtrl_Registers 20014 */ 20015 /**************************************************************************** 20016 * sys_device1 :: xgxsControl 20017 */ 20018 /* sys_device1 :: xgxsControl :: pgen_en [15:15] */ 20019 #define PHY84328_SYS_DEV1_XGXSCONTROL_PGEN_EN_MASK 0x8000 20020 #define PHY84328_SYS_DEV1_XGXSCONTROL_PGEN_EN_ALIGN 0 20021 #define PHY84328_SYS_DEV1_XGXSCONTROL_PGEN_EN_BITS 1 20022 #define PHY84328_SYS_DEV1_XGXSCONTROL_PGEN_EN_SHIFT 15 20023 20024 /* sys_device1 :: xgxsControl :: pcmp_en [14:14] */ 20025 #define PHY84328_SYS_DEV1_XGXSCONTROL_PCMP_EN_MASK 0x4000 20026 #define PHY84328_SYS_DEV1_XGXSCONTROL_PCMP_EN_ALIGN 0 20027 #define PHY84328_SYS_DEV1_XGXSCONTROL_PCMP_EN_BITS 1 20028 #define PHY84328_SYS_DEV1_XGXSCONTROL_PCMP_EN_SHIFT 14 20029 20030 /* sys_device1 :: xgxsControl :: start_sequencer [13:13] */ 20031 #define PHY84328_SYS_DEV1_XGXSCONTROL_START_SEQUENCER_MASK 0x2000 20032 #define PHY84328_SYS_DEV1_XGXSCONTROL_START_SEQUENCER_ALIGN 0 20033 #define PHY84328_SYS_DEV1_XGXSCONTROL_START_SEQUENCER_BITS 1 20034 #define PHY84328_SYS_DEV1_XGXSCONTROL_START_SEQUENCER_SHIFT 13 20035 20036 /* sys_device1 :: xgxsControl :: reset_anlg [12:12] */ 20037 #define PHY84328_SYS_DEV1_XGXSCONTROL_RESET_ANLG_MASK 0x1000 20038 #define PHY84328_SYS_DEV1_XGXSCONTROL_RESET_ANLG_ALIGN 0 20039 #define PHY84328_SYS_DEV1_XGXSCONTROL_RESET_ANLG_BITS 1 20040 #define PHY84328_SYS_DEV1_XGXSCONTROL_RESET_ANLG_SHIFT 12 20041 20042 /* sys_device1 :: xgxsControl :: mode_10g [11:08] */ 20043 #define PHY84328_SYS_DEV1_XGXSCONTROL_MODE_10G_MASK 0x0f00 20044 #define PHY84328_SYS_DEV1_XGXSCONTROL_MODE_10G_ALIGN 0 20045 #define PHY84328_SYS_DEV1_XGXSCONTROL_MODE_10G_BITS 4 20046 #define PHY84328_SYS_DEV1_XGXSCONTROL_MODE_10G_SHIFT 8 20047 20048 /* sys_device1 :: xgxsControl :: pll_bypass [07:07] */ 20049 #define PHY84328_SYS_DEV1_XGXSCONTROL_PLL_BYPASS_MASK 0x0080 20050 #define PHY84328_SYS_DEV1_XGXSCONTROL_PLL_BYPASS_ALIGN 0 20051 #define PHY84328_SYS_DEV1_XGXSCONTROL_PLL_BYPASS_BITS 1 20052 #define PHY84328_SYS_DEV1_XGXSCONTROL_PLL_BYPASS_SHIFT 7 20053 20054 /* sys_device1 :: xgxsControl :: rloop [06:06] */ 20055 #define PHY84328_SYS_DEV1_XGXSCONTROL_RLOOP_MASK 0x0040 20056 #define PHY84328_SYS_DEV1_XGXSCONTROL_RLOOP_ALIGN 0 20057 #define PHY84328_SYS_DEV1_XGXSCONTROL_RLOOP_BITS 1 20058 #define PHY84328_SYS_DEV1_XGXSCONTROL_RLOOP_SHIFT 6 20059 20060 /* sys_device1 :: xgxsControl :: reserved0 [05:05] */ 20061 #define PHY84328_SYS_DEV1_XGXSCONTROL_RESERVED0_MASK 0x0020 20062 #define PHY84328_SYS_DEV1_XGXSCONTROL_RESERVED0_ALIGN 0 20063 #define PHY84328_SYS_DEV1_XGXSCONTROL_RESERVED0_BITS 1 20064 #define PHY84328_SYS_DEV1_XGXSCONTROL_RESERVED0_SHIFT 5 20065 20066 /* sys_device1 :: xgxsControl :: mdio_cont_en [04:04] */ 20067 #define PHY84328_SYS_DEV1_XGXSCONTROL_MDIO_CONT_EN_MASK 0x0010 20068 #define PHY84328_SYS_DEV1_XGXSCONTROL_MDIO_CONT_EN_ALIGN 0 20069 #define PHY84328_SYS_DEV1_XGXSCONTROL_MDIO_CONT_EN_BITS 1 20070 #define PHY84328_SYS_DEV1_XGXSCONTROL_MDIO_CONT_EN_SHIFT 4 20071 20072 /* sys_device1 :: xgxsControl :: cdet_en [03:03] */ 20073 #define PHY84328_SYS_DEV1_XGXSCONTROL_CDET_EN_MASK 0x0008 20074 #define PHY84328_SYS_DEV1_XGXSCONTROL_CDET_EN_ALIGN 0 20075 #define PHY84328_SYS_DEV1_XGXSCONTROL_CDET_EN_BITS 1 20076 #define PHY84328_SYS_DEV1_XGXSCONTROL_CDET_EN_SHIFT 3 20077 20078 /* sys_device1 :: xgxsControl :: eden [02:02] */ 20079 #define PHY84328_SYS_DEV1_XGXSCONTROL_EDEN_MASK 0x0004 20080 #define PHY84328_SYS_DEV1_XGXSCONTROL_EDEN_ALIGN 0 20081 #define PHY84328_SYS_DEV1_XGXSCONTROL_EDEN_BITS 1 20082 #define PHY84328_SYS_DEV1_XGXSCONTROL_EDEN_SHIFT 2 20083 20084 /* sys_device1 :: xgxsControl :: afrst_en [01:01] */ 20085 #define PHY84328_SYS_DEV1_XGXSCONTROL_AFRST_EN_MASK 0x0002 20086 #define PHY84328_SYS_DEV1_XGXSCONTROL_AFRST_EN_ALIGN 0 20087 #define PHY84328_SYS_DEV1_XGXSCONTROL_AFRST_EN_BITS 1 20088 #define PHY84328_SYS_DEV1_XGXSCONTROL_AFRST_EN_SHIFT 1 20089 20090 /* sys_device1 :: xgxsControl :: txcko_div [00:00] */ 20091 #define PHY84328_SYS_DEV1_XGXSCONTROL_TXCKO_DIV_MASK 0x0001 20092 #define PHY84328_SYS_DEV1_XGXSCONTROL_TXCKO_DIV_ALIGN 0 20093 #define PHY84328_SYS_DEV1_XGXSCONTROL_TXCKO_DIV_BITS 1 20094 #define PHY84328_SYS_DEV1_XGXSCONTROL_TXCKO_DIV_SHIFT 0 20095 20096 20097 /**************************************************************************** 20098 * sys_device1 :: xgxsStatus 20099 */ 20100 /* sys_device1 :: xgxsStatus :: status_en [15:15] */ 20101 #define PHY84328_SYS_DEV1_XGXSSTATUS_STATUS_EN_MASK 0x8000 20102 #define PHY84328_SYS_DEV1_XGXSSTATUS_STATUS_EN_ALIGN 0 20103 #define PHY84328_SYS_DEV1_XGXSSTATUS_STATUS_EN_BITS 1 20104 #define PHY84328_SYS_DEV1_XGXSSTATUS_STATUS_EN_SHIFT 15 20105 20106 /* sys_device1 :: xgxsStatus :: reserved0 [14:12] */ 20107 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED0_MASK 0x7000 20108 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED0_ALIGN 0 20109 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED0_BITS 3 20110 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED0_SHIFT 12 20111 20112 /* sys_device1 :: xgxsStatus :: txpll_lock [11:11] */ 20113 #define PHY84328_SYS_DEV1_XGXSSTATUS_TXPLL_LOCK_MASK 0x0800 20114 #define PHY84328_SYS_DEV1_XGXSSTATUS_TXPLL_LOCK_ALIGN 0 20115 #define PHY84328_SYS_DEV1_XGXSSTATUS_TXPLL_LOCK_BITS 1 20116 #define PHY84328_SYS_DEV1_XGXSSTATUS_TXPLL_LOCK_SHIFT 11 20117 20118 /* sys_device1 :: xgxsStatus :: reserved1 [10:04] */ 20119 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED1_MASK 0x07f0 20120 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED1_ALIGN 0 20121 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED1_BITS 7 20122 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED1_SHIFT 4 20123 20124 /* sys_device1 :: xgxsStatus :: pll_mode_afe [03:03] */ 20125 #define PHY84328_SYS_DEV1_XGXSSTATUS_PLL_MODE_AFE_MASK 0x0008 20126 #define PHY84328_SYS_DEV1_XGXSSTATUS_PLL_MODE_AFE_ALIGN 0 20127 #define PHY84328_SYS_DEV1_XGXSSTATUS_PLL_MODE_AFE_BITS 1 20128 #define PHY84328_SYS_DEV1_XGXSSTATUS_PLL_MODE_AFE_SHIFT 3 20129 20130 /* sys_device1 :: xgxsStatus :: reserved2 [02:00] */ 20131 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED2_MASK 0x0007 20132 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED2_ALIGN 0 20133 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED2_BITS 3 20134 #define PHY84328_SYS_DEV1_XGXSSTATUS_RESERVED2_SHIFT 0 20135 20136 20137 /**************************************************************************** 20138 * sys_device1 :: miscControl1 20139 */ 20140 /* sys_device1 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */ 20141 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK 0x8000 20142 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN 0 20143 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS 1 20144 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT 15 20145 20146 /* sys_device1 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */ 20147 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK 0x4000 20148 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN 0 20149 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS 1 20150 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT 14 20151 20152 /* sys_device1 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */ 20153 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK 0x2000 20154 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN 0 20155 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS 1 20156 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT 13 20157 20158 /* sys_device1 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */ 20159 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK 0x1000 20160 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN 0 20161 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS 1 20162 #define PHY84328_SYS_DEV1_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT 12 20163 20164 /* sys_device1 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 20165 #define PHY84328_SYS_DEV1_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 20166 #define PHY84328_SYS_DEV1_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 20167 #define PHY84328_SYS_DEV1_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 20168 #define PHY84328_SYS_DEV1_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 20169 20170 /* sys_device1 :: miscControl1 :: reserved0 [10:05] */ 20171 #define PHY84328_SYS_DEV1_MISCCONTROL1_RESERVED0_MASK 0x07e0 20172 #define PHY84328_SYS_DEV1_MISCCONTROL1_RESERVED0_ALIGN 0 20173 #define PHY84328_SYS_DEV1_MISCCONTROL1_RESERVED0_BITS 6 20174 #define PHY84328_SYS_DEV1_MISCCONTROL1_RESERVED0_SHIFT 5 20175 20176 /* sys_device1 :: miscControl1 :: force_div5_for_lxck25 [04:04] */ 20177 #define PHY84328_SYS_DEV1_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK 0x0010 20178 #define PHY84328_SYS_DEV1_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN 0 20179 #define PHY84328_SYS_DEV1_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS 1 20180 #define PHY84328_SYS_DEV1_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT 4 20181 20182 /* sys_device1 :: miscControl1 :: reserved1 [03:03] */ 20183 #define PHY84328_SYS_DEV1_MISCCONTROL1_RESERVED1_MASK 0x0008 20184 #define PHY84328_SYS_DEV1_MISCCONTROL1_RESERVED1_ALIGN 0 20185 #define PHY84328_SYS_DEV1_MISCCONTROL1_RESERVED1_BITS 1 20186 #define PHY84328_SYS_DEV1_MISCCONTROL1_RESERVED1_SHIFT 3 20187 20188 /* sys_device1 :: miscControl1 :: invert_rx_sigdet [02:02] */ 20189 #define PHY84328_SYS_DEV1_MISCCONTROL1_INVERT_RX_SIGDET_MASK 0x0004 20190 #define PHY84328_SYS_DEV1_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN 0 20191 #define PHY84328_SYS_DEV1_MISCCONTROL1_INVERT_RX_SIGDET_BITS 1 20192 #define PHY84328_SYS_DEV1_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT 2 20193 20194 /* sys_device1 :: miscControl1 :: ieee_blksel_autodet [01:01] */ 20195 #define PHY84328_SYS_DEV1_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK 0x0002 20196 #define PHY84328_SYS_DEV1_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN 0 20197 #define PHY84328_SYS_DEV1_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS 1 20198 #define PHY84328_SYS_DEV1_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT 1 20199 20200 /* sys_device1 :: miscControl1 :: ieee_blksel_val [00:00] */ 20201 #define PHY84328_SYS_DEV1_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK 0x0001 20202 #define PHY84328_SYS_DEV1_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN 0 20203 #define PHY84328_SYS_DEV1_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS 1 20204 #define PHY84328_SYS_DEV1_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT 0 20205 20206 20207 /**************************************************************************** 20208 * sys_device1 :: laneCtrl2 20209 */ 20210 /* sys_device1 :: laneCtrl2 :: reserved0 [15:08] */ 20211 #define PHY84328_SYS_DEV1_LANECTRL2_RESERVED0_MASK 0xff00 20212 #define PHY84328_SYS_DEV1_LANECTRL2_RESERVED0_ALIGN 0 20213 #define PHY84328_SYS_DEV1_LANECTRL2_RESERVED0_BITS 8 20214 #define PHY84328_SYS_DEV1_LANECTRL2_RESERVED0_SHIFT 8 20215 20216 /* sys_device1 :: laneCtrl2 :: rloop1g [07:04] */ 20217 #define PHY84328_SYS_DEV1_LANECTRL2_RLOOP1G_MASK 0x00f0 20218 #define PHY84328_SYS_DEV1_LANECTRL2_RLOOP1G_ALIGN 0 20219 #define PHY84328_SYS_DEV1_LANECTRL2_RLOOP1G_BITS 4 20220 #define PHY84328_SYS_DEV1_LANECTRL2_RLOOP1G_SHIFT 4 20221 20222 /* sys_device1 :: laneCtrl2 :: reserved1 [03:00] */ 20223 #define PHY84328_SYS_DEV1_LANECTRL2_RESERVED1_MASK 0x000f 20224 #define PHY84328_SYS_DEV1_LANECTRL2_RESERVED1_ALIGN 0 20225 #define PHY84328_SYS_DEV1_LANECTRL2_RESERVED1_BITS 4 20226 #define PHY84328_SYS_DEV1_LANECTRL2_RESERVED1_SHIFT 0 20227 20228 20229 /**************************************************************************** 20230 * sys_device1 :: laneCtrl3 20231 */ 20232 /* sys_device1 :: laneCtrl3 :: lock_ref [15:12] */ 20233 #define PHY84328_SYS_DEV1_LANECTRL3_LOCK_REF_MASK 0xf000 20234 #define PHY84328_SYS_DEV1_LANECTRL3_LOCK_REF_ALIGN 0 20235 #define PHY84328_SYS_DEV1_LANECTRL3_LOCK_REF_BITS 4 20236 #define PHY84328_SYS_DEV1_LANECTRL3_LOCK_REF_SHIFT 12 20237 20238 /* sys_device1 :: laneCtrl3 :: pwrdwn_force [11:11] */ 20239 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN_FORCE_MASK 0x0800 20240 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN_FORCE_ALIGN 0 20241 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN_FORCE_BITS 1 20242 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN_FORCE_SHIFT 11 20243 20244 /* sys_device1 :: laneCtrl3 :: lock_ref_en [10:10] */ 20245 #define PHY84328_SYS_DEV1_LANECTRL3_LOCK_REF_EN_MASK 0x0400 20246 #define PHY84328_SYS_DEV1_LANECTRL3_LOCK_REF_EN_ALIGN 0 20247 #define PHY84328_SYS_DEV1_LANECTRL3_LOCK_REF_EN_BITS 1 20248 #define PHY84328_SYS_DEV1_LANECTRL3_LOCK_REF_EN_SHIFT 10 20249 20250 /* sys_device1 :: laneCtrl3 :: pwrdwn10g_pll_dis [09:09] */ 20251 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN10G_PLL_DIS_MASK 0x0200 20252 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN10G_PLL_DIS_ALIGN 0 20253 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN10G_PLL_DIS_BITS 1 20254 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN10G_PLL_DIS_SHIFT 9 20255 20256 /* sys_device1 :: laneCtrl3 :: pwrdwn_pll [08:08] */ 20257 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN_PLL_MASK 0x0100 20258 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN_PLL_ALIGN 0 20259 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN_PLL_BITS 1 20260 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDWN_PLL_SHIFT 8 20261 20262 /* sys_device1 :: laneCtrl3 :: pwrdn_tx [07:04] */ 20263 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDN_TX_MASK 0x00f0 20264 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDN_TX_ALIGN 0 20265 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDN_TX_BITS 4 20266 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDN_TX_SHIFT 4 20267 20268 /* sys_device1 :: laneCtrl3 :: pwrdn_rx [03:00] */ 20269 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDN_RX_MASK 0x000f 20270 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDN_RX_ALIGN 0 20271 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDN_RX_BITS 4 20272 #define PHY84328_SYS_DEV1_LANECTRL3_PWRDN_RX_SHIFT 0 20273 20274 20275 /**************************************************************************** 20276 * sys_device1 :: lanePrbs 20277 */ 20278 /* sys_device1 :: lanePrbs :: prbs_en3 [15:15] */ 20279 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN3_MASK 0x8000 20280 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN3_ALIGN 0 20281 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN3_BITS 1 20282 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN3_SHIFT 15 20283 20284 /* sys_device1 :: lanePrbs :: prbs_inv3 [14:14] */ 20285 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV3_MASK 0x4000 20286 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV3_ALIGN 0 20287 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV3_BITS 1 20288 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV3_SHIFT 14 20289 20290 /* sys_device1 :: lanePrbs :: prbs_order3 [13:12] */ 20291 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER3_MASK 0x3000 20292 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER3_ALIGN 0 20293 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER3_BITS 2 20294 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER3_SHIFT 12 20295 20296 /* sys_device1 :: lanePrbs :: prbs_en2 [11:11] */ 20297 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN2_MASK 0x0800 20298 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN2_ALIGN 0 20299 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN2_BITS 1 20300 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN2_SHIFT 11 20301 20302 /* sys_device1 :: lanePrbs :: prbs_inv2 [10:10] */ 20303 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV2_MASK 0x0400 20304 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV2_ALIGN 0 20305 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV2_BITS 1 20306 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV2_SHIFT 10 20307 20308 /* sys_device1 :: lanePrbs :: prbs_order2 [09:08] */ 20309 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER2_MASK 0x0300 20310 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER2_ALIGN 0 20311 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER2_BITS 2 20312 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER2_SHIFT 8 20313 20314 /* sys_device1 :: lanePrbs :: prbs_en1 [07:07] */ 20315 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN1_MASK 0x0080 20316 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN1_ALIGN 0 20317 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN1_BITS 1 20318 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN1_SHIFT 7 20319 20320 /* sys_device1 :: lanePrbs :: prbs_inv1 [06:06] */ 20321 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV1_MASK 0x0040 20322 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV1_ALIGN 0 20323 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV1_BITS 1 20324 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV1_SHIFT 6 20325 20326 /* sys_device1 :: lanePrbs :: prbs_order1 [05:04] */ 20327 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER1_MASK 0x0030 20328 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER1_ALIGN 0 20329 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER1_BITS 2 20330 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER1_SHIFT 4 20331 20332 /* sys_device1 :: lanePrbs :: prbs_en0 [03:03] */ 20333 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN0_MASK 0x0008 20334 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN0_ALIGN 0 20335 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN0_BITS 1 20336 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_EN0_SHIFT 3 20337 20338 /* sys_device1 :: lanePrbs :: prbs_inv0 [02:02] */ 20339 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV0_MASK 0x0004 20340 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV0_ALIGN 0 20341 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV0_BITS 1 20342 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_INV0_SHIFT 2 20343 20344 /* sys_device1 :: lanePrbs :: prbs_order0 [01:00] */ 20345 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER0_MASK 0x0003 20346 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER0_ALIGN 0 20347 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER0_BITS 2 20348 #define PHY84328_SYS_DEV1_LANEPRBS_PRBS_ORDER0_SHIFT 0 20349 20350 20351 /**************************************************************************** 20352 * sys_device1 :: laneCtrl 20353 */ 20354 /* sys_device1 :: laneCtrl :: reserved0 [15:11] */ 20355 #define PHY84328_SYS_DEV1_LANECTRL_RESERVED0_MASK 0xf800 20356 #define PHY84328_SYS_DEV1_LANECTRL_RESERVED0_ALIGN 0 20357 #define PHY84328_SYS_DEV1_LANECTRL_RESERVED0_BITS 5 20358 #define PHY84328_SYS_DEV1_LANECTRL_RESERVED0_SHIFT 11 20359 20360 /* sys_device1 :: laneCtrl :: pwrdn_ext_dis [10:10] */ 20361 #define PHY84328_SYS_DEV1_LANECTRL_PWRDN_EXT_DIS_MASK 0x0400 20362 #define PHY84328_SYS_DEV1_LANECTRL_PWRDN_EXT_DIS_ALIGN 0 20363 #define PHY84328_SYS_DEV1_LANECTRL_PWRDN_EXT_DIS_BITS 1 20364 #define PHY84328_SYS_DEV1_LANECTRL_PWRDN_EXT_DIS_SHIFT 10 20365 20366 /* sys_device1 :: laneCtrl :: pwrdn_safe_dis [09:09] */ 20367 #define PHY84328_SYS_DEV1_LANECTRL_PWRDN_SAFE_DIS_MASK 0x0200 20368 #define PHY84328_SYS_DEV1_LANECTRL_PWRDN_SAFE_DIS_ALIGN 0 20369 #define PHY84328_SYS_DEV1_LANECTRL_PWRDN_SAFE_DIS_BITS 1 20370 #define PHY84328_SYS_DEV1_LANECTRL_PWRDN_SAFE_DIS_SHIFT 9 20371 20372 /* sys_device1 :: laneCtrl :: pwrdwn_clks_en [08:08] */ 20373 #define PHY84328_SYS_DEV1_LANECTRL_PWRDWN_CLKS_EN_MASK 0x0100 20374 #define PHY84328_SYS_DEV1_LANECTRL_PWRDWN_CLKS_EN_ALIGN 0 20375 #define PHY84328_SYS_DEV1_LANECTRL_PWRDWN_CLKS_EN_BITS 1 20376 #define PHY84328_SYS_DEV1_LANECTRL_PWRDWN_CLKS_EN_SHIFT 8 20377 20378 /* sys_device1 :: laneCtrl :: rxSeqStart_ext_dis [07:07] */ 20379 #define PHY84328_SYS_DEV1_LANECTRL_RXSEQSTART_EXT_DIS_MASK 0x0080 20380 #define PHY84328_SYS_DEV1_LANECTRL_RXSEQSTART_EXT_DIS_ALIGN 0 20381 #define PHY84328_SYS_DEV1_LANECTRL_RXSEQSTART_EXT_DIS_BITS 1 20382 #define PHY84328_SYS_DEV1_LANECTRL_RXSEQSTART_EXT_DIS_SHIFT 7 20383 20384 /* sys_device1 :: laneCtrl :: pll_lock_rstb_r [06:06] */ 20385 #define PHY84328_SYS_DEV1_LANECTRL_PLL_LOCK_RSTB_R_MASK 0x0040 20386 #define PHY84328_SYS_DEV1_LANECTRL_PLL_LOCK_RSTB_R_ALIGN 0 20387 #define PHY84328_SYS_DEV1_LANECTRL_PLL_LOCK_RSTB_R_BITS 1 20388 #define PHY84328_SYS_DEV1_LANECTRL_PLL_LOCK_RSTB_R_SHIFT 6 20389 20390 /* sys_device1 :: laneCtrl :: lfck_bypass [05:05] */ 20391 #define PHY84328_SYS_DEV1_LANECTRL_LFCK_BYPASS_MASK 0x0020 20392 #define PHY84328_SYS_DEV1_LANECTRL_LFCK_BYPASS_ALIGN 0 20393 #define PHY84328_SYS_DEV1_LANECTRL_LFCK_BYPASS_BITS 1 20394 #define PHY84328_SYS_DEV1_LANECTRL_LFCK_BYPASS_SHIFT 5 20395 20396 /* sys_device1 :: laneCtrl :: rx_snoop_en [04:04] */ 20397 #define PHY84328_SYS_DEV1_LANECTRL_RX_SNOOP_EN_MASK 0x0010 20398 #define PHY84328_SYS_DEV1_LANECTRL_RX_SNOOP_EN_ALIGN 0 20399 #define PHY84328_SYS_DEV1_LANECTRL_RX_SNOOP_EN_BITS 1 20400 #define PHY84328_SYS_DEV1_LANECTRL_RX_SNOOP_EN_SHIFT 4 20401 20402 /* sys_device1 :: laneCtrl :: mode_10g_snoop [03:00] */ 20403 #define PHY84328_SYS_DEV1_LANECTRL_MODE_10G_SNOOP_MASK 0x000f 20404 #define PHY84328_SYS_DEV1_LANECTRL_MODE_10G_SNOOP_ALIGN 0 20405 #define PHY84328_SYS_DEV1_LANECTRL_MODE_10G_SNOOP_BITS 4 20406 #define PHY84328_SYS_DEV1_LANECTRL_MODE_10G_SNOOP_SHIFT 0 20407 20408 20409 /**************************************************************************** 20410 * sys_device1 :: TestModeLane 20411 */ 20412 /* sys_device1 :: TestModeLane :: eee_fast_timer_en [15:15] */ 20413 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_FAST_TIMER_EN_MASK 0x8000 20414 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_FAST_TIMER_EN_ALIGN 0 20415 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_FAST_TIMER_EN_BITS 1 20416 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_FAST_TIMER_EN_SHIFT 15 20417 20418 /* sys_device1 :: TestModeLane :: eee_gateclk_en [14:14] */ 20419 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_GATECLK_EN_MASK 0x4000 20420 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_GATECLK_EN_ALIGN 0 20421 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_GATECLK_EN_BITS 1 20422 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_GATECLK_EN_SHIFT 14 20423 20424 /* sys_device1 :: TestModeLane :: eee_gateoutclk_en [13:13] */ 20425 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_GATEOUTCLK_EN_MASK 0x2000 20426 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_GATEOUTCLK_EN_ALIGN 0 20427 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_GATEOUTCLK_EN_BITS 1 20428 #define PHY84328_SYS_DEV1_TESTMODELANE_EEE_GATEOUTCLK_EN_SHIFT 13 20429 20430 /* sys_device1 :: TestModeLane :: reserved0 [12:11] */ 20431 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED0_MASK 0x1800 20432 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED0_ALIGN 0 20433 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED0_BITS 2 20434 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED0_SHIFT 11 20435 20436 /* sys_device1 :: TestModeLane :: indck_mode_en_rx_force [10:10] */ 20437 #define PHY84328_SYS_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_MASK 0x0400 20438 #define PHY84328_SYS_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_ALIGN 0 20439 #define PHY84328_SYS_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_BITS 1 20440 #define PHY84328_SYS_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_SHIFT 10 20441 20442 /* sys_device1 :: TestModeLane :: indck_mode_en_rx_val [09:09] */ 20443 #define PHY84328_SYS_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_VAL_MASK 0x0200 20444 #define PHY84328_SYS_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_VAL_ALIGN 0 20445 #define PHY84328_SYS_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_VAL_BITS 1 20446 #define PHY84328_SYS_DEV1_TESTMODELANE_INDCK_MODE_EN_RX_VAL_SHIFT 9 20447 20448 /* sys_device1 :: TestModeLane :: use_cl82en_cya [08:08] */ 20449 #define PHY84328_SYS_DEV1_TESTMODELANE_USE_CL82EN_CYA_MASK 0x0100 20450 #define PHY84328_SYS_DEV1_TESTMODELANE_USE_CL82EN_CYA_ALIGN 0 20451 #define PHY84328_SYS_DEV1_TESTMODELANE_USE_CL82EN_CYA_BITS 1 20452 #define PHY84328_SYS_DEV1_TESTMODELANE_USE_CL82EN_CYA_SHIFT 8 20453 20454 /* sys_device1 :: TestModeLane :: txfifo_bypass [07:07] */ 20455 #define PHY84328_SYS_DEV1_TESTMODELANE_TXFIFO_BYPASS_MASK 0x0080 20456 #define PHY84328_SYS_DEV1_TESTMODELANE_TXFIFO_BYPASS_ALIGN 0 20457 #define PHY84328_SYS_DEV1_TESTMODELANE_TXFIFO_BYPASS_BITS 1 20458 #define PHY84328_SYS_DEV1_TESTMODELANE_TXFIFO_BYPASS_SHIFT 7 20459 20460 /* sys_device1 :: TestModeLane :: reserved1 [06:06] */ 20461 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED1_MASK 0x0040 20462 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED1_ALIGN 0 20463 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED1_BITS 1 20464 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED1_SHIFT 6 20465 20466 /* sys_device1 :: TestModeLane :: mode_change_rst_disable_for_tx [05:05] */ 20467 #define PHY84328_SYS_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_TX_MASK 0x0020 20468 #define PHY84328_SYS_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_TX_ALIGN 0 20469 #define PHY84328_SYS_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_TX_BITS 1 20470 #define PHY84328_SYS_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_TX_SHIFT 5 20471 20472 /* sys_device1 :: TestModeLane :: mode_change_rst_disable_for_rx [04:04] */ 20473 #define PHY84328_SYS_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_RX_MASK 0x0010 20474 #define PHY84328_SYS_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_RX_ALIGN 0 20475 #define PHY84328_SYS_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_RX_BITS 1 20476 #define PHY84328_SYS_DEV1_TESTMODELANE_MODE_CHANGE_RST_DISABLE_FOR_RX_SHIFT 4 20477 20478 /* sys_device1 :: TestModeLane :: reserved2 [03:00] */ 20479 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED2_MASK 0x000f 20480 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED2_ALIGN 0 20481 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED2_BITS 4 20482 #define PHY84328_SYS_DEV1_TESTMODELANE_RESERVED2_SHIFT 0 20483 20484 20485 /**************************************************************************** 20486 * sys_device1 :: laneReset 20487 */ 20488 /* sys_device1 :: laneReset :: reset_mdio [15:15] */ 20489 #define PHY84328_SYS_DEV1_LANERESET_RESET_MDIO_MASK 0x8000 20490 #define PHY84328_SYS_DEV1_LANERESET_RESET_MDIO_ALIGN 0 20491 #define PHY84328_SYS_DEV1_LANERESET_RESET_MDIO_BITS 1 20492 #define PHY84328_SYS_DEV1_LANERESET_RESET_MDIO_SHIFT 15 20493 20494 /* sys_device1 :: laneReset :: reserved0 [14:09] */ 20495 #define PHY84328_SYS_DEV1_LANERESET_RESERVED0_MASK 0x7e00 20496 #define PHY84328_SYS_DEV1_LANERESET_RESERVED0_ALIGN 0 20497 #define PHY84328_SYS_DEV1_LANERESET_RESERVED0_BITS 6 20498 #define PHY84328_SYS_DEV1_LANERESET_RESERVED0_SHIFT 9 20499 20500 /* sys_device1 :: laneReset :: reset_pll [08:08] */ 20501 #define PHY84328_SYS_DEV1_LANERESET_RESET_PLL_MASK 0x0100 20502 #define PHY84328_SYS_DEV1_LANERESET_RESET_PLL_ALIGN 0 20503 #define PHY84328_SYS_DEV1_LANERESET_RESET_PLL_BITS 1 20504 #define PHY84328_SYS_DEV1_LANERESET_RESET_PLL_SHIFT 8 20505 20506 /* sys_device1 :: laneReset :: reset_tx [07:04] */ 20507 #define PHY84328_SYS_DEV1_LANERESET_RESET_TX_MASK 0x00f0 20508 #define PHY84328_SYS_DEV1_LANERESET_RESET_TX_ALIGN 0 20509 #define PHY84328_SYS_DEV1_LANERESET_RESET_TX_BITS 4 20510 #define PHY84328_SYS_DEV1_LANERESET_RESET_TX_SHIFT 4 20511 20512 /* sys_device1 :: laneReset :: reset_rx [03:00] */ 20513 #define PHY84328_SYS_DEV1_LANERESET_RESET_RX_MASK 0x000f 20514 #define PHY84328_SYS_DEV1_LANERESET_RESET_RX_ALIGN 0 20515 #define PHY84328_SYS_DEV1_LANERESET_RESET_RX_BITS 4 20516 #define PHY84328_SYS_DEV1_LANERESET_RESET_RX_SHIFT 0 20517 20518 20519 /**************************************************************************** 20520 * sys_device1 :: XFIcontrol 20521 */ 20522 /* sys_device1 :: XFIcontrol :: reserved0 [15:06] */ 20523 #define PHY84328_SYS_DEV1_XFICONTROL_RESERVED0_MASK 0xffc0 20524 #define PHY84328_SYS_DEV1_XFICONTROL_RESERVED0_ALIGN 0 20525 #define PHY84328_SYS_DEV1_XFICONTROL_RESERVED0_BITS 10 20526 #define PHY84328_SYS_DEV1_XFICONTROL_RESERVED0_SHIFT 6 20527 20528 /* sys_device1 :: XFIcontrol :: fc_mode_disable [05:05] */ 20529 #define PHY84328_SYS_DEV1_XFICONTROL_FC_MODE_DISABLE_MASK 0x0020 20530 #define PHY84328_SYS_DEV1_XFICONTROL_FC_MODE_DISABLE_ALIGN 0 20531 #define PHY84328_SYS_DEV1_XFICONTROL_FC_MODE_DISABLE_BITS 1 20532 #define PHY84328_SYS_DEV1_XFICONTROL_FC_MODE_DISABLE_SHIFT 5 20533 20534 /* sys_device1 :: XFIcontrol :: xfipcs_pwrdown [04:04] */ 20535 #define PHY84328_SYS_DEV1_XFICONTROL_XFIPCS_PWRDOWN_MASK 0x0010 20536 #define PHY84328_SYS_DEV1_XFICONTROL_XFIPCS_PWRDOWN_ALIGN 0 20537 #define PHY84328_SYS_DEV1_XFICONTROL_XFIPCS_PWRDOWN_BITS 1 20538 #define PHY84328_SYS_DEV1_XFICONTROL_XFIPCS_PWRDOWN_SHIFT 4 20539 20540 /* sys_device1 :: XFIcontrol :: xfi_rx_bypass_val [03:03] */ 20541 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_RX_BYPASS_VAL_MASK 0x0008 20542 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_RX_BYPASS_VAL_ALIGN 0 20543 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_RX_BYPASS_VAL_BITS 1 20544 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_RX_BYPASS_VAL_SHIFT 3 20545 20546 /* sys_device1 :: XFIcontrol :: xfi_rx_bypass_force [02:02] */ 20547 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_RX_BYPASS_FORCE_MASK 0x0004 20548 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_RX_BYPASS_FORCE_ALIGN 0 20549 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_RX_BYPASS_FORCE_BITS 1 20550 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_RX_BYPASS_FORCE_SHIFT 2 20551 20552 /* sys_device1 :: XFIcontrol :: xfi_tx_bypass_val [01:01] */ 20553 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_TX_BYPASS_VAL_MASK 0x0002 20554 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_TX_BYPASS_VAL_ALIGN 0 20555 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_TX_BYPASS_VAL_BITS 1 20556 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_TX_BYPASS_VAL_SHIFT 1 20557 20558 /* sys_device1 :: XFIcontrol :: xfi_tx_bypass_force [00:00] */ 20559 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_TX_BYPASS_FORCE_MASK 0x0001 20560 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_TX_BYPASS_FORCE_ALIGN 0 20561 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_TX_BYPASS_FORCE_BITS 1 20562 #define PHY84328_SYS_DEV1_XFICONTROL_XFI_TX_BYPASS_FORCE_SHIFT 0 20563 20564 20565 /**************************************************************************** 20566 * sys_device1 :: cl73Control7 20567 */ 20568 /* sys_device1 :: cl73Control7 :: cl73_an_switch_cntL [15:00] */ 20569 #define PHY84328_SYS_DEV1_CL73CONTROL7_CL73_AN_SWITCH_CNTL_MASK 0xffff 20570 #define PHY84328_SYS_DEV1_CL73CONTROL7_CL73_AN_SWITCH_CNTL_ALIGN 0 20571 #define PHY84328_SYS_DEV1_CL73CONTROL7_CL73_AN_SWITCH_CNTL_BITS 16 20572 #define PHY84328_SYS_DEV1_CL73CONTROL7_CL73_AN_SWITCH_CNTL_SHIFT 0 20573 20574 20575 /**************************************************************************** 20576 * sys_device1 :: cl73Control8 20577 */ 20578 /* sys_device1 :: cl73Control8 :: cl73_refclk_161_offset_cnt [15:08] */ 20579 #define PHY84328_SYS_DEV1_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_MASK 0xff00 20580 #define PHY84328_SYS_DEV1_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_ALIGN 0 20581 #define PHY84328_SYS_DEV1_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_BITS 8 20582 #define PHY84328_SYS_DEV1_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_SHIFT 8 20583 20584 /* sys_device1 :: cl73Control8 :: cl73_an_switch_cntH [07:00] */ 20585 #define PHY84328_SYS_DEV1_CL73CONTROL8_CL73_AN_SWITCH_CNTH_MASK 0x00ff 20586 #define PHY84328_SYS_DEV1_CL73CONTROL8_CL73_AN_SWITCH_CNTH_ALIGN 0 20587 #define PHY84328_SYS_DEV1_CL73CONTROL8_CL73_AN_SWITCH_CNTH_BITS 8 20588 #define PHY84328_SYS_DEV1_CL73CONTROL8_CL73_AN_SWITCH_CNTH_SHIFT 0 20589 20590 20591 /**************************************************************************** 20592 * sys_device1 :: cl73Control9 20593 */ 20594 /* sys_device1 :: cl73Control9 :: reserved0 [15:15] */ 20595 #define PHY84328_SYS_DEV1_CL73CONTROL9_RESERVED0_MASK 0x8000 20596 #define PHY84328_SYS_DEV1_CL73CONTROL9_RESERVED0_ALIGN 0 20597 #define PHY84328_SYS_DEV1_CL73CONTROL9_RESERVED0_BITS 1 20598 #define PHY84328_SYS_DEV1_CL73CONTROL9_RESERVED0_SHIFT 15 20599 20600 /* sys_device1 :: cl73Control9 :: rxSeqDone_cya [14:14] */ 20601 #define PHY84328_SYS_DEV1_CL73CONTROL9_RXSEQDONE_CYA_MASK 0x4000 20602 #define PHY84328_SYS_DEV1_CL73CONTROL9_RXSEQDONE_CYA_ALIGN 0 20603 #define PHY84328_SYS_DEV1_CL73CONTROL9_RXSEQDONE_CYA_BITS 1 20604 #define PHY84328_SYS_DEV1_CL73CONTROL9_RXSEQDONE_CYA_SHIFT 14 20605 20606 /* sys_device1 :: cl73Control9 :: cl73_link_fail_inhibit_timer_kr_val [13:00] */ 20607 #define PHY84328_SYS_DEV1_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_MASK 0x3fff 20608 #define PHY84328_SYS_DEV1_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_ALIGN 0 20609 #define PHY84328_SYS_DEV1_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_BITS 14 20610 #define PHY84328_SYS_DEV1_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_SHIFT 0 20611 20612 20613 /**************************************************************************** 20614 * sys_device1 :: cl73Control10 20615 */ 20616 /* sys_device1 :: cl73Control10 :: reserved0 [15:14] */ 20617 #define PHY84328_SYS_DEV1_CL73CONTROL10_RESERVED0_MASK 0xc000 20618 #define PHY84328_SYS_DEV1_CL73CONTROL10_RESERVED0_ALIGN 0 20619 #define PHY84328_SYS_DEV1_CL73CONTROL10_RESERVED0_BITS 2 20620 #define PHY84328_SYS_DEV1_CL73CONTROL10_RESERVED0_SHIFT 14 20621 20622 /* sys_device1 :: cl73Control10 :: cl73_link_fail_inhibit_timer_cl72_val [13:00] */ 20623 #define PHY84328_SYS_DEV1_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_MASK 0x3fff 20624 #define PHY84328_SYS_DEV1_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_ALIGN 0 20625 #define PHY84328_SYS_DEV1_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_BITS 14 20626 #define PHY84328_SYS_DEV1_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_SHIFT 0 20627 20628 20629 /**************************************************************************** 20630 * sys_device1 :: xfi_afe_ctl1 20631 */ 20632 /* sys_device1 :: xfi_afe_ctl1 :: refclk_val [15:15] */ 20633 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_REFCLK_VAL_MASK 0x8000 20634 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_REFCLK_VAL_ALIGN 0 20635 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_REFCLK_VAL_BITS 1 20636 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_REFCLK_VAL_SHIFT 15 20637 20638 /* sys_device1 :: xfi_afe_ctl1 :: refclk_sel [14:14] */ 20639 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_REFCLK_SEL_MASK 0x4000 20640 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_REFCLK_SEL_ALIGN 0 20641 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_REFCLK_SEL_BITS 1 20642 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_REFCLK_SEL_SHIFT 14 20643 20644 /* sys_device1 :: xfi_afe_ctl1 :: tx_fir_sel [13:13] */ 20645 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_TX_FIR_SEL_MASK 0x2000 20646 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_TX_FIR_SEL_ALIGN 0 20647 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_TX_FIR_SEL_BITS 1 20648 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_TX_FIR_SEL_SHIFT 13 20649 20650 /* sys_device1 :: xfi_afe_ctl1 :: cal_valid_value [12:12] */ 20651 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_CAL_VALID_VALUE_MASK 0x1000 20652 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_CAL_VALID_VALUE_ALIGN 0 20653 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_CAL_VALID_VALUE_BITS 1 20654 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_CAL_VALID_VALUE_SHIFT 12 20655 20656 /* sys_device1 :: xfi_afe_ctl1 :: calibration_valid [11:11] */ 20657 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_CALIBRATION_VALID_MASK 0x0800 20658 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_CALIBRATION_VALID_ALIGN 0 20659 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_CALIBRATION_VALID_BITS 1 20660 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_CALIBRATION_VALID_SHIFT 11 20661 20662 /* sys_device1 :: xfi_afe_ctl1 :: Status_Select [10:08] */ 20663 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_STATUS_SELECT_MASK 0x0700 20664 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_STATUS_SELECT_ALIGN 0 20665 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_STATUS_SELECT_BITS 3 20666 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_STATUS_SELECT_SHIFT 8 20667 20668 /* sys_device1 :: xfi_afe_ctl1 :: drv5g_sel [07:07] */ 20669 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_DRV5G_SEL_MASK 0x0080 20670 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_DRV5G_SEL_ALIGN 0 20671 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_DRV5G_SEL_BITS 1 20672 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_DRV5G_SEL_SHIFT 7 20673 20674 /* sys_device1 :: xfi_afe_ctl1 :: buf10g_sel [06:06] */ 20675 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_BUF10G_SEL_MASK 0x0040 20676 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_BUF10G_SEL_ALIGN 0 20677 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_BUF10G_SEL_BITS 1 20678 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_BUF10G_SEL_SHIFT 6 20679 20680 /* sys_device1 :: xfi_afe_ctl1 :: pll_range_sel [05:05] */ 20681 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RANGE_SEL_MASK 0x0020 20682 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RANGE_SEL_ALIGN 0 20683 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RANGE_SEL_BITS 1 20684 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RANGE_SEL_SHIFT 5 20685 20686 /* sys_device1 :: xfi_afe_ctl1 :: pll_rescal_sel [04:04] */ 20687 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_SEL_MASK 0x0010 20688 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_SEL_ALIGN 0 20689 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_SEL_BITS 1 20690 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_SEL_SHIFT 4 20691 20692 /* sys_device1 :: xfi_afe_ctl1 :: pll_rescal_offset_sel [03:03] */ 20693 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SEL_MASK 0x0008 20694 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SEL_ALIGN 0 20695 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SEL_BITS 1 20696 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SEL_SHIFT 3 20697 20698 /* sys_device1 :: xfi_afe_ctl1 :: pll_rescal_offset [02:00] */ 20699 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_MASK 0x0007 20700 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_ALIGN 0 20701 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_BITS 3 20702 #define PHY84328_SYS_DEV1_XFI_AFE_CTL1_PLL_RESCAL_OFFSET_SHIFT 0 20703 20704 20705 /**************************************************************************** 20706 * sys_device1 :: xfi_afe_ctl2 20707 */ 20708 /* sys_device1 :: xfi_afe_ctl2 :: reserved0 [15:14] */ 20709 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_RESERVED0_MASK 0xc000 20710 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_RESERVED0_ALIGN 0 20711 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_RESERVED0_BITS 2 20712 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_RESERVED0_SHIFT 14 20713 20714 /* sys_device1 :: xfi_afe_ctl2 :: pll_mode_sel [13:13] */ 20715 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_PLL_MODE_SEL_MASK 0x2000 20716 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_PLL_MODE_SEL_ALIGN 0 20717 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_PLL_MODE_SEL_BITS 1 20718 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_PLL_MODE_SEL_SHIFT 13 20719 20720 /* sys_device1 :: xfi_afe_ctl2 :: pll_sts_sel [12:12] */ 20721 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_PLL_STS_SEL_MASK 0x1000 20722 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_PLL_STS_SEL_ALIGN 0 20723 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_PLL_STS_SEL_BITS 1 20724 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_PLL_STS_SEL_SHIFT 12 20725 20726 /* sys_device1 :: xfi_afe_ctl2 :: Ge50sel_val [11:11] */ 20727 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_GE50SEL_VAL_MASK 0x0800 20728 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_GE50SEL_VAL_ALIGN 0 20729 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_GE50SEL_VAL_BITS 1 20730 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_GE50SEL_VAL_SHIFT 11 20731 20732 /* sys_device1 :: xfi_afe_ctl2 :: Ge50sel [10:10] */ 20733 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_GE50SEL_MASK 0x0400 20734 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_GE50SEL_ALIGN 0 20735 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_GE50SEL_BITS 1 20736 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_GE50SEL_SHIFT 10 20737 20738 /* sys_device1 :: xfi_afe_ctl2 :: Fc156sel_val [09:09] */ 20739 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_FC156SEL_VAL_MASK 0x0200 20740 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_FC156SEL_VAL_ALIGN 0 20741 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_FC156SEL_VAL_BITS 1 20742 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_FC156SEL_VAL_SHIFT 9 20743 20744 /* sys_device1 :: xfi_afe_ctl2 :: Fc156sel [08:08] */ 20745 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_FC156SEL_MASK 0x0100 20746 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_FC156SEL_ALIGN 0 20747 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_FC156SEL_BITS 1 20748 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_FC156SEL_SHIFT 8 20749 20750 /* sys_device1 :: xfi_afe_ctl2 :: tx_rescal_sel [07:04] */ 20751 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_TX_RESCAL_SEL_MASK 0x00f0 20752 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_TX_RESCAL_SEL_ALIGN 0 20753 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_TX_RESCAL_SEL_BITS 4 20754 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_TX_RESCAL_SEL_SHIFT 4 20755 20756 /* sys_device1 :: xfi_afe_ctl2 :: tx_fir_sel [03:00] */ 20757 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_TX_FIR_SEL_MASK 0x000f 20758 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_TX_FIR_SEL_ALIGN 0 20759 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_TX_FIR_SEL_BITS 4 20760 #define PHY84328_SYS_DEV1_XFI_AFE_CTL2_TX_FIR_SEL_SHIFT 0 20761 20762 20763 20764 /**************************************************************************** 20765 * sys_device7_AN_Standard_Registers 20766 */ 20767 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER 0x00000000 /* AN Control Register */ 20768 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER 0x00000001 /* AN Status Register */ 20769 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_0 0x00000002 /* AN Identifier Register 0 */ 20770 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_1 0x00000003 /* AN Identifier Register 1 */ 20771 #define PHY84328_SYS_DEV7_AN_OUI_ID0_REGISTER 0x0000000e /* AN OUI ID0 Register */ 20772 #define PHY84328_SYS_DEV7_AN_OUI_ID1_REG 0x0000000f /* AN OUI ID1 Reg */ 20773 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER 0x00000010 /* AN Advertisement 1 Register */ 20774 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER 0x00000011 /* AN Advertisement 2 Register */ 20775 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER 0x00000012 /* AN Advertisement 3 Register */ 20776 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG 0x00000013 /* AN LP Base Page Ability 1 Register */ 20777 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG 0x00000014 /* AN LP Base Page Ability 2 Register */ 20778 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG 0x00000015 /* AN LP Base Page Ability 3 Register */ 20779 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER 0x00000016 /* AN XNP transmit 1 Register */ 20780 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_2_REGISTER 0x00000017 /* AN XNP transmit 2 Register */ 20781 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_3_REGISTER 0x00000018 /* AN XNP transmit 3 Register */ 20782 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER 0x00000019 /* AN LP XNP transmit 1 Register */ 20783 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER 0x0000001a /* AN LP XNP transmit 2 Register */ 20784 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER 0x0000001b /* AN LP XNP transmit 3 Register */ 20785 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER 0x00000030 /* Backplane Ethernet Status Register */ 20786 #define PHY84328_SYS_DEV7_EEE_ADV 0x0000003c /* EEE_adv_type */ 20787 #define PHY84328_SYS_DEV7_EEE_LP_ADV 0x0000003d /* EEE_lp_adv_type */ 20788 20789 20790 /**************************************************************************** 20791 * sys_device7_cl73_userb0 20792 */ 20793 #define PHY84328_SYS_DEV7_CL73_UCTRL1 0x0000c370 /* CL73_UCtrl1_type */ 20794 #define PHY84328_SYS_DEV7_CL73_USTAT1 0x0000c371 /* CL73_UStat1_type */ 20795 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1 0x0000c372 /* CL73_BAMCtrl1_type */ 20796 #define PHY84328_SYS_DEV7_CL73_BAMCTRL2 0x0000c373 /* CL73_BAMCtrl2_type */ 20797 #define PHY84328_SYS_DEV7_CL73_BAMCTRL3 0x0000c374 /* CL73_BAMCtrl3_type */ 20798 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1 0x0000c375 /* CL73_BAMStat1_type */ 20799 #define PHY84328_SYS_DEV7_CL73_BAMSTAT2 0x0000c376 /* CL73_BAMStat2_type */ 20800 #define PHY84328_SYS_DEV7_CL73_BAMSTAT3 0x0000c377 /* CL73_BAMStat3_type */ 20801 #define PHY84328_SYS_DEV7_CL73_UCTRL2 0x0000c378 /* CL73_UCtrl2_type */ 20802 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE 0x0000c37e /* CL73_EEECtrl_type */ 20803 20804 20805 /**************************************************************************** 20806 * sys_device7_gp_status 20807 */ 20808 #define PHY84328_SYS_DEV7_MISCRXSTATUS 0x0000c120 /* MiscRxStatus_Reg */ 20809 #define PHY84328_SYS_DEV7_X2500STATUS1 0x0000c12a /* basex2500Status1_Reg */ 20810 #define PHY84328_SYS_DEV7_TOPANSTATUS1 0x0000c12b /* topANStatus1_Reg */ 20811 #define PHY84328_SYS_DEV7_LP_UP1 0x0000c12c /* LP_UP1_Reg */ 20812 #define PHY84328_SYS_DEV7_LP_UP2 0x0000c12d /* LP_UP2_Reg */ 20813 #define PHY84328_SYS_DEV7_LP_UP3 0x0000c12e /* LP_UP3_Reg */ 20814 20815 20816 /**************************************************************************** 20817 * sys_device7_userPerLnCtrl_Registers 20818 */ 20819 #define PHY84328_SYS_DEV7_CL73CONTROL1 0x0000c135 /* Clause 73 auto-negotiation control register 1 */ 20820 #define PHY84328_SYS_DEV7_CL73CONTROL2 0x0000c136 /* Clause 73 auto-negotiation control register 2 */ 20821 #define PHY84328_SYS_DEV7_CL73CONTROL3 0x0000c137 /* Clause 73 auto-negotiation control register 3 */ 20822 #define PHY84328_SYS_DEV7_CL73CONTROL4 0x0000c138 /* Clause 73 auto-negotiation control register 4 */ 20823 #define PHY84328_SYS_DEV7_CL73CONTROL5 0x0000c139 /* Clause 73 auto-negotiation control register 5 */ 20824 #define PHY84328_SYS_DEV7_CL73CONTROL6 0x0000c13a /* Clause 73 auto-negotiation control register 6 */ 20825 #define PHY84328_SYS_DEV7_CL73DMETMRS 0x0000c13b /* Clause 73 auto-negotiation DME Timers Register */ 20826 #define PHY84328_SYS_DEV7_CONTROL1000X1 0x0000c300 /* 1000X control 1 register */ 20827 #define PHY84328_SYS_DEV7_CONTROL1000X2 0x0000c301 /* 1000X control 2 register */ 20828 #define PHY84328_SYS_DEV7_CONTROL1000X3 0x0000c302 /* 1000X control 3 register */ 20829 #define PHY84328_SYS_DEV7_CONTROL1000X4 0x0000c303 /* 1000X control 4 register */ 20830 #define PHY84328_SYS_DEV7_STATUS1000X1 0x0000c304 /* 1000X status 1 register */ 20831 #define PHY84328_SYS_DEV7_STATUS1000X2 0x0000c305 /* 1000X status 2 register */ 20832 #define PHY84328_SYS_DEV7_STATUS1000X3 0x0000c306 /* 1000X status 3 register */ 20833 #define PHY84328_SYS_DEV7_BADCODEGROUP 0x0000c307 /* Invalid code group count register */ 20834 #define PHY84328_SYS_DEV7_MISC1 0x0000c308 /* Miscellaneous 1 control register */ 20835 #define PHY84328_SYS_DEV7_MISC2 0x0000c309 /* Miscellaneous 2 control register */ 20836 #define PHY84328_SYS_DEV7_PATGENCTRL 0x0000c30a /* Pattern generator control register */ 20837 #define PHY84328_SYS_DEV7_PATGENSTAT 0x0000c30b /* Pattern generator status register */ 20838 #define PHY84328_SYS_DEV7_TESTMODE 0x0000c30c /* Test mode register */ 20839 #define PHY84328_SYS_DEV7_TXPKTCNT 0x0000c30d /* Tx packet count register */ 20840 #define PHY84328_SYS_DEV7_RXPKTCNT 0x0000c30e /* Rx packet count register */ 20841 #define PHY84328_SYS_DEV7_DIGCTL_3_0 0x0000c320 /* AN lost link count time, bits 15:0 */ 20842 #define PHY84328_SYS_DEV7_DIGCTL_3_1 0x0000c321 /* AN switch count time, bits 15:0 */ 20843 #define PHY84328_SYS_DEV7_DIGCTL_3_2 0x0000c322 /* AN link count time, bits 15:0 */ 20844 #define PHY84328_SYS_DEV7_DIGCTL_3_3 0x0000c323 /* AN switch count & link count time, bits 23:16 */ 20845 #define PHY84328_SYS_DEV7_DIGCTL_3_4 0x0000c324 /* Over 1G message page number & AN fail count timer */ 20846 #define PHY84328_SYS_DEV7_DIGCTL_3_5 0x0000c325 /* AN ignore link count time, bits 15:0 */ 20847 #define PHY84328_SYS_DEV7_DIGCTL_3_6 0x0000c326 /* AN lost link count & ignore link count time, bits 23:16 */ 20848 #define PHY84328_SYS_DEV7_UP1 0x0000c329 /* AN local device user page 1 */ 20849 #define PHY84328_SYS_DEV7_UP2 0x0000c32a /* AN local device user page 2 */ 20850 #define PHY84328_SYS_DEV7_UP3 0x0000c32b /* AN local device user page 3 */ 20851 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1 0x0000c32c /* AN link partner user page 1 */ 20852 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2 0x0000c32d /* AN link partner user page 2 */ 20853 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3 0x0000c32e /* AN link partner user page 3 */ 20854 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS 0x0000c330 /* Dig 4 Miscellaneous Rx status register */ 20855 #define PHY84328_SYS_DEV7_LP_BASEPAGE 0x0000c331 /* Dig 4 Link partner basepage register */ 20856 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_0 0x0000c332 /* Dig 4 Link partner nextpage 0 register */ 20857 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_1 0x0000c333 /* Dig 4 Link partner nextpage 1 register */ 20858 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_2 0x0000c334 /* Dig 4 Link partner nextpage 2 register */ 20859 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_3 0x0000c335 /* Dig 4 Link partner nextpage 3 register */ 20860 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_4 0x0000c336 /* Dig 4 Link partner nextpage 4 register */ 20861 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0 0x0000c337 /* Remote phy nextpage 0 register */ 20862 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1 0x0000c338 /* Dig 4 Remote phy nextpage 1 register */ 20863 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2 0x0000c339 /* Dig 4 Remote phy nextpage 2 register */ 20864 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3 0x0000c33a /* Dig 4 Remote phy nextpage 3 register */ 20865 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4 0x0000c33b /* Dig 4 Remote phy nextpage 4 register */ 20866 #define PHY84328_SYS_DEV7_MISC3 0x0000c33c /* Dig 4 Miscellaneous 3 control register */ 20867 #define PHY84328_SYS_DEV7_MISC4 0x0000c33d /* Dig 4 Miscelaneous 4 control register */ 20868 #define PHY84328_SYS_DEV7_MISC5 0x0000c33e /* Dig 4 Miscelaneous 5 control register */ 20869 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB 0x0000c340 /* CL72 Link counter MSB [23:16] */ 20870 #define PHY84328_SYS_DEV7_LINKCNT_CL72_LSB 0x0000c341 /* CL72 Link counter LSB [15:0] */ 20871 #define PHY84328_SYS_DEV7_LP_UP4 0x0000c342 /* Link Partner's UP4 page */ 20872 #define PHY84328_SYS_DEV7_LP_UP5 0x0000c343 /* Link Partner's UP5 page */ 20873 #define PHY84328_SYS_DEV7_MISC6 0x0000c345 /* Misc6 */ 20874 #define PHY84328_SYS_DEV7_MISC7 0x0000c349 /* Misc7 */ 20875 #define PHY84328_SYS_DEV7_MISC8 0x0000c34a /* Misc8 */ 20876 #define PHY84328_SYS_DEV7_LINK_STATUS 0x0000c34d /* link_status */ 20877 #define PHY84328_SYS_DEV7_ACTUAL_SPEED 0x0000c34e /* Actual Speed status */ 20878 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL 0x0000c350 /* MP5, Message Page 5, next page control register */ 20879 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1 0x0000c351 /* sgmii & max timer offsets */ 20880 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2 0x0000c352 /* link up & link down timer offsets */ 20881 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3 0x0000c353 /* break link & next page link timer offsets */ 20882 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD 0x0000c354 /* 11 MSbits of the oui, oui[23:13] */ 20883 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD 0x0000c355 /* 11 middle bits of the oui, oui[12:2] */ 20884 #define PHY84328_SYS_DEV7_UD_FIELD 0x0000c357 /* User defined field of MP5 */ 20885 #define PHY84328_SYS_DEV7_LP_UD_FIELD 0x0000c35b /* Link partner's User defined field of MP5 */ 20886 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE 0x0000c35c /* sgmii_basepage */ 20887 #define PHY84328_SYS_DEV7_UP5 0x0000c35e /* AN local device user page 5 */ 20888 20889 20890 /**************************************************************************** 20891 * sys_device7_AN_Standard_Registers 20892 */ 20893 /**************************************************************************** 20894 * sys_device7 :: an_control_register 20895 */ 20896 /* sys_device7 :: an_control_register :: an_reset [15:15] */ 20897 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_AN_RESET_MASK 0x8000 20898 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_AN_RESET_ALIGN 0 20899 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_AN_RESET_BITS 1 20900 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_AN_RESET_SHIFT 15 20901 20902 /* sys_device7 :: an_control_register :: reserved0 [14:14] */ 20903 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED0_MASK 0x4000 20904 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED0_ALIGN 0 20905 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED0_BITS 1 20906 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED0_SHIFT 14 20907 20908 /* sys_device7 :: an_control_register :: extended_nextpage_control [13:13] */ 20909 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_EXTENDED_NEXTPAGE_CONTROL_MASK 0x2000 20910 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_EXTENDED_NEXTPAGE_CONTROL_ALIGN 0 20911 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_EXTENDED_NEXTPAGE_CONTROL_BITS 1 20912 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_EXTENDED_NEXTPAGE_CONTROL_SHIFT 13 20913 20914 /* sys_device7 :: an_control_register :: auto_negotiationenable [12:12] */ 20915 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_AUTO_NEGOTIATIONENABLE_MASK 0x1000 20916 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_AUTO_NEGOTIATIONENABLE_ALIGN 0 20917 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_AUTO_NEGOTIATIONENABLE_BITS 1 20918 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_AUTO_NEGOTIATIONENABLE_SHIFT 12 20919 20920 /* sys_device7 :: an_control_register :: reserved1 [11:10] */ 20921 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED1_MASK 0x0c00 20922 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED1_ALIGN 0 20923 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED1_BITS 2 20924 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED1_SHIFT 10 20925 20926 /* sys_device7 :: an_control_register :: restart_auto_negotiation [09:09] */ 20927 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESTART_AUTO_NEGOTIATION_MASK 0x0200 20928 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESTART_AUTO_NEGOTIATION_ALIGN 0 20929 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESTART_AUTO_NEGOTIATION_BITS 1 20930 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESTART_AUTO_NEGOTIATION_SHIFT 9 20931 20932 /* sys_device7 :: an_control_register :: reserved2 [08:00] */ 20933 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED2_MASK 0x01ff 20934 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED2_ALIGN 0 20935 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED2_BITS 9 20936 #define PHY84328_SYS_DEV7_AN_CONTROL_REGISTER_RESERVED2_SHIFT 0 20937 20938 20939 /**************************************************************************** 20940 * sys_device7 :: an_status_register 20941 */ 20942 /* sys_device7 :: an_status_register :: reserved0 [15:10] */ 20943 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED0_MASK 0xfc00 20944 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED0_ALIGN 0 20945 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED0_BITS 6 20946 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED0_SHIFT 10 20947 20948 /* sys_device7 :: an_status_register :: parallel_detection_fault [09:09] */ 20949 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_PARALLEL_DETECTION_FAULT_MASK 0x0200 20950 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_PARALLEL_DETECTION_FAULT_ALIGN 0 20951 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_PARALLEL_DETECTION_FAULT_BITS 1 20952 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_PARALLEL_DETECTION_FAULT_SHIFT 9 20953 20954 /* sys_device7 :: an_status_register :: reserved1 [08:08] */ 20955 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED1_MASK 0x0100 20956 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED1_ALIGN 0 20957 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED1_BITS 1 20958 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED1_SHIFT 8 20959 20960 /* sys_device7 :: an_status_register :: extended_next_pagestatus [07:07] */ 20961 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_EXTENDED_NEXT_PAGESTATUS_MASK 0x0080 20962 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_EXTENDED_NEXT_PAGESTATUS_ALIGN 0 20963 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_EXTENDED_NEXT_PAGESTATUS_BITS 1 20964 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_EXTENDED_NEXT_PAGESTATUS_SHIFT 7 20965 20966 /* sys_device7 :: an_status_register :: page_received [06:06] */ 20967 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_PAGE_RECEIVED_MASK 0x0040 20968 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_PAGE_RECEIVED_ALIGN 0 20969 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_PAGE_RECEIVED_BITS 1 20970 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_PAGE_RECEIVED_SHIFT 6 20971 20972 /* sys_device7 :: an_status_register :: auto_negotiationcomplete [05:05] */ 20973 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONCOMPLETE_MASK 0x0020 20974 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONCOMPLETE_ALIGN 0 20975 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONCOMPLETE_BITS 1 20976 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONCOMPLETE_SHIFT 5 20977 20978 /* sys_device7 :: an_status_register :: remote_fault [04:04] */ 20979 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_REMOTE_FAULT_MASK 0x0010 20980 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_REMOTE_FAULT_ALIGN 0 20981 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_REMOTE_FAULT_BITS 1 20982 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_REMOTE_FAULT_SHIFT 4 20983 20984 /* sys_device7 :: an_status_register :: auto_negotiationability [03:03] */ 20985 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONABILITY_MASK 0x0008 20986 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONABILITY_ALIGN 0 20987 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONABILITY_BITS 1 20988 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_AUTO_NEGOTIATIONABILITY_SHIFT 3 20989 20990 /* sys_device7 :: an_status_register :: link_status [02:02] */ 20991 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_LINK_STATUS_MASK 0x0004 20992 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_LINK_STATUS_ALIGN 0 20993 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_LINK_STATUS_BITS 1 20994 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_LINK_STATUS_SHIFT 2 20995 20996 /* sys_device7 :: an_status_register :: reserved2 [01:01] */ 20997 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED2_MASK 0x0002 20998 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED2_ALIGN 0 20999 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED2_BITS 1 21000 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_RESERVED2_SHIFT 1 21001 21002 /* sys_device7 :: an_status_register :: link_partner_auto_negotiationability [00:00] */ 21003 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_LINK_PARTNER_AUTO_NEGOTIATIONABILITY_MASK 0x0001 21004 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_LINK_PARTNER_AUTO_NEGOTIATIONABILITY_ALIGN 0 21005 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_LINK_PARTNER_AUTO_NEGOTIATIONABILITY_BITS 1 21006 #define PHY84328_SYS_DEV7_AN_STATUS_REGISTER_LINK_PARTNER_AUTO_NEGOTIATIONABILITY_SHIFT 0 21007 21008 21009 /**************************************************************************** 21010 * sys_device7 :: an_identifier_register_0 21011 */ 21012 /* sys_device7 :: an_identifier_register_0 :: device_id_0 [15:00] */ 21013 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_0_DEVICE_ID_0_MASK 0xffff 21014 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_0_DEVICE_ID_0_ALIGN 0 21015 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_0_DEVICE_ID_0_BITS 16 21016 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_0_DEVICE_ID_0_SHIFT 0 21017 21018 21019 /**************************************************************************** 21020 * sys_device7 :: an_identifier_register_1 21021 */ 21022 /* sys_device7 :: an_identifier_register_1 :: device_id_1 [15:00] */ 21023 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_1_DEVICE_ID_1_MASK 0xffff 21024 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_1_DEVICE_ID_1_ALIGN 0 21025 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_1_DEVICE_ID_1_BITS 16 21026 #define PHY84328_SYS_DEV7_AN_IDENTIFIER_REGISTER_1_DEVICE_ID_1_SHIFT 0 21027 21028 21029 /**************************************************************************** 21030 * sys_device7 :: an_oui_id0_register 21031 */ 21032 /* sys_device7 :: an_oui_id0_register :: device_id_0 [15:00] */ 21033 #define PHY84328_SYS_DEV7_AN_OUI_ID0_REGISTER_DEVICE_ID_0_MASK 0xffff 21034 #define PHY84328_SYS_DEV7_AN_OUI_ID0_REGISTER_DEVICE_ID_0_ALIGN 0 21035 #define PHY84328_SYS_DEV7_AN_OUI_ID0_REGISTER_DEVICE_ID_0_BITS 16 21036 #define PHY84328_SYS_DEV7_AN_OUI_ID0_REGISTER_DEVICE_ID_0_SHIFT 0 21037 21038 21039 /**************************************************************************** 21040 * sys_device7 :: an_oui_id1_reg 21041 */ 21042 /* sys_device7 :: an_oui_id1_reg :: device_id_1 [15:00] */ 21043 #define PHY84328_SYS_DEV7_AN_OUI_ID1_REG_DEVICE_ID_1_MASK 0xffff 21044 #define PHY84328_SYS_DEV7_AN_OUI_ID1_REG_DEVICE_ID_1_ALIGN 0 21045 #define PHY84328_SYS_DEV7_AN_OUI_ID1_REG_DEVICE_ID_1_BITS 16 21046 #define PHY84328_SYS_DEV7_AN_OUI_ID1_REG_DEVICE_ID_1_SHIFT 0 21047 21048 21049 /**************************************************************************** 21050 * sys_device7 :: an_advertisement_1_register 21051 */ 21052 /* sys_device7 :: an_advertisement_1_register :: next_page [15:15] */ 21053 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_MASK 0x8000 21054 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_ALIGN 0 21055 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_BITS 1 21056 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_SHIFT 15 21057 21058 /* sys_device7 :: an_advertisement_1_register :: acknowledge [14:14] */ 21059 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_MASK 0x4000 21060 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_ALIGN 0 21061 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_BITS 1 21062 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_SHIFT 14 21063 21064 /* sys_device7 :: an_advertisement_1_register :: remote_fault [13:13] */ 21065 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_MASK 0x2000 21066 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_ALIGN 0 21067 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_BITS 1 21068 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_SHIFT 13 21069 21070 /* sys_device7 :: an_advertisement_1_register :: pause [12:10] */ 21071 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_PAUSE_MASK 0x1c00 21072 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_PAUSE_ALIGN 0 21073 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_PAUSE_BITS 3 21074 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_PAUSE_SHIFT 10 21075 21076 /* sys_device7 :: an_advertisement_1_register :: echoed_nonce [09:05] */ 21077 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_MASK 0x03e0 21078 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_ALIGN 0 21079 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_BITS 5 21080 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_SHIFT 5 21081 21082 /* sys_device7 :: an_advertisement_1_register :: selector_field [04:00] */ 21083 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_MASK 0x001f 21084 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_ALIGN 0 21085 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_BITS 5 21086 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_SHIFT 0 21087 21088 21089 /**************************************************************************** 21090 * sys_device7 :: an_advertisement_2_register 21091 */ 21092 /* sys_device7 :: an_advertisement_2_register :: techAbility [15:05] */ 21093 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_MASK 0xffe0 21094 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_ALIGN 0 21095 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_BITS 11 21096 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_SHIFT 5 21097 21098 /* sys_device7 :: an_advertisement_2_register :: transmitted_nonce [04:00] */ 21099 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_MASK 0x001f 21100 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_ALIGN 0 21101 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_BITS 5 21102 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_SHIFT 0 21103 21104 21105 /**************************************************************************** 21106 * sys_device7 :: an_advertisement_3_register 21107 */ 21108 /* sys_device7 :: an_advertisement_3_register :: fec_requested [15:14] */ 21109 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_MASK 0xc000 21110 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_ALIGN 0 21111 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_BITS 2 21112 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_SHIFT 14 21113 21114 /* sys_device7 :: an_advertisement_3_register :: reserved0 [13:00] */ 21115 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER_RESERVED0_MASK 0x3fff 21116 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER_RESERVED0_ALIGN 0 21117 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER_RESERVED0_BITS 14 21118 #define PHY84328_SYS_DEV7_AN_ADVERTISEMENT_3_REGISTER_RESERVED0_SHIFT 0 21119 21120 21121 /**************************************************************************** 21122 * sys_device7 :: an_lp_base_page_ability_1_reg 21123 */ 21124 /* sys_device7 :: an_lp_base_page_ability_1_reg :: d15_d0 [15:00] */ 21125 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_MASK 0xffff 21126 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_ALIGN 0 21127 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_BITS 16 21128 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_SHIFT 0 21129 21130 21131 /**************************************************************************** 21132 * sys_device7 :: an_lp_base_page_ability_2_reg 21133 */ 21134 /* sys_device7 :: an_lp_base_page_ability_2_reg :: d31_16 [15:00] */ 21135 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_MASK 0xffff 21136 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_ALIGN 0 21137 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_BITS 16 21138 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_SHIFT 0 21139 21140 21141 /**************************************************************************** 21142 * sys_device7 :: an_lp_base_page_ability_3_reg 21143 */ 21144 /* sys_device7 :: an_lp_base_page_ability_3_reg :: d47_32 [15:00] */ 21145 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_MASK 0xffff 21146 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_ALIGN 0 21147 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_BITS 16 21148 #define PHY84328_SYS_DEV7_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_SHIFT 0 21149 21150 21151 /**************************************************************************** 21152 * sys_device7 :: an_xnp_transmit_1_register 21153 */ 21154 /* sys_device7 :: an_xnp_transmit_1_register :: next_page [15:15] */ 21155 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_MASK 0x8000 21156 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_ALIGN 0 21157 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_BITS 1 21158 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_SHIFT 15 21159 21160 /* sys_device7 :: an_xnp_transmit_1_register :: reserved0 [14:14] */ 21161 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_MASK 0x4000 21162 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_ALIGN 0 21163 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_BITS 1 21164 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_SHIFT 14 21165 21166 /* sys_device7 :: an_xnp_transmit_1_register :: message_page [13:13] */ 21167 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_MASK 0x2000 21168 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_ALIGN 0 21169 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_BITS 1 21170 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_SHIFT 13 21171 21172 /* sys_device7 :: an_xnp_transmit_1_register :: acknowledge_2 [12:12] */ 21173 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_MASK 0x1000 21174 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_ALIGN 0 21175 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_BITS 1 21176 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_SHIFT 12 21177 21178 /* sys_device7 :: an_xnp_transmit_1_register :: toggle [11:11] */ 21179 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_MASK 0x0800 21180 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_ALIGN 0 21181 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_BITS 1 21182 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_SHIFT 11 21183 21184 /* sys_device7 :: an_xnp_transmit_1_register :: message_unformatedcode_field [10:00] */ 21185 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_MASK 0x07ff 21186 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_ALIGN 0 21187 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_BITS 11 21188 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_SHIFT 0 21189 21190 21191 /**************************************************************************** 21192 * sys_device7 :: an_xnp_transmit_2_register 21193 */ 21194 /* sys_device7 :: an_xnp_transmit_2_register :: unformated_codefield_1 [15:00] */ 21195 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_MASK 0xffff 21196 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_ALIGN 0 21197 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_BITS 16 21198 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_SHIFT 0 21199 21200 21201 /**************************************************************************** 21202 * sys_device7 :: an_xnp_transmit_3_register 21203 */ 21204 /* sys_device7 :: an_xnp_transmit_3_register :: unformated_codefield_3 [15:00] */ 21205 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_MASK 0xffff 21206 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_ALIGN 0 21207 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_BITS 16 21208 #define PHY84328_SYS_DEV7_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_SHIFT 0 21209 21210 21211 /**************************************************************************** 21212 * sys_device7 :: an_lp_xnp_transmit_1_register 21213 */ 21214 /* sys_device7 :: an_lp_xnp_transmit_1_register :: next_page [15:15] */ 21215 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_MASK 0x8000 21216 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_ALIGN 0 21217 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_BITS 1 21218 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_SHIFT 15 21219 21220 /* sys_device7 :: an_lp_xnp_transmit_1_register :: acknowledge [14:14] */ 21221 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_MASK 0x4000 21222 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_ALIGN 0 21223 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_BITS 1 21224 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_SHIFT 14 21225 21226 /* sys_device7 :: an_lp_xnp_transmit_1_register :: message_page [13:13] */ 21227 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_MASK 0x2000 21228 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_ALIGN 0 21229 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_BITS 1 21230 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_SHIFT 13 21231 21232 /* sys_device7 :: an_lp_xnp_transmit_1_register :: acknowledge_2 [12:12] */ 21233 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_MASK 0x1000 21234 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_ALIGN 0 21235 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_BITS 1 21236 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_SHIFT 12 21237 21238 /* sys_device7 :: an_lp_xnp_transmit_1_register :: toggle [11:11] */ 21239 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_MASK 0x0800 21240 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_ALIGN 0 21241 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_BITS 1 21242 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_SHIFT 11 21243 21244 /* sys_device7 :: an_lp_xnp_transmit_1_register :: message_unformatedcode_field [10:00] */ 21245 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_MASK 0x07ff 21246 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_ALIGN 0 21247 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_BITS 11 21248 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_SHIFT 0 21249 21250 21251 /**************************************************************************** 21252 * sys_device7 :: an_lp_xnp_transmit_2_register 21253 */ 21254 /* sys_device7 :: an_lp_xnp_transmit_2_register :: unformated_codefield_1 [15:00] */ 21255 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_MASK 0xffff 21256 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_ALIGN 0 21257 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_BITS 16 21258 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_SHIFT 0 21259 21260 21261 /**************************************************************************** 21262 * sys_device7 :: an_lp_xnp_transmit_3_register 21263 */ 21264 /* sys_device7 :: an_lp_xnp_transmit_3_register :: unformated_codefield_3 [15:00] */ 21265 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_MASK 0xffff 21266 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_ALIGN 0 21267 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_BITS 16 21268 #define PHY84328_SYS_DEV7_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_SHIFT 0 21269 21270 21271 /**************************************************************************** 21272 * sys_device7 :: backplane_ethernet_status_register 21273 */ 21274 /* sys_device7 :: backplane_ethernet_status_register :: reserved0 [15:07] */ 21275 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_MASK 0xff80 21276 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_ALIGN 0 21277 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_BITS 9 21278 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_SHIFT 7 21279 21280 /* sys_device7 :: backplane_ethernet_status_register :: fortygbase_cr4 [06:06] */ 21281 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_MASK 0x0040 21282 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_ALIGN 0 21283 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_BITS 1 21284 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_SHIFT 6 21285 21286 /* sys_device7 :: backplane_ethernet_status_register :: fortygbase_kr [05:05] */ 21287 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR_MASK 0x0020 21288 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR_ALIGN 0 21289 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR_BITS 1 21290 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR_SHIFT 5 21291 21292 /* sys_device7 :: backplane_ethernet_status_register :: tengbase_kr_fecnegotiated [04:04] */ 21293 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_FECNEGOTIATED_MASK 0x0010 21294 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_FECNEGOTIATED_ALIGN 0 21295 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_FECNEGOTIATED_BITS 1 21296 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_FECNEGOTIATED_SHIFT 4 21297 21298 /* sys_device7 :: backplane_ethernet_status_register :: tengbase_kr [03:03] */ 21299 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_MASK 0x0008 21300 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_ALIGN 0 21301 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_BITS 1 21302 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_SHIFT 3 21303 21304 /* sys_device7 :: backplane_ethernet_status_register :: tengbase_kx4 [02:02] */ 21305 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_MASK 0x0004 21306 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_ALIGN 0 21307 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_BITS 1 21308 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_SHIFT 2 21309 21310 /* sys_device7 :: backplane_ethernet_status_register :: gigbase_kx [01:01] */ 21311 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_MASK 0x0002 21312 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_ALIGN 0 21313 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_BITS 1 21314 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_SHIFT 1 21315 21316 /* sys_device7 :: backplane_ethernet_status_register :: bp_an_ability [00:00] */ 21317 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_MASK 0x0001 21318 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_ALIGN 0 21319 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_BITS 1 21320 #define PHY84328_SYS_DEV7_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_SHIFT 0 21321 21322 21323 /**************************************************************************** 21324 * sys_device7 :: EEE_adv 21325 */ 21326 /* sys_device7 :: EEE_adv :: reserved0 [15:07] */ 21327 #define PHY84328_SYS_DEV7_EEE_ADV_RESERVED0_MASK 0xff80 21328 #define PHY84328_SYS_DEV7_EEE_ADV_RESERVED0_ALIGN 0 21329 #define PHY84328_SYS_DEV7_EEE_ADV_RESERVED0_BITS 9 21330 #define PHY84328_SYS_DEV7_EEE_ADV_RESERVED0_SHIFT 7 21331 21332 /* sys_device7 :: EEE_adv :: EEE_10G_KR [06:06] */ 21333 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_10G_KR_MASK 0x0040 21334 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_10G_KR_ALIGN 0 21335 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_10G_KR_BITS 1 21336 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_10G_KR_SHIFT 6 21337 21338 /* sys_device7 :: EEE_adv :: EEE_10G_KX4 [05:05] */ 21339 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_10G_KX4_MASK 0x0020 21340 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_10G_KX4_ALIGN 0 21341 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_10G_KX4_BITS 1 21342 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_10G_KX4_SHIFT 5 21343 21344 /* sys_device7 :: EEE_adv :: EEE_1G_KX [04:04] */ 21345 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_1G_KX_MASK 0x0010 21346 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_1G_KX_ALIGN 0 21347 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_1G_KX_BITS 1 21348 #define PHY84328_SYS_DEV7_EEE_ADV_EEE_1G_KX_SHIFT 4 21349 21350 /* sys_device7 :: EEE_adv :: reserved1 [03:00] */ 21351 #define PHY84328_SYS_DEV7_EEE_ADV_RESERVED1_MASK 0x000f 21352 #define PHY84328_SYS_DEV7_EEE_ADV_RESERVED1_ALIGN 0 21353 #define PHY84328_SYS_DEV7_EEE_ADV_RESERVED1_BITS 4 21354 #define PHY84328_SYS_DEV7_EEE_ADV_RESERVED1_SHIFT 0 21355 21356 21357 /**************************************************************************** 21358 * sys_device7 :: EEE_lp_adv 21359 */ 21360 /* sys_device7 :: EEE_lp_adv :: reserved0 [15:07] */ 21361 #define PHY84328_SYS_DEV7_EEE_LP_ADV_RESERVED0_MASK 0xff80 21362 #define PHY84328_SYS_DEV7_EEE_LP_ADV_RESERVED0_ALIGN 0 21363 #define PHY84328_SYS_DEV7_EEE_LP_ADV_RESERVED0_BITS 9 21364 #define PHY84328_SYS_DEV7_EEE_LP_ADV_RESERVED0_SHIFT 7 21365 21366 /* sys_device7 :: EEE_lp_adv :: EEE_10G_KR [06:06] */ 21367 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_10G_KR_MASK 0x0040 21368 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_10G_KR_ALIGN 0 21369 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_10G_KR_BITS 1 21370 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_10G_KR_SHIFT 6 21371 21372 /* sys_device7 :: EEE_lp_adv :: EEE_10G_KX4 [05:05] */ 21373 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_10G_KX4_MASK 0x0020 21374 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_10G_KX4_ALIGN 0 21375 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_10G_KX4_BITS 1 21376 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_10G_KX4_SHIFT 5 21377 21378 /* sys_device7 :: EEE_lp_adv :: EEE_1G_KX [04:04] */ 21379 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_1G_KX_MASK 0x0010 21380 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_1G_KX_ALIGN 0 21381 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_1G_KX_BITS 1 21382 #define PHY84328_SYS_DEV7_EEE_LP_ADV_EEE_1G_KX_SHIFT 4 21383 21384 /* sys_device7 :: EEE_lp_adv :: reserved1 [03:00] */ 21385 #define PHY84328_SYS_DEV7_EEE_LP_ADV_RESERVED1_MASK 0x000f 21386 #define PHY84328_SYS_DEV7_EEE_LP_ADV_RESERVED1_ALIGN 0 21387 #define PHY84328_SYS_DEV7_EEE_LP_ADV_RESERVED1_BITS 4 21388 #define PHY84328_SYS_DEV7_EEE_LP_ADV_RESERVED1_SHIFT 0 21389 21390 21391 /**************************************************************************** 21392 * sys_device7_cl73_userb0 21393 */ 21394 /**************************************************************************** 21395 * sys_device7 :: CL73_UCtrl1 21396 */ 21397 /* sys_device7 :: CL73_UCtrl1 :: cl73_fast_timers [15:15] */ 21398 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_FAST_TIMERS_MASK 0x8000 21399 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_FAST_TIMERS_ALIGN 0 21400 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_FAST_TIMERS_BITS 1 21401 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_FAST_TIMERS_SHIFT 15 21402 21403 /* sys_device7 :: CL73_UCtrl1 :: txDisableBam_en_over [14:14] */ 21404 #define PHY84328_SYS_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_OVER_MASK 0x4000 21405 #define PHY84328_SYS_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_OVER_ALIGN 0 21406 #define PHY84328_SYS_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_OVER_BITS 1 21407 #define PHY84328_SYS_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_OVER_SHIFT 14 21408 21409 /* sys_device7 :: CL73_UCtrl1 :: txDisableBam_en_val [13:13] */ 21410 #define PHY84328_SYS_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_VAL_MASK 0x2000 21411 #define PHY84328_SYS_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_VAL_ALIGN 0 21412 #define PHY84328_SYS_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_VAL_BITS 1 21413 #define PHY84328_SYS_DEV7_CL73_UCTRL1_TXDISABLEBAM_EN_VAL_SHIFT 13 21414 21415 /* sys_device7 :: CL73_UCtrl1 :: cl73_lossOfSyncFail_en [12:12] */ 21416 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_MASK 0x1000 21417 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_ALIGN 0 21418 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_BITS 1 21419 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_SHIFT 12 21420 21421 /* sys_device7 :: CL73_UCtrl1 :: cl73_parDet_dis [11:11] */ 21422 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_PARDET_DIS_MASK 0x0800 21423 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_PARDET_DIS_ALIGN 0 21424 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_PARDET_DIS_BITS 1 21425 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_PARDET_DIS_SHIFT 11 21426 21427 /* sys_device7 :: CL73_UCtrl1 :: cl73_allowCl37AN [10:10] */ 21428 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_ALLOWCL37AN_MASK 0x0400 21429 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_ALLOWCL37AN_ALIGN 0 21430 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_ALLOWCL37AN_BITS 1 21431 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_ALLOWCL37AN_SHIFT 10 21432 21433 /* sys_device7 :: CL73_UCtrl1 :: longParDetTimer_dis [09:09] */ 21434 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LONGPARDETTIMER_DIS_MASK 0x0200 21435 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LONGPARDETTIMER_DIS_ALIGN 0 21436 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LONGPARDETTIMER_DIS_BITS 1 21437 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LONGPARDETTIMER_DIS_SHIFT 9 21438 21439 /* sys_device7 :: CL73_UCtrl1 :: linkFailTimer_dis [08:08] */ 21440 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LINKFAILTIMER_DIS_MASK 0x0100 21441 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LINKFAILTIMER_DIS_ALIGN 0 21442 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LINKFAILTIMER_DIS_BITS 1 21443 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LINKFAILTIMER_DIS_SHIFT 8 21444 21445 /* sys_device7 :: CL73_UCtrl1 :: linkFailTimerQual_en [07:07] */ 21446 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_MASK 0x0080 21447 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_ALIGN 0 21448 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_BITS 1 21449 #define PHY84328_SYS_DEV7_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_SHIFT 7 21450 21451 /* sys_device7 :: CL73_UCtrl1 :: cl73_nonce_match_over [06:06] */ 21452 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK 0x0040 21453 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN 0 21454 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS 1 21455 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT 6 21456 21457 /* sys_device7 :: CL73_UCtrl1 :: cl73_nonce_match_val [05:05] */ 21458 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK 0x0020 21459 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN 0 21460 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS 1 21461 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT 5 21462 21463 /* sys_device7 :: CL73_UCtrl1 :: couple_w_cl73_restart_wo_link_fail [04:04] */ 21464 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_MASK 0x0010 21465 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_ALIGN 0 21466 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_BITS 1 21467 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_SHIFT 4 21468 21469 /* sys_device7 :: CL73_UCtrl1 :: couple_w_cl73_restart [03:03] */ 21470 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_MASK 0x0008 21471 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_ALIGN 0 21472 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_BITS 1 21473 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL73_RESTART_SHIFT 3 21474 21475 /* sys_device7 :: CL73_UCtrl1 :: couple_w_cl37_restart [02:02] */ 21476 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL37_RESTART_MASK 0x0004 21477 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL37_RESTART_ALIGN 0 21478 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL37_RESTART_BITS 1 21479 #define PHY84328_SYS_DEV7_CL73_UCTRL1_COUPLE_W_CL37_RESTART_SHIFT 2 21480 21481 /* sys_device7 :: CL73_UCtrl1 :: CL73_UStat1_muxsel [01:01] */ 21482 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_USTAT1_MUXSEL_MASK 0x0002 21483 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_USTAT1_MUXSEL_ALIGN 0 21484 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_USTAT1_MUXSEL_BITS 1 21485 #define PHY84328_SYS_DEV7_CL73_UCTRL1_CL73_USTAT1_MUXSEL_SHIFT 1 21486 21487 /* sys_device7 :: CL73_UCtrl1 :: force_cl73_tx_omux_en [00:00] */ 21488 #define PHY84328_SYS_DEV7_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_MASK 0x0001 21489 #define PHY84328_SYS_DEV7_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_ALIGN 0 21490 #define PHY84328_SYS_DEV7_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_BITS 1 21491 #define PHY84328_SYS_DEV7_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_SHIFT 0 21492 21493 21494 /**************************************************************************** 21495 * sys_device7 :: CL73_UStat1 21496 */ 21497 /* sys_device7 :: CL73_UStat1 :: reserved0 [15:10] */ 21498 #define PHY84328_SYS_DEV7_CL73_USTAT1_RESERVED0_MASK 0xfc00 21499 #define PHY84328_SYS_DEV7_CL73_USTAT1_RESERVED0_ALIGN 0 21500 #define PHY84328_SYS_DEV7_CL73_USTAT1_RESERVED0_BITS 6 21501 #define PHY84328_SYS_DEV7_CL73_USTAT1_RESERVED0_SHIFT 10 21502 21503 /* sys_device7 :: CL73_UStat1 :: arb_fsm [09:00] */ 21504 #define PHY84328_SYS_DEV7_CL73_USTAT1_ARB_FSM_MASK 0x03ff 21505 #define PHY84328_SYS_DEV7_CL73_USTAT1_ARB_FSM_ALIGN 0 21506 #define PHY84328_SYS_DEV7_CL73_USTAT1_ARB_FSM_BITS 10 21507 #define PHY84328_SYS_DEV7_CL73_USTAT1_ARB_FSM_SHIFT 0 21508 21509 21510 /**************************************************************************** 21511 * sys_device7 :: CL73_BAMCtrl1 21512 */ 21513 /* sys_device7 :: CL73_BAMCtrl1 :: CL73_bamEn [15:15] */ 21514 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAMEN_MASK 0x8000 21515 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAMEN_ALIGN 0 21516 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAMEN_BITS 1 21517 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAMEN_SHIFT 15 21518 21519 /* sys_device7 :: CL73_BAMCtrl1 :: CL73_bam_station_mngr_en [14:14] */ 21520 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_MASK 0x4000 21521 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_ALIGN 0 21522 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_BITS 1 21523 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_SHIFT 14 21524 21525 /* sys_device7 :: CL73_BAMCtrl1 :: CL73_bamNP_after_bp_en [13:13] */ 21526 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_MASK 0x2000 21527 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_ALIGN 0 21528 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_BITS 1 21529 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_SHIFT 13 21530 21531 /* sys_device7 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_en [12:12] */ 21532 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_MASK 0x1000 21533 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_ALIGN 0 21534 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_BITS 1 21535 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_SHIFT 12 21536 21537 /* sys_device7 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_step [11:11] */ 21538 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_MASK 0x0800 21539 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_ALIGN 0 21540 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_BITS 1 21541 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_SHIFT 11 21542 21543 /* sys_device7 :: CL73_BAMCtrl1 :: reserved0 [10:10] */ 21544 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_RESERVED0_MASK 0x0400 21545 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_RESERVED0_ALIGN 0 21546 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_RESERVED0_BITS 1 21547 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_RESERVED0_SHIFT 10 21548 21549 /* sys_device7 :: CL73_BAMCtrl1 :: UD_code_field_41_32 [09:00] */ 21550 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_UD_CODE_FIELD_41_32_MASK 0x03ff 21551 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_UD_CODE_FIELD_41_32_ALIGN 0 21552 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_UD_CODE_FIELD_41_32_BITS 10 21553 #define PHY84328_SYS_DEV7_CL73_BAMCTRL1_UD_CODE_FIELD_41_32_SHIFT 0 21554 21555 21556 /**************************************************************************** 21557 * sys_device7 :: CL73_BAMCtrl2 21558 */ 21559 /* sys_device7 :: CL73_BAMCtrl2 :: UD_code_field_31_16 [15:00] */ 21560 #define PHY84328_SYS_DEV7_CL73_BAMCTRL2_UD_CODE_FIELD_31_16_MASK 0xffff 21561 #define PHY84328_SYS_DEV7_CL73_BAMCTRL2_UD_CODE_FIELD_31_16_ALIGN 0 21562 #define PHY84328_SYS_DEV7_CL73_BAMCTRL2_UD_CODE_FIELD_31_16_BITS 16 21563 #define PHY84328_SYS_DEV7_CL73_BAMCTRL2_UD_CODE_FIELD_31_16_SHIFT 0 21564 21565 21566 /**************************************************************************** 21567 * sys_device7 :: CL73_BAMCtrl3 21568 */ 21569 /* sys_device7 :: CL73_BAMCtrl3 :: UD_code_field_15_0 [15:00] */ 21570 #define PHY84328_SYS_DEV7_CL73_BAMCTRL3_UD_CODE_FIELD_15_0_MASK 0xffff 21571 #define PHY84328_SYS_DEV7_CL73_BAMCTRL3_UD_CODE_FIELD_15_0_ALIGN 0 21572 #define PHY84328_SYS_DEV7_CL73_BAMCTRL3_UD_CODE_FIELD_15_0_BITS 16 21573 #define PHY84328_SYS_DEV7_CL73_BAMCTRL3_UD_CODE_FIELD_15_0_SHIFT 0 21574 21575 21576 /**************************************************************************** 21577 * sys_device7 :: CL73_BAMStat1 21578 */ 21579 /* sys_device7 :: CL73_BAMStat1 :: reserved0 [15:10] */ 21580 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1_RESERVED0_MASK 0xfc00 21581 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1_RESERVED0_ALIGN 0 21582 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1_RESERVED0_BITS 6 21583 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1_RESERVED0_SHIFT 10 21584 21585 /* sys_device7 :: CL73_BAMStat1 :: LP_UD_code_field_41_32 [09:00] */ 21586 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1_LP_UD_CODE_FIELD_41_32_MASK 0x03ff 21587 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1_LP_UD_CODE_FIELD_41_32_ALIGN 0 21588 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1_LP_UD_CODE_FIELD_41_32_BITS 10 21589 #define PHY84328_SYS_DEV7_CL73_BAMSTAT1_LP_UD_CODE_FIELD_41_32_SHIFT 0 21590 21591 21592 /**************************************************************************** 21593 * sys_device7 :: CL73_BAMStat2 21594 */ 21595 /* sys_device7 :: CL73_BAMStat2 :: LP_UD_code_field_31_16 [15:00] */ 21596 #define PHY84328_SYS_DEV7_CL73_BAMSTAT2_LP_UD_CODE_FIELD_31_16_MASK 0xffff 21597 #define PHY84328_SYS_DEV7_CL73_BAMSTAT2_LP_UD_CODE_FIELD_31_16_ALIGN 0 21598 #define PHY84328_SYS_DEV7_CL73_BAMSTAT2_LP_UD_CODE_FIELD_31_16_BITS 16 21599 #define PHY84328_SYS_DEV7_CL73_BAMSTAT2_LP_UD_CODE_FIELD_31_16_SHIFT 0 21600 21601 21602 /**************************************************************************** 21603 * sys_device7 :: CL73_BAMStat3 21604 */ 21605 /* sys_device7 :: CL73_BAMStat3 :: LP_UD_code_field_15_0 [15:00] */ 21606 #define PHY84328_SYS_DEV7_CL73_BAMSTAT3_LP_UD_CODE_FIELD_15_0_MASK 0xffff 21607 #define PHY84328_SYS_DEV7_CL73_BAMSTAT3_LP_UD_CODE_FIELD_15_0_ALIGN 0 21608 #define PHY84328_SYS_DEV7_CL73_BAMSTAT3_LP_UD_CODE_FIELD_15_0_BITS 16 21609 #define PHY84328_SYS_DEV7_CL73_BAMSTAT3_LP_UD_CODE_FIELD_15_0_SHIFT 0 21610 21611 21612 /**************************************************************************** 21613 * sys_device7 :: CL73_UCtrl2 21614 */ 21615 /* sys_device7 :: CL73_UCtrl2 :: reserved0 [15:15] */ 21616 #define PHY84328_SYS_DEV7_CL73_UCTRL2_RESERVED0_MASK 0x8000 21617 #define PHY84328_SYS_DEV7_CL73_UCTRL2_RESERVED0_ALIGN 0 21618 #define PHY84328_SYS_DEV7_CL73_UCTRL2_RESERVED0_BITS 1 21619 #define PHY84328_SYS_DEV7_CL73_UCTRL2_RESERVED0_SHIFT 15 21620 21621 /* sys_device7 :: CL73_UCtrl2 :: Disable_Wait4_DME_RxSeqDone_4_AN_START [14:14] */ 21622 #define PHY84328_SYS_DEV7_CL73_UCTRL2_DISABLE_WAIT4_DME_RXSEQDONE_4_AN_START_MASK 0x4000 21623 #define PHY84328_SYS_DEV7_CL73_UCTRL2_DISABLE_WAIT4_DME_RXSEQDONE_4_AN_START_ALIGN 0 21624 #define PHY84328_SYS_DEV7_CL73_UCTRL2_DISABLE_WAIT4_DME_RXSEQDONE_4_AN_START_BITS 1 21625 #define PHY84328_SYS_DEV7_CL73_UCTRL2_DISABLE_WAIT4_DME_RXSEQDONE_4_AN_START_SHIFT 14 21626 21627 /* sys_device7 :: CL73_UCtrl2 :: an_good_trap [13:13] */ 21628 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_TRAP_MASK 0x2000 21629 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_TRAP_ALIGN 0 21630 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_TRAP_BITS 1 21631 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_TRAP_SHIFT 13 21632 21633 /* sys_device7 :: CL73_UCtrl2 :: an_good_checkTrap [12:12] */ 21634 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_CHECKTRAP_MASK 0x1000 21635 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_CHECKTRAP_ALIGN 0 21636 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_CHECKTRAP_BITS 1 21637 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_CHECKTRAP_SHIFT 12 21638 21639 /* sys_device7 :: CL73_UCtrl2 :: uselink [11:11] */ 21640 #define PHY84328_SYS_DEV7_CL73_UCTRL2_USELINK_MASK 0x0800 21641 #define PHY84328_SYS_DEV7_CL73_UCTRL2_USELINK_ALIGN 0 21642 #define PHY84328_SYS_DEV7_CL73_UCTRL2_USELINK_BITS 1 21643 #define PHY84328_SYS_DEV7_CL73_UCTRL2_USELINK_SHIFT 11 21644 21645 /* sys_device7 :: CL73_UCtrl2 :: rx_dme_status_sel [10:09] */ 21646 #define PHY84328_SYS_DEV7_CL73_UCTRL2_RX_DME_STATUS_SEL_MASK 0x0600 21647 #define PHY84328_SYS_DEV7_CL73_UCTRL2_RX_DME_STATUS_SEL_ALIGN 0 21648 #define PHY84328_SYS_DEV7_CL73_UCTRL2_RX_DME_STATUS_SEL_BITS 2 21649 #define PHY84328_SYS_DEV7_CL73_UCTRL2_RX_DME_STATUS_SEL_SHIFT 9 21650 21651 /* sys_device7 :: CL73_UCtrl2 :: cl73_suppress_mr_page_rx_dis [08:08] */ 21652 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_MASK 0x0100 21653 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_ALIGN 0 21654 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_BITS 1 21655 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_SUPPRESS_MR_PAGE_RX_DIS_SHIFT 8 21656 21657 /* sys_device7 :: CL73_UCtrl2 :: cl73_record_2NP_after_BP_en [07:07] */ 21658 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_MASK 0x0080 21659 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_ALIGN 0 21660 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_BITS 1 21661 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_RECORD_2NP_AFTER_BP_EN_SHIFT 7 21662 21663 /* sys_device7 :: CL73_UCtrl2 :: cl73_BAMStat123_sel [06:04] */ 21664 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_BAMSTAT123_SEL_MASK 0x0070 21665 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_BAMSTAT123_SEL_ALIGN 0 21666 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_BAMSTAT123_SEL_BITS 3 21667 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CL73_BAMSTAT123_SEL_SHIFT 4 21668 21669 /* sys_device7 :: CL73_UCtrl2 :: sigdet_timer_dis [03:03] */ 21670 #define PHY84328_SYS_DEV7_CL73_UCTRL2_SIGDET_TIMER_DIS_MASK 0x0008 21671 #define PHY84328_SYS_DEV7_CL73_UCTRL2_SIGDET_TIMER_DIS_ALIGN 0 21672 #define PHY84328_SYS_DEV7_CL73_UCTRL2_SIGDET_TIMER_DIS_BITS 1 21673 #define PHY84328_SYS_DEV7_CL73_UCTRL2_SIGDET_TIMER_DIS_SHIFT 3 21674 21675 /* sys_device7 :: CL73_UCtrl2 :: an_good_check_bam37_dis [02:02] */ 21676 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_MASK 0x0004 21677 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_ALIGN 0 21678 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_BITS 1 21679 #define PHY84328_SYS_DEV7_CL73_UCTRL2_AN_GOOD_CHECK_BAM37_DIS_SHIFT 2 21680 21681 /* sys_device7 :: CL73_UCtrl2 :: config_match_dis [01:01] */ 21682 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CONFIG_MATCH_DIS_MASK 0x0002 21683 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CONFIG_MATCH_DIS_ALIGN 0 21684 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CONFIG_MATCH_DIS_BITS 1 21685 #define PHY84328_SYS_DEV7_CL73_UCTRL2_CONFIG_MATCH_DIS_SHIFT 1 21686 21687 /* sys_device7 :: CL73_UCtrl2 :: hold_lp_ability [00:00] */ 21688 #define PHY84328_SYS_DEV7_CL73_UCTRL2_HOLD_LP_ABILITY_MASK 0x0001 21689 #define PHY84328_SYS_DEV7_CL73_UCTRL2_HOLD_LP_ABILITY_ALIGN 0 21690 #define PHY84328_SYS_DEV7_CL73_UCTRL2_HOLD_LP_ABILITY_BITS 1 21691 #define PHY84328_SYS_DEV7_CL73_UCTRL2_HOLD_LP_ABILITY_SHIFT 0 21692 21693 21694 /**************************************************************************** 21695 * sys_device7 :: CL73_EEECtrl_type 21696 */ 21697 /* sys_device7 :: CL73_EEECtrl_type :: CL73_eeeEn [15:15] */ 21698 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_CL73_EEEEN_MASK 0x8000 21699 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_CL73_EEEEN_ALIGN 0 21700 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_CL73_EEEEN_BITS 1 21701 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_CL73_EEEEN_SHIFT 15 21702 21703 /* sys_device7 :: CL73_EEECtrl_type :: CL73_eeeNP_after_bp_en [14:14] */ 21704 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_CL73_EEENP_AFTER_BP_EN_MASK 0x4000 21705 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_CL73_EEENP_AFTER_BP_EN_ALIGN 0 21706 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_CL73_EEENP_AFTER_BP_EN_BITS 1 21707 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_CL73_EEENP_AFTER_BP_EN_SHIFT 14 21708 21709 /* sys_device7 :: CL73_EEECtrl_type :: hold_eee_lp_ability [13:13] */ 21710 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_HOLD_EEE_LP_ABILITY_MASK 0x2000 21711 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_HOLD_EEE_LP_ABILITY_ALIGN 0 21712 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_HOLD_EEE_LP_ABILITY_BITS 1 21713 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_HOLD_EEE_LP_ABILITY_SHIFT 13 21714 21715 /* sys_device7 :: CL73_EEECtrl_type :: reserved0 [12:00] */ 21716 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_RESERVED0_MASK 0x1fff 21717 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_RESERVED0_ALIGN 0 21718 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_RESERVED0_BITS 13 21719 #define PHY84328_SYS_DEV7_CL73_EEECTRL_TYPE_RESERVED0_SHIFT 0 21720 21721 21722 /**************************************************************************** 21723 * sys_device7_gp_status 21724 */ 21725 /**************************************************************************** 21726 * sys_device7 :: miscrxstatus 21727 */ 21728 /* sys_device7 :: miscrxstatus :: capture_NP_lh [15:15] */ 21729 #define PHY84328_SYS_DEV7_MISCRXSTATUS_CAPTURE_NP_LH_MASK 0x8000 21730 #define PHY84328_SYS_DEV7_MISCRXSTATUS_CAPTURE_NP_LH_ALIGN 0 21731 #define PHY84328_SYS_DEV7_MISCRXSTATUS_CAPTURE_NP_LH_BITS 1 21732 #define PHY84328_SYS_DEV7_MISCRXSTATUS_CAPTURE_NP_LH_SHIFT 15 21733 21734 /* sys_device7 :: miscrxstatus :: teton_brk_link_lh [14:14] */ 21735 #define PHY84328_SYS_DEV7_MISCRXSTATUS_TETON_BRK_LINK_LH_MASK 0x4000 21736 #define PHY84328_SYS_DEV7_MISCRXSTATUS_TETON_BRK_LINK_LH_ALIGN 0 21737 #define PHY84328_SYS_DEV7_MISCRXSTATUS_TETON_BRK_LINK_LH_BITS 1 21738 #define PHY84328_SYS_DEV7_MISCRXSTATUS_TETON_BRK_LINK_LH_SHIFT 14 21739 21740 /* sys_device7 :: miscrxstatus :: UP3_lh [13:13] */ 21741 #define PHY84328_SYS_DEV7_MISCRXSTATUS_UP3_LH_MASK 0x2000 21742 #define PHY84328_SYS_DEV7_MISCRXSTATUS_UP3_LH_ALIGN 0 21743 #define PHY84328_SYS_DEV7_MISCRXSTATUS_UP3_LH_BITS 1 21744 #define PHY84328_SYS_DEV7_MISCRXSTATUS_UP3_LH_SHIFT 13 21745 21746 /* sys_device7 :: miscrxstatus :: MP5_lh [12:12] */ 21747 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MP5_LH_MASK 0x1000 21748 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MP5_LH_ALIGN 0 21749 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MP5_LH_BITS 1 21750 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MP5_LH_SHIFT 12 21751 21752 /* sys_device7 :: miscrxstatus :: nonMatchingOUI_lh [11:11] */ 21753 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NONMATCHINGOUI_LH_MASK 0x0800 21754 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NONMATCHINGOUI_LH_ALIGN 0 21755 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NONMATCHINGOUI_LH_BITS 1 21756 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NONMATCHINGOUI_LH_SHIFT 11 21757 21758 /* sys_device7 :: miscrxstatus :: matchingOUI_msb_lh [10:10] */ 21759 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MATCHINGOUI_MSB_LH_MASK 0x0400 21760 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MATCHINGOUI_MSB_LH_ALIGN 0 21761 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MATCHINGOUI_MSB_LH_BITS 1 21762 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MATCHINGOUI_MSB_LH_SHIFT 10 21763 21764 /* sys_device7 :: miscrxstatus :: matchingOUI_lsb_lh [09:09] */ 21765 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MATCHINGOUI_LSB_LH_MASK 0x0200 21766 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MATCHINGOUI_LSB_LH_ALIGN 0 21767 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MATCHINGOUI_LSB_LH_BITS 1 21768 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MATCHINGOUI_LSB_LH_SHIFT 9 21769 21770 /* sys_device7 :: miscrxstatus :: invalidSeq_lh [08:08] */ 21771 #define PHY84328_SYS_DEV7_MISCRXSTATUS_INVALIDSEQ_LH_MASK 0x0100 21772 #define PHY84328_SYS_DEV7_MISCRXSTATUS_INVALIDSEQ_LH_ALIGN 0 21773 #define PHY84328_SYS_DEV7_MISCRXSTATUS_INVALIDSEQ_LH_BITS 1 21774 #define PHY84328_SYS_DEV7_MISCRXSTATUS_INVALIDSEQ_LH_SHIFT 8 21775 21776 /* sys_device7 :: miscrxstatus :: nullMP_lh [07:07] */ 21777 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NULLMP_LH_MASK 0x0080 21778 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NULLMP_LH_ALIGN 0 21779 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NULLMP_LH_BITS 1 21780 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NULLMP_LH_SHIFT 7 21781 21782 /* sys_device7 :: miscrxstatus :: remotePhyMP_lh [06:06] */ 21783 #define PHY84328_SYS_DEV7_MISCRXSTATUS_REMOTEPHYMP_LH_MASK 0x0040 21784 #define PHY84328_SYS_DEV7_MISCRXSTATUS_REMOTEPHYMP_LH_ALIGN 0 21785 #define PHY84328_SYS_DEV7_MISCRXSTATUS_REMOTEPHYMP_LH_BITS 1 21786 #define PHY84328_SYS_DEV7_MISCRXSTATUS_REMOTEPHYMP_LH_SHIFT 6 21787 21788 /* sys_device7 :: miscrxstatus :: nonMatchingMP_lh [05:05] */ 21789 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NONMATCHINGMP_LH_MASK 0x0020 21790 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NONMATCHINGMP_LH_ALIGN 0 21791 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NONMATCHINGMP_LH_BITS 1 21792 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NONMATCHINGMP_LH_SHIFT 5 21793 21794 /* sys_device7 :: miscrxstatus :: over1gMP_lh [04:04] */ 21795 #define PHY84328_SYS_DEV7_MISCRXSTATUS_OVER1GMP_LH_MASK 0x0010 21796 #define PHY84328_SYS_DEV7_MISCRXSTATUS_OVER1GMP_LH_ALIGN 0 21797 #define PHY84328_SYS_DEV7_MISCRXSTATUS_OVER1GMP_LH_BITS 1 21798 #define PHY84328_SYS_DEV7_MISCRXSTATUS_OVER1GMP_LH_SHIFT 4 21799 21800 /* sys_device7 :: miscrxstatus :: rx_config_is_0_lh [03:03] */ 21801 #define PHY84328_SYS_DEV7_MISCRXSTATUS_RX_CONFIG_IS_0_LH_MASK 0x0008 21802 #define PHY84328_SYS_DEV7_MISCRXSTATUS_RX_CONFIG_IS_0_LH_ALIGN 0 21803 #define PHY84328_SYS_DEV7_MISCRXSTATUS_RX_CONFIG_IS_0_LH_BITS 1 21804 #define PHY84328_SYS_DEV7_MISCRXSTATUS_RX_CONFIG_IS_0_LH_SHIFT 3 21805 21806 /* sys_device7 :: miscrxstatus :: np_toggle_err_lh [02:02] */ 21807 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NP_TOGGLE_ERR_LH_MASK 0x0004 21808 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NP_TOGGLE_ERR_LH_ALIGN 0 21809 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NP_TOGGLE_ERR_LH_BITS 1 21810 #define PHY84328_SYS_DEV7_MISCRXSTATUS_NP_TOGGLE_ERR_LH_SHIFT 2 21811 21812 /* sys_device7 :: miscrxstatus :: mr_np_lh [01:01] */ 21813 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MR_NP_LH_MASK 0x0002 21814 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MR_NP_LH_ALIGN 0 21815 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MR_NP_LH_BITS 1 21816 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MR_NP_LH_SHIFT 1 21817 21818 /* sys_device7 :: miscrxstatus :: mr_bp_lh [00:00] */ 21819 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MR_BP_LH_MASK 0x0001 21820 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MR_BP_LH_ALIGN 0 21821 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MR_BP_LH_BITS 1 21822 #define PHY84328_SYS_DEV7_MISCRXSTATUS_MR_BP_LH_SHIFT 0 21823 21824 21825 /**************************************************************************** 21826 * sys_device7 :: x2500status1 21827 */ 21828 /* sys_device7 :: x2500status1 :: hcd_over_1g_or [15:15] */ 21829 #define PHY84328_SYS_DEV7_X2500STATUS1_HCD_OVER_1G_OR_MASK 0x8000 21830 #define PHY84328_SYS_DEV7_X2500STATUS1_HCD_OVER_1G_OR_ALIGN 0 21831 #define PHY84328_SYS_DEV7_X2500STATUS1_HCD_OVER_1G_OR_BITS 1 21832 #define PHY84328_SYS_DEV7_X2500STATUS1_HCD_OVER_1G_OR_SHIFT 15 21833 21834 /* sys_device7 :: x2500status1 :: latch_hcd_over_1g [14:14] */ 21835 #define PHY84328_SYS_DEV7_X2500STATUS1_LATCH_HCD_OVER_1G_MASK 0x4000 21836 #define PHY84328_SYS_DEV7_X2500STATUS1_LATCH_HCD_OVER_1G_ALIGN 0 21837 #define PHY84328_SYS_DEV7_X2500STATUS1_LATCH_HCD_OVER_1G_BITS 1 21838 #define PHY84328_SYS_DEV7_X2500STATUS1_LATCH_HCD_OVER_1G_SHIFT 14 21839 21840 /* sys_device7 :: x2500status1 :: latchmdio [13:13] */ 21841 #define PHY84328_SYS_DEV7_X2500STATUS1_LATCHMDIO_MASK 0x2000 21842 #define PHY84328_SYS_DEV7_X2500STATUS1_LATCHMDIO_ALIGN 0 21843 #define PHY84328_SYS_DEV7_X2500STATUS1_LATCHMDIO_BITS 1 21844 #define PHY84328_SYS_DEV7_X2500STATUS1_LATCHMDIO_SHIFT 13 21845 21846 /* sys_device7 :: x2500status1 :: s_bc_reg_rst [12:12] */ 21847 #define PHY84328_SYS_DEV7_X2500STATUS1_S_BC_REG_RST_MASK 0x1000 21848 #define PHY84328_SYS_DEV7_X2500STATUS1_S_BC_REG_RST_ALIGN 0 21849 #define PHY84328_SYS_DEV7_X2500STATUS1_S_BC_REG_RST_BITS 1 21850 #define PHY84328_SYS_DEV7_X2500STATUS1_S_BC_REG_RST_SHIFT 12 21851 21852 /* sys_device7 :: x2500status1 :: s_wait2res [11:11] */ 21853 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT2RES_MASK 0x0800 21854 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT2RES_ALIGN 0 21855 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT2RES_BITS 1 21856 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT2RES_SHIFT 11 21857 21858 /* sys_device7 :: x2500status1 :: s_wait30ms [10:10] */ 21859 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT30MS_MASK 0x0400 21860 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT30MS_ALIGN 0 21861 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT30MS_BITS 1 21862 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT30MS_SHIFT 10 21863 21864 /* sys_device7 :: x2500status1 :: s_clockswit [09:09] */ 21865 #define PHY84328_SYS_DEV7_X2500STATUS1_S_CLOCKSWIT_MASK 0x0200 21866 #define PHY84328_SYS_DEV7_X2500STATUS1_S_CLOCKSWIT_ALIGN 0 21867 #define PHY84328_SYS_DEV7_X2500STATUS1_S_CLOCKSWIT_BITS 1 21868 #define PHY84328_SYS_DEV7_X2500STATUS1_S_CLOCKSWIT_SHIFT 9 21869 21870 /* sys_device7 :: x2500status1 :: s_pllswit [08:08] */ 21871 #define PHY84328_SYS_DEV7_X2500STATUS1_S_PLLSWIT_MASK 0x0100 21872 #define PHY84328_SYS_DEV7_X2500STATUS1_S_PLLSWIT_ALIGN 0 21873 #define PHY84328_SYS_DEV7_X2500STATUS1_S_PLLSWIT_BITS 1 21874 #define PHY84328_SYS_DEV7_X2500STATUS1_S_PLLSWIT_SHIFT 8 21875 21876 /* sys_device7 :: x2500status1 :: s_wait4link [07:07] */ 21877 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT4LINK_MASK 0x0080 21878 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT4LINK_ALIGN 0 21879 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT4LINK_BITS 1 21880 #define PHY84328_SYS_DEV7_X2500STATUS1_S_WAIT4LINK_SHIFT 7 21881 21882 /* sys_device7 :: x2500status1 :: s_complete [06:06] */ 21883 #define PHY84328_SYS_DEV7_X2500STATUS1_S_COMPLETE_MASK 0x0040 21884 #define PHY84328_SYS_DEV7_X2500STATUS1_S_COMPLETE_ALIGN 0 21885 #define PHY84328_SYS_DEV7_X2500STATUS1_S_COMPLETE_BITS 1 21886 #define PHY84328_SYS_DEV7_X2500STATUS1_S_COMPLETE_SHIFT 6 21887 21888 /* sys_device7 :: x2500status1 :: s_lostlink [05:05] */ 21889 #define PHY84328_SYS_DEV7_X2500STATUS1_S_LOSTLINK_MASK 0x0020 21890 #define PHY84328_SYS_DEV7_X2500STATUS1_S_LOSTLINK_ALIGN 0 21891 #define PHY84328_SYS_DEV7_X2500STATUS1_S_LOSTLINK_BITS 1 21892 #define PHY84328_SYS_DEV7_X2500STATUS1_S_LOSTLINK_SHIFT 5 21893 21894 /* sys_device7 :: x2500status1 :: s_dead [04:04] */ 21895 #define PHY84328_SYS_DEV7_X2500STATUS1_S_DEAD_MASK 0x0010 21896 #define PHY84328_SYS_DEV7_X2500STATUS1_S_DEAD_ALIGN 0 21897 #define PHY84328_SYS_DEV7_X2500STATUS1_S_DEAD_BITS 1 21898 #define PHY84328_SYS_DEV7_X2500STATUS1_S_DEAD_SHIFT 4 21899 21900 /* sys_device7 :: x2500status1 :: fail_cnt [03:00] */ 21901 #define PHY84328_SYS_DEV7_X2500STATUS1_FAIL_CNT_MASK 0x000f 21902 #define PHY84328_SYS_DEV7_X2500STATUS1_FAIL_CNT_ALIGN 0 21903 #define PHY84328_SYS_DEV7_X2500STATUS1_FAIL_CNT_BITS 4 21904 #define PHY84328_SYS_DEV7_X2500STATUS1_FAIL_CNT_SHIFT 0 21905 21906 21907 /**************************************************************************** 21908 * sys_device7 :: topanstatus1 21909 */ 21910 /* sys_device7 :: topanstatus1 :: reserved0 [15:14] */ 21911 #define PHY84328_SYS_DEV7_TOPANSTATUS1_RESERVED0_MASK 0xc000 21912 #define PHY84328_SYS_DEV7_TOPANSTATUS1_RESERVED0_ALIGN 0 21913 #define PHY84328_SYS_DEV7_TOPANSTATUS1_RESERVED0_BITS 2 21914 #define PHY84328_SYS_DEV7_TOPANSTATUS1_RESERVED0_SHIFT 14 21915 21916 /* sys_device7 :: topanstatus1 :: actual_speed [13:08] */ 21917 #define PHY84328_SYS_DEV7_TOPANSTATUS1_ACTUAL_SPEED_MASK 0x3f00 21918 #define PHY84328_SYS_DEV7_TOPANSTATUS1_ACTUAL_SPEED_ALIGN 0 21919 #define PHY84328_SYS_DEV7_TOPANSTATUS1_ACTUAL_SPEED_BITS 6 21920 #define PHY84328_SYS_DEV7_TOPANSTATUS1_ACTUAL_SPEED_SHIFT 8 21921 21922 /* sys_device7 :: topanstatus1 :: pause_resolution_rxside [07:07] */ 21923 #define PHY84328_SYS_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0080 21924 #define PHY84328_SYS_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 21925 #define PHY84328_SYS_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_BITS 1 21926 #define PHY84328_SYS_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_SHIFT 7 21927 21928 /* sys_device7 :: topanstatus1 :: pause_resolution_txside [06:06] */ 21929 #define PHY84328_SYS_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0040 21930 #define PHY84328_SYS_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 21931 #define PHY84328_SYS_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_BITS 1 21932 #define PHY84328_SYS_DEV7_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_SHIFT 6 21933 21934 /* sys_device7 :: topanstatus1 :: cl73_lp_np_BAM_able [05:05] */ 21935 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_MASK 0x0020 21936 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_ALIGN 0 21937 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_BITS 1 21938 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_SHIFT 5 21939 21940 /* sys_device7 :: topanstatus1 :: cl73_mr_lp_autoneg_able [04:04] */ 21941 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_MASK 0x0010 21942 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 21943 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_BITS 1 21944 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 21945 21946 /* sys_device7 :: topanstatus1 :: duplex_status [03:03] */ 21947 #define PHY84328_SYS_DEV7_TOPANSTATUS1_DUPLEX_STATUS_MASK 0x0008 21948 #define PHY84328_SYS_DEV7_TOPANSTATUS1_DUPLEX_STATUS_ALIGN 0 21949 #define PHY84328_SYS_DEV7_TOPANSTATUS1_DUPLEX_STATUS_BITS 1 21950 #define PHY84328_SYS_DEV7_TOPANSTATUS1_DUPLEX_STATUS_SHIFT 3 21951 21952 /* sys_device7 :: topanstatus1 :: link_status [02:02] */ 21953 #define PHY84328_SYS_DEV7_TOPANSTATUS1_LINK_STATUS_MASK 0x0004 21954 #define PHY84328_SYS_DEV7_TOPANSTATUS1_LINK_STATUS_ALIGN 0 21955 #define PHY84328_SYS_DEV7_TOPANSTATUS1_LINK_STATUS_BITS 1 21956 #define PHY84328_SYS_DEV7_TOPANSTATUS1_LINK_STATUS_SHIFT 2 21957 21958 /* sys_device7 :: topanstatus1 :: cl37_autoneg_complete [01:01] */ 21959 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK 0x0002 21960 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN 0 21961 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS 1 21962 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT 1 21963 21964 /* sys_device7 :: topanstatus1 :: cl73_autoneg_complete [00:00] */ 21965 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK 0x0001 21966 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN 0 21967 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS 1 21968 #define PHY84328_SYS_DEV7_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT 0 21969 21970 21971 /**************************************************************************** 21972 * sys_device7 :: lp_up1 21973 */ 21974 /* sys_device7 :: lp_up1 :: reserved0 [15:11] */ 21975 #define PHY84328_SYS_DEV7_LP_UP1_RESERVED0_MASK 0xf800 21976 #define PHY84328_SYS_DEV7_LP_UP1_RESERVED0_ALIGN 0 21977 #define PHY84328_SYS_DEV7_LP_UP1_RESERVED0_BITS 5 21978 #define PHY84328_SYS_DEV7_LP_UP1_RESERVED0_SHIFT 11 21979 21980 /* sys_device7 :: lp_up1 :: lp_adv_over_1g [10:00] */ 21981 #define PHY84328_SYS_DEV7_LP_UP1_LP_ADV_OVER_1G_MASK 0x07ff 21982 #define PHY84328_SYS_DEV7_LP_UP1_LP_ADV_OVER_1G_ALIGN 0 21983 #define PHY84328_SYS_DEV7_LP_UP1_LP_ADV_OVER_1G_BITS 11 21984 #define PHY84328_SYS_DEV7_LP_UP1_LP_ADV_OVER_1G_SHIFT 0 21985 21986 21987 /**************************************************************************** 21988 * sys_device7 :: lp_up2 21989 */ 21990 /* sys_device7 :: lp_up2 :: reserved0 [15:11] */ 21991 #define PHY84328_SYS_DEV7_LP_UP2_RESERVED0_MASK 0xf800 21992 #define PHY84328_SYS_DEV7_LP_UP2_RESERVED0_ALIGN 0 21993 #define PHY84328_SYS_DEV7_LP_UP2_RESERVED0_BITS 5 21994 #define PHY84328_SYS_DEV7_LP_UP2_RESERVED0_SHIFT 11 21995 21996 /* sys_device7 :: lp_up2 :: lp_adv_over_1g [10:00] */ 21997 #define PHY84328_SYS_DEV7_LP_UP2_LP_ADV_OVER_1G_MASK 0x07ff 21998 #define PHY84328_SYS_DEV7_LP_UP2_LP_ADV_OVER_1G_ALIGN 0 21999 #define PHY84328_SYS_DEV7_LP_UP2_LP_ADV_OVER_1G_BITS 11 22000 #define PHY84328_SYS_DEV7_LP_UP2_LP_ADV_OVER_1G_SHIFT 0 22001 22002 22003 /**************************************************************************** 22004 * sys_device7 :: lp_up3 22005 */ 22006 /* sys_device7 :: lp_up3 :: reserved0 [15:11] */ 22007 #define PHY84328_SYS_DEV7_LP_UP3_RESERVED0_MASK 0xf800 22008 #define PHY84328_SYS_DEV7_LP_UP3_RESERVED0_ALIGN 0 22009 #define PHY84328_SYS_DEV7_LP_UP3_RESERVED0_BITS 5 22010 #define PHY84328_SYS_DEV7_LP_UP3_RESERVED0_SHIFT 11 22011 22012 /* sys_device7 :: lp_up3 :: lp_adv_over_1g [10:00] */ 22013 #define PHY84328_SYS_DEV7_LP_UP3_LP_ADV_OVER_1G_MASK 0x07ff 22014 #define PHY84328_SYS_DEV7_LP_UP3_LP_ADV_OVER_1G_ALIGN 0 22015 #define PHY84328_SYS_DEV7_LP_UP3_LP_ADV_OVER_1G_BITS 11 22016 #define PHY84328_SYS_DEV7_LP_UP3_LP_ADV_OVER_1G_SHIFT 0 22017 22018 22019 /**************************************************************************** 22020 * sys_device7_userPerLnCtrl_Registers 22021 */ 22022 /**************************************************************************** 22023 * sys_device7 :: cl73Control1 22024 */ 22025 /* sys_device7 :: cl73Control1 :: reserved0 [15:08] */ 22026 #define PHY84328_SYS_DEV7_CL73CONTROL1_RESERVED0_MASK 0xff00 22027 #define PHY84328_SYS_DEV7_CL73CONTROL1_RESERVED0_ALIGN 0 22028 #define PHY84328_SYS_DEV7_CL73CONTROL1_RESERVED0_BITS 8 22029 #define PHY84328_SYS_DEV7_CL73CONTROL1_RESERVED0_SHIFT 8 22030 22031 /* sys_device7 :: cl73Control1 :: cl73_internal_10us_timer_val [07:00] */ 22032 #define PHY84328_SYS_DEV7_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_MASK 0x00ff 22033 #define PHY84328_SYS_DEV7_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_ALIGN 0 22034 #define PHY84328_SYS_DEV7_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_BITS 8 22035 #define PHY84328_SYS_DEV7_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_SHIFT 0 22036 22037 22038 /**************************************************************************** 22039 * sys_device7 :: cl73Control2 22040 */ 22041 /* sys_device7 :: cl73Control2 :: reserved0 [15:13] */ 22042 #define PHY84328_SYS_DEV7_CL73CONTROL2_RESERVED0_MASK 0xe000 22043 #define PHY84328_SYS_DEV7_CL73CONTROL2_RESERVED0_ALIGN 0 22044 #define PHY84328_SYS_DEV7_CL73CONTROL2_RESERVED0_BITS 3 22045 #define PHY84328_SYS_DEV7_CL73CONTROL2_RESERVED0_SHIFT 13 22046 22047 /* sys_device7 :: cl73Control2 :: cl73_link_fail_inhibit_timer_val [12:00] */ 22048 #define PHY84328_SYS_DEV7_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_MASK 0x1fff 22049 #define PHY84328_SYS_DEV7_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_ALIGN 0 22050 #define PHY84328_SYS_DEV7_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_BITS 13 22051 #define PHY84328_SYS_DEV7_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_SHIFT 0 22052 22053 22054 /**************************************************************************** 22055 * sys_device7 :: cl73Control3 22056 */ 22057 /* sys_device7 :: cl73Control3 :: reserved0 [15:13] */ 22058 #define PHY84328_SYS_DEV7_CL73CONTROL3_RESERVED0_MASK 0xe000 22059 #define PHY84328_SYS_DEV7_CL73CONTROL3_RESERVED0_ALIGN 0 22060 #define PHY84328_SYS_DEV7_CL73CONTROL3_RESERVED0_BITS 3 22061 #define PHY84328_SYS_DEV7_CL73CONTROL3_RESERVED0_SHIFT 13 22062 22063 /* sys_device7 :: cl73Control3 :: cl73_an_wait_timer_val [12:00] */ 22064 #define PHY84328_SYS_DEV7_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_MASK 0x1fff 22065 #define PHY84328_SYS_DEV7_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_ALIGN 0 22066 #define PHY84328_SYS_DEV7_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_BITS 13 22067 #define PHY84328_SYS_DEV7_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_SHIFT 0 22068 22069 22070 /**************************************************************************** 22071 * sys_device7 :: cl73Control4 22072 */ 22073 /* sys_device7 :: cl73Control4 :: reserved0 [15:13] */ 22074 #define PHY84328_SYS_DEV7_CL73CONTROL4_RESERVED0_MASK 0xe000 22075 #define PHY84328_SYS_DEV7_CL73CONTROL4_RESERVED0_ALIGN 0 22076 #define PHY84328_SYS_DEV7_CL73CONTROL4_RESERVED0_BITS 3 22077 #define PHY84328_SYS_DEV7_CL73CONTROL4_RESERVED0_SHIFT 13 22078 22079 /* sys_device7 :: cl73Control4 :: cl73_break_link_timer_val [12:00] */ 22080 #define PHY84328_SYS_DEV7_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_MASK 0x1fff 22081 #define PHY84328_SYS_DEV7_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_ALIGN 0 22082 #define PHY84328_SYS_DEV7_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_BITS 13 22083 #define PHY84328_SYS_DEV7_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_SHIFT 0 22084 22085 22086 /**************************************************************************** 22087 * sys_device7 :: cl73Control5 22088 */ 22089 /* sys_device7 :: cl73Control5 :: reserved0 [15:13] */ 22090 #define PHY84328_SYS_DEV7_CL73CONTROL5_RESERVED0_MASK 0xe000 22091 #define PHY84328_SYS_DEV7_CL73CONTROL5_RESERVED0_ALIGN 0 22092 #define PHY84328_SYS_DEV7_CL73CONTROL5_RESERVED0_BITS 3 22093 #define PHY84328_SYS_DEV7_CL73CONTROL5_RESERVED0_SHIFT 13 22094 22095 /* sys_device7 :: cl73Control5 :: cl73_break_link_timer_bam_val [12:00] */ 22096 #define PHY84328_SYS_DEV7_CL73CONTROL5_CL73_BREAK_LINK_TIMER_BAM_VAL_MASK 0x1fff 22097 #define PHY84328_SYS_DEV7_CL73CONTROL5_CL73_BREAK_LINK_TIMER_BAM_VAL_ALIGN 0 22098 #define PHY84328_SYS_DEV7_CL73CONTROL5_CL73_BREAK_LINK_TIMER_BAM_VAL_BITS 13 22099 #define PHY84328_SYS_DEV7_CL73CONTROL5_CL73_BREAK_LINK_TIMER_BAM_VAL_SHIFT 0 22100 22101 22102 /**************************************************************************** 22103 * sys_device7 :: cl73Control6 22104 */ 22105 /* sys_device7 :: cl73Control6 :: reserved0 [15:13] */ 22106 #define PHY84328_SYS_DEV7_CL73CONTROL6_RESERVED0_MASK 0xe000 22107 #define PHY84328_SYS_DEV7_CL73CONTROL6_RESERVED0_ALIGN 0 22108 #define PHY84328_SYS_DEV7_CL73CONTROL6_RESERVED0_BITS 3 22109 #define PHY84328_SYS_DEV7_CL73CONTROL6_RESERVED0_SHIFT 13 22110 22111 /* sys_device7 :: cl73Control6 :: cl73_ignore_link_timer_val [12:00] */ 22112 #define PHY84328_SYS_DEV7_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_MASK 0x1fff 22113 #define PHY84328_SYS_DEV7_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_ALIGN 0 22114 #define PHY84328_SYS_DEV7_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_BITS 13 22115 #define PHY84328_SYS_DEV7_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_SHIFT 0 22116 22117 22118 /**************************************************************************** 22119 * sys_device7 :: cl73DmeTmrs 22120 */ 22121 /* sys_device7 :: cl73DmeTmrs :: cl73_dme_page_test_max_cnt_val [15:08] */ 22122 #define PHY84328_SYS_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_MASK 0xff00 22123 #define PHY84328_SYS_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_ALIGN 0 22124 #define PHY84328_SYS_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_BITS 8 22125 #define PHY84328_SYS_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_SHIFT 8 22126 22127 /* sys_device7 :: cl73DmeTmrs :: cl73_dme_page_test_min_cnt_val [07:00] */ 22128 #define PHY84328_SYS_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_MASK 0x00ff 22129 #define PHY84328_SYS_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_ALIGN 0 22130 #define PHY84328_SYS_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_BITS 8 22131 #define PHY84328_SYS_DEV7_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_SHIFT 0 22132 22133 22134 /**************************************************************************** 22135 * sys_device7 :: Control1000X1 22136 */ 22137 /* sys_device7 :: Control1000X1 :: reserved0 [15:15] */ 22138 #define PHY84328_SYS_DEV7_CONTROL1000X1_RESERVED0_MASK 0x8000 22139 #define PHY84328_SYS_DEV7_CONTROL1000X1_RESERVED0_ALIGN 0 22140 #define PHY84328_SYS_DEV7_CONTROL1000X1_RESERVED0_BITS 1 22141 #define PHY84328_SYS_DEV7_CONTROL1000X1_RESERVED0_SHIFT 15 22142 22143 /* sys_device7 :: Control1000X1 :: disable_signal_detect_filter [14:14] */ 22144 #define PHY84328_SYS_DEV7_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000 22145 #define PHY84328_SYS_DEV7_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0 22146 #define PHY84328_SYS_DEV7_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1 22147 #define PHY84328_SYS_DEV7_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14 22148 22149 /* sys_device7 :: Control1000X1 :: reserved1 [13:12] */ 22150 #define PHY84328_SYS_DEV7_CONTROL1000X1_RESERVED1_MASK 0x3000 22151 #define PHY84328_SYS_DEV7_CONTROL1000X1_RESERVED1_ALIGN 0 22152 #define PHY84328_SYS_DEV7_CONTROL1000X1_RESERVED1_BITS 2 22153 #define PHY84328_SYS_DEV7_CONTROL1000X1_RESERVED1_SHIFT 12 22154 22155 /* sys_device7 :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */ 22156 #define PHY84328_SYS_DEV7_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK 0x0800 22157 #define PHY84328_SYS_DEV7_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN 0 22158 #define PHY84328_SYS_DEV7_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS 1 22159 #define PHY84328_SYS_DEV7_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT 11 22160 22161 /* sys_device7 :: Control1000X1 :: remote_loopback [10:10] */ 22162 #define PHY84328_SYS_DEV7_CONTROL1000X1_REMOTE_LOOPBACK_MASK 0x0400 22163 #define PHY84328_SYS_DEV7_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN 0 22164 #define PHY84328_SYS_DEV7_CONTROL1000X1_REMOTE_LOOPBACK_BITS 1 22165 #define PHY84328_SYS_DEV7_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT 10 22166 22167 /* sys_device7 :: Control1000X1 :: zero_comma_detector_phase [09:09] */ 22168 #define PHY84328_SYS_DEV7_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200 22169 #define PHY84328_SYS_DEV7_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0 22170 #define PHY84328_SYS_DEV7_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1 22171 #define PHY84328_SYS_DEV7_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9 22172 22173 /* sys_device7 :: Control1000X1 :: comma_det_en [08:08] */ 22174 #define PHY84328_SYS_DEV7_CONTROL1000X1_COMMA_DET_EN_MASK 0x0100 22175 #define PHY84328_SYS_DEV7_CONTROL1000X1_COMMA_DET_EN_ALIGN 0 22176 #define PHY84328_SYS_DEV7_CONTROL1000X1_COMMA_DET_EN_BITS 1 22177 #define PHY84328_SYS_DEV7_CONTROL1000X1_COMMA_DET_EN_SHIFT 8 22178 22179 /* sys_device7 :: Control1000X1 :: crc_checker_disable [07:07] */ 22180 #define PHY84328_SYS_DEV7_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK 0x0080 22181 #define PHY84328_SYS_DEV7_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN 0 22182 #define PHY84328_SYS_DEV7_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS 1 22183 #define PHY84328_SYS_DEV7_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT 7 22184 22185 /* sys_device7 :: Control1000X1 :: disable_pll_pwrdwn [06:06] */ 22186 #define PHY84328_SYS_DEV7_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK 0x0040 22187 #define PHY84328_SYS_DEV7_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN 0 22188 #define PHY84328_SYS_DEV7_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS 1 22189 #define PHY84328_SYS_DEV7_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT 6 22190 22191 /* sys_device7 :: Control1000X1 :: sgmii_master_mode [05:05] */ 22192 #define PHY84328_SYS_DEV7_CONTROL1000X1_SGMII_MASTER_MODE_MASK 0x0020 22193 #define PHY84328_SYS_DEV7_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN 0 22194 #define PHY84328_SYS_DEV7_CONTROL1000X1_SGMII_MASTER_MODE_BITS 1 22195 #define PHY84328_SYS_DEV7_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT 5 22196 22197 /* sys_device7 :: Control1000X1 :: autodet_en [04:04] */ 22198 #define PHY84328_SYS_DEV7_CONTROL1000X1_AUTODET_EN_MASK 0x0010 22199 #define PHY84328_SYS_DEV7_CONTROL1000X1_AUTODET_EN_ALIGN 0 22200 #define PHY84328_SYS_DEV7_CONTROL1000X1_AUTODET_EN_BITS 1 22201 #define PHY84328_SYS_DEV7_CONTROL1000X1_AUTODET_EN_SHIFT 4 22202 22203 /* sys_device7 :: Control1000X1 :: invert_signal_detect [03:03] */ 22204 #define PHY84328_SYS_DEV7_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK 0x0008 22205 #define PHY84328_SYS_DEV7_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN 0 22206 #define PHY84328_SYS_DEV7_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS 1 22207 #define PHY84328_SYS_DEV7_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT 3 22208 22209 /* sys_device7 :: Control1000X1 :: signal_detect_en [02:02] */ 22210 #define PHY84328_SYS_DEV7_CONTROL1000X1_SIGNAL_DETECT_EN_MASK 0x0004 22211 #define PHY84328_SYS_DEV7_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN 0 22212 #define PHY84328_SYS_DEV7_CONTROL1000X1_SIGNAL_DETECT_EN_BITS 1 22213 #define PHY84328_SYS_DEV7_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT 2 22214 22215 /* sys_device7 :: Control1000X1 :: tbi_interface [01:01] */ 22216 #define PHY84328_SYS_DEV7_CONTROL1000X1_TBI_INTERFACE_MASK 0x0002 22217 #define PHY84328_SYS_DEV7_CONTROL1000X1_TBI_INTERFACE_ALIGN 0 22218 #define PHY84328_SYS_DEV7_CONTROL1000X1_TBI_INTERFACE_BITS 1 22219 #define PHY84328_SYS_DEV7_CONTROL1000X1_TBI_INTERFACE_SHIFT 1 22220 22221 /* sys_device7 :: Control1000X1 :: fiber_mode_1000X [00:00] */ 22222 #define PHY84328_SYS_DEV7_CONTROL1000X1_FIBER_MODE_1000X_MASK 0x0001 22223 #define PHY84328_SYS_DEV7_CONTROL1000X1_FIBER_MODE_1000X_ALIGN 0 22224 #define PHY84328_SYS_DEV7_CONTROL1000X1_FIBER_MODE_1000X_BITS 1 22225 #define PHY84328_SYS_DEV7_CONTROL1000X1_FIBER_MODE_1000X_SHIFT 0 22226 22227 22228 /**************************************************************************** 22229 * sys_device7 :: Control1000X2 22230 */ 22231 /* sys_device7 :: Control1000X2 :: disable_extend_fdx_only [15:15] */ 22232 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK 0x8000 22233 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0 22234 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS 1 22235 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15 22236 22237 /* sys_device7 :: Control1000X2 :: clear_ber_counter [14:14] */ 22238 #define PHY84328_SYS_DEV7_CONTROL1000X2_CLEAR_BER_COUNTER_MASK 0x4000 22239 #define PHY84328_SYS_DEV7_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN 0 22240 #define PHY84328_SYS_DEV7_CONTROL1000X2_CLEAR_BER_COUNTER_BITS 1 22241 #define PHY84328_SYS_DEV7_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT 14 22242 22243 /* sys_device7 :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */ 22244 #define PHY84328_SYS_DEV7_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000 22245 #define PHY84328_SYS_DEV7_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0 22246 #define PHY84328_SYS_DEV7_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1 22247 #define PHY84328_SYS_DEV7_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13 22248 22249 /* sys_device7 :: Control1000X2 :: transmit_packet_seq_test [12:12] */ 22250 #define PHY84328_SYS_DEV7_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK 0x1000 22251 #define PHY84328_SYS_DEV7_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0 22252 #define PHY84328_SYS_DEV7_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS 1 22253 #define PHY84328_SYS_DEV7_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12 22254 22255 /* sys_device7 :: Control1000X2 :: test_cntr [11:11] */ 22256 #define PHY84328_SYS_DEV7_CONTROL1000X2_TEST_CNTR_MASK 0x0800 22257 #define PHY84328_SYS_DEV7_CONTROL1000X2_TEST_CNTR_ALIGN 0 22258 #define PHY84328_SYS_DEV7_CONTROL1000X2_TEST_CNTR_BITS 1 22259 #define PHY84328_SYS_DEV7_CONTROL1000X2_TEST_CNTR_SHIFT 11 22260 22261 /* sys_device7 :: Control1000X2 :: bypass_pcs_tx [10:10] */ 22262 #define PHY84328_SYS_DEV7_CONTROL1000X2_BYPASS_PCS_TX_MASK 0x0400 22263 #define PHY84328_SYS_DEV7_CONTROL1000X2_BYPASS_PCS_TX_ALIGN 0 22264 #define PHY84328_SYS_DEV7_CONTROL1000X2_BYPASS_PCS_TX_BITS 1 22265 #define PHY84328_SYS_DEV7_CONTROL1000X2_BYPASS_PCS_TX_SHIFT 10 22266 22267 /* sys_device7 :: Control1000X2 :: bypass_pcs_rx [09:09] */ 22268 #define PHY84328_SYS_DEV7_CONTROL1000X2_BYPASS_PCS_RX_MASK 0x0200 22269 #define PHY84328_SYS_DEV7_CONTROL1000X2_BYPASS_PCS_RX_ALIGN 0 22270 #define PHY84328_SYS_DEV7_CONTROL1000X2_BYPASS_PCS_RX_BITS 1 22271 #define PHY84328_SYS_DEV7_CONTROL1000X2_BYPASS_PCS_RX_SHIFT 9 22272 22273 /* sys_device7 :: Control1000X2 :: disable_TRRR_generation [08:08] */ 22274 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK 0x0100 22275 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0 22276 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS 1 22277 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8 22278 22279 /* sys_device7 :: Control1000X2 :: disable_carrier_extend [07:07] */ 22280 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK 0x0080 22281 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN 0 22282 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS 1 22283 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT 7 22284 22285 /* sys_device7 :: Control1000X2 :: autoneg_fast_timers [06:06] */ 22286 #define PHY84328_SYS_DEV7_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK 0x0040 22287 #define PHY84328_SYS_DEV7_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN 0 22288 #define PHY84328_SYS_DEV7_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS 1 22289 #define PHY84328_SYS_DEV7_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT 6 22290 22291 /* sys_device7 :: Control1000X2 :: force_xmit_data_on_txside [05:05] */ 22292 #define PHY84328_SYS_DEV7_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020 22293 #define PHY84328_SYS_DEV7_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0 22294 #define PHY84328_SYS_DEV7_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1 22295 #define PHY84328_SYS_DEV7_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5 22296 22297 /* sys_device7 :: Control1000X2 :: disable_remote_fault_sensing [04:04] */ 22298 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010 22299 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0 22300 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1 22301 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4 22302 22303 /* sys_device7 :: Control1000X2 :: enable_autoneg_err_timer [03:03] */ 22304 #define PHY84328_SYS_DEV7_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008 22305 #define PHY84328_SYS_DEV7_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0 22306 #define PHY84328_SYS_DEV7_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1 22307 #define PHY84328_SYS_DEV7_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3 22308 22309 /* sys_device7 :: Control1000X2 :: filter_force_link [02:02] */ 22310 #define PHY84328_SYS_DEV7_CONTROL1000X2_FILTER_FORCE_LINK_MASK 0x0004 22311 #define PHY84328_SYS_DEV7_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN 0 22312 #define PHY84328_SYS_DEV7_CONTROL1000X2_FILTER_FORCE_LINK_BITS 1 22313 #define PHY84328_SYS_DEV7_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT 2 22314 22315 /* sys_device7 :: Control1000X2 :: disable_false_link [01:01] */ 22316 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_FALSE_LINK_MASK 0x0002 22317 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN 0 22318 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_FALSE_LINK_BITS 1 22319 #define PHY84328_SYS_DEV7_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT 1 22320 22321 /* sys_device7 :: Control1000X2 :: enable_parallel_detection [00:00] */ 22322 #define PHY84328_SYS_DEV7_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK 0x0001 22323 #define PHY84328_SYS_DEV7_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN 0 22324 #define PHY84328_SYS_DEV7_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS 1 22325 #define PHY84328_SYS_DEV7_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT 0 22326 22327 22328 /**************************************************************************** 22329 * sys_device7 :: Control1000X3 22330 */ 22331 /* sys_device7 :: Control1000X3 :: disable_packet_misalign [15:15] */ 22332 #define PHY84328_SYS_DEV7_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK 0x8000 22333 #define PHY84328_SYS_DEV7_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN 0 22334 #define PHY84328_SYS_DEV7_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS 1 22335 #define PHY84328_SYS_DEV7_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT 15 22336 22337 /* sys_device7 :: Control1000X3 :: rxfifo_gmii_reset [14:14] */ 22338 #define PHY84328_SYS_DEV7_CONTROL1000X3_RXFIFO_GMII_RESET_MASK 0x4000 22339 #define PHY84328_SYS_DEV7_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN 0 22340 #define PHY84328_SYS_DEV7_CONTROL1000X3_RXFIFO_GMII_RESET_BITS 1 22341 #define PHY84328_SYS_DEV7_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT 14 22342 22343 /* sys_device7 :: Control1000X3 :: disable_tx_crs [13:13] */ 22344 #define PHY84328_SYS_DEV7_CONTROL1000X3_DISABLE_TX_CRS_MASK 0x2000 22345 #define PHY84328_SYS_DEV7_CONTROL1000X3_DISABLE_TX_CRS_ALIGN 0 22346 #define PHY84328_SYS_DEV7_CONTROL1000X3_DISABLE_TX_CRS_BITS 1 22347 #define PHY84328_SYS_DEV7_CONTROL1000X3_DISABLE_TX_CRS_SHIFT 13 22348 22349 /* sys_device7 :: Control1000X3 :: invert_ext_phy_crs [12:12] */ 22350 #define PHY84328_SYS_DEV7_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK 0x1000 22351 #define PHY84328_SYS_DEV7_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN 0 22352 #define PHY84328_SYS_DEV7_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS 1 22353 #define PHY84328_SYS_DEV7_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT 12 22354 22355 /* sys_device7 :: Control1000X3 :: ext_phy_crs_mode [11:11] */ 22356 #define PHY84328_SYS_DEV7_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK 0x0800 22357 #define PHY84328_SYS_DEV7_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN 0 22358 #define PHY84328_SYS_DEV7_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS 1 22359 #define PHY84328_SYS_DEV7_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT 11 22360 22361 /* sys_device7 :: Control1000X3 :: jam_false_carrier_mode [10:10] */ 22362 #define PHY84328_SYS_DEV7_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK 0x0400 22363 #define PHY84328_SYS_DEV7_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN 0 22364 #define PHY84328_SYS_DEV7_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS 1 22365 #define PHY84328_SYS_DEV7_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT 10 22366 22367 /* sys_device7 :: Control1000X3 :: block_txen_mode [09:09] */ 22368 #define PHY84328_SYS_DEV7_CONTROL1000X3_BLOCK_TXEN_MODE_MASK 0x0200 22369 #define PHY84328_SYS_DEV7_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN 0 22370 #define PHY84328_SYS_DEV7_CONTROL1000X3_BLOCK_TXEN_MODE_BITS 1 22371 #define PHY84328_SYS_DEV7_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT 9 22372 22373 /* sys_device7 :: Control1000X3 :: force_txfifo_on [08:08] */ 22374 #define PHY84328_SYS_DEV7_CONTROL1000X3_FORCE_TXFIFO_ON_MASK 0x0100 22375 #define PHY84328_SYS_DEV7_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN 0 22376 #define PHY84328_SYS_DEV7_CONTROL1000X3_FORCE_TXFIFO_ON_BITS 1 22377 #define PHY84328_SYS_DEV7_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT 8 22378 22379 /* sys_device7 :: Control1000X3 :: bypass_txfifo1000 [07:07] */ 22380 #define PHY84328_SYS_DEV7_CONTROL1000X3_BYPASS_TXFIFO1000_MASK 0x0080 22381 #define PHY84328_SYS_DEV7_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN 0 22382 #define PHY84328_SYS_DEV7_CONTROL1000X3_BYPASS_TXFIFO1000_BITS 1 22383 #define PHY84328_SYS_DEV7_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT 7 22384 22385 /* sys_device7 :: Control1000X3 :: freq_lock_elasticity_tx [06:06] */ 22386 #define PHY84328_SYS_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_MASK 0x0040 22387 #define PHY84328_SYS_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_ALIGN 0 22388 #define PHY84328_SYS_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_BITS 1 22389 #define PHY84328_SYS_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_SHIFT 6 22390 22391 /* sys_device7 :: Control1000X3 :: freq_lock_elasticity_rx [05:05] */ 22392 #define PHY84328_SYS_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_MASK 0x0020 22393 #define PHY84328_SYS_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_ALIGN 0 22394 #define PHY84328_SYS_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_BITS 1 22395 #define PHY84328_SYS_DEV7_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_SHIFT 5 22396 22397 /* sys_device7 :: Control1000X3 :: early_preamble_rx [04:04] */ 22398 #define PHY84328_SYS_DEV7_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK 0x0010 22399 #define PHY84328_SYS_DEV7_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN 0 22400 #define PHY84328_SYS_DEV7_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS 1 22401 #define PHY84328_SYS_DEV7_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT 4 22402 22403 /* sys_device7 :: Control1000X3 :: early_preamble_tx [03:03] */ 22404 #define PHY84328_SYS_DEV7_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK 0x0008 22405 #define PHY84328_SYS_DEV7_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN 0 22406 #define PHY84328_SYS_DEV7_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS 1 22407 #define PHY84328_SYS_DEV7_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT 3 22408 22409 /* sys_device7 :: Control1000X3 :: fifo_elasicity_tx [02:01] */ 22410 #define PHY84328_SYS_DEV7_CONTROL1000X3_FIFO_ELASICITY_TX_MASK 0x0006 22411 #define PHY84328_SYS_DEV7_CONTROL1000X3_FIFO_ELASICITY_TX_ALIGN 0 22412 #define PHY84328_SYS_DEV7_CONTROL1000X3_FIFO_ELASICITY_TX_BITS 2 22413 #define PHY84328_SYS_DEV7_CONTROL1000X3_FIFO_ELASICITY_TX_SHIFT 1 22414 22415 /* sys_device7 :: Control1000X3 :: tx_fifo_rst [00:00] */ 22416 #define PHY84328_SYS_DEV7_CONTROL1000X3_TX_FIFO_RST_MASK 0x0001 22417 #define PHY84328_SYS_DEV7_CONTROL1000X3_TX_FIFO_RST_ALIGN 0 22418 #define PHY84328_SYS_DEV7_CONTROL1000X3_TX_FIFO_RST_BITS 1 22419 #define PHY84328_SYS_DEV7_CONTROL1000X3_TX_FIFO_RST_SHIFT 0 22420 22421 22422 /**************************************************************************** 22423 * sys_device7 :: Control1000X4 22424 */ 22425 /* sys_device7 :: Control1000X4 :: reserved0 [15:14] */ 22426 #define PHY84328_SYS_DEV7_CONTROL1000X4_RESERVED0_MASK 0xc000 22427 #define PHY84328_SYS_DEV7_CONTROL1000X4_RESERVED0_ALIGN 0 22428 #define PHY84328_SYS_DEV7_CONTROL1000X4_RESERVED0_BITS 2 22429 #define PHY84328_SYS_DEV7_CONTROL1000X4_RESERVED0_SHIFT 14 22430 22431 /* sys_device7 :: Control1000X4 :: disable_resolution_err_restart [13:13] */ 22432 #define PHY84328_SYS_DEV7_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000 22433 #define PHY84328_SYS_DEV7_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0 22434 #define PHY84328_SYS_DEV7_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1 22435 #define PHY84328_SYS_DEV7_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13 22436 22437 /* sys_device7 :: Control1000X4 :: enable_last_resolution_err [12:12] */ 22438 #define PHY84328_SYS_DEV7_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000 22439 #define PHY84328_SYS_DEV7_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0 22440 #define PHY84328_SYS_DEV7_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1 22441 #define PHY84328_SYS_DEV7_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12 22442 22443 /* sys_device7 :: Control1000X4 :: tx_config_reg_sel [11:11] */ 22444 #define PHY84328_SYS_DEV7_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK 0x0800 22445 #define PHY84328_SYS_DEV7_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN 0 22446 #define PHY84328_SYS_DEV7_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS 1 22447 #define PHY84328_SYS_DEV7_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT 11 22448 22449 /* sys_device7 :: Control1000X4 :: zero_rxdgmii [10:10] */ 22450 #define PHY84328_SYS_DEV7_CONTROL1000X4_ZERO_RXDGMII_MASK 0x0400 22451 #define PHY84328_SYS_DEV7_CONTROL1000X4_ZERO_RXDGMII_ALIGN 0 22452 #define PHY84328_SYS_DEV7_CONTROL1000X4_ZERO_RXDGMII_BITS 1 22453 #define PHY84328_SYS_DEV7_CONTROL1000X4_ZERO_RXDGMII_SHIFT 10 22454 22455 /* sys_device7 :: Control1000X4 :: clear_linkdown [09:09] */ 22456 #define PHY84328_SYS_DEV7_CONTROL1000X4_CLEAR_LINKDOWN_MASK 0x0200 22457 #define PHY84328_SYS_DEV7_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN 0 22458 #define PHY84328_SYS_DEV7_CONTROL1000X4_CLEAR_LINKDOWN_BITS 1 22459 #define PHY84328_SYS_DEV7_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT 9 22460 22461 /* sys_device7 :: Control1000X4 :: latch_linkdown_enable [08:08] */ 22462 #define PHY84328_SYS_DEV7_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK 0x0100 22463 #define PHY84328_SYS_DEV7_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN 0 22464 #define PHY84328_SYS_DEV7_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS 1 22465 #define PHY84328_SYS_DEV7_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT 8 22466 22467 /* sys_device7 :: Control1000X4 :: link_force [07:07] */ 22468 #define PHY84328_SYS_DEV7_CONTROL1000X4_LINK_FORCE_MASK 0x0080 22469 #define PHY84328_SYS_DEV7_CONTROL1000X4_LINK_FORCE_ALIGN 0 22470 #define PHY84328_SYS_DEV7_CONTROL1000X4_LINK_FORCE_BITS 1 22471 #define PHY84328_SYS_DEV7_CONTROL1000X4_LINK_FORCE_SHIFT 7 22472 22473 /* sys_device7 :: Control1000X4 :: reserved1 [06:06] */ 22474 #define PHY84328_SYS_DEV7_CONTROL1000X4_RESERVED1_MASK 0x0040 22475 #define PHY84328_SYS_DEV7_CONTROL1000X4_RESERVED1_ALIGN 0 22476 #define PHY84328_SYS_DEV7_CONTROL1000X4_RESERVED1_BITS 1 22477 #define PHY84328_SYS_DEV7_CONTROL1000X4_RESERVED1_SHIFT 6 22478 22479 /* sys_device7 :: Control1000X4 :: lp_next_page_sel [05:05] */ 22480 #define PHY84328_SYS_DEV7_CONTROL1000X4_LP_NEXT_PAGE_SEL_MASK 0x0020 22481 #define PHY84328_SYS_DEV7_CONTROL1000X4_LP_NEXT_PAGE_SEL_ALIGN 0 22482 #define PHY84328_SYS_DEV7_CONTROL1000X4_LP_NEXT_PAGE_SEL_BITS 1 22483 #define PHY84328_SYS_DEV7_CONTROL1000X4_LP_NEXT_PAGE_SEL_SHIFT 5 22484 22485 /* sys_device7 :: Control1000X4 :: np_count_ClrnBp [04:04] */ 22486 #define PHY84328_SYS_DEV7_CONTROL1000X4_NP_COUNT_CLRNBP_MASK 0x0010 22487 #define PHY84328_SYS_DEV7_CONTROL1000X4_NP_COUNT_CLRNBP_ALIGN 0 22488 #define PHY84328_SYS_DEV7_CONTROL1000X4_NP_COUNT_CLRNBP_BITS 1 22489 #define PHY84328_SYS_DEV7_CONTROL1000X4_NP_COUNT_CLRNBP_SHIFT 4 22490 22491 /* sys_device7 :: Control1000X4 :: np_count_ClrnRd [03:03] */ 22492 #define PHY84328_SYS_DEV7_CONTROL1000X4_NP_COUNT_CLRNRD_MASK 0x0008 22493 #define PHY84328_SYS_DEV7_CONTROL1000X4_NP_COUNT_CLRNRD_ALIGN 0 22494 #define PHY84328_SYS_DEV7_CONTROL1000X4_NP_COUNT_CLRNRD_BITS 1 22495 #define PHY84328_SYS_DEV7_CONTROL1000X4_NP_COUNT_CLRNRD_SHIFT 3 22496 22497 /* sys_device7 :: Control1000X4 :: MiscRxStatus_sel [02:00] */ 22498 #define PHY84328_SYS_DEV7_CONTROL1000X4_MISCRXSTATUS_SEL_MASK 0x0007 22499 #define PHY84328_SYS_DEV7_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN 0 22500 #define PHY84328_SYS_DEV7_CONTROL1000X4_MISCRXSTATUS_SEL_BITS 3 22501 #define PHY84328_SYS_DEV7_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT 0 22502 22503 22504 /**************************************************************************** 22505 * sys_device7 :: Status1000X1 22506 */ 22507 /* sys_device7 :: Status1000X1 :: txfifo_err_detected [15:15] */ 22508 #define PHY84328_SYS_DEV7_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK 0x8000 22509 #define PHY84328_SYS_DEV7_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN 0 22510 #define PHY84328_SYS_DEV7_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS 1 22511 #define PHY84328_SYS_DEV7_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT 15 22512 22513 /* sys_device7 :: Status1000X1 :: rxfifo_err_detected [14:14] */ 22514 #define PHY84328_SYS_DEV7_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK 0x4000 22515 #define PHY84328_SYS_DEV7_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN 0 22516 #define PHY84328_SYS_DEV7_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS 1 22517 #define PHY84328_SYS_DEV7_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT 14 22518 22519 /* sys_device7 :: Status1000X1 :: false_carrier_detected [13:13] */ 22520 #define PHY84328_SYS_DEV7_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK 0x2000 22521 #define PHY84328_SYS_DEV7_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN 0 22522 #define PHY84328_SYS_DEV7_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS 1 22523 #define PHY84328_SYS_DEV7_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT 13 22524 22525 /* sys_device7 :: Status1000X1 :: crc_err_detected [12:12] */ 22526 #define PHY84328_SYS_DEV7_STATUS1000X1_CRC_ERR_DETECTED_MASK 0x1000 22527 #define PHY84328_SYS_DEV7_STATUS1000X1_CRC_ERR_DETECTED_ALIGN 0 22528 #define PHY84328_SYS_DEV7_STATUS1000X1_CRC_ERR_DETECTED_BITS 1 22529 #define PHY84328_SYS_DEV7_STATUS1000X1_CRC_ERR_DETECTED_SHIFT 12 22530 22531 /* sys_device7 :: Status1000X1 :: tx_err_detected [11:11] */ 22532 #define PHY84328_SYS_DEV7_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 22533 #define PHY84328_SYS_DEV7_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 22534 #define PHY84328_SYS_DEV7_STATUS1000X1_TX_ERR_DETECTED_BITS 1 22535 #define PHY84328_SYS_DEV7_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 22536 22537 /* sys_device7 :: Status1000X1 :: rx_err_detected [10:10] */ 22538 #define PHY84328_SYS_DEV7_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 22539 #define PHY84328_SYS_DEV7_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 22540 #define PHY84328_SYS_DEV7_STATUS1000X1_RX_ERR_DETECTED_BITS 1 22541 #define PHY84328_SYS_DEV7_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 22542 22543 /* sys_device7 :: Status1000X1 :: carrier_extend_err_detected [09:09] */ 22544 #define PHY84328_SYS_DEV7_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200 22545 #define PHY84328_SYS_DEV7_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0 22546 #define PHY84328_SYS_DEV7_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1 22547 #define PHY84328_SYS_DEV7_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9 22548 22549 /* sys_device7 :: Status1000X1 :: early_end_extension_detected [08:08] */ 22550 #define PHY84328_SYS_DEV7_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100 22551 #define PHY84328_SYS_DEV7_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0 22552 #define PHY84328_SYS_DEV7_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1 22553 #define PHY84328_SYS_DEV7_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8 22554 22555 /* sys_device7 :: Status1000X1 :: link_status_change [07:07] */ 22556 #define PHY84328_SYS_DEV7_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 22557 #define PHY84328_SYS_DEV7_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 22558 #define PHY84328_SYS_DEV7_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 22559 #define PHY84328_SYS_DEV7_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 22560 22561 /* sys_device7 :: Status1000X1 :: pause_resolution_rxside [06:06] */ 22562 #define PHY84328_SYS_DEV7_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0040 22563 #define PHY84328_SYS_DEV7_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 22564 #define PHY84328_SYS_DEV7_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS 1 22565 #define PHY84328_SYS_DEV7_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT 6 22566 22567 /* sys_device7 :: Status1000X1 :: pause_resolution_txside [05:05] */ 22568 #define PHY84328_SYS_DEV7_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0020 22569 #define PHY84328_SYS_DEV7_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 22570 #define PHY84328_SYS_DEV7_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS 1 22571 #define PHY84328_SYS_DEV7_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT 5 22572 22573 /* sys_device7 :: Status1000X1 :: speed_status [04:03] */ 22574 #define PHY84328_SYS_DEV7_STATUS1000X1_SPEED_STATUS_MASK 0x0018 22575 #define PHY84328_SYS_DEV7_STATUS1000X1_SPEED_STATUS_ALIGN 0 22576 #define PHY84328_SYS_DEV7_STATUS1000X1_SPEED_STATUS_BITS 2 22577 #define PHY84328_SYS_DEV7_STATUS1000X1_SPEED_STATUS_SHIFT 3 22578 22579 /* sys_device7 :: Status1000X1 :: duplex_status [02:02] */ 22580 #define PHY84328_SYS_DEV7_STATUS1000X1_DUPLEX_STATUS_MASK 0x0004 22581 #define PHY84328_SYS_DEV7_STATUS1000X1_DUPLEX_STATUS_ALIGN 0 22582 #define PHY84328_SYS_DEV7_STATUS1000X1_DUPLEX_STATUS_BITS 1 22583 #define PHY84328_SYS_DEV7_STATUS1000X1_DUPLEX_STATUS_SHIFT 2 22584 22585 /* sys_device7 :: Status1000X1 :: link_status [01:01] */ 22586 #define PHY84328_SYS_DEV7_STATUS1000X1_LINK_STATUS_MASK 0x0002 22587 #define PHY84328_SYS_DEV7_STATUS1000X1_LINK_STATUS_ALIGN 0 22588 #define PHY84328_SYS_DEV7_STATUS1000X1_LINK_STATUS_BITS 1 22589 #define PHY84328_SYS_DEV7_STATUS1000X1_LINK_STATUS_SHIFT 1 22590 22591 /* sys_device7 :: Status1000X1 :: sgmii_mode [00:00] */ 22592 #define PHY84328_SYS_DEV7_STATUS1000X1_SGMII_MODE_MASK 0x0001 22593 #define PHY84328_SYS_DEV7_STATUS1000X1_SGMII_MODE_ALIGN 0 22594 #define PHY84328_SYS_DEV7_STATUS1000X1_SGMII_MODE_BITS 1 22595 #define PHY84328_SYS_DEV7_STATUS1000X1_SGMII_MODE_SHIFT 0 22596 22597 22598 /**************************************************************************** 22599 * sys_device7 :: Status1000X2 22600 */ 22601 /* sys_device7 :: Status1000X2 :: sgmii_mode_change [15:15] */ 22602 #define PHY84328_SYS_DEV7_STATUS1000X2_SGMII_MODE_CHANGE_MASK 0x8000 22603 #define PHY84328_SYS_DEV7_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN 0 22604 #define PHY84328_SYS_DEV7_STATUS1000X2_SGMII_MODE_CHANGE_BITS 1 22605 #define PHY84328_SYS_DEV7_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT 15 22606 22607 /* sys_device7 :: Status1000X2 :: consistency_mismatch [14:14] */ 22608 #define PHY84328_SYS_DEV7_STATUS1000X2_CONSISTENCY_MISMATCH_MASK 0x4000 22609 #define PHY84328_SYS_DEV7_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN 0 22610 #define PHY84328_SYS_DEV7_STATUS1000X2_CONSISTENCY_MISMATCH_BITS 1 22611 #define PHY84328_SYS_DEV7_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT 14 22612 22613 /* sys_device7 :: Status1000X2 :: autoneg_resolution_err [13:13] */ 22614 #define PHY84328_SYS_DEV7_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK 0x2000 22615 #define PHY84328_SYS_DEV7_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN 0 22616 #define PHY84328_SYS_DEV7_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS 1 22617 #define PHY84328_SYS_DEV7_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT 13 22618 22619 /* sys_device7 :: Status1000X2 :: sgmii_selector_mismatch [12:12] */ 22620 #define PHY84328_SYS_DEV7_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK 0x1000 22621 #define PHY84328_SYS_DEV7_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN 0 22622 #define PHY84328_SYS_DEV7_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS 1 22623 #define PHY84328_SYS_DEV7_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT 12 22624 22625 /* sys_device7 :: Status1000X2 :: sync_status_fail [11:11] */ 22626 #define PHY84328_SYS_DEV7_STATUS1000X2_SYNC_STATUS_FAIL_MASK 0x0800 22627 #define PHY84328_SYS_DEV7_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN 0 22628 #define PHY84328_SYS_DEV7_STATUS1000X2_SYNC_STATUS_FAIL_BITS 1 22629 #define PHY84328_SYS_DEV7_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT 11 22630 22631 /* sys_device7 :: Status1000X2 :: sync_status_ok [10:10] */ 22632 #define PHY84328_SYS_DEV7_STATUS1000X2_SYNC_STATUS_OK_MASK 0x0400 22633 #define PHY84328_SYS_DEV7_STATUS1000X2_SYNC_STATUS_OK_ALIGN 0 22634 #define PHY84328_SYS_DEV7_STATUS1000X2_SYNC_STATUS_OK_BITS 1 22635 #define PHY84328_SYS_DEV7_STATUS1000X2_SYNC_STATUS_OK_SHIFT 10 22636 22637 /* sys_device7 :: Status1000X2 :: rudi_c [09:09] */ 22638 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_C_MASK 0x0200 22639 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_C_ALIGN 0 22640 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_C_BITS 1 22641 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_C_SHIFT 9 22642 22643 /* sys_device7 :: Status1000X2 :: rudi_I [08:08] */ 22644 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_I_MASK 0x0100 22645 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_I_ALIGN 0 22646 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_I_BITS 1 22647 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_I_SHIFT 8 22648 22649 /* sys_device7 :: Status1000X2 :: rudi_invalid [07:07] */ 22650 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_INVALID_MASK 0x0080 22651 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_INVALID_ALIGN 0 22652 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_INVALID_BITS 1 22653 #define PHY84328_SYS_DEV7_STATUS1000X2_RUDI_INVALID_SHIFT 7 22654 22655 /* sys_device7 :: Status1000X2 :: linkDown_syncLoss [06:06] */ 22656 #define PHY84328_SYS_DEV7_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK 0x0040 22657 #define PHY84328_SYS_DEV7_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN 0 22658 #define PHY84328_SYS_DEV7_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS 1 22659 #define PHY84328_SYS_DEV7_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT 6 22660 22661 /* sys_device7 :: Status1000X2 :: idle_detect_state [05:05] */ 22662 #define PHY84328_SYS_DEV7_STATUS1000X2_IDLE_DETECT_STATE_MASK 0x0020 22663 #define PHY84328_SYS_DEV7_STATUS1000X2_IDLE_DETECT_STATE_ALIGN 0 22664 #define PHY84328_SYS_DEV7_STATUS1000X2_IDLE_DETECT_STATE_BITS 1 22665 #define PHY84328_SYS_DEV7_STATUS1000X2_IDLE_DETECT_STATE_SHIFT 5 22666 22667 /* sys_device7 :: Status1000X2 :: complete_acknowledge_state [04:04] */ 22668 #define PHY84328_SYS_DEV7_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010 22669 #define PHY84328_SYS_DEV7_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0 22670 #define PHY84328_SYS_DEV7_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1 22671 #define PHY84328_SYS_DEV7_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4 22672 22673 /* sys_device7 :: Status1000X2 :: acknowledge_detect_state [03:03] */ 22674 #define PHY84328_SYS_DEV7_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK 0x0008 22675 #define PHY84328_SYS_DEV7_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0 22676 #define PHY84328_SYS_DEV7_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS 1 22677 #define PHY84328_SYS_DEV7_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3 22678 22679 /* sys_device7 :: Status1000X2 :: ability_detect_state [02:02] */ 22680 #define PHY84328_SYS_DEV7_STATUS1000X2_ABILITY_DETECT_STATE_MASK 0x0004 22681 #define PHY84328_SYS_DEV7_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN 0 22682 #define PHY84328_SYS_DEV7_STATUS1000X2_ABILITY_DETECT_STATE_BITS 1 22683 #define PHY84328_SYS_DEV7_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT 2 22684 22685 /* sys_device7 :: Status1000X2 :: reserved0 [01:01] */ 22686 #define PHY84328_SYS_DEV7_STATUS1000X2_RESERVED0_MASK 0x0002 22687 #define PHY84328_SYS_DEV7_STATUS1000X2_RESERVED0_ALIGN 0 22688 #define PHY84328_SYS_DEV7_STATUS1000X2_RESERVED0_BITS 1 22689 #define PHY84328_SYS_DEV7_STATUS1000X2_RESERVED0_SHIFT 1 22690 22691 /* sys_device7 :: Status1000X2 :: an_enable_state [00:00] */ 22692 #define PHY84328_SYS_DEV7_STATUS1000X2_AN_ENABLE_STATE_MASK 0x0001 22693 #define PHY84328_SYS_DEV7_STATUS1000X2_AN_ENABLE_STATE_ALIGN 0 22694 #define PHY84328_SYS_DEV7_STATUS1000X2_AN_ENABLE_STATE_BITS 1 22695 #define PHY84328_SYS_DEV7_STATUS1000X2_AN_ENABLE_STATE_SHIFT 0 22696 22697 22698 /**************************************************************************** 22699 * sys_device7 :: Status1000X3 22700 */ 22701 /* sys_device7 :: Status1000X3 :: reserved0 [15:14] */ 22702 #define PHY84328_SYS_DEV7_STATUS1000X3_RESERVED0_MASK 0xc000 22703 #define PHY84328_SYS_DEV7_STATUS1000X3_RESERVED0_ALIGN 0 22704 #define PHY84328_SYS_DEV7_STATUS1000X3_RESERVED0_BITS 2 22705 #define PHY84328_SYS_DEV7_STATUS1000X3_RESERVED0_SHIFT 14 22706 22707 /* sys_device7 :: Status1000X3 :: tx_os_fifo_error [13:13] */ 22708 #define PHY84328_SYS_DEV7_STATUS1000X3_TX_OS_FIFO_ERROR_MASK 0x2000 22709 #define PHY84328_SYS_DEV7_STATUS1000X3_TX_OS_FIFO_ERROR_ALIGN 0 22710 #define PHY84328_SYS_DEV7_STATUS1000X3_TX_OS_FIFO_ERROR_BITS 1 22711 #define PHY84328_SYS_DEV7_STATUS1000X3_TX_OS_FIFO_ERROR_SHIFT 13 22712 22713 /* sys_device7 :: Status1000X3 :: pd_park_an [12:12] */ 22714 #define PHY84328_SYS_DEV7_STATUS1000X3_PD_PARK_AN_MASK 0x1000 22715 #define PHY84328_SYS_DEV7_STATUS1000X3_PD_PARK_AN_ALIGN 0 22716 #define PHY84328_SYS_DEV7_STATUS1000X3_PD_PARK_AN_BITS 1 22717 #define PHY84328_SYS_DEV7_STATUS1000X3_PD_PARK_AN_SHIFT 12 22718 22719 /* sys_device7 :: Status1000X3 :: remotePhy_autosel [11:11] */ 22720 #define PHY84328_SYS_DEV7_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK 0x0800 22721 #define PHY84328_SYS_DEV7_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN 0 22722 #define PHY84328_SYS_DEV7_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS 1 22723 #define PHY84328_SYS_DEV7_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT 11 22724 22725 /* sys_device7 :: Status1000X3 :: latch_linkdown [10:10] */ 22726 #define PHY84328_SYS_DEV7_STATUS1000X3_LATCH_LINKDOWN_MASK 0x0400 22727 #define PHY84328_SYS_DEV7_STATUS1000X3_LATCH_LINKDOWN_ALIGN 0 22728 #define PHY84328_SYS_DEV7_STATUS1000X3_LATCH_LINKDOWN_BITS 1 22729 #define PHY84328_SYS_DEV7_STATUS1000X3_LATCH_LINKDOWN_SHIFT 10 22730 22731 /* sys_device7 :: Status1000X3 :: sd_filter [09:09] */ 22732 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_FILTER_MASK 0x0200 22733 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_FILTER_ALIGN 0 22734 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_FILTER_BITS 1 22735 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_FILTER_SHIFT 9 22736 22737 /* sys_device7 :: Status1000X3 :: sd_mux [08:08] */ 22738 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_MUX_MASK 0x0100 22739 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_MUX_ALIGN 0 22740 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_MUX_BITS 1 22741 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_MUX_SHIFT 8 22742 22743 /* sys_device7 :: Status1000X3 :: sd_filter_chg [07:07] */ 22744 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_FILTER_CHG_MASK 0x0080 22745 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_FILTER_CHG_ALIGN 0 22746 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_FILTER_CHG_BITS 1 22747 #define PHY84328_SYS_DEV7_STATUS1000X3_SD_FILTER_CHG_SHIFT 7 22748 22749 /* sys_device7 :: Status1000X3 :: reserved1 [06:00] */ 22750 #define PHY84328_SYS_DEV7_STATUS1000X3_RESERVED1_MASK 0x007f 22751 #define PHY84328_SYS_DEV7_STATUS1000X3_RESERVED1_ALIGN 0 22752 #define PHY84328_SYS_DEV7_STATUS1000X3_RESERVED1_BITS 7 22753 #define PHY84328_SYS_DEV7_STATUS1000X3_RESERVED1_SHIFT 0 22754 22755 22756 /**************************************************************************** 22757 * sys_device7 :: BadCodeGroup 22758 */ 22759 /* sys_device7 :: BadCodeGroup :: badCodeGroups [15:08] */ 22760 #define PHY84328_SYS_DEV7_BADCODEGROUP_BADCODEGROUPS_MASK 0xff00 22761 #define PHY84328_SYS_DEV7_BADCODEGROUP_BADCODEGROUPS_ALIGN 0 22762 #define PHY84328_SYS_DEV7_BADCODEGROUP_BADCODEGROUPS_BITS 8 22763 #define PHY84328_SYS_DEV7_BADCODEGROUP_BADCODEGROUPS_SHIFT 8 22764 22765 /* sys_device7 :: BadCodeGroup :: reserved0 [07:00] */ 22766 #define PHY84328_SYS_DEV7_BADCODEGROUP_RESERVED0_MASK 0x00ff 22767 #define PHY84328_SYS_DEV7_BADCODEGROUP_RESERVED0_ALIGN 0 22768 #define PHY84328_SYS_DEV7_BADCODEGROUP_RESERVED0_BITS 8 22769 #define PHY84328_SYS_DEV7_BADCODEGROUP_RESERVED0_SHIFT 0 22770 22771 22772 /**************************************************************************** 22773 * sys_device7 :: Misc1 22774 */ 22775 /* sys_device7 :: Misc1 :: refclk_sel [15:13] */ 22776 #define PHY84328_SYS_DEV7_MISC1_REFCLK_SEL_MASK 0xe000 22777 #define PHY84328_SYS_DEV7_MISC1_REFCLK_SEL_ALIGN 0 22778 #define PHY84328_SYS_DEV7_MISC1_REFCLK_SEL_BITS 3 22779 #define PHY84328_SYS_DEV7_MISC1_REFCLK_SEL_SHIFT 13 22780 22781 /* sys_device7 :: Misc1 :: force_pll_mode_afe_sel [12:12] */ 22782 #define PHY84328_SYS_DEV7_MISC1_FORCE_PLL_MODE_AFE_SEL_MASK 0x1000 22783 #define PHY84328_SYS_DEV7_MISC1_FORCE_PLL_MODE_AFE_SEL_ALIGN 0 22784 #define PHY84328_SYS_DEV7_MISC1_FORCE_PLL_MODE_AFE_SEL_BITS 1 22785 #define PHY84328_SYS_DEV7_MISC1_FORCE_PLL_MODE_AFE_SEL_SHIFT 12 22786 22787 /* sys_device7 :: Misc1 :: force_pll_mode_afe [11:08] */ 22788 #define PHY84328_SYS_DEV7_MISC1_FORCE_PLL_MODE_AFE_MASK 0x0f00 22789 #define PHY84328_SYS_DEV7_MISC1_FORCE_PLL_MODE_AFE_ALIGN 0 22790 #define PHY84328_SYS_DEV7_MISC1_FORCE_PLL_MODE_AFE_BITS 4 22791 #define PHY84328_SYS_DEV7_MISC1_FORCE_PLL_MODE_AFE_SHIFT 8 22792 22793 /* sys_device7 :: Misc1 :: force_tick0_sw2 [07:07] */ 22794 #define PHY84328_SYS_DEV7_MISC1_FORCE_TICK0_SW2_MASK 0x0080 22795 #define PHY84328_SYS_DEV7_MISC1_FORCE_TICK0_SW2_ALIGN 0 22796 #define PHY84328_SYS_DEV7_MISC1_FORCE_TICK0_SW2_BITS 1 22797 #define PHY84328_SYS_DEV7_MISC1_FORCE_TICK0_SW2_SHIFT 7 22798 22799 /* sys_device7 :: Misc1 :: tx_underrun_1000_dis [06:06] */ 22800 #define PHY84328_SYS_DEV7_MISC1_TX_UNDERRUN_1000_DIS_MASK 0x0040 22801 #define PHY84328_SYS_DEV7_MISC1_TX_UNDERRUN_1000_DIS_ALIGN 0 22802 #define PHY84328_SYS_DEV7_MISC1_TX_UNDERRUN_1000_DIS_BITS 1 22803 #define PHY84328_SYS_DEV7_MISC1_TX_UNDERRUN_1000_DIS_SHIFT 6 22804 22805 /* sys_device7 :: Misc1 :: force_ln_mode [05:05] */ 22806 #define PHY84328_SYS_DEV7_MISC1_FORCE_LN_MODE_MASK 0x0020 22807 #define PHY84328_SYS_DEV7_MISC1_FORCE_LN_MODE_ALIGN 0 22808 #define PHY84328_SYS_DEV7_MISC1_FORCE_LN_MODE_BITS 1 22809 #define PHY84328_SYS_DEV7_MISC1_FORCE_LN_MODE_SHIFT 5 22810 22811 /* sys_device7 :: Misc1 :: force_speed [04:00] */ 22812 #define PHY84328_SYS_DEV7_MISC1_FORCE_SPEED_MASK 0x001f 22813 #define PHY84328_SYS_DEV7_MISC1_FORCE_SPEED_ALIGN 0 22814 #define PHY84328_SYS_DEV7_MISC1_FORCE_SPEED_BITS 5 22815 #define PHY84328_SYS_DEV7_MISC1_FORCE_SPEED_SHIFT 0 22816 22817 22818 /**************************************************************************** 22819 * sys_device7 :: Misc2 22820 */ 22821 /* sys_device7 :: Misc2 :: rxckpl_sel_combo [15:15] */ 22822 #define PHY84328_SYS_DEV7_MISC2_RXCKPL_SEL_COMBO_MASK 0x8000 22823 #define PHY84328_SYS_DEV7_MISC2_RXCKPL_SEL_COMBO_ALIGN 0 22824 #define PHY84328_SYS_DEV7_MISC2_RXCKPL_SEL_COMBO_BITS 1 22825 #define PHY84328_SYS_DEV7_MISC2_RXCKPL_SEL_COMBO_SHIFT 15 22826 22827 /* sys_device7 :: Misc2 :: rxck_mii_gen_sel_force [14:14] */ 22828 #define PHY84328_SYS_DEV7_MISC2_RXCK_MII_GEN_SEL_FORCE_MASK 0x4000 22829 #define PHY84328_SYS_DEV7_MISC2_RXCK_MII_GEN_SEL_FORCE_ALIGN 0 22830 #define PHY84328_SYS_DEV7_MISC2_RXCK_MII_GEN_SEL_FORCE_BITS 1 22831 #define PHY84328_SYS_DEV7_MISC2_RXCK_MII_GEN_SEL_FORCE_SHIFT 14 22832 22833 /* sys_device7 :: Misc2 :: rxck_mii_gen_sel_val [13:13] */ 22834 #define PHY84328_SYS_DEV7_MISC2_RXCK_MII_GEN_SEL_VAL_MASK 0x2000 22835 #define PHY84328_SYS_DEV7_MISC2_RXCK_MII_GEN_SEL_VAL_ALIGN 0 22836 #define PHY84328_SYS_DEV7_MISC2_RXCK_MII_GEN_SEL_VAL_BITS 1 22837 #define PHY84328_SYS_DEV7_MISC2_RXCK_MII_GEN_SEL_VAL_SHIFT 13 22838 22839 /* sys_device7 :: Misc2 :: rlpbk_sw_force [12:12] */ 22840 #define PHY84328_SYS_DEV7_MISC2_RLPBK_SW_FORCE_MASK 0x1000 22841 #define PHY84328_SYS_DEV7_MISC2_RLPBK_SW_FORCE_ALIGN 0 22842 #define PHY84328_SYS_DEV7_MISC2_RLPBK_SW_FORCE_BITS 1 22843 #define PHY84328_SYS_DEV7_MISC2_RLPBK_SW_FORCE_SHIFT 12 22844 22845 /* sys_device7 :: Misc2 :: rlpbk_RxRst_en [11:11] */ 22846 #define PHY84328_SYS_DEV7_MISC2_RLPBK_RXRST_EN_MASK 0x0800 22847 #define PHY84328_SYS_DEV7_MISC2_RLPBK_RXRST_EN_ALIGN 0 22848 #define PHY84328_SYS_DEV7_MISC2_RLPBK_RXRST_EN_BITS 1 22849 #define PHY84328_SYS_DEV7_MISC2_RLPBK_RXRST_EN_SHIFT 11 22850 22851 /* sys_device7 :: Misc2 :: clkSigdet_bypass [10:10] */ 22852 #define PHY84328_SYS_DEV7_MISC2_CLKSIGDET_BYPASS_MASK 0x0400 22853 #define PHY84328_SYS_DEV7_MISC2_CLKSIGDET_BYPASS_ALIGN 0 22854 #define PHY84328_SYS_DEV7_MISC2_CLKSIGDET_BYPASS_BITS 1 22855 #define PHY84328_SYS_DEV7_MISC2_CLKSIGDET_BYPASS_SHIFT 10 22856 22857 /* sys_device7 :: Misc2 :: clk41_bypass [09:09] */ 22858 #define PHY84328_SYS_DEV7_MISC2_CLK41_BYPASS_MASK 0x0200 22859 #define PHY84328_SYS_DEV7_MISC2_CLK41_BYPASS_ALIGN 0 22860 #define PHY84328_SYS_DEV7_MISC2_CLK41_BYPASS_BITS 1 22861 #define PHY84328_SYS_DEV7_MISC2_CLK41_BYPASS_SHIFT 9 22862 22863 /* sys_device7 :: Misc2 :: miiGmiiDly_en [08:08] */ 22864 #define PHY84328_SYS_DEV7_MISC2_MIIGMIIDLY_EN_MASK 0x0100 22865 #define PHY84328_SYS_DEV7_MISC2_MIIGMIIDLY_EN_ALIGN 0 22866 #define PHY84328_SYS_DEV7_MISC2_MIIGMIIDLY_EN_BITS 1 22867 #define PHY84328_SYS_DEV7_MISC2_MIIGMIIDLY_EN_SHIFT 8 22868 22869 /* sys_device7 :: Misc2 :: miiGmiiMux_en [07:07] */ 22870 #define PHY84328_SYS_DEV7_MISC2_MIIGMIIMUX_EN_MASK 0x0080 22871 #define PHY84328_SYS_DEV7_MISC2_MIIGMIIMUX_EN_ALIGN 0 22872 #define PHY84328_SYS_DEV7_MISC2_MIIGMIIMUX_EN_BITS 1 22873 #define PHY84328_SYS_DEV7_MISC2_MIIGMIIMUX_EN_SHIFT 7 22874 22875 /* sys_device7 :: Misc2 :: KX_cl73_an_en [06:06] */ 22876 #define PHY84328_SYS_DEV7_MISC2_KX_CL73_AN_EN_MASK 0x0040 22877 #define PHY84328_SYS_DEV7_MISC2_KX_CL73_AN_EN_ALIGN 0 22878 #define PHY84328_SYS_DEV7_MISC2_KX_CL73_AN_EN_BITS 1 22879 #define PHY84328_SYS_DEV7_MISC2_KX_CL73_AN_EN_SHIFT 6 22880 22881 /* sys_device7 :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */ 22882 #define PHY84328_SYS_DEV7_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK 0x0020 22883 #define PHY84328_SYS_DEV7_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN 0 22884 #define PHY84328_SYS_DEV7_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS 1 22885 #define PHY84328_SYS_DEV7_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT 5 22886 22887 /* sys_device7 :: Misc2 :: fifo_err_cya [04:04] */ 22888 #define PHY84328_SYS_DEV7_MISC2_FIFO_ERR_CYA_MASK 0x0010 22889 #define PHY84328_SYS_DEV7_MISC2_FIFO_ERR_CYA_ALIGN 0 22890 #define PHY84328_SYS_DEV7_MISC2_FIFO_ERR_CYA_BITS 1 22891 #define PHY84328_SYS_DEV7_MISC2_FIFO_ERR_CYA_SHIFT 4 22892 22893 /* sys_device7 :: Misc2 :: an_txdisablePhase [03:03] */ 22894 #define PHY84328_SYS_DEV7_MISC2_AN_TXDISABLEPHASE_MASK 0x0008 22895 #define PHY84328_SYS_DEV7_MISC2_AN_TXDISABLEPHASE_ALIGN 0 22896 #define PHY84328_SYS_DEV7_MISC2_AN_TXDISABLEPHASE_BITS 1 22897 #define PHY84328_SYS_DEV7_MISC2_AN_TXDISABLEPHASE_SHIFT 3 22898 22899 /* sys_device7 :: Misc2 :: an_rxSeqStartDis [02:02] */ 22900 #define PHY84328_SYS_DEV7_MISC2_AN_RXSEQSTARTDIS_MASK 0x0004 22901 #define PHY84328_SYS_DEV7_MISC2_AN_RXSEQSTARTDIS_ALIGN 0 22902 #define PHY84328_SYS_DEV7_MISC2_AN_RXSEQSTARTDIS_BITS 1 22903 #define PHY84328_SYS_DEV7_MISC2_AN_RXSEQSTARTDIS_SHIFT 2 22904 22905 /* sys_device7 :: Misc2 :: an_txdisable_ln [01:01] */ 22906 #define PHY84328_SYS_DEV7_MISC2_AN_TXDISABLE_LN_MASK 0x0002 22907 #define PHY84328_SYS_DEV7_MISC2_AN_TXDISABLE_LN_ALIGN 0 22908 #define PHY84328_SYS_DEV7_MISC2_AN_TXDISABLE_LN_BITS 1 22909 #define PHY84328_SYS_DEV7_MISC2_AN_TXDISABLE_LN_SHIFT 1 22910 22911 /* sys_device7 :: Misc2 :: an_deadTrap [00:00] */ 22912 #define PHY84328_SYS_DEV7_MISC2_AN_DEADTRAP_MASK 0x0001 22913 #define PHY84328_SYS_DEV7_MISC2_AN_DEADTRAP_ALIGN 0 22914 #define PHY84328_SYS_DEV7_MISC2_AN_DEADTRAP_BITS 1 22915 #define PHY84328_SYS_DEV7_MISC2_AN_DEADTRAP_SHIFT 0 22916 22917 22918 /**************************************************************************** 22919 * sys_device7 :: PatGenCtrl 22920 */ 22921 /* sys_device7 :: PatGenCtrl :: patgen_lpi_en [15:15] */ 22922 #define PHY84328_SYS_DEV7_PATGENCTRL_PATGEN_LPI_EN_MASK 0x8000 22923 #define PHY84328_SYS_DEV7_PATGENCTRL_PATGEN_LPI_EN_ALIGN 0 22924 #define PHY84328_SYS_DEV7_PATGENCTRL_PATGEN_LPI_EN_BITS 1 22925 #define PHY84328_SYS_DEV7_PATGENCTRL_PATGEN_LPI_EN_SHIFT 15 22926 22927 /* sys_device7 :: PatGenCtrl :: tx_err [14:14] */ 22928 #define PHY84328_SYS_DEV7_PATGENCTRL_TX_ERR_MASK 0x4000 22929 #define PHY84328_SYS_DEV7_PATGENCTRL_TX_ERR_ALIGN 0 22930 #define PHY84328_SYS_DEV7_PATGENCTRL_TX_ERR_BITS 1 22931 #define PHY84328_SYS_DEV7_PATGENCTRL_TX_ERR_SHIFT 14 22932 22933 /* sys_device7 :: PatGenCtrl :: skip_crc [13:13] */ 22934 #define PHY84328_SYS_DEV7_PATGENCTRL_SKIP_CRC_MASK 0x2000 22935 #define PHY84328_SYS_DEV7_PATGENCTRL_SKIP_CRC_ALIGN 0 22936 #define PHY84328_SYS_DEV7_PATGENCTRL_SKIP_CRC_BITS 1 22937 #define PHY84328_SYS_DEV7_PATGENCTRL_SKIP_CRC_SHIFT 13 22938 22939 /* sys_device7 :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */ 22940 #define PHY84328_SYS_DEV7_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000 22941 #define PHY84328_SYS_DEV7_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0 22942 #define PHY84328_SYS_DEV7_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1 22943 #define PHY84328_SYS_DEV7_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12 22944 22945 /* sys_device7 :: PatGenCtrl :: ipg_select [11:09] */ 22946 #define PHY84328_SYS_DEV7_PATGENCTRL_IPG_SELECT_MASK 0x0e00 22947 #define PHY84328_SYS_DEV7_PATGENCTRL_IPG_SELECT_ALIGN 0 22948 #define PHY84328_SYS_DEV7_PATGENCTRL_IPG_SELECT_BITS 3 22949 #define PHY84328_SYS_DEV7_PATGENCTRL_IPG_SELECT_SHIFT 9 22950 22951 /* sys_device7 :: PatGenCtrl :: pkt_size [08:03] */ 22952 #define PHY84328_SYS_DEV7_PATGENCTRL_PKT_SIZE_MASK 0x01f8 22953 #define PHY84328_SYS_DEV7_PATGENCTRL_PKT_SIZE_ALIGN 0 22954 #define PHY84328_SYS_DEV7_PATGENCTRL_PKT_SIZE_BITS 6 22955 #define PHY84328_SYS_DEV7_PATGENCTRL_PKT_SIZE_SHIFT 3 22956 22957 /* sys_device7 :: PatGenCtrl :: single_pass_mode [02:02] */ 22958 #define PHY84328_SYS_DEV7_PATGENCTRL_SINGLE_PASS_MODE_MASK 0x0004 22959 #define PHY84328_SYS_DEV7_PATGENCTRL_SINGLE_PASS_MODE_ALIGN 0 22960 #define PHY84328_SYS_DEV7_PATGENCTRL_SINGLE_PASS_MODE_BITS 1 22961 #define PHY84328_SYS_DEV7_PATGENCTRL_SINGLE_PASS_MODE_SHIFT 2 22962 22963 /* sys_device7 :: PatGenCtrl :: run_pattern_gen [01:01] */ 22964 #define PHY84328_SYS_DEV7_PATGENCTRL_RUN_PATTERN_GEN_MASK 0x0002 22965 #define PHY84328_SYS_DEV7_PATGENCTRL_RUN_PATTERN_GEN_ALIGN 0 22966 #define PHY84328_SYS_DEV7_PATGENCTRL_RUN_PATTERN_GEN_BITS 1 22967 #define PHY84328_SYS_DEV7_PATGENCTRL_RUN_PATTERN_GEN_SHIFT 1 22968 22969 /* sys_device7 :: PatGenCtrl :: sel_pattern_gen_data [00:00] */ 22970 #define PHY84328_SYS_DEV7_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK 0x0001 22971 #define PHY84328_SYS_DEV7_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN 0 22972 #define PHY84328_SYS_DEV7_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS 1 22973 #define PHY84328_SYS_DEV7_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT 0 22974 22975 22976 /**************************************************************************** 22977 * sys_device7 :: PatGenStat 22978 */ 22979 /* sys_device7 :: PatGenStat :: reserved0 [15:04] */ 22980 #define PHY84328_SYS_DEV7_PATGENSTAT_RESERVED0_MASK 0xfff0 22981 #define PHY84328_SYS_DEV7_PATGENSTAT_RESERVED0_ALIGN 0 22982 #define PHY84328_SYS_DEV7_PATGENSTAT_RESERVED0_BITS 12 22983 #define PHY84328_SYS_DEV7_PATGENSTAT_RESERVED0_SHIFT 4 22984 22985 /* sys_device7 :: PatGenStat :: pattern_gen_active [03:03] */ 22986 #define PHY84328_SYS_DEV7_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK 0x0008 22987 #define PHY84328_SYS_DEV7_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN 0 22988 #define PHY84328_SYS_DEV7_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS 1 22989 #define PHY84328_SYS_DEV7_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT 3 22990 22991 /* sys_device7 :: PatGenStat :: pattern_gen_fsm [02:00] */ 22992 #define PHY84328_SYS_DEV7_PATGENSTAT_PATTERN_GEN_FSM_MASK 0x0007 22993 #define PHY84328_SYS_DEV7_PATGENSTAT_PATTERN_GEN_FSM_ALIGN 0 22994 #define PHY84328_SYS_DEV7_PATGENSTAT_PATTERN_GEN_FSM_BITS 3 22995 #define PHY84328_SYS_DEV7_PATGENSTAT_PATTERN_GEN_FSM_SHIFT 0 22996 22997 22998 /**************************************************************************** 22999 * sys_device7 :: TestMode 23000 */ 23001 /* sys_device7 :: TestMode :: disable_reset_cnt [15:15] */ 23002 #define PHY84328_SYS_DEV7_TESTMODE_DISABLE_RESET_CNT_MASK 0x8000 23003 #define PHY84328_SYS_DEV7_TESTMODE_DISABLE_RESET_CNT_ALIGN 0 23004 #define PHY84328_SYS_DEV7_TESTMODE_DISABLE_RESET_CNT_BITS 1 23005 #define PHY84328_SYS_DEV7_TESTMODE_DISABLE_RESET_CNT_SHIFT 15 23006 23007 /* sys_device7 :: TestMode :: clear_packet_counters [14:14] */ 23008 #define PHY84328_SYS_DEV7_TESTMODE_CLEAR_PACKET_COUNTERS_MASK 0x4000 23009 #define PHY84328_SYS_DEV7_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN 0 23010 #define PHY84328_SYS_DEV7_TESTMODE_CLEAR_PACKET_COUNTERS_BITS 1 23011 #define PHY84328_SYS_DEV7_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT 14 23012 23013 /* sys_device7 :: TestMode :: reserved0 [13:05] */ 23014 #define PHY84328_SYS_DEV7_TESTMODE_RESERVED0_MASK 0x3fe0 23015 #define PHY84328_SYS_DEV7_TESTMODE_RESERVED0_ALIGN 0 23016 #define PHY84328_SYS_DEV7_TESTMODE_RESERVED0_BITS 9 23017 #define PHY84328_SYS_DEV7_TESTMODE_RESERVED0_SHIFT 5 23018 23019 /* sys_device7 :: TestMode :: fifo_fsm_cya_rx [04:04] */ 23020 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_FSM_CYA_RX_MASK 0x0010 23021 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_FSM_CYA_RX_ALIGN 0 23022 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_FSM_CYA_RX_BITS 1 23023 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_FSM_CYA_RX_SHIFT 4 23024 23025 /* sys_device7 :: TestMode :: dig1000x_afrst_cya [03:03] */ 23026 #define PHY84328_SYS_DEV7_TESTMODE_DIG1000X_AFRST_CYA_MASK 0x0008 23027 #define PHY84328_SYS_DEV7_TESTMODE_DIG1000X_AFRST_CYA_ALIGN 0 23028 #define PHY84328_SYS_DEV7_TESTMODE_DIG1000X_AFRST_CYA_BITS 1 23029 #define PHY84328_SYS_DEV7_TESTMODE_DIG1000X_AFRST_CYA_SHIFT 3 23030 23031 /* sys_device7 :: TestMode :: fifo_elasicity_rx [02:01] */ 23032 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_ELASICITY_RX_MASK 0x0006 23033 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_ELASICITY_RX_ALIGN 0 23034 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_ELASICITY_RX_BITS 2 23035 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_ELASICITY_RX_SHIFT 1 23036 23037 /* sys_device7 :: TestMode :: fifo_ipg_rx_cya [00:00] */ 23038 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_IPG_RX_CYA_MASK 0x0001 23039 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_IPG_RX_CYA_ALIGN 0 23040 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_IPG_RX_CYA_BITS 1 23041 #define PHY84328_SYS_DEV7_TESTMODE_FIFO_IPG_RX_CYA_SHIFT 0 23042 23043 23044 /**************************************************************************** 23045 * sys_device7 :: TxPktCnt 23046 */ 23047 /* sys_device7 :: TxPktCnt :: TxPktCnt [15:00] */ 23048 #define PHY84328_SYS_DEV7_TXPKTCNT_TXPKTCNT_MASK 0xffff 23049 #define PHY84328_SYS_DEV7_TXPKTCNT_TXPKTCNT_ALIGN 0 23050 #define PHY84328_SYS_DEV7_TXPKTCNT_TXPKTCNT_BITS 16 23051 #define PHY84328_SYS_DEV7_TXPKTCNT_TXPKTCNT_SHIFT 0 23052 23053 23054 /**************************************************************************** 23055 * sys_device7 :: RxPktCnt 23056 */ 23057 /* sys_device7 :: RxPktCnt :: RxPktCnt [15:00] */ 23058 #define PHY84328_SYS_DEV7_RXPKTCNT_RXPKTCNT_MASK 0xffff 23059 #define PHY84328_SYS_DEV7_RXPKTCNT_RXPKTCNT_ALIGN 0 23060 #define PHY84328_SYS_DEV7_RXPKTCNT_RXPKTCNT_BITS 16 23061 #define PHY84328_SYS_DEV7_RXPKTCNT_RXPKTCNT_SHIFT 0 23062 23063 23064 /**************************************************************************** 23065 * sys_device7 :: digctl_3_0 23066 */ 23067 /* sys_device7 :: digctl_3_0 :: an_lostLink_cnt [15:00] */ 23068 #define PHY84328_SYS_DEV7_DIGCTL_3_0_AN_LOSTLINK_CNT_MASK 0xffff 23069 #define PHY84328_SYS_DEV7_DIGCTL_3_0_AN_LOSTLINK_CNT_ALIGN 0 23070 #define PHY84328_SYS_DEV7_DIGCTL_3_0_AN_LOSTLINK_CNT_BITS 16 23071 #define PHY84328_SYS_DEV7_DIGCTL_3_0_AN_LOSTLINK_CNT_SHIFT 0 23072 23073 23074 /**************************************************************************** 23075 * sys_device7 :: digctl_3_1 23076 */ 23077 /* sys_device7 :: digctl_3_1 :: an_switch_cnt [15:00] */ 23078 #define PHY84328_SYS_DEV7_DIGCTL_3_1_AN_SWITCH_CNT_MASK 0xffff 23079 #define PHY84328_SYS_DEV7_DIGCTL_3_1_AN_SWITCH_CNT_ALIGN 0 23080 #define PHY84328_SYS_DEV7_DIGCTL_3_1_AN_SWITCH_CNT_BITS 16 23081 #define PHY84328_SYS_DEV7_DIGCTL_3_1_AN_SWITCH_CNT_SHIFT 0 23082 23083 23084 /**************************************************************************** 23085 * sys_device7 :: digctl_3_2 23086 */ 23087 /* sys_device7 :: digctl_3_2 :: an_link_cnt [15:00] */ 23088 #define PHY84328_SYS_DEV7_DIGCTL_3_2_AN_LINK_CNT_MASK 0xffff 23089 #define PHY84328_SYS_DEV7_DIGCTL_3_2_AN_LINK_CNT_ALIGN 0 23090 #define PHY84328_SYS_DEV7_DIGCTL_3_2_AN_LINK_CNT_BITS 16 23091 #define PHY84328_SYS_DEV7_DIGCTL_3_2_AN_LINK_CNT_SHIFT 0 23092 23093 23094 /**************************************************************************** 23095 * sys_device7 :: digctl_3_3 23096 */ 23097 /* sys_device7 :: digctl_3_3 :: an_switch_cnt2 [15:08] */ 23098 #define PHY84328_SYS_DEV7_DIGCTL_3_3_AN_SWITCH_CNT2_MASK 0xff00 23099 #define PHY84328_SYS_DEV7_DIGCTL_3_3_AN_SWITCH_CNT2_ALIGN 0 23100 #define PHY84328_SYS_DEV7_DIGCTL_3_3_AN_SWITCH_CNT2_BITS 8 23101 #define PHY84328_SYS_DEV7_DIGCTL_3_3_AN_SWITCH_CNT2_SHIFT 8 23102 23103 /* sys_device7 :: digctl_3_3 :: an_link_cnt2 [07:00] */ 23104 #define PHY84328_SYS_DEV7_DIGCTL_3_3_AN_LINK_CNT2_MASK 0x00ff 23105 #define PHY84328_SYS_DEV7_DIGCTL_3_3_AN_LINK_CNT2_ALIGN 0 23106 #define PHY84328_SYS_DEV7_DIGCTL_3_3_AN_LINK_CNT2_BITS 8 23107 #define PHY84328_SYS_DEV7_DIGCTL_3_3_AN_LINK_CNT2_SHIFT 0 23108 23109 23110 /**************************************************************************** 23111 * sys_device7 :: digctl_3_4 23112 */ 23113 /* sys_device7 :: digctl_3_4 :: mp_number [15:05] */ 23114 #define PHY84328_SYS_DEV7_DIGCTL_3_4_MP_NUMBER_MASK 0xffe0 23115 #define PHY84328_SYS_DEV7_DIGCTL_3_4_MP_NUMBER_ALIGN 0 23116 #define PHY84328_SYS_DEV7_DIGCTL_3_4_MP_NUMBER_BITS 11 23117 #define PHY84328_SYS_DEV7_DIGCTL_3_4_MP_NUMBER_SHIFT 5 23118 23119 /* sys_device7 :: digctl_3_4 :: no_fail_cnt [04:04] */ 23120 #define PHY84328_SYS_DEV7_DIGCTL_3_4_NO_FAIL_CNT_MASK 0x0010 23121 #define PHY84328_SYS_DEV7_DIGCTL_3_4_NO_FAIL_CNT_ALIGN 0 23122 #define PHY84328_SYS_DEV7_DIGCTL_3_4_NO_FAIL_CNT_BITS 1 23123 #define PHY84328_SYS_DEV7_DIGCTL_3_4_NO_FAIL_CNT_SHIFT 4 23124 23125 /* sys_device7 :: digctl_3_4 :: an_fail_cnt [03:00] */ 23126 #define PHY84328_SYS_DEV7_DIGCTL_3_4_AN_FAIL_CNT_MASK 0x000f 23127 #define PHY84328_SYS_DEV7_DIGCTL_3_4_AN_FAIL_CNT_ALIGN 0 23128 #define PHY84328_SYS_DEV7_DIGCTL_3_4_AN_FAIL_CNT_BITS 4 23129 #define PHY84328_SYS_DEV7_DIGCTL_3_4_AN_FAIL_CNT_SHIFT 0 23130 23131 23132 /**************************************************************************** 23133 * sys_device7 :: digctl_3_5 23134 */ 23135 /* sys_device7 :: digctl_3_5 :: an_ignoreLink_cnt [15:00] */ 23136 #define PHY84328_SYS_DEV7_DIGCTL_3_5_AN_IGNORELINK_CNT_MASK 0xffff 23137 #define PHY84328_SYS_DEV7_DIGCTL_3_5_AN_IGNORELINK_CNT_ALIGN 0 23138 #define PHY84328_SYS_DEV7_DIGCTL_3_5_AN_IGNORELINK_CNT_BITS 16 23139 #define PHY84328_SYS_DEV7_DIGCTL_3_5_AN_IGNORELINK_CNT_SHIFT 0 23140 23141 23142 /**************************************************************************** 23143 * sys_device7 :: digctl_3_6 23144 */ 23145 /* sys_device7 :: digctl_3_6 :: an_lostLink_cnt2 [15:08] */ 23146 #define PHY84328_SYS_DEV7_DIGCTL_3_6_AN_LOSTLINK_CNT2_MASK 0xff00 23147 #define PHY84328_SYS_DEV7_DIGCTL_3_6_AN_LOSTLINK_CNT2_ALIGN 0 23148 #define PHY84328_SYS_DEV7_DIGCTL_3_6_AN_LOSTLINK_CNT2_BITS 8 23149 #define PHY84328_SYS_DEV7_DIGCTL_3_6_AN_LOSTLINK_CNT2_SHIFT 8 23150 23151 /* sys_device7 :: digctl_3_6 :: an_ingoreLink_cnt2 [07:00] */ 23152 #define PHY84328_SYS_DEV7_DIGCTL_3_6_AN_INGORELINK_CNT2_MASK 0x00ff 23153 #define PHY84328_SYS_DEV7_DIGCTL_3_6_AN_INGORELINK_CNT2_ALIGN 0 23154 #define PHY84328_SYS_DEV7_DIGCTL_3_6_AN_INGORELINK_CNT2_BITS 8 23155 #define PHY84328_SYS_DEV7_DIGCTL_3_6_AN_INGORELINK_CNT2_SHIFT 0 23156 23157 23158 /**************************************************************************** 23159 * sys_device7 :: UP1 23160 */ 23161 /* sys_device7 :: UP1 :: reserved0 [15:11] */ 23162 #define PHY84328_SYS_DEV7_UP1_RESERVED0_MASK 0xf800 23163 #define PHY84328_SYS_DEV7_UP1_RESERVED0_ALIGN 0 23164 #define PHY84328_SYS_DEV7_UP1_RESERVED0_BITS 5 23165 #define PHY84328_SYS_DEV7_UP1_RESERVED0_SHIFT 11 23166 23167 /* sys_device7 :: UP1 :: dataRate_20GX4 [10:10] */ 23168 #define PHY84328_SYS_DEV7_UP1_DATARATE_20GX4_MASK 0x0400 23169 #define PHY84328_SYS_DEV7_UP1_DATARATE_20GX4_ALIGN 0 23170 #define PHY84328_SYS_DEV7_UP1_DATARATE_20GX4_BITS 1 23171 #define PHY84328_SYS_DEV7_UP1_DATARATE_20GX4_SHIFT 10 23172 23173 /* sys_device7 :: UP1 :: dataRate_16GX4 [09:09] */ 23174 #define PHY84328_SYS_DEV7_UP1_DATARATE_16GX4_MASK 0x0200 23175 #define PHY84328_SYS_DEV7_UP1_DATARATE_16GX4_ALIGN 0 23176 #define PHY84328_SYS_DEV7_UP1_DATARATE_16GX4_BITS 1 23177 #define PHY84328_SYS_DEV7_UP1_DATARATE_16GX4_SHIFT 9 23178 23179 /* sys_device7 :: UP1 :: dataRate_15GX4 [08:08] */ 23180 #define PHY84328_SYS_DEV7_UP1_DATARATE_15GX4_MASK 0x0100 23181 #define PHY84328_SYS_DEV7_UP1_DATARATE_15GX4_ALIGN 0 23182 #define PHY84328_SYS_DEV7_UP1_DATARATE_15GX4_BITS 1 23183 #define PHY84328_SYS_DEV7_UP1_DATARATE_15GX4_SHIFT 8 23184 23185 /* sys_device7 :: UP1 :: dataRate_13GX4 [07:07] */ 23186 #define PHY84328_SYS_DEV7_UP1_DATARATE_13GX4_MASK 0x0080 23187 #define PHY84328_SYS_DEV7_UP1_DATARATE_13GX4_ALIGN 0 23188 #define PHY84328_SYS_DEV7_UP1_DATARATE_13GX4_BITS 1 23189 #define PHY84328_SYS_DEV7_UP1_DATARATE_13GX4_SHIFT 7 23190 23191 /* sys_device7 :: UP1 :: dataRate_12p5GX4 [06:06] */ 23192 #define PHY84328_SYS_DEV7_UP1_DATARATE_12P5GX4_MASK 0x0040 23193 #define PHY84328_SYS_DEV7_UP1_DATARATE_12P5GX4_ALIGN 0 23194 #define PHY84328_SYS_DEV7_UP1_DATARATE_12P5GX4_BITS 1 23195 #define PHY84328_SYS_DEV7_UP1_DATARATE_12P5GX4_SHIFT 6 23196 23197 /* sys_device7 :: UP1 :: dataRate_12GX4 [05:05] */ 23198 #define PHY84328_SYS_DEV7_UP1_DATARATE_12GX4_MASK 0x0020 23199 #define PHY84328_SYS_DEV7_UP1_DATARATE_12GX4_ALIGN 0 23200 #define PHY84328_SYS_DEV7_UP1_DATARATE_12GX4_BITS 1 23201 #define PHY84328_SYS_DEV7_UP1_DATARATE_12GX4_SHIFT 5 23202 23203 /* sys_device7 :: UP1 :: dataRate_10GCX4 [04:04] */ 23204 #define PHY84328_SYS_DEV7_UP1_DATARATE_10GCX4_MASK 0x0010 23205 #define PHY84328_SYS_DEV7_UP1_DATARATE_10GCX4_ALIGN 0 23206 #define PHY84328_SYS_DEV7_UP1_DATARATE_10GCX4_BITS 1 23207 #define PHY84328_SYS_DEV7_UP1_DATARATE_10GCX4_SHIFT 4 23208 23209 /* sys_device7 :: UP1 :: dataRate_10GX4 [03:03] */ 23210 #define PHY84328_SYS_DEV7_UP1_DATARATE_10GX4_MASK 0x0008 23211 #define PHY84328_SYS_DEV7_UP1_DATARATE_10GX4_ALIGN 0 23212 #define PHY84328_SYS_DEV7_UP1_DATARATE_10GX4_BITS 1 23213 #define PHY84328_SYS_DEV7_UP1_DATARATE_10GX4_SHIFT 3 23214 23215 /* sys_device7 :: UP1 :: dataRate_6GX4 [02:02] */ 23216 #define PHY84328_SYS_DEV7_UP1_DATARATE_6GX4_MASK 0x0004 23217 #define PHY84328_SYS_DEV7_UP1_DATARATE_6GX4_ALIGN 0 23218 #define PHY84328_SYS_DEV7_UP1_DATARATE_6GX4_BITS 1 23219 #define PHY84328_SYS_DEV7_UP1_DATARATE_6GX4_SHIFT 2 23220 23221 /* sys_device7 :: UP1 :: dataRate_5GX4 [01:01] */ 23222 #define PHY84328_SYS_DEV7_UP1_DATARATE_5GX4_MASK 0x0002 23223 #define PHY84328_SYS_DEV7_UP1_DATARATE_5GX4_ALIGN 0 23224 #define PHY84328_SYS_DEV7_UP1_DATARATE_5GX4_BITS 1 23225 #define PHY84328_SYS_DEV7_UP1_DATARATE_5GX4_SHIFT 1 23226 23227 /* sys_device7 :: UP1 :: dataRate_2p5GX1 [00:00] */ 23228 #define PHY84328_SYS_DEV7_UP1_DATARATE_2P5GX1_MASK 0x0001 23229 #define PHY84328_SYS_DEV7_UP1_DATARATE_2P5GX1_ALIGN 0 23230 #define PHY84328_SYS_DEV7_UP1_DATARATE_2P5GX1_BITS 1 23231 #define PHY84328_SYS_DEV7_UP1_DATARATE_2P5GX1_SHIFT 0 23232 23233 23234 /**************************************************************************** 23235 * sys_device7 :: UP2 23236 */ 23237 /* sys_device7 :: UP2 :: reserved0 [15:11] */ 23238 #define PHY84328_SYS_DEV7_UP2_RESERVED0_MASK 0xf800 23239 #define PHY84328_SYS_DEV7_UP2_RESERVED0_ALIGN 0 23240 #define PHY84328_SYS_DEV7_UP2_RESERVED0_BITS 5 23241 #define PHY84328_SYS_DEV7_UP2_RESERVED0_SHIFT 11 23242 23243 /* sys_device7 :: UP2 :: valid [10:10] */ 23244 #define PHY84328_SYS_DEV7_UP2_VALID_MASK 0x0400 23245 #define PHY84328_SYS_DEV7_UP2_VALID_ALIGN 0 23246 #define PHY84328_SYS_DEV7_UP2_VALID_BITS 1 23247 #define PHY84328_SYS_DEV7_UP2_VALID_SHIFT 10 23248 23249 /* sys_device7 :: UP2 :: preemphasis [09:06] */ 23250 #define PHY84328_SYS_DEV7_UP2_PREEMPHASIS_MASK 0x03c0 23251 #define PHY84328_SYS_DEV7_UP2_PREEMPHASIS_ALIGN 0 23252 #define PHY84328_SYS_DEV7_UP2_PREEMPHASIS_BITS 4 23253 #define PHY84328_SYS_DEV7_UP2_PREEMPHASIS_SHIFT 6 23254 23255 /* sys_device7 :: UP2 :: idriver [05:03] */ 23256 #define PHY84328_SYS_DEV7_UP2_IDRIVER_MASK 0x0038 23257 #define PHY84328_SYS_DEV7_UP2_IDRIVER_ALIGN 0 23258 #define PHY84328_SYS_DEV7_UP2_IDRIVER_BITS 3 23259 #define PHY84328_SYS_DEV7_UP2_IDRIVER_SHIFT 3 23260 23261 /* sys_device7 :: UP2 :: ipredriver [02:00] */ 23262 #define PHY84328_SYS_DEV7_UP2_IPREDRIVER_MASK 0x0007 23263 #define PHY84328_SYS_DEV7_UP2_IPREDRIVER_ALIGN 0 23264 #define PHY84328_SYS_DEV7_UP2_IPREDRIVER_BITS 3 23265 #define PHY84328_SYS_DEV7_UP2_IPREDRIVER_SHIFT 0 23266 23267 23268 /**************************************************************************** 23269 * sys_device7 :: UP3 23270 */ 23271 /* sys_device7 :: UP3 :: reserved0 [15:11] */ 23272 #define PHY84328_SYS_DEV7_UP3_RESERVED0_MASK 0xf800 23273 #define PHY84328_SYS_DEV7_UP3_RESERVED0_ALIGN 0 23274 #define PHY84328_SYS_DEV7_UP3_RESERVED0_BITS 5 23275 #define PHY84328_SYS_DEV7_UP3_RESERVED0_SHIFT 11 23276 23277 /* sys_device7 :: UP3 :: last [10:10] */ 23278 #define PHY84328_SYS_DEV7_UP3_LAST_MASK 0x0400 23279 #define PHY84328_SYS_DEV7_UP3_LAST_ALIGN 0 23280 #define PHY84328_SYS_DEV7_UP3_LAST_BITS 1 23281 #define PHY84328_SYS_DEV7_UP3_LAST_SHIFT 10 23282 23283 /* sys_device7 :: UP3 :: dataRate_21GX4 [09:09] */ 23284 #define PHY84328_SYS_DEV7_UP3_DATARATE_21GX4_MASK 0x0200 23285 #define PHY84328_SYS_DEV7_UP3_DATARATE_21GX4_ALIGN 0 23286 #define PHY84328_SYS_DEV7_UP3_DATARATE_21GX4_BITS 1 23287 #define PHY84328_SYS_DEV7_UP3_DATARATE_21GX4_SHIFT 9 23288 23289 /* sys_device7 :: UP3 :: dataRate_25p45GX4 [08:08] */ 23290 #define PHY84328_SYS_DEV7_UP3_DATARATE_25P45GX4_MASK 0x0100 23291 #define PHY84328_SYS_DEV7_UP3_DATARATE_25P45GX4_ALIGN 0 23292 #define PHY84328_SYS_DEV7_UP3_DATARATE_25P45GX4_BITS 1 23293 #define PHY84328_SYS_DEV7_UP3_DATARATE_25P45GX4_SHIFT 8 23294 23295 /* sys_device7 :: UP3 :: dataRate_31p5G [07:07] */ 23296 #define PHY84328_SYS_DEV7_UP3_DATARATE_31P5G_MASK 0x0080 23297 #define PHY84328_SYS_DEV7_UP3_DATARATE_31P5G_ALIGN 0 23298 #define PHY84328_SYS_DEV7_UP3_DATARATE_31P5G_BITS 1 23299 #define PHY84328_SYS_DEV7_UP3_DATARATE_31P5G_SHIFT 7 23300 23301 /* sys_device7 :: UP3 :: reserved1 [06:06] */ 23302 #define PHY84328_SYS_DEV7_UP3_RESERVED1_MASK 0x0040 23303 #define PHY84328_SYS_DEV7_UP3_RESERVED1_ALIGN 0 23304 #define PHY84328_SYS_DEV7_UP3_RESERVED1_BITS 1 23305 #define PHY84328_SYS_DEV7_UP3_RESERVED1_SHIFT 6 23306 23307 /* sys_device7 :: UP3 :: dataRate_40G [05:05] */ 23308 #define PHY84328_SYS_DEV7_UP3_DATARATE_40G_MASK 0x0020 23309 #define PHY84328_SYS_DEV7_UP3_DATARATE_40G_ALIGN 0 23310 #define PHY84328_SYS_DEV7_UP3_DATARATE_40G_BITS 1 23311 #define PHY84328_SYS_DEV7_UP3_DATARATE_40G_SHIFT 5 23312 23313 /* sys_device7 :: UP3 :: reserved2 [04:03] */ 23314 #define PHY84328_SYS_DEV7_UP3_RESERVED2_MASK 0x0018 23315 #define PHY84328_SYS_DEV7_UP3_RESERVED2_ALIGN 0 23316 #define PHY84328_SYS_DEV7_UP3_RESERVED2_BITS 2 23317 #define PHY84328_SYS_DEV7_UP3_RESERVED2_SHIFT 3 23318 23319 /* sys_device7 :: UP3 :: Cl72 [02:02] */ 23320 #define PHY84328_SYS_DEV7_UP3_CL72_MASK 0x0004 23321 #define PHY84328_SYS_DEV7_UP3_CL72_ALIGN 0 23322 #define PHY84328_SYS_DEV7_UP3_CL72_BITS 1 23323 #define PHY84328_SYS_DEV7_UP3_CL72_SHIFT 2 23324 23325 /* sys_device7 :: UP3 :: FEC [01:01] */ 23326 #define PHY84328_SYS_DEV7_UP3_FEC_MASK 0x0002 23327 #define PHY84328_SYS_DEV7_UP3_FEC_ALIGN 0 23328 #define PHY84328_SYS_DEV7_UP3_FEC_BITS 1 23329 #define PHY84328_SYS_DEV7_UP3_FEC_SHIFT 1 23330 23331 /* sys_device7 :: UP3 :: HiGig2 [00:00] */ 23332 #define PHY84328_SYS_DEV7_UP3_HIGIG2_MASK 0x0001 23333 #define PHY84328_SYS_DEV7_UP3_HIGIG2_ALIGN 0 23334 #define PHY84328_SYS_DEV7_UP3_HIGIG2_BITS 1 23335 #define PHY84328_SYS_DEV7_UP3_HIGIG2_SHIFT 0 23336 23337 23338 /**************************************************************************** 23339 * sys_device7 :: xgxsblock4LP_UP1 23340 */ 23341 /* sys_device7 :: xgxsblock4LP_UP1 :: reserved0 [15:11] */ 23342 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_RESERVED0_MASK 0xf800 23343 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_RESERVED0_ALIGN 0 23344 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_RESERVED0_BITS 5 23345 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_RESERVED0_SHIFT 11 23346 23347 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_20GX4 [10:10] */ 23348 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_20GX4_MASK 0x0400 23349 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_20GX4_ALIGN 0 23350 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_20GX4_BITS 1 23351 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_20GX4_SHIFT 10 23352 23353 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_16GX4 [09:09] */ 23354 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_16GX4_MASK 0x0200 23355 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_16GX4_ALIGN 0 23356 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_16GX4_BITS 1 23357 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_16GX4_SHIFT 9 23358 23359 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_15GX4 [08:08] */ 23360 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_15GX4_MASK 0x0100 23361 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_15GX4_ALIGN 0 23362 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_15GX4_BITS 1 23363 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_15GX4_SHIFT 8 23364 23365 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_13GX4 [07:07] */ 23366 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_13GX4_MASK 0x0080 23367 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_13GX4_ALIGN 0 23368 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_13GX4_BITS 1 23369 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_13GX4_SHIFT 7 23370 23371 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_12p5GX4 [06:06] */ 23372 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12P5GX4_MASK 0x0040 23373 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12P5GX4_ALIGN 0 23374 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12P5GX4_BITS 1 23375 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12P5GX4_SHIFT 6 23376 23377 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_12GX4 [05:05] */ 23378 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12GX4_MASK 0x0020 23379 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12GX4_ALIGN 0 23380 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12GX4_BITS 1 23381 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_12GX4_SHIFT 5 23382 23383 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_10GCX4 [04:04] */ 23384 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GCX4_MASK 0x0010 23385 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GCX4_ALIGN 0 23386 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GCX4_BITS 1 23387 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GCX4_SHIFT 4 23388 23389 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_10GX4 [03:03] */ 23390 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GX4_MASK 0x0008 23391 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GX4_ALIGN 0 23392 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GX4_BITS 1 23393 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_10GX4_SHIFT 3 23394 23395 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_6GX4 [02:02] */ 23396 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_6GX4_MASK 0x0004 23397 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_6GX4_ALIGN 0 23398 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_6GX4_BITS 1 23399 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_6GX4_SHIFT 2 23400 23401 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_5GX4 [01:01] */ 23402 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_5GX4_MASK 0x0002 23403 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_5GX4_ALIGN 0 23404 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_5GX4_BITS 1 23405 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_5GX4_SHIFT 1 23406 23407 /* sys_device7 :: xgxsblock4LP_UP1 :: dataRate_2p5GX1 [00:00] */ 23408 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_2P5GX1_MASK 0x0001 23409 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_2P5GX1_ALIGN 0 23410 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_2P5GX1_BITS 1 23411 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP1_DATARATE_2P5GX1_SHIFT 0 23412 23413 23414 /**************************************************************************** 23415 * sys_device7 :: xgxsblock4LP_UP2 23416 */ 23417 /* sys_device7 :: xgxsblock4LP_UP2 :: reserved0 [15:11] */ 23418 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_RESERVED0_MASK 0xf800 23419 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_RESERVED0_ALIGN 0 23420 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_RESERVED0_BITS 5 23421 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_RESERVED0_SHIFT 11 23422 23423 /* sys_device7 :: xgxsblock4LP_UP2 :: valid [10:10] */ 23424 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_VALID_MASK 0x0400 23425 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_VALID_ALIGN 0 23426 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_VALID_BITS 1 23427 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_VALID_SHIFT 10 23428 23429 /* sys_device7 :: xgxsblock4LP_UP2 :: preemphasis [09:06] */ 23430 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_PREEMPHASIS_MASK 0x03c0 23431 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_PREEMPHASIS_ALIGN 0 23432 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_PREEMPHASIS_BITS 4 23433 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_PREEMPHASIS_SHIFT 6 23434 23435 /* sys_device7 :: xgxsblock4LP_UP2 :: idriver [05:03] */ 23436 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_IDRIVER_MASK 0x0038 23437 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_IDRIVER_ALIGN 0 23438 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_IDRIVER_BITS 3 23439 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_IDRIVER_SHIFT 3 23440 23441 /* sys_device7 :: xgxsblock4LP_UP2 :: ipredriver [02:00] */ 23442 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_IPREDRIVER_MASK 0x0007 23443 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_IPREDRIVER_ALIGN 0 23444 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_IPREDRIVER_BITS 3 23445 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP2_IPREDRIVER_SHIFT 0 23446 23447 23448 /**************************************************************************** 23449 * sys_device7 :: xgxsblock4LP_UP3 23450 */ 23451 /* sys_device7 :: xgxsblock4LP_UP3 :: reserved0 [15:11] */ 23452 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED0_MASK 0xf800 23453 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED0_ALIGN 0 23454 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED0_BITS 5 23455 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED0_SHIFT 11 23456 23457 /* sys_device7 :: xgxsblock4LP_UP3 :: last [10:10] */ 23458 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_LAST_MASK 0x0400 23459 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_LAST_ALIGN 0 23460 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_LAST_BITS 1 23461 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_LAST_SHIFT 10 23462 23463 /* sys_device7 :: xgxsblock4LP_UP3 :: dataRate_21GX4 [09:09] */ 23464 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_21GX4_MASK 0x0200 23465 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_21GX4_ALIGN 0 23466 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_21GX4_BITS 1 23467 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_21GX4_SHIFT 9 23468 23469 /* sys_device7 :: xgxsblock4LP_UP3 :: dataRate_25p45GX4 [08:08] */ 23470 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_25P45GX4_MASK 0x0100 23471 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_25P45GX4_ALIGN 0 23472 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_25P45GX4_BITS 1 23473 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_25P45GX4_SHIFT 8 23474 23475 /* sys_device7 :: xgxsblock4LP_UP3 :: dataRate_31p5G [07:07] */ 23476 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_31P5G_MASK 0x0080 23477 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_31P5G_ALIGN 0 23478 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_31P5G_BITS 1 23479 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_31P5G_SHIFT 7 23480 23481 /* sys_device7 :: xgxsblock4LP_UP3 :: reserved1 [06:06] */ 23482 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED1_MASK 0x0040 23483 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED1_ALIGN 0 23484 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED1_BITS 1 23485 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED1_SHIFT 6 23486 23487 /* sys_device7 :: xgxsblock4LP_UP3 :: dataRate_40G [05:05] */ 23488 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_40G_MASK 0x0020 23489 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_40G_ALIGN 0 23490 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_40G_BITS 1 23491 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_DATARATE_40G_SHIFT 5 23492 23493 /* sys_device7 :: xgxsblock4LP_UP3 :: reserved2 [04:03] */ 23494 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED2_MASK 0x0018 23495 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED2_ALIGN 0 23496 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED2_BITS 2 23497 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_RESERVED2_SHIFT 3 23498 23499 /* sys_device7 :: xgxsblock4LP_UP3 :: Cl72 [02:02] */ 23500 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_CL72_MASK 0x0004 23501 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_CL72_ALIGN 0 23502 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_CL72_BITS 1 23503 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_CL72_SHIFT 2 23504 23505 /* sys_device7 :: xgxsblock4LP_UP3 :: FEC [01:01] */ 23506 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_FEC_MASK 0x0002 23507 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_FEC_ALIGN 0 23508 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_FEC_BITS 1 23509 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_FEC_SHIFT 1 23510 23511 /* sys_device7 :: xgxsblock4LP_UP3 :: HiGig2 [00:00] */ 23512 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_HIGIG2_MASK 0x0001 23513 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_HIGIG2_ALIGN 0 23514 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_HIGIG2_BITS 1 23515 #define PHY84328_SYS_DEV7_XGXSBLOCK4LP_UP3_HIGIG2_SHIFT 0 23516 23517 23518 /**************************************************************************** 23519 * sys_device7 :: rphyMiscRxStatus 23520 */ 23521 /* sys_device7 :: rphyMiscRxStatus :: capture_NP_lh [15:15] */ 23522 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_CAPTURE_NP_LH_MASK 0x8000 23523 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_CAPTURE_NP_LH_ALIGN 0 23524 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_CAPTURE_NP_LH_BITS 1 23525 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_CAPTURE_NP_LH_SHIFT 15 23526 23527 /* sys_device7 :: rphyMiscRxStatus :: teton_brk_link_lh [14:14] */ 23528 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_TETON_BRK_LINK_LH_MASK 0x4000 23529 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_TETON_BRK_LINK_LH_ALIGN 0 23530 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_TETON_BRK_LINK_LH_BITS 1 23531 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_TETON_BRK_LINK_LH_SHIFT 14 23532 23533 /* sys_device7 :: rphyMiscRxStatus :: UP3_lh [13:13] */ 23534 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_UP3_LH_MASK 0x2000 23535 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_UP3_LH_ALIGN 0 23536 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_UP3_LH_BITS 1 23537 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_UP3_LH_SHIFT 13 23538 23539 /* sys_device7 :: rphyMiscRxStatus :: MP5_lh [12:12] */ 23540 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MP5_LH_MASK 0x1000 23541 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MP5_LH_ALIGN 0 23542 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MP5_LH_BITS 1 23543 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MP5_LH_SHIFT 12 23544 23545 /* sys_device7 :: rphyMiscRxStatus :: nonMatchingOUI_lh [11:11] */ 23546 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NONMATCHINGOUI_LH_MASK 0x0800 23547 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NONMATCHINGOUI_LH_ALIGN 0 23548 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NONMATCHINGOUI_LH_BITS 1 23549 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NONMATCHINGOUI_LH_SHIFT 11 23550 23551 /* sys_device7 :: rphyMiscRxStatus :: matchingOUI_msb_lh [10:10] */ 23552 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_MSB_LH_MASK 0x0400 23553 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_MSB_LH_ALIGN 0 23554 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_MSB_LH_BITS 1 23555 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_MSB_LH_SHIFT 10 23556 23557 /* sys_device7 :: rphyMiscRxStatus :: matchingOUI_lsb_lh [09:09] */ 23558 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_LSB_LH_MASK 0x0200 23559 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_LSB_LH_ALIGN 0 23560 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_LSB_LH_BITS 1 23561 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MATCHINGOUI_LSB_LH_SHIFT 9 23562 23563 /* sys_device7 :: rphyMiscRxStatus :: invalidSeq_lh [08:08] */ 23564 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_INVALIDSEQ_LH_MASK 0x0100 23565 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_INVALIDSEQ_LH_ALIGN 0 23566 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_INVALIDSEQ_LH_BITS 1 23567 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_INVALIDSEQ_LH_SHIFT 8 23568 23569 /* sys_device7 :: rphyMiscRxStatus :: nullMP_lh [07:07] */ 23570 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NULLMP_LH_MASK 0x0080 23571 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NULLMP_LH_ALIGN 0 23572 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NULLMP_LH_BITS 1 23573 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NULLMP_LH_SHIFT 7 23574 23575 /* sys_device7 :: rphyMiscRxStatus :: remotePhyMP_lh [06:06] */ 23576 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_REMOTEPHYMP_LH_MASK 0x0040 23577 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_REMOTEPHYMP_LH_ALIGN 0 23578 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_REMOTEPHYMP_LH_BITS 1 23579 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_REMOTEPHYMP_LH_SHIFT 6 23580 23581 /* sys_device7 :: rphyMiscRxStatus :: nonMatchingMP_lh [05:05] */ 23582 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NONMATCHINGMP_LH_MASK 0x0020 23583 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NONMATCHINGMP_LH_ALIGN 0 23584 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NONMATCHINGMP_LH_BITS 1 23585 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NONMATCHINGMP_LH_SHIFT 5 23586 23587 /* sys_device7 :: rphyMiscRxStatus :: over1gMP_lh [04:04] */ 23588 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_OVER1GMP_LH_MASK 0x0010 23589 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_OVER1GMP_LH_ALIGN 0 23590 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_OVER1GMP_LH_BITS 1 23591 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_OVER1GMP_LH_SHIFT 4 23592 23593 /* sys_device7 :: rphyMiscRxStatus :: rx_config_is_0_lh [03:03] */ 23594 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_RX_CONFIG_IS_0_LH_MASK 0x0008 23595 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_RX_CONFIG_IS_0_LH_ALIGN 0 23596 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_RX_CONFIG_IS_0_LH_BITS 1 23597 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_RX_CONFIG_IS_0_LH_SHIFT 3 23598 23599 /* sys_device7 :: rphyMiscRxStatus :: np_toggle_err_lh [02:02] */ 23600 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NP_TOGGLE_ERR_LH_MASK 0x0004 23601 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NP_TOGGLE_ERR_LH_ALIGN 0 23602 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NP_TOGGLE_ERR_LH_BITS 1 23603 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_NP_TOGGLE_ERR_LH_SHIFT 2 23604 23605 /* sys_device7 :: rphyMiscRxStatus :: mr_np_lh [01:01] */ 23606 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MR_NP_LH_MASK 0x0002 23607 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MR_NP_LH_ALIGN 0 23608 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MR_NP_LH_BITS 1 23609 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MR_NP_LH_SHIFT 1 23610 23611 /* sys_device7 :: rphyMiscRxStatus :: mr_bp_lh [00:00] */ 23612 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MR_BP_LH_MASK 0x0001 23613 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MR_BP_LH_ALIGN 0 23614 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MR_BP_LH_BITS 1 23615 #define PHY84328_SYS_DEV7_RPHYMISCRXSTATUS_MR_BP_LH_SHIFT 0 23616 23617 23618 /**************************************************************************** 23619 * sys_device7 :: lp_basePage 23620 */ 23621 /* sys_device7 :: lp_basePage :: lp_basePage [15:00] */ 23622 #define PHY84328_SYS_DEV7_LP_BASEPAGE_LP_BASEPAGE_MASK 0xffff 23623 #define PHY84328_SYS_DEV7_LP_BASEPAGE_LP_BASEPAGE_ALIGN 0 23624 #define PHY84328_SYS_DEV7_LP_BASEPAGE_LP_BASEPAGE_BITS 16 23625 #define PHY84328_SYS_DEV7_LP_BASEPAGE_LP_BASEPAGE_SHIFT 0 23626 23627 23628 /**************************************************************************** 23629 * sys_device7 :: lp_nextPage_0 23630 */ 23631 /* sys_device7 :: lp_nextPage_0 :: lp_nextPage_0 [15:00] */ 23632 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_0_LP_NEXTPAGE_0_MASK 0xffff 23633 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_0_LP_NEXTPAGE_0_ALIGN 0 23634 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_0_LP_NEXTPAGE_0_BITS 16 23635 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_0_LP_NEXTPAGE_0_SHIFT 0 23636 23637 23638 /**************************************************************************** 23639 * sys_device7 :: lp_nextPage_1 23640 */ 23641 /* sys_device7 :: lp_nextPage_1 :: lp_nextPage_1 [15:00] */ 23642 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_1_LP_NEXTPAGE_1_MASK 0xffff 23643 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_1_LP_NEXTPAGE_1_ALIGN 0 23644 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_1_LP_NEXTPAGE_1_BITS 16 23645 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_1_LP_NEXTPAGE_1_SHIFT 0 23646 23647 23648 /**************************************************************************** 23649 * sys_device7 :: lp_nextPage_2 23650 */ 23651 /* sys_device7 :: lp_nextPage_2 :: lp_nextPage_2 [15:00] */ 23652 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_2_LP_NEXTPAGE_2_MASK 0xffff 23653 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_2_LP_NEXTPAGE_2_ALIGN 0 23654 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_2_LP_NEXTPAGE_2_BITS 16 23655 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_2_LP_NEXTPAGE_2_SHIFT 0 23656 23657 23658 /**************************************************************************** 23659 * sys_device7 :: lp_nextPage_3 23660 */ 23661 /* sys_device7 :: lp_nextPage_3 :: lp_nextPage_3 [15:00] */ 23662 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_3_LP_NEXTPAGE_3_MASK 0xffff 23663 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_3_LP_NEXTPAGE_3_ALIGN 0 23664 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_3_LP_NEXTPAGE_3_BITS 16 23665 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_3_LP_NEXTPAGE_3_SHIFT 0 23666 23667 23668 /**************************************************************************** 23669 * sys_device7 :: lp_nextPage_4 23670 */ 23671 /* sys_device7 :: lp_nextPage_4 :: lp_nextPage_4 [15:00] */ 23672 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_4_LP_NEXTPAGE_4_MASK 0xffff 23673 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_4_LP_NEXTPAGE_4_ALIGN 0 23674 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_4_LP_NEXTPAGE_4_BITS 16 23675 #define PHY84328_SYS_DEV7_LP_NEXTPAGE_4_LP_NEXTPAGE_4_SHIFT 0 23676 23677 23678 /**************************************************************************** 23679 * sys_device7 :: rp_nextPage_0 23680 */ 23681 /* sys_device7 :: rp_nextPage_0 :: reserved0 [15:15] */ 23682 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_RESERVED0_MASK 0x8000 23683 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_RESERVED0_ALIGN 0 23684 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_RESERVED0_BITS 1 23685 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_RESERVED0_SHIFT 15 23686 23687 /* sys_device7 :: rp_nextPage_0 :: extra_page_disable [14:14] */ 23688 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_MASK 0x4000 23689 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_ALIGN 0 23690 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_BITS 1 23691 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_SHIFT 14 23692 23693 /* sys_device7 :: rp_nextPage_0 :: null_page_enable [13:13] */ 23694 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_MASK 0x2000 23695 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_ALIGN 0 23696 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_BITS 1 23697 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_SHIFT 13 23698 23699 /* sys_device7 :: rp_nextPage_0 :: over_1g_disable [12:12] */ 23700 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_OVER_1G_DISABLE_MASK 0x1000 23701 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_OVER_1G_DISABLE_ALIGN 0 23702 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_OVER_1G_DISABLE_BITS 1 23703 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_OVER_1G_DISABLE_SHIFT 12 23704 23705 /* sys_device7 :: rp_nextPage_0 :: remote_phy_enable [11:11] */ 23706 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_MASK 0x0800 23707 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_ALIGN 0 23708 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_BITS 1 23709 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_SHIFT 11 23710 23711 /* sys_device7 :: rp_nextPage_0 :: rp_nextPage_0 [10:00] */ 23712 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_RP_NEXTPAGE_0_MASK 0x07ff 23713 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_RP_NEXTPAGE_0_ALIGN 0 23714 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_RP_NEXTPAGE_0_BITS 11 23715 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_0_RP_NEXTPAGE_0_SHIFT 0 23716 23717 23718 /**************************************************************************** 23719 * sys_device7 :: rp_nextPage_1 23720 */ 23721 /* sys_device7 :: rp_nextPage_1 :: reserved0 [15:15] */ 23722 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_RESERVED0_MASK 0x8000 23723 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_RESERVED0_ALIGN 0 23724 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_RESERVED0_BITS 1 23725 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_RESERVED0_SHIFT 15 23726 23727 /* sys_device7 :: rp_nextPage_1 :: remotePhy_linkDown_rstrt_disable [14:14] */ 23728 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_MASK 0x4000 23729 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_ALIGN 0 23730 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_BITS 1 23731 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_SHIFT 14 23732 23733 /* sys_device7 :: rp_nextPage_1 :: remotePhy_rsltn_err_rstrt_disable [13:13] */ 23734 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_MASK 0x2000 23735 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_ALIGN 0 23736 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_BITS 1 23737 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_SHIFT 13 23738 23739 /* sys_device7 :: rp_nextPage_1 :: remotePhy_resolution_disable [12:12] */ 23740 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_MASK 0x1000 23741 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_ALIGN 0 23742 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_BITS 1 23743 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_SHIFT 12 23744 23745 /* sys_device7 :: rp_nextPage_1 :: remotePhy_decode_enable [11:11] */ 23746 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_MASK 0x0800 23747 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_ALIGN 0 23748 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_BITS 1 23749 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_SHIFT 11 23750 23751 /* sys_device7 :: rp_nextPage_1 :: rp_nextPage_1 [10:00] */ 23752 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_RP_NEXTPAGE_1_MASK 0x07ff 23753 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_RP_NEXTPAGE_1_ALIGN 0 23754 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_RP_NEXTPAGE_1_BITS 11 23755 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_1_RP_NEXTPAGE_1_SHIFT 0 23756 23757 23758 /**************************************************************************** 23759 * sys_device7 :: rp_nextPage_2 23760 */ 23761 /* sys_device7 :: rp_nextPage_2 :: reserved0 [15:12] */ 23762 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_RESERVED0_MASK 0xf000 23763 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_RESERVED0_ALIGN 0 23764 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_RESERVED0_BITS 4 23765 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_RESERVED0_SHIFT 12 23766 23767 /* sys_device7 :: rp_nextPage_2 :: remPhy_NP_clr_disable [11:11] */ 23768 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_MASK 0x0800 23769 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_ALIGN 0 23770 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_BITS 1 23771 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_SHIFT 11 23772 23773 /* sys_device7 :: rp_nextPage_2 :: rp_nextPage_2 [10:00] */ 23774 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_RP_NEXTPAGE_2_MASK 0x07ff 23775 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_RP_NEXTPAGE_2_ALIGN 0 23776 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_RP_NEXTPAGE_2_BITS 11 23777 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_2_RP_NEXTPAGE_2_SHIFT 0 23778 23779 23780 /**************************************************************************** 23781 * sys_device7 :: rp_nextPage_3 23782 */ 23783 /* sys_device7 :: rp_nextPage_3 :: reserved0 [15:11] */ 23784 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3_RESERVED0_MASK 0xf800 23785 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3_RESERVED0_ALIGN 0 23786 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3_RESERVED0_BITS 5 23787 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3_RESERVED0_SHIFT 11 23788 23789 /* sys_device7 :: rp_nextPage_3 :: rp_nextPage_3 [10:00] */ 23790 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3_RP_NEXTPAGE_3_MASK 0x07ff 23791 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3_RP_NEXTPAGE_3_ALIGN 0 23792 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3_RP_NEXTPAGE_3_BITS 11 23793 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_3_RP_NEXTPAGE_3_SHIFT 0 23794 23795 23796 /**************************************************************************** 23797 * sys_device7 :: rp_nextPage_4 23798 */ 23799 /* sys_device7 :: rp_nextPage_4 :: reserved0 [15:11] */ 23800 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4_RESERVED0_MASK 0xf800 23801 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4_RESERVED0_ALIGN 0 23802 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4_RESERVED0_BITS 5 23803 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4_RESERVED0_SHIFT 11 23804 23805 /* sys_device7 :: rp_nextPage_4 :: rp_nextPage_4 [10:00] */ 23806 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4_RP_NEXTPAGE_4_MASK 0x07ff 23807 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4_RP_NEXTPAGE_4_ALIGN 0 23808 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4_RP_NEXTPAGE_4_BITS 11 23809 #define PHY84328_SYS_DEV7_RP_NEXTPAGE_4_RP_NEXTPAGE_4_SHIFT 0 23810 23811 23812 /**************************************************************************** 23813 * sys_device7 :: Misc3 23814 */ 23815 /* sys_device7 :: Misc3 :: ind_40bitif [15:15] */ 23816 #define PHY84328_SYS_DEV7_MISC3_IND_40BITIF_MASK 0x8000 23817 #define PHY84328_SYS_DEV7_MISC3_IND_40BITIF_ALIGN 0 23818 #define PHY84328_SYS_DEV7_MISC3_IND_40BITIF_BITS 1 23819 #define PHY84328_SYS_DEV7_MISC3_IND_40BITIF_SHIFT 15 23820 23821 /* sys_device7 :: Misc3 :: cl49_ed66_en_override [14:14] */ 23822 #define PHY84328_SYS_DEV7_MISC3_CL49_ED66_EN_OVERRIDE_MASK 0x4000 23823 #define PHY84328_SYS_DEV7_MISC3_CL49_ED66_EN_OVERRIDE_ALIGN 0 23824 #define PHY84328_SYS_DEV7_MISC3_CL49_ED66_EN_OVERRIDE_BITS 1 23825 #define PHY84328_SYS_DEV7_MISC3_CL49_ED66_EN_OVERRIDE_SHIFT 14 23826 23827 /* sys_device7 :: Misc3 :: cl49_ed66_en_val [13:13] */ 23828 #define PHY84328_SYS_DEV7_MISC3_CL49_ED66_EN_VAL_MASK 0x2000 23829 #define PHY84328_SYS_DEV7_MISC3_CL49_ED66_EN_VAL_ALIGN 0 23830 #define PHY84328_SYS_DEV7_MISC3_CL49_ED66_EN_VAL_BITS 1 23831 #define PHY84328_SYS_DEV7_MISC3_CL49_ED66_EN_VAL_SHIFT 13 23832 23833 /* sys_device7 :: Misc3 :: fifo_fsm_cya [12:12] */ 23834 #define PHY84328_SYS_DEV7_MISC3_FIFO_FSM_CYA_MASK 0x1000 23835 #define PHY84328_SYS_DEV7_MISC3_FIFO_FSM_CYA_ALIGN 0 23836 #define PHY84328_SYS_DEV7_MISC3_FIFO_FSM_CYA_BITS 1 23837 #define PHY84328_SYS_DEV7_MISC3_FIFO_FSM_CYA_SHIFT 12 23838 23839 /* sys_device7 :: Misc3 :: rxck_mii_override_val [11:11] */ 23840 #define PHY84328_SYS_DEV7_MISC3_RXCK_MII_OVERRIDE_VAL_MASK 0x0800 23841 #define PHY84328_SYS_DEV7_MISC3_RXCK_MII_OVERRIDE_VAL_ALIGN 0 23842 #define PHY84328_SYS_DEV7_MISC3_RXCK_MII_OVERRIDE_VAL_BITS 1 23843 #define PHY84328_SYS_DEV7_MISC3_RXCK_MII_OVERRIDE_VAL_SHIFT 11 23844 23845 /* sys_device7 :: Misc3 :: rxck_mii_override [10:10] */ 23846 #define PHY84328_SYS_DEV7_MISC3_RXCK_MII_OVERRIDE_MASK 0x0400 23847 #define PHY84328_SYS_DEV7_MISC3_RXCK_MII_OVERRIDE_ALIGN 0 23848 #define PHY84328_SYS_DEV7_MISC3_RXCK_MII_OVERRIDE_BITS 1 23849 #define PHY84328_SYS_DEV7_MISC3_RXCK_MII_OVERRIDE_SHIFT 10 23850 23851 /* sys_device7 :: Misc3 :: fifo_ipg_cya [09:09] */ 23852 #define PHY84328_SYS_DEV7_MISC3_FIFO_IPG_CYA_MASK 0x0200 23853 #define PHY84328_SYS_DEV7_MISC3_FIFO_IPG_CYA_ALIGN 0 23854 #define PHY84328_SYS_DEV7_MISC3_FIFO_IPG_CYA_BITS 1 23855 #define PHY84328_SYS_DEV7_MISC3_FIFO_IPG_CYA_SHIFT 9 23856 23857 /* sys_device7 :: Misc3 :: scr_en_per_lane [08:08] */ 23858 #define PHY84328_SYS_DEV7_MISC3_SCR_EN_PER_LANE_MASK 0x0100 23859 #define PHY84328_SYS_DEV7_MISC3_SCR_EN_PER_LANE_ALIGN 0 23860 #define PHY84328_SYS_DEV7_MISC3_SCR_EN_PER_LANE_BITS 1 23861 #define PHY84328_SYS_DEV7_MISC3_SCR_EN_PER_LANE_SHIFT 8 23862 23863 /* sys_device7 :: Misc3 :: force_speed_b5 [07:07] */ 23864 #define PHY84328_SYS_DEV7_MISC3_FORCE_SPEED_B5_MASK 0x0080 23865 #define PHY84328_SYS_DEV7_MISC3_FORCE_SPEED_B5_ALIGN 0 23866 #define PHY84328_SYS_DEV7_MISC3_FORCE_SPEED_B5_BITS 1 23867 #define PHY84328_SYS_DEV7_MISC3_FORCE_SPEED_B5_SHIFT 7 23868 23869 /* sys_device7 :: Misc3 :: laneDisable [06:06] */ 23870 #define PHY84328_SYS_DEV7_MISC3_LANEDISABLE_MASK 0x0040 23871 #define PHY84328_SYS_DEV7_MISC3_LANEDISABLE_ALIGN 0 23872 #define PHY84328_SYS_DEV7_MISC3_LANEDISABLE_BITS 1 23873 #define PHY84328_SYS_DEV7_MISC3_LANEDISABLE_SHIFT 6 23874 23875 /* sys_device7 :: Misc3 :: fifo_err_cya2 [05:05] */ 23876 #define PHY84328_SYS_DEV7_MISC3_FIFO_ERR_CYA2_MASK 0x0020 23877 #define PHY84328_SYS_DEV7_MISC3_FIFO_ERR_CYA2_ALIGN 0 23878 #define PHY84328_SYS_DEV7_MISC3_FIFO_ERR_CYA2_BITS 1 23879 #define PHY84328_SYS_DEV7_MISC3_FIFO_ERR_CYA2_SHIFT 5 23880 23881 /* sys_device7 :: Misc3 :: disable_pcs_tx_r [04:04] */ 23882 #define PHY84328_SYS_DEV7_MISC3_DISABLE_PCS_TX_R_MASK 0x0010 23883 #define PHY84328_SYS_DEV7_MISC3_DISABLE_PCS_TX_R_ALIGN 0 23884 #define PHY84328_SYS_DEV7_MISC3_DISABLE_PCS_TX_R_BITS 1 23885 #define PHY84328_SYS_DEV7_MISC3_DISABLE_PCS_TX_R_SHIFT 4 23886 23887 /* sys_device7 :: Misc3 :: disable_pcs_tx_force_r [03:03] */ 23888 #define PHY84328_SYS_DEV7_MISC3_DISABLE_PCS_TX_FORCE_R_MASK 0x0008 23889 #define PHY84328_SYS_DEV7_MISC3_DISABLE_PCS_TX_FORCE_R_ALIGN 0 23890 #define PHY84328_SYS_DEV7_MISC3_DISABLE_PCS_TX_FORCE_R_BITS 1 23891 #define PHY84328_SYS_DEV7_MISC3_DISABLE_PCS_TX_FORCE_R_SHIFT 3 23892 23893 /* sys_device7 :: Misc3 :: tbi_mode_force_r [02:02] */ 23894 #define PHY84328_SYS_DEV7_MISC3_TBI_MODE_FORCE_R_MASK 0x0004 23895 #define PHY84328_SYS_DEV7_MISC3_TBI_MODE_FORCE_R_ALIGN 0 23896 #define PHY84328_SYS_DEV7_MISC3_TBI_MODE_FORCE_R_BITS 1 23897 #define PHY84328_SYS_DEV7_MISC3_TBI_MODE_FORCE_R_SHIFT 2 23898 23899 /* sys_device7 :: Misc3 :: rxSigdetPwrdn_override_val [01:01] */ 23900 #define PHY84328_SYS_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_MASK 0x0002 23901 #define PHY84328_SYS_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_ALIGN 0 23902 #define PHY84328_SYS_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_BITS 1 23903 #define PHY84328_SYS_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_SHIFT 1 23904 23905 /* sys_device7 :: Misc3 :: rxSigdetPwrdn_override [00:00] */ 23906 #define PHY84328_SYS_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_MASK 0x0001 23907 #define PHY84328_SYS_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_ALIGN 0 23908 #define PHY84328_SYS_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_BITS 1 23909 #define PHY84328_SYS_DEV7_MISC3_RXSIGDETPWRDN_OVERRIDE_SHIFT 0 23910 23911 23912 /**************************************************************************** 23913 * sys_device7 :: Misc4 23914 */ 23915 /* sys_device7 :: Misc4 :: reserved0 [15:15] */ 23916 #define PHY84328_SYS_DEV7_MISC4_RESERVED0_MASK 0x8000 23917 #define PHY84328_SYS_DEV7_MISC4_RESERVED0_ALIGN 0 23918 #define PHY84328_SYS_DEV7_MISC4_RESERVED0_BITS 1 23919 #define PHY84328_SYS_DEV7_MISC4_RESERVED0_SHIFT 15 23920 23921 /* sys_device7 :: Misc4 :: scr_en_over [14:14] */ 23922 #define PHY84328_SYS_DEV7_MISC4_SCR_EN_OVER_MASK 0x4000 23923 #define PHY84328_SYS_DEV7_MISC4_SCR_EN_OVER_ALIGN 0 23924 #define PHY84328_SYS_DEV7_MISC4_SCR_EN_OVER_BITS 1 23925 #define PHY84328_SYS_DEV7_MISC4_SCR_EN_OVER_SHIFT 14 23926 23927 /* sys_device7 :: Misc4 :: div33_clk_use_cya [13:13] */ 23928 #define PHY84328_SYS_DEV7_MISC4_DIV33_CLK_USE_CYA_MASK 0x2000 23929 #define PHY84328_SYS_DEV7_MISC4_DIV33_CLK_USE_CYA_ALIGN 0 23930 #define PHY84328_SYS_DEV7_MISC4_DIV33_CLK_USE_CYA_BITS 1 23931 #define PHY84328_SYS_DEV7_MISC4_DIV33_CLK_USE_CYA_SHIFT 13 23932 23933 /* sys_device7 :: Misc4 :: os3_en_val [12:12] */ 23934 #define PHY84328_SYS_DEV7_MISC4_OS3_EN_VAL_MASK 0x1000 23935 #define PHY84328_SYS_DEV7_MISC4_OS3_EN_VAL_ALIGN 0 23936 #define PHY84328_SYS_DEV7_MISC4_OS3_EN_VAL_BITS 1 23937 #define PHY84328_SYS_DEV7_MISC4_OS3_EN_VAL_SHIFT 12 23938 23939 /* sys_device7 :: Misc4 :: os3_en_override [11:11] */ 23940 #define PHY84328_SYS_DEV7_MISC4_OS3_EN_OVERRIDE_MASK 0x0800 23941 #define PHY84328_SYS_DEV7_MISC4_OS3_EN_OVERRIDE_ALIGN 0 23942 #define PHY84328_SYS_DEV7_MISC4_OS3_EN_OVERRIDE_BITS 1 23943 #define PHY84328_SYS_DEV7_MISC4_OS3_EN_OVERRIDE_SHIFT 11 23944 23945 /* sys_device7 :: Misc4 :: decouple_actual_speed [10:10] */ 23946 #define PHY84328_SYS_DEV7_MISC4_DECOUPLE_ACTUAL_SPEED_MASK 0x0400 23947 #define PHY84328_SYS_DEV7_MISC4_DECOUPLE_ACTUAL_SPEED_ALIGN 0 23948 #define PHY84328_SYS_DEV7_MISC4_DECOUPLE_ACTUAL_SPEED_BITS 1 23949 #define PHY84328_SYS_DEV7_MISC4_DECOUPLE_ACTUAL_SPEED_SHIFT 10 23950 23951 /* sys_device7 :: Misc4 :: fx_mode_rx_pre [09:09] */ 23952 #define PHY84328_SYS_DEV7_MISC4_FX_MODE_RX_PRE_MASK 0x0200 23953 #define PHY84328_SYS_DEV7_MISC4_FX_MODE_RX_PRE_ALIGN 0 23954 #define PHY84328_SYS_DEV7_MISC4_FX_MODE_RX_PRE_BITS 1 23955 #define PHY84328_SYS_DEV7_MISC4_FX_MODE_RX_PRE_SHIFT 9 23956 23957 /* sys_device7 :: Misc4 :: fiber_select_rx_pre [08:08] */ 23958 #define PHY84328_SYS_DEV7_MISC4_FIBER_SELECT_RX_PRE_MASK 0x0100 23959 #define PHY84328_SYS_DEV7_MISC4_FIBER_SELECT_RX_PRE_ALIGN 0 23960 #define PHY84328_SYS_DEV7_MISC4_FIBER_SELECT_RX_PRE_BITS 1 23961 #define PHY84328_SYS_DEV7_MISC4_FIBER_SELECT_RX_PRE_SHIFT 8 23962 23963 /* sys_device7 :: Misc4 :: force_speed_rx_pre [07:02] */ 23964 #define PHY84328_SYS_DEV7_MISC4_FORCE_SPEED_RX_PRE_MASK 0x00fc 23965 #define PHY84328_SYS_DEV7_MISC4_FORCE_SPEED_RX_PRE_ALIGN 0 23966 #define PHY84328_SYS_DEV7_MISC4_FORCE_SPEED_RX_PRE_BITS 6 23967 #define PHY84328_SYS_DEV7_MISC4_FORCE_SPEED_RX_PRE_SHIFT 2 23968 23969 /* sys_device7 :: Misc4 :: reg0_forced_speed_rx_pre [01:00] */ 23970 #define PHY84328_SYS_DEV7_MISC4_REG0_FORCED_SPEED_RX_PRE_MASK 0x0003 23971 #define PHY84328_SYS_DEV7_MISC4_REG0_FORCED_SPEED_RX_PRE_ALIGN 0 23972 #define PHY84328_SYS_DEV7_MISC4_REG0_FORCED_SPEED_RX_PRE_BITS 2 23973 #define PHY84328_SYS_DEV7_MISC4_REG0_FORCED_SPEED_RX_PRE_SHIFT 0 23974 23975 23976 /**************************************************************************** 23977 * sys_device7 :: Misc5 23978 */ 23979 /* sys_device7 :: Misc5 :: LPI_en_rx [15:15] */ 23980 #define PHY84328_SYS_DEV7_MISC5_LPI_EN_RX_MASK 0x8000 23981 #define PHY84328_SYS_DEV7_MISC5_LPI_EN_RX_ALIGN 0 23982 #define PHY84328_SYS_DEV7_MISC5_LPI_EN_RX_BITS 1 23983 #define PHY84328_SYS_DEV7_MISC5_LPI_EN_RX_SHIFT 15 23984 23985 /* sys_device7 :: Misc5 :: LPI_en_tx [14:14] */ 23986 #define PHY84328_SYS_DEV7_MISC5_LPI_EN_TX_MASK 0x4000 23987 #define PHY84328_SYS_DEV7_MISC5_LPI_EN_TX_ALIGN 0 23988 #define PHY84328_SYS_DEV7_MISC5_LPI_EN_TX_BITS 1 23989 #define PHY84328_SYS_DEV7_MISC5_LPI_EN_TX_SHIFT 14 23990 23991 /* sys_device7 :: Misc5 :: tgen_data_sel [13:13] */ 23992 #define PHY84328_SYS_DEV7_MISC5_TGEN_DATA_SEL_MASK 0x2000 23993 #define PHY84328_SYS_DEV7_MISC5_TGEN_DATA_SEL_ALIGN 0 23994 #define PHY84328_SYS_DEV7_MISC5_TGEN_DATA_SEL_BITS 1 23995 #define PHY84328_SYS_DEV7_MISC5_TGEN_DATA_SEL_SHIFT 13 23996 23997 /* sys_device7 :: Misc5 :: tgen_cx4 [12:12] */ 23998 #define PHY84328_SYS_DEV7_MISC5_TGEN_CX4_MASK 0x1000 23999 #define PHY84328_SYS_DEV7_MISC5_TGEN_CX4_ALIGN 0 24000 #define PHY84328_SYS_DEV7_MISC5_TGEN_CX4_BITS 1 24001 #define PHY84328_SYS_DEV7_MISC5_TGEN_CX4_SHIFT 12 24002 24003 /* sys_device7 :: Misc5 :: tgen_link [11:11] */ 24004 #define PHY84328_SYS_DEV7_MISC5_TGEN_LINK_MASK 0x0800 24005 #define PHY84328_SYS_DEV7_MISC5_TGEN_LINK_ALIGN 0 24006 #define PHY84328_SYS_DEV7_MISC5_TGEN_LINK_BITS 1 24007 #define PHY84328_SYS_DEV7_MISC5_TGEN_LINK_SHIFT 11 24008 24009 /* sys_device7 :: Misc5 :: tgen_tmsel [10:08] */ 24010 #define PHY84328_SYS_DEV7_MISC5_TGEN_TMSEL_MASK 0x0700 24011 #define PHY84328_SYS_DEV7_MISC5_TGEN_TMSEL_ALIGN 0 24012 #define PHY84328_SYS_DEV7_MISC5_TGEN_TMSEL_BITS 3 24013 #define PHY84328_SYS_DEV7_MISC5_TGEN_TMSEL_SHIFT 8 24014 24015 /* sys_device7 :: Misc5 :: reserved0 [07:04] */ 24016 #define PHY84328_SYS_DEV7_MISC5_RESERVED0_MASK 0x00f0 24017 #define PHY84328_SYS_DEV7_MISC5_RESERVED0_ALIGN 0 24018 #define PHY84328_SYS_DEV7_MISC5_RESERVED0_BITS 4 24019 #define PHY84328_SYS_DEV7_MISC5_RESERVED0_SHIFT 4 24020 24021 /* sys_device7 :: Misc5 :: rchk_en [03:03] */ 24022 #define PHY84328_SYS_DEV7_MISC5_RCHK_EN_MASK 0x0008 24023 #define PHY84328_SYS_DEV7_MISC5_RCHK_EN_ALIGN 0 24024 #define PHY84328_SYS_DEV7_MISC5_RCHK_EN_BITS 1 24025 #define PHY84328_SYS_DEV7_MISC5_RCHK_EN_SHIFT 3 24026 24027 /* sys_device7 :: Misc5 :: rchk_tmsel [02:00] */ 24028 #define PHY84328_SYS_DEV7_MISC5_RCHK_TMSEL_MASK 0x0007 24029 #define PHY84328_SYS_DEV7_MISC5_RCHK_TMSEL_ALIGN 0 24030 #define PHY84328_SYS_DEV7_MISC5_RCHK_TMSEL_BITS 3 24031 #define PHY84328_SYS_DEV7_MISC5_RCHK_TMSEL_SHIFT 0 24032 24033 24034 /**************************************************************************** 24035 * sys_device7 :: linkcnt_cl72_msb 24036 */ 24037 /* sys_device7 :: linkcnt_cl72_msb :: reserved_for_eco0 [15:08] */ 24038 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_MASK 0xff00 24039 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_ALIGN 0 24040 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_BITS 8 24041 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB_RESERVED_FOR_ECO0_SHIFT 8 24042 24043 /* sys_device7 :: linkcnt_cl72_msb :: link_cnt_cl72_msbB [07:00] */ 24044 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_MASK 0x00ff 24045 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_ALIGN 0 24046 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_BITS 8 24047 #define PHY84328_SYS_DEV7_LINKCNT_CL72_MSB_LINK_CNT_CL72_MSBB_SHIFT 0 24048 24049 24050 /**************************************************************************** 24051 * sys_device7 :: linkcnt_cl72_lsb 24052 */ 24053 /* sys_device7 :: linkcnt_cl72_lsb :: link_cnt_cl72_lsbB [15:00] */ 24054 #define PHY84328_SYS_DEV7_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_MASK 0xffff 24055 #define PHY84328_SYS_DEV7_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_ALIGN 0 24056 #define PHY84328_SYS_DEV7_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_BITS 16 24057 #define PHY84328_SYS_DEV7_LINKCNT_CL72_LSB_LINK_CNT_CL72_LSBB_SHIFT 0 24058 24059 24060 /**************************************************************************** 24061 * sys_device7 :: LP_UP4 24062 */ 24063 /* sys_device7 :: LP_UP4 :: reserved0 [15:11] */ 24064 #define PHY84328_SYS_DEV7_LP_UP4_RESERVED0_MASK 0xf800 24065 #define PHY84328_SYS_DEV7_LP_UP4_RESERVED0_ALIGN 0 24066 #define PHY84328_SYS_DEV7_LP_UP4_RESERVED0_BITS 5 24067 #define PHY84328_SYS_DEV7_LP_UP4_RESERVED0_SHIFT 11 24068 24069 /* sys_device7 :: LP_UP4 :: last [10:10] */ 24070 #define PHY84328_SYS_DEV7_LP_UP4_LAST_MASK 0x0400 24071 #define PHY84328_SYS_DEV7_LP_UP4_LAST_ALIGN 0 24072 #define PHY84328_SYS_DEV7_LP_UP4_LAST_BITS 1 24073 #define PHY84328_SYS_DEV7_LP_UP4_LAST_SHIFT 10 24074 24075 /* sys_device7 :: LP_UP4 :: dataRate_1GCX1 [09:09] */ 24076 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_1GCX1_MASK 0x0200 24077 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_1GCX1_ALIGN 0 24078 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_1GCX1_BITS 1 24079 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_1GCX1_SHIFT 9 24080 24081 /* sys_device7 :: LP_UP4 :: dataRate_10GCX1 [08:08] */ 24082 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10GCX1_MASK 0x0100 24083 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10GCX1_ALIGN 0 24084 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10GCX1_BITS 1 24085 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10GCX1_SHIFT 8 24086 24087 /* sys_device7 :: LP_UP4 :: dataRate_15p75G_dxgxs [07:07] */ 24088 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_15P75G_DXGXS_MASK 0x0080 24089 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_15P75G_DXGXS_ALIGN 0 24090 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_15P75G_DXGXS_BITS 1 24091 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_15P75G_DXGXS_SHIFT 7 24092 24093 /* sys_device7 :: LP_UP4 :: dataRate_20G_dxgxs [06:06] */ 24094 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20G_DXGXS_MASK 0x0040 24095 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20G_DXGXS_ALIGN 0 24096 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20G_DXGXS_BITS 1 24097 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20G_DXGXS_SHIFT 6 24098 24099 /* sys_device7 :: LP_UP4 :: dataRate_20Gh_dxgxs [05:05] */ 24100 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20GH_DXGXS_MASK 0x0020 24101 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20GH_DXGXS_ALIGN 0 24102 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20GH_DXGXS_BITS 1 24103 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20GH_DXGXS_SHIFT 5 24104 24105 /* sys_device7 :: LP_UP4 :: dataRate_12p7G_dxgxs [04:04] */ 24106 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_12P7G_DXGXS_MASK 0x0010 24107 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_12P7G_DXGXS_ALIGN 0 24108 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_12P7G_DXGXS_BITS 1 24109 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_12P7G_DXGXS_SHIFT 4 24110 24111 /* sys_device7 :: LP_UP4 :: dataRate_10p5G_dxgxs [03:03] */ 24112 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10P5G_DXGXS_MASK 0x0008 24113 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10P5G_DXGXS_ALIGN 0 24114 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10P5G_DXGXS_BITS 1 24115 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10P5G_DXGXS_SHIFT 3 24116 24117 /* sys_device7 :: LP_UP4 :: dataRate_10G_dxgxs [02:02] */ 24118 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10G_DXGXS_MASK 0x0004 24119 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10G_DXGXS_ALIGN 0 24120 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10G_DXGXS_BITS 1 24121 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10G_DXGXS_SHIFT 2 24122 24123 /* sys_device7 :: LP_UP4 :: dataRate_10Gh_dxgxs [01:01] */ 24124 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10GH_DXGXS_MASK 0x0002 24125 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10GH_DXGXS_ALIGN 0 24126 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10GH_DXGXS_BITS 1 24127 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_10GH_DXGXS_SHIFT 1 24128 24129 /* sys_device7 :: LP_UP4 :: dataRate_20G [00:00] */ 24130 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20G_MASK 0x0001 24131 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20G_ALIGN 0 24132 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20G_BITS 1 24133 #define PHY84328_SYS_DEV7_LP_UP4_DATARATE_20G_SHIFT 0 24134 24135 24136 /**************************************************************************** 24137 * sys_device7 :: LP_UP5 24138 */ 24139 /* sys_device7 :: LP_UP5 :: reserved0 [15:11] */ 24140 #define PHY84328_SYS_DEV7_LP_UP5_RESERVED0_MASK 0xf800 24141 #define PHY84328_SYS_DEV7_LP_UP5_RESERVED0_ALIGN 0 24142 #define PHY84328_SYS_DEV7_LP_UP5_RESERVED0_BITS 5 24143 #define PHY84328_SYS_DEV7_LP_UP5_RESERVED0_SHIFT 11 24144 24145 /* sys_device7 :: LP_UP5 :: last [10:10] */ 24146 #define PHY84328_SYS_DEV7_LP_UP5_LAST_MASK 0x0400 24147 #define PHY84328_SYS_DEV7_LP_UP5_LAST_ALIGN 0 24148 #define PHY84328_SYS_DEV7_LP_UP5_LAST_BITS 1 24149 #define PHY84328_SYS_DEV7_LP_UP5_LAST_SHIFT 10 24150 24151 /* sys_device7 :: LP_UP5 :: reserved1 [09:00] */ 24152 #define PHY84328_SYS_DEV7_LP_UP5_RESERVED1_MASK 0x03ff 24153 #define PHY84328_SYS_DEV7_LP_UP5_RESERVED1_ALIGN 0 24154 #define PHY84328_SYS_DEV7_LP_UP5_RESERVED1_BITS 10 24155 #define PHY84328_SYS_DEV7_LP_UP5_RESERVED1_SHIFT 0 24156 24157 24158 /**************************************************************************** 24159 * sys_device7 :: Misc6 24160 */ 24161 /* sys_device7 :: Misc6 :: reset_rx_asic [15:15] */ 24162 #define PHY84328_SYS_DEV7_MISC6_RESET_RX_ASIC_MASK 0x8000 24163 #define PHY84328_SYS_DEV7_MISC6_RESET_RX_ASIC_ALIGN 0 24164 #define PHY84328_SYS_DEV7_MISC6_RESET_RX_ASIC_BITS 1 24165 #define PHY84328_SYS_DEV7_MISC6_RESET_RX_ASIC_SHIFT 15 24166 24167 /* sys_device7 :: Misc6 :: reset_tx_asic [14:14] */ 24168 #define PHY84328_SYS_DEV7_MISC6_RESET_TX_ASIC_MASK 0x4000 24169 #define PHY84328_SYS_DEV7_MISC6_RESET_TX_ASIC_ALIGN 0 24170 #define PHY84328_SYS_DEV7_MISC6_RESET_TX_ASIC_BITS 1 24171 #define PHY84328_SYS_DEV7_MISC6_RESET_TX_ASIC_SHIFT 14 24172 24173 /* sys_device7 :: Misc6 :: reserved0 [13:09] */ 24174 #define PHY84328_SYS_DEV7_MISC6_RESERVED0_MASK 0x3e00 24175 #define PHY84328_SYS_DEV7_MISC6_RESERVED0_ALIGN 0 24176 #define PHY84328_SYS_DEV7_MISC6_RESERVED0_BITS 5 24177 #define PHY84328_SYS_DEV7_MISC6_RESERVED0_SHIFT 9 24178 24179 /* sys_device7 :: Misc6 :: rx_os8_frst_SM [08:08] */ 24180 #define PHY84328_SYS_DEV7_MISC6_RX_OS8_FRST_SM_MASK 0x0100 24181 #define PHY84328_SYS_DEV7_MISC6_RX_OS8_FRST_SM_ALIGN 0 24182 #define PHY84328_SYS_DEV7_MISC6_RX_OS8_FRST_SM_BITS 1 24183 #define PHY84328_SYS_DEV7_MISC6_RX_OS8_FRST_SM_SHIFT 8 24184 24185 /* sys_device7 :: Misc6 :: use_brcm6466_31500_cya [07:07] */ 24186 #define PHY84328_SYS_DEV7_MISC6_USE_BRCM6466_31500_CYA_MASK 0x0080 24187 #define PHY84328_SYS_DEV7_MISC6_USE_BRCM6466_31500_CYA_ALIGN 0 24188 #define PHY84328_SYS_DEV7_MISC6_USE_BRCM6466_31500_CYA_BITS 1 24189 #define PHY84328_SYS_DEV7_MISC6_USE_BRCM6466_31500_CYA_SHIFT 7 24190 24191 /* sys_device7 :: Misc6 :: cx4_sigdet_filt_all_speed [06:06] */ 24192 #define PHY84328_SYS_DEV7_MISC6_CX4_SIGDET_FILT_ALL_SPEED_MASK 0x0040 24193 #define PHY84328_SYS_DEV7_MISC6_CX4_SIGDET_FILT_ALL_SPEED_ALIGN 0 24194 #define PHY84328_SYS_DEV7_MISC6_CX4_SIGDET_FILT_ALL_SPEED_BITS 1 24195 #define PHY84328_SYS_DEV7_MISC6_CX4_SIGDET_FILT_ALL_SPEED_SHIFT 6 24196 24197 /* sys_device7 :: Misc6 :: pcs_type_sel_1000x_cya [05:05] */ 24198 #define PHY84328_SYS_DEV7_MISC6_PCS_TYPE_SEL_1000X_CYA_MASK 0x0020 24199 #define PHY84328_SYS_DEV7_MISC6_PCS_TYPE_SEL_1000X_CYA_ALIGN 0 24200 #define PHY84328_SYS_DEV7_MISC6_PCS_TYPE_SEL_1000X_CYA_BITS 1 24201 #define PHY84328_SYS_DEV7_MISC6_PCS_TYPE_SEL_1000X_CYA_SHIFT 5 24202 24203 /* sys_device7 :: Misc6 :: rx_os8_os3_alt_bits_cya [04:04] */ 24204 #define PHY84328_SYS_DEV7_MISC6_RX_OS8_OS3_ALT_BITS_CYA_MASK 0x0010 24205 #define PHY84328_SYS_DEV7_MISC6_RX_OS8_OS3_ALT_BITS_CYA_ALIGN 0 24206 #define PHY84328_SYS_DEV7_MISC6_RX_OS8_OS3_ALT_BITS_CYA_BITS 1 24207 #define PHY84328_SYS_DEV7_MISC6_RX_OS8_OS3_ALT_BITS_CYA_SHIFT 4 24208 24209 /* sys_device7 :: Misc6 :: reserved1 [03:02] */ 24210 #define PHY84328_SYS_DEV7_MISC6_RESERVED1_MASK 0x000c 24211 #define PHY84328_SYS_DEV7_MISC6_RESERVED1_ALIGN 0 24212 #define PHY84328_SYS_DEV7_MISC6_RESERVED1_BITS 2 24213 #define PHY84328_SYS_DEV7_MISC6_RESERVED1_SHIFT 2 24214 24215 /* sys_device7 :: Misc6 :: tx_os8_afrst_en [01:01] */ 24216 #define PHY84328_SYS_DEV7_MISC6_TX_OS8_AFRST_EN_MASK 0x0002 24217 #define PHY84328_SYS_DEV7_MISC6_TX_OS8_AFRST_EN_ALIGN 0 24218 #define PHY84328_SYS_DEV7_MISC6_TX_OS8_AFRST_EN_BITS 1 24219 #define PHY84328_SYS_DEV7_MISC6_TX_OS8_AFRST_EN_SHIFT 1 24220 24221 /* sys_device7 :: Misc6 :: tx_os8_frst_SM [00:00] */ 24222 #define PHY84328_SYS_DEV7_MISC6_TX_OS8_FRST_SM_MASK 0x0001 24223 #define PHY84328_SYS_DEV7_MISC6_TX_OS8_FRST_SM_ALIGN 0 24224 #define PHY84328_SYS_DEV7_MISC6_TX_OS8_FRST_SM_BITS 1 24225 #define PHY84328_SYS_DEV7_MISC6_TX_OS8_FRST_SM_SHIFT 0 24226 24227 24228 /**************************************************************************** 24229 * sys_device7 :: Misc7 24230 */ 24231 /* sys_device7 :: Misc7 :: reserved0 [15:14] */ 24232 #define PHY84328_SYS_DEV7_MISC7_RESERVED0_MASK 0xc000 24233 #define PHY84328_SYS_DEV7_MISC7_RESERVED0_ALIGN 0 24234 #define PHY84328_SYS_DEV7_MISC7_RESERVED0_BITS 2 24235 #define PHY84328_SYS_DEV7_MISC7_RESERVED0_SHIFT 14 24236 24237 /* sys_device7 :: Misc7 :: force_oscdr_mode_val [13:10] */ 24238 #define PHY84328_SYS_DEV7_MISC7_FORCE_OSCDR_MODE_VAL_MASK 0x3c00 24239 #define PHY84328_SYS_DEV7_MISC7_FORCE_OSCDR_MODE_VAL_ALIGN 0 24240 #define PHY84328_SYS_DEV7_MISC7_FORCE_OSCDR_MODE_VAL_BITS 4 24241 #define PHY84328_SYS_DEV7_MISC7_FORCE_OSCDR_MODE_VAL_SHIFT 10 24242 24243 /* sys_device7 :: Misc7 :: force_oscdr_mode_en [09:09] */ 24244 #define PHY84328_SYS_DEV7_MISC7_FORCE_OSCDR_MODE_EN_MASK 0x0200 24245 #define PHY84328_SYS_DEV7_MISC7_FORCE_OSCDR_MODE_EN_ALIGN 0 24246 #define PHY84328_SYS_DEV7_MISC7_FORCE_OSCDR_MODE_EN_BITS 1 24247 #define PHY84328_SYS_DEV7_MISC7_FORCE_OSCDR_MODE_EN_SHIFT 9 24248 24249 /* sys_device7 :: Misc7 :: reserved1 [08:08] */ 24250 #define PHY84328_SYS_DEV7_MISC7_RESERVED1_MASK 0x0100 24251 #define PHY84328_SYS_DEV7_MISC7_RESERVED1_ALIGN 0 24252 #define PHY84328_SYS_DEV7_MISC7_RESERVED1_BITS 1 24253 #define PHY84328_SYS_DEV7_MISC7_RESERVED1_SHIFT 8 24254 24255 /* sys_device7 :: Misc7 :: force_speed_rx_pre_7_6 [07:06] */ 24256 #define PHY84328_SYS_DEV7_MISC7_FORCE_SPEED_RX_PRE_7_6_MASK 0x00c0 24257 #define PHY84328_SYS_DEV7_MISC7_FORCE_SPEED_RX_PRE_7_6_ALIGN 0 24258 #define PHY84328_SYS_DEV7_MISC7_FORCE_SPEED_RX_PRE_7_6_BITS 2 24259 #define PHY84328_SYS_DEV7_MISC7_FORCE_SPEED_RX_PRE_7_6_SHIFT 6 24260 24261 /* sys_device7 :: Misc7 :: brcm6466_cl49_in_all_mode_cya [05:05] */ 24262 #define PHY84328_SYS_DEV7_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_MASK 0x0020 24263 #define PHY84328_SYS_DEV7_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_ALIGN 0 24264 #define PHY84328_SYS_DEV7_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_BITS 1 24265 #define PHY84328_SYS_DEV7_MISC7_BRCM6466_CL49_IN_ALL_MODE_CYA_SHIFT 5 24266 24267 /* sys_device7 :: Misc7 :: xfi_txfault_pll_cya [04:04] */ 24268 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_PLL_CYA_MASK 0x0010 24269 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_PLL_CYA_ALIGN 0 24270 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_PLL_CYA_BITS 1 24271 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_PLL_CYA_SHIFT 4 24272 24273 /* sys_device7 :: Misc7 :: xfi_txfault_ext_cya [03:03] */ 24274 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_EXT_CYA_MASK 0x0008 24275 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_EXT_CYA_ALIGN 0 24276 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_EXT_CYA_BITS 1 24277 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_EXT_CYA_SHIFT 3 24278 24279 /* sys_device7 :: Misc7 :: xfi_txfault_det_cya [02:02] */ 24280 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_DET_CYA_MASK 0x0004 24281 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_DET_CYA_ALIGN 0 24282 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_DET_CYA_BITS 1 24283 #define PHY84328_SYS_DEV7_MISC7_XFI_TXFAULT_DET_CYA_SHIFT 2 24284 24285 /* sys_device7 :: Misc7 :: xfi_rxfault_link_cya [01:01] */ 24286 #define PHY84328_SYS_DEV7_MISC7_XFI_RXFAULT_LINK_CYA_MASK 0x0002 24287 #define PHY84328_SYS_DEV7_MISC7_XFI_RXFAULT_LINK_CYA_ALIGN 0 24288 #define PHY84328_SYS_DEV7_MISC7_XFI_RXFAULT_LINK_CYA_BITS 1 24289 #define PHY84328_SYS_DEV7_MISC7_XFI_RXFAULT_LINK_CYA_SHIFT 1 24290 24291 /* sys_device7 :: Misc7 :: xfi_rxfault_det_cya [00:00] */ 24292 #define PHY84328_SYS_DEV7_MISC7_XFI_RXFAULT_DET_CYA_MASK 0x0001 24293 #define PHY84328_SYS_DEV7_MISC7_XFI_RXFAULT_DET_CYA_ALIGN 0 24294 #define PHY84328_SYS_DEV7_MISC7_XFI_RXFAULT_DET_CYA_BITS 1 24295 #define PHY84328_SYS_DEV7_MISC7_XFI_RXFAULT_DET_CYA_SHIFT 0 24296 24297 24298 /**************************************************************************** 24299 * sys_device7 :: Misc8 24300 */ 24301 /* sys_device7 :: Misc8 :: reserved0 [15:05] */ 24302 #define PHY84328_SYS_DEV7_MISC8_RESERVED0_MASK 0xffe0 24303 #define PHY84328_SYS_DEV7_MISC8_RESERVED0_ALIGN 0 24304 #define PHY84328_SYS_DEV7_MISC8_RESERVED0_BITS 11 24305 #define PHY84328_SYS_DEV7_MISC8_RESERVED0_SHIFT 5 24306 24307 /* sys_device7 :: Misc8 :: force_oscdr_mode_en_rx [04:04] */ 24308 #define PHY84328_SYS_DEV7_MISC8_FORCE_OSCDR_MODE_EN_RX_MASK 0x0010 24309 #define PHY84328_SYS_DEV7_MISC8_FORCE_OSCDR_MODE_EN_RX_ALIGN 0 24310 #define PHY84328_SYS_DEV7_MISC8_FORCE_OSCDR_MODE_EN_RX_BITS 1 24311 #define PHY84328_SYS_DEV7_MISC8_FORCE_OSCDR_MODE_EN_RX_SHIFT 4 24312 24313 /* sys_device7 :: Misc8 :: force_oscdr_mode_val [03:00] */ 24314 #define PHY84328_SYS_DEV7_MISC8_FORCE_OSCDR_MODE_VAL_MASK 0x000f 24315 #define PHY84328_SYS_DEV7_MISC8_FORCE_OSCDR_MODE_VAL_ALIGN 0 24316 #define PHY84328_SYS_DEV7_MISC8_FORCE_OSCDR_MODE_VAL_BITS 4 24317 #define PHY84328_SYS_DEV7_MISC8_FORCE_OSCDR_MODE_VAL_SHIFT 0 24318 24319 24320 /**************************************************************************** 24321 * sys_device7 :: link_status 24322 */ 24323 /* sys_device7 :: link_status :: reserved0 [15:06] */ 24324 #define PHY84328_SYS_DEV7_LINK_STATUS_RESERVED0_MASK 0xffc0 24325 #define PHY84328_SYS_DEV7_LINK_STATUS_RESERVED0_ALIGN 0 24326 #define PHY84328_SYS_DEV7_LINK_STATUS_RESERVED0_BITS 10 24327 #define PHY84328_SYS_DEV7_LINK_STATUS_RESERVED0_SHIFT 6 24328 24329 /* sys_device7 :: link_status :: ll_link [05:05] */ 24330 #define PHY84328_SYS_DEV7_LINK_STATUS_LL_LINK_MASK 0x0020 24331 #define PHY84328_SYS_DEV7_LINK_STATUS_LL_LINK_ALIGN 0 24332 #define PHY84328_SYS_DEV7_LINK_STATUS_LL_LINK_BITS 1 24333 #define PHY84328_SYS_DEV7_LINK_STATUS_LL_LINK_SHIFT 5 24334 24335 /* sys_device7 :: link_status :: l_an_link [04:04] */ 24336 #define PHY84328_SYS_DEV7_LINK_STATUS_L_AN_LINK_MASK 0x0010 24337 #define PHY84328_SYS_DEV7_LINK_STATUS_L_AN_LINK_ALIGN 0 24338 #define PHY84328_SYS_DEV7_LINK_STATUS_L_AN_LINK_BITS 1 24339 #define PHY84328_SYS_DEV7_LINK_STATUS_L_AN_LINK_SHIFT 4 24340 24341 /* sys_device7 :: link_status :: l_link_kr [03:03] */ 24342 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_KR_MASK 0x0008 24343 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_KR_ALIGN 0 24344 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_KR_BITS 1 24345 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_KR_SHIFT 3 24346 24347 /* sys_device7 :: link_status :: l_link10g [02:02] */ 24348 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK10G_MASK 0x0004 24349 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK10G_ALIGN 0 24350 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK10G_BITS 1 24351 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK10G_SHIFT 2 24352 24353 /* sys_device7 :: link_status :: l_link_status [01:01] */ 24354 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_STATUS_MASK 0x0002 24355 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_STATUS_ALIGN 0 24356 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_STATUS_BITS 1 24357 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_STATUS_SHIFT 1 24358 24359 /* sys_device7 :: link_status :: l_link [00:00] */ 24360 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_MASK 0x0001 24361 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_ALIGN 0 24362 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_BITS 1 24363 #define PHY84328_SYS_DEV7_LINK_STATUS_L_LINK_SHIFT 0 24364 24365 24366 /**************************************************************************** 24367 * sys_device7 :: actual_speed 24368 */ 24369 /* sys_device7 :: actual_speed :: reserved0 [15:14] */ 24370 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_RESERVED0_MASK 0xc000 24371 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_RESERVED0_ALIGN 0 24372 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_RESERVED0_BITS 2 24373 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_RESERVED0_SHIFT 14 24374 24375 /* sys_device7 :: actual_speed :: actual_speed_rx [13:08] */ 24376 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_RX_MASK 0x3f00 24377 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_RX_ALIGN 0 24378 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_RX_BITS 6 24379 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_RX_SHIFT 8 24380 24381 /* sys_device7 :: actual_speed :: reserved1 [07:06] */ 24382 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_RESERVED1_MASK 0x00c0 24383 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_RESERVED1_ALIGN 0 24384 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_RESERVED1_BITS 2 24385 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_RESERVED1_SHIFT 6 24386 24387 /* sys_device7 :: actual_speed :: actual_speed_tx [05:00] */ 24388 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_TX_MASK 0x003f 24389 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_TX_ALIGN 0 24390 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_TX_BITS 6 24391 #define PHY84328_SYS_DEV7_ACTUAL_SPEED_ACTUAL_SPEED_TX_SHIFT 0 24392 24393 24394 /**************************************************************************** 24395 * sys_device7 :: mp5_NextPageCtrl 24396 */ 24397 /* sys_device7 :: mp5_NextPageCtrl :: reserved0 [15:04] */ 24398 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_RESERVED0_MASK 0xfff0 24399 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_RESERVED0_ALIGN 0 24400 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_RESERVED0_BITS 12 24401 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_RESERVED0_SHIFT 4 24402 24403 /* sys_device7 :: mp5_NextPageCtrl :: np_sw_overRide_en [03:03] */ 24404 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_MASK 0x0008 24405 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_ALIGN 0 24406 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_BITS 1 24407 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_SHIFT 3 24408 24409 /* sys_device7 :: mp5_NextPageCtrl :: teton_mode_up3_en [02:02] */ 24410 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_MASK 0x0004 24411 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_ALIGN 0 24412 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_BITS 1 24413 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_SHIFT 2 24414 24415 /* sys_device7 :: mp5_NextPageCtrl :: teton_mode [01:01] */ 24416 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_MASK 0x0002 24417 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_ALIGN 0 24418 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_BITS 1 24419 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_TETON_MODE_SHIFT 1 24420 24421 /* sys_device7 :: mp5_NextPageCtrl :: bam_mode [00:00] */ 24422 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_BAM_MODE_MASK 0x0001 24423 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_BAM_MODE_ALIGN 0 24424 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_BAM_MODE_BITS 1 24425 #define PHY84328_SYS_DEV7_MP5_NEXTPAGECTRL_BAM_MODE_SHIFT 0 24426 24427 24428 /**************************************************************************** 24429 * sys_device7 :: link_timer_offset1 24430 */ 24431 /* sys_device7 :: link_timer_offset1 :: sgmii_offset [15:08] */ 24432 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1_SGMII_OFFSET_MASK 0xff00 24433 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1_SGMII_OFFSET_ALIGN 0 24434 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1_SGMII_OFFSET_BITS 8 24435 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1_SGMII_OFFSET_SHIFT 8 24436 24437 /* sys_device7 :: link_timer_offset1 :: max_offset [07:00] */ 24438 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1_MAX_OFFSET_MASK 0x00ff 24439 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1_MAX_OFFSET_ALIGN 0 24440 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1_MAX_OFFSET_BITS 8 24441 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET1_MAX_OFFSET_SHIFT 0 24442 24443 24444 /**************************************************************************** 24445 * sys_device7 :: link_timer_offset2 24446 */ 24447 /* sys_device7 :: link_timer_offset2 :: link_up_offset [15:08] */ 24448 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_MASK 0xff00 24449 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_ALIGN 0 24450 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_BITS 8 24451 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_SHIFT 8 24452 24453 /* sys_device7 :: link_timer_offset2 :: link_down_offset [07:00] */ 24454 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_MASK 0x00ff 24455 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_ALIGN 0 24456 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_BITS 8 24457 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_SHIFT 0 24458 24459 24460 /**************************************************************************** 24461 * sys_device7 :: link_timer_offset3 24462 */ 24463 /* sys_device7 :: link_timer_offset3 :: break_link_offset [15:08] */ 24464 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_MASK 0xff00 24465 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_ALIGN 0 24466 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_BITS 8 24467 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_SHIFT 8 24468 24469 /* sys_device7 :: link_timer_offset3 :: np_link_offset [07:00] */ 24470 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_MASK 0x00ff 24471 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_ALIGN 0 24472 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_BITS 8 24473 #define PHY84328_SYS_DEV7_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_SHIFT 0 24474 24475 24476 /**************************************************************************** 24477 * sys_device7 :: oui_msb_field 24478 */ 24479 /* sys_device7 :: oui_msb_field :: reserved0 [15:11] */ 24480 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD_RESERVED0_MASK 0xf800 24481 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD_RESERVED0_ALIGN 0 24482 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD_RESERVED0_BITS 5 24483 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD_RESERVED0_SHIFT 11 24484 24485 /* sys_device7 :: oui_msb_field :: oui_msb_field [10:00] */ 24486 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK 0x07ff 24487 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN 0 24488 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS 11 24489 #define PHY84328_SYS_DEV7_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT 0 24490 24491 24492 /**************************************************************************** 24493 * sys_device7 :: oui_lsb_field 24494 */ 24495 /* sys_device7 :: oui_lsb_field :: reserved0 [15:11] */ 24496 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD_RESERVED0_MASK 0xf800 24497 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD_RESERVED0_ALIGN 0 24498 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD_RESERVED0_BITS 5 24499 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD_RESERVED0_SHIFT 11 24500 24501 /* sys_device7 :: oui_lsb_field :: oui_lsb_field [10:00] */ 24502 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK 0x07ff 24503 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN 0 24504 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS 11 24505 #define PHY84328_SYS_DEV7_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT 0 24506 24507 24508 /**************************************************************************** 24509 * sys_device7 :: ud_field 24510 */ 24511 /* sys_device7 :: ud_field :: reserved0 [15:11] */ 24512 #define PHY84328_SYS_DEV7_UD_FIELD_RESERVED0_MASK 0xf800 24513 #define PHY84328_SYS_DEV7_UD_FIELD_RESERVED0_ALIGN 0 24514 #define PHY84328_SYS_DEV7_UD_FIELD_RESERVED0_BITS 5 24515 #define PHY84328_SYS_DEV7_UD_FIELD_RESERVED0_SHIFT 11 24516 24517 /* sys_device7 :: ud_field :: ud_reserved [10:06] */ 24518 #define PHY84328_SYS_DEV7_UD_FIELD_UD_RESERVED_MASK 0x07c0 24519 #define PHY84328_SYS_DEV7_UD_FIELD_UD_RESERVED_ALIGN 0 24520 #define PHY84328_SYS_DEV7_UD_FIELD_UD_RESERVED_BITS 5 24521 #define PHY84328_SYS_DEV7_UD_FIELD_UD_RESERVED_SHIFT 6 24522 24523 /* sys_device7 :: ud_field :: remote_BN_page [05:05] */ 24524 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 24525 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 24526 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_BN_PAGE_BITS 1 24527 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 24528 24529 /* sys_device7 :: ud_field :: inband_MDIO [04:04] */ 24530 #define PHY84328_SYS_DEV7_UD_FIELD_INBAND_MDIO_MASK 0x0010 24531 #define PHY84328_SYS_DEV7_UD_FIELD_INBAND_MDIO_ALIGN 0 24532 #define PHY84328_SYS_DEV7_UD_FIELD_INBAND_MDIO_BITS 1 24533 #define PHY84328_SYS_DEV7_UD_FIELD_INBAND_MDIO_SHIFT 4 24534 24535 /* sys_device7 :: ud_field :: autoneg_MDIO [03:03] */ 24536 #define PHY84328_SYS_DEV7_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 24537 #define PHY84328_SYS_DEV7_UD_FIELD_AUTONEG_MDIO_ALIGN 0 24538 #define PHY84328_SYS_DEV7_UD_FIELD_AUTONEG_MDIO_BITS 1 24539 #define PHY84328_SYS_DEV7_UD_FIELD_AUTONEG_MDIO_SHIFT 3 24540 24541 /* sys_device7 :: ud_field :: remote_serdes_phy [02:02] */ 24542 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 24543 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 24544 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 24545 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 24546 24547 /* sys_device7 :: ud_field :: remote_cu_phy [01:01] */ 24548 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 24549 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 24550 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_CU_PHY_BITS 1 24551 #define PHY84328_SYS_DEV7_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 24552 24553 /* sys_device7 :: ud_field :: over1g [00:00] */ 24554 #define PHY84328_SYS_DEV7_UD_FIELD_OVER1G_MASK 0x0001 24555 #define PHY84328_SYS_DEV7_UD_FIELD_OVER1G_ALIGN 0 24556 #define PHY84328_SYS_DEV7_UD_FIELD_OVER1G_BITS 1 24557 #define PHY84328_SYS_DEV7_UD_FIELD_OVER1G_SHIFT 0 24558 24559 24560 /**************************************************************************** 24561 * sys_device7 :: lp_ud_field 24562 */ 24563 /* sys_device7 :: lp_ud_field :: reserved0 [15:11] */ 24564 #define PHY84328_SYS_DEV7_LP_UD_FIELD_RESERVED0_MASK 0xf800 24565 #define PHY84328_SYS_DEV7_LP_UD_FIELD_RESERVED0_ALIGN 0 24566 #define PHY84328_SYS_DEV7_LP_UD_FIELD_RESERVED0_BITS 5 24567 #define PHY84328_SYS_DEV7_LP_UD_FIELD_RESERVED0_SHIFT 11 24568 24569 /* sys_device7 :: lp_ud_field :: ud_reserved [10:06] */ 24570 #define PHY84328_SYS_DEV7_LP_UD_FIELD_UD_RESERVED_MASK 0x07c0 24571 #define PHY84328_SYS_DEV7_LP_UD_FIELD_UD_RESERVED_ALIGN 0 24572 #define PHY84328_SYS_DEV7_LP_UD_FIELD_UD_RESERVED_BITS 5 24573 #define PHY84328_SYS_DEV7_LP_UD_FIELD_UD_RESERVED_SHIFT 6 24574 24575 /* sys_device7 :: lp_ud_field :: remote_BN_page [05:05] */ 24576 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 24577 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 24578 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_BN_PAGE_BITS 1 24579 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 24580 24581 /* sys_device7 :: lp_ud_field :: inband_MDIO [04:04] */ 24582 #define PHY84328_SYS_DEV7_LP_UD_FIELD_INBAND_MDIO_MASK 0x0010 24583 #define PHY84328_SYS_DEV7_LP_UD_FIELD_INBAND_MDIO_ALIGN 0 24584 #define PHY84328_SYS_DEV7_LP_UD_FIELD_INBAND_MDIO_BITS 1 24585 #define PHY84328_SYS_DEV7_LP_UD_FIELD_INBAND_MDIO_SHIFT 4 24586 24587 /* sys_device7 :: lp_ud_field :: autoneg_MDIO [03:03] */ 24588 #define PHY84328_SYS_DEV7_LP_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 24589 #define PHY84328_SYS_DEV7_LP_UD_FIELD_AUTONEG_MDIO_ALIGN 0 24590 #define PHY84328_SYS_DEV7_LP_UD_FIELD_AUTONEG_MDIO_BITS 1 24591 #define PHY84328_SYS_DEV7_LP_UD_FIELD_AUTONEG_MDIO_SHIFT 3 24592 24593 /* sys_device7 :: lp_ud_field :: remote_serdes_phy [02:02] */ 24594 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 24595 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 24596 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 24597 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 24598 24599 /* sys_device7 :: lp_ud_field :: remote_cu_phy [01:01] */ 24600 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 24601 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 24602 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_CU_PHY_BITS 1 24603 #define PHY84328_SYS_DEV7_LP_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 24604 24605 /* sys_device7 :: lp_ud_field :: over1g [00:00] */ 24606 #define PHY84328_SYS_DEV7_LP_UD_FIELD_OVER1G_MASK 0x0001 24607 #define PHY84328_SYS_DEV7_LP_UD_FIELD_OVER1G_ALIGN 0 24608 #define PHY84328_SYS_DEV7_LP_UD_FIELD_OVER1G_BITS 1 24609 #define PHY84328_SYS_DEV7_LP_UD_FIELD_OVER1G_SHIFT 0 24610 24611 24612 /**************************************************************************** 24613 * sys_device7 :: SGMIIbasepage 24614 */ 24615 /* sys_device7 :: SGMIIbasepage :: reserved0 [15:12] */ 24616 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE_RESERVED0_MASK 0xf000 24617 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE_RESERVED0_ALIGN 0 24618 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE_RESERVED0_BITS 4 24619 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE_RESERVED0_SHIFT 12 24620 24621 /* sys_device7 :: SGMIIbasepage :: sgmii_basepage [11:00] */ 24622 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE_SGMII_BASEPAGE_MASK 0x0fff 24623 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE_SGMII_BASEPAGE_ALIGN 0 24624 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE_SGMII_BASEPAGE_BITS 12 24625 #define PHY84328_SYS_DEV7_SGMIIBASEPAGE_SGMII_BASEPAGE_SHIFT 0 24626 24627 24628 /**************************************************************************** 24629 * sys_device7 :: UP5 24630 */ 24631 /* sys_device7 :: UP5 :: reserved0 [15:11] */ 24632 #define PHY84328_SYS_DEV7_UP5_RESERVED0_MASK 0xf800 24633 #define PHY84328_SYS_DEV7_UP5_RESERVED0_ALIGN 0 24634 #define PHY84328_SYS_DEV7_UP5_RESERVED0_BITS 5 24635 #define PHY84328_SYS_DEV7_UP5_RESERVED0_SHIFT 11 24636 24637 /* sys_device7 :: UP5 :: last [10:10] */ 24638 #define PHY84328_SYS_DEV7_UP5_LAST_MASK 0x0400 24639 #define PHY84328_SYS_DEV7_UP5_LAST_ALIGN 0 24640 #define PHY84328_SYS_DEV7_UP5_LAST_BITS 1 24641 #define PHY84328_SYS_DEV7_UP5_LAST_SHIFT 10 24642 24643 /* sys_device7 :: UP5 :: reserved1 [09:00] */ 24644 #define PHY84328_SYS_DEV7_UP5_RESERVED1_MASK 0x03ff 24645 #define PHY84328_SYS_DEV7_UP5_RESERVED1_ALIGN 0 24646 #define PHY84328_SYS_DEV7_UP5_RESERVED1_BITS 10 24647 #define PHY84328_SYS_DEV7_UP5_RESERVED1_SHIFT 0 24648