phy82328.h (735499B)
1 /*************************************************************************** 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * Copyright (c) 1999-2013, Broadcom Corporation 7 * All Rights Reserved 8 * Confidential Property of Broadcom Corporation 9 * 10 * 11 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 12 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 13 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 14 * 15 * $brcm_Workfile: $ 16 * $brcm_Revision: $ 17 * $brcm_Date: $ 18 * 19 * Module Description: 20 * DO NOT EDIT THIS FILE DIRECTLY 21 * 22 * This module was generated magically with RDB from a source description 23 * file. You must edit the source file for changes to be made to this file. 24 * 25 * 26 * Date: Generated on Fri Jun 28 04:13:30 2013 27 * MD5 Checksum 327f72e85e64afb2b473248f4b1b9231 28 * 29 * Compiled with: RDB Utility 5.0 30 * RDB Parser 3.0 31 * rdb2macro.pm 4.0 32 * Perl Interpreter 5.008008 33 * Operating System solaris 34 * 35 * Spec Versions: BASER_PCS_DETECT 1 36 * GP2 1 37 * IEEE0_AN_BLK 1 38 * IEEE0_BLK_PMA_PMD 1 39 * IEEE10_BLK_PMA_PMD 1 40 * IEEE1_AN_BLK 1 41 * IEEE3_AN_BLK 1 42 * LN_FC_RX 1 43 * RX 1 44 * TX 1 45 * XGXS_BLK0 1 46 * XGXS_BLK1 1 47 * XGXS_BLK2 1 48 * XGXS_BLK8 1 49 * ams_rx 1 50 * ams_tx 1 51 * amscom 1 52 * ckrst_ctrl 1 53 * cl72_ieee_rx 1 54 * cl72_ieee_tx 1 55 * cl72_user_rx 1 56 * cl72_user_tx_rptr 1 57 * digcom_gallardo 1 58 * dsc_a 1 59 * dsc_b 1 60 * dsc_c 1 61 * dsc_d 1 62 * dsc_e 1 63 * mgt_top 1 64 * patt_gen 1 65 * pll_cal 1 66 * sigdet 1 67 * tlb_rx 1 68 * tlb_tx 1 69 * tx_fed_rptr 1 70 * tx_pi 1 71 * txcom_rptr 1 72 * 73 * RDB Files: /projects/ntsw-sw2/home/arunkuma/gallardo28/sdk/src/soc/phy/regs/scripts/Linux/phy82328_register.rdb 74 * 75 * Revision History: 76 * 77 * $brcm_Log: $ 78 */ 79 80 #ifndef PHY82328_H__ 81 #define PHY82328_H__ 82 83 /** 84 * m = memory, c = core, r = register, f = field, d = data. 85 */ 86 #if !defined(GET_FIELD) && !defined(SET_FIELD) 87 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 88 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 89 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 90 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 91 92 #define GET_FIELD(m,c,r,f) \ 93 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 94 95 #define SET_FIELD(m,c,r,f,d) \ 96 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 97 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 98 ) 99 100 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 101 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 102 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 103 104 #endif /* GET & SET */ 105 106 #define PHY82328_C45_DEV_PMA_PMD 0x01 107 #define PHY82328_C45_DEV_AN 0x07 108 109 #define PHY82328_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 110 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 111 #define PHY82328_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 112 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 113 #define PHY82328_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 114 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 115 116 /* 117 * Line side 118 */ 119 /* PMA/PMD Device (Dev Addr 1) */ 120 #define READ_PHY82328_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 121 PHY82328_REG_READ((_unit), (_phy_ctrl), \ 122 SOC_PHY_CLAUSE45_ADDR(PHY82328_C45_DEV_PMA_PMD, (_reg)), (_val)) 123 #define WRITE_PHY82328_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 124 PHY82328_REG_WRITE((_unit), (_phy_ctrl), \ 125 SOC_PHY_CLAUSE45_ADDR(PHY82328_C45_DEV_PMA_PMD, (_reg)), (_val)) 126 #define MODIFY_PHY82328_MMF_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 127 PHY82328_REG_MODIFY((_unit), (_phy_ctrl), \ 128 SOC_PHY_CLAUSE45_ADDR(PHY82328_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask)) 129 130 /* AN Device (Dev Addr 7) */ 131 #define READ_PHY82328_MMF_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 132 PHY82328_REG_READ((_unit), (_phy_ctrl), \ 133 SOC_PHY_CLAUSE45_ADDR(PHY82328_C45_DEV_AN, (_reg)), (_val)) 134 #define WRITE_PHY82328_MMF_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 135 PHY82328_REG_WRITE((_unit), (_phy_ctrl), \ 136 SOC_PHY_CLAUSE45_ADDR(PHY82328_C45_DEV_AN, (_reg)), (_val)) 137 #define MODIFY_PHY82328_MMF_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 138 PHY82328_REG_MODIFY((_unit), (_phy_ctrl), \ 139 SOC_PHY_CLAUSE45_ADDR(PHY82328_C45_DEV_AN, (_reg)), (_val), (_mask)) 140 141 142 /**************************************************************************** 143 * Core Enums. 144 */ 145 /**************************************************************************** 146 * merlin_gallardo_mgt_top_blk_MGT_TOP_I2C 147 */ 148 #define MGT_TOP_I2C_CONTROL_REGISTER 0x00008000 /* I2C Control Register */ 149 #define MGT_TOP_I2C_CHECK_SUM_REGISTER 0x00008001 /* I2C Check Sum Register */ 150 #define MGT_TOP_I2C_TRANSFER_SIZE_REGISTER 0x00008002 /* I2C Transfer Size Register */ 151 #define MGT_TOP_I2C_EXTERNAL_NVM_ADDRESS_REGISTER 0x00008003 /* I2C External NVM Address Register */ 152 #define MGT_TOP_I2C_INTERNAL_ADDRESS_REGISTER 0x00008004 /* I2C Internal Address Register */ 153 #define MGT_TOP_I2C_SLAVE_ID_ADDRESS_REGISTER 0x00008005 /* I2C Slave ID Address Register */ 154 155 156 /**************************************************************************** 157 * merlin_gallardo_mgt_top_blk_MGT_TOP_PMD_USR 158 */ 159 #define MGT_TOP_PWR_RAMP 0x0000c800 /* PHY Identifier */ 160 #define MGT_TOP_CHIP_REV_REGISTER 0x0000c801 /* Chip REV Register */ 161 #define MGT_TOP_CHIP_ID0_REGISTER 0x0000c802 /* Chip ID 0 Register */ 162 #define MGT_TOP_CHIP_ID1_REGISTER 0x0000c803 /* Chip ID 1 Register */ 163 #define MGT_TOP_PMD_STATUS_REGISTER 0x0000c804 /* PMD Status Register */ 164 #define MGT_TOP_GPIO_CONTROL_REGISTER 0x0000c808 /* GPIO Control Register */ 165 #define MGT_TOP_GP_IO_CONTROL_REGISTER 0x0000c80e /* General Purpose IO Control Register */ 166 #define MGT_TOP_SPEED_LINK_DETECT_STATUS 0x0000c81f /* Speed Link Detect Status */ 167 #define MGT_TOP_CH_RESET_CONTROL 0x0000c822 /* Channel SW Reset Control */ 168 #define MGT_TOP_CL73_PARALLEL_PORT_ADDRESS_PORT 0x0000c828 /* Cl-73 Parallel Port Address Port */ 169 #define MGT_TOP_XCL73_PARALLEL_PORT_ADDRESS_PORT 0x0000c82c /* XCl-73 Parallel Port Address Port */ 170 #define MGT_TOP_PAD_CTRL_REGISTER 0x0000c82f /* I2C RxLos And MOD-ABS PAD Control */ 171 #define MGT_TOP_INTERRUPT_M8051_REGISTER 0x0000c830 /* Interrupt Register */ 172 #define MGT_TOP_INTERRUPT_M8051_ENABLE_REGISTER 0x0000c831 /* Interrupt Enable Register */ 173 #define MGT_TOP_INTERRUPT_M8051_STATUS_REGISTER 0x0000c832 /* Interrupt Status Register */ 174 #define MGT_TOP_INTERRUPT_M8051_POLARITY_REGISTER 0x0000c833 /* Interrupt Polarity Register */ 175 #define MGT_TOP_GP_REGISTER_0 0x0000c840 /* General Purpose Register-0 */ 176 #define MGT_TOP_GP_REGISTER_1 0x0000c841 /* General Purpose Register-1 */ 177 #define MGT_TOP_GP_REGISTER_2 0x0000c842 /* General Purpose Register-2 */ 178 #define MGT_TOP_GP_REGISTER_3 0x0000c843 /* General Purpose Register-3 */ 179 #define MGT_TOP_GP_STATUS_REGISTER_0 0x0000c844 /* GP Misc. Status Register-0 */ 180 #define MGT_TOP_GP_STATUS_REGISTER_1 0x0000c845 /* GP Misc. Status Register-1 */ 181 #define MGT_TOP_SPA_CONTROL_STATUS_REGISTER 0x0000c848 /* SPI Port Control/Status Register */ 182 #define MGT_TOP_OTP_MISC_SIG1_REGISTER 0x0000c858 /* OTP MISC Signal1 Register */ 183 #define MGT_TOP_OTP_MISC_SIG2_REGISTER 0x0000c859 /* OTP MISC Signal2 Register */ 184 #define MGT_TOP_OTP_MISC_SIG3_REGISTER 0x0000c85a /* OTP MISC Signal3 Register */ 185 #define MGT_TOP_OTP_MISC_SIG4_REGISTER 0x0000c85b /* OTP MISC Signal4 Register */ 186 #define MGT_TOP_OTP_MISC_SIG5_REGISTER 0x0000c85c /* OTP MISC Signal5 Register */ 187 #define MGT_TOP_OTP_MISC_SIG6_REGISTER 0x0000c85d /* OTP MISC Signal6 Register */ 188 #define MGT_TOP_GP_REG_C870_REGISTER 0x0000c870 /* GP Reg @C870 Register */ 189 #define MGT_TOP_M8051_WATCHDOG_CONTROL_REGISTER 0x0000c872 /* m8051 Watchdog Control Register */ 190 #define MGT_TOP_M8051_WATCHDOG_STATUS_REGISTER 0x0000c873 /* m8051 Watchdog Status Register */ 191 #define MGT_TOP_CHIP_INTR_STAT 0x0000c874 /* Chip interrupt status register */ 192 #define MGT_TOP_CHIP_INTR_EN 0x0000c876 /* Interrupt Enable register */ 193 #define MGT_TOP_CHIP_INTR_VALUE 0x0000c878 /* Chip interrupt value register */ 194 #define MGT_TOP_CHIP_INTR_CTRL 0x0000c87a /* Chip interrupt control register */ 195 #define MGT_TOP_CH_INTR_CTRL 0x0000c87c /* Chip global interrupt control register */ 196 #define MGT_TOP_OTP_OVR_REV_ID_REGISTER 0x0000c88b /* OTP_OVR_REV_ID_REG */ 197 #define MGT_TOP_OTP_OVR_CHP_ID0_REGISTER 0x0000c88c /* OTP_OVR_REV_ID0_REG */ 198 #define MGT_TOP_OTP_OVR_CHP_ID1_REGISTER 0x0000c88d /* OTP_OVR_REV_ID1_REG */ 199 #define MGT_TOP_OTP_RDY_CNT_STAT_REG 0x0000c88e /* OTP_RDY_CNT_STAT_REG */ 200 #define MGT_TOP_OTP_OVR_DEVICE_ID_0 0x0000c890 /* OTP Override Device ID 0. */ 201 #define MGT_TOP_OTP_OVR_DEVICE_ID_1 0x0000c891 /* OTP Override Device ID 1. */ 202 #define MGT_TOP_OTP_OVR_DEVICE_ID_0_1_CNTL 0x0000c892 /* OTP Override Control for Device id0 and id1. */ 203 #define MGT_TOP_DIE_ID 0x0000c899 /* Die ID register */ 204 #define MGT_TOP_OPTICAL_CONFIGURATION 0x0000c8e4 /* Optical Configuration */ 205 #define MGT_TOP_BROADCAST_CTRL 0x0000c8fe /* Select Broadcast Mechanism for MDIO ADDR/Write Operations. */ 206 #define MGT_TOP_XPMD_REGS_SEL 0x0000ffff /* Select System Side Registers For MDIO OP. */ 207 208 209 /**************************************************************************** 210 * merlin_gallardo_mgt_top_blk_MGT_TOP_CMN_CTLR 211 */ 212 #define MGT_TOP_REGUALTOR_CTRL 0x0000c850 /* Regulator_control */ 213 #define MGT_TOP_GEN_CTRL 0x0000ca10 /* GEN_CTRL */ 214 #define MGT_TOP_RAM_LWPR_CTRL 0x0000ca11 /* RAM_LWPR_CTRL */ 215 #define MGT_TOP_MSG_IN 0x0000ca12 /* MSG_IN */ 216 #define MGT_TOP_MSG_OUT 0x0000ca13 /* MSG_OUT */ 217 #define MGT_TOP_ERRORED_SRAM_ADDRESS 0x0000ca14 /* SRAM_ADDRESS_WITH_ERROR */ 218 #define MGT_TOP_ERRORED_SRAM_DATA 0x0000ca15 /* SRAM_ERROR_STATUS */ 219 #define MGT_TOP_GP_REG_0 0x0000ca18 /* GP_REG_0 */ 220 #define MGT_TOP_GP_REG_1 0x0000ca19 /* GP_REG_1 */ 221 #define MGT_TOP_GP_REG_2 0x0000ca1a /* GP_REG_2 */ 222 #define MGT_TOP_GP_REG_3 0x0000ca1b /* GP_REG_3 */ 223 #define MGT_TOP_GP_REG_4 0x0000ca1c /* GP_REG_4 */ 224 #define MGT_TOP_FW_PARAM 0x0000ca1d /* FW_PARAM */ 225 #define MGT_TOP_FW_CMD 0x0000ca1e /* FW_CMD */ 226 #define MGT_TOP_HEARTBEAT_COUNT 0x0000ca1f /* HEARTBEAT_COUNT */ 227 #define MGT_TOP_LOGAD_CTRL 0x0000ca7b /* LOG_CTRL */ 228 #define MGT_TOP_SW_RESET_CTRL 0x0000ca82 /* SW_RESET_CTRL */ 229 #define MGT_TOP_MISC_CTRL 0x0000ca85 /* MISC_CTRL */ 230 #define MGT_TOP_SINGLE_PMD_CTRL 0x0000ca86 /* SINGLE_PMD_CTRL */ 231 #define MGT_TOP_GP_REG_5 0x0000ca88 /* GP_REG_5 */ 232 #define MGT_TOP_GP_REG_6 0x0000ca89 /* GP_REG_6 */ 233 #define MGT_TOP_GP_REG_7 0x0000ca8a /* GP_REG_7 */ 234 #define MGT_TOP_GP_REG_8 0x0000ca8b /* GP_REG_8 */ 235 #define MGT_TOP_GP_REG_9 0x0000ca8c /* GP_REG_9 */ 236 #define MGT_TOP_MEMORY_TM_CTRL_0 0x0000cbe0 /* MEMORY_TM_CTRL_0 */ 237 #define MGT_TOP_MEMORY_TM_CTRL_1 0x0000cbe1 /* MEMORY_TM_CTRL_1 */ 238 #define MGT_TOP_MEMORY_STBY_CTRL_0 0x0000cbe2 /* MEMORY_STBY_CTRL_0 */ 239 #define MGT_TOP_VTMON_CTRL_0 0x0000cbf0 /* VTMON_CTRL_0 */ 240 #define MGT_TOP_VTMON_CTRL_1 0x0000cbf1 /* VTMON_CTRL_1 */ 241 #define MGT_TOP_VTMON_STATUS 0x0000cbf2 /* VTMON_STATUS */ 242 #define MGT_TOP_VTMON_CTRL_2 0x0000cbf3 /* VTMON_CTRL_2 */ 243 #define MGT_TOP_RESCAL_CTRL_DFS 0x0000cbf4 /* RESCAL_ctrl_dfs_type */ 244 #define MGT_TOP_RESCAL_STATUS 0x0000cbf5 /* RESCAL_status_type */ 245 #define MGT_TOP_RESCAL_CTRL 0x0000cbf6 /* RESCAL_ctrl_type */ 246 #define MGT_TOP_RING_OSC_CONTROL_REGISTER 0x0000cbf7 /* Ring Oscillator Control Register */ 247 #define MGT_TOP_IO_RING_CONTROL 0x0000cbf8 /* Chip IO Ring Control Register */ 248 #define MGT_TOP_CHARGE_PUMP_CONTROL_1 0x0000cbf9 /* Charge Pump Control 1 Register */ 249 #define MGT_TOP_CHARGE_PUMP_CONTROL_2 0x0000cbfa /* Charge Pump Control 2 Register */ 250 #define MGT_TOP_CHARGE_PUMP_CONTROL_3 0x0000cbfb /* Charge Pump Control 3 Register */ 251 252 253 /**************************************************************************** 254 * merlin_gallardo_mgt_top_blk_MGT_TOP_LK_MTR_TMR 255 */ 256 #define MGT_TOP_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0 0x0000ca90 /* Link Monitor Timer Control Status Register 0 */ 257 #define MGT_TOP_LINK_MON_TIMER_COUNT_REGISTER_0 0x0000ca91 /* Link Monitor Timer Count Register 0 */ 258 #define MGT_TOP_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1 0x0000ca92 /* Link Monitor Timer Control Status Register 1 */ 259 #define MGT_TOP_LINK_MON_TIMER_COUNT_REGISTER_1 0x0000ca93 /* Link Monitor Timer Count Register 1 */ 260 #define MGT_TOP_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2 0x0000ca94 /* Link Monitor Timer Control Status Register 2 */ 261 #define MGT_TOP_LINK_MON_TIMER_COUNT_REGISTER_2 0x0000ca95 /* Link Monitor Timer Count Register 2 */ 262 #define MGT_TOP_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3 0x0000ca96 /* Link Monitor Timer Control Status Register 3 */ 263 #define MGT_TOP_LINK_MON_TIMER_COUNT_REGISTER_3 0x0000ca97 /* Link Monitor Timer Count Register 3 */ 264 #define MGT_TOP_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4 0x0000ca98 /* Link Monitor Timer Control Status Register 4 */ 265 #define MGT_TOP_LINK_MON_TIMER_COUNT_REGISTER_4 0x0000ca99 /* Link Monitor Timer Count Register 4 */ 266 #define MGT_TOP_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5 0x0000ca9a /* Link Monitor Timer Control Status Register 5 */ 267 #define MGT_TOP_LINK_MON_TIMER_COUNT_REGISTER_5 0x0000ca9b /* Link Monitor Timer Count Register 5 */ 268 #define MGT_TOP_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6 0x0000ca9c /* Link Monitor Timer Control Status Register 6 */ 269 #define MGT_TOP_LINK_MON_TIMER_COUNT_REGISTER_6 0x0000ca9d /* Link Monitor Timer Count Register 6 */ 270 #define MGT_TOP_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7 0x0000ca9e /* Link Monitor Timer Control Status Register 7 */ 271 #define MGT_TOP_LINK_MON_TIMER_COUNT_REGISTER_7 0x0000ca9f /* Link Monitor Timer Count Register 7 */ 272 273 274 /**************************************************************************** 275 * merlin_gallardo_qsfi_blk_QSFI_IEEE0 276 */ 277 #define IEEE0_BLK_PMA_PMD_PMD_CONTROL_REGISTER 0x00000000 /* ieee Control1 register */ 278 #define IEEE0_BLK_PMA_PMD_STATUS_REGISTER 0x00000001 /* ieee Status 1 register */ 279 #define IEEE0_BLK_PMA_PMD_PMD_IDENTIFIER_REGISTER_0 0x00000002 /* PMD Identifier Register 0 */ 280 #define IEEE0_BLK_PMA_PMD_PMD_IDENTIFIER_REGISTER_1 0x00000003 /* PMD Identifier Register 1 */ 281 #define IEEE0_BLK_PMA_PMD_PMD_SPEED_ABILITY 0x00000004 /* ieee PMD Speed Ability register */ 282 #define IEEE0_BLK_PMA_PMD_DEVICES_IN_PACKAGE_1 0x00000005 /* ieee Device in Package 1 register */ 283 #define IEEE0_BLK_PMA_PMD_DEVICES_IN_PACKAGE_2 0x00000006 /* ieee Device in Package 1 register */ 284 #define IEEE0_BLK_PMA_PMD_PMD_CONTROL_2_REGISTER 0x00000007 /* ieee Control2 register */ 285 #define IEEE0_BLK_PMA_PMD_STATUS_REGISTER_2 0x00000008 /* ieee Status 2 register */ 286 #define IEEE0_BLK_PMA_PMD_PMD_TRANSMIT_DISABLE_REGISTER 0x00000009 /* ieee Transmit Disable register */ 287 #define IEEE0_BLK_PMA_PMD_PMD_RECEIVE_SIGNAL_DETECT_REGISTER 0x0000000a /* ieee receive Signal Detect register */ 288 #define IEEE0_BLK_PMA_PMD_PMD_EXTENDED_ABILITY_REGISTER 0x0000000b /* ieee Extended Ability register */ 289 #define IEEE0_BLK_PMA_PMD_FORTYG_PMD_EXTENDED_ABILITY_REGISTER 0x0000000d /* Fortyg PMD extended ability Register */ 290 #define IEEE0_BLK_PMA_PMD_PMD_OUI_ID0_REGISTER 0x0000000e /* PMD OUI ID0 Register */ 291 #define IEEE0_BLK_PMA_PMD_PMD_OUI_ID1_REG 0x0000000f /* PMD OUI ID1 Reg */ 292 293 294 /**************************************************************************** 295 * merlin_gallardo_qsfi_cl73_QSFI_AN_IEEE1 296 */ 297 #define IEEE1_AN_BLK_AN_ADVERTISEMENT_1_REGISTER 0x00000010 /* AN Advertisement 1 Register */ 298 #define IEEE1_AN_BLK_AN_ADVERTISEMENT_2_REGISTER 0x00000011 /* AN Advertisement 2 Register */ 299 #define IEEE1_AN_BLK_AN_ADVERTISEMENT_3_REGISTER 0x00000012 /* AN Advertisement 3 Register */ 300 #define IEEE1_AN_BLK_AN_LP_BASE_PAGE_ABILITY_1_REG 0x00000013 /* AN LP Base Page Ability 1 Register */ 301 #define IEEE1_AN_BLK_AN_LP_BASE_PAGE_ABILITY_2_REG 0x00000014 /* AN LP Base Page Ability 2 Register */ 302 #define IEEE1_AN_BLK_AN_LP_BASE_PAGE_ABILITY_3_REG 0x00000015 /* AN LP Base Page Ability 3 Register */ 303 #define IEEE1_AN_BLK_AN_XNP_TRANSMIT_1_REGISTER 0x00000016 /* AN XNP transmit 1 Register */ 304 #define IEEE1_AN_BLK_AN_XNP_TRANSMIT_2_REGISTER 0x00000017 /* AN XNP transmit 2 Register */ 305 #define IEEE1_AN_BLK_AN_XNP_TRANSMIT_3_REGISTER 0x00000018 /* AN XNP transmit 3 Register */ 306 #define IEEE1_AN_BLK_AN_LP_XNP_TRANSMIT_1_REGISTER 0x00000019 /* AN LP XNP transmit 1 Registe */ 307 #define IEEE1_AN_BLK_AN_LP_XNP_TRANSMIT_2_REGISTER 0x0000001a /* AN LP XNP transmit 2 Register */ 308 #define IEEE1_AN_BLK_AN_LP_XNP_TRANSMIT_3_REGISTER 0x0000001b /* AN LP XNP transmit 3 Register */ 309 310 311 /**************************************************************************** 312 * merlin_gallardo_qsfi_cl73_QSFI_AN_IEEE3 313 */ 314 #define IEEE3_AN_BLK_BACKPLANE_ETHERNET_STATUS_REGISTER 0x00000030 /* BPEther Status register */ 315 #define IEEE3_AN_BLK_EEE_ADV 0x0000003c /* anEEE ADV control register */ 316 #define IEEE3_AN_BLK_EEE_LP_ADV 0x0000003d /* anEEE LP ADV Status register */ 317 318 319 /**************************************************************************** 320 * merlin_gallardo_cl72b_ieee_blk_CL72_IEEE_TX 321 */ 322 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150 0x00000096 /* BASE-R PMD control register 150 */ 323 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151 0x00000097 /* BASE-R PMD status register 151 */ 324 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152 0x00000098 /* BASE-R LP coeff update register 152 */ 325 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154 0x0000009a /* BASE-R LD coeff update register 154 */ 326 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155 0x0000009b /* BASE-R LD status report register 155 */ 327 328 329 /**************************************************************************** 330 * merlin_gallardo_cl72b_ieee_blk_CL72_IEEE_RX 331 */ 332 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153 0x00000099 /* BASE-R LP status report register 153 */ 333 334 335 /**************************************************************************** 336 * merlin_gallardo_qsfi_blk_QSFI_IEEE10 337 */ 338 #define IEEE10_BLK_PMA_PMD_TENGBASE_KX_CONTROL_REGISTER 0x000000a0 /* ieee 1000KX Control 1 register */ 339 #define IEEE10_BLK_PMA_PMD_TENGBASE_KX_STATUS_REGISTER 0x000000a1 /* ieee 1000KX Status 1 register */ 340 341 342 /**************************************************************************** 343 * merlin_gallardo_qsfi_blk_QSFI_XGXS_BLK0 344 */ 345 #define XGXS_BLK0_XGXSCONTROL 0x0000c000 /* XGXS Control register */ 346 #define XGXS_BLK0_XGXSSTATUS 0x0000c001 /* XGXS Status register */ 347 #define XGXS_BLK0_MISCCONTROL1 0x0000c00e /* Miscellaneous Control register */ 348 349 350 /**************************************************************************** 351 * merlin_gallardo_qsfi_blk_QSFI_XGXS_BLK1 352 */ 353 #define XGXS_BLK1_LANECTRL2 0x0000c017 /* Lane Control 2 register */ 354 #define XGXS_BLK1_LANECTRL3 0x0000c018 /* Lane Control 3 register */ 355 #define XGXS_BLK1_LANETEST 0x0000c01a /* Lane TEST register */ 356 357 358 /**************************************************************************** 359 * merlin_gallardo_qsfi_blk_QSFI_TX 360 */ 361 #define TX_ANATXASTATUS 0x0000c080 /* TX ANA Status register */ 362 #define TX_ANATXACONTROL0 0x0000c081 /* TX ANA Control 0 register */ 363 #define TX_ANATXACONTROL6 0x0000c08a /* TX Control 6 register */ 364 #define TX_ANATXACONTROL7 0x0000c08b /* TX Control 7 register */ 365 366 367 /**************************************************************************** 368 * merlin_gallardo_qsfi_blk_QSFI_RX 369 */ 370 #define RX_ANARXSTATUS 0x0000c0b0 /* Rx Status register */ 371 #define RX_ANARXCONTROL 0x0000c0b1 /* Rx Control1 register */ 372 #define RX_ANARXSIGDET 0x0000c0b4 /* Rx Sigdet control register */ 373 #define RX_ANARXCONTROL2 0x0000c0b6 /* Rx Control2 register */ 374 #define RX_ANARXCONTROL3 0x0000c0ba /* Rx Control3 register */ 375 376 377 /**************************************************************************** 378 * merlin_gallardo_qsfi_blk_QSFI_XGXS_BLK2 379 */ 380 #define XGXS_BLK2_LANERESET 0x0000c10a /* Lane reset register */ 381 382 383 /**************************************************************************** 384 * merlin_gallardo_qsfi_blk_QSFI_XGXS_BLK8 385 */ 386 #define XGXS_BLK8_CL73CONTROL8 0x0000c161 /* CL73 Control 8 Register */ 387 #define XGXS_BLK8_CL73CONTROL9 0x0000c162 /* CL73 Control 9 Register */ 388 #define XGXS_BLK8_CL73CONTROL10 0x0000c163 /* CL73 Control 10 Register */ 389 390 391 /**************************************************************************** 392 * merlin_gallardo_qsfi_blk_QSFI_GP2 393 */ 394 #define GP2_GP2_0 0x0000c1d0 /* PLL Status Register */ 395 #define GP2_GP2_1 0x0000c1d1 /* OSR Status Register */ 396 #define GP2_GP2_2 0x0000c1d2 /* speed lane 0 1 Register */ 397 #define GP2_GP2_3 0x0000c1d3 /* speed lane 2 3 Register */ 398 #define GP2_GP2_4 0x0000c1d4 /* Autoneg Status Register */ 399 #define GP2_GP2_5 0x0000c1d5 /* CL73_BAMStat1 Register */ 400 #define GP2_GP2_6 0x0000c1d6 /* CL73_BAMStat2 Register */ 401 #define GP2_GP2_7 0x0000c1d7 /* CL73_BAMStat3 Register */ 402 #define GP2_GP2_8 0x0000c1d8 /* an speed lane 0 1 Register */ 403 #define GP2_GP2_9 0x0000c1d9 /* an speed lane 2 3 Register */ 404 405 406 /**************************************************************************** 407 * merlin_gallardo_qsfi_blk_QSFI_FC_RX 408 */ 409 #define LN_FC_RX_LN_FC_RX_CONTROL_REG 0x0000c470 /* LN Fiber Channel Rx controls */ 410 #define LN_FC_RX_LN_FC_RX_STATUS_REG 0x0000c471 /* LN Fiber Channel Rx status */ 411 #define LN_FC_RX_LN_FC_RX_INTERRUPTS_REG 0x0000c472 /* LN Fiber Channel Rx interrupts */ 412 #define LN_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG 0x0000c473 /* LN Fiber Channel Rx interrupt enables */ 413 #define LN_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG 0x0000c474 /* LN Fiber Channel Rx Auto-Speed Detection configuration */ 414 #define LN_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS 0x0000c475 /* LN Fiber Channel Rx Auto-Speed Detection status */ 415 #define LN_FC_RX_LN_FC_RX_R_T_TOV 0x0000c476 /* LN Fiber Channel Rx Word Synchronization Watchdog */ 416 #define LN_FC_RX_LN_FC_RX_TPAT_MON_CONFIG 0x0000c477 /* LN Fiber Channel Rx Test Pattern Monitor configuration */ 417 #define LN_FC_RX_LN_FC_RX_TPAT_MON_STATUS 0x0000c478 /* LN Fiber Channel Rx Test Pattern Monitor status */ 418 #define LN_FC_RX_LN_FC_RX_RECEIVED_TPAT_CNT 0x0000c479 /* LN Fiber Channel Received Test Pattern counter */ 419 #define LN_FC_RX_LN_FC_RX_TPAT_ERROR_CNT 0x0000c47a /* LN Fiber Channel Rx Test Pattern error counter */ 420 421 422 /**************************************************************************** 423 * merlin_gallardo_qsfi_blk_QSFI_BASER 424 */ 425 #define BASER_PCS_DETECT_CONTROL_0 0x0000c480 /* Rx_BaseR_PCS_Detect control_0 register */ 426 #define BASER_PCS_DETECT_CONTROL_1 0x0000c481 /* Rx_BaseR_PCS_Detect control_1 register */ 427 #define BASER_PCS_DETECT_CONTROL_2 0x0000c482 /* Rx_BaseR_PCS_Detect control_2 register */ 428 #define BASER_PCS_DETECT_CONTROL_3 0x0000c483 /* Rx_BaseR_PCS_Detect control_3 register */ 429 #define BASER_PCS_DETECT_CONTROL_4 0x0000c484 /* Rx_BaseR_PCS_Detect control_4 register */ 430 #define BASER_PCS_DETECT_CONTROL_5 0x0000c485 /* Rx_BaseR_PCS_Detect control_5 register */ 431 #define BASER_PCS_DETECT_STATUS_0 0x0000c486 /* Rx_BaseR_PCS_Detect status_0 register */ 432 #define BASER_PCS_DETECT_STATUS_1 0x0000c487 /* Rx_BaseR_PCS_Detect status_1 register */ 433 #define BASER_PCS_DETECT_STATUS_2 0x0000c488 /* Rx_BaseR_PCS_Detect status_2 register */ 434 435 436 /**************************************************************************** 437 * merlin_gallardo_dsc_blk_DSC_A 438 */ 439 #define DSC_A_CDR_CONTROL_0 0x0000d001 /* CDR Control 0 */ 440 #define DSC_A_CDR_CONTROL_1 0x0000d002 /* CDR Control 1 */ 441 #define DSC_A_CDR_CONTROL_2 0x0000d003 /* CDR Control 2 */ 442 #define DSC_A_RX_PI_CONTROL 0x0000d004 /* RX PI control */ 443 #define DSC_A_CDR_STATUS_INTEG_REG 0x0000d005 /* CDR Status Integ Reg */ 444 #define DSC_A_CDR_STATUS_PHASE_ERROR 0x0000d006 /* CDR Status phase err */ 445 #define DSC_A_RX_PI_CNT_BIN_D 0x0000d007 /* Rx PI {P1, D} */ 446 #define DSC_A_RX_PI_CNT_BIN_P 0x0000d008 /* Rx PI {M1, P1} */ 447 #define DSC_A_RX_PI_CNT_BIN_M 0x0000d009 /* Rx PI {D, M1} */ 448 #define DSC_A_RX_PI_DIFF_BIN 0x0000d00a /* Rx PI {D-P1, D-M1} */ 449 #define DSC_A_TRNSUM_CNTL_5 0x0000d00b /* training sum control 5 */ 450 #define DSC_A_DSC_UC_CTRL 0x0000d00d /* DSC uC Control */ 451 #define DSC_A_DSC_SCRATCH 0x0000d00e /* DSC uC Control */ 452 453 454 /**************************************************************************** 455 * merlin_gallardo_dsc_blk_DSC_B 456 */ 457 #define DSC_B_DSC_SM_CTRL_0 0x0000d010 /* DSC STATE MACHINE CONTROL 0 */ 458 #define DSC_B_DSC_SM_CTRL_1 0x0000d011 /* DSC STATE MACHINE CONTROL 1 */ 459 #define DSC_B_DSC_SM_CTRL_2 0x0000d012 /* DSC STATE MACHINE CONTROL 2 */ 460 #define DSC_B_DSC_SM_CTRL_3 0x0000d013 /* DSC STATE MACHINE CONTROL 3 */ 461 #define DSC_B_DSC_SM_CTRL_4 0x0000d014 /* DSC STATE MACHINE CONTROL 4 */ 462 #define DSC_B_DSC_SM_CTRL_5 0x0000d015 /* DSC STATE MACHINE CONTROL 5 */ 463 #define DSC_B_DSC_SM_CTRL_6 0x0000d016 /* DSC STATE MACHINE CONTROL 6 */ 464 #define DSC_B_DSC_SM_CTRL_7 0x0000d017 /* DSC STATE MACHINE CONTROL 7 */ 465 #define DSC_B_DSC_SM_CTRL_8 0x0000d018 /* DSC STATE MACHINE CONTROL 8 */ 466 #define DSC_B_DSC_SM_CTRL_9 0x0000d019 /* DSC STATE MACHINE CONTROL 9 */ 467 #define DSC_B_DSC_SM_STATUS_DSC_LOCK 0x0000d01a /* DSC STATE MACHINE DSC_LOCK STATUS */ 468 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT 0x0000d01b /* DSC STATE MACHINE STATUS ONE HOT */ 469 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT 0x0000d01c /* DSC STATE MACHINE STATUS EEE ONE HOT */ 470 #define DSC_B_DSC_SM_STATUS_RESTART 0x0000d01d /* DSC STATE MACHINE STATUS RESTART */ 471 #define DSC_B_DSC_SM_STATUS_DSC_STATE 0x0000d01e /* DSC STATE MACHINE STATUS */ 472 473 474 /**************************************************************************** 475 * merlin_gallardo_dsc_blk_DSC_C 476 */ 477 #define DSC_C_DFE_COMMON_CTL 0x0000d020 /* DFE Common Control */ 478 #define DSC_C_DFE_1_CTL 0x0000d021 /* DFE 1 Control */ 479 #define DSC_C_DFE_1_PAT_CTL 0x0000d022 /* DFE 1 Pat Control */ 480 #define DSC_C_DFE_2_CTL 0x0000d023 /* DFE 2 Control */ 481 #define DSC_C_DFE_2_PAT_CTL 0x0000d024 /* DFE 2 Pat Control */ 482 #define DSC_C_DFE_3_CTL 0x0000d025 /* DFE 3 Control */ 483 #define DSC_C_DFE_3_PAT_CTL 0x0000d026 /* DFE 3 Pat Control */ 484 #define DSC_C_DFE_4_CTL 0x0000d027 /* DFE 4 Control */ 485 #define DSC_C_DFE_4_PAT_CTL 0x0000d028 /* DFE 4 Pat Control */ 486 #define DSC_C_DFE_5_CTL 0x0000d029 /* DFE 5 Control */ 487 #define DSC_C_DFE_5_PAT_CTL 0x0000d02a /* DFE 5 Pat Control */ 488 #define DSC_C_DFE_VGA_OVERRIDE 0x0000d02b /* DFE Overrude */ 489 #define DSC_C_VGA_CTL 0x0000d02c /* VGA Control */ 490 #define DSC_C_VGA_PAT_EYEDIAG_CTL 0x0000d02d /* VGA Pat Control */ 491 492 493 /**************************************************************************** 494 * merlin_gallardo_dsc_blk_DSC_D 495 */ 496 #define DSC_D_TRNSUM_CTL_1 0x0000d030 /* Trnsum Ctl 1 */ 497 #define DSC_D_TRNSUM_CTL_2 0x0000d031 /* Trnsum Ctl 2 */ 498 #define DSC_D_TRNSUM_CTL_3 0x0000d032 /* Trnsum Ctl 3 */ 499 #define DSC_D_TRNSUM_CTL_4 0x0000d033 /* Trnsum Ctl 4 */ 500 #define DSC_D_TRNSUM_STS_1 0x0000d034 /* Trnsum Status 1 */ 501 #define DSC_D_TRNSUM_STS_2 0x0000d035 /* Trnsum Status 2 */ 502 #define DSC_D_TRNSUM_STS_3 0x0000d036 /* Trnsum Status 3 */ 503 #define DSC_D_TRNSUM_STS_4 0x0000d037 /* Trnsum Status 4 */ 504 #define DSC_D_TRNSUM_STS_5 0x0000d038 /* Trnsum Status 5 */ 505 #define DSC_D_TRNSUM_STS_6 0x0000d039 /* Trnsum Status 6 */ 506 #define DSC_D_VGA_P1EYEDIAG_STS 0x0000d03a /* VGA status */ 507 #define DSC_D_DFE_1_STS 0x0000d03b /* DFE 1 status */ 508 #define DSC_D_DFE_2_STS 0x0000d03c /* DFE 2 status */ 509 #define DSC_D_DFE_3_4_5_STS 0x0000d03d /* DFE 3,4,5 status */ 510 #define DSC_D_VGA_TAP_BIN 0x0000d03e /* VGA binary tap values */ 511 512 513 /**************************************************************************** 514 * merlin_gallardo_dsc_blk_DSC_E 515 */ 516 #define DSC_E_DSC_E_CTRL 0x0000d040 /* dsc_e_ctrl */ 517 #define DSC_E_DSC_E_PF_CTRL 0x0000d041 /* dsc_e_pf_ctrl */ 518 #define DSC_E_DSC_E_PF2_LOWP_CTRL 0x0000d042 /* dsc_e_pf2_lowp_ctrl */ 519 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD 0x0000d043 /* dsc_e_offset_adj_data_odd */ 520 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN 0x0000d044 /* dsc_e_offset_adj_data_even */ 521 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD 0x0000d045 /* dsc_e_offset_adj_p1_odd */ 522 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN 0x0000d046 /* dsc_e_offset_adj_p1_even */ 523 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD 0x0000d047 /* dsc_e_offset_adj_m1_odd */ 524 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN 0x0000d048 /* dsc_e_offset_adj_m1_even */ 525 #define DSC_E_DSC_E_DC_OFFSET 0x0000d049 /* dsc_e_dc_offset */ 526 527 528 /**************************************************************************** 529 * merlin_gallardo_cl72_user_blk_CL72_USER_RX 530 */ 531 #define CL72_USER_RX_RCVD_STATUS_REGISTER 0x0000d050 /* CL72 Status Report Register */ 532 #define CL72_USER_RX_MISC1_CONTROL 0x0000d051 /* CL72 Miscellaneous_1 Control Register */ 533 #define CL72_USER_RX_DEBUG_2_REGISTER 0x0000d052 /* CL72 Debug 2 Register */ 534 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE 0x0000d053 /* */ 535 #define CL72_USER_RX_CL72_STATUS1_REGISTER 0x0000d054 /* CL72 Status 1 Register */ 536 537 538 /**************************************************************************** 539 * merlin_gallardo_cl72_user_blk_CL72_USER_TX 540 */ 541 #define CL72_USER_TX_RPTR_XMT_UPDATE_REGISTER 0x0000d060 /* CL72 TX Coefficient Update Register */ 542 #define CL72_USER_TX_RPTR_MISC2_CONTROL 0x0000d061 /* CL72 Miscellaneous_2 Control Register */ 543 #define CL72_USER_TX_RPTR_DEBUG_3_REGISTER 0x0000d062 /* CL72 Debug 3 Register */ 544 #define CL72_USER_TX_RPTR_PCS_INTERFACE_CONTROL_REGISTER 0x0000d063 /* CL72 PCS interface control Register */ 545 #define CL72_USER_TX_RPTR_CL72_LD_STATUS_PAGE 0x0000d064 /* CL72 local device status Register */ 546 #define CL72_USER_TX_RPTR_CL72_READY_FOR_CMD_REGISTER 0x0000d065 /* CL72 Ready for command registers */ 547 #define CL72_USER_TX_RPTR_KR_DEFAULT_CONTROL1 0x0000d066 /* CL72 KR Default Control 1 Register */ 548 #define CL72_USER_TX_RPTR_KR_DEFAULT_CONTROL2 0x0000d067 /* CL72 KR Default Control 2 Register */ 549 #define CL72_USER_TX_RPTR_MISC_COEFF_CONTROL 0x0000d068 /* CL72 Misc Coefficient Control Register */ 550 #define CL72_USER_TX_RPTR_CL72_LD_XMT_STATUS_PAGE_OVERRIDE 0x0000d069 /* CL72 Local Device Status Page Override Register */ 551 #define CL72_USER_TX_RPTR_CL72_TX_DEBUG_STATUS 0x0000d06a /* CL72 debug status register */ 552 553 554 /**************************************************************************** 555 * merlin_gallardo_tx_pi_blk_TX_PI 556 */ 557 #define TX_PI_TX_PI_CONTROL_0 0x0000d070 /* TX Phase Interpolator Control 0 */ 558 #define TX_PI_TX_PI_CONTROL_1 0x0000d071 /* TX Phase Interpolator Control 1 */ 559 #define TX_PI_TX_PI_CONTROL_2 0x0000d072 /* TX Phase Interpolator Control 2 */ 560 #define TX_PI_TX_PI_CONTROL_3 0x0000d073 /* TX Phase Interpolator Control 3 */ 561 #define TX_PI_TX_PI_CONTROL_4 0x0000d074 /* TX Phase Interpolator Control 4 */ 562 #define TX_PI_TX_PI_CONTROL_5 0x0000d075 /* TX Phase Interpolator Control 5 (ONLY Applicable to Merlin) */ 563 #define TX_PI_TX_PI_CONTROL_6 0x0000d076 /* TX Phase Interpolator Control 6 (ONLY Applicable to Eagle) */ 564 #define TX_PI_TX_PI_STATUS_0 0x0000d078 /* TX Phase Interpolator Status 0 */ 565 #define TX_PI_TX_PI_STATUS_1 0x0000d079 /* TX Phase Interpolator Status 1 */ 566 #define TX_PI_TX_PI_STATUS_2 0x0000d07a /* TX Phase Interpolator Status 2 */ 567 #define TX_PI_TX_PI_STATUS_3 0x0000d07b /* TX Phase Interpolator Status 3 */ 568 #define TX_PI_TX_PI_STATUS_4 0x0000d07c /* TX Phase Interpolator Status 4 (ONLY Applicable to Merlin) */ 569 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS 0x0000d07d /* TX FIFO Overflow Status (ONLY Applicable to Merlin) */ 570 571 572 /**************************************************************************** 573 * merlin_gallardo_ckrst_ctrl_blk_CKRST_CTRL 574 */ 575 #define CKRST_CTRL_OSR_MODE_CONTROL 0x0000d080 /* OSR_MODE_CONTROL */ 576 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL 0x0000d081 /* LANE_CLK_RESET_N_POWERDOWN_CONTROL */ 577 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL 0x0000d082 /* LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL */ 578 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL 0x0000d083 /* LANE_RESET_N_PWRDN_PIN_KILL_CONTROL */ 579 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL 0x0000d084 /* LANE_DEBUG_RESET_CONTROL */ 580 #define CKRST_CTRL_UC_ACK_LANE_CONTROL 0x0000d085 /* UC_ACK_LANE_CONTROL */ 581 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL 0x0000d086 /* LANE_REG_RESET_OCCURRED_CONTROL */ 582 #define CKRST_CTRL_PMD_LANE_MODE_STATUS 0x0000d088 /* PMD_LANE_MODE_STATUS */ 583 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS 0x0000d089 /* LANE_DP_RESET_STATE_STATUS */ 584 #define CKRST_CTRL_LN_MASK 0x0000d08a /* LN_MASK */ 585 #define CKRST_CTRL_OSR_MODE_STATUS 0x0000d08b /* OSR_MODE_STATUS */ 586 587 588 /**************************************************************************** 589 * merlin_gallardo_ams_blk_AMS_RX 590 */ 591 #define AMS_RX_RX_CTRL_0 0x0000d090 /* RX_CTRL_0 */ 592 #define AMS_RX_RX_CTRL_1 0x0000d091 /* RX_CTRL_1 */ 593 #define AMS_RX_RX_CTRL_2 0x0000d092 /* RX_CTRL_2 */ 594 #define AMS_RX_RX_CTRL_3 0x0000d093 /* RX_CTRL_3 */ 595 #define AMS_RX_RX_CTRL_4 0x0000d094 /* RX_CTRL_4 */ 596 #define AMS_RX_RX_CTRL_5 0x0000d095 /* RX_CTRL_5 */ 597 #define AMS_RX_RX_CTRL_6 0x0000d096 /* RX_CTRL_6 */ 598 #define AMS_RX_RX_INT 0x0000d098 /* RX_CTRL_INT */ 599 #define AMS_RX_RX_STS 0x0000d099 /* RX_STS */ 600 601 602 /**************************************************************************** 603 * merlin_gallardo_ams_blk_AMS_TX 604 */ 605 #define AMS_TX_TX_CTRL_0 0x0000d0a0 /* TX_CTRL_0 */ 606 #define AMS_TX_TX_CTRL_1 0x0000d0a1 /* TX_CTRL_1 */ 607 #define AMS_TX_TX_CTRL_2 0x0000d0a2 /* TX_CTRL_2 */ 608 #define AMS_TX_TX_CTRL_3 0x0000d0a3 /* TX_CTRL_3 */ 609 #define AMS_TX_TX_CTRL_4 0x0000d0a4 /* TX_CTRL_4 */ 610 #define AMS_TX_TX_CTRL_5 0x0000d0a5 /* TX_CTRL_5 */ 611 #define AMS_TX_TX_INT 0x0000d0a8 /* TX_CTRL_INT */ 612 #define AMS_TX_TX_STS 0x0000d0a9 /* TX_STS */ 613 614 615 /**************************************************************************** 616 * merlin_gallardo_ams_blk_AMSCOM 617 */ 618 #define AMSCOM_PLL_CTRL_0 0x0000d0b0 /* PLL_CTRL_0 */ 619 #define AMSCOM_PLL_CTRL_1 0x0000d0b1 /* PLL_CTRL_1 */ 620 #define AMSCOM_PLL_CTRL_2 0x0000d0b2 /* PLL_CTRL_2 */ 621 #define AMSCOM_PLL_CTRL_3 0x0000d0b3 /* PLL_CTRL_3 */ 622 #define AMSCOM_PLL_CTRL_4 0x0000d0b4 /* PLL_CTRL_4 */ 623 #define AMSCOM_PLL_CTRL_5 0x0000d0b5 /* PLL_CTRL_5 */ 624 #define AMSCOM_PLL_CTRL_6 0x0000d0b6 /* PLL_CTRL_6 */ 625 #define AMSCOM_PLL_CTRL_7 0x0000d0b7 /* PLL_CTRL_7 */ 626 #define AMSCOM_PLL_CTRL_8 0x0000d0b8 /* PLL_CTRL_8 */ 627 #define AMSCOM_PLL_CTRL_9 0x0000d0b9 /* PLL_CTRL_9 */ 628 #define AMSCOM_PLL_CTRL_10 0x0000d0ba /* PLL_CTRL_10 */ 629 630 631 /**************************************************************************** 632 * merlin_gallardo_sigdet_blk_SIGDET 633 */ 634 #define SIGDET_SIGDET_CTRL_0 0x0000d0c0 /* SIGDET_CTRL_0 */ 635 #define SIGDET_SIGDET_CTRL_1 0x0000d0c1 /* SIGDET_CTRL_1 */ 636 #define SIGDET_SIGDET_CTRL_2 0x0000d0c2 /* SIGDET_CTRL_2 */ 637 #define SIGDET_SIGDET_STATUS_0 0x0000d0c8 /* SIGDET_STATUS_0 */ 638 639 640 /**************************************************************************** 641 * merlin_gallardo_tlb_blk_TLB_RX 642 */ 643 #define TLB_RX_PRBS_CHK_CONFIG 0x0000d0d1 /* PRBS Generator Control */ 644 #define TLB_RX_DIG_LPBK_CONFIG 0x0000d0d2 /* Remote Loopback Control */ 645 #define TLB_RX_TLB_RX_MISC_CONFIG 0x0000d0d3 /* TLB RX Misc. Control */ 646 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL 0x0000d0d4 /* TLB RX PRBS Checker Enable Timer Control */ 647 #define TLB_RX_DIG_LPBK_PD_STATUS 0x0000d0d8 /* Remote Loopback Status */ 648 #define TLB_RX_PRBS_CHK_LOCK_STATUS 0x0000d0d9 /* PRBS Checker LOCK Status */ 649 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS 0x0000d0da /* PRBS Checker Error Counter MSB Status */ 650 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS 0x0000d0db /* PRBS Checker Error Counter LSB Status */ 651 #define TLB_RX_PMD_RX_LOCK_STATUS 0x0000d0dc /* PMD RX LOCK Status */ 652 653 654 /**************************************************************************** 655 * merlin_gallardo_tlb_blk_TLB_TX 656 */ 657 #define TLB_TX_PATT_GEN_CONFIG 0x0000d0e0 /* Pattern Generator Control */ 658 #define TLB_TX_PRBS_GEN_CONFIG 0x0000d0e1 /* PRBS Generator Control */ 659 #define TLB_TX_RMT_LPBK_CONFIG 0x0000d0e2 /* Remote Loopback Control */ 660 #define TLB_TX_TLB_TX_MISC_CONFIG 0x0000d0e3 /* TLB TX Misc. Control */ 661 #define TLB_TX_RMT_LPBK_PD_STATUS 0x0000d0e8 /* Remote Loopback Status */ 662 663 664 /**************************************************************************** 665 * merlin_gallardo_digcom_blk_DIGCOM 666 */ 667 #define DIGCOM_GALLARDO_REVID0 0x0000d0f0 /* REVID0 */ 668 #define DIGCOM_GALLARDO_RESET_CONTROL_PMD 0x0000d0f1 /* RESET_CONTROL_PMD */ 669 #define DIGCOM_GALLARDO_RESET_CONTROL_CORE_DP 0x0000d0f2 /* RESET_CONTROL_CORE_DP */ 670 #define DIGCOM_GALLARDO_LANE_MASK 0x0000d0f3 /* LANE_MASK */ 671 #define DIGCOM_GALLARDO_HEARTBEAT_TIMER_CONTROL 0x0000d0f4 /* HEARTBEAT_TIMER_CONTROL */ 672 #define DIGCOM_GALLARDO_UC_ACK_CORE_CONTROL 0x0000d0f5 /* UC_ACK_CORE_CONTROL */ 673 #define DIGCOM_GALLARDO_CORE_REG_RESET_OCCURRED_CONTROL 0x0000d0f6 /* CORE_REG_RESET_OCCURRED_CONTROL */ 674 #define DIGCOM_GALLARDO_RST_SEQ_TIMER_CONTROL 0x0000d0f7 /* RST_SEQ_TIMER_CONTROL */ 675 #define DIGCOM_GALLARDO_CORE_DP_RESET_STATE_STATUS 0x0000d0f8 /* CORE_DP_RESET_STATE_STATUS */ 676 #define DIGCOM_GALLARDO_PMD_CORE_MODE_STATUS 0x0000d0f9 /* PMD_CORE_MODE_STATUS */ 677 #define DIGCOM_GALLARDO_REVID1 0x0000d0fa /* REVID1 */ 678 #define DIGCOM_GALLARDO_REVID2 0x0000d0fe /* REVID2 */ 679 680 681 /**************************************************************************** 682 * merlin_gallardo_patt_gen_blk_PATT_GEN 683 */ 684 #define PATT_GEN_PATT_GEN_SEQ_0 0x0000d100 /* Pattern Generator Sequence Word 0 */ 685 #define PATT_GEN_PATT_GEN_SEQ_1 0x0000d101 /* Pattern Generator Sequence Word 1 */ 686 #define PATT_GEN_PATT_GEN_SEQ_2 0x0000d102 /* Pattern Generator Sequence Word 2 */ 687 #define PATT_GEN_PATT_GEN_SEQ_3 0x0000d103 /* Pattern Generator Sequence Word 3 */ 688 #define PATT_GEN_PATT_GEN_SEQ_4 0x0000d104 /* Pattern Generator Sequence Word 4 */ 689 #define PATT_GEN_PATT_GEN_SEQ_5 0x0000d105 /* Pattern Generator Sequence Word 5 */ 690 #define PATT_GEN_PATT_GEN_SEQ_6 0x0000d106 /* Pattern Generator Sequence Word 6 */ 691 #define PATT_GEN_PATT_GEN_SEQ_7 0x0000d107 /* Pattern Generator Sequence Word 7 */ 692 #define PATT_GEN_PATT_GEN_SEQ_8 0x0000d108 /* Pattern Generator Sequence Word 8 */ 693 #define PATT_GEN_PATT_GEN_SEQ_9 0x0000d109 /* Pattern Generator Sequence Word 9 */ 694 #define PATT_GEN_PATT_GEN_SEQ_10 0x0000d10a /* Pattern Generator Sequence Word 10 */ 695 #define PATT_GEN_PATT_GEN_SEQ_11 0x0000d10b /* Pattern Generator Sequence Word 11 */ 696 #define PATT_GEN_PATT_GEN_SEQ_12 0x0000d10c /* Pattern Generator Sequence Word 12 */ 697 #define PATT_GEN_PATT_GEN_SEQ_13 0x0000d10d /* Pattern Generator Sequence Word 13 */ 698 #define PATT_GEN_PATT_GEN_SEQ_14 0x0000d10e /* Pattern Generator Sequence Word 14 */ 699 700 701 /**************************************************************************** 702 * merlin_gallardo_tx_fed_blk_TX_FED 703 */ 704 #define TX_FED_RPTR_TXFIR_CONTROL1 0x0000d110 /* TX FIR Control1 Register */ 705 #define TX_FED_RPTR_TXFIR_CONTROL2 0x0000d111 /* TX FIR Control2 Register */ 706 #define TX_FED_RPTR_TXFIR_CONTROL3 0x0000d112 /* TX FIR Control3 Register */ 707 #define TX_FED_RPTR_TXFIR_STATUS1 0x0000d113 /* TX FIR Status1 Register */ 708 #define TX_FED_RPTR_TXFIR_STATUS2 0x0000d114 /* TX FIR Status2 Register */ 709 #define TX_FED_RPTR_TXFIR_STATUS3 0x0000d115 /* TX FIR Status3 Register */ 710 #define TX_FED_RPTR_TXFIR_STATUS4 0x0000d116 /* TX FIR Status4 Register */ 711 #define TX_FED_RPTR_MICRO_CONTROL 0x0000d117 /* Micro Control Register */ 712 #define TX_FED_RPTR_MISC_CONTROL1 0x0000d118 /* Misc Control 1 Register */ 713 #define TX_FED_RPTR_MISC_CONTROL2 0x0000d119 /* Misc Control 2 Register */ 714 #define TX_FED_RPTR_MISC_CONTROL3 0x0000d11a /* Misc Control 3 Register */ 715 716 717 /**************************************************************************** 718 * merlin_gallardo_pll_cal_blk_PLL_CAL 719 */ 720 #define PLL_CAL_PLL_CALCTL_0 0x0000d120 /* PLL_CALCTL_0 */ 721 #define PLL_CAL_PLL_CALCTL_1 0x0000d121 /* PLL_CALCTL_1 */ 722 #define PLL_CAL_PLL_CALCTL_2 0x0000d122 /* PLL_CALCTL_2 */ 723 #define PLL_CAL_PLL_CALCTL_3 0x0000d123 /* PLL_CALCTL_3 */ 724 #define PLL_CAL_PLL_CALCTL_4 0x0000d124 /* PLL_CALCTL_4 */ 725 #define PLL_CAL_PLL_CALCTL_5 0x0000d125 /* PLL_CALCTL_5 */ 726 #define PLL_CAL_PLL_CALCTL_6 0x0000d126 /* PLL_CALCTL_6 */ 727 #define PLL_CAL_PLL_CALSTS_0 0x0000d128 /* PLL_CALSTS_0 */ 728 #define PLL_CAL_PLL_CALSTS_1 0x0000d129 /* PLL_CALSTS_1 */ 729 #define PLL_CAL_PLL_CALSTS_2 0x0000d12a /* PLL_CALSTS_2 */ 730 #define PLL_CAL_PLL_CALSTS_3 0x0000d12b /* PLL_CALSTS_3 */ 731 #define PLL_CAL_PLL_CALSTS_4 0x0000d12c /* PLL_CALSTS_4 */ 732 #define PLL_CAL_PLL_CALSTS_5 0x0000d12d /* PLL_CALSTS_5 */ 733 #define PLL_CAL_PLL_CALSTS_6 0x0000d12e /* PLL_CALSTS_6 */ 734 735 736 /**************************************************************************** 737 * merlin_gallardo_txcom_blk_TXCOM 738 */ 739 #define TXCOM_RPTR_CL72_TAP_LIMIT_CONTROL1 0x0000d130 /* CL72 Tap Limit Control 1 Register */ 740 #define TXCOM_RPTR_CL72_TAP_LIMIT_CONTROL2 0x0000d131 /* CL72 Tap Limit Control 2 Register */ 741 #define TXCOM_RPTR_CL72_TAP_PRESET_CONTROL 0x0000d132 /* CL72 Tap Present Control Register */ 742 #define TXCOM_RPTR_CL72_DEBUG_1_REGISTER 0x0000d133 /* CL72 Debug 1 Register */ 743 #define TXCOM_RPTR_CL72_MAX_WAIT_TIMER_REGISTER 0x0000d134 /* CL72 Max Wait Timer Register */ 744 #define TXCOM_RPTR_CL72_WAIT_TIMER_REGISTER 0x0000d135 /* CL72 Wait Timer Register */ 745 746 747 /**************************************************************************** 748 * merlin_gallardo_mgt_top_blk_MGT_TOP_I2C 749 */ 750 /**************************************************************************** 751 * MGT_TOP_I2C :: i2c_control_register 752 */ 753 /* MGT_TOP_I2C :: i2c_control_register :: i2c_master_enable [15:15] */ 754 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_I2C_MASTER_ENABLE_MASK 0x8000 755 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_I2C_MASTER_ENABLE_ALIGN 0 756 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_I2C_MASTER_ENABLE_BITS 1 757 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_I2C_MASTER_ENABLE_SHIFT 15 758 759 /* MGT_TOP_I2C :: i2c_control_register :: regs_imc_i2cflush [14:14] */ 760 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_REGS_IMC_I2CFLUSH_MASK 0x4000 761 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_REGS_IMC_I2CFLUSH_ALIGN 0 762 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_REGS_IMC_I2CFLUSH_BITS 1 763 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_REGS_IMC_I2CFLUSH_SHIFT 14 764 765 /* MGT_TOP_I2C :: i2c_control_register :: imc_sl_add_cnt [13:13] */ 766 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_SL_ADD_CNT_MASK 0x2000 767 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_SL_ADD_CNT_ALIGN 0 768 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_SL_ADD_CNT_BITS 1 769 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_SL_ADD_CNT_SHIFT 13 770 771 /* MGT_TOP_I2C :: i2c_control_register :: imc_sl_dat_cnt [12:12] */ 772 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_SL_DAT_CNT_MASK 0x1000 773 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_SL_DAT_CNT_ALIGN 0 774 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_SL_DAT_CNT_BITS 1 775 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_SL_DAT_CNT_SHIFT 12 776 777 /* MGT_TOP_I2C :: i2c_control_register :: nvm_chsum_ok [11:11] */ 778 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_NVM_CHSUM_OK_MASK 0x0800 779 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_NVM_CHSUM_OK_ALIGN 0 780 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_NVM_CHSUM_OK_BITS 1 781 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_NVM_CHSUM_OK_SHIFT 11 782 783 /* MGT_TOP_I2C :: i2c_control_register :: imc_regs_xfer_stat [10:09] */ 784 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_REGS_XFER_STAT_MASK 0x0600 785 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_REGS_XFER_STAT_ALIGN 0 786 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_REGS_XFER_STAT_BITS 2 787 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_IMC_REGS_XFER_STAT_SHIFT 9 788 789 /* MGT_TOP_I2C :: i2c_control_register :: reserved0 [08:06] */ 790 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_RESERVED0_MASK 0x01c0 791 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_RESERVED0_ALIGN 0 792 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_RESERVED0_BITS 3 793 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_RESERVED0_SHIFT 6 794 795 /* MGT_TOP_I2C :: i2c_control_register :: slave_cmd [05:05] */ 796 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_SLAVE_CMD_MASK 0x0020 797 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_SLAVE_CMD_ALIGN 0 798 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_SLAVE_CMD_BITS 1 799 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_SLAVE_CMD_SHIFT 5 800 801 /* MGT_TOP_I2C :: i2c_control_register :: reserved1 [04:04] */ 802 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_RESERVED1_MASK 0x0010 803 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_RESERVED1_ALIGN 0 804 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_RESERVED1_BITS 1 805 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_RESERVED1_SHIFT 4 806 807 /* MGT_TOP_I2C :: i2c_control_register :: i2c_status [03:02] */ 808 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_I2C_STATUS_MASK 0x000c 809 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_I2C_STATUS_ALIGN 0 810 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_I2C_STATUS_BITS 2 811 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_I2C_STATUS_SHIFT 2 812 813 /* MGT_TOP_I2C :: i2c_control_register :: extended_r_w [01:00] */ 814 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_EXTENDED_R_W_MASK 0x0003 815 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_EXTENDED_R_W_ALIGN 0 816 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_EXTENDED_R_W_BITS 2 817 #define MGT_TOP_I2C_I2C_CONTROL_REGISTER_EXTENDED_R_W_SHIFT 0 818 819 820 /**************************************************************************** 821 * MGT_TOP_I2C :: i2c_check_sum_register 822 */ 823 /* MGT_TOP_I2C :: i2c_check_sum_register :: reserved0 [15:08] */ 824 #define MGT_TOP_I2C_I2C_CHECK_SUM_REGISTER_RESERVED0_MASK 0xff00 825 #define MGT_TOP_I2C_I2C_CHECK_SUM_REGISTER_RESERVED0_ALIGN 0 826 #define MGT_TOP_I2C_I2C_CHECK_SUM_REGISTER_RESERVED0_BITS 8 827 #define MGT_TOP_I2C_I2C_CHECK_SUM_REGISTER_RESERVED0_SHIFT 8 828 829 /* MGT_TOP_I2C :: i2c_check_sum_register :: i2c_csum [07:00] */ 830 #define MGT_TOP_I2C_I2C_CHECK_SUM_REGISTER_I2C_CSUM_MASK 0x00ff 831 #define MGT_TOP_I2C_I2C_CHECK_SUM_REGISTER_I2C_CSUM_ALIGN 0 832 #define MGT_TOP_I2C_I2C_CHECK_SUM_REGISTER_I2C_CSUM_BITS 8 833 #define MGT_TOP_I2C_I2C_CHECK_SUM_REGISTER_I2C_CSUM_SHIFT 0 834 835 836 /**************************************************************************** 837 * MGT_TOP_I2C :: i2c_transfer_size_register 838 */ 839 /* MGT_TOP_I2C :: i2c_transfer_size_register :: i2c_config_status [15:14] */ 840 #define MGT_TOP_I2C_I2C_TRANSFER_SIZE_REGISTER_I2C_CONFIG_STATUS_MASK 0xc000 841 #define MGT_TOP_I2C_I2C_TRANSFER_SIZE_REGISTER_I2C_CONFIG_STATUS_ALIGN 0 842 #define MGT_TOP_I2C_I2C_TRANSFER_SIZE_REGISTER_I2C_CONFIG_STATUS_BITS 2 843 #define MGT_TOP_I2C_I2C_TRANSFER_SIZE_REGISTER_I2C_CONFIG_STATUS_SHIFT 14 844 845 /* MGT_TOP_I2C :: i2c_transfer_size_register :: imc_xfer_cnt [13:00] */ 846 #define MGT_TOP_I2C_I2C_TRANSFER_SIZE_REGISTER_IMC_XFER_CNT_MASK 0x3fff 847 #define MGT_TOP_I2C_I2C_TRANSFER_SIZE_REGISTER_IMC_XFER_CNT_ALIGN 0 848 #define MGT_TOP_I2C_I2C_TRANSFER_SIZE_REGISTER_IMC_XFER_CNT_BITS 14 849 #define MGT_TOP_I2C_I2C_TRANSFER_SIZE_REGISTER_IMC_XFER_CNT_SHIFT 0 850 851 852 /**************************************************************************** 853 * MGT_TOP_I2C :: i2c_external_nvm_address_register 854 */ 855 /* MGT_TOP_I2C :: i2c_external_nvm_address_register :: imc_slave_addr [15:00] */ 856 #define MGT_TOP_I2C_I2C_EXTERNAL_NVM_ADDRESS_REGISTER_IMC_SLAVE_ADDR_MASK 0xffff 857 #define MGT_TOP_I2C_I2C_EXTERNAL_NVM_ADDRESS_REGISTER_IMC_SLAVE_ADDR_ALIGN 0 858 #define MGT_TOP_I2C_I2C_EXTERNAL_NVM_ADDRESS_REGISTER_IMC_SLAVE_ADDR_BITS 16 859 #define MGT_TOP_I2C_I2C_EXTERNAL_NVM_ADDRESS_REGISTER_IMC_SLAVE_ADDR_SHIFT 0 860 861 862 /**************************************************************************** 863 * MGT_TOP_I2C :: i2c_internal_address_register 864 */ 865 /* MGT_TOP_I2C :: i2c_internal_address_register :: imc_xfer_addr_15_0 [15:00] */ 866 #define MGT_TOP_I2C_I2C_INTERNAL_ADDRESS_REGISTER_IMC_XFER_ADDR_15_0_MASK 0xffff 867 #define MGT_TOP_I2C_I2C_INTERNAL_ADDRESS_REGISTER_IMC_XFER_ADDR_15_0_ALIGN 0 868 #define MGT_TOP_I2C_I2C_INTERNAL_ADDRESS_REGISTER_IMC_XFER_ADDR_15_0_BITS 16 869 #define MGT_TOP_I2C_I2C_INTERNAL_ADDRESS_REGISTER_IMC_XFER_ADDR_15_0_SHIFT 0 870 871 872 /**************************************************************************** 873 * MGT_TOP_I2C :: i2c_slave_id_address_register 874 */ 875 /* MGT_TOP_I2C :: i2c_slave_id_address_register :: imc_sl_dev_add [15:09] */ 876 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_SL_DEV_ADD_MASK 0xfe00 877 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_SL_DEV_ADD_ALIGN 0 878 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_SL_DEV_ADD_BITS 7 879 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_SL_DEV_ADD_SHIFT 9 880 881 /* MGT_TOP_I2C :: i2c_slave_id_address_register :: imc_i2c_speed [08:08] */ 882 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_I2C_SPEED_MASK 0x0100 883 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_I2C_SPEED_ALIGN 0 884 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_I2C_SPEED_BITS 1 885 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_I2C_SPEED_SHIFT 8 886 887 /* MGT_TOP_I2C :: i2c_slave_id_address_register :: imc_xfer_addr_23_16 [07:00] */ 888 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_XFER_ADDR_23_16_MASK 0x00ff 889 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_XFER_ADDR_23_16_ALIGN 0 890 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_XFER_ADDR_23_16_BITS 8 891 #define MGT_TOP_I2C_I2C_SLAVE_ID_ADDRESS_REGISTER_IMC_XFER_ADDR_23_16_SHIFT 0 892 893 894 /**************************************************************************** 895 * merlin_gallardo_mgt_top_blk_MGT_TOP_PMD_USR 896 */ 897 /**************************************************************************** 898 * MGT_TOP_PMD_USR :: pwr_ramp 899 */ 900 /* MGT_TOP_PMD_USR :: pwr_ramp :: pwr_on_en15_0 [15:00] */ 901 #define MGT_TOP_PMD_USR_PWR_RAMP_PWR_ON_EN15_0_MASK 0xffff 902 #define MGT_TOP_PMD_USR_PWR_RAMP_PWR_ON_EN15_0_ALIGN 0 903 #define MGT_TOP_PMD_USR_PWR_RAMP_PWR_ON_EN15_0_BITS 16 904 #define MGT_TOP_PMD_USR_PWR_RAMP_PWR_ON_EN15_0_SHIFT 0 905 906 907 /**************************************************************************** 908 * MGT_TOP_PMD_USR :: chip_rev_register 909 */ 910 /* MGT_TOP_PMD_USR :: chip_rev_register :: reserved0 [15:08] */ 911 #define MGT_TOP_PMD_USR_CHIP_REV_REGISTER_RESERVED0_MASK 0xff00 912 #define MGT_TOP_PMD_USR_CHIP_REV_REGISTER_RESERVED0_ALIGN 0 913 #define MGT_TOP_PMD_USR_CHIP_REV_REGISTER_RESERVED0_BITS 8 914 #define MGT_TOP_PMD_USR_CHIP_REV_REGISTER_RESERVED0_SHIFT 8 915 916 /* MGT_TOP_PMD_USR :: chip_rev_register :: rev [07:00] */ 917 #define MGT_TOP_PMD_USR_CHIP_REV_REGISTER_REV_MASK 0x00ff 918 #define MGT_TOP_PMD_USR_CHIP_REV_REGISTER_REV_ALIGN 0 919 #define MGT_TOP_PMD_USR_CHIP_REV_REGISTER_REV_BITS 8 920 #define MGT_TOP_PMD_USR_CHIP_REV_REGISTER_REV_SHIFT 0 921 922 923 /**************************************************************************** 924 * MGT_TOP_PMD_USR :: chip_id0_register 925 */ 926 /* MGT_TOP_PMD_USR :: chip_id0_register :: chip_id_lower [15:00] */ 927 #define MGT_TOP_PMD_USR_CHIP_ID0_REGISTER_CHIP_ID_LOWER_MASK 0xffff 928 #define MGT_TOP_PMD_USR_CHIP_ID0_REGISTER_CHIP_ID_LOWER_ALIGN 0 929 #define MGT_TOP_PMD_USR_CHIP_ID0_REGISTER_CHIP_ID_LOWER_BITS 16 930 #define MGT_TOP_PMD_USR_CHIP_ID0_REGISTER_CHIP_ID_LOWER_SHIFT 0 931 932 933 /**************************************************************************** 934 * MGT_TOP_PMD_USR :: chip_id1_register 935 */ 936 /* MGT_TOP_PMD_USR :: chip_id1_register :: reserved0 [15:04] */ 937 #define MGT_TOP_PMD_USR_CHIP_ID1_REGISTER_RESERVED0_MASK 0xfff0 938 #define MGT_TOP_PMD_USR_CHIP_ID1_REGISTER_RESERVED0_ALIGN 0 939 #define MGT_TOP_PMD_USR_CHIP_ID1_REGISTER_RESERVED0_BITS 12 940 #define MGT_TOP_PMD_USR_CHIP_ID1_REGISTER_RESERVED0_SHIFT 4 941 942 /* MGT_TOP_PMD_USR :: chip_id1_register :: chip_id_upper [03:00] */ 943 #define MGT_TOP_PMD_USR_CHIP_ID1_REGISTER_CHIP_ID_UPPER_MASK 0x000f 944 #define MGT_TOP_PMD_USR_CHIP_ID1_REGISTER_CHIP_ID_UPPER_ALIGN 0 945 #define MGT_TOP_PMD_USR_CHIP_ID1_REGISTER_CHIP_ID_UPPER_BITS 4 946 #define MGT_TOP_PMD_USR_CHIP_ID1_REGISTER_CHIP_ID_UPPER_SHIFT 0 947 948 949 /**************************************************************************** 950 * MGT_TOP_PMD_USR :: pmd_status_register 951 */ 952 /* MGT_TOP_PMD_USR :: pmd_status_register :: reserved0 [15:08] */ 953 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_RESERVED0_MASK 0xff00 954 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_RESERVED0_ALIGN 0 955 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_RESERVED0_BITS 8 956 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_RESERVED0_SHIFT 8 957 958 /* MGT_TOP_PMD_USR :: pmd_status_register :: sys_lkdtcmu [07:07] */ 959 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LKDTCMU_MASK 0x0080 960 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LKDTCMU_ALIGN 0 961 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LKDTCMU_BITS 1 962 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LKDTCMU_SHIFT 7 963 964 /* MGT_TOP_PMD_USR :: pmd_status_register :: sys_lkdtcdr [06:06] */ 965 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LKDTCDR_MASK 0x0040 966 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LKDTCDR_ALIGN 0 967 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LKDTCDR_BITS 1 968 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LKDTCDR_SHIFT 6 969 970 /* MGT_TOP_PMD_USR :: pmd_status_register :: reserved1 [05:05] */ 971 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_RESERVED1_MASK 0x0020 972 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_RESERVED1_ALIGN 0 973 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_RESERVED1_BITS 1 974 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_RESERVED1_SHIFT 5 975 976 /* MGT_TOP_PMD_USR :: pmd_status_register :: sys_los [04:04] */ 977 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LOS_MASK 0x0010 978 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LOS_ALIGN 0 979 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LOS_BITS 1 980 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_SYS_LOS_SHIFT 4 981 982 /* MGT_TOP_PMD_USR :: pmd_status_register :: ln_lkdtcmu [03:03] */ 983 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LKDTCMU_MASK 0x0008 984 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LKDTCMU_ALIGN 0 985 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LKDTCMU_BITS 1 986 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LKDTCMU_SHIFT 3 987 988 /* MGT_TOP_PMD_USR :: pmd_status_register :: ln_lkdtcdr [02:02] */ 989 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LKDTCDR_MASK 0x0004 990 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LKDTCDR_ALIGN 0 991 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LKDTCDR_BITS 1 992 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LKDTCDR_SHIFT 2 993 994 /* MGT_TOP_PMD_USR :: pmd_status_register :: oplosb [01:01] */ 995 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_OPLOSB_MASK 0x0002 996 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_OPLOSB_ALIGN 0 997 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_OPLOSB_BITS 1 998 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_OPLOSB_SHIFT 1 999 1000 /* MGT_TOP_PMD_USR :: pmd_status_register :: ln_los [00:00] */ 1001 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LOS_MASK 0x0001 1002 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LOS_ALIGN 0 1003 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LOS_BITS 1 1004 #define MGT_TOP_PMD_USR_PMD_STATUS_REGISTER_LN_LOS_SHIFT 0 1005 1006 1007 /**************************************************************************** 1008 * MGT_TOP_PMD_USR :: gpio_control_register 1009 */ 1010 /* MGT_TOP_PMD_USR :: gpio_control_register :: reserved0 [15:09] */ 1011 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_RESERVED0_MASK 0xfe00 1012 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_RESERVED0_ALIGN 0 1013 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_RESERVED0_BITS 7 1014 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_RESERVED0_SHIFT 9 1015 1016 /* MGT_TOP_PMD_USR :: gpio_control_register :: sys_pll_ool_mask [08:08] */ 1017 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SYS_PLL_OOL_MASK_MASK 0x0100 1018 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SYS_PLL_OOL_MASK_ALIGN 0 1019 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SYS_PLL_OOL_MASK_BITS 1 1020 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SYS_PLL_OOL_MASK_SHIFT 8 1021 1022 /* MGT_TOP_PMD_USR :: gpio_control_register :: ln_pll_ool_mask [07:07] */ 1023 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_LN_PLL_OOL_MASK_MASK 0x0080 1024 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_LN_PLL_OOL_MASK_ALIGN 0 1025 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_LN_PLL_OOL_MASK_BITS 1 1026 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_LN_PLL_OOL_MASK_SHIFT 7 1027 1028 /* MGT_TOP_PMD_USR :: gpio_control_register :: gpio_sel [06:04] */ 1029 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_GPIO_SEL_MASK 0x0070 1030 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_GPIO_SEL_ALIGN 0 1031 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_GPIO_SEL_BITS 3 1032 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_GPIO_SEL_SHIFT 4 1033 1034 /* MGT_TOP_PMD_USR :: gpio_control_register :: reserved1 [03:02] */ 1035 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_RESERVED1_MASK 0x000c 1036 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_RESERVED1_ALIGN 0 1037 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_RESERVED1_BITS 2 1038 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_RESERVED1_SHIFT 2 1039 1040 /* MGT_TOP_PMD_USR :: gpio_control_register :: sel_txdis_as_gpio1 [01:01] */ 1041 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SEL_TXDIS_AS_GPIO1_MASK 0x0002 1042 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SEL_TXDIS_AS_GPIO1_ALIGN 0 1043 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SEL_TXDIS_AS_GPIO1_BITS 1 1044 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SEL_TXDIS_AS_GPIO1_SHIFT 1 1045 1046 /* MGT_TOP_PMD_USR :: gpio_control_register :: sel_txon_as_gpio0 [00:00] */ 1047 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SEL_TXON_AS_GPIO0_MASK 0x0001 1048 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SEL_TXON_AS_GPIO0_ALIGN 0 1049 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SEL_TXON_AS_GPIO0_BITS 1 1050 #define MGT_TOP_PMD_USR_GPIO_CONTROL_REGISTER_SEL_TXON_AS_GPIO0_SHIFT 0 1051 1052 1053 /**************************************************************************** 1054 * MGT_TOP_PMD_USR :: gp_io_control_register 1055 */ 1056 /* MGT_TOP_PMD_USR :: gp_io_control_register :: reserved0 [15:10] */ 1057 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED0_MASK 0xfc00 1058 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED0_ALIGN 0 1059 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED0_BITS 6 1060 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED0_SHIFT 10 1061 1062 /* MGT_TOP_PMD_USR :: gp_io_control_register :: in_gp_dat [09:08] */ 1063 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_IN_GP_DAT_MASK 0x0300 1064 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_IN_GP_DAT_ALIGN 0 1065 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_IN_GP_DAT_BITS 2 1066 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_IN_GP_DAT_SHIFT 8 1067 1068 /* MGT_TOP_PMD_USR :: gp_io_control_register :: reserved1 [07:06] */ 1069 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED1_MASK 0x00c0 1070 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED1_ALIGN 0 1071 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED1_BITS 2 1072 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED1_SHIFT 6 1073 1074 /* MGT_TOP_PMD_USR :: gp_io_control_register :: out_gp_dis [05:04] */ 1075 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_OUT_GP_DIS_MASK 0x0030 1076 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_OUT_GP_DIS_ALIGN 0 1077 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_OUT_GP_DIS_BITS 2 1078 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_OUT_GP_DIS_SHIFT 4 1079 1080 /* MGT_TOP_PMD_USR :: gp_io_control_register :: reserved2 [03:02] */ 1081 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED2_MASK 0x000c 1082 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED2_ALIGN 0 1083 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED2_BITS 2 1084 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_RESERVED2_SHIFT 2 1085 1086 /* MGT_TOP_PMD_USR :: gp_io_control_register :: out_gp_dat [01:00] */ 1087 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_OUT_GP_DAT_MASK 0x0003 1088 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_OUT_GP_DAT_ALIGN 0 1089 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_OUT_GP_DAT_BITS 2 1090 #define MGT_TOP_PMD_USR_GP_IO_CONTROL_REGISTER_OUT_GP_DAT_SHIFT 0 1091 1092 1093 /**************************************************************************** 1094 * MGT_TOP_PMD_USR :: speed_link_detect_status 1095 */ 1096 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: sys_rx_sigdet [15:15] */ 1097 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_RX_SIGDET_MASK 0x8000 1098 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_RX_SIGDET_ALIGN 0 1099 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_RX_SIGDET_BITS 1 1100 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_RX_SIGDET_SHIFT 15 1101 1102 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: sys_an_complete [14:14] */ 1103 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_AN_COMPLETE_MASK 0x4000 1104 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_AN_COMPLETE_ALIGN 0 1105 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_AN_COMPLETE_BITS 1 1106 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_AN_COMPLETE_SHIFT 14 1107 1108 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: sys_pmd_speed40G [13:13] */ 1109 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED40G_MASK 0x2000 1110 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED40G_ALIGN 0 1111 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED40G_BITS 1 1112 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED40G_SHIFT 13 1113 1114 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: sys_pmd_speed10G [12:12] */ 1115 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10G_MASK 0x1000 1116 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10G_ALIGN 0 1117 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10G_BITS 1 1118 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10G_SHIFT 12 1119 1120 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: reserved0 [11:11] */ 1121 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_RESERVED0_MASK 0x0800 1122 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_RESERVED0_ALIGN 0 1123 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_RESERVED0_BITS 1 1124 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_RESERVED0_SHIFT 11 1125 1126 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: sys_pmd_speed1G [10:10] */ 1127 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED1G_MASK 0x0400 1128 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED1G_ALIGN 0 1129 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED1G_BITS 1 1130 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED1G_SHIFT 10 1131 1132 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: sys_pmd_speed100M [09:09] */ 1133 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED100M_MASK 0x0200 1134 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED100M_ALIGN 0 1135 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED100M_BITS 1 1136 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED100M_SHIFT 9 1137 1138 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: sys_pmd_speed10M [08:08] */ 1139 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10M_MASK 0x0100 1140 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10M_ALIGN 0 1141 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10M_BITS 1 1142 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_SYS_PMD_SPEED10M_SHIFT 8 1143 1144 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: ln_rx_sigdet [07:07] */ 1145 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_RX_SIGDET_MASK 0x0080 1146 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_RX_SIGDET_ALIGN 0 1147 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_RX_SIGDET_BITS 1 1148 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_RX_SIGDET_SHIFT 7 1149 1150 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: ln_an_complete [06:06] */ 1151 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_AN_COMPLETE_MASK 0x0040 1152 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_AN_COMPLETE_ALIGN 0 1153 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_AN_COMPLETE_BITS 1 1154 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_AN_COMPLETE_SHIFT 6 1155 1156 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: ln_pmd_speed40g [05:05] */ 1157 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED40G_MASK 0x0020 1158 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED40G_ALIGN 0 1159 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED40G_BITS 1 1160 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED40G_SHIFT 5 1161 1162 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: ln_pmd_speed10G [04:04] */ 1163 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10G_MASK 0x0010 1164 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10G_ALIGN 0 1165 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10G_BITS 1 1166 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10G_SHIFT 4 1167 1168 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: reserved1 [03:03] */ 1169 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_RESERVED1_MASK 0x0008 1170 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_RESERVED1_ALIGN 0 1171 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_RESERVED1_BITS 1 1172 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_RESERVED1_SHIFT 3 1173 1174 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: ln_pmd_speed1G [02:02] */ 1175 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED1G_MASK 0x0004 1176 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED1G_ALIGN 0 1177 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED1G_BITS 1 1178 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED1G_SHIFT 2 1179 1180 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: ln_pmd_speed100M [01:01] */ 1181 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED100M_MASK 0x0002 1182 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED100M_ALIGN 0 1183 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED100M_BITS 1 1184 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED100M_SHIFT 1 1185 1186 /* MGT_TOP_PMD_USR :: speed_link_detect_status :: ln_pmd_speed10M [00:00] */ 1187 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10M_MASK 0x0001 1188 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10M_ALIGN 0 1189 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10M_BITS 1 1190 #define MGT_TOP_PMD_USR_SPEED_LINK_DETECT_STATUS_LN_PMD_SPEED10M_SHIFT 0 1191 1192 1193 /**************************************************************************** 1194 * MGT_TOP_PMD_USR :: ch_reset_control 1195 */ 1196 /* MGT_TOP_PMD_USR :: ch_reset_control :: cl73_manhw_rst_n [15:12] */ 1197 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_CL73_MANHW_RST_N_MASK 0xf000 1198 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_CL73_MANHW_RST_N_ALIGN 0 1199 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_CL73_MANHW_RST_N_BITS 4 1200 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_CL73_MANHW_RST_N_SHIFT 12 1201 1202 /* MGT_TOP_PMD_USR :: ch_reset_control :: cl73_mandp_rst_n [11:08] */ 1203 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_CL73_MANDP_RST_N_MASK 0x0f00 1204 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_CL73_MANDP_RST_N_ALIGN 0 1205 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_CL73_MANDP_RST_N_BITS 4 1206 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_CL73_MANDP_RST_N_SHIFT 8 1207 1208 /* MGT_TOP_PMD_USR :: ch_reset_control :: xcl73_manhw_rst_n [07:04] */ 1209 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_XCL73_MANHW_RST_N_MASK 0x00f0 1210 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_XCL73_MANHW_RST_N_ALIGN 0 1211 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_XCL73_MANHW_RST_N_BITS 4 1212 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_XCL73_MANHW_RST_N_SHIFT 4 1213 1214 /* MGT_TOP_PMD_USR :: ch_reset_control :: xcl73_mandp_rst_n [03:00] */ 1215 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_XCL73_MANDP_RST_N_MASK 0x000f 1216 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_XCL73_MANDP_RST_N_ALIGN 0 1217 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_XCL73_MANDP_RST_N_BITS 4 1218 #define MGT_TOP_PMD_USR_CH_RESET_CONTROL_XCL73_MANDP_RST_N_SHIFT 0 1219 1220 1221 /**************************************************************************** 1222 * MGT_TOP_PMD_USR :: cl73_parallel_port_address_port 1223 */ 1224 /* MGT_TOP_PMD_USR :: cl73_parallel_port_address_port :: reserved0 [15:13] */ 1225 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_MASK 0xe000 1226 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_ALIGN 0 1227 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_BITS 3 1228 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_SHIFT 13 1229 1230 /* MGT_TOP_PMD_USR :: cl73_parallel_port_address_port :: cl73_pmd_aer [12:08] */ 1231 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_MASK 0x1f00 1232 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_ALIGN 0 1233 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_BITS 5 1234 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_SHIFT 8 1235 1236 /* MGT_TOP_PMD_USR :: cl73_parallel_port_address_port :: reserved1 [07:05] */ 1237 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_MASK 0x00e0 1238 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_ALIGN 0 1239 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_BITS 3 1240 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_SHIFT 5 1241 1242 /* MGT_TOP_PMD_USR :: cl73_parallel_port_address_port :: cl73_ang_aer [04:00] */ 1243 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_MASK 0x001f 1244 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_ALIGN 0 1245 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_BITS 5 1246 #define MGT_TOP_PMD_USR_CL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_SHIFT 0 1247 1248 1249 /**************************************************************************** 1250 * MGT_TOP_PMD_USR :: xcl73_parallel_port_address_port 1251 */ 1252 /* MGT_TOP_PMD_USR :: xcl73_parallel_port_address_port :: reserved0 [15:13] */ 1253 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_MASK 0xe000 1254 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_ALIGN 0 1255 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_BITS 3 1256 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED0_SHIFT 13 1257 1258 /* MGT_TOP_PMD_USR :: xcl73_parallel_port_address_port :: cl73_pmd_aer [12:08] */ 1259 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_MASK 0x1f00 1260 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_ALIGN 0 1261 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_BITS 5 1262 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_PMD_AER_SHIFT 8 1263 1264 /* MGT_TOP_PMD_USR :: xcl73_parallel_port_address_port :: reserved1 [07:05] */ 1265 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_MASK 0x00e0 1266 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_ALIGN 0 1267 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_BITS 3 1268 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_RESERVED1_SHIFT 5 1269 1270 /* MGT_TOP_PMD_USR :: xcl73_parallel_port_address_port :: cl73_ang_aer [04:00] */ 1271 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_MASK 0x001f 1272 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_ALIGN 0 1273 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_BITS 5 1274 #define MGT_TOP_PMD_USR_XCL73_PARALLEL_PORT_ADDRESS_PORT_CL73_ANG_AER_SHIFT 0 1275 1276 1277 /**************************************************************************** 1278 * MGT_TOP_PMD_USR :: pad_ctrl_register 1279 */ 1280 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: i2c_pad_func_ctrl [15:15] */ 1281 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_PAD_FUNC_CTRL_MASK 0x8000 1282 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_PAD_FUNC_CTRL_ALIGN 0 1283 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_PAD_FUNC_CTRL_BITS 1 1284 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_PAD_FUNC_CTRL_SHIFT 15 1285 1286 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: i2c_scl_pad_input [14:14] */ 1287 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_PAD_INPUT_MASK 0x4000 1288 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_PAD_INPUT_ALIGN 0 1289 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_PAD_INPUT_BITS 1 1290 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_PAD_INPUT_SHIFT 14 1291 1292 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: i2c_scl_dir_ctrl [13:13] */ 1293 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_DIR_CTRL_MASK 0x2000 1294 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_DIR_CTRL_ALIGN 0 1295 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_DIR_CTRL_BITS 1 1296 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_DIR_CTRL_SHIFT 13 1297 1298 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: i2c_scl_output [12:12] */ 1299 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_OUTPUT_MASK 0x1000 1300 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_OUTPUT_ALIGN 0 1301 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_OUTPUT_BITS 1 1302 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SCL_OUTPUT_SHIFT 12 1303 1304 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: reserved0 [11:11] */ 1305 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_RESERVED0_MASK 0x0800 1306 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_RESERVED0_ALIGN 0 1307 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_RESERVED0_BITS 1 1308 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_RESERVED0_SHIFT 11 1309 1310 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: i2c_sda_pad_input [10:10] */ 1311 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_PAD_INPUT_MASK 0x0400 1312 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_PAD_INPUT_ALIGN 0 1313 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_PAD_INPUT_BITS 1 1314 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_PAD_INPUT_SHIFT 10 1315 1316 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: i2c_sda_dir_ctrl [09:09] */ 1317 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_DIR_CTRL_MASK 0x0200 1318 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_DIR_CTRL_ALIGN 0 1319 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_DIR_CTRL_BITS 1 1320 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_DIR_CTRL_SHIFT 9 1321 1322 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: i2c_sda_output [08:08] */ 1323 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_OUTPUT_MASK 0x0100 1324 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_OUTPUT_ALIGN 0 1325 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_OUTPUT_BITS 1 1326 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_I2C_SDA_OUTPUT_SHIFT 8 1327 1328 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: mod_abs_debounce_delay_msb [07:07] */ 1329 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_DEBOUNCE_DELAY_MSB_MASK 0x0080 1330 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_DEBOUNCE_DELAY_MSB_ALIGN 0 1331 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_DEBOUNCE_DELAY_MSB_BITS 1 1332 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_DEBOUNCE_DELAY_MSB_SHIFT 7 1333 1334 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: mod_abs_pad_input [06:06] */ 1335 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_PAD_INPUT_MASK 0x0040 1336 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_PAD_INPUT_ALIGN 0 1337 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_PAD_INPUT_BITS 1 1338 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_PAD_INPUT_SHIFT 6 1339 1340 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: mod_abs_ctrl [05:05] */ 1341 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_CTRL_MASK 0x0020 1342 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_CTRL_ALIGN 0 1343 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_CTRL_BITS 1 1344 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_CTRL_SHIFT 5 1345 1346 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: mod_abs_output [04:04] */ 1347 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_OUTPUT_MASK 0x0010 1348 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_OUTPUT_ALIGN 0 1349 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_OUTPUT_BITS 1 1350 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_OUTPUT_SHIFT 4 1351 1352 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: mod_abs_debounce_delay_lsb [03:03] */ 1353 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_DEBOUNCE_DELAY_LSB_MASK 0x0008 1354 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_DEBOUNCE_DELAY_LSB_ALIGN 0 1355 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_DEBOUNCE_DELAY_LSB_BITS 1 1356 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_MOD_ABS_DEBOUNCE_DELAY_LSB_SHIFT 3 1357 1358 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: oprxlos_pad_input [02:02] */ 1359 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_PAD_INPUT_MASK 0x0004 1360 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_PAD_INPUT_ALIGN 0 1361 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_PAD_INPUT_BITS 1 1362 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_PAD_INPUT_SHIFT 2 1363 1364 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: oprxlos_ctrl [01:01] */ 1365 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_CTRL_MASK 0x0002 1366 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_CTRL_ALIGN 0 1367 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_CTRL_BITS 1 1368 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_CTRL_SHIFT 1 1369 1370 /* MGT_TOP_PMD_USR :: pad_ctrl_register :: oprxlos_output [00:00] */ 1371 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_OUTPUT_MASK 0x0001 1372 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_OUTPUT_ALIGN 0 1373 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_OUTPUT_BITS 1 1374 #define MGT_TOP_PMD_USR_PAD_CTRL_REGISTER_OPRXLOS_OUTPUT_SHIFT 0 1375 1376 1377 /**************************************************************************** 1378 * MGT_TOP_PMD_USR :: interrupt_m8051_register 1379 */ 1380 /* MGT_TOP_PMD_USR :: interrupt_m8051_register :: QSFI_ch_interrupt_TBD [15:14] */ 1381 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_QSFI_CH_INTERRUPT_TBD_MASK 0xc000 1382 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_QSFI_CH_INTERRUPT_TBD_ALIGN 0 1383 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_QSFI_CH_INTERRUPT_TBD_BITS 2 1384 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_QSFI_CH_INTERRUPT_TBD_SHIFT 14 1385 1386 /* MGT_TOP_PMD_USR :: interrupt_m8051_register :: External_PCS_Linkup [13:13] */ 1387 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKUP_MASK 0x2000 1388 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKUP_ALIGN 0 1389 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKUP_BITS 1 1390 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKUP_SHIFT 13 1391 1392 /* MGT_TOP_PMD_USR :: interrupt_m8051_register :: External_PCS_Linkdown [12:12] */ 1393 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKDOWN_MASK 0x1000 1394 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKDOWN_ALIGN 0 1395 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKDOWN_BITS 1 1396 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_EXTERNAL_PCS_LINKDOWN_SHIFT 12 1397 1398 /* MGT_TOP_PMD_USR :: interrupt_m8051_register :: loss_of_optical_rxsignal_interrupt [11:08] */ 1399 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_MASK 0x0f00 1400 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_ALIGN 0 1401 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_BITS 4 1402 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_SHIFT 8 1403 1404 /* MGT_TOP_PMD_USR :: interrupt_m8051_register :: gpio_1_interrupt [07:04] */ 1405 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_GPIO_1_INTERRUPT_MASK 0x00f0 1406 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_GPIO_1_INTERRUPT_ALIGN 0 1407 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_GPIO_1_INTERRUPT_BITS 4 1408 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_GPIO_1_INTERRUPT_SHIFT 4 1409 1410 /* MGT_TOP_PMD_USR :: interrupt_m8051_register :: gpio_0_interrupt [03:00] */ 1411 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_GPIO_0_INTERRUPT_MASK 0x000f 1412 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_GPIO_0_INTERRUPT_ALIGN 0 1413 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_GPIO_0_INTERRUPT_BITS 4 1414 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_REGISTER_GPIO_0_INTERRUPT_SHIFT 0 1415 1416 1417 /**************************************************************************** 1418 * MGT_TOP_PMD_USR :: interrupt_m8051_enable_register 1419 */ 1420 /* MGT_TOP_PMD_USR :: interrupt_m8051_enable_register :: QSFI_ch_interrupt_enable [15:14] */ 1421 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_QSFI_CH_INTERRUPT_ENABLE_MASK 0xc000 1422 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_QSFI_CH_INTERRUPT_ENABLE_ALIGN 0 1423 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_QSFI_CH_INTERRUPT_ENABLE_BITS 2 1424 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_QSFI_CH_INTERRUPT_ENABLE_SHIFT 14 1425 1426 /* MGT_TOP_PMD_USR :: interrupt_m8051_enable_register :: External_PCS_Linkup_enable [13:13] */ 1427 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKUP_ENABLE_MASK 0x2000 1428 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKUP_ENABLE_ALIGN 0 1429 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKUP_ENABLE_BITS 1 1430 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKUP_ENABLE_SHIFT 13 1431 1432 /* MGT_TOP_PMD_USR :: interrupt_m8051_enable_register :: External_PCS_Linkdown_enable [12:12] */ 1433 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKDOWN_ENABLE_MASK 0x1000 1434 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKDOWN_ENABLE_ALIGN 0 1435 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKDOWN_ENABLE_BITS 1 1436 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_EXTERNAL_PCS_LINKDOWN_ENABLE_SHIFT 12 1437 1438 /* MGT_TOP_PMD_USR :: interrupt_m8051_enable_register :: loss_of_opt_rx_interrupt_enable [11:08] */ 1439 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_LOSS_OF_OPT_RX_INTERRUPT_ENABLE_MASK 0x0f00 1440 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_LOSS_OF_OPT_RX_INTERRUPT_ENABLE_ALIGN 0 1441 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_LOSS_OF_OPT_RX_INTERRUPT_ENABLE_BITS 4 1442 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_LOSS_OF_OPT_RX_INTERRUPT_ENABLE_SHIFT 8 1443 1444 /* MGT_TOP_PMD_USR :: interrupt_m8051_enable_register :: gpio_1_interrupt [07:04] */ 1445 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_1_INTERRUPT_MASK 0x00f0 1446 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_1_INTERRUPT_ALIGN 0 1447 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_1_INTERRUPT_BITS 4 1448 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_1_INTERRUPT_SHIFT 4 1449 1450 /* MGT_TOP_PMD_USR :: interrupt_m8051_enable_register :: gpio_0_interrupt [03:00] */ 1451 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_0_INTERRUPT_MASK 0x000f 1452 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_0_INTERRUPT_ALIGN 0 1453 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_0_INTERRUPT_BITS 4 1454 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_ENABLE_REGISTER_GPIO_0_INTERRUPT_SHIFT 0 1455 1456 1457 /**************************************************************************** 1458 * MGT_TOP_PMD_USR :: interrupt_m8051_status_register 1459 */ 1460 /* MGT_TOP_PMD_USR :: interrupt_m8051_status_register :: QSFI_ch_interrupt_status [15:14] */ 1461 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_QSFI_CH_INTERRUPT_STATUS_MASK 0xc000 1462 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_QSFI_CH_INTERRUPT_STATUS_ALIGN 0 1463 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_QSFI_CH_INTERRUPT_STATUS_BITS 2 1464 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_QSFI_CH_INTERRUPT_STATUS_SHIFT 14 1465 1466 /* MGT_TOP_PMD_USR :: interrupt_m8051_status_register :: External_PCS_Linkup_status [13:13] */ 1467 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKUP_STATUS_MASK 0x2000 1468 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKUP_STATUS_ALIGN 0 1469 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKUP_STATUS_BITS 1 1470 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKUP_STATUS_SHIFT 13 1471 1472 /* MGT_TOP_PMD_USR :: interrupt_m8051_status_register :: External_PCS_Linkdown_status [12:12] */ 1473 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKDOWN_STATUS_MASK 0x1000 1474 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKDOWN_STATUS_ALIGN 0 1475 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKDOWN_STATUS_BITS 1 1476 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_EXTERNAL_PCS_LINKDOWN_STATUS_SHIFT 12 1477 1478 /* MGT_TOP_PMD_USR :: interrupt_m8051_status_register :: loss_of_optical_rxsignal_interrupt [11:08] */ 1479 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_MASK 0x0f00 1480 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_ALIGN 0 1481 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_BITS 4 1482 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_LOSS_OF_OPTICAL_RXSIGNAL_INTERRUPT_SHIFT 8 1483 1484 /* MGT_TOP_PMD_USR :: interrupt_m8051_status_register :: gpio_1_interrupt [07:04] */ 1485 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_GPIO_1_INTERRUPT_MASK 0x00f0 1486 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_GPIO_1_INTERRUPT_ALIGN 0 1487 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_GPIO_1_INTERRUPT_BITS 4 1488 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_GPIO_1_INTERRUPT_SHIFT 4 1489 1490 /* MGT_TOP_PMD_USR :: interrupt_m8051_status_register :: gpio_0_interrupt [03:00] */ 1491 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_GPIO_0_INTERRUPT_MASK 0x000f 1492 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_GPIO_0_INTERRUPT_ALIGN 0 1493 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_GPIO_0_INTERRUPT_BITS 4 1494 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_STATUS_REGISTER_GPIO_0_INTERRUPT_SHIFT 0 1495 1496 1497 /**************************************************************************** 1498 * MGT_TOP_PMD_USR :: interrupt_m8051_polarity_register 1499 */ 1500 /* MGT_TOP_PMD_USR :: interrupt_m8051_polarity_register :: assertion_level_for_QSFI_ch_interrupt [15:12] */ 1501 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_QSFI_CH_INTERRUPT_MASK 0xf000 1502 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_QSFI_CH_INTERRUPT_ALIGN 0 1503 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_QSFI_CH_INTERRUPT_BITS 4 1504 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_QSFI_CH_INTERRUPT_SHIFT 12 1505 1506 /* MGT_TOP_PMD_USR :: interrupt_m8051_polarity_register :: assertion_level_for_opt_Rx_los_interrupt [11:08] */ 1507 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_OPT_RX_LOS_INTERRUPT_MASK 0x0f00 1508 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_OPT_RX_LOS_INTERRUPT_ALIGN 0 1509 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_OPT_RX_LOS_INTERRUPT_BITS 4 1510 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_OPT_RX_LOS_INTERRUPT_SHIFT 8 1511 1512 /* MGT_TOP_PMD_USR :: interrupt_m8051_polarity_register :: assertion_level_for_GPIO1_interrupt [07:04] */ 1513 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO1_INTERRUPT_MASK 0x00f0 1514 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO1_INTERRUPT_ALIGN 0 1515 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO1_INTERRUPT_BITS 4 1516 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO1_INTERRUPT_SHIFT 4 1517 1518 /* MGT_TOP_PMD_USR :: interrupt_m8051_polarity_register :: assertion_level_for_GPIO0_interrupt [03:00] */ 1519 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO0_INTERRUPT_MASK 0x000f 1520 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO0_INTERRUPT_ALIGN 0 1521 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO0_INTERRUPT_BITS 4 1522 #define MGT_TOP_PMD_USR_INTERRUPT_M8051_POLARITY_REGISTER_ASSERTION_LEVEL_FOR_GPIO0_INTERRUPT_SHIFT 0 1523 1524 1525 /**************************************************************************** 1526 * MGT_TOP_PMD_USR :: gp_register_0 1527 */ 1528 /* MGT_TOP_PMD_USR :: gp_register_0 :: gp_register_0 [15:08] */ 1529 #define MGT_TOP_PMD_USR_GP_REGISTER_0_GP_REGISTER_0_MASK 0xff00 1530 #define MGT_TOP_PMD_USR_GP_REGISTER_0_GP_REGISTER_0_ALIGN 0 1531 #define MGT_TOP_PMD_USR_GP_REGISTER_0_GP_REGISTER_0_BITS 8 1532 #define MGT_TOP_PMD_USR_GP_REGISTER_0_GP_REGISTER_0_SHIFT 8 1533 1534 /* MGT_TOP_PMD_USR :: gp_register_0 :: module_resolution_failure [07:07] */ 1535 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MODULE_RESOLUTION_FAILURE_MASK 0x0080 1536 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MODULE_RESOLUTION_FAILURE_ALIGN 0 1537 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MODULE_RESOLUTION_FAILURE_BITS 1 1538 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MODULE_RESOLUTION_FAILURE_SHIFT 7 1539 1540 /* MGT_TOP_PMD_USR :: gp_register_0 :: i2c_data_failure [06:06] */ 1541 #define MGT_TOP_PMD_USR_GP_REGISTER_0_I2C_DATA_FAILURE_MASK 0x0040 1542 #define MGT_TOP_PMD_USR_GP_REGISTER_0_I2C_DATA_FAILURE_ALIGN 0 1543 #define MGT_TOP_PMD_USR_GP_REGISTER_0_I2C_DATA_FAILURE_BITS 1 1544 #define MGT_TOP_PMD_USR_GP_REGISTER_0_I2C_DATA_FAILURE_SHIFT 6 1545 1546 /* MGT_TOP_PMD_USR :: gp_register_0 :: Restart_i2c_access [05:05] */ 1547 #define MGT_TOP_PMD_USR_GP_REGISTER_0_RESTART_I2C_ACCESS_MASK 0x0020 1548 #define MGT_TOP_PMD_USR_GP_REGISTER_0_RESTART_I2C_ACCESS_ALIGN 0 1549 #define MGT_TOP_PMD_USR_GP_REGISTER_0_RESTART_I2C_ACCESS_BITS 1 1550 #define MGT_TOP_PMD_USR_GP_REGISTER_0_RESTART_I2C_ACCESS_SHIFT 5 1551 1552 /* MGT_TOP_PMD_USR :: gp_register_0 :: i2c_access_failure [04:04] */ 1553 #define MGT_TOP_PMD_USR_GP_REGISTER_0_I2C_ACCESS_FAILURE_MASK 0x0010 1554 #define MGT_TOP_PMD_USR_GP_REGISTER_0_I2C_ACCESS_FAILURE_ALIGN 0 1555 #define MGT_TOP_PMD_USR_GP_REGISTER_0_I2C_ACCESS_FAILURE_BITS 1 1556 #define MGT_TOP_PMD_USR_GP_REGISTER_0_I2C_ACCESS_FAILURE_SHIFT 4 1557 1558 /* MGT_TOP_PMD_USR :: gp_register_0 :: Enable_i2c_dynamic_reset [03:03] */ 1559 #define MGT_TOP_PMD_USR_GP_REGISTER_0_ENABLE_I2C_DYNAMIC_RESET_MASK 0x0008 1560 #define MGT_TOP_PMD_USR_GP_REGISTER_0_ENABLE_I2C_DYNAMIC_RESET_ALIGN 0 1561 #define MGT_TOP_PMD_USR_GP_REGISTER_0_ENABLE_I2C_DYNAMIC_RESET_BITS 1 1562 #define MGT_TOP_PMD_USR_GP_REGISTER_0_ENABLE_I2C_DYNAMIC_RESET_SHIFT 3 1563 1564 /* MGT_TOP_PMD_USR :: gp_register_0 :: gp_register_0_bit_2 [02:02] */ 1565 #define MGT_TOP_PMD_USR_GP_REGISTER_0_GP_REGISTER_0_BIT_2_MASK 0x0004 1566 #define MGT_TOP_PMD_USR_GP_REGISTER_0_GP_REGISTER_0_BIT_2_ALIGN 0 1567 #define MGT_TOP_PMD_USR_GP_REGISTER_0_GP_REGISTER_0_BIT_2_BITS 1 1568 #define MGT_TOP_PMD_USR_GP_REGISTER_0_GP_REGISTER_0_BIT_2_SHIFT 2 1569 1570 /* MGT_TOP_PMD_USR :: gp_register_0 :: Micro_timeout_4_i2c_access [01:01] */ 1571 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MICRO_TIMEOUT_4_I2C_ACCESS_MASK 0x0002 1572 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MICRO_TIMEOUT_4_I2C_ACCESS_ALIGN 0 1573 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MICRO_TIMEOUT_4_I2C_ACCESS_BITS 1 1574 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MICRO_TIMEOUT_4_I2C_ACCESS_SHIFT 1 1575 1576 /* MGT_TOP_PMD_USR :: gp_register_0 :: Mod_ABS_asserted [00:00] */ 1577 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MOD_ABS_ASSERTED_MASK 0x0001 1578 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MOD_ABS_ASSERTED_ALIGN 0 1579 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MOD_ABS_ASSERTED_BITS 1 1580 #define MGT_TOP_PMD_USR_GP_REGISTER_0_MOD_ABS_ASSERTED_SHIFT 0 1581 1582 1583 /**************************************************************************** 1584 * MGT_TOP_PMD_USR :: gp_register_1 1585 */ 1586 /* MGT_TOP_PMD_USR :: gp_register_1 :: System_LR_mode [15:15] */ 1587 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_LR_MODE_MASK 0x8000 1588 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_LR_MODE_ALIGN 0 1589 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_LR_MODE_BITS 1 1590 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_LR_MODE_SHIFT 15 1591 1592 /* MGT_TOP_PMD_USR :: gp_register_1 :: Line_LR_mode [14:14] */ 1593 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_LR_MODE_MASK 0x4000 1594 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_LR_MODE_ALIGN 0 1595 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_LR_MODE_BITS 1 1596 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_LR_MODE_SHIFT 14 1597 1598 /* MGT_TOP_PMD_USR :: gp_register_1 :: System_Forced_CL72_mode [13:13] */ 1599 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_FORCED_CL72_MODE_MASK 0x2000 1600 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_FORCED_CL72_MODE_ALIGN 0 1601 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_FORCED_CL72_MODE_BITS 1 1602 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_FORCED_CL72_MODE_SHIFT 13 1603 1604 /* MGT_TOP_PMD_USR :: gp_register_1 :: Line_Forced_CL72_mode [12:12] */ 1605 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_FORCED_CL72_MODE_MASK 0x1000 1606 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_FORCED_CL72_MODE_ALIGN 0 1607 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_FORCED_CL72_MODE_BITS 1 1608 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_FORCED_CL72_MODE_SHIFT 12 1609 1610 /* MGT_TOP_PMD_USR :: gp_register_1 :: System_Cu_Type [11:11] */ 1611 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_CU_TYPE_MASK 0x0800 1612 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_CU_TYPE_ALIGN 0 1613 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_CU_TYPE_BITS 1 1614 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_CU_TYPE_SHIFT 11 1615 1616 /* MGT_TOP_PMD_USR :: gp_register_1 :: System_Type [10:10] */ 1617 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_TYPE_MASK 0x0400 1618 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_TYPE_ALIGN 0 1619 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_TYPE_BITS 1 1620 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SYSTEM_TYPE_SHIFT 10 1621 1622 /* MGT_TOP_PMD_USR :: gp_register_1 :: Line_Cu_Type [09:09] */ 1623 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_CU_TYPE_MASK 0x0200 1624 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_CU_TYPE_ALIGN 0 1625 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_CU_TYPE_BITS 1 1626 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_CU_TYPE_SHIFT 9 1627 1628 /* MGT_TOP_PMD_USR :: gp_register_1 :: Line_Type [08:08] */ 1629 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_TYPE_MASK 0x0100 1630 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_TYPE_ALIGN 0 1631 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_TYPE_BITS 1 1632 #define MGT_TOP_PMD_USR_GP_REGISTER_1_LINE_TYPE_SHIFT 8 1633 1634 /* MGT_TOP_PMD_USR :: gp_register_1 :: finish_change [07:07] */ 1635 #define MGT_TOP_PMD_USR_GP_REGISTER_1_FINISH_CHANGE_MASK 0x0080 1636 #define MGT_TOP_PMD_USR_GP_REGISTER_1_FINISH_CHANGE_ALIGN 0 1637 #define MGT_TOP_PMD_USR_GP_REGISTER_1_FINISH_CHANGE_BITS 1 1638 #define MGT_TOP_PMD_USR_GP_REGISTER_1_FINISH_CHANGE_SHIFT 7 1639 1640 /* MGT_TOP_PMD_USR :: gp_register_1 :: Enable_ultra_low_latency_datapath [06:06] */ 1641 #define MGT_TOP_PMD_USR_GP_REGISTER_1_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_MASK 0x0040 1642 #define MGT_TOP_PMD_USR_GP_REGISTER_1_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_ALIGN 0 1643 #define MGT_TOP_PMD_USR_GP_REGISTER_1_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_BITS 1 1644 #define MGT_TOP_PMD_USR_GP_REGISTER_1_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_SHIFT 6 1645 1646 /* MGT_TOP_PMD_USR :: gp_register_1 :: ULL_datapath_latency [05:05] */ 1647 #define MGT_TOP_PMD_USR_GP_REGISTER_1_ULL_DATAPATH_LATENCY_MASK 0x0020 1648 #define MGT_TOP_PMD_USR_GP_REGISTER_1_ULL_DATAPATH_LATENCY_ALIGN 0 1649 #define MGT_TOP_PMD_USR_GP_REGISTER_1_ULL_DATAPATH_LATENCY_BITS 1 1650 #define MGT_TOP_PMD_USR_GP_REGISTER_1_ULL_DATAPATH_LATENCY_SHIFT 5 1651 1652 /* MGT_TOP_PMD_USR :: gp_register_1 :: Speed_or_Type_change [04:04] */ 1653 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_OR_TYPE_CHANGE_MASK 0x0010 1654 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_OR_TYPE_CHANGE_ALIGN 0 1655 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_OR_TYPE_CHANGE_BITS 1 1656 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_OR_TYPE_CHANGE_SHIFT 4 1657 1658 /* MGT_TOP_PMD_USR :: gp_register_1 :: Speed_100G [03:03] */ 1659 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_100G_MASK 0x0008 1660 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_100G_ALIGN 0 1661 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_100G_BITS 1 1662 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_100G_SHIFT 3 1663 1664 /* MGT_TOP_PMD_USR :: gp_register_1 :: Speed_40G [02:02] */ 1665 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_40G_MASK 0x0004 1666 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_40G_ALIGN 0 1667 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_40G_BITS 1 1668 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_40G_SHIFT 2 1669 1670 /* MGT_TOP_PMD_USR :: gp_register_1 :: Speed_10G [01:01] */ 1671 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_10G_MASK 0x0002 1672 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_10G_ALIGN 0 1673 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_10G_BITS 1 1674 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_10G_SHIFT 1 1675 1676 /* MGT_TOP_PMD_USR :: gp_register_1 :: Speed_1G [00:00] */ 1677 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_1G_MASK 0x0001 1678 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_1G_ALIGN 0 1679 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_1G_BITS 1 1680 #define MGT_TOP_PMD_USR_GP_REGISTER_1_SPEED_1G_SHIFT 0 1681 1682 1683 /**************************************************************************** 1684 * MGT_TOP_PMD_USR :: gp_register_2 1685 */ 1686 /* MGT_TOP_PMD_USR :: gp_register_2 :: gp_register_2 [15:00] */ 1687 #define MGT_TOP_PMD_USR_GP_REGISTER_2_GP_REGISTER_2_MASK 0xffff 1688 #define MGT_TOP_PMD_USR_GP_REGISTER_2_GP_REGISTER_2_ALIGN 0 1689 #define MGT_TOP_PMD_USR_GP_REGISTER_2_GP_REGISTER_2_BITS 16 1690 #define MGT_TOP_PMD_USR_GP_REGISTER_2_GP_REGISTER_2_SHIFT 0 1691 1692 1693 /**************************************************************************** 1694 * MGT_TOP_PMD_USR :: gp_register_3 1695 */ 1696 /* MGT_TOP_PMD_USR :: gp_register_3 :: System_LR_mode [15:15] */ 1697 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_LR_MODE_MASK 0x8000 1698 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_LR_MODE_ALIGN 0 1699 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_LR_MODE_BITS 1 1700 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_LR_MODE_SHIFT 15 1701 1702 /* MGT_TOP_PMD_USR :: gp_register_3 :: Line_LR_mode [14:14] */ 1703 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_LR_MODE_MASK 0x4000 1704 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_LR_MODE_ALIGN 0 1705 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_LR_MODE_BITS 1 1706 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_LR_MODE_SHIFT 14 1707 1708 /* MGT_TOP_PMD_USR :: gp_register_3 :: System_Forced_CL72_mode [13:13] */ 1709 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_FORCED_CL72_MODE_MASK 0x2000 1710 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_FORCED_CL72_MODE_ALIGN 0 1711 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_FORCED_CL72_MODE_BITS 1 1712 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_FORCED_CL72_MODE_SHIFT 13 1713 1714 /* MGT_TOP_PMD_USR :: gp_register_3 :: Line_Forced_CL72_mode [12:12] */ 1715 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_FORCED_CL72_MODE_MASK 0x1000 1716 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_FORCED_CL72_MODE_ALIGN 0 1717 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_FORCED_CL72_MODE_BITS 1 1718 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_FORCED_CL72_MODE_SHIFT 12 1719 1720 /* MGT_TOP_PMD_USR :: gp_register_3 :: System_Cu_Type [11:11] */ 1721 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_CU_TYPE_MASK 0x0800 1722 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_CU_TYPE_ALIGN 0 1723 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_CU_TYPE_BITS 1 1724 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_CU_TYPE_SHIFT 11 1725 1726 /* MGT_TOP_PMD_USR :: gp_register_3 :: System_Type [10:10] */ 1727 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_TYPE_MASK 0x0400 1728 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_TYPE_ALIGN 0 1729 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_TYPE_BITS 1 1730 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SYSTEM_TYPE_SHIFT 10 1731 1732 /* MGT_TOP_PMD_USR :: gp_register_3 :: Line_Cu_Type [09:09] */ 1733 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_CU_TYPE_MASK 0x0200 1734 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_CU_TYPE_ALIGN 0 1735 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_CU_TYPE_BITS 1 1736 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_CU_TYPE_SHIFT 9 1737 1738 /* MGT_TOP_PMD_USR :: gp_register_3 :: Line_Type [08:08] */ 1739 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_TYPE_MASK 0x0100 1740 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_TYPE_ALIGN 0 1741 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_TYPE_BITS 1 1742 #define MGT_TOP_PMD_USR_GP_REGISTER_3_LINE_TYPE_SHIFT 8 1743 1744 /* MGT_TOP_PMD_USR :: gp_register_3 :: finish_change [07:07] */ 1745 #define MGT_TOP_PMD_USR_GP_REGISTER_3_FINISH_CHANGE_MASK 0x0080 1746 #define MGT_TOP_PMD_USR_GP_REGISTER_3_FINISH_CHANGE_ALIGN 0 1747 #define MGT_TOP_PMD_USR_GP_REGISTER_3_FINISH_CHANGE_BITS 1 1748 #define MGT_TOP_PMD_USR_GP_REGISTER_3_FINISH_CHANGE_SHIFT 7 1749 1750 /* MGT_TOP_PMD_USR :: gp_register_3 :: Enable_ultra_low_latency_datapath [06:06] */ 1751 #define MGT_TOP_PMD_USR_GP_REGISTER_3_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_MASK 0x0040 1752 #define MGT_TOP_PMD_USR_GP_REGISTER_3_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_ALIGN 0 1753 #define MGT_TOP_PMD_USR_GP_REGISTER_3_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_BITS 1 1754 #define MGT_TOP_PMD_USR_GP_REGISTER_3_ENABLE_ULTRA_LOW_LATENCY_DATAPATH_SHIFT 6 1755 1756 /* MGT_TOP_PMD_USR :: gp_register_3 :: ULL_datapath_latency [05:05] */ 1757 #define MGT_TOP_PMD_USR_GP_REGISTER_3_ULL_DATAPATH_LATENCY_MASK 0x0020 1758 #define MGT_TOP_PMD_USR_GP_REGISTER_3_ULL_DATAPATH_LATENCY_ALIGN 0 1759 #define MGT_TOP_PMD_USR_GP_REGISTER_3_ULL_DATAPATH_LATENCY_BITS 1 1760 #define MGT_TOP_PMD_USR_GP_REGISTER_3_ULL_DATAPATH_LATENCY_SHIFT 5 1761 1762 /* MGT_TOP_PMD_USR :: gp_register_3 :: Speed_or_Type_change [04:04] */ 1763 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_OR_TYPE_CHANGE_MASK 0x0010 1764 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_OR_TYPE_CHANGE_ALIGN 0 1765 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_OR_TYPE_CHANGE_BITS 1 1766 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_OR_TYPE_CHANGE_SHIFT 4 1767 1768 /* MGT_TOP_PMD_USR :: gp_register_3 :: Speed_100G [03:03] */ 1769 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_100G_MASK 0x0008 1770 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_100G_ALIGN 0 1771 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_100G_BITS 1 1772 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_100G_SHIFT 3 1773 1774 /* MGT_TOP_PMD_USR :: gp_register_3 :: Speed_40G [02:02] */ 1775 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_40G_MASK 0x0004 1776 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_40G_ALIGN 0 1777 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_40G_BITS 1 1778 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_40G_SHIFT 2 1779 1780 /* MGT_TOP_PMD_USR :: gp_register_3 :: Speed_10G [01:01] */ 1781 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_10G_MASK 0x0002 1782 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_10G_ALIGN 0 1783 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_10G_BITS 1 1784 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_10G_SHIFT 1 1785 1786 /* MGT_TOP_PMD_USR :: gp_register_3 :: Speed_1G [00:00] */ 1787 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_1G_MASK 0x0001 1788 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_1G_ALIGN 0 1789 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_1G_BITS 1 1790 #define MGT_TOP_PMD_USR_GP_REGISTER_3_SPEED_1G_SHIFT 0 1791 1792 1793 /**************************************************************************** 1794 * MGT_TOP_PMD_USR :: gp_status_register_0 1795 */ 1796 /* MGT_TOP_PMD_USR :: gp_status_register_0 :: misc_status_15_0 [15:00] */ 1797 #define MGT_TOP_PMD_USR_GP_STATUS_REGISTER_0_MISC_STATUS_15_0_MASK 0xffff 1798 #define MGT_TOP_PMD_USR_GP_STATUS_REGISTER_0_MISC_STATUS_15_0_ALIGN 0 1799 #define MGT_TOP_PMD_USR_GP_STATUS_REGISTER_0_MISC_STATUS_15_0_BITS 16 1800 #define MGT_TOP_PMD_USR_GP_STATUS_REGISTER_0_MISC_STATUS_15_0_SHIFT 0 1801 1802 1803 /**************************************************************************** 1804 * MGT_TOP_PMD_USR :: gp_status_register_1 1805 */ 1806 /* MGT_TOP_PMD_USR :: gp_status_register_1 :: misc_status_31_16 [15:00] */ 1807 #define MGT_TOP_PMD_USR_GP_STATUS_REGISTER_1_MISC_STATUS_31_16_MASK 0xffff 1808 #define MGT_TOP_PMD_USR_GP_STATUS_REGISTER_1_MISC_STATUS_31_16_ALIGN 0 1809 #define MGT_TOP_PMD_USR_GP_STATUS_REGISTER_1_MISC_STATUS_31_16_BITS 16 1810 #define MGT_TOP_PMD_USR_GP_STATUS_REGISTER_1_MISC_STATUS_31_16_SHIFT 0 1811 1812 1813 /**************************************************************************** 1814 * MGT_TOP_PMD_USR :: spa_control_status_register 1815 */ 1816 /* MGT_TOP_PMD_USR :: spa_control_status_register :: spi_port_used [15:15] */ 1817 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_PORT_USED_MASK 0x8000 1818 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_PORT_USED_ALIGN 0 1819 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_PORT_USED_BITS 1 1820 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_PORT_USED_SHIFT 15 1821 1822 /* MGT_TOP_PMD_USR :: spa_control_status_register :: spi_boot [14:14] */ 1823 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_BOOT_MASK 0x4000 1824 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_BOOT_ALIGN 0 1825 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_BOOT_BITS 1 1826 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_BOOT_SHIFT 14 1827 1828 /* MGT_TOP_PMD_USR :: spa_control_status_register :: spi_dwld_done [13:13] */ 1829 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_DWLD_DONE_MASK 0x2000 1830 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_DWLD_DONE_ALIGN 0 1831 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_DWLD_DONE_BITS 1 1832 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_DWLD_DONE_SHIFT 13 1833 1834 /* MGT_TOP_PMD_USR :: spa_control_status_register :: spa_en [12:12] */ 1835 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPA_EN_MASK 0x1000 1836 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPA_EN_ALIGN 0 1837 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPA_EN_BITS 1 1838 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPA_EN_SHIFT 12 1839 1840 /* MGT_TOP_PMD_USR :: spa_control_status_register :: gp_por_ctl [11:04] */ 1841 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_GP_POR_CTL_MASK 0x0ff0 1842 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_GP_POR_CTL_ALIGN 0 1843 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_GP_POR_CTL_BITS 8 1844 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_GP_POR_CTL_SHIFT 4 1845 1846 /* MGT_TOP_PMD_USR :: spa_control_status_register :: use_irom_isr [03:03] */ 1847 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_USE_IROM_ISR_MASK 0x0008 1848 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_USE_IROM_ISR_ALIGN 0 1849 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_USE_IROM_ISR_BITS 1 1850 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_USE_IROM_ISR_SHIFT 3 1851 1852 /* MGT_TOP_PMD_USR :: spa_control_status_register :: reserved0 [02:01] */ 1853 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_RESERVED0_MASK 0x0006 1854 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_RESERVED0_ALIGN 0 1855 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_RESERVED0_BITS 2 1856 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_RESERVED0_SHIFT 1 1857 1858 /* MGT_TOP_PMD_USR :: spa_control_status_register :: spi_ports_enable [00:00] */ 1859 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_PORTS_ENABLE_MASK 0x0001 1860 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_PORTS_ENABLE_ALIGN 0 1861 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_PORTS_ENABLE_BITS 1 1862 #define MGT_TOP_PMD_USR_SPA_CONTROL_STATUS_REGISTER_SPI_PORTS_ENABLE_SHIFT 0 1863 1864 1865 /**************************************************************************** 1866 * MGT_TOP_PMD_USR :: otp_misc_sig1_register 1867 */ 1868 /* MGT_TOP_PMD_USR :: otp_misc_sig1_register :: otp_misc_sig1 [15:00] */ 1869 #define MGT_TOP_PMD_USR_OTP_MISC_SIG1_REGISTER_OTP_MISC_SIG1_MASK 0xffff 1870 #define MGT_TOP_PMD_USR_OTP_MISC_SIG1_REGISTER_OTP_MISC_SIG1_ALIGN 0 1871 #define MGT_TOP_PMD_USR_OTP_MISC_SIG1_REGISTER_OTP_MISC_SIG1_BITS 16 1872 #define MGT_TOP_PMD_USR_OTP_MISC_SIG1_REGISTER_OTP_MISC_SIG1_SHIFT 0 1873 1874 1875 /**************************************************************************** 1876 * MGT_TOP_PMD_USR :: otp_misc_sig2_register 1877 */ 1878 /* MGT_TOP_PMD_USR :: otp_misc_sig2_register :: otp_misc_sig2 [15:00] */ 1879 #define MGT_TOP_PMD_USR_OTP_MISC_SIG2_REGISTER_OTP_MISC_SIG2_MASK 0xffff 1880 #define MGT_TOP_PMD_USR_OTP_MISC_SIG2_REGISTER_OTP_MISC_SIG2_ALIGN 0 1881 #define MGT_TOP_PMD_USR_OTP_MISC_SIG2_REGISTER_OTP_MISC_SIG2_BITS 16 1882 #define MGT_TOP_PMD_USR_OTP_MISC_SIG2_REGISTER_OTP_MISC_SIG2_SHIFT 0 1883 1884 1885 /**************************************************************************** 1886 * MGT_TOP_PMD_USR :: otp_misc_sig3_register 1887 */ 1888 /* MGT_TOP_PMD_USR :: otp_misc_sig3_register :: otp_misc_sig3 [15:00] */ 1889 #define MGT_TOP_PMD_USR_OTP_MISC_SIG3_REGISTER_OTP_MISC_SIG3_MASK 0xffff 1890 #define MGT_TOP_PMD_USR_OTP_MISC_SIG3_REGISTER_OTP_MISC_SIG3_ALIGN 0 1891 #define MGT_TOP_PMD_USR_OTP_MISC_SIG3_REGISTER_OTP_MISC_SIG3_BITS 16 1892 #define MGT_TOP_PMD_USR_OTP_MISC_SIG3_REGISTER_OTP_MISC_SIG3_SHIFT 0 1893 1894 1895 /**************************************************************************** 1896 * MGT_TOP_PMD_USR :: otp_misc_sig4_register 1897 */ 1898 /* MGT_TOP_PMD_USR :: otp_misc_sig4_register :: otp_misc_sig4 [15:00] */ 1899 #define MGT_TOP_PMD_USR_OTP_MISC_SIG4_REGISTER_OTP_MISC_SIG4_MASK 0xffff 1900 #define MGT_TOP_PMD_USR_OTP_MISC_SIG4_REGISTER_OTP_MISC_SIG4_ALIGN 0 1901 #define MGT_TOP_PMD_USR_OTP_MISC_SIG4_REGISTER_OTP_MISC_SIG4_BITS 16 1902 #define MGT_TOP_PMD_USR_OTP_MISC_SIG4_REGISTER_OTP_MISC_SIG4_SHIFT 0 1903 1904 1905 /**************************************************************************** 1906 * MGT_TOP_PMD_USR :: otp_misc_sig5_register 1907 */ 1908 /* MGT_TOP_PMD_USR :: otp_misc_sig5_register :: otp_misc_sig5 [15:00] */ 1909 #define MGT_TOP_PMD_USR_OTP_MISC_SIG5_REGISTER_OTP_MISC_SIG5_MASK 0xffff 1910 #define MGT_TOP_PMD_USR_OTP_MISC_SIG5_REGISTER_OTP_MISC_SIG5_ALIGN 0 1911 #define MGT_TOP_PMD_USR_OTP_MISC_SIG5_REGISTER_OTP_MISC_SIG5_BITS 16 1912 #define MGT_TOP_PMD_USR_OTP_MISC_SIG5_REGISTER_OTP_MISC_SIG5_SHIFT 0 1913 1914 1915 /**************************************************************************** 1916 * MGT_TOP_PMD_USR :: otp_misc_sig6_register 1917 */ 1918 /* MGT_TOP_PMD_USR :: otp_misc_sig6_register :: otp_misc_sig6 [15:00] */ 1919 #define MGT_TOP_PMD_USR_OTP_MISC_SIG6_REGISTER_OTP_MISC_SIG6_MASK 0xffff 1920 #define MGT_TOP_PMD_USR_OTP_MISC_SIG6_REGISTER_OTP_MISC_SIG6_ALIGN 0 1921 #define MGT_TOP_PMD_USR_OTP_MISC_SIG6_REGISTER_OTP_MISC_SIG6_BITS 16 1922 #define MGT_TOP_PMD_USR_OTP_MISC_SIG6_REGISTER_OTP_MISC_SIG6_SHIFT 0 1923 1924 1925 /**************************************************************************** 1926 * MGT_TOP_PMD_USR :: gp_reg_c870_register 1927 */ 1928 /* MGT_TOP_PMD_USR :: gp_reg_c870_register :: reserved0 [15:11] */ 1929 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RESERVED0_MASK 0xf800 1930 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RESERVED0_ALIGN 0 1931 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RESERVED0_BITS 5 1932 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RESERVED0_SHIFT 11 1933 1934 /* MGT_TOP_PMD_USR :: gp_reg_c870_register :: cdr_lkdt_manual_value [10:10] */ 1935 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_VALUE_MASK 0x0400 1936 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_VALUE_ALIGN 0 1937 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_VALUE_BITS 1 1938 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_VALUE_SHIFT 10 1939 1940 /* MGT_TOP_PMD_USR :: gp_reg_c870_register :: cdr_lkdt_manual_en [09:09] */ 1941 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_EN_MASK 0x0200 1942 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_EN_ALIGN 0 1943 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_EN_BITS 1 1944 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_CDR_LKDT_MANUAL_EN_SHIFT 9 1945 1946 /* MGT_TOP_PMD_USR :: gp_reg_c870_register :: rx_los_manual_value [08:08] */ 1947 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RX_LOS_MANUAL_VALUE_MASK 0x0100 1948 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RX_LOS_MANUAL_VALUE_ALIGN 0 1949 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RX_LOS_MANUAL_VALUE_BITS 1 1950 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RX_LOS_MANUAL_VALUE_SHIFT 8 1951 1952 /* MGT_TOP_PMD_USR :: gp_reg_c870_register :: rx_los_manual_en [07:07] */ 1953 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RX_LOS_MANUAL_EN_MASK 0x0080 1954 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RX_LOS_MANUAL_EN_ALIGN 0 1955 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RX_LOS_MANUAL_EN_BITS 1 1956 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RX_LOS_MANUAL_EN_SHIFT 7 1957 1958 /* MGT_TOP_PMD_USR :: gp_reg_c870_register :: sys_cdr_lkdt_manual_value [06:06] */ 1959 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_VALUE_MASK 0x0040 1960 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_VALUE_ALIGN 0 1961 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_VALUE_BITS 1 1962 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_VALUE_SHIFT 6 1963 1964 /* MGT_TOP_PMD_USR :: gp_reg_c870_register :: sys_cdr_lkdt_manual_en [05:05] */ 1965 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_EN_MASK 0x0020 1966 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_EN_ALIGN 0 1967 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_EN_BITS 1 1968 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_SYS_CDR_LKDT_MANUAL_EN_SHIFT 5 1969 1970 /* MGT_TOP_PMD_USR :: gp_reg_c870_register :: reserved1 [04:00] */ 1971 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RESERVED1_MASK 0x001f 1972 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RESERVED1_ALIGN 0 1973 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RESERVED1_BITS 5 1974 #define MGT_TOP_PMD_USR_GP_REG_C870_REGISTER_RESERVED1_SHIFT 0 1975 1976 1977 /**************************************************************************** 1978 * MGT_TOP_PMD_USR :: m8051_watchdog_control_register 1979 */ 1980 /* MGT_TOP_PMD_USR :: m8051_watchdog_control_register :: m8051_wdog_freeze [15:15] */ 1981 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_FREEZE_MASK 0x8000 1982 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_FREEZE_ALIGN 0 1983 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_FREEZE_BITS 1 1984 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_FREEZE_SHIFT 15 1985 1986 /* MGT_TOP_PMD_USR :: m8051_watchdog_control_register :: reserved0 [14:12] */ 1987 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_RESERVED0_MASK 0x7000 1988 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_RESERVED0_ALIGN 0 1989 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_RESERVED0_BITS 3 1990 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_RESERVED0_SHIFT 12 1991 1992 /* MGT_TOP_PMD_USR :: m8051_watchdog_control_register :: m8051_wdog_init [11:00] */ 1993 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_INIT_MASK 0x0fff 1994 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_INIT_ALIGN 0 1995 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_INIT_BITS 12 1996 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_CONTROL_REGISTER_M8051_WDOG_INIT_SHIFT 0 1997 1998 1999 /**************************************************************************** 2000 * MGT_TOP_PMD_USR :: m8051_watchdog_status_register 2001 */ 2002 /* MGT_TOP_PMD_USR :: m8051_watchdog_status_register :: reserved0 [15:12] */ 2003 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_STATUS_REGISTER_RESERVED0_MASK 0xf000 2004 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_STATUS_REGISTER_RESERVED0_ALIGN 0 2005 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_STATUS_REGISTER_RESERVED0_BITS 4 2006 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_STATUS_REGISTER_RESERVED0_SHIFT 12 2007 2008 /* MGT_TOP_PMD_USR :: m8051_watchdog_status_register :: m8051_wdog_cnt [11:00] */ 2009 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_STATUS_REGISTER_M8051_WDOG_CNT_MASK 0x0fff 2010 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_STATUS_REGISTER_M8051_WDOG_CNT_ALIGN 0 2011 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_STATUS_REGISTER_M8051_WDOG_CNT_BITS 12 2012 #define MGT_TOP_PMD_USR_M8051_WATCHDOG_STATUS_REGISTER_M8051_WDOG_CNT_SHIFT 0 2013 2014 2015 /**************************************************************************** 2016 * MGT_TOP_PMD_USR :: chip_intr_stat 2017 */ 2018 /* MGT_TOP_PMD_USR :: chip_intr_stat :: uncorrectable_error_det_sram_stat [15:15] */ 2019 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_UNCORRECTABLE_ERROR_DET_SRAM_STAT_MASK 0x8000 2020 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_UNCORRECTABLE_ERROR_DET_SRAM_STAT_ALIGN 0 2021 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_UNCORRECTABLE_ERROR_DET_SRAM_STAT_BITS 1 2022 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_UNCORRECTABLE_ERROR_DET_SRAM_STAT_SHIFT 15 2023 2024 /* MGT_TOP_PMD_USR :: chip_intr_stat :: correctable_error_det_sram_stat [14:14] */ 2025 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_CORRECTABLE_ERROR_DET_SRAM_STAT_MASK 0x4000 2026 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_CORRECTABLE_ERROR_DET_SRAM_STAT_ALIGN 0 2027 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_CORRECTABLE_ERROR_DET_SRAM_STAT_BITS 1 2028 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_CORRECTABLE_ERROR_DET_SRAM_STAT_SHIFT 14 2029 2030 /* MGT_TOP_PMD_USR :: chip_intr_stat :: Micro_generated_attention_stat [13:13] */ 2031 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MICRO_GENERATED_ATTENTION_STAT_MASK 0x2000 2032 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MICRO_GENERATED_ATTENTION_STAT_ALIGN 0 2033 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MICRO_GENERATED_ATTENTION_STAT_BITS 1 2034 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MICRO_GENERATED_ATTENTION_STAT_SHIFT 13 2035 2036 /* MGT_TOP_PMD_USR :: chip_intr_stat :: watch_dog_timer_expired_stat [12:12] */ 2037 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_WATCH_DOG_TIMER_EXPIRED_STAT_MASK 0x1000 2038 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_WATCH_DOG_TIMER_EXPIRED_STAT_ALIGN 0 2039 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_WATCH_DOG_TIMER_EXPIRED_STAT_BITS 1 2040 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_WATCH_DOG_TIMER_EXPIRED_STAT_SHIFT 12 2041 2042 /* MGT_TOP_PMD_USR :: chip_intr_stat :: ln_autoneg_completed_stat [11:11] */ 2043 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_AUTONEG_COMPLETED_STAT_MASK 0x0800 2044 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_AUTONEG_COMPLETED_STAT_ALIGN 0 2045 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_AUTONEG_COMPLETED_STAT_BITS 1 2046 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_AUTONEG_COMPLETED_STAT_SHIFT 11 2047 2048 /* MGT_TOP_PMD_USR :: chip_intr_stat :: sys_autoneg_completed_stat [10:10] */ 2049 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_AUTONEG_COMPLETED_STAT_MASK 0x0400 2050 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_AUTONEG_COMPLETED_STAT_ALIGN 0 2051 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_AUTONEG_COMPLETED_STAT_BITS 1 2052 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_AUTONEG_COMPLETED_STAT_SHIFT 10 2053 2054 /* MGT_TOP_PMD_USR :: chip_intr_stat :: Micro_message_stat [09:09] */ 2055 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MICRO_MESSAGE_STAT_MASK 0x0200 2056 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MICRO_MESSAGE_STAT_ALIGN 0 2057 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MICRO_MESSAGE_STAT_BITS 1 2058 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MICRO_MESSAGE_STAT_SHIFT 9 2059 2060 /* MGT_TOP_PMD_USR :: chip_intr_stat :: pad_gp_in_1 [08:08] */ 2061 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_GP_IN_1_MASK 0x0100 2062 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_GP_IN_1_ALIGN 0 2063 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_GP_IN_1_BITS 1 2064 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_GP_IN_1_SHIFT 8 2065 2066 /* MGT_TOP_PMD_USR :: chip_intr_stat :: pad_gp_in_0 [07:07] */ 2067 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_GP_IN_0_MASK 0x0080 2068 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_GP_IN_0_ALIGN 0 2069 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_GP_IN_0_BITS 1 2070 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_GP_IN_0_SHIFT 7 2071 2072 /* MGT_TOP_PMD_USR :: chip_intr_stat :: pad_extPCS_Link [06:06] */ 2073 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_EXTPCS_LINK_MASK 0x0040 2074 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_EXTPCS_LINK_ALIGN 0 2075 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_EXTPCS_LINK_BITS 1 2076 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_PAD_EXTPCS_LINK_SHIFT 6 2077 2078 /* MGT_TOP_PMD_USR :: chip_intr_stat :: sys_cmu_lkdt_stat [05:05] */ 2079 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_CMU_LKDT_STAT_MASK 0x0020 2080 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_CMU_LKDT_STAT_ALIGN 0 2081 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_CMU_LKDT_STAT_BITS 1 2082 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_CMU_LKDT_STAT_SHIFT 5 2083 2084 /* MGT_TOP_PMD_USR :: chip_intr_stat :: ln_cmu_lkdt_stat [04:04] */ 2085 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_CMU_LKDT_STAT_MASK 0x0010 2086 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_CMU_LKDT_STAT_ALIGN 0 2087 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_CMU_LKDT_STAT_BITS 1 2088 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_CMU_LKDT_STAT_SHIFT 4 2089 2090 /* MGT_TOP_PMD_USR :: chip_intr_stat :: ln_cdr_lkdt_stat [03:03] */ 2091 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_CDR_LKDT_STAT_MASK 0x0008 2092 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_CDR_LKDT_STAT_ALIGN 0 2093 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_CDR_LKDT_STAT_BITS 1 2094 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_LN_CDR_LKDT_STAT_SHIFT 3 2095 2096 /* MGT_TOP_PMD_USR :: chip_intr_stat :: opt_los_stat [02:02] */ 2097 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_OPT_LOS_STAT_MASK 0x0004 2098 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_OPT_LOS_STAT_ALIGN 0 2099 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_OPT_LOS_STAT_BITS 1 2100 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_OPT_LOS_STAT_SHIFT 2 2101 2102 /* MGT_TOP_PMD_USR :: chip_intr_stat :: sys_cdr_lkdt_stat [01:01] */ 2103 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_CDR_LKDT_STAT_MASK 0x0002 2104 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_CDR_LKDT_STAT_ALIGN 0 2105 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_CDR_LKDT_STAT_BITS 1 2106 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_SYS_CDR_LKDT_STAT_SHIFT 1 2107 2108 /* MGT_TOP_PMD_USR :: chip_intr_stat :: mod_abs_stat [00:00] */ 2109 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MOD_ABS_STAT_MASK 0x0001 2110 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MOD_ABS_STAT_ALIGN 0 2111 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MOD_ABS_STAT_BITS 1 2112 #define MGT_TOP_PMD_USR_CHIP_INTR_STAT_MOD_ABS_STAT_SHIFT 0 2113 2114 2115 /**************************************************************************** 2116 * MGT_TOP_PMD_USR :: chip_intr_en 2117 */ 2118 /* MGT_TOP_PMD_USR :: chip_intr_en :: Micro_intr_en [15:14] */ 2119 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_MICRO_INTR_EN_MASK 0xc000 2120 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_MICRO_INTR_EN_ALIGN 0 2121 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_MICRO_INTR_EN_BITS 2 2122 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_MICRO_INTR_EN_SHIFT 14 2123 2124 /* MGT_TOP_PMD_USR :: chip_intr_en :: sw_intr_en [13:13] */ 2125 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SW_INTR_EN_MASK 0x2000 2126 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SW_INTR_EN_ALIGN 0 2127 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SW_INTR_EN_BITS 1 2128 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SW_INTR_EN_SHIFT 13 2129 2130 /* MGT_TOP_PMD_USR :: chip_intr_en :: watchdog_timer_expiry_intr_en [12:12] */ 2131 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_WATCHDOG_TIMER_EXPIRY_INTR_EN_MASK 0x1000 2132 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_WATCHDOG_TIMER_EXPIRY_INTR_EN_ALIGN 0 2133 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_WATCHDOG_TIMER_EXPIRY_INTR_EN_BITS 1 2134 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_WATCHDOG_TIMER_EXPIRY_INTR_EN_SHIFT 12 2135 2136 /* MGT_TOP_PMD_USR :: chip_intr_en :: ln_autoneg_completed_intr_en [11:11] */ 2137 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_AUTONEG_COMPLETED_INTR_EN_MASK 0x0800 2138 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_AUTONEG_COMPLETED_INTR_EN_ALIGN 0 2139 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_AUTONEG_COMPLETED_INTR_EN_BITS 1 2140 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_AUTONEG_COMPLETED_INTR_EN_SHIFT 11 2141 2142 /* MGT_TOP_PMD_USR :: chip_intr_en :: sys_autoneg_completed_intr_en [10:10] */ 2143 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_AUTONEG_COMPLETED_INTR_EN_MASK 0x0400 2144 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_AUTONEG_COMPLETED_INTR_EN_ALIGN 0 2145 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_AUTONEG_COMPLETED_INTR_EN_BITS 1 2146 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_AUTONEG_COMPLETED_INTR_EN_SHIFT 10 2147 2148 /* MGT_TOP_PMD_USR :: chip_intr_en :: Micro_message_out_intr_en [09:09] */ 2149 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_MICRO_MESSAGE_OUT_INTR_EN_MASK 0x0200 2150 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_MICRO_MESSAGE_OUT_INTR_EN_ALIGN 0 2151 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_MICRO_MESSAGE_OUT_INTR_EN_BITS 1 2152 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_MICRO_MESSAGE_OUT_INTR_EN_SHIFT 9 2153 2154 /* MGT_TOP_PMD_USR :: chip_intr_en :: GPIO_IN_1_intr_en [08:08] */ 2155 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_GPIO_IN_1_INTR_EN_MASK 0x0100 2156 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_GPIO_IN_1_INTR_EN_ALIGN 0 2157 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_GPIO_IN_1_INTR_EN_BITS 1 2158 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_GPIO_IN_1_INTR_EN_SHIFT 8 2159 2160 /* MGT_TOP_PMD_USR :: chip_intr_en :: GPIO_IN_0_intr_en [07:07] */ 2161 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_GPIO_IN_0_INTR_EN_MASK 0x0080 2162 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_GPIO_IN_0_INTR_EN_ALIGN 0 2163 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_GPIO_IN_0_INTR_EN_BITS 1 2164 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_GPIO_IN_0_INTR_EN_SHIFT 7 2165 2166 /* MGT_TOP_PMD_USR :: chip_intr_en :: pad_extPCS_Link [06:06] */ 2167 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_EXTPCS_LINK_MASK 0x0040 2168 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_EXTPCS_LINK_ALIGN 0 2169 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_EXTPCS_LINK_BITS 1 2170 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_EXTPCS_LINK_SHIFT 6 2171 2172 /* MGT_TOP_PMD_USR :: chip_intr_en :: sys_cmu_lkdt_en [05:05] */ 2173 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_CMU_LKDT_EN_MASK 0x0020 2174 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_CMU_LKDT_EN_ALIGN 0 2175 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_CMU_LKDT_EN_BITS 1 2176 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_CMU_LKDT_EN_SHIFT 5 2177 2178 /* MGT_TOP_PMD_USR :: chip_intr_en :: ln_cmu_lkdt_en [04:04] */ 2179 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_CMU_LKDT_EN_MASK 0x0010 2180 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_CMU_LKDT_EN_ALIGN 0 2181 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_CMU_LKDT_EN_BITS 1 2182 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_CMU_LKDT_EN_SHIFT 4 2183 2184 /* MGT_TOP_PMD_USR :: chip_intr_en :: ln_cdr_lkdt_en [03:03] */ 2185 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_CDR_LKDT_EN_MASK 0x0008 2186 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_CDR_LKDT_EN_ALIGN 0 2187 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_CDR_LKDT_EN_BITS 1 2188 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_LN_CDR_LKDT_EN_SHIFT 3 2189 2190 /* MGT_TOP_PMD_USR :: chip_intr_en :: pad_opt_los_en [02:02] */ 2191 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_OPT_LOS_EN_MASK 0x0004 2192 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_OPT_LOS_EN_ALIGN 0 2193 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_OPT_LOS_EN_BITS 1 2194 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_OPT_LOS_EN_SHIFT 2 2195 2196 /* MGT_TOP_PMD_USR :: chip_intr_en :: sys_cdr_lkdt_en [01:01] */ 2197 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_CDR_LKDT_EN_MASK 0x0002 2198 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_CDR_LKDT_EN_ALIGN 0 2199 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_CDR_LKDT_EN_BITS 1 2200 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_SYS_CDR_LKDT_EN_SHIFT 1 2201 2202 /* MGT_TOP_PMD_USR :: chip_intr_en :: pad_mod_abs_en [00:00] */ 2203 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_MOD_ABS_EN_MASK 0x0001 2204 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_MOD_ABS_EN_ALIGN 0 2205 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_MOD_ABS_EN_BITS 1 2206 #define MGT_TOP_PMD_USR_CHIP_INTR_EN_PAD_MOD_ABS_EN_SHIFT 0 2207 2208 2209 /**************************************************************************** 2210 * MGT_TOP_PMD_USR :: chip_intr_value 2211 */ 2212 /* MGT_TOP_PMD_USR :: chip_intr_value :: micro_intr_value [15:14] */ 2213 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_MICRO_INTR_VALUE_MASK 0xc000 2214 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_MICRO_INTR_VALUE_ALIGN 0 2215 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_MICRO_INTR_VALUE_BITS 2 2216 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_MICRO_INTR_VALUE_SHIFT 14 2217 2218 /* MGT_TOP_PMD_USR :: chip_intr_value :: sw_intr_value [13:13] */ 2219 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SW_INTR_VALUE_MASK 0x2000 2220 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SW_INTR_VALUE_ALIGN 0 2221 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SW_INTR_VALUE_BITS 1 2222 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SW_INTR_VALUE_SHIFT 13 2223 2224 /* MGT_TOP_PMD_USR :: chip_intr_value :: watchdog_timer_expiry [12:12] */ 2225 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_WATCHDOG_TIMER_EXPIRY_MASK 0x1000 2226 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_WATCHDOG_TIMER_EXPIRY_ALIGN 0 2227 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_WATCHDOG_TIMER_EXPIRY_BITS 1 2228 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_WATCHDOG_TIMER_EXPIRY_SHIFT 12 2229 2230 /* MGT_TOP_PMD_USR :: chip_intr_value :: ln_autoneg_completed_value [11:11] */ 2231 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_AUTONEG_COMPLETED_VALUE_MASK 0x0800 2232 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_AUTONEG_COMPLETED_VALUE_ALIGN 0 2233 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_AUTONEG_COMPLETED_VALUE_BITS 1 2234 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_AUTONEG_COMPLETED_VALUE_SHIFT 11 2235 2236 /* MGT_TOP_PMD_USR :: chip_intr_value :: sys_autoneg_completed_value [10:10] */ 2237 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_AUTONEG_COMPLETED_VALUE_MASK 0x0400 2238 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_AUTONEG_COMPLETED_VALUE_ALIGN 0 2239 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_AUTONEG_COMPLETED_VALUE_BITS 1 2240 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_AUTONEG_COMPLETED_VALUE_SHIFT 10 2241 2242 /* MGT_TOP_PMD_USR :: chip_intr_value :: message_out_intr_value [09:09] */ 2243 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_MESSAGE_OUT_INTR_VALUE_MASK 0x0200 2244 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_MESSAGE_OUT_INTR_VALUE_ALIGN 0 2245 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_MESSAGE_OUT_INTR_VALUE_BITS 1 2246 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_MESSAGE_OUT_INTR_VALUE_SHIFT 9 2247 2248 /* MGT_TOP_PMD_USR :: chip_intr_value :: gpio_in_1_value [08:08] */ 2249 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_GPIO_IN_1_VALUE_MASK 0x0100 2250 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_GPIO_IN_1_VALUE_ALIGN 0 2251 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_GPIO_IN_1_VALUE_BITS 1 2252 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_GPIO_IN_1_VALUE_SHIFT 8 2253 2254 /* MGT_TOP_PMD_USR :: chip_intr_value :: gpio_in_0_value [07:07] */ 2255 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_GPIO_IN_0_VALUE_MASK 0x0080 2256 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_GPIO_IN_0_VALUE_ALIGN 0 2257 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_GPIO_IN_0_VALUE_BITS 1 2258 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_GPIO_IN_0_VALUE_SHIFT 7 2259 2260 /* MGT_TOP_PMD_USR :: chip_intr_value :: extPCS_Link_value [06:06] */ 2261 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_EXTPCS_LINK_VALUE_MASK 0x0040 2262 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_EXTPCS_LINK_VALUE_ALIGN 0 2263 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_EXTPCS_LINK_VALUE_BITS 1 2264 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_EXTPCS_LINK_VALUE_SHIFT 6 2265 2266 /* MGT_TOP_PMD_USR :: chip_intr_value :: sys_cmu_lkdt_value [05:05] */ 2267 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_CMU_LKDT_VALUE_MASK 0x0020 2268 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_CMU_LKDT_VALUE_ALIGN 0 2269 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_CMU_LKDT_VALUE_BITS 1 2270 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_CMU_LKDT_VALUE_SHIFT 5 2271 2272 /* MGT_TOP_PMD_USR :: chip_intr_value :: ln_cmu_lkdt_value [04:04] */ 2273 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_CMU_LKDT_VALUE_MASK 0x0010 2274 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_CMU_LKDT_VALUE_ALIGN 0 2275 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_CMU_LKDT_VALUE_BITS 1 2276 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_CMU_LKDT_VALUE_SHIFT 4 2277 2278 /* MGT_TOP_PMD_USR :: chip_intr_value :: ln_cdr_lkdt_value [03:03] */ 2279 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_CDR_LKDT_VALUE_MASK 0x0008 2280 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_CDR_LKDT_VALUE_ALIGN 0 2281 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_CDR_LKDT_VALUE_BITS 1 2282 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_LN_CDR_LKDT_VALUE_SHIFT 3 2283 2284 /* MGT_TOP_PMD_USR :: chip_intr_value :: pad_rx__los_value [02:02] */ 2285 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_PAD_RX__LOS_VALUE_MASK 0x0004 2286 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_PAD_RX__LOS_VALUE_ALIGN 0 2287 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_PAD_RX__LOS_VALUE_BITS 1 2288 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_PAD_RX__LOS_VALUE_SHIFT 2 2289 2290 /* MGT_TOP_PMD_USR :: chip_intr_value :: sys_cdr_lkdt_value [01:01] */ 2291 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_CDR_LKDT_VALUE_MASK 0x0002 2292 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_CDR_LKDT_VALUE_ALIGN 0 2293 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_CDR_LKDT_VALUE_BITS 1 2294 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_SYS_CDR_LKDT_VALUE_SHIFT 1 2295 2296 /* MGT_TOP_PMD_USR :: chip_intr_value :: pad_mod_abs_value [00:00] */ 2297 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_PAD_MOD_ABS_VALUE_MASK 0x0001 2298 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_PAD_MOD_ABS_VALUE_ALIGN 0 2299 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_PAD_MOD_ABS_VALUE_BITS 1 2300 #define MGT_TOP_PMD_USR_CHIP_INTR_VALUE_PAD_MOD_ABS_VALUE_SHIFT 0 2301 2302 2303 /**************************************************************************** 2304 * MGT_TOP_PMD_USR :: chip_intr_ctrl 2305 */ 2306 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: uncorrectable_sram_error_ctrl [15:15] */ 2307 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_UNCORRECTABLE_SRAM_ERROR_CTRL_MASK 0x8000 2308 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_UNCORRECTABLE_SRAM_ERROR_CTRL_ALIGN 0 2309 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_UNCORRECTABLE_SRAM_ERROR_CTRL_BITS 1 2310 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_UNCORRECTABLE_SRAM_ERROR_CTRL_SHIFT 15 2311 2312 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: correctable_sram_error_ctrl [14:14] */ 2313 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_CORRECTABLE_SRAM_ERROR_CTRL_MASK 0x4000 2314 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_CORRECTABLE_SRAM_ERROR_CTRL_ALIGN 0 2315 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_CORRECTABLE_SRAM_ERROR_CTRL_BITS 1 2316 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_CORRECTABLE_SRAM_ERROR_CTRL_SHIFT 14 2317 2318 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: sw_attention_ctrl [13:13] */ 2319 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SW_ATTENTION_CTRL_MASK 0x2000 2320 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SW_ATTENTION_CTRL_ALIGN 0 2321 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SW_ATTENTION_CTRL_BITS 1 2322 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SW_ATTENTION_CTRL_SHIFT 13 2323 2324 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: wdog_timer_expire_ctrl [12:12] */ 2325 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_WDOG_TIMER_EXPIRE_CTRL_MASK 0x1000 2326 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_WDOG_TIMER_EXPIRE_CTRL_ALIGN 0 2327 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_WDOG_TIMER_EXPIRE_CTRL_BITS 1 2328 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_WDOG_TIMER_EXPIRE_CTRL_SHIFT 12 2329 2330 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: ln_autoneg_completed_ctrl [11:11] */ 2331 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_AUTONEG_COMPLETED_CTRL_MASK 0x0800 2332 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_AUTONEG_COMPLETED_CTRL_ALIGN 0 2333 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_AUTONEG_COMPLETED_CTRL_BITS 1 2334 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_AUTONEG_COMPLETED_CTRL_SHIFT 11 2335 2336 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: sys_autoneg_completed_ctrl [10:10] */ 2337 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_AUTONEG_COMPLETED_CTRL_MASK 0x0400 2338 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_AUTONEG_COMPLETED_CTRL_ALIGN 0 2339 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_AUTONEG_COMPLETED_CTRL_BITS 1 2340 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_AUTONEG_COMPLETED_CTRL_SHIFT 10 2341 2342 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: message_out_status_ctrl [09:09] */ 2343 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_MESSAGE_OUT_STATUS_CTRL_MASK 0x0200 2344 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_MESSAGE_OUT_STATUS_CTRL_ALIGN 0 2345 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_MESSAGE_OUT_STATUS_CTRL_BITS 1 2346 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_MESSAGE_OUT_STATUS_CTRL_SHIFT 9 2347 2348 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: pad_gp_in_1_ctrl [08:08] */ 2349 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_GP_IN_1_CTRL_MASK 0x0100 2350 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_GP_IN_1_CTRL_ALIGN 0 2351 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_GP_IN_1_CTRL_BITS 1 2352 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_GP_IN_1_CTRL_SHIFT 8 2353 2354 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: pad_gp_in_0_ctrl [07:07] */ 2355 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_GP_IN_0_CTRL_MASK 0x0080 2356 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_GP_IN_0_CTRL_ALIGN 0 2357 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_GP_IN_0_CTRL_BITS 1 2358 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_GP_IN_0_CTRL_SHIFT 7 2359 2360 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: pad_extPCS_link_ctrl [06:06] */ 2361 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_EXTPCS_LINK_CTRL_MASK 0x0040 2362 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_EXTPCS_LINK_CTRL_ALIGN 0 2363 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_EXTPCS_LINK_CTRL_BITS 1 2364 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_PAD_EXTPCS_LINK_CTRL_SHIFT 6 2365 2366 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: sys_cmu_lkdt_ctrl [05:05] */ 2367 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_CMU_LKDT_CTRL_MASK 0x0020 2368 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_CMU_LKDT_CTRL_ALIGN 0 2369 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_CMU_LKDT_CTRL_BITS 1 2370 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_CMU_LKDT_CTRL_SHIFT 5 2371 2372 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: ln_cmu_lkdt_ctrl [04:04] */ 2373 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_CMU_LKDT_CTRL_MASK 0x0010 2374 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_CMU_LKDT_CTRL_ALIGN 0 2375 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_CMU_LKDT_CTRL_BITS 1 2376 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_CMU_LKDT_CTRL_SHIFT 4 2377 2378 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: ln_cdr_lkdt_ctrl [03:03] */ 2379 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_CDR_LKDT_CTRL_MASK 0x0008 2380 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_CDR_LKDT_CTRL_ALIGN 0 2381 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_CDR_LKDT_CTRL_BITS 1 2382 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_LN_CDR_LKDT_CTRL_SHIFT 3 2383 2384 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: opt_los_ctrl [02:02] */ 2385 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_OPT_LOS_CTRL_MASK 0x0004 2386 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_OPT_LOS_CTRL_ALIGN 0 2387 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_OPT_LOS_CTRL_BITS 1 2388 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_OPT_LOS_CTRL_SHIFT 2 2389 2390 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: sys_cdr_lkdt_ctrl [01:01] */ 2391 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_CDR_LKDT_CTRL_MASK 0x0002 2392 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_CDR_LKDT_CTRL_ALIGN 0 2393 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_CDR_LKDT_CTRL_BITS 1 2394 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_SYS_CDR_LKDT_CTRL_SHIFT 1 2395 2396 /* MGT_TOP_PMD_USR :: chip_intr_ctrl :: mod_abs_ctrl [00:00] */ 2397 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_MOD_ABS_CTRL_MASK 0x0001 2398 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_MOD_ABS_CTRL_ALIGN 0 2399 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_MOD_ABS_CTRL_BITS 1 2400 #define MGT_TOP_PMD_USR_CHIP_INTR_CTRL_MOD_ABS_CTRL_SHIFT 0 2401 2402 2403 /**************************************************************************** 2404 * MGT_TOP_PMD_USR :: ch_intr_ctrl 2405 */ 2406 /* MGT_TOP_PMD_USR :: ch_intr_ctrl :: reserved0 [15:14] */ 2407 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_RESERVED0_MASK 0xc000 2408 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_RESERVED0_ALIGN 0 2409 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_RESERVED0_BITS 2 2410 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_RESERVED0_SHIFT 14 2411 2412 /* MGT_TOP_PMD_USR :: ch_intr_ctrl :: edc_interrupt_pad_control [13:06] */ 2413 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_EDC_INTERRUPT_PAD_CONTROL_MASK 0x3fc0 2414 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_EDC_INTERRUPT_PAD_CONTROL_ALIGN 0 2415 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_EDC_INTERRUPT_PAD_CONTROL_BITS 8 2416 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_EDC_INTERRUPT_PAD_CONTROL_SHIFT 6 2417 2418 /* MGT_TOP_PMD_USR :: ch_intr_ctrl :: interrupt_clear_sel [05:05] */ 2419 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_INTERRUPT_CLEAR_SEL_MASK 0x0020 2420 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_INTERRUPT_CLEAR_SEL_ALIGN 0 2421 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_INTERRUPT_CLEAR_SEL_BITS 1 2422 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_INTERRUPT_CLEAR_SEL_SHIFT 5 2423 2424 /* MGT_TOP_PMD_USR :: ch_intr_ctrl :: ch_intr_en [04:04] */ 2425 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_CH_INTR_EN_MASK 0x0010 2426 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_CH_INTR_EN_ALIGN 0 2427 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_CH_INTR_EN_BITS 1 2428 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_CH_INTR_EN_SHIFT 4 2429 2430 /* MGT_TOP_PMD_USR :: ch_intr_ctrl :: chip_intr_ctr [03:00] */ 2431 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_CHIP_INTR_CTR_MASK 0x000f 2432 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_CHIP_INTR_CTR_ALIGN 0 2433 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_CHIP_INTR_CTR_BITS 4 2434 #define MGT_TOP_PMD_USR_CH_INTR_CTRL_CHIP_INTR_CTR_SHIFT 0 2435 2436 2437 /**************************************************************************** 2438 * MGT_TOP_PMD_USR :: otp_ovr_rev_id_register 2439 */ 2440 /* MGT_TOP_PMD_USR :: otp_ovr_rev_id_register :: otp_revid_override_ctl [15:15] */ 2441 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_OTP_REVID_OVERRIDE_CTL_MASK 0x8000 2442 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_OTP_REVID_OVERRIDE_CTL_ALIGN 0 2443 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_OTP_REVID_OVERRIDE_CTL_BITS 1 2444 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_OTP_REVID_OVERRIDE_CTL_SHIFT 15 2445 2446 /* MGT_TOP_PMD_USR :: otp_ovr_rev_id_register :: reserved0 [14:08] */ 2447 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_RESERVED0_MASK 0x7f00 2448 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_RESERVED0_ALIGN 0 2449 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_RESERVED0_BITS 7 2450 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_RESERVED0_SHIFT 8 2451 2452 /* MGT_TOP_PMD_USR :: otp_ovr_rev_id_register :: reg_chip_rev_id [07:00] */ 2453 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_REG_CHIP_REV_ID_MASK 0x00ff 2454 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_REG_CHIP_REV_ID_ALIGN 0 2455 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_REG_CHIP_REV_ID_BITS 8 2456 #define MGT_TOP_PMD_USR_OTP_OVR_REV_ID_REGISTER_REG_CHIP_REV_ID_SHIFT 0 2457 2458 2459 /**************************************************************************** 2460 * MGT_TOP_PMD_USR :: otp_ovr_chp_id0_register 2461 */ 2462 /* MGT_TOP_PMD_USR :: otp_ovr_chp_id0_register :: otp_ovr_chp_id0 [15:00] */ 2463 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID0_REGISTER_OTP_OVR_CHP_ID0_MASK 0xffff 2464 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID0_REGISTER_OTP_OVR_CHP_ID0_ALIGN 0 2465 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID0_REGISTER_OTP_OVR_CHP_ID0_BITS 16 2466 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID0_REGISTER_OTP_OVR_CHP_ID0_SHIFT 0 2467 2468 2469 /**************************************************************************** 2470 * MGT_TOP_PMD_USR :: otp_ovr_chp_id1_register 2471 */ 2472 /* MGT_TOP_PMD_USR :: otp_ovr_chp_id1_register :: otp_chipid_override_ctl [15:15] */ 2473 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_OTP_CHIPID_OVERRIDE_CTL_MASK 0x8000 2474 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_OTP_CHIPID_OVERRIDE_CTL_ALIGN 0 2475 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_OTP_CHIPID_OVERRIDE_CTL_BITS 1 2476 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_OTP_CHIPID_OVERRIDE_CTL_SHIFT 15 2477 2478 /* MGT_TOP_PMD_USR :: otp_ovr_chp_id1_register :: reserved0 [14:04] */ 2479 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_RESERVED0_MASK 0x7ff0 2480 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_RESERVED0_ALIGN 0 2481 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_RESERVED0_BITS 11 2482 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_RESERVED0_SHIFT 4 2483 2484 /* MGT_TOP_PMD_USR :: otp_ovr_chp_id1_register :: otp_ovr_chp_id1 [03:00] */ 2485 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_OTP_OVR_CHP_ID1_MASK 0x000f 2486 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_OTP_OVR_CHP_ID1_ALIGN 0 2487 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_OTP_OVR_CHP_ID1_BITS 4 2488 #define MGT_TOP_PMD_USR_OTP_OVR_CHP_ID1_REGISTER_OTP_OVR_CHP_ID1_SHIFT 0 2489 2490 2491 /**************************************************************************** 2492 * MGT_TOP_PMD_USR :: otp_rdy_cnt_stat_reg 2493 */ 2494 /* MGT_TOP_PMD_USR :: otp_rdy_cnt_stat_reg :: reserved0 [15:13] */ 2495 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_RESERVED0_MASK 0xe000 2496 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_RESERVED0_ALIGN 0 2497 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_RESERVED0_BITS 3 2498 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_RESERVED0_SHIFT 13 2499 2500 /* MGT_TOP_PMD_USR :: otp_rdy_cnt_stat_reg :: otp_rdy_cnt_status [12:08] */ 2501 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_RDY_CNT_STATUS_MASK 0x1f00 2502 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_RDY_CNT_STATUS_ALIGN 0 2503 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_RDY_CNT_STATUS_BITS 5 2504 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_RDY_CNT_STATUS_SHIFT 8 2505 2506 /* MGT_TOP_PMD_USR :: otp_rdy_cnt_stat_reg :: reserved1 [07:02] */ 2507 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_RESERVED1_MASK 0x00fc 2508 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_RESERVED1_ALIGN 0 2509 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_RESERVED1_BITS 6 2510 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_RESERVED1_SHIFT 2 2511 2512 /* MGT_TOP_PMD_USR :: otp_rdy_cnt_stat_reg :: otp_ready_sample_val [01:01] */ 2513 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_READY_SAMPLE_VAL_MASK 0x0002 2514 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_READY_SAMPLE_VAL_ALIGN 0 2515 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_READY_SAMPLE_VAL_BITS 1 2516 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_READY_SAMPLE_VAL_SHIFT 1 2517 2518 /* MGT_TOP_PMD_USR :: otp_rdy_cnt_stat_reg :: otp_ready_raw_val [00:00] */ 2519 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_READY_RAW_VAL_MASK 0x0001 2520 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_READY_RAW_VAL_ALIGN 0 2521 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_READY_RAW_VAL_BITS 1 2522 #define MGT_TOP_PMD_USR_OTP_RDY_CNT_STAT_REG_OTP_READY_RAW_VAL_SHIFT 0 2523 2524 2525 /**************************************************************************** 2526 * MGT_TOP_PMD_USR :: otp_ovr_device_id_0 2527 */ 2528 /* MGT_TOP_PMD_USR :: otp_ovr_device_id_0 :: otp_ovr_device_id_0 [15:00] */ 2529 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_OTP_OVR_DEVICE_ID_0_MASK 0xffff 2530 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_OTP_OVR_DEVICE_ID_0_ALIGN 0 2531 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_OTP_OVR_DEVICE_ID_0_BITS 16 2532 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_OTP_OVR_DEVICE_ID_0_SHIFT 0 2533 2534 2535 /**************************************************************************** 2536 * MGT_TOP_PMD_USR :: otp_ovr_device_id_1 2537 */ 2538 /* MGT_TOP_PMD_USR :: otp_ovr_device_id_1 :: otp_ovr_device_id_1 [15:00] */ 2539 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_1_OTP_OVR_DEVICE_ID_1_MASK 0xffff 2540 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_1_OTP_OVR_DEVICE_ID_1_ALIGN 0 2541 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_1_OTP_OVR_DEVICE_ID_1_BITS 16 2542 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_1_OTP_OVR_DEVICE_ID_1_SHIFT 0 2543 2544 2545 /**************************************************************************** 2546 * MGT_TOP_PMD_USR :: otp_ovr_device_id_0_1_cntl 2547 */ 2548 /* MGT_TOP_PMD_USR :: otp_ovr_device_id_0_1_cntl :: reserved0 [15:02] */ 2549 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_RESERVED0_MASK 0xfffc 2550 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_RESERVED0_ALIGN 0 2551 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_RESERVED0_BITS 14 2552 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_RESERVED0_SHIFT 2 2553 2554 /* MGT_TOP_PMD_USR :: otp_ovr_device_id_0_1_cntl :: otp_ovr_device_id_1_cntl [01:01] */ 2555 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_1_CNTL_MASK 0x0002 2556 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_1_CNTL_ALIGN 0 2557 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_1_CNTL_BITS 1 2558 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_1_CNTL_SHIFT 1 2559 2560 /* MGT_TOP_PMD_USR :: otp_ovr_device_id_0_1_cntl :: otp_ovr_device_id_0_cntl [00:00] */ 2561 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_0_CNTL_MASK 0x0001 2562 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_0_CNTL_ALIGN 0 2563 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_0_CNTL_BITS 1 2564 #define MGT_TOP_PMD_USR_OTP_OVR_DEVICE_ID_0_1_CNTL_OTP_OVR_DEVICE_ID_0_CNTL_SHIFT 0 2565 2566 2567 /**************************************************************************** 2568 * MGT_TOP_PMD_USR :: die_id 2569 */ 2570 /* MGT_TOP_PMD_USR :: die_id :: reserved0 [15:08] */ 2571 #define MGT_TOP_PMD_USR_DIE_ID_RESERVED0_MASK 0xff00 2572 #define MGT_TOP_PMD_USR_DIE_ID_RESERVED0_ALIGN 0 2573 #define MGT_TOP_PMD_USR_DIE_ID_RESERVED0_BITS 8 2574 #define MGT_TOP_PMD_USR_DIE_ID_RESERVED0_SHIFT 8 2575 2576 /* MGT_TOP_PMD_USR :: die_id :: die_id [07:00] */ 2577 #define MGT_TOP_PMD_USR_DIE_ID_DIE_ID_MASK 0x00ff 2578 #define MGT_TOP_PMD_USR_DIE_ID_DIE_ID_ALIGN 0 2579 #define MGT_TOP_PMD_USR_DIE_ID_DIE_ID_BITS 8 2580 #define MGT_TOP_PMD_USR_DIE_ID_DIE_ID_SHIFT 0 2581 2582 2583 /**************************************************************************** 2584 * MGT_TOP_PMD_USR :: optical_configuration 2585 */ 2586 /* MGT_TOP_PMD_USR :: optical_configuration :: optxenb_lvl [15:15] */ 2587 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTXENB_LVL_MASK 0x8000 2588 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTXENB_LVL_ALIGN 0 2589 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTXENB_LVL_BITS 1 2590 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTXENB_LVL_SHIFT 15 2591 2592 /* MGT_TOP_PMD_USR :: optical_configuration :: man_oplosb_en [14:14] */ 2593 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_OPLOSB_EN_MASK 0x4000 2594 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_OPLOSB_EN_ALIGN 0 2595 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_OPLOSB_EN_BITS 1 2596 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_OPLOSB_EN_SHIFT 14 2597 2598 /* MGT_TOP_PMD_USR :: optical_configuration :: man_extPCS_Link [13:13] */ 2599 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_EXTPCS_LINK_MASK 0x2000 2600 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_EXTPCS_LINK_ALIGN 0 2601 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_EXTPCS_LINK_BITS 1 2602 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_EXTPCS_LINK_SHIFT 13 2603 2604 /* MGT_TOP_PMD_USR :: optical_configuration :: man_txon_en [12:12] */ 2605 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_TXON_EN_MASK 0x1000 2606 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_TXON_EN_ALIGN 0 2607 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_TXON_EN_BITS 1 2608 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MAN_TXON_EN_SHIFT 12 2609 2610 /* MGT_TOP_PMD_USR :: optical_configuration :: optrxlos_lvl [11:11] */ 2611 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTRXLOS_LVL_MASK 0x0800 2612 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTRXLOS_LVL_ALIGN 0 2613 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTRXLOS_LVL_BITS 1 2614 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTRXLOS_LVL_SHIFT 11 2615 2616 /* MGT_TOP_PMD_USR :: optical_configuration :: optxon_lvl [10:10] */ 2617 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTXON_LVL_MASK 0x0400 2618 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTXON_LVL_ALIGN 0 2619 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTXON_LVL_BITS 1 2620 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_OPTXON_LVL_SHIFT 10 2621 2622 /* MGT_TOP_PMD_USR :: optical_configuration :: Enable_extPCS_Link_for_Line [09:09] */ 2623 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_LINE_MASK 0x0200 2624 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_LINE_ALIGN 0 2625 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_LINE_BITS 1 2626 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_LINE_SHIFT 9 2627 2628 /* MGT_TOP_PMD_USR :: optical_configuration :: Enable_extPCS_Link_for_Sys [08:08] */ 2629 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_SYS_MASK 0x0100 2630 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_SYS_ALIGN 0 2631 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_SYS_BITS 1 2632 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_ENABLE_EXTPCS_LINK_FOR_SYS_SHIFT 8 2633 2634 /* MGT_TOP_PMD_USR :: optical_configuration :: txenb [07:07] */ 2635 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXENB_MASK 0x0080 2636 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXENB_ALIGN 0 2637 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXENB_BITS 1 2638 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXENB_SHIFT 7 2639 2640 /* MGT_TOP_PMD_USR :: optical_configuration :: md_opt_losb [06:06] */ 2641 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MD_OPT_LOSB_MASK 0x0040 2642 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MD_OPT_LOSB_ALIGN 0 2643 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MD_OPT_LOSB_BITS 1 2644 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_MD_OPT_LOSB_SHIFT 6 2645 2646 /* MGT_TOP_PMD_USR :: optical_configuration :: extPCS_Link [05:05] */ 2647 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EXTPCS_LINK_MASK 0x0020 2648 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EXTPCS_LINK_ALIGN 0 2649 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EXTPCS_LINK_BITS 1 2650 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EXTPCS_LINK_SHIFT 5 2651 2652 /* MGT_TOP_PMD_USR :: optical_configuration :: txofft [04:04] */ 2653 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXOFFT_MASK 0x0010 2654 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXOFFT_ALIGN 0 2655 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXOFFT_BITS 1 2656 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXOFFT_SHIFT 4 2657 2658 /* MGT_TOP_PMD_USR :: optical_configuration :: txenb_oen [03:03] */ 2659 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXENB_OEN_MASK 0x0008 2660 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXENB_OEN_ALIGN 0 2661 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXENB_OEN_BITS 1 2662 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_TXENB_OEN_SHIFT 3 2663 2664 /* MGT_TOP_PMD_USR :: optical_configuration :: reserved_txon_oen [02:02] */ 2665 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_RESERVED_TXON_OEN_MASK 0x0004 2666 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_RESERVED_TXON_OEN_ALIGN 0 2667 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_RESERVED_TXON_OEN_BITS 1 2668 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_RESERVED_TXON_OEN_SHIFT 2 2669 2670 /* MGT_TOP_PMD_USR :: optical_configuration :: en_txenb_int [01:01] */ 2671 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EN_TXENB_INT_MASK 0x0002 2672 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EN_TXENB_INT_ALIGN 0 2673 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EN_TXENB_INT_BITS 1 2674 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EN_TXENB_INT_SHIFT 1 2675 2676 /* MGT_TOP_PMD_USR :: optical_configuration :: en_txonb_int [00:00] */ 2677 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EN_TXONB_INT_MASK 0x0001 2678 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EN_TXONB_INT_ALIGN 0 2679 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EN_TXONB_INT_BITS 1 2680 #define MGT_TOP_PMD_USR_OPTICAL_CONFIGURATION_EN_TXONB_INT_SHIFT 0 2681 2682 2683 /**************************************************************************** 2684 * MGT_TOP_PMD_USR :: broadcast_ctrl 2685 */ 2686 /* MGT_TOP_PMD_USR :: broadcast_ctrl :: reserved0 [15:07] */ 2687 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_RESERVED0_MASK 0xff80 2688 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_RESERVED0_ALIGN 0 2689 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_RESERVED0_BITS 9 2690 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_RESERVED0_SHIFT 7 2691 2692 /* MGT_TOP_PMD_USR :: broadcast_ctrl :: multiport_address [06:02] */ 2693 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_MULTIPORT_ADDRESS_MASK 0x007c 2694 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_MULTIPORT_ADDRESS_ALIGN 0 2695 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_MULTIPORT_ADDRESS_BITS 5 2696 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_MULTIPORT_ADDRESS_SHIFT 2 2697 2698 /* MGT_TOP_PMD_USR :: broadcast_ctrl :: multiport_addressing_enable [01:01] */ 2699 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_MULTIPORT_ADDRESSING_ENABLE_MASK 0x0002 2700 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_MULTIPORT_ADDRESSING_ENABLE_ALIGN 0 2701 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_MULTIPORT_ADDRESSING_ENABLE_BITS 1 2702 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_MULTIPORT_ADDRESSING_ENABLE_SHIFT 1 2703 2704 /* MGT_TOP_PMD_USR :: broadcast_ctrl :: broadcast_mode_enable [00:00] */ 2705 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_BROADCAST_MODE_ENABLE_MASK 0x0001 2706 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_BROADCAST_MODE_ENABLE_ALIGN 0 2707 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_BROADCAST_MODE_ENABLE_BITS 1 2708 #define MGT_TOP_PMD_USR_BROADCAST_CTRL_BROADCAST_MODE_ENABLE_SHIFT 0 2709 2710 2711 /**************************************************************************** 2712 * MGT_TOP_PMD_USR :: xpmd_regs_sel 2713 */ 2714 /* MGT_TOP_PMD_USR :: xpmd_regs_sel :: reserved0 [15:01] */ 2715 #define MGT_TOP_PMD_USR_XPMD_REGS_SEL_RESERVED0_MASK 0xfffe 2716 #define MGT_TOP_PMD_USR_XPMD_REGS_SEL_RESERVED0_ALIGN 0 2717 #define MGT_TOP_PMD_USR_XPMD_REGS_SEL_RESERVED0_BITS 15 2718 #define MGT_TOP_PMD_USR_XPMD_REGS_SEL_RESERVED0_SHIFT 1 2719 2720 /* MGT_TOP_PMD_USR :: xpmd_regs_sel :: select_sys_registers [00:00] */ 2721 #define MGT_TOP_PMD_USR_XPMD_REGS_SEL_SELECT_SYS_REGISTERS_MASK 0x0001 2722 #define MGT_TOP_PMD_USR_XPMD_REGS_SEL_SELECT_SYS_REGISTERS_ALIGN 0 2723 #define MGT_TOP_PMD_USR_XPMD_REGS_SEL_SELECT_SYS_REGISTERS_BITS 1 2724 #define MGT_TOP_PMD_USR_XPMD_REGS_SEL_SELECT_SYS_REGISTERS_SHIFT 0 2725 2726 2727 /**************************************************************************** 2728 * merlin_gallardo_mgt_top_blk_MGT_TOP_CMN_CTLR 2729 */ 2730 /**************************************************************************** 2731 * MGT_TOP_CMN_CTLR :: regualtor_ctrl 2732 */ 2733 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: reserved0 [15:15] */ 2734 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_RESERVED0_MASK 0x8000 2735 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_RESERVED0_ALIGN 0 2736 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_RESERVED0_BITS 1 2737 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_RESERVED0_SHIFT 15 2738 2739 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: vregcntl_en [14:14] */ 2740 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCNTL_EN_MASK 0x4000 2741 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCNTL_EN_ALIGN 0 2742 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCNTL_EN_BITS 1 2743 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCNTL_EN_SHIFT 14 2744 2745 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: pwrdn [13:13] */ 2746 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_PWRDN_MASK 0x2000 2747 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_PWRDN_ALIGN 0 2748 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_PWRDN_BITS 1 2749 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_PWRDN_SHIFT 13 2750 2751 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: vregctl_100kohm [12:12] */ 2752 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_100KOHM_MASK 0x1000 2753 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_100KOHM_ALIGN 0 2754 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_100KOHM_BITS 1 2755 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_100KOHM_SHIFT 12 2756 2757 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: vregctl_Rpole_tuning [11:10] */ 2758 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_RPOLE_TUNING_MASK 0x0c00 2759 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_RPOLE_TUNING_ALIGN 0 2760 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_RPOLE_TUNING_BITS 2 2761 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_RPOLE_TUNING_SHIFT 10 2762 2763 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: vregctl_output_voltage_ctrl [09:09] */ 2764 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_OUTPUT_VOLTAGE_CTRL_MASK 0x0200 2765 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_OUTPUT_VOLTAGE_CTRL_ALIGN 0 2766 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_OUTPUT_VOLTAGE_CTRL_BITS 1 2767 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_OUTPUT_VOLTAGE_CTRL_SHIFT 9 2768 2769 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: reserved1 [08:08] */ 2770 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_RESERVED1_MASK 0x0100 2771 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_RESERVED1_ALIGN 0 2772 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_RESERVED1_BITS 1 2773 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_RESERVED1_SHIFT 8 2774 2775 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: vregctl_Ovolt_tuning [07:04] */ 2776 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_OVOLT_TUNING_MASK 0x00f0 2777 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_OVOLT_TUNING_ALIGN 0 2778 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_OVOLT_TUNING_BITS 4 2779 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_OVOLT_TUNING_SHIFT 4 2780 2781 /* MGT_TOP_CMN_CTLR :: regualtor_ctrl :: vregctl_Bg_tuning [03:00] */ 2782 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_BG_TUNING_MASK 0x000f 2783 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_BG_TUNING_ALIGN 0 2784 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_BG_TUNING_BITS 4 2785 #define MGT_TOP_CMN_CTLR_REGUALTOR_CTRL_VREGCTL_BG_TUNING_SHIFT 0 2786 2787 2788 /**************************************************************************** 2789 * MGT_TOP_CMN_CTLR :: gen_ctrl 2790 */ 2791 /* MGT_TOP_CMN_CTLR :: gen_ctrl :: m51_i2c_wr_ctrl [15:12] */ 2792 #define MGT_TOP_CMN_CTLR_GEN_CTRL_M51_I2C_WR_CTRL_MASK 0xf000 2793 #define MGT_TOP_CMN_CTLR_GEN_CTRL_M51_I2C_WR_CTRL_ALIGN 0 2794 #define MGT_TOP_CMN_CTLR_GEN_CTRL_M51_I2C_WR_CTRL_BITS 4 2795 #define MGT_TOP_CMN_CTLR_GEN_CTRL_M51_I2C_WR_CTRL_SHIFT 12 2796 2797 /* MGT_TOP_CMN_CTLR :: gen_ctrl :: reserved0 [11:09] */ 2798 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED0_MASK 0x0e00 2799 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED0_ALIGN 0 2800 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED0_BITS 3 2801 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED0_SHIFT 9 2802 2803 /* MGT_TOP_CMN_CTLR :: gen_ctrl :: uc_refclk_sel [08:08] */ 2804 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UC_REFCLK_SEL_MASK 0x0100 2805 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UC_REFCLK_SEL_ALIGN 0 2806 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UC_REFCLK_SEL_BITS 1 2807 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UC_REFCLK_SEL_SHIFT 8 2808 2809 /* MGT_TOP_CMN_CTLR :: gen_ctrl :: reserved1 [07:07] */ 2810 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED1_MASK 0x0080 2811 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED1_ALIGN 0 2812 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED1_BITS 1 2813 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED1_SHIFT 7 2814 2815 /* MGT_TOP_CMN_CTLR :: gen_ctrl :: ucclksel_speed_sel [06:06] */ 2816 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UCCLKSEL_SPEED_SEL_MASK 0x0040 2817 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UCCLKSEL_SPEED_SEL_ALIGN 0 2818 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UCCLKSEL_SPEED_SEL_BITS 1 2819 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UCCLKSEL_SPEED_SEL_SHIFT 6 2820 2821 /* MGT_TOP_CMN_CTLR :: gen_ctrl :: reserved2 [05:03] */ 2822 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED2_MASK 0x0038 2823 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED2_ALIGN 0 2824 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED2_BITS 3 2825 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED2_SHIFT 3 2826 2827 /* MGT_TOP_CMN_CTLR :: gen_ctrl :: ucrst [02:02] */ 2828 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UCRST_MASK 0x0004 2829 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UCRST_ALIGN 0 2830 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UCRST_BITS 1 2831 #define MGT_TOP_CMN_CTLR_GEN_CTRL_UCRST_SHIFT 2 2832 2833 /* MGT_TOP_CMN_CTLR :: gen_ctrl :: reserved3 [01:00] */ 2834 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED3_MASK 0x0003 2835 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED3_ALIGN 0 2836 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED3_BITS 2 2837 #define MGT_TOP_CMN_CTLR_GEN_CTRL_RESERVED3_SHIFT 0 2838 2839 2840 /**************************************************************************** 2841 * MGT_TOP_CMN_CTLR :: ram_lwpr_ctrl 2842 */ 2843 /* MGT_TOP_CMN_CTLR :: ram_lwpr_ctrl :: RAM_LWPR_CTRL [15:08] */ 2844 #define MGT_TOP_CMN_CTLR_RAM_LWPR_CTRL_RAM_LWPR_CTRL_MASK 0xff00 2845 #define MGT_TOP_CMN_CTLR_RAM_LWPR_CTRL_RAM_LWPR_CTRL_ALIGN 0 2846 #define MGT_TOP_CMN_CTLR_RAM_LWPR_CTRL_RAM_LWPR_CTRL_BITS 8 2847 #define MGT_TOP_CMN_CTLR_RAM_LWPR_CTRL_RAM_LWPR_CTRL_SHIFT 8 2848 2849 /* MGT_TOP_CMN_CTLR :: ram_lwpr_ctrl :: reserved0 [07:00] */ 2850 #define MGT_TOP_CMN_CTLR_RAM_LWPR_CTRL_RESERVED0_MASK 0x00ff 2851 #define MGT_TOP_CMN_CTLR_RAM_LWPR_CTRL_RESERVED0_ALIGN 0 2852 #define MGT_TOP_CMN_CTLR_RAM_LWPR_CTRL_RESERVED0_BITS 8 2853 #define MGT_TOP_CMN_CTLR_RAM_LWPR_CTRL_RESERVED0_SHIFT 0 2854 2855 2856 /**************************************************************************** 2857 * MGT_TOP_CMN_CTLR :: msg_in 2858 */ 2859 /* MGT_TOP_CMN_CTLR :: msg_in :: message_in [15:00] */ 2860 #define MGT_TOP_CMN_CTLR_MSG_IN_MESSAGE_IN_MASK 0xffff 2861 #define MGT_TOP_CMN_CTLR_MSG_IN_MESSAGE_IN_ALIGN 0 2862 #define MGT_TOP_CMN_CTLR_MSG_IN_MESSAGE_IN_BITS 16 2863 #define MGT_TOP_CMN_CTLR_MSG_IN_MESSAGE_IN_SHIFT 0 2864 2865 2866 /**************************************************************************** 2867 * MGT_TOP_CMN_CTLR :: msg_out 2868 */ 2869 /* MGT_TOP_CMN_CTLR :: msg_out :: message_out [15:00] */ 2870 #define MGT_TOP_CMN_CTLR_MSG_OUT_MESSAGE_OUT_MASK 0xffff 2871 #define MGT_TOP_CMN_CTLR_MSG_OUT_MESSAGE_OUT_ALIGN 0 2872 #define MGT_TOP_CMN_CTLR_MSG_OUT_MESSAGE_OUT_BITS 16 2873 #define MGT_TOP_CMN_CTLR_MSG_OUT_MESSAGE_OUT_SHIFT 0 2874 2875 2876 /**************************************************************************** 2877 * MGT_TOP_CMN_CTLR :: errored_sram_address 2878 */ 2879 /* MGT_TOP_CMN_CTLR :: errored_sram_address :: current_sram_address [15:00] */ 2880 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_ADDRESS_CURRENT_SRAM_ADDRESS_MASK 0xffff 2881 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_ADDRESS_CURRENT_SRAM_ADDRESS_ALIGN 0 2882 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_ADDRESS_CURRENT_SRAM_ADDRESS_BITS 16 2883 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_ADDRESS_CURRENT_SRAM_ADDRESS_SHIFT 0 2884 2885 2886 /**************************************************************************** 2887 * MGT_TOP_CMN_CTLR :: errored_sram_data 2888 */ 2889 /* MGT_TOP_CMN_CTLR :: errored_sram_data :: Uncorrectable_Low_Mem_Error [15:15] */ 2890 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_UNCORRECTABLE_LOW_MEM_ERROR_MASK 0x8000 2891 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_UNCORRECTABLE_LOW_MEM_ERROR_ALIGN 0 2892 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_UNCORRECTABLE_LOW_MEM_ERROR_BITS 1 2893 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_UNCORRECTABLE_LOW_MEM_ERROR_SHIFT 15 2894 2895 /* MGT_TOP_CMN_CTLR :: errored_sram_data :: Low_Mem_Error_Corrected [14:14] */ 2896 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_LOW_MEM_ERROR_CORRECTED_MASK 0x4000 2897 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_LOW_MEM_ERROR_CORRECTED_ALIGN 0 2898 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_LOW_MEM_ERROR_CORRECTED_BITS 1 2899 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_LOW_MEM_ERROR_CORRECTED_SHIFT 14 2900 2901 /* MGT_TOP_CMN_CTLR :: errored_sram_data :: Uncorrectable_High_Mem_Error [13:13] */ 2902 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_UNCORRECTABLE_HIGH_MEM_ERROR_MASK 0x2000 2903 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_UNCORRECTABLE_HIGH_MEM_ERROR_ALIGN 0 2904 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_UNCORRECTABLE_HIGH_MEM_ERROR_BITS 1 2905 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_UNCORRECTABLE_HIGH_MEM_ERROR_SHIFT 13 2906 2907 /* MGT_TOP_CMN_CTLR :: errored_sram_data :: High_Mem_Error_Corrected [12:12] */ 2908 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_HIGH_MEM_ERROR_CORRECTED_MASK 0x1000 2909 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_HIGH_MEM_ERROR_CORRECTED_ALIGN 0 2910 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_HIGH_MEM_ERROR_CORRECTED_BITS 1 2911 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_HIGH_MEM_ERROR_CORRECTED_SHIFT 12 2912 2913 /* MGT_TOP_CMN_CTLR :: errored_sram_data :: reserved0 [11:10] */ 2914 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_RESERVED0_MASK 0x0c00 2915 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_RESERVED0_ALIGN 0 2916 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_RESERVED0_BITS 2 2917 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_RESERVED0_SHIFT 10 2918 2919 /* MGT_TOP_CMN_CTLR :: errored_sram_data :: Mem_Error_Corrected_8051_interrupt_mask [09:09] */ 2920 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_MEM_ERROR_CORRECTED_8051_INTERRUPT_MASK_MASK 0x0200 2921 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_MEM_ERROR_CORRECTED_8051_INTERRUPT_MASK_ALIGN 0 2922 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_MEM_ERROR_CORRECTED_8051_INTERRUPT_MASK_BITS 1 2923 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_MEM_ERROR_CORRECTED_8051_INTERRUPT_MASK_SHIFT 9 2924 2925 /* MGT_TOP_CMN_CTLR :: errored_sram_data :: Mem_Error_Uncorrected_8051_interrupt_mask [08:08] */ 2926 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_MEM_ERROR_UNCORRECTED_8051_INTERRUPT_MASK_MASK 0x0100 2927 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_MEM_ERROR_UNCORRECTED_8051_INTERRUPT_MASK_ALIGN 0 2928 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_MEM_ERROR_UNCORRECTED_8051_INTERRUPT_MASK_BITS 1 2929 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_MEM_ERROR_UNCORRECTED_8051_INTERRUPT_MASK_SHIFT 8 2930 2931 /* MGT_TOP_CMN_CTLR :: errored_sram_data :: current_sram_data [07:00] */ 2932 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_CURRENT_SRAM_DATA_MASK 0x00ff 2933 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_CURRENT_SRAM_DATA_ALIGN 0 2934 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_CURRENT_SRAM_DATA_BITS 8 2935 #define MGT_TOP_CMN_CTLR_ERRORED_SRAM_DATA_CURRENT_SRAM_DATA_SHIFT 0 2936 2937 2938 /**************************************************************************** 2939 * MGT_TOP_CMN_CTLR :: gp_reg_0 2940 */ 2941 /* MGT_TOP_CMN_CTLR :: gp_reg_0 :: Enable_line_3_0 [15:12] */ 2942 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_LINE_3_0_MASK 0xf000 2943 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_LINE_3_0_ALIGN 0 2944 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_LINE_3_0_BITS 4 2945 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_LINE_3_0_SHIFT 12 2946 2947 /* MGT_TOP_CMN_CTLR :: gp_reg_0 :: Enable_system_3_0 [11:08] */ 2948 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_SYSTEM_3_0_MASK 0x0f00 2949 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_SYSTEM_3_0_ALIGN 0 2950 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_SYSTEM_3_0_BITS 4 2951 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_SYSTEM_3_0_SHIFT 8 2952 2953 /* MGT_TOP_CMN_CTLR :: gp_reg_0 :: Disable_Tx_Squelching [07:07] */ 2954 #define MGT_TOP_CMN_CTLR_GP_REG_0_DISABLE_TX_SQUELCHING_MASK 0x0080 2955 #define MGT_TOP_CMN_CTLR_GP_REG_0_DISABLE_TX_SQUELCHING_ALIGN 0 2956 #define MGT_TOP_CMN_CTLR_GP_REG_0_DISABLE_TX_SQUELCHING_BITS 1 2957 #define MGT_TOP_CMN_CTLR_GP_REG_0_DISABLE_TX_SQUELCHING_SHIFT 7 2958 2959 /* MGT_TOP_CMN_CTLR :: gp_reg_0 :: gpreg0_data_6_3 [06:03] */ 2960 #define MGT_TOP_CMN_CTLR_GP_REG_0_GPREG0_DATA_6_3_MASK 0x0078 2961 #define MGT_TOP_CMN_CTLR_GP_REG_0_GPREG0_DATA_6_3_ALIGN 0 2962 #define MGT_TOP_CMN_CTLR_GP_REG_0_GPREG0_DATA_6_3_BITS 4 2963 #define MGT_TOP_CMN_CTLR_GP_REG_0_GPREG0_DATA_6_3_SHIFT 3 2964 2965 /* MGT_TOP_CMN_CTLR :: gp_reg_0 :: i2c_operation_in_progress [02:02] */ 2966 #define MGT_TOP_CMN_CTLR_GP_REG_0_I2C_OPERATION_IN_PROGRESS_MASK 0x0004 2967 #define MGT_TOP_CMN_CTLR_GP_REG_0_I2C_OPERATION_IN_PROGRESS_ALIGN 0 2968 #define MGT_TOP_CMN_CTLR_GP_REG_0_I2C_OPERATION_IN_PROGRESS_BITS 1 2969 #define MGT_TOP_CMN_CTLR_GP_REG_0_I2C_OPERATION_IN_PROGRESS_SHIFT 2 2970 2971 /* MGT_TOP_CMN_CTLR :: gp_reg_0 :: Enable_QSFP_Mod_detect [01:01] */ 2972 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_QSFP_MOD_DETECT_MASK 0x0002 2973 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_QSFP_MOD_DETECT_ALIGN 0 2974 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_QSFP_MOD_DETECT_BITS 1 2975 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_QSFP_MOD_DETECT_SHIFT 1 2976 2977 /* MGT_TOP_CMN_CTLR :: gp_reg_0 :: Enable_SFP_Mod_detect [00:00] */ 2978 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_SFP_MOD_DETECT_MASK 0x0001 2979 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_SFP_MOD_DETECT_ALIGN 0 2980 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_SFP_MOD_DETECT_BITS 1 2981 #define MGT_TOP_CMN_CTLR_GP_REG_0_ENABLE_SFP_MOD_DETECT_SHIFT 0 2982 2983 2984 /**************************************************************************** 2985 * MGT_TOP_CMN_CTLR :: gp_reg_1 2986 */ 2987 /* MGT_TOP_CMN_CTLR :: gp_reg_1 :: gpreg1_data [15:00] */ 2988 #define MGT_TOP_CMN_CTLR_GP_REG_1_GPREG1_DATA_MASK 0xffff 2989 #define MGT_TOP_CMN_CTLR_GP_REG_1_GPREG1_DATA_ALIGN 0 2990 #define MGT_TOP_CMN_CTLR_GP_REG_1_GPREG1_DATA_BITS 16 2991 #define MGT_TOP_CMN_CTLR_GP_REG_1_GPREG1_DATA_SHIFT 0 2992 2993 2994 /**************************************************************************** 2995 * MGT_TOP_CMN_CTLR :: gp_reg_2 2996 */ 2997 /* MGT_TOP_CMN_CTLR :: gp_reg_2 :: gpreg2_data [15:00] */ 2998 #define MGT_TOP_CMN_CTLR_GP_REG_2_GPREG2_DATA_MASK 0xffff 2999 #define MGT_TOP_CMN_CTLR_GP_REG_2_GPREG2_DATA_ALIGN 0 3000 #define MGT_TOP_CMN_CTLR_GP_REG_2_GPREG2_DATA_BITS 16 3001 #define MGT_TOP_CMN_CTLR_GP_REG_2_GPREG2_DATA_SHIFT 0 3002 3003 3004 /**************************************************************************** 3005 * MGT_TOP_CMN_CTLR :: gp_reg_3 3006 */ 3007 /* MGT_TOP_CMN_CTLR :: gp_reg_3 :: gpreg3_data [15:00] */ 3008 #define MGT_TOP_CMN_CTLR_GP_REG_3_GPREG3_DATA_MASK 0xffff 3009 #define MGT_TOP_CMN_CTLR_GP_REG_3_GPREG3_DATA_ALIGN 0 3010 #define MGT_TOP_CMN_CTLR_GP_REG_3_GPREG3_DATA_BITS 16 3011 #define MGT_TOP_CMN_CTLR_GP_REG_3_GPREG3_DATA_SHIFT 0 3012 3013 3014 /**************************************************************************** 3015 * MGT_TOP_CMN_CTLR :: gp_reg_4 3016 */ 3017 /* MGT_TOP_CMN_CTLR :: gp_reg_4 :: gpreg4_data [15:00] */ 3018 #define MGT_TOP_CMN_CTLR_GP_REG_4_GPREG4_DATA_MASK 0xffff 3019 #define MGT_TOP_CMN_CTLR_GP_REG_4_GPREG4_DATA_ALIGN 0 3020 #define MGT_TOP_CMN_CTLR_GP_REG_4_GPREG4_DATA_BITS 16 3021 #define MGT_TOP_CMN_CTLR_GP_REG_4_GPREG4_DATA_SHIFT 0 3022 3023 3024 /**************************************************************************** 3025 * MGT_TOP_CMN_CTLR :: fw_param 3026 */ 3027 /* MGT_TOP_CMN_CTLR :: fw_param :: param [15:00] */ 3028 #define MGT_TOP_CMN_CTLR_FW_PARAM_PARAM_MASK 0xffff 3029 #define MGT_TOP_CMN_CTLR_FW_PARAM_PARAM_ALIGN 0 3030 #define MGT_TOP_CMN_CTLR_FW_PARAM_PARAM_BITS 16 3031 #define MGT_TOP_CMN_CTLR_FW_PARAM_PARAM_SHIFT 0 3032 3033 3034 /**************************************************************************** 3035 * MGT_TOP_CMN_CTLR :: fw_cmd 3036 */ 3037 /* MGT_TOP_CMN_CTLR :: fw_cmd :: cmd [15:00] */ 3038 #define MGT_TOP_CMN_CTLR_FW_CMD_CMD_MASK 0xffff 3039 #define MGT_TOP_CMN_CTLR_FW_CMD_CMD_ALIGN 0 3040 #define MGT_TOP_CMN_CTLR_FW_CMD_CMD_BITS 16 3041 #define MGT_TOP_CMN_CTLR_FW_CMD_CMD_SHIFT 0 3042 3043 3044 /**************************************************************************** 3045 * MGT_TOP_CMN_CTLR :: heartbeat_count 3046 */ 3047 /* MGT_TOP_CMN_CTLR :: heartbeat_count :: count [15:00] */ 3048 #define MGT_TOP_CMN_CTLR_HEARTBEAT_COUNT_COUNT_MASK 0xffff 3049 #define MGT_TOP_CMN_CTLR_HEARTBEAT_COUNT_COUNT_ALIGN 0 3050 #define MGT_TOP_CMN_CTLR_HEARTBEAT_COUNT_COUNT_BITS 16 3051 #define MGT_TOP_CMN_CTLR_HEARTBEAT_COUNT_COUNT_SHIFT 0 3052 3053 3054 /**************************************************************************** 3055 * MGT_TOP_CMN_CTLR :: logad_ctrl 3056 */ 3057 /* MGT_TOP_CMN_CTLR :: logad_ctrl :: reserved0 [15:08] */ 3058 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_RESERVED0_MASK 0xff00 3059 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_RESERVED0_ALIGN 0 3060 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_RESERVED0_BITS 8 3061 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_RESERVED0_SHIFT 8 3062 3063 /* MGT_TOP_CMN_CTLR :: logad_ctrl :: Logical_ch_numbering_4_physical_ch3 [07:06] */ 3064 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH3_MASK 0x00c0 3065 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH3_ALIGN 0 3066 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH3_BITS 2 3067 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH3_SHIFT 6 3068 3069 /* MGT_TOP_CMN_CTLR :: logad_ctrl :: Logical_ch_numbering_4_physical_ch2 [05:04] */ 3070 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH2_MASK 0x0030 3071 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH2_ALIGN 0 3072 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH2_BITS 2 3073 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH2_SHIFT 4 3074 3075 /* MGT_TOP_CMN_CTLR :: logad_ctrl :: Logical_ch_numbering_4_physical_ch1 [03:02] */ 3076 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH1_MASK 0x000c 3077 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH1_ALIGN 0 3078 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH1_BITS 2 3079 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH1_SHIFT 2 3080 3081 /* MGT_TOP_CMN_CTLR :: logad_ctrl :: Logical_ch_numbering_4_physical_ch0 [01:00] */ 3082 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH0_MASK 0x0003 3083 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH0_ALIGN 0 3084 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH0_BITS 2 3085 #define MGT_TOP_CMN_CTLR_LOGAD_CTRL_LOGICAL_CH_NUMBERING_4_PHYSICAL_CH0_SHIFT 0 3086 3087 3088 /**************************************************************************** 3089 * MGT_TOP_CMN_CTLR :: sw_reset_ctrl 3090 */ 3091 /* MGT_TOP_CMN_CTLR :: sw_reset_ctrl :: reserved0 [15:03] */ 3092 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_RESERVED0_MASK 0xfff8 3093 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_RESERVED0_ALIGN 0 3094 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_RESERVED0_BITS 13 3095 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_RESERVED0_SHIFT 3 3096 3097 /* MGT_TOP_CMN_CTLR :: sw_reset_ctrl :: i2c_master_blk_sw_rst [02:02] */ 3098 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_I2C_MASTER_BLK_SW_RST_MASK 0x0004 3099 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_I2C_MASTER_BLK_SW_RST_ALIGN 0 3100 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_I2C_MASTER_BLK_SW_RST_BITS 1 3101 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_I2C_MASTER_BLK_SW_RST_SHIFT 2 3102 3103 /* MGT_TOP_CMN_CTLR :: sw_reset_ctrl :: i2c_slave_blk_sw_rst [01:01] */ 3104 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_I2C_SLAVE_BLK_SW_RST_MASK 0x0002 3105 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_I2C_SLAVE_BLK_SW_RST_ALIGN 0 3106 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_I2C_SLAVE_BLK_SW_RST_BITS 1 3107 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_I2C_SLAVE_BLK_SW_RST_SHIFT 1 3108 3109 /* MGT_TOP_CMN_CTLR :: sw_reset_ctrl :: reserved1 [00:00] */ 3110 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_RESERVED1_MASK 0x0001 3111 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_RESERVED1_ALIGN 0 3112 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_RESERVED1_BITS 1 3113 #define MGT_TOP_CMN_CTLR_SW_RESET_CTRL_RESERVED1_SHIFT 0 3114 3115 3116 /**************************************************************************** 3117 * MGT_TOP_CMN_CTLR :: misc_ctrl 3118 */ 3119 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: Serial_broadcast_Mode [15:15] */ 3120 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SERIAL_BROADCAST_MODE_MASK 0x8000 3121 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SERIAL_BROADCAST_MODE_ALIGN 0 3122 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SERIAL_BROADCAST_MODE_BITS 1 3123 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SERIAL_BROADCAST_MODE_SHIFT 15 3124 3125 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: rescal_done_stat [14:14] */ 3126 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESCAL_DONE_STAT_MASK 0x4000 3127 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESCAL_DONE_STAT_ALIGN 0 3128 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESCAL_DONE_STAT_BITS 1 3129 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESCAL_DONE_STAT_SHIFT 14 3130 3131 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: rxd_oen [13:13] */ 3132 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RXD_OEN_MASK 0x2000 3133 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RXD_OEN_ALIGN 0 3134 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RXD_OEN_BITS 1 3135 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RXD_OEN_SHIFT 13 3136 3137 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: txd_oen [12:12] */ 3138 #define MGT_TOP_CMN_CTLR_MISC_CTRL_TXD_OEN_MASK 0x1000 3139 #define MGT_TOP_CMN_CTLR_MISC_CTRL_TXD_OEN_ALIGN 0 3140 #define MGT_TOP_CMN_CTLR_MISC_CTRL_TXD_OEN_BITS 1 3141 #define MGT_TOP_CMN_CTLR_MISC_CTRL_TXD_OEN_SHIFT 12 3142 3143 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: rescal [11:08] */ 3144 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESCAL_MASK 0x0f00 3145 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESCAL_ALIGN 0 3146 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESCAL_BITS 4 3147 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESCAL_SHIFT 8 3148 3149 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: global_chip_intr_en [07:07] */ 3150 #define MGT_TOP_CMN_CTLR_MISC_CTRL_GLOBAL_CHIP_INTR_EN_MASK 0x0080 3151 #define MGT_TOP_CMN_CTLR_MISC_CTRL_GLOBAL_CHIP_INTR_EN_ALIGN 0 3152 #define MGT_TOP_CMN_CTLR_MISC_CTRL_GLOBAL_CHIP_INTR_EN_BITS 1 3153 #define MGT_TOP_CMN_CTLR_MISC_CTRL_GLOBAL_CHIP_INTR_EN_SHIFT 7 3154 3155 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: reserved0 [06:05] */ 3156 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESERVED0_MASK 0x0060 3157 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESERVED0_ALIGN 0 3158 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESERVED0_BITS 2 3159 #define MGT_TOP_CMN_CTLR_MISC_CTRL_RESERVED0_SHIFT 5 3160 3161 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: message_out_status [04:04] */ 3162 #define MGT_TOP_CMN_CTLR_MISC_CTRL_MESSAGE_OUT_STATUS_MASK 0x0010 3163 #define MGT_TOP_CMN_CTLR_MISC_CTRL_MESSAGE_OUT_STATUS_ALIGN 0 3164 #define MGT_TOP_CMN_CTLR_MISC_CTRL_MESSAGE_OUT_STATUS_BITS 1 3165 #define MGT_TOP_CMN_CTLR_MISC_CTRL_MESSAGE_OUT_STATUS_SHIFT 4 3166 3167 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: spi_download_size [03:03] */ 3168 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SPI_DOWNLOAD_SIZE_MASK 0x0008 3169 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SPI_DOWNLOAD_SIZE_ALIGN 0 3170 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SPI_DOWNLOAD_SIZE_BITS 1 3171 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SPI_DOWNLOAD_SIZE_SHIFT 3 3172 3173 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: spi_download_clock_speed [02:02] */ 3174 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SPI_DOWNLOAD_CLOCK_SPEED_MASK 0x0004 3175 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SPI_DOWNLOAD_CLOCK_SPEED_ALIGN 0 3176 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SPI_DOWNLOAD_CLOCK_SPEED_BITS 1 3177 #define MGT_TOP_CMN_CTLR_MISC_CTRL_SPI_DOWNLOAD_CLOCK_SPEED_SHIFT 2 3178 3179 /* MGT_TOP_CMN_CTLR :: misc_ctrl :: i2c_port_sel [01:00] */ 3180 #define MGT_TOP_CMN_CTLR_MISC_CTRL_I2C_PORT_SEL_MASK 0x0003 3181 #define MGT_TOP_CMN_CTLR_MISC_CTRL_I2C_PORT_SEL_ALIGN 0 3182 #define MGT_TOP_CMN_CTLR_MISC_CTRL_I2C_PORT_SEL_BITS 2 3183 #define MGT_TOP_CMN_CTLR_MISC_CTRL_I2C_PORT_SEL_SHIFT 0 3184 3185 3186 /**************************************************************************** 3187 * MGT_TOP_CMN_CTLR :: single_pmd_ctrl 3188 */ 3189 /* MGT_TOP_CMN_CTLR :: single_pmd_ctrl :: reserved0 [15:10] */ 3190 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_RESERVED0_MASK 0xfc00 3191 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_RESERVED0_ALIGN 0 3192 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_RESERVED0_BITS 6 3193 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_RESERVED0_SHIFT 10 3194 3195 /* MGT_TOP_CMN_CTLR :: single_pmd_ctrl :: gallardoA0_dis [09:09] */ 3196 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_GALLARDOA0_DIS_MASK 0x0200 3197 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_GALLARDOA0_DIS_ALIGN 0 3198 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_GALLARDOA0_DIS_BITS 1 3199 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_GALLARDOA0_DIS_SHIFT 9 3200 3201 /* MGT_TOP_CMN_CTLR :: single_pmd_ctrl :: single_pmd_ch_sel [08:08] */ 3202 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_SINGLE_PMD_CH_SEL_MASK 0x0100 3203 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_SINGLE_PMD_CH_SEL_ALIGN 0 3204 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_SINGLE_PMD_CH_SEL_BITS 1 3205 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_SINGLE_PMD_CH_SEL_SHIFT 8 3206 3207 /* MGT_TOP_CMN_CTLR :: single_pmd_ctrl :: Single_pmd_mode [07:07] */ 3208 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_SINGLE_PMD_MODE_MASK 0x0080 3209 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_SINGLE_PMD_MODE_ALIGN 0 3210 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_SINGLE_PMD_MODE_BITS 1 3211 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_SINGLE_PMD_MODE_SHIFT 7 3212 3213 /* MGT_TOP_CMN_CTLR :: single_pmd_ctrl :: reserved1 [06:06] */ 3214 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_RESERVED1_MASK 0x0040 3215 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_RESERVED1_ALIGN 0 3216 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_RESERVED1_BITS 1 3217 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_RESERVED1_SHIFT 6 3218 3219 /* MGT_TOP_CMN_CTLR :: single_pmd_ctrl :: phy_ch_to_access_in_single_pmd [05:04] */ 3220 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_PHY_CH_TO_ACCESS_IN_SINGLE_PMD_MASK 0x0030 3221 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_PHY_CH_TO_ACCESS_IN_SINGLE_PMD_ALIGN 0 3222 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_PHY_CH_TO_ACCESS_IN_SINGLE_PMD_BITS 2 3223 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_PHY_CH_TO_ACCESS_IN_SINGLE_PMD_SHIFT 4 3224 3225 /* MGT_TOP_CMN_CTLR :: single_pmd_ctrl :: phy_ch_to_be_disable_in_single_pmd [03:00] */ 3226 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_PHY_CH_TO_BE_DISABLE_IN_SINGLE_PMD_MASK 0x000f 3227 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_PHY_CH_TO_BE_DISABLE_IN_SINGLE_PMD_ALIGN 0 3228 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_PHY_CH_TO_BE_DISABLE_IN_SINGLE_PMD_BITS 4 3229 #define MGT_TOP_CMN_CTLR_SINGLE_PMD_CTRL_PHY_CH_TO_BE_DISABLE_IN_SINGLE_PMD_SHIFT 0 3230 3231 3232 /**************************************************************************** 3233 * MGT_TOP_CMN_CTLR :: gp_reg_5 3234 */ 3235 /* MGT_TOP_CMN_CTLR :: gp_reg_5 :: gpreg5_data [15:00] */ 3236 #define MGT_TOP_CMN_CTLR_GP_REG_5_GPREG5_DATA_MASK 0xffff 3237 #define MGT_TOP_CMN_CTLR_GP_REG_5_GPREG5_DATA_ALIGN 0 3238 #define MGT_TOP_CMN_CTLR_GP_REG_5_GPREG5_DATA_BITS 16 3239 #define MGT_TOP_CMN_CTLR_GP_REG_5_GPREG5_DATA_SHIFT 0 3240 3241 3242 /**************************************************************************** 3243 * MGT_TOP_CMN_CTLR :: gp_reg_6 3244 */ 3245 /* MGT_TOP_CMN_CTLR :: gp_reg_6 :: gpreg6_data [15:00] */ 3246 #define MGT_TOP_CMN_CTLR_GP_REG_6_GPREG6_DATA_MASK 0xffff 3247 #define MGT_TOP_CMN_CTLR_GP_REG_6_GPREG6_DATA_ALIGN 0 3248 #define MGT_TOP_CMN_CTLR_GP_REG_6_GPREG6_DATA_BITS 16 3249 #define MGT_TOP_CMN_CTLR_GP_REG_6_GPREG6_DATA_SHIFT 0 3250 3251 3252 /**************************************************************************** 3253 * MGT_TOP_CMN_CTLR :: gp_reg_7 3254 */ 3255 /* MGT_TOP_CMN_CTLR :: gp_reg_7 :: gpreg7_data [15:00] */ 3256 #define MGT_TOP_CMN_CTLR_GP_REG_7_GPREG7_DATA_MASK 0xffff 3257 #define MGT_TOP_CMN_CTLR_GP_REG_7_GPREG7_DATA_ALIGN 0 3258 #define MGT_TOP_CMN_CTLR_GP_REG_7_GPREG7_DATA_BITS 16 3259 #define MGT_TOP_CMN_CTLR_GP_REG_7_GPREG7_DATA_SHIFT 0 3260 3261 3262 /**************************************************************************** 3263 * MGT_TOP_CMN_CTLR :: gp_reg_8 3264 */ 3265 /* MGT_TOP_CMN_CTLR :: gp_reg_8 :: gpreg8_data [15:00] */ 3266 #define MGT_TOP_CMN_CTLR_GP_REG_8_GPREG8_DATA_MASK 0xffff 3267 #define MGT_TOP_CMN_CTLR_GP_REG_8_GPREG8_DATA_ALIGN 0 3268 #define MGT_TOP_CMN_CTLR_GP_REG_8_GPREG8_DATA_BITS 16 3269 #define MGT_TOP_CMN_CTLR_GP_REG_8_GPREG8_DATA_SHIFT 0 3270 3271 3272 /**************************************************************************** 3273 * MGT_TOP_CMN_CTLR :: gp_reg_9 3274 */ 3275 /* MGT_TOP_CMN_CTLR :: gp_reg_9 :: gpreg9_data [15:00] */ 3276 #define MGT_TOP_CMN_CTLR_GP_REG_9_GPREG9_DATA_MASK 0xffff 3277 #define MGT_TOP_CMN_CTLR_GP_REG_9_GPREG9_DATA_ALIGN 0 3278 #define MGT_TOP_CMN_CTLR_GP_REG_9_GPREG9_DATA_BITS 16 3279 #define MGT_TOP_CMN_CTLR_GP_REG_9_GPREG9_DATA_SHIFT 0 3280 3281 3282 /**************************************************************************** 3283 * MGT_TOP_CMN_CTLR :: memory_tm_ctrl_0 3284 */ 3285 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_0 :: reserved0 [15:15] */ 3286 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_RESERVED0_MASK 0x8000 3287 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_RESERVED0_ALIGN 0 3288 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_RESERVED0_BITS 1 3289 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_RESERVED0_SHIFT 15 3290 3291 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_0 :: data_ram_tm [14:08] */ 3292 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_DATA_RAM_TM_MASK 0x7f00 3293 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_DATA_RAM_TM_ALIGN 0 3294 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_DATA_RAM_TM_BITS 7 3295 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_DATA_RAM_TM_SHIFT 8 3296 3297 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_0 :: reserved1 [07:07] */ 3298 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_RESERVED1_MASK 0x0080 3299 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_RESERVED1_ALIGN 0 3300 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_RESERVED1_BITS 1 3301 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_RESERVED1_SHIFT 7 3302 3303 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_0 :: code_ram_tm [06:00] */ 3304 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_CODE_RAM_TM_MASK 0x007f 3305 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_CODE_RAM_TM_ALIGN 0 3306 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_CODE_RAM_TM_BITS 7 3307 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_0_CODE_RAM_TM_SHIFT 0 3308 3309 3310 /**************************************************************************** 3311 * MGT_TOP_CMN_CTLR :: memory_tm_ctrl_1 3312 */ 3313 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_1 :: reserved0 [15:14] */ 3314 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RESERVED0_MASK 0xc000 3315 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RESERVED0_ALIGN 0 3316 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RESERVED0_BITS 2 3317 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RESERVED0_SHIFT 14 3318 3319 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_1 :: ram256_tm [13:11] */ 3320 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RAM256_TM_MASK 0x3800 3321 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RAM256_TM_ALIGN 0 3322 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RAM256_TM_BITS 3 3323 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RAM256_TM_SHIFT 11 3324 3325 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_1 :: ram1024_tm [10:08] */ 3326 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RAM1024_TM_MASK 0x0700 3327 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RAM1024_TM_ALIGN 0 3328 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RAM1024_TM_BITS 3 3329 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RAM1024_TM_SHIFT 8 3330 3331 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_1 :: reserved1 [07:06] */ 3332 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RESERVED1_MASK 0x00c0 3333 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RESERVED1_ALIGN 0 3334 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RESERVED1_BITS 2 3335 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_RESERVED1_SHIFT 6 3336 3337 /* MGT_TOP_CMN_CTLR :: memory_tm_ctrl_1 :: cf_ram_tm [05:00] */ 3338 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_CF_RAM_TM_MASK 0x003f 3339 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_CF_RAM_TM_ALIGN 0 3340 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_CF_RAM_TM_BITS 6 3341 #define MGT_TOP_CMN_CTLR_MEMORY_TM_CTRL_1_CF_RAM_TM_SHIFT 0 3342 3343 3344 /**************************************************************************** 3345 * MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 3346 */ 3347 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: reserved0 [15:12] */ 3348 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RESERVED0_MASK 0xf000 3349 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RESERVED0_ALIGN 0 3350 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RESERVED0_BITS 4 3351 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RESERVED0_SHIFT 12 3352 3353 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: xpak_mem_stby [11:11] */ 3354 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_XPAK_MEM_STBY_MASK 0x0800 3355 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_XPAK_MEM_STBY_ALIGN 0 3356 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_XPAK_MEM_STBY_BITS 1 3357 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_XPAK_MEM_STBY_SHIFT 11 3358 3359 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: lo8k_rom_stby [10:10] */ 3360 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_LO8K_ROM_STBY_MASK 0x0400 3361 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_LO8K_ROM_STBY_ALIGN 0 3362 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_LO8K_ROM_STBY_BITS 1 3363 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_LO8K_ROM_STBY_SHIFT 10 3364 3365 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: hi8k_rom1_stby [09:09] */ 3366 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM1_STBY_MASK 0x0200 3367 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM1_STBY_ALIGN 0 3368 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM1_STBY_BITS 1 3369 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM1_STBY_SHIFT 9 3370 3371 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: hi8k_rom2_stby [08:08] */ 3372 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM2_STBY_MASK 0x0100 3373 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM2_STBY_ALIGN 0 3374 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM2_STBY_BITS 1 3375 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM2_STBY_SHIFT 8 3376 3377 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: hi8k_rom3_stby [07:07] */ 3378 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM3_STBY_MASK 0x0080 3379 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM3_STBY_ALIGN 0 3380 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM3_STBY_BITS 1 3381 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_HI8K_ROM3_STBY_SHIFT 7 3382 3383 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: dataram2k_stby [06:06] */ 3384 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_DATARAM2K_STBY_MASK 0x0040 3385 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_DATARAM2K_STBY_ALIGN 0 3386 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_DATARAM2K_STBY_BITS 1 3387 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_DATARAM2K_STBY_SHIFT 6 3388 3389 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: ram256_stby [05:05] */ 3390 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RAM256_STBY_MASK 0x0020 3391 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RAM256_STBY_ALIGN 0 3392 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RAM256_STBY_BITS 1 3393 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RAM256_STBY_SHIFT 5 3394 3395 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: ram1024_stby [04:04] */ 3396 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RAM1024_STBY_MASK 0x0010 3397 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RAM1024_STBY_ALIGN 0 3398 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RAM1024_STBY_BITS 1 3399 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_RAM1024_STBY_SHIFT 4 3400 3401 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: code_ram_i3_stby [03:03] */ 3402 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I3_STBY_MASK 0x0008 3403 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I3_STBY_ALIGN 0 3404 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I3_STBY_BITS 1 3405 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I3_STBY_SHIFT 3 3406 3407 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: code_ram_i2_stby [02:02] */ 3408 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I2_STBY_MASK 0x0004 3409 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I2_STBY_ALIGN 0 3410 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I2_STBY_BITS 1 3411 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I2_STBY_SHIFT 2 3412 3413 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: code_ram_i1_stby [01:01] */ 3414 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I1_STBY_MASK 0x0002 3415 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I1_STBY_ALIGN 0 3416 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I1_STBY_BITS 1 3417 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I1_STBY_SHIFT 1 3418 3419 /* MGT_TOP_CMN_CTLR :: memory_stby_ctrl_0 :: code_ram_i0_stby [00:00] */ 3420 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I0_STBY_MASK 0x0001 3421 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I0_STBY_ALIGN 0 3422 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I0_STBY_BITS 1 3423 #define MGT_TOP_CMN_CTLR_MEMORY_STBY_CTRL_0_CODE_RAM_I0_STBY_SHIFT 0 3424 3425 3426 /**************************************************************************** 3427 * MGT_TOP_CMN_CTLR :: vtmon_ctrl_0 3428 */ 3429 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_0 :: DAC_Enable [15:15] */ 3430 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_DAC_ENABLE_MASK 0x8000 3431 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_DAC_ENABLE_ALIGN 0 3432 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_DAC_ENABLE_BITS 1 3433 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_DAC_ENABLE_SHIFT 15 3434 3435 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_0 :: ADC_input_select [14:13] */ 3436 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_ADC_INPUT_SELECT_MASK 0x6000 3437 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_ADC_INPUT_SELECT_ALIGN 0 3438 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_ADC_INPUT_SELECT_BITS 2 3439 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_ADC_INPUT_SELECT_SHIFT 13 3440 3441 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_0 :: mode [12:10] */ 3442 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_MODE_MASK 0x1c00 3443 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_MODE_ALIGN 0 3444 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_MODE_BITS 3 3445 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_MODE_SHIFT 10 3446 3447 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_0 :: reserved0 [09:07] */ 3448 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_RESERVED0_MASK 0x0380 3449 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_RESERVED0_ALIGN 0 3450 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_RESERVED0_BITS 3 3451 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_RESERVED0_SHIFT 7 3452 3453 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_0 :: vtmon_test_sel [06:03] */ 3454 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_VTMON_TEST_SEL_MASK 0x0078 3455 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_VTMON_TEST_SEL_ALIGN 0 3456 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_VTMON_TEST_SEL_BITS 4 3457 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_VTMON_TEST_SEL_SHIFT 3 3458 3459 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_0 :: vtmon_bg_adj [02:00] */ 3460 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_VTMON_BG_ADJ_MASK 0x0007 3461 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_VTMON_BG_ADJ_ALIGN 0 3462 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_VTMON_BG_ADJ_BITS 3 3463 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_0_VTMON_BG_ADJ_SHIFT 0 3464 3465 3466 /**************************************************************************** 3467 * MGT_TOP_CMN_CTLR :: vtmon_ctrl_1 3468 */ 3469 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_1 :: reserved0 [15:08] */ 3470 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_RESERVED0_MASK 0xff00 3471 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_RESERVED0_ALIGN 0 3472 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_RESERVED0_BITS 8 3473 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_RESERVED0_SHIFT 8 3474 3475 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_1 :: pvtmon_idoffmon_pwrdn [07:07] */ 3476 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_PVTMON_IDOFFMON_PWRDN_MASK 0x0080 3477 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_PVTMON_IDOFFMON_PWRDN_ALIGN 0 3478 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_PVTMON_IDOFFMON_PWRDN_BITS 1 3479 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_PVTMON_IDOFFMON_PWRDN_SHIFT 7 3480 3481 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_1 :: vtmon_strb [06:06] */ 3482 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_STRB_MASK 0x0040 3483 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_STRB_ALIGN 0 3484 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_STRB_BITS 1 3485 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_STRB_SHIFT 6 3486 3487 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_1 :: vtmon_pwrdn [05:05] */ 3488 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_PWRDN_MASK 0x0020 3489 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_PWRDN_ALIGN 0 3490 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_PWRDN_BITS 1 3491 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_PWRDN_SHIFT 5 3492 3493 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_1 :: vtmon_rstb [04:04] */ 3494 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_RSTB_MASK 0x0010 3495 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_RSTB_ALIGN 0 3496 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_RSTB_BITS 1 3497 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_RSTB_SHIFT 4 3498 3499 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_1 :: reserved1 [03:03] */ 3500 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_RESERVED1_MASK 0x0008 3501 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_RESERVED1_ALIGN 0 3502 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_RESERVED1_BITS 1 3503 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_RESERVED1_SHIFT 3 3504 3505 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_1 :: vtmon_mode_sel [02:00] */ 3506 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_MODE_SEL_MASK 0x0007 3507 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_MODE_SEL_ALIGN 0 3508 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_MODE_SEL_BITS 3 3509 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_1_VTMON_MODE_SEL_SHIFT 0 3510 3511 3512 /**************************************************************************** 3513 * MGT_TOP_CMN_CTLR :: vtmon_status 3514 */ 3515 /* MGT_TOP_CMN_CTLR :: vtmon_status :: vtmon_maxb0 [15:15] */ 3516 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MAXB0_MASK 0x8000 3517 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MAXB0_ALIGN 0 3518 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MAXB0_BITS 1 3519 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MAXB0_SHIFT 15 3520 3521 /* MGT_TOP_CMN_CTLR :: vtmon_status :: vtmon_maxb1 [14:14] */ 3522 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MAXB1_MASK 0x4000 3523 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MAXB1_ALIGN 0 3524 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MAXB1_BITS 1 3525 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MAXB1_SHIFT 14 3526 3527 /* MGT_TOP_CMN_CTLR :: vtmon_status :: vtmon_minb0 [13:13] */ 3528 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MINB0_MASK 0x2000 3529 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MINB0_ALIGN 0 3530 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MINB0_BITS 1 3531 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MINB0_SHIFT 13 3532 3533 /* MGT_TOP_CMN_CTLR :: vtmon_status :: vtmon_minb1 [12:12] */ 3534 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MINB1_MASK 0x1000 3535 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MINB1_ALIGN 0 3536 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MINB1_BITS 1 3537 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_MINB1_SHIFT 12 3538 3539 /* MGT_TOP_CMN_CTLR :: vtmon_status :: vtmon_warningb0 [11:11] */ 3540 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_WARNINGB0_MASK 0x0800 3541 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_WARNINGB0_ALIGN 0 3542 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_WARNINGB0_BITS 1 3543 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_WARNINGB0_SHIFT 11 3544 3545 /* MGT_TOP_CMN_CTLR :: vtmon_status :: vtmon_warningb1 [10:10] */ 3546 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_WARNINGB1_MASK 0x0400 3547 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_WARNINGB1_ALIGN 0 3548 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_WARNINGB1_BITS 1 3549 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_WARNINGB1_SHIFT 10 3550 3551 /* MGT_TOP_CMN_CTLR :: vtmon_status :: vtmon_data [09:00] */ 3552 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_DATA_MASK 0x03ff 3553 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_DATA_ALIGN 0 3554 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_DATA_BITS 10 3555 #define MGT_TOP_CMN_CTLR_VTMON_STATUS_VTMON_DATA_SHIFT 0 3556 3557 3558 /**************************************************************************** 3559 * MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 3560 */ 3561 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 :: VDDCMON_refadj_max [15:13] */ 3562 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MAX_MASK 0xe000 3563 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MAX_ALIGN 0 3564 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MAX_BITS 3 3565 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MAX_SHIFT 13 3566 3567 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 :: DAC_set [12:12] */ 3568 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_DAC_SET_MASK 0x1000 3569 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_DAC_SET_ALIGN 0 3570 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_DAC_SET_BITS 1 3571 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_DAC_SET_SHIFT 12 3572 3573 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 :: DAC_reset [11:11] */ 3574 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_DAC_RESET_MASK 0x0800 3575 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_DAC_RESET_ALIGN 0 3576 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_DAC_RESET_BITS 1 3577 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_DAC_RESET_SHIFT 11 3578 3579 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 :: VDDCMON_refadj_min1 [10:08] */ 3580 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MIN1_MASK 0x0700 3581 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MIN1_ALIGN 0 3582 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MIN1_BITS 3 3583 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MIN1_SHIFT 8 3584 3585 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 :: VDDCMON_refadj_min0 [07:04] */ 3586 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MIN0_MASK 0x00f0 3587 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MIN0_ALIGN 0 3588 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MIN0_BITS 4 3589 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_VDDCMON_REFADJ_MIN0_SHIFT 4 3590 3591 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 :: reserved0 [03:02] */ 3592 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_RESERVED0_MASK 0x000c 3593 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_RESERVED0_ALIGN 0 3594 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_RESERVED0_BITS 2 3595 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_RESERVED0_SHIFT 2 3596 3597 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 :: Burnin_en [01:01] */ 3598 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_BURNIN_EN_MASK 0x0002 3599 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_BURNIN_EN_ALIGN 0 3600 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_BURNIN_EN_BITS 1 3601 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_BURNIN_EN_SHIFT 1 3602 3603 /* MGT_TOP_CMN_CTLR :: vtmon_ctrl_2 :: Con_pad [00:00] */ 3604 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_CON_PAD_MASK 0x0001 3605 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_CON_PAD_ALIGN 0 3606 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_CON_PAD_BITS 1 3607 #define MGT_TOP_CMN_CTLR_VTMON_CTRL_2_CON_PAD_SHIFT 0 3608 3609 3610 /**************************************************************************** 3611 * MGT_TOP_CMN_CTLR :: RESCAL_ctrl_dfs 3612 */ 3613 /* MGT_TOP_CMN_CTLR :: RESCAL_ctrl_dfs :: reserved0 [15:13] */ 3614 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_DFS_RESERVED0_MASK 0xe000 3615 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_DFS_RESERVED0_ALIGN 0 3616 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_DFS_RESERVED0_BITS 3 3617 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_DFS_RESERVED0_SHIFT 13 3618 3619 /* MGT_TOP_CMN_CTLR :: RESCAL_ctrl_dfs :: rescal_ctrl_dfs_value [12:00] */ 3620 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_DFS_RESCAL_CTRL_DFS_VALUE_MASK 0x1fff 3621 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_DFS_RESCAL_CTRL_DFS_VALUE_ALIGN 0 3622 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_DFS_RESCAL_CTRL_DFS_VALUE_BITS 13 3623 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_DFS_RESCAL_CTRL_DFS_VALUE_SHIFT 0 3624 3625 3626 /**************************************************************************** 3627 * MGT_TOP_CMN_CTLR :: RESCAL_status 3628 */ 3629 /* MGT_TOP_CMN_CTLR :: RESCAL_status :: reserved0 [15:15] */ 3630 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESERVED0_MASK 0x8000 3631 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESERVED0_ALIGN 0 3632 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESERVED0_BITS 1 3633 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESERVED0_SHIFT 15 3634 3635 /* MGT_TOP_CMN_CTLR :: RESCAL_status :: rescal_curr_comp_cnt [14:09] */ 3636 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_CURR_COMP_CNT_MASK 0x7e00 3637 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_CURR_COMP_CNT_ALIGN 0 3638 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_CURR_COMP_CNT_BITS 6 3639 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_CURR_COMP_CNT_SHIFT 9 3640 3641 /* MGT_TOP_CMN_CTLR :: RESCAL_status :: rescal_prev_comp_cnt [08:05] */ 3642 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_PREV_COMP_CNT_MASK 0x01e0 3643 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_PREV_COMP_CNT_ALIGN 0 3644 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_PREV_COMP_CNT_BITS 4 3645 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_PREV_COMP_CNT_SHIFT 5 3646 3647 /* MGT_TOP_CMN_CTLR :: RESCAL_status :: rescal_state [04:02] */ 3648 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_STATE_MASK 0x001c 3649 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_STATE_ALIGN 0 3650 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_STATE_BITS 3 3651 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_STATE_SHIFT 2 3652 3653 /* MGT_TOP_CMN_CTLR :: RESCAL_status :: rescal_comp [01:01] */ 3654 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_COMP_MASK 0x0002 3655 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_COMP_ALIGN 0 3656 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_COMP_BITS 1 3657 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_COMP_SHIFT 1 3658 3659 /* MGT_TOP_CMN_CTLR :: RESCAL_status :: rescal_valid [00:00] */ 3660 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_VALID_MASK 0x0001 3661 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_VALID_ALIGN 0 3662 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_VALID_BITS 1 3663 #define MGT_TOP_CMN_CTLR_RESCAL_STATUS_RESCAL_VALID_SHIFT 0 3664 3665 3666 /**************************************************************************** 3667 * MGT_TOP_CMN_CTLR :: RESCAL_ctrl 3668 */ 3669 /* MGT_TOP_CMN_CTLR :: RESCAL_ctrl :: reserved0 [15:15] */ 3670 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESERVED0_MASK 0x8000 3671 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESERVED0_ALIGN 0 3672 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESERVED0_BITS 1 3673 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESERVED0_SHIFT 15 3674 3675 /* MGT_TOP_CMN_CTLR :: RESCAL_ctrl :: rescal_power_down [14:14] */ 3676 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_POWER_DOWN_MASK 0x4000 3677 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_POWER_DOWN_ALIGN 0 3678 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_POWER_DOWN_BITS 1 3679 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_POWER_DOWN_SHIFT 14 3680 3681 /* MGT_TOP_CMN_CTLR :: RESCAL_ctrl :: rescal_diag_on [13:13] */ 3682 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_DIAG_ON_MASK 0x2000 3683 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_DIAG_ON_ALIGN 0 3684 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_DIAG_ON_BITS 1 3685 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_DIAG_ON_SHIFT 13 3686 3687 /* MGT_TOP_CMN_CTLR :: RESCAL_ctrl :: rescal_ctrl [12:00] */ 3688 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_CTRL_MASK 0x1fff 3689 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_CTRL_ALIGN 0 3690 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_CTRL_BITS 13 3691 #define MGT_TOP_CMN_CTLR_RESCAL_CTRL_RESCAL_CTRL_SHIFT 0 3692 3693 3694 /**************************************************************************** 3695 * MGT_TOP_CMN_CTLR :: ring_osc_control_register 3696 */ 3697 /* MGT_TOP_CMN_CTLR :: ring_osc_control_register :: reserved0 [15:10] */ 3698 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RESERVED0_MASK 0xfc00 3699 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RESERVED0_ALIGN 0 3700 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RESERVED0_BITS 6 3701 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RESERVED0_SHIFT 10 3702 3703 /* MGT_TOP_CMN_CTLR :: ring_osc_control_register :: ring_osc_2_active [09:09] */ 3704 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RING_OSC_2_ACTIVE_MASK 0x0200 3705 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RING_OSC_2_ACTIVE_ALIGN 0 3706 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RING_OSC_2_ACTIVE_BITS 1 3707 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RING_OSC_2_ACTIVE_SHIFT 9 3708 3709 /* MGT_TOP_CMN_CTLR :: ring_osc_control_register :: ring_osc_1_active [08:08] */ 3710 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RING_OSC_1_ACTIVE_MASK 0x0100 3711 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RING_OSC_1_ACTIVE_ALIGN 0 3712 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RING_OSC_1_ACTIVE_BITS 1 3713 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_RING_OSC_1_ACTIVE_SHIFT 8 3714 3715 /* MGT_TOP_CMN_CTLR :: ring_osc_control_register :: osc_en_sel [07:04] */ 3716 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_OSC_EN_SEL_MASK 0x00f0 3717 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_OSC_EN_SEL_ALIGN 0 3718 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_OSC_EN_SEL_BITS 4 3719 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_OSC_EN_SEL_SHIFT 4 3720 3721 /* MGT_TOP_CMN_CTLR :: ring_osc_control_register :: osc_out_sel [03:00] */ 3722 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_OSC_OUT_SEL_MASK 0x000f 3723 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_OSC_OUT_SEL_ALIGN 0 3724 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_OSC_OUT_SEL_BITS 4 3725 #define MGT_TOP_CMN_CTLR_RING_OSC_CONTROL_REGISTER_OSC_OUT_SEL_SHIFT 0 3726 3727 3728 /**************************************************************************** 3729 * MGT_TOP_CMN_CTLR :: io_ring_control 3730 */ 3731 /* MGT_TOP_CMN_CTLR :: io_ring_control :: reserved0 [15:09] */ 3732 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED0_MASK 0xfe00 3733 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED0_ALIGN 0 3734 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED0_BITS 7 3735 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED0_SHIFT 9 3736 3737 /* MGT_TOP_CMN_CTLR :: io_ring_control :: CP_vdd1p8_ok [08:08] */ 3738 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_CP_VDD1P8_OK_MASK 0x0100 3739 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_CP_VDD1P8_OK_ALIGN 0 3740 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_CP_VDD1P8_OK_BITS 1 3741 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_CP_VDD1P8_OK_SHIFT 8 3742 3743 /* MGT_TOP_CMN_CTLR :: io_ring_control :: reserved1 [07:06] */ 3744 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED1_MASK 0x00c0 3745 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED1_ALIGN 0 3746 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED1_BITS 2 3747 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED1_SHIFT 6 3748 3749 /* MGT_TOP_CMN_CTLR :: io_ring_control :: gpio_opdr [05:05] */ 3750 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_GPIO_OPDR_MASK 0x0020 3751 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_GPIO_OPDR_ALIGN 0 3752 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_GPIO_OPDR_BITS 1 3753 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_GPIO_OPDR_SHIFT 5 3754 3755 /* MGT_TOP_CMN_CTLR :: io_ring_control :: modehv [04:04] */ 3756 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_MODEHV_MASK 0x0010 3757 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_MODEHV_ALIGN 0 3758 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_MODEHV_BITS 1 3759 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_MODEHV_SHIFT 4 3760 3761 /* MGT_TOP_CMN_CTLR :: io_ring_control :: reserved2 [03:02] */ 3762 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED2_MASK 0x000c 3763 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED2_ALIGN 0 3764 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED2_BITS 2 3765 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_RESERVED2_SHIFT 2 3766 3767 /* MGT_TOP_CMN_CTLR :: io_ring_control :: mdio_drv_lvl [01:00] */ 3768 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_MDIO_DRV_LVL_MASK 0x0003 3769 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_MDIO_DRV_LVL_ALIGN 0 3770 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_MDIO_DRV_LVL_BITS 2 3771 #define MGT_TOP_CMN_CTLR_IO_RING_CONTROL_MDIO_DRV_LVL_SHIFT 0 3772 3773 3774 /**************************************************************************** 3775 * MGT_TOP_CMN_CTLR :: charge_pump_control_1 3776 */ 3777 /* MGT_TOP_CMN_CTLR :: charge_pump_control_1 :: CP_rsvd_15_14 [15:14] */ 3778 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_RSVD_15_14_MASK 0xc000 3779 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_RSVD_15_14_ALIGN 0 3780 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_RSVD_15_14_BITS 2 3781 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_RSVD_15_14_SHIFT 14 3782 3783 /* MGT_TOP_CMN_CTLR :: charge_pump_control_1 :: CP_clk_sel [13:13] */ 3784 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_CLK_SEL_MASK 0x2000 3785 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_CLK_SEL_ALIGN 0 3786 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_CLK_SEL_BITS 1 3787 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_CLK_SEL_SHIFT 13 3788 3789 /* MGT_TOP_CMN_CTLR :: charge_pump_control_1 :: CP_bg_ctat [12:09] */ 3790 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_CTAT_MASK 0x1e00 3791 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_CTAT_ALIGN 0 3792 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_CTAT_BITS 4 3793 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_CTAT_SHIFT 9 3794 3795 /* MGT_TOP_CMN_CTLR :: charge_pump_control_1 :: CP_bg_trim [08:05] */ 3796 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_TRIM_MASK 0x01e0 3797 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_TRIM_ALIGN 0 3798 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_TRIM_BITS 4 3799 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_TRIM_SHIFT 5 3800 3801 /* MGT_TOP_CMN_CTLR :: charge_pump_control_1 :: CP_bg_ref_sel [04:04] */ 3802 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_REF_SEL_MASK 0x0010 3803 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_REF_SEL_ALIGN 0 3804 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_REF_SEL_BITS 1 3805 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_BG_REF_SEL_SHIFT 4 3806 3807 /* MGT_TOP_CMN_CTLR :: charge_pump_control_1 :: CP_vsel [03:01] */ 3808 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_VSEL_MASK 0x000e 3809 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_VSEL_ALIGN 0 3810 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_VSEL_BITS 3 3811 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_VSEL_SHIFT 1 3812 3813 /* MGT_TOP_CMN_CTLR :: charge_pump_control_1 :: CP_pd [00:00] */ 3814 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_PD_MASK 0x0001 3815 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_PD_ALIGN 0 3816 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_PD_BITS 1 3817 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_1_CP_PD_SHIFT 0 3818 3819 3820 /**************************************************************************** 3821 * MGT_TOP_CMN_CTLR :: charge_pump_control_2 3822 */ 3823 /* MGT_TOP_CMN_CTLR :: charge_pump_control_2 :: CP_rsvd_31_20 [15:04] */ 3824 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_RSVD_31_20_MASK 0xfff0 3825 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_RSVD_31_20_ALIGN 0 3826 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_RSVD_31_20_BITS 12 3827 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_RSVD_31_20_SHIFT 4 3828 3829 /* MGT_TOP_CMN_CTLR :: charge_pump_control_2 :: CP_spdup [03:03] */ 3830 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_SPDUP_MASK 0x0008 3831 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_SPDUP_ALIGN 0 3832 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_SPDUP_BITS 1 3833 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_SPDUP_SHIFT 3 3834 3835 /* MGT_TOP_CMN_CTLR :: charge_pump_control_2 :: CP_nol_sel [02:01] */ 3836 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_NOL_SEL_MASK 0x0006 3837 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_NOL_SEL_ALIGN 0 3838 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_NOL_SEL_BITS 2 3839 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_NOL_SEL_SHIFT 1 3840 3841 /* MGT_TOP_CMN_CTLR :: charge_pump_control_2 :: CP_hys_en [00:00] */ 3842 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_HYS_EN_MASK 0x0001 3843 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_HYS_EN_ALIGN 0 3844 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_HYS_EN_BITS 1 3845 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_2_CP_HYS_EN_SHIFT 0 3846 3847 3848 /**************************************************************************** 3849 * MGT_TOP_CMN_CTLR :: charge_pump_control_3 3850 */ 3851 /* MGT_TOP_CMN_CTLR :: charge_pump_control_3 :: CP_rsvd_47_37 [15:05] */ 3852 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_RSVD_47_37_MASK 0xffe0 3853 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_RSVD_47_37_ALIGN 0 3854 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_RSVD_47_37_BITS 11 3855 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_RSVD_47_37_SHIFT 5 3856 3857 /* MGT_TOP_CMN_CTLR :: charge_pump_control_3 :: CP_mux_sel [04:02] */ 3858 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_MUX_SEL_MASK 0x001c 3859 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_MUX_SEL_ALIGN 0 3860 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_MUX_SEL_BITS 3 3861 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_MUX_SEL_SHIFT 2 3862 3863 /* MGT_TOP_CMN_CTLR :: charge_pump_control_3 :: CP_test_en [01:01] */ 3864 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_TEST_EN_MASK 0x0002 3865 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_TEST_EN_ALIGN 0 3866 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_TEST_EN_BITS 1 3867 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_TEST_EN_SHIFT 1 3868 3869 /* MGT_TOP_CMN_CTLR :: charge_pump_control_3 :: CP_dis_pok [00:00] */ 3870 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_DIS_POK_MASK 0x0001 3871 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_DIS_POK_ALIGN 0 3872 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_DIS_POK_BITS 1 3873 #define MGT_TOP_CMN_CTLR_CHARGE_PUMP_CONTROL_3_CP_DIS_POK_SHIFT 0 3874 3875 3876 /**************************************************************************** 3877 * merlin_gallardo_mgt_top_blk_MGT_TOP_LK_MTR_TMR 3878 */ 3879 /**************************************************************************** 3880 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_0 3881 */ 3882 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_0 :: reserved0 [15:09] */ 3883 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_RESERVED0_MASK 0xfe00 3884 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_RESERVED0_ALIGN 0 3885 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_RESERVED0_BITS 7 3886 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_RESERVED0_SHIFT 9 3887 3888 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_0 :: timer_tc [08:08] */ 3889 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_TIMER_TC_MASK 0x0100 3890 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_TIMER_TC_ALIGN 0 3891 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_TIMER_TC_BITS 1 3892 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_TIMER_TC_SHIFT 8 3893 3894 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_0 :: reserved1 [07:01] */ 3895 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_RESERVED1_MASK 0x00fe 3896 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_RESERVED1_ALIGN 0 3897 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_RESERVED1_BITS 7 3898 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_RESERVED1_SHIFT 1 3899 3900 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_0 :: timer_en [00:00] */ 3901 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_TIMER_EN_MASK 0x0001 3902 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_TIMER_EN_ALIGN 0 3903 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_TIMER_EN_BITS 1 3904 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_0_TIMER_EN_SHIFT 0 3905 3906 3907 /**************************************************************************** 3908 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_0 3909 */ 3910 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_0 :: timer_count [15:00] */ 3911 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_0_TIMER_COUNT_MASK 0xffff 3912 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_0_TIMER_COUNT_ALIGN 0 3913 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_0_TIMER_COUNT_BITS 16 3914 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_0_TIMER_COUNT_SHIFT 0 3915 3916 3917 /**************************************************************************** 3918 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_1 3919 */ 3920 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_1 :: reserved0 [15:09] */ 3921 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_RESERVED0_MASK 0xfe00 3922 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_RESERVED0_ALIGN 0 3923 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_RESERVED0_BITS 7 3924 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_RESERVED0_SHIFT 9 3925 3926 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_1 :: timer_tc [08:08] */ 3927 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_TIMER_TC_MASK 0x0100 3928 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_TIMER_TC_ALIGN 0 3929 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_TIMER_TC_BITS 1 3930 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_TIMER_TC_SHIFT 8 3931 3932 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_1 :: reserved1 [07:01] */ 3933 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_RESERVED1_MASK 0x00fe 3934 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_RESERVED1_ALIGN 0 3935 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_RESERVED1_BITS 7 3936 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_RESERVED1_SHIFT 1 3937 3938 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_1 :: timer_en [00:00] */ 3939 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_TIMER_EN_MASK 0x0001 3940 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_TIMER_EN_ALIGN 0 3941 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_TIMER_EN_BITS 1 3942 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_1_TIMER_EN_SHIFT 0 3943 3944 3945 /**************************************************************************** 3946 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_1 3947 */ 3948 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_1 :: timer_count [15:00] */ 3949 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_1_TIMER_COUNT_MASK 0xffff 3950 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_1_TIMER_COUNT_ALIGN 0 3951 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_1_TIMER_COUNT_BITS 16 3952 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_1_TIMER_COUNT_SHIFT 0 3953 3954 3955 /**************************************************************************** 3956 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_2 3957 */ 3958 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_2 :: reserved0 [15:09] */ 3959 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_RESERVED0_MASK 0xfe00 3960 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_RESERVED0_ALIGN 0 3961 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_RESERVED0_BITS 7 3962 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_RESERVED0_SHIFT 9 3963 3964 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_2 :: timer_tc [08:08] */ 3965 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_TIMER_TC_MASK 0x0100 3966 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_TIMER_TC_ALIGN 0 3967 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_TIMER_TC_BITS 1 3968 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_TIMER_TC_SHIFT 8 3969 3970 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_2 :: reserved1 [07:01] */ 3971 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_RESERVED1_MASK 0x00fe 3972 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_RESERVED1_ALIGN 0 3973 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_RESERVED1_BITS 7 3974 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_RESERVED1_SHIFT 1 3975 3976 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_2 :: timer_en [00:00] */ 3977 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_TIMER_EN_MASK 0x0001 3978 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_TIMER_EN_ALIGN 0 3979 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_TIMER_EN_BITS 1 3980 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_2_TIMER_EN_SHIFT 0 3981 3982 3983 /**************************************************************************** 3984 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_2 3985 */ 3986 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_2 :: timer_count [15:00] */ 3987 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_2_TIMER_COUNT_MASK 0xffff 3988 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_2_TIMER_COUNT_ALIGN 0 3989 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_2_TIMER_COUNT_BITS 16 3990 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_2_TIMER_COUNT_SHIFT 0 3991 3992 3993 /**************************************************************************** 3994 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_3 3995 */ 3996 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_3 :: reserved0 [15:09] */ 3997 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_RESERVED0_MASK 0xfe00 3998 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_RESERVED0_ALIGN 0 3999 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_RESERVED0_BITS 7 4000 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_RESERVED0_SHIFT 9 4001 4002 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_3 :: timer_tc [08:08] */ 4003 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_TIMER_TC_MASK 0x0100 4004 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_TIMER_TC_ALIGN 0 4005 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_TIMER_TC_BITS 1 4006 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_TIMER_TC_SHIFT 8 4007 4008 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_3 :: reserved1 [07:01] */ 4009 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_RESERVED1_MASK 0x00fe 4010 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_RESERVED1_ALIGN 0 4011 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_RESERVED1_BITS 7 4012 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_RESERVED1_SHIFT 1 4013 4014 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_3 :: timer_en [00:00] */ 4015 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_TIMER_EN_MASK 0x0001 4016 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_TIMER_EN_ALIGN 0 4017 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_TIMER_EN_BITS 1 4018 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_3_TIMER_EN_SHIFT 0 4019 4020 4021 /**************************************************************************** 4022 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_3 4023 */ 4024 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_3 :: timer_count [15:00] */ 4025 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_3_TIMER_COUNT_MASK 0xffff 4026 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_3_TIMER_COUNT_ALIGN 0 4027 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_3_TIMER_COUNT_BITS 16 4028 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_3_TIMER_COUNT_SHIFT 0 4029 4030 4031 /**************************************************************************** 4032 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_4 4033 */ 4034 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_4 :: reserved0 [15:09] */ 4035 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_RESERVED0_MASK 0xfe00 4036 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_RESERVED0_ALIGN 0 4037 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_RESERVED0_BITS 7 4038 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_RESERVED0_SHIFT 9 4039 4040 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_4 :: timer_tc [08:08] */ 4041 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_TIMER_TC_MASK 0x0100 4042 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_TIMER_TC_ALIGN 0 4043 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_TIMER_TC_BITS 1 4044 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_TIMER_TC_SHIFT 8 4045 4046 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_4 :: reserved1 [07:01] */ 4047 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_RESERVED1_MASK 0x00fe 4048 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_RESERVED1_ALIGN 0 4049 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_RESERVED1_BITS 7 4050 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_RESERVED1_SHIFT 1 4051 4052 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_4 :: timer_en [00:00] */ 4053 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_TIMER_EN_MASK 0x0001 4054 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_TIMER_EN_ALIGN 0 4055 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_TIMER_EN_BITS 1 4056 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_4_TIMER_EN_SHIFT 0 4057 4058 4059 /**************************************************************************** 4060 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_4 4061 */ 4062 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_4 :: timer_count [15:00] */ 4063 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_4_TIMER_COUNT_MASK 0xffff 4064 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_4_TIMER_COUNT_ALIGN 0 4065 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_4_TIMER_COUNT_BITS 16 4066 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_4_TIMER_COUNT_SHIFT 0 4067 4068 4069 /**************************************************************************** 4070 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_5 4071 */ 4072 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_5 :: reserved0 [15:09] */ 4073 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_RESERVED0_MASK 0xfe00 4074 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_RESERVED0_ALIGN 0 4075 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_RESERVED0_BITS 7 4076 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_RESERVED0_SHIFT 9 4077 4078 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_5 :: timer_tc [08:08] */ 4079 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_TIMER_TC_MASK 0x0100 4080 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_TIMER_TC_ALIGN 0 4081 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_TIMER_TC_BITS 1 4082 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_TIMER_TC_SHIFT 8 4083 4084 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_5 :: reserved1 [07:01] */ 4085 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_RESERVED1_MASK 0x00fe 4086 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_RESERVED1_ALIGN 0 4087 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_RESERVED1_BITS 7 4088 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_RESERVED1_SHIFT 1 4089 4090 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_5 :: timer_en [00:00] */ 4091 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_TIMER_EN_MASK 0x0001 4092 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_TIMER_EN_ALIGN 0 4093 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_TIMER_EN_BITS 1 4094 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_5_TIMER_EN_SHIFT 0 4095 4096 4097 /**************************************************************************** 4098 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_5 4099 */ 4100 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_5 :: timer_count [15:00] */ 4101 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_5_TIMER_COUNT_MASK 0xffff 4102 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_5_TIMER_COUNT_ALIGN 0 4103 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_5_TIMER_COUNT_BITS 16 4104 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_5_TIMER_COUNT_SHIFT 0 4105 4106 4107 /**************************************************************************** 4108 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_6 4109 */ 4110 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_6 :: reserved0 [15:09] */ 4111 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_RESERVED0_MASK 0xfe00 4112 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_RESERVED0_ALIGN 0 4113 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_RESERVED0_BITS 7 4114 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_RESERVED0_SHIFT 9 4115 4116 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_6 :: timer_tc [08:08] */ 4117 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_TIMER_TC_MASK 0x0100 4118 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_TIMER_TC_ALIGN 0 4119 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_TIMER_TC_BITS 1 4120 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_TIMER_TC_SHIFT 8 4121 4122 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_6 :: reserved1 [07:01] */ 4123 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_RESERVED1_MASK 0x00fe 4124 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_RESERVED1_ALIGN 0 4125 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_RESERVED1_BITS 7 4126 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_RESERVED1_SHIFT 1 4127 4128 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_6 :: timer_en [00:00] */ 4129 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_TIMER_EN_MASK 0x0001 4130 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_TIMER_EN_ALIGN 0 4131 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_TIMER_EN_BITS 1 4132 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_6_TIMER_EN_SHIFT 0 4133 4134 4135 /**************************************************************************** 4136 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_6 4137 */ 4138 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_6 :: timer_count [15:00] */ 4139 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_6_TIMER_COUNT_MASK 0xffff 4140 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_6_TIMER_COUNT_ALIGN 0 4141 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_6_TIMER_COUNT_BITS 16 4142 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_6_TIMER_COUNT_SHIFT 0 4143 4144 4145 /**************************************************************************** 4146 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_7 4147 */ 4148 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_7 :: reserved0 [15:09] */ 4149 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_RESERVED0_MASK 0xfe00 4150 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_RESERVED0_ALIGN 0 4151 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_RESERVED0_BITS 7 4152 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_RESERVED0_SHIFT 9 4153 4154 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_7 :: timer_tc [08:08] */ 4155 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_TIMER_TC_MASK 0x0100 4156 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_TIMER_TC_ALIGN 0 4157 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_TIMER_TC_BITS 1 4158 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_TIMER_TC_SHIFT 8 4159 4160 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_7 :: reserved1 [07:01] */ 4161 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_RESERVED1_MASK 0x00fe 4162 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_RESERVED1_ALIGN 0 4163 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_RESERVED1_BITS 7 4164 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_RESERVED1_SHIFT 1 4165 4166 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_control_status_register_7 :: timer_en [00:00] */ 4167 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_TIMER_EN_MASK 0x0001 4168 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_TIMER_EN_ALIGN 0 4169 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_TIMER_EN_BITS 1 4170 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_CONTROL_STATUS_REGISTER_7_TIMER_EN_SHIFT 0 4171 4172 4173 /**************************************************************************** 4174 * MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_7 4175 */ 4176 /* MGT_TOP_LK_MTR_TMR :: link_mon_timer_count_register_7 :: timer_count [15:00] */ 4177 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_7_TIMER_COUNT_MASK 0xffff 4178 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_7_TIMER_COUNT_ALIGN 0 4179 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_7_TIMER_COUNT_BITS 16 4180 #define MGT_TOP_LK_MTR_TMR_LINK_MON_TIMER_COUNT_REGISTER_7_TIMER_COUNT_SHIFT 0 4181 4182 4183 /**************************************************************************** 4184 * merlin_gallardo_qsfi_blk_QSFI_IEEE0 4185 */ 4186 /**************************************************************************** 4187 * QSFI_IEEE0 :: pmd_control_register 4188 */ 4189 /* QSFI_IEEE0 :: pmd_control_register :: reset [15:15] */ 4190 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESET_MASK 0x8000 4191 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESET_ALIGN 0 4192 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESET_BITS 1 4193 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESET_SHIFT 15 4194 4195 /* QSFI_IEEE0 :: pmd_control_register :: reserved0 [14:14] */ 4196 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED0_MASK 0x4000 4197 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED0_ALIGN 0 4198 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED0_BITS 1 4199 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED0_SHIFT 14 4200 4201 /* QSFI_IEEE0 :: pmd_control_register :: speed_selectionlsb [13:13] */ 4202 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_MASK 0x2000 4203 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_ALIGN 0 4204 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_BITS 1 4205 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTIONLSB_SHIFT 13 4206 4207 /* QSFI_IEEE0 :: pmd_control_register :: reserved1 [12:12] */ 4208 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED1_MASK 0x1000 4209 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED1_ALIGN 0 4210 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED1_BITS 1 4211 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED1_SHIFT 12 4212 4213 /* QSFI_IEEE0 :: pmd_control_register :: power_down [11:11] */ 4214 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_POWER_DOWN_MASK 0x0800 4215 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_POWER_DOWN_ALIGN 0 4216 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_POWER_DOWN_BITS 1 4217 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_POWER_DOWN_SHIFT 11 4218 4219 /* QSFI_IEEE0 :: pmd_control_register :: reserved2 [10:07] */ 4220 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED2_MASK 0x0780 4221 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED2_ALIGN 0 4222 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED2_BITS 4 4223 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_RESERVED2_SHIFT 7 4224 4225 /* QSFI_IEEE0 :: pmd_control_register :: speed_selectionmsb [06:06] */ 4226 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_MASK 0x0040 4227 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_ALIGN 0 4228 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_BITS 1 4229 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTIONMSB_SHIFT 6 4230 4231 /* QSFI_IEEE0 :: pmd_control_register :: speed_selection [05:02] */ 4232 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTION_MASK 0x003c 4233 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTION_ALIGN 0 4234 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTION_BITS 4 4235 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_SPEED_SELECTION_SHIFT 2 4236 4237 /* QSFI_IEEE0 :: pmd_control_register :: pma_remote_loopback [01:01] */ 4238 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_PMA_REMOTE_LOOPBACK_MASK 0x0002 4239 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_PMA_REMOTE_LOOPBACK_ALIGN 0 4240 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_PMA_REMOTE_LOOPBACK_BITS 1 4241 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_PMA_REMOTE_LOOPBACK_SHIFT 1 4242 4243 /* QSFI_IEEE0 :: pmd_control_register :: pma_loopback [00:00] */ 4244 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_PMA_LOOPBACK_MASK 0x0001 4245 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_PMA_LOOPBACK_ALIGN 0 4246 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_PMA_LOOPBACK_BITS 1 4247 #define QSFI_IEEE0_PMD_CONTROL_REGISTER_PMA_LOOPBACK_SHIFT 0 4248 4249 4250 /**************************************************************************** 4251 * QSFI_IEEE0 :: status_register 4252 */ 4253 /* QSFI_IEEE0 :: status_register :: reserved0 [15:08] */ 4254 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED0_MASK 0xff00 4255 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED0_ALIGN 0 4256 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED0_BITS 8 4257 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED0_SHIFT 8 4258 4259 /* QSFI_IEEE0 :: status_register :: fault [07:07] */ 4260 #define QSFI_IEEE0_STATUS_REGISTER_FAULT_MASK 0x0080 4261 #define QSFI_IEEE0_STATUS_REGISTER_FAULT_ALIGN 0 4262 #define QSFI_IEEE0_STATUS_REGISTER_FAULT_BITS 1 4263 #define QSFI_IEEE0_STATUS_REGISTER_FAULT_SHIFT 7 4264 4265 /* QSFI_IEEE0 :: status_register :: reserved1 [06:03] */ 4266 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED1_MASK 0x0078 4267 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED1_ALIGN 0 4268 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED1_BITS 4 4269 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED1_SHIFT 3 4270 4271 /* QSFI_IEEE0 :: status_register :: receive_link_status [02:02] */ 4272 #define QSFI_IEEE0_STATUS_REGISTER_RECEIVE_LINK_STATUS_MASK 0x0004 4273 #define QSFI_IEEE0_STATUS_REGISTER_RECEIVE_LINK_STATUS_ALIGN 0 4274 #define QSFI_IEEE0_STATUS_REGISTER_RECEIVE_LINK_STATUS_BITS 1 4275 #define QSFI_IEEE0_STATUS_REGISTER_RECEIVE_LINK_STATUS_SHIFT 2 4276 4277 /* QSFI_IEEE0 :: status_register :: low_power_ability [01:01] */ 4278 #define QSFI_IEEE0_STATUS_REGISTER_LOW_POWER_ABILITY_MASK 0x0002 4279 #define QSFI_IEEE0_STATUS_REGISTER_LOW_POWER_ABILITY_ALIGN 0 4280 #define QSFI_IEEE0_STATUS_REGISTER_LOW_POWER_ABILITY_BITS 1 4281 #define QSFI_IEEE0_STATUS_REGISTER_LOW_POWER_ABILITY_SHIFT 1 4282 4283 /* QSFI_IEEE0 :: status_register :: reserved2 [00:00] */ 4284 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED2_MASK 0x0001 4285 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED2_ALIGN 0 4286 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED2_BITS 1 4287 #define QSFI_IEEE0_STATUS_REGISTER_RESERVED2_SHIFT 0 4288 4289 4290 /**************************************************************************** 4291 * QSFI_IEEE0 :: pmd_identifier_register_0 4292 */ 4293 /* QSFI_IEEE0 :: pmd_identifier_register_0 :: device_id_0 [15:00] */ 4294 #define QSFI_IEEE0_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_MASK 0xffff 4295 #define QSFI_IEEE0_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_ALIGN 0 4296 #define QSFI_IEEE0_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_BITS 16 4297 #define QSFI_IEEE0_PMD_IDENTIFIER_REGISTER_0_DEVICE_ID_0_SHIFT 0 4298 4299 4300 /**************************************************************************** 4301 * QSFI_IEEE0 :: pmd_identifier_register_1 4302 */ 4303 /* QSFI_IEEE0 :: pmd_identifier_register_1 :: device_id_1 [15:00] */ 4304 #define QSFI_IEEE0_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_MASK 0xffff 4305 #define QSFI_IEEE0_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_ALIGN 0 4306 #define QSFI_IEEE0_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_BITS 16 4307 #define QSFI_IEEE0_PMD_IDENTIFIER_REGISTER_1_DEVICE_ID_1_SHIFT 0 4308 4309 4310 /**************************************************************************** 4311 * QSFI_IEEE0 :: pmd_speed_ability 4312 */ 4313 /* QSFI_IEEE0 :: pmd_speed_ability :: reserved0 [15:10] */ 4314 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED0_MASK 0xfc00 4315 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED0_ALIGN 0 4316 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED0_BITS 6 4317 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED0_SHIFT 10 4318 4319 /* QSFI_IEEE0 :: pmd_speed_ability :: one_hundredG_capable [09:09] */ 4320 #define QSFI_IEEE0_PMD_SPEED_ABILITY_ONE_HUNDREDG_CAPABLE_MASK 0x0200 4321 #define QSFI_IEEE0_PMD_SPEED_ABILITY_ONE_HUNDREDG_CAPABLE_ALIGN 0 4322 #define QSFI_IEEE0_PMD_SPEED_ABILITY_ONE_HUNDREDG_CAPABLE_BITS 1 4323 #define QSFI_IEEE0_PMD_SPEED_ABILITY_ONE_HUNDREDG_CAPABLE_SHIFT 9 4324 4325 /* QSFI_IEEE0 :: pmd_speed_ability :: fortyG_capable [08:08] */ 4326 #define QSFI_IEEE0_PMD_SPEED_ABILITY_FORTYG_CAPABLE_MASK 0x0100 4327 #define QSFI_IEEE0_PMD_SPEED_ABILITY_FORTYG_CAPABLE_ALIGN 0 4328 #define QSFI_IEEE0_PMD_SPEED_ABILITY_FORTYG_CAPABLE_BITS 1 4329 #define QSFI_IEEE0_PMD_SPEED_ABILITY_FORTYG_CAPABLE_SHIFT 8 4330 4331 /* QSFI_IEEE0 :: pmd_speed_ability :: reserved1 [07:05] */ 4332 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED1_MASK 0x00e0 4333 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED1_ALIGN 0 4334 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED1_BITS 3 4335 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED1_SHIFT 5 4336 4337 /* QSFI_IEEE0 :: pmd_speed_ability :: oneG_capable [04:04] */ 4338 #define QSFI_IEEE0_PMD_SPEED_ABILITY_ONEG_CAPABLE_MASK 0x0010 4339 #define QSFI_IEEE0_PMD_SPEED_ABILITY_ONEG_CAPABLE_ALIGN 0 4340 #define QSFI_IEEE0_PMD_SPEED_ABILITY_ONEG_CAPABLE_BITS 1 4341 #define QSFI_IEEE0_PMD_SPEED_ABILITY_ONEG_CAPABLE_SHIFT 4 4342 4343 /* QSFI_IEEE0 :: pmd_speed_ability :: reserved2 [03:01] */ 4344 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED2_MASK 0x000e 4345 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED2_ALIGN 0 4346 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED2_BITS 3 4347 #define QSFI_IEEE0_PMD_SPEED_ABILITY_RESERVED2_SHIFT 1 4348 4349 /* QSFI_IEEE0 :: pmd_speed_ability :: tenG_capable [00:00] */ 4350 #define QSFI_IEEE0_PMD_SPEED_ABILITY_TENG_CAPABLE_MASK 0x0001 4351 #define QSFI_IEEE0_PMD_SPEED_ABILITY_TENG_CAPABLE_ALIGN 0 4352 #define QSFI_IEEE0_PMD_SPEED_ABILITY_TENG_CAPABLE_BITS 1 4353 #define QSFI_IEEE0_PMD_SPEED_ABILITY_TENG_CAPABLE_SHIFT 0 4354 4355 4356 /**************************************************************************** 4357 * QSFI_IEEE0 :: devices_in_package_1 4358 */ 4359 /* QSFI_IEEE0 :: devices_in_package_1 :: reserved0 [15:12] */ 4360 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_RESERVED0_MASK 0xf000 4361 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_RESERVED0_ALIGN 0 4362 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_RESERVED0_BITS 4 4363 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_RESERVED0_SHIFT 12 4364 4365 /* QSFI_IEEE0 :: devices_in_package_1 :: Seperate_PMA_4_Present [11:11] */ 4366 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_4_PRESENT_MASK 0x0800 4367 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_4_PRESENT_ALIGN 0 4368 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_4_PRESENT_BITS 1 4369 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_4_PRESENT_SHIFT 11 4370 4371 /* QSFI_IEEE0 :: devices_in_package_1 :: Seperate_PMA_3_Present [10:10] */ 4372 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_3_PRESENT_MASK 0x0400 4373 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_3_PRESENT_ALIGN 0 4374 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_3_PRESENT_BITS 1 4375 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_3_PRESENT_SHIFT 10 4376 4377 /* QSFI_IEEE0 :: devices_in_package_1 :: Seperate_PMA_2_Present [09:09] */ 4378 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_2_PRESENT_MASK 0x0200 4379 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_2_PRESENT_ALIGN 0 4380 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_2_PRESENT_BITS 1 4381 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_2_PRESENT_SHIFT 9 4382 4383 /* QSFI_IEEE0 :: devices_in_package_1 :: Seperate_PMA_1_Present [08:08] */ 4384 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_1_PRESENT_MASK 0x0100 4385 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_1_PRESENT_ALIGN 0 4386 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_1_PRESENT_BITS 1 4387 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_SEPERATE_PMA_1_PRESENT_SHIFT 8 4388 4389 /* QSFI_IEEE0 :: devices_in_package_1 :: an_present [07:07] */ 4390 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_AN_PRESENT_MASK 0x0080 4391 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_AN_PRESENT_ALIGN 0 4392 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_AN_PRESENT_BITS 1 4393 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_AN_PRESENT_SHIFT 7 4394 4395 /* QSFI_IEEE0 :: devices_in_package_1 :: tc_present [06:06] */ 4396 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_TC_PRESENT_MASK 0x0040 4397 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_TC_PRESENT_ALIGN 0 4398 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_TC_PRESENT_BITS 1 4399 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_TC_PRESENT_SHIFT 6 4400 4401 /* QSFI_IEEE0 :: devices_in_package_1 :: dte_xs_present [05:05] */ 4402 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_DTE_XS_PRESENT_MASK 0x0020 4403 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_DTE_XS_PRESENT_ALIGN 0 4404 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_DTE_XS_PRESENT_BITS 1 4405 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_DTE_XS_PRESENT_SHIFT 5 4406 4407 /* QSFI_IEEE0 :: devices_in_package_1 :: phy_xs_present [04:04] */ 4408 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PHY_XS_PRESENT_MASK 0x0010 4409 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PHY_XS_PRESENT_ALIGN 0 4410 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PHY_XS_PRESENT_BITS 1 4411 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PHY_XS_PRESENT_SHIFT 4 4412 4413 /* QSFI_IEEE0 :: devices_in_package_1 :: pcs_present [03:03] */ 4414 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PCS_PRESENT_MASK 0x0008 4415 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PCS_PRESENT_ALIGN 0 4416 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PCS_PRESENT_BITS 1 4417 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PCS_PRESENT_SHIFT 3 4418 4419 /* QSFI_IEEE0 :: devices_in_package_1 :: wis_present [02:02] */ 4420 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_WIS_PRESENT_MASK 0x0004 4421 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_WIS_PRESENT_ALIGN 0 4422 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_WIS_PRESENT_BITS 1 4423 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_WIS_PRESENT_SHIFT 2 4424 4425 /* QSFI_IEEE0 :: devices_in_package_1 :: pmd_pma_present [01:01] */ 4426 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PMD_PMA_PRESENT_MASK 0x0002 4427 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PMD_PMA_PRESENT_ALIGN 0 4428 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PMD_PMA_PRESENT_BITS 1 4429 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_PMD_PMA_PRESENT_SHIFT 1 4430 4431 /* QSFI_IEEE0 :: devices_in_package_1 :: clause_22registers_present [00:00] */ 4432 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_CLAUSE_22REGISTERS_PRESENT_MASK 0x0001 4433 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_CLAUSE_22REGISTERS_PRESENT_ALIGN 0 4434 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_CLAUSE_22REGISTERS_PRESENT_BITS 1 4435 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_1_CLAUSE_22REGISTERS_PRESENT_SHIFT 0 4436 4437 4438 /**************************************************************************** 4439 * QSFI_IEEE0 :: devices_in_package_2 4440 */ 4441 /* QSFI_IEEE0 :: devices_in_package_2 :: vendor_specificdevice_2_present [15:15] */ 4442 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_MASK 0x8000 4443 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_ALIGN 0 4444 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_BITS 1 4445 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_2_PRESENT_SHIFT 15 4446 4447 /* QSFI_IEEE0 :: devices_in_package_2 :: vendor_specificdevice_1_present [14:14] */ 4448 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_MASK 0x4000 4449 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_ALIGN 0 4450 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_BITS 1 4451 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_VENDOR_SPECIFICDEVICE_1_PRESENT_SHIFT 14 4452 4453 /* QSFI_IEEE0 :: devices_in_package_2 :: clause_22extension_present [13:13] */ 4454 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_MASK 0x2000 4455 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_ALIGN 0 4456 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_BITS 1 4457 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_CLAUSE_22EXTENSION_PRESENT_SHIFT 13 4458 4459 /* QSFI_IEEE0 :: devices_in_package_2 :: reserved0 [12:00] */ 4460 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_RESERVED0_MASK 0x1fff 4461 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_RESERVED0_ALIGN 0 4462 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_RESERVED0_BITS 13 4463 #define QSFI_IEEE0_DEVICES_IN_PACKAGE_2_RESERVED0_SHIFT 0 4464 4465 4466 /**************************************************************************** 4467 * QSFI_IEEE0 :: pmd_control_2_register 4468 */ 4469 /* QSFI_IEEE0 :: pmd_control_2_register :: reserved0 [15:06] */ 4470 #define QSFI_IEEE0_PMD_CONTROL_2_REGISTER_RESERVED0_MASK 0xffc0 4471 #define QSFI_IEEE0_PMD_CONTROL_2_REGISTER_RESERVED0_ALIGN 0 4472 #define QSFI_IEEE0_PMD_CONTROL_2_REGISTER_RESERVED0_BITS 10 4473 #define QSFI_IEEE0_PMD_CONTROL_2_REGISTER_RESERVED0_SHIFT 6 4474 4475 /* QSFI_IEEE0 :: pmd_control_2_register :: pma_typeselection [05:00] */ 4476 #define QSFI_IEEE0_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_MASK 0x003f 4477 #define QSFI_IEEE0_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_ALIGN 0 4478 #define QSFI_IEEE0_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_BITS 6 4479 #define QSFI_IEEE0_PMD_CONTROL_2_REGISTER_PMA_TYPESELECTION_SHIFT 0 4480 4481 4482 /**************************************************************************** 4483 * QSFI_IEEE0 :: status_register_2 4484 */ 4485 /* QSFI_IEEE0 :: status_register_2 :: device_present [15:14] */ 4486 #define QSFI_IEEE0_STATUS_REGISTER_2_DEVICE_PRESENT_MASK 0xc000 4487 #define QSFI_IEEE0_STATUS_REGISTER_2_DEVICE_PRESENT_ALIGN 0 4488 #define QSFI_IEEE0_STATUS_REGISTER_2_DEVICE_PRESENT_BITS 2 4489 #define QSFI_IEEE0_STATUS_REGISTER_2_DEVICE_PRESENT_SHIFT 14 4490 4491 /* QSFI_IEEE0 :: status_register_2 :: transmit_localfault_ability [13:13] */ 4492 #define QSFI_IEEE0_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_MASK 0x2000 4493 #define QSFI_IEEE0_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_ALIGN 0 4494 #define QSFI_IEEE0_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_BITS 1 4495 #define QSFI_IEEE0_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ABILITY_SHIFT 13 4496 4497 /* QSFI_IEEE0 :: status_register_2 :: receive_localfault_ability [12:12] */ 4498 #define QSFI_IEEE0_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_MASK 0x1000 4499 #define QSFI_IEEE0_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_ALIGN 0 4500 #define QSFI_IEEE0_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_BITS 1 4501 #define QSFI_IEEE0_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ABILITY_SHIFT 12 4502 4503 /* QSFI_IEEE0 :: status_register_2 :: transmit_localfault [11:11] */ 4504 #define QSFI_IEEE0_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_MASK 0x0800 4505 #define QSFI_IEEE0_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_ALIGN 0 4506 #define QSFI_IEEE0_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_BITS 1 4507 #define QSFI_IEEE0_STATUS_REGISTER_2_TRANSMIT_LOCALFAULT_SHIFT 11 4508 4509 /* QSFI_IEEE0 :: status_register_2 :: receive_localfault [10:10] */ 4510 #define QSFI_IEEE0_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_MASK 0x0400 4511 #define QSFI_IEEE0_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_ALIGN 0 4512 #define QSFI_IEEE0_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_BITS 1 4513 #define QSFI_IEEE0_STATUS_REGISTER_2_RECEIVE_LOCALFAULT_SHIFT 10 4514 4515 /* QSFI_IEEE0 :: status_register_2 :: extended_abilities [09:09] */ 4516 #define QSFI_IEEE0_STATUS_REGISTER_2_EXTENDED_ABILITIES_MASK 0x0200 4517 #define QSFI_IEEE0_STATUS_REGISTER_2_EXTENDED_ABILITIES_ALIGN 0 4518 #define QSFI_IEEE0_STATUS_REGISTER_2_EXTENDED_ABILITIES_BITS 1 4519 #define QSFI_IEEE0_STATUS_REGISTER_2_EXTENDED_ABILITIES_SHIFT 9 4520 4521 /* QSFI_IEEE0 :: status_register_2 :: pmd_transmitdisable_ability [08:08] */ 4522 #define QSFI_IEEE0_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_MASK 0x0100 4523 #define QSFI_IEEE0_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_ALIGN 0 4524 #define QSFI_IEEE0_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_BITS 1 4525 #define QSFI_IEEE0_STATUS_REGISTER_2_PMD_TRANSMITDISABLE_ABILITY_SHIFT 8 4526 4527 /* QSFI_IEEE0 :: status_register_2 :: tengbase_sr_ability [07:07] */ 4528 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_SR_ABILITY_MASK 0x0080 4529 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_SR_ABILITY_ALIGN 0 4530 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_SR_ABILITY_BITS 1 4531 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_SR_ABILITY_SHIFT 7 4532 4533 /* QSFI_IEEE0 :: status_register_2 :: tengbase_lr_ability [06:06] */ 4534 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LR_ABILITY_MASK 0x0040 4535 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LR_ABILITY_ALIGN 0 4536 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LR_ABILITY_BITS 1 4537 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LR_ABILITY_SHIFT 6 4538 4539 /* QSFI_IEEE0 :: status_register_2 :: tengbase_er_ability [05:05] */ 4540 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_ER_ABILITY_MASK 0x0020 4541 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_ER_ABILITY_ALIGN 0 4542 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_ER_ABILITY_BITS 1 4543 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_ER_ABILITY_SHIFT 5 4544 4545 /* QSFI_IEEE0 :: status_register_2 :: tengbase_lx4_ability [04:04] */ 4546 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LX4_ABILITY_MASK 0x0010 4547 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LX4_ABILITY_ALIGN 0 4548 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LX4_ABILITY_BITS 1 4549 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LX4_ABILITY_SHIFT 4 4550 4551 /* QSFI_IEEE0 :: status_register_2 :: tengbase_sw_ability [03:03] */ 4552 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_SW_ABILITY_MASK 0x0008 4553 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_SW_ABILITY_ALIGN 0 4554 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_SW_ABILITY_BITS 1 4555 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_SW_ABILITY_SHIFT 3 4556 4557 /* QSFI_IEEE0 :: status_register_2 :: tengbase_lw_ability [02:02] */ 4558 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LW_ABILITY_MASK 0x0004 4559 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LW_ABILITY_ALIGN 0 4560 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LW_ABILITY_BITS 1 4561 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_LW_ABILITY_SHIFT 2 4562 4563 /* QSFI_IEEE0 :: status_register_2 :: tengbase_ew_ability [01:01] */ 4564 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_EW_ABILITY_MASK 0x0002 4565 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_EW_ABILITY_ALIGN 0 4566 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_EW_ABILITY_BITS 1 4567 #define QSFI_IEEE0_STATUS_REGISTER_2_TENGBASE_EW_ABILITY_SHIFT 1 4568 4569 /* QSFI_IEEE0 :: status_register_2 :: pma_local_loopback_ability [00:00] */ 4570 #define QSFI_IEEE0_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACK_ABILITY_MASK 0x0001 4571 #define QSFI_IEEE0_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACK_ABILITY_ALIGN 0 4572 #define QSFI_IEEE0_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACK_ABILITY_BITS 1 4573 #define QSFI_IEEE0_STATUS_REGISTER_2_PMA_LOCAL_LOOPBACK_ABILITY_SHIFT 0 4574 4575 4576 /**************************************************************************** 4577 * QSFI_IEEE0 :: pmd_transmit_disable_register 4578 */ 4579 /* QSFI_IEEE0 :: pmd_transmit_disable_register :: reserved0 [15:05] */ 4580 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_RESERVED0_MASK 0xffe0 4581 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_RESERVED0_ALIGN 0 4582 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_RESERVED0_BITS 11 4583 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_RESERVED0_SHIFT 5 4584 4585 /* QSFI_IEEE0 :: pmd_transmit_disable_register :: pmd_transmitdisable_3 [04:04] */ 4586 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_3_MASK 0x0010 4587 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_3_ALIGN 0 4588 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_3_BITS 1 4589 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_3_SHIFT 4 4590 4591 /* QSFI_IEEE0 :: pmd_transmit_disable_register :: pmd_transmitdisable_2 [03:03] */ 4592 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_2_MASK 0x0008 4593 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_2_ALIGN 0 4594 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_2_BITS 1 4595 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_2_SHIFT 3 4596 4597 /* QSFI_IEEE0 :: pmd_transmit_disable_register :: pmd_transmitdisable_1 [02:02] */ 4598 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_1_MASK 0x0004 4599 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_1_ALIGN 0 4600 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_1_BITS 1 4601 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_1_SHIFT 2 4602 4603 /* QSFI_IEEE0 :: pmd_transmit_disable_register :: pmd_transmitdisable_0 [01:01] */ 4604 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_0_MASK 0x0002 4605 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_0_ALIGN 0 4606 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_0_BITS 1 4607 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_PMD_TRANSMITDISABLE_0_SHIFT 1 4608 4609 /* QSFI_IEEE0 :: pmd_transmit_disable_register :: global_pmdtransmit_disable [00:00] */ 4610 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_GLOBAL_PMDTRANSMIT_DISABLE_MASK 0x0001 4611 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_GLOBAL_PMDTRANSMIT_DISABLE_ALIGN 0 4612 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_GLOBAL_PMDTRANSMIT_DISABLE_BITS 1 4613 #define QSFI_IEEE0_PMD_TRANSMIT_DISABLE_REGISTER_GLOBAL_PMDTRANSMIT_DISABLE_SHIFT 0 4614 4615 4616 /**************************************************************************** 4617 * QSFI_IEEE0 :: pmd_receive_signal_detect_register 4618 */ 4619 /* QSFI_IEEE0 :: pmd_receive_signal_detect_register :: reserved0 [15:05] */ 4620 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_MASK 0xffe0 4621 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_ALIGN 0 4622 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_BITS 11 4623 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_RESERVED0_SHIFT 5 4624 4625 /* QSFI_IEEE0 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_3 [04:04] */ 4626 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_MASK 0x0010 4627 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_ALIGN 0 4628 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_BITS 1 4629 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_3_SHIFT 4 4630 4631 /* QSFI_IEEE0 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_2 [03:03] */ 4632 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_MASK 0x0008 4633 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_ALIGN 0 4634 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_BITS 1 4635 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_2_SHIFT 3 4636 4637 /* QSFI_IEEE0 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_1 [02:02] */ 4638 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_MASK 0x0004 4639 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_ALIGN 0 4640 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_BITS 1 4641 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_1_SHIFT 2 4642 4643 /* QSFI_IEEE0 :: pmd_receive_signal_detect_register :: pmd_receivesignal_detect_0 [01:01] */ 4644 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_MASK 0x0002 4645 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_ALIGN 0 4646 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_BITS 1 4647 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_PMD_RECEIVESIGNAL_DETECT_0_SHIFT 1 4648 4649 /* QSFI_IEEE0 :: pmd_receive_signal_detect_register :: global_pmdreceive_signal_ok [00:00] */ 4650 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_MASK 0x0001 4651 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_ALIGN 0 4652 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_BITS 1 4653 #define QSFI_IEEE0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_GLOBAL_PMDRECEIVE_SIGNAL_OK_SHIFT 0 4654 4655 4656 /**************************************************************************** 4657 * QSFI_IEEE0 :: pmd_extended_ability_register 4658 */ 4659 /* QSFI_IEEE0 :: pmd_extended_ability_register :: reserved0 [15:11] */ 4660 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_MASK 0xf800 4661 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_ALIGN 0 4662 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_BITS 5 4663 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_SHIFT 11 4664 4665 /* QSFI_IEEE0 :: pmd_extended_ability_register :: fortygbase_ability [10:10] */ 4666 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_ABILITY_MASK 0x0400 4667 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_ABILITY_ALIGN 0 4668 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_ABILITY_BITS 1 4669 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_ABILITY_SHIFT 10 4670 4671 /* QSFI_IEEE0 :: pmd_extended_ability_register :: reserved1 [09:09] */ 4672 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_MASK 0x0200 4673 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_ALIGN 0 4674 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_BITS 1 4675 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_SHIFT 9 4676 4677 /* QSFI_IEEE0 :: pmd_extended_ability_register :: tenbase_t_ability [08:08] */ 4678 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_T_ABILITY_MASK 0x0100 4679 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_T_ABILITY_ALIGN 0 4680 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_T_ABILITY_BITS 1 4681 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENBASE_T_ABILITY_SHIFT 8 4682 4683 /* QSFI_IEEE0 :: pmd_extended_ability_register :: hundredbase_tx_ability [07:07] */ 4684 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_MASK 0x0080 4685 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_ALIGN 0 4686 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_BITS 1 4687 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_HUNDREDBASE_TX_ABILITY_SHIFT 7 4688 4689 /* QSFI_IEEE0 :: pmd_extended_ability_register :: gigbase_kx_ability [06:06] */ 4690 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KX_ABILITY_MASK 0x0040 4691 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KX_ABILITY_ALIGN 0 4692 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KX_ABILITY_BITS 1 4693 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_KX_ABILITY_SHIFT 6 4694 4695 /* QSFI_IEEE0 :: pmd_extended_ability_register :: gigbase_t_ability [05:05] */ 4696 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_T_ABILITY_MASK 0x0020 4697 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_T_ABILITY_ALIGN 0 4698 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_T_ABILITY_BITS 1 4699 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_GIGBASE_T_ABILITY_SHIFT 5 4700 4701 /* QSFI_IEEE0 :: pmd_extended_ability_register :: tengbase_kr_ability [04:04] */ 4702 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KR_ABILITY_MASK 0x0010 4703 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KR_ABILITY_ALIGN 0 4704 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KR_ABILITY_BITS 1 4705 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KR_ABILITY_SHIFT 4 4706 4707 /* QSFI_IEEE0 :: pmd_extended_ability_register :: tengbase_kx4_ability [03:03] */ 4708 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4_ABILITY_MASK 0x0008 4709 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4_ABILITY_ALIGN 0 4710 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4_ABILITY_BITS 1 4711 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_KX4_ABILITY_SHIFT 3 4712 4713 /* QSFI_IEEE0 :: pmd_extended_ability_register :: tengbase_t_ability [02:02] */ 4714 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_T_ABILITY_MASK 0x0004 4715 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_T_ABILITY_ALIGN 0 4716 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_T_ABILITY_BITS 1 4717 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_T_ABILITY_SHIFT 2 4718 4719 /* QSFI_IEEE0 :: pmd_extended_ability_register :: tengbase_lrm_ability [01:01] */ 4720 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRM_ABILITY_MASK 0x0002 4721 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRM_ABILITY_ALIGN 0 4722 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRM_ABILITY_BITS 1 4723 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_LRM_ABILITY_SHIFT 1 4724 4725 /* QSFI_IEEE0 :: pmd_extended_ability_register :: tengbase_cx4_ability [00:00] */ 4726 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4_ABILITY_MASK 0x0001 4727 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4_ABILITY_ALIGN 0 4728 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4_ABILITY_BITS 1 4729 #define QSFI_IEEE0_PMD_EXTENDED_ABILITY_REGISTER_TENGBASE_CX4_ABILITY_SHIFT 0 4730 4731 4732 /**************************************************************************** 4733 * QSFI_IEEE0 :: fortyg_pmd_extended_ability_register 4734 */ 4735 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: PMA_remote_loopback_Ability [15:15] */ 4736 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_PMA_REMOTE_LOOPBACK_ABILITY_MASK 0x8000 4737 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_PMA_REMOTE_LOOPBACK_ABILITY_ALIGN 0 4738 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_PMA_REMOTE_LOOPBACK_ABILITY_BITS 1 4739 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_PMA_REMOTE_LOOPBACK_ABILITY_SHIFT 15 4740 4741 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: reserved0 [14:12] */ 4742 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_MASK 0x7000 4743 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_ALIGN 0 4744 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_BITS 3 4745 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED0_SHIFT 12 4746 4747 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: one_hundredgbase_ER4_ability [11:11] */ 4748 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_ER4_ABILITY_MASK 0x0800 4749 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_ER4_ABILITY_ALIGN 0 4750 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_ER4_ABILITY_BITS 1 4751 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_ER4_ABILITY_SHIFT 11 4752 4753 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: one_hundredgbase_LR4_ability [10:10] */ 4754 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_LR4_ABILITY_MASK 0x0400 4755 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_LR4_ABILITY_ALIGN 0 4756 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_LR4_ABILITY_BITS 1 4757 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_LR4_ABILITY_SHIFT 10 4758 4759 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: one_hundredgbase_SR10_ability [09:09] */ 4760 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_SR10_ABILITY_MASK 0x0200 4761 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_SR10_ABILITY_ALIGN 0 4762 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_SR10_ABILITY_BITS 1 4763 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_SR10_ABILITY_SHIFT 9 4764 4765 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: one_hundredgbase_CR10_ability [08:08] */ 4766 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_CR10_ABILITY_MASK 0x0100 4767 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_CR10_ABILITY_ALIGN 0 4768 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_CR10_ABILITY_BITS 1 4769 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ONE_HUNDREDGBASE_CR10_ABILITY_SHIFT 8 4770 4771 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: reserved1 [07:05] */ 4772 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_MASK 0x00e0 4773 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_ALIGN 0 4774 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_BITS 3 4775 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_RESERVED1_SHIFT 5 4776 4777 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: fortygbase_FR_ability [04:04] */ 4778 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_FR_ABILITY_MASK 0x0010 4779 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_FR_ABILITY_ALIGN 0 4780 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_FR_ABILITY_BITS 1 4781 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_FR_ABILITY_SHIFT 4 4782 4783 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: fortygbase_LR4_ability [03:03] */ 4784 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_LR4_ABILITY_MASK 0x0008 4785 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_LR4_ABILITY_ALIGN 0 4786 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_LR4_ABILITY_BITS 1 4787 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_LR4_ABILITY_SHIFT 3 4788 4789 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: fortygbase_SR4_ability [02:02] */ 4790 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_SR4_ABILITY_MASK 0x0004 4791 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_SR4_ABILITY_ALIGN 0 4792 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_SR4_ABILITY_BITS 1 4793 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_SR4_ABILITY_SHIFT 2 4794 4795 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: fortygbase_CR4_ability [01:01] */ 4796 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_CR4_ABILITY_MASK 0x0002 4797 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_CR4_ABILITY_ALIGN 0 4798 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_CR4_ABILITY_BITS 1 4799 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_CR4_ABILITY_SHIFT 1 4800 4801 /* QSFI_IEEE0 :: fortyg_pmd_extended_ability_register :: fortygbase_KR4_ability [00:00] */ 4802 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_KR4_ABILITY_MASK 0x0001 4803 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_KR4_ABILITY_ALIGN 0 4804 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_KR4_ABILITY_BITS 1 4805 #define QSFI_IEEE0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_FORTYGBASE_KR4_ABILITY_SHIFT 0 4806 4807 4808 /**************************************************************************** 4809 * QSFI_IEEE0 :: pmd_oui_id0_register 4810 */ 4811 /* QSFI_IEEE0 :: pmd_oui_id0_register :: device_id_0 [15:00] */ 4812 #define QSFI_IEEE0_PMD_OUI_ID0_REGISTER_DEVICE_ID_0_MASK 0xffff 4813 #define QSFI_IEEE0_PMD_OUI_ID0_REGISTER_DEVICE_ID_0_ALIGN 0 4814 #define QSFI_IEEE0_PMD_OUI_ID0_REGISTER_DEVICE_ID_0_BITS 16 4815 #define QSFI_IEEE0_PMD_OUI_ID0_REGISTER_DEVICE_ID_0_SHIFT 0 4816 4817 4818 /**************************************************************************** 4819 * QSFI_IEEE0 :: pmd_oui_id1_reg 4820 */ 4821 /* QSFI_IEEE0 :: pmd_oui_id1_reg :: device_id_1 [15:00] */ 4822 #define QSFI_IEEE0_PMD_OUI_ID1_REG_DEVICE_ID_1_MASK 0xffff 4823 #define QSFI_IEEE0_PMD_OUI_ID1_REG_DEVICE_ID_1_ALIGN 0 4824 #define QSFI_IEEE0_PMD_OUI_ID1_REG_DEVICE_ID_1_BITS 16 4825 #define QSFI_IEEE0_PMD_OUI_ID1_REG_DEVICE_ID_1_SHIFT 0 4826 4827 4828 /**************************************************************************** 4829 * merlin_gallardo_qsfi_cl73_QSFI_AN_IEEE1 4830 */ 4831 /**************************************************************************** 4832 * QSFI_AN_IEEE1 :: an_advertisement_1_register 4833 */ 4834 /* QSFI_AN_IEEE1 :: an_advertisement_1_register :: next_page [15:15] */ 4835 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_MASK 0x8000 4836 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_ALIGN 0 4837 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_BITS 1 4838 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_NEXT_PAGE_SHIFT 15 4839 4840 /* QSFI_AN_IEEE1 :: an_advertisement_1_register :: acknowledge [14:14] */ 4841 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_MASK 0x4000 4842 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_ALIGN 0 4843 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_BITS 1 4844 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_ACKNOWLEDGE_SHIFT 14 4845 4846 /* QSFI_AN_IEEE1 :: an_advertisement_1_register :: remote_fault [13:13] */ 4847 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_MASK 0x2000 4848 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_ALIGN 0 4849 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_BITS 1 4850 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_REMOTE_FAULT_SHIFT 13 4851 4852 /* QSFI_AN_IEEE1 :: an_advertisement_1_register :: pause [12:10] */ 4853 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_PAUSE_MASK 0x1c00 4854 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_PAUSE_ALIGN 0 4855 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_PAUSE_BITS 3 4856 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_PAUSE_SHIFT 10 4857 4858 /* QSFI_AN_IEEE1 :: an_advertisement_1_register :: echoed_nonce [09:05] */ 4859 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_MASK 0x03e0 4860 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_ALIGN 0 4861 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_BITS 5 4862 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_ECHOED_NONCE_SHIFT 5 4863 4864 /* QSFI_AN_IEEE1 :: an_advertisement_1_register :: selector_field [04:00] */ 4865 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_MASK 0x001f 4866 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_ALIGN 0 4867 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_BITS 5 4868 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_1_REGISTER_SELECTOR_FIELD_SHIFT 0 4869 4870 4871 /**************************************************************************** 4872 * QSFI_AN_IEEE1 :: an_advertisement_2_register 4873 */ 4874 /* QSFI_AN_IEEE1 :: an_advertisement_2_register :: techAbility [15:05] */ 4875 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_MASK 0xffe0 4876 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_ALIGN 0 4877 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_BITS 11 4878 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_2_REGISTER_TECHABILITY_SHIFT 5 4879 4880 /* QSFI_AN_IEEE1 :: an_advertisement_2_register :: transmitted_nonce [04:00] */ 4881 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_MASK 0x001f 4882 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_ALIGN 0 4883 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_BITS 5 4884 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_2_REGISTER_TRANSMITTED_NONCE_SHIFT 0 4885 4886 4887 /**************************************************************************** 4888 * QSFI_AN_IEEE1 :: an_advertisement_3_register 4889 */ 4890 /* QSFI_AN_IEEE1 :: an_advertisement_3_register :: fec_requested [15:14] */ 4891 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_MASK 0xc000 4892 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_ALIGN 0 4893 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_BITS 2 4894 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_3_REGISTER_FEC_REQUESTED_SHIFT 14 4895 4896 /* QSFI_AN_IEEE1 :: an_advertisement_3_register :: an_adv_d45_d32 [13:00] */ 4897 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_3_REGISTER_AN_ADV_D45_D32_MASK 0x3fff 4898 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_3_REGISTER_AN_ADV_D45_D32_ALIGN 0 4899 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_3_REGISTER_AN_ADV_D45_D32_BITS 14 4900 #define QSFI_AN_IEEE1_AN_ADVERTISEMENT_3_REGISTER_AN_ADV_D45_D32_SHIFT 0 4901 4902 4903 /**************************************************************************** 4904 * QSFI_AN_IEEE1 :: an_lp_base_page_ability_1_reg 4905 */ 4906 /* QSFI_AN_IEEE1 :: an_lp_base_page_ability_1_reg :: d15_d0 [15:00] */ 4907 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_MASK 0xffff 4908 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_ALIGN 0 4909 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_BITS 16 4910 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_1_REG_D15_D0_SHIFT 0 4911 4912 4913 /**************************************************************************** 4914 * QSFI_AN_IEEE1 :: an_lp_base_page_ability_2_reg 4915 */ 4916 /* QSFI_AN_IEEE1 :: an_lp_base_page_ability_2_reg :: d31_16 [15:00] */ 4917 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_MASK 0xffff 4918 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_ALIGN 0 4919 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_BITS 16 4920 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_2_REG_D31_16_SHIFT 0 4921 4922 4923 /**************************************************************************** 4924 * QSFI_AN_IEEE1 :: an_lp_base_page_ability_3_reg 4925 */ 4926 /* QSFI_AN_IEEE1 :: an_lp_base_page_ability_3_reg :: d47_32 [15:00] */ 4927 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_MASK 0xffff 4928 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_ALIGN 0 4929 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_BITS 16 4930 #define QSFI_AN_IEEE1_AN_LP_BASE_PAGE_ABILITY_3_REG_D47_32_SHIFT 0 4931 4932 4933 /**************************************************************************** 4934 * QSFI_AN_IEEE1 :: an_xnp_transmit_1_register 4935 */ 4936 /* QSFI_AN_IEEE1 :: an_xnp_transmit_1_register :: next_page [15:15] */ 4937 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_MASK 0x8000 4938 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_ALIGN 0 4939 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_BITS 1 4940 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_SHIFT 15 4941 4942 /* QSFI_AN_IEEE1 :: an_xnp_transmit_1_register :: reserved0 [14:14] */ 4943 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_MASK 0x4000 4944 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_ALIGN 0 4945 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_BITS 1 4946 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_RESERVED0_SHIFT 14 4947 4948 /* QSFI_AN_IEEE1 :: an_xnp_transmit_1_register :: message_page [13:13] */ 4949 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_MASK 0x2000 4950 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_ALIGN 0 4951 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_BITS 1 4952 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_SHIFT 13 4953 4954 /* QSFI_AN_IEEE1 :: an_xnp_transmit_1_register :: acknowledge_2 [12:12] */ 4955 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_MASK 0x1000 4956 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_ALIGN 0 4957 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_BITS 1 4958 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_SHIFT 12 4959 4960 /* QSFI_AN_IEEE1 :: an_xnp_transmit_1_register :: toggle [11:11] */ 4961 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_MASK 0x0800 4962 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_ALIGN 0 4963 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_BITS 1 4964 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_TOGGLE_SHIFT 11 4965 4966 /* QSFI_AN_IEEE1 :: an_xnp_transmit_1_register :: message_unformatedcode_field [10:00] */ 4967 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_MASK 0x07ff 4968 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_ALIGN 0 4969 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_BITS 11 4970 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_SHIFT 0 4971 4972 4973 /**************************************************************************** 4974 * QSFI_AN_IEEE1 :: an_xnp_transmit_2_register 4975 */ 4976 /* QSFI_AN_IEEE1 :: an_xnp_transmit_2_register :: unformated_codefield_1 [15:00] */ 4977 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_MASK 0xffff 4978 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_ALIGN 0 4979 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_BITS 16 4980 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_SHIFT 0 4981 4982 4983 /**************************************************************************** 4984 * QSFI_AN_IEEE1 :: an_xnp_transmit_3_register 4985 */ 4986 /* QSFI_AN_IEEE1 :: an_xnp_transmit_3_register :: unformated_codefield_3 [15:00] */ 4987 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_MASK 0xffff 4988 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_ALIGN 0 4989 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_BITS 16 4990 #define QSFI_AN_IEEE1_AN_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_SHIFT 0 4991 4992 4993 /**************************************************************************** 4994 * QSFI_AN_IEEE1 :: an_lp_xnp_transmit_1_register 4995 */ 4996 /* QSFI_AN_IEEE1 :: an_lp_xnp_transmit_1_register :: next_page [15:15] */ 4997 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_MASK 0x8000 4998 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_ALIGN 0 4999 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_BITS 1 5000 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_NEXT_PAGE_SHIFT 15 5001 5002 /* QSFI_AN_IEEE1 :: an_lp_xnp_transmit_1_register :: acknowledge [14:14] */ 5003 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_MASK 0x4000 5004 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_ALIGN 0 5005 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_BITS 1 5006 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_SHIFT 14 5007 5008 /* QSFI_AN_IEEE1 :: an_lp_xnp_transmit_1_register :: message_page [13:13] */ 5009 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_MASK 0x2000 5010 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_ALIGN 0 5011 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_BITS 1 5012 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_PAGE_SHIFT 13 5013 5014 /* QSFI_AN_IEEE1 :: an_lp_xnp_transmit_1_register :: acknowledge_2 [12:12] */ 5015 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_MASK 0x1000 5016 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_ALIGN 0 5017 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_BITS 1 5018 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_ACKNOWLEDGE_2_SHIFT 12 5019 5020 /* QSFI_AN_IEEE1 :: an_lp_xnp_transmit_1_register :: toggle [11:11] */ 5021 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_MASK 0x0800 5022 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_ALIGN 0 5023 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_BITS 1 5024 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_TOGGLE_SHIFT 11 5025 5026 /* QSFI_AN_IEEE1 :: an_lp_xnp_transmit_1_register :: message_unformatedcode_field [10:00] */ 5027 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_MASK 0x07ff 5028 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_ALIGN 0 5029 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_BITS 11 5030 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_1_REGISTER_MESSAGE_UNFORMATEDCODE_FIELD_SHIFT 0 5031 5032 5033 /**************************************************************************** 5034 * QSFI_AN_IEEE1 :: an_lp_xnp_transmit_2_register 5035 */ 5036 /* QSFI_AN_IEEE1 :: an_lp_xnp_transmit_2_register :: unformated_codefield_1 [15:00] */ 5037 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_MASK 0xffff 5038 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_ALIGN 0 5039 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_BITS 16 5040 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_2_REGISTER_UNFORMATED_CODEFIELD_1_SHIFT 0 5041 5042 5043 /**************************************************************************** 5044 * QSFI_AN_IEEE1 :: an_lp_xnp_transmit_3_register 5045 */ 5046 /* QSFI_AN_IEEE1 :: an_lp_xnp_transmit_3_register :: unformated_codefield_3 [15:00] */ 5047 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_MASK 0xffff 5048 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_ALIGN 0 5049 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_BITS 16 5050 #define QSFI_AN_IEEE1_AN_LP_XNP_TRANSMIT_3_REGISTER_UNFORMATED_CODEFIELD_3_SHIFT 0 5051 5052 5053 /**************************************************************************** 5054 * merlin_gallardo_qsfi_cl73_QSFI_AN_IEEE3 5055 */ 5056 /**************************************************************************** 5057 * QSFI_AN_IEEE3 :: backplane_ethernet_status_register 5058 */ 5059 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: reserved0 [15:09] */ 5060 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_MASK 0xfe00 5061 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_ALIGN 0 5062 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_BITS 7 5063 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED0_SHIFT 9 5064 5065 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: onehundredbase_cr10 [08:08] */ 5066 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_ONEHUNDREDBASE_CR10_MASK 0x0100 5067 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_ONEHUNDREDBASE_CR10_ALIGN 0 5068 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_ONEHUNDREDBASE_CR10_BITS 1 5069 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_ONEHUNDREDBASE_CR10_SHIFT 8 5070 5071 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: reserved1 [07:07] */ 5072 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED1_MASK 0x0080 5073 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED1_ALIGN 0 5074 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED1_BITS 1 5075 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_RESERVED1_SHIFT 7 5076 5077 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: fortygbase_cr4 [06:06] */ 5078 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_MASK 0x0040 5079 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_ALIGN 0 5080 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_BITS 1 5081 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_CR4_SHIFT 6 5082 5083 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: fortygbase_kr4 [05:05] */ 5084 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR4_MASK 0x0020 5085 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR4_ALIGN 0 5086 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR4_BITS 1 5087 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FORTYGBASE_KR4_SHIFT 5 5088 5089 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: fec_negotiated [04:04] */ 5090 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FEC_NEGOTIATED_MASK 0x0010 5091 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FEC_NEGOTIATED_ALIGN 0 5092 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FEC_NEGOTIATED_BITS 1 5093 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_FEC_NEGOTIATED_SHIFT 4 5094 5095 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: tengbase_kr [03:03] */ 5096 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_MASK 0x0008 5097 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_ALIGN 0 5098 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_BITS 1 5099 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KR_SHIFT 3 5100 5101 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: tengbase_kx4 [02:02] */ 5102 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_MASK 0x0004 5103 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_ALIGN 0 5104 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_BITS 1 5105 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_TENGBASE_KX4_SHIFT 2 5106 5107 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: gigbase_kx [01:01] */ 5108 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_MASK 0x0002 5109 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_ALIGN 0 5110 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_BITS 1 5111 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_GIGBASE_KX_SHIFT 1 5112 5113 /* QSFI_AN_IEEE3 :: backplane_ethernet_status_register :: bp_an_ability [00:00] */ 5114 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_MASK 0x0001 5115 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_ALIGN 0 5116 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_BITS 1 5117 #define QSFI_AN_IEEE3_BACKPLANE_ETHERNET_STATUS_REGISTER_BP_AN_ABILITY_SHIFT 0 5118 5119 5120 /**************************************************************************** 5121 * QSFI_AN_IEEE3 :: EEE_adv 5122 */ 5123 /* QSFI_AN_IEEE3 :: EEE_adv :: reserved0 [15:07] */ 5124 #define QSFI_AN_IEEE3_EEE_ADV_RESERVED0_MASK 0xff80 5125 #define QSFI_AN_IEEE3_EEE_ADV_RESERVED0_ALIGN 0 5126 #define QSFI_AN_IEEE3_EEE_ADV_RESERVED0_BITS 9 5127 #define QSFI_AN_IEEE3_EEE_ADV_RESERVED0_SHIFT 7 5128 5129 /* QSFI_AN_IEEE3 :: EEE_adv :: EEE_10G_KR [06:06] */ 5130 #define QSFI_AN_IEEE3_EEE_ADV_EEE_10G_KR_MASK 0x0040 5131 #define QSFI_AN_IEEE3_EEE_ADV_EEE_10G_KR_ALIGN 0 5132 #define QSFI_AN_IEEE3_EEE_ADV_EEE_10G_KR_BITS 1 5133 #define QSFI_AN_IEEE3_EEE_ADV_EEE_10G_KR_SHIFT 6 5134 5135 /* QSFI_AN_IEEE3 :: EEE_adv :: EEE_10G_KX4 [05:05] */ 5136 #define QSFI_AN_IEEE3_EEE_ADV_EEE_10G_KX4_MASK 0x0020 5137 #define QSFI_AN_IEEE3_EEE_ADV_EEE_10G_KX4_ALIGN 0 5138 #define QSFI_AN_IEEE3_EEE_ADV_EEE_10G_KX4_BITS 1 5139 #define QSFI_AN_IEEE3_EEE_ADV_EEE_10G_KX4_SHIFT 5 5140 5141 /* QSFI_AN_IEEE3 :: EEE_adv :: EEE_1G_KX [04:04] */ 5142 #define QSFI_AN_IEEE3_EEE_ADV_EEE_1G_KX_MASK 0x0010 5143 #define QSFI_AN_IEEE3_EEE_ADV_EEE_1G_KX_ALIGN 0 5144 #define QSFI_AN_IEEE3_EEE_ADV_EEE_1G_KX_BITS 1 5145 #define QSFI_AN_IEEE3_EEE_ADV_EEE_1G_KX_SHIFT 4 5146 5147 /* QSFI_AN_IEEE3 :: EEE_adv :: reserved1 [03:00] */ 5148 #define QSFI_AN_IEEE3_EEE_ADV_RESERVED1_MASK 0x000f 5149 #define QSFI_AN_IEEE3_EEE_ADV_RESERVED1_ALIGN 0 5150 #define QSFI_AN_IEEE3_EEE_ADV_RESERVED1_BITS 4 5151 #define QSFI_AN_IEEE3_EEE_ADV_RESERVED1_SHIFT 0 5152 5153 5154 /**************************************************************************** 5155 * QSFI_AN_IEEE3 :: EEE_lp_adv 5156 */ 5157 /* QSFI_AN_IEEE3 :: EEE_lp_adv :: reserved0 [15:07] */ 5158 #define QSFI_AN_IEEE3_EEE_LP_ADV_RESERVED0_MASK 0xff80 5159 #define QSFI_AN_IEEE3_EEE_LP_ADV_RESERVED0_ALIGN 0 5160 #define QSFI_AN_IEEE3_EEE_LP_ADV_RESERVED0_BITS 9 5161 #define QSFI_AN_IEEE3_EEE_LP_ADV_RESERVED0_SHIFT 7 5162 5163 /* QSFI_AN_IEEE3 :: EEE_lp_adv :: EEE_10G_KR [06:06] */ 5164 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_10G_KR_MASK 0x0040 5165 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_10G_KR_ALIGN 0 5166 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_10G_KR_BITS 1 5167 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_10G_KR_SHIFT 6 5168 5169 /* QSFI_AN_IEEE3 :: EEE_lp_adv :: EEE_10G_KX4 [05:05] */ 5170 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_10G_KX4_MASK 0x0020 5171 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_10G_KX4_ALIGN 0 5172 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_10G_KX4_BITS 1 5173 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_10G_KX4_SHIFT 5 5174 5175 /* QSFI_AN_IEEE3 :: EEE_lp_adv :: EEE_1G_KX [04:04] */ 5176 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_1G_KX_MASK 0x0010 5177 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_1G_KX_ALIGN 0 5178 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_1G_KX_BITS 1 5179 #define QSFI_AN_IEEE3_EEE_LP_ADV_EEE_1G_KX_SHIFT 4 5180 5181 /* QSFI_AN_IEEE3 :: EEE_lp_adv :: reserved1 [03:00] */ 5182 #define QSFI_AN_IEEE3_EEE_LP_ADV_RESERVED1_MASK 0x000f 5183 #define QSFI_AN_IEEE3_EEE_LP_ADV_RESERVED1_ALIGN 0 5184 #define QSFI_AN_IEEE3_EEE_LP_ADV_RESERVED1_BITS 4 5185 #define QSFI_AN_IEEE3_EEE_LP_ADV_RESERVED1_SHIFT 0 5186 5187 5188 /**************************************************************************** 5189 * merlin_gallardo_cl72b_ieee_blk_CL72_IEEE_TX 5190 */ 5191 /**************************************************************************** 5192 * CL72_IEEE_TX :: BASE_R_PMD_control_register_150 5193 */ 5194 /* CL72_IEEE_TX :: BASE_R_PMD_control_register_150 :: reserved0 [15:02] */ 5195 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESERVED0_MASK 0xfffc 5196 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESERVED0_ALIGN 0 5197 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESERVED0_BITS 14 5198 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESERVED0_SHIFT 2 5199 5200 /* CL72_IEEE_TX :: BASE_R_PMD_control_register_150 :: training_enable [01:01] */ 5201 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_MASK 0x0002 5202 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_ALIGN 0 5203 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_BITS 1 5204 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_TRAINING_ENABLE_SHIFT 1 5205 5206 /* CL72_IEEE_TX :: BASE_R_PMD_control_register_150 :: restart_training [00:00] */ 5207 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_MASK 0x0001 5208 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_ALIGN 0 5209 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_BITS 1 5210 #define CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_RESTART_TRAINING_SHIFT 0 5211 5212 5213 /**************************************************************************** 5214 * CL72_IEEE_TX :: BASE_R_PMD_status_register_151 5215 */ 5216 /* CL72_IEEE_TX :: BASE_R_PMD_status_register_151 :: reserved0 [15:04] */ 5217 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RESERVED0_MASK 0xfff0 5218 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RESERVED0_ALIGN 0 5219 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RESERVED0_BITS 12 5220 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RESERVED0_SHIFT 4 5221 5222 /* CL72_IEEE_TX :: BASE_R_PMD_status_register_151 :: training_failure [03:03] */ 5223 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_MASK 0x0008 5224 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_ALIGN 0 5225 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_BITS 1 5226 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TRAINING_FAILURE_SHIFT 3 5227 5228 /* CL72_IEEE_TX :: BASE_R_PMD_status_register_151 :: training_status [02:02] */ 5229 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TRAINING_STATUS_MASK 0x0004 5230 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TRAINING_STATUS_ALIGN 0 5231 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TRAINING_STATUS_BITS 1 5232 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TRAINING_STATUS_SHIFT 2 5233 5234 /* CL72_IEEE_TX :: BASE_R_PMD_status_register_151 :: frame_lock [01:01] */ 5235 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_FRAME_LOCK_MASK 0x0002 5236 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_FRAME_LOCK_ALIGN 0 5237 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_FRAME_LOCK_BITS 1 5238 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_FRAME_LOCK_SHIFT 1 5239 5240 /* CL72_IEEE_TX :: BASE_R_PMD_status_register_151 :: receiver_status [00:00] */ 5241 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_MASK 0x0001 5242 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_ALIGN 0 5243 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_BITS 1 5244 #define CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_RECEIVER_STATUS_SHIFT 0 5245 5246 5247 /**************************************************************************** 5248 * CL72_IEEE_TX :: BASE_R_LP_coeff_update_register_152 5249 */ 5250 /* CL72_IEEE_TX :: BASE_R_LP_coeff_update_register_152 :: lp_coeff_update [15:00] */ 5251 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_LP_COEFF_UPDATE_MASK 0xffff 5252 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_LP_COEFF_UPDATE_ALIGN 0 5253 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_LP_COEFF_UPDATE_BITS 16 5254 #define CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_LP_COEFF_UPDATE_SHIFT 0 5255 5256 5257 /**************************************************************************** 5258 * CL72_IEEE_TX :: BASE_R_LD_coeff_update_register_154 5259 */ 5260 /* CL72_IEEE_TX :: BASE_R_LD_coeff_update_register_154 :: ld_coeff_update [15:00] */ 5261 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_LD_COEFF_UPDATE_MASK 0xffff 5262 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_LD_COEFF_UPDATE_ALIGN 0 5263 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_LD_COEFF_UPDATE_BITS 16 5264 #define CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_LD_COEFF_UPDATE_SHIFT 0 5265 5266 5267 /**************************************************************************** 5268 * CL72_IEEE_TX :: BASE_R_LD_status_report_register_155 5269 */ 5270 /* CL72_IEEE_TX :: BASE_R_LD_status_report_register_155 :: ld_status_report [15:00] */ 5271 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_LD_STATUS_REPORT_MASK 0xffff 5272 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_LD_STATUS_REPORT_ALIGN 0 5273 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_LD_STATUS_REPORT_BITS 16 5274 #define CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_LD_STATUS_REPORT_SHIFT 0 5275 5276 5277 /**************************************************************************** 5278 * merlin_gallardo_cl72b_ieee_blk_CL72_IEEE_RX 5279 */ 5280 /**************************************************************************** 5281 * CL72_IEEE_RX :: BASE_R_LD_status_report_register_153 5282 */ 5283 /* CL72_IEEE_RX :: BASE_R_LD_status_report_register_153 :: lp_status_report [15:00] */ 5284 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_LP_STATUS_REPORT_MASK 0xffff 5285 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_LP_STATUS_REPORT_ALIGN 0 5286 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_LP_STATUS_REPORT_BITS 16 5287 #define CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_LP_STATUS_REPORT_SHIFT 0 5288 5289 5290 /**************************************************************************** 5291 * merlin_gallardo_qsfi_blk_QSFI_IEEE10 5292 */ 5293 /**************************************************************************** 5294 * QSFI_IEEE10 :: tengbase_kx_control_register 5295 */ 5296 /* QSFI_IEEE10 :: tengbase_kx_control_register :: reserved0 [15:01] */ 5297 #define QSFI_IEEE10_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_MASK 0xfffe 5298 #define QSFI_IEEE10_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_ALIGN 0 5299 #define QSFI_IEEE10_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_BITS 15 5300 #define QSFI_IEEE10_TENGBASE_KX_CONTROL_REGISTER_RESERVED0_SHIFT 1 5301 5302 /* QSFI_IEEE10 :: tengbase_kx_control_register :: pmd_transmit_disable [00:00] */ 5303 #define QSFI_IEEE10_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_MASK 0x0001 5304 #define QSFI_IEEE10_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_ALIGN 0 5305 #define QSFI_IEEE10_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_BITS 1 5306 #define QSFI_IEEE10_TENGBASE_KX_CONTROL_REGISTER_PMD_TRANSMIT_DISABLE_SHIFT 0 5307 5308 5309 /**************************************************************************** 5310 * QSFI_IEEE10 :: tengbase_kx_status_register 5311 */ 5312 /* QSFI_IEEE10 :: tengbase_kx_status_register :: reserved0 [15:14] */ 5313 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED0_MASK 0xc000 5314 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED0_ALIGN 0 5315 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED0_BITS 2 5316 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED0_SHIFT 14 5317 5318 /* QSFI_IEEE10 :: tengbase_kx_status_register :: transmit_faultability [13:13] */ 5319 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_MASK 0x2000 5320 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_ALIGN 0 5321 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_BITS 1 5322 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULTABILITY_SHIFT 13 5323 5324 /* QSFI_IEEE10 :: tengbase_kx_status_register :: receive_faultability [12:12] */ 5325 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_MASK 0x1000 5326 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_ALIGN 0 5327 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_BITS 1 5328 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULTABILITY_SHIFT 12 5329 5330 /* QSFI_IEEE10 :: tengbase_kx_status_register :: transmit_fault [11:11] */ 5331 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_MASK 0x0800 5332 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_ALIGN 0 5333 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_BITS 1 5334 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_TRANSMIT_FAULT_SHIFT 11 5335 5336 /* QSFI_IEEE10 :: tengbase_kx_status_register :: receive_fault [10:10] */ 5337 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_MASK 0x0400 5338 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_ALIGN 0 5339 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_BITS 1 5340 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RECEIVE_FAULT_SHIFT 10 5341 5342 /* QSFI_IEEE10 :: tengbase_kx_status_register :: reserved1 [09:09] */ 5343 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED1_MASK 0x0200 5344 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED1_ALIGN 0 5345 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED1_BITS 1 5346 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED1_SHIFT 9 5347 5348 /* QSFI_IEEE10 :: tengbase_kx_status_register :: pmd_transmitdisable_ability [08:08] */ 5349 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_MASK 0x0100 5350 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_ALIGN 0 5351 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_BITS 1 5352 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_PMD_TRANSMITDISABLE_ABILITY_SHIFT 8 5353 5354 /* QSFI_IEEE10 :: tengbase_kx_status_register :: reserved2 [07:01] */ 5355 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED2_MASK 0x00fe 5356 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED2_ALIGN 0 5357 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED2_BITS 7 5358 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_RESERVED2_SHIFT 1 5359 5360 /* QSFI_IEEE10 :: tengbase_kx_status_register :: signal_detectfrom_pmd [00:00] */ 5361 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_MASK 0x0001 5362 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_ALIGN 0 5363 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_BITS 1 5364 #define QSFI_IEEE10_TENGBASE_KX_STATUS_REGISTER_SIGNAL_DETECTFROM_PMD_SHIFT 0 5365 5366 5367 /**************************************************************************** 5368 * merlin_gallardo_qsfi_blk_QSFI_XGXS_BLK0 5369 */ 5370 /**************************************************************************** 5371 * QSFI_XGXS_BLK0 :: xgxsControl 5372 */ 5373 /* QSFI_XGXS_BLK0 :: xgxsControl :: reserved0 [15:14] */ 5374 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED0_MASK 0xc000 5375 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED0_ALIGN 0 5376 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED0_BITS 2 5377 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED0_SHIFT 14 5378 5379 /* QSFI_XGXS_BLK0 :: xgxsControl :: start_sequencer [13:13] */ 5380 #define QSFI_XGXS_BLK0_XGXSCONTROL_START_SEQUENCER_MASK 0x2000 5381 #define QSFI_XGXS_BLK0_XGXSCONTROL_START_SEQUENCER_ALIGN 0 5382 #define QSFI_XGXS_BLK0_XGXSCONTROL_START_SEQUENCER_BITS 1 5383 #define QSFI_XGXS_BLK0_XGXSCONTROL_START_SEQUENCER_SHIFT 13 5384 5385 /* QSFI_XGXS_BLK0 :: xgxsControl :: reserved1 [12:12] */ 5386 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED1_MASK 0x1000 5387 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED1_ALIGN 0 5388 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED1_BITS 1 5389 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED1_SHIFT 12 5390 5391 /* QSFI_XGXS_BLK0 :: xgxsControl :: mode10gXgxsControl [11:08] */ 5392 #define QSFI_XGXS_BLK0_XGXSCONTROL_MODE10GXGXSCONTROL_MASK 0x0f00 5393 #define QSFI_XGXS_BLK0_XGXSCONTROL_MODE10GXGXSCONTROL_ALIGN 0 5394 #define QSFI_XGXS_BLK0_XGXSCONTROL_MODE10GXGXSCONTROL_BITS 4 5395 #define QSFI_XGXS_BLK0_XGXSCONTROL_MODE10GXGXSCONTROL_SHIFT 8 5396 5397 /* QSFI_XGXS_BLK0 :: xgxsControl :: reserved2 [07:00] */ 5398 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED2_MASK 0x00ff 5399 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED2_ALIGN 0 5400 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED2_BITS 8 5401 #define QSFI_XGXS_BLK0_XGXSCONTROL_RESERVED2_SHIFT 0 5402 5403 5404 /**************************************************************************** 5405 * QSFI_XGXS_BLK0 :: xgxsStatus 5406 */ 5407 /* QSFI_XGXS_BLK0 :: xgxsStatus :: status_en [15:15] */ 5408 #define QSFI_XGXS_BLK0_XGXSSTATUS_STATUS_EN_MASK 0x8000 5409 #define QSFI_XGXS_BLK0_XGXSSTATUS_STATUS_EN_ALIGN 0 5410 #define QSFI_XGXS_BLK0_XGXSSTATUS_STATUS_EN_BITS 1 5411 #define QSFI_XGXS_BLK0_XGXSSTATUS_STATUS_EN_SHIFT 15 5412 5413 /* QSFI_XGXS_BLK0 :: xgxsStatus :: reserved0 [14:12] */ 5414 #define QSFI_XGXS_BLK0_XGXSSTATUS_RESERVED0_MASK 0x7000 5415 #define QSFI_XGXS_BLK0_XGXSSTATUS_RESERVED0_ALIGN 0 5416 #define QSFI_XGXS_BLK0_XGXSSTATUS_RESERVED0_BITS 3 5417 #define QSFI_XGXS_BLK0_XGXSSTATUS_RESERVED0_SHIFT 12 5418 5419 /* QSFI_XGXS_BLK0 :: xgxsStatus :: txpll_lock [11:11] */ 5420 #define QSFI_XGXS_BLK0_XGXSSTATUS_TXPLL_LOCK_MASK 0x0800 5421 #define QSFI_XGXS_BLK0_XGXSSTATUS_TXPLL_LOCK_ALIGN 0 5422 #define QSFI_XGXS_BLK0_XGXSSTATUS_TXPLL_LOCK_BITS 1 5423 #define QSFI_XGXS_BLK0_XGXSSTATUS_TXPLL_LOCK_SHIFT 11 5424 5425 /* QSFI_XGXS_BLK0 :: xgxsStatus :: reserved1 [10:00] */ 5426 #define QSFI_XGXS_BLK0_XGXSSTATUS_RESERVED1_MASK 0x07ff 5427 #define QSFI_XGXS_BLK0_XGXSSTATUS_RESERVED1_ALIGN 0 5428 #define QSFI_XGXS_BLK0_XGXSSTATUS_RESERVED1_BITS 11 5429 #define QSFI_XGXS_BLK0_XGXSSTATUS_RESERVED1_SHIFT 0 5430 5431 5432 /**************************************************************************** 5433 * QSFI_XGXS_BLK0 :: miscControl1 5434 */ 5435 /* QSFI_XGXS_BLK0 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */ 5436 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK 0x8000 5437 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN 0 5438 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS 1 5439 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT 15 5440 5441 /* QSFI_XGXS_BLK0 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */ 5442 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK 0x4000 5443 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN 0 5444 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS 1 5445 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT 14 5446 5447 /* QSFI_XGXS_BLK0 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */ 5448 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK 0x2000 5449 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN 0 5450 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS 1 5451 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT 13 5452 5453 /* QSFI_XGXS_BLK0 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */ 5454 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK 0x1000 5455 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN 0 5456 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS 1 5457 #define QSFI_XGXS_BLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT 12 5458 5459 /* QSFI_XGXS_BLK0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 5460 #define QSFI_XGXS_BLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 5461 #define QSFI_XGXS_BLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 5462 #define QSFI_XGXS_BLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 5463 #define QSFI_XGXS_BLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 5464 5465 /* QSFI_XGXS_BLK0 :: miscControl1 :: reserved0 [10:08] */ 5466 #define QSFI_XGXS_BLK0_MISCCONTROL1_RESERVED0_MASK 0x0700 5467 #define QSFI_XGXS_BLK0_MISCCONTROL1_RESERVED0_ALIGN 0 5468 #define QSFI_XGXS_BLK0_MISCCONTROL1_RESERVED0_BITS 3 5469 #define QSFI_XGXS_BLK0_MISCCONTROL1_RESERVED0_SHIFT 8 5470 5471 /* QSFI_XGXS_BLK0 :: miscControl1 :: i_testsel [07:05] */ 5472 #define QSFI_XGXS_BLK0_MISCCONTROL1_I_TESTSEL_MASK 0x00e0 5473 #define QSFI_XGXS_BLK0_MISCCONTROL1_I_TESTSEL_ALIGN 0 5474 #define QSFI_XGXS_BLK0_MISCCONTROL1_I_TESTSEL_BITS 3 5475 #define QSFI_XGXS_BLK0_MISCCONTROL1_I_TESTSEL_SHIFT 5 5476 5477 /* QSFI_XGXS_BLK0 :: miscControl1 :: force_div5_for_lxck25 [04:04] */ 5478 #define QSFI_XGXS_BLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK 0x0010 5479 #define QSFI_XGXS_BLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN 0 5480 #define QSFI_XGXS_BLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS 1 5481 #define QSFI_XGXS_BLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT 4 5482 5483 /* QSFI_XGXS_BLK0 :: miscControl1 :: reserved1 [03:02] */ 5484 #define QSFI_XGXS_BLK0_MISCCONTROL1_RESERVED1_MASK 0x000c 5485 #define QSFI_XGXS_BLK0_MISCCONTROL1_RESERVED1_ALIGN 0 5486 #define QSFI_XGXS_BLK0_MISCCONTROL1_RESERVED1_BITS 2 5487 #define QSFI_XGXS_BLK0_MISCCONTROL1_RESERVED1_SHIFT 2 5488 5489 /* QSFI_XGXS_BLK0 :: miscControl1 :: txen_mask2 [01:01] */ 5490 #define QSFI_XGXS_BLK0_MISCCONTROL1_TXEN_MASK2_MASK 0x0002 5491 #define QSFI_XGXS_BLK0_MISCCONTROL1_TXEN_MASK2_ALIGN 0 5492 #define QSFI_XGXS_BLK0_MISCCONTROL1_TXEN_MASK2_BITS 1 5493 #define QSFI_XGXS_BLK0_MISCCONTROL1_TXEN_MASK2_SHIFT 1 5494 5495 /* QSFI_XGXS_BLK0 :: miscControl1 :: txen_mask1 [00:00] */ 5496 #define QSFI_XGXS_BLK0_MISCCONTROL1_TXEN_MASK1_MASK 0x0001 5497 #define QSFI_XGXS_BLK0_MISCCONTROL1_TXEN_MASK1_ALIGN 0 5498 #define QSFI_XGXS_BLK0_MISCCONTROL1_TXEN_MASK1_BITS 1 5499 #define QSFI_XGXS_BLK0_MISCCONTROL1_TXEN_MASK1_SHIFT 0 5500 5501 5502 /**************************************************************************** 5503 * merlin_gallardo_qsfi_blk_QSFI_XGXS_BLK1 5504 */ 5505 /**************************************************************************** 5506 * QSFI_XGXS_BLK1 :: laneCtrl2 5507 */ 5508 /* QSFI_XGXS_BLK1 :: laneCtrl2 :: reserved0 [15:08] */ 5509 #define QSFI_XGXS_BLK1_LANECTRL2_RESERVED0_MASK 0xff00 5510 #define QSFI_XGXS_BLK1_LANECTRL2_RESERVED0_ALIGN 0 5511 #define QSFI_XGXS_BLK1_LANECTRL2_RESERVED0_BITS 8 5512 #define QSFI_XGXS_BLK1_LANECTRL2_RESERVED0_SHIFT 8 5513 5514 /* QSFI_XGXS_BLK1 :: laneCtrl2 :: rloop1g [07:04] */ 5515 #define QSFI_XGXS_BLK1_LANECTRL2_RLOOP1G_MASK 0x00f0 5516 #define QSFI_XGXS_BLK1_LANECTRL2_RLOOP1G_ALIGN 0 5517 #define QSFI_XGXS_BLK1_LANECTRL2_RLOOP1G_BITS 4 5518 #define QSFI_XGXS_BLK1_LANECTRL2_RLOOP1G_SHIFT 4 5519 5520 /* QSFI_XGXS_BLK1 :: laneCtrl2 :: reserved1 [03:00] */ 5521 #define QSFI_XGXS_BLK1_LANECTRL2_RESERVED1_MASK 0x000f 5522 #define QSFI_XGXS_BLK1_LANECTRL2_RESERVED1_ALIGN 0 5523 #define QSFI_XGXS_BLK1_LANECTRL2_RESERVED1_BITS 4 5524 #define QSFI_XGXS_BLK1_LANECTRL2_RESERVED1_SHIFT 0 5525 5526 5527 /**************************************************************************** 5528 * QSFI_XGXS_BLK1 :: laneCtrl3 5529 */ 5530 /* QSFI_XGXS_BLK1 :: laneCtrl3 :: reserved0 [15:10] */ 5531 #define QSFI_XGXS_BLK1_LANECTRL3_RESERVED0_MASK 0xfc00 5532 #define QSFI_XGXS_BLK1_LANECTRL3_RESERVED0_ALIGN 0 5533 #define QSFI_XGXS_BLK1_LANECTRL3_RESERVED0_BITS 6 5534 #define QSFI_XGXS_BLK1_LANECTRL3_RESERVED0_SHIFT 10 5535 5536 /* QSFI_XGXS_BLK1 :: laneCtrl3 :: pwrdwn_pll_dis [09:09] */ 5537 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDWN_PLL_DIS_MASK 0x0200 5538 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDWN_PLL_DIS_ALIGN 0 5539 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDWN_PLL_DIS_BITS 1 5540 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDWN_PLL_DIS_SHIFT 9 5541 5542 /* QSFI_XGXS_BLK1 :: laneCtrl3 :: pwrdwn_pll [08:08] */ 5543 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDWN_PLL_MASK 0x0100 5544 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDWN_PLL_ALIGN 0 5545 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDWN_PLL_BITS 1 5546 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDWN_PLL_SHIFT 8 5547 5548 /* QSFI_XGXS_BLK1 :: laneCtrl3 :: pwrdn_tx [07:04] */ 5549 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDN_TX_MASK 0x00f0 5550 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDN_TX_ALIGN 0 5551 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDN_TX_BITS 4 5552 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDN_TX_SHIFT 4 5553 5554 /* QSFI_XGXS_BLK1 :: laneCtrl3 :: pwrdn_rx [03:00] */ 5555 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDN_RX_MASK 0x000f 5556 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDN_RX_ALIGN 0 5557 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDN_RX_BITS 4 5558 #define QSFI_XGXS_BLK1_LANECTRL3_PWRDN_RX_SHIFT 0 5559 5560 5561 /**************************************************************************** 5562 * QSFI_XGXS_BLK1 :: laneTest 5563 */ 5564 /* QSFI_XGXS_BLK1 :: laneTest :: reserved0 [15:11] */ 5565 #define QSFI_XGXS_BLK1_LANETEST_RESERVED0_MASK 0xf800 5566 #define QSFI_XGXS_BLK1_LANETEST_RESERVED0_ALIGN 0 5567 #define QSFI_XGXS_BLK1_LANETEST_RESERVED0_BITS 5 5568 #define QSFI_XGXS_BLK1_LANETEST_RESERVED0_SHIFT 11 5569 5570 /* QSFI_XGXS_BLK1 :: laneTest :: ext_pwrdn_dis [10:10] */ 5571 #define QSFI_XGXS_BLK1_LANETEST_EXT_PWRDN_DIS_MASK 0x0400 5572 #define QSFI_XGXS_BLK1_LANETEST_EXT_PWRDN_DIS_ALIGN 0 5573 #define QSFI_XGXS_BLK1_LANETEST_EXT_PWRDN_DIS_BITS 1 5574 #define QSFI_XGXS_BLK1_LANETEST_EXT_PWRDN_DIS_SHIFT 10 5575 5576 /* QSFI_XGXS_BLK1 :: laneTest :: reserved1 [09:09] */ 5577 #define QSFI_XGXS_BLK1_LANETEST_RESERVED1_MASK 0x0200 5578 #define QSFI_XGXS_BLK1_LANETEST_RESERVED1_ALIGN 0 5579 #define QSFI_XGXS_BLK1_LANETEST_RESERVED1_BITS 1 5580 #define QSFI_XGXS_BLK1_LANETEST_RESERVED1_SHIFT 9 5581 5582 /* QSFI_XGXS_BLK1 :: laneTest :: pwrdwn_clks_en [08:08] */ 5583 #define QSFI_XGXS_BLK1_LANETEST_PWRDWN_CLKS_EN_MASK 0x0100 5584 #define QSFI_XGXS_BLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN 0 5585 #define QSFI_XGXS_BLK1_LANETEST_PWRDWN_CLKS_EN_BITS 1 5586 #define QSFI_XGXS_BLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT 8 5587 5588 /* QSFI_XGXS_BLK1 :: laneTest :: reserved2 [07:06] */ 5589 #define QSFI_XGXS_BLK1_LANETEST_RESERVED2_MASK 0x00c0 5590 #define QSFI_XGXS_BLK1_LANETEST_RESERVED2_ALIGN 0 5591 #define QSFI_XGXS_BLK1_LANETEST_RESERVED2_BITS 2 5592 #define QSFI_XGXS_BLK1_LANETEST_RESERVED2_SHIFT 6 5593 5594 /* QSFI_XGXS_BLK1 :: laneTest :: lfck_bypass [05:05] */ 5595 #define QSFI_XGXS_BLK1_LANETEST_LFCK_BYPASS_MASK 0x0020 5596 #define QSFI_XGXS_BLK1_LANETEST_LFCK_BYPASS_ALIGN 0 5597 #define QSFI_XGXS_BLK1_LANETEST_LFCK_BYPASS_BITS 1 5598 #define QSFI_XGXS_BLK1_LANETEST_LFCK_BYPASS_SHIFT 5 5599 5600 /* QSFI_XGXS_BLK1 :: laneTest :: reserved3 [04:00] */ 5601 #define QSFI_XGXS_BLK1_LANETEST_RESERVED3_MASK 0x001f 5602 #define QSFI_XGXS_BLK1_LANETEST_RESERVED3_ALIGN 0 5603 #define QSFI_XGXS_BLK1_LANETEST_RESERVED3_BITS 5 5604 #define QSFI_XGXS_BLK1_LANETEST_RESERVED3_SHIFT 0 5605 5606 5607 /**************************************************************************** 5608 * merlin_gallardo_qsfi_blk_QSFI_TX 5609 */ 5610 /**************************************************************************** 5611 * QSFI_TX :: anaTxAStatus 5612 */ 5613 /* QSFI_TX :: anaTxAStatus :: test_bus [15:08] */ 5614 #define QSFI_TX_ANATXASTATUS_TEST_BUS_MASK 0xff00 5615 #define QSFI_TX_ANATXASTATUS_TEST_BUS_ALIGN 0 5616 #define QSFI_TX_ANATXASTATUS_TEST_BUS_BITS 8 5617 #define QSFI_TX_ANATXASTATUS_TEST_BUS_SHIFT 8 5618 5619 /* QSFI_TX :: anaTxAStatus :: reserved0 [07:05] */ 5620 #define QSFI_TX_ANATXASTATUS_RESERVED0_MASK 0x00e0 5621 #define QSFI_TX_ANATXASTATUS_RESERVED0_ALIGN 0 5622 #define QSFI_TX_ANATXASTATUS_RESERVED0_BITS 3 5623 #define QSFI_TX_ANATXASTATUS_RESERVED0_SHIFT 5 5624 5625 /* QSFI_TX :: anaTxAStatus :: pmd_tx_clk_vld [04:04] */ 5626 #define QSFI_TX_ANATXASTATUS_PMD_TX_CLK_VLD_MASK 0x0010 5627 #define QSFI_TX_ANATXASTATUS_PMD_TX_CLK_VLD_ALIGN 0 5628 #define QSFI_TX_ANATXASTATUS_PMD_TX_CLK_VLD_BITS 1 5629 #define QSFI_TX_ANATXASTATUS_PMD_TX_CLK_VLD_SHIFT 4 5630 5631 /* QSFI_TX :: anaTxAStatus :: pmd_ln_dp_tx_rst [03:03] */ 5632 #define QSFI_TX_ANATXASTATUS_PMD_LN_DP_TX_RST_MASK 0x0008 5633 #define QSFI_TX_ANATXASTATUS_PMD_LN_DP_TX_RST_ALIGN 0 5634 #define QSFI_TX_ANATXASTATUS_PMD_LN_DP_TX_RST_BITS 1 5635 #define QSFI_TX_ANATXASTATUS_PMD_LN_DP_TX_RST_SHIFT 3 5636 5637 /* QSFI_TX :: anaTxAStatus :: pmd_ln_tx_h_pwrdn [02:02] */ 5638 #define QSFI_TX_ANATXASTATUS_PMD_LN_TX_H_PWRDN_MASK 0x0004 5639 #define QSFI_TX_ANATXASTATUS_PMD_LN_TX_H_PWRDN_ALIGN 0 5640 #define QSFI_TX_ANATXASTATUS_PMD_LN_TX_H_PWRDN_BITS 1 5641 #define QSFI_TX_ANATXASTATUS_PMD_LN_TX_H_PWRDN_SHIFT 2 5642 5643 /* QSFI_TX :: anaTxAStatus :: txferr_stky [01:01] */ 5644 #define QSFI_TX_ANATXASTATUS_TXFERR_STKY_MASK 0x0002 5645 #define QSFI_TX_ANATXASTATUS_TXFERR_STKY_ALIGN 0 5646 #define QSFI_TX_ANATXASTATUS_TXFERR_STKY_BITS 1 5647 #define QSFI_TX_ANATXASTATUS_TXFERR_STKY_SHIFT 1 5648 5649 /* QSFI_TX :: anaTxAStatus :: pcb_pmd_pwrdwn_tx [00:00] */ 5650 #define QSFI_TX_ANATXASTATUS_PCB_PMD_PWRDWN_TX_MASK 0x0001 5651 #define QSFI_TX_ANATXASTATUS_PCB_PMD_PWRDWN_TX_ALIGN 0 5652 #define QSFI_TX_ANATXASTATUS_PCB_PMD_PWRDWN_TX_BITS 1 5653 #define QSFI_TX_ANATXASTATUS_PCB_PMD_PWRDWN_TX_SHIFT 0 5654 5655 5656 /**************************************************************************** 5657 * QSFI_TX :: anaTxAControl0 5658 */ 5659 /* QSFI_TX :: anaTxAControl0 :: reserved0 [15:14] */ 5660 #define QSFI_TX_ANATXACONTROL0_RESERVED0_MASK 0xc000 5661 #define QSFI_TX_ANATXACONTROL0_RESERVED0_ALIGN 0 5662 #define QSFI_TX_ANATXACONTROL0_RESERVED0_BITS 2 5663 #define QSFI_TX_ANATXACONTROL0_RESERVED0_SHIFT 14 5664 5665 /* QSFI_TX :: anaTxAControl0 :: tx1g_frst_SM [13:13] */ 5666 #define QSFI_TX_ANATXACONTROL0_TX1G_FRST_SM_MASK 0x2000 5667 #define QSFI_TX_ANATXACONTROL0_TX1G_FRST_SM_ALIGN 0 5668 #define QSFI_TX_ANATXACONTROL0_TX1G_FRST_SM_BITS 1 5669 #define QSFI_TX_ANATXACONTROL0_TX1G_FRST_SM_SHIFT 13 5670 5671 /* QSFI_TX :: anaTxAControl0 :: tx1g_afrst_en_SM [12:12] */ 5672 #define QSFI_TX_ANATXACONTROL0_TX1G_AFRST_EN_SM_MASK 0x1000 5673 #define QSFI_TX_ANATXACONTROL0_TX1G_AFRST_EN_SM_ALIGN 0 5674 #define QSFI_TX_ANATXACONTROL0_TX1G_AFRST_EN_SM_BITS 1 5675 #define QSFI_TX_ANATXACONTROL0_TX1G_AFRST_EN_SM_SHIFT 12 5676 5677 /* QSFI_TX :: anaTxAControl0 :: tx1g_fprst_SM [11:11] */ 5678 #define QSFI_TX_ANATXACONTROL0_TX1G_FPRST_SM_MASK 0x0800 5679 #define QSFI_TX_ANATXACONTROL0_TX1G_FPRST_SM_ALIGN 0 5680 #define QSFI_TX_ANATXACONTROL0_TX1G_FPRST_SM_BITS 1 5681 #define QSFI_TX_ANATXACONTROL0_TX1G_FPRST_SM_SHIFT 11 5682 5683 /* QSFI_TX :: anaTxAControl0 :: txck_dme_en_SM [10:10] */ 5684 #define QSFI_TX_ANATXACONTROL0_TXCK_DME_EN_SM_MASK 0x0400 5685 #define QSFI_TX_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN 0 5686 #define QSFI_TX_ANATXACONTROL0_TXCK_DME_EN_SM_BITS 1 5687 #define QSFI_TX_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT 10 5688 5689 /* QSFI_TX :: anaTxAControl0 :: reserved1 [09:08] */ 5690 #define QSFI_TX_ANATXACONTROL0_RESERVED1_MASK 0x0300 5691 #define QSFI_TX_ANATXACONTROL0_RESERVED1_ALIGN 0 5692 #define QSFI_TX_ANATXACONTROL0_RESERVED1_BITS 2 5693 #define QSFI_TX_ANATXACONTROL0_RESERVED1_SHIFT 8 5694 5695 /* QSFI_TX :: anaTxAControl0 :: txStat_sel [07:07] */ 5696 #define QSFI_TX_ANATXACONTROL0_TXSTAT_SEL_MASK 0x0080 5697 #define QSFI_TX_ANATXACONTROL0_TXSTAT_SEL_ALIGN 0 5698 #define QSFI_TX_ANATXACONTROL0_TXSTAT_SEL_BITS 1 5699 #define QSFI_TX_ANATXACONTROL0_TXSTAT_SEL_SHIFT 7 5700 5701 /* QSFI_TX :: anaTxAControl0 :: tx_tstsel_SM [06:04] */ 5702 #define QSFI_TX_ANATXACONTROL0_TX_TSTSEL_SM_MASK 0x0070 5703 #define QSFI_TX_ANATXACONTROL0_TX_TSTSEL_SM_ALIGN 0 5704 #define QSFI_TX_ANATXACONTROL0_TX_TSTSEL_SM_BITS 3 5705 #define QSFI_TX_ANATXACONTROL0_TX_TSTSEL_SM_SHIFT 4 5706 5707 /* QSFI_TX :: anaTxAControl0 :: reserved2 [03:00] */ 5708 #define QSFI_TX_ANATXACONTROL0_RESERVED2_MASK 0x000f 5709 #define QSFI_TX_ANATXACONTROL0_RESERVED2_ALIGN 0 5710 #define QSFI_TX_ANATXACONTROL0_RESERVED2_BITS 4 5711 #define QSFI_TX_ANATXACONTROL0_RESERVED2_SHIFT 0 5712 5713 5714 /**************************************************************************** 5715 * QSFI_TX :: anaTxAControl6 5716 */ 5717 /* QSFI_TX :: anaTxAControl6 :: baseR_patgen_en [15:15] */ 5718 #define QSFI_TX_ANATXACONTROL6_BASER_PATGEN_EN_MASK 0x8000 5719 #define QSFI_TX_ANATXACONTROL6_BASER_PATGEN_EN_ALIGN 0 5720 #define QSFI_TX_ANATXACONTROL6_BASER_PATGEN_EN_BITS 1 5721 #define QSFI_TX_ANATXACONTROL6_BASER_PATGEN_EN_SHIFT 15 5722 5723 /* QSFI_TX :: anaTxAControl6 :: idle_fault_sel [14:13] */ 5724 #define QSFI_TX_ANATXACONTROL6_IDLE_FAULT_SEL_MASK 0x6000 5725 #define QSFI_TX_ANATXACONTROL6_IDLE_FAULT_SEL_ALIGN 0 5726 #define QSFI_TX_ANATXACONTROL6_IDLE_FAULT_SEL_BITS 2 5727 #define QSFI_TX_ANATXACONTROL6_IDLE_FAULT_SEL_SHIFT 13 5728 5729 /* QSFI_TX :: anaTxAControl6 :: baseR_patgen_sel [12:12] */ 5730 #define QSFI_TX_ANATXACONTROL6_BASER_PATGEN_SEL_MASK 0x1000 5731 #define QSFI_TX_ANATXACONTROL6_BASER_PATGEN_SEL_ALIGN 0 5732 #define QSFI_TX_ANATXACONTROL6_BASER_PATGEN_SEL_BITS 1 5733 #define QSFI_TX_ANATXACONTROL6_BASER_PATGEN_SEL_SHIFT 12 5734 5735 /* QSFI_TX :: anaTxAControl6 :: reserved0 [11:00] */ 5736 #define QSFI_TX_ANATXACONTROL6_RESERVED0_MASK 0x0fff 5737 #define QSFI_TX_ANATXACONTROL6_RESERVED0_ALIGN 0 5738 #define QSFI_TX_ANATXACONTROL6_RESERVED0_BITS 12 5739 #define QSFI_TX_ANATXACONTROL6_RESERVED0_SHIFT 0 5740 5741 5742 /**************************************************************************** 5743 * QSFI_TX :: anaTxAControl7 5744 */ 5745 /* QSFI_TX :: anaTxAControl7 :: reserved0 [15:12] */ 5746 #define QSFI_TX_ANATXACONTROL7_RESERVED0_MASK 0xf000 5747 #define QSFI_TX_ANATXACONTROL7_RESERVED0_ALIGN 0 5748 #define QSFI_TX_ANATXACONTROL7_RESERVED0_BITS 4 5749 #define QSFI_TX_ANATXACONTROL7_RESERVED0_SHIFT 12 5750 5751 /* QSFI_TX :: anaTxAControl7 :: tx_bitswap [11:11] */ 5752 #define QSFI_TX_ANATXACONTROL7_TX_BITSWAP_MASK 0x0800 5753 #define QSFI_TX_ANATXACONTROL7_TX_BITSWAP_ALIGN 0 5754 #define QSFI_TX_ANATXACONTROL7_TX_BITSWAP_BITS 1 5755 #define QSFI_TX_ANATXACONTROL7_TX_BITSWAP_SHIFT 11 5756 5757 /* QSFI_TX :: anaTxAControl7 :: pmd_ln_dp_tx_rst_SM [10:10] */ 5758 #define QSFI_TX_ANATXACONTROL7_PMD_LN_DP_TX_RST_SM_MASK 0x0400 5759 #define QSFI_TX_ANATXACONTROL7_PMD_LN_DP_TX_RST_SM_ALIGN 0 5760 #define QSFI_TX_ANATXACONTROL7_PMD_LN_DP_TX_RST_SM_BITS 1 5761 #define QSFI_TX_ANATXACONTROL7_PMD_LN_DP_TX_RST_SM_SHIFT 10 5762 5763 /* QSFI_TX :: anaTxAControl7 :: pmd_ln_tx_h_pwrdn_val_SM [09:09] */ 5764 #define QSFI_TX_ANATXACONTROL7_PMD_LN_TX_H_PWRDN_VAL_SM_MASK 0x0200 5765 #define QSFI_TX_ANATXACONTROL7_PMD_LN_TX_H_PWRDN_VAL_SM_ALIGN 0 5766 #define QSFI_TX_ANATXACONTROL7_PMD_LN_TX_H_PWRDN_VAL_SM_BITS 1 5767 #define QSFI_TX_ANATXACONTROL7_PMD_LN_TX_H_PWRDN_VAL_SM_SHIFT 9 5768 5769 /* QSFI_TX :: anaTxAControl7 :: pmd_ln_tx_h_pwrdn_enb_SM [08:08] */ 5770 #define QSFI_TX_ANATXACONTROL7_PMD_LN_TX_H_PWRDN_ENB_SM_MASK 0x0100 5771 #define QSFI_TX_ANATXACONTROL7_PMD_LN_TX_H_PWRDN_ENB_SM_ALIGN 0 5772 #define QSFI_TX_ANATXACONTROL7_PMD_LN_TX_H_PWRDN_ENB_SM_BITS 1 5773 #define QSFI_TX_ANATXACONTROL7_PMD_LN_TX_H_PWRDN_ENB_SM_SHIFT 8 5774 5775 /* QSFI_TX :: anaTxAControl7 :: reserved1 [07:06] */ 5776 #define QSFI_TX_ANATXACONTROL7_RESERVED1_MASK 0x00c0 5777 #define QSFI_TX_ANATXACONTROL7_RESERVED1_ALIGN 0 5778 #define QSFI_TX_ANATXACONTROL7_RESERVED1_BITS 2 5779 #define QSFI_TX_ANATXACONTROL7_RESERVED1_SHIFT 6 5780 5781 /* QSFI_TX :: anaTxAControl7 :: use_mgt_pmd_lock_4_tx_squelch_SM [05:05] */ 5782 #define QSFI_TX_ANATXACONTROL7_USE_MGT_PMD_LOCK_4_TX_SQUELCH_SM_MASK 0x0020 5783 #define QSFI_TX_ANATXACONTROL7_USE_MGT_PMD_LOCK_4_TX_SQUELCH_SM_ALIGN 0 5784 #define QSFI_TX_ANATXACONTROL7_USE_MGT_PMD_LOCK_4_TX_SQUELCH_SM_BITS 1 5785 #define QSFI_TX_ANATXACONTROL7_USE_MGT_PMD_LOCK_4_TX_SQUELCH_SM_SHIFT 5 5786 5787 /* QSFI_TX :: anaTxAControl7 :: tx_disable_an_good_SM [04:04] */ 5788 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_AN_GOOD_SM_MASK 0x0010 5789 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_AN_GOOD_SM_ALIGN 0 5790 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_AN_GOOD_SM_BITS 1 5791 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_AN_GOOD_SM_SHIFT 4 5792 5793 /* QSFI_TX :: anaTxAControl7 :: tx_disable_force_en_SM [03:03] */ 5794 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_FORCE_EN_SM_MASK 0x0008 5795 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_FORCE_EN_SM_ALIGN 0 5796 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_FORCE_EN_SM_BITS 1 5797 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_FORCE_EN_SM_SHIFT 3 5798 5799 /* QSFI_TX :: anaTxAControl7 :: tx_disable_force_val_SM [02:02] */ 5800 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_FORCE_VAL_SM_MASK 0x0004 5801 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_FORCE_VAL_SM_ALIGN 0 5802 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_FORCE_VAL_SM_BITS 1 5803 #define QSFI_TX_ANATXACONTROL7_TX_DISABLE_FORCE_VAL_SM_SHIFT 2 5804 5805 /* QSFI_TX :: anaTxAControl7 :: tx_squelch_force_en_SM [01:01] */ 5806 #define QSFI_TX_ANATXACONTROL7_TX_SQUELCH_FORCE_EN_SM_MASK 0x0002 5807 #define QSFI_TX_ANATXACONTROL7_TX_SQUELCH_FORCE_EN_SM_ALIGN 0 5808 #define QSFI_TX_ANATXACONTROL7_TX_SQUELCH_FORCE_EN_SM_BITS 1 5809 #define QSFI_TX_ANATXACONTROL7_TX_SQUELCH_FORCE_EN_SM_SHIFT 1 5810 5811 /* QSFI_TX :: anaTxAControl7 :: tx_squelch_force_val_SM [00:00] */ 5812 #define QSFI_TX_ANATXACONTROL7_TX_SQUELCH_FORCE_VAL_SM_MASK 0x0001 5813 #define QSFI_TX_ANATXACONTROL7_TX_SQUELCH_FORCE_VAL_SM_ALIGN 0 5814 #define QSFI_TX_ANATXACONTROL7_TX_SQUELCH_FORCE_VAL_SM_BITS 1 5815 #define QSFI_TX_ANATXACONTROL7_TX_SQUELCH_FORCE_VAL_SM_SHIFT 0 5816 5817 5818 /**************************************************************************** 5819 * merlin_gallardo_qsfi_blk_QSFI_RX 5820 */ 5821 /**************************************************************************** 5822 * QSFI_RX :: anaRxStatus 5823 */ 5824 /* QSFI_RX :: anaRxStatus :: rxStatus [15:00] */ 5825 #define QSFI_RX_ANARXSTATUS_RXSTATUS_MASK 0xffff 5826 #define QSFI_RX_ANARXSTATUS_RXSTATUS_ALIGN 0 5827 #define QSFI_RX_ANARXSTATUS_RXSTATUS_BITS 16 5828 #define QSFI_RX_ANARXSTATUS_RXSTATUS_SHIFT 0 5829 5830 5831 /**************************************************************************** 5832 * QSFI_RX :: anaRxControl 5833 */ 5834 /* QSFI_RX :: anaRxControl :: reserved0 [15:10] */ 5835 #define QSFI_RX_ANARXCONTROL_RESERVED0_MASK 0xfc00 5836 #define QSFI_RX_ANARXCONTROL_RESERVED0_ALIGN 0 5837 #define QSFI_RX_ANARXCONTROL_RESERVED0_BITS 6 5838 #define QSFI_RX_ANARXCONTROL_RESERVED0_SHIFT 10 5839 5840 /* QSFI_RX :: anaRxControl :: force_pmd_lock_SM [09:09] */ 5841 #define QSFI_RX_ANARXCONTROL_FORCE_PMD_LOCK_SM_MASK 0x0200 5842 #define QSFI_RX_ANARXCONTROL_FORCE_PMD_LOCK_SM_ALIGN 0 5843 #define QSFI_RX_ANARXCONTROL_FORCE_PMD_LOCK_SM_BITS 1 5844 #define QSFI_RX_ANARXCONTROL_FORCE_PMD_LOCK_SM_SHIFT 9 5845 5846 /* QSFI_RX :: anaRxControl :: force_pmd_lock_val_SM [08:08] */ 5847 #define QSFI_RX_ANARXCONTROL_FORCE_PMD_LOCK_VAL_SM_MASK 0x0100 5848 #define QSFI_RX_ANARXCONTROL_FORCE_PMD_LOCK_VAL_SM_ALIGN 0 5849 #define QSFI_RX_ANARXCONTROL_FORCE_PMD_LOCK_VAL_SM_BITS 1 5850 #define QSFI_RX_ANARXCONTROL_FORCE_PMD_LOCK_VAL_SM_SHIFT 8 5851 5852 /* QSFI_RX :: anaRxControl :: use_cl73_an_good_KR4_SM [07:07] */ 5853 #define QSFI_RX_ANARXCONTROL_USE_CL73_AN_GOOD_KR4_SM_MASK 0x0080 5854 #define QSFI_RX_ANARXCONTROL_USE_CL73_AN_GOOD_KR4_SM_ALIGN 0 5855 #define QSFI_RX_ANARXCONTROL_USE_CL73_AN_GOOD_KR4_SM_BITS 1 5856 #define QSFI_RX_ANARXCONTROL_USE_CL73_AN_GOOD_KR4_SM_SHIFT 7 5857 5858 /* QSFI_RX :: anaRxControl :: use_cl73_an_good_SM [06:06] */ 5859 #define QSFI_RX_ANARXCONTROL_USE_CL73_AN_GOOD_SM_MASK 0x0040 5860 #define QSFI_RX_ANARXCONTROL_USE_CL73_AN_GOOD_SM_ALIGN 0 5861 #define QSFI_RX_ANARXCONTROL_USE_CL73_AN_GOOD_SM_BITS 1 5862 #define QSFI_RX_ANARXCONTROL_USE_CL73_AN_GOOD_SM_SHIFT 6 5863 5864 /* QSFI_RX :: anaRxControl :: forceRxSeqDone_en_SM [05:05] */ 5865 #define QSFI_RX_ANARXCONTROL_FORCERXSEQDONE_EN_SM_MASK 0x0020 5866 #define QSFI_RX_ANARXCONTROL_FORCERXSEQDONE_EN_SM_ALIGN 0 5867 #define QSFI_RX_ANARXCONTROL_FORCERXSEQDONE_EN_SM_BITS 1 5868 #define QSFI_RX_ANARXCONTROL_FORCERXSEQDONE_EN_SM_SHIFT 5 5869 5870 /* QSFI_RX :: anaRxControl :: forceRxSeqDone_val_SM [04:04] */ 5871 #define QSFI_RX_ANARXCONTROL_FORCERXSEQDONE_VAL_SM_MASK 0x0010 5872 #define QSFI_RX_ANARXCONTROL_FORCERXSEQDONE_VAL_SM_ALIGN 0 5873 #define QSFI_RX_ANARXCONTROL_FORCERXSEQDONE_VAL_SM_BITS 1 5874 #define QSFI_RX_ANARXCONTROL_FORCERXSEQDONE_VAL_SM_SHIFT 4 5875 5876 /* QSFI_RX :: anaRxControl :: reserved1 [03:03] */ 5877 #define QSFI_RX_ANARXCONTROL_RESERVED1_MASK 0x0008 5878 #define QSFI_RX_ANARXCONTROL_RESERVED1_ALIGN 0 5879 #define QSFI_RX_ANARXCONTROL_RESERVED1_BITS 1 5880 #define QSFI_RX_ANARXCONTROL_RESERVED1_SHIFT 3 5881 5882 /* QSFI_RX :: anaRxControl :: status_sel [02:00] */ 5883 #define QSFI_RX_ANARXCONTROL_STATUS_SEL_MASK 0x0007 5884 #define QSFI_RX_ANARXCONTROL_STATUS_SEL_ALIGN 0 5885 #define QSFI_RX_ANARXCONTROL_STATUS_SEL_BITS 3 5886 #define QSFI_RX_ANARXCONTROL_STATUS_SEL_SHIFT 0 5887 5888 5889 /**************************************************************************** 5890 * QSFI_RX :: anaRxSigdet 5891 */ 5892 /* QSFI_RX :: anaRxSigdet :: reserved0 [15:05] */ 5893 #define QSFI_RX_ANARXSIGDET_RESERVED0_MASK 0xffe0 5894 #define QSFI_RX_ANARXSIGDET_RESERVED0_ALIGN 0 5895 #define QSFI_RX_ANARXSIGDET_RESERVED0_BITS 11 5896 #define QSFI_RX_ANARXSIGDET_RESERVED0_SHIFT 5 5897 5898 /* QSFI_RX :: anaRxSigdet :: rx_sigdet_r [04:04] */ 5899 #define QSFI_RX_ANARXSIGDET_RX_SIGDET_R_MASK 0x0010 5900 #define QSFI_RX_ANARXSIGDET_RX_SIGDET_R_ALIGN 0 5901 #define QSFI_RX_ANARXSIGDET_RX_SIGDET_R_BITS 1 5902 #define QSFI_RX_ANARXSIGDET_RX_SIGDET_R_SHIFT 4 5903 5904 /* QSFI_RX :: anaRxSigdet :: rx_sigdet_force_r [03:03] */ 5905 #define QSFI_RX_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK 0x0008 5906 #define QSFI_RX_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN 0 5907 #define QSFI_RX_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS 1 5908 #define QSFI_RX_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT 3 5909 5910 /* QSFI_RX :: anaRxSigdet :: reserved1 [02:00] */ 5911 #define QSFI_RX_ANARXSIGDET_RESERVED1_MASK 0x0007 5912 #define QSFI_RX_ANARXSIGDET_RESERVED1_ALIGN 0 5913 #define QSFI_RX_ANARXSIGDET_RESERVED1_BITS 3 5914 #define QSFI_RX_ANARXSIGDET_RESERVED1_SHIFT 0 5915 5916 5917 /**************************************************************************** 5918 * QSFI_RX :: anaRxControl2 5919 */ 5920 /* QSFI_RX :: anaRxControl2 :: reserved0 [15:12] */ 5921 #define QSFI_RX_ANARXCONTROL2_RESERVED0_MASK 0xf000 5922 #define QSFI_RX_ANARXCONTROL2_RESERVED0_ALIGN 0 5923 #define QSFI_RX_ANARXCONTROL2_RESERVED0_BITS 4 5924 #define QSFI_RX_ANARXCONTROL2_RESERVED0_SHIFT 12 5925 5926 /* QSFI_RX :: anaRxControl2 :: rx_bitswap [11:11] */ 5927 #define QSFI_RX_ANARXCONTROL2_RX_BITSWAP_MASK 0x0800 5928 #define QSFI_RX_ANARXCONTROL2_RX_BITSWAP_ALIGN 0 5929 #define QSFI_RX_ANARXCONTROL2_RX_BITSWAP_BITS 1 5930 #define QSFI_RX_ANARXCONTROL2_RX_BITSWAP_SHIFT 11 5931 5932 /* QSFI_RX :: anaRxControl2 :: pmd_ln_rx_h_pwrdn_enb_SM [10:10] */ 5933 #define QSFI_RX_ANARXCONTROL2_PMD_LN_RX_H_PWRDN_ENB_SM_MASK 0x0400 5934 #define QSFI_RX_ANARXCONTROL2_PMD_LN_RX_H_PWRDN_ENB_SM_ALIGN 0 5935 #define QSFI_RX_ANARXCONTROL2_PMD_LN_RX_H_PWRDN_ENB_SM_BITS 1 5936 #define QSFI_RX_ANARXCONTROL2_PMD_LN_RX_H_PWRDN_ENB_SM_SHIFT 10 5937 5938 /* QSFI_RX :: anaRxControl2 :: pmd_ln_rx_h_pwrdn_val_SM [09:09] */ 5939 #define QSFI_RX_ANARXCONTROL2_PMD_LN_RX_H_PWRDN_VAL_SM_MASK 0x0200 5940 #define QSFI_RX_ANARXCONTROL2_PMD_LN_RX_H_PWRDN_VAL_SM_ALIGN 0 5941 #define QSFI_RX_ANARXCONTROL2_PMD_LN_RX_H_PWRDN_VAL_SM_BITS 1 5942 #define QSFI_RX_ANARXCONTROL2_PMD_LN_RX_H_PWRDN_VAL_SM_SHIFT 9 5943 5944 /* QSFI_RX :: anaRxControl2 :: pmd_ln_dp_rx_rst_SM [08:08] */ 5945 #define QSFI_RX_ANARXCONTROL2_PMD_LN_DP_RX_RST_SM_MASK 0x0100 5946 #define QSFI_RX_ANARXCONTROL2_PMD_LN_DP_RX_RST_SM_ALIGN 0 5947 #define QSFI_RX_ANARXCONTROL2_PMD_LN_DP_RX_RST_SM_BITS 1 5948 #define QSFI_RX_ANARXCONTROL2_PMD_LN_DP_RX_RST_SM_SHIFT 8 5949 5950 /* QSFI_RX :: anaRxControl2 :: reserved1 [07:02] */ 5951 #define QSFI_RX_ANARXCONTROL2_RESERVED1_MASK 0x00fc 5952 #define QSFI_RX_ANARXCONTROL2_RESERVED1_ALIGN 0 5953 #define QSFI_RX_ANARXCONTROL2_RESERVED1_BITS 6 5954 #define QSFI_RX_ANARXCONTROL2_RESERVED1_SHIFT 2 5955 5956 /* QSFI_RX :: anaRxControl2 :: rxtm_tstsel_SM [01:00] */ 5957 #define QSFI_RX_ANARXCONTROL2_RXTM_TSTSEL_SM_MASK 0x0003 5958 #define QSFI_RX_ANARXCONTROL2_RXTM_TSTSEL_SM_ALIGN 0 5959 #define QSFI_RX_ANARXCONTROL2_RXTM_TSTSEL_SM_BITS 2 5960 #define QSFI_RX_ANARXCONTROL2_RXTM_TSTSEL_SM_SHIFT 0 5961 5962 5963 /**************************************************************************** 5964 * QSFI_RX :: anaRxControl3 5965 */ 5966 /* QSFI_RX :: anaRxControl3 :: rxck_dme_en_force [15:15] */ 5967 #define QSFI_RX_ANARXCONTROL3_RXCK_DME_EN_FORCE_MASK 0x8000 5968 #define QSFI_RX_ANARXCONTROL3_RXCK_DME_EN_FORCE_ALIGN 0 5969 #define QSFI_RX_ANARXCONTROL3_RXCK_DME_EN_FORCE_BITS 1 5970 #define QSFI_RX_ANARXCONTROL3_RXCK_DME_EN_FORCE_SHIFT 15 5971 5972 /* QSFI_RX :: anaRxControl3 :: rxck_dme_en_r [14:14] */ 5973 #define QSFI_RX_ANARXCONTROL3_RXCK_DME_EN_R_MASK 0x4000 5974 #define QSFI_RX_ANARXCONTROL3_RXCK_DME_EN_R_ALIGN 0 5975 #define QSFI_RX_ANARXCONTROL3_RXCK_DME_EN_R_BITS 1 5976 #define QSFI_RX_ANARXCONTROL3_RXCK_DME_EN_R_SHIFT 14 5977 5978 /* QSFI_RX :: anaRxControl3 :: rst_dme_en_force [13:13] */ 5979 #define QSFI_RX_ANARXCONTROL3_RST_DME_EN_FORCE_MASK 0x2000 5980 #define QSFI_RX_ANARXCONTROL3_RST_DME_EN_FORCE_ALIGN 0 5981 #define QSFI_RX_ANARXCONTROL3_RST_DME_EN_FORCE_BITS 1 5982 #define QSFI_RX_ANARXCONTROL3_RST_DME_EN_FORCE_SHIFT 13 5983 5984 /* QSFI_RX :: anaRxControl3 :: rst_dme_en_r [12:12] */ 5985 #define QSFI_RX_ANARXCONTROL3_RST_DME_EN_R_MASK 0x1000 5986 #define QSFI_RX_ANARXCONTROL3_RST_DME_EN_R_ALIGN 0 5987 #define QSFI_RX_ANARXCONTROL3_RST_DME_EN_R_BITS 1 5988 #define QSFI_RX_ANARXCONTROL3_RST_DME_EN_R_SHIFT 12 5989 5990 /* QSFI_RX :: anaRxControl3 :: cl73_clk25_rst_SM [11:11] */ 5991 #define QSFI_RX_ANARXCONTROL3_CL73_CLK25_RST_SM_MASK 0x0800 5992 #define QSFI_RX_ANARXCONTROL3_CL73_CLK25_RST_SM_ALIGN 0 5993 #define QSFI_RX_ANARXCONTROL3_CL73_CLK25_RST_SM_BITS 1 5994 #define QSFI_RX_ANARXCONTROL3_CL73_CLK25_RST_SM_SHIFT 11 5995 5996 /* QSFI_RX :: anaRxControl3 :: cl73_clk25_en_SM [10:10] */ 5997 #define QSFI_RX_ANARXCONTROL3_CL73_CLK25_EN_SM_MASK 0x0400 5998 #define QSFI_RX_ANARXCONTROL3_CL73_CLK25_EN_SM_ALIGN 0 5999 #define QSFI_RX_ANARXCONTROL3_CL73_CLK25_EN_SM_BITS 1 6000 #define QSFI_RX_ANARXCONTROL3_CL73_CLK25_EN_SM_SHIFT 10 6001 6002 /* QSFI_RX :: anaRxControl3 :: cl73_gloop_en_SM [09:09] */ 6003 #define QSFI_RX_ANARXCONTROL3_CL73_GLOOP_EN_SM_MASK 0x0200 6004 #define QSFI_RX_ANARXCONTROL3_CL73_GLOOP_EN_SM_ALIGN 0 6005 #define QSFI_RX_ANARXCONTROL3_CL73_GLOOP_EN_SM_BITS 1 6006 #define QSFI_RX_ANARXCONTROL3_CL73_GLOOP_EN_SM_SHIFT 9 6007 6008 /* QSFI_RX :: anaRxControl3 :: cl73_rloop_en_SM [08:08] */ 6009 #define QSFI_RX_ANARXCONTROL3_CL73_RLOOP_EN_SM_MASK 0x0100 6010 #define QSFI_RX_ANARXCONTROL3_CL73_RLOOP_EN_SM_ALIGN 0 6011 #define QSFI_RX_ANARXCONTROL3_CL73_RLOOP_EN_SM_BITS 1 6012 #define QSFI_RX_ANARXCONTROL3_CL73_RLOOP_EN_SM_SHIFT 8 6013 6014 /* QSFI_RX :: anaRxControl3 :: use_KR_block_lock_SM [07:07] */ 6015 #define QSFI_RX_ANARXCONTROL3_USE_KR_BLOCK_LOCK_SM_MASK 0x0080 6016 #define QSFI_RX_ANARXCONTROL3_USE_KR_BLOCK_LOCK_SM_ALIGN 0 6017 #define QSFI_RX_ANARXCONTROL3_USE_KR_BLOCK_LOCK_SM_BITS 1 6018 #define QSFI_RX_ANARXCONTROL3_USE_KR_BLOCK_LOCK_SM_SHIFT 7 6019 6020 /* QSFI_RX :: anaRxControl3 :: use_KR4_block_lock_SM [06:06] */ 6021 #define QSFI_RX_ANARXCONTROL3_USE_KR4_BLOCK_LOCK_SM_MASK 0x0040 6022 #define QSFI_RX_ANARXCONTROL3_USE_KR4_BLOCK_LOCK_SM_ALIGN 0 6023 #define QSFI_RX_ANARXCONTROL3_USE_KR4_BLOCK_LOCK_SM_BITS 1 6024 #define QSFI_RX_ANARXCONTROL3_USE_KR4_BLOCK_LOCK_SM_SHIFT 6 6025 6026 /* QSFI_RX :: anaRxControl3 :: link_en_force_SM [05:05] */ 6027 #define QSFI_RX_ANARXCONTROL3_LINK_EN_FORCE_SM_MASK 0x0020 6028 #define QSFI_RX_ANARXCONTROL3_LINK_EN_FORCE_SM_ALIGN 0 6029 #define QSFI_RX_ANARXCONTROL3_LINK_EN_FORCE_SM_BITS 1 6030 #define QSFI_RX_ANARXCONTROL3_LINK_EN_FORCE_SM_SHIFT 5 6031 6032 /* QSFI_RX :: anaRxControl3 :: link_en_r [04:04] */ 6033 #define QSFI_RX_ANARXCONTROL3_LINK_EN_R_MASK 0x0010 6034 #define QSFI_RX_ANARXCONTROL3_LINK_EN_R_ALIGN 0 6035 #define QSFI_RX_ANARXCONTROL3_LINK_EN_R_BITS 1 6036 #define QSFI_RX_ANARXCONTROL3_LINK_EN_R_SHIFT 4 6037 6038 /* QSFI_RX :: anaRxControl3 :: use_KR4_pmd_lock_SM [03:03] */ 6039 #define QSFI_RX_ANARXCONTROL3_USE_KR4_PMD_LOCK_SM_MASK 0x0008 6040 #define QSFI_RX_ANARXCONTROL3_USE_KR4_PMD_LOCK_SM_ALIGN 0 6041 #define QSFI_RX_ANARXCONTROL3_USE_KR4_PMD_LOCK_SM_BITS 1 6042 #define QSFI_RX_ANARXCONTROL3_USE_KR4_PMD_LOCK_SM_SHIFT 3 6043 6044 /* QSFI_RX :: anaRxControl3 :: cl82_en_SM [02:02] */ 6045 #define QSFI_RX_ANARXCONTROL3_CL82_EN_SM_MASK 0x0004 6046 #define QSFI_RX_ANARXCONTROL3_CL82_EN_SM_ALIGN 0 6047 #define QSFI_RX_ANARXCONTROL3_CL82_EN_SM_BITS 1 6048 #define QSFI_RX_ANARXCONTROL3_CL82_EN_SM_SHIFT 2 6049 6050 /* QSFI_RX :: anaRxControl3 :: cl49_dis_SM [01:01] */ 6051 #define QSFI_RX_ANARXCONTROL3_CL49_DIS_SM_MASK 0x0002 6052 #define QSFI_RX_ANARXCONTROL3_CL49_DIS_SM_ALIGN 0 6053 #define QSFI_RX_ANARXCONTROL3_CL49_DIS_SM_BITS 1 6054 #define QSFI_RX_ANARXCONTROL3_CL49_DIS_SM_SHIFT 1 6055 6056 /* QSFI_RX :: anaRxControl3 :: indck_os5_mode_dis_rx_SM [00:00] */ 6057 #define QSFI_RX_ANARXCONTROL3_INDCK_OS5_MODE_DIS_RX_SM_MASK 0x0001 6058 #define QSFI_RX_ANARXCONTROL3_INDCK_OS5_MODE_DIS_RX_SM_ALIGN 0 6059 #define QSFI_RX_ANARXCONTROL3_INDCK_OS5_MODE_DIS_RX_SM_BITS 1 6060 #define QSFI_RX_ANARXCONTROL3_INDCK_OS5_MODE_DIS_RX_SM_SHIFT 0 6061 6062 6063 /**************************************************************************** 6064 * merlin_gallardo_qsfi_blk_QSFI_XGXS_BLK2 6065 */ 6066 /**************************************************************************** 6067 * QSFI_XGXS_BLK2 :: laneReset 6068 */ 6069 /* QSFI_XGXS_BLK2 :: laneReset :: reset_mdio [15:15] */ 6070 #define QSFI_XGXS_BLK2_LANERESET_RESET_MDIO_MASK 0x8000 6071 #define QSFI_XGXS_BLK2_LANERESET_RESET_MDIO_ALIGN 0 6072 #define QSFI_XGXS_BLK2_LANERESET_RESET_MDIO_BITS 1 6073 #define QSFI_XGXS_BLK2_LANERESET_RESET_MDIO_SHIFT 15 6074 6075 /* QSFI_XGXS_BLK2 :: laneReset :: reserved0 [14:09] */ 6076 #define QSFI_XGXS_BLK2_LANERESET_RESERVED0_MASK 0x7e00 6077 #define QSFI_XGXS_BLK2_LANERESET_RESERVED0_ALIGN 0 6078 #define QSFI_XGXS_BLK2_LANERESET_RESERVED0_BITS 6 6079 #define QSFI_XGXS_BLK2_LANERESET_RESERVED0_SHIFT 9 6080 6081 /* QSFI_XGXS_BLK2 :: laneReset :: reset_pll [08:08] */ 6082 #define QSFI_XGXS_BLK2_LANERESET_RESET_PLL_MASK 0x0100 6083 #define QSFI_XGXS_BLK2_LANERESET_RESET_PLL_ALIGN 0 6084 #define QSFI_XGXS_BLK2_LANERESET_RESET_PLL_BITS 1 6085 #define QSFI_XGXS_BLK2_LANERESET_RESET_PLL_SHIFT 8 6086 6087 /* QSFI_XGXS_BLK2 :: laneReset :: reserved1 [07:04] */ 6088 #define QSFI_XGXS_BLK2_LANERESET_RESERVED1_MASK 0x00f0 6089 #define QSFI_XGXS_BLK2_LANERESET_RESERVED1_ALIGN 0 6090 #define QSFI_XGXS_BLK2_LANERESET_RESERVED1_BITS 4 6091 #define QSFI_XGXS_BLK2_LANERESET_RESERVED1_SHIFT 4 6092 6093 /* QSFI_XGXS_BLK2 :: laneReset :: lane_reset [03:00] */ 6094 #define QSFI_XGXS_BLK2_LANERESET_LANE_RESET_MASK 0x000f 6095 #define QSFI_XGXS_BLK2_LANERESET_LANE_RESET_ALIGN 0 6096 #define QSFI_XGXS_BLK2_LANERESET_LANE_RESET_BITS 4 6097 #define QSFI_XGXS_BLK2_LANERESET_LANE_RESET_SHIFT 0 6098 6099 6100 /**************************************************************************** 6101 * merlin_gallardo_qsfi_blk_QSFI_XGXS_BLK8 6102 */ 6103 /**************************************************************************** 6104 * QSFI_XGXS_BLK8 :: cl73Control8 6105 */ 6106 /* QSFI_XGXS_BLK8 :: cl73Control8 :: cl73_refclk_161_offset_cnt [15:08] */ 6107 #define QSFI_XGXS_BLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_MASK 0xff00 6108 #define QSFI_XGXS_BLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_ALIGN 0 6109 #define QSFI_XGXS_BLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_BITS 8 6110 #define QSFI_XGXS_BLK8_CL73CONTROL8_CL73_REFCLK_161_OFFSET_CNT_SHIFT 8 6111 6112 /* QSFI_XGXS_BLK8 :: cl73Control8 :: reserved0 [07:00] */ 6113 #define QSFI_XGXS_BLK8_CL73CONTROL8_RESERVED0_MASK 0x00ff 6114 #define QSFI_XGXS_BLK8_CL73CONTROL8_RESERVED0_ALIGN 0 6115 #define QSFI_XGXS_BLK8_CL73CONTROL8_RESERVED0_BITS 8 6116 #define QSFI_XGXS_BLK8_CL73CONTROL8_RESERVED0_SHIFT 0 6117 6118 6119 /**************************************************************************** 6120 * QSFI_XGXS_BLK8 :: cl73Control9 6121 */ 6122 /* QSFI_XGXS_BLK8 :: cl73Control9 :: reserved0 [15:14] */ 6123 #define QSFI_XGXS_BLK8_CL73CONTROL9_RESERVED0_MASK 0xc000 6124 #define QSFI_XGXS_BLK8_CL73CONTROL9_RESERVED0_ALIGN 0 6125 #define QSFI_XGXS_BLK8_CL73CONTROL9_RESERVED0_BITS 2 6126 #define QSFI_XGXS_BLK8_CL73CONTROL9_RESERVED0_SHIFT 14 6127 6128 /* QSFI_XGXS_BLK8 :: cl73Control9 :: cl73_link_fail_inhibit_timer_kr_val [13:00] */ 6129 #define QSFI_XGXS_BLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_MASK 0x3fff 6130 #define QSFI_XGXS_BLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_ALIGN 0 6131 #define QSFI_XGXS_BLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_BITS 14 6132 #define QSFI_XGXS_BLK8_CL73CONTROL9_CL73_LINK_FAIL_INHIBIT_TIMER_KR_VAL_SHIFT 0 6133 6134 6135 /**************************************************************************** 6136 * QSFI_XGXS_BLK8 :: cl73Control10 6137 */ 6138 /* QSFI_XGXS_BLK8 :: cl73Control10 :: reserved0 [15:14] */ 6139 #define QSFI_XGXS_BLK8_CL73CONTROL10_RESERVED0_MASK 0xc000 6140 #define QSFI_XGXS_BLK8_CL73CONTROL10_RESERVED0_ALIGN 0 6141 #define QSFI_XGXS_BLK8_CL73CONTROL10_RESERVED0_BITS 2 6142 #define QSFI_XGXS_BLK8_CL73CONTROL10_RESERVED0_SHIFT 14 6143 6144 /* QSFI_XGXS_BLK8 :: cl73Control10 :: cl73_link_fail_inhibit_timer_cl72_val [13:00] */ 6145 #define QSFI_XGXS_BLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_MASK 0x3fff 6146 #define QSFI_XGXS_BLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_ALIGN 0 6147 #define QSFI_XGXS_BLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_BITS 14 6148 #define QSFI_XGXS_BLK8_CL73CONTROL10_CL73_LINK_FAIL_INHIBIT_TIMER_CL72_VAL_SHIFT 0 6149 6150 6151 /**************************************************************************** 6152 * merlin_gallardo_qsfi_blk_QSFI_GP2 6153 */ 6154 /**************************************************************************** 6155 * QSFI_GP2 :: GP2_0 6156 */ 6157 /* QSFI_GP2 :: GP2_0 :: pmd_pll_mode [15:12] */ 6158 #define QSFI_GP2_GP2_0_PMD_PLL_MODE_MASK 0xf000 6159 #define QSFI_GP2_GP2_0_PMD_PLL_MODE_ALIGN 0 6160 #define QSFI_GP2_GP2_0_PMD_PLL_MODE_BITS 4 6161 #define QSFI_GP2_GP2_0_PMD_PLL_MODE_SHIFT 12 6162 6163 /* QSFI_GP2 :: GP2_0 :: pmd_rx_sigdet [11:08] */ 6164 #define QSFI_GP2_GP2_0_PMD_RX_SIGDET_MASK 0x0f00 6165 #define QSFI_GP2_GP2_0_PMD_RX_SIGDET_ALIGN 0 6166 #define QSFI_GP2_GP2_0_PMD_RX_SIGDET_BITS 4 6167 #define QSFI_GP2_GP2_0_PMD_RX_SIGDET_SHIFT 8 6168 6169 /* QSFI_GP2 :: GP2_0 :: pmd_tx_clk_vld [07:04] */ 6170 #define QSFI_GP2_GP2_0_PMD_TX_CLK_VLD_MASK 0x00f0 6171 #define QSFI_GP2_GP2_0_PMD_TX_CLK_VLD_ALIGN 0 6172 #define QSFI_GP2_GP2_0_PMD_TX_CLK_VLD_BITS 4 6173 #define QSFI_GP2_GP2_0_PMD_TX_CLK_VLD_SHIFT 4 6174 6175 /* QSFI_GP2 :: GP2_0 :: pmd_rx_pmd_lock [03:00] */ 6176 #define QSFI_GP2_GP2_0_PMD_RX_PMD_LOCK_MASK 0x000f 6177 #define QSFI_GP2_GP2_0_PMD_RX_PMD_LOCK_ALIGN 0 6178 #define QSFI_GP2_GP2_0_PMD_RX_PMD_LOCK_BITS 4 6179 #define QSFI_GP2_GP2_0_PMD_RX_PMD_LOCK_SHIFT 0 6180 6181 6182 /**************************************************************************** 6183 * QSFI_GP2 :: GP2_1 6184 */ 6185 /* QSFI_GP2 :: GP2_1 :: pmd_osr_mode_ln3 [15:12] */ 6186 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN3_MASK 0xf000 6187 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN3_ALIGN 0 6188 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN3_BITS 4 6189 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN3_SHIFT 12 6190 6191 /* QSFI_GP2 :: GP2_1 :: pmd_osr_mode_ln2 [11:08] */ 6192 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN2_MASK 0x0f00 6193 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN2_ALIGN 0 6194 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN2_BITS 4 6195 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN2_SHIFT 8 6196 6197 /* QSFI_GP2 :: GP2_1 :: pmd_osr_mode_ln1 [07:04] */ 6198 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN1_MASK 0x00f0 6199 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN1_ALIGN 0 6200 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN1_BITS 4 6201 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN1_SHIFT 4 6202 6203 /* QSFI_GP2 :: GP2_1 :: pmd_osr_mode_ln0 [03:00] */ 6204 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN0_MASK 0x000f 6205 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN0_ALIGN 0 6206 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN0_BITS 4 6207 #define QSFI_GP2_GP2_1_PMD_OSR_MODE_LN0_SHIFT 0 6208 6209 6210 /**************************************************************************** 6211 * QSFI_GP2 :: GP2_2 6212 */ 6213 /* QSFI_GP2 :: GP2_2 :: reserved0 [15:15] */ 6214 #define QSFI_GP2_GP2_2_RESERVED0_MASK 0x8000 6215 #define QSFI_GP2_GP2_2_RESERVED0_ALIGN 0 6216 #define QSFI_GP2_GP2_2_RESERVED0_BITS 1 6217 #define QSFI_GP2_GP2_2_RESERVED0_SHIFT 15 6218 6219 /* QSFI_GP2 :: GP2_2 :: actual_speed_ln1 [14:08] */ 6220 #define QSFI_GP2_GP2_2_ACTUAL_SPEED_LN1_MASK 0x7f00 6221 #define QSFI_GP2_GP2_2_ACTUAL_SPEED_LN1_ALIGN 0 6222 #define QSFI_GP2_GP2_2_ACTUAL_SPEED_LN1_BITS 7 6223 #define QSFI_GP2_GP2_2_ACTUAL_SPEED_LN1_SHIFT 8 6224 6225 /* QSFI_GP2 :: GP2_2 :: reserved1 [07:07] */ 6226 #define QSFI_GP2_GP2_2_RESERVED1_MASK 0x0080 6227 #define QSFI_GP2_GP2_2_RESERVED1_ALIGN 0 6228 #define QSFI_GP2_GP2_2_RESERVED1_BITS 1 6229 #define QSFI_GP2_GP2_2_RESERVED1_SHIFT 7 6230 6231 /* QSFI_GP2 :: GP2_2 :: actual_speed_ln0 [06:00] */ 6232 #define QSFI_GP2_GP2_2_ACTUAL_SPEED_LN0_MASK 0x007f 6233 #define QSFI_GP2_GP2_2_ACTUAL_SPEED_LN0_ALIGN 0 6234 #define QSFI_GP2_GP2_2_ACTUAL_SPEED_LN0_BITS 7 6235 #define QSFI_GP2_GP2_2_ACTUAL_SPEED_LN0_SHIFT 0 6236 6237 6238 /**************************************************************************** 6239 * QSFI_GP2 :: GP2_3 6240 */ 6241 /* QSFI_GP2 :: GP2_3 :: reserved0 [15:15] */ 6242 #define QSFI_GP2_GP2_3_RESERVED0_MASK 0x8000 6243 #define QSFI_GP2_GP2_3_RESERVED0_ALIGN 0 6244 #define QSFI_GP2_GP2_3_RESERVED0_BITS 1 6245 #define QSFI_GP2_GP2_3_RESERVED0_SHIFT 15 6246 6247 /* QSFI_GP2 :: GP2_3 :: actual_speed_ln3 [14:08] */ 6248 #define QSFI_GP2_GP2_3_ACTUAL_SPEED_LN3_MASK 0x7f00 6249 #define QSFI_GP2_GP2_3_ACTUAL_SPEED_LN3_ALIGN 0 6250 #define QSFI_GP2_GP2_3_ACTUAL_SPEED_LN3_BITS 7 6251 #define QSFI_GP2_GP2_3_ACTUAL_SPEED_LN3_SHIFT 8 6252 6253 /* QSFI_GP2 :: GP2_3 :: reserved1 [07:07] */ 6254 #define QSFI_GP2_GP2_3_RESERVED1_MASK 0x0080 6255 #define QSFI_GP2_GP2_3_RESERVED1_ALIGN 0 6256 #define QSFI_GP2_GP2_3_RESERVED1_BITS 1 6257 #define QSFI_GP2_GP2_3_RESERVED1_SHIFT 7 6258 6259 /* QSFI_GP2 :: GP2_3 :: actual_speed_ln2 [06:00] */ 6260 #define QSFI_GP2_GP2_3_ACTUAL_SPEED_LN2_MASK 0x007f 6261 #define QSFI_GP2_GP2_3_ACTUAL_SPEED_LN2_ALIGN 0 6262 #define QSFI_GP2_GP2_3_ACTUAL_SPEED_LN2_BITS 7 6263 #define QSFI_GP2_GP2_3_ACTUAL_SPEED_LN2_SHIFT 0 6264 6265 6266 /**************************************************************************** 6267 * QSFI_GP2 :: GP2_4 6268 */ 6269 /* QSFI_GP2 :: GP2_4 :: cl73_autoneg_complete [15:12] */ 6270 #define QSFI_GP2_GP2_4_CL73_AUTONEG_COMPLETE_MASK 0xf000 6271 #define QSFI_GP2_GP2_4_CL73_AUTONEG_COMPLETE_ALIGN 0 6272 #define QSFI_GP2_GP2_4_CL73_AUTONEG_COMPLETE_BITS 4 6273 #define QSFI_GP2_GP2_4_CL73_AUTONEG_COMPLETE_SHIFT 12 6274 6275 /* QSFI_GP2 :: GP2_4 :: pmd_rx_dme_en [11:08] */ 6276 #define QSFI_GP2_GP2_4_PMD_RX_DME_EN_MASK 0x0f00 6277 #define QSFI_GP2_GP2_4_PMD_RX_DME_EN_ALIGN 0 6278 #define QSFI_GP2_GP2_4_PMD_RX_DME_EN_BITS 4 6279 #define QSFI_GP2_GP2_4_PMD_RX_DME_EN_SHIFT 8 6280 6281 /* QSFI_GP2 :: GP2_4 :: cl73_mr_lp_autoneg_able [07:04] */ 6282 #define QSFI_GP2_GP2_4_CL73_MR_LP_AUTONEG_ABLE_MASK 0x00f0 6283 #define QSFI_GP2_GP2_4_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 6284 #define QSFI_GP2_GP2_4_CL73_MR_LP_AUTONEG_ABLE_BITS 4 6285 #define QSFI_GP2_GP2_4_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 6286 6287 /* QSFI_GP2 :: GP2_4 :: cl73_mr_autoneg_able [03:00] */ 6288 #define QSFI_GP2_GP2_4_CL73_MR_AUTONEG_ABLE_MASK 0x000f 6289 #define QSFI_GP2_GP2_4_CL73_MR_AUTONEG_ABLE_ALIGN 0 6290 #define QSFI_GP2_GP2_4_CL73_MR_AUTONEG_ABLE_BITS 4 6291 #define QSFI_GP2_GP2_4_CL73_MR_AUTONEG_ABLE_SHIFT 0 6292 6293 6294 /**************************************************************************** 6295 * QSFI_GP2 :: GP2_5 6296 */ 6297 /* QSFI_GP2 :: GP2_5 :: Cl73_BAMStat123_ln0 [15:00] */ 6298 #define QSFI_GP2_GP2_5_CL73_BAMSTAT123_LN0_MASK 0xffff 6299 #define QSFI_GP2_GP2_5_CL73_BAMSTAT123_LN0_ALIGN 0 6300 #define QSFI_GP2_GP2_5_CL73_BAMSTAT123_LN0_BITS 16 6301 #define QSFI_GP2_GP2_5_CL73_BAMSTAT123_LN0_SHIFT 0 6302 6303 6304 /**************************************************************************** 6305 * QSFI_GP2 :: GP2_6 6306 */ 6307 /* QSFI_GP2 :: GP2_6 :: Cl73_BAMStat123_ln0 [15:00] */ 6308 #define QSFI_GP2_GP2_6_CL73_BAMSTAT123_LN0_MASK 0xffff 6309 #define QSFI_GP2_GP2_6_CL73_BAMSTAT123_LN0_ALIGN 0 6310 #define QSFI_GP2_GP2_6_CL73_BAMSTAT123_LN0_BITS 16 6311 #define QSFI_GP2_GP2_6_CL73_BAMSTAT123_LN0_SHIFT 0 6312 6313 6314 /**************************************************************************** 6315 * QSFI_GP2 :: GP2_7 6316 */ 6317 /* QSFI_GP2 :: GP2_7 :: Cl73_BAMStat123_ln0 [15:00] */ 6318 #define QSFI_GP2_GP2_7_CL73_BAMSTAT123_LN0_MASK 0xffff 6319 #define QSFI_GP2_GP2_7_CL73_BAMSTAT123_LN0_ALIGN 0 6320 #define QSFI_GP2_GP2_7_CL73_BAMSTAT123_LN0_BITS 16 6321 #define QSFI_GP2_GP2_7_CL73_BAMSTAT123_LN0_SHIFT 0 6322 6323 6324 /**************************************************************************** 6325 * QSFI_GP2 :: GP2_8 6326 */ 6327 /* QSFI_GP2 :: GP2_8 :: reserved0 [15:15] */ 6328 #define QSFI_GP2_GP2_8_RESERVED0_MASK 0x8000 6329 #define QSFI_GP2_GP2_8_RESERVED0_ALIGN 0 6330 #define QSFI_GP2_GP2_8_RESERVED0_BITS 1 6331 #define QSFI_GP2_GP2_8_RESERVED0_SHIFT 15 6332 6333 /* QSFI_GP2 :: GP2_8 :: an_speed_ln1 [14:08] */ 6334 #define QSFI_GP2_GP2_8_AN_SPEED_LN1_MASK 0x7f00 6335 #define QSFI_GP2_GP2_8_AN_SPEED_LN1_ALIGN 0 6336 #define QSFI_GP2_GP2_8_AN_SPEED_LN1_BITS 7 6337 #define QSFI_GP2_GP2_8_AN_SPEED_LN1_SHIFT 8 6338 6339 /* QSFI_GP2 :: GP2_8 :: reserved1 [07:07] */ 6340 #define QSFI_GP2_GP2_8_RESERVED1_MASK 0x0080 6341 #define QSFI_GP2_GP2_8_RESERVED1_ALIGN 0 6342 #define QSFI_GP2_GP2_8_RESERVED1_BITS 1 6343 #define QSFI_GP2_GP2_8_RESERVED1_SHIFT 7 6344 6345 /* QSFI_GP2 :: GP2_8 :: an_speed_ln0 [06:00] */ 6346 #define QSFI_GP2_GP2_8_AN_SPEED_LN0_MASK 0x007f 6347 #define QSFI_GP2_GP2_8_AN_SPEED_LN0_ALIGN 0 6348 #define QSFI_GP2_GP2_8_AN_SPEED_LN0_BITS 7 6349 #define QSFI_GP2_GP2_8_AN_SPEED_LN0_SHIFT 0 6350 6351 6352 /**************************************************************************** 6353 * QSFI_GP2 :: GP2_9 6354 */ 6355 /* QSFI_GP2 :: GP2_9 :: reserved0 [15:15] */ 6356 #define QSFI_GP2_GP2_9_RESERVED0_MASK 0x8000 6357 #define QSFI_GP2_GP2_9_RESERVED0_ALIGN 0 6358 #define QSFI_GP2_GP2_9_RESERVED0_BITS 1 6359 #define QSFI_GP2_GP2_9_RESERVED0_SHIFT 15 6360 6361 /* QSFI_GP2 :: GP2_9 :: an_speed_ln3 [14:08] */ 6362 #define QSFI_GP2_GP2_9_AN_SPEED_LN3_MASK 0x7f00 6363 #define QSFI_GP2_GP2_9_AN_SPEED_LN3_ALIGN 0 6364 #define QSFI_GP2_GP2_9_AN_SPEED_LN3_BITS 7 6365 #define QSFI_GP2_GP2_9_AN_SPEED_LN3_SHIFT 8 6366 6367 /* QSFI_GP2 :: GP2_9 :: reserved1 [07:07] */ 6368 #define QSFI_GP2_GP2_9_RESERVED1_MASK 0x0080 6369 #define QSFI_GP2_GP2_9_RESERVED1_ALIGN 0 6370 #define QSFI_GP2_GP2_9_RESERVED1_BITS 1 6371 #define QSFI_GP2_GP2_9_RESERVED1_SHIFT 7 6372 6373 /* QSFI_GP2 :: GP2_9 :: an_speed_ln2 [06:00] */ 6374 #define QSFI_GP2_GP2_9_AN_SPEED_LN2_MASK 0x007f 6375 #define QSFI_GP2_GP2_9_AN_SPEED_LN2_ALIGN 0 6376 #define QSFI_GP2_GP2_9_AN_SPEED_LN2_BITS 7 6377 #define QSFI_GP2_GP2_9_AN_SPEED_LN2_SHIFT 0 6378 6379 6380 /**************************************************************************** 6381 * merlin_gallardo_qsfi_blk_QSFI_FC_RX 6382 */ 6383 /**************************************************************************** 6384 * QSFI_FC_RX :: ln_fc_rx_control_reg 6385 */ 6386 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: reserved0 [15:10] */ 6387 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_RESERVED0_MASK 0xfc00 6388 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_RESERVED0_ALIGN 0 6389 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_RESERVED0_BITS 6 6390 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_RESERVED0_SHIFT 10 6391 6392 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: fc_cdr_rxseqstart [09:09] */ 6393 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_CDR_RXSEQSTART_MASK 0x0200 6394 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_CDR_RXSEQSTART_ALIGN 0 6395 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_CDR_RXSEQSTART_BITS 1 6396 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_CDR_RXSEQSTART_SHIFT 9 6397 6398 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: fc_rx_lsb_first [08:08] */ 6399 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_RX_LSB_FIRST_MASK 0x0100 6400 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_RX_LSB_FIRST_ALIGN 0 6401 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_RX_LSB_FIRST_BITS 1 6402 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_RX_LSB_FIRST_SHIFT 8 6403 6404 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: comma_detect_window [07:05] */ 6405 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_COMMA_DETECT_WINDOW_MASK 0x00e0 6406 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_COMMA_DETECT_WINDOW_ALIGN 0 6407 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_COMMA_DETECT_WINDOW_BITS 3 6408 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_COMMA_DETECT_WINDOW_SHIFT 5 6409 6410 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: wsync_rst [04:04] */ 6411 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_WSYNC_RST_MASK 0x0010 6412 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_WSYNC_RST_ALIGN 0 6413 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_WSYNC_RST_BITS 1 6414 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_WSYNC_RST_SHIFT 4 6415 6416 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: wsync_mode [03:03] */ 6417 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_WSYNC_MODE_MASK 0x0008 6418 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_WSYNC_MODE_ALIGN 0 6419 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_WSYNC_MODE_BITS 1 6420 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_WSYNC_MODE_SHIFT 3 6421 6422 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: reserved1 [02:02] */ 6423 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_RESERVED1_MASK 0x0004 6424 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_RESERVED1_ALIGN 0 6425 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_RESERVED1_BITS 1 6426 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_RESERVED1_SHIFT 2 6427 6428 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: fc_sw_rst [01:01] */ 6429 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_SW_RST_MASK 0x0002 6430 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_SW_RST_ALIGN 0 6431 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_SW_RST_BITS 1 6432 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_SW_RST_SHIFT 1 6433 6434 /* QSFI_FC_RX :: ln_fc_rx_control_reg :: fc_pwr_dwn [00:00] */ 6435 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_PWR_DWN_MASK 0x0001 6436 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_PWR_DWN_ALIGN 0 6437 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_PWR_DWN_BITS 1 6438 #define QSFI_FC_RX_LN_FC_RX_CONTROL_REG_FC_PWR_DWN_SHIFT 0 6439 6440 6441 /**************************************************************************** 6442 * QSFI_FC_RX :: ln_fc_rx_status_reg 6443 */ 6444 /* QSFI_FC_RX :: ln_fc_rx_status_reg :: reserved0 [15:14] */ 6445 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED0_MASK 0xc000 6446 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED0_ALIGN 0 6447 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED0_BITS 2 6448 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED0_SHIFT 14 6449 6450 /* QSFI_FC_RX :: ln_fc_rx_status_reg :: fc_los [13:13] */ 6451 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_LOS_MASK 0x2000 6452 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_LOS_ALIGN 0 6453 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_LOS_BITS 1 6454 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_LOS_SHIFT 13 6455 6456 /* QSFI_FC_RX :: ln_fc_rx_status_reg :: fc_cdr_lock [12:12] */ 6457 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_CDR_LOCK_MASK 0x1000 6458 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_CDR_LOCK_ALIGN 0 6459 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_CDR_LOCK_BITS 1 6460 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_CDR_LOCK_SHIFT 12 6461 6462 /* QSFI_FC_RX :: ln_fc_rx_status_reg :: tx_fault [11:11] */ 6463 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_TX_FAULT_MASK 0x0800 6464 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_TX_FAULT_ALIGN 0 6465 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_TX_FAULT_BITS 1 6466 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_TX_FAULT_SHIFT 11 6467 6468 /* QSFI_FC_RX :: ln_fc_rx_status_reg :: reserved1 [10:03] */ 6469 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED1_MASK 0x07f8 6470 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED1_ALIGN 0 6471 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED1_BITS 8 6472 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED1_SHIFT 3 6473 6474 /* QSFI_FC_RX :: ln_fc_rx_status_reg :: fc_speed_acq [02:02] */ 6475 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_SPEED_ACQ_MASK 0x0004 6476 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_SPEED_ACQ_ALIGN 0 6477 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_SPEED_ACQ_BITS 1 6478 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_SPEED_ACQ_SHIFT 2 6479 6480 /* QSFI_FC_RX :: ln_fc_rx_status_reg :: reserved2 [01:01] */ 6481 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED2_MASK 0x0002 6482 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED2_ALIGN 0 6483 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED2_BITS 1 6484 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_RESERVED2_SHIFT 1 6485 6486 /* QSFI_FC_RX :: ln_fc_rx_status_reg :: fc_word_sync_acq [00:00] */ 6487 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_WORD_SYNC_ACQ_MASK 0x0001 6488 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_WORD_SYNC_ACQ_ALIGN 0 6489 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_WORD_SYNC_ACQ_BITS 1 6490 #define QSFI_FC_RX_LN_FC_RX_STATUS_REG_FC_WORD_SYNC_ACQ_SHIFT 0 6491 6492 6493 /**************************************************************************** 6494 * QSFI_FC_RX :: ln_fc_rx_interrupts_reg 6495 */ 6496 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: reserved0 [15:11] */ 6497 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_RESERVED0_MASK 0xf800 6498 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_RESERVED0_ALIGN 0 6499 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_RESERVED0_BITS 5 6500 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_RESERVED0_SHIFT 11 6501 6502 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: tx_fault_int [10:10] */ 6503 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_TX_FAULT_INT_MASK 0x0400 6504 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_TX_FAULT_INT_ALIGN 0 6505 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_TX_FAULT_INT_BITS 1 6506 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_TX_FAULT_INT_SHIFT 10 6507 6508 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_8g_sync_test_failed_int [09:09] */ 6509 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8G_SYNC_TEST_FAILED_INT_MASK 0x0200 6510 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8G_SYNC_TEST_FAILED_INT_ALIGN 0 6511 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8G_SYNC_TEST_FAILED_INT_BITS 1 6512 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8G_SYNC_TEST_FAILED_INT_SHIFT 9 6513 6514 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_4g_sync_test_failed_int [08:08] */ 6515 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_4G_SYNC_TEST_FAILED_INT_MASK 0x0100 6516 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_4G_SYNC_TEST_FAILED_INT_ALIGN 0 6517 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_4G_SYNC_TEST_FAILED_INT_BITS 1 6518 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_4G_SYNC_TEST_FAILED_INT_SHIFT 8 6519 6520 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_2g_sync_test_failed_int [07:07] */ 6521 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_2G_SYNC_TEST_FAILED_INT_MASK 0x0080 6522 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_2G_SYNC_TEST_FAILED_INT_ALIGN 0 6523 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_2G_SYNC_TEST_FAILED_INT_BITS 1 6524 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_2G_SYNC_TEST_FAILED_INT_SHIFT 7 6525 6526 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_comma_detect_int [06:06] */ 6527 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_COMMA_DETECT_INT_MASK 0x0040 6528 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_COMMA_DETECT_INT_ALIGN 0 6529 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_COMMA_DETECT_INT_BITS 1 6530 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_COMMA_DETECT_INT_SHIFT 6 6531 6532 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_40b_code_error_int [05:05] */ 6533 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_40B_CODE_ERROR_INT_MASK 0x0020 6534 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_40B_CODE_ERROR_INT_ALIGN 0 6535 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_40B_CODE_ERROR_INT_BITS 1 6536 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_40B_CODE_ERROR_INT_SHIFT 5 6537 6538 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_8b10b_disparity_error_int [04:04] */ 6539 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8B10B_DISPARITY_ERROR_INT_MASK 0x0010 6540 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8B10B_DISPARITY_ERROR_INT_ALIGN 0 6541 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8B10B_DISPARITY_ERROR_INT_BITS 1 6542 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8B10B_DISPARITY_ERROR_INT_SHIFT 4 6543 6544 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_8b10b_code_error_int [03:03] */ 6545 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8B10B_CODE_ERROR_INT_MASK 0x0008 6546 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8B10B_CODE_ERROR_INT_ALIGN 0 6547 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8B10B_CODE_ERROR_INT_BITS 1 6548 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_8B10B_CODE_ERROR_INT_SHIFT 3 6549 6550 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_speed_acq_int [02:02] */ 6551 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_SPEED_ACQ_INT_MASK 0x0004 6552 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_SPEED_ACQ_INT_ALIGN 0 6553 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_SPEED_ACQ_INT_BITS 1 6554 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_SPEED_ACQ_INT_SHIFT 2 6555 6556 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_link_fail_int [01:01] */ 6557 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_LINK_FAIL_INT_MASK 0x0002 6558 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_LINK_FAIL_INT_ALIGN 0 6559 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_LINK_FAIL_INT_BITS 1 6560 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_LINK_FAIL_INT_SHIFT 1 6561 6562 /* QSFI_FC_RX :: ln_fc_rx_interrupts_reg :: fc_word_sync_acq_int [00:00] */ 6563 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_WORD_SYNC_ACQ_INT_MASK 0x0001 6564 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_WORD_SYNC_ACQ_INT_ALIGN 0 6565 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_WORD_SYNC_ACQ_INT_BITS 1 6566 #define QSFI_FC_RX_LN_FC_RX_INTERRUPTS_REG_FC_WORD_SYNC_ACQ_INT_SHIFT 0 6567 6568 6569 /**************************************************************************** 6570 * QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg 6571 */ 6572 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: reserved0 [15:11] */ 6573 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_RESERVED0_MASK 0xf800 6574 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_RESERVED0_ALIGN 0 6575 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_RESERVED0_BITS 5 6576 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_RESERVED0_SHIFT 11 6577 6578 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: tx_fault_enable [10:10] */ 6579 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_TX_FAULT_ENABLE_MASK 0x0400 6580 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_TX_FAULT_ENABLE_ALIGN 0 6581 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_TX_FAULT_ENABLE_BITS 1 6582 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_TX_FAULT_ENABLE_SHIFT 10 6583 6584 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_8g_sync_test_failed_enable [09:09] */ 6585 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8G_SYNC_TEST_FAILED_ENABLE_MASK 0x0200 6586 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8G_SYNC_TEST_FAILED_ENABLE_ALIGN 0 6587 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8G_SYNC_TEST_FAILED_ENABLE_BITS 1 6588 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8G_SYNC_TEST_FAILED_ENABLE_SHIFT 9 6589 6590 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_4g_sync_test_failed_enable [08:08] */ 6591 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_4G_SYNC_TEST_FAILED_ENABLE_MASK 0x0100 6592 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_4G_SYNC_TEST_FAILED_ENABLE_ALIGN 0 6593 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_4G_SYNC_TEST_FAILED_ENABLE_BITS 1 6594 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_4G_SYNC_TEST_FAILED_ENABLE_SHIFT 8 6595 6596 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_2g_sync_test_failed_enable [07:07] */ 6597 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_2G_SYNC_TEST_FAILED_ENABLE_MASK 0x0080 6598 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_2G_SYNC_TEST_FAILED_ENABLE_ALIGN 0 6599 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_2G_SYNC_TEST_FAILED_ENABLE_BITS 1 6600 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_2G_SYNC_TEST_FAILED_ENABLE_SHIFT 7 6601 6602 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_comma_detect_enable [06:06] */ 6603 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_COMMA_DETECT_ENABLE_MASK 0x0040 6604 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_COMMA_DETECT_ENABLE_ALIGN 0 6605 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_COMMA_DETECT_ENABLE_BITS 1 6606 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_COMMA_DETECT_ENABLE_SHIFT 6 6607 6608 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_40b_code_error_enable [05:05] */ 6609 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_40B_CODE_ERROR_ENABLE_MASK 0x0020 6610 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_40B_CODE_ERROR_ENABLE_ALIGN 0 6611 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_40B_CODE_ERROR_ENABLE_BITS 1 6612 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_40B_CODE_ERROR_ENABLE_SHIFT 5 6613 6614 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_8b10b_disparity_error_enable [04:04] */ 6615 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8B10B_DISPARITY_ERROR_ENABLE_MASK 0x0010 6616 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8B10B_DISPARITY_ERROR_ENABLE_ALIGN 0 6617 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8B10B_DISPARITY_ERROR_ENABLE_BITS 1 6618 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8B10B_DISPARITY_ERROR_ENABLE_SHIFT 4 6619 6620 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_8b10b_code_error_enable [03:03] */ 6621 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8B10B_CODE_ERROR_ENABLE_MASK 0x0008 6622 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8B10B_CODE_ERROR_ENABLE_ALIGN 0 6623 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8B10B_CODE_ERROR_ENABLE_BITS 1 6624 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_8B10B_CODE_ERROR_ENABLE_SHIFT 3 6625 6626 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_speed_acq_enable [02:02] */ 6627 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_SPEED_ACQ_ENABLE_MASK 0x0004 6628 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_SPEED_ACQ_ENABLE_ALIGN 0 6629 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_SPEED_ACQ_ENABLE_BITS 1 6630 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_SPEED_ACQ_ENABLE_SHIFT 2 6631 6632 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_link_fail_enable [01:01] */ 6633 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_LINK_FAIL_ENABLE_MASK 0x0002 6634 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_LINK_FAIL_ENABLE_ALIGN 0 6635 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_LINK_FAIL_ENABLE_BITS 1 6636 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_LINK_FAIL_ENABLE_SHIFT 1 6637 6638 /* QSFI_FC_RX :: ln_fc_rx_interrupt_enables_reg :: fc_word_sync_acq_enable [00:00] */ 6639 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_WORD_SYNC_ACQ_ENABLE_MASK 0x0001 6640 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_WORD_SYNC_ACQ_ENABLE_ALIGN 0 6641 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_WORD_SYNC_ACQ_ENABLE_BITS 1 6642 #define QSFI_FC_RX_LN_FC_RX_INTERRUPT_ENABLES_REG_FC_WORD_SYNC_ACQ_ENABLE_SHIFT 0 6643 6644 6645 /**************************************************************************** 6646 * QSFI_FC_RX :: ln_fc_rx_auto_speed_config 6647 */ 6648 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_config :: reserved0 [15:11] */ 6649 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_RESERVED0_MASK 0xf800 6650 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_RESERVED0_ALIGN 0 6651 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_RESERVED0_BITS 5 6652 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_RESERVED0_SHIFT 11 6653 6654 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_config :: fc_auto_speed_self_restart [10:10] */ 6655 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_SELF_RESTART_MASK 0x0400 6656 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_SELF_RESTART_ALIGN 0 6657 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_SELF_RESTART_BITS 1 6658 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_SELF_RESTART_SHIFT 10 6659 6660 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_config :: fc_auto_speed_delay [09:08] */ 6661 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_DELAY_MASK 0x0300 6662 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_DELAY_ALIGN 0 6663 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_DELAY_BITS 2 6664 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_DELAY_SHIFT 8 6665 6666 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_config :: fc_auto_speed_sync_test_start [07:07] */ 6667 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_SYNC_TEST_START_MASK 0x0080 6668 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_SYNC_TEST_START_ALIGN 0 6669 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_SYNC_TEST_START_BITS 1 6670 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_SYNC_TEST_START_SHIFT 7 6671 6672 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_config :: fc_auto_speed_reset [06:06] */ 6673 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_RESET_MASK 0x0040 6674 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_RESET_ALIGN 0 6675 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_RESET_BITS 1 6676 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_AUTO_SPEED_RESET_SHIFT 6 6677 6678 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_config :: fc_cdr_forced_speed_enc_rx [05:05] */ 6679 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_CDR_FORCED_SPEED_ENC_RX_MASK 0x0020 6680 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_CDR_FORCED_SPEED_ENC_RX_ALIGN 0 6681 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_CDR_FORCED_SPEED_ENC_RX_BITS 1 6682 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_CDR_FORCED_SPEED_ENC_RX_SHIFT 5 6683 6684 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_config :: reserved1 [04:03] */ 6685 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_RESERVED1_MASK 0x0018 6686 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_RESERVED1_ALIGN 0 6687 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_RESERVED1_BITS 2 6688 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_RESERVED1_SHIFT 3 6689 6690 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_config :: fc_oper_rate [02:00] */ 6691 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_OPER_RATE_MASK 0x0007 6692 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_OPER_RATE_ALIGN 0 6693 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_OPER_RATE_BITS 3 6694 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_CONFIG_FC_OPER_RATE_SHIFT 0 6695 6696 6697 /**************************************************************************** 6698 * QSFI_FC_RX :: ln_fc_rx_auto_speed_status 6699 */ 6700 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_status :: reserved0 [15:09] */ 6701 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_RESERVED0_MASK 0xfe00 6702 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_RESERVED0_ALIGN 0 6703 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_RESERVED0_BITS 7 6704 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_RESERVED0_SHIFT 9 6705 6706 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_status :: fc_auto_speed_sync_test_fail [08:08] */ 6707 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_AUTO_SPEED_SYNC_TEST_FAIL_MASK 0x0100 6708 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_AUTO_SPEED_SYNC_TEST_FAIL_ALIGN 0 6709 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_AUTO_SPEED_SYNC_TEST_FAIL_BITS 1 6710 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_AUTO_SPEED_SYNC_TEST_FAIL_SHIFT 8 6711 6712 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_status :: fc_auto_speed_sync_test_end [07:07] */ 6713 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_AUTO_SPEED_SYNC_TEST_END_MASK 0x0080 6714 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_AUTO_SPEED_SYNC_TEST_END_ALIGN 0 6715 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_AUTO_SPEED_SYNC_TEST_END_BITS 1 6716 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_AUTO_SPEED_SYNC_TEST_END_SHIFT 7 6717 6718 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_status :: reserved1 [06:03] */ 6719 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_RESERVED1_MASK 0x0078 6720 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_RESERVED1_ALIGN 0 6721 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_RESERVED1_BITS 4 6722 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_RESERVED1_SHIFT 3 6723 6724 /* QSFI_FC_RX :: ln_fc_rx_auto_speed_status :: fc_rx_link_speed [02:00] */ 6725 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_RX_LINK_SPEED_MASK 0x0007 6726 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_RX_LINK_SPEED_ALIGN 0 6727 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_RX_LINK_SPEED_BITS 3 6728 #define QSFI_FC_RX_LN_FC_RX_AUTO_SPEED_STATUS_FC_RX_LINK_SPEED_SHIFT 0 6729 6730 6731 /**************************************************************************** 6732 * QSFI_FC_RX :: ln_fc_rx_r_t_tov 6733 */ 6734 /* QSFI_FC_RX :: ln_fc_rx_r_t_tov :: r_t_tov [15:00] */ 6735 #define QSFI_FC_RX_LN_FC_RX_R_T_TOV_R_T_TOV_MASK 0xffff 6736 #define QSFI_FC_RX_LN_FC_RX_R_T_TOV_R_T_TOV_ALIGN 0 6737 #define QSFI_FC_RX_LN_FC_RX_R_T_TOV_R_T_TOV_BITS 16 6738 #define QSFI_FC_RX_LN_FC_RX_R_T_TOV_R_T_TOV_SHIFT 0 6739 6740 6741 /**************************************************************************** 6742 * QSFI_FC_RX :: ln_fc_rx_tpat_mon_config 6743 */ 6744 /* QSFI_FC_RX :: ln_fc_rx_tpat_mon_config :: reserved0 [15:07] */ 6745 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_RESERVED0_MASK 0xff80 6746 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_RESERVED0_ALIGN 0 6747 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_RESERVED0_BITS 9 6748 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_RESERVED0_SHIFT 7 6749 6750 /* QSFI_FC_RX :: ln_fc_rx_tpat_mon_config :: fc_tpat_idle [06:03] */ 6751 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_IDLE_MASK 0x0078 6752 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_IDLE_ALIGN 0 6753 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_IDLE_BITS 4 6754 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_IDLE_SHIFT 3 6755 6756 /* QSFI_FC_RX :: ln_fc_rx_tpat_mon_config :: fc_tpat_mode [02:01] */ 6757 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_MODE_MASK 0x0006 6758 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_MODE_ALIGN 0 6759 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_MODE_BITS 2 6760 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_MODE_SHIFT 1 6761 6762 /* QSFI_FC_RX :: ln_fc_rx_tpat_mon_config :: fc_tpat_mon_enable [00:00] */ 6763 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_MON_ENABLE_MASK 0x0001 6764 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_MON_ENABLE_ALIGN 0 6765 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_MON_ENABLE_BITS 1 6766 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_CONFIG_FC_TPAT_MON_ENABLE_SHIFT 0 6767 6768 6769 /**************************************************************************** 6770 * QSFI_FC_RX :: ln_fc_rx_tpat_mon_status 6771 */ 6772 /* QSFI_FC_RX :: ln_fc_rx_tpat_mon_status :: reserved0 [15:01] */ 6773 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_STATUS_RESERVED0_MASK 0xfffe 6774 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_STATUS_RESERVED0_ALIGN 0 6775 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_STATUS_RESERVED0_BITS 15 6776 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_STATUS_RESERVED0_SHIFT 1 6777 6778 /* QSFI_FC_RX :: ln_fc_rx_tpat_mon_status :: fc_tpat_mon_lock [00:00] */ 6779 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_STATUS_FC_TPAT_MON_LOCK_MASK 0x0001 6780 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_STATUS_FC_TPAT_MON_LOCK_ALIGN 0 6781 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_STATUS_FC_TPAT_MON_LOCK_BITS 1 6782 #define QSFI_FC_RX_LN_FC_RX_TPAT_MON_STATUS_FC_TPAT_MON_LOCK_SHIFT 0 6783 6784 6785 /**************************************************************************** 6786 * QSFI_FC_RX :: ln_fc_rx_received_tpat_cnt 6787 */ 6788 /* QSFI_FC_RX :: ln_fc_rx_received_tpat_cnt :: fc_received_tpat_cnt [15:00] */ 6789 #define QSFI_FC_RX_LN_FC_RX_RECEIVED_TPAT_CNT_FC_RECEIVED_TPAT_CNT_MASK 0xffff 6790 #define QSFI_FC_RX_LN_FC_RX_RECEIVED_TPAT_CNT_FC_RECEIVED_TPAT_CNT_ALIGN 0 6791 #define QSFI_FC_RX_LN_FC_RX_RECEIVED_TPAT_CNT_FC_RECEIVED_TPAT_CNT_BITS 16 6792 #define QSFI_FC_RX_LN_FC_RX_RECEIVED_TPAT_CNT_FC_RECEIVED_TPAT_CNT_SHIFT 0 6793 6794 6795 /**************************************************************************** 6796 * QSFI_FC_RX :: ln_fc_rx_tpat_error_cnt 6797 */ 6798 /* QSFI_FC_RX :: ln_fc_rx_tpat_error_cnt :: fc_tpat_error_cnt [15:00] */ 6799 #define QSFI_FC_RX_LN_FC_RX_TPAT_ERROR_CNT_FC_TPAT_ERROR_CNT_MASK 0xffff 6800 #define QSFI_FC_RX_LN_FC_RX_TPAT_ERROR_CNT_FC_TPAT_ERROR_CNT_ALIGN 0 6801 #define QSFI_FC_RX_LN_FC_RX_TPAT_ERROR_CNT_FC_TPAT_ERROR_CNT_BITS 16 6802 #define QSFI_FC_RX_LN_FC_RX_TPAT_ERROR_CNT_FC_TPAT_ERROR_CNT_SHIFT 0 6803 6804 6805 /**************************************************************************** 6806 * merlin_gallardo_qsfi_blk_QSFI_BASER 6807 */ 6808 /**************************************************************************** 6809 * QSFI_BASER :: control_0 6810 */ 6811 /* QSFI_BASER :: control_0 :: reserved0 [15:14] */ 6812 #define QSFI_BASER_CONTROL_0_RESERVED0_MASK 0xc000 6813 #define QSFI_BASER_CONTROL_0_RESERVED0_ALIGN 0 6814 #define QSFI_BASER_CONTROL_0_RESERVED0_BITS 2 6815 #define QSFI_BASER_CONTROL_0_RESERVED0_SHIFT 14 6816 6817 /* QSFI_BASER :: control_0 :: fast_lock_cya [13:13] */ 6818 #define QSFI_BASER_CONTROL_0_FAST_LOCK_CYA_MASK 0x2000 6819 #define QSFI_BASER_CONTROL_0_FAST_LOCK_CYA_ALIGN 0 6820 #define QSFI_BASER_CONTROL_0_FAST_LOCK_CYA_BITS 1 6821 #define QSFI_BASER_CONTROL_0_FAST_LOCK_CYA_SHIFT 13 6822 6823 /* QSFI_BASER :: control_0 :: use_cl49_lsm_for_cl82_cya [12:12] */ 6824 #define QSFI_BASER_CONTROL_0_USE_CL49_LSM_FOR_CL82_CYA_MASK 0x1000 6825 #define QSFI_BASER_CONTROL_0_USE_CL49_LSM_FOR_CL82_CYA_ALIGN 0 6826 #define QSFI_BASER_CONTROL_0_USE_CL49_LSM_FOR_CL82_CYA_BITS 1 6827 #define QSFI_BASER_CONTROL_0_USE_CL49_LSM_FOR_CL82_CYA_SHIFT 12 6828 6829 /* QSFI_BASER :: control_0 :: sh_cnt_cl82_ext [11:00] */ 6830 #define QSFI_BASER_CONTROL_0_SH_CNT_CL82_EXT_MASK 0x0fff 6831 #define QSFI_BASER_CONTROL_0_SH_CNT_CL82_EXT_ALIGN 0 6832 #define QSFI_BASER_CONTROL_0_SH_CNT_CL82_EXT_BITS 12 6833 #define QSFI_BASER_CONTROL_0_SH_CNT_CL82_EXT_SHIFT 0 6834 6835 6836 /**************************************************************************** 6837 * QSFI_BASER :: control_1 6838 */ 6839 /* QSFI_BASER :: control_1 :: rst_gbox [15:15] */ 6840 #define QSFI_BASER_CONTROL_1_RST_GBOX_MASK 0x8000 6841 #define QSFI_BASER_CONTROL_1_RST_GBOX_ALIGN 0 6842 #define QSFI_BASER_CONTROL_1_RST_GBOX_BITS 1 6843 #define QSFI_BASER_CONTROL_1_RST_GBOX_SHIFT 15 6844 6845 /* QSFI_BASER :: control_1 :: rx_baseR_pcs_detect_en [14:14] */ 6846 #define QSFI_BASER_CONTROL_1_RX_BASER_PCS_DETECT_EN_MASK 0x4000 6847 #define QSFI_BASER_CONTROL_1_RX_BASER_PCS_DETECT_EN_ALIGN 0 6848 #define QSFI_BASER_CONTROL_1_RX_BASER_PCS_DETECT_EN_BITS 1 6849 #define QSFI_BASER_CONTROL_1_RX_BASER_PCS_DETECT_EN_SHIFT 14 6850 6851 /* QSFI_BASER :: control_1 :: reserved0 [13:10] */ 6852 #define QSFI_BASER_CONTROL_1_RESERVED0_MASK 0x3c00 6853 #define QSFI_BASER_CONTROL_1_RESERVED0_ALIGN 0 6854 #define QSFI_BASER_CONTROL_1_RESERVED0_BITS 4 6855 #define QSFI_BASER_CONTROL_1_RESERVED0_SHIFT 10 6856 6857 /* QSFI_BASER :: control_1 :: force_en_64bit_output_override [09:09] */ 6858 #define QSFI_BASER_CONTROL_1_FORCE_EN_64BIT_OUTPUT_OVERRIDE_MASK 0x0200 6859 #define QSFI_BASER_CONTROL_1_FORCE_EN_64BIT_OUTPUT_OVERRIDE_ALIGN 0 6860 #define QSFI_BASER_CONTROL_1_FORCE_EN_64BIT_OUTPUT_OVERRIDE_BITS 1 6861 #define QSFI_BASER_CONTROL_1_FORCE_EN_64BIT_OUTPUT_OVERRIDE_SHIFT 9 6862 6863 /* QSFI_BASER :: control_1 :: force_en_64bit_output_val [08:08] */ 6864 #define QSFI_BASER_CONTROL_1_FORCE_EN_64BIT_OUTPUT_VAL_MASK 0x0100 6865 #define QSFI_BASER_CONTROL_1_FORCE_EN_64BIT_OUTPUT_VAL_ALIGN 0 6866 #define QSFI_BASER_CONTROL_1_FORCE_EN_64BIT_OUTPUT_VAL_BITS 1 6867 #define QSFI_BASER_CONTROL_1_FORCE_EN_64BIT_OUTPUT_VAL_SHIFT 8 6868 6869 /* QSFI_BASER :: control_1 :: force_rxck_int66_en_override [07:07] */ 6870 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT66_EN_OVERRIDE_MASK 0x0080 6871 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT66_EN_OVERRIDE_ALIGN 0 6872 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT66_EN_OVERRIDE_BITS 1 6873 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT66_EN_OVERRIDE_SHIFT 7 6874 6875 /* QSFI_BASER :: control_1 :: force_rxck_int66_en_val [06:06] */ 6876 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT66_EN_VAL_MASK 0x0040 6877 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT66_EN_VAL_ALIGN 0 6878 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT66_EN_VAL_BITS 1 6879 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT66_EN_VAL_SHIFT 6 6880 6881 /* QSFI_BASER :: control_1 :: force_rxck_int64_en_override [05:05] */ 6882 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT64_EN_OVERRIDE_MASK 0x0020 6883 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT64_EN_OVERRIDE_ALIGN 0 6884 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT64_EN_OVERRIDE_BITS 1 6885 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT64_EN_OVERRIDE_SHIFT 5 6886 6887 /* QSFI_BASER :: control_1 :: force_rxck_int64_en_val [04:04] */ 6888 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT64_EN_VAL_MASK 0x0010 6889 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT64_EN_VAL_ALIGN 0 6890 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT64_EN_VAL_BITS 1 6891 #define QSFI_BASER_CONTROL_1_FORCE_RXCK_INT64_EN_VAL_SHIFT 4 6892 6893 /* QSFI_BASER :: control_1 :: force_rstb_rxck_int64_override [03:03] */ 6894 #define QSFI_BASER_CONTROL_1_FORCE_RSTB_RXCK_INT64_OVERRIDE_MASK 0x0008 6895 #define QSFI_BASER_CONTROL_1_FORCE_RSTB_RXCK_INT64_OVERRIDE_ALIGN 0 6896 #define QSFI_BASER_CONTROL_1_FORCE_RSTB_RXCK_INT64_OVERRIDE_BITS 1 6897 #define QSFI_BASER_CONTROL_1_FORCE_RSTB_RXCK_INT64_OVERRIDE_SHIFT 3 6898 6899 /* QSFI_BASER :: control_1 :: force_rstb_rxck_int64_val [02:02] */ 6900 #define QSFI_BASER_CONTROL_1_FORCE_RSTB_RXCK_INT64_VAL_MASK 0x0004 6901 #define QSFI_BASER_CONTROL_1_FORCE_RSTB_RXCK_INT64_VAL_ALIGN 0 6902 #define QSFI_BASER_CONTROL_1_FORCE_RSTB_RXCK_INT64_VAL_BITS 1 6903 #define QSFI_BASER_CONTROL_1_FORCE_RSTB_RXCK_INT64_VAL_SHIFT 2 6904 6905 /* QSFI_BASER :: control_1 :: force_all_gbox_clks_override [01:01] */ 6906 #define QSFI_BASER_CONTROL_1_FORCE_ALL_GBOX_CLKS_OVERRIDE_MASK 0x0002 6907 #define QSFI_BASER_CONTROL_1_FORCE_ALL_GBOX_CLKS_OVERRIDE_ALIGN 0 6908 #define QSFI_BASER_CONTROL_1_FORCE_ALL_GBOX_CLKS_OVERRIDE_BITS 1 6909 #define QSFI_BASER_CONTROL_1_FORCE_ALL_GBOX_CLKS_OVERRIDE_SHIFT 1 6910 6911 /* QSFI_BASER :: control_1 :: force_all_gbox_clks_val [00:00] */ 6912 #define QSFI_BASER_CONTROL_1_FORCE_ALL_GBOX_CLKS_VAL_MASK 0x0001 6913 #define QSFI_BASER_CONTROL_1_FORCE_ALL_GBOX_CLKS_VAL_ALIGN 0 6914 #define QSFI_BASER_CONTROL_1_FORCE_ALL_GBOX_CLKS_VAL_BITS 1 6915 #define QSFI_BASER_CONTROL_1_FORCE_ALL_GBOX_CLKS_VAL_SHIFT 0 6916 6917 6918 /**************************************************************************** 6919 * QSFI_BASER :: control_2 6920 */ 6921 /* QSFI_BASER :: control_2 :: reserved0 [15:12] */ 6922 #define QSFI_BASER_CONTROL_2_RESERVED0_MASK 0xf000 6923 #define QSFI_BASER_CONTROL_2_RESERVED0_ALIGN 0 6924 #define QSFI_BASER_CONTROL_2_RESERVED0_BITS 4 6925 #define QSFI_BASER_CONTROL_2_RESERVED0_SHIFT 12 6926 6927 /* QSFI_BASER :: control_2 :: invalid_sh_cnt_cl82_ext [11:00] */ 6928 #define QSFI_BASER_CONTROL_2_INVALID_SH_CNT_CL82_EXT_MASK 0x0fff 6929 #define QSFI_BASER_CONTROL_2_INVALID_SH_CNT_CL82_EXT_ALIGN 0 6930 #define QSFI_BASER_CONTROL_2_INVALID_SH_CNT_CL82_EXT_BITS 12 6931 #define QSFI_BASER_CONTROL_2_INVALID_SH_CNT_CL82_EXT_SHIFT 0 6932 6933 6934 /**************************************************************************** 6935 * QSFI_BASER :: control_3 6936 */ 6937 /* QSFI_BASER :: control_3 :: valid_sh_cnt [15:08] */ 6938 #define QSFI_BASER_CONTROL_3_VALID_SH_CNT_MASK 0xff00 6939 #define QSFI_BASER_CONTROL_3_VALID_SH_CNT_ALIGN 0 6940 #define QSFI_BASER_CONTROL_3_VALID_SH_CNT_BITS 8 6941 #define QSFI_BASER_CONTROL_3_VALID_SH_CNT_SHIFT 8 6942 6943 /* QSFI_BASER :: control_3 :: invalid_sh_cnt [07:00] */ 6944 #define QSFI_BASER_CONTROL_3_INVALID_SH_CNT_MASK 0x00ff 6945 #define QSFI_BASER_CONTROL_3_INVALID_SH_CNT_ALIGN 0 6946 #define QSFI_BASER_CONTROL_3_INVALID_SH_CNT_BITS 8 6947 #define QSFI_BASER_CONTROL_3_INVALID_SH_CNT_SHIFT 0 6948 6949 6950 /**************************************************************************** 6951 * QSFI_BASER :: control_4 6952 */ 6953 /* QSFI_BASER :: control_4 :: timer125us [15:00] */ 6954 #define QSFI_BASER_CONTROL_4_TIMER125US_MASK 0xffff 6955 #define QSFI_BASER_CONTROL_4_TIMER125US_ALIGN 0 6956 #define QSFI_BASER_CONTROL_4_TIMER125US_BITS 16 6957 #define QSFI_BASER_CONTROL_4_TIMER125US_SHIFT 0 6958 6959 6960 /**************************************************************************** 6961 * QSFI_BASER :: control_5 6962 */ 6963 /* QSFI_BASER :: control_5 :: reserved0 [15:11] */ 6964 #define QSFI_BASER_CONTROL_5_RESERVED0_MASK 0xf800 6965 #define QSFI_BASER_CONTROL_5_RESERVED0_ALIGN 0 6966 #define QSFI_BASER_CONTROL_5_RESERVED0_BITS 5 6967 #define QSFI_BASER_CONTROL_5_RESERVED0_SHIFT 11 6968 6969 /* QSFI_BASER :: control_5 :: force_BER_mon_on_en_override [10:10] */ 6970 #define QSFI_BASER_CONTROL_5_FORCE_BER_MON_ON_EN_OVERRIDE_MASK 0x0400 6971 #define QSFI_BASER_CONTROL_5_FORCE_BER_MON_ON_EN_OVERRIDE_ALIGN 0 6972 #define QSFI_BASER_CONTROL_5_FORCE_BER_MON_ON_EN_OVERRIDE_BITS 1 6973 #define QSFI_BASER_CONTROL_5_FORCE_BER_MON_ON_EN_OVERRIDE_SHIFT 10 6974 6975 /* QSFI_BASER :: control_5 :: reserved1 [09:07] */ 6976 #define QSFI_BASER_CONTROL_5_RESERVED1_MASK 0x0380 6977 #define QSFI_BASER_CONTROL_5_RESERVED1_ALIGN 0 6978 #define QSFI_BASER_CONTROL_5_RESERVED1_BITS 3 6979 #define QSFI_BASER_CONTROL_5_RESERVED1_SHIFT 7 6980 6981 /* QSFI_BASER :: control_5 :: dis_cl49R2_bermon [06:06] */ 6982 #define QSFI_BASER_CONTROL_5_DIS_CL49R2_BERMON_MASK 0x0040 6983 #define QSFI_BASER_CONTROL_5_DIS_CL49R2_BERMON_ALIGN 0 6984 #define QSFI_BASER_CONTROL_5_DIS_CL49R2_BERMON_BITS 1 6985 #define QSFI_BASER_CONTROL_5_DIS_CL49R2_BERMON_SHIFT 6 6986 6987 /* QSFI_BASER :: control_5 :: bercnt [05:00] */ 6988 #define QSFI_BASER_CONTROL_5_BERCNT_MASK 0x003f 6989 #define QSFI_BASER_CONTROL_5_BERCNT_ALIGN 0 6990 #define QSFI_BASER_CONTROL_5_BERCNT_BITS 6 6991 #define QSFI_BASER_CONTROL_5_BERCNT_SHIFT 0 6992 6993 6994 /**************************************************************************** 6995 * QSFI_BASER :: status_0 6996 */ 6997 /* QSFI_BASER :: status_0 :: block_lock [15:15] */ 6998 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_MASK 0x8000 6999 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_ALIGN 0 7000 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_BITS 1 7001 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_SHIFT 15 7002 7003 /* QSFI_BASER :: status_0 :: block_lock_asserted_lh [14:14] */ 7004 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_ASSERTED_LH_MASK 0x4000 7005 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_ASSERTED_LH_ALIGN 0 7006 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_ASSERTED_LH_BITS 1 7007 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_ASSERTED_LH_SHIFT 14 7008 7009 /* QSFI_BASER :: status_0 :: block_lock_deasserted_lh [13:13] */ 7010 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_DEASSERTED_LH_MASK 0x2000 7011 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_DEASSERTED_LH_ALIGN 0 7012 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_DEASSERTED_LH_BITS 1 7013 #define QSFI_BASER_STATUS_0_BLOCK_LOCK_DEASSERTED_LH_SHIFT 13 7014 7015 /* QSFI_BASER :: status_0 :: llsm_state [12:04] */ 7016 #define QSFI_BASER_STATUS_0_LLSM_STATE_MASK 0x1ff0 7017 #define QSFI_BASER_STATUS_0_LLSM_STATE_ALIGN 0 7018 #define QSFI_BASER_STATUS_0_LLSM_STATE_BITS 9 7019 #define QSFI_BASER_STATUS_0_LLSM_STATE_SHIFT 4 7020 7021 /* QSFI_BASER :: status_0 :: lsm_state [03:00] */ 7022 #define QSFI_BASER_STATUS_0_LSM_STATE_MASK 0x000f 7023 #define QSFI_BASER_STATUS_0_LSM_STATE_ALIGN 0 7024 #define QSFI_BASER_STATUS_0_LSM_STATE_BITS 4 7025 #define QSFI_BASER_STATUS_0_LSM_STATE_SHIFT 0 7026 7027 7028 /**************************************************************************** 7029 * QSFI_BASER :: status_1 7030 */ 7031 /* QSFI_BASER :: status_1 :: block_lock [15:15] */ 7032 #define QSFI_BASER_STATUS_1_BLOCK_LOCK_MASK 0x8000 7033 #define QSFI_BASER_STATUS_1_BLOCK_LOCK_ALIGN 0 7034 #define QSFI_BASER_STATUS_1_BLOCK_LOCK_BITS 1 7035 #define QSFI_BASER_STATUS_1_BLOCK_LOCK_SHIFT 15 7036 7037 /* QSFI_BASER :: status_1 :: latch_hi_BER [14:14] */ 7038 #define QSFI_BASER_STATUS_1_LATCH_HI_BER_MASK 0x4000 7039 #define QSFI_BASER_STATUS_1_LATCH_HI_BER_ALIGN 0 7040 #define QSFI_BASER_STATUS_1_LATCH_HI_BER_BITS 1 7041 #define QSFI_BASER_STATUS_1_LATCH_HI_BER_SHIFT 14 7042 7043 /* QSFI_BASER :: status_1 :: BER [13:08] */ 7044 #define QSFI_BASER_STATUS_1_BER_MASK 0x3f00 7045 #define QSFI_BASER_STATUS_1_BER_ALIGN 0 7046 #define QSFI_BASER_STATUS_1_BER_BITS 6 7047 #define QSFI_BASER_STATUS_1_BER_SHIFT 8 7048 7049 /* QSFI_BASER :: status_1 :: reserved0 [07:00] */ 7050 #define QSFI_BASER_STATUS_1_RESERVED0_MASK 0x00ff 7051 #define QSFI_BASER_STATUS_1_RESERVED0_ALIGN 0 7052 #define QSFI_BASER_STATUS_1_RESERVED0_BITS 8 7053 #define QSFI_BASER_STATUS_1_RESERVED0_SHIFT 0 7054 7055 7056 /**************************************************************************** 7057 * QSFI_BASER :: status_2 7058 */ 7059 /* QSFI_BASER :: status_2 :: reserved0 [15:15] */ 7060 #define QSFI_BASER_STATUS_2_RESERVED0_MASK 0x8000 7061 #define QSFI_BASER_STATUS_2_RESERVED0_ALIGN 0 7062 #define QSFI_BASER_STATUS_2_RESERVED0_BITS 1 7063 #define QSFI_BASER_STATUS_2_RESERVED0_SHIFT 15 7064 7065 /* QSFI_BASER :: status_2 :: block_lock_status [14:14] */ 7066 #define QSFI_BASER_STATUS_2_BLOCK_LOCK_STATUS_MASK 0x4000 7067 #define QSFI_BASER_STATUS_2_BLOCK_LOCK_STATUS_ALIGN 0 7068 #define QSFI_BASER_STATUS_2_BLOCK_LOCK_STATUS_BITS 1 7069 #define QSFI_BASER_STATUS_2_BLOCK_LOCK_STATUS_SHIFT 14 7070 7071 /* QSFI_BASER :: status_2 :: hi_ber [13:13] */ 7072 #define QSFI_BASER_STATUS_2_HI_BER_MASK 0x2000 7073 #define QSFI_BASER_STATUS_2_HI_BER_ALIGN 0 7074 #define QSFI_BASER_STATUS_2_HI_BER_BITS 1 7075 #define QSFI_BASER_STATUS_2_HI_BER_SHIFT 13 7076 7077 /* QSFI_BASER :: status_2 :: t125us_done [12:12] */ 7078 #define QSFI_BASER_STATUS_2_T125US_DONE_MASK 0x1000 7079 #define QSFI_BASER_STATUS_2_T125US_DONE_ALIGN 0 7080 #define QSFI_BASER_STATUS_2_T125US_DONE_BITS 1 7081 #define QSFI_BASER_STATUS_2_T125US_DONE_SHIFT 12 7082 7083 /* QSFI_BASER :: status_2 :: lbermon_state [11:06] */ 7084 #define QSFI_BASER_STATUS_2_LBERMON_STATE_MASK 0x0fc0 7085 #define QSFI_BASER_STATUS_2_LBERMON_STATE_ALIGN 0 7086 #define QSFI_BASER_STATUS_2_LBERMON_STATE_BITS 6 7087 #define QSFI_BASER_STATUS_2_LBERMON_STATE_SHIFT 6 7088 7089 /* QSFI_BASER :: status_2 :: bermon_state [05:00] */ 7090 #define QSFI_BASER_STATUS_2_BERMON_STATE_MASK 0x003f 7091 #define QSFI_BASER_STATUS_2_BERMON_STATE_ALIGN 0 7092 #define QSFI_BASER_STATUS_2_BERMON_STATE_BITS 6 7093 #define QSFI_BASER_STATUS_2_BERMON_STATE_SHIFT 0 7094 7095 7096 /**************************************************************************** 7097 * merlin_gallardo_dsc_blk_DSC_A 7098 */ 7099 /**************************************************************************** 7100 * DSC_A :: cdr_control_0 7101 */ 7102 /* DSC_A :: cdr_control_0 :: reserved0 [15:12] */ 7103 #define DSC_A_CDR_CONTROL_0_RESERVED0_MASK 0xf000 7104 #define DSC_A_CDR_CONTROL_0_RESERVED0_ALIGN 0 7105 #define DSC_A_CDR_CONTROL_0_RESERVED0_BITS 4 7106 #define DSC_A_CDR_CONTROL_0_RESERVED0_SHIFT 12 7107 7108 /* DSC_A :: cdr_control_0 :: cdr_lm_thr_sel [11:08] */ 7109 #define DSC_A_CDR_CONTROL_0_CDR_LM_THR_SEL_MASK 0x0f00 7110 #define DSC_A_CDR_CONTROL_0_CDR_LM_THR_SEL_ALIGN 0 7111 #define DSC_A_CDR_CONTROL_0_CDR_LM_THR_SEL_BITS 4 7112 #define DSC_A_CDR_CONTROL_0_CDR_LM_THR_SEL_SHIFT 8 7113 7114 /* DSC_A :: cdr_control_0 :: cdr_freq_override_en [07:07] */ 7115 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_OVERRIDE_EN_MASK 0x0080 7116 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 7117 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_OVERRIDE_EN_BITS 1 7118 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_OVERRIDE_EN_SHIFT 7 7119 7120 /* DSC_A :: cdr_control_0 :: cdr_integ_sat_sel [06:06] */ 7121 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_SAT_SEL_MASK 0x0040 7122 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_SAT_SEL_ALIGN 0 7123 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_SAT_SEL_BITS 1 7124 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_SAT_SEL_SHIFT 6 7125 7126 /* DSC_A :: cdr_control_0 :: cdr_phase_err_frz [05:05] */ 7127 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_ERR_FRZ_MASK 0x0020 7128 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_ERR_FRZ_ALIGN 0 7129 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_ERR_FRZ_BITS 1 7130 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_ERR_FRZ_SHIFT 5 7131 7132 /* DSC_A :: cdr_control_0 :: cdr_integ_reg_clr [04:04] */ 7133 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_REG_CLR_MASK 0x0010 7134 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_REG_CLR_ALIGN 0 7135 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_REG_CLR_BITS 1 7136 #define DSC_A_CDR_CONTROL_0_CDR_INTEG_REG_CLR_SHIFT 4 7137 7138 /* DSC_A :: cdr_control_0 :: reserved1 [03:03] */ 7139 #define DSC_A_CDR_CONTROL_0_RESERVED1_MASK 0x0008 7140 #define DSC_A_CDR_CONTROL_0_RESERVED1_ALIGN 0 7141 #define DSC_A_CDR_CONTROL_0_RESERVED1_BITS 1 7142 #define DSC_A_CDR_CONTROL_0_RESERVED1_SHIFT 3 7143 7144 /* DSC_A :: cdr_control_0 :: cdr_freq_en [02:02] */ 7145 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_EN_MASK 0x0004 7146 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_EN_ALIGN 0 7147 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_EN_BITS 1 7148 #define DSC_A_CDR_CONTROL_0_CDR_FREQ_EN_SHIFT 2 7149 7150 /* DSC_A :: cdr_control_0 :: br_pd_en [01:01] */ 7151 #define DSC_A_CDR_CONTROL_0_BR_PD_EN_MASK 0x0002 7152 #define DSC_A_CDR_CONTROL_0_BR_PD_EN_ALIGN 0 7153 #define DSC_A_CDR_CONTROL_0_BR_PD_EN_BITS 1 7154 #define DSC_A_CDR_CONTROL_0_BR_PD_EN_SHIFT 1 7155 7156 /* DSC_A :: cdr_control_0 :: cdr_phase_sat_ctrl [00:00] */ 7157 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_SAT_CTRL_MASK 0x0001 7158 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_SAT_CTRL_ALIGN 0 7159 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_SAT_CTRL_BITS 1 7160 #define DSC_A_CDR_CONTROL_0_CDR_PHASE_SAT_CTRL_SHIFT 0 7161 7162 7163 /**************************************************************************** 7164 * DSC_A :: cdr_control_1 7165 */ 7166 /* DSC_A :: cdr_control_1 :: cdr_freq_override_val [15:00] */ 7167 #define DSC_A_CDR_CONTROL_1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 7168 #define DSC_A_CDR_CONTROL_1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 7169 #define DSC_A_CDR_CONTROL_1_CDR_FREQ_OVERRIDE_VAL_BITS 16 7170 #define DSC_A_CDR_CONTROL_1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 7171 7172 7173 /**************************************************************************** 7174 * DSC_A :: cdr_control_2 7175 */ 7176 /* DSC_A :: cdr_control_2 :: reserved0 [15:10] */ 7177 #define DSC_A_CDR_CONTROL_2_RESERVED0_MASK 0xfc00 7178 #define DSC_A_CDR_CONTROL_2_RESERVED0_ALIGN 0 7179 #define DSC_A_CDR_CONTROL_2_RESERVED0_BITS 6 7180 #define DSC_A_CDR_CONTROL_2_RESERVED0_SHIFT 10 7181 7182 /* DSC_A :: cdr_control_2 :: osx2p_pherr_gain [09:08] */ 7183 #define DSC_A_CDR_CONTROL_2_OSX2P_PHERR_GAIN_MASK 0x0300 7184 #define DSC_A_CDR_CONTROL_2_OSX2P_PHERR_GAIN_ALIGN 0 7185 #define DSC_A_CDR_CONTROL_2_OSX2P_PHERR_GAIN_BITS 2 7186 #define DSC_A_CDR_CONTROL_2_OSX2P_PHERR_GAIN_SHIFT 8 7187 7188 /* DSC_A :: cdr_control_2 :: pattern_sel [07:04] */ 7189 #define DSC_A_CDR_CONTROL_2_PATTERN_SEL_MASK 0x00f0 7190 #define DSC_A_CDR_CONTROL_2_PATTERN_SEL_ALIGN 0 7191 #define DSC_A_CDR_CONTROL_2_PATTERN_SEL_BITS 4 7192 #define DSC_A_CDR_CONTROL_2_PATTERN_SEL_SHIFT 4 7193 7194 /* DSC_A :: cdr_control_2 :: reserved1 [03:02] */ 7195 #define DSC_A_CDR_CONTROL_2_RESERVED1_MASK 0x000c 7196 #define DSC_A_CDR_CONTROL_2_RESERVED1_ALIGN 0 7197 #define DSC_A_CDR_CONTROL_2_RESERVED1_BITS 2 7198 #define DSC_A_CDR_CONTROL_2_RESERVED1_SHIFT 2 7199 7200 /* DSC_A :: cdr_control_2 :: cdr_peak_polarity [01:01] */ 7201 #define DSC_A_CDR_CONTROL_2_CDR_PEAK_POLARITY_MASK 0x0002 7202 #define DSC_A_CDR_CONTROL_2_CDR_PEAK_POLARITY_ALIGN 0 7203 #define DSC_A_CDR_CONTROL_2_CDR_PEAK_POLARITY_BITS 1 7204 #define DSC_A_CDR_CONTROL_2_CDR_PEAK_POLARITY_SHIFT 1 7205 7206 /* DSC_A :: cdr_control_2 :: cdr_zero_polarity [00:00] */ 7207 #define DSC_A_CDR_CONTROL_2_CDR_ZERO_POLARITY_MASK 0x0001 7208 #define DSC_A_CDR_CONTROL_2_CDR_ZERO_POLARITY_ALIGN 0 7209 #define DSC_A_CDR_CONTROL_2_CDR_ZERO_POLARITY_BITS 1 7210 #define DSC_A_CDR_CONTROL_2_CDR_ZERO_POLARITY_SHIFT 0 7211 7212 7213 /**************************************************************************** 7214 * DSC_A :: rx_pi_control 7215 */ 7216 /* DSC_A :: rx_pi_control :: pi_manual_reset [15:15] */ 7217 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_RESET_MASK 0x8000 7218 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_RESET_ALIGN 0 7219 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_RESET_BITS 1 7220 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_RESET_SHIFT 15 7221 7222 /* DSC_A :: rx_pi_control :: reserved0 [14:13] */ 7223 #define DSC_A_RX_PI_CONTROL_RESERVED0_MASK 0x6000 7224 #define DSC_A_RX_PI_CONTROL_RESERVED0_ALIGN 0 7225 #define DSC_A_RX_PI_CONTROL_RESERVED0_BITS 2 7226 #define DSC_A_RX_PI_CONTROL_RESERVED0_SHIFT 13 7227 7228 /* DSC_A :: rx_pi_control :: pi_manual_strobe [12:12] */ 7229 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_STROBE_MASK 0x1000 7230 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_STROBE_ALIGN 0 7231 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_STROBE_BITS 1 7232 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_STROBE_SHIFT 12 7233 7234 /* DSC_A :: rx_pi_control :: pi_manual_mode [11:11] */ 7235 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_MODE_MASK 0x0800 7236 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_MODE_ALIGN 0 7237 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_MODE_BITS 1 7238 #define DSC_A_RX_PI_CONTROL_PI_MANUAL_MODE_SHIFT 11 7239 7240 /* DSC_A :: rx_pi_control :: pi_phase_step_dir [10:10] */ 7241 #define DSC_A_RX_PI_CONTROL_PI_PHASE_STEP_DIR_MASK 0x0400 7242 #define DSC_A_RX_PI_CONTROL_PI_PHASE_STEP_DIR_ALIGN 0 7243 #define DSC_A_RX_PI_CONTROL_PI_PHASE_STEP_DIR_BITS 1 7244 #define DSC_A_RX_PI_CONTROL_PI_PHASE_STEP_DIR_SHIFT 10 7245 7246 /* DSC_A :: rx_pi_control :: pi_slicers_en [09:07] */ 7247 #define DSC_A_RX_PI_CONTROL_PI_SLICERS_EN_MASK 0x0380 7248 #define DSC_A_RX_PI_CONTROL_PI_SLICERS_EN_ALIGN 0 7249 #define DSC_A_RX_PI_CONTROL_PI_SLICERS_EN_BITS 3 7250 #define DSC_A_RX_PI_CONTROL_PI_SLICERS_EN_SHIFT 7 7251 7252 /* DSC_A :: rx_pi_control :: pi_phase_step_cnt [06:00] */ 7253 #define DSC_A_RX_PI_CONTROL_PI_PHASE_STEP_CNT_MASK 0x007f 7254 #define DSC_A_RX_PI_CONTROL_PI_PHASE_STEP_CNT_ALIGN 0 7255 #define DSC_A_RX_PI_CONTROL_PI_PHASE_STEP_CNT_BITS 7 7256 #define DSC_A_RX_PI_CONTROL_PI_PHASE_STEP_CNT_SHIFT 0 7257 7258 7259 /**************************************************************************** 7260 * DSC_A :: cdr_status_integ_reg 7261 */ 7262 /* DSC_A :: cdr_status_integ_reg :: cdr_integ_reg [15:00] */ 7263 #define DSC_A_CDR_STATUS_INTEG_REG_CDR_INTEG_REG_MASK 0xffff 7264 #define DSC_A_CDR_STATUS_INTEG_REG_CDR_INTEG_REG_ALIGN 0 7265 #define DSC_A_CDR_STATUS_INTEG_REG_CDR_INTEG_REG_BITS 16 7266 #define DSC_A_CDR_STATUS_INTEG_REG_CDR_INTEG_REG_SHIFT 0 7267 7268 7269 /**************************************************************************** 7270 * DSC_A :: cdr_status_phase_error 7271 */ 7272 /* DSC_A :: cdr_status_phase_error :: reserved0 [15:09] */ 7273 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED0_MASK 0xfe00 7274 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED0_ALIGN 0 7275 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED0_BITS 7 7276 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED0_SHIFT 9 7277 7278 /* DSC_A :: cdr_status_phase_error :: cdr_lm_outoflock [08:08] */ 7279 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_LM_OUTOFLOCK_MASK 0x0100 7280 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_LM_OUTOFLOCK_ALIGN 0 7281 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_LM_OUTOFLOCK_BITS 1 7282 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_LM_OUTOFLOCK_SHIFT 8 7283 7284 /* DSC_A :: cdr_status_phase_error :: reserved1 [07:05] */ 7285 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED1_MASK 0x00e0 7286 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED1_ALIGN 0 7287 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED1_BITS 3 7288 #define DSC_A_CDR_STATUS_PHASE_ERROR_RESERVED1_SHIFT 5 7289 7290 /* DSC_A :: cdr_status_phase_error :: cdr_phase_err [04:00] */ 7291 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_PHASE_ERR_MASK 0x001f 7292 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_PHASE_ERR_ALIGN 0 7293 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_PHASE_ERR_BITS 5 7294 #define DSC_A_CDR_STATUS_PHASE_ERROR_CDR_PHASE_ERR_SHIFT 0 7295 7296 7297 /**************************************************************************** 7298 * DSC_A :: rx_pi_cnt_bin_d 7299 */ 7300 /* DSC_A :: rx_pi_cnt_bin_d :: reserved0 [15:15] */ 7301 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED0_MASK 0x8000 7302 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED0_ALIGN 0 7303 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED0_BITS 1 7304 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED0_SHIFT 15 7305 7306 /* DSC_A :: rx_pi_cnt_bin_d :: cnt_bin_p1_dreg [14:08] */ 7307 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_P1_DREG_MASK 0x7f00 7308 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_P1_DREG_ALIGN 0 7309 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_P1_DREG_BITS 7 7310 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_P1_DREG_SHIFT 8 7311 7312 /* DSC_A :: rx_pi_cnt_bin_d :: reserved1 [07:07] */ 7313 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED1_MASK 0x0080 7314 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED1_ALIGN 0 7315 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED1_BITS 1 7316 #define DSC_A_RX_PI_CNT_BIN_D_RESERVED1_SHIFT 7 7317 7318 /* DSC_A :: rx_pi_cnt_bin_d :: cnt_bin_d_dreg [06:00] */ 7319 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_D_DREG_MASK 0x007f 7320 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_D_DREG_ALIGN 0 7321 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_D_DREG_BITS 7 7322 #define DSC_A_RX_PI_CNT_BIN_D_CNT_BIN_D_DREG_SHIFT 0 7323 7324 7325 /**************************************************************************** 7326 * DSC_A :: rx_pi_cnt_bin_p 7327 */ 7328 /* DSC_A :: rx_pi_cnt_bin_p :: reserved0 [15:15] */ 7329 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED0_MASK 0x8000 7330 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED0_ALIGN 0 7331 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED0_BITS 1 7332 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED0_SHIFT 15 7333 7334 /* DSC_A :: rx_pi_cnt_bin_p :: cnt_bin_m1_preg [14:08] */ 7335 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_M1_PREG_MASK 0x7f00 7336 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_M1_PREG_ALIGN 0 7337 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_M1_PREG_BITS 7 7338 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_M1_PREG_SHIFT 8 7339 7340 /* DSC_A :: rx_pi_cnt_bin_p :: reserved1 [07:07] */ 7341 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED1_MASK 0x0080 7342 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED1_ALIGN 0 7343 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED1_BITS 1 7344 #define DSC_A_RX_PI_CNT_BIN_P_RESERVED1_SHIFT 7 7345 7346 /* DSC_A :: rx_pi_cnt_bin_p :: cnt_bin_p1_preg [06:00] */ 7347 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_P1_PREG_MASK 0x007f 7348 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_P1_PREG_ALIGN 0 7349 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_P1_PREG_BITS 7 7350 #define DSC_A_RX_PI_CNT_BIN_P_CNT_BIN_P1_PREG_SHIFT 0 7351 7352 7353 /**************************************************************************** 7354 * DSC_A :: rx_pi_cnt_bin_m 7355 */ 7356 /* DSC_A :: rx_pi_cnt_bin_m :: reserved0 [15:15] */ 7357 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED0_MASK 0x8000 7358 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED0_ALIGN 0 7359 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED0_BITS 1 7360 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED0_SHIFT 15 7361 7362 /* DSC_A :: rx_pi_cnt_bin_m :: cnt_bin_d_mreg [14:08] */ 7363 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_D_MREG_MASK 0x7f00 7364 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_D_MREG_ALIGN 0 7365 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_D_MREG_BITS 7 7366 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_D_MREG_SHIFT 8 7367 7368 /* DSC_A :: rx_pi_cnt_bin_m :: reserved1 [07:07] */ 7369 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED1_MASK 0x0080 7370 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED1_ALIGN 0 7371 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED1_BITS 1 7372 #define DSC_A_RX_PI_CNT_BIN_M_RESERVED1_SHIFT 7 7373 7374 /* DSC_A :: rx_pi_cnt_bin_m :: cnt_bin_m1_mreg [06:00] */ 7375 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_M1_MREG_MASK 0x007f 7376 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_M1_MREG_ALIGN 0 7377 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_M1_MREG_BITS 7 7378 #define DSC_A_RX_PI_CNT_BIN_M_CNT_BIN_M1_MREG_SHIFT 0 7379 7380 7381 /**************************************************************************** 7382 * DSC_A :: rx_pi_diff_bin 7383 */ 7384 /* DSC_A :: rx_pi_diff_bin :: cnt_d_minus_p1 [15:08] */ 7385 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_P1_MASK 0xff00 7386 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_P1_ALIGN 0 7387 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_P1_BITS 8 7388 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_P1_SHIFT 8 7389 7390 /* DSC_A :: rx_pi_diff_bin :: cnt_d_minus_m1 [07:00] */ 7391 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_M1_MASK 0x00ff 7392 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_M1_ALIGN 0 7393 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_M1_BITS 8 7394 #define DSC_A_RX_PI_DIFF_BIN_CNT_D_MINUS_M1_SHIFT 0 7395 7396 7397 /**************************************************************************** 7398 * DSC_A :: trnsum_cntl_5 7399 */ 7400 /* DSC_A :: trnsum_cntl_5 :: edge_count_refless_en [15:15] */ 7401 #define DSC_A_TRNSUM_CNTL_5_EDGE_COUNT_REFLESS_EN_MASK 0x8000 7402 #define DSC_A_TRNSUM_CNTL_5_EDGE_COUNT_REFLESS_EN_ALIGN 0 7403 #define DSC_A_TRNSUM_CNTL_5_EDGE_COUNT_REFLESS_EN_BITS 1 7404 #define DSC_A_TRNSUM_CNTL_5_EDGE_COUNT_REFLESS_EN_SHIFT 15 7405 7406 /* DSC_A :: trnsum_cntl_5 :: send_lms_to_pcs [14:14] */ 7407 #define DSC_A_TRNSUM_CNTL_5_SEND_LMS_TO_PCS_MASK 0x4000 7408 #define DSC_A_TRNSUM_CNTL_5_SEND_LMS_TO_PCS_ALIGN 0 7409 #define DSC_A_TRNSUM_CNTL_5_SEND_LMS_TO_PCS_BITS 1 7410 #define DSC_A_TRNSUM_CNTL_5_SEND_LMS_TO_PCS_SHIFT 14 7411 7412 /* DSC_A :: trnsum_cntl_5 :: reserved0 [13:00] */ 7413 #define DSC_A_TRNSUM_CNTL_5_RESERVED0_MASK 0x3fff 7414 #define DSC_A_TRNSUM_CNTL_5_RESERVED0_ALIGN 0 7415 #define DSC_A_TRNSUM_CNTL_5_RESERVED0_BITS 14 7416 #define DSC_A_TRNSUM_CNTL_5_RESERVED0_SHIFT 0 7417 7418 7419 /**************************************************************************** 7420 * DSC_A :: dsc_uc_ctrl 7421 */ 7422 /* DSC_A :: dsc_uc_ctrl :: uc_dsc_supp_info [15:08] */ 7423 #define DSC_A_DSC_UC_CTRL_UC_DSC_SUPP_INFO_MASK 0xff00 7424 #define DSC_A_DSC_UC_CTRL_UC_DSC_SUPP_INFO_ALIGN 0 7425 #define DSC_A_DSC_UC_CTRL_UC_DSC_SUPP_INFO_BITS 8 7426 #define DSC_A_DSC_UC_CTRL_UC_DSC_SUPP_INFO_SHIFT 8 7427 7428 /* DSC_A :: dsc_uc_ctrl :: uc_dsc_ready_for_cmd [07:07] */ 7429 #define DSC_A_DSC_UC_CTRL_UC_DSC_READY_FOR_CMD_MASK 0x0080 7430 #define DSC_A_DSC_UC_CTRL_UC_DSC_READY_FOR_CMD_ALIGN 0 7431 #define DSC_A_DSC_UC_CTRL_UC_DSC_READY_FOR_CMD_BITS 1 7432 #define DSC_A_DSC_UC_CTRL_UC_DSC_READY_FOR_CMD_SHIFT 7 7433 7434 /* DSC_A :: dsc_uc_ctrl :: uc_dsc_error_found [06:06] */ 7435 #define DSC_A_DSC_UC_CTRL_UC_DSC_ERROR_FOUND_MASK 0x0040 7436 #define DSC_A_DSC_UC_CTRL_UC_DSC_ERROR_FOUND_ALIGN 0 7437 #define DSC_A_DSC_UC_CTRL_UC_DSC_ERROR_FOUND_BITS 1 7438 #define DSC_A_DSC_UC_CTRL_UC_DSC_ERROR_FOUND_SHIFT 6 7439 7440 /* DSC_A :: dsc_uc_ctrl :: uc_dsc_gp_uc_req [05:00] */ 7441 #define DSC_A_DSC_UC_CTRL_UC_DSC_GP_UC_REQ_MASK 0x003f 7442 #define DSC_A_DSC_UC_CTRL_UC_DSC_GP_UC_REQ_ALIGN 0 7443 #define DSC_A_DSC_UC_CTRL_UC_DSC_GP_UC_REQ_BITS 6 7444 #define DSC_A_DSC_UC_CTRL_UC_DSC_GP_UC_REQ_SHIFT 0 7445 7446 7447 /**************************************************************************** 7448 * DSC_A :: dsc_scratch 7449 */ 7450 /* DSC_A :: dsc_scratch :: uc_dsc_scratch [15:00] */ 7451 #define DSC_A_DSC_SCRATCH_UC_DSC_SCRATCH_MASK 0xffff 7452 #define DSC_A_DSC_SCRATCH_UC_DSC_SCRATCH_ALIGN 0 7453 #define DSC_A_DSC_SCRATCH_UC_DSC_SCRATCH_BITS 16 7454 #define DSC_A_DSC_SCRATCH_UC_DSC_SCRATCH_SHIFT 0 7455 7456 7457 /**************************************************************************** 7458 * merlin_gallardo_dsc_blk_DSC_B 7459 */ 7460 /**************************************************************************** 7461 * DSC_B :: dsc_sm_ctrl_0 7462 */ 7463 /* DSC_B :: dsc_sm_ctrl_0 :: reserved0 [15:15] */ 7464 #define DSC_B_DSC_SM_CTRL_0_RESERVED0_MASK 0x8000 7465 #define DSC_B_DSC_SM_CTRL_0_RESERVED0_ALIGN 0 7466 #define DSC_B_DSC_SM_CTRL_0_RESERVED0_BITS 1 7467 #define DSC_B_DSC_SM_CTRL_0_RESERVED0_SHIFT 15 7468 7469 /* DSC_B :: dsc_sm_ctrl_0 :: uc_ack_dsc_config [14:14] */ 7470 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_CONFIG_MASK 0x4000 7471 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_CONFIG_ALIGN 0 7472 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_CONFIG_BITS 1 7473 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_CONFIG_SHIFT 14 7474 7475 /* DSC_B :: dsc_sm_ctrl_0 :: uc_ack_dsc_restart [13:13] */ 7476 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESTART_MASK 0x2000 7477 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESTART_ALIGN 0 7478 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESTART_BITS 1 7479 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESTART_SHIFT 13 7480 7481 /* DSC_B :: dsc_sm_ctrl_0 :: uc_ack_dsc_reset [12:12] */ 7482 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESET_MASK 0x1000 7483 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESET_ALIGN 0 7484 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESET_BITS 1 7485 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_RESET_SHIFT 12 7486 7487 /* DSC_B :: dsc_sm_ctrl_0 :: uc_ack_dsc_eee_done [11:11] */ 7488 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_EEE_DONE_MASK 0x0800 7489 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_EEE_DONE_ALIGN 0 7490 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_EEE_DONE_BITS 1 7491 #define DSC_B_DSC_SM_CTRL_0_UC_ACK_DSC_EEE_DONE_SHIFT 11 7492 7493 /* DSC_B :: dsc_sm_ctrl_0 :: reserved1 [10:09] */ 7494 #define DSC_B_DSC_SM_CTRL_0_RESERVED1_MASK 0x0600 7495 #define DSC_B_DSC_SM_CTRL_0_RESERVED1_ALIGN 0 7496 #define DSC_B_DSC_SM_CTRL_0_RESERVED1_BITS 2 7497 #define DSC_B_DSC_SM_CTRL_0_RESERVED1_SHIFT 9 7498 7499 /* DSC_B :: dsc_sm_ctrl_0 :: eee_measure_en [08:08] */ 7500 #define DSC_B_DSC_SM_CTRL_0_EEE_MEASURE_EN_MASK 0x0100 7501 #define DSC_B_DSC_SM_CTRL_0_EEE_MEASURE_EN_ALIGN 0 7502 #define DSC_B_DSC_SM_CTRL_0_EEE_MEASURE_EN_BITS 1 7503 #define DSC_B_DSC_SM_CTRL_0_EEE_MEASURE_EN_SHIFT 8 7504 7505 /* DSC_B :: dsc_sm_ctrl_0 :: uc_trnsum_en [07:07] */ 7506 #define DSC_B_DSC_SM_CTRL_0_UC_TRNSUM_EN_MASK 0x0080 7507 #define DSC_B_DSC_SM_CTRL_0_UC_TRNSUM_EN_ALIGN 0 7508 #define DSC_B_DSC_SM_CTRL_0_UC_TRNSUM_EN_BITS 1 7509 #define DSC_B_DSC_SM_CTRL_0_UC_TRNSUM_EN_SHIFT 7 7510 7511 /* DSC_B :: dsc_sm_ctrl_0 :: hw_tune_en [06:06] */ 7512 #define DSC_B_DSC_SM_CTRL_0_HW_TUNE_EN_MASK 0x0040 7513 #define DSC_B_DSC_SM_CTRL_0_HW_TUNE_EN_ALIGN 0 7514 #define DSC_B_DSC_SM_CTRL_0_HW_TUNE_EN_BITS 1 7515 #define DSC_B_DSC_SM_CTRL_0_HW_TUNE_EN_SHIFT 6 7516 7517 /* DSC_B :: dsc_sm_ctrl_0 :: uc_tune_en [05:05] */ 7518 #define DSC_B_DSC_SM_CTRL_0_UC_TUNE_EN_MASK 0x0020 7519 #define DSC_B_DSC_SM_CTRL_0_UC_TUNE_EN_ALIGN 0 7520 #define DSC_B_DSC_SM_CTRL_0_UC_TUNE_EN_BITS 1 7521 #define DSC_B_DSC_SM_CTRL_0_UC_TUNE_EN_SHIFT 5 7522 7523 /* DSC_B :: dsc_sm_ctrl_0 :: cl72_timer_en [04:04] */ 7524 #define DSC_B_DSC_SM_CTRL_0_CL72_TIMER_EN_MASK 0x0010 7525 #define DSC_B_DSC_SM_CTRL_0_CL72_TIMER_EN_ALIGN 0 7526 #define DSC_B_DSC_SM_CTRL_0_CL72_TIMER_EN_BITS 1 7527 #define DSC_B_DSC_SM_CTRL_0_CL72_TIMER_EN_SHIFT 4 7528 7529 /* DSC_B :: dsc_sm_ctrl_0 :: ignore_rx_mode [03:03] */ 7530 #define DSC_B_DSC_SM_CTRL_0_IGNORE_RX_MODE_MASK 0x0008 7531 #define DSC_B_DSC_SM_CTRL_0_IGNORE_RX_MODE_ALIGN 0 7532 #define DSC_B_DSC_SM_CTRL_0_IGNORE_RX_MODE_BITS 1 7533 #define DSC_B_DSC_SM_CTRL_0_IGNORE_RX_MODE_SHIFT 3 7534 7535 /* DSC_B :: dsc_sm_ctrl_0 :: eee_quiet_rx_afe_pwrdwn_val [02:02] */ 7536 #define DSC_B_DSC_SM_CTRL_0_EEE_QUIET_RX_AFE_PWRDWN_VAL_MASK 0x0004 7537 #define DSC_B_DSC_SM_CTRL_0_EEE_QUIET_RX_AFE_PWRDWN_VAL_ALIGN 0 7538 #define DSC_B_DSC_SM_CTRL_0_EEE_QUIET_RX_AFE_PWRDWN_VAL_BITS 1 7539 #define DSC_B_DSC_SM_CTRL_0_EEE_QUIET_RX_AFE_PWRDWN_VAL_SHIFT 2 7540 7541 /* DSC_B :: dsc_sm_ctrl_0 :: eee_mode_en [01:01] */ 7542 #define DSC_B_DSC_SM_CTRL_0_EEE_MODE_EN_MASK 0x0002 7543 #define DSC_B_DSC_SM_CTRL_0_EEE_MODE_EN_ALIGN 0 7544 #define DSC_B_DSC_SM_CTRL_0_EEE_MODE_EN_BITS 1 7545 #define DSC_B_DSC_SM_CTRL_0_EEE_MODE_EN_SHIFT 1 7546 7547 /* DSC_B :: dsc_sm_ctrl_0 :: rx_restart_pmd_hold [00:00] */ 7548 #define DSC_B_DSC_SM_CTRL_0_RX_RESTART_PMD_HOLD_MASK 0x0001 7549 #define DSC_B_DSC_SM_CTRL_0_RX_RESTART_PMD_HOLD_ALIGN 0 7550 #define DSC_B_DSC_SM_CTRL_0_RX_RESTART_PMD_HOLD_BITS 1 7551 #define DSC_B_DSC_SM_CTRL_0_RX_RESTART_PMD_HOLD_SHIFT 0 7552 7553 7554 /**************************************************************************** 7555 * DSC_B :: dsc_sm_ctrl_1 7556 */ 7557 /* DSC_B :: dsc_sm_ctrl_1 :: reserved0 [15:14] */ 7558 #define DSC_B_DSC_SM_CTRL_1_RESERVED0_MASK 0xc000 7559 #define DSC_B_DSC_SM_CTRL_1_RESERVED0_ALIGN 0 7560 #define DSC_B_DSC_SM_CTRL_1_RESERVED0_BITS 2 7561 #define DSC_B_DSC_SM_CTRL_1_RESERVED0_SHIFT 14 7562 7563 /* DSC_B :: dsc_sm_ctrl_1 :: trnsum_clr_frc_val [13:13] */ 7564 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_VAL_MASK 0x2000 7565 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_VAL_ALIGN 0 7566 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_VAL_BITS 1 7567 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_VAL_SHIFT 13 7568 7569 /* DSC_B :: dsc_sm_ctrl_1 :: trnsum_clr_frc [12:12] */ 7570 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_MASK 0x1000 7571 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_ALIGN 0 7572 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_BITS 1 7573 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_CLR_FRC_SHIFT 12 7574 7575 /* DSC_B :: dsc_sm_ctrl_1 :: cdr_frz_frc_val [11:11] */ 7576 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_VAL_MASK 0x0800 7577 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_VAL_ALIGN 0 7578 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_VAL_BITS 1 7579 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_VAL_SHIFT 11 7580 7581 /* DSC_B :: dsc_sm_ctrl_1 :: cdr_frz_frc [10:10] */ 7582 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_MASK 0x0400 7583 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_ALIGN 0 7584 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_BITS 1 7585 #define DSC_B_DSC_SM_CTRL_1_CDR_FRZ_FRC_SHIFT 10 7586 7587 /* DSC_B :: dsc_sm_ctrl_1 :: freq_upd_en_frc_val [09:09] */ 7588 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_VAL_MASK 0x0200 7589 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_VAL_ALIGN 0 7590 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_VAL_BITS 1 7591 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_VAL_SHIFT 9 7592 7593 /* DSC_B :: dsc_sm_ctrl_1 :: freq_upd_en_frc [08:08] */ 7594 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_MASK 0x0100 7595 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_ALIGN 0 7596 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_BITS 1 7597 #define DSC_B_DSC_SM_CTRL_1_FREQ_UPD_EN_FRC_SHIFT 8 7598 7599 /* DSC_B :: dsc_sm_ctrl_1 :: timer_done_frc_val [07:07] */ 7600 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_VAL_MASK 0x0080 7601 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_VAL_ALIGN 0 7602 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_VAL_BITS 1 7603 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_VAL_SHIFT 7 7604 7605 /* DSC_B :: dsc_sm_ctrl_1 :: timer_done_frc [06:06] */ 7606 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_MASK 0x0040 7607 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_ALIGN 0 7608 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_BITS 1 7609 #define DSC_B_DSC_SM_CTRL_1_TIMER_DONE_FRC_SHIFT 6 7610 7611 /* DSC_B :: dsc_sm_ctrl_1 :: trnsum_frz_val [05:05] */ 7612 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_VAL_MASK 0x0020 7613 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_VAL_ALIGN 0 7614 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_VAL_BITS 1 7615 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_VAL_SHIFT 5 7616 7617 /* DSC_B :: dsc_sm_ctrl_1 :: trnsum_frz_frc [04:04] */ 7618 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_MASK 0x0010 7619 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_ALIGN 0 7620 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_BITS 1 7621 #define DSC_B_DSC_SM_CTRL_1_TRNSUM_FRZ_FRC_SHIFT 4 7622 7623 /* DSC_B :: dsc_sm_ctrl_1 :: dsc_clr_frc_val [03:03] */ 7624 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_VAL_MASK 0x0008 7625 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_VAL_ALIGN 0 7626 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_VAL_BITS 1 7627 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_VAL_SHIFT 3 7628 7629 /* DSC_B :: dsc_sm_ctrl_1 :: dsc_clr_frc [02:02] */ 7630 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_MASK 0x0004 7631 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_ALIGN 0 7632 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_BITS 1 7633 #define DSC_B_DSC_SM_CTRL_1_DSC_CLR_FRC_SHIFT 2 7634 7635 /* DSC_B :: dsc_sm_ctrl_1 :: rx_dsc_lock_frc_val [01:01] */ 7636 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_VAL_MASK 0x0002 7637 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_VAL_ALIGN 0 7638 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_VAL_BITS 1 7639 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_VAL_SHIFT 1 7640 7641 /* DSC_B :: dsc_sm_ctrl_1 :: rx_dsc_lock_frc [00:00] */ 7642 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_MASK 0x0001 7643 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_ALIGN 0 7644 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_BITS 1 7645 #define DSC_B_DSC_SM_CTRL_1_RX_DSC_LOCK_FRC_SHIFT 0 7646 7647 7648 /**************************************************************************** 7649 * DSC_B :: dsc_sm_ctrl_2 7650 */ 7651 /* DSC_B :: dsc_sm_ctrl_2 :: reserved0 [15:13] */ 7652 #define DSC_B_DSC_SM_CTRL_2_RESERVED0_MASK 0xe000 7653 #define DSC_B_DSC_SM_CTRL_2_RESERVED0_ALIGN 0 7654 #define DSC_B_DSC_SM_CTRL_2_RESERVED0_BITS 3 7655 #define DSC_B_DSC_SM_CTRL_2_RESERVED0_SHIFT 13 7656 7657 /* DSC_B :: dsc_sm_ctrl_2 :: eee_lfsr_cnt [12:00] */ 7658 #define DSC_B_DSC_SM_CTRL_2_EEE_LFSR_CNT_MASK 0x1fff 7659 #define DSC_B_DSC_SM_CTRL_2_EEE_LFSR_CNT_ALIGN 0 7660 #define DSC_B_DSC_SM_CTRL_2_EEE_LFSR_CNT_BITS 13 7661 #define DSC_B_DSC_SM_CTRL_2_EEE_LFSR_CNT_SHIFT 0 7662 7663 7664 /**************************************************************************** 7665 * DSC_B :: dsc_sm_ctrl_3 7666 */ 7667 /* DSC_B :: dsc_sm_ctrl_3 :: reserved0 [15:13] */ 7668 #define DSC_B_DSC_SM_CTRL_3_RESERVED0_MASK 0xe000 7669 #define DSC_B_DSC_SM_CTRL_3_RESERVED0_ALIGN 0 7670 #define DSC_B_DSC_SM_CTRL_3_RESERVED0_BITS 3 7671 #define DSC_B_DSC_SM_CTRL_3_RESERVED0_SHIFT 13 7672 7673 /* DSC_B :: dsc_sm_ctrl_3 :: measure_lfsr_cnt [12:00] */ 7674 #define DSC_B_DSC_SM_CTRL_3_MEASURE_LFSR_CNT_MASK 0x1fff 7675 #define DSC_B_DSC_SM_CTRL_3_MEASURE_LFSR_CNT_ALIGN 0 7676 #define DSC_B_DSC_SM_CTRL_3_MEASURE_LFSR_CNT_BITS 13 7677 #define DSC_B_DSC_SM_CTRL_3_MEASURE_LFSR_CNT_SHIFT 0 7678 7679 7680 /**************************************************************************** 7681 * DSC_B :: dsc_sm_ctrl_4 7682 */ 7683 /* DSC_B :: dsc_sm_ctrl_4 :: reserved0 [15:15] */ 7684 #define DSC_B_DSC_SM_CTRL_4_RESERVED0_MASK 0x8000 7685 #define DSC_B_DSC_SM_CTRL_4_RESERVED0_ALIGN 0 7686 #define DSC_B_DSC_SM_CTRL_4_RESERVED0_BITS 1 7687 #define DSC_B_DSC_SM_CTRL_4_RESERVED0_SHIFT 15 7688 7689 /* DSC_B :: dsc_sm_ctrl_4 :: hw_tune_timeout [14:10] */ 7690 #define DSC_B_DSC_SM_CTRL_4_HW_TUNE_TIMEOUT_MASK 0x7c00 7691 #define DSC_B_DSC_SM_CTRL_4_HW_TUNE_TIMEOUT_ALIGN 0 7692 #define DSC_B_DSC_SM_CTRL_4_HW_TUNE_TIMEOUT_BITS 5 7693 #define DSC_B_DSC_SM_CTRL_4_HW_TUNE_TIMEOUT_SHIFT 10 7694 7695 /* DSC_B :: dsc_sm_ctrl_4 :: cdr_settle_timeout [09:05] */ 7696 #define DSC_B_DSC_SM_CTRL_4_CDR_SETTLE_TIMEOUT_MASK 0x03e0 7697 #define DSC_B_DSC_SM_CTRL_4_CDR_SETTLE_TIMEOUT_ALIGN 0 7698 #define DSC_B_DSC_SM_CTRL_4_CDR_SETTLE_TIMEOUT_BITS 5 7699 #define DSC_B_DSC_SM_CTRL_4_CDR_SETTLE_TIMEOUT_SHIFT 5 7700 7701 /* DSC_B :: dsc_sm_ctrl_4 :: acq_cdr_timeout [04:00] */ 7702 #define DSC_B_DSC_SM_CTRL_4_ACQ_CDR_TIMEOUT_MASK 0x001f 7703 #define DSC_B_DSC_SM_CTRL_4_ACQ_CDR_TIMEOUT_ALIGN 0 7704 #define DSC_B_DSC_SM_CTRL_4_ACQ_CDR_TIMEOUT_BITS 5 7705 #define DSC_B_DSC_SM_CTRL_4_ACQ_CDR_TIMEOUT_SHIFT 0 7706 7707 7708 /**************************************************************************** 7709 * DSC_B :: dsc_sm_ctrl_5 7710 */ 7711 /* DSC_B :: dsc_sm_ctrl_5 :: reserved0 [15:15] */ 7712 #define DSC_B_DSC_SM_CTRL_5_RESERVED0_MASK 0x8000 7713 #define DSC_B_DSC_SM_CTRL_5_RESERVED0_ALIGN 0 7714 #define DSC_B_DSC_SM_CTRL_5_RESERVED0_BITS 1 7715 #define DSC_B_DSC_SM_CTRL_5_RESERVED0_SHIFT 15 7716 7717 /* DSC_B :: dsc_sm_ctrl_5 :: eee_cdr_settle_timeout [14:10] */ 7718 #define DSC_B_DSC_SM_CTRL_5_EEE_CDR_SETTLE_TIMEOUT_MASK 0x7c00 7719 #define DSC_B_DSC_SM_CTRL_5_EEE_CDR_SETTLE_TIMEOUT_ALIGN 0 7720 #define DSC_B_DSC_SM_CTRL_5_EEE_CDR_SETTLE_TIMEOUT_BITS 5 7721 #define DSC_B_DSC_SM_CTRL_5_EEE_CDR_SETTLE_TIMEOUT_SHIFT 10 7722 7723 /* DSC_B :: dsc_sm_ctrl_5 :: eee_acq_cdr_timeout [09:05] */ 7724 #define DSC_B_DSC_SM_CTRL_5_EEE_ACQ_CDR_TIMEOUT_MASK 0x03e0 7725 #define DSC_B_DSC_SM_CTRL_5_EEE_ACQ_CDR_TIMEOUT_ALIGN 0 7726 #define DSC_B_DSC_SM_CTRL_5_EEE_ACQ_CDR_TIMEOUT_BITS 5 7727 #define DSC_B_DSC_SM_CTRL_5_EEE_ACQ_CDR_TIMEOUT_SHIFT 5 7728 7729 /* DSC_B :: dsc_sm_ctrl_5 :: measure_timeout [04:00] */ 7730 #define DSC_B_DSC_SM_CTRL_5_MEASURE_TIMEOUT_MASK 0x001f 7731 #define DSC_B_DSC_SM_CTRL_5_MEASURE_TIMEOUT_ALIGN 0 7732 #define DSC_B_DSC_SM_CTRL_5_MEASURE_TIMEOUT_BITS 5 7733 #define DSC_B_DSC_SM_CTRL_5_MEASURE_TIMEOUT_SHIFT 0 7734 7735 7736 /**************************************************************************** 7737 * DSC_B :: dsc_sm_ctrl_6 7738 */ 7739 /* DSC_B :: dsc_sm_ctrl_6 :: reserved0 [15:10] */ 7740 #define DSC_B_DSC_SM_CTRL_6_RESERVED0_MASK 0xfc00 7741 #define DSC_B_DSC_SM_CTRL_6_RESERVED0_ALIGN 0 7742 #define DSC_B_DSC_SM_CTRL_6_RESERVED0_BITS 6 7743 #define DSC_B_DSC_SM_CTRL_6_RESERVED0_SHIFT 10 7744 7745 /* DSC_B :: dsc_sm_ctrl_6 :: eee_ana_pwr_timeout [09:05] */ 7746 #define DSC_B_DSC_SM_CTRL_6_EEE_ANA_PWR_TIMEOUT_MASK 0x03e0 7747 #define DSC_B_DSC_SM_CTRL_6_EEE_ANA_PWR_TIMEOUT_ALIGN 0 7748 #define DSC_B_DSC_SM_CTRL_6_EEE_ANA_PWR_TIMEOUT_BITS 5 7749 #define DSC_B_DSC_SM_CTRL_6_EEE_ANA_PWR_TIMEOUT_SHIFT 5 7750 7751 /* DSC_B :: dsc_sm_ctrl_6 :: eee_hw_tune_timeout [04:00] */ 7752 #define DSC_B_DSC_SM_CTRL_6_EEE_HW_TUNE_TIMEOUT_MASK 0x001f 7753 #define DSC_B_DSC_SM_CTRL_6_EEE_HW_TUNE_TIMEOUT_ALIGN 0 7754 #define DSC_B_DSC_SM_CTRL_6_EEE_HW_TUNE_TIMEOUT_BITS 5 7755 #define DSC_B_DSC_SM_CTRL_6_EEE_HW_TUNE_TIMEOUT_SHIFT 0 7756 7757 7758 /**************************************************************************** 7759 * DSC_B :: dsc_sm_ctrl_7 7760 */ 7761 /* DSC_B :: dsc_sm_ctrl_7 :: cdr_bwsel_prop_norm [15:14] */ 7762 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_NORM_MASK 0xc000 7763 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_NORM_ALIGN 0 7764 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_NORM_BITS 2 7765 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_NORM_SHIFT 14 7766 7767 /* DSC_B :: dsc_sm_ctrl_7 :: cdr_bwsel_prop_acqcdr [13:12] */ 7768 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_ACQCDR_MASK 0x3000 7769 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_ACQCDR_ALIGN 0 7770 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_ACQCDR_BITS 2 7771 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_PROP_ACQCDR_SHIFT 12 7772 7773 /* DSC_B :: dsc_sm_ctrl_7 :: cdr_bwsel_integ_norm [11:08] */ 7774 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_NORM_MASK 0x0f00 7775 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_NORM_ALIGN 0 7776 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_NORM_BITS 4 7777 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_NORM_SHIFT 8 7778 7779 /* DSC_B :: dsc_sm_ctrl_7 :: cdr_bwsel_integ_eee_acqcdr [07:04] */ 7780 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_EEE_ACQCDR_MASK 0x00f0 7781 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_EEE_ACQCDR_ALIGN 0 7782 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_EEE_ACQCDR_BITS 4 7783 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_EEE_ACQCDR_SHIFT 4 7784 7785 /* DSC_B :: dsc_sm_ctrl_7 :: cdr_bwsel_integ_acqcdr [03:00] */ 7786 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_ACQCDR_MASK 0x000f 7787 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_ACQCDR_ALIGN 0 7788 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_ACQCDR_BITS 4 7789 #define DSC_B_DSC_SM_CTRL_7_CDR_BWSEL_INTEG_ACQCDR_SHIFT 0 7790 7791 7792 /**************************************************************************** 7793 * DSC_B :: dsc_sm_ctrl_8 7794 */ 7795 /* DSC_B :: dsc_sm_ctrl_8 :: cdr_bwsel_prop_eee_acqcdr [15:14] */ 7796 #define DSC_B_DSC_SM_CTRL_8_CDR_BWSEL_PROP_EEE_ACQCDR_MASK 0xc000 7797 #define DSC_B_DSC_SM_CTRL_8_CDR_BWSEL_PROP_EEE_ACQCDR_ALIGN 0 7798 #define DSC_B_DSC_SM_CTRL_8_CDR_BWSEL_PROP_EEE_ACQCDR_BITS 2 7799 #define DSC_B_DSC_SM_CTRL_8_CDR_BWSEL_PROP_EEE_ACQCDR_SHIFT 14 7800 7801 /* DSC_B :: dsc_sm_ctrl_8 :: reserved0 [13:12] */ 7802 #define DSC_B_DSC_SM_CTRL_8_RESERVED0_MASK 0x3000 7803 #define DSC_B_DSC_SM_CTRL_8_RESERVED0_ALIGN 0 7804 #define DSC_B_DSC_SM_CTRL_8_RESERVED0_BITS 2 7805 #define DSC_B_DSC_SM_CTRL_8_RESERVED0_SHIFT 12 7806 7807 /* DSC_B :: dsc_sm_ctrl_8 :: eee_phase_err_offset_en [11:10] */ 7808 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_EN_MASK 0x0c00 7809 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_EN_ALIGN 0 7810 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_EN_BITS 2 7811 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_EN_SHIFT 10 7812 7813 /* DSC_B :: dsc_sm_ctrl_8 :: phase_err_offset_en [09:08] */ 7814 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_EN_MASK 0x0300 7815 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_EN_ALIGN 0 7816 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_EN_BITS 2 7817 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_EN_SHIFT 8 7818 7819 /* DSC_B :: dsc_sm_ctrl_8 :: eee_phase_err_offset [07:04] */ 7820 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_MASK 0x00f0 7821 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_ALIGN 0 7822 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_BITS 4 7823 #define DSC_B_DSC_SM_CTRL_8_EEE_PHASE_ERR_OFFSET_SHIFT 4 7824 7825 /* DSC_B :: dsc_sm_ctrl_8 :: phase_err_offset [03:00] */ 7826 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_MASK 0x000f 7827 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_ALIGN 0 7828 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_BITS 4 7829 #define DSC_B_DSC_SM_CTRL_8_PHASE_ERR_OFFSET_SHIFT 0 7830 7831 7832 /**************************************************************************** 7833 * DSC_B :: dsc_sm_ctrl_9 7834 */ 7835 /* DSC_B :: dsc_sm_ctrl_9 :: reserved0 [15:01] */ 7836 #define DSC_B_DSC_SM_CTRL_9_RESERVED0_MASK 0xfffe 7837 #define DSC_B_DSC_SM_CTRL_9_RESERVED0_ALIGN 0 7838 #define DSC_B_DSC_SM_CTRL_9_RESERVED0_BITS 15 7839 #define DSC_B_DSC_SM_CTRL_9_RESERVED0_SHIFT 1 7840 7841 /* DSC_B :: dsc_sm_ctrl_9 :: rx_restart_pmd [00:00] */ 7842 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_MASK 0x0001 7843 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_ALIGN 0 7844 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_BITS 1 7845 #define DSC_B_DSC_SM_CTRL_9_RX_RESTART_PMD_SHIFT 0 7846 7847 7848 /**************************************************************************** 7849 * DSC_B :: dsc_sm_status_dsc_lock 7850 */ 7851 /* DSC_B :: dsc_sm_status_dsc_lock :: reserved0 [15:01] */ 7852 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RESERVED0_MASK 0xfffe 7853 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RESERVED0_ALIGN 0 7854 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RESERVED0_BITS 15 7855 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RESERVED0_SHIFT 1 7856 7857 /* DSC_B :: dsc_sm_status_dsc_lock :: rx_dsc_lock [00:00] */ 7858 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RX_DSC_LOCK_MASK 0x0001 7859 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RX_DSC_LOCK_ALIGN 0 7860 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RX_DSC_LOCK_BITS 1 7861 #define DSC_B_DSC_SM_STATUS_DSC_LOCK_RX_DSC_LOCK_SHIFT 0 7862 7863 7864 /**************************************************************************** 7865 * DSC_B :: dsc_sm_status_dsc_state_one_hot 7866 */ 7867 /* DSC_B :: dsc_sm_status_dsc_state_one_hot :: reserved0 [15:10] */ 7868 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_RESERVED0_MASK 0xfc00 7869 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_RESERVED0_ALIGN 0 7870 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_RESERVED0_BITS 6 7871 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_RESERVED0_SHIFT 10 7872 7873 /* DSC_B :: dsc_sm_status_dsc_state_one_hot :: dsc_state_one_hot [09:00] */ 7874 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_DSC_STATE_ONE_HOT_MASK 0x03ff 7875 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_DSC_STATE_ONE_HOT_ALIGN 0 7876 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_DSC_STATE_ONE_HOT_BITS 10 7877 #define DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_DSC_STATE_ONE_HOT_SHIFT 0 7878 7879 7880 /**************************************************************************** 7881 * DSC_B :: dsc_sm_status_dsc_state_eee_one_hot 7882 */ 7883 /* DSC_B :: dsc_sm_status_dsc_state_eee_one_hot :: reserved0 [15:07] */ 7884 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_RESERVED0_MASK 0xff80 7885 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_RESERVED0_ALIGN 0 7886 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_RESERVED0_BITS 9 7887 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_RESERVED0_SHIFT 7 7888 7889 /* DSC_B :: dsc_sm_status_dsc_state_eee_one_hot :: dsc_state_eee_one_hot [06:00] */ 7890 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_DSC_STATE_EEE_ONE_HOT_MASK 0x007f 7891 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_DSC_STATE_EEE_ONE_HOT_ALIGN 0 7892 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_DSC_STATE_EEE_ONE_HOT_BITS 7 7893 #define DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT_DSC_STATE_EEE_ONE_HOT_SHIFT 0 7894 7895 7896 /**************************************************************************** 7897 * DSC_B :: dsc_sm_status_restart 7898 */ 7899 /* DSC_B :: dsc_sm_status_restart :: reserved0 [15:04] */ 7900 #define DSC_B_DSC_SM_STATUS_RESTART_RESERVED0_MASK 0xfff0 7901 #define DSC_B_DSC_SM_STATUS_RESTART_RESERVED0_ALIGN 0 7902 #define DSC_B_DSC_SM_STATUS_RESTART_RESERVED0_BITS 12 7903 #define DSC_B_DSC_SM_STATUS_RESTART_RESERVED0_SHIFT 4 7904 7905 /* DSC_B :: dsc_sm_status_restart :: eee_quiet_from_eee_states [03:03] */ 7906 #define DSC_B_DSC_SM_STATUS_RESTART_EEE_QUIET_FROM_EEE_STATES_MASK 0x0008 7907 #define DSC_B_DSC_SM_STATUS_RESTART_EEE_QUIET_FROM_EEE_STATES_ALIGN 0 7908 #define DSC_B_DSC_SM_STATUS_RESTART_EEE_QUIET_FROM_EEE_STATES_BITS 1 7909 #define DSC_B_DSC_SM_STATUS_RESTART_EEE_QUIET_FROM_EEE_STATES_SHIFT 3 7910 7911 /* DSC_B :: dsc_sm_status_restart :: restart_pmd_restart [02:02] */ 7912 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PMD_RESTART_MASK 0x0004 7913 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PMD_RESTART_ALIGN 0 7914 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PMD_RESTART_BITS 1 7915 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PMD_RESTART_SHIFT 2 7916 7917 /* DSC_B :: dsc_sm_status_restart :: restart_sigdet [01:01] */ 7918 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_SIGDET_MASK 0x0002 7919 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_SIGDET_ALIGN 0 7920 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_SIGDET_BITS 1 7921 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_SIGDET_SHIFT 1 7922 7923 /* DSC_B :: dsc_sm_status_restart :: restart_pi_ext_mode [00:00] */ 7924 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PI_EXT_MODE_MASK 0x0001 7925 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PI_EXT_MODE_ALIGN 0 7926 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PI_EXT_MODE_BITS 1 7927 #define DSC_B_DSC_SM_STATUS_RESTART_RESTART_PI_EXT_MODE_SHIFT 0 7928 7929 7930 /**************************************************************************** 7931 * DSC_B :: dsc_sm_status_dsc_state 7932 */ 7933 /* DSC_B :: dsc_sm_status_dsc_state :: dsc_state [15:11] */ 7934 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_STATE_MASK 0xf800 7935 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_STATE_ALIGN 0 7936 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_STATE_BITS 5 7937 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_STATE_SHIFT 11 7938 7939 /* DSC_B :: dsc_sm_status_dsc_state :: dsc_sm_gp_uc_req [10:05] */ 7940 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_GP_UC_REQ_MASK 0x07e0 7941 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_GP_UC_REQ_ALIGN 0 7942 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_GP_UC_REQ_BITS 6 7943 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_GP_UC_REQ_SHIFT 5 7944 7945 /* DSC_B :: dsc_sm_status_dsc_state :: dsc_sm_ready_for_cmd [04:04] */ 7946 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_READY_FOR_CMD_MASK 0x0010 7947 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_READY_FOR_CMD_ALIGN 0 7948 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_READY_FOR_CMD_BITS 1 7949 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_READY_FOR_CMD_SHIFT 4 7950 7951 /* DSC_B :: dsc_sm_status_dsc_state :: dsc_sm_scratch [03:00] */ 7952 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_SCRATCH_MASK 0x000f 7953 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_SCRATCH_ALIGN 0 7954 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_SCRATCH_BITS 4 7955 #define DSC_B_DSC_SM_STATUS_DSC_STATE_DSC_SM_SCRATCH_SHIFT 0 7956 7957 7958 /**************************************************************************** 7959 * merlin_gallardo_dsc_blk_DSC_C 7960 */ 7961 /**************************************************************************** 7962 * DSC_C :: dfe_common_ctl 7963 */ 7964 /* DSC_C :: dfe_common_ctl :: dfe_acc_hys_en [15:15] */ 7965 #define DSC_C_DFE_COMMON_CTL_DFE_ACC_HYS_EN_MASK 0x8000 7966 #define DSC_C_DFE_COMMON_CTL_DFE_ACC_HYS_EN_ALIGN 0 7967 #define DSC_C_DFE_COMMON_CTL_DFE_ACC_HYS_EN_BITS 1 7968 #define DSC_C_DFE_COMMON_CTL_DFE_ACC_HYS_EN_SHIFT 15 7969 7970 /* DSC_C :: dfe_common_ctl :: dfe_allow_simult [14:14] */ 7971 #define DSC_C_DFE_COMMON_CTL_DFE_ALLOW_SIMULT_MASK 0x4000 7972 #define DSC_C_DFE_COMMON_CTL_DFE_ALLOW_SIMULT_ALIGN 0 7973 #define DSC_C_DFE_COMMON_CTL_DFE_ALLOW_SIMULT_BITS 1 7974 #define DSC_C_DFE_COMMON_CTL_DFE_ALLOW_SIMULT_SHIFT 14 7975 7976 /* DSC_C :: dfe_common_ctl :: dfe_update_gain [13:13] */ 7977 #define DSC_C_DFE_COMMON_CTL_DFE_UPDATE_GAIN_MASK 0x2000 7978 #define DSC_C_DFE_COMMON_CTL_DFE_UPDATE_GAIN_ALIGN 0 7979 #define DSC_C_DFE_COMMON_CTL_DFE_UPDATE_GAIN_BITS 1 7980 #define DSC_C_DFE_COMMON_CTL_DFE_UPDATE_GAIN_SHIFT 13 7981 7982 /* DSC_C :: dfe_common_ctl :: reserved0 [12:00] */ 7983 #define DSC_C_DFE_COMMON_CTL_RESERVED0_MASK 0x1fff 7984 #define DSC_C_DFE_COMMON_CTL_RESERVED0_ALIGN 0 7985 #define DSC_C_DFE_COMMON_CTL_RESERVED0_BITS 13 7986 #define DSC_C_DFE_COMMON_CTL_RESERVED0_SHIFT 0 7987 7988 7989 /**************************************************************************** 7990 * DSC_C :: dfe_1_ctl 7991 */ 7992 /* DSC_C :: dfe_1_ctl :: dfe_1_en [15:15] */ 7993 #define DSC_C_DFE_1_CTL_DFE_1_EN_MASK 0x8000 7994 #define DSC_C_DFE_1_CTL_DFE_1_EN_ALIGN 0 7995 #define DSC_C_DFE_1_CTL_DFE_1_EN_BITS 1 7996 #define DSC_C_DFE_1_CTL_DFE_1_EN_SHIFT 15 7997 7998 /* DSC_C :: dfe_1_ctl :: dfe_1_err_sel [14:13] */ 7999 #define DSC_C_DFE_1_CTL_DFE_1_ERR_SEL_MASK 0x6000 8000 #define DSC_C_DFE_1_CTL_DFE_1_ERR_SEL_ALIGN 0 8001 #define DSC_C_DFE_1_CTL_DFE_1_ERR_SEL_BITS 2 8002 #define DSC_C_DFE_1_CTL_DFE_1_ERR_SEL_SHIFT 13 8003 8004 /* DSC_C :: dfe_1_ctl :: dfe_1_gradient_invert [12:12] */ 8005 #define DSC_C_DFE_1_CTL_DFE_1_GRADIENT_INVERT_MASK 0x1000 8006 #define DSC_C_DFE_1_CTL_DFE_1_GRADIENT_INVERT_ALIGN 0 8007 #define DSC_C_DFE_1_CTL_DFE_1_GRADIENT_INVERT_BITS 1 8008 #define DSC_C_DFE_1_CTL_DFE_1_GRADIENT_INVERT_SHIFT 12 8009 8010 /* DSC_C :: dfe_1_ctl :: dfe_1_err_gain [11:10] */ 8011 #define DSC_C_DFE_1_CTL_DFE_1_ERR_GAIN_MASK 0x0c00 8012 #define DSC_C_DFE_1_CTL_DFE_1_ERR_GAIN_ALIGN 0 8013 #define DSC_C_DFE_1_CTL_DFE_1_ERR_GAIN_BITS 2 8014 #define DSC_C_DFE_1_CTL_DFE_1_ERR_GAIN_SHIFT 10 8015 8016 /* DSC_C :: dfe_1_ctl :: dfe_1_inv_m1 [09:09] */ 8017 #define DSC_C_DFE_1_CTL_DFE_1_INV_M1_MASK 0x0200 8018 #define DSC_C_DFE_1_CTL_DFE_1_INV_M1_ALIGN 0 8019 #define DSC_C_DFE_1_CTL_DFE_1_INV_M1_BITS 1 8020 #define DSC_C_DFE_1_CTL_DFE_1_INV_M1_SHIFT 9 8021 8022 /* DSC_C :: dfe_1_ctl :: dfe_1_inv_p1 [08:08] */ 8023 #define DSC_C_DFE_1_CTL_DFE_1_INV_P1_MASK 0x0100 8024 #define DSC_C_DFE_1_CTL_DFE_1_INV_P1_ALIGN 0 8025 #define DSC_C_DFE_1_CTL_DFE_1_INV_P1_BITS 1 8026 #define DSC_C_DFE_1_CTL_DFE_1_INV_P1_SHIFT 8 8027 8028 /* DSC_C :: dfe_1_ctl :: reserved0 [07:02] */ 8029 #define DSC_C_DFE_1_CTL_RESERVED0_MASK 0x00fc 8030 #define DSC_C_DFE_1_CTL_RESERVED0_ALIGN 0 8031 #define DSC_C_DFE_1_CTL_RESERVED0_BITS 6 8032 #define DSC_C_DFE_1_CTL_RESERVED0_SHIFT 2 8033 8034 /* DSC_C :: dfe_1_ctl :: dfe_1_cmn_only [01:01] */ 8035 #define DSC_C_DFE_1_CTL_DFE_1_CMN_ONLY_MASK 0x0002 8036 #define DSC_C_DFE_1_CTL_DFE_1_CMN_ONLY_ALIGN 0 8037 #define DSC_C_DFE_1_CTL_DFE_1_CMN_ONLY_BITS 1 8038 #define DSC_C_DFE_1_CTL_DFE_1_CMN_ONLY_SHIFT 1 8039 8040 /* DSC_C :: dfe_1_ctl :: dfe_1_tap_clr [00:00] */ 8041 #define DSC_C_DFE_1_CTL_DFE_1_TAP_CLR_MASK 0x0001 8042 #define DSC_C_DFE_1_CTL_DFE_1_TAP_CLR_ALIGN 0 8043 #define DSC_C_DFE_1_CTL_DFE_1_TAP_CLR_BITS 1 8044 #define DSC_C_DFE_1_CTL_DFE_1_TAP_CLR_SHIFT 0 8045 8046 8047 /**************************************************************************** 8048 * DSC_C :: dfe_1_pat_ctl 8049 */ 8050 /* DSC_C :: dfe_1_pat_ctl :: reserved0 [15:14] */ 8051 #define DSC_C_DFE_1_PAT_CTL_RESERVED0_MASK 0xc000 8052 #define DSC_C_DFE_1_PAT_CTL_RESERVED0_ALIGN 0 8053 #define DSC_C_DFE_1_PAT_CTL_RESERVED0_BITS 2 8054 #define DSC_C_DFE_1_PAT_CTL_RESERVED0_SHIFT 14 8055 8056 /* DSC_C :: dfe_1_pat_ctl :: dfe_1_pattern_bit_en [13:08] */ 8057 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BIT_EN_MASK 0x3f00 8058 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BIT_EN_ALIGN 0 8059 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BIT_EN_BITS 6 8060 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BIT_EN_SHIFT 8 8061 8062 /* DSC_C :: dfe_1_pat_ctl :: reserved1 [07:06] */ 8063 #define DSC_C_DFE_1_PAT_CTL_RESERVED1_MASK 0x00c0 8064 #define DSC_C_DFE_1_PAT_CTL_RESERVED1_ALIGN 0 8065 #define DSC_C_DFE_1_PAT_CTL_RESERVED1_BITS 2 8066 #define DSC_C_DFE_1_PAT_CTL_RESERVED1_SHIFT 6 8067 8068 /* DSC_C :: dfe_1_pat_ctl :: dfe_1_pattern [05:00] */ 8069 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_MASK 0x003f 8070 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_ALIGN 0 8071 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_BITS 6 8072 #define DSC_C_DFE_1_PAT_CTL_DFE_1_PATTERN_SHIFT 0 8073 8074 8075 /**************************************************************************** 8076 * DSC_C :: dfe_2_ctl 8077 */ 8078 /* DSC_C :: dfe_2_ctl :: dfe_2_en [15:15] */ 8079 #define DSC_C_DFE_2_CTL_DFE_2_EN_MASK 0x8000 8080 #define DSC_C_DFE_2_CTL_DFE_2_EN_ALIGN 0 8081 #define DSC_C_DFE_2_CTL_DFE_2_EN_BITS 1 8082 #define DSC_C_DFE_2_CTL_DFE_2_EN_SHIFT 15 8083 8084 /* DSC_C :: dfe_2_ctl :: dfe_2_err_sel [14:13] */ 8085 #define DSC_C_DFE_2_CTL_DFE_2_ERR_SEL_MASK 0x6000 8086 #define DSC_C_DFE_2_CTL_DFE_2_ERR_SEL_ALIGN 0 8087 #define DSC_C_DFE_2_CTL_DFE_2_ERR_SEL_BITS 2 8088 #define DSC_C_DFE_2_CTL_DFE_2_ERR_SEL_SHIFT 13 8089 8090 /* DSC_C :: dfe_2_ctl :: dfe_2_gradient_invert [12:12] */ 8091 #define DSC_C_DFE_2_CTL_DFE_2_GRADIENT_INVERT_MASK 0x1000 8092 #define DSC_C_DFE_2_CTL_DFE_2_GRADIENT_INVERT_ALIGN 0 8093 #define DSC_C_DFE_2_CTL_DFE_2_GRADIENT_INVERT_BITS 1 8094 #define DSC_C_DFE_2_CTL_DFE_2_GRADIENT_INVERT_SHIFT 12 8095 8096 /* DSC_C :: dfe_2_ctl :: dfe_2_err_gain [11:10] */ 8097 #define DSC_C_DFE_2_CTL_DFE_2_ERR_GAIN_MASK 0x0c00 8098 #define DSC_C_DFE_2_CTL_DFE_2_ERR_GAIN_ALIGN 0 8099 #define DSC_C_DFE_2_CTL_DFE_2_ERR_GAIN_BITS 2 8100 #define DSC_C_DFE_2_CTL_DFE_2_ERR_GAIN_SHIFT 10 8101 8102 /* DSC_C :: dfe_2_ctl :: dfe_2_inv_m1 [09:09] */ 8103 #define DSC_C_DFE_2_CTL_DFE_2_INV_M1_MASK 0x0200 8104 #define DSC_C_DFE_2_CTL_DFE_2_INV_M1_ALIGN 0 8105 #define DSC_C_DFE_2_CTL_DFE_2_INV_M1_BITS 1 8106 #define DSC_C_DFE_2_CTL_DFE_2_INV_M1_SHIFT 9 8107 8108 /* DSC_C :: dfe_2_ctl :: dfe_2_inv_p1 [08:08] */ 8109 #define DSC_C_DFE_2_CTL_DFE_2_INV_P1_MASK 0x0100 8110 #define DSC_C_DFE_2_CTL_DFE_2_INV_P1_ALIGN 0 8111 #define DSC_C_DFE_2_CTL_DFE_2_INV_P1_BITS 1 8112 #define DSC_C_DFE_2_CTL_DFE_2_INV_P1_SHIFT 8 8113 8114 /* DSC_C :: dfe_2_ctl :: reserved0 [07:02] */ 8115 #define DSC_C_DFE_2_CTL_RESERVED0_MASK 0x00fc 8116 #define DSC_C_DFE_2_CTL_RESERVED0_ALIGN 0 8117 #define DSC_C_DFE_2_CTL_RESERVED0_BITS 6 8118 #define DSC_C_DFE_2_CTL_RESERVED0_SHIFT 2 8119 8120 /* DSC_C :: dfe_2_ctl :: dfe_2_cmn_only [01:01] */ 8121 #define DSC_C_DFE_2_CTL_DFE_2_CMN_ONLY_MASK 0x0002 8122 #define DSC_C_DFE_2_CTL_DFE_2_CMN_ONLY_ALIGN 0 8123 #define DSC_C_DFE_2_CTL_DFE_2_CMN_ONLY_BITS 1 8124 #define DSC_C_DFE_2_CTL_DFE_2_CMN_ONLY_SHIFT 1 8125 8126 /* DSC_C :: dfe_2_ctl :: dfe_2_tap_clr [00:00] */ 8127 #define DSC_C_DFE_2_CTL_DFE_2_TAP_CLR_MASK 0x0001 8128 #define DSC_C_DFE_2_CTL_DFE_2_TAP_CLR_ALIGN 0 8129 #define DSC_C_DFE_2_CTL_DFE_2_TAP_CLR_BITS 1 8130 #define DSC_C_DFE_2_CTL_DFE_2_TAP_CLR_SHIFT 0 8131 8132 8133 /**************************************************************************** 8134 * DSC_C :: dfe_2_pat_ctl 8135 */ 8136 /* DSC_C :: dfe_2_pat_ctl :: reserved0 [15:14] */ 8137 #define DSC_C_DFE_2_PAT_CTL_RESERVED0_MASK 0xc000 8138 #define DSC_C_DFE_2_PAT_CTL_RESERVED0_ALIGN 0 8139 #define DSC_C_DFE_2_PAT_CTL_RESERVED0_BITS 2 8140 #define DSC_C_DFE_2_PAT_CTL_RESERVED0_SHIFT 14 8141 8142 /* DSC_C :: dfe_2_pat_ctl :: dfe_2_pattern_bit_en [13:08] */ 8143 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BIT_EN_MASK 0x3f00 8144 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BIT_EN_ALIGN 0 8145 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BIT_EN_BITS 6 8146 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BIT_EN_SHIFT 8 8147 8148 /* DSC_C :: dfe_2_pat_ctl :: reserved1 [07:06] */ 8149 #define DSC_C_DFE_2_PAT_CTL_RESERVED1_MASK 0x00c0 8150 #define DSC_C_DFE_2_PAT_CTL_RESERVED1_ALIGN 0 8151 #define DSC_C_DFE_2_PAT_CTL_RESERVED1_BITS 2 8152 #define DSC_C_DFE_2_PAT_CTL_RESERVED1_SHIFT 6 8153 8154 /* DSC_C :: dfe_2_pat_ctl :: dfe_2_pattern [05:00] */ 8155 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_MASK 0x003f 8156 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_ALIGN 0 8157 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_BITS 6 8158 #define DSC_C_DFE_2_PAT_CTL_DFE_2_PATTERN_SHIFT 0 8159 8160 8161 /**************************************************************************** 8162 * DSC_C :: dfe_3_ctl 8163 */ 8164 /* DSC_C :: dfe_3_ctl :: dfe_3_en [15:15] */ 8165 #define DSC_C_DFE_3_CTL_DFE_3_EN_MASK 0x8000 8166 #define DSC_C_DFE_3_CTL_DFE_3_EN_ALIGN 0 8167 #define DSC_C_DFE_3_CTL_DFE_3_EN_BITS 1 8168 #define DSC_C_DFE_3_CTL_DFE_3_EN_SHIFT 15 8169 8170 /* DSC_C :: dfe_3_ctl :: dfe_3_err_sel [14:13] */ 8171 #define DSC_C_DFE_3_CTL_DFE_3_ERR_SEL_MASK 0x6000 8172 #define DSC_C_DFE_3_CTL_DFE_3_ERR_SEL_ALIGN 0 8173 #define DSC_C_DFE_3_CTL_DFE_3_ERR_SEL_BITS 2 8174 #define DSC_C_DFE_3_CTL_DFE_3_ERR_SEL_SHIFT 13 8175 8176 /* DSC_C :: dfe_3_ctl :: dfe_3_gradient_invert [12:12] */ 8177 #define DSC_C_DFE_3_CTL_DFE_3_GRADIENT_INVERT_MASK 0x1000 8178 #define DSC_C_DFE_3_CTL_DFE_3_GRADIENT_INVERT_ALIGN 0 8179 #define DSC_C_DFE_3_CTL_DFE_3_GRADIENT_INVERT_BITS 1 8180 #define DSC_C_DFE_3_CTL_DFE_3_GRADIENT_INVERT_SHIFT 12 8181 8182 /* DSC_C :: dfe_3_ctl :: dfe_3_err_gain [11:10] */ 8183 #define DSC_C_DFE_3_CTL_DFE_3_ERR_GAIN_MASK 0x0c00 8184 #define DSC_C_DFE_3_CTL_DFE_3_ERR_GAIN_ALIGN 0 8185 #define DSC_C_DFE_3_CTL_DFE_3_ERR_GAIN_BITS 2 8186 #define DSC_C_DFE_3_CTL_DFE_3_ERR_GAIN_SHIFT 10 8187 8188 /* DSC_C :: dfe_3_ctl :: dfe_3_inv_m1 [09:09] */ 8189 #define DSC_C_DFE_3_CTL_DFE_3_INV_M1_MASK 0x0200 8190 #define DSC_C_DFE_3_CTL_DFE_3_INV_M1_ALIGN 0 8191 #define DSC_C_DFE_3_CTL_DFE_3_INV_M1_BITS 1 8192 #define DSC_C_DFE_3_CTL_DFE_3_INV_M1_SHIFT 9 8193 8194 /* DSC_C :: dfe_3_ctl :: dfe_3_inv_p1 [08:08] */ 8195 #define DSC_C_DFE_3_CTL_DFE_3_INV_P1_MASK 0x0100 8196 #define DSC_C_DFE_3_CTL_DFE_3_INV_P1_ALIGN 0 8197 #define DSC_C_DFE_3_CTL_DFE_3_INV_P1_BITS 1 8198 #define DSC_C_DFE_3_CTL_DFE_3_INV_P1_SHIFT 8 8199 8200 /* DSC_C :: dfe_3_ctl :: reserved0 [07:01] */ 8201 #define DSC_C_DFE_3_CTL_RESERVED0_MASK 0x00fe 8202 #define DSC_C_DFE_3_CTL_RESERVED0_ALIGN 0 8203 #define DSC_C_DFE_3_CTL_RESERVED0_BITS 7 8204 #define DSC_C_DFE_3_CTL_RESERVED0_SHIFT 1 8205 8206 /* DSC_C :: dfe_3_ctl :: dfe_3_tap_clr [00:00] */ 8207 #define DSC_C_DFE_3_CTL_DFE_3_TAP_CLR_MASK 0x0001 8208 #define DSC_C_DFE_3_CTL_DFE_3_TAP_CLR_ALIGN 0 8209 #define DSC_C_DFE_3_CTL_DFE_3_TAP_CLR_BITS 1 8210 #define DSC_C_DFE_3_CTL_DFE_3_TAP_CLR_SHIFT 0 8211 8212 8213 /**************************************************************************** 8214 * DSC_C :: dfe_3_pat_ctl 8215 */ 8216 /* DSC_C :: dfe_3_pat_ctl :: reserved0 [15:14] */ 8217 #define DSC_C_DFE_3_PAT_CTL_RESERVED0_MASK 0xc000 8218 #define DSC_C_DFE_3_PAT_CTL_RESERVED0_ALIGN 0 8219 #define DSC_C_DFE_3_PAT_CTL_RESERVED0_BITS 2 8220 #define DSC_C_DFE_3_PAT_CTL_RESERVED0_SHIFT 14 8221 8222 /* DSC_C :: dfe_3_pat_ctl :: dfe_3_pattern_bit_en [13:08] */ 8223 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BIT_EN_MASK 0x3f00 8224 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BIT_EN_ALIGN 0 8225 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BIT_EN_BITS 6 8226 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BIT_EN_SHIFT 8 8227 8228 /* DSC_C :: dfe_3_pat_ctl :: reserved1 [07:06] */ 8229 #define DSC_C_DFE_3_PAT_CTL_RESERVED1_MASK 0x00c0 8230 #define DSC_C_DFE_3_PAT_CTL_RESERVED1_ALIGN 0 8231 #define DSC_C_DFE_3_PAT_CTL_RESERVED1_BITS 2 8232 #define DSC_C_DFE_3_PAT_CTL_RESERVED1_SHIFT 6 8233 8234 /* DSC_C :: dfe_3_pat_ctl :: dfe_3_pattern [05:00] */ 8235 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_MASK 0x003f 8236 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_ALIGN 0 8237 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_BITS 6 8238 #define DSC_C_DFE_3_PAT_CTL_DFE_3_PATTERN_SHIFT 0 8239 8240 8241 /**************************************************************************** 8242 * DSC_C :: dfe_4_ctl 8243 */ 8244 /* DSC_C :: dfe_4_ctl :: dfe_4_en [15:15] */ 8245 #define DSC_C_DFE_4_CTL_DFE_4_EN_MASK 0x8000 8246 #define DSC_C_DFE_4_CTL_DFE_4_EN_ALIGN 0 8247 #define DSC_C_DFE_4_CTL_DFE_4_EN_BITS 1 8248 #define DSC_C_DFE_4_CTL_DFE_4_EN_SHIFT 15 8249 8250 /* DSC_C :: dfe_4_ctl :: dfe_4_err_sel [14:13] */ 8251 #define DSC_C_DFE_4_CTL_DFE_4_ERR_SEL_MASK 0x6000 8252 #define DSC_C_DFE_4_CTL_DFE_4_ERR_SEL_ALIGN 0 8253 #define DSC_C_DFE_4_CTL_DFE_4_ERR_SEL_BITS 2 8254 #define DSC_C_DFE_4_CTL_DFE_4_ERR_SEL_SHIFT 13 8255 8256 /* DSC_C :: dfe_4_ctl :: dfe_4_gradient_invert [12:12] */ 8257 #define DSC_C_DFE_4_CTL_DFE_4_GRADIENT_INVERT_MASK 0x1000 8258 #define DSC_C_DFE_4_CTL_DFE_4_GRADIENT_INVERT_ALIGN 0 8259 #define DSC_C_DFE_4_CTL_DFE_4_GRADIENT_INVERT_BITS 1 8260 #define DSC_C_DFE_4_CTL_DFE_4_GRADIENT_INVERT_SHIFT 12 8261 8262 /* DSC_C :: dfe_4_ctl :: dfe_4_err_gain [11:10] */ 8263 #define DSC_C_DFE_4_CTL_DFE_4_ERR_GAIN_MASK 0x0c00 8264 #define DSC_C_DFE_4_CTL_DFE_4_ERR_GAIN_ALIGN 0 8265 #define DSC_C_DFE_4_CTL_DFE_4_ERR_GAIN_BITS 2 8266 #define DSC_C_DFE_4_CTL_DFE_4_ERR_GAIN_SHIFT 10 8267 8268 /* DSC_C :: dfe_4_ctl :: dfe_4_inv_m1 [09:09] */ 8269 #define DSC_C_DFE_4_CTL_DFE_4_INV_M1_MASK 0x0200 8270 #define DSC_C_DFE_4_CTL_DFE_4_INV_M1_ALIGN 0 8271 #define DSC_C_DFE_4_CTL_DFE_4_INV_M1_BITS 1 8272 #define DSC_C_DFE_4_CTL_DFE_4_INV_M1_SHIFT 9 8273 8274 /* DSC_C :: dfe_4_ctl :: dfe_4_inv_p1 [08:08] */ 8275 #define DSC_C_DFE_4_CTL_DFE_4_INV_P1_MASK 0x0100 8276 #define DSC_C_DFE_4_CTL_DFE_4_INV_P1_ALIGN 0 8277 #define DSC_C_DFE_4_CTL_DFE_4_INV_P1_BITS 1 8278 #define DSC_C_DFE_4_CTL_DFE_4_INV_P1_SHIFT 8 8279 8280 /* DSC_C :: dfe_4_ctl :: reserved0 [07:01] */ 8281 #define DSC_C_DFE_4_CTL_RESERVED0_MASK 0x00fe 8282 #define DSC_C_DFE_4_CTL_RESERVED0_ALIGN 0 8283 #define DSC_C_DFE_4_CTL_RESERVED0_BITS 7 8284 #define DSC_C_DFE_4_CTL_RESERVED0_SHIFT 1 8285 8286 /* DSC_C :: dfe_4_ctl :: dfe_4_tap_clr [00:00] */ 8287 #define DSC_C_DFE_4_CTL_DFE_4_TAP_CLR_MASK 0x0001 8288 #define DSC_C_DFE_4_CTL_DFE_4_TAP_CLR_ALIGN 0 8289 #define DSC_C_DFE_4_CTL_DFE_4_TAP_CLR_BITS 1 8290 #define DSC_C_DFE_4_CTL_DFE_4_TAP_CLR_SHIFT 0 8291 8292 8293 /**************************************************************************** 8294 * DSC_C :: dfe_4_pat_ctl 8295 */ 8296 /* DSC_C :: dfe_4_pat_ctl :: reserved0 [15:14] */ 8297 #define DSC_C_DFE_4_PAT_CTL_RESERVED0_MASK 0xc000 8298 #define DSC_C_DFE_4_PAT_CTL_RESERVED0_ALIGN 0 8299 #define DSC_C_DFE_4_PAT_CTL_RESERVED0_BITS 2 8300 #define DSC_C_DFE_4_PAT_CTL_RESERVED0_SHIFT 14 8301 8302 /* DSC_C :: dfe_4_pat_ctl :: dfe_4_pattern_bit_en [13:08] */ 8303 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BIT_EN_MASK 0x3f00 8304 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BIT_EN_ALIGN 0 8305 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BIT_EN_BITS 6 8306 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BIT_EN_SHIFT 8 8307 8308 /* DSC_C :: dfe_4_pat_ctl :: reserved1 [07:06] */ 8309 #define DSC_C_DFE_4_PAT_CTL_RESERVED1_MASK 0x00c0 8310 #define DSC_C_DFE_4_PAT_CTL_RESERVED1_ALIGN 0 8311 #define DSC_C_DFE_4_PAT_CTL_RESERVED1_BITS 2 8312 #define DSC_C_DFE_4_PAT_CTL_RESERVED1_SHIFT 6 8313 8314 /* DSC_C :: dfe_4_pat_ctl :: dfe_4_pattern [05:00] */ 8315 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_MASK 0x003f 8316 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_ALIGN 0 8317 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_BITS 6 8318 #define DSC_C_DFE_4_PAT_CTL_DFE_4_PATTERN_SHIFT 0 8319 8320 8321 /**************************************************************************** 8322 * DSC_C :: dfe_5_ctl 8323 */ 8324 /* DSC_C :: dfe_5_ctl :: dfe_5_en [15:15] */ 8325 #define DSC_C_DFE_5_CTL_DFE_5_EN_MASK 0x8000 8326 #define DSC_C_DFE_5_CTL_DFE_5_EN_ALIGN 0 8327 #define DSC_C_DFE_5_CTL_DFE_5_EN_BITS 1 8328 #define DSC_C_DFE_5_CTL_DFE_5_EN_SHIFT 15 8329 8330 /* DSC_C :: dfe_5_ctl :: dfe_5_err_sel [14:13] */ 8331 #define DSC_C_DFE_5_CTL_DFE_5_ERR_SEL_MASK 0x6000 8332 #define DSC_C_DFE_5_CTL_DFE_5_ERR_SEL_ALIGN 0 8333 #define DSC_C_DFE_5_CTL_DFE_5_ERR_SEL_BITS 2 8334 #define DSC_C_DFE_5_CTL_DFE_5_ERR_SEL_SHIFT 13 8335 8336 /* DSC_C :: dfe_5_ctl :: dfe_5_gradient_invert [12:12] */ 8337 #define DSC_C_DFE_5_CTL_DFE_5_GRADIENT_INVERT_MASK 0x1000 8338 #define DSC_C_DFE_5_CTL_DFE_5_GRADIENT_INVERT_ALIGN 0 8339 #define DSC_C_DFE_5_CTL_DFE_5_GRADIENT_INVERT_BITS 1 8340 #define DSC_C_DFE_5_CTL_DFE_5_GRADIENT_INVERT_SHIFT 12 8341 8342 /* DSC_C :: dfe_5_ctl :: dfe_5_err_gain [11:10] */ 8343 #define DSC_C_DFE_5_CTL_DFE_5_ERR_GAIN_MASK 0x0c00 8344 #define DSC_C_DFE_5_CTL_DFE_5_ERR_GAIN_ALIGN 0 8345 #define DSC_C_DFE_5_CTL_DFE_5_ERR_GAIN_BITS 2 8346 #define DSC_C_DFE_5_CTL_DFE_5_ERR_GAIN_SHIFT 10 8347 8348 /* DSC_C :: dfe_5_ctl :: dfe_5_inv_m1 [09:09] */ 8349 #define DSC_C_DFE_5_CTL_DFE_5_INV_M1_MASK 0x0200 8350 #define DSC_C_DFE_5_CTL_DFE_5_INV_M1_ALIGN 0 8351 #define DSC_C_DFE_5_CTL_DFE_5_INV_M1_BITS 1 8352 #define DSC_C_DFE_5_CTL_DFE_5_INV_M1_SHIFT 9 8353 8354 /* DSC_C :: dfe_5_ctl :: dfe_5_inv_p1 [08:08] */ 8355 #define DSC_C_DFE_5_CTL_DFE_5_INV_P1_MASK 0x0100 8356 #define DSC_C_DFE_5_CTL_DFE_5_INV_P1_ALIGN 0 8357 #define DSC_C_DFE_5_CTL_DFE_5_INV_P1_BITS 1 8358 #define DSC_C_DFE_5_CTL_DFE_5_INV_P1_SHIFT 8 8359 8360 /* DSC_C :: dfe_5_ctl :: reserved0 [07:01] */ 8361 #define DSC_C_DFE_5_CTL_RESERVED0_MASK 0x00fe 8362 #define DSC_C_DFE_5_CTL_RESERVED0_ALIGN 0 8363 #define DSC_C_DFE_5_CTL_RESERVED0_BITS 7 8364 #define DSC_C_DFE_5_CTL_RESERVED0_SHIFT 1 8365 8366 /* DSC_C :: dfe_5_ctl :: dfe_5_tap_clr [00:00] */ 8367 #define DSC_C_DFE_5_CTL_DFE_5_TAP_CLR_MASK 0x0001 8368 #define DSC_C_DFE_5_CTL_DFE_5_TAP_CLR_ALIGN 0 8369 #define DSC_C_DFE_5_CTL_DFE_5_TAP_CLR_BITS 1 8370 #define DSC_C_DFE_5_CTL_DFE_5_TAP_CLR_SHIFT 0 8371 8372 8373 /**************************************************************************** 8374 * DSC_C :: dfe_5_pat_ctl 8375 */ 8376 /* DSC_C :: dfe_5_pat_ctl :: reserved0 [15:14] */ 8377 #define DSC_C_DFE_5_PAT_CTL_RESERVED0_MASK 0xc000 8378 #define DSC_C_DFE_5_PAT_CTL_RESERVED0_ALIGN 0 8379 #define DSC_C_DFE_5_PAT_CTL_RESERVED0_BITS 2 8380 #define DSC_C_DFE_5_PAT_CTL_RESERVED0_SHIFT 14 8381 8382 /* DSC_C :: dfe_5_pat_ctl :: dfe_5_pattern_bit_en [13:08] */ 8383 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BIT_EN_MASK 0x3f00 8384 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BIT_EN_ALIGN 0 8385 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BIT_EN_BITS 6 8386 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BIT_EN_SHIFT 8 8387 8388 /* DSC_C :: dfe_5_pat_ctl :: reserved1 [07:06] */ 8389 #define DSC_C_DFE_5_PAT_CTL_RESERVED1_MASK 0x00c0 8390 #define DSC_C_DFE_5_PAT_CTL_RESERVED1_ALIGN 0 8391 #define DSC_C_DFE_5_PAT_CTL_RESERVED1_BITS 2 8392 #define DSC_C_DFE_5_PAT_CTL_RESERVED1_SHIFT 6 8393 8394 /* DSC_C :: dfe_5_pat_ctl :: dfe_5_pattern [05:00] */ 8395 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_MASK 0x003f 8396 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_ALIGN 0 8397 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_BITS 6 8398 #define DSC_C_DFE_5_PAT_CTL_DFE_5_PATTERN_SHIFT 0 8399 8400 8401 /**************************************************************************** 8402 * DSC_C :: dfe_vga_override 8403 */ 8404 /* DSC_C :: dfe_vga_override :: dfe_vga_write_en [15:15] */ 8405 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_EN_MASK 0x8000 8406 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_EN_ALIGN 0 8407 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_EN_BITS 1 8408 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_EN_SHIFT 15 8409 8410 /* DSC_C :: dfe_vga_override :: reserved0 [14:14] */ 8411 #define DSC_C_DFE_VGA_OVERRIDE_RESERVED0_MASK 0x4000 8412 #define DSC_C_DFE_VGA_OVERRIDE_RESERVED0_ALIGN 0 8413 #define DSC_C_DFE_VGA_OVERRIDE_RESERVED0_BITS 1 8414 #define DSC_C_DFE_VGA_OVERRIDE_RESERVED0_SHIFT 14 8415 8416 /* DSC_C :: dfe_vga_override :: dfe_vga_write_tapsel [13:09] */ 8417 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_TAPSEL_MASK 0x3e00 8418 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_TAPSEL_ALIGN 0 8419 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_TAPSEL_BITS 5 8420 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_TAPSEL_SHIFT 9 8421 8422 /* DSC_C :: dfe_vga_override :: dfe_vga_write_val [08:00] */ 8423 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_VAL_MASK 0x01ff 8424 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_VAL_ALIGN 0 8425 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_VAL_BITS 9 8426 #define DSC_C_DFE_VGA_OVERRIDE_DFE_VGA_WRITE_VAL_SHIFT 0 8427 8428 8429 /**************************************************************************** 8430 * DSC_C :: vga_ctl 8431 */ 8432 /* DSC_C :: vga_ctl :: vga_en [15:15] */ 8433 #define DSC_C_VGA_CTL_VGA_EN_MASK 0x8000 8434 #define DSC_C_VGA_CTL_VGA_EN_ALIGN 0 8435 #define DSC_C_VGA_CTL_VGA_EN_BITS 1 8436 #define DSC_C_VGA_CTL_VGA_EN_SHIFT 15 8437 8438 /* DSC_C :: vga_ctl :: vga_err_sel [14:13] */ 8439 #define DSC_C_VGA_CTL_VGA_ERR_SEL_MASK 0x6000 8440 #define DSC_C_VGA_CTL_VGA_ERR_SEL_ALIGN 0 8441 #define DSC_C_VGA_CTL_VGA_ERR_SEL_BITS 2 8442 #define DSC_C_VGA_CTL_VGA_ERR_SEL_SHIFT 13 8443 8444 /* DSC_C :: vga_ctl :: vga_gradient_invert [12:12] */ 8445 #define DSC_C_VGA_CTL_VGA_GRADIENT_INVERT_MASK 0x1000 8446 #define DSC_C_VGA_CTL_VGA_GRADIENT_INVERT_ALIGN 0 8447 #define DSC_C_VGA_CTL_VGA_GRADIENT_INVERT_BITS 1 8448 #define DSC_C_VGA_CTL_VGA_GRADIENT_INVERT_SHIFT 12 8449 8450 /* DSC_C :: vga_ctl :: vga_err_gain [11:10] */ 8451 #define DSC_C_VGA_CTL_VGA_ERR_GAIN_MASK 0x0c00 8452 #define DSC_C_VGA_CTL_VGA_ERR_GAIN_ALIGN 0 8453 #define DSC_C_VGA_CTL_VGA_ERR_GAIN_BITS 2 8454 #define DSC_C_VGA_CTL_VGA_ERR_GAIN_SHIFT 10 8455 8456 /* DSC_C :: vga_ctl :: vga_inv_m1 [09:09] */ 8457 #define DSC_C_VGA_CTL_VGA_INV_M1_MASK 0x0200 8458 #define DSC_C_VGA_CTL_VGA_INV_M1_ALIGN 0 8459 #define DSC_C_VGA_CTL_VGA_INV_M1_BITS 1 8460 #define DSC_C_VGA_CTL_VGA_INV_M1_SHIFT 9 8461 8462 /* DSC_C :: vga_ctl :: vga_inv_p1 [08:08] */ 8463 #define DSC_C_VGA_CTL_VGA_INV_P1_MASK 0x0100 8464 #define DSC_C_VGA_CTL_VGA_INV_P1_ALIGN 0 8465 #define DSC_C_VGA_CTL_VGA_INV_P1_BITS 1 8466 #define DSC_C_VGA_CTL_VGA_INV_P1_SHIFT 8 8467 8468 /* DSC_C :: vga_ctl :: vga_update_gain [07:06] */ 8469 #define DSC_C_VGA_CTL_VGA_UPDATE_GAIN_MASK 0x00c0 8470 #define DSC_C_VGA_CTL_VGA_UPDATE_GAIN_ALIGN 0 8471 #define DSC_C_VGA_CTL_VGA_UPDATE_GAIN_BITS 2 8472 #define DSC_C_VGA_CTL_VGA_UPDATE_GAIN_SHIFT 6 8473 8474 /* DSC_C :: vga_ctl :: reserved0 [05:04] */ 8475 #define DSC_C_VGA_CTL_RESERVED0_MASK 0x0030 8476 #define DSC_C_VGA_CTL_RESERVED0_ALIGN 0 8477 #define DSC_C_VGA_CTL_RESERVED0_BITS 2 8478 #define DSC_C_VGA_CTL_RESERVED0_SHIFT 4 8479 8480 /* DSC_C :: vga_ctl :: vga_update_style [03:02] */ 8481 #define DSC_C_VGA_CTL_VGA_UPDATE_STYLE_MASK 0x000c 8482 #define DSC_C_VGA_CTL_VGA_UPDATE_STYLE_ALIGN 0 8483 #define DSC_C_VGA_CTL_VGA_UPDATE_STYLE_BITS 2 8484 #define DSC_C_VGA_CTL_VGA_UPDATE_STYLE_SHIFT 2 8485 8486 /* DSC_C :: vga_ctl :: vga_acc_hys_en [01:01] */ 8487 #define DSC_C_VGA_CTL_VGA_ACC_HYS_EN_MASK 0x0002 8488 #define DSC_C_VGA_CTL_VGA_ACC_HYS_EN_ALIGN 0 8489 #define DSC_C_VGA_CTL_VGA_ACC_HYS_EN_BITS 1 8490 #define DSC_C_VGA_CTL_VGA_ACC_HYS_EN_SHIFT 1 8491 8492 /* DSC_C :: vga_ctl :: vga_tap_clr [00:00] */ 8493 #define DSC_C_VGA_CTL_VGA_TAP_CLR_MASK 0x0001 8494 #define DSC_C_VGA_CTL_VGA_TAP_CLR_ALIGN 0 8495 #define DSC_C_VGA_CTL_VGA_TAP_CLR_BITS 1 8496 #define DSC_C_VGA_CTL_VGA_TAP_CLR_SHIFT 0 8497 8498 8499 /**************************************************************************** 8500 * DSC_C :: vga_pat_eyediag_ctl 8501 */ 8502 /* DSC_C :: vga_pat_eyediag_ctl :: p1_eyediag_en [15:15] */ 8503 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_EN_MASK 0x8000 8504 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_EN_ALIGN 0 8505 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_EN_BITS 1 8506 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_EN_SHIFT 15 8507 8508 /* DSC_C :: vga_pat_eyediag_ctl :: p1_eyediag_clr [14:14] */ 8509 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_CLR_MASK 0x4000 8510 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_CLR_ALIGN 0 8511 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_CLR_BITS 1 8512 #define DSC_C_VGA_PAT_EYEDIAG_CTL_P1_EYEDIAG_CLR_SHIFT 14 8513 8514 /* DSC_C :: vga_pat_eyediag_ctl :: reserved0 [13:08] */ 8515 #define DSC_C_VGA_PAT_EYEDIAG_CTL_RESERVED0_MASK 0x3f00 8516 #define DSC_C_VGA_PAT_EYEDIAG_CTL_RESERVED0_ALIGN 0 8517 #define DSC_C_VGA_PAT_EYEDIAG_CTL_RESERVED0_BITS 6 8518 #define DSC_C_VGA_PAT_EYEDIAG_CTL_RESERVED0_SHIFT 8 8519 8520 /* DSC_C :: vga_pat_eyediag_ctl :: vga_pattern_bit_en [07:04] */ 8521 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BIT_EN_MASK 0x00f0 8522 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BIT_EN_ALIGN 0 8523 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BIT_EN_BITS 4 8524 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BIT_EN_SHIFT 4 8525 8526 /* DSC_C :: vga_pat_eyediag_ctl :: vga_pattern [03:00] */ 8527 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_MASK 0x000f 8528 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_ALIGN 0 8529 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_BITS 4 8530 #define DSC_C_VGA_PAT_EYEDIAG_CTL_VGA_PATTERN_SHIFT 0 8531 8532 8533 /**************************************************************************** 8534 * merlin_gallardo_dsc_blk_DSC_D 8535 */ 8536 /**************************************************************************** 8537 * DSC_D :: trnsum_ctl_1 8538 */ 8539 /* DSC_D :: trnsum_ctl_1 :: trnsum_en [15:15] */ 8540 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EN_MASK 0x8000 8541 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EN_ALIGN 0 8542 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EN_BITS 1 8543 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EN_SHIFT 15 8544 8545 /* DSC_D :: trnsum_ctl_1 :: trnsum_err_sel [14:12] */ 8546 #define DSC_D_TRNSUM_CTL_1_TRNSUM_ERR_SEL_MASK 0x7000 8547 #define DSC_D_TRNSUM_CTL_1_TRNSUM_ERR_SEL_ALIGN 0 8548 #define DSC_D_TRNSUM_CTL_1_TRNSUM_ERR_SEL_BITS 3 8549 #define DSC_D_TRNSUM_CTL_1_TRNSUM_ERR_SEL_SHIFT 12 8550 8551 /* DSC_D :: trnsum_ctl_1 :: trnsum_random_tapsel_disable [11:11] */ 8552 #define DSC_D_TRNSUM_CTL_1_TRNSUM_RANDOM_TAPSEL_DISABLE_MASK 0x0800 8553 #define DSC_D_TRNSUM_CTL_1_TRNSUM_RANDOM_TAPSEL_DISABLE_ALIGN 0 8554 #define DSC_D_TRNSUM_CTL_1_TRNSUM_RANDOM_TAPSEL_DISABLE_BITS 1 8555 #define DSC_D_TRNSUM_CTL_1_TRNSUM_RANDOM_TAPSEL_DISABLE_SHIFT 11 8556 8557 /* DSC_D :: trnsum_ctl_1 :: trnsum_inv_pattern_en [10:10] */ 8558 #define DSC_D_TRNSUM_CTL_1_TRNSUM_INV_PATTERN_EN_MASK 0x0400 8559 #define DSC_D_TRNSUM_CTL_1_TRNSUM_INV_PATTERN_EN_ALIGN 0 8560 #define DSC_D_TRNSUM_CTL_1_TRNSUM_INV_PATTERN_EN_BITS 1 8561 #define DSC_D_TRNSUM_CTL_1_TRNSUM_INV_PATTERN_EN_SHIFT 10 8562 8563 /* DSC_D :: trnsum_ctl_1 :: trnsum_pattern_full_check_off [09:09] */ 8564 #define DSC_D_TRNSUM_CTL_1_TRNSUM_PATTERN_FULL_CHECK_OFF_MASK 0x0200 8565 #define DSC_D_TRNSUM_CTL_1_TRNSUM_PATTERN_FULL_CHECK_OFF_ALIGN 0 8566 #define DSC_D_TRNSUM_CTL_1_TRNSUM_PATTERN_FULL_CHECK_OFF_BITS 1 8567 #define DSC_D_TRNSUM_CTL_1_TRNSUM_PATTERN_FULL_CHECK_OFF_SHIFT 9 8568 8569 /* DSC_D :: trnsum_ctl_1 :: reserved0 [08:08] */ 8570 #define DSC_D_TRNSUM_CTL_1_RESERVED0_MASK 0x0100 8571 #define DSC_D_TRNSUM_CTL_1_RESERVED0_ALIGN 0 8572 #define DSC_D_TRNSUM_CTL_1_RESERVED0_BITS 1 8573 #define DSC_D_TRNSUM_CTL_1_RESERVED0_SHIFT 8 8574 8575 /* DSC_D :: trnsum_ctl_1 :: trnsum_gain [07:06] */ 8576 #define DSC_D_TRNSUM_CTL_1_TRNSUM_GAIN_MASK 0x00c0 8577 #define DSC_D_TRNSUM_CTL_1_TRNSUM_GAIN_ALIGN 0 8578 #define DSC_D_TRNSUM_CTL_1_TRNSUM_GAIN_BITS 2 8579 #define DSC_D_TRNSUM_CTL_1_TRNSUM_GAIN_SHIFT 6 8580 8581 /* DSC_D :: trnsum_ctl_1 :: trnsum_eye_closure_en [05:05] */ 8582 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EYE_CLOSURE_EN_MASK 0x0020 8583 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EYE_CLOSURE_EN_ALIGN 0 8584 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EYE_CLOSURE_EN_BITS 1 8585 #define DSC_D_TRNSUM_CTL_1_TRNSUM_EYE_CLOSURE_EN_SHIFT 5 8586 8587 /* DSC_D :: trnsum_ctl_1 :: cdr_qphase_mult_en [04:04] */ 8588 #define DSC_D_TRNSUM_CTL_1_CDR_QPHASE_MULT_EN_MASK 0x0010 8589 #define DSC_D_TRNSUM_CTL_1_CDR_QPHASE_MULT_EN_ALIGN 0 8590 #define DSC_D_TRNSUM_CTL_1_CDR_QPHASE_MULT_EN_BITS 1 8591 #define DSC_D_TRNSUM_CTL_1_CDR_QPHASE_MULT_EN_SHIFT 4 8592 8593 /* DSC_D :: trnsum_ctl_1 :: trnsum_tap_range_sel [03:02] */ 8594 #define DSC_D_TRNSUM_CTL_1_TRNSUM_TAP_RANGE_SEL_MASK 0x000c 8595 #define DSC_D_TRNSUM_CTL_1_TRNSUM_TAP_RANGE_SEL_ALIGN 0 8596 #define DSC_D_TRNSUM_CTL_1_TRNSUM_TAP_RANGE_SEL_BITS 2 8597 #define DSC_D_TRNSUM_CTL_1_TRNSUM_TAP_RANGE_SEL_SHIFT 2 8598 8599 /* DSC_D :: trnsum_ctl_1 :: reserved1 [01:00] */ 8600 #define DSC_D_TRNSUM_CTL_1_RESERVED1_MASK 0x0003 8601 #define DSC_D_TRNSUM_CTL_1_RESERVED1_ALIGN 0 8602 #define DSC_D_TRNSUM_CTL_1_RESERVED1_BITS 2 8603 #define DSC_D_TRNSUM_CTL_1_RESERVED1_SHIFT 0 8604 8605 8606 /**************************************************************************** 8607 * DSC_D :: trnsum_ctl_2 8608 */ 8609 /* DSC_D :: trnsum_ctl_2 :: trnsum_pattern [15:08] */ 8610 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_MASK 0xff00 8611 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_ALIGN 0 8612 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BITS 8 8613 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_SHIFT 8 8614 8615 /* DSC_D :: trnsum_ctl_2 :: trnsum_pattern_bit_en [07:00] */ 8616 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BIT_EN_MASK 0x00ff 8617 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BIT_EN_ALIGN 0 8618 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BIT_EN_BITS 8 8619 #define DSC_D_TRNSUM_CTL_2_TRNSUM_PATTERN_BIT_EN_SHIFT 0 8620 8621 8622 /**************************************************************************** 8623 * DSC_D :: trnsum_ctl_3 8624 */ 8625 /* DSC_D :: trnsum_ctl_3 :: trnsum_tap_en [15:08] */ 8626 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_EN_MASK 0xff00 8627 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_EN_ALIGN 0 8628 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_EN_BITS 8 8629 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_EN_SHIFT 8 8630 8631 /* DSC_D :: trnsum_ctl_3 :: trnsum_tap_sign [07:00] */ 8632 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_SIGN_MASK 0x00ff 8633 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_SIGN_ALIGN 0 8634 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_SIGN_BITS 8 8635 #define DSC_D_TRNSUM_CTL_3_TRNSUM_TAP_SIGN_SHIFT 0 8636 8637 8638 /**************************************************************************** 8639 * DSC_D :: trnsum_ctl_4 8640 */ 8641 /* DSC_D :: trnsum_ctl_4 :: tdr_trnsum_en [15:15] */ 8642 #define DSC_D_TRNSUM_CTL_4_TDR_TRNSUM_EN_MASK 0x8000 8643 #define DSC_D_TRNSUM_CTL_4_TDR_TRNSUM_EN_ALIGN 0 8644 #define DSC_D_TRNSUM_CTL_4_TDR_TRNSUM_EN_BITS 1 8645 #define DSC_D_TRNSUM_CTL_4_TDR_TRNSUM_EN_SHIFT 15 8646 8647 /* DSC_D :: trnsum_ctl_4 :: tdr_cycle_bin [14:11] */ 8648 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_BIN_MASK 0x7800 8649 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_BIN_ALIGN 0 8650 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_BIN_BITS 4 8651 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_BIN_SHIFT 11 8652 8653 /* DSC_D :: trnsum_ctl_4 :: tdr_cycle_sel [10:07] */ 8654 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_SEL_MASK 0x0780 8655 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_SEL_ALIGN 0 8656 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_SEL_BITS 4 8657 #define DSC_D_TRNSUM_CTL_4_TDR_CYCLE_SEL_SHIFT 7 8658 8659 /* DSC_D :: trnsum_ctl_4 :: tdr_bit_sel [06:02] */ 8660 #define DSC_D_TRNSUM_CTL_4_TDR_BIT_SEL_MASK 0x007c 8661 #define DSC_D_TRNSUM_CTL_4_TDR_BIT_SEL_ALIGN 0 8662 #define DSC_D_TRNSUM_CTL_4_TDR_BIT_SEL_BITS 5 8663 #define DSC_D_TRNSUM_CTL_4_TDR_BIT_SEL_SHIFT 2 8664 8665 /* DSC_D :: trnsum_ctl_4 :: trnsum_unsigned_flip [01:01] */ 8666 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_FLIP_MASK 0x0002 8667 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_FLIP_ALIGN 0 8668 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_FLIP_BITS 1 8669 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_FLIP_SHIFT 1 8670 8671 /* DSC_D :: trnsum_ctl_4 :: trnsum_unsigned_corr [00:00] */ 8672 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_CORR_MASK 0x0001 8673 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_CORR_ALIGN 0 8674 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_CORR_BITS 1 8675 #define DSC_D_TRNSUM_CTL_4_TRNSUM_UNSIGNED_CORR_SHIFT 0 8676 8677 8678 /**************************************************************************** 8679 * DSC_D :: trnsum_sts_1 8680 */ 8681 /* DSC_D :: trnsum_sts_1 :: trnsum_e_high [15:00] */ 8682 #define DSC_D_TRNSUM_STS_1_TRNSUM_E_HIGH_MASK 0xffff 8683 #define DSC_D_TRNSUM_STS_1_TRNSUM_E_HIGH_ALIGN 0 8684 #define DSC_D_TRNSUM_STS_1_TRNSUM_E_HIGH_BITS 16 8685 #define DSC_D_TRNSUM_STS_1_TRNSUM_E_HIGH_SHIFT 0 8686 8687 8688 /**************************************************************************** 8689 * DSC_D :: trnsum_sts_2 8690 */ 8691 /* DSC_D :: trnsum_sts_2 :: reserved0 [15:08] */ 8692 #define DSC_D_TRNSUM_STS_2_RESERVED0_MASK 0xff00 8693 #define DSC_D_TRNSUM_STS_2_RESERVED0_ALIGN 0 8694 #define DSC_D_TRNSUM_STS_2_RESERVED0_BITS 8 8695 #define DSC_D_TRNSUM_STS_2_RESERVED0_SHIFT 8 8696 8697 /* DSC_D :: trnsum_sts_2 :: trnsum_e_low [07:00] */ 8698 #define DSC_D_TRNSUM_STS_2_TRNSUM_E_LOW_MASK 0x00ff 8699 #define DSC_D_TRNSUM_STS_2_TRNSUM_E_LOW_ALIGN 0 8700 #define DSC_D_TRNSUM_STS_2_TRNSUM_E_LOW_BITS 8 8701 #define DSC_D_TRNSUM_STS_2_TRNSUM_E_LOW_SHIFT 0 8702 8703 8704 /**************************************************************************** 8705 * DSC_D :: trnsum_sts_3 8706 */ 8707 /* DSC_D :: trnsum_sts_3 :: trnsum_o_high [15:00] */ 8708 #define DSC_D_TRNSUM_STS_3_TRNSUM_O_HIGH_MASK 0xffff 8709 #define DSC_D_TRNSUM_STS_3_TRNSUM_O_HIGH_ALIGN 0 8710 #define DSC_D_TRNSUM_STS_3_TRNSUM_O_HIGH_BITS 16 8711 #define DSC_D_TRNSUM_STS_3_TRNSUM_O_HIGH_SHIFT 0 8712 8713 8714 /**************************************************************************** 8715 * DSC_D :: trnsum_sts_4 8716 */ 8717 /* DSC_D :: trnsum_sts_4 :: reserved0 [15:08] */ 8718 #define DSC_D_TRNSUM_STS_4_RESERVED0_MASK 0xff00 8719 #define DSC_D_TRNSUM_STS_4_RESERVED0_ALIGN 0 8720 #define DSC_D_TRNSUM_STS_4_RESERVED0_BITS 8 8721 #define DSC_D_TRNSUM_STS_4_RESERVED0_SHIFT 8 8722 8723 /* DSC_D :: trnsum_sts_4 :: trnsum_o_low [07:00] */ 8724 #define DSC_D_TRNSUM_STS_4_TRNSUM_O_LOW_MASK 0x00ff 8725 #define DSC_D_TRNSUM_STS_4_TRNSUM_O_LOW_ALIGN 0 8726 #define DSC_D_TRNSUM_STS_4_TRNSUM_O_LOW_BITS 8 8727 #define DSC_D_TRNSUM_STS_4_TRNSUM_O_LOW_SHIFT 0 8728 8729 8730 /**************************************************************************** 8731 * DSC_D :: trnsum_sts_5 8732 */ 8733 /* DSC_D :: trnsum_sts_5 :: trnsum_high [15:00] */ 8734 #define DSC_D_TRNSUM_STS_5_TRNSUM_HIGH_MASK 0xffff 8735 #define DSC_D_TRNSUM_STS_5_TRNSUM_HIGH_ALIGN 0 8736 #define DSC_D_TRNSUM_STS_5_TRNSUM_HIGH_BITS 16 8737 #define DSC_D_TRNSUM_STS_5_TRNSUM_HIGH_SHIFT 0 8738 8739 8740 /**************************************************************************** 8741 * DSC_D :: trnsum_sts_6 8742 */ 8743 /* DSC_D :: trnsum_sts_6 :: reserved0 [15:10] */ 8744 #define DSC_D_TRNSUM_STS_6_RESERVED0_MASK 0xfc00 8745 #define DSC_D_TRNSUM_STS_6_RESERVED0_ALIGN 0 8746 #define DSC_D_TRNSUM_STS_6_RESERVED0_BITS 6 8747 #define DSC_D_TRNSUM_STS_6_RESERVED0_SHIFT 10 8748 8749 /* DSC_D :: trnsum_sts_6 :: trnsum_low [09:00] */ 8750 #define DSC_D_TRNSUM_STS_6_TRNSUM_LOW_MASK 0x03ff 8751 #define DSC_D_TRNSUM_STS_6_TRNSUM_LOW_ALIGN 0 8752 #define DSC_D_TRNSUM_STS_6_TRNSUM_LOW_BITS 10 8753 #define DSC_D_TRNSUM_STS_6_TRNSUM_LOW_SHIFT 0 8754 8755 8756 /**************************************************************************** 8757 * DSC_D :: vga_p1eyediag_sts 8758 */ 8759 /* DSC_D :: vga_p1eyediag_sts :: reserved0 [15:14] */ 8760 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED0_MASK 0xc000 8761 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED0_ALIGN 0 8762 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED0_BITS 2 8763 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED0_SHIFT 14 8764 8765 /* DSC_D :: vga_p1eyediag_sts :: p1_eyediag_bin [13:08] */ 8766 #define DSC_D_VGA_P1EYEDIAG_STS_P1_EYEDIAG_BIN_MASK 0x3f00 8767 #define DSC_D_VGA_P1EYEDIAG_STS_P1_EYEDIAG_BIN_ALIGN 0 8768 #define DSC_D_VGA_P1EYEDIAG_STS_P1_EYEDIAG_BIN_BITS 6 8769 #define DSC_D_VGA_P1EYEDIAG_STS_P1_EYEDIAG_BIN_SHIFT 8 8770 8771 /* DSC_D :: vga_p1eyediag_sts :: reserved1 [07:06] */ 8772 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED1_MASK 0x00c0 8773 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED1_ALIGN 0 8774 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED1_BITS 2 8775 #define DSC_D_VGA_P1EYEDIAG_STS_RESERVED1_SHIFT 6 8776 8777 /* DSC_D :: vga_p1eyediag_sts :: vga_bin [05:00] */ 8778 #define DSC_D_VGA_P1EYEDIAG_STS_VGA_BIN_MASK 0x003f 8779 #define DSC_D_VGA_P1EYEDIAG_STS_VGA_BIN_ALIGN 0 8780 #define DSC_D_VGA_P1EYEDIAG_STS_VGA_BIN_BITS 6 8781 #define DSC_D_VGA_P1EYEDIAG_STS_VGA_BIN_SHIFT 0 8782 8783 8784 /**************************************************************************** 8785 * DSC_D :: dfe_1_sts 8786 */ 8787 /* DSC_D :: dfe_1_sts :: dfe_1_wants_negative [15:15] */ 8788 #define DSC_D_DFE_1_STS_DFE_1_WANTS_NEGATIVE_MASK 0x8000 8789 #define DSC_D_DFE_1_STS_DFE_1_WANTS_NEGATIVE_ALIGN 0 8790 #define DSC_D_DFE_1_STS_DFE_1_WANTS_NEGATIVE_BITS 1 8791 #define DSC_D_DFE_1_STS_DFE_1_WANTS_NEGATIVE_SHIFT 15 8792 8793 /* DSC_D :: dfe_1_sts :: reserved0 [14:14] */ 8794 #define DSC_D_DFE_1_STS_RESERVED0_MASK 0x4000 8795 #define DSC_D_DFE_1_STS_RESERVED0_ALIGN 0 8796 #define DSC_D_DFE_1_STS_RESERVED0_BITS 1 8797 #define DSC_D_DFE_1_STS_RESERVED0_SHIFT 14 8798 8799 /* DSC_D :: dfe_1_sts :: dfe_1_e [13:11] */ 8800 #define DSC_D_DFE_1_STS_DFE_1_E_MASK 0x3800 8801 #define DSC_D_DFE_1_STS_DFE_1_E_ALIGN 0 8802 #define DSC_D_DFE_1_STS_DFE_1_E_BITS 3 8803 #define DSC_D_DFE_1_STS_DFE_1_E_SHIFT 11 8804 8805 /* DSC_D :: dfe_1_sts :: dfe_1_o [10:08] */ 8806 #define DSC_D_DFE_1_STS_DFE_1_O_MASK 0x0700 8807 #define DSC_D_DFE_1_STS_DFE_1_O_ALIGN 0 8808 #define DSC_D_DFE_1_STS_DFE_1_O_BITS 3 8809 #define DSC_D_DFE_1_STS_DFE_1_O_SHIFT 8 8810 8811 /* DSC_D :: dfe_1_sts :: reserved1 [07:06] */ 8812 #define DSC_D_DFE_1_STS_RESERVED1_MASK 0x00c0 8813 #define DSC_D_DFE_1_STS_RESERVED1_ALIGN 0 8814 #define DSC_D_DFE_1_STS_RESERVED1_BITS 2 8815 #define DSC_D_DFE_1_STS_RESERVED1_SHIFT 6 8816 8817 /* DSC_D :: dfe_1_sts :: dfe_1_cmn [05:00] */ 8818 #define DSC_D_DFE_1_STS_DFE_1_CMN_MASK 0x003f 8819 #define DSC_D_DFE_1_STS_DFE_1_CMN_ALIGN 0 8820 #define DSC_D_DFE_1_STS_DFE_1_CMN_BITS 6 8821 #define DSC_D_DFE_1_STS_DFE_1_CMN_SHIFT 0 8822 8823 8824 /**************************************************************************** 8825 * DSC_D :: dfe_2_sts 8826 */ 8827 /* DSC_D :: dfe_2_sts :: dfe_2_wants_negative [15:15] */ 8828 #define DSC_D_DFE_2_STS_DFE_2_WANTS_NEGATIVE_MASK 0x8000 8829 #define DSC_D_DFE_2_STS_DFE_2_WANTS_NEGATIVE_ALIGN 0 8830 #define DSC_D_DFE_2_STS_DFE_2_WANTS_NEGATIVE_BITS 1 8831 #define DSC_D_DFE_2_STS_DFE_2_WANTS_NEGATIVE_SHIFT 15 8832 8833 /* DSC_D :: dfe_2_sts :: reserved0 [14:14] */ 8834 #define DSC_D_DFE_2_STS_RESERVED0_MASK 0x4000 8835 #define DSC_D_DFE_2_STS_RESERVED0_ALIGN 0 8836 #define DSC_D_DFE_2_STS_RESERVED0_BITS 1 8837 #define DSC_D_DFE_2_STS_RESERVED0_SHIFT 14 8838 8839 /* DSC_D :: dfe_2_sts :: dfe_2_e [13:11] */ 8840 #define DSC_D_DFE_2_STS_DFE_2_E_MASK 0x3800 8841 #define DSC_D_DFE_2_STS_DFE_2_E_ALIGN 0 8842 #define DSC_D_DFE_2_STS_DFE_2_E_BITS 3 8843 #define DSC_D_DFE_2_STS_DFE_2_E_SHIFT 11 8844 8845 /* DSC_D :: dfe_2_sts :: dfe_2_o [10:08] */ 8846 #define DSC_D_DFE_2_STS_DFE_2_O_MASK 0x0700 8847 #define DSC_D_DFE_2_STS_DFE_2_O_ALIGN 0 8848 #define DSC_D_DFE_2_STS_DFE_2_O_BITS 3 8849 #define DSC_D_DFE_2_STS_DFE_2_O_SHIFT 8 8850 8851 /* DSC_D :: dfe_2_sts :: reserved1 [07:07] */ 8852 #define DSC_D_DFE_2_STS_RESERVED1_MASK 0x0080 8853 #define DSC_D_DFE_2_STS_RESERVED1_ALIGN 0 8854 #define DSC_D_DFE_2_STS_RESERVED1_BITS 1 8855 #define DSC_D_DFE_2_STS_RESERVED1_SHIFT 7 8856 8857 /* DSC_D :: dfe_2_sts :: dfe_2_se [06:06] */ 8858 #define DSC_D_DFE_2_STS_DFE_2_SE_MASK 0x0040 8859 #define DSC_D_DFE_2_STS_DFE_2_SE_ALIGN 0 8860 #define DSC_D_DFE_2_STS_DFE_2_SE_BITS 1 8861 #define DSC_D_DFE_2_STS_DFE_2_SE_SHIFT 6 8862 8863 /* DSC_D :: dfe_2_sts :: dfe_2_so [05:05] */ 8864 #define DSC_D_DFE_2_STS_DFE_2_SO_MASK 0x0020 8865 #define DSC_D_DFE_2_STS_DFE_2_SO_ALIGN 0 8866 #define DSC_D_DFE_2_STS_DFE_2_SO_BITS 1 8867 #define DSC_D_DFE_2_STS_DFE_2_SO_SHIFT 5 8868 8869 /* DSC_D :: dfe_2_sts :: dfe_2_cmn [04:00] */ 8870 #define DSC_D_DFE_2_STS_DFE_2_CMN_MASK 0x001f 8871 #define DSC_D_DFE_2_STS_DFE_2_CMN_ALIGN 0 8872 #define DSC_D_DFE_2_STS_DFE_2_CMN_BITS 5 8873 #define DSC_D_DFE_2_STS_DFE_2_CMN_SHIFT 0 8874 8875 8876 /**************************************************************************** 8877 * DSC_D :: dfe_3_4_5_sts 8878 */ 8879 /* DSC_D :: dfe_3_4_5_sts :: dfe_5_cmn [15:11] */ 8880 #define DSC_D_DFE_3_4_5_STS_DFE_5_CMN_MASK 0xf800 8881 #define DSC_D_DFE_3_4_5_STS_DFE_5_CMN_ALIGN 0 8882 #define DSC_D_DFE_3_4_5_STS_DFE_5_CMN_BITS 5 8883 #define DSC_D_DFE_3_4_5_STS_DFE_5_CMN_SHIFT 11 8884 8885 /* DSC_D :: dfe_3_4_5_sts :: dfe_4_cmn [10:06] */ 8886 #define DSC_D_DFE_3_4_5_STS_DFE_4_CMN_MASK 0x07c0 8887 #define DSC_D_DFE_3_4_5_STS_DFE_4_CMN_ALIGN 0 8888 #define DSC_D_DFE_3_4_5_STS_DFE_4_CMN_BITS 5 8889 #define DSC_D_DFE_3_4_5_STS_DFE_4_CMN_SHIFT 6 8890 8891 /* DSC_D :: dfe_3_4_5_sts :: dfe_3_cmn [05:00] */ 8892 #define DSC_D_DFE_3_4_5_STS_DFE_3_CMN_MASK 0x003f 8893 #define DSC_D_DFE_3_4_5_STS_DFE_3_CMN_ALIGN 0 8894 #define DSC_D_DFE_3_4_5_STS_DFE_3_CMN_BITS 6 8895 #define DSC_D_DFE_3_4_5_STS_DFE_3_CMN_SHIFT 0 8896 8897 8898 /**************************************************************************** 8899 * DSC_D :: vga_tap_bin 8900 */ 8901 /* DSC_D :: vga_tap_bin :: reserved0 [15:12] */ 8902 #define DSC_D_VGA_TAP_BIN_RESERVED0_MASK 0xf000 8903 #define DSC_D_VGA_TAP_BIN_RESERVED0_ALIGN 0 8904 #define DSC_D_VGA_TAP_BIN_RESERVED0_BITS 4 8905 #define DSC_D_VGA_TAP_BIN_RESERVED0_SHIFT 12 8906 8907 /* DSC_D :: vga_tap_bin :: vga3_ctrl_bin [11:08] */ 8908 #define DSC_D_VGA_TAP_BIN_VGA3_CTRL_BIN_MASK 0x0f00 8909 #define DSC_D_VGA_TAP_BIN_VGA3_CTRL_BIN_ALIGN 0 8910 #define DSC_D_VGA_TAP_BIN_VGA3_CTRL_BIN_BITS 4 8911 #define DSC_D_VGA_TAP_BIN_VGA3_CTRL_BIN_SHIFT 8 8912 8913 /* DSC_D :: vga_tap_bin :: vga2_ctrl_bin [07:04] */ 8914 #define DSC_D_VGA_TAP_BIN_VGA2_CTRL_BIN_MASK 0x00f0 8915 #define DSC_D_VGA_TAP_BIN_VGA2_CTRL_BIN_ALIGN 0 8916 #define DSC_D_VGA_TAP_BIN_VGA2_CTRL_BIN_BITS 4 8917 #define DSC_D_VGA_TAP_BIN_VGA2_CTRL_BIN_SHIFT 4 8918 8919 /* DSC_D :: vga_tap_bin :: vga1_ctrl_bin [03:00] */ 8920 #define DSC_D_VGA_TAP_BIN_VGA1_CTRL_BIN_MASK 0x000f 8921 #define DSC_D_VGA_TAP_BIN_VGA1_CTRL_BIN_ALIGN 0 8922 #define DSC_D_VGA_TAP_BIN_VGA1_CTRL_BIN_BITS 4 8923 #define DSC_D_VGA_TAP_BIN_VGA1_CTRL_BIN_SHIFT 0 8924 8925 8926 /**************************************************************************** 8927 * merlin_gallardo_dsc_blk_DSC_E 8928 */ 8929 /**************************************************************************** 8930 * DSC_E :: dsc_e_ctrl 8931 */ 8932 /* DSC_E :: dsc_e_ctrl :: reserved0 [15:08] */ 8933 #define DSC_E_DSC_E_CTRL_RESERVED0_MASK 0xff00 8934 #define DSC_E_DSC_E_CTRL_RESERVED0_ALIGN 0 8935 #define DSC_E_DSC_E_CTRL_RESERVED0_BITS 8 8936 #define DSC_E_DSC_E_CTRL_RESERVED0_SHIFT 8 8937 8938 /* DSC_E :: dsc_e_ctrl :: pf_hiz [07:07] */ 8939 #define DSC_E_DSC_E_CTRL_PF_HIZ_MASK 0x0080 8940 #define DSC_E_DSC_E_CTRL_PF_HIZ_ALIGN 0 8941 #define DSC_E_DSC_E_CTRL_PF_HIZ_BITS 1 8942 #define DSC_E_DSC_E_CTRL_PF_HIZ_SHIFT 7 8943 8944 /* DSC_E :: dsc_e_ctrl :: thresh_sel [06:05] */ 8945 #define DSC_E_DSC_E_CTRL_THRESH_SEL_MASK 0x0060 8946 #define DSC_E_DSC_E_CTRL_THRESH_SEL_ALIGN 0 8947 #define DSC_E_DSC_E_CTRL_THRESH_SEL_BITS 2 8948 #define DSC_E_DSC_E_CTRL_THRESH_SEL_SHIFT 5 8949 8950 /* DSC_E :: dsc_e_ctrl :: m1_thresh_zero [04:04] */ 8951 #define DSC_E_DSC_E_CTRL_M1_THRESH_ZERO_MASK 0x0010 8952 #define DSC_E_DSC_E_CTRL_M1_THRESH_ZERO_ALIGN 0 8953 #define DSC_E_DSC_E_CTRL_M1_THRESH_ZERO_BITS 1 8954 #define DSC_E_DSC_E_CTRL_M1_THRESH_ZERO_SHIFT 4 8955 8956 /* DSC_E :: dsc_e_ctrl :: p1_thresh_sel [03:03] */ 8957 #define DSC_E_DSC_E_CTRL_P1_THRESH_SEL_MASK 0x0008 8958 #define DSC_E_DSC_E_CTRL_P1_THRESH_SEL_ALIGN 0 8959 #define DSC_E_DSC_E_CTRL_P1_THRESH_SEL_BITS 1 8960 #define DSC_E_DSC_E_CTRL_P1_THRESH_SEL_SHIFT 3 8961 8962 /* DSC_E :: dsc_e_ctrl :: en_hgain [02:02] */ 8963 #define DSC_E_DSC_E_CTRL_EN_HGAIN_MASK 0x0004 8964 #define DSC_E_DSC_E_CTRL_EN_HGAIN_ALIGN 0 8965 #define DSC_E_DSC_E_CTRL_EN_HGAIN_BITS 1 8966 #define DSC_E_DSC_E_CTRL_EN_HGAIN_SHIFT 2 8967 8968 /* DSC_E :: dsc_e_ctrl :: offset_pd [01:01] */ 8969 #define DSC_E_DSC_E_CTRL_OFFSET_PD_MASK 0x0002 8970 #define DSC_E_DSC_E_CTRL_OFFSET_PD_ALIGN 0 8971 #define DSC_E_DSC_E_CTRL_OFFSET_PD_BITS 1 8972 #define DSC_E_DSC_E_CTRL_OFFSET_PD_SHIFT 1 8973 8974 /* DSC_E :: dsc_e_ctrl :: pd_ch_p1 [00:00] */ 8975 #define DSC_E_DSC_E_CTRL_PD_CH_P1_MASK 0x0001 8976 #define DSC_E_DSC_E_CTRL_PD_CH_P1_ALIGN 0 8977 #define DSC_E_DSC_E_CTRL_PD_CH_P1_BITS 1 8978 #define DSC_E_DSC_E_CTRL_PD_CH_P1_SHIFT 0 8979 8980 8981 /**************************************************************************** 8982 * DSC_E :: dsc_e_pf_ctrl 8983 */ 8984 /* DSC_E :: dsc_e_pf_ctrl :: reserved0 [15:04] */ 8985 #define DSC_E_DSC_E_PF_CTRL_RESERVED0_MASK 0xfff0 8986 #define DSC_E_DSC_E_PF_CTRL_RESERVED0_ALIGN 0 8987 #define DSC_E_DSC_E_PF_CTRL_RESERVED0_BITS 12 8988 #define DSC_E_DSC_E_PF_CTRL_RESERVED0_SHIFT 4 8989 8990 /* DSC_E :: dsc_e_pf_ctrl :: pf_ctrl [03:00] */ 8991 #define DSC_E_DSC_E_PF_CTRL_PF_CTRL_MASK 0x000f 8992 #define DSC_E_DSC_E_PF_CTRL_PF_CTRL_ALIGN 0 8993 #define DSC_E_DSC_E_PF_CTRL_PF_CTRL_BITS 4 8994 #define DSC_E_DSC_E_PF_CTRL_PF_CTRL_SHIFT 0 8995 8996 8997 /**************************************************************************** 8998 * DSC_E :: dsc_e_pf2_lowp_ctrl 8999 */ 9000 /* DSC_E :: dsc_e_pf2_lowp_ctrl :: reserved0 [15:03] */ 9001 #define DSC_E_DSC_E_PF2_LOWP_CTRL_RESERVED0_MASK 0xfff8 9002 #define DSC_E_DSC_E_PF2_LOWP_CTRL_RESERVED0_ALIGN 0 9003 #define DSC_E_DSC_E_PF2_LOWP_CTRL_RESERVED0_BITS 13 9004 #define DSC_E_DSC_E_PF2_LOWP_CTRL_RESERVED0_SHIFT 3 9005 9006 /* DSC_E :: dsc_e_pf2_lowp_ctrl :: pf2_lowp_ctrl [02:00] */ 9007 #define DSC_E_DSC_E_PF2_LOWP_CTRL_PF2_LOWP_CTRL_MASK 0x0007 9008 #define DSC_E_DSC_E_PF2_LOWP_CTRL_PF2_LOWP_CTRL_ALIGN 0 9009 #define DSC_E_DSC_E_PF2_LOWP_CTRL_PF2_LOWP_CTRL_BITS 3 9010 #define DSC_E_DSC_E_PF2_LOWP_CTRL_PF2_LOWP_CTRL_SHIFT 0 9011 9012 9013 /**************************************************************************** 9014 * DSC_E :: dsc_e_offset_adj_data_odd 9015 */ 9016 /* DSC_E :: dsc_e_offset_adj_data_odd :: reserved0 [15:06] */ 9017 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD_RESERVED0_MASK 0xffc0 9018 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD_RESERVED0_ALIGN 0 9019 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD_RESERVED0_BITS 10 9020 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD_RESERVED0_SHIFT 6 9021 9022 /* DSC_E :: dsc_e_offset_adj_data_odd :: dfe_offset_adj_data_odd [05:00] */ 9023 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD_DFE_OFFSET_ADJ_DATA_ODD_MASK 0x003f 9024 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD_DFE_OFFSET_ADJ_DATA_ODD_ALIGN 0 9025 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD_DFE_OFFSET_ADJ_DATA_ODD_BITS 6 9026 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_ODD_DFE_OFFSET_ADJ_DATA_ODD_SHIFT 0 9027 9028 9029 /**************************************************************************** 9030 * DSC_E :: dsc_e_offset_adj_data_even 9031 */ 9032 /* DSC_E :: dsc_e_offset_adj_data_even :: reserved0 [15:06] */ 9033 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN_RESERVED0_MASK 0xffc0 9034 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN_RESERVED0_ALIGN 0 9035 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN_RESERVED0_BITS 10 9036 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN_RESERVED0_SHIFT 6 9037 9038 /* DSC_E :: dsc_e_offset_adj_data_even :: dfe_offset_adj_data_even [05:00] */ 9039 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN_DFE_OFFSET_ADJ_DATA_EVEN_MASK 0x003f 9040 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN_DFE_OFFSET_ADJ_DATA_EVEN_ALIGN 0 9041 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN_DFE_OFFSET_ADJ_DATA_EVEN_BITS 6 9042 #define DSC_E_DSC_E_OFFSET_ADJ_DATA_EVEN_DFE_OFFSET_ADJ_DATA_EVEN_SHIFT 0 9043 9044 9045 /**************************************************************************** 9046 * DSC_E :: dsc_e_offset_adj_p1_odd 9047 */ 9048 /* DSC_E :: dsc_e_offset_adj_p1_odd :: reserved0 [15:06] */ 9049 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD_RESERVED0_MASK 0xffc0 9050 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD_RESERVED0_ALIGN 0 9051 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD_RESERVED0_BITS 10 9052 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD_RESERVED0_SHIFT 6 9053 9054 /* DSC_E :: dsc_e_offset_adj_p1_odd :: dfe_offset_adj_p1_odd [05:00] */ 9055 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD_DFE_OFFSET_ADJ_P1_ODD_MASK 0x003f 9056 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD_DFE_OFFSET_ADJ_P1_ODD_ALIGN 0 9057 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD_DFE_OFFSET_ADJ_P1_ODD_BITS 6 9058 #define DSC_E_DSC_E_OFFSET_ADJ_P1_ODD_DFE_OFFSET_ADJ_P1_ODD_SHIFT 0 9059 9060 9061 /**************************************************************************** 9062 * DSC_E :: dsc_e_offset_adj_p1_even 9063 */ 9064 /* DSC_E :: dsc_e_offset_adj_p1_even :: reserved0 [15:06] */ 9065 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN_RESERVED0_MASK 0xffc0 9066 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN_RESERVED0_ALIGN 0 9067 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN_RESERVED0_BITS 10 9068 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN_RESERVED0_SHIFT 6 9069 9070 /* DSC_E :: dsc_e_offset_adj_p1_even :: dfe_offset_adj_p1_even [05:00] */ 9071 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN_DFE_OFFSET_ADJ_P1_EVEN_MASK 0x003f 9072 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN_DFE_OFFSET_ADJ_P1_EVEN_ALIGN 0 9073 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN_DFE_OFFSET_ADJ_P1_EVEN_BITS 6 9074 #define DSC_E_DSC_E_OFFSET_ADJ_P1_EVEN_DFE_OFFSET_ADJ_P1_EVEN_SHIFT 0 9075 9076 9077 /**************************************************************************** 9078 * DSC_E :: dsc_e_offset_adj_m1_odd 9079 */ 9080 /* DSC_E :: dsc_e_offset_adj_m1_odd :: reserved0 [15:06] */ 9081 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD_RESERVED0_MASK 0xffc0 9082 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD_RESERVED0_ALIGN 0 9083 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD_RESERVED0_BITS 10 9084 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD_RESERVED0_SHIFT 6 9085 9086 /* DSC_E :: dsc_e_offset_adj_m1_odd :: dfe_offset_adj_m1_odd [05:00] */ 9087 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD_DFE_OFFSET_ADJ_M1_ODD_MASK 0x003f 9088 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD_DFE_OFFSET_ADJ_M1_ODD_ALIGN 0 9089 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD_DFE_OFFSET_ADJ_M1_ODD_BITS 6 9090 #define DSC_E_DSC_E_OFFSET_ADJ_M1_ODD_DFE_OFFSET_ADJ_M1_ODD_SHIFT 0 9091 9092 9093 /**************************************************************************** 9094 * DSC_E :: dsc_e_offset_adj_m1_even 9095 */ 9096 /* DSC_E :: dsc_e_offset_adj_m1_even :: reserved0 [15:06] */ 9097 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN_RESERVED0_MASK 0xffc0 9098 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN_RESERVED0_ALIGN 0 9099 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN_RESERVED0_BITS 10 9100 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN_RESERVED0_SHIFT 6 9101 9102 /* DSC_E :: dsc_e_offset_adj_m1_even :: dfe_offset_adj_m1_even [05:00] */ 9103 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN_DFE_OFFSET_ADJ_M1_EVEN_MASK 0x003f 9104 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN_DFE_OFFSET_ADJ_M1_EVEN_ALIGN 0 9105 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN_DFE_OFFSET_ADJ_M1_EVEN_BITS 6 9106 #define DSC_E_DSC_E_OFFSET_ADJ_M1_EVEN_DFE_OFFSET_ADJ_M1_EVEN_SHIFT 0 9107 9108 9109 /**************************************************************************** 9110 * DSC_E :: dsc_e_dc_offset 9111 */ 9112 /* DSC_E :: dsc_e_dc_offset :: reserved0 [15:07] */ 9113 #define DSC_E_DSC_E_DC_OFFSET_RESERVED0_MASK 0xff80 9114 #define DSC_E_DSC_E_DC_OFFSET_RESERVED0_ALIGN 0 9115 #define DSC_E_DSC_E_DC_OFFSET_RESERVED0_BITS 9 9116 #define DSC_E_DSC_E_DC_OFFSET_RESERVED0_SHIFT 7 9117 9118 /* DSC_E :: dsc_e_dc_offset :: dc_offset [06:00] */ 9119 #define DSC_E_DSC_E_DC_OFFSET_DC_OFFSET_MASK 0x007f 9120 #define DSC_E_DSC_E_DC_OFFSET_DC_OFFSET_ALIGN 0 9121 #define DSC_E_DSC_E_DC_OFFSET_DC_OFFSET_BITS 7 9122 #define DSC_E_DSC_E_DC_OFFSET_DC_OFFSET_SHIFT 0 9123 9124 9125 /**************************************************************************** 9126 * merlin_gallardo_cl72_user_blk_CL72_USER_RX 9127 */ 9128 /**************************************************************************** 9129 * CL72_USER_RX :: rcvd_status_register 9130 */ 9131 /* CL72_USER_RX :: rcvd_status_register :: rcvd_status_page [15:00] */ 9132 #define CL72_USER_RX_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_MASK 0xffff 9133 #define CL72_USER_RX_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_ALIGN 0 9134 #define CL72_USER_RX_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_BITS 16 9135 #define CL72_USER_RX_RCVD_STATUS_REGISTER_RCVD_STATUS_PAGE_SHIFT 0 9136 9137 9138 /**************************************************************************** 9139 * CL72_USER_RX :: misc1_control 9140 */ 9141 /* CL72_USER_RX :: misc1_control :: reserved0 [15:03] */ 9142 #define CL72_USER_RX_MISC1_CONTROL_RESERVED0_MASK 0xfff8 9143 #define CL72_USER_RX_MISC1_CONTROL_RESERVED0_ALIGN 0 9144 #define CL72_USER_RX_MISC1_CONTROL_RESERVED0_BITS 13 9145 #define CL72_USER_RX_MISC1_CONTROL_RESERVED0_SHIFT 3 9146 9147 /* CL72_USER_RX :: misc1_control :: rx_dp_ln_clk_en [02:02] */ 9148 #define CL72_USER_RX_MISC1_CONTROL_RX_DP_LN_CLK_EN_MASK 0x0004 9149 #define CL72_USER_RX_MISC1_CONTROL_RX_DP_LN_CLK_EN_ALIGN 0 9150 #define CL72_USER_RX_MISC1_CONTROL_RX_DP_LN_CLK_EN_BITS 1 9151 #define CL72_USER_RX_MISC1_CONTROL_RX_DP_LN_CLK_EN_SHIFT 2 9152 9153 /* CL72_USER_RX :: misc1_control :: tr_coarse_lock [01:01] */ 9154 #define CL72_USER_RX_MISC1_CONTROL_TR_COARSE_LOCK_MASK 0x0002 9155 #define CL72_USER_RX_MISC1_CONTROL_TR_COARSE_LOCK_ALIGN 0 9156 #define CL72_USER_RX_MISC1_CONTROL_TR_COARSE_LOCK_BITS 1 9157 #define CL72_USER_RX_MISC1_CONTROL_TR_COARSE_LOCK_SHIFT 1 9158 9159 /* CL72_USER_RX :: misc1_control :: reserved1 [00:00] */ 9160 #define CL72_USER_RX_MISC1_CONTROL_RESERVED1_MASK 0x0001 9161 #define CL72_USER_RX_MISC1_CONTROL_RESERVED1_ALIGN 0 9162 #define CL72_USER_RX_MISC1_CONTROL_RESERVED1_BITS 1 9163 #define CL72_USER_RX_MISC1_CONTROL_RESERVED1_SHIFT 0 9164 9165 9166 /**************************************************************************** 9167 * CL72_USER_RX :: debug_2_register 9168 */ 9169 /* CL72_USER_RX :: debug_2_register :: reserved0 [15:15] */ 9170 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED0_MASK 0x8000 9171 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED0_ALIGN 0 9172 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED0_BITS 1 9173 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED0_SHIFT 15 9174 9175 /* CL72_USER_RX :: debug_2_register :: ppm_offset_en [14:14] */ 9176 #define CL72_USER_RX_DEBUG_2_REGISTER_PPM_OFFSET_EN_MASK 0x4000 9177 #define CL72_USER_RX_DEBUG_2_REGISTER_PPM_OFFSET_EN_ALIGN 0 9178 #define CL72_USER_RX_DEBUG_2_REGISTER_PPM_OFFSET_EN_BITS 1 9179 #define CL72_USER_RX_DEBUG_2_REGISTER_PPM_OFFSET_EN_SHIFT 14 9180 9181 /* CL72_USER_RX :: debug_2_register :: strict_marker_chk [13:13] */ 9182 #define CL72_USER_RX_DEBUG_2_REGISTER_STRICT_MARKER_CHK_MASK 0x2000 9183 #define CL72_USER_RX_DEBUG_2_REGISTER_STRICT_MARKER_CHK_ALIGN 0 9184 #define CL72_USER_RX_DEBUG_2_REGISTER_STRICT_MARKER_CHK_BITS 1 9185 #define CL72_USER_RX_DEBUG_2_REGISTER_STRICT_MARKER_CHK_SHIFT 13 9186 9187 /* CL72_USER_RX :: debug_2_register :: strict_dme_chk [12:12] */ 9188 #define CL72_USER_RX_DEBUG_2_REGISTER_STRICT_DME_CHK_MASK 0x1000 9189 #define CL72_USER_RX_DEBUG_2_REGISTER_STRICT_DME_CHK_ALIGN 0 9190 #define CL72_USER_RX_DEBUG_2_REGISTER_STRICT_DME_CHK_BITS 1 9191 #define CL72_USER_RX_DEBUG_2_REGISTER_STRICT_DME_CHK_SHIFT 12 9192 9193 /* CL72_USER_RX :: debug_2_register :: ctrl_frame_dly [11:08] */ 9194 #define CL72_USER_RX_DEBUG_2_REGISTER_CTRL_FRAME_DLY_MASK 0x0f00 9195 #define CL72_USER_RX_DEBUG_2_REGISTER_CTRL_FRAME_DLY_ALIGN 0 9196 #define CL72_USER_RX_DEBUG_2_REGISTER_CTRL_FRAME_DLY_BITS 4 9197 #define CL72_USER_RX_DEBUG_2_REGISTER_CTRL_FRAME_DLY_SHIFT 8 9198 9199 /* CL72_USER_RX :: debug_2_register :: dme_cell_boundary_chk [07:07] */ 9200 #define CL72_USER_RX_DEBUG_2_REGISTER_DME_CELL_BOUNDARY_CHK_MASK 0x0080 9201 #define CL72_USER_RX_DEBUG_2_REGISTER_DME_CELL_BOUNDARY_CHK_ALIGN 0 9202 #define CL72_USER_RX_DEBUG_2_REGISTER_DME_CELL_BOUNDARY_CHK_BITS 1 9203 #define CL72_USER_RX_DEBUG_2_REGISTER_DME_CELL_BOUNDARY_CHK_SHIFT 7 9204 9205 /* CL72_USER_RX :: debug_2_register :: reserved1 [06:05] */ 9206 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED1_MASK 0x0060 9207 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED1_ALIGN 0 9208 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED1_BITS 2 9209 #define CL72_USER_RX_DEBUG_2_REGISTER_RESERVED1_SHIFT 5 9210 9211 /* CL72_USER_RX :: debug_2_register :: bad_marker_cnt [04:02] */ 9212 #define CL72_USER_RX_DEBUG_2_REGISTER_BAD_MARKER_CNT_MASK 0x001c 9213 #define CL72_USER_RX_DEBUG_2_REGISTER_BAD_MARKER_CNT_ALIGN 0 9214 #define CL72_USER_RX_DEBUG_2_REGISTER_BAD_MARKER_CNT_BITS 3 9215 #define CL72_USER_RX_DEBUG_2_REGISTER_BAD_MARKER_CNT_SHIFT 2 9216 9217 /* CL72_USER_RX :: debug_2_register :: good_marker_cnt [01:00] */ 9218 #define CL72_USER_RX_DEBUG_2_REGISTER_GOOD_MARKER_CNT_MASK 0x0003 9219 #define CL72_USER_RX_DEBUG_2_REGISTER_GOOD_MARKER_CNT_ALIGN 0 9220 #define CL72_USER_RX_DEBUG_2_REGISTER_GOOD_MARKER_CNT_BITS 2 9221 #define CL72_USER_RX_DEBUG_2_REGISTER_GOOD_MARKER_CNT_SHIFT 0 9222 9223 9224 /**************************************************************************** 9225 * CL72_USER_RX :: cl72_lp_control_page 9226 */ 9227 /* CL72_USER_RX :: cl72_lp_control_page :: lp_control_page [15:00] */ 9228 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE_LP_CONTROL_PAGE_MASK 0xffff 9229 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE_LP_CONTROL_PAGE_ALIGN 0 9230 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE_LP_CONTROL_PAGE_BITS 16 9231 #define CL72_USER_RX_CL72_LP_CONTROL_PAGE_LP_CONTROL_PAGE_SHIFT 0 9232 9233 9234 /**************************************************************************** 9235 * CL72_USER_RX :: cl72_status1_register 9236 */ 9237 /* CL72_USER_RX :: cl72_status1_register :: reserved0 [15:01] */ 9238 #define CL72_USER_RX_CL72_STATUS1_REGISTER_RESERVED0_MASK 0xfffe 9239 #define CL72_USER_RX_CL72_STATUS1_REGISTER_RESERVED0_ALIGN 0 9240 #define CL72_USER_RX_CL72_STATUS1_REGISTER_RESERVED0_BITS 15 9241 #define CL72_USER_RX_CL72_STATUS1_REGISTER_RESERVED0_SHIFT 1 9242 9243 /* CL72_USER_RX :: cl72_status1_register :: cl72_signal_detect [00:00] */ 9244 #define CL72_USER_RX_CL72_STATUS1_REGISTER_CL72_SIGNAL_DETECT_MASK 0x0001 9245 #define CL72_USER_RX_CL72_STATUS1_REGISTER_CL72_SIGNAL_DETECT_ALIGN 0 9246 #define CL72_USER_RX_CL72_STATUS1_REGISTER_CL72_SIGNAL_DETECT_BITS 1 9247 #define CL72_USER_RX_CL72_STATUS1_REGISTER_CL72_SIGNAL_DETECT_SHIFT 0 9248 9249 9250 /**************************************************************************** 9251 * merlin_gallardo_cl72_user_blk_CL72_USER_TX 9252 */ 9253 /**************************************************************************** 9254 * CL72_USER_TX :: xmt_update_register 9255 */ 9256 /* CL72_USER_TX :: xmt_update_register :: xmt_update_page [15:00] */ 9257 #define CL72_USER_TX_XMT_UPDATE_REGISTER_XMT_UPDATE_PAGE_MASK 0xffff 9258 #define CL72_USER_TX_XMT_UPDATE_REGISTER_XMT_UPDATE_PAGE_ALIGN 0 9259 #define CL72_USER_TX_XMT_UPDATE_REGISTER_XMT_UPDATE_PAGE_BITS 16 9260 #define CL72_USER_TX_XMT_UPDATE_REGISTER_XMT_UPDATE_PAGE_SHIFT 0 9261 9262 9263 /**************************************************************************** 9264 * CL72_USER_TX :: misc2_control 9265 */ 9266 /* CL72_USER_TX :: misc2_control :: reserved0 [15:03] */ 9267 #define CL72_USER_TX_MISC2_CONTROL_RESERVED0_MASK 0xfff8 9268 #define CL72_USER_TX_MISC2_CONTROL_RESERVED0_ALIGN 0 9269 #define CL72_USER_TX_MISC2_CONTROL_RESERVED0_BITS 13 9270 #define CL72_USER_TX_MISC2_CONTROL_RESERVED0_SHIFT 3 9271 9272 /* CL72_USER_TX :: misc2_control :: tx_dp_ln_clk_en [02:02] */ 9273 #define CL72_USER_TX_MISC2_CONTROL_TX_DP_LN_CLK_EN_MASK 0x0004 9274 #define CL72_USER_TX_MISC2_CONTROL_TX_DP_LN_CLK_EN_ALIGN 0 9275 #define CL72_USER_TX_MISC2_CONTROL_TX_DP_LN_CLK_EN_BITS 1 9276 #define CL72_USER_TX_MISC2_CONTROL_TX_DP_LN_CLK_EN_SHIFT 2 9277 9278 /* CL72_USER_TX :: misc2_control :: signal_det_force [01:01] */ 9279 #define CL72_USER_TX_MISC2_CONTROL_SIGNAL_DET_FORCE_MASK 0x0002 9280 #define CL72_USER_TX_MISC2_CONTROL_SIGNAL_DET_FORCE_ALIGN 0 9281 #define CL72_USER_TX_MISC2_CONTROL_SIGNAL_DET_FORCE_BITS 1 9282 #define CL72_USER_TX_MISC2_CONTROL_SIGNAL_DET_FORCE_SHIFT 1 9283 9284 /* CL72_USER_TX :: misc2_control :: rx_trained [00:00] */ 9285 #define CL72_USER_TX_MISC2_CONTROL_RX_TRAINED_MASK 0x0001 9286 #define CL72_USER_TX_MISC2_CONTROL_RX_TRAINED_ALIGN 0 9287 #define CL72_USER_TX_MISC2_CONTROL_RX_TRAINED_BITS 1 9288 #define CL72_USER_TX_MISC2_CONTROL_RX_TRAINED_SHIFT 0 9289 9290 9291 /**************************************************************************** 9292 * CL72_USER_TX :: debug_3_register 9293 */ 9294 /* CL72_USER_TX :: debug_3_register :: reserved0 [15:02] */ 9295 #define CL72_USER_TX_DEBUG_3_REGISTER_RESERVED0_MASK 0xfffc 9296 #define CL72_USER_TX_DEBUG_3_REGISTER_RESERVED0_ALIGN 0 9297 #define CL72_USER_TX_DEBUG_3_REGISTER_RESERVED0_BITS 14 9298 #define CL72_USER_TX_DEBUG_3_REGISTER_RESERVED0_SHIFT 2 9299 9300 /* CL72_USER_TX :: debug_3_register :: frame_lock_rdy_for_cmd_en [01:01] */ 9301 #define CL72_USER_TX_DEBUG_3_REGISTER_FRAME_LOCK_RDY_FOR_CMD_EN_MASK 0x0002 9302 #define CL72_USER_TX_DEBUG_3_REGISTER_FRAME_LOCK_RDY_FOR_CMD_EN_ALIGN 0 9303 #define CL72_USER_TX_DEBUG_3_REGISTER_FRAME_LOCK_RDY_FOR_CMD_EN_BITS 1 9304 #define CL72_USER_TX_DEBUG_3_REGISTER_FRAME_LOCK_RDY_FOR_CMD_EN_SHIFT 1 9305 9306 /* CL72_USER_TX :: debug_3_register :: brk_ring_osc [00:00] */ 9307 #define CL72_USER_TX_DEBUG_3_REGISTER_BRK_RING_OSC_MASK 0x0001 9308 #define CL72_USER_TX_DEBUG_3_REGISTER_BRK_RING_OSC_ALIGN 0 9309 #define CL72_USER_TX_DEBUG_3_REGISTER_BRK_RING_OSC_BITS 1 9310 #define CL72_USER_TX_DEBUG_3_REGISTER_BRK_RING_OSC_SHIFT 0 9311 9312 9313 /**************************************************************************** 9314 * CL72_USER_TX :: pcs_interface_control_register 9315 */ 9316 /* CL72_USER_TX :: pcs_interface_control_register :: reserved0 [15:01] */ 9317 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_RESERVED0_MASK 0xfffe 9318 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_RESERVED0_ALIGN 0 9319 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_RESERVED0_BITS 15 9320 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_RESERVED0_SHIFT 1 9321 9322 /* CL72_USER_TX :: pcs_interface_control_register :: dis_max_wait_timer [00:00] */ 9323 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_DIS_MAX_WAIT_TIMER_MASK 0x0001 9324 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_DIS_MAX_WAIT_TIMER_ALIGN 0 9325 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_DIS_MAX_WAIT_TIMER_BITS 1 9326 #define CL72_USER_TX_PCS_INTERFACE_CONTROL_REGISTER_DIS_MAX_WAIT_TIMER_SHIFT 0 9327 9328 9329 /**************************************************************************** 9330 * CL72_USER_TX :: cl72_ld_status_page 9331 */ 9332 /* CL72_USER_TX :: cl72_ld_status_page :: ld_status_page [15:00] */ 9333 #define CL72_USER_TX_CL72_LD_STATUS_PAGE_LD_STATUS_PAGE_MASK 0xffff 9334 #define CL72_USER_TX_CL72_LD_STATUS_PAGE_LD_STATUS_PAGE_ALIGN 0 9335 #define CL72_USER_TX_CL72_LD_STATUS_PAGE_LD_STATUS_PAGE_BITS 16 9336 #define CL72_USER_TX_CL72_LD_STATUS_PAGE_LD_STATUS_PAGE_SHIFT 0 9337 9338 9339 /**************************************************************************** 9340 * CL72_USER_TX :: cl72_ready_for_cmd_register 9341 */ 9342 /* CL72_USER_TX :: cl72_ready_for_cmd_register :: reserved0 [15:01] */ 9343 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_RESERVED0_MASK 0xfffe 9344 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_RESERVED0_ALIGN 0 9345 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_RESERVED0_BITS 15 9346 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_RESERVED0_SHIFT 1 9347 9348 /* CL72_USER_TX :: cl72_ready_for_cmd_register :: ready_for_cmd [00:00] */ 9349 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_READY_FOR_CMD_MASK 0x0001 9350 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_READY_FOR_CMD_ALIGN 0 9351 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_READY_FOR_CMD_BITS 1 9352 #define CL72_USER_TX_CL72_READY_FOR_CMD_REGISTER_READY_FOR_CMD_SHIFT 0 9353 9354 9355 /**************************************************************************** 9356 * CL72_USER_TX :: kr_default_control1 9357 */ 9358 /* CL72_USER_TX :: kr_default_control1 :: reserved0 [15:10] */ 9359 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED0_MASK 0xfc00 9360 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED0_ALIGN 0 9361 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED0_BITS 6 9362 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED0_SHIFT 10 9363 9364 /* CL72_USER_TX :: kr_default_control1 :: tx_fir_tap_post_kr_init_val [09:05] */ 9365 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_TX_FIR_TAP_POST_KR_INIT_VAL_MASK 0x03e0 9366 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_TX_FIR_TAP_POST_KR_INIT_VAL_ALIGN 0 9367 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_TX_FIR_TAP_POST_KR_INIT_VAL_BITS 5 9368 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_TX_FIR_TAP_POST_KR_INIT_VAL_SHIFT 5 9369 9370 /* CL72_USER_TX :: kr_default_control1 :: reserved1 [04:04] */ 9371 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED1_MASK 0x0010 9372 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED1_ALIGN 0 9373 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED1_BITS 1 9374 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_RESERVED1_SHIFT 4 9375 9376 /* CL72_USER_TX :: kr_default_control1 :: tx_fir_tap_pre_kr_init_val [03:00] */ 9377 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_TX_FIR_TAP_PRE_KR_INIT_VAL_MASK 0x000f 9378 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_TX_FIR_TAP_PRE_KR_INIT_VAL_ALIGN 0 9379 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_TX_FIR_TAP_PRE_KR_INIT_VAL_BITS 4 9380 #define CL72_USER_TX_KR_DEFAULT_CONTROL1_TX_FIR_TAP_PRE_KR_INIT_VAL_SHIFT 0 9381 9382 9383 /**************************************************************************** 9384 * CL72_USER_TX :: kr_default_control2 9385 */ 9386 /* CL72_USER_TX :: kr_default_control2 :: reserved0 [15:06] */ 9387 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_RESERVED0_MASK 0xffc0 9388 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_RESERVED0_ALIGN 0 9389 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_RESERVED0_BITS 10 9390 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_RESERVED0_SHIFT 6 9391 9392 /* CL72_USER_TX :: kr_default_control2 :: tx_fir_tap_main_kr_init_val [05:00] */ 9393 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_TX_FIR_TAP_MAIN_KR_INIT_VAL_MASK 0x003f 9394 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_TX_FIR_TAP_MAIN_KR_INIT_VAL_ALIGN 0 9395 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_TX_FIR_TAP_MAIN_KR_INIT_VAL_BITS 6 9396 #define CL72_USER_TX_KR_DEFAULT_CONTROL2_TX_FIR_TAP_MAIN_KR_INIT_VAL_SHIFT 0 9397 9398 9399 /**************************************************************************** 9400 * CL72_USER_TX :: misc_coeff_control 9401 */ 9402 /* CL72_USER_TX :: misc_coeff_control :: reserved0 [15:13] */ 9403 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED0_MASK 0xe000 9404 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED0_ALIGN 0 9405 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED0_BITS 3 9406 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED0_SHIFT 13 9407 9408 /* CL72_USER_TX :: misc_coeff_control :: double_cmd_en [12:12] */ 9409 #define CL72_USER_TX_MISC_COEFF_CONTROL_DOUBLE_CMD_EN_MASK 0x1000 9410 #define CL72_USER_TX_MISC_COEFF_CONTROL_DOUBLE_CMD_EN_ALIGN 0 9411 #define CL72_USER_TX_MISC_COEFF_CONTROL_DOUBLE_CMD_EN_BITS 1 9412 #define CL72_USER_TX_MISC_COEFF_CONTROL_DOUBLE_CMD_EN_SHIFT 12 9413 9414 /* CL72_USER_TX :: misc_coeff_control :: dis_lp_coeff_updates_to_ld [11:11] */ 9415 #define CL72_USER_TX_MISC_COEFF_CONTROL_DIS_LP_COEFF_UPDATES_TO_LD_MASK 0x0800 9416 #define CL72_USER_TX_MISC_COEFF_CONTROL_DIS_LP_COEFF_UPDATES_TO_LD_ALIGN 0 9417 #define CL72_USER_TX_MISC_COEFF_CONTROL_DIS_LP_COEFF_UPDATES_TO_LD_BITS 1 9418 #define CL72_USER_TX_MISC_COEFF_CONTROL_DIS_LP_COEFF_UPDATES_TO_LD_SHIFT 11 9419 9420 /* CL72_USER_TX :: misc_coeff_control :: ld_xmt_status_override [10:10] */ 9421 #define CL72_USER_TX_MISC_COEFF_CONTROL_LD_XMT_STATUS_OVERRIDE_MASK 0x0400 9422 #define CL72_USER_TX_MISC_COEFF_CONTROL_LD_XMT_STATUS_OVERRIDE_ALIGN 0 9423 #define CL72_USER_TX_MISC_COEFF_CONTROL_LD_XMT_STATUS_OVERRIDE_BITS 1 9424 #define CL72_USER_TX_MISC_COEFF_CONTROL_LD_XMT_STATUS_OVERRIDE_SHIFT 10 9425 9426 /* CL72_USER_TX :: misc_coeff_control :: ld_xmt_status_load [09:09] */ 9427 #define CL72_USER_TX_MISC_COEFF_CONTROL_LD_XMT_STATUS_LOAD_MASK 0x0200 9428 #define CL72_USER_TX_MISC_COEFF_CONTROL_LD_XMT_STATUS_LOAD_ALIGN 0 9429 #define CL72_USER_TX_MISC_COEFF_CONTROL_LD_XMT_STATUS_LOAD_BITS 1 9430 #define CL72_USER_TX_MISC_COEFF_CONTROL_LD_XMT_STATUS_LOAD_SHIFT 9 9431 9432 /* CL72_USER_TX :: misc_coeff_control :: v2_constraint_dis [08:08] */ 9433 #define CL72_USER_TX_MISC_COEFF_CONTROL_V2_CONSTRAINT_DIS_MASK 0x0100 9434 #define CL72_USER_TX_MISC_COEFF_CONTROL_V2_CONSTRAINT_DIS_ALIGN 0 9435 #define CL72_USER_TX_MISC_COEFF_CONTROL_V2_CONSTRAINT_DIS_BITS 1 9436 #define CL72_USER_TX_MISC_COEFF_CONTROL_V2_CONSTRAINT_DIS_SHIFT 8 9437 9438 /* CL72_USER_TX :: misc_coeff_control :: reserved1 [07:07] */ 9439 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED1_MASK 0x0080 9440 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED1_ALIGN 0 9441 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED1_BITS 1 9442 #define CL72_USER_TX_MISC_COEFF_CONTROL_RESERVED1_SHIFT 7 9443 9444 /* CL72_USER_TX :: misc_coeff_control :: tap_v2_val [06:02] */ 9445 #define CL72_USER_TX_MISC_COEFF_CONTROL_TAP_V2_VAL_MASK 0x007c 9446 #define CL72_USER_TX_MISC_COEFF_CONTROL_TAP_V2_VAL_ALIGN 0 9447 #define CL72_USER_TX_MISC_COEFF_CONTROL_TAP_V2_VAL_BITS 5 9448 #define CL72_USER_TX_MISC_COEFF_CONTROL_TAP_V2_VAL_SHIFT 2 9449 9450 /* CL72_USER_TX :: misc_coeff_control :: inc_dec_val_sel [01:00] */ 9451 #define CL72_USER_TX_MISC_COEFF_CONTROL_INC_DEC_VAL_SEL_MASK 0x0003 9452 #define CL72_USER_TX_MISC_COEFF_CONTROL_INC_DEC_VAL_SEL_ALIGN 0 9453 #define CL72_USER_TX_MISC_COEFF_CONTROL_INC_DEC_VAL_SEL_BITS 2 9454 #define CL72_USER_TX_MISC_COEFF_CONTROL_INC_DEC_VAL_SEL_SHIFT 0 9455 9456 9457 /**************************************************************************** 9458 * CL72_USER_TX :: cl72_ld_xmt_status_page_override 9459 */ 9460 /* CL72_USER_TX :: cl72_ld_xmt_status_page_override :: overide_ld_status_page [15:00] */ 9461 #define CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE_OVERIDE_LD_STATUS_PAGE_MASK 0xffff 9462 #define CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE_OVERIDE_LD_STATUS_PAGE_ALIGN 0 9463 #define CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE_OVERIDE_LD_STATUS_PAGE_BITS 16 9464 #define CL72_USER_TX_CL72_LD_XMT_STATUS_PAGE_OVERRIDE_OVERIDE_LD_STATUS_PAGE_SHIFT 0 9465 9466 9467 /**************************************************************************** 9468 * CL72_USER_TX :: cl72_tx_debug_status 9469 */ 9470 /* CL72_USER_TX :: cl72_tx_debug_status :: reserved0 [15:12] */ 9471 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_RESERVED0_MASK 0xf000 9472 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_RESERVED0_ALIGN 0 9473 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_RESERVED0_BITS 4 9474 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_RESERVED0_SHIFT 12 9475 9476 /* CL72_USER_TX :: cl72_tx_debug_status :: cl72_frame_lock_lh [11:11] */ 9477 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_FRAME_LOCK_LH_MASK 0x0800 9478 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_FRAME_LOCK_LH_ALIGN 0 9479 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_FRAME_LOCK_LH_BITS 1 9480 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_FRAME_LOCK_LH_SHIFT 11 9481 9482 /* CL72_USER_TX :: cl72_tx_debug_status :: cl72_ld_coeff_cmd_hist [10:00] */ 9483 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_LD_COEFF_CMD_HIST_MASK 0x07ff 9484 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_LD_COEFF_CMD_HIST_ALIGN 0 9485 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_LD_COEFF_CMD_HIST_BITS 11 9486 #define CL72_USER_TX_CL72_TX_DEBUG_STATUS_CL72_LD_COEFF_CMD_HIST_SHIFT 0 9487 9488 9489 /**************************************************************************** 9490 * merlin_gallardo_tx_pi_blk_TX_PI 9491 */ 9492 /**************************************************************************** 9493 * TX_PI :: tx_pi_control_0 9494 */ 9495 /* TX_PI :: tx_pi_control_0 :: tx_pi_frc_phase_step_mux_sel [15:15] */ 9496 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FRC_PHASE_STEP_MUX_SEL_MASK 0x8000 9497 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FRC_PHASE_STEP_MUX_SEL_ALIGN 0 9498 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FRC_PHASE_STEP_MUX_SEL_BITS 1 9499 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FRC_PHASE_STEP_MUX_SEL_SHIFT 15 9500 9501 /* TX_PI :: tx_pi_control_0 :: reserved0 [14:14] */ 9502 #define TX_PI_TX_PI_CONTROL_0_RESERVED0_MASK 0x4000 9503 #define TX_PI_TX_PI_CONTROL_0_RESERVED0_ALIGN 0 9504 #define TX_PI_TX_PI_CONTROL_0_RESERVED0_BITS 1 9505 #define TX_PI_TX_PI_CONTROL_0_RESERVED0_SHIFT 14 9506 9507 /* TX_PI :: tx_pi_control_0 :: tx_pi_second_order_bwsel_integ [13:12] */ 9508 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SECOND_ORDER_BWSEL_INTEG_MASK 0x3000 9509 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SECOND_ORDER_BWSEL_INTEG_ALIGN 0 9510 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SECOND_ORDER_BWSEL_INTEG_BITS 2 9511 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SECOND_ORDER_BWSEL_INTEG_SHIFT 12 9512 9513 /* TX_PI :: tx_pi_control_0 :: tx_pi_first_order_bwsel_integ [11:10] */ 9514 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FIRST_ORDER_BWSEL_INTEG_MASK 0x0c00 9515 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FIRST_ORDER_BWSEL_INTEG_ALIGN 0 9516 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FIRST_ORDER_BWSEL_INTEG_BITS 2 9517 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FIRST_ORDER_BWSEL_INTEG_SHIFT 10 9518 9519 /* TX_PI :: tx_pi_control_0 :: tx_pi_rmt_lpbk_bypass_flt [09:09] */ 9520 #define TX_PI_TX_PI_CONTROL_0_TX_PI_RMT_LPBK_BYPASS_FLT_MASK 0x0200 9521 #define TX_PI_TX_PI_CONTROL_0_TX_PI_RMT_LPBK_BYPASS_FLT_ALIGN 0 9522 #define TX_PI_TX_PI_CONTROL_0_TX_PI_RMT_LPBK_BYPASS_FLT_BITS 1 9523 #define TX_PI_TX_PI_CONTROL_0_TX_PI_RMT_LPBK_BYPASS_FLT_SHIFT 9 9524 9525 /* TX_PI :: tx_pi_control_0 :: tx_pi_second_order_loop_en [08:08] */ 9526 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SECOND_ORDER_LOOP_EN_MASK 0x0100 9527 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SECOND_ORDER_LOOP_EN_ALIGN 0 9528 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SECOND_ORDER_LOOP_EN_BITS 1 9529 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SECOND_ORDER_LOOP_EN_SHIFT 8 9530 9531 /* TX_PI :: tx_pi_control_0 :: tx_pi_reset_code_dbg [07:07] */ 9532 #define TX_PI_TX_PI_CONTROL_0_TX_PI_RESET_CODE_DBG_MASK 0x0080 9533 #define TX_PI_TX_PI_CONTROL_0_TX_PI_RESET_CODE_DBG_ALIGN 0 9534 #define TX_PI_TX_PI_CONTROL_0_TX_PI_RESET_CODE_DBG_BITS 1 9535 #define TX_PI_TX_PI_CONTROL_0_TX_PI_RESET_CODE_DBG_SHIFT 7 9536 9537 /* TX_PI :: tx_pi_control_0 :: tx_pi_jit_ssc_freq_mode [06:06] */ 9538 #define TX_PI_TX_PI_CONTROL_0_TX_PI_JIT_SSC_FREQ_MODE_MASK 0x0040 9539 #define TX_PI_TX_PI_CONTROL_0_TX_PI_JIT_SSC_FREQ_MODE_ALIGN 0 9540 #define TX_PI_TX_PI_CONTROL_0_TX_PI_JIT_SSC_FREQ_MODE_BITS 1 9541 #define TX_PI_TX_PI_CONTROL_0_TX_PI_JIT_SSC_FREQ_MODE_SHIFT 6 9542 9543 /* TX_PI :: tx_pi_control_0 :: tx_pi_ssc_gen_en [05:05] */ 9544 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SSC_GEN_EN_MASK 0x0020 9545 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SSC_GEN_EN_ALIGN 0 9546 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SSC_GEN_EN_BITS 1 9547 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SSC_GEN_EN_SHIFT 5 9548 9549 /* TX_PI :: tx_pi_control_0 :: tx_pi_sj_gen_en [04:04] */ 9550 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SJ_GEN_EN_MASK 0x0010 9551 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SJ_GEN_EN_ALIGN 0 9552 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SJ_GEN_EN_BITS 1 9553 #define TX_PI_TX_PI_CONTROL_0_TX_PI_SJ_GEN_EN_SHIFT 4 9554 9555 /* TX_PI :: tx_pi_control_0 :: tx_pi_freq_override_en [03:03] */ 9556 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FREQ_OVERRIDE_EN_MASK 0x0008 9557 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FREQ_OVERRIDE_EN_ALIGN 0 9558 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FREQ_OVERRIDE_EN_BITS 1 9559 #define TX_PI_TX_PI_CONTROL_0_TX_PI_FREQ_OVERRIDE_EN_SHIFT 3 9560 9561 /* TX_PI :: tx_pi_control_0 :: tx_pi_ext_ctrl_en [02:02] */ 9562 #define TX_PI_TX_PI_CONTROL_0_TX_PI_EXT_CTRL_EN_MASK 0x0004 9563 #define TX_PI_TX_PI_CONTROL_0_TX_PI_EXT_CTRL_EN_ALIGN 0 9564 #define TX_PI_TX_PI_CONTROL_0_TX_PI_EXT_CTRL_EN_BITS 1 9565 #define TX_PI_TX_PI_CONTROL_0_TX_PI_EXT_CTRL_EN_SHIFT 2 9566 9567 /* TX_PI :: tx_pi_control_0 :: tx_pi_loop_timing_en [01:01] */ 9568 #define TX_PI_TX_PI_CONTROL_0_TX_PI_LOOP_TIMING_EN_MASK 0x0002 9569 #define TX_PI_TX_PI_CONTROL_0_TX_PI_LOOP_TIMING_EN_ALIGN 0 9570 #define TX_PI_TX_PI_CONTROL_0_TX_PI_LOOP_TIMING_EN_BITS 1 9571 #define TX_PI_TX_PI_CONTROL_0_TX_PI_LOOP_TIMING_EN_SHIFT 1 9572 9573 /* TX_PI :: tx_pi_control_0 :: tx_pi_en [00:00] */ 9574 #define TX_PI_TX_PI_CONTROL_0_TX_PI_EN_MASK 0x0001 9575 #define TX_PI_TX_PI_CONTROL_0_TX_PI_EN_ALIGN 0 9576 #define TX_PI_TX_PI_CONTROL_0_TX_PI_EN_BITS 1 9577 #define TX_PI_TX_PI_CONTROL_0_TX_PI_EN_SHIFT 0 9578 9579 9580 /**************************************************************************** 9581 * TX_PI :: tx_pi_control_1 9582 */ 9583 /* TX_PI :: tx_pi_control_1 :: reserved0 [15:15] */ 9584 #define TX_PI_TX_PI_CONTROL_1_RESERVED0_MASK 0x8000 9585 #define TX_PI_TX_PI_CONTROL_1_RESERVED0_ALIGN 0 9586 #define TX_PI_TX_PI_CONTROL_1_RESERVED0_BITS 1 9587 #define TX_PI_TX_PI_CONTROL_1_RESERVED0_SHIFT 15 9588 9589 /* TX_PI :: tx_pi_control_1 :: tx_pi_freq_override_val [14:00] */ 9590 #define TX_PI_TX_PI_CONTROL_1_TX_PI_FREQ_OVERRIDE_VAL_MASK 0x7fff 9591 #define TX_PI_TX_PI_CONTROL_1_TX_PI_FREQ_OVERRIDE_VAL_ALIGN 0 9592 #define TX_PI_TX_PI_CONTROL_1_TX_PI_FREQ_OVERRIDE_VAL_BITS 15 9593 #define TX_PI_TX_PI_CONTROL_1_TX_PI_FREQ_OVERRIDE_VAL_SHIFT 0 9594 9595 9596 /**************************************************************************** 9597 * TX_PI :: tx_pi_control_2 9598 */ 9599 /* TX_PI :: tx_pi_control_2 :: reserved0 [15:12] */ 9600 #define TX_PI_TX_PI_CONTROL_2_RESERVED0_MASK 0xf000 9601 #define TX_PI_TX_PI_CONTROL_2_RESERVED0_ALIGN 0 9602 #define TX_PI_TX_PI_CONTROL_2_RESERVED0_BITS 4 9603 #define TX_PI_TX_PI_CONTROL_2_RESERVED0_SHIFT 12 9604 9605 /* TX_PI :: tx_pi_control_2 :: tx_pi_jit_amp [11:06] */ 9606 #define TX_PI_TX_PI_CONTROL_2_TX_PI_JIT_AMP_MASK 0x0fc0 9607 #define TX_PI_TX_PI_CONTROL_2_TX_PI_JIT_AMP_ALIGN 0 9608 #define TX_PI_TX_PI_CONTROL_2_TX_PI_JIT_AMP_BITS 6 9609 #define TX_PI_TX_PI_CONTROL_2_TX_PI_JIT_AMP_SHIFT 6 9610 9611 /* TX_PI :: tx_pi_control_2 :: tx_pi_jit_freq_idx [05:00] */ 9612 #define TX_PI_TX_PI_CONTROL_2_TX_PI_JIT_FREQ_IDX_MASK 0x003f 9613 #define TX_PI_TX_PI_CONTROL_2_TX_PI_JIT_FREQ_IDX_ALIGN 0 9614 #define TX_PI_TX_PI_CONTROL_2_TX_PI_JIT_FREQ_IDX_BITS 6 9615 #define TX_PI_TX_PI_CONTROL_2_TX_PI_JIT_FREQ_IDX_SHIFT 0 9616 9617 9618 /**************************************************************************** 9619 * TX_PI :: tx_pi_control_3 9620 */ 9621 /* TX_PI :: tx_pi_control_3 :: reserved0 [15:15] */ 9622 #define TX_PI_TX_PI_CONTROL_3_RESERVED0_MASK 0x8000 9623 #define TX_PI_TX_PI_CONTROL_3_RESERVED0_ALIGN 0 9624 #define TX_PI_TX_PI_CONTROL_3_RESERVED0_BITS 1 9625 #define TX_PI_TX_PI_CONTROL_3_RESERVED0_SHIFT 15 9626 9627 /* TX_PI :: tx_pi_control_3 :: tx_pi_ext_phase_bwsel_integ [14:12] */ 9628 #define TX_PI_TX_PI_CONTROL_3_TX_PI_EXT_PHASE_BWSEL_INTEG_MASK 0x7000 9629 #define TX_PI_TX_PI_CONTROL_3_TX_PI_EXT_PHASE_BWSEL_INTEG_ALIGN 0 9630 #define TX_PI_TX_PI_CONTROL_3_TX_PI_EXT_PHASE_BWSEL_INTEG_BITS 3 9631 #define TX_PI_TX_PI_CONTROL_3_TX_PI_EXT_PHASE_BWSEL_INTEG_SHIFT 12 9632 9633 /* TX_PI :: tx_pi_control_3 :: reserved1 [11:05] */ 9634 #define TX_PI_TX_PI_CONTROL_3_RESERVED1_MASK 0x0fe0 9635 #define TX_PI_TX_PI_CONTROL_3_RESERVED1_ALIGN 0 9636 #define TX_PI_TX_PI_CONTROL_3_RESERVED1_BITS 7 9637 #define TX_PI_TX_PI_CONTROL_3_RESERVED1_SHIFT 5 9638 9639 /* TX_PI :: tx_pi_control_3 :: tx_pi_phase_invert [04:04] */ 9640 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_INVERT_MASK 0x0010 9641 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_INVERT_ALIGN 0 9642 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_INVERT_BITS 1 9643 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_INVERT_SHIFT 4 9644 9645 /* TX_PI :: tx_pi_control_3 :: tx_pi_phase_step_osr [03:03] */ 9646 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STEP_OSR_MASK 0x0008 9647 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STEP_OSR_ALIGN 0 9648 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STEP_OSR_BITS 1 9649 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STEP_OSR_SHIFT 3 9650 9651 /* TX_PI :: tx_pi_control_3 :: tx_pi_phase_step_dir [02:02] */ 9652 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STEP_DIR_MASK 0x0004 9653 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STEP_DIR_ALIGN 0 9654 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STEP_DIR_BITS 1 9655 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STEP_DIR_SHIFT 2 9656 9657 /* TX_PI :: tx_pi_control_3 :: tx_pi_phase_strobe [01:01] */ 9658 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STROBE_MASK 0x0002 9659 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STROBE_ALIGN 0 9660 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STROBE_BITS 1 9661 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_STROBE_SHIFT 1 9662 9663 /* TX_PI :: tx_pi_control_3 :: tx_pi_phase_override [00:00] */ 9664 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_OVERRIDE_MASK 0x0001 9665 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_OVERRIDE_ALIGN 0 9666 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_OVERRIDE_BITS 1 9667 #define TX_PI_TX_PI_CONTROL_3_TX_PI_PHASE_OVERRIDE_SHIFT 0 9668 9669 9670 /**************************************************************************** 9671 * TX_PI :: tx_pi_control_4 9672 */ 9673 /* TX_PI :: tx_pi_control_4 :: reserved0 [15:03] */ 9674 #define TX_PI_TX_PI_CONTROL_4_RESERVED0_MASK 0xfff8 9675 #define TX_PI_TX_PI_CONTROL_4_RESERVED0_ALIGN 0 9676 #define TX_PI_TX_PI_CONTROL_4_RESERVED0_BITS 13 9677 #define TX_PI_TX_PI_CONTROL_4_RESERVED0_SHIFT 3 9678 9679 /* TX_PI :: tx_pi_control_4 :: tx_pi_frz_mode [02:02] */ 9680 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_MODE_MASK 0x0004 9681 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_MODE_ALIGN 0 9682 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_MODE_BITS 1 9683 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_MODE_SHIFT 2 9684 9685 /* TX_PI :: tx_pi_control_4 :: tx_pi_frz_frc_val [01:01] */ 9686 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_FRC_VAL_MASK 0x0002 9687 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_FRC_VAL_ALIGN 0 9688 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_FRC_VAL_BITS 1 9689 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_FRC_VAL_SHIFT 1 9690 9691 /* TX_PI :: tx_pi_control_4 :: tx_pi_frz_frc [00:00] */ 9692 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_FRC_MASK 0x0001 9693 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_FRC_ALIGN 0 9694 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_FRC_BITS 1 9695 #define TX_PI_TX_PI_CONTROL_4_TX_PI_FRZ_FRC_SHIFT 0 9696 9697 9698 /**************************************************************************** 9699 * TX_PI :: tx_pi_control_5 9700 */ 9701 /* TX_PI :: tx_pi_control_5 :: reserved0 [15:10] */ 9702 #define TX_PI_TX_PI_CONTROL_5_RESERVED0_MASK 0xfc00 9703 #define TX_PI_TX_PI_CONTROL_5_RESERVED0_ALIGN 0 9704 #define TX_PI_TX_PI_CONTROL_5_RESERVED0_BITS 6 9705 #define TX_PI_TX_PI_CONTROL_5_RESERVED0_SHIFT 10 9706 9707 /* TX_PI :: tx_pi_control_5 :: afe_tx_fifo_resetb_frc [09:09] */ 9708 #define TX_PI_TX_PI_CONTROL_5_AFE_TX_FIFO_RESETB_FRC_MASK 0x0200 9709 #define TX_PI_TX_PI_CONTROL_5_AFE_TX_FIFO_RESETB_FRC_ALIGN 0 9710 #define TX_PI_TX_PI_CONTROL_5_AFE_TX_FIFO_RESETB_FRC_BITS 1 9711 #define TX_PI_TX_PI_CONTROL_5_AFE_TX_FIFO_RESETB_FRC_SHIFT 9 9712 9713 /* TX_PI :: tx_pi_control_5 :: afe_tx_fifo_resetb [08:08] */ 9714 #define TX_PI_TX_PI_CONTROL_5_AFE_TX_FIFO_RESETB_MASK 0x0100 9715 #define TX_PI_TX_PI_CONTROL_5_AFE_TX_FIFO_RESETB_ALIGN 0 9716 #define TX_PI_TX_PI_CONTROL_5_AFE_TX_FIFO_RESETB_BITS 1 9717 #define TX_PI_TX_PI_CONTROL_5_AFE_TX_FIFO_RESETB_SHIFT 8 9718 9719 /* TX_PI :: tx_pi_control_5 :: reserved1 [07:03] */ 9720 #define TX_PI_TX_PI_CONTROL_5_RESERVED1_MASK 0x00f8 9721 #define TX_PI_TX_PI_CONTROL_5_RESERVED1_ALIGN 0 9722 #define TX_PI_TX_PI_CONTROL_5_RESERVED1_BITS 5 9723 #define TX_PI_TX_PI_CONTROL_5_RESERVED1_SHIFT 3 9724 9725 /* TX_PI :: tx_pi_control_5 :: tx_pi_pass_thru_sel [02:02] */ 9726 #define TX_PI_TX_PI_CONTROL_5_TX_PI_PASS_THRU_SEL_MASK 0x0004 9727 #define TX_PI_TX_PI_CONTROL_5_TX_PI_PASS_THRU_SEL_ALIGN 0 9728 #define TX_PI_TX_PI_CONTROL_5_TX_PI_PASS_THRU_SEL_BITS 1 9729 #define TX_PI_TX_PI_CONTROL_5_TX_PI_PASS_THRU_SEL_SHIFT 2 9730 9731 /* TX_PI :: tx_pi_control_5 :: tx_pi_hs_fifo_phserr_invert [01:01] */ 9732 #define TX_PI_TX_PI_CONTROL_5_TX_PI_HS_FIFO_PHSERR_INVERT_MASK 0x0002 9733 #define TX_PI_TX_PI_CONTROL_5_TX_PI_HS_FIFO_PHSERR_INVERT_ALIGN 0 9734 #define TX_PI_TX_PI_CONTROL_5_TX_PI_HS_FIFO_PHSERR_INVERT_BITS 1 9735 #define TX_PI_TX_PI_CONTROL_5_TX_PI_HS_FIFO_PHSERR_INVERT_SHIFT 1 9736 9737 /* TX_PI :: tx_pi_control_5 :: reserved2 [00:00] */ 9738 #define TX_PI_TX_PI_CONTROL_5_RESERVED2_MASK 0x0001 9739 #define TX_PI_TX_PI_CONTROL_5_RESERVED2_ALIGN 0 9740 #define TX_PI_TX_PI_CONTROL_5_RESERVED2_BITS 1 9741 #define TX_PI_TX_PI_CONTROL_5_RESERVED2_SHIFT 0 9742 9743 9744 /**************************************************************************** 9745 * TX_PI :: tx_pi_control_6 9746 */ 9747 /* TX_PI :: tx_pi_control_6 :: reserved0 [15:02] */ 9748 #define TX_PI_TX_PI_CONTROL_6_RESERVED0_MASK 0xfffc 9749 #define TX_PI_TX_PI_CONTROL_6_RESERVED0_ALIGN 0 9750 #define TX_PI_TX_PI_CONTROL_6_RESERVED0_BITS 14 9751 #define TX_PI_TX_PI_CONTROL_6_RESERVED0_SHIFT 2 9752 9753 /* TX_PI :: tx_pi_control_6 :: tx_pi_lane_sel [01:00] */ 9754 #define TX_PI_TX_PI_CONTROL_6_TX_PI_LANE_SEL_MASK 0x0003 9755 #define TX_PI_TX_PI_CONTROL_6_TX_PI_LANE_SEL_ALIGN 0 9756 #define TX_PI_TX_PI_CONTROL_6_TX_PI_LANE_SEL_BITS 2 9757 #define TX_PI_TX_PI_CONTROL_6_TX_PI_LANE_SEL_SHIFT 0 9758 9759 9760 /**************************************************************************** 9761 * TX_PI :: tx_pi_status_0 9762 */ 9763 /* TX_PI :: tx_pi_status_0 :: reserved0 [15:07] */ 9764 #define TX_PI_TX_PI_STATUS_0_RESERVED0_MASK 0xff80 9765 #define TX_PI_TX_PI_STATUS_0_RESERVED0_ALIGN 0 9766 #define TX_PI_TX_PI_STATUS_0_RESERVED0_BITS 9 9767 #define TX_PI_TX_PI_STATUS_0_RESERVED0_SHIFT 7 9768 9769 /* TX_PI :: tx_pi_status_0 :: tx_pi_phase_cntr [06:00] */ 9770 #define TX_PI_TX_PI_STATUS_0_TX_PI_PHASE_CNTR_MASK 0x007f 9771 #define TX_PI_TX_PI_STATUS_0_TX_PI_PHASE_CNTR_ALIGN 0 9772 #define TX_PI_TX_PI_STATUS_0_TX_PI_PHASE_CNTR_BITS 7 9773 #define TX_PI_TX_PI_STATUS_0_TX_PI_PHASE_CNTR_SHIFT 0 9774 9775 9776 /**************************************************************************** 9777 * TX_PI :: tx_pi_status_1 9778 */ 9779 /* TX_PI :: tx_pi_status_1 :: reserved0 [15:14] */ 9780 #define TX_PI_TX_PI_STATUS_1_RESERVED0_MASK 0xc000 9781 #define TX_PI_TX_PI_STATUS_1_RESERVED0_ALIGN 0 9782 #define TX_PI_TX_PI_STATUS_1_RESERVED0_BITS 2 9783 #define TX_PI_TX_PI_STATUS_1_RESERVED0_SHIFT 14 9784 9785 /* TX_PI :: tx_pi_status_1 :: tx_pi_integ1_reg [13:00] */ 9786 #define TX_PI_TX_PI_STATUS_1_TX_PI_INTEG1_REG_MASK 0x3fff 9787 #define TX_PI_TX_PI_STATUS_1_TX_PI_INTEG1_REG_ALIGN 0 9788 #define TX_PI_TX_PI_STATUS_1_TX_PI_INTEG1_REG_BITS 14 9789 #define TX_PI_TX_PI_STATUS_1_TX_PI_INTEG1_REG_SHIFT 0 9790 9791 9792 /**************************************************************************** 9793 * TX_PI :: tx_pi_status_2 9794 */ 9795 /* TX_PI :: tx_pi_status_2 :: reserved0 [15:15] */ 9796 #define TX_PI_TX_PI_STATUS_2_RESERVED0_MASK 0x8000 9797 #define TX_PI_TX_PI_STATUS_2_RESERVED0_ALIGN 0 9798 #define TX_PI_TX_PI_STATUS_2_RESERVED0_BITS 1 9799 #define TX_PI_TX_PI_STATUS_2_RESERVED0_SHIFT 15 9800 9801 /* TX_PI :: tx_pi_status_2 :: tx_pi_integ2_reg [14:00] */ 9802 #define TX_PI_TX_PI_STATUS_2_TX_PI_INTEG2_REG_MASK 0x7fff 9803 #define TX_PI_TX_PI_STATUS_2_TX_PI_INTEG2_REG_ALIGN 0 9804 #define TX_PI_TX_PI_STATUS_2_TX_PI_INTEG2_REG_BITS 15 9805 #define TX_PI_TX_PI_STATUS_2_TX_PI_INTEG2_REG_SHIFT 0 9806 9807 9808 /**************************************************************************** 9809 * TX_PI :: tx_pi_status_3 9810 */ 9811 /* TX_PI :: tx_pi_status_3 :: reserved0 [15:06] */ 9812 #define TX_PI_TX_PI_STATUS_3_RESERVED0_MASK 0xffc0 9813 #define TX_PI_TX_PI_STATUS_3_RESERVED0_ALIGN 0 9814 #define TX_PI_TX_PI_STATUS_3_RESERVED0_BITS 10 9815 #define TX_PI_TX_PI_STATUS_3_RESERVED0_SHIFT 6 9816 9817 /* TX_PI :: tx_pi_status_3 :: tx_pi_phase_err [05:00] */ 9818 #define TX_PI_TX_PI_STATUS_3_TX_PI_PHASE_ERR_MASK 0x003f 9819 #define TX_PI_TX_PI_STATUS_3_TX_PI_PHASE_ERR_ALIGN 0 9820 #define TX_PI_TX_PI_STATUS_3_TX_PI_PHASE_ERR_BITS 6 9821 #define TX_PI_TX_PI_STATUS_3_TX_PI_PHASE_ERR_SHIFT 0 9822 9823 9824 /**************************************************************************** 9825 * TX_PI :: tx_pi_status_4 9826 */ 9827 /* TX_PI :: tx_pi_status_4 :: reserved0 [15:02] */ 9828 #define TX_PI_TX_PI_STATUS_4_RESERVED0_MASK 0xfffc 9829 #define TX_PI_TX_PI_STATUS_4_RESERVED0_ALIGN 0 9830 #define TX_PI_TX_PI_STATUS_4_RESERVED0_BITS 14 9831 #define TX_PI_TX_PI_STATUS_4_RESERVED0_SHIFT 2 9832 9833 /* TX_PI :: tx_pi_status_4 :: st_afe_tx_fifo_resetb [01:01] */ 9834 #define TX_PI_TX_PI_STATUS_4_ST_AFE_TX_FIFO_RESETB_MASK 0x0002 9835 #define TX_PI_TX_PI_STATUS_4_ST_AFE_TX_FIFO_RESETB_ALIGN 0 9836 #define TX_PI_TX_PI_STATUS_4_ST_AFE_TX_FIFO_RESETB_BITS 1 9837 #define TX_PI_TX_PI_STATUS_4_ST_AFE_TX_FIFO_RESETB_SHIFT 1 9838 9839 /* TX_PI :: tx_pi_status_4 :: tx_pi_hs_fifo_phserr [00:00] */ 9840 #define TX_PI_TX_PI_STATUS_4_TX_PI_HS_FIFO_PHSERR_MASK 0x0001 9841 #define TX_PI_TX_PI_STATUS_4_TX_PI_HS_FIFO_PHSERR_ALIGN 0 9842 #define TX_PI_TX_PI_STATUS_4_TX_PI_HS_FIFO_PHSERR_BITS 1 9843 #define TX_PI_TX_PI_STATUS_4_TX_PI_HS_FIFO_PHSERR_SHIFT 0 9844 9845 9846 /**************************************************************************** 9847 * TX_PI :: tx_pi_tx_fifo_ovfb_status 9848 */ 9849 /* TX_PI :: tx_pi_tx_fifo_ovfb_status :: reserved0 [15:02] */ 9850 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_RESERVED0_MASK 0xfffc 9851 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_RESERVED0_ALIGN 0 9852 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_RESERVED0_BITS 14 9853 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_RESERVED0_SHIFT 2 9854 9855 /* TX_PI :: tx_pi_tx_fifo_ovfb_status :: tx_fifo_ovfb_fall_edge_lh [01:01] */ 9856 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_TX_FIFO_OVFB_FALL_EDGE_LH_MASK 0x0002 9857 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_TX_FIFO_OVFB_FALL_EDGE_LH_ALIGN 0 9858 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_TX_FIFO_OVFB_FALL_EDGE_LH_BITS 1 9859 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_TX_FIFO_OVFB_FALL_EDGE_LH_SHIFT 1 9860 9861 /* TX_PI :: tx_pi_tx_fifo_ovfb_status :: tx_fifo_ovfb [00:00] */ 9862 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_TX_FIFO_OVFB_MASK 0x0001 9863 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_TX_FIFO_OVFB_ALIGN 0 9864 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_TX_FIFO_OVFB_BITS 1 9865 #define TX_PI_TX_PI_TX_FIFO_OVFB_STATUS_TX_FIFO_OVFB_SHIFT 0 9866 9867 9868 /**************************************************************************** 9869 * merlin_gallardo_ckrst_ctrl_blk_CKRST_CTRL 9870 */ 9871 /**************************************************************************** 9872 * CKRST_CTRL :: OSR_MODE_CONTROL 9873 */ 9874 /* CKRST_CTRL :: OSR_MODE_CONTROL :: osr_mode_frc [15:15] */ 9875 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_MASK 0x8000 9876 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_ALIGN 0 9877 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_BITS 1 9878 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_FRC_SHIFT 15 9879 9880 /* CKRST_CTRL :: OSR_MODE_CONTROL :: reserved0 [14:04] */ 9881 #define CKRST_CTRL_OSR_MODE_CONTROL_RESERVED0_MASK 0x7ff0 9882 #define CKRST_CTRL_OSR_MODE_CONTROL_RESERVED0_ALIGN 0 9883 #define CKRST_CTRL_OSR_MODE_CONTROL_RESERVED0_BITS 11 9884 #define CKRST_CTRL_OSR_MODE_CONTROL_RESERVED0_SHIFT 4 9885 9886 /* CKRST_CTRL :: OSR_MODE_CONTROL :: osr_mode [03:00] */ 9887 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_MASK 0x000f 9888 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_ALIGN 0 9889 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_BITS 4 9890 #define CKRST_CTRL_OSR_MODE_CONTROL_OSR_MODE_SHIFT 0 9891 9892 9893 /**************************************************************************** 9894 * CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL 9895 */ 9896 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: pmd_rx_clk_vld_frc_val [15:15] */ 9897 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_RX_CLK_VLD_FRC_VAL_MASK 0x8000 9898 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_RX_CLK_VLD_FRC_VAL_ALIGN 0 9899 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_RX_CLK_VLD_FRC_VAL_BITS 1 9900 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_RX_CLK_VLD_FRC_VAL_SHIFT 15 9901 9902 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: pmd_rx_clk_vld_frc [14:14] */ 9903 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_RX_CLK_VLD_FRC_MASK 0x4000 9904 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_RX_CLK_VLD_FRC_ALIGN 0 9905 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_RX_CLK_VLD_FRC_BITS 1 9906 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_RX_CLK_VLD_FRC_SHIFT 14 9907 9908 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: pmd_tx_clk_vld_frc_val [13:13] */ 9909 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_TX_CLK_VLD_FRC_VAL_MASK 0x2000 9910 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_TX_CLK_VLD_FRC_VAL_ALIGN 0 9911 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_TX_CLK_VLD_FRC_VAL_BITS 1 9912 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_TX_CLK_VLD_FRC_VAL_SHIFT 13 9913 9914 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: pmd_tx_clk_vld_frc [12:12] */ 9915 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_TX_CLK_VLD_FRC_MASK 0x1000 9916 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_TX_CLK_VLD_FRC_ALIGN 0 9917 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_TX_CLK_VLD_FRC_BITS 1 9918 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_PMD_TX_CLK_VLD_FRC_SHIFT 12 9919 9920 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_tx_s_pwrdn [11:11] */ 9921 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_PWRDN_MASK 0x0800 9922 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_PWRDN_ALIGN 0 9923 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_PWRDN_BITS 1 9924 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_PWRDN_SHIFT 11 9925 9926 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_tx_s_comclk_frc [10:10] */ 9927 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_COMCLK_FRC_MASK 0x0400 9928 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_COMCLK_FRC_ALIGN 0 9929 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_COMCLK_FRC_BITS 1 9930 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_COMCLK_FRC_SHIFT 10 9931 9932 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_tx_s_comclk_sel [09:09] */ 9933 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_COMCLK_SEL_MASK 0x0200 9934 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_COMCLK_SEL_ALIGN 0 9935 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_COMCLK_SEL_BITS 1 9936 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_COMCLK_SEL_SHIFT 9 9937 9938 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_tx_s_clkgate_frc [08:08] */ 9939 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_CLKGATE_FRC_MASK 0x0100 9940 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_CLKGATE_FRC_ALIGN 0 9941 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_CLKGATE_FRC_BITS 1 9942 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_CLKGATE_FRC_SHIFT 8 9943 9944 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_tx_s_clkgate [07:07] */ 9945 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_CLKGATE_MASK 0x0080 9946 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_CLKGATE_ALIGN 0 9947 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_CLKGATE_BITS 1 9948 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_TX_S_CLKGATE_SHIFT 7 9949 9950 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_rx_s_pwrdn [06:06] */ 9951 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_PWRDN_MASK 0x0040 9952 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_PWRDN_ALIGN 0 9953 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_PWRDN_BITS 1 9954 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_PWRDN_SHIFT 6 9955 9956 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_rx_s_comclk_frc [05:05] */ 9957 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_COMCLK_FRC_MASK 0x0020 9958 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_COMCLK_FRC_ALIGN 0 9959 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_COMCLK_FRC_BITS 1 9960 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_COMCLK_FRC_SHIFT 5 9961 9962 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_rx_s_comclk_sel [04:04] */ 9963 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_COMCLK_SEL_MASK 0x0010 9964 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_COMCLK_SEL_ALIGN 0 9965 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_COMCLK_SEL_BITS 1 9966 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_COMCLK_SEL_SHIFT 4 9967 9968 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_rx_s_clkgate_frc [03:03] */ 9969 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_CLKGATE_FRC_MASK 0x0008 9970 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_CLKGATE_FRC_ALIGN 0 9971 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_CLKGATE_FRC_BITS 1 9972 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_CLKGATE_FRC_SHIFT 3 9973 9974 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_rx_s_clkgate [02:02] */ 9975 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_CLKGATE_MASK 0x0004 9976 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_CLKGATE_ALIGN 0 9977 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_CLKGATE_BITS 1 9978 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_RX_S_CLKGATE_SHIFT 2 9979 9980 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_dp_s_rstb [01:01] */ 9981 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_DP_S_RSTB_MASK 0x0002 9982 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_DP_S_RSTB_ALIGN 0 9983 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_DP_S_RSTB_BITS 1 9984 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_DP_S_RSTB_SHIFT 1 9985 9986 /* CKRST_CTRL :: LANE_CLK_RESET_N_POWERDOWN_CONTROL :: ln_s_rstb [00:00] */ 9987 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_S_RSTB_MASK 0x0001 9988 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_S_RSTB_ALIGN 0 9989 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_S_RSTB_BITS 1 9990 #define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_LN_S_RSTB_SHIFT 0 9991 9992 9993 /**************************************************************************** 9994 * CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL 9995 */ 9996 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: reserved0 [15:11] */ 9997 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_RESERVED0_MASK 0xf800 9998 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_RESERVED0_ALIGN 0 9999 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_RESERVED0_BITS 5 10000 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_RESERVED0_SHIFT 11 10001 10002 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_txclk_reset_frc_val [10:10] */ 10003 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TXCLK_RESET_FRC_VAL_MASK 0x0400 10004 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TXCLK_RESET_FRC_VAL_ALIGN 0 10005 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TXCLK_RESET_FRC_VAL_BITS 1 10006 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TXCLK_RESET_FRC_VAL_SHIFT 10 10007 10008 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_txclk_reset_frc [09:09] */ 10009 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TXCLK_RESET_FRC_MASK 0x0200 10010 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TXCLK_RESET_FRC_ALIGN 0 10011 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TXCLK_RESET_FRC_BITS 1 10012 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TXCLK_RESET_FRC_SHIFT 9 10013 10014 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_SigDetPwrDn [08:08] */ 10015 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_SIGDETPWRDN_MASK 0x0100 10016 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_SIGDETPWRDN_ALIGN 0 10017 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_SIGDETPWRDN_BITS 1 10018 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_SIGDETPWRDN_SHIFT 8 10019 10020 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_tx_reset_frc_val [07:07] */ 10021 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_VAL_MASK 0x0080 10022 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_VAL_ALIGN 0 10023 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_VAL_BITS 1 10024 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_VAL_SHIFT 7 10025 10026 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_tx_reset_frc [06:06] */ 10027 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_MASK 0x0040 10028 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_ALIGN 0 10029 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_BITS 1 10030 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_RESET_FRC_SHIFT 6 10031 10032 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_tx_pwrdn_frc_val [05:05] */ 10033 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_VAL_MASK 0x0020 10034 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_VAL_ALIGN 0 10035 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_VAL_BITS 1 10036 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_VAL_SHIFT 5 10037 10038 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_tx_pwrdn_frc [04:04] */ 10039 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_MASK 0x0010 10040 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_ALIGN 0 10041 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_BITS 1 10042 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_TX_PWRDN_FRC_SHIFT 4 10043 10044 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_rx_reset_frc_val [03:03] */ 10045 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_VAL_MASK 0x0008 10046 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_VAL_ALIGN 0 10047 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_VAL_BITS 1 10048 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_VAL_SHIFT 3 10049 10050 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_rx_reset_frc [02:02] */ 10051 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_MASK 0x0004 10052 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_ALIGN 0 10053 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_BITS 1 10054 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_RESET_FRC_SHIFT 2 10055 10056 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_rx_pwrdn_frc_val [01:01] */ 10057 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_VAL_MASK 0x0002 10058 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_VAL_ALIGN 0 10059 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_VAL_BITS 1 10060 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_VAL_SHIFT 1 10061 10062 /* CKRST_CTRL :: LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL :: afe_rx_pwrdn_frc [00:00] */ 10063 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_MASK 0x0001 10064 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_ALIGN 0 10065 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_BITS 1 10066 #define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_AFE_RX_PWRDN_FRC_SHIFT 0 10067 10068 10069 /**************************************************************************** 10070 * CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL 10071 */ 10072 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: reserved0 [15:04] */ 10073 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_RESERVED0_MASK 0xfff0 10074 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_RESERVED0_ALIGN 0 10075 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_RESERVED0_BITS 12 10076 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_RESERVED0_SHIFT 4 10077 10078 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: pmd_ln_tx_h_pwrdn_pkill [03:03] */ 10079 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_TX_H_PWRDN_PKILL_MASK 0x0008 10080 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_TX_H_PWRDN_PKILL_ALIGN 0 10081 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_TX_H_PWRDN_PKILL_BITS 1 10082 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_TX_H_PWRDN_PKILL_SHIFT 3 10083 10084 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: pmd_ln_rx_h_pwrdn_pkill [02:02] */ 10085 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_RX_H_PWRDN_PKILL_MASK 0x0004 10086 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_RX_H_PWRDN_PKILL_ALIGN 0 10087 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_RX_H_PWRDN_PKILL_BITS 1 10088 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_RX_H_PWRDN_PKILL_SHIFT 2 10089 10090 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: pmd_ln_dp_h_rstb_pkill [01:01] */ 10091 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_DP_H_RSTB_PKILL_MASK 0x0002 10092 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_DP_H_RSTB_PKILL_ALIGN 0 10093 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_DP_H_RSTB_PKILL_BITS 1 10094 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_DP_H_RSTB_PKILL_SHIFT 1 10095 10096 /* CKRST_CTRL :: LANE_RESET_N_PWRDN_PIN_KILL_CONTROL :: pmd_ln_h_rstb_pkill [00:00] */ 10097 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_H_RSTB_PKILL_MASK 0x0001 10098 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_H_RSTB_PKILL_ALIGN 0 10099 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_H_RSTB_PKILL_BITS 1 10100 #define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_PMD_LN_H_RSTB_PKILL_SHIFT 0 10101 10102 10103 /**************************************************************************** 10104 * CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL 10105 */ 10106 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: reserved0 [15:10] */ 10107 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED0_MASK 0xfc00 10108 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED0_ALIGN 0 10109 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED0_BITS 6 10110 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED0_SHIFT 10 10111 10112 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: ln_tx_dp_s_rstb [09:09] */ 10113 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_DP_S_RSTB_MASK 0x0200 10114 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_DP_S_RSTB_ALIGN 0 10115 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_DP_S_RSTB_BITS 1 10116 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_DP_S_RSTB_SHIFT 9 10117 10118 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: ln_tx_s_rstb [08:08] */ 10119 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_S_RSTB_MASK 0x0100 10120 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_S_RSTB_ALIGN 0 10121 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_S_RSTB_BITS 1 10122 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_TX_S_RSTB_SHIFT 8 10123 10124 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: reserved1 [07:03] */ 10125 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED1_MASK 0x00f8 10126 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED1_ALIGN 0 10127 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED1_BITS 5 10128 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_RESERVED1_SHIFT 3 10129 10130 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: sigdet_dp_rstb_en [02:02] */ 10131 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_SIGDET_DP_RSTB_EN_MASK 0x0004 10132 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_SIGDET_DP_RSTB_EN_ALIGN 0 10133 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_SIGDET_DP_RSTB_EN_BITS 1 10134 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_SIGDET_DP_RSTB_EN_SHIFT 2 10135 10136 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: ln_rx_dp_s_rstb [01:01] */ 10137 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_DP_S_RSTB_MASK 0x0002 10138 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_DP_S_RSTB_ALIGN 0 10139 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_DP_S_RSTB_BITS 1 10140 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_DP_S_RSTB_SHIFT 1 10141 10142 /* CKRST_CTRL :: LANE_DEBUG_RESET_CONTROL :: ln_rx_s_rstb [00:00] */ 10143 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_S_RSTB_MASK 0x0001 10144 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_S_RSTB_ALIGN 0 10145 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_S_RSTB_BITS 1 10146 #define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL_LN_RX_S_RSTB_SHIFT 0 10147 10148 10149 /**************************************************************************** 10150 * CKRST_CTRL :: UC_ACK_LANE_CONTROL 10151 */ 10152 /* CKRST_CTRL :: UC_ACK_LANE_CONTROL :: reserved0 [15:02] */ 10153 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_RESERVED0_MASK 0xfffc 10154 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_RESERVED0_ALIGN 0 10155 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_RESERVED0_BITS 14 10156 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_RESERVED0_SHIFT 2 10157 10158 /* CKRST_CTRL :: UC_ACK_LANE_CONTROL :: uc_ack_lane_dp_reset [01:01] */ 10159 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_DP_RESET_MASK 0x0002 10160 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_DP_RESET_ALIGN 0 10161 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_DP_RESET_BITS 1 10162 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_DP_RESET_SHIFT 1 10163 10164 /* CKRST_CTRL :: UC_ACK_LANE_CONTROL :: uc_ack_lane_cfg_done [00:00] */ 10165 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_CFG_DONE_MASK 0x0001 10166 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_CFG_DONE_ALIGN 0 10167 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_CFG_DONE_BITS 1 10168 #define CKRST_CTRL_UC_ACK_LANE_CONTROL_UC_ACK_LANE_CFG_DONE_SHIFT 0 10169 10170 10171 /**************************************************************************** 10172 * CKRST_CTRL :: LANE_REG_RESET_OCCURRED_CONTROL 10173 */ 10174 /* CKRST_CTRL :: LANE_REG_RESET_OCCURRED_CONTROL :: reserved0 [15:01] */ 10175 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_RESERVED0_MASK 0xfffe 10176 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_RESERVED0_ALIGN 0 10177 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_RESERVED0_BITS 15 10178 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_RESERVED0_SHIFT 1 10179 10180 /* CKRST_CTRL :: LANE_REG_RESET_OCCURRED_CONTROL :: lane_reg_reset_occurred [00:00] */ 10181 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_LANE_REG_RESET_OCCURRED_MASK 0x0001 10182 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_LANE_REG_RESET_OCCURRED_ALIGN 0 10183 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_LANE_REG_RESET_OCCURRED_BITS 1 10184 #define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL_LANE_REG_RESET_OCCURRED_SHIFT 0 10185 10186 10187 /**************************************************************************** 10188 * CKRST_CTRL :: PMD_LANE_MODE_STATUS 10189 */ 10190 /* CKRST_CTRL :: PMD_LANE_MODE_STATUS :: reserved0 [15:08] */ 10191 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_RESERVED0_MASK 0xff00 10192 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_RESERVED0_ALIGN 0 10193 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_RESERVED0_BITS 8 10194 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_RESERVED0_SHIFT 8 10195 10196 /* CKRST_CTRL :: PMD_LANE_MODE_STATUS :: pmd_lane_mode [07:00] */ 10197 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_PMD_LANE_MODE_MASK 0x00ff 10198 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_PMD_LANE_MODE_ALIGN 0 10199 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_PMD_LANE_MODE_BITS 8 10200 #define CKRST_CTRL_PMD_LANE_MODE_STATUS_PMD_LANE_MODE_SHIFT 0 10201 10202 10203 /**************************************************************************** 10204 * CKRST_CTRL :: LANE_DP_RESET_STATE_STATUS 10205 */ 10206 /* CKRST_CTRL :: LANE_DP_RESET_STATE_STATUS :: reserved0 [15:03] */ 10207 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_RESERVED0_MASK 0xfff8 10208 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_RESERVED0_ALIGN 0 10209 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_RESERVED0_BITS 13 10210 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_RESERVED0_SHIFT 3 10211 10212 /* CKRST_CTRL :: LANE_DP_RESET_STATE_STATUS :: lane_dp_reset_state [02:00] */ 10213 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_LANE_DP_RESET_STATE_MASK 0x0007 10214 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_LANE_DP_RESET_STATE_ALIGN 0 10215 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_LANE_DP_RESET_STATE_BITS 3 10216 #define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS_LANE_DP_RESET_STATE_SHIFT 0 10217 10218 10219 /**************************************************************************** 10220 * CKRST_CTRL :: LN_MASK 10221 */ 10222 /* CKRST_CTRL :: LN_MASK :: reserved0 [15:01] */ 10223 #define CKRST_CTRL_LN_MASK_RESERVED0_MASK 0xfffe 10224 #define CKRST_CTRL_LN_MASK_RESERVED0_ALIGN 0 10225 #define CKRST_CTRL_LN_MASK_RESERVED0_BITS 15 10226 #define CKRST_CTRL_LN_MASK_RESERVED0_SHIFT 1 10227 10228 /* CKRST_CTRL :: LN_MASK :: ln_mask [00:00] */ 10229 #define CKRST_CTRL_LN_MASK_LN_MASK_MASK 0x0001 10230 #define CKRST_CTRL_LN_MASK_LN_MASK_ALIGN 0 10231 #define CKRST_CTRL_LN_MASK_LN_MASK_BITS 1 10232 #define CKRST_CTRL_LN_MASK_LN_MASK_SHIFT 0 10233 10234 10235 /**************************************************************************** 10236 * CKRST_CTRL :: OSR_MODE_STATUS 10237 */ 10238 /* CKRST_CTRL :: OSR_MODE_STATUS :: reserved0 [15:04] */ 10239 #define CKRST_CTRL_OSR_MODE_STATUS_RESERVED0_MASK 0xfff0 10240 #define CKRST_CTRL_OSR_MODE_STATUS_RESERVED0_ALIGN 0 10241 #define CKRST_CTRL_OSR_MODE_STATUS_RESERVED0_BITS 12 10242 #define CKRST_CTRL_OSR_MODE_STATUS_RESERVED0_SHIFT 4 10243 10244 /* CKRST_CTRL :: OSR_MODE_STATUS :: st_osr_mode [03:00] */ 10245 #define CKRST_CTRL_OSR_MODE_STATUS_ST_OSR_MODE_MASK 0x000f 10246 #define CKRST_CTRL_OSR_MODE_STATUS_ST_OSR_MODE_ALIGN 0 10247 #define CKRST_CTRL_OSR_MODE_STATUS_ST_OSR_MODE_BITS 4 10248 #define CKRST_CTRL_OSR_MODE_STATUS_ST_OSR_MODE_SHIFT 0 10249 10250 10251 /**************************************************************************** 10252 * merlin_gallardo_ams_blk_AMS_RX 10253 */ 10254 /**************************************************************************** 10255 * AMS_RX :: RX_CTRL_0 10256 */ 10257 /* AMS_RX :: RX_CTRL_0 :: term_lowZvdd [15:15] */ 10258 #define AMS_RX_RX_CTRL_0_TERM_LOWZVDD_MASK 0x8000 10259 #define AMS_RX_RX_CTRL_0_TERM_LOWZVDD_ALIGN 0 10260 #define AMS_RX_RX_CTRL_0_TERM_LOWZVDD_BITS 1 10261 #define AMS_RX_RX_CTRL_0_TERM_LOWZVDD_SHIFT 15 10262 10263 /* AMS_RX :: RX_CTRL_0 :: term_lowZgnd [14:14] */ 10264 #define AMS_RX_RX_CTRL_0_TERM_LOWZGND_MASK 0x4000 10265 #define AMS_RX_RX_CTRL_0_TERM_LOWZGND_ALIGN 0 10266 #define AMS_RX_RX_CTRL_0_TERM_LOWZGND_BITS 1 10267 #define AMS_RX_RX_CTRL_0_TERM_LOWZGND_SHIFT 14 10268 10269 /* AMS_RX :: RX_CTRL_0 :: term_cmult_ena [13:13] */ 10270 #define AMS_RX_RX_CTRL_0_TERM_CMULT_ENA_MASK 0x2000 10271 #define AMS_RX_RX_CTRL_0_TERM_CMULT_ENA_ALIGN 0 10272 #define AMS_RX_RX_CTRL_0_TERM_CMULT_ENA_BITS 1 10273 #define AMS_RX_RX_CTRL_0_TERM_CMULT_ENA_SHIFT 13 10274 10275 /* AMS_RX :: RX_CTRL_0 :: term_cm_ena [12:12] */ 10276 #define AMS_RX_RX_CTRL_0_TERM_CM_ENA_MASK 0x1000 10277 #define AMS_RX_RX_CTRL_0_TERM_CM_ENA_ALIGN 0 10278 #define AMS_RX_RX_CTRL_0_TERM_CM_ENA_BITS 1 10279 #define AMS_RX_RX_CTRL_0_TERM_CM_ENA_SHIFT 12 10280 10281 /* AMS_RX :: RX_CTRL_0 :: en_rxck_test [11:10] */ 10282 #define AMS_RX_RX_CTRL_0_EN_RXCK_TEST_MASK 0x0c00 10283 #define AMS_RX_RX_CTRL_0_EN_RXCK_TEST_ALIGN 0 10284 #define AMS_RX_RX_CTRL_0_EN_RXCK_TEST_BITS 2 10285 #define AMS_RX_RX_CTRL_0_EN_RXCK_TEST_SHIFT 10 10286 10287 /* AMS_RX :: RX_CTRL_0 :: en_rxck_testport [09:09] */ 10288 #define AMS_RX_RX_CTRL_0_EN_RXCK_TESTPORT_MASK 0x0200 10289 #define AMS_RX_RX_CTRL_0_EN_RXCK_TESTPORT_ALIGN 0 10290 #define AMS_RX_RX_CTRL_0_EN_RXCK_TESTPORT_BITS 1 10291 #define AMS_RX_RX_CTRL_0_EN_RXCK_TESTPORT_SHIFT 9 10292 10293 /* AMS_RX :: RX_CTRL_0 :: ams_8_5 [08:05] */ 10294 #define AMS_RX_RX_CTRL_0_AMS_8_5_MASK 0x01e0 10295 #define AMS_RX_RX_CTRL_0_AMS_8_5_ALIGN 0 10296 #define AMS_RX_RX_CTRL_0_AMS_8_5_BITS 4 10297 #define AMS_RX_RX_CTRL_0_AMS_8_5_SHIFT 5 10298 10299 /* AMS_RX :: RX_CTRL_0 :: sigdet_modesel [04:04] */ 10300 #define AMS_RX_RX_CTRL_0_SIGDET_MODESEL_MASK 0x0010 10301 #define AMS_RX_RX_CTRL_0_SIGDET_MODESEL_ALIGN 0 10302 #define AMS_RX_RX_CTRL_0_SIGDET_MODESEL_BITS 1 10303 #define AMS_RX_RX_CTRL_0_SIGDET_MODESEL_SHIFT 4 10304 10305 /* AMS_RX :: RX_CTRL_0 :: sigdet_bypass [03:03] */ 10306 #define AMS_RX_RX_CTRL_0_SIGDET_BYPASS_MASK 0x0008 10307 #define AMS_RX_RX_CTRL_0_SIGDET_BYPASS_ALIGN 0 10308 #define AMS_RX_RX_CTRL_0_SIGDET_BYPASS_BITS 1 10309 #define AMS_RX_RX_CTRL_0_SIGDET_BYPASS_SHIFT 3 10310 10311 /* AMS_RX :: RX_CTRL_0 :: sigdet_pwrdn [02:02] */ 10312 #define AMS_RX_RX_CTRL_0_SIGDET_PWRDN_MASK 0x0004 10313 #define AMS_RX_RX_CTRL_0_SIGDET_PWRDN_ALIGN 0 10314 #define AMS_RX_RX_CTRL_0_SIGDET_PWRDN_BITS 1 10315 #define AMS_RX_RX_CTRL_0_SIGDET_PWRDN_SHIFT 2 10316 10317 /* AMS_RX :: RX_CTRL_0 :: ams_spare_0_0 [01:00] */ 10318 #define AMS_RX_RX_CTRL_0_AMS_SPARE_0_0_MASK 0x0003 10319 #define AMS_RX_RX_CTRL_0_AMS_SPARE_0_0_ALIGN 0 10320 #define AMS_RX_RX_CTRL_0_AMS_SPARE_0_0_BITS 2 10321 #define AMS_RX_RX_CTRL_0_AMS_SPARE_0_0_SHIFT 0 10322 10323 10324 /**************************************************************************** 10325 * AMS_RX :: RX_CTRL_1 10326 */ 10327 /* AMS_RX :: RX_CTRL_1 :: reserved0 [15:14] */ 10328 #define AMS_RX_RX_CTRL_1_RESERVED0_MASK 0xc000 10329 #define AMS_RX_RX_CTRL_1_RESERVED0_ALIGN 0 10330 #define AMS_RX_RX_CTRL_1_RESERVED0_BITS 2 10331 #define AMS_RX_RX_CTRL_1_RESERVED0_SHIFT 14 10332 10333 /* AMS_RX :: RX_CTRL_1 :: curr_dfe_taps [13:11] */ 10334 #define AMS_RX_RX_CTRL_1_CURR_DFE_TAPS_MASK 0x3800 10335 #define AMS_RX_RX_CTRL_1_CURR_DFE_TAPS_ALIGN 0 10336 #define AMS_RX_RX_CTRL_1_CURR_DFE_TAPS_BITS 3 10337 #define AMS_RX_RX_CTRL_1_CURR_DFE_TAPS_SHIFT 11 10338 10339 /* AMS_RX :: RX_CTRL_1 :: curr_vga [10:08] */ 10340 #define AMS_RX_RX_CTRL_1_CURR_VGA_MASK 0x0700 10341 #define AMS_RX_RX_CTRL_1_CURR_VGA_ALIGN 0 10342 #define AMS_RX_RX_CTRL_1_CURR_VGA_BITS 3 10343 #define AMS_RX_RX_CTRL_1_CURR_VGA_SHIFT 8 10344 10345 /* AMS_RX :: RX_CTRL_1 :: curr_pi [07:05] */ 10346 #define AMS_RX_RX_CTRL_1_CURR_PI_MASK 0x00e0 10347 #define AMS_RX_RX_CTRL_1_CURR_PI_ALIGN 0 10348 #define AMS_RX_RX_CTRL_1_CURR_PI_BITS 3 10349 #define AMS_RX_RX_CTRL_1_CURR_PI_SHIFT 5 10350 10351 /* AMS_RX :: RX_CTRL_1 :: ams_spare_1_0 [04:01] */ 10352 #define AMS_RX_RX_CTRL_1_AMS_SPARE_1_0_MASK 0x001e 10353 #define AMS_RX_RX_CTRL_1_AMS_SPARE_1_0_ALIGN 0 10354 #define AMS_RX_RX_CTRL_1_AMS_SPARE_1_0_BITS 4 10355 #define AMS_RX_RX_CTRL_1_AMS_SPARE_1_0_SHIFT 1 10356 10357 /* AMS_RX :: RX_CTRL_1 :: vga_out_idle [00:00] */ 10358 #define AMS_RX_RX_CTRL_1_VGA_OUT_IDLE_MASK 0x0001 10359 #define AMS_RX_RX_CTRL_1_VGA_OUT_IDLE_ALIGN 0 10360 #define AMS_RX_RX_CTRL_1_VGA_OUT_IDLE_BITS 1 10361 #define AMS_RX_RX_CTRL_1_VGA_OUT_IDLE_SHIFT 0 10362 10363 10364 /**************************************************************************** 10365 * AMS_RX :: RX_CTRL_2 10366 */ 10367 /* AMS_RX :: RX_CTRL_2 :: sel_th4dfe [15:14] */ 10368 #define AMS_RX_RX_CTRL_2_SEL_TH4DFE_MASK 0xc000 10369 #define AMS_RX_RX_CTRL_2_SEL_TH4DFE_ALIGN 0 10370 #define AMS_RX_RX_CTRL_2_SEL_TH4DFE_BITS 2 10371 #define AMS_RX_RX_CTRL_2_SEL_TH4DFE_SHIFT 14 10372 10373 /* AMS_RX :: RX_CTRL_2 :: ams_spare_2_0 [13:09] */ 10374 #define AMS_RX_RX_CTRL_2_AMS_SPARE_2_0_MASK 0x3e00 10375 #define AMS_RX_RX_CTRL_2_AMS_SPARE_2_0_ALIGN 0 10376 #define AMS_RX_RX_CTRL_2_AMS_SPARE_2_0_BITS 5 10377 #define AMS_RX_RX_CTRL_2_AMS_SPARE_2_0_SHIFT 9 10378 10379 /* AMS_RX :: RX_CTRL_2 :: curr_dfe_summer [08:06] */ 10380 #define AMS_RX_RX_CTRL_2_CURR_DFE_SUMMER_MASK 0x01c0 10381 #define AMS_RX_RX_CTRL_2_CURR_DFE_SUMMER_ALIGN 0 10382 #define AMS_RX_RX_CTRL_2_CURR_DFE_SUMMER_BITS 3 10383 #define AMS_RX_RX_CTRL_2_CURR_DFE_SUMMER_SHIFT 6 10384 10385 /* AMS_RX :: RX_CTRL_2 :: curr_dfe_ref [05:03] */ 10386 #define AMS_RX_RX_CTRL_2_CURR_DFE_REF_MASK 0x0038 10387 #define AMS_RX_RX_CTRL_2_CURR_DFE_REF_ALIGN 0 10388 #define AMS_RX_RX_CTRL_2_CURR_DFE_REF_BITS 3 10389 #define AMS_RX_RX_CTRL_2_CURR_DFE_REF_SHIFT 3 10390 10391 /* AMS_RX :: RX_CTRL_2 :: curr_ctle [02:00] */ 10392 #define AMS_RX_RX_CTRL_2_CURR_CTLE_MASK 0x0007 10393 #define AMS_RX_RX_CTRL_2_CURR_CTLE_ALIGN 0 10394 #define AMS_RX_RX_CTRL_2_CURR_CTLE_BITS 3 10395 #define AMS_RX_RX_CTRL_2_CURR_CTLE_SHIFT 0 10396 10397 10398 /**************************************************************************** 10399 * AMS_RX :: RX_CTRL_3 10400 */ 10401 /* AMS_RX :: RX_CTRL_3 :: reserved0 [15:15] */ 10402 #define AMS_RX_RX_CTRL_3_RESERVED0_MASK 0x8000 10403 #define AMS_RX_RX_CTRL_3_RESERVED0_ALIGN 0 10404 #define AMS_RX_RX_CTRL_3_RESERVED0_BITS 1 10405 #define AMS_RX_RX_CTRL_3_RESERVED0_SHIFT 15 10406 10407 /* AMS_RX :: RX_CTRL_3 :: ll_en [14:14] */ 10408 #define AMS_RX_RX_CTRL_3_LL_EN_MASK 0x4000 10409 #define AMS_RX_RX_CTRL_3_LL_EN_ALIGN 0 10410 #define AMS_RX_RX_CTRL_3_LL_EN_BITS 1 10411 #define AMS_RX_RX_CTRL_3_LL_EN_SHIFT 14 10412 10413 /* AMS_RX :: RX_CTRL_3 :: seli1P25dfe [13:13] */ 10414 #define AMS_RX_RX_CTRL_3_SELI1P25DFE_MASK 0x2000 10415 #define AMS_RX_RX_CTRL_3_SELI1P25DFE_ALIGN 0 10416 #define AMS_RX_RX_CTRL_3_SELI1P25DFE_BITS 1 10417 #define AMS_RX_RX_CTRL_3_SELI1P25DFE_SHIFT 13 10418 10419 /* AMS_RX :: RX_CTRL_3 :: i4deadzone [12:12] */ 10420 #define AMS_RX_RX_CTRL_3_I4DEADZONE_MASK 0x1000 10421 #define AMS_RX_RX_CTRL_3_I4DEADZONE_ALIGN 0 10422 #define AMS_RX_RX_CTRL_3_I4DEADZONE_BITS 1 10423 #define AMS_RX_RX_CTRL_3_I4DEADZONE_SHIFT 12 10424 10425 /* AMS_RX :: RX_CTRL_3 :: curr_sigdet [11:09] */ 10426 #define AMS_RX_RX_CTRL_3_CURR_SIGDET_MASK 0x0e00 10427 #define AMS_RX_RX_CTRL_3_CURR_SIGDET_ALIGN 0 10428 #define AMS_RX_RX_CTRL_3_CURR_SIGDET_BITS 3 10429 #define AMS_RX_RX_CTRL_3_CURR_SIGDET_SHIFT 9 10430 10431 /* AMS_RX :: RX_CTRL_3 :: ams_spare_3_1 [08:06] */ 10432 #define AMS_RX_RX_CTRL_3_AMS_SPARE_3_1_MASK 0x01c0 10433 #define AMS_RX_RX_CTRL_3_AMS_SPARE_3_1_ALIGN 0 10434 #define AMS_RX_RX_CTRL_3_AMS_SPARE_3_1_BITS 3 10435 #define AMS_RX_RX_CTRL_3_AMS_SPARE_3_1_SHIFT 6 10436 10437 /* AMS_RX :: RX_CTRL_3 :: ams_spare_3_0 [05:03] */ 10438 #define AMS_RX_RX_CTRL_3_AMS_SPARE_3_0_MASK 0x0038 10439 #define AMS_RX_RX_CTRL_3_AMS_SPARE_3_0_ALIGN 0 10440 #define AMS_RX_RX_CTRL_3_AMS_SPARE_3_0_BITS 3 10441 #define AMS_RX_RX_CTRL_3_AMS_SPARE_3_0_SHIFT 3 10442 10443 /* AMS_RX :: RX_CTRL_3 :: en_clk16 [02:02] */ 10444 #define AMS_RX_RX_CTRL_3_EN_CLK16_MASK 0x0004 10445 #define AMS_RX_RX_CTRL_3_EN_CLK16_ALIGN 0 10446 #define AMS_RX_RX_CTRL_3_EN_CLK16_BITS 1 10447 #define AMS_RX_RX_CTRL_3_EN_CLK16_SHIFT 2 10448 10449 /* AMS_RX :: RX_CTRL_3 :: en_clk33 [01:01] */ 10450 #define AMS_RX_RX_CTRL_3_EN_CLK33_MASK 0x0002 10451 #define AMS_RX_RX_CTRL_3_EN_CLK33_ALIGN 0 10452 #define AMS_RX_RX_CTRL_3_EN_CLK33_BITS 1 10453 #define AMS_RX_RX_CTRL_3_EN_CLK33_SHIFT 1 10454 10455 /* AMS_RX :: RX_CTRL_3 :: en_vcctrl [00:00] */ 10456 #define AMS_RX_RX_CTRL_3_EN_VCCTRL_MASK 0x0001 10457 #define AMS_RX_RX_CTRL_3_EN_VCCTRL_ALIGN 0 10458 #define AMS_RX_RX_CTRL_3_EN_VCCTRL_BITS 1 10459 #define AMS_RX_RX_CTRL_3_EN_VCCTRL_SHIFT 0 10460 10461 10462 /**************************************************************************** 10463 * AMS_RX :: RX_CTRL_4 10464 */ 10465 /* AMS_RX :: RX_CTRL_4 :: vga_pon [15:12] */ 10466 #define AMS_RX_RX_CTRL_4_VGA_PON_MASK 0xf000 10467 #define AMS_RX_RX_CTRL_4_VGA_PON_ALIGN 0 10468 #define AMS_RX_RX_CTRL_4_VGA_PON_BITS 4 10469 #define AMS_RX_RX_CTRL_4_VGA_PON_SHIFT 12 10470 10471 /* AMS_RX :: RX_CTRL_4 :: oc_2x [11:11] */ 10472 #define AMS_RX_RX_CTRL_4_OC_2X_MASK 0x0800 10473 #define AMS_RX_RX_CTRL_4_OC_2X_ALIGN 0 10474 #define AMS_RX_RX_CTRL_4_OC_2X_BITS 1 10475 #define AMS_RX_RX_CTRL_4_OC_2X_SHIFT 11 10476 10477 /* AMS_RX :: RX_CTRL_4 :: ams_spare_4_0 [10:00] */ 10478 #define AMS_RX_RX_CTRL_4_AMS_SPARE_4_0_MASK 0x07ff 10479 #define AMS_RX_RX_CTRL_4_AMS_SPARE_4_0_ALIGN 0 10480 #define AMS_RX_RX_CTRL_4_AMS_SPARE_4_0_BITS 11 10481 #define AMS_RX_RX_CTRL_4_AMS_SPARE_4_0_SHIFT 0 10482 10483 10484 /**************************************************************************** 10485 * AMS_RX :: RX_CTRL_5 10486 */ 10487 /* AMS_RX :: RX_CTRL_5 :: ams_spare_5_0 [15:13] */ 10488 #define AMS_RX_RX_CTRL_5_AMS_SPARE_5_0_MASK 0xe000 10489 #define AMS_RX_RX_CTRL_5_AMS_SPARE_5_0_ALIGN 0 10490 #define AMS_RX_RX_CTRL_5_AMS_SPARE_5_0_BITS 3 10491 #define AMS_RX_RX_CTRL_5_AMS_SPARE_5_0_SHIFT 13 10492 10493 /* AMS_RX :: RX_CTRL_5 :: degcap_adj [12:10] */ 10494 #define AMS_RX_RX_CTRL_5_DEGCAP_ADJ_MASK 0x1c00 10495 #define AMS_RX_RX_CTRL_5_DEGCAP_ADJ_ALIGN 0 10496 #define AMS_RX_RX_CTRL_5_DEGCAP_ADJ_BITS 3 10497 #define AMS_RX_RX_CTRL_5_DEGCAP_ADJ_SHIFT 10 10498 10499 /* AMS_RX :: RX_CTRL_5 :: en_dfeclk [09:09] */ 10500 #define AMS_RX_RX_CTRL_5_EN_DFECLK_MASK 0x0200 10501 #define AMS_RX_RX_CTRL_5_EN_DFECLK_ALIGN 0 10502 #define AMS_RX_RX_CTRL_5_EN_DFECLK_BITS 1 10503 #define AMS_RX_RX_CTRL_5_EN_DFECLK_SHIFT 9 10504 10505 /* AMS_RX :: RX_CTRL_5 :: pkbst [08:07] */ 10506 #define AMS_RX_RX_CTRL_5_PKBST_MASK 0x0180 10507 #define AMS_RX_RX_CTRL_5_PKBST_ALIGN 0 10508 #define AMS_RX_RX_CTRL_5_PKBST_BITS 2 10509 #define AMS_RX_RX_CTRL_5_PKBST_SHIFT 7 10510 10511 /* AMS_RX :: RX_CTRL_5 :: curr_in_offset [06:04] */ 10512 #define AMS_RX_RX_CTRL_5_CURR_IN_OFFSET_MASK 0x0070 10513 #define AMS_RX_RX_CTRL_5_CURR_IN_OFFSET_ALIGN 0 10514 #define AMS_RX_RX_CTRL_5_CURR_IN_OFFSET_BITS 3 10515 #define AMS_RX_RX_CTRL_5_CURR_IN_OFFSET_SHIFT 4 10516 10517 /* AMS_RX :: RX_CTRL_5 :: rx_pon [03:00] */ 10518 #define AMS_RX_RX_CTRL_5_RX_PON_MASK 0x000f 10519 #define AMS_RX_RX_CTRL_5_RX_PON_ALIGN 0 10520 #define AMS_RX_RX_CTRL_5_RX_PON_BITS 4 10521 #define AMS_RX_RX_CTRL_5_RX_PON_SHIFT 0 10522 10523 10524 /**************************************************************************** 10525 * AMS_RX :: RX_CTRL_6 10526 */ 10527 /* AMS_RX :: RX_CTRL_6 :: reserved0 [15:03] */ 10528 #define AMS_RX_RX_CTRL_6_RESERVED0_MASK 0xfff8 10529 #define AMS_RX_RX_CTRL_6_RESERVED0_ALIGN 0 10530 #define AMS_RX_RX_CTRL_6_RESERVED0_BITS 13 10531 #define AMS_RX_RX_CTRL_6_RESERVED0_SHIFT 3 10532 10533 /* AMS_RX :: RX_CTRL_6 :: ams_spare_6_0 [02:00] */ 10534 #define AMS_RX_RX_CTRL_6_AMS_SPARE_6_0_MASK 0x0007 10535 #define AMS_RX_RX_CTRL_6_AMS_SPARE_6_0_ALIGN 0 10536 #define AMS_RX_RX_CTRL_6_AMS_SPARE_6_0_BITS 3 10537 #define AMS_RX_RX_CTRL_6_AMS_SPARE_6_0_SHIFT 0 10538 10539 10540 /**************************************************************************** 10541 * AMS_RX :: RX_INT 10542 */ 10543 /* AMS_RX :: RX_INT :: reserved0 [15:02] */ 10544 #define AMS_RX_RX_INT_RESERVED0_MASK 0xfffc 10545 #define AMS_RX_RX_INT_RESERVED0_ALIGN 0 10546 #define AMS_RX_RX_INT_RESERVED0_BITS 14 10547 #define AMS_RX_RX_INT_RESERVED0_SHIFT 2 10548 10549 /* AMS_RX :: RX_INT :: rxpon_sel [01:01] */ 10550 #define AMS_RX_RX_INT_RXPON_SEL_MASK 0x0002 10551 #define AMS_RX_RX_INT_RXPON_SEL_ALIGN 0 10552 #define AMS_RX_RX_INT_RXPON_SEL_BITS 1 10553 #define AMS_RX_RX_INT_RXPON_SEL_SHIFT 1 10554 10555 /* AMS_RX :: RX_INT :: vgapon_sel [00:00] */ 10556 #define AMS_RX_RX_INT_VGAPON_SEL_MASK 0x0001 10557 #define AMS_RX_RX_INT_VGAPON_SEL_ALIGN 0 10558 #define AMS_RX_RX_INT_VGAPON_SEL_BITS 1 10559 #define AMS_RX_RX_INT_VGAPON_SEL_SHIFT 0 10560 10561 10562 /**************************************************************************** 10563 * AMS_RX :: RX_STS 10564 */ 10565 /* AMS_RX :: RX_STS :: reserved0 [15:08] */ 10566 #define AMS_RX_RX_STS_RESERVED0_MASK 0xff00 10567 #define AMS_RX_RX_STS_RESERVED0_ALIGN 0 10568 #define AMS_RX_RX_STS_RESERVED0_BITS 8 10569 #define AMS_RX_RX_STS_RESERVED0_SHIFT 8 10570 10571 /* AMS_RX :: RX_STS :: vgapon_mux [07:04] */ 10572 #define AMS_RX_RX_STS_VGAPON_MUX_MASK 0x00f0 10573 #define AMS_RX_RX_STS_VGAPON_MUX_ALIGN 0 10574 #define AMS_RX_RX_STS_VGAPON_MUX_BITS 4 10575 #define AMS_RX_RX_STS_VGAPON_MUX_SHIFT 4 10576 10577 /* AMS_RX :: RX_STS :: rxpon_mux [03:00] */ 10578 #define AMS_RX_RX_STS_RXPON_MUX_MASK 0x000f 10579 #define AMS_RX_RX_STS_RXPON_MUX_ALIGN 0 10580 #define AMS_RX_RX_STS_RXPON_MUX_BITS 4 10581 #define AMS_RX_RX_STS_RXPON_MUX_SHIFT 0 10582 10583 10584 /**************************************************************************** 10585 * merlin_gallardo_ams_blk_AMS_TX 10586 */ 10587 /**************************************************************************** 10588 * AMS_TX :: TX_CTRL_0 10589 */ 10590 /* AMS_TX :: TX_CTRL_0 :: lowlatency_en [15:15] */ 10591 #define AMS_TX_TX_CTRL_0_LOWLATENCY_EN_MASK 0x8000 10592 #define AMS_TX_TX_CTRL_0_LOWLATENCY_EN_ALIGN 0 10593 #define AMS_TX_TX_CTRL_0_LOWLATENCY_EN_BITS 1 10594 #define AMS_TX_TX_CTRL_0_LOWLATENCY_EN_SHIFT 15 10595 10596 /* AMS_TX :: TX_CTRL_0 :: ams_14 [14:14] */ 10597 #define AMS_TX_TX_CTRL_0_AMS_14_MASK 0x4000 10598 #define AMS_TX_TX_CTRL_0_AMS_14_ALIGN 0 10599 #define AMS_TX_TX_CTRL_0_AMS_14_BITS 1 10600 #define AMS_TX_TX_CTRL_0_AMS_14_SHIFT 14 10601 10602 /* AMS_TX :: TX_CTRL_0 :: ll_fifo_ctrl [13:11] */ 10603 #define AMS_TX_TX_CTRL_0_LL_FIFO_CTRL_MASK 0x3800 10604 #define AMS_TX_TX_CTRL_0_LL_FIFO_CTRL_ALIGN 0 10605 #define AMS_TX_TX_CTRL_0_LL_FIFO_CTRL_BITS 3 10606 #define AMS_TX_TX_CTRL_0_LL_FIFO_CTRL_SHIFT 11 10607 10608 /* AMS_TX :: TX_CTRL_0 :: ll_fifo_zero_out [10:10] */ 10609 #define AMS_TX_TX_CTRL_0_LL_FIFO_ZERO_OUT_MASK 0x0400 10610 #define AMS_TX_TX_CTRL_0_LL_FIFO_ZERO_OUT_ALIGN 0 10611 #define AMS_TX_TX_CTRL_0_LL_FIFO_ZERO_OUT_BITS 1 10612 #define AMS_TX_TX_CTRL_0_LL_FIFO_ZERO_OUT_SHIFT 10 10613 10614 /* AMS_TX :: TX_CTRL_0 :: ll_polarity_flip [09:09] */ 10615 #define AMS_TX_TX_CTRL_0_LL_POLARITY_FLIP_MASK 0x0200 10616 #define AMS_TX_TX_CTRL_0_LL_POLARITY_FLIP_ALIGN 0 10617 #define AMS_TX_TX_CTRL_0_LL_POLARITY_FLIP_BITS 1 10618 #define AMS_TX_TX_CTRL_0_LL_POLARITY_FLIP_SHIFT 9 10619 10620 /* AMS_TX :: TX_CTRL_0 :: ll_selpath_tx [08:08] */ 10621 #define AMS_TX_TX_CTRL_0_LL_SELPATH_TX_MASK 0x0100 10622 #define AMS_TX_TX_CTRL_0_LL_SELPATH_TX_ALIGN 0 10623 #define AMS_TX_TX_CTRL_0_LL_SELPATH_TX_BITS 1 10624 #define AMS_TX_TX_CTRL_0_LL_SELPATH_TX_SHIFT 8 10625 10626 /* AMS_TX :: TX_CTRL_0 :: noise_cancel_ctrl_0 [07:07] */ 10627 #define AMS_TX_TX_CTRL_0_NOISE_CANCEL_CTRL_0_MASK 0x0080 10628 #define AMS_TX_TX_CTRL_0_NOISE_CANCEL_CTRL_0_ALIGN 0 10629 #define AMS_TX_TX_CTRL_0_NOISE_CANCEL_CTRL_0_BITS 1 10630 #define AMS_TX_TX_CTRL_0_NOISE_CANCEL_CTRL_0_SHIFT 7 10631 10632 /* AMS_TX :: TX_CTRL_0 :: tx_pon [06:03] */ 10633 #define AMS_TX_TX_CTRL_0_TX_PON_MASK 0x0078 10634 #define AMS_TX_TX_CTRL_0_TX_PON_ALIGN 0 10635 #define AMS_TX_TX_CTRL_0_TX_PON_BITS 4 10636 #define AMS_TX_TX_CTRL_0_TX_PON_SHIFT 3 10637 10638 /* AMS_TX :: TX_CTRL_0 :: ticksel [02:01] */ 10639 #define AMS_TX_TX_CTRL_0_TICKSEL_MASK 0x0006 10640 #define AMS_TX_TX_CTRL_0_TICKSEL_ALIGN 0 10641 #define AMS_TX_TX_CTRL_0_TICKSEL_BITS 2 10642 #define AMS_TX_TX_CTRL_0_TICKSEL_SHIFT 1 10643 10644 /* AMS_TX :: TX_CTRL_0 :: tx_pwrdn [00:00] */ 10645 #define AMS_TX_TX_CTRL_0_TX_PWRDN_MASK 0x0001 10646 #define AMS_TX_TX_CTRL_0_TX_PWRDN_ALIGN 0 10647 #define AMS_TX_TX_CTRL_0_TX_PWRDN_BITS 1 10648 #define AMS_TX_TX_CTRL_0_TX_PWRDN_SHIFT 0 10649 10650 10651 /**************************************************************************** 10652 * AMS_TX :: TX_CTRL_1 10653 */ 10654 /* AMS_TX :: TX_CTRL_1 :: reserved0 [15:15] */ 10655 #define AMS_TX_TX_CTRL_1_RESERVED0_MASK 0x8000 10656 #define AMS_TX_TX_CTRL_1_RESERVED0_ALIGN 0 10657 #define AMS_TX_TX_CTRL_1_RESERVED0_BITS 1 10658 #define AMS_TX_TX_CTRL_1_RESERVED0_SHIFT 15 10659 10660 /* AMS_TX :: TX_CTRL_1 :: en_slow [14:11] */ 10661 #define AMS_TX_TX_CTRL_1_EN_SLOW_MASK 0x7800 10662 #define AMS_TX_TX_CTRL_1_EN_SLOW_ALIGN 0 10663 #define AMS_TX_TX_CTRL_1_EN_SLOW_BITS 4 10664 #define AMS_TX_TX_CTRL_1_EN_SLOW_SHIFT 11 10665 10666 /* AMS_TX :: TX_CTRL_1 :: en_wclk33 [10:10] */ 10667 #define AMS_TX_TX_CTRL_1_EN_WCLK33_MASK 0x0400 10668 #define AMS_TX_TX_CTRL_1_EN_WCLK33_ALIGN 0 10669 #define AMS_TX_TX_CTRL_1_EN_WCLK33_BITS 1 10670 #define AMS_TX_TX_CTRL_1_EN_WCLK33_SHIFT 10 10671 10672 /* AMS_TX :: TX_CTRL_1 :: en_wclk20 [09:09] */ 10673 #define AMS_TX_TX_CTRL_1_EN_WCLK20_MASK 0x0200 10674 #define AMS_TX_TX_CTRL_1_EN_WCLK20_ALIGN 0 10675 #define AMS_TX_TX_CTRL_1_EN_WCLK20_BITS 1 10676 #define AMS_TX_TX_CTRL_1_EN_WCLK20_SHIFT 9 10677 10678 /* AMS_TX :: TX_CTRL_1 :: en_wclk16 [08:08] */ 10679 #define AMS_TX_TX_CTRL_1_EN_WCLK16_MASK 0x0100 10680 #define AMS_TX_TX_CTRL_1_EN_WCLK16_ALIGN 0 10681 #define AMS_TX_TX_CTRL_1_EN_WCLK16_BITS 1 10682 #define AMS_TX_TX_CTRL_1_EN_WCLK16_SHIFT 8 10683 10684 /* AMS_TX :: TX_CTRL_1 :: testclk_ena [07:07] */ 10685 #define AMS_TX_TX_CTRL_1_TESTCLK_ENA_MASK 0x0080 10686 #define AMS_TX_TX_CTRL_1_TESTCLK_ENA_ALIGN 0 10687 #define AMS_TX_TX_CTRL_1_TESTCLK_ENA_BITS 1 10688 #define AMS_TX_TX_CTRL_1_TESTCLK_ENA_SHIFT 7 10689 10690 /* AMS_TX :: TX_CTRL_1 :: testsel [06:05] */ 10691 #define AMS_TX_TX_CTRL_1_TESTSEL_MASK 0x0060 10692 #define AMS_TX_TX_CTRL_1_TESTSEL_ALIGN 0 10693 #define AMS_TX_TX_CTRL_1_TESTSEL_BITS 2 10694 #define AMS_TX_TX_CTRL_1_TESTSEL_SHIFT 5 10695 10696 /* AMS_TX :: TX_CTRL_1 :: noise_cancel_ctrl_1 [04:04] */ 10697 #define AMS_TX_TX_CTRL_1_NOISE_CANCEL_CTRL_1_MASK 0x0010 10698 #define AMS_TX_TX_CTRL_1_NOISE_CANCEL_CTRL_1_ALIGN 0 10699 #define AMS_TX_TX_CTRL_1_NOISE_CANCEL_CTRL_1_BITS 1 10700 #define AMS_TX_TX_CTRL_1_NOISE_CANCEL_CTRL_1_SHIFT 4 10701 10702 /* AMS_TX :: TX_CTRL_1 :: shunt_dc_level_post2 [03:00] */ 10703 #define AMS_TX_TX_CTRL_1_SHUNT_DC_LEVEL_POST2_MASK 0x000f 10704 #define AMS_TX_TX_CTRL_1_SHUNT_DC_LEVEL_POST2_ALIGN 0 10705 #define AMS_TX_TX_CTRL_1_SHUNT_DC_LEVEL_POST2_BITS 4 10706 #define AMS_TX_TX_CTRL_1_SHUNT_DC_LEVEL_POST2_SHIFT 0 10707 10708 10709 /**************************************************************************** 10710 * AMS_TX :: TX_CTRL_2 10711 */ 10712 /* AMS_TX :: TX_CTRL_2 :: reserved0 [15:15] */ 10713 #define AMS_TX_TX_CTRL_2_RESERVED0_MASK 0x8000 10714 #define AMS_TX_TX_CTRL_2_RESERVED0_ALIGN 0 10715 #define AMS_TX_TX_CTRL_2_RESERVED0_BITS 1 10716 #define AMS_TX_TX_CTRL_2_RESERVED0_SHIFT 15 10717 10718 /* AMS_TX :: TX_CTRL_2 :: fifo_phsdetect_mode [14:14] */ 10719 #define AMS_TX_TX_CTRL_2_FIFO_PHSDETECT_MODE_MASK 0x4000 10720 #define AMS_TX_TX_CTRL_2_FIFO_PHSDETECT_MODE_ALIGN 0 10721 #define AMS_TX_TX_CTRL_2_FIFO_PHSDETECT_MODE_BITS 1 10722 #define AMS_TX_TX_CTRL_2_FIFO_PHSDETECT_MODE_SHIFT 14 10723 10724 /* AMS_TX :: TX_CTRL_2 :: ibias_pibuf_cntl [13:11] */ 10725 #define AMS_TX_TX_CTRL_2_IBIAS_PIBUF_CNTL_MASK 0x3800 10726 #define AMS_TX_TX_CTRL_2_IBIAS_PIBUF_CNTL_ALIGN 0 10727 #define AMS_TX_TX_CTRL_2_IBIAS_PIBUF_CNTL_BITS 3 10728 #define AMS_TX_TX_CTRL_2_IBIAS_PIBUF_CNTL_SHIFT 11 10729 10730 /* AMS_TX :: TX_CTRL_2 :: ibias_pi_cntl [10:08] */ 10731 #define AMS_TX_TX_CTRL_2_IBIAS_PI_CNTL_MASK 0x0700 10732 #define AMS_TX_TX_CTRL_2_IBIAS_PI_CNTL_ALIGN 0 10733 #define AMS_TX_TX_CTRL_2_IBIAS_PI_CNTL_BITS 3 10734 #define AMS_TX_TX_CTRL_2_IBIAS_PI_CNTL_SHIFT 8 10735 10736 /* AMS_TX :: TX_CTRL_2 :: ibias_opamp_cntl [07:05] */ 10737 #define AMS_TX_TX_CTRL_2_IBIAS_OPAMP_CNTL_MASK 0x00e0 10738 #define AMS_TX_TX_CTRL_2_IBIAS_OPAMP_CNTL_ALIGN 0 10739 #define AMS_TX_TX_CTRL_2_IBIAS_OPAMP_CNTL_BITS 3 10740 #define AMS_TX_TX_CTRL_2_IBIAS_OPAMP_CNTL_SHIFT 5 10741 10742 /* AMS_TX :: TX_CTRL_2 :: dcc_en [04:04] */ 10743 #define AMS_TX_TX_CTRL_2_DCC_EN_MASK 0x0010 10744 #define AMS_TX_TX_CTRL_2_DCC_EN_ALIGN 0 10745 #define AMS_TX_TX_CTRL_2_DCC_EN_BITS 1 10746 #define AMS_TX_TX_CTRL_2_DCC_EN_SHIFT 4 10747 10748 /* AMS_TX :: TX_CTRL_2 :: en_hpf [03:00] */ 10749 #define AMS_TX_TX_CTRL_2_EN_HPF_MASK 0x000f 10750 #define AMS_TX_TX_CTRL_2_EN_HPF_ALIGN 0 10751 #define AMS_TX_TX_CTRL_2_EN_HPF_BITS 4 10752 #define AMS_TX_TX_CTRL_2_EN_HPF_SHIFT 0 10753 10754 10755 /**************************************************************************** 10756 * AMS_TX :: TX_CTRL_3 10757 */ 10758 /* AMS_TX :: TX_CTRL_3 :: reserved0 [15:14] */ 10759 #define AMS_TX_TX_CTRL_3_RESERVED0_MASK 0xc000 10760 #define AMS_TX_TX_CTRL_3_RESERVED0_ALIGN 0 10761 #define AMS_TX_TX_CTRL_3_RESERVED0_BITS 2 10762 #define AMS_TX_TX_CTRL_3_RESERVED0_SHIFT 14 10763 10764 /* AMS_TX :: TX_CTRL_3 :: refcalm [13:10] */ 10765 #define AMS_TX_TX_CTRL_3_REFCALM_MASK 0x3c00 10766 #define AMS_TX_TX_CTRL_3_REFCALM_ALIGN 0 10767 #define AMS_TX_TX_CTRL_3_REFCALM_BITS 4 10768 #define AMS_TX_TX_CTRL_3_REFCALM_SHIFT 10 10769 10770 /* AMS_TX :: TX_CTRL_3 :: refcalp [09:06] */ 10771 #define AMS_TX_TX_CTRL_3_REFCALP_MASK 0x03c0 10772 #define AMS_TX_TX_CTRL_3_REFCALP_ALIGN 0 10773 #define AMS_TX_TX_CTRL_3_REFCALP_BITS 4 10774 #define AMS_TX_TX_CTRL_3_REFCALP_SHIFT 6 10775 10776 /* AMS_TX :: TX_CTRL_3 :: refcalshunt [05:02] */ 10777 #define AMS_TX_TX_CTRL_3_REFCALSHUNT_MASK 0x003c 10778 #define AMS_TX_TX_CTRL_3_REFCALSHUNT_ALIGN 0 10779 #define AMS_TX_TX_CTRL_3_REFCALSHUNT_BITS 4 10780 #define AMS_TX_TX_CTRL_3_REFCALSHUNT_SHIFT 2 10781 10782 /* AMS_TX :: TX_CTRL_3 :: refnwbias [01:00] */ 10783 #define AMS_TX_TX_CTRL_3_REFNWBIAS_MASK 0x0003 10784 #define AMS_TX_TX_CTRL_3_REFNWBIAS_ALIGN 0 10785 #define AMS_TX_TX_CTRL_3_REFNWBIAS_BITS 2 10786 #define AMS_TX_TX_CTRL_3_REFNWBIAS_SHIFT 0 10787 10788 10789 /**************************************************************************** 10790 * AMS_TX :: TX_CTRL_4 10791 */ 10792 /* AMS_TX :: TX_CTRL_4 :: reserved0 [15:15] */ 10793 #define AMS_TX_TX_CTRL_4_RESERVED0_MASK 0x8000 10794 #define AMS_TX_TX_CTRL_4_RESERVED0_ALIGN 0 10795 #define AMS_TX_TX_CTRL_4_RESERVED0_BITS 1 10796 #define AMS_TX_TX_CTRL_4_RESERVED0_SHIFT 15 10797 10798 /* AMS_TX :: TX_CTRL_4 :: en_shuntmode [14:14] */ 10799 #define AMS_TX_TX_CTRL_4_EN_SHUNTMODE_MASK 0x4000 10800 #define AMS_TX_TX_CTRL_4_EN_SHUNTMODE_ALIGN 0 10801 #define AMS_TX_TX_CTRL_4_EN_SHUNTMODE_BITS 1 10802 #define AMS_TX_TX_CTRL_4_EN_SHUNTMODE_SHIFT 14 10803 10804 /* AMS_TX :: TX_CTRL_4 :: shunt_pre_shared [13:11] */ 10805 #define AMS_TX_TX_CTRL_4_SHUNT_PRE_SHARED_MASK 0x3800 10806 #define AMS_TX_TX_CTRL_4_SHUNT_PRE_SHARED_ALIGN 0 10807 #define AMS_TX_TX_CTRL_4_SHUNT_PRE_SHARED_BITS 3 10808 #define AMS_TX_TX_CTRL_4_SHUNT_PRE_SHARED_SHIFT 11 10809 10810 /* AMS_TX :: TX_CTRL_4 :: shunt_dc_level [10:10] */ 10811 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_MASK 0x0400 10812 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_ALIGN 0 10813 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_BITS 1 10814 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_SHIFT 10 10815 10816 /* AMS_TX :: TX_CTRL_4 :: shunt_dc_level_pre [09:07] */ 10817 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_PRE_MASK 0x0380 10818 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_PRE_ALIGN 0 10819 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_PRE_BITS 3 10820 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_PRE_SHIFT 7 10821 10822 /* AMS_TX :: TX_CTRL_4 :: shunt_dc_level_post1 [06:03] */ 10823 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_POST1_MASK 0x0078 10824 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_POST1_ALIGN 0 10825 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_POST1_BITS 4 10826 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_POST1_SHIFT 3 10827 10828 /* AMS_TX :: TX_CTRL_4 :: shunt_dc_level_shared [02:00] */ 10829 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_SHARED_MASK 0x0007 10830 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_SHARED_ALIGN 0 10831 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_SHARED_BITS 3 10832 #define AMS_TX_TX_CTRL_4_SHUNT_DC_LEVEL_SHARED_SHIFT 0 10833 10834 10835 /**************************************************************************** 10836 * AMS_TX :: TX_CTRL_5 10837 */ 10838 /* AMS_TX :: TX_CTRL_5 :: Post2to1 [15:15] */ 10839 #define AMS_TX_TX_CTRL_5_POST2TO1_MASK 0x8000 10840 #define AMS_TX_TX_CTRL_5_POST2TO1_ALIGN 0 10841 #define AMS_TX_TX_CTRL_5_POST2TO1_BITS 1 10842 #define AMS_TX_TX_CTRL_5_POST2TO1_SHIFT 15 10843 10844 /* AMS_TX :: TX_CTRL_5 :: en_pre [14:14] */ 10845 #define AMS_TX_TX_CTRL_5_EN_PRE_MASK 0x4000 10846 #define AMS_TX_TX_CTRL_5_EN_PRE_ALIGN 0 10847 #define AMS_TX_TX_CTRL_5_EN_PRE_BITS 1 10848 #define AMS_TX_TX_CTRL_5_EN_PRE_SHIFT 14 10849 10850 /* AMS_TX :: TX_CTRL_5 :: en_post1 [13:13] */ 10851 #define AMS_TX_TX_CTRL_5_EN_POST1_MASK 0x2000 10852 #define AMS_TX_TX_CTRL_5_EN_POST1_ALIGN 0 10853 #define AMS_TX_TX_CTRL_5_EN_POST1_BITS 1 10854 #define AMS_TX_TX_CTRL_5_EN_POST1_SHIFT 13 10855 10856 /* AMS_TX :: TX_CTRL_5 :: en_post2 [12:12] */ 10857 #define AMS_TX_TX_CTRL_5_EN_POST2_MASK 0x1000 10858 #define AMS_TX_TX_CTRL_5_EN_POST2_ALIGN 0 10859 #define AMS_TX_TX_CTRL_5_EN_POST2_BITS 1 10860 #define AMS_TX_TX_CTRL_5_EN_POST2_SHIFT 12 10861 10862 /* AMS_TX :: TX_CTRL_5 :: shunt_post2 [11:08] */ 10863 #define AMS_TX_TX_CTRL_5_SHUNT_POST2_MASK 0x0f00 10864 #define AMS_TX_TX_CTRL_5_SHUNT_POST2_ALIGN 0 10865 #define AMS_TX_TX_CTRL_5_SHUNT_POST2_BITS 4 10866 #define AMS_TX_TX_CTRL_5_SHUNT_POST2_SHIFT 8 10867 10868 /* AMS_TX :: TX_CTRL_5 :: shunt_post1 [07:03] */ 10869 #define AMS_TX_TX_CTRL_5_SHUNT_POST1_MASK 0x00f8 10870 #define AMS_TX_TX_CTRL_5_SHUNT_POST1_ALIGN 0 10871 #define AMS_TX_TX_CTRL_5_SHUNT_POST1_BITS 5 10872 #define AMS_TX_TX_CTRL_5_SHUNT_POST1_SHIFT 3 10873 10874 /* AMS_TX :: TX_CTRL_5 :: shunt_pre [02:00] */ 10875 #define AMS_TX_TX_CTRL_5_SHUNT_PRE_MASK 0x0007 10876 #define AMS_TX_TX_CTRL_5_SHUNT_PRE_ALIGN 0 10877 #define AMS_TX_TX_CTRL_5_SHUNT_PRE_BITS 3 10878 #define AMS_TX_TX_CTRL_5_SHUNT_PRE_SHIFT 0 10879 10880 10881 /**************************************************************************** 10882 * AMS_TX :: TX_INT 10883 */ 10884 /* AMS_TX :: TX_INT :: reserved0 [15:03] */ 10885 #define AMS_TX_TX_INT_RESERVED0_MASK 0xfff8 10886 #define AMS_TX_TX_INT_RESERVED0_ALIGN 0 10887 #define AMS_TX_TX_INT_RESERVED0_BITS 13 10888 #define AMS_TX_TX_INT_RESERVED0_SHIFT 3 10889 10890 /* AMS_TX :: TX_INT :: auto_ll_selpath_tx_dis [02:02] */ 10891 #define AMS_TX_TX_INT_AUTO_LL_SELPATH_TX_DIS_MASK 0x0004 10892 #define AMS_TX_TX_INT_AUTO_LL_SELPATH_TX_DIS_ALIGN 0 10893 #define AMS_TX_TX_INT_AUTO_LL_SELPATH_TX_DIS_BITS 1 10894 #define AMS_TX_TX_INT_AUTO_LL_SELPATH_TX_DIS_SHIFT 2 10895 10896 /* AMS_TX :: TX_INT :: txpon_sel [01:01] */ 10897 #define AMS_TX_TX_INT_TXPON_SEL_MASK 0x0002 10898 #define AMS_TX_TX_INT_TXPON_SEL_ALIGN 0 10899 #define AMS_TX_TX_INT_TXPON_SEL_BITS 1 10900 #define AMS_TX_TX_INT_TXPON_SEL_SHIFT 1 10901 10902 /* AMS_TX :: TX_INT :: reserved1 [00:00] */ 10903 #define AMS_TX_TX_INT_RESERVED1_MASK 0x0001 10904 #define AMS_TX_TX_INT_RESERVED1_ALIGN 0 10905 #define AMS_TX_TX_INT_RESERVED1_BITS 1 10906 #define AMS_TX_TX_INT_RESERVED1_SHIFT 0 10907 10908 10909 /**************************************************************************** 10910 * AMS_TX :: TX_STS 10911 */ 10912 /* AMS_TX :: TX_STS :: reserved0 [15:08] */ 10913 #define AMS_TX_TX_STS_RESERVED0_MASK 0xff00 10914 #define AMS_TX_TX_STS_RESERVED0_ALIGN 0 10915 #define AMS_TX_TX_STS_RESERVED0_BITS 8 10916 #define AMS_TX_TX_STS_RESERVED0_SHIFT 8 10917 10918 /* AMS_TX :: TX_STS :: rescal [07:04] */ 10919 #define AMS_TX_TX_STS_RESCAL_MASK 0x00f0 10920 #define AMS_TX_TX_STS_RESCAL_ALIGN 0 10921 #define AMS_TX_TX_STS_RESCAL_BITS 4 10922 #define AMS_TX_TX_STS_RESCAL_SHIFT 4 10923 10924 /* AMS_TX :: TX_STS :: txpon_mux [03:00] */ 10925 #define AMS_TX_TX_STS_TXPON_MUX_MASK 0x000f 10926 #define AMS_TX_TX_STS_TXPON_MUX_ALIGN 0 10927 #define AMS_TX_TX_STS_TXPON_MUX_BITS 4 10928 #define AMS_TX_TX_STS_TXPON_MUX_SHIFT 0 10929 10930 10931 /**************************************************************************** 10932 * merlin_gallardo_ams_blk_AMSCOM 10933 */ 10934 /**************************************************************************** 10935 * AMSCOM :: PLL_CTRL_0 10936 */ 10937 /* AMSCOM :: PLL_CTRL_0 :: cpar [15:14] */ 10938 #define AMSCOM_PLL_CTRL_0_CPAR_MASK 0xc000 10939 #define AMSCOM_PLL_CTRL_0_CPAR_ALIGN 0 10940 #define AMSCOM_PLL_CTRL_0_CPAR_BITS 2 10941 #define AMSCOM_PLL_CTRL_0_CPAR_SHIFT 14 10942 10943 /* AMSCOM :: PLL_CTRL_0 :: term_cm_en [13:13] */ 10944 #define AMSCOM_PLL_CTRL_0_TERM_CM_EN_MASK 0x2000 10945 #define AMSCOM_PLL_CTRL_0_TERM_CM_EN_ALIGN 0 10946 #define AMSCOM_PLL_CTRL_0_TERM_CM_EN_BITS 1 10947 #define AMSCOM_PLL_CTRL_0_TERM_CM_EN_SHIFT 13 10948 10949 /* AMSCOM :: PLL_CTRL_0 :: rpar [12:09] */ 10950 #define AMSCOM_PLL_CTRL_0_RPAR_MASK 0x1e00 10951 #define AMSCOM_PLL_CTRL_0_RPAR_ALIGN 0 10952 #define AMSCOM_PLL_CTRL_0_RPAR_BITS 4 10953 #define AMSCOM_PLL_CTRL_0_RPAR_SHIFT 9 10954 10955 /* AMSCOM :: PLL_CTRL_0 :: xtal_core_bias [08:05] */ 10956 #define AMSCOM_PLL_CTRL_0_XTAL_CORE_BIAS_MASK 0x01e0 10957 #define AMSCOM_PLL_CTRL_0_XTAL_CORE_BIAS_ALIGN 0 10958 #define AMSCOM_PLL_CTRL_0_XTAL_CORE_BIAS_BITS 4 10959 #define AMSCOM_PLL_CTRL_0_XTAL_CORE_BIAS_SHIFT 5 10960 10961 /* AMSCOM :: PLL_CTRL_0 :: xtal_bias [04:02] */ 10962 #define AMSCOM_PLL_CTRL_0_XTAL_BIAS_MASK 0x001c 10963 #define AMSCOM_PLL_CTRL_0_XTAL_BIAS_ALIGN 0 10964 #define AMSCOM_PLL_CTRL_0_XTAL_BIAS_BITS 3 10965 #define AMSCOM_PLL_CTRL_0_XTAL_BIAS_SHIFT 2 10966 10967 /* AMSCOM :: PLL_CTRL_0 :: hipass [01:01] */ 10968 #define AMSCOM_PLL_CTRL_0_HIPASS_MASK 0x0002 10969 #define AMSCOM_PLL_CTRL_0_HIPASS_ALIGN 0 10970 #define AMSCOM_PLL_CTRL_0_HIPASS_BITS 1 10971 #define AMSCOM_PLL_CTRL_0_HIPASS_SHIFT 1 10972 10973 /* AMSCOM :: PLL_CTRL_0 :: xtal_cm_sel [00:00] */ 10974 #define AMSCOM_PLL_CTRL_0_XTAL_CM_SEL_MASK 0x0001 10975 #define AMSCOM_PLL_CTRL_0_XTAL_CM_SEL_ALIGN 0 10976 #define AMSCOM_PLL_CTRL_0_XTAL_CM_SEL_BITS 1 10977 #define AMSCOM_PLL_CTRL_0_XTAL_CM_SEL_SHIFT 0 10978 10979 10980 /**************************************************************************** 10981 * AMSCOM :: PLL_CTRL_1 10982 */ 10983 /* AMSCOM :: PLL_CTRL_1 :: pll_spare1_1 [15:13] */ 10984 #define AMSCOM_PLL_CTRL_1_PLL_SPARE1_1_MASK 0xe000 10985 #define AMSCOM_PLL_CTRL_1_PLL_SPARE1_1_ALIGN 0 10986 #define AMSCOM_PLL_CTRL_1_PLL_SPARE1_1_BITS 3 10987 #define AMSCOM_PLL_CTRL_1_PLL_SPARE1_1_SHIFT 13 10988 10989 /* AMSCOM :: PLL_CTRL_1 :: vco_range [12:06] */ 10990 #define AMSCOM_PLL_CTRL_1_VCO_RANGE_MASK 0x1fc0 10991 #define AMSCOM_PLL_CTRL_1_VCO_RANGE_ALIGN 0 10992 #define AMSCOM_PLL_CTRL_1_VCO_RANGE_BITS 7 10993 #define AMSCOM_PLL_CTRL_1_VCO_RANGE_SHIFT 6 10994 10995 /* AMSCOM :: PLL_CTRL_1 :: pll_spare1_0 [05:05] */ 10996 #define AMSCOM_PLL_CTRL_1_PLL_SPARE1_0_MASK 0x0020 10997 #define AMSCOM_PLL_CTRL_1_PLL_SPARE1_0_ALIGN 0 10998 #define AMSCOM_PLL_CTRL_1_PLL_SPARE1_0_BITS 1 10999 #define AMSCOM_PLL_CTRL_1_PLL_SPARE1_0_SHIFT 5 11000 11001 /* AMSCOM :: PLL_CTRL_1 :: xtal_cm_en [04:04] */ 11002 #define AMSCOM_PLL_CTRL_1_XTAL_CM_EN_MASK 0x0010 11003 #define AMSCOM_PLL_CTRL_1_XTAL_CM_EN_ALIGN 0 11004 #define AMSCOM_PLL_CTRL_1_XTAL_CM_EN_BITS 1 11005 #define AMSCOM_PLL_CTRL_1_XTAL_CM_EN_SHIFT 4 11006 11007 /* AMSCOM :: PLL_CTRL_1 :: curr_sel [03:00] */ 11008 #define AMSCOM_PLL_CTRL_1_CURR_SEL_MASK 0x000f 11009 #define AMSCOM_PLL_CTRL_1_CURR_SEL_ALIGN 0 11010 #define AMSCOM_PLL_CTRL_1_CURR_SEL_BITS 4 11011 #define AMSCOM_PLL_CTRL_1_CURR_SEL_SHIFT 0 11012 11013 11014 /**************************************************************************** 11015 * AMSCOM :: PLL_CTRL_2 11016 */ 11017 /* AMSCOM :: PLL_CTRL_2 :: en_i4iqbuf [15:14] */ 11018 #define AMSCOM_PLL_CTRL_2_EN_I4IQBUF_MASK 0xc000 11019 #define AMSCOM_PLL_CTRL_2_EN_I4IQBUF_ALIGN 0 11020 #define AMSCOM_PLL_CTRL_2_EN_I4IQBUF_BITS 2 11021 #define AMSCOM_PLL_CTRL_2_EN_I4IQBUF_SHIFT 14 11022 11023 /* AMSCOM :: PLL_CTRL_2 :: vco_buf_pon [13:10] */ 11024 #define AMSCOM_PLL_CTRL_2_VCO_BUF_PON_MASK 0x3c00 11025 #define AMSCOM_PLL_CTRL_2_VCO_BUF_PON_ALIGN 0 11026 #define AMSCOM_PLL_CTRL_2_VCO_BUF_PON_BITS 4 11027 #define AMSCOM_PLL_CTRL_2_VCO_BUF_PON_SHIFT 10 11028 11029 /* AMSCOM :: PLL_CTRL_2 :: pll_clkvco_cal_invert [09:09] */ 11030 #define AMSCOM_PLL_CTRL_2_PLL_CLKVCO_CAL_INVERT_MASK 0x0200 11031 #define AMSCOM_PLL_CTRL_2_PLL_CLKVCO_CAL_INVERT_ALIGN 0 11032 #define AMSCOM_PLL_CTRL_2_PLL_CLKVCO_CAL_INVERT_BITS 1 11033 #define AMSCOM_PLL_CTRL_2_PLL_CLKVCO_CAL_INVERT_SHIFT 9 11034 11035 /* AMSCOM :: PLL_CTRL_2 :: pll_spare2_0 [08:08] */ 11036 #define AMSCOM_PLL_CTRL_2_PLL_SPARE2_0_MASK 0x0100 11037 #define AMSCOM_PLL_CTRL_2_PLL_SPARE2_0_ALIGN 0 11038 #define AMSCOM_PLL_CTRL_2_PLL_SPARE2_0_BITS 1 11039 #define AMSCOM_PLL_CTRL_2_PLL_SPARE2_0_SHIFT 8 11040 11041 /* AMSCOM :: PLL_CTRL_2 :: calib_adj [07:05] */ 11042 #define AMSCOM_PLL_CTRL_2_CALIB_ADJ_MASK 0x00e0 11043 #define AMSCOM_PLL_CTRL_2_CALIB_ADJ_ALIGN 0 11044 #define AMSCOM_PLL_CTRL_2_CALIB_ADJ_BITS 3 11045 #define AMSCOM_PLL_CTRL_2_CALIB_ADJ_SHIFT 5 11046 11047 /* AMSCOM :: PLL_CTRL_2 :: en_8p5g [04:04] */ 11048 #define AMSCOM_PLL_CTRL_2_EN_8P5G_MASK 0x0010 11049 #define AMSCOM_PLL_CTRL_2_EN_8P5G_ALIGN 0 11050 #define AMSCOM_PLL_CTRL_2_EN_8P5G_BITS 1 11051 #define AMSCOM_PLL_CTRL_2_EN_8P5G_SHIFT 4 11052 11053 /* AMSCOM :: PLL_CTRL_2 :: vco_pon [03:00] */ 11054 #define AMSCOM_PLL_CTRL_2_VCO_PON_MASK 0x000f 11055 #define AMSCOM_PLL_CTRL_2_VCO_PON_ALIGN 0 11056 #define AMSCOM_PLL_CTRL_2_VCO_PON_BITS 4 11057 #define AMSCOM_PLL_CTRL_2_VCO_PON_SHIFT 0 11058 11059 11060 /**************************************************************************** 11061 * AMSCOM :: PLL_CTRL_3 11062 */ 11063 /* AMSCOM :: PLL_CTRL_3 :: div [15:11] */ 11064 #define AMSCOM_PLL_CTRL_3_DIV_MASK 0xf800 11065 #define AMSCOM_PLL_CTRL_3_DIV_ALIGN 0 11066 #define AMSCOM_PLL_CTRL_3_DIV_BITS 5 11067 #define AMSCOM_PLL_CTRL_3_DIV_SHIFT 11 11068 11069 /* AMSCOM :: PLL_CTRL_3 :: en_cmos_refout [10:10] */ 11070 #define AMSCOM_PLL_CTRL_3_EN_CMOS_REFOUT_MASK 0x0400 11071 #define AMSCOM_PLL_CTRL_3_EN_CMOS_REFOUT_ALIGN 0 11072 #define AMSCOM_PLL_CTRL_3_EN_CMOS_REFOUT_BITS 1 11073 #define AMSCOM_PLL_CTRL_3_EN_CMOS_REFOUT_SHIFT 10 11074 11075 /* AMSCOM :: PLL_CTRL_3 :: en_cml_refout [09:09] */ 11076 #define AMSCOM_PLL_CTRL_3_EN_CML_REFOUT_MASK 0x0200 11077 #define AMSCOM_PLL_CTRL_3_EN_CML_REFOUT_ALIGN 0 11078 #define AMSCOM_PLL_CTRL_3_EN_CML_REFOUT_BITS 1 11079 #define AMSCOM_PLL_CTRL_3_EN_CML_REFOUT_SHIFT 9 11080 11081 /* AMSCOM :: PLL_CTRL_3 :: pllclksel [08:08] */ 11082 #define AMSCOM_PLL_CTRL_3_PLLCLKSEL_MASK 0x0100 11083 #define AMSCOM_PLL_CTRL_3_PLLCLKSEL_ALIGN 0 11084 #define AMSCOM_PLL_CTRL_3_PLLCLKSEL_BITS 1 11085 #define AMSCOM_PLL_CTRL_3_PLLCLKSEL_SHIFT 8 11086 11087 /* AMSCOM :: PLL_CTRL_3 :: en_rclk_refout [07:07] */ 11088 #define AMSCOM_PLL_CTRL_3_EN_RCLK_REFOUT_MASK 0x0080 11089 #define AMSCOM_PLL_CTRL_3_EN_RCLK_REFOUT_ALIGN 0 11090 #define AMSCOM_PLL_CTRL_3_EN_RCLK_REFOUT_BITS 1 11091 #define AMSCOM_PLL_CTRL_3_EN_RCLK_REFOUT_SHIFT 7 11092 11093 /* AMSCOM :: PLL_CTRL_3 :: en_cmos_refout_overwr [06:06] */ 11094 #define AMSCOM_PLL_CTRL_3_EN_CMOS_REFOUT_OVERWR_MASK 0x0040 11095 #define AMSCOM_PLL_CTRL_3_EN_CMOS_REFOUT_OVERWR_ALIGN 0 11096 #define AMSCOM_PLL_CTRL_3_EN_CMOS_REFOUT_OVERWR_BITS 1 11097 #define AMSCOM_PLL_CTRL_3_EN_CMOS_REFOUT_OVERWR_SHIFT 6 11098 11099 /* AMSCOM :: PLL_CTRL_3 :: en_cml_refout_overwr [05:05] */ 11100 #define AMSCOM_PLL_CTRL_3_EN_CML_REFOUT_OVERWR_MASK 0x0020 11101 #define AMSCOM_PLL_CTRL_3_EN_CML_REFOUT_OVERWR_ALIGN 0 11102 #define AMSCOM_PLL_CTRL_3_EN_CML_REFOUT_OVERWR_BITS 1 11103 #define AMSCOM_PLL_CTRL_3_EN_CML_REFOUT_OVERWR_SHIFT 5 11104 11105 /* AMSCOM :: PLL_CTRL_3 :: en_test_frac_clk [04:04] */ 11106 #define AMSCOM_PLL_CTRL_3_EN_TEST_FRAC_CLK_MASK 0x0010 11107 #define AMSCOM_PLL_CTRL_3_EN_TEST_FRAC_CLK_ALIGN 0 11108 #define AMSCOM_PLL_CTRL_3_EN_TEST_FRAC_CLK_BITS 1 11109 #define AMSCOM_PLL_CTRL_3_EN_TEST_FRAC_CLK_SHIFT 4 11110 11111 /* AMSCOM :: PLL_CTRL_3 :: en_test_integer_clk [03:03] */ 11112 #define AMSCOM_PLL_CTRL_3_EN_TEST_INTEGER_CLK_MASK 0x0008 11113 #define AMSCOM_PLL_CTRL_3_EN_TEST_INTEGER_CLK_ALIGN 0 11114 #define AMSCOM_PLL_CTRL_3_EN_TEST_INTEGER_CLK_BITS 1 11115 #define AMSCOM_PLL_CTRL_3_EN_TEST_INTEGER_CLK_SHIFT 3 11116 11117 /* AMSCOM :: PLL_CTRL_3 :: band_Iqbuf_ctr [02:00] */ 11118 #define AMSCOM_PLL_CTRL_3_BAND_IQBUF_CTR_MASK 0x0007 11119 #define AMSCOM_PLL_CTRL_3_BAND_IQBUF_CTR_ALIGN 0 11120 #define AMSCOM_PLL_CTRL_3_BAND_IQBUF_CTR_BITS 3 11121 #define AMSCOM_PLL_CTRL_3_BAND_IQBUF_CTR_SHIFT 0 11122 11123 11124 /**************************************************************************** 11125 * AMSCOM :: PLL_CTRL_4 11126 */ 11127 /* AMSCOM :: PLL_CTRL_4 :: reserved0 [15:15] */ 11128 #define AMSCOM_PLL_CTRL_4_RESERVED0_MASK 0x8000 11129 #define AMSCOM_PLL_CTRL_4_RESERVED0_ALIGN 0 11130 #define AMSCOM_PLL_CTRL_4_RESERVED0_BITS 1 11131 #define AMSCOM_PLL_CTRL_4_RESERVED0_SHIFT 15 11132 11133 /* AMSCOM :: PLL_CTRL_4 :: test_sel [14:12] */ 11134 #define AMSCOM_PLL_CTRL_4_TEST_SEL_MASK 0x7000 11135 #define AMSCOM_PLL_CTRL_4_TEST_SEL_ALIGN 0 11136 #define AMSCOM_PLL_CTRL_4_TEST_SEL_BITS 3 11137 #define AMSCOM_PLL_CTRL_4_TEST_SEL_SHIFT 12 11138 11139 /* AMSCOM :: PLL_CTRL_4 :: test_amp [11:10] */ 11140 #define AMSCOM_PLL_CTRL_4_TEST_AMP_MASK 0x0c00 11141 #define AMSCOM_PLL_CTRL_4_TEST_AMP_ALIGN 0 11142 #define AMSCOM_PLL_CTRL_4_TEST_AMP_BITS 2 11143 #define AMSCOM_PLL_CTRL_4_TEST_AMP_SHIFT 10 11144 11145 /* AMSCOM :: PLL_CTRL_4 :: pll_spare4_1 [09:05] */ 11146 #define AMSCOM_PLL_CTRL_4_PLL_SPARE4_1_MASK 0x03e0 11147 #define AMSCOM_PLL_CTRL_4_PLL_SPARE4_1_ALIGN 0 11148 #define AMSCOM_PLL_CTRL_4_PLL_SPARE4_1_BITS 5 11149 #define AMSCOM_PLL_CTRL_4_PLL_SPARE4_1_SHIFT 5 11150 11151 /* AMSCOM :: PLL_CTRL_4 :: lp_adj [04:02] */ 11152 #define AMSCOM_PLL_CTRL_4_LP_ADJ_MASK 0x001c 11153 #define AMSCOM_PLL_CTRL_4_LP_ADJ_ALIGN 0 11154 #define AMSCOM_PLL_CTRL_4_LP_ADJ_BITS 3 11155 #define AMSCOM_PLL_CTRL_4_LP_ADJ_SHIFT 2 11156 11157 /* AMSCOM :: PLL_CTRL_4 :: pll_spare4_0 [01:01] */ 11158 #define AMSCOM_PLL_CTRL_4_PLL_SPARE4_0_MASK 0x0002 11159 #define AMSCOM_PLL_CTRL_4_PLL_SPARE4_0_ALIGN 0 11160 #define AMSCOM_PLL_CTRL_4_PLL_SPARE4_0_BITS 1 11161 #define AMSCOM_PLL_CTRL_4_PLL_SPARE4_0_SHIFT 1 11162 11163 /* AMSCOM :: PLL_CTRL_4 :: test_pll_mode [00:00] */ 11164 #define AMSCOM_PLL_CTRL_4_TEST_PLL_MODE_MASK 0x0001 11165 #define AMSCOM_PLL_CTRL_4_TEST_PLL_MODE_ALIGN 0 11166 #define AMSCOM_PLL_CTRL_4_TEST_PLL_MODE_BITS 1 11167 #define AMSCOM_PLL_CTRL_4_TEST_PLL_MODE_SHIFT 0 11168 11169 11170 /**************************************************************************** 11171 * AMSCOM :: PLL_CTRL_5 11172 */ 11173 /* AMSCOM :: PLL_CTRL_5 :: reserved0 [15:13] */ 11174 #define AMSCOM_PLL_CTRL_5_RESERVED0_MASK 0xe000 11175 #define AMSCOM_PLL_CTRL_5_RESERVED0_ALIGN 0 11176 #define AMSCOM_PLL_CTRL_5_RESERVED0_BITS 3 11177 #define AMSCOM_PLL_CTRL_5_RESERVED0_SHIFT 13 11178 11179 /* AMSCOM :: PLL_CTRL_5 :: en_cur [12:10] */ 11180 #define AMSCOM_PLL_CTRL_5_EN_CUR_MASK 0x1c00 11181 #define AMSCOM_PLL_CTRL_5_EN_CUR_ALIGN 0 11182 #define AMSCOM_PLL_CTRL_5_EN_CUR_BITS 3 11183 #define AMSCOM_PLL_CTRL_5_EN_CUR_SHIFT 10 11184 11185 /* AMSCOM :: PLL_CTRL_5 :: pwdb_dum [09:09] */ 11186 #define AMSCOM_PLL_CTRL_5_PWDB_DUM_MASK 0x0200 11187 #define AMSCOM_PLL_CTRL_5_PWDB_DUM_ALIGN 0 11188 #define AMSCOM_PLL_CTRL_5_PWDB_DUM_BITS 1 11189 #define AMSCOM_PLL_CTRL_5_PWDB_DUM_SHIFT 9 11190 11191 /* AMSCOM :: PLL_CTRL_5 :: bias_pwd [08:08] */ 11192 #define AMSCOM_PLL_CTRL_5_BIAS_PWD_MASK 0x0100 11193 #define AMSCOM_PLL_CTRL_5_BIAS_PWD_ALIGN 0 11194 #define AMSCOM_PLL_CTRL_5_BIAS_PWD_BITS 1 11195 #define AMSCOM_PLL_CTRL_5_BIAS_PWD_SHIFT 8 11196 11197 /* AMSCOM :: PLL_CTRL_5 :: pll_pwrdn [07:07] */ 11198 #define AMSCOM_PLL_CTRL_5_PLL_PWRDN_MASK 0x0080 11199 #define AMSCOM_PLL_CTRL_5_PLL_PWRDN_ALIGN 0 11200 #define AMSCOM_PLL_CTRL_5_PLL_PWRDN_BITS 1 11201 #define AMSCOM_PLL_CTRL_5_PLL_PWRDN_SHIFT 7 11202 11203 /* AMSCOM :: PLL_CTRL_5 :: term_sel [06:05] */ 11204 #define AMSCOM_PLL_CTRL_5_TERM_SEL_MASK 0x0060 11205 #define AMSCOM_PLL_CTRL_5_TERM_SEL_ALIGN 0 11206 #define AMSCOM_PLL_CTRL_5_TERM_SEL_BITS 2 11207 #define AMSCOM_PLL_CTRL_5_TERM_SEL_SHIFT 5 11208 11209 /* AMSCOM :: PLL_CTRL_5 :: test_sel_overwrite [04:04] */ 11210 #define AMSCOM_PLL_CTRL_5_TEST_SEL_OVERWRITE_MASK 0x0010 11211 #define AMSCOM_PLL_CTRL_5_TEST_SEL_OVERWRITE_ALIGN 0 11212 #define AMSCOM_PLL_CTRL_5_TEST_SEL_OVERWRITE_BITS 1 11213 #define AMSCOM_PLL_CTRL_5_TEST_SEL_OVERWRITE_SHIFT 4 11214 11215 /* AMSCOM :: PLL_CTRL_5 :: test_vc [03:03] */ 11216 #define AMSCOM_PLL_CTRL_5_TEST_VC_MASK 0x0008 11217 #define AMSCOM_PLL_CTRL_5_TEST_VC_ALIGN 0 11218 #define AMSCOM_PLL_CTRL_5_TEST_VC_BITS 1 11219 #define AMSCOM_PLL_CTRL_5_TEST_VC_SHIFT 3 11220 11221 /* AMSCOM :: PLL_CTRL_5 :: clk_test_sel [02:00] */ 11222 #define AMSCOM_PLL_CTRL_5_CLK_TEST_SEL_MASK 0x0007 11223 #define AMSCOM_PLL_CTRL_5_CLK_TEST_SEL_ALIGN 0 11224 #define AMSCOM_PLL_CTRL_5_CLK_TEST_SEL_BITS 3 11225 #define AMSCOM_PLL_CTRL_5_CLK_TEST_SEL_SHIFT 0 11226 11227 11228 /**************************************************************************** 11229 * AMSCOM :: PLL_CTRL_6 11230 */ 11231 /* AMSCOM :: PLL_CTRL_6 :: i_ndiv_frac_l [15:12] */ 11232 #define AMSCOM_PLL_CTRL_6_I_NDIV_FRAC_L_MASK 0xf000 11233 #define AMSCOM_PLL_CTRL_6_I_NDIV_FRAC_L_ALIGN 0 11234 #define AMSCOM_PLL_CTRL_6_I_NDIV_FRAC_L_BITS 4 11235 #define AMSCOM_PLL_CTRL_6_I_NDIV_FRAC_L_SHIFT 12 11236 11237 /* AMSCOM :: PLL_CTRL_6 :: i_pfd_offset [11:10] */ 11238 #define AMSCOM_PLL_CTRL_6_I_PFD_OFFSET_MASK 0x0c00 11239 #define AMSCOM_PLL_CTRL_6_I_PFD_OFFSET_ALIGN 0 11240 #define AMSCOM_PLL_CTRL_6_I_PFD_OFFSET_BITS 2 11241 #define AMSCOM_PLL_CTRL_6_I_PFD_OFFSET_SHIFT 10 11242 11243 /* AMSCOM :: PLL_CTRL_6 :: ref_doubler_en [09:09] */ 11244 #define AMSCOM_PLL_CTRL_6_REF_DOUBLER_EN_MASK 0x0200 11245 #define AMSCOM_PLL_CTRL_6_REF_DOUBLER_EN_ALIGN 0 11246 #define AMSCOM_PLL_CTRL_6_REF_DOUBLER_EN_BITS 1 11247 #define AMSCOM_PLL_CTRL_6_REF_DOUBLER_EN_SHIFT 9 11248 11249 /* AMSCOM :: PLL_CTRL_6 :: i_pfd_offset_enlarge [08:08] */ 11250 #define AMSCOM_PLL_CTRL_6_I_PFD_OFFSET_ENLARGE_MASK 0x0100 11251 #define AMSCOM_PLL_CTRL_6_I_PFD_OFFSET_ENLARGE_ALIGN 0 11252 #define AMSCOM_PLL_CTRL_6_I_PFD_OFFSET_ENLARGE_BITS 1 11253 #define AMSCOM_PLL_CTRL_6_I_PFD_OFFSET_ENLARGE_SHIFT 8 11254 11255 /* AMSCOM :: PLL_CTRL_6 :: en_cap [07:05] */ 11256 #define AMSCOM_PLL_CTRL_6_EN_CAP_MASK 0x00e0 11257 #define AMSCOM_PLL_CTRL_6_EN_CAP_ALIGN 0 11258 #define AMSCOM_PLL_CTRL_6_EN_CAP_BITS 3 11259 #define AMSCOM_PLL_CTRL_6_EN_CAP_SHIFT 5 11260 11261 /* AMSCOM :: PLL_CTRL_6 :: pll_spare6_0 [04:04] */ 11262 #define AMSCOM_PLL_CTRL_6_PLL_SPARE6_0_MASK 0x0010 11263 #define AMSCOM_PLL_CTRL_6_PLL_SPARE6_0_ALIGN 0 11264 #define AMSCOM_PLL_CTRL_6_PLL_SPARE6_0_BITS 1 11265 #define AMSCOM_PLL_CTRL_6_PLL_SPARE6_0_SHIFT 4 11266 11267 /* AMSCOM :: PLL_CTRL_6 :: pll_pon [03:00] */ 11268 #define AMSCOM_PLL_CTRL_6_PLL_PON_MASK 0x000f 11269 #define AMSCOM_PLL_CTRL_6_PLL_PON_ALIGN 0 11270 #define AMSCOM_PLL_CTRL_6_PLL_PON_BITS 4 11271 #define AMSCOM_PLL_CTRL_6_PLL_PON_SHIFT 0 11272 11273 11274 /**************************************************************************** 11275 * AMSCOM :: PLL_CTRL_7 11276 */ 11277 /* AMSCOM :: PLL_CTRL_7 :: reserved0 [15:14] */ 11278 #define AMSCOM_PLL_CTRL_7_RESERVED0_MASK 0xc000 11279 #define AMSCOM_PLL_CTRL_7_RESERVED0_ALIGN 0 11280 #define AMSCOM_PLL_CTRL_7_RESERVED0_BITS 2 11281 #define AMSCOM_PLL_CTRL_7_RESERVED0_SHIFT 14 11282 11283 /* AMSCOM :: PLL_CTRL_7 :: i_ndiv_frac_h [13:00] */ 11284 #define AMSCOM_PLL_CTRL_7_I_NDIV_FRAC_H_MASK 0x3fff 11285 #define AMSCOM_PLL_CTRL_7_I_NDIV_FRAC_H_ALIGN 0 11286 #define AMSCOM_PLL_CTRL_7_I_NDIV_FRAC_H_BITS 14 11287 #define AMSCOM_PLL_CTRL_7_I_NDIV_FRAC_H_SHIFT 0 11288 11289 11290 /**************************************************************************** 11291 * AMSCOM :: PLL_CTRL_8 11292 */ 11293 /* AMSCOM :: PLL_CTRL_8 :: i_ndiv_dither_en [15:15] */ 11294 #define AMSCOM_PLL_CTRL_8_I_NDIV_DITHER_EN_MASK 0x8000 11295 #define AMSCOM_PLL_CTRL_8_I_NDIV_DITHER_EN_ALIGN 0 11296 #define AMSCOM_PLL_CTRL_8_I_NDIV_DITHER_EN_BITS 1 11297 #define AMSCOM_PLL_CTRL_8_I_NDIV_DITHER_EN_SHIFT 15 11298 11299 /* AMSCOM :: PLL_CTRL_8 :: i_pll_sdm_pwrdnb [14:14] */ 11300 #define AMSCOM_PLL_CTRL_8_I_PLL_SDM_PWRDNB_MASK 0x4000 11301 #define AMSCOM_PLL_CTRL_8_I_PLL_SDM_PWRDNB_ALIGN 0 11302 #define AMSCOM_PLL_CTRL_8_I_PLL_SDM_PWRDNB_BITS 1 11303 #define AMSCOM_PLL_CTRL_8_I_PLL_SDM_PWRDNB_SHIFT 14 11304 11305 /* AMSCOM :: PLL_CTRL_8 :: mmd_en [13:13] */ 11306 #define AMSCOM_PLL_CTRL_8_MMD_EN_MASK 0x2000 11307 #define AMSCOM_PLL_CTRL_8_MMD_EN_ALIGN 0 11308 #define AMSCOM_PLL_CTRL_8_MMD_EN_BITS 1 11309 #define AMSCOM_PLL_CTRL_8_MMD_EN_SHIFT 13 11310 11311 /* AMSCOM :: PLL_CTRL_8 :: mmd_prsc4or5pwdb [12:12] */ 11312 #define AMSCOM_PLL_CTRL_8_MMD_PRSC4OR5PWDB_MASK 0x1000 11313 #define AMSCOM_PLL_CTRL_8_MMD_PRSC4OR5PWDB_ALIGN 0 11314 #define AMSCOM_PLL_CTRL_8_MMD_PRSC4OR5PWDB_BITS 1 11315 #define AMSCOM_PLL_CTRL_8_MMD_PRSC4OR5PWDB_SHIFT 12 11316 11317 /* AMSCOM :: PLL_CTRL_8 :: mmd_prsc8or9pwdb [11:11] */ 11318 #define AMSCOM_PLL_CTRL_8_MMD_PRSC8OR9PWDB_MASK 0x0800 11319 #define AMSCOM_PLL_CTRL_8_MMD_PRSC8OR9PWDB_ALIGN 0 11320 #define AMSCOM_PLL_CTRL_8_MMD_PRSC8OR9PWDB_BITS 1 11321 #define AMSCOM_PLL_CTRL_8_MMD_PRSC8OR9PWDB_SHIFT 11 11322 11323 /* AMSCOM :: PLL_CTRL_8 :: mmd_div_range [10:10] */ 11324 #define AMSCOM_PLL_CTRL_8_MMD_DIV_RANGE_MASK 0x0400 11325 #define AMSCOM_PLL_CTRL_8_MMD_DIV_RANGE_ALIGN 0 11326 #define AMSCOM_PLL_CTRL_8_MMD_DIV_RANGE_BITS 1 11327 #define AMSCOM_PLL_CTRL_8_MMD_DIV_RANGE_SHIFT 10 11328 11329 /* AMSCOM :: PLL_CTRL_8 :: i_ndiv_int [09:00] */ 11330 #define AMSCOM_PLL_CTRL_8_I_NDIV_INT_MASK 0x03ff 11331 #define AMSCOM_PLL_CTRL_8_I_NDIV_INT_ALIGN 0 11332 #define AMSCOM_PLL_CTRL_8_I_NDIV_INT_BITS 10 11333 #define AMSCOM_PLL_CTRL_8_I_NDIV_INT_SHIFT 0 11334 11335 11336 /**************************************************************************** 11337 * AMSCOM :: PLL_CTRL_9 11338 */ 11339 /* AMSCOM :: PLL_CTRL_9 :: refclk_out_bias [15:14] */ 11340 #define AMSCOM_PLL_CTRL_9_REFCLK_OUT_BIAS_MASK 0xc000 11341 #define AMSCOM_PLL_CTRL_9_REFCLK_OUT_BIAS_ALIGN 0 11342 #define AMSCOM_PLL_CTRL_9_REFCLK_OUT_BIAS_BITS 2 11343 #define AMSCOM_PLL_CTRL_9_REFCLK_OUT_BIAS_SHIFT 14 11344 11345 /* AMSCOM :: PLL_CTRL_9 :: bias_iq_ctrl [13:11] */ 11346 #define AMSCOM_PLL_CTRL_9_BIAS_IQ_CTRL_MASK 0x3800 11347 #define AMSCOM_PLL_CTRL_9_BIAS_IQ_CTRL_ALIGN 0 11348 #define AMSCOM_PLL_CTRL_9_BIAS_IQ_CTRL_BITS 3 11349 #define AMSCOM_PLL_CTRL_9_BIAS_IQ_CTRL_SHIFT 11 11350 11351 /* AMSCOM :: PLL_CTRL_9 :: bias_div_ctrl [10:08] */ 11352 #define AMSCOM_PLL_CTRL_9_BIAS_DIV_CTRL_MASK 0x0700 11353 #define AMSCOM_PLL_CTRL_9_BIAS_DIV_CTRL_ALIGN 0 11354 #define AMSCOM_PLL_CTRL_9_BIAS_DIV_CTRL_BITS 3 11355 #define AMSCOM_PLL_CTRL_9_BIAS_DIV_CTRL_SHIFT 8 11356 11357 /* AMSCOM :: PLL_CTRL_9 :: low_supply_en [07:07] */ 11358 #define AMSCOM_PLL_CTRL_9_LOW_SUPPLY_EN_MASK 0x0080 11359 #define AMSCOM_PLL_CTRL_9_LOW_SUPPLY_EN_ALIGN 0 11360 #define AMSCOM_PLL_CTRL_9_LOW_SUPPLY_EN_BITS 1 11361 #define AMSCOM_PLL_CTRL_9_LOW_SUPPLY_EN_SHIFT 7 11362 11363 /* AMSCOM :: PLL_CTRL_9 :: sel_fp3cap [06:03] */ 11364 #define AMSCOM_PLL_CTRL_9_SEL_FP3CAP_MASK 0x0078 11365 #define AMSCOM_PLL_CTRL_9_SEL_FP3CAP_ALIGN 0 11366 #define AMSCOM_PLL_CTRL_9_SEL_FP3CAP_BITS 4 11367 #define AMSCOM_PLL_CTRL_9_SEL_FP3CAP_SHIFT 3 11368 11369 /* AMSCOM :: PLL_CTRL_9 :: i_pll_frac_mode [02:01] */ 11370 #define AMSCOM_PLL_CTRL_9_I_PLL_FRAC_MODE_MASK 0x0006 11371 #define AMSCOM_PLL_CTRL_9_I_PLL_FRAC_MODE_ALIGN 0 11372 #define AMSCOM_PLL_CTRL_9_I_PLL_FRAC_MODE_BITS 2 11373 #define AMSCOM_PLL_CTRL_9_I_PLL_FRAC_MODE_SHIFT 1 11374 11375 /* AMSCOM :: PLL_CTRL_9 :: mmd_resetb [00:00] */ 11376 #define AMSCOM_PLL_CTRL_9_MMD_RESETB_MASK 0x0001 11377 #define AMSCOM_PLL_CTRL_9_MMD_RESETB_ALIGN 0 11378 #define AMSCOM_PLL_CTRL_9_MMD_RESETB_BITS 1 11379 #define AMSCOM_PLL_CTRL_9_MMD_RESETB_SHIFT 0 11380 11381 11382 /**************************************************************************** 11383 * AMSCOM :: PLL_CTRL_10 11384 */ 11385 /* AMSCOM :: PLL_CTRL_10 :: reserved0 [15:13] */ 11386 #define AMSCOM_PLL_CTRL_10_RESERVED0_MASK 0xe000 11387 #define AMSCOM_PLL_CTRL_10_RESERVED0_ALIGN 0 11388 #define AMSCOM_PLL_CTRL_10_RESERVED0_BITS 3 11389 #define AMSCOM_PLL_CTRL_10_RESERVED0_SHIFT 13 11390 11391 /* AMSCOM :: PLL_CTRL_10 :: pll_spare_10_0 [12:06] */ 11392 #define AMSCOM_PLL_CTRL_10_PLL_SPARE_10_0_MASK 0x1fc0 11393 #define AMSCOM_PLL_CTRL_10_PLL_SPARE_10_0_ALIGN 0 11394 #define AMSCOM_PLL_CTRL_10_PLL_SPARE_10_0_BITS 7 11395 #define AMSCOM_PLL_CTRL_10_PLL_SPARE_10_0_SHIFT 6 11396 11397 /* AMSCOM :: PLL_CTRL_10 :: refclk_in_bias [05:00] */ 11398 #define AMSCOM_PLL_CTRL_10_REFCLK_IN_BIAS_MASK 0x003f 11399 #define AMSCOM_PLL_CTRL_10_REFCLK_IN_BIAS_ALIGN 0 11400 #define AMSCOM_PLL_CTRL_10_REFCLK_IN_BIAS_BITS 6 11401 #define AMSCOM_PLL_CTRL_10_REFCLK_IN_BIAS_SHIFT 0 11402 11403 11404 /**************************************************************************** 11405 * merlin_gallardo_sigdet_blk_SIGDET 11406 */ 11407 /**************************************************************************** 11408 * SIGDET :: SIGDET_CTRL_0 11409 */ 11410 /* SIGDET :: SIGDET_CTRL_0 :: reserved0 [15:15] */ 11411 #define SIGDET_SIGDET_CTRL_0_RESERVED0_MASK 0x8000 11412 #define SIGDET_SIGDET_CTRL_0_RESERVED0_ALIGN 0 11413 #define SIGDET_SIGDET_CTRL_0_RESERVED0_BITS 1 11414 #define SIGDET_SIGDET_CTRL_0_RESERVED0_SHIFT 15 11415 11416 /* SIGDET :: SIGDET_CTRL_0 :: energy_detect_mask_count [14:10] */ 11417 #define SIGDET_SIGDET_CTRL_0_ENERGY_DETECT_MASK_COUNT_MASK 0x7c00 11418 #define SIGDET_SIGDET_CTRL_0_ENERGY_DETECT_MASK_COUNT_ALIGN 0 11419 #define SIGDET_SIGDET_CTRL_0_ENERGY_DETECT_MASK_COUNT_BITS 5 11420 #define SIGDET_SIGDET_CTRL_0_ENERGY_DETECT_MASK_COUNT_SHIFT 10 11421 11422 /* SIGDET :: SIGDET_CTRL_0 :: los_filter_count [09:05] */ 11423 #define SIGDET_SIGDET_CTRL_0_LOS_FILTER_COUNT_MASK 0x03e0 11424 #define SIGDET_SIGDET_CTRL_0_LOS_FILTER_COUNT_ALIGN 0 11425 #define SIGDET_SIGDET_CTRL_0_LOS_FILTER_COUNT_BITS 5 11426 #define SIGDET_SIGDET_CTRL_0_LOS_FILTER_COUNT_SHIFT 5 11427 11428 /* SIGDET :: SIGDET_CTRL_0 :: signal_detect_filter_count [04:00] */ 11429 #define SIGDET_SIGDET_CTRL_0_SIGNAL_DETECT_FILTER_COUNT_MASK 0x001f 11430 #define SIGDET_SIGDET_CTRL_0_SIGNAL_DETECT_FILTER_COUNT_ALIGN 0 11431 #define SIGDET_SIGDET_CTRL_0_SIGNAL_DETECT_FILTER_COUNT_BITS 5 11432 #define SIGDET_SIGDET_CTRL_0_SIGNAL_DETECT_FILTER_COUNT_SHIFT 0 11433 11434 11435 /**************************************************************************** 11436 * SIGDET :: SIGDET_CTRL_1 11437 */ 11438 /* SIGDET :: SIGDET_CTRL_1 :: reserved0 [15:09] */ 11439 #define SIGDET_SIGDET_CTRL_1_RESERVED0_MASK 0xfe00 11440 #define SIGDET_SIGDET_CTRL_1_RESERVED0_ALIGN 0 11441 #define SIGDET_SIGDET_CTRL_1_RESERVED0_BITS 7 11442 #define SIGDET_SIGDET_CTRL_1_RESERVED0_SHIFT 9 11443 11444 /* SIGDET :: SIGDET_CTRL_1 :: signal_detect_frc_val [08:08] */ 11445 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FRC_VAL_MASK 0x0100 11446 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FRC_VAL_ALIGN 0 11447 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FRC_VAL_BITS 1 11448 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FRC_VAL_SHIFT 8 11449 11450 /* SIGDET :: SIGDET_CTRL_1 :: signal_detect_frc [07:07] */ 11451 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FRC_MASK 0x0080 11452 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FRC_ALIGN 0 11453 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FRC_BITS 1 11454 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FRC_SHIFT 7 11455 11456 /* SIGDET :: SIGDET_CTRL_1 :: energy_detect_frc_val [06:06] */ 11457 #define SIGDET_SIGDET_CTRL_1_ENERGY_DETECT_FRC_VAL_MASK 0x0040 11458 #define SIGDET_SIGDET_CTRL_1_ENERGY_DETECT_FRC_VAL_ALIGN 0 11459 #define SIGDET_SIGDET_CTRL_1_ENERGY_DETECT_FRC_VAL_BITS 1 11460 #define SIGDET_SIGDET_CTRL_1_ENERGY_DETECT_FRC_VAL_SHIFT 6 11461 11462 /* SIGDET :: SIGDET_CTRL_1 :: energy_detect_frc [05:05] */ 11463 #define SIGDET_SIGDET_CTRL_1_ENERGY_DETECT_FRC_MASK 0x0020 11464 #define SIGDET_SIGDET_CTRL_1_ENERGY_DETECT_FRC_ALIGN 0 11465 #define SIGDET_SIGDET_CTRL_1_ENERGY_DETECT_FRC_BITS 1 11466 #define SIGDET_SIGDET_CTRL_1_ENERGY_DETECT_FRC_SHIFT 5 11467 11468 /* SIGDET :: SIGDET_CTRL_1 :: signal_detect_filter_1us [04:04] */ 11469 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FILTER_1US_MASK 0x0010 11470 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FILTER_1US_ALIGN 0 11471 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FILTER_1US_BITS 1 11472 #define SIGDET_SIGDET_CTRL_1_SIGNAL_DETECT_FILTER_1US_SHIFT 4 11473 11474 /* SIGDET :: SIGDET_CTRL_1 :: ignore_lp_mode [03:03] */ 11475 #define SIGDET_SIGDET_CTRL_1_IGNORE_LP_MODE_MASK 0x0008 11476 #define SIGDET_SIGDET_CTRL_1_IGNORE_LP_MODE_ALIGN 0 11477 #define SIGDET_SIGDET_CTRL_1_IGNORE_LP_MODE_BITS 1 11478 #define SIGDET_SIGDET_CTRL_1_IGNORE_LP_MODE_SHIFT 3 11479 11480 /* SIGDET :: SIGDET_CTRL_1 :: ext_los_inv [02:02] */ 11481 #define SIGDET_SIGDET_CTRL_1_EXT_LOS_INV_MASK 0x0004 11482 #define SIGDET_SIGDET_CTRL_1_EXT_LOS_INV_ALIGN 0 11483 #define SIGDET_SIGDET_CTRL_1_EXT_LOS_INV_BITS 1 11484 #define SIGDET_SIGDET_CTRL_1_EXT_LOS_INV_SHIFT 2 11485 11486 /* SIGDET :: SIGDET_CTRL_1 :: ext_los_en [01:01] */ 11487 #define SIGDET_SIGDET_CTRL_1_EXT_LOS_EN_MASK 0x0002 11488 #define SIGDET_SIGDET_CTRL_1_EXT_LOS_EN_ALIGN 0 11489 #define SIGDET_SIGDET_CTRL_1_EXT_LOS_EN_BITS 1 11490 #define SIGDET_SIGDET_CTRL_1_EXT_LOS_EN_SHIFT 1 11491 11492 /* SIGDET :: SIGDET_CTRL_1 :: afe_signal_detect_dis [00:00] */ 11493 #define SIGDET_SIGDET_CTRL_1_AFE_SIGNAL_DETECT_DIS_MASK 0x0001 11494 #define SIGDET_SIGDET_CTRL_1_AFE_SIGNAL_DETECT_DIS_ALIGN 0 11495 #define SIGDET_SIGDET_CTRL_1_AFE_SIGNAL_DETECT_DIS_BITS 1 11496 #define SIGDET_SIGDET_CTRL_1_AFE_SIGNAL_DETECT_DIS_SHIFT 0 11497 11498 11499 /**************************************************************************** 11500 * SIGDET :: SIGDET_CTRL_2 11501 */ 11502 /* SIGDET :: SIGDET_CTRL_2 :: reserved0 [15:14] */ 11503 #define SIGDET_SIGDET_CTRL_2_RESERVED0_MASK 0xc000 11504 #define SIGDET_SIGDET_CTRL_2_RESERVED0_ALIGN 0 11505 #define SIGDET_SIGDET_CTRL_2_RESERVED0_BITS 2 11506 #define SIGDET_SIGDET_CTRL_2_RESERVED0_SHIFT 14 11507 11508 /* SIGDET :: SIGDET_CTRL_2 :: hold_sd_count [13:11] */ 11509 #define SIGDET_SIGDET_CTRL_2_HOLD_SD_COUNT_MASK 0x3800 11510 #define SIGDET_SIGDET_CTRL_2_HOLD_SD_COUNT_ALIGN 0 11511 #define SIGDET_SIGDET_CTRL_2_HOLD_SD_COUNT_BITS 3 11512 #define SIGDET_SIGDET_CTRL_2_HOLD_SD_COUNT_SHIFT 11 11513 11514 /* SIGDET :: SIGDET_CTRL_2 :: hold_los_count [10:08] */ 11515 #define SIGDET_SIGDET_CTRL_2_HOLD_LOS_COUNT_MASK 0x0700 11516 #define SIGDET_SIGDET_CTRL_2_HOLD_LOS_COUNT_ALIGN 0 11517 #define SIGDET_SIGDET_CTRL_2_HOLD_LOS_COUNT_BITS 3 11518 #define SIGDET_SIGDET_CTRL_2_HOLD_LOS_COUNT_SHIFT 8 11519 11520 /* SIGDET :: SIGDET_CTRL_2 :: signal_detect_thresh [07:04] */ 11521 #define SIGDET_SIGDET_CTRL_2_SIGNAL_DETECT_THRESH_MASK 0x00f0 11522 #define SIGDET_SIGDET_CTRL_2_SIGNAL_DETECT_THRESH_ALIGN 0 11523 #define SIGDET_SIGDET_CTRL_2_SIGNAL_DETECT_THRESH_BITS 4 11524 #define SIGDET_SIGDET_CTRL_2_SIGNAL_DETECT_THRESH_SHIFT 4 11525 11526 /* SIGDET :: SIGDET_CTRL_2 :: los_thresh [03:00] */ 11527 #define SIGDET_SIGDET_CTRL_2_LOS_THRESH_MASK 0x000f 11528 #define SIGDET_SIGDET_CTRL_2_LOS_THRESH_ALIGN 0 11529 #define SIGDET_SIGDET_CTRL_2_LOS_THRESH_BITS 4 11530 #define SIGDET_SIGDET_CTRL_2_LOS_THRESH_SHIFT 0 11531 11532 11533 /**************************************************************************** 11534 * SIGDET :: SIGDET_STATUS_0 11535 */ 11536 /* SIGDET :: SIGDET_STATUS_0 :: reserved0 [15:12] */ 11537 #define SIGDET_SIGDET_STATUS_0_RESERVED0_MASK 0xf000 11538 #define SIGDET_SIGDET_STATUS_0_RESERVED0_ALIGN 0 11539 #define SIGDET_SIGDET_STATUS_0_RESERVED0_BITS 4 11540 #define SIGDET_SIGDET_STATUS_0_RESERVED0_SHIFT 12 11541 11542 /* SIGDET :: SIGDET_STATUS_0 :: afe_sigdet_thresh [11:08] */ 11543 #define SIGDET_SIGDET_STATUS_0_AFE_SIGDET_THRESH_MASK 0x0f00 11544 #define SIGDET_SIGDET_STATUS_0_AFE_SIGDET_THRESH_ALIGN 0 11545 #define SIGDET_SIGDET_STATUS_0_AFE_SIGDET_THRESH_BITS 4 11546 #define SIGDET_SIGDET_STATUS_0_AFE_SIGDET_THRESH_SHIFT 8 11547 11548 /* SIGDET :: SIGDET_STATUS_0 :: reserved1 [07:06] */ 11549 #define SIGDET_SIGDET_STATUS_0_RESERVED1_MASK 0x00c0 11550 #define SIGDET_SIGDET_STATUS_0_RESERVED1_ALIGN 0 11551 #define SIGDET_SIGDET_STATUS_0_RESERVED1_BITS 2 11552 #define SIGDET_SIGDET_STATUS_0_RESERVED1_SHIFT 6 11553 11554 /* SIGDET :: SIGDET_STATUS_0 :: signal_detect_raw_change [05:05] */ 11555 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_RAW_CHANGE_MASK 0x0020 11556 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_RAW_CHANGE_ALIGN 0 11557 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_RAW_CHANGE_BITS 1 11558 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_RAW_CHANGE_SHIFT 5 11559 11560 /* SIGDET :: SIGDET_STATUS_0 :: signal_detect_raw [04:04] */ 11561 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_RAW_MASK 0x0010 11562 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_RAW_ALIGN 0 11563 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_RAW_BITS 1 11564 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_RAW_SHIFT 4 11565 11566 /* SIGDET :: SIGDET_STATUS_0 :: energy_detect_change [03:03] */ 11567 #define SIGDET_SIGDET_STATUS_0_ENERGY_DETECT_CHANGE_MASK 0x0008 11568 #define SIGDET_SIGDET_STATUS_0_ENERGY_DETECT_CHANGE_ALIGN 0 11569 #define SIGDET_SIGDET_STATUS_0_ENERGY_DETECT_CHANGE_BITS 1 11570 #define SIGDET_SIGDET_STATUS_0_ENERGY_DETECT_CHANGE_SHIFT 3 11571 11572 /* SIGDET :: SIGDET_STATUS_0 :: energy_detect [02:02] */ 11573 #define SIGDET_SIGDET_STATUS_0_ENERGY_DETECT_MASK 0x0004 11574 #define SIGDET_SIGDET_STATUS_0_ENERGY_DETECT_ALIGN 0 11575 #define SIGDET_SIGDET_STATUS_0_ENERGY_DETECT_BITS 1 11576 #define SIGDET_SIGDET_STATUS_0_ENERGY_DETECT_SHIFT 2 11577 11578 /* SIGDET :: SIGDET_STATUS_0 :: signal_detect_change [01:01] */ 11579 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_CHANGE_MASK 0x0002 11580 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_CHANGE_ALIGN 0 11581 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_CHANGE_BITS 1 11582 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_CHANGE_SHIFT 1 11583 11584 /* SIGDET :: SIGDET_STATUS_0 :: signal_detect [00:00] */ 11585 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_MASK 0x0001 11586 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_ALIGN 0 11587 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_BITS 1 11588 #define SIGDET_SIGDET_STATUS_0_SIGNAL_DETECT_SHIFT 0 11589 11590 11591 /**************************************************************************** 11592 * merlin_gallardo_tlb_blk_TLB_RX 11593 */ 11594 /**************************************************************************** 11595 * TLB_RX :: prbs_chk_config 11596 */ 11597 /* TLB_RX :: prbs_chk_config :: reserved0 [15:11] */ 11598 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED0_MASK 0xf800 11599 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED0_ALIGN 0 11600 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED0_BITS 5 11601 #define TLB_RX_PRBS_CHK_CONFIG_RESERVED0_SHIFT 11 11602 11603 /* TLB_RX :: prbs_chk_config :: trnsum_error_count_en [10:10] */ 11604 #define TLB_RX_PRBS_CHK_CONFIG_TRNSUM_ERROR_COUNT_EN_MASK 0x0400 11605 #define TLB_RX_PRBS_CHK_CONFIG_TRNSUM_ERROR_COUNT_EN_ALIGN 0 11606 #define TLB_RX_PRBS_CHK_CONFIG_TRNSUM_ERROR_COUNT_EN_BITS 1 11607 #define TLB_RX_PRBS_CHK_CONFIG_TRNSUM_ERROR_COUNT_EN_SHIFT 10 11608 11609 /* TLB_RX :: prbs_chk_config :: prbs_chk_err_cnt_burst_mode [09:09] */ 11610 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_ERR_CNT_BURST_MODE_MASK 0x0200 11611 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_ERR_CNT_BURST_MODE_ALIGN 0 11612 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_ERR_CNT_BURST_MODE_BITS 1 11613 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_ERR_CNT_BURST_MODE_SHIFT 9 11614 11615 /* TLB_RX :: prbs_chk_config :: prbs_chk_out_of_lock_mode_31 [08:08] */ 11616 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_OUT_OF_LOCK_MODE_31_MASK 0x0100 11617 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_OUT_OF_LOCK_MODE_31_ALIGN 0 11618 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_OUT_OF_LOCK_MODE_31_BITS 1 11619 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_OUT_OF_LOCK_MODE_31_SHIFT 8 11620 11621 /* TLB_RX :: prbs_chk_config :: prbs_chk_en_auto_mode [07:07] */ 11622 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_AUTO_MODE_MASK 0x0080 11623 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_AUTO_MODE_ALIGN 0 11624 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_AUTO_MODE_BITS 1 11625 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_AUTO_MODE_SHIFT 7 11626 11627 /* TLB_RX :: prbs_chk_config :: prbs_chk_mode [06:05] */ 11628 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_MASK 0x0060 11629 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_ALIGN 0 11630 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_BITS 2 11631 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SHIFT 5 11632 11633 /* TLB_RX :: prbs_chk_config :: prbs_chk_inv [04:04] */ 11634 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_INV_MASK 0x0010 11635 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_INV_ALIGN 0 11636 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_INV_BITS 1 11637 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_INV_SHIFT 4 11638 11639 /* TLB_RX :: prbs_chk_config :: prbs_chk_mode_sel [03:01] */ 11640 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SEL_MASK 0x000e 11641 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SEL_ALIGN 0 11642 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SEL_BITS 3 11643 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_MODE_SEL_SHIFT 1 11644 11645 /* TLB_RX :: prbs_chk_config :: prbs_chk_en [00:00] */ 11646 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_MASK 0x0001 11647 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_ALIGN 0 11648 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_BITS 1 11649 #define TLB_RX_PRBS_CHK_CONFIG_PRBS_CHK_EN_SHIFT 0 11650 11651 11652 /**************************************************************************** 11653 * TLB_RX :: dig_lpbk_config 11654 */ 11655 /* TLB_RX :: dig_lpbk_config :: reserved0 [15:03] */ 11656 #define TLB_RX_DIG_LPBK_CONFIG_RESERVED0_MASK 0xfff8 11657 #define TLB_RX_DIG_LPBK_CONFIG_RESERVED0_ALIGN 0 11658 #define TLB_RX_DIG_LPBK_CONFIG_RESERVED0_BITS 13 11659 #define TLB_RX_DIG_LPBK_CONFIG_RESERVED0_SHIFT 3 11660 11661 /* TLB_RX :: dig_lpbk_config :: dig_lpbk_pd_flt_bypass [02:02] */ 11662 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_FLT_BYPASS_MASK 0x0004 11663 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_FLT_BYPASS_ALIGN 0 11664 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_FLT_BYPASS_BITS 1 11665 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_FLT_BYPASS_SHIFT 2 11666 11667 /* TLB_RX :: dig_lpbk_config :: dig_lpbk_pd_mode [01:01] */ 11668 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_MODE_MASK 0x0002 11669 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_MODE_ALIGN 0 11670 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_MODE_BITS 1 11671 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_PD_MODE_SHIFT 1 11672 11673 /* TLB_RX :: dig_lpbk_config :: dig_lpbk_en [00:00] */ 11674 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_EN_MASK 0x0001 11675 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_EN_ALIGN 0 11676 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_EN_BITS 1 11677 #define TLB_RX_DIG_LPBK_CONFIG_DIG_LPBK_EN_SHIFT 0 11678 11679 11680 /**************************************************************************** 11681 * TLB_RX :: tlb_rx_misc_config 11682 */ 11683 /* TLB_RX :: tlb_rx_misc_config :: reserved0 [15:03] */ 11684 #define TLB_RX_TLB_RX_MISC_CONFIG_RESERVED0_MASK 0xfff8 11685 #define TLB_RX_TLB_RX_MISC_CONFIG_RESERVED0_ALIGN 0 11686 #define TLB_RX_TLB_RX_MISC_CONFIG_RESERVED0_BITS 13 11687 #define TLB_RX_TLB_RX_MISC_CONFIG_RESERVED0_SHIFT 3 11688 11689 /* TLB_RX :: tlb_rx_misc_config :: dbg_mask_dig_lpbk_en [02:02] */ 11690 #define TLB_RX_TLB_RX_MISC_CONFIG_DBG_MASK_DIG_LPBK_EN_MASK 0x0004 11691 #define TLB_RX_TLB_RX_MISC_CONFIG_DBG_MASK_DIG_LPBK_EN_ALIGN 0 11692 #define TLB_RX_TLB_RX_MISC_CONFIG_DBG_MASK_DIG_LPBK_EN_BITS 1 11693 #define TLB_RX_TLB_RX_MISC_CONFIG_DBG_MASK_DIG_LPBK_EN_SHIFT 2 11694 11695 /* TLB_RX :: tlb_rx_misc_config :: rx_aggregator_bypass_en [01:01] */ 11696 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_AGGREGATOR_BYPASS_EN_MASK 0x0002 11697 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_AGGREGATOR_BYPASS_EN_ALIGN 0 11698 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_AGGREGATOR_BYPASS_EN_BITS 1 11699 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_AGGREGATOR_BYPASS_EN_SHIFT 1 11700 11701 /* TLB_RX :: tlb_rx_misc_config :: rx_pmd_dp_invert [00:00] */ 11702 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_PMD_DP_INVERT_MASK 0x0001 11703 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_PMD_DP_INVERT_ALIGN 0 11704 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_PMD_DP_INVERT_BITS 1 11705 #define TLB_RX_TLB_RX_MISC_CONFIG_RX_PMD_DP_INVERT_SHIFT 0 11706 11707 11708 /**************************************************************************** 11709 * TLB_RX :: prbs_chk_en_timer_control 11710 */ 11711 /* TLB_RX :: prbs_chk_en_timer_control :: reserved0 [15:09] */ 11712 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED0_MASK 0xfe00 11713 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED0_ALIGN 0 11714 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED0_BITS 7 11715 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED0_SHIFT 9 11716 11717 /* TLB_RX :: prbs_chk_en_timer_control :: prbs_chk_en_timeout [08:04] */ 11718 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMEOUT_MASK 0x01f0 11719 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMEOUT_ALIGN 0 11720 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMEOUT_BITS 5 11721 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMEOUT_SHIFT 4 11722 11723 /* TLB_RX :: prbs_chk_en_timer_control :: reserved1 [03:02] */ 11724 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED1_MASK 0x000c 11725 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED1_ALIGN 0 11726 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED1_BITS 2 11727 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_RESERVED1_SHIFT 2 11728 11729 /* TLB_RX :: prbs_chk_en_timer_control :: prbs_chk_en_timer_mode [01:00] */ 11730 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMER_MODE_MASK 0x0003 11731 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMER_MODE_ALIGN 0 11732 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMER_MODE_BITS 2 11733 #define TLB_RX_PRBS_CHK_EN_TIMER_CONTROL_PRBS_CHK_EN_TIMER_MODE_SHIFT 0 11734 11735 11736 /**************************************************************************** 11737 * TLB_RX :: dig_lpbk_pd_status 11738 */ 11739 /* TLB_RX :: dig_lpbk_pd_status :: reserved0 [15:02] */ 11740 #define TLB_RX_DIG_LPBK_PD_STATUS_RESERVED0_MASK 0xfffc 11741 #define TLB_RX_DIG_LPBK_PD_STATUS_RESERVED0_ALIGN 0 11742 #define TLB_RX_DIG_LPBK_PD_STATUS_RESERVED0_BITS 14 11743 #define TLB_RX_DIG_LPBK_PD_STATUS_RESERVED0_SHIFT 2 11744 11745 /* TLB_RX :: dig_lpbk_pd_status :: dig_lpbk_pd_early_ind [01:01] */ 11746 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_EARLY_IND_MASK 0x0002 11747 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_EARLY_IND_ALIGN 0 11748 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_EARLY_IND_BITS 1 11749 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_EARLY_IND_SHIFT 1 11750 11751 /* TLB_RX :: dig_lpbk_pd_status :: dig_lpbk_pd_late_ind [00:00] */ 11752 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_LATE_IND_MASK 0x0001 11753 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_LATE_IND_ALIGN 0 11754 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_LATE_IND_BITS 1 11755 #define TLB_RX_DIG_LPBK_PD_STATUS_DIG_LPBK_PD_LATE_IND_SHIFT 0 11756 11757 11758 /**************************************************************************** 11759 * TLB_RX :: prbs_chk_lock_status 11760 */ 11761 /* TLB_RX :: prbs_chk_lock_status :: reserved0 [15:01] */ 11762 #define TLB_RX_PRBS_CHK_LOCK_STATUS_RESERVED0_MASK 0xfffe 11763 #define TLB_RX_PRBS_CHK_LOCK_STATUS_RESERVED0_ALIGN 0 11764 #define TLB_RX_PRBS_CHK_LOCK_STATUS_RESERVED0_BITS 15 11765 #define TLB_RX_PRBS_CHK_LOCK_STATUS_RESERVED0_SHIFT 1 11766 11767 /* TLB_RX :: prbs_chk_lock_status :: prbs_chk_lock [00:00] */ 11768 #define TLB_RX_PRBS_CHK_LOCK_STATUS_PRBS_CHK_LOCK_MASK 0x0001 11769 #define TLB_RX_PRBS_CHK_LOCK_STATUS_PRBS_CHK_LOCK_ALIGN 0 11770 #define TLB_RX_PRBS_CHK_LOCK_STATUS_PRBS_CHK_LOCK_BITS 1 11771 #define TLB_RX_PRBS_CHK_LOCK_STATUS_PRBS_CHK_LOCK_SHIFT 0 11772 11773 11774 /**************************************************************************** 11775 * TLB_RX :: prbs_chk_err_cnt_msb_status 11776 */ 11777 /* TLB_RX :: prbs_chk_err_cnt_msb_status :: prbs_chk_lock_lost_lh [15:15] */ 11778 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_LOCK_LOST_LH_MASK 0x8000 11779 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_LOCK_LOST_LH_ALIGN 0 11780 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_LOCK_LOST_LH_BITS 1 11781 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_LOCK_LOST_LH_SHIFT 15 11782 11783 /* TLB_RX :: prbs_chk_err_cnt_msb_status :: prbs_chk_err_cnt_msb [14:00] */ 11784 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_ERR_CNT_MSB_MASK 0x7fff 11785 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_ERR_CNT_MSB_ALIGN 0 11786 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_ERR_CNT_MSB_BITS 15 11787 #define TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_PRBS_CHK_ERR_CNT_MSB_SHIFT 0 11788 11789 11790 /**************************************************************************** 11791 * TLB_RX :: prbs_chk_err_cnt_lsb_status 11792 */ 11793 /* TLB_RX :: prbs_chk_err_cnt_lsb_status :: prbs_chk_err_cnt_lsb [15:00] */ 11794 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_PRBS_CHK_ERR_CNT_LSB_MASK 0xffff 11795 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_PRBS_CHK_ERR_CNT_LSB_ALIGN 0 11796 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_PRBS_CHK_ERR_CNT_LSB_BITS 16 11797 #define TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_PRBS_CHK_ERR_CNT_LSB_SHIFT 0 11798 11799 11800 /**************************************************************************** 11801 * TLB_RX :: pmd_rx_lock_status 11802 */ 11803 /* TLB_RX :: pmd_rx_lock_status :: reserved0 [15:02] */ 11804 #define TLB_RX_PMD_RX_LOCK_STATUS_RESERVED0_MASK 0xfffc 11805 #define TLB_RX_PMD_RX_LOCK_STATUS_RESERVED0_ALIGN 0 11806 #define TLB_RX_PMD_RX_LOCK_STATUS_RESERVED0_BITS 14 11807 #define TLB_RX_PMD_RX_LOCK_STATUS_RESERVED0_SHIFT 2 11808 11809 /* TLB_RX :: pmd_rx_lock_status :: pmd_rx_lock_change [01:01] */ 11810 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_CHANGE_MASK 0x0002 11811 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_CHANGE_ALIGN 0 11812 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_CHANGE_BITS 1 11813 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_CHANGE_SHIFT 1 11814 11815 /* TLB_RX :: pmd_rx_lock_status :: pmd_rx_lock [00:00] */ 11816 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_MASK 0x0001 11817 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_ALIGN 0 11818 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_BITS 1 11819 #define TLB_RX_PMD_RX_LOCK_STATUS_PMD_RX_LOCK_SHIFT 0 11820 11821 11822 /**************************************************************************** 11823 * merlin_gallardo_tlb_blk_TLB_TX 11824 */ 11825 /**************************************************************************** 11826 * TLB_TX :: patt_gen_config 11827 */ 11828 /* TLB_TX :: patt_gen_config :: reserved0 [15:04] */ 11829 #define TLB_TX_PATT_GEN_CONFIG_RESERVED0_MASK 0xfff0 11830 #define TLB_TX_PATT_GEN_CONFIG_RESERVED0_ALIGN 0 11831 #define TLB_TX_PATT_GEN_CONFIG_RESERVED0_BITS 12 11832 #define TLB_TX_PATT_GEN_CONFIG_RESERVED0_SHIFT 4 11833 11834 /* TLB_TX :: patt_gen_config :: patt_gen_mode_sel [03:01] */ 11835 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_MODE_SEL_MASK 0x000e 11836 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_MODE_SEL_ALIGN 0 11837 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_MODE_SEL_BITS 3 11838 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_MODE_SEL_SHIFT 1 11839 11840 /* TLB_TX :: patt_gen_config :: patt_gen_en [00:00] */ 11841 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_EN_MASK 0x0001 11842 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_EN_ALIGN 0 11843 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_EN_BITS 1 11844 #define TLB_TX_PATT_GEN_CONFIG_PATT_GEN_EN_SHIFT 0 11845 11846 11847 /**************************************************************************** 11848 * TLB_TX :: prbs_gen_config 11849 */ 11850 /* TLB_TX :: prbs_gen_config :: reserved0 [15:06] */ 11851 #define TLB_TX_PRBS_GEN_CONFIG_RESERVED0_MASK 0xffc0 11852 #define TLB_TX_PRBS_GEN_CONFIG_RESERVED0_ALIGN 0 11853 #define TLB_TX_PRBS_GEN_CONFIG_RESERVED0_BITS 10 11854 #define TLB_TX_PRBS_GEN_CONFIG_RESERVED0_SHIFT 6 11855 11856 /* TLB_TX :: prbs_gen_config :: prbs_gen_err_ins [05:05] */ 11857 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_ERR_INS_MASK 0x0020 11858 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_ERR_INS_ALIGN 0 11859 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_ERR_INS_BITS 1 11860 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_ERR_INS_SHIFT 5 11861 11862 /* TLB_TX :: prbs_gen_config :: prbs_gen_inv [04:04] */ 11863 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_INV_MASK 0x0010 11864 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_INV_ALIGN 0 11865 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_INV_BITS 1 11866 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_INV_SHIFT 4 11867 11868 /* TLB_TX :: prbs_gen_config :: prbs_gen_mode_sel [03:01] */ 11869 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_MODE_SEL_MASK 0x000e 11870 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_MODE_SEL_ALIGN 0 11871 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_MODE_SEL_BITS 3 11872 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_MODE_SEL_SHIFT 1 11873 11874 /* TLB_TX :: prbs_gen_config :: prbs_gen_en [00:00] */ 11875 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_EN_MASK 0x0001 11876 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_EN_ALIGN 0 11877 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_EN_BITS 1 11878 #define TLB_TX_PRBS_GEN_CONFIG_PRBS_GEN_EN_SHIFT 0 11879 11880 11881 /**************************************************************************** 11882 * TLB_TX :: rmt_lpbk_config 11883 */ 11884 /* TLB_TX :: rmt_lpbk_config :: reserved0 [15:02] */ 11885 #define TLB_TX_RMT_LPBK_CONFIG_RESERVED0_MASK 0xfffc 11886 #define TLB_TX_RMT_LPBK_CONFIG_RESERVED0_ALIGN 0 11887 #define TLB_TX_RMT_LPBK_CONFIG_RESERVED0_BITS 14 11888 #define TLB_TX_RMT_LPBK_CONFIG_RESERVED0_SHIFT 2 11889 11890 /* TLB_TX :: rmt_lpbk_config :: rmt_lpbk_pd_mode [01:01] */ 11891 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_MODE_MASK 0x0002 11892 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_MODE_ALIGN 0 11893 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_MODE_BITS 1 11894 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_PD_MODE_SHIFT 1 11895 11896 /* TLB_TX :: rmt_lpbk_config :: rmt_lpbk_en [00:00] */ 11897 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_EN_MASK 0x0001 11898 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_EN_ALIGN 0 11899 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_EN_BITS 1 11900 #define TLB_TX_RMT_LPBK_CONFIG_RMT_LPBK_EN_SHIFT 0 11901 11902 11903 /**************************************************************************** 11904 * TLB_TX :: tlb_tx_misc_config 11905 */ 11906 /* TLB_TX :: tlb_tx_misc_config :: reserved0 [15:03] */ 11907 #define TLB_TX_TLB_TX_MISC_CONFIG_RESERVED0_MASK 0xfff8 11908 #define TLB_TX_TLB_TX_MISC_CONFIG_RESERVED0_ALIGN 0 11909 #define TLB_TX_TLB_TX_MISC_CONFIG_RESERVED0_BITS 13 11910 #define TLB_TX_TLB_TX_MISC_CONFIG_RESERVED0_SHIFT 3 11911 11912 /* TLB_TX :: tlb_tx_misc_config :: tx_mux_sel_order [02:02] */ 11913 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_MUX_SEL_ORDER_MASK 0x0004 11914 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_MUX_SEL_ORDER_ALIGN 0 11915 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_MUX_SEL_ORDER_BITS 1 11916 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_MUX_SEL_ORDER_SHIFT 2 11917 11918 /* TLB_TX :: tlb_tx_misc_config :: tx_pcs_native_ana_frmt_en [01:01] */ 11919 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PCS_NATIVE_ANA_FRMT_EN_MASK 0x0002 11920 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PCS_NATIVE_ANA_FRMT_EN_ALIGN 0 11921 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PCS_NATIVE_ANA_FRMT_EN_BITS 1 11922 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PCS_NATIVE_ANA_FRMT_EN_SHIFT 1 11923 11924 /* TLB_TX :: tlb_tx_misc_config :: tx_pmd_dp_invert [00:00] */ 11925 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PMD_DP_INVERT_MASK 0x0001 11926 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PMD_DP_INVERT_ALIGN 0 11927 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PMD_DP_INVERT_BITS 1 11928 #define TLB_TX_TLB_TX_MISC_CONFIG_TX_PMD_DP_INVERT_SHIFT 0 11929 11930 11931 /**************************************************************************** 11932 * TLB_TX :: rmt_lpbk_pd_status 11933 */ 11934 /* TLB_TX :: rmt_lpbk_pd_status :: reserved0 [15:02] */ 11935 #define TLB_TX_RMT_LPBK_PD_STATUS_RESERVED0_MASK 0xfffc 11936 #define TLB_TX_RMT_LPBK_PD_STATUS_RESERVED0_ALIGN 0 11937 #define TLB_TX_RMT_LPBK_PD_STATUS_RESERVED0_BITS 14 11938 #define TLB_TX_RMT_LPBK_PD_STATUS_RESERVED0_SHIFT 2 11939 11940 /* TLB_TX :: rmt_lpbk_pd_status :: rmt_lpbk_pd_early_ind [01:01] */ 11941 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_EARLY_IND_MASK 0x0002 11942 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_EARLY_IND_ALIGN 0 11943 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_EARLY_IND_BITS 1 11944 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_EARLY_IND_SHIFT 1 11945 11946 /* TLB_TX :: rmt_lpbk_pd_status :: rmt_lpbk_pd_late_ind [00:00] */ 11947 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_LATE_IND_MASK 0x0001 11948 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_LATE_IND_ALIGN 0 11949 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_LATE_IND_BITS 1 11950 #define TLB_TX_RMT_LPBK_PD_STATUS_RMT_LPBK_PD_LATE_IND_SHIFT 0 11951 11952 11953 /**************************************************************************** 11954 * merlin_gallardo_digcom_blk_DIGCOM 11955 */ 11956 /**************************************************************************** 11957 * DIGCOM :: REVID0 11958 */ 11959 /* DIGCOM :: REVID0 :: rev_letter [15:14] */ 11960 #define DIGCOM_REVID0_REV_LETTER_MASK 0xc000 11961 #define DIGCOM_REVID0_REV_LETTER_ALIGN 0 11962 #define DIGCOM_REVID0_REV_LETTER_BITS 2 11963 #define DIGCOM_REVID0_REV_LETTER_SHIFT 14 11964 11965 /* DIGCOM :: REVID0 :: rev_number [13:11] */ 11966 #define DIGCOM_REVID0_REV_NUMBER_MASK 0x3800 11967 #define DIGCOM_REVID0_REV_NUMBER_ALIGN 0 11968 #define DIGCOM_REVID0_REV_NUMBER_BITS 3 11969 #define DIGCOM_REVID0_REV_NUMBER_SHIFT 11 11970 11971 /* DIGCOM :: REVID0 :: bonding [10:09] */ 11972 #define DIGCOM_REVID0_BONDING_MASK 0x0600 11973 #define DIGCOM_REVID0_BONDING_ALIGN 0 11974 #define DIGCOM_REVID0_BONDING_BITS 2 11975 #define DIGCOM_REVID0_BONDING_SHIFT 9 11976 11977 /* DIGCOM :: REVID0 :: process [08:06] */ 11978 #define DIGCOM_REVID0_PROCESS_MASK 0x01c0 11979 #define DIGCOM_REVID0_PROCESS_ALIGN 0 11980 #define DIGCOM_REVID0_PROCESS_BITS 3 11981 #define DIGCOM_REVID0_PROCESS_SHIFT 6 11982 11983 /* DIGCOM :: REVID0 :: model [05:00] */ 11984 #define DIGCOM_REVID0_MODEL_MASK 0x003f 11985 #define DIGCOM_REVID0_MODEL_ALIGN 0 11986 #define DIGCOM_REVID0_MODEL_BITS 6 11987 #define DIGCOM_REVID0_MODEL_SHIFT 0 11988 11989 11990 /**************************************************************************** 11991 * DIGCOM :: RESET_CONTROL_PMD 11992 */ 11993 /* DIGCOM :: RESET_CONTROL_PMD :: reserved0 [15:01] */ 11994 #define DIGCOM_RESET_CONTROL_PMD_RESERVED0_MASK 0xfffe 11995 #define DIGCOM_RESET_CONTROL_PMD_RESERVED0_ALIGN 0 11996 #define DIGCOM_RESET_CONTROL_PMD_RESERVED0_BITS 15 11997 #define DIGCOM_RESET_CONTROL_PMD_RESERVED0_SHIFT 1 11998 11999 /* DIGCOM :: RESET_CONTROL_PMD :: pmd_s_rstb [00:00] */ 12000 #define DIGCOM_RESET_CONTROL_PMD_PMD_S_RSTB_MASK 0x0001 12001 #define DIGCOM_RESET_CONTROL_PMD_PMD_S_RSTB_ALIGN 0 12002 #define DIGCOM_RESET_CONTROL_PMD_PMD_S_RSTB_BITS 1 12003 #define DIGCOM_RESET_CONTROL_PMD_PMD_S_RSTB_SHIFT 0 12004 12005 12006 /**************************************************************************** 12007 * DIGCOM :: RESET_CONTROL_CORE_DP 12008 */ 12009 /* DIGCOM :: RESET_CONTROL_CORE_DP :: reserved0 [15:07] */ 12010 #define DIGCOM_RESET_CONTROL_CORE_DP_RESERVED0_MASK 0xff80 12011 #define DIGCOM_RESET_CONTROL_CORE_DP_RESERVED0_ALIGN 0 12012 #define DIGCOM_RESET_CONTROL_CORE_DP_RESERVED0_BITS 9 12013 #define DIGCOM_RESET_CONTROL_CORE_DP_RESERVED0_SHIFT 7 12014 12015 /* DIGCOM :: RESET_CONTROL_CORE_DP :: uc_active [06:06] */ 12016 #define DIGCOM_RESET_CONTROL_CORE_DP_UC_ACTIVE_MASK 0x0040 12017 #define DIGCOM_RESET_CONTROL_CORE_DP_UC_ACTIVE_ALIGN 0 12018 #define DIGCOM_RESET_CONTROL_CORE_DP_UC_ACTIVE_BITS 1 12019 #define DIGCOM_RESET_CONTROL_CORE_DP_UC_ACTIVE_SHIFT 6 12020 12021 /* DIGCOM :: RESET_CONTROL_CORE_DP :: pmd_mdio_trans_pkill [05:05] */ 12022 #define DIGCOM_RESET_CONTROL_CORE_DP_PMD_MDIO_TRANS_PKILL_MASK 0x0020 12023 #define DIGCOM_RESET_CONTROL_CORE_DP_PMD_MDIO_TRANS_PKILL_ALIGN 0 12024 #define DIGCOM_RESET_CONTROL_CORE_DP_PMD_MDIO_TRANS_PKILL_BITS 1 12025 #define DIGCOM_RESET_CONTROL_CORE_DP_PMD_MDIO_TRANS_PKILL_SHIFT 5 12026 12027 /* DIGCOM :: RESET_CONTROL_CORE_DP :: sup_rst_seq_frc [04:04] */ 12028 #define DIGCOM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_MASK 0x0010 12029 #define DIGCOM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_ALIGN 0 12030 #define DIGCOM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_BITS 1 12031 #define DIGCOM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_FRC_SHIFT 4 12032 12033 /* DIGCOM :: RESET_CONTROL_CORE_DP :: sup_rst_seq [03:03] */ 12034 #define DIGCOM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_MASK 0x0008 12035 #define DIGCOM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_ALIGN 0 12036 #define DIGCOM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_BITS 1 12037 #define DIGCOM_RESET_CONTROL_CORE_DP_SUP_RST_SEQ_SHIFT 3 12038 12039 /* DIGCOM :: RESET_CONTROL_CORE_DP :: afe_s_pll_pwrdn [02:02] */ 12040 #define DIGCOM_RESET_CONTROL_CORE_DP_AFE_S_PLL_PWRDN_MASK 0x0004 12041 #define DIGCOM_RESET_CONTROL_CORE_DP_AFE_S_PLL_PWRDN_ALIGN 0 12042 #define DIGCOM_RESET_CONTROL_CORE_DP_AFE_S_PLL_PWRDN_BITS 1 12043 #define DIGCOM_RESET_CONTROL_CORE_DP_AFE_S_PLL_PWRDN_SHIFT 2 12044 12045 /* DIGCOM :: RESET_CONTROL_CORE_DP :: pmd_core_dp_h_rstb_pkill [01:01] */ 12046 #define DIGCOM_RESET_CONTROL_CORE_DP_PMD_CORE_DP_H_RSTB_PKILL_MASK 0x0002 12047 #define DIGCOM_RESET_CONTROL_CORE_DP_PMD_CORE_DP_H_RSTB_PKILL_ALIGN 0 12048 #define DIGCOM_RESET_CONTROL_CORE_DP_PMD_CORE_DP_H_RSTB_PKILL_BITS 1 12049 #define DIGCOM_RESET_CONTROL_CORE_DP_PMD_CORE_DP_H_RSTB_PKILL_SHIFT 1 12050 12051 /* DIGCOM :: RESET_CONTROL_CORE_DP :: core_dp_s_rstb [00:00] */ 12052 #define DIGCOM_RESET_CONTROL_CORE_DP_CORE_DP_S_RSTB_MASK 0x0001 12053 #define DIGCOM_RESET_CONTROL_CORE_DP_CORE_DP_S_RSTB_ALIGN 0 12054 #define DIGCOM_RESET_CONTROL_CORE_DP_CORE_DP_S_RSTB_BITS 1 12055 #define DIGCOM_RESET_CONTROL_CORE_DP_CORE_DP_S_RSTB_SHIFT 0 12056 12057 12058 /**************************************************************************** 12059 * DIGCOM :: LANE_MASK 12060 */ 12061 /* DIGCOM :: LANE_MASK :: reserved0 [15:04] */ 12062 #define DIGCOM_LANE_MASK_RESERVED0_MASK 0xfff0 12063 #define DIGCOM_LANE_MASK_RESERVED0_ALIGN 0 12064 #define DIGCOM_LANE_MASK_RESERVED0_BITS 12 12065 #define DIGCOM_LANE_MASK_RESERVED0_SHIFT 4 12066 12067 /* DIGCOM :: LANE_MASK :: lane_mask [03:00] */ 12068 #define DIGCOM_LANE_MASK_LANE_MASK_MASK 0x000f 12069 #define DIGCOM_LANE_MASK_LANE_MASK_ALIGN 0 12070 #define DIGCOM_LANE_MASK_LANE_MASK_BITS 4 12071 #define DIGCOM_LANE_MASK_LANE_MASK_SHIFT 0 12072 12073 12074 /**************************************************************************** 12075 * DIGCOM :: HEARTBEAT_TIMER_CONTROL 12076 */ 12077 /* DIGCOM :: HEARTBEAT_TIMER_CONTROL :: reserved0 [15:10] */ 12078 #define DIGCOM_HEARTBEAT_TIMER_CONTROL_RESERVED0_MASK 0xfc00 12079 #define DIGCOM_HEARTBEAT_TIMER_CONTROL_RESERVED0_ALIGN 0 12080 #define DIGCOM_HEARTBEAT_TIMER_CONTROL_RESERVED0_BITS 6 12081 #define DIGCOM_HEARTBEAT_TIMER_CONTROL_RESERVED0_SHIFT 10 12082 12083 /* DIGCOM :: HEARTBEAT_TIMER_CONTROL :: heartbeat_count_1us [09:00] */ 12084 #define DIGCOM_HEARTBEAT_TIMER_CONTROL_HEARTBEAT_COUNT_1US_MASK 0x03ff 12085 #define DIGCOM_HEARTBEAT_TIMER_CONTROL_HEARTBEAT_COUNT_1US_ALIGN 0 12086 #define DIGCOM_HEARTBEAT_TIMER_CONTROL_HEARTBEAT_COUNT_1US_BITS 10 12087 #define DIGCOM_HEARTBEAT_TIMER_CONTROL_HEARTBEAT_COUNT_1US_SHIFT 0 12088 12089 12090 /**************************************************************************** 12091 * DIGCOM :: UC_ACK_CORE_CONTROL 12092 */ 12093 /* DIGCOM :: UC_ACK_CORE_CONTROL :: reserved0 [15:02] */ 12094 #define DIGCOM_UC_ACK_CORE_CONTROL_RESERVED0_MASK 0xfffc 12095 #define DIGCOM_UC_ACK_CORE_CONTROL_RESERVED0_ALIGN 0 12096 #define DIGCOM_UC_ACK_CORE_CONTROL_RESERVED0_BITS 14 12097 #define DIGCOM_UC_ACK_CORE_CONTROL_RESERVED0_SHIFT 2 12098 12099 /* DIGCOM :: UC_ACK_CORE_CONTROL :: uc_ack_core_dp_reset [01:01] */ 12100 #define DIGCOM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_DP_RESET_MASK 0x0002 12101 #define DIGCOM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_DP_RESET_ALIGN 0 12102 #define DIGCOM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_DP_RESET_BITS 1 12103 #define DIGCOM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_DP_RESET_SHIFT 1 12104 12105 /* DIGCOM :: UC_ACK_CORE_CONTROL :: uc_ack_core_cfg_done [00:00] */ 12106 #define DIGCOM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_CFG_DONE_MASK 0x0001 12107 #define DIGCOM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_CFG_DONE_ALIGN 0 12108 #define DIGCOM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_CFG_DONE_BITS 1 12109 #define DIGCOM_UC_ACK_CORE_CONTROL_UC_ACK_CORE_CFG_DONE_SHIFT 0 12110 12111 12112 /**************************************************************************** 12113 * DIGCOM :: CORE_REG_RESET_OCCURRED_CONTROL 12114 */ 12115 /* DIGCOM :: CORE_REG_RESET_OCCURRED_CONTROL :: reserved0 [15:01] */ 12116 #define DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL_RESERVED0_MASK 0xfffe 12117 #define DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL_RESERVED0_ALIGN 0 12118 #define DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL_RESERVED0_BITS 15 12119 #define DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL_RESERVED0_SHIFT 1 12120 12121 /* DIGCOM :: CORE_REG_RESET_OCCURRED_CONTROL :: core_reg_reset_occurred [00:00] */ 12122 #define DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL_CORE_REG_RESET_OCCURRED_MASK 0x0001 12123 #define DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL_CORE_REG_RESET_OCCURRED_ALIGN 0 12124 #define DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL_CORE_REG_RESET_OCCURRED_BITS 1 12125 #define DIGCOM_CORE_REG_RESET_OCCURRED_CONTROL_CORE_REG_RESET_OCCURRED_SHIFT 0 12126 12127 12128 /**************************************************************************** 12129 * DIGCOM :: RST_SEQ_TIMER_CONTROL 12130 */ 12131 /* DIGCOM :: RST_SEQ_TIMER_CONTROL :: reserved0 [15:09] */ 12132 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RESERVED0_MASK 0xfe00 12133 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RESERVED0_ALIGN 0 12134 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RESERVED0_BITS 7 12135 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RESERVED0_SHIFT 9 12136 12137 /* DIGCOM :: RST_SEQ_TIMER_CONTROL :: rst_seq_timer_en_clkgate [08:08] */ 12138 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_EN_CLKGATE_MASK 0x0100 12139 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_EN_CLKGATE_ALIGN 0 12140 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_EN_CLKGATE_BITS 1 12141 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_EN_CLKGATE_SHIFT 8 12142 12143 /* DIGCOM :: RST_SEQ_TIMER_CONTROL :: reserved1 [07:04] */ 12144 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RESERVED1_MASK 0x00f0 12145 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RESERVED1_ALIGN 0 12146 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RESERVED1_BITS 4 12147 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RESERVED1_SHIFT 4 12148 12149 /* DIGCOM :: RST_SEQ_TIMER_CONTROL :: rst_seq_timer [03:00] */ 12150 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_MASK 0x000f 12151 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_ALIGN 0 12152 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_BITS 4 12153 #define DIGCOM_RST_SEQ_TIMER_CONTROL_RST_SEQ_TIMER_SHIFT 0 12154 12155 12156 /**************************************************************************** 12157 * DIGCOM :: CORE_DP_RESET_STATE_STATUS 12158 */ 12159 /* DIGCOM :: CORE_DP_RESET_STATE_STATUS :: reserved0 [15:15] */ 12160 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED0_MASK 0x8000 12161 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED0_ALIGN 0 12162 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED0_BITS 1 12163 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED0_SHIFT 15 12164 12165 /* DIGCOM :: CORE_DP_RESET_STATE_STATUS :: lane_reset_released [14:14] */ 12166 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_MASK 0x4000 12167 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_ALIGN 0 12168 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_BITS 1 12169 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_SHIFT 14 12170 12171 /* DIGCOM :: CORE_DP_RESET_STATE_STATUS :: reserved1 [13:13] */ 12172 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED1_MASK 0x2000 12173 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED1_ALIGN 0 12174 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED1_BITS 1 12175 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED1_SHIFT 13 12176 12177 /* DIGCOM :: CORE_DP_RESET_STATE_STATUS :: lane_reset_released_index [12:08] */ 12178 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_INDEX_MASK 0x1f00 12179 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_INDEX_ALIGN 0 12180 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_INDEX_BITS 5 12181 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_LANE_RESET_RELEASED_INDEX_SHIFT 8 12182 12183 /* DIGCOM :: CORE_DP_RESET_STATE_STATUS :: reserved2 [07:03] */ 12184 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED2_MASK 0x00f8 12185 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED2_ALIGN 0 12186 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED2_BITS 5 12187 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_RESERVED2_SHIFT 3 12188 12189 /* DIGCOM :: CORE_DP_RESET_STATE_STATUS :: core_dp_reset_state [02:00] */ 12190 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_CORE_DP_RESET_STATE_MASK 0x0007 12191 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_CORE_DP_RESET_STATE_ALIGN 0 12192 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_CORE_DP_RESET_STATE_BITS 3 12193 #define DIGCOM_CORE_DP_RESET_STATE_STATUS_CORE_DP_RESET_STATE_SHIFT 0 12194 12195 12196 /**************************************************************************** 12197 * DIGCOM :: PMD_CORE_MODE_STATUS 12198 */ 12199 /* DIGCOM :: PMD_CORE_MODE_STATUS :: reserved0 [15:08] */ 12200 #define DIGCOM_PMD_CORE_MODE_STATUS_RESERVED0_MASK 0xff00 12201 #define DIGCOM_PMD_CORE_MODE_STATUS_RESERVED0_ALIGN 0 12202 #define DIGCOM_PMD_CORE_MODE_STATUS_RESERVED0_BITS 8 12203 #define DIGCOM_PMD_CORE_MODE_STATUS_RESERVED0_SHIFT 8 12204 12205 /* DIGCOM :: PMD_CORE_MODE_STATUS :: pmd_core_mode [07:00] */ 12206 #define DIGCOM_PMD_CORE_MODE_STATUS_PMD_CORE_MODE_MASK 0x00ff 12207 #define DIGCOM_PMD_CORE_MODE_STATUS_PMD_CORE_MODE_ALIGN 0 12208 #define DIGCOM_PMD_CORE_MODE_STATUS_PMD_CORE_MODE_BITS 8 12209 #define DIGCOM_PMD_CORE_MODE_STATUS_PMD_CORE_MODE_SHIFT 0 12210 12211 12212 /**************************************************************************** 12213 * DIGCOM :: REVID1 12214 */ 12215 /* DIGCOM :: REVID1 :: multiplicity [15:12] */ 12216 #define DIGCOM_REVID1_MULTIPLICITY_MASK 0xf000 12217 #define DIGCOM_REVID1_MULTIPLICITY_ALIGN 0 12218 #define DIGCOM_REVID1_MULTIPLICITY_BITS 4 12219 #define DIGCOM_REVID1_MULTIPLICITY_SHIFT 12 12220 12221 /* DIGCOM :: REVID1 :: reserved0 [11:06] */ 12222 #define DIGCOM_REVID1_RESERVED0_MASK 0x0fc0 12223 #define DIGCOM_REVID1_RESERVED0_ALIGN 0 12224 #define DIGCOM_REVID1_RESERVED0_BITS 6 12225 #define DIGCOM_REVID1_RESERVED0_SHIFT 6 12226 12227 /* DIGCOM :: REVID1 :: mdio [05:05] */ 12228 #define DIGCOM_REVID1_MDIO_MASK 0x0020 12229 #define DIGCOM_REVID1_MDIO_ALIGN 0 12230 #define DIGCOM_REVID1_MDIO_BITS 1 12231 #define DIGCOM_REVID1_MDIO_SHIFT 5 12232 12233 /* DIGCOM :: REVID1 :: micro [04:04] */ 12234 #define DIGCOM_REVID1_MICRO_MASK 0x0010 12235 #define DIGCOM_REVID1_MICRO_ALIGN 0 12236 #define DIGCOM_REVID1_MICRO_BITS 1 12237 #define DIGCOM_REVID1_MICRO_SHIFT 4 12238 12239 /* DIGCOM :: REVID1 :: CL72 [03:03] */ 12240 #define DIGCOM_REVID1_CL72_MASK 0x0008 12241 #define DIGCOM_REVID1_CL72_ALIGN 0 12242 #define DIGCOM_REVID1_CL72_BITS 1 12243 #define DIGCOM_REVID1_CL72_SHIFT 3 12244 12245 /* DIGCOM :: REVID1 :: PIR [02:02] */ 12246 #define DIGCOM_REVID1_PIR_MASK 0x0004 12247 #define DIGCOM_REVID1_PIR_ALIGN 0 12248 #define DIGCOM_REVID1_PIR_BITS 1 12249 #define DIGCOM_REVID1_PIR_SHIFT 2 12250 12251 /* DIGCOM :: REVID1 :: LLP [01:01] */ 12252 #define DIGCOM_REVID1_LLP_MASK 0x0002 12253 #define DIGCOM_REVID1_LLP_ALIGN 0 12254 #define DIGCOM_REVID1_LLP_BITS 1 12255 #define DIGCOM_REVID1_LLP_SHIFT 1 12256 12257 /* DIGCOM :: REVID1 :: EEE [00:00] */ 12258 #define DIGCOM_REVID1_EEE_MASK 0x0001 12259 #define DIGCOM_REVID1_EEE_ALIGN 0 12260 #define DIGCOM_REVID1_EEE_BITS 1 12261 #define DIGCOM_REVID1_EEE_SHIFT 0 12262 12263 12264 /**************************************************************************** 12265 * DIGCOM :: REVID2 12266 */ 12267 /* DIGCOM :: REVID2 :: reserved0 [15:04] */ 12268 #define DIGCOM_REVID2_RESERVED0_MASK 0xfff0 12269 #define DIGCOM_REVID2_RESERVED0_ALIGN 0 12270 #define DIGCOM_REVID2_RESERVED0_BITS 12 12271 #define DIGCOM_REVID2_RESERVED0_SHIFT 4 12272 12273 /* DIGCOM :: REVID2 :: revid2 [03:00] */ 12274 #define DIGCOM_REVID2_REVID2_MASK 0x000f 12275 #define DIGCOM_REVID2_REVID2_ALIGN 0 12276 #define DIGCOM_REVID2_REVID2_BITS 4 12277 #define DIGCOM_REVID2_REVID2_SHIFT 0 12278 12279 12280 /**************************************************************************** 12281 * merlin_gallardo_patt_gen_blk_PATT_GEN 12282 */ 12283 /**************************************************************************** 12284 * PATT_GEN :: patt_gen_seq_0 12285 */ 12286 /* PATT_GEN :: patt_gen_seq_0 :: patt_gen_seq_0 [15:00] */ 12287 #define PATT_GEN_PATT_GEN_SEQ_0_PATT_GEN_SEQ_0_MASK 0xffff 12288 #define PATT_GEN_PATT_GEN_SEQ_0_PATT_GEN_SEQ_0_ALIGN 0 12289 #define PATT_GEN_PATT_GEN_SEQ_0_PATT_GEN_SEQ_0_BITS 16 12290 #define PATT_GEN_PATT_GEN_SEQ_0_PATT_GEN_SEQ_0_SHIFT 0 12291 12292 12293 /**************************************************************************** 12294 * PATT_GEN :: patt_gen_seq_1 12295 */ 12296 /* PATT_GEN :: patt_gen_seq_1 :: patt_gen_seq_1 [15:00] */ 12297 #define PATT_GEN_PATT_GEN_SEQ_1_PATT_GEN_SEQ_1_MASK 0xffff 12298 #define PATT_GEN_PATT_GEN_SEQ_1_PATT_GEN_SEQ_1_ALIGN 0 12299 #define PATT_GEN_PATT_GEN_SEQ_1_PATT_GEN_SEQ_1_BITS 16 12300 #define PATT_GEN_PATT_GEN_SEQ_1_PATT_GEN_SEQ_1_SHIFT 0 12301 12302 12303 /**************************************************************************** 12304 * PATT_GEN :: patt_gen_seq_2 12305 */ 12306 /* PATT_GEN :: patt_gen_seq_2 :: patt_gen_seq_2 [15:00] */ 12307 #define PATT_GEN_PATT_GEN_SEQ_2_PATT_GEN_SEQ_2_MASK 0xffff 12308 #define PATT_GEN_PATT_GEN_SEQ_2_PATT_GEN_SEQ_2_ALIGN 0 12309 #define PATT_GEN_PATT_GEN_SEQ_2_PATT_GEN_SEQ_2_BITS 16 12310 #define PATT_GEN_PATT_GEN_SEQ_2_PATT_GEN_SEQ_2_SHIFT 0 12311 12312 12313 /**************************************************************************** 12314 * PATT_GEN :: patt_gen_seq_3 12315 */ 12316 /* PATT_GEN :: patt_gen_seq_3 :: patt_gen_seq_3 [15:00] */ 12317 #define PATT_GEN_PATT_GEN_SEQ_3_PATT_GEN_SEQ_3_MASK 0xffff 12318 #define PATT_GEN_PATT_GEN_SEQ_3_PATT_GEN_SEQ_3_ALIGN 0 12319 #define PATT_GEN_PATT_GEN_SEQ_3_PATT_GEN_SEQ_3_BITS 16 12320 #define PATT_GEN_PATT_GEN_SEQ_3_PATT_GEN_SEQ_3_SHIFT 0 12321 12322 12323 /**************************************************************************** 12324 * PATT_GEN :: patt_gen_seq_4 12325 */ 12326 /* PATT_GEN :: patt_gen_seq_4 :: patt_gen_seq_4 [15:00] */ 12327 #define PATT_GEN_PATT_GEN_SEQ_4_PATT_GEN_SEQ_4_MASK 0xffff 12328 #define PATT_GEN_PATT_GEN_SEQ_4_PATT_GEN_SEQ_4_ALIGN 0 12329 #define PATT_GEN_PATT_GEN_SEQ_4_PATT_GEN_SEQ_4_BITS 16 12330 #define PATT_GEN_PATT_GEN_SEQ_4_PATT_GEN_SEQ_4_SHIFT 0 12331 12332 12333 /**************************************************************************** 12334 * PATT_GEN :: patt_gen_seq_5 12335 */ 12336 /* PATT_GEN :: patt_gen_seq_5 :: patt_gen_seq_5 [15:00] */ 12337 #define PATT_GEN_PATT_GEN_SEQ_5_PATT_GEN_SEQ_5_MASK 0xffff 12338 #define PATT_GEN_PATT_GEN_SEQ_5_PATT_GEN_SEQ_5_ALIGN 0 12339 #define PATT_GEN_PATT_GEN_SEQ_5_PATT_GEN_SEQ_5_BITS 16 12340 #define PATT_GEN_PATT_GEN_SEQ_5_PATT_GEN_SEQ_5_SHIFT 0 12341 12342 12343 /**************************************************************************** 12344 * PATT_GEN :: patt_gen_seq_6 12345 */ 12346 /* PATT_GEN :: patt_gen_seq_6 :: patt_gen_seq_6 [15:00] */ 12347 #define PATT_GEN_PATT_GEN_SEQ_6_PATT_GEN_SEQ_6_MASK 0xffff 12348 #define PATT_GEN_PATT_GEN_SEQ_6_PATT_GEN_SEQ_6_ALIGN 0 12349 #define PATT_GEN_PATT_GEN_SEQ_6_PATT_GEN_SEQ_6_BITS 16 12350 #define PATT_GEN_PATT_GEN_SEQ_6_PATT_GEN_SEQ_6_SHIFT 0 12351 12352 12353 /**************************************************************************** 12354 * PATT_GEN :: patt_gen_seq_7 12355 */ 12356 /* PATT_GEN :: patt_gen_seq_7 :: patt_gen_seq_7 [15:00] */ 12357 #define PATT_GEN_PATT_GEN_SEQ_7_PATT_GEN_SEQ_7_MASK 0xffff 12358 #define PATT_GEN_PATT_GEN_SEQ_7_PATT_GEN_SEQ_7_ALIGN 0 12359 #define PATT_GEN_PATT_GEN_SEQ_7_PATT_GEN_SEQ_7_BITS 16 12360 #define PATT_GEN_PATT_GEN_SEQ_7_PATT_GEN_SEQ_7_SHIFT 0 12361 12362 12363 /**************************************************************************** 12364 * PATT_GEN :: patt_gen_seq_8 12365 */ 12366 /* PATT_GEN :: patt_gen_seq_8 :: patt_gen_seq_8 [15:00] */ 12367 #define PATT_GEN_PATT_GEN_SEQ_8_PATT_GEN_SEQ_8_MASK 0xffff 12368 #define PATT_GEN_PATT_GEN_SEQ_8_PATT_GEN_SEQ_8_ALIGN 0 12369 #define PATT_GEN_PATT_GEN_SEQ_8_PATT_GEN_SEQ_8_BITS 16 12370 #define PATT_GEN_PATT_GEN_SEQ_8_PATT_GEN_SEQ_8_SHIFT 0 12371 12372 12373 /**************************************************************************** 12374 * PATT_GEN :: patt_gen_seq_9 12375 */ 12376 /* PATT_GEN :: patt_gen_seq_9 :: patt_gen_seq_9 [15:00] */ 12377 #define PATT_GEN_PATT_GEN_SEQ_9_PATT_GEN_SEQ_9_MASK 0xffff 12378 #define PATT_GEN_PATT_GEN_SEQ_9_PATT_GEN_SEQ_9_ALIGN 0 12379 #define PATT_GEN_PATT_GEN_SEQ_9_PATT_GEN_SEQ_9_BITS 16 12380 #define PATT_GEN_PATT_GEN_SEQ_9_PATT_GEN_SEQ_9_SHIFT 0 12381 12382 12383 /**************************************************************************** 12384 * PATT_GEN :: patt_gen_seq_10 12385 */ 12386 /* PATT_GEN :: patt_gen_seq_10 :: patt_gen_seq_10 [15:00] */ 12387 #define PATT_GEN_PATT_GEN_SEQ_10_PATT_GEN_SEQ_10_MASK 0xffff 12388 #define PATT_GEN_PATT_GEN_SEQ_10_PATT_GEN_SEQ_10_ALIGN 0 12389 #define PATT_GEN_PATT_GEN_SEQ_10_PATT_GEN_SEQ_10_BITS 16 12390 #define PATT_GEN_PATT_GEN_SEQ_10_PATT_GEN_SEQ_10_SHIFT 0 12391 12392 12393 /**************************************************************************** 12394 * PATT_GEN :: patt_gen_seq_11 12395 */ 12396 /* PATT_GEN :: patt_gen_seq_11 :: patt_gen_seq_11 [15:00] */ 12397 #define PATT_GEN_PATT_GEN_SEQ_11_PATT_GEN_SEQ_11_MASK 0xffff 12398 #define PATT_GEN_PATT_GEN_SEQ_11_PATT_GEN_SEQ_11_ALIGN 0 12399 #define PATT_GEN_PATT_GEN_SEQ_11_PATT_GEN_SEQ_11_BITS 16 12400 #define PATT_GEN_PATT_GEN_SEQ_11_PATT_GEN_SEQ_11_SHIFT 0 12401 12402 12403 /**************************************************************************** 12404 * PATT_GEN :: patt_gen_seq_12 12405 */ 12406 /* PATT_GEN :: patt_gen_seq_12 :: patt_gen_seq_12 [15:00] */ 12407 #define PATT_GEN_PATT_GEN_SEQ_12_PATT_GEN_SEQ_12_MASK 0xffff 12408 #define PATT_GEN_PATT_GEN_SEQ_12_PATT_GEN_SEQ_12_ALIGN 0 12409 #define PATT_GEN_PATT_GEN_SEQ_12_PATT_GEN_SEQ_12_BITS 16 12410 #define PATT_GEN_PATT_GEN_SEQ_12_PATT_GEN_SEQ_12_SHIFT 0 12411 12412 12413 /**************************************************************************** 12414 * PATT_GEN :: patt_gen_seq_13 12415 */ 12416 /* PATT_GEN :: patt_gen_seq_13 :: patt_gen_seq_13 [15:00] */ 12417 #define PATT_GEN_PATT_GEN_SEQ_13_PATT_GEN_SEQ_13_MASK 0xffff 12418 #define PATT_GEN_PATT_GEN_SEQ_13_PATT_GEN_SEQ_13_ALIGN 0 12419 #define PATT_GEN_PATT_GEN_SEQ_13_PATT_GEN_SEQ_13_BITS 16 12420 #define PATT_GEN_PATT_GEN_SEQ_13_PATT_GEN_SEQ_13_SHIFT 0 12421 12422 12423 /**************************************************************************** 12424 * PATT_GEN :: patt_gen_seq_14 12425 */ 12426 /* PATT_GEN :: patt_gen_seq_14 :: patt_gen_seq_14 [15:00] */ 12427 #define PATT_GEN_PATT_GEN_SEQ_14_PATT_GEN_SEQ_14_MASK 0xffff 12428 #define PATT_GEN_PATT_GEN_SEQ_14_PATT_GEN_SEQ_14_ALIGN 0 12429 #define PATT_GEN_PATT_GEN_SEQ_14_PATT_GEN_SEQ_14_BITS 16 12430 #define PATT_GEN_PATT_GEN_SEQ_14_PATT_GEN_SEQ_14_SHIFT 0 12431 12432 12433 /**************************************************************************** 12434 * merlin_gallardo_tx_fed_blk_TX_FED 12435 */ 12436 /**************************************************************************** 12437 * TX_FED :: txfir_control1 12438 */ 12439 /* TX_FED :: txfir_control1 :: reserved0 [15:10] */ 12440 #define TX_FED_TXFIR_CONTROL1_RESERVED0_MASK 0xfc00 12441 #define TX_FED_TXFIR_CONTROL1_RESERVED0_ALIGN 0 12442 #define TX_FED_TXFIR_CONTROL1_RESERVED0_BITS 6 12443 #define TX_FED_TXFIR_CONTROL1_RESERVED0_SHIFT 10 12444 12445 /* TX_FED :: txfir_control1 :: txfir_post_override [09:05] */ 12446 #define TX_FED_TXFIR_CONTROL1_TXFIR_POST_OVERRIDE_MASK 0x03e0 12447 #define TX_FED_TXFIR_CONTROL1_TXFIR_POST_OVERRIDE_ALIGN 0 12448 #define TX_FED_TXFIR_CONTROL1_TXFIR_POST_OVERRIDE_BITS 5 12449 #define TX_FED_TXFIR_CONTROL1_TXFIR_POST_OVERRIDE_SHIFT 5 12450 12451 /* TX_FED :: txfir_control1 :: reserved1 [04:04] */ 12452 #define TX_FED_TXFIR_CONTROL1_RESERVED1_MASK 0x0010 12453 #define TX_FED_TXFIR_CONTROL1_RESERVED1_ALIGN 0 12454 #define TX_FED_TXFIR_CONTROL1_RESERVED1_BITS 1 12455 #define TX_FED_TXFIR_CONTROL1_RESERVED1_SHIFT 4 12456 12457 /* TX_FED :: txfir_control1 :: txfir_pre_override [03:00] */ 12458 #define TX_FED_TXFIR_CONTROL1_TXFIR_PRE_OVERRIDE_MASK 0x000f 12459 #define TX_FED_TXFIR_CONTROL1_TXFIR_PRE_OVERRIDE_ALIGN 0 12460 #define TX_FED_TXFIR_CONTROL1_TXFIR_PRE_OVERRIDE_BITS 4 12461 #define TX_FED_TXFIR_CONTROL1_TXFIR_PRE_OVERRIDE_SHIFT 0 12462 12463 12464 /**************************************************************************** 12465 * TX_FED :: txfir_control2 12466 */ 12467 /* TX_FED :: txfir_control2 :: txfir_override_en [15:15] */ 12468 #define TX_FED_TXFIR_CONTROL2_TXFIR_OVERRIDE_EN_MASK 0x8000 12469 #define TX_FED_TXFIR_CONTROL2_TXFIR_OVERRIDE_EN_ALIGN 0 12470 #define TX_FED_TXFIR_CONTROL2_TXFIR_OVERRIDE_EN_BITS 1 12471 #define TX_FED_TXFIR_CONTROL2_TXFIR_OVERRIDE_EN_SHIFT 15 12472 12473 /* TX_FED :: txfir_control2 :: reserved0 [14:11] */ 12474 #define TX_FED_TXFIR_CONTROL2_RESERVED0_MASK 0x7800 12475 #define TX_FED_TXFIR_CONTROL2_RESERVED0_ALIGN 0 12476 #define TX_FED_TXFIR_CONTROL2_RESERVED0_BITS 4 12477 #define TX_FED_TXFIR_CONTROL2_RESERVED0_SHIFT 11 12478 12479 /* TX_FED :: txfir_control2 :: txfir_post2 [10:07] */ 12480 #define TX_FED_TXFIR_CONTROL2_TXFIR_POST2_MASK 0x0780 12481 #define TX_FED_TXFIR_CONTROL2_TXFIR_POST2_ALIGN 0 12482 #define TX_FED_TXFIR_CONTROL2_TXFIR_POST2_BITS 4 12483 #define TX_FED_TXFIR_CONTROL2_TXFIR_POST2_SHIFT 7 12484 12485 /* TX_FED :: txfir_control2 :: reserved1 [06:06] */ 12486 #define TX_FED_TXFIR_CONTROL2_RESERVED1_MASK 0x0040 12487 #define TX_FED_TXFIR_CONTROL2_RESERVED1_ALIGN 0 12488 #define TX_FED_TXFIR_CONTROL2_RESERVED1_BITS 1 12489 #define TX_FED_TXFIR_CONTROL2_RESERVED1_SHIFT 6 12490 12491 /* TX_FED :: txfir_control2 :: txfir_main_override [05:00] */ 12492 #define TX_FED_TXFIR_CONTROL2_TXFIR_MAIN_OVERRIDE_MASK 0x003f 12493 #define TX_FED_TXFIR_CONTROL2_TXFIR_MAIN_OVERRIDE_ALIGN 0 12494 #define TX_FED_TXFIR_CONTROL2_TXFIR_MAIN_OVERRIDE_BITS 6 12495 #define TX_FED_TXFIR_CONTROL2_TXFIR_MAIN_OVERRIDE_SHIFT 0 12496 12497 12498 /**************************************************************************** 12499 * TX_FED :: txfir_control3 12500 */ 12501 /* TX_FED :: txfir_control3 :: txfir_post2_offset [15:12] */ 12502 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST2_OFFSET_MASK 0xf000 12503 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST2_OFFSET_ALIGN 0 12504 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST2_OFFSET_BITS 4 12505 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST2_OFFSET_SHIFT 12 12506 12507 /* TX_FED :: txfir_control3 :: txfir_post_offset [11:08] */ 12508 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST_OFFSET_MASK 0x0f00 12509 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST_OFFSET_ALIGN 0 12510 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST_OFFSET_BITS 4 12511 #define TX_FED_TXFIR_CONTROL3_TXFIR_POST_OFFSET_SHIFT 8 12512 12513 /* TX_FED :: txfir_control3 :: txfir_main_offset [07:04] */ 12514 #define TX_FED_TXFIR_CONTROL3_TXFIR_MAIN_OFFSET_MASK 0x00f0 12515 #define TX_FED_TXFIR_CONTROL3_TXFIR_MAIN_OFFSET_ALIGN 0 12516 #define TX_FED_TXFIR_CONTROL3_TXFIR_MAIN_OFFSET_BITS 4 12517 #define TX_FED_TXFIR_CONTROL3_TXFIR_MAIN_OFFSET_SHIFT 4 12518 12519 /* TX_FED :: txfir_control3 :: txfir_pre_offset [03:00] */ 12520 #define TX_FED_TXFIR_CONTROL3_TXFIR_PRE_OFFSET_MASK 0x000f 12521 #define TX_FED_TXFIR_CONTROL3_TXFIR_PRE_OFFSET_ALIGN 0 12522 #define TX_FED_TXFIR_CONTROL3_TXFIR_PRE_OFFSET_BITS 4 12523 #define TX_FED_TXFIR_CONTROL3_TXFIR_PRE_OFFSET_SHIFT 0 12524 12525 12526 /**************************************************************************** 12527 * TX_FED :: txfir_status1 12528 */ 12529 /* TX_FED :: txfir_status1 :: reserved0 [15:10] */ 12530 #define TX_FED_TXFIR_STATUS1_RESERVED0_MASK 0xfc00 12531 #define TX_FED_TXFIR_STATUS1_RESERVED0_ALIGN 0 12532 #define TX_FED_TXFIR_STATUS1_RESERVED0_BITS 6 12533 #define TX_FED_TXFIR_STATUS1_RESERVED0_SHIFT 10 12534 12535 /* TX_FED :: txfir_status1 :: txfir_post_after_ovr [09:05] */ 12536 #define TX_FED_TXFIR_STATUS1_TXFIR_POST_AFTER_OVR_MASK 0x03e0 12537 #define TX_FED_TXFIR_STATUS1_TXFIR_POST_AFTER_OVR_ALIGN 0 12538 #define TX_FED_TXFIR_STATUS1_TXFIR_POST_AFTER_OVR_BITS 5 12539 #define TX_FED_TXFIR_STATUS1_TXFIR_POST_AFTER_OVR_SHIFT 5 12540 12541 /* TX_FED :: txfir_status1 :: reserved1 [04:04] */ 12542 #define TX_FED_TXFIR_STATUS1_RESERVED1_MASK 0x0010 12543 #define TX_FED_TXFIR_STATUS1_RESERVED1_ALIGN 0 12544 #define TX_FED_TXFIR_STATUS1_RESERVED1_BITS 1 12545 #define TX_FED_TXFIR_STATUS1_RESERVED1_SHIFT 4 12546 12547 /* TX_FED :: txfir_status1 :: txfir_pre_after_ovr [03:00] */ 12548 #define TX_FED_TXFIR_STATUS1_TXFIR_PRE_AFTER_OVR_MASK 0x000f 12549 #define TX_FED_TXFIR_STATUS1_TXFIR_PRE_AFTER_OVR_ALIGN 0 12550 #define TX_FED_TXFIR_STATUS1_TXFIR_PRE_AFTER_OVR_BITS 4 12551 #define TX_FED_TXFIR_STATUS1_TXFIR_PRE_AFTER_OVR_SHIFT 0 12552 12553 12554 /**************************************************************************** 12555 * TX_FED :: txfir_status2 12556 */ 12557 /* TX_FED :: txfir_status2 :: reserved0 [15:06] */ 12558 #define TX_FED_TXFIR_STATUS2_RESERVED0_MASK 0xffc0 12559 #define TX_FED_TXFIR_STATUS2_RESERVED0_ALIGN 0 12560 #define TX_FED_TXFIR_STATUS2_RESERVED0_BITS 10 12561 #define TX_FED_TXFIR_STATUS2_RESERVED0_SHIFT 6 12562 12563 /* TX_FED :: txfir_status2 :: txfir_main_after_ovr [05:00] */ 12564 #define TX_FED_TXFIR_STATUS2_TXFIR_MAIN_AFTER_OVR_MASK 0x003f 12565 #define TX_FED_TXFIR_STATUS2_TXFIR_MAIN_AFTER_OVR_ALIGN 0 12566 #define TX_FED_TXFIR_STATUS2_TXFIR_MAIN_AFTER_OVR_BITS 6 12567 #define TX_FED_TXFIR_STATUS2_TXFIR_MAIN_AFTER_OVR_SHIFT 0 12568 12569 12570 /**************************************************************************** 12571 * TX_FED :: txfir_status3 12572 */ 12573 /* TX_FED :: txfir_status3 :: reserved0 [15:10] */ 12574 #define TX_FED_TXFIR_STATUS3_RESERVED0_MASK 0xfc00 12575 #define TX_FED_TXFIR_STATUS3_RESERVED0_ALIGN 0 12576 #define TX_FED_TXFIR_STATUS3_RESERVED0_BITS 6 12577 #define TX_FED_TXFIR_STATUS3_RESERVED0_SHIFT 10 12578 12579 /* TX_FED :: txfir_status3 :: txfir_post_adjusted [09:05] */ 12580 #define TX_FED_TXFIR_STATUS3_TXFIR_POST_ADJUSTED_MASK 0x03e0 12581 #define TX_FED_TXFIR_STATUS3_TXFIR_POST_ADJUSTED_ALIGN 0 12582 #define TX_FED_TXFIR_STATUS3_TXFIR_POST_ADJUSTED_BITS 5 12583 #define TX_FED_TXFIR_STATUS3_TXFIR_POST_ADJUSTED_SHIFT 5 12584 12585 /* TX_FED :: txfir_status3 :: reserved1 [04:04] */ 12586 #define TX_FED_TXFIR_STATUS3_RESERVED1_MASK 0x0010 12587 #define TX_FED_TXFIR_STATUS3_RESERVED1_ALIGN 0 12588 #define TX_FED_TXFIR_STATUS3_RESERVED1_BITS 1 12589 #define TX_FED_TXFIR_STATUS3_RESERVED1_SHIFT 4 12590 12591 /* TX_FED :: txfir_status3 :: txfir_pre_adjusted [03:00] */ 12592 #define TX_FED_TXFIR_STATUS3_TXFIR_PRE_ADJUSTED_MASK 0x000f 12593 #define TX_FED_TXFIR_STATUS3_TXFIR_PRE_ADJUSTED_ALIGN 0 12594 #define TX_FED_TXFIR_STATUS3_TXFIR_PRE_ADJUSTED_BITS 4 12595 #define TX_FED_TXFIR_STATUS3_TXFIR_PRE_ADJUSTED_SHIFT 0 12596 12597 12598 /**************************************************************************** 12599 * TX_FED :: txfir_status4 12600 */ 12601 /* TX_FED :: txfir_status4 :: reserved0 [15:11] */ 12602 #define TX_FED_TXFIR_STATUS4_RESERVED0_MASK 0xf800 12603 #define TX_FED_TXFIR_STATUS4_RESERVED0_ALIGN 0 12604 #define TX_FED_TXFIR_STATUS4_RESERVED0_BITS 5 12605 #define TX_FED_TXFIR_STATUS4_RESERVED0_SHIFT 11 12606 12607 /* TX_FED :: txfir_status4 :: txfir_post2_adjusted [10:07] */ 12608 #define TX_FED_TXFIR_STATUS4_TXFIR_POST2_ADJUSTED_MASK 0x0780 12609 #define TX_FED_TXFIR_STATUS4_TXFIR_POST2_ADJUSTED_ALIGN 0 12610 #define TX_FED_TXFIR_STATUS4_TXFIR_POST2_ADJUSTED_BITS 4 12611 #define TX_FED_TXFIR_STATUS4_TXFIR_POST2_ADJUSTED_SHIFT 7 12612 12613 /* TX_FED :: txfir_status4 :: reserved1 [06:06] */ 12614 #define TX_FED_TXFIR_STATUS4_RESERVED1_MASK 0x0040 12615 #define TX_FED_TXFIR_STATUS4_RESERVED1_ALIGN 0 12616 #define TX_FED_TXFIR_STATUS4_RESERVED1_BITS 1 12617 #define TX_FED_TXFIR_STATUS4_RESERVED1_SHIFT 6 12618 12619 /* TX_FED :: txfir_status4 :: txfir_main_adjusted [05:00] */ 12620 #define TX_FED_TXFIR_STATUS4_TXFIR_MAIN_ADJUSTED_MASK 0x003f 12621 #define TX_FED_TXFIR_STATUS4_TXFIR_MAIN_ADJUSTED_ALIGN 0 12622 #define TX_FED_TXFIR_STATUS4_TXFIR_MAIN_ADJUSTED_BITS 6 12623 #define TX_FED_TXFIR_STATUS4_TXFIR_MAIN_ADJUSTED_SHIFT 0 12624 12625 12626 /**************************************************************************** 12627 * TX_FED :: micro_control 12628 */ 12629 /* TX_FED :: micro_control :: reserved0 [15:01] */ 12630 #define TX_FED_MICRO_CONTROL_RESERVED0_MASK 0xfffe 12631 #define TX_FED_MICRO_CONTROL_RESERVED0_ALIGN 0 12632 #define TX_FED_MICRO_CONTROL_RESERVED0_BITS 15 12633 #define TX_FED_MICRO_CONTROL_RESERVED0_SHIFT 1 12634 12635 /* TX_FED :: micro_control :: micro_tx_disable [00:00] */ 12636 #define TX_FED_MICRO_CONTROL_MICRO_TX_DISABLE_MASK 0x0001 12637 #define TX_FED_MICRO_CONTROL_MICRO_TX_DISABLE_ALIGN 0 12638 #define TX_FED_MICRO_CONTROL_MICRO_TX_DISABLE_BITS 1 12639 #define TX_FED_MICRO_CONTROL_MICRO_TX_DISABLE_SHIFT 0 12640 12641 12642 /**************************************************************************** 12643 * TX_FED :: misc_control1 12644 */ 12645 /* TX_FED :: misc_control1 :: reserved0 [15:13] */ 12646 #define TX_FED_MISC_CONTROL1_RESERVED0_MASK 0xe000 12647 #define TX_FED_MISC_CONTROL1_RESERVED0_ALIGN 0 12648 #define TX_FED_MISC_CONTROL1_RESERVED0_BITS 3 12649 #define TX_FED_MISC_CONTROL1_RESERVED0_SHIFT 13 12650 12651 /* TX_FED :: misc_control1 :: dp_reset_tx_disable_dis [12:12] */ 12652 #define TX_FED_MISC_CONTROL1_DP_RESET_TX_DISABLE_DIS_MASK 0x1000 12653 #define TX_FED_MISC_CONTROL1_DP_RESET_TX_DISABLE_DIS_ALIGN 0 12654 #define TX_FED_MISC_CONTROL1_DP_RESET_TX_DISABLE_DIS_BITS 1 12655 #define TX_FED_MISC_CONTROL1_DP_RESET_TX_DISABLE_DIS_SHIFT 12 12656 12657 /* TX_FED :: misc_control1 :: tx_disable_output_sel [11:10] */ 12658 #define TX_FED_MISC_CONTROL1_TX_DISABLE_OUTPUT_SEL_MASK 0x0c00 12659 #define TX_FED_MISC_CONTROL1_TX_DISABLE_OUTPUT_SEL_ALIGN 0 12660 #define TX_FED_MISC_CONTROL1_TX_DISABLE_OUTPUT_SEL_BITS 2 12661 #define TX_FED_MISC_CONTROL1_TX_DISABLE_OUTPUT_SEL_SHIFT 10 12662 12663 /* TX_FED :: misc_control1 :: tx_eee_alert_en [09:09] */ 12664 #define TX_FED_MISC_CONTROL1_TX_EEE_ALERT_EN_MASK 0x0200 12665 #define TX_FED_MISC_CONTROL1_TX_EEE_ALERT_EN_ALIGN 0 12666 #define TX_FED_MISC_CONTROL1_TX_EEE_ALERT_EN_BITS 1 12667 #define TX_FED_MISC_CONTROL1_TX_EEE_ALERT_EN_SHIFT 9 12668 12669 /* TX_FED :: misc_control1 :: tx_eee_quiet_en [08:08] */ 12670 #define TX_FED_MISC_CONTROL1_TX_EEE_QUIET_EN_MASK 0x0100 12671 #define TX_FED_MISC_CONTROL1_TX_EEE_QUIET_EN_ALIGN 0 12672 #define TX_FED_MISC_CONTROL1_TX_EEE_QUIET_EN_BITS 1 12673 #define TX_FED_MISC_CONTROL1_TX_EEE_QUIET_EN_SHIFT 8 12674 12675 /* TX_FED :: misc_control1 :: tx_disable_timer_ctrl [07:02] */ 12676 #define TX_FED_MISC_CONTROL1_TX_DISABLE_TIMER_CTRL_MASK 0x00fc 12677 #define TX_FED_MISC_CONTROL1_TX_DISABLE_TIMER_CTRL_ALIGN 0 12678 #define TX_FED_MISC_CONTROL1_TX_DISABLE_TIMER_CTRL_BITS 6 12679 #define TX_FED_MISC_CONTROL1_TX_DISABLE_TIMER_CTRL_SHIFT 2 12680 12681 /* TX_FED :: misc_control1 :: pmd_tx_disable_pin_dis [01:01] */ 12682 #define TX_FED_MISC_CONTROL1_PMD_TX_DISABLE_PIN_DIS_MASK 0x0002 12683 #define TX_FED_MISC_CONTROL1_PMD_TX_DISABLE_PIN_DIS_ALIGN 0 12684 #define TX_FED_MISC_CONTROL1_PMD_TX_DISABLE_PIN_DIS_BITS 1 12685 #define TX_FED_MISC_CONTROL1_PMD_TX_DISABLE_PIN_DIS_SHIFT 1 12686 12687 /* TX_FED :: misc_control1 :: sdk_tx_disable [00:00] */ 12688 #define TX_FED_MISC_CONTROL1_SDK_TX_DISABLE_MASK 0x0001 12689 #define TX_FED_MISC_CONTROL1_SDK_TX_DISABLE_ALIGN 0 12690 #define TX_FED_MISC_CONTROL1_SDK_TX_DISABLE_BITS 1 12691 #define TX_FED_MISC_CONTROL1_SDK_TX_DISABLE_SHIFT 0 12692 12693 12694 /**************************************************************************** 12695 * TX_FED :: misc_control2 12696 */ 12697 /* TX_FED :: misc_control2 :: txfir_dc_level_frc_en [15:15] */ 12698 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_FRC_EN_MASK 0x8000 12699 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_FRC_EN_ALIGN 0 12700 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_FRC_EN_BITS 1 12701 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_FRC_EN_SHIFT 15 12702 12703 /* TX_FED :: misc_control2 :: txfir_dc_level_lsb_frc_val [14:14] */ 12704 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_LSB_FRC_VAL_MASK 0x4000 12705 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_LSB_FRC_VAL_ALIGN 0 12706 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_LSB_FRC_VAL_BITS 1 12707 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_LSB_FRC_VAL_SHIFT 14 12708 12709 /* TX_FED :: misc_control2 :: txfir_dc_level_pre_frc_val [13:11] */ 12710 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_PRE_FRC_VAL_MASK 0x3800 12711 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_PRE_FRC_VAL_ALIGN 0 12712 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_PRE_FRC_VAL_BITS 3 12713 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_PRE_FRC_VAL_SHIFT 11 12714 12715 /* TX_FED :: misc_control2 :: txfir_dc_level_post1_frc_val [10:07] */ 12716 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_POST1_FRC_VAL_MASK 0x0780 12717 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_POST1_FRC_VAL_ALIGN 0 12718 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_POST1_FRC_VAL_BITS 4 12719 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_POST1_FRC_VAL_SHIFT 7 12720 12721 /* TX_FED :: misc_control2 :: txfir_dc_level_post2_frc_val [06:03] */ 12722 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_POST2_FRC_VAL_MASK 0x0078 12723 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_POST2_FRC_VAL_ALIGN 0 12724 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_POST2_FRC_VAL_BITS 4 12725 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_POST2_FRC_VAL_SHIFT 3 12726 12727 /* TX_FED :: misc_control2 :: txfir_dc_level_shared_frc_val [02:00] */ 12728 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_SHARED_FRC_VAL_MASK 0x0007 12729 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_SHARED_FRC_VAL_ALIGN 0 12730 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_SHARED_FRC_VAL_BITS 3 12731 #define TX_FED_MISC_CONTROL2_TXFIR_DC_LEVEL_SHARED_FRC_VAL_SHIFT 0 12732 12733 12734 /**************************************************************************** 12735 * TX_FED :: misc_control3 12736 */ 12737 /* TX_FED :: misc_control3 :: reserved0 [15:01] */ 12738 #define TX_FED_MISC_CONTROL3_RESERVED0_MASK 0xfffe 12739 #define TX_FED_MISC_CONTROL3_RESERVED0_ALIGN 0 12740 #define TX_FED_MISC_CONTROL3_RESERVED0_BITS 15 12741 #define TX_FED_MISC_CONTROL3_RESERVED0_SHIFT 1 12742 12743 /* TX_FED :: misc_control3 :: txfir_post2_hw_limit_max_sel [00:00] */ 12744 #define TX_FED_MISC_CONTROL3_TXFIR_POST2_HW_LIMIT_MAX_SEL_MASK 0x0001 12745 #define TX_FED_MISC_CONTROL3_TXFIR_POST2_HW_LIMIT_MAX_SEL_ALIGN 0 12746 #define TX_FED_MISC_CONTROL3_TXFIR_POST2_HW_LIMIT_MAX_SEL_BITS 1 12747 #define TX_FED_MISC_CONTROL3_TXFIR_POST2_HW_LIMIT_MAX_SEL_SHIFT 0 12748 12749 12750 /**************************************************************************** 12751 * merlin_gallardo_pll_cal_blk_PLL_CAL 12752 */ 12753 /**************************************************************************** 12754 * PLL_CAL :: PLL_CALCTL_0 12755 */ 12756 /* PLL_CAL :: PLL_CALCTL_0 :: cal_th [15:14] */ 12757 #define PLL_CAL_PLL_CALCTL_0_CAL_TH_MASK 0xc000 12758 #define PLL_CAL_PLL_CALCTL_0_CAL_TH_ALIGN 0 12759 #define PLL_CAL_PLL_CALCTL_0_CAL_TH_BITS 2 12760 #define PLL_CAL_PLL_CALCTL_0_CAL_TH_SHIFT 14 12761 12762 /* PLL_CAL :: PLL_CALCTL_0 :: reserved0 [13:13] */ 12763 #define PLL_CAL_PLL_CALCTL_0_RESERVED0_MASK 0x2000 12764 #define PLL_CAL_PLL_CALCTL_0_RESERVED0_ALIGN 0 12765 #define PLL_CAL_PLL_CALCTL_0_RESERVED0_BITS 1 12766 #define PLL_CAL_PLL_CALCTL_0_RESERVED0_SHIFT 13 12767 12768 /* PLL_CAL :: PLL_CALCTL_0 :: calib_step_time [12:00] */ 12769 #define PLL_CAL_PLL_CALCTL_0_CALIB_STEP_TIME_MASK 0x1fff 12770 #define PLL_CAL_PLL_CALCTL_0_CALIB_STEP_TIME_ALIGN 0 12771 #define PLL_CAL_PLL_CALCTL_0_CALIB_STEP_TIME_BITS 13 12772 #define PLL_CAL_PLL_CALCTL_0_CALIB_STEP_TIME_SHIFT 0 12773 12774 12775 /**************************************************************************** 12776 * PLL_CAL :: PLL_CALCTL_1 12777 */ 12778 /* PLL_CAL :: PLL_CALCTL_1 :: freqdet_time [15:00] */ 12779 #define PLL_CAL_PLL_CALCTL_1_FREQDET_TIME_MASK 0xffff 12780 #define PLL_CAL_PLL_CALCTL_1_FREQDET_TIME_ALIGN 0 12781 #define PLL_CAL_PLL_CALCTL_1_FREQDET_TIME_BITS 16 12782 #define PLL_CAL_PLL_CALCTL_1_FREQDET_TIME_SHIFT 0 12783 12784 12785 /**************************************************************************** 12786 * PLL_CAL :: PLL_CALCTL_2 12787 */ 12788 /* PLL_CAL :: PLL_CALCTL_2 :: reserved0 [15:12] */ 12789 #define PLL_CAL_PLL_CALCTL_2_RESERVED0_MASK 0xf000 12790 #define PLL_CAL_PLL_CALCTL_2_RESERVED0_ALIGN 0 12791 #define PLL_CAL_PLL_CALCTL_2_RESERVED0_BITS 4 12792 #define PLL_CAL_PLL_CALCTL_2_RESERVED0_SHIFT 12 12793 12794 /* PLL_CAL :: PLL_CALCTL_2 :: calib_cap_charge_time [11:00] */ 12795 #define PLL_CAL_PLL_CALCTL_2_CALIB_CAP_CHARGE_TIME_MASK 0x0fff 12796 #define PLL_CAL_PLL_CALCTL_2_CALIB_CAP_CHARGE_TIME_ALIGN 0 12797 #define PLL_CAL_PLL_CALCTL_2_CALIB_CAP_CHARGE_TIME_BITS 12 12798 #define PLL_CAL_PLL_CALCTL_2_CALIB_CAP_CHARGE_TIME_SHIFT 0 12799 12800 12801 /**************************************************************************** 12802 * PLL_CAL :: PLL_CALCTL_3 12803 */ 12804 /* PLL_CAL :: PLL_CALCTL_3 :: ext_state [15:12] */ 12805 #define PLL_CAL_PLL_CALCTL_3_EXT_STATE_MASK 0xf000 12806 #define PLL_CAL_PLL_CALCTL_3_EXT_STATE_ALIGN 0 12807 #define PLL_CAL_PLL_CALCTL_3_EXT_STATE_BITS 4 12808 #define PLL_CAL_PLL_CALCTL_3_EXT_STATE_SHIFT 12 12809 12810 /* PLL_CAL :: PLL_CALCTL_3 :: accel_en [11:11] */ 12811 #define PLL_CAL_PLL_CALCTL_3_ACCEL_EN_MASK 0x0800 12812 #define PLL_CAL_PLL_CALCTL_3_ACCEL_EN_ALIGN 0 12813 #define PLL_CAL_PLL_CALCTL_3_ACCEL_EN_BITS 1 12814 #define PLL_CAL_PLL_CALCTL_3_ACCEL_EN_SHIFT 11 12815 12816 /* PLL_CAL :: PLL_CALCTL_3 :: debug_clr [10:10] */ 12817 #define PLL_CAL_PLL_CALCTL_3_DEBUG_CLR_MASK 0x0400 12818 #define PLL_CAL_PLL_CALCTL_3_DEBUG_CLR_ALIGN 0 12819 #define PLL_CAL_PLL_CALCTL_3_DEBUG_CLR_BITS 1 12820 #define PLL_CAL_PLL_CALCTL_3_DEBUG_CLR_SHIFT 10 12821 12822 /* PLL_CAL :: PLL_CALCTL_3 :: freqdet_time_msb [09:09] */ 12823 #define PLL_CAL_PLL_CALCTL_3_FREQDET_TIME_MSB_MASK 0x0200 12824 #define PLL_CAL_PLL_CALCTL_3_FREQDET_TIME_MSB_ALIGN 0 12825 #define PLL_CAL_PLL_CALCTL_3_FREQDET_TIME_MSB_BITS 1 12826 #define PLL_CAL_PLL_CALCTL_3_FREQDET_TIME_MSB_SHIFT 9 12827 12828 /* PLL_CAL :: PLL_CALCTL_3 :: reserved0 [08:08] */ 12829 #define PLL_CAL_PLL_CALCTL_3_RESERVED0_MASK 0x0100 12830 #define PLL_CAL_PLL_CALCTL_3_RESERVED0_ALIGN 0 12831 #define PLL_CAL_PLL_CALCTL_3_RESERVED0_BITS 1 12832 #define PLL_CAL_PLL_CALCTL_3_RESERVED0_SHIFT 8 12833 12834 /* PLL_CAL :: PLL_CALCTL_3 :: freqdet_win [07:00] */ 12835 #define PLL_CAL_PLL_CALCTL_3_FREQDET_WIN_MASK 0x00ff 12836 #define PLL_CAL_PLL_CALCTL_3_FREQDET_WIN_ALIGN 0 12837 #define PLL_CAL_PLL_CALCTL_3_FREQDET_WIN_BITS 8 12838 #define PLL_CAL_PLL_CALCTL_3_FREQDET_WIN_SHIFT 0 12839 12840 12841 /**************************************************************************** 12842 * PLL_CAL :: PLL_CALCTL_4 12843 */ 12844 /* PLL_CAL :: PLL_CALCTL_4 :: halfstep_en [15:15] */ 12845 #define PLL_CAL_PLL_CALCTL_4_HALFSTEP_EN_MASK 0x8000 12846 #define PLL_CAL_PLL_CALCTL_4_HALFSTEP_EN_ALIGN 0 12847 #define PLL_CAL_PLL_CALCTL_4_HALFSTEP_EN_BITS 1 12848 #define PLL_CAL_PLL_CALCTL_4_HALFSTEP_EN_SHIFT 15 12849 12850 /* PLL_CAL :: PLL_CALCTL_4 :: pllForceCapPass_en [14:14] */ 12851 #define PLL_CAL_PLL_CALCTL_4_PLLFORCECAPPASS_EN_MASK 0x4000 12852 #define PLL_CAL_PLL_CALCTL_4_PLLFORCECAPPASS_EN_ALIGN 0 12853 #define PLL_CAL_PLL_CALCTL_4_PLLFORCECAPPASS_EN_BITS 1 12854 #define PLL_CAL_PLL_CALCTL_4_PLLFORCECAPPASS_EN_SHIFT 14 12855 12856 /* PLL_CAL :: PLL_CALCTL_4 :: pllForceCapPass [13:13] */ 12857 #define PLL_CAL_PLL_CALCTL_4_PLLFORCECAPPASS_MASK 0x2000 12858 #define PLL_CAL_PLL_CALCTL_4_PLLFORCECAPPASS_ALIGN 0 12859 #define PLL_CAL_PLL_CALCTL_4_PLLFORCECAPPASS_BITS 1 12860 #define PLL_CAL_PLL_CALCTL_4_PLLFORCECAPPASS_SHIFT 13 12861 12862 /* PLL_CAL :: PLL_CALCTL_4 :: cal_pause_en [12:12] */ 12863 #define PLL_CAL_PLL_CALCTL_4_CAL_PAUSE_EN_MASK 0x1000 12864 #define PLL_CAL_PLL_CALCTL_4_CAL_PAUSE_EN_ALIGN 0 12865 #define PLL_CAL_PLL_CALCTL_4_CAL_PAUSE_EN_BITS 1 12866 #define PLL_CAL_PLL_CALCTL_4_CAL_PAUSE_EN_SHIFT 12 12867 12868 /* PLL_CAL :: PLL_CALCTL_4 :: cal_pause_rel [11:11] */ 12869 #define PLL_CAL_PLL_CALCTL_4_CAL_PAUSE_REL_MASK 0x0800 12870 #define PLL_CAL_PLL_CALCTL_4_CAL_PAUSE_REL_ALIGN 0 12871 #define PLL_CAL_PLL_CALCTL_4_CAL_PAUSE_REL_BITS 1 12872 #define PLL_CAL_PLL_CALCTL_4_CAL_PAUSE_REL_SHIFT 11 12873 12874 /* PLL_CAL :: PLL_CALCTL_4 :: cap_delay [10:10] */ 12875 #define PLL_CAL_PLL_CALCTL_4_CAP_DELAY_MASK 0x0400 12876 #define PLL_CAL_PLL_CALCTL_4_CAP_DELAY_ALIGN 0 12877 #define PLL_CAL_PLL_CALCTL_4_CAP_DELAY_BITS 1 12878 #define PLL_CAL_PLL_CALCTL_4_CAP_DELAY_SHIFT 10 12879 12880 /* PLL_CAL :: PLL_CALCTL_4 :: calib_start [09:09] */ 12881 #define PLL_CAL_PLL_CALCTL_4_CALIB_START_MASK 0x0200 12882 #define PLL_CAL_PLL_CALCTL_4_CALIB_START_ALIGN 0 12883 #define PLL_CAL_PLL_CALCTL_4_CALIB_START_BITS 1 12884 #define PLL_CAL_PLL_CALCTL_4_CALIB_START_SHIFT 9 12885 12886 /* PLL_CAL :: PLL_CALCTL_4 :: en_calib_n [08:08] */ 12887 #define PLL_CAL_PLL_CALCTL_4_EN_CALIB_N_MASK 0x0100 12888 #define PLL_CAL_PLL_CALCTL_4_EN_CALIB_N_ALIGN 0 12889 #define PLL_CAL_PLL_CALCTL_4_EN_CALIB_N_BITS 1 12890 #define PLL_CAL_PLL_CALCTL_4_EN_CALIB_N_SHIFT 8 12891 12892 /* PLL_CAL :: PLL_CALCTL_4 :: reserved0 [07:07] */ 12893 #define PLL_CAL_PLL_CALCTL_4_RESERVED0_MASK 0x0080 12894 #define PLL_CAL_PLL_CALCTL_4_RESERVED0_ALIGN 0 12895 #define PLL_CAL_PLL_CALCTL_4_RESERVED0_BITS 1 12896 #define PLL_CAL_PLL_CALCTL_4_RESERVED0_SHIFT 7 12897 12898 /* PLL_CAL :: PLL_CALCTL_4 :: ext_range [06:00] */ 12899 #define PLL_CAL_PLL_CALCTL_4_EXT_RANGE_MASK 0x007f 12900 #define PLL_CAL_PLL_CALCTL_4_EXT_RANGE_ALIGN 0 12901 #define PLL_CAL_PLL_CALCTL_4_EXT_RANGE_BITS 7 12902 #define PLL_CAL_PLL_CALCTL_4_EXT_RANGE_SHIFT 0 12903 12904 12905 /**************************************************************************** 12906 * PLL_CAL :: PLL_CALCTL_5 12907 */ 12908 /* PLL_CAL :: PLL_CALCTL_5 :: pll_seq_start [15:15] */ 12909 #define PLL_CAL_PLL_CALCTL_5_PLL_SEQ_START_MASK 0x8000 12910 #define PLL_CAL_PLL_CALCTL_5_PLL_SEQ_START_ALIGN 0 12911 #define PLL_CAL_PLL_CALCTL_5_PLL_SEQ_START_BITS 1 12912 #define PLL_CAL_PLL_CALCTL_5_PLL_SEQ_START_SHIFT 15 12913 12914 /* PLL_CAL :: PLL_CALCTL_5 :: lkdt_pause_en [14:14] */ 12915 #define PLL_CAL_PLL_CALCTL_5_LKDT_PAUSE_EN_MASK 0x4000 12916 #define PLL_CAL_PLL_CALCTL_5_LKDT_PAUSE_EN_ALIGN 0 12917 #define PLL_CAL_PLL_CALCTL_5_LKDT_PAUSE_EN_BITS 1 12918 #define PLL_CAL_PLL_CALCTL_5_LKDT_PAUSE_EN_SHIFT 14 12919 12920 /* PLL_CAL :: PLL_CALCTL_5 :: lkdt_pause_rel [13:13] */ 12921 #define PLL_CAL_PLL_CALCTL_5_LKDT_PAUSE_REL_MASK 0x2000 12922 #define PLL_CAL_PLL_CALCTL_5_LKDT_PAUSE_REL_ALIGN 0 12923 #define PLL_CAL_PLL_CALCTL_5_LKDT_PAUSE_REL_BITS 1 12924 #define PLL_CAL_PLL_CALCTL_5_LKDT_PAUSE_REL_SHIFT 13 12925 12926 /* PLL_CAL :: PLL_CALCTL_5 :: vco_rst_en [12:12] */ 12927 #define PLL_CAL_PLL_CALCTL_5_VCO_RST_EN_MASK 0x1000 12928 #define PLL_CAL_PLL_CALCTL_5_VCO_RST_EN_ALIGN 0 12929 #define PLL_CAL_PLL_CALCTL_5_VCO_RST_EN_BITS 1 12930 #define PLL_CAL_PLL_CALCTL_5_VCO_RST_EN_SHIFT 12 12931 12932 /* PLL_CAL :: PLL_CALCTL_5 :: reserved0 [11:09] */ 12933 #define PLL_CAL_PLL_CALCTL_5_RESERVED0_MASK 0x0e00 12934 #define PLL_CAL_PLL_CALCTL_5_RESERVED0_ALIGN 0 12935 #define PLL_CAL_PLL_CALCTL_5_RESERVED0_BITS 3 12936 #define PLL_CAL_PLL_CALCTL_5_RESERVED0_SHIFT 9 12937 12938 /* PLL_CAL :: PLL_CALCTL_5 :: autocal_en [08:08] */ 12939 #define PLL_CAL_PLL_CALCTL_5_AUTOCAL_EN_MASK 0x0100 12940 #define PLL_CAL_PLL_CALCTL_5_AUTOCAL_EN_ALIGN 0 12941 #define PLL_CAL_PLL_CALCTL_5_AUTOCAL_EN_BITS 1 12942 #define PLL_CAL_PLL_CALCTL_5_AUTOCAL_EN_SHIFT 8 12943 12944 /* PLL_CAL :: PLL_CALCTL_5 :: autocal_cnt [07:05] */ 12945 #define PLL_CAL_PLL_CALCTL_5_AUTOCAL_CNT_MASK 0x00e0 12946 #define PLL_CAL_PLL_CALCTL_5_AUTOCAL_CNT_ALIGN 0 12947 #define PLL_CAL_PLL_CALCTL_5_AUTOCAL_CNT_BITS 3 12948 #define PLL_CAL_PLL_CALCTL_5_AUTOCAL_CNT_SHIFT 5 12949 12950 /* PLL_CAL :: PLL_CALCTL_5 :: lkdt_byp [04:04] */ 12951 #define PLL_CAL_PLL_CALCTL_5_LKDT_BYP_MASK 0x0010 12952 #define PLL_CAL_PLL_CALCTL_5_LKDT_BYP_ALIGN 0 12953 #define PLL_CAL_PLL_CALCTL_5_LKDT_BYP_BITS 1 12954 #define PLL_CAL_PLL_CALCTL_5_LKDT_BYP_SHIFT 4 12955 12956 /* PLL_CAL :: PLL_CALCTL_5 :: pll_lock_frcval [03:03] */ 12957 #define PLL_CAL_PLL_CALCTL_5_PLL_LOCK_FRCVAL_MASK 0x0008 12958 #define PLL_CAL_PLL_CALCTL_5_PLL_LOCK_FRCVAL_ALIGN 0 12959 #define PLL_CAL_PLL_CALCTL_5_PLL_LOCK_FRCVAL_BITS 1 12960 #define PLL_CAL_PLL_CALCTL_5_PLL_LOCK_FRCVAL_SHIFT 3 12961 12962 /* PLL_CAL :: PLL_CALCTL_5 :: pll_lock_frc [02:02] */ 12963 #define PLL_CAL_PLL_CALCTL_5_PLL_LOCK_FRC_MASK 0x0004 12964 #define PLL_CAL_PLL_CALCTL_5_PLL_LOCK_FRC_ALIGN 0 12965 #define PLL_CAL_PLL_CALCTL_5_PLL_LOCK_FRC_BITS 1 12966 #define PLL_CAL_PLL_CALCTL_5_PLL_LOCK_FRC_SHIFT 2 12967 12968 /* PLL_CAL :: PLL_CALCTL_5 :: pllforce_fdone [01:01] */ 12969 #define PLL_CAL_PLL_CALCTL_5_PLLFORCE_FDONE_MASK 0x0002 12970 #define PLL_CAL_PLL_CALCTL_5_PLLFORCE_FDONE_ALIGN 0 12971 #define PLL_CAL_PLL_CALCTL_5_PLLFORCE_FDONE_BITS 1 12972 #define PLL_CAL_PLL_CALCTL_5_PLLFORCE_FDONE_SHIFT 1 12973 12974 /* PLL_CAL :: PLL_CALCTL_5 :: pllforce_fdone_en [00:00] */ 12975 #define PLL_CAL_PLL_CALCTL_5_PLLFORCE_FDONE_EN_MASK 0x0001 12976 #define PLL_CAL_PLL_CALCTL_5_PLLFORCE_FDONE_EN_ALIGN 0 12977 #define PLL_CAL_PLL_CALCTL_5_PLLFORCE_FDONE_EN_BITS 1 12978 #define PLL_CAL_PLL_CALCTL_5_PLLFORCE_FDONE_EN_SHIFT 0 12979 12980 12981 /**************************************************************************** 12982 * PLL_CAL :: PLL_CALCTL_6 12983 */ 12984 /* PLL_CAL :: PLL_CALCTL_6 :: reserved0 [15:08] */ 12985 #define PLL_CAL_PLL_CALCTL_6_RESERVED0_MASK 0xff00 12986 #define PLL_CAL_PLL_CALCTL_6_RESERVED0_ALIGN 0 12987 #define PLL_CAL_PLL_CALCTL_6_RESERVED0_BITS 8 12988 #define PLL_CAL_PLL_CALCTL_6_RESERVED0_SHIFT 8 12989 12990 /* PLL_CAL :: PLL_CALCTL_6 :: band_iqbuf_sel [07:07] */ 12991 #define PLL_CAL_PLL_CALCTL_6_BAND_IQBUF_SEL_MASK 0x0080 12992 #define PLL_CAL_PLL_CALCTL_6_BAND_IQBUF_SEL_ALIGN 0 12993 #define PLL_CAL_PLL_CALCTL_6_BAND_IQBUF_SEL_BITS 1 12994 #define PLL_CAL_PLL_CALCTL_6_BAND_IQBUF_SEL_SHIFT 7 12995 12996 /* PLL_CAL :: PLL_CALCTL_6 :: vcorange_sel [06:06] */ 12997 #define PLL_CAL_PLL_CALCTL_6_VCORANGE_SEL_MASK 0x0040 12998 #define PLL_CAL_PLL_CALCTL_6_VCORANGE_SEL_ALIGN 0 12999 #define PLL_CAL_PLL_CALCTL_6_VCORANGE_SEL_BITS 1 13000 #define PLL_CAL_PLL_CALCTL_6_VCORANGE_SEL_SHIFT 6 13001 13002 /* PLL_CAL :: PLL_CALCTL_6 :: vcobufpon_sel [05:05] */ 13003 #define PLL_CAL_PLL_CALCTL_6_VCOBUFPON_SEL_MASK 0x0020 13004 #define PLL_CAL_PLL_CALCTL_6_VCOBUFPON_SEL_ALIGN 0 13005 #define PLL_CAL_PLL_CALCTL_6_VCOBUFPON_SEL_BITS 1 13006 #define PLL_CAL_PLL_CALCTL_6_VCOBUFPON_SEL_SHIFT 5 13007 13008 /* PLL_CAL :: PLL_CALCTL_6 :: reserved1 [04:04] */ 13009 #define PLL_CAL_PLL_CALCTL_6_RESERVED1_MASK 0x0010 13010 #define PLL_CAL_PLL_CALCTL_6_RESERVED1_ALIGN 0 13011 #define PLL_CAL_PLL_CALCTL_6_RESERVED1_BITS 1 13012 #define PLL_CAL_PLL_CALCTL_6_RESERVED1_SHIFT 4 13013 13014 /* PLL_CAL :: PLL_CALCTL_6 :: vcopon_sel [03:03] */ 13015 #define PLL_CAL_PLL_CALCTL_6_VCOPON_SEL_MASK 0x0008 13016 #define PLL_CAL_PLL_CALCTL_6_VCOPON_SEL_ALIGN 0 13017 #define PLL_CAL_PLL_CALCTL_6_VCOPON_SEL_BITS 1 13018 #define PLL_CAL_PLL_CALCTL_6_VCOPON_SEL_SHIFT 3 13019 13020 /* PLL_CAL :: PLL_CALCTL_6 :: reserved2 [02:02] */ 13021 #define PLL_CAL_PLL_CALCTL_6_RESERVED2_MASK 0x0004 13022 #define PLL_CAL_PLL_CALCTL_6_RESERVED2_ALIGN 0 13023 #define PLL_CAL_PLL_CALCTL_6_RESERVED2_BITS 1 13024 #define PLL_CAL_PLL_CALCTL_6_RESERVED2_SHIFT 2 13025 13026 /* PLL_CAL :: PLL_CALCTL_6 :: pllpon_sel [01:01] */ 13027 #define PLL_CAL_PLL_CALCTL_6_PLLPON_SEL_MASK 0x0002 13028 #define PLL_CAL_PLL_CALCTL_6_PLLPON_SEL_ALIGN 0 13029 #define PLL_CAL_PLL_CALCTL_6_PLLPON_SEL_BITS 1 13030 #define PLL_CAL_PLL_CALCTL_6_PLLPON_SEL_SHIFT 1 13031 13032 /* PLL_CAL :: PLL_CALCTL_6 :: reserved3 [00:00] */ 13033 #define PLL_CAL_PLL_CALCTL_6_RESERVED3_MASK 0x0001 13034 #define PLL_CAL_PLL_CALCTL_6_RESERVED3_ALIGN 0 13035 #define PLL_CAL_PLL_CALCTL_6_RESERVED3_BITS 1 13036 #define PLL_CAL_PLL_CALCTL_6_RESERVED3_SHIFT 0 13037 13038 13039 /**************************************************************************** 13040 * PLL_CAL :: PLL_CALSTS_0 13041 */ 13042 /* PLL_CAL :: PLL_CALSTS_0 :: pll_fail_stky [15:15] */ 13043 #define PLL_CAL_PLL_CALSTS_0_PLL_FAIL_STKY_MASK 0x8000 13044 #define PLL_CAL_PLL_CALSTS_0_PLL_FAIL_STKY_ALIGN 0 13045 #define PLL_CAL_PLL_CALSTS_0_PLL_FAIL_STKY_BITS 1 13046 #define PLL_CAL_PLL_CALSTS_0_PLL_FAIL_STKY_SHIFT 15 13047 13048 /* PLL_CAL :: PLL_CALSTS_0 :: cal_state [14:11] */ 13049 #define PLL_CAL_PLL_CALSTS_0_CAL_STATE_MASK 0x7800 13050 #define PLL_CAL_PLL_CALSTS_0_CAL_STATE_ALIGN 0 13051 #define PLL_CAL_PLL_CALSTS_0_CAL_STATE_BITS 4 13052 #define PLL_CAL_PLL_CALSTS_0_CAL_STATE_SHIFT 11 13053 13054 /* PLL_CAL :: PLL_CALSTS_0 :: cal_valid [10:10] */ 13055 #define PLL_CAL_PLL_CALSTS_0_CAL_VALID_MASK 0x0400 13056 #define PLL_CAL_PLL_CALSTS_0_CAL_VALID_ALIGN 0 13057 #define PLL_CAL_PLL_CALSTS_0_CAL_VALID_BITS 1 13058 #define PLL_CAL_PLL_CALSTS_0_CAL_VALID_SHIFT 10 13059 13060 /* PLL_CAL :: PLL_CALSTS_0 :: pll_lock [09:09] */ 13061 #define PLL_CAL_PLL_CALSTS_0_PLL_LOCK_MASK 0x0200 13062 #define PLL_CAL_PLL_CALSTS_0_PLL_LOCK_ALIGN 0 13063 #define PLL_CAL_PLL_CALSTS_0_PLL_LOCK_BITS 1 13064 #define PLL_CAL_PLL_CALSTS_0_PLL_LOCK_SHIFT 9 13065 13066 /* PLL_CAL :: PLL_CALSTS_0 :: pll_lock_bar_stky [08:08] */ 13067 #define PLL_CAL_PLL_CALSTS_0_PLL_LOCK_BAR_STKY_MASK 0x0100 13068 #define PLL_CAL_PLL_CALSTS_0_PLL_LOCK_BAR_STKY_ALIGN 0 13069 #define PLL_CAL_PLL_CALSTS_0_PLL_LOCK_BAR_STKY_BITS 1 13070 #define PLL_CAL_PLL_CALSTS_0_PLL_LOCK_BAR_STKY_SHIFT 8 13071 13072 /* PLL_CAL :: PLL_CALSTS_0 :: reserved0 [07:07] */ 13073 #define PLL_CAL_PLL_CALSTS_0_RESERVED0_MASK 0x0080 13074 #define PLL_CAL_PLL_CALSTS_0_RESERVED0_ALIGN 0 13075 #define PLL_CAL_PLL_CALSTS_0_RESERVED0_BITS 1 13076 #define PLL_CAL_PLL_CALSTS_0_RESERVED0_SHIFT 7 13077 13078 /* PLL_CAL :: PLL_CALSTS_0 :: pll_range [06:00] */ 13079 #define PLL_CAL_PLL_CALSTS_0_PLL_RANGE_MASK 0x007f 13080 #define PLL_CAL_PLL_CALSTS_0_PLL_RANGE_ALIGN 0 13081 #define PLL_CAL_PLL_CALSTS_0_PLL_RANGE_BITS 7 13082 #define PLL_CAL_PLL_CALSTS_0_PLL_RANGE_SHIFT 0 13083 13084 13085 /**************************************************************************** 13086 * PLL_CAL :: PLL_CALSTS_1 13087 */ 13088 /* PLL_CAL :: PLL_CALSTS_1 :: lkdtref_counter_msb [15:15] */ 13089 #define PLL_CAL_PLL_CALSTS_1_LKDTREF_COUNTER_MSB_MASK 0x8000 13090 #define PLL_CAL_PLL_CALSTS_1_LKDTREF_COUNTER_MSB_ALIGN 0 13091 #define PLL_CAL_PLL_CALSTS_1_LKDTREF_COUNTER_MSB_BITS 1 13092 #define PLL_CAL_PLL_CALSTS_1_LKDTREF_COUNTER_MSB_SHIFT 15 13093 13094 /* PLL_CAL :: PLL_CALSTS_1 :: lkdtvco_counter_msb [14:14] */ 13095 #define PLL_CAL_PLL_CALSTS_1_LKDTVCO_COUNTER_MSB_MASK 0x4000 13096 #define PLL_CAL_PLL_CALSTS_1_LKDTVCO_COUNTER_MSB_ALIGN 0 13097 #define PLL_CAL_PLL_CALSTS_1_LKDTVCO_COUNTER_MSB_BITS 1 13098 #define PLL_CAL_PLL_CALSTS_1_LKDTVCO_COUNTER_MSB_SHIFT 14 13099 13100 /* PLL_CAL :: PLL_CALSTS_1 :: reserved0 [13:13] */ 13101 #define PLL_CAL_PLL_CALSTS_1_RESERVED0_MASK 0x2000 13102 #define PLL_CAL_PLL_CALSTS_1_RESERVED0_ALIGN 0 13103 #define PLL_CAL_PLL_CALSTS_1_RESERVED0_BITS 1 13104 #define PLL_CAL_PLL_CALSTS_1_RESERVED0_SHIFT 13 13105 13106 /* PLL_CAL :: PLL_CALSTS_1 :: calref_counter [12:00] */ 13107 #define PLL_CAL_PLL_CALSTS_1_CALREF_COUNTER_MASK 0x1fff 13108 #define PLL_CAL_PLL_CALSTS_1_CALREF_COUNTER_ALIGN 0 13109 #define PLL_CAL_PLL_CALSTS_1_CALREF_COUNTER_BITS 13 13110 #define PLL_CAL_PLL_CALSTS_1_CALREF_COUNTER_SHIFT 0 13111 13112 13113 /**************************************************************************** 13114 * PLL_CAL :: PLL_CALSTS_2 13115 */ 13116 /* PLL_CAL :: PLL_CALSTS_2 :: band_iqbuf_mux [15:13] */ 13117 #define PLL_CAL_PLL_CALSTS_2_BAND_IQBUF_MUX_MASK 0xe000 13118 #define PLL_CAL_PLL_CALSTS_2_BAND_IQBUF_MUX_ALIGN 0 13119 #define PLL_CAL_PLL_CALSTS_2_BAND_IQBUF_MUX_BITS 3 13120 #define PLL_CAL_PLL_CALSTS_2_BAND_IQBUF_MUX_SHIFT 13 13121 13122 /* PLL_CAL :: PLL_CALSTS_2 :: calvco_counter [12:00] */ 13123 #define PLL_CAL_PLL_CALSTS_2_CALVCO_COUNTER_MASK 0x1fff 13124 #define PLL_CAL_PLL_CALSTS_2_CALVCO_COUNTER_ALIGN 0 13125 #define PLL_CAL_PLL_CALSTS_2_CALVCO_COUNTER_BITS 13 13126 #define PLL_CAL_PLL_CALSTS_2_CALVCO_COUNTER_SHIFT 0 13127 13128 13129 /**************************************************************************** 13130 * PLL_CAL :: PLL_CALSTS_3 13131 */ 13132 /* PLL_CAL :: PLL_CALSTS_3 :: lkdtref_counter [15:00] */ 13133 #define PLL_CAL_PLL_CALSTS_3_LKDTREF_COUNTER_MASK 0xffff 13134 #define PLL_CAL_PLL_CALSTS_3_LKDTREF_COUNTER_ALIGN 0 13135 #define PLL_CAL_PLL_CALSTS_3_LKDTREF_COUNTER_BITS 16 13136 #define PLL_CAL_PLL_CALSTS_3_LKDTREF_COUNTER_SHIFT 0 13137 13138 13139 /**************************************************************************** 13140 * PLL_CAL :: PLL_CALSTS_4 13141 */ 13142 /* PLL_CAL :: PLL_CALSTS_4 :: lkdtvco_counter [15:00] */ 13143 #define PLL_CAL_PLL_CALSTS_4_LKDTVCO_COUNTER_MASK 0xffff 13144 #define PLL_CAL_PLL_CALSTS_4_LKDTVCO_COUNTER_ALIGN 0 13145 #define PLL_CAL_PLL_CALSTS_4_LKDTVCO_COUNTER_BITS 16 13146 #define PLL_CAL_PLL_CALSTS_4_LKDTVCO_COUNTER_SHIFT 0 13147 13148 13149 /**************************************************************************** 13150 * PLL_CAL :: PLL_CALSTS_5 13151 */ 13152 /* PLL_CAL :: PLL_CALSTS_5 :: reserved0 [15:14] */ 13153 #define PLL_CAL_PLL_CALSTS_5_RESERVED0_MASK 0xc000 13154 #define PLL_CAL_PLL_CALSTS_5_RESERVED0_ALIGN 0 13155 #define PLL_CAL_PLL_CALSTS_5_RESERVED0_BITS 2 13156 #define PLL_CAL_PLL_CALSTS_5_RESERVED0_SHIFT 14 13157 13158 /* PLL_CAL :: PLL_CALSTS_5 :: vcobufpon_mux [13:10] */ 13159 #define PLL_CAL_PLL_CALSTS_5_VCOBUFPON_MUX_MASK 0x3c00 13160 #define PLL_CAL_PLL_CALSTS_5_VCOBUFPON_MUX_ALIGN 0 13161 #define PLL_CAL_PLL_CALSTS_5_VCOBUFPON_MUX_BITS 4 13162 #define PLL_CAL_PLL_CALSTS_5_VCOBUFPON_MUX_SHIFT 10 13163 13164 /* PLL_CAL :: PLL_CALSTS_5 :: calstate_onehot [09:00] */ 13165 #define PLL_CAL_PLL_CALSTS_5_CALSTATE_ONEHOT_MASK 0x03ff 13166 #define PLL_CAL_PLL_CALSTS_5_CALSTATE_ONEHOT_ALIGN 0 13167 #define PLL_CAL_PLL_CALSTS_5_CALSTATE_ONEHOT_BITS 10 13168 #define PLL_CAL_PLL_CALSTS_5_CALSTATE_ONEHOT_SHIFT 0 13169 13170 13171 /**************************************************************************** 13172 * PLL_CAL :: PLL_CALSTS_6 13173 */ 13174 /* PLL_CAL :: PLL_CALSTS_6 :: pll_pwrdn_or [15:15] */ 13175 #define PLL_CAL_PLL_CALSTS_6_PLL_PWRDN_OR_MASK 0x8000 13176 #define PLL_CAL_PLL_CALSTS_6_PLL_PWRDN_OR_ALIGN 0 13177 #define PLL_CAL_PLL_CALSTS_6_PLL_PWRDN_OR_BITS 1 13178 #define PLL_CAL_PLL_CALSTS_6_PLL_PWRDN_OR_SHIFT 15 13179 13180 /* PLL_CAL :: PLL_CALSTS_6 :: vco_range_mux [14:08] */ 13181 #define PLL_CAL_PLL_CALSTS_6_VCO_RANGE_MUX_MASK 0x7f00 13182 #define PLL_CAL_PLL_CALSTS_6_VCO_RANGE_MUX_ALIGN 0 13183 #define PLL_CAL_PLL_CALSTS_6_VCO_RANGE_MUX_BITS 7 13184 #define PLL_CAL_PLL_CALSTS_6_VCO_RANGE_MUX_SHIFT 8 13185 13186 /* PLL_CAL :: PLL_CALSTS_6 :: vcopon_mux [07:04] */ 13187 #define PLL_CAL_PLL_CALSTS_6_VCOPON_MUX_MASK 0x00f0 13188 #define PLL_CAL_PLL_CALSTS_6_VCOPON_MUX_ALIGN 0 13189 #define PLL_CAL_PLL_CALSTS_6_VCOPON_MUX_BITS 4 13190 #define PLL_CAL_PLL_CALSTS_6_VCOPON_MUX_SHIFT 4 13191 13192 /* PLL_CAL :: PLL_CALSTS_6 :: pllpon_mux [03:00] */ 13193 #define PLL_CAL_PLL_CALSTS_6_PLLPON_MUX_MASK 0x000f 13194 #define PLL_CAL_PLL_CALSTS_6_PLLPON_MUX_ALIGN 0 13195 #define PLL_CAL_PLL_CALSTS_6_PLLPON_MUX_BITS 4 13196 #define PLL_CAL_PLL_CALSTS_6_PLLPON_MUX_SHIFT 0 13197 13198 13199 /**************************************************************************** 13200 * merlin_gallardo_txcom_blk_TXCOM 13201 */ 13202 /**************************************************************************** 13203 * TXCOM :: CL72_tap_limit_control1 13204 */ 13205 /* TXCOM :: CL72_tap_limit_control1 :: reserved0 [15:10] */ 13206 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_RESERVED0_MASK 0xfc00 13207 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_RESERVED0_ALIGN 0 13208 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_RESERVED0_BITS 6 13209 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_RESERVED0_SHIFT 10 13210 13211 /* TXCOM :: CL72_tap_limit_control1 :: post_tap_limit [09:05] */ 13212 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_POST_TAP_LIMIT_MASK 0x03e0 13213 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_POST_TAP_LIMIT_ALIGN 0 13214 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_POST_TAP_LIMIT_BITS 5 13215 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_POST_TAP_LIMIT_SHIFT 5 13216 13217 /* TXCOM :: CL72_tap_limit_control1 :: reserved1 [04:04] */ 13218 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_RESERVED1_MASK 0x0010 13219 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_RESERVED1_ALIGN 0 13220 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_RESERVED1_BITS 1 13221 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_RESERVED1_SHIFT 4 13222 13223 /* TXCOM :: CL72_tap_limit_control1 :: pre_tap_limit [03:00] */ 13224 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_PRE_TAP_LIMIT_MASK 0x000f 13225 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_PRE_TAP_LIMIT_ALIGN 0 13226 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_PRE_TAP_LIMIT_BITS 4 13227 #define TXCOM_CL72_TAP_LIMIT_CONTROL1_PRE_TAP_LIMIT_SHIFT 0 13228 13229 13230 /**************************************************************************** 13231 * TXCOM :: CL72_tap_limit_control2 13232 */ 13233 /* TXCOM :: CL72_tap_limit_control2 :: reserved0 [15:06] */ 13234 #define TXCOM_CL72_TAP_LIMIT_CONTROL2_RESERVED0_MASK 0xffc0 13235 #define TXCOM_CL72_TAP_LIMIT_CONTROL2_RESERVED0_ALIGN 0 13236 #define TXCOM_CL72_TAP_LIMIT_CONTROL2_RESERVED0_BITS 10 13237 #define TXCOM_CL72_TAP_LIMIT_CONTROL2_RESERVED0_SHIFT 6 13238 13239 /* TXCOM :: CL72_tap_limit_control2 :: main_tap_limit [05:00] */ 13240 #define TXCOM_CL72_TAP_LIMIT_CONTROL2_MAIN_TAP_LIMIT_MASK 0x003f 13241 #define TXCOM_CL72_TAP_LIMIT_CONTROL2_MAIN_TAP_LIMIT_ALIGN 0 13242 #define TXCOM_CL72_TAP_LIMIT_CONTROL2_MAIN_TAP_LIMIT_BITS 6 13243 #define TXCOM_CL72_TAP_LIMIT_CONTROL2_MAIN_TAP_LIMIT_SHIFT 0 13244 13245 13246 /**************************************************************************** 13247 * TXCOM :: CL72_tap_preset_control 13248 */ 13249 /* TXCOM :: CL72_tap_preset_control :: reserved0 [15:10] */ 13250 #define TXCOM_CL72_TAP_PRESET_CONTROL_RESERVED0_MASK 0xfc00 13251 #define TXCOM_CL72_TAP_PRESET_CONTROL_RESERVED0_ALIGN 0 13252 #define TXCOM_CL72_TAP_PRESET_CONTROL_RESERVED0_BITS 6 13253 #define TXCOM_CL72_TAP_PRESET_CONTROL_RESERVED0_SHIFT 10 13254 13255 /* TXCOM :: CL72_tap_preset_control :: pre_tap_preset_val [09:06] */ 13256 #define TXCOM_CL72_TAP_PRESET_CONTROL_PRE_TAP_PRESET_VAL_MASK 0x03c0 13257 #define TXCOM_CL72_TAP_PRESET_CONTROL_PRE_TAP_PRESET_VAL_ALIGN 0 13258 #define TXCOM_CL72_TAP_PRESET_CONTROL_PRE_TAP_PRESET_VAL_BITS 4 13259 #define TXCOM_CL72_TAP_PRESET_CONTROL_PRE_TAP_PRESET_VAL_SHIFT 6 13260 13261 /* TXCOM :: CL72_tap_preset_control :: reserved1 [05:05] */ 13262 #define TXCOM_CL72_TAP_PRESET_CONTROL_RESERVED1_MASK 0x0020 13263 #define TXCOM_CL72_TAP_PRESET_CONTROL_RESERVED1_ALIGN 0 13264 #define TXCOM_CL72_TAP_PRESET_CONTROL_RESERVED1_BITS 1 13265 #define TXCOM_CL72_TAP_PRESET_CONTROL_RESERVED1_SHIFT 5 13266 13267 /* TXCOM :: CL72_tap_preset_control :: post_tap_preset_val [04:00] */ 13268 #define TXCOM_CL72_TAP_PRESET_CONTROL_POST_TAP_PRESET_VAL_MASK 0x001f 13269 #define TXCOM_CL72_TAP_PRESET_CONTROL_POST_TAP_PRESET_VAL_ALIGN 0 13270 #define TXCOM_CL72_TAP_PRESET_CONTROL_POST_TAP_PRESET_VAL_BITS 5 13271 #define TXCOM_CL72_TAP_PRESET_CONTROL_POST_TAP_PRESET_VAL_SHIFT 0 13272 13273 13274 /**************************************************************************** 13275 * TXCOM :: CL72_debug_1_register 13276 */ 13277 /* TXCOM :: CL72_debug_1_register :: reserved0 [15:14] */ 13278 #define TXCOM_CL72_DEBUG_1_REGISTER_RESERVED0_MASK 0xc000 13279 #define TXCOM_CL72_DEBUG_1_REGISTER_RESERVED0_ALIGN 0 13280 #define TXCOM_CL72_DEBUG_1_REGISTER_RESERVED0_BITS 2 13281 #define TXCOM_CL72_DEBUG_1_REGISTER_RESERVED0_SHIFT 14 13282 13283 /* TXCOM :: CL72_debug_1_register :: tap_sum_max_val [13:07] */ 13284 #define TXCOM_CL72_DEBUG_1_REGISTER_TAP_SUM_MAX_VAL_MASK 0x3f80 13285 #define TXCOM_CL72_DEBUG_1_REGISTER_TAP_SUM_MAX_VAL_ALIGN 0 13286 #define TXCOM_CL72_DEBUG_1_REGISTER_TAP_SUM_MAX_VAL_BITS 7 13287 #define TXCOM_CL72_DEBUG_1_REGISTER_TAP_SUM_MAX_VAL_SHIFT 7 13288 13289 /* TXCOM :: CL72_debug_1_register :: reserved1 [06:06] */ 13290 #define TXCOM_CL72_DEBUG_1_REGISTER_RESERVED1_MASK 0x0040 13291 #define TXCOM_CL72_DEBUG_1_REGISTER_RESERVED1_ALIGN 0 13292 #define TXCOM_CL72_DEBUG_1_REGISTER_RESERVED1_BITS 1 13293 #define TXCOM_CL72_DEBUG_1_REGISTER_RESERVED1_SHIFT 6 13294 13295 /* TXCOM :: CL72_debug_1_register :: main_tap_min_val [05:00] */ 13296 #define TXCOM_CL72_DEBUG_1_REGISTER_MAIN_TAP_MIN_VAL_MASK 0x003f 13297 #define TXCOM_CL72_DEBUG_1_REGISTER_MAIN_TAP_MIN_VAL_ALIGN 0 13298 #define TXCOM_CL72_DEBUG_1_REGISTER_MAIN_TAP_MIN_VAL_BITS 6 13299 #define TXCOM_CL72_DEBUG_1_REGISTER_MAIN_TAP_MIN_VAL_SHIFT 0 13300 13301 13302 /**************************************************************************** 13303 * TXCOM :: CL72_max_wait_timer_register 13304 */ 13305 /* TXCOM :: CL72_max_wait_timer_register :: max_wait_timer_period [15:00] */ 13306 #define TXCOM_CL72_MAX_WAIT_TIMER_REGISTER_MAX_WAIT_TIMER_PERIOD_MASK 0xffff 13307 #define TXCOM_CL72_MAX_WAIT_TIMER_REGISTER_MAX_WAIT_TIMER_PERIOD_ALIGN 0 13308 #define TXCOM_CL72_MAX_WAIT_TIMER_REGISTER_MAX_WAIT_TIMER_PERIOD_BITS 16 13309 #define TXCOM_CL72_MAX_WAIT_TIMER_REGISTER_MAX_WAIT_TIMER_PERIOD_SHIFT 0 13310 13311 13312 /**************************************************************************** 13313 * TXCOM :: CL72_wait_timer_register 13314 */ 13315 /* TXCOM :: CL72_wait_timer_register :: reserved0 [15:09] */ 13316 #define TXCOM_CL72_WAIT_TIMER_REGISTER_RESERVED0_MASK 0xfe00 13317 #define TXCOM_CL72_WAIT_TIMER_REGISTER_RESERVED0_ALIGN 0 13318 #define TXCOM_CL72_WAIT_TIMER_REGISTER_RESERVED0_BITS 7 13319 #define TXCOM_CL72_WAIT_TIMER_REGISTER_RESERVED0_SHIFT 9 13320 13321 /* TXCOM :: CL72_wait_timer_register :: wait_cntr_limit [08:00] */ 13322 #define TXCOM_CL72_WAIT_TIMER_REGISTER_WAIT_CNTR_LIMIT_MASK 0x01ff 13323 #define TXCOM_CL72_WAIT_TIMER_REGISTER_WAIT_CNTR_LIMIT_ALIGN 0 13324 #define TXCOM_CL72_WAIT_TIMER_REGISTER_WAIT_CNTR_LIMIT_BITS 9 13325 #define TXCOM_CL72_WAIT_TIMER_REGISTER_WAIT_CNTR_LIMIT_SHIFT 0 13326 13327 13328 /**************************************************************************** 13329 * Datatype Definitions. 13330 */ 13331 #endif /* #ifndef PHY82328_H__ */ 13332 13333 /* End of File */ 13334