phy8072.h (15387B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8072.h 8 */ 9 10 #ifndef _PHY8072_H_ 11 #define _PHY8072_H_ 12 13 #include <soc/phy.h> 14 15 #define MII_CTRL_PMA_LOOPBACK (1 << 0) 16 17 #define PHY8072_C45_DEV_PMA_PMD 0x01 18 #define PHY8072_C45_DEV_PCS 0x03 19 #define PHY8072_C45_DEV_PHYXS 0x04 20 #define PHY8072_C45_DEV_DTEXS 0x05 21 #define PHY8072_C45_DEV_AN 0x07 22 23 #define PHY8072_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 24 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 25 #define PHY8072_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 26 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 27 #define PHY8072_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 28 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 29 30 /* PMA/PMD Device (Dev Addr 1) */ 31 32 #define READ_PHY8072_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 33 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 34 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, (_reg)), (_val)) 35 #define WRITE_PHY8072_PMA_PMD_REG(_unit, _phy_ctrl, _reg,_val) \ 36 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 37 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, (_reg)), (_val)) 38 #define MODIFY_PHY8072_PMA_PMD_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 39 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 40 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, (_reg)), (_val), (_mask)) 41 42 /* Control Register (Addr 0000h) */ 43 #define READ_PHY8072_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 44 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 45 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0), (_val)) 46 #define WRITE_PHY8072_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val) \ 47 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 48 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0), (_val)) 49 #define MODIFY_PHY8072_PMA_PMD_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 50 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 51 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0), (_val), (_mask)) 52 53 /* Status Register (Addr 0001h) */ 54 #define READ_PHY8072_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 55 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 56 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 1), (_val)) 57 #define WRITE_PHY8072_PMA_PMD_STATr(_unit, _phy_ctrl, _val) \ 58 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 59 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 1), (_val)) 60 #define MODIFY_PHY8072_PMA_PMD_STATr(_unit, _phy_ctrl, _val, _mask) \ 61 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 62 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 1), (_val), (_mask)) 63 64 /* ID0 Register (Addr 0002h) */ 65 #define PMAD_ID0_REG 0x2 66 67 /* ID1 Register (Addr 0003h) */ 68 #define PMAD_ID1_REG 0x3 69 70 /* Speed Ability Register (Addr 0004h) */ 71 /* Devices in Package 1 Register (Addr 0005h) */ 72 /* Devices in Package 2 Register (Addr 0006h) */ 73 74 /* Control 2 Register (Addr 0007h) */ 75 #define PMAD_CTRL2_REG 0x7 76 77 #define PMAD_CTRL2r_PMA_TYPE_MASK 0xF 78 #define PMAD_CTRL2r_PMA_TYPE_1G 0xD 79 #define PMAD_CTRL2r_PMA_TYPE_10G 0xB 80 81 /* Status 2 Register (Addr 0008h) */ 82 83 /* Transmit Disable Register (Addr 0009h) */ 84 #define READ_PHY8072_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 85 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 86 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 9), (_val)) 87 #define WRITE_PHY8072_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val) \ 88 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 89 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 9), (_val)) 90 #define MODIFY_PHY8072_PMA_PMD_TX_DISABLEr(_unit, _phy_ctrl, _val, _mask) \ 91 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 92 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 9), (_val), (_mask)) 93 94 /* Receive Signal Detect Register (Addr 000Ah) */ 95 /* Organizationlly Unique Identifier 0 Register (Addr 000Eh) */ 96 /* Organizationlly Unique Identifier 1 Register (Addr 000Fh) */ 97 98 /* PMA/PMD device specific registers */ 99 100 /* User Status Register. This register collects all speeds, link and 101 * auto-neg status from 4 IEEE status registers 102 */ 103 #define PMAD_USR_STATUS_REG 0xC820 104 105 /* autoneg 10G link up */ 106 #define PMAD_STATUS_AN_10G(_s) (((_s) & 0xEC44) == 0x6C44) 107 #define PMAD_STATUS_AN_2p5G(_s) (((_s) & 0x8C22) == 0x8C22) 108 #define PMAD_STATUS_MODE_2p5G (1<<5) 109 #define PMAD_STATUS_1G_LINKDOWN (1<<13) 110 #define PMAD_STATUS_2p5G_LINKDOWN (1<<14) 111 #define PMAD_STATUS_10G_LINKDOWN (1<<15) 112 113 /* Chip revision register */ 114 #define PMAD_CHIP_REV_REG 0xC801 115 116 /* General control status register */ 117 #define PMAD_GEN_CTRL_STAT_REG 0xCA10 118 119 /* General Purpose Register 2 */ 120 #define PMAD_GEN2_REG 0xCA1A 121 122 123 /* PCS Device (Dev Addr 3) */ 124 /* Control 1 Register (Addr 0000h) */ 125 #define READ_PHY8072_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 126 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 127 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PCS, 0), (_val)) 128 #define WRITE_PHY8072_PCS_CTRLr(_unit, _phy_ctrl, _val) \ 129 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 130 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PCS, 0), (_val)) 131 #define MODIFY_PHY8072_PCS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 132 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 133 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PCS, 0), (_val), (_mask)) 134 135 /* Status 1 Register (Addr 0001h) */ 136 #define READ_PHY8072_PCS_STATr(_unit, _phy_ctrl, _val) \ 137 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 138 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PCS, 1), (_val)) 139 #define WRITE_PHY8072_PCS_STATr(_unit, _phy_ctrl, _val) \ 140 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 141 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PCS, 1), (_val)) 142 #define MODIFY_PHY8072_PCS_STATr(_unit, _phy_ctrl, _val, _mask) \ 143 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 144 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PCS, 1), (_val), (_mask)) 145 146 /* PCS Identifier 0 Register (Addr 0002h) */ 147 148 /* PCS Identifier 1 Register (Addr 0003h) */ 149 150 /* Speed Ability (Addr 0004h) */ 151 152 /* Devices in Package 1 (Addr 0005h) */ 153 154 /* Devices in Package 2 (Addr 0006h) */ 155 156 /* PCS Control 2 Register (Addr 0007h) */ 157 158 /* PCS Status 2 Register (Addr 0008h) */ 159 160 /* Organizationally Unique Identifier 0 Register (Addr 000eh) */ 161 /* Organizationally Unique Identifier 1 Register (Addr 000fh) */ 162 /* 10GBASE-X PCS Status Register (Addr 0x0018h) */ 163 /* 10GBASE-R PCS Status Register (Addr 0x0020h) */ 164 /* 10GBASE-R PCS Status 2 Register (Addr 0x0021h) */ 165 /* 10GBASE-R PCS Jitter Test Seed A0 Register (Addr 0x0022h) */ 166 /* 10GBASE-R PCS Jitter Test Seed A1 Register (Addr 0x0023h) */ 167 /* 10GBASE-R PCS Jitter Test Seed A2 Register (Addr 0x0024h) */ 168 /* 10GBASE-R PCS Jitter Test Seed A3 Register (Addr 0x0025h) */ 169 /* 10GBASE-R PCS Jitter Test Seed B0 Register (Addr 0x0026h) */ 170 /* 10GBASE-R PCS Jitter Test Seed B1 Register (Addr 0x0027h) */ 171 /* 10GBASE-R PCS Jitter Test Seed B2 Register (Addr 0x0028h) */ 172 /* 10GBASE-R PCS Jitter Test Seed B3 Register (Addr 0x0029h) */ 173 /* 10GBASE-R PCS Jitter Test Control Register (Addr 0x002ah) */ 174 /* 10GBASE-R PCS Jitter Test Error Counter Register (Addr 0x002Bh) */ 175 /* PRBS23 WIN_2 Register (Addr = 0xc92dh) */ 176 177 /****************************/ 178 /* XGXS Device (Dev Addr 4) */ 179 /****************************/ 180 #define READ_PHY8072_PHYXS_REG(_unit, _phy_ctrl, _reg,_val) \ 181 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 182 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, (_reg)), (_val)) 183 #define WRITE_PHY8072_PHYXS_REG(_unit, _phy_ctrl, _reg,_val) \ 184 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 185 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, (_reg)), (_val)) 186 #define MODIFY_PHY8072_PHYXS_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 187 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 188 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, (_reg)), (_val), (_mask)) 189 190 /* Control 1 Register (Addr 0000h) */ 191 #define READ_PHY8072_PHYXS_CTRLr(_unit, _phy_ctrl, _val) \ 192 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 193 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0), (_val)) 194 #define WRITE_PHY8072_PHYXS_CTRLr(_unit, _phy_ctrl, _val) \ 195 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 196 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0), (_val)) 197 #define MODIFY_PHY8072_PHYXS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 198 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 199 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0), (_val), (_mask)) 200 201 /* Status 1 Register (Addr 0001h) */ 202 #define READ_PHY8072_PHYXS_STATr(_unit, _phy_ctrl, _val) \ 203 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 204 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 1), (_val)) 205 #define WRITE_PHY8072_PHYXS_STATr(_unit, _phy_ctrl, _val) \ 206 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 207 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 1), (_val)) 208 #define MODIFY_PHY8072_PHYXS_STATr(_unit, _phy_ctrl, _val, _mask) \ 209 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 210 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 1), (_val), (_mask)) 211 212 /* PHY Identifier Register 0 (Addr 0002h) */ 213 /* PHY Identifier Register 1 (Addr 0003h) */ 214 /* Speed Ability (Addr 0004h) */ 215 /* Device in Package 2 (Addr 0005h) */ 216 /* Device in Package 1 (Addr 0006h) */ 217 /* Status 2 Register (Addr 0008h) */ 218 /* Organizatioally Unique Identifier 0 Register (Addr 000eh) */ 219 /* Organizationally Unique Identifier 1 Register (Addr 000fh) */ 220 221 /* XGXS Lane Status Register (Addr 0018h) */ 222 #define READ_PHY8072_PHYXS_XGXS_LANE_STATr(_unit, _phy_ctrl, _val) \ 223 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 224 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0x18), (_val)) 225 #define WRITE_PHY8072_PHYXS_XGXS_LANE_STATr(_unit, _phy_ctrl, _val) \ 226 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 227 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0x18), (_val)) 228 #define MODIFY_PHY8072_PHYXS_XGXS_LANE_STATr(_unit, _phy_ctrl, _val, _mask) \ 229 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 230 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0x18), \ 231 (_val), (_mask)) 232 233 /* XGXS Test Control Register (Addr 0019h) */ 234 235 /* XGXS mode control register */ 236 237 /* XGXS control register */ 238 239 #define XGXS_MODE_CTRLr 0x8000 240 #define XGXS_MODE_SHIFTER 8 241 #define XGXS_MODE_NORMAL (0x1 << XGXS_MODE_SHIFTER) 242 #define XGXS_MODE_SYSTEM_LOOPBACK (0x0 << XGXS_MODE_SHIFTER) 243 #define XGXS_MODE_MASK (0xf << XGXS_MODE_SHIFTER) 244 #define XGXS_CTRL_RLOOP (1 << 6) 245 246 /************************************************/ 247 /* User Defined Registers (Devices 1, 2, and 3) */ 248 /************************************************/ 249 250 #define READ_PHY8072_IDENTIFIERr(_unit, _phy_ctrl, _val) \ 251 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 252 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xc800), (_val)) 253 #define WRITE_PHY8072_IDENTIFIERr(_unit, _phy_ctrl, _val) \ 254 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 255 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xc800), (_val)) 256 #define MODIFY_PHY8072_IDENTIFIERr(_unit, _phy_ctrl, _val, _mask) \ 257 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 258 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xc800), \ 259 (_val), (_mask)) 260 261 #define READ_PHY8072_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 262 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 263 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xca0a), (_val)) 264 #define WRITE_PHY8072_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 265 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 266 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xca0a), (_val)) 267 #define MODIFY_PHY8072_PMD_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 268 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 269 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xca0a), \ 270 (_val), (_mask)) 271 272 #define READ_PHY8072_TXA_ACTRL_3r(_unit, _phy_ctrl, _val) \ 273 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 274 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0x80a7), (_val)) 275 #define WRITE_PHY8072_TXA_ACTRL_3r(_unit, _phy_ctrl, _val) \ 276 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 277 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0x80a7), (_val)) 278 #define MODIFY_PHY8072_TXA_ACTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 279 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 280 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PHYXS, 0x80a7), \ 281 (_val), (_mask)) 282 283 /* General Purpose Register 1 */ 284 #define READ_PHY8072_GENREG1r(_unit, _phy_ctrl, _val) \ 285 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 286 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xca19), (_val)) 287 #define WRITE_PHY8072_GENREG1r(_unit, _phy_ctrl, _val) \ 288 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 289 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xca19), (_val)) 290 #define MODIFY_PHY8072_GENREG1r(_unit, _phy_ctrl, _val, _mask) \ 291 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 292 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_PMA_PMD, 0xca19), \ 293 (_val), (_mask)) 294 #define PMDA_ROM_LOAD_8072ID 0xbcb0 295 #define PMDA_ROM_LOAD_8073ID 0xbaa0 296 297 /* Auto-Neotiation device */ 298 299 #define READ_PHY8072_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 300 PHY8072_REG_READ((_unit), (_phy_ctrl), \ 301 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_AN, (_reg)), (_val)) 302 #define WRITE_PHY8072_AN_REG(_unit, _phy_ctrl, _reg,_val) \ 303 PHY8072_REG_WRITE((_unit), (_phy_ctrl), \ 304 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_AN, (_reg)), (_val)) 305 #define MODIFY_PHY8072_AN_REG(_unit, _phy_ctrl, _reg, _val, _mask) \ 306 PHY8072_REG_MODIFY((_unit), (_phy_ctrl), \ 307 SOC_PHY_CLAUSE45_ADDR(PHY8072_C45_DEV_AN, (_reg)), (_val), (_mask)) 308 309 /* autoneg control register */ 310 311 #define AN_CTRL_REG 0 312 #define AN_EXT_NXT_PAGE (1 << 13) 313 #define AN_ENABLE (1 << 12) 314 #define AN_RESTART (1 << 9) 315 316 /* autoneg status register */ 317 318 #define AN_STATUS_REG 1 319 #define AN_LP_AN_ABILITY (1 << 0) 320 #define AN_LINK (1 << 2) 321 #define AN_DONE (1 << 5) 322 323 /* autoneg advertisement register 0 */ 324 325 #define AN_ADVERT_0_REG 0x10 326 #define AN_ADVERT_PAUSE (1 << 10) 327 #define AN_ADVERT_PAUSE_ASYM (1 << 11) 328 329 /* autoneg advertisement register 1 */ 330 331 #define AN_ADVERT_1_REG 0x11 332 #define AN_ADVERT_10G (1 << 7) 333 #define AN_ADVERT_1G (1 << 5) 334 335 /* autoneg advertisement register 2 */ 336 337 #define AN_ADVERT_2_REG 0x12 338 #define AN_ADVERT_FEC (1 << 15) 339 340 /* Link Partner base ability page 0 */ 341 342 #define AN_LP_ABILITY_0_REG 0x13 343 344 /* Link Partner base ability page 1 */ 345 346 #define AN_LP_ABILITY_1_REG 0x14 347 348 /* Link Partner base ability page 2 */ 349 350 #define AN_LP_ABILITY_2_REG 0x15 351 352 /* BP ethernet status register */ 353 354 #define AN_ETH_STATUS_REG 0x30 355 #define AN_SPEED_1000BASE_KX (1 << 1) 356 #define AN_SPEED_10GBASE_KR (1 << 3) 357 358 /* misc. registers */ 359 #define AN_MISC1_REG 0x8308 360 #define AN_MISC2_REG 0x8309 361 #define PMD_FORCED_SP_MASK (1 << 5) 362 #define FORCED_SP_SEL_MASK (1 << 4) 363 364 #endif /* _PHY8072_H_ */