phy8040.h (3876B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy8040.h 8 */ 9 10 #ifndef _phy8040_H_ 11 #define _phy8040_H_ 12 13 #include <soc/phy.h> 14 15 /* 16 * By default assume ports 0 <--> 1 are connected. 17 */ 18 #define PHY8040_DFLT_SWITCH_PORT 1 19 #define PHY8040_DFLT_MUX_PORT0 0 20 #define PHY8040_DFLT_MUX_PORT1 3 21 22 /* 23 * Pick the same phy address as top level but different dev address 24 * for XGXS blocks. 25 */ 26 #define PHY8040_C45_DEV_TOPLVL 0x1 27 #define PHY8040_C45_DEV_XGXS0 0x3 28 #define PHY8040_C45_DEV_XGXS1 0x4 29 #define PHY8040_C45_DEV_XGXS2 0x6 30 #define PHY8040_C45_DEV_XGXS3 0x7 31 32 #define PHY8040_REG_READ(_unit, _phy_ctrl, _addr, _val) \ 33 READ_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 34 #define PHY8040_REG_WRITE(_unit, _phy_ctrl, _addr, _val) \ 35 WRITE_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val)) 36 #define PHY8040_REG_MODIFY(_unit, _phy_ctrl, _addr, _val, _mask) \ 37 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_addr), (_val), (_mask)) 38 39 /* Power down XGXS blocks (Dev Addr 1) */ 40 #define PHY8040_PWRCTRL_RSVD 0x7830 /* only last nibble is writeable */ 41 #define READ_PHY8040_PWR_CTLr(_unit, _phy_ctrl, _val) \ 42 PHY8040_REG_READ((_unit), (_phy_ctrl), \ 43 SOC_PHY_CLAUSE45_ADDR(PHY8040_C45_DEV_TOPLVL, 0x8001), (_val)) 44 #define WRITE_PHY8040_PWR_CTRLr(_unit, _phy_ctrl, _val) \ 45 PHY8040_REG_WRITE((_unit), (_phy_ctrl), \ 46 SOC_PHY_CLAUSE45_ADDR(PHY8040_C45_DEV_TOPLVL, 0x8001), (_val)) 47 48 /* XGXS {_xgxs=0,1,2,3} Control Register (Addr 0000h) */ 49 #define PHY8040_XGXS_CTRL_SRC(_mux) (((_mux) & 0xf)<<12) 50 #define PHY8040_XGXS_CTRL_MDMX (1<<11) 51 #define PHY8040_XGXS_CTRL_C45 (1<<10) 52 #define PHY8040_XGXS_CTRL_DEVID(_id) (((_id) & 0x1f)<<5) 53 #define PHY8040_XGXS_CTRL_PRTAD(_ad) ((_ad) & 0x1f) 54 55 #define READ_PHY8040_XGXSn_CTRLr(_unit, _phy_ctrl, _xgxs,_val) \ 56 PHY8040_REG_READ((_unit), (_phy_ctrl), \ 57 SOC_PHY_CLAUSE45_ADDR(PHY8040_C45_DEV_TOPLVL, (0x8010|(_xgxs)))) 58 #define WRITE_PHY8040_XGXSn_CTRLr(_unit, _phy_ctrl, _xgxs, _val) \ 59 PHY8040_REG_WRITE((_unit), (_phy_ctrl), \ 60 SOC_PHY_CLAUSE45_ADDR(PHY8040_C45_DEV_TOPLVL, (0x8010|(_xgxs))), (_val)) 61 #define MODIFY_PHY8040_XGXSn_CTRLr(_unit, _phy_ctrl, _xgxs, _val, _mask) \ 62 PHY8040_REG_MODIFY((_unit), (_phy_ctrl), \ 63 SOC_PHY_CLAUSE45_ADDR(PHY8040_C45_DEV_TOPLVL, (0x8010|(_xgxs))), (_val), (_mask)) 64 65 /* Generic XGXSn port/phy register reg access */ 66 #define PHY8040_PRE_EMPHASIS_REG 0x80A7 67 #define PHY8040_PRE_EMPHASIS(_P) (((_P) & 0xf) << 12) 68 #define PHY8040_DRIVER_STRENGTH(_C) (((_C) & 0xf) << 8) 69 70 #define PHY8040_LANE_STATUS_REG 0x0018 71 72 #define READ_PHY8040_XGXSn_REG(_unit, _phy_ctrl, _devid, _reg, _val) \ 73 PHY8040_REG_READ((_unit), (_phy_ctrl), \ 74 SOC_PHY_CLAUSE45_ADDR((_devid), (_reg)), (_val)) 75 #define WRITE_PHY8040_XGXSn_REG(_unit, _phy_ctrl, _devid, _reg, _val) \ 76 PHY8040_REG_WRITE((_unit), (_phy_ctrl), \ 77 SOC_PHY_CLAUSE45_ADDR((_devid), (_reg)), (_val)) 78 #define MODIFY_PHY8040_XGXSn_REG(_unit, _phy_ctrl, _devid, _reg, _val, _mask) \ 79 PHY8040_REG_MODIFY((_unit), (_phy_ctrl), \ 80 SOC_PHY_CLAUSE45_ADDR((_devid), (_reg)), (_val), (_mask)) 81 82 /* user registers */ 83 #define PHY8040_XGXS_CTRL_REG 0x8000 84 #define PHY8040_LANE_CTRL1_REG 0x8016 85 #define PHY8040_LANE_CTRL2_REG 0x8017 86 #define PHY8040_TX0A_CTRL1_REG 0x80A7 87 #define PHY8040_RX_CTRL_REG 0x80F1 88 #define PHY8040_RX_STATUS_REG 0x80b0 89 90 /* RX status register */ 91 #define PHY8040_1G_LINKUP_MASK ((1 << 15) | (1 << 12)) 92 93 #endif /* _phy8705_H_ */