phy56xxx5601x.h (24547B)
1 2 /* 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * File: phy56xxx5601x.h 9 * Purpose: BCM56xxx (FB/ER) Internal Dodeca Serdes PHY Driver 10 * with shadow registers 11 */ 12 13 #ifndef _PHY56XXX_5601X_H_ 14 #define _PHY56XXX_5601X_H_ 15 16 #include <soc/phy.h> 17 18 /* 19 * Definitions for Internal SerDes 10/100/1000 PHY 20 */ 21 22 /* MII Control Register */ 23 24 /* DDS: MII Control bit definitions, same as Standard 10/100 PHY */ 25 #define DDS_MII_CTRL_RESET MII_CTRL_RESET /* Self clearing SW reset */ 26 #define DDS_MII_CTRL_SS_LSB MII_CTRL_SS_LSB /* Speed Select, LSB */ 27 #define DDS_MII_CTRL_SS_MSB MII_CTRL_SS_MSB /* Speed Select, MSB */ 28 #define DDS_MII_CTRL_SS(_x) MII_CTRL_SS(_x) 29 #define DDS_MII_CTRL_SS_10 MII_CTRL_SS_10 30 #define DDS_MII_CTRL_SS_100 MII_CTRL_SS_100 31 #define DDS_MII_CTRL_SS_1000 MII_CTRL_SS_1000 32 #define DDS_MII_CTRL_SS_INVALID MII_CTRL_SS_INVALID 33 #define DDS_MII_CTRL_SS_MASK MII_CTRL_SS_MASK 34 #define DDS_MII_CTRL_FD MII_CTRL_FD /* Full Duplex */ 35 #define DDS_MII_CTRL_AN_RESTART (1 << 9) /* Auto Negotiation Enable */ 36 #define DDS_MII_CTRL_AN_ENABLE (1 << 12) /* Auto Negotiation Enable */ 37 #define DDS_MII_CTRL_PD MII_CTRL_PD /* Power Down Enable */ 38 #define DDS_MII_CTRL_LOOPBACK (1 << 14) /* Loopback Enable */ 39 40 /* MII Status Register */ 41 /* DDS: MII Status Register: not the same as standard 10/100 PHY */ 42 #define DDS_MII_STAT_RF MII_STAT_RF /* Remote fault */ 43 #define DDS_MII_STAT_LA MII_STAT_LA /* Link Up */ 44 #define DDS_MII_STAT_AN_COMPLETE (1 << 5) /* AN complete */ 45 46 /* Bit defines for ANA register */ 47 #define DDS_MII_ANA_HD (1 << 6) 48 #define DDS_MII_ANA_FD (1 << 5) 49 #define DDS_MII_ANA_PAUSE_NONE (0 << 7) 50 #define DDS_MII_ANA_PAUSE_SYM (1 << 7) 51 #define DDS_MII_ANA_PAUSE_ASYM (1 << 8) 52 #define DDS_MII_ANA_PAUSE_MASK (3 << 7) 53 54 /* Auto-Negotiation Link-Partner Ability Register */ 55 56 #define DDS_MII_ANP_FIBER_NEXT_PG (1 << 15) 57 #define DDS_MII_ANP_FIBER_ACK (1 << 14) 58 #define DDS_MII_ANP_FIBER_RF_SHFT (12) /* Remote fault */ 59 #define DDS_MII_ANP_FIBER_RF_MASK (0x3000) 60 #define DDS_MII_ANP_FIBER_PAUSE_ASYM (1 << 8) 61 #define DDS_MII_ANP_FIBER_PAUSE_SYM (1 << 7) 62 #define DDS_MII_ANP_FIBER_HD (1 << 6) 63 #define DDS_MII_ANP_FIBER_FD (1 << 5) 64 65 #define DDS_MII_ANP_SGMII (1 << 0) 66 #define DDS_MII_ANP_SGMII_DUPLEX (1 << 12) 67 #define DDS_MII_ANP_SGMII_SPEED (3 << 10) 68 #define DDS_MII_ANP_SGMII_SPEED_10 (0) 69 #define DDS_MII_ANP_SGMII_SPEED_100 (1 << 10) 70 #define DDS_MII_ANP_SGMII_SPEED_1000 (1 << 11) 71 72 /* Auto-Negotiation Expansion Register */ 73 #define DDS_ANA_EXPANSION_PR (1 << 1) /* Page received */ 74 75 76 /* If application want to use this header file for accessing PHY registers, 77 * simply redefine SERDES_5601X_REG macros to use BCM API as follows. 78 * 79 * #define SERDES_5601X_REG_READ(_unit, _port, _flags, _reg_bank, \ 80 * _reg_addr, _val) \ 81 * bcm_port_phy_get((_unit), (_port), 0, 82 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 83 * (_val)) 84 * 85 * #define SERDES_5601X_REG_WRITE(_unit, _port, _flags, _reg_bank, \ 86 * _reg_addr, _val) \ 87 * bcm_port_phy_set((_unit), (_port), 0, 88 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 89 * (_val)) 90 * 91 * #define SERDES_5601X_REG_MODIFY(_unit, _port, _flags, _reg_bank, \ 92 * _reg_addr, _val)\ 93 * do { \ 94 * return BCM_E_UNAVAIL; \ 95 * } while(0) 96 */ 97 98 /* SERDES register access */ 99 #define SERDES_5601X_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 100 _reg_addr, _val) \ 101 phy_serdes_5601x_reg_read((_unit), (_phy_ctrl), (_reg_bank), \ 102 (_reg_addr), (_val)) 103 #define SERDES_5601X_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 104 _reg_addr, _val) \ 105 phy_serdes_5601x_reg_write((_unit), (_phy_ctrl), (_reg_bank), \ 106 (_reg_addr), (_val)) 107 #define SERDES_5601X_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 108 _reg_addr, _val, _mask) \ 109 phy_serdes_5601x_reg_modify((_unit), (_phy_ctrl), (_reg_bank), \ 110 (_reg_addr), (_val), (_mask)) 111 112 /***************************/ 113 /* Standard IEEE Registers */ 114 /***************************/ 115 116 /* MII Control (Addr 00h) */ 117 #define READ_SERDES_5601X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 118 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 119 0x00, 0x0000, 0x00, (_val)) 120 #define WRITE_SERDES_5601X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 121 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 122 0x00, 0x0000, 0x00, (_val)) 123 #define MODIFY_SERDES_5601X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 124 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 125 (_val), (_mask)) 126 127 /* MII Status (Addr 01h) */ 128 #define READ_SERDES_5601X_MII_STATr(_unit, _phy_ctrl, _val) \ 129 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 130 0x00, 0x0000, 0x01, (_val)) 131 #define WRITE_SERDES_5601X_MII_STATr(_unit, _phy_ctrl, _val) \ 132 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 133 0x00, 0x0000, 0x01, (_val)) 134 #define MODIFY_SERDES_5601X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 135 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 136 (_val), (_mask)) 137 138 /* PHY ID 0 (Addr 02h) */ 139 #define READ_SERDES_5601X_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 140 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 141 0x00, 0x0000, 0x02, (_val)) 142 #define WRITE_SERDES_5601X_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 143 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 144 0x00, 0x0000, 0x02, (_val)) 145 #define MODIFY_SERDES_5601X_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 146 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 147 (_val), (_mask)) 148 149 /* PHY ID 1 (Addr 03h) */ 150 #define READ_SERDES_5601X_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 151 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 152 0x00, 0x0000, 0x03, (_val)) 153 #define WRITE_SERDES_5601X_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 154 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 155 0x00, 0x0000, 0x03, (_val)) 156 #define MODIFY_SERDES_5601X_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 157 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 158 (_val), (_mask)) 159 160 /* Autoneg Adv (Addr 04h) */ 161 #define READ_SERDES_5601X_MII_ANAr(_unit, _phy_ctrl, _val) \ 162 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 163 0x00, 0x0000, 0x04, (_val)) 164 #define WRITE_SERDES_5601X_MII_ANAr(_unit, _phy_ctrl, _val) \ 165 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 166 0x00, 0x0000, 0x04, (_val)) 167 #define MODIFY_SERDES_5601X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 168 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 169 (_val), (_mask)) 170 171 /* Autoneg Link Partner Ability (Addr 05h) */ 172 #define READ_SERDES_5601X_MII_ANPr(_unit, _phy_ctrl, _val) \ 173 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 174 0x00, 0x0000, 0x05, (_val)) 175 #define WRITE_SERDES_5601X_MII_ANPr(_unit, _phy_ctrl, _val) \ 176 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 177 0x00, 0x0000, 0x05, (_val)) 178 #define MODIFY_SERDES_5601X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 179 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 180 (_val), (_mask)) 181 182 /* Autoneg Expansion (Addr 06h) */ 183 #define READ_SERDES_5601X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 184 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 185 0x00, 0x0000, 0x06, (_val)) 186 #define WRITE_SERDES_5601X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 187 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 188 0x00, 0x0000, 0x06, (_val)) 189 #define MODIFY_SERDES_5601X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 190 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 191 (_val), (_mask)) 192 193 /* Extended Status (Addr 0fh) */ 194 195 /*************************/ 196 /* Digital Block (Blk 0) */ 197 /*************************/ 198 /* 1000X Control 1 (Addr 10h) */ 199 #define READ_SERDES_5601X_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 200 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 201 0x00, 0x0000, 0x10, (_val)) 202 #define WRITE_SERDES_5601X_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 203 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 204 0x00, 0x0000, 0x10, (_val)) 205 #define MODIFY_SERDES_5601X_1000X_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 206 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 207 (_val), (_mask)) 208 209 /* 1000X Control 2 (Addr 11h) */ 210 #define READ_SERDES_5601X_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 211 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 212 0x00, 0x0000, 0x11, (_val)) 213 #define WRITE_SERDES_5601X_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 214 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 215 0x00, 0x0000, 0x11, (_val)) 216 #define MODIFY_SERDES_5601X_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 217 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 218 (_val), (_mask)) 219 220 /* 1000X Control 3 (Addr 12h) */ 221 #define READ_SERDES_5601X_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 222 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 223 0x00, 0x0000, 0x12, (_val)) 224 #define WRITE_SERDES_5601X_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 225 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 226 0x00, 0x0000, 0x12, (_val)) 227 #define MODIFY_SERDES_5601X_1000X_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 228 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x12, \ 229 (_val), (_mask)) 230 231 /* 1000X Control 4 (Addr 13h) */ 232 #define READ_SERDES_5601X_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 233 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 234 0x00, 0x0000, 0x13, (_val)) 235 #define WRITE_SERDES_5601X_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 236 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 237 0x00, 0x0000, 0x13, (_val)) 238 #define MODIFY_SERDES_5601X_1000X_CTRL4r(_unit, _phy_ctrl, _val, _mask) \ 239 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x13, \ 240 (_val), (_mask)) 241 242 /* 1000X Status 1 (Addr 14h) */ 243 #define READ_SERDES_5601X_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 244 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 245 0x00, 0x0000, 0x14, (_val)) 246 #define WRITE_SERDES_5601X_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 247 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 248 0x00, 0x0000, 0x14, (_val)) 249 #define MODIFY_SERDES_5601X_1000X_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 250 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x14, \ 251 (_val), (_mask)) 252 253 /* 1000X Status 2 (Addr 15h) */ 254 #define READ_SERDES_5601X_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 255 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 256 0x00, 0x0000, 0x15, (_val)) 257 #define WRITE_SERDES_5601X_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 258 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 259 0x00, 0x0000, 0x15, (_val)) 260 #define MODIFY_SERDES_5601X_1000X_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 261 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x15, \ 262 (_val), (_mask)) 263 264 /* 1000X Status 3 (Addr 16h) */ 265 #define READ_SERDES_5601X_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 266 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 267 0x00, 0x0000, 0x16, (_val)) 268 #define WRITE_SERDES_5601X_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 269 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 270 0x00, 0x0000, 0x16, (_val)) 271 #define MODIFY_SERDES_5601X_1000X_STAT3r(_unit, _phy_ctrl, _val, _mask) \ 272 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x16, \ 273 (_val), (_mask)) 274 275 /* Ber Crc Err Rx Pkt cntr (Addr 17h) */ 276 #define READ_SERDES_5601X_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 277 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 278 0x00, 0x0000, 0x17, (_val)) 279 #define WRITE_SERDES_5601X_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 280 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 281 0x00, 0x0000, 0x17, (_val)) 282 #define MODIFY_SERDES_5601X_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 283 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x17, \ 284 (_val), (_mask)) 285 286 /* Prbs Control (Addr 18h) */ 287 #define READ_SERDES_5601X_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 288 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 289 0x00, 0x0000, 0x18, (_val)) 290 #define WRITE_SERDES_5601X_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 291 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 292 0x00, 0x0000, 0x18, (_val)) 293 #define MODIFY_SERDES_5601X_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 294 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 295 (_val), (_mask)) 296 297 /* Prbs Status (Addr 19h) */ 298 #define READ_SERDES_5601X_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 299 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 300 0x00, 0x0000, 0x19, (_val)) 301 #define WRITE_SERDES_5601X_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 302 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 303 0x00, 0x0000, 0x19, (_val)) 304 #define MODIFY_SERDES_5601X_1000X_PRBS_STATr(_unit, _phy_ctrl, _val, _mask) \ 305 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x19, \ 306 (_val), (_mask)) 307 308 /* Pat Gen Control (Addr 1Ah) */ 309 #define READ_SERDES_5601X_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 310 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 311 0x00, 0x0000, 0x1a, (_val)) 312 #define WRITE_SERDES_5601X_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 313 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 314 0x00, 0x0000, 0x1a, (_val)) 315 #define MODIFY_SERDES_5601X_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 316 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1a, \ 317 (_val), (_mask)) 318 319 /* Pat Gen Status (Addr 1Bh) */ 320 #define READ_SERDES_5601X_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 321 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 322 0x00, 0x0000, 0x1b, (_val)) 323 #define WRITE_SERDES_5601X_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 324 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 325 0x00, 0x0000, 0x1b, (_val)) 326 #define MODIFY_SERDES_5601X_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val, _mask) \ 327 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1b, \ 328 (_val), (_mask)) 329 330 /* Test Mode (Addr 1Ch) */ 331 #define READ_SERDES_5601X_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 332 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 333 0x00, 0x0000, 0x1c, (_val)) 334 #define WRITE_SERDES_5601X_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 335 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 336 0x00, 0x0000, 0x1c, (_val)) 337 #define MODIFY_SERDES_5601X_1000X_TEST_MODEr(_unit, _phy_ctrl, _val, _mask) \ 338 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1c, \ 339 (_val), (_mask)) 340 341 /* Force Tx Data1 (Addr 1Dh) */ 342 #define READ_SERDES_5601X_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 343 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 344 0x00, 0x0000, 0x1d, (_val)) 345 #define WRITE_SERDES_5601X_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 346 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 347 0x00, 0x0000, 0x1d, (_val)) 348 #define MODIFY_SERDES_5601X_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val, _mask) \ 349 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1d, \ 350 (_val), (_mask)) 351 352 /* Force Tx Data2 (Addr 1Eh) */ 353 #define READ_SERDES_5601X_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 354 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 355 0x00, 0x0000, 0x1e, (_val)) 356 #define WRITE_SERDES_5601X_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 357 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 358 0x00, 0x0000, 0x1e, (_val)) 359 #define MODIFY_SERDES_5601X_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val, _mask) \ 360 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 361 (_val), (_mask)) 362 363 /* 1000X Control #1 Register: Controls 10B/SGMII mode */ 364 #define DDS_1000X_FIBER_MODE (1 << 0) /* Enable SGMII fiber mode */ 365 #define DDS_1000X_EN10B_MODE (1 << 1) /* Enable TBI 10B interface */ 366 #define DDS_1000X_INVERT_SD (1 << 3) /* Invert Signal Detect */ 367 #define DDS_1000X_AUTO_DETECT (1 << 4) /* Auto-detect SGMII and 1000X */ 368 #define DDS_1000X_SGMII_MASTER (1 << 5) /* SGMII Master mode enable */ 369 #define DDS_1000X_RX_PKTS_CNTR_SEL (1 << 11) /* Select receive counter for 17h*/ 370 #define DDS_1000X_TX_AMPLITUDE_OVRD (1 << 12) 371 372 /* 1000X Control #2 Register Fields */ 373 #define DDS_1000X_PAR_DET_EN (1 << 0) /* Enable Parallel Detect */ 374 #define DDS_1000X_FALSE_LNK_DIS (1 << 1) /* Disable false link */ 375 #define DDS_1000X_FLT_FORCE_EN (1 << 2) /* Enable filter force link */ 376 #define DDS_1000X_CLRAR_BER_CNTR (1 << 14) /* Clear bit-err-rate counter */ 377 378 /* 1000X Control #3 Register Fields */ 379 #define DDS_1000X_TX_FIFO_RST (1 << 0) /* Reset TX FIFO */ 380 #define DDS_1000X_FIFO_ELASTICITY_MASK (0x3 << 1) /* Fifo Elasticity */ 381 #define DDS_1000X_FIFO_ELASTICITY_5K (0x0 << 1) /* 5 Kbytes */ 382 #define DDS_1000X_FIFO_ELASTICITY_10K (0x1 << 1) /* 10 Kbytes */ 383 #define DDS_1000X_FIFO_ELASTICITY_13_5K (0x2 << 1) /* 13.5 Kbytes */ 384 #define DDS_1000X_RX_FIFO_RST (1 << 14) /* Reset RX FIFO */ 385 386 /* 1000X Control #4 Register Fields */ 387 #define DDS_1000X_DIG_RESET (1 << 6) /* Reset Datapath */ 388 389 /* 1000X Status #1 Register Fields */ 390 #define DDS_1000X_STATUS1_SGMII_MODE (1 << 0) 391 #define DDS_1000X_STATUS1_SPEED (3 << 3) 392 #define DDS_1000X_STATUS1_SPEED_10 (0) 393 #define DDS_1000X_STATUS1_SPEED_100 (1 << 3) 394 #define DDS_1000X_STATUS1_SPEED_1000 (1 << 4) 395 396 397 /************************/ 398 /* Analog Block (Blk 1) */ 399 /************************/ 400 /* Analog Tx (Addr 10h) */ 401 #define READ_SERDES_5601X_ANALOG_TXr(_unit, _phy_ctrl, _val) \ 402 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 403 0x00, 0x0001, 0x10, (_val)) 404 #define WRITE_SERDES_5601X_ANALOG_TXr(_unit, _phy_ctrl, _val) \ 405 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 406 0x00, 0x0001, 0x10, (_val)) 407 #define MODIFY_SERDES_5601X_ANALOG_TXr(_unit, _phy_ctrl, _val, _mask) \ 408 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x10, \ 409 (_val), (_mask)) 410 411 /* Analog RX1 (Addr 11h) */ 412 #define READ_SERDES_5601X_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 413 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 414 0x00, 0x0001, 0x11, (_val)) 415 #define WRITE_SERDES_5601X_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 416 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 417 0x00, 0x0001, 0x11, (_val)) 418 #define MODIFY_SERDES_5601X_ANALOG_RX1r(_unit, _phy_ctrl, _val, _mask) \ 419 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x11, \ 420 (_val), (_mask)) 421 422 /* Analog RX2 (Addr 12h) */ 423 #define READ_SERDES_5601X_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 424 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 425 0x00, 0x0001, 0x12, (_val)) 426 #define WRITE_SERDES_5601X_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 427 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 428 0x00, 0x0001, 0x12, (_val)) 429 #define MODIFY_SERDES_5601X_ANALOG_RX2r(_unit, _phy_ctrl, _val, _mask) \ 430 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x12, \ 431 (_val), (_mask)) 432 433 /* Analog PLL (Addr 13h) */ 434 #define READ_SERDES_5601X_ANALOG_PLLr(_unit, _phy_ctrl, _val) \ 435 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 436 0x00, 0x0001, 0x13, (_val)) 437 #define WRITE_SERDES_5601X_ANALOG_PLLr(_unit, _phy_ctrl, _val) \ 438 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 439 0x00, 0x0001, 0x13, (_val)) 440 #define MODIFY_SERDES_5601X_ANALOG_PLLr(_unit, _phy_ctrl, _val, _mask) \ 441 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x13, \ 442 (_val), (_mask)) 443 444 /* Analog RX3 (Addr 14h) */ 445 #define READ_SERDES_5601X_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 446 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 447 0x00, 0x0001, 0x14, (_val)) 448 #define WRITE_SERDES_5601X_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 449 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 450 0x00, 0x0001, 0x14, (_val)) 451 #define MODIFY_SERDES_5601X_ANALOG_RX3r(_unit, _phy_ctrl, _val, _mask) \ 452 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x14, \ 453 (_val), (_mask)) 454 455 /* TPOUT1 (Addr 18h) */ 456 #define READ_SERDES_5601X_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val) \ 457 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 458 0x00, 0x0001, 0x18, (_val)) 459 #define WRITE_SERDES_5601X_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val) \ 460 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 461 0x00, 0x0001, 0x18, (_val)) 462 #define MODIFY_SERDES_5601X_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val, _mask) \ 463 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 464 (_val), (_mask)) 465 466 /* TPOUT2 (Addr 19h) */ 467 #define READ_SERDES_5601X_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val) \ 468 SERDES_5601X_REG_READ((_unit), (_phy_ctrl), \ 469 0x00, 0x0001, 0x19, (_val)) 470 #define WRITE_SERDES_5601X_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val) \ 471 SERDES_5601X_REG_WRITE((_unit), (_phy_ctrl), \ 472 0x00, 0x0001, 0x19, (_val)) 473 #define MODIFY_SERDES_5601X_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val, _mask) \ 474 SERDES_5601X_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x19, \ 475 (_val), (_mask)) 476 477 /* Analog Rx 1 Register Fields */ 478 #define DDS_ANALOG_RX1_IDDQ (1 << 0) 479 #define DDS_ANALOG_RX1_RESET (1 << 1) 480 #define DDS_ANALOG_RX1_EDGE_SEL (1 << 8) 481 #define DDS_ANALOG_RX1_SIG_DET (1 << 10) 482 483 #endif /* _PHY56XXX_5601X_H_ */