phy56xxx.h (24163B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: serdesdozen.h 8 * Purpose: BCM56xxx (FB/ER) Internal Dodeca Serdes PHY Driver 9 */ 10 11 #ifndef _SERDES_DOZEN_H_ 12 #define _SERDES_DOZEN_H_ 13 14 #include <soc/phy.h> 15 16 /* 17 * Definitions for Internal SerDes 10/100/1000 PHY 18 */ 19 20 /* MII Control Register */ 21 22 /* DDS: MII Control bit definitions, same as Standard 10/100 PHY */ 23 #define DDS_MII_CTRL_RESET MII_CTRL_RESET /* Self clearing SW reset */ 24 #define DDS_MII_CTRL_SS_LSB MII_CTRL_SS_LSB /* Speed Select, LSB */ 25 #define DDS_MII_CTRL_SS_MSB MII_CTRL_SS_MSB /* Speed Select, MSB */ 26 #define DDS_MII_CTRL_SS(_x) MII_CTRL_SS(_x) 27 #define DDS_MII_CTRL_SS_10 MII_CTRL_SS_10 28 #define DDS_MII_CTRL_SS_100 MII_CTRL_SS_100 29 #define DDS_MII_CTRL_SS_1000 MII_CTRL_SS_1000 30 #define DDS_MII_CTRL_SS_INVALID MII_CTRL_SS_INVALID 31 #define DDS_MII_CTRL_SS_MASK MII_CTRL_SS_MASK 32 #define DDS_MII_CTRL_FD MII_CTRL_FD /* Full Duplex */ 33 #define DDS_MII_CTRL_AN_RESTART (1 << 9) /* Auto Negotiation Enable */ 34 #define DDS_MII_CTRL_AN_ENABLE (1 << 12) /* Auto Negotiation Enable */ 35 #define DDS_MII_CTRL_PD MII_CTRL_PD /* Power Down Enable */ 36 #define DDS_MII_CTRL_LOOPBACK (1 << 14) /* Loopback Enable */ 37 38 /* MII Status Register */ 39 /* DDS: MII Status Register: not the same as standard 10/100 PHY */ 40 #define DDS_MII_STAT_RF MII_STAT_RF /* Remote fault */ 41 #define DDS_MII_STAT_LA MII_STAT_LA /* Link Up */ 42 #define DDS_MII_STAT_AN_COMPLETE (1 << 5) /* AN complete */ 43 44 /* Bit defines for ANA register */ 45 #define DDS_MII_ANA_HD (1 << 6) 46 #define DDS_MII_ANA_FD (1 << 5) 47 #define DDS_MII_ANA_PAUSE_NONE (0 << 7) 48 #define DDS_MII_ANA_PAUSE_SYM (1 << 7) 49 #define DDS_MII_ANA_PAUSE_ASYM (1 << 8) 50 #define DDS_MII_ANA_PAUSE_MASK (3 << 7) 51 52 /* Auto-Negotiation Link-Partner Ability Register */ 53 54 #define DDS_MII_ANP_FIBER_NEXT_PG (1 << 15) 55 #define DDS_MII_ANP_FIBER_ACK (1 << 14) 56 #define DDS_MII_ANP_FIBER_RF_SHFT (12) /* Remote fault */ 57 #define DDS_MII_ANP_FIBER_RF_MASK (0x3000) 58 #define DDS_MII_ANP_FIBER_PAUSE_ASYM (1 << 8) 59 #define DDS_MII_ANP_FIBER_PAUSE_SYM (1 << 7) 60 #define DDS_MII_ANP_FIBER_HD (1 << 6) 61 #define DDS_MII_ANP_FIBER_FD (1 << 5) 62 63 #define DDS_MII_ANP_SGMII (1 << 0) 64 #define DDS_MII_ANP_SGMII_DUPLEX (1 << 12) 65 #define DDS_MII_ANP_SGMII_SPEED (3 << 10) 66 #define DDS_MII_ANP_SGMII_SPEED_10 (0) 67 #define DDS_MII_ANP_SGMII_SPEED_100 (1 << 10) 68 #define DDS_MII_ANP_SGMII_SPEED_1000 (1 << 11) 69 70 /* Auto-Negotiation Expansion Register */ 71 #define DDS_ANA_EXPANSION_PR (1 << 1) /* Page received */ 72 73 74 /* If application want to use this header file for accessing PHY registers, 75 * simply redefine SERDESDDS_REG macros to use BCM API as follows. 76 * 77 * #define SERDESDDS_REG_READ(_unit, _port, _flags, _reg_bank, \ 78 * _reg_addr, _val) \ 79 * bcm_port_phy_get((_unit), (_port), 0, 80 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 81 * (_val)) 82 * 83 * #define SERDESDDS_REG_WRITE(_unit, _port, _flags, _reg_bank, \ 84 * _reg_addr, _val) \ 85 * bcm_port_phy_set((_unit), (_port), 0, 86 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 87 * (_val)) 88 * 89 * #define SERDESDDS_REG_MODIFY(_unit, _port, _flags, _reg_bank, \ 90 * _reg_addr, _val)\ 91 * do { \ 92 * return BCM_E_UNAVAIL; \ 93 * } while(0) 94 */ 95 96 /* SERDES register access */ 97 #define SERDESDDS_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, \ 98 _reg_addr, _val) \ 99 phy_reg_serdes_read((_unit), (_phy_ctrl), (_reg_bank), \ 100 (_reg_addr), (_val)) 101 #define SERDESDDS_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 102 _reg_addr, _val) \ 103 phy_reg_serdes_write((_unit), (_phy_ctrl), (_reg_bank), \ 104 (_reg_addr), (_val)) 105 #define SERDESDDS_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 106 _reg_addr, _val, _mask) \ 107 phy_reg_serdes_modify((_unit), (_phy_ctrl), (_reg_bank), \ 108 (_reg_addr), (_val), (_mask)) 109 110 /***************************/ 111 /* Standard IEEE Registers */ 112 /***************************/ 113 114 /* MII Control (Addr 00h) */ 115 #define READ_SERDESDDS_MII_CTRLr(_unit, _phy_ctrl, _val) \ 116 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 117 0x00, 0x0000, 0x00, (_val)) 118 #define WRITE_SERDESDDS_MII_CTRLr(_unit, _phy_ctrl, _val) \ 119 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 120 0x00, 0x0000, 0x00, (_val)) 121 #define MODIFY_SERDESDDS_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 122 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 123 (_val), (_mask)) 124 125 /* MII Status (Addr 01h) */ 126 #define READ_SERDESDDS_MII_STATr(_unit, _phy_ctrl, _val) \ 127 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 128 0x00, 0x0000, 0x01, (_val)) 129 #define WRITE_SERDESDDS_MII_STATr(_unit, _phy_ctrl, _val) \ 130 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 131 0x00, 0x0000, 0x01, (_val)) 132 #define MODIFY_SERDESDDS_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 133 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 134 (_val), (_mask)) 135 136 /* PHY ID 0 (Addr 02h) */ 137 #define READ_SERDESDDS_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 138 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 139 0x00, 0x0000, 0x02, (_val)) 140 #define WRITE_SERDESDDS_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 141 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 142 0x00, 0x0000, 0x02, (_val)) 143 #define MODIFY_SERDESDDS_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 144 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 145 (_val), (_mask)) 146 147 /* PHY ID 1 (Addr 03h) */ 148 #define READ_SERDESDDS_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 149 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 150 0x00, 0x0000, 0x03, (_val)) 151 #define WRITE_SERDESDDS_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 152 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 153 0x00, 0x0000, 0x03, (_val)) 154 #define MODIFY_SERDESDDS_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 155 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 156 (_val), (_mask)) 157 158 /* Autoneg Adv (Addr 04h) */ 159 #define READ_SERDESDDS_MII_ANAr(_unit, _phy_ctrl, _val) \ 160 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 161 0x00, 0x0000, 0x04, (_val)) 162 #define WRITE_SERDESDDS_MII_ANAr(_unit, _phy_ctrl, _val) \ 163 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 164 0x00, 0x0000, 0x04, (_val)) 165 #define MODIFY_SERDESDDS_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 166 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 167 (_val), (_mask)) 168 169 /* Autoneg Link Partner Ability (Addr 05h) */ 170 #define READ_SERDESDDS_MII_ANPr(_unit, _phy_ctrl, _val) \ 171 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 172 0x00, 0x0000, 0x05, (_val)) 173 #define WRITE_SERDESDDS_MII_ANPr(_unit, _phy_ctrl, _val) \ 174 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 175 0x00, 0x0000, 0x05, (_val)) 176 #define MODIFY_SERDESDDS_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 177 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 178 (_val), (_mask)) 179 180 /* Autoneg Expansion (Addr 06h) */ 181 #define READ_SERDESDDS_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 182 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 183 0x00, 0x0000, 0x06, (_val)) 184 #define WRITE_SERDESDDS_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 185 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 186 0x00, 0x0000, 0x06, (_val)) 187 #define MODIFY_SERDESDDS_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 188 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 189 (_val), (_mask)) 190 191 /* Extended Status (Addr 0fh) */ 192 193 /*************************/ 194 /* Digital Block (Blk 0) */ 195 /*************************/ 196 /* 1000X Control 1 (Addr 10h) */ 197 #define READ_SERDESDDS_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 198 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 199 0x00, 0x0000, 0x10, (_val)) 200 #define WRITE_SERDESDDS_1000X_CTRL1r(_unit, _phy_ctrl, _val) \ 201 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 202 0x00, 0x0000, 0x10, (_val)) 203 #define MODIFY_SERDESDDS_1000X_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 204 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 205 (_val), (_mask)) 206 207 /* 1000X Control 2 (Addr 11h) */ 208 #define READ_SERDESDDS_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 209 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 210 0x00, 0x0000, 0x11, (_val)) 211 #define WRITE_SERDESDDS_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 212 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 213 0x00, 0x0000, 0x11, (_val)) 214 #define MODIFY_SERDESDDS_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 215 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 216 (_val), (_mask)) 217 218 /* 1000X Control 3 (Addr 12h) */ 219 #define READ_SERDESDDS_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 220 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 221 0x00, 0x0000, 0x12, (_val)) 222 #define WRITE_SERDESDDS_1000X_CTRL3r(_unit, _phy_ctrl, _val) \ 223 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 224 0x00, 0x0000, 0x12, (_val)) 225 #define MODIFY_SERDESDDS_1000X_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 226 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x12, \ 227 (_val), (_mask)) 228 229 /* 1000X Control 4 (Addr 13h) */ 230 #define READ_SERDESDDS_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 231 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 232 0x00, 0x0000, 0x13, (_val)) 233 #define WRITE_SERDESDDS_1000X_CTRL4r(_unit, _phy_ctrl, _val) \ 234 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 235 0x00, 0x0000, 0x13, (_val)) 236 #define MODIFY_SERDESDDS_1000X_CTRL4r(_unit, _phy_ctrl, _val, _mask) \ 237 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x13, \ 238 (_val), (_mask)) 239 240 /* 1000X Status 1 (Addr 14h) */ 241 #define READ_SERDESDDS_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 242 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 243 0x00, 0x0000, 0x14, (_val)) 244 #define WRITE_SERDESDDS_1000X_STAT1r(_unit, _phy_ctrl, _val) \ 245 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 246 0x00, 0x0000, 0x14, (_val)) 247 #define MODIFY_SERDESDDS_1000X_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 248 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x14, \ 249 (_val), (_mask)) 250 251 /* 1000X Status 2 (Addr 15h) */ 252 #define READ_SERDESDDS_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 253 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 254 0x00, 0x0000, 0x15, (_val)) 255 #define WRITE_SERDESDDS_1000X_STAT2r(_unit, _phy_ctrl, _val) \ 256 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 257 0x00, 0x0000, 0x15, (_val)) 258 #define MODIFY_SERDESDDS_1000X_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 259 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x15, \ 260 (_val), (_mask)) 261 262 /* 1000X Status 3 (Addr 16h) */ 263 #define READ_SERDESDDS_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 264 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 265 0x00, 0x0000, 0x16, (_val)) 266 #define WRITE_SERDESDDS_1000X_STAT3r(_unit, _phy_ctrl, _val) \ 267 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 268 0x00, 0x0000, 0x16, (_val)) 269 #define MODIFY_SERDESDDS_1000X_STAT3r(_unit, _phy_ctrl, _val, _mask) \ 270 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x16, \ 271 (_val), (_mask)) 272 273 /* Ber Crc Err Rx Pkt cntr (Addr 17h) */ 274 #define READ_SERDESDDS_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 275 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 276 0x00, 0x0000, 0x17, (_val)) 277 #define WRITE_SERDESDDS_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 278 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 279 0x00, 0x0000, 0x17, (_val)) 280 #define MODIFY_SERDESDDS_1000X_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 281 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x17, \ 282 (_val), (_mask)) 283 284 /* Prbs Control (Addr 18h) */ 285 #define READ_SERDESDDS_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 286 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 287 0x00, 0x0000, 0x18, (_val)) 288 #define WRITE_SERDESDDS_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val) \ 289 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 290 0x00, 0x0000, 0x18, (_val)) 291 #define MODIFY_SERDESDDS_1000X_PRBS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 292 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 293 (_val), (_mask)) 294 295 /* Prbs Status (Addr 19h) */ 296 #define READ_SERDESDDS_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 297 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 298 0x00, 0x0000, 0x19, (_val)) 299 #define WRITE_SERDESDDS_1000X_PRBS_STATr(_unit, _phy_ctrl, _val) \ 300 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 301 0x00, 0x0000, 0x19, (_val)) 302 #define MODIFY_SERDESDDS_1000X_PRBS_STATr(_unit, _phy_ctrl, _val, _mask) \ 303 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x19, \ 304 (_val), (_mask)) 305 306 /* Pat Gen Control (Addr 1Ah) */ 307 #define READ_SERDESDDS_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 308 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 309 0x00, 0x0000, 0x1a, (_val)) 310 #define WRITE_SERDESDDS_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val) \ 311 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 312 0x00, 0x0000, 0x1a, (_val)) 313 #define MODIFY_SERDESDDS_1000X_PAT_GEN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 314 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1a, \ 315 (_val), (_mask)) 316 317 /* Pat Gen Status (Addr 1Bh) */ 318 #define READ_SERDESDDS_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 319 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 320 0x00, 0x0000, 0x1b, (_val)) 321 #define WRITE_SERDESDDS_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val) \ 322 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 323 0x00, 0x0000, 0x1b, (_val)) 324 #define MODIFY_SERDESDDS_1000X_PAT_GEN_STATr(_unit, _phy_ctrl, _val, _mask) \ 325 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1b, \ 326 (_val), (_mask)) 327 328 /* Test Mode (Addr 1Ch) */ 329 #define READ_SERDESDDS_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 330 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 331 0x00, 0x0000, 0x1c, (_val)) 332 #define WRITE_SERDESDDS_1000X_TEST_MODEr(_unit, _phy_ctrl, _val) \ 333 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 334 0x00, 0x0000, 0x1c, (_val)) 335 #define MODIFY_SERDESDDS_1000X_TEST_MODEr(_unit, _phy_ctrl, _val, _mask) \ 336 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1c, \ 337 (_val), (_mask)) 338 339 /* Force Tx Data1 (Addr 1Dh) */ 340 #define READ_SERDESDDS_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 341 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 342 0x00, 0x0000, 0x1d, (_val)) 343 #define WRITE_SERDESDDS_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val) \ 344 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 345 0x00, 0x0000, 0x1d, (_val)) 346 #define MODIFY_SERDESDDS_1000X_FORCE_TX_DATA1r(_unit, _phy_ctrl, _val, _mask) \ 347 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1d, \ 348 (_val), (_mask)) 349 350 /* Force Tx Data2 (Addr 1Eh) */ 351 #define READ_SERDESDDS_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 352 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 353 0x00, 0x0000, 0x1e, (_val)) 354 #define WRITE_SERDESDDS_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val) \ 355 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 356 0x00, 0x0000, 0x1e, (_val)) 357 #define MODIFY_SERDESDDS_1000X_FORCE_TX_DATA2r(_unit, _phy_ctrl, _val, _mask) \ 358 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 359 (_val), (_mask)) 360 361 /* 1000X Control #1 Register: Controls 10B/SGMII mode */ 362 #define DDS_1000X_FIBER_MODE (1 << 0) /* Enable SGMII fiber mode */ 363 #define DDS_1000X_EN10B_MODE (1 << 1) /* Enable TBI 10B interface */ 364 #define DDS_1000X_INVERT_SD (1 << 3) /* Invert Signal Detect */ 365 #define DDS_1000X_AUTO_DETECT (1 << 4) /* Auto-detect SGMII and 1000X */ 366 #define DDS_1000X_SGMII_MASTER (1 << 5) /* SGMII Master mode enable */ 367 #define DDS_1000X_RX_PKTS_CNTR_SEL (1 << 11) /* Select receive counter for 17h*/ 368 #define DDS_1000X_TX_AMPLITUDE_OVRD (1 << 12) 369 370 /* 1000X Control #2 Register Fields */ 371 #define DDS_1000X_PAR_DET_EN (1 << 0) /* Enable Parallel Detect */ 372 #define DDS_1000X_FALSE_LNK_DIS (1 << 1) /* Disable false link */ 373 #define DDS_1000X_FLT_FORCE_EN (1 << 2) /* Enable filter force link */ 374 #define DDS_1000X_FORCE_XMIT_TX (1 << 5) /* Force xmit on tx side */ 375 #define DDS_1000X_CLRAR_BER_CNTR (1 << 14) /* Clear bit-err-rate counter */ 376 377 /* 1000X Control #3 Register Fields */ 378 #define DDS_1000X_TX_FIFO_RST (1 << 0) /* Reset TX FIFO */ 379 #define DDS_1000X_FIFO_ELASTICITY_MASK (0x3 << 1) /* Fifo Elasticity */ 380 #define DDS_1000X_FIFO_ELASTICITY_5K (0x0 << 1) /* 5 Kbytes */ 381 #define DDS_1000X_FIFO_ELASTICITY_10K (0x1 << 1) /* 10 Kbytes */ 382 #define DDS_1000X_FIFO_ELASTICITY_13_5K (0x2 << 1) /* 13.5 Kbytes */ 383 #define DDS_1000X_RX_FIFO_RST (1 << 14) /* Reset RX FIFO */ 384 385 /* 1000X Control #4 Register Fields */ 386 #define DDS_1000X_LINK_FORCE (1 << 7) /* Link Force */ 387 #define DDS_1000X_DIG_RESET (1 << 6) /* Reset Datapath */ 388 #define DDS_1000X_ANALOG_SIG_DETECT (1 << 0) /* User analog signal det */ 389 390 /* 1000X Status #1 Register Fields */ 391 #define DDS_1000X_STATUS1_SGMII_MODE (1 << 0) 392 #define DDS_1000X_STATUS1_SPEED (3 << 3) 393 #define DDS_1000X_STATUS1_SPEED_10 (0) 394 #define DDS_1000X_STATUS1_SPEED_100 (1 << 3) 395 #define DDS_1000X_STATUS1_SPEED_1000 (1 << 4) 396 397 398 /************************/ 399 /* Analog Block (Blk 1) */ 400 /************************/ 401 /* Analog Tx (Addr 10h) */ 402 #define READ_SERDESDDS_ANALOG_TXr(_unit, _phy_ctrl, _val) \ 403 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 404 0x00, 0x0001, 0x10, (_val)) 405 #define WRITE_SERDESDDS_ANALOG_TXr(_unit, _phy_ctrl, _val) \ 406 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 407 0x00, 0x0001, 0x10, (_val)) 408 #define MODIFY_SERDESDDS_ANALOG_TXr(_unit, _phy_ctrl, _val, _mask) \ 409 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x10, \ 410 (_val), (_mask)) 411 412 /* Analog RX1 (Addr 11h) */ 413 #define READ_SERDESDDS_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 414 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 415 0x00, 0x0001, 0x11, (_val)) 416 #define WRITE_SERDESDDS_ANALOG_RX1r(_unit, _phy_ctrl, _val) \ 417 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 418 0x00, 0x0001, 0x11, (_val)) 419 #define MODIFY_SERDESDDS_ANALOG_RX1r(_unit, _phy_ctrl, _val, _mask) \ 420 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x11, \ 421 (_val), (_mask)) 422 423 /* Analog RX2 (Addr 12h) */ 424 #define READ_SERDESDDS_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 425 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 426 0x00, 0x0001, 0x12, (_val)) 427 #define WRITE_SERDESDDS_ANALOG_RX2r(_unit, _phy_ctrl, _val) \ 428 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 429 0x00, 0x0001, 0x12, (_val)) 430 #define MODIFY_SERDESDDS_ANALOG_RX2r(_unit, _phy_ctrl, _val, _mask) \ 431 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x12, \ 432 (_val), (_mask)) 433 434 /* Analog PLL (Addr 13h) */ 435 #define READ_SERDESDDS_ANALOG_PLLr(_unit, _phy_ctrl, _val) \ 436 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 437 0x00, 0x0001, 0x13, (_val)) 438 #define WRITE_SERDESDDS_ANALOG_PLLr(_unit, _phy_ctrl, _val) \ 439 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 440 0x00, 0x0001, 0x13, (_val)) 441 #define MODIFY_SERDESDDS_ANALOG_PLLr(_unit, _phy_ctrl, _val, _mask) \ 442 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x13, \ 443 (_val), (_mask)) 444 445 /* Analog RX3 (Addr 14h) */ 446 #define READ_SERDESDDS_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 447 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 448 0x00, 0x0001, 0x14, (_val)) 449 #define WRITE_SERDESDDS_ANALOG_RX3r(_unit, _phy_ctrl, _val) \ 450 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 451 0x00, 0x0001, 0x14, (_val)) 452 #define MODIFY_SERDESDDS_ANALOG_RX3r(_unit, _phy_ctrl, _val, _mask) \ 453 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x14, \ 454 (_val), (_mask)) 455 456 /* TPOUT1 (Addr 18h) */ 457 #define READ_SERDESDDS_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val) \ 458 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 459 0x00, 0x0001, 0x18, (_val)) 460 #define WRITE_SERDESDDS_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val) \ 461 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 462 0x00, 0x0001, 0x18, (_val)) 463 #define MODIFY_SERDESDDS_ANALOG_TPOUT1r(_unit, _phy_ctrl, _val, _mask) \ 464 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 465 (_val), (_mask)) 466 467 /* TPOUT2 (Addr 19h) */ 468 #define READ_SERDESDDS_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val) \ 469 SERDESDDS_REG_READ((_unit), (_phy_ctrl), \ 470 0x00, 0x0001, 0x19, (_val)) 471 #define WRITE_SERDESDDS_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val) \ 472 SERDESDDS_REG_WRITE((_unit), (_phy_ctrl), \ 473 0x00, 0x0001, 0x19, (_val)) 474 #define MODIFY_SERDESDDS_ANALOG_TPOUT2r(_unit, _phy_ctrl, _val, _mask) \ 475 SERDESDDS_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x19, \ 476 (_val), (_mask)) 477 478 /* Analog Rx 1 Register Fields */ 479 #define DDS_ANALOG_RX1_IDDQ (1 << 0) 480 #define DDS_ANALOG_RX1_RESET (1 << 1) 481 #define DDS_ANALOG_RX1_EDGE_SEL (1 << 8) 482 #define DDS_ANALOG_RX1_SIG_DET (1 << 10) 483 484 #endif /* _SERDES_DOZEN_H_ */