phy5690.h (6925B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy5690.h 8 * Purpose: BCM5690 (Draco) Internal Quad Serdes PHY Driver 9 */ 10 11 #ifndef _PHY_5690_H_ 12 #define _PHY_5690_H_ 13 14 #include <soc/phy.h> 15 16 /* 17 * Definitions for Draco Quad Serdes Internal 10/100/1000 PHY 18 * From: Draco Serdes MII Register Specification: v2.0 19 */ 20 21 /* MII Control register */ 22 #define QS_MII_CTRL_REG MII_CTRL_REG /* 0x00 */ 23 /* QS: MII Control bit definitions, same as Standard 10/100 PHY */ 24 #define QS_MII_CTRL_RESET MII_CTRL_RESET /* Pulse 1us, for SW reset */ 25 #define QS_MII_CTRL_SS_LSB MII_CTRL_SS_LSB /* Speed Select, LSB */ 26 #define QS_MII_CTRL_SS_MSB MII_CTRL_SS_MSB /* Speed Select, MSB */ 27 #define QS_MII_CTRL_SS(_x) MII_CTRL_SS(_x) 28 #define QS_MII_CTRL_SS_10 MII_CTRL_SS_10 29 #define QS_MII_CTRL_SS_100 MII_CTRL_SS_100 30 #define QS_MII_CTRL_SS_1000 MII_CTRL_SS_1000 31 #define QS_MII_CTRL_SS_INVALID MII_CTRL_SS_INVALID 32 #define QS_MII_CTRL_SS_MASK MII_CTRL_SS_MASK 33 #define QS_MII_CTRL_FD MII_CTRL_FD /* Full Duplex */ 34 35 #define QS_MII_STAT_REG MII_STAT_REG /* 0x01 */ 36 /* QS: MII Status Register: not the same as standard 10/100 PHY */ 37 #define QS_MII_STAT_RF MII_STAT_RF /* Remote fault */ 38 #define QS_MII_STAT_LA MII_STAT_LA /* Link active */ 39 #define QS_MII_FD_CAPABLE (1 << 6) 40 #define QS_MII_HD_CAPABLE (1 << 5) 41 42 /* Auto-negotiation advertisement register */ 43 #define QS_ANA_REG 0x04 44 45 /* Bit defines for ANA register */ 46 #define QS_MII_ANA_FD (1 << 6) 47 #define QS_MII_ANA_HD (1 << 5) 48 49 /* Auto-Negotiation Link-Partner Ability Register */ 50 #define QS_ANP_REG 0x05 51 52 #define QS_MII_ANP_SGMII_LINK (1 << 15) 53 #define QS_MII_ANP_SGMII_FD (1 << 12) 54 #define QS_MII_ANP_SGMII_SPEED_SHFT 10 55 #define QS_MII_ANP_SGMII_SPEED_MASK 0x0c00 56 57 #define QS_MII_ANP_FIBER_NEXT_PG (1 << 15) 58 #define QS_MII_ANP_FIBER_ACK (1 << 14) 59 #define QS_MII_ANP_FIBER_RF_SHFT 12 /* Remote fault */ 60 #define QS_MII_ANP_FIBER_RF_MASK 0x3000 61 #define QS_MII_ANP_FIBER_PAUSE_ASYM (1 << 8) 62 #define QS_MII_ANP_FIBER_PAUSE_SYM (1 << 7) 63 #define QS_MII_ANP_FIBER_HD (1 << 6) 64 #define QS_MII_ANP_FIBER_FD (1 << 5) 65 66 /* Auto-Negotiation Expansion Register */ 67 #define QS_ANA_EXPANSION_REG MII_AN_EXP_REG 68 #define QS_ANA_EXPANSION_PR (1 << 1) /* Page received */ 69 70 /* SGMII Control register. Quad Serdes comes up with ANA enabled. */ 71 #define QS_SGMII_CTRL_REG 0x0B 72 #define QS_SGMII_FORCE_DATA (1 << 15) /* Force Data mode (see spec) */ 73 #define QS_SGMII_RF_SHFT 13 /* Remote Fault */ 74 #define QS_SGMII_RF_MASK 0x6000 75 #define QS_SGMII_PAUSE_ASYM (1 << 12) 76 #define QS_SGMII_PAUSE_SYM (1 << 11) 77 #define QS_SGMII_AN_SEL (1 << 10) /* Select SGMII ANA, or IEEE c37 ANA */ 78 #define QS_SGMII_RX_PRE_EXT (1 << 9) /* If 1, disable RX early preamble */ 79 /* extension for 10/100 mode. */ 80 /* This bit is not in 5690A0/A1). */ 81 #define QS_SGMII_ERR_TIMER_EN (1 << 8) 82 #define QS_SGMII_REV_PHASE (1 << 7) 83 #define QS_SGMII_EXT_CTRL (1 << 6) 84 #define QS_SGMII_TX_PRE_EXT (1 << 5) /* If 1, enable TX early preamble */ 85 /* extension for all speeds (short */ 86 /* latency enable). */ 87 #define QS_SGMII_CDET_DISABLE (1 << 4) /* If 1, disable comma detector */ 88 #define QS_SGMII_AN_TEST_MODE (1 << 3) 89 #define QS_SGMII_AN_DISABLE (1 << 2) /* If 1, disable ANA to data mode*/ 90 #define QS_SGMII_REMOTE_LOOP (1 << 1) /* Enable remote loopback */ 91 #define QS_SGMII_TBI_LOOP (1 << 0) /* Enable TBI loopback */ 92 93 /* SGMII Status Register */ 94 #define QS_SGMII_STAT_REG 0x0C 95 #define QS_SGMII_ANA_COMPLETE (1 << 1) /* Autonegotiation completed */ 96 #define QS_SGMII_ANA_ERROR (1 << 0) /* SGMII Autoneg error flag */ 97 98 /* SGMII CRC Register: bits 0:15 contain SGMII CRC value */ 99 #define QS_SGMII_CRC_REG 0x0D 100 101 /* SGMII Misc Control Register */ 102 #define QS_SGMII_MISC_REG 0x0E 103 #define QS_SGMII_ANA_RESTART (1 << 0) /* Restart Autonegotiation */ 104 105 /* SGMII Control #2 Register: Controls 10B/SGMII mode */ 106 #define QS_SGMII_CTRL2_REG 0x0F 107 #define QS_SGMII_EN10B_MODE (1 << 1) /* Enable TBI 10B interface */ 108 #define QS_SGMII_FIBER_MODE (1 << 0) /* Enable SGMII fiber mode */ 109 110 /* Serdes TX Control register */ 111 #define QS_SERDES_TX_CTRL_REG 0x10 112 #define QS_SERDES_TX_PD (1 << 15) /* Power-down Serdes */ 113 #define QS_SERDES_BIAS_REFH (1 << 14) /* Bias generator RefH */ 114 #define QS_SERDES_BIAS_REFL (1 << 13) /* Bias generator RefL */ 115 #define QS_SERDES_CPM_ENABLE (1 << 12) /* Clock Phase Mode enable */ 116 #define QS_SERDES_RXW_SEL (1 << 11) /* Clock (rxwclk) edge select */ 117 118 /* Serdes RX Control register */ 119 #define QS_SERDES_RX_CTRL_REG 0x11 120 #define QS_SERDES_RX_PD (1 << 15) /* Power-down Serdes */ 121 #define QS_SERDES_PE_ENA (1 << 14) /* Pre-Emphasis enable */ 122 #define QS_SERDES_TX_CRS_LB (1 << 13) /* If 0, MAC_CRS = RX_CRS or TX_CRS */ 123 /* If 1, MAC_CRS = RX_CRS only */ 124 #define QS_SERDES_PL_CLK_EDGE (1 << 12) /* Parallel load clock edge */ 125 126 /* Phase Control and Status Registers */ 127 #define QS_PHASE_CTRL_REG 0x12 128 #define QS_PHASE_STAT_REG 0x13 129 130 /* SGMII Misc control register */ 131 #define QS_SGMII_MISC_CTRL_REG 0x14 132 133 #define QS_SGMII_IDDQ_MODE (1 << 5) /* Put Serdes in IDDQ mode */ 134 /* Configuration/Link detection in SGMII mode */ 135 #define QS_SGMII_SIGNAL_DETECT (1 << 3) /* When in SGMII, pin tied to 1*/ 136 #define QS_SGMII_SGMII_ENABLE (1 << 2) /* If 1, enable SGMII mode */ 137 138 /* When autoneg is enabled, MAC_MODE=0, When disabled, MAC_MODE=1 */ 139 #define QS_SGMII_MAC_MODE (1 << 1) /* Always inverse of MII_CTRL.an_ena */ 140 141 /* External PHY link status */ 142 #define QS_SGMII_LINK_STATUS (1 << 0) /* Copper XCVR final status*/ 143 144 /* Misc SGMII control definitions */ 145 #define QS_SGMII_MISC_STAT_REG 0x15 146 #define QS_SGMII_MISC_PRLE (1 << 2) /* Priority resolution error enable*/ 147 #define QS_SGMII_PLL_LOCK (1 << 1) /* PLL lock detect */ 148 149 /* Common registers: Shares for all 4-ports on Serdes Module */ 150 #define QS_PLL_CTRL_REG 0x16 151 #define QS_HW_RESET (1 << 7) /* S/W Hard reset of Serdes core*/ 152 #define QS_PLL_TEST_ENA (1 << 2) /* Enable PLL test */ 153 #define QS_PLL_RESET (1 << 1) /* Reset PLL */ 154 #define QS_PLL_PD (1 << 0) /* Powerdown PLL */ 155 156 /* Other test and Control registers */ 157 #define QS_TEST_MUX_CTRL_REG 0x17 /* Shared for all 4-ports */ 158 #define QS_PRBS_TEST_CTRL_REG 0x18 159 #define QS_PRBS_TEST_STAT_REG 0x19 160 #define QS_BERT_IPG_REG 0x1A 161 #define QS_BERT_CTRL_REG 0x1B 162 #define QS_BERT_OVERFLOW_REG 0x1C 163 #define QS_BERT_MDIO_CTRL_REG 0x1D 164 #define QS_BERT_MDIO_DATA_REG 0x1E 165 166 167 /* To Use onboard MII Controller, Bit 7 selects internal MDIO */ 168 #define QS_PHY_ADDR(phyid) (0x80 | (phyid)) 169 170 #endif /* _PHY_5690_H_ */