phy54xx.h (15512B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy54xx.h 8 */ 9 10 #ifndef _PHY54XX_H_ 11 #define _PHY54XX_H_ 12 13 #include <soc/phy.h> 14 15 /* PHY register access */ 16 #define PHY54XX_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 17 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 18 (_reg_addr), (_val)) 19 #define PHY54XX_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, \ 20 _reg_addr, _val) \ 21 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 22 (_reg_addr), (_val)) 23 #define PHY54XX_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 24 _reg_addr, _val, _mask) \ 25 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 26 (_reg_addr), (_val), (_mask)) 27 28 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 29 #define READ_PHY54XX_MII_CTRLr(_unit, _phy_ctrl, _val) \ 30 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 31 #define WRITE_PHY54XX_MII_CTRLr(_unit, _phy_ctrl, _val) \ 32 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 33 #define MODIFY_PHY54XX_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 34 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 35 (_val), (_mask)) 36 37 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 38 #define READ_PHY54XX_MII_STATr(_unit, _phy_ctrl, _val) \ 39 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 40 #define WRITE_PHY54XX_MII_STATr(_unit, _phy_ctrl, _val) \ 41 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 42 #define MODIFY_PHY54XX_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 43 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 44 (_val), (_mask)) 45 46 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 47 #define READ_PHY54XX_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 48 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 49 #define WRITE_PHY54XX_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 50 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 51 #define MODIFY_PHY54XX_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 52 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 53 (_val), (_mask)) 54 55 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 56 #define READ_PHY54XX_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 57 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 58 #define WRITE_PHY54XX_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 59 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 60 #define MODIFY_PHY54XX_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 61 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 62 (_val), (_mask)) 63 64 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 65 #define READ_PHY54XX_MII_ANAr(_unit, _phy_ctrl, _val) \ 66 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 67 #define WRITE_PHY54XX_MII_ANAr(_unit, _phy_ctrl, _val) \ 68 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 69 #define MODIFY_PHY54XX_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 70 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 71 (_val), (_mask)) 72 73 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 74 #define READ_PHY54XX_MII_ANPr(_unit, _phy_ctrl, _val) \ 75 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 76 #define WRITE_PHY54XX_MII_ANPr(_unit, _phy_ctrl, _val) \ 77 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 78 #define MODIFY_PHY54XX_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 79 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 80 (_val), (_mask)) 81 82 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 83 #define READ_PHY54XX_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 84 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 85 #define WRITE_PHY54XX_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 86 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 87 #define MODIFY_PHY54XX_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 88 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 89 (_val), (_mask)) 90 91 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 92 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 93 94 /* 1000BASE-T Control Register (ADDR 09h) */ 95 #define READ_PHY54XX_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 96 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 97 #define WRITE_PHY54XX_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 98 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 99 #define MODIFY_PHY54XX_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 100 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 101 (_val), (_mask)) 102 103 /* 1000BASE-T Status Register (ADDR 0ah) */ 104 #define READ_PHY54XX_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 105 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 106 #define WRITE_PHY54XX_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 107 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 108 #define MODIFY_PHY54XX_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 109 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 110 (_val), (_mask)) 111 112 /* SGMII/1000X Control Register (Addr 0bh) */ 113 #define READ_PHY54XX_SGMII_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 114 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0b, (_val)) 115 #define WRITE_PHY54XX_SGMII_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 116 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0b, (_val)) 117 #define MODIFY_PHY54XX_SGMII_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 118 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0b, \ 119 (_val), (_mask)) 120 121 /* SGMII/1000X Status Register (Addr 0ch) */ 122 #define READ_PHY54XX_SGMII_1000X_STATr(_unit, _phy_ctrl, _val) \ 123 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0c, (_val)) 124 #define WRITE_PHY54XX_SGMII_1000X_STATr(_unit, _phy_ctrl, _val) \ 125 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0c, (_val)) 126 #define MODIFY_PHY54XX_SGMII_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 127 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0c, \ 128 (_val), (_mask)) 129 130 /* 1000-X Link Partner Capabilities Register (Addr 0dh) */ 131 #define READ_PHY54XX_1000X_ANPr(_unit, _phy_ctrl, _val) \ 132 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0d, (_val)) 133 #define WRITE_PHY54XX_1000X_ANPr(_unit, _phy_ctrl, _val) \ 134 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0d, (_val)) 135 #define MODIFY_PHY54XX_1000X_ANPr(_unit, _phy_ctrl, _val, _mask) \ 136 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0d, \ 137 (_val), (_mask)) 138 139 /* SGMII/1000-X Misc Register (Addr 0eh) */ 140 #define READ_PHY54XX_SGMII_1000X_MISCr(_unit, _phy_ctrl, _val) \ 141 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0e, (_val)) 142 #define WRITE_PHY54XX_SGMII_1000X_MISCr(_unit, _phy_ctrl, _val) \ 143 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0e, (_val)) 144 #define MODIFY_PHY54XX_SGMII_1000X_MISCr(_unit, _phy_ctrl, _val, _mask) \ 145 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0e, \ 146 (_val), (_mask)) 147 148 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 149 150 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 151 #define READ_PHY54XX_MII_ECRr(_unit, _phy_ctrl, _val) \ 152 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 153 #define WRITE_PHY54XX_MII_ECRr(_unit, _phy_ctrl, _val) \ 154 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 155 #define MODIFY_PHY54XX_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 156 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 157 (_val), (_mask)) 158 159 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 160 #define READ_PHY54XX_MII_ESRr(_unit, _phy_ctrl, _val) \ 161 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 162 #define WRITE_PHY54XX_MII_ESRr(_unit, _phy_ctrl, _val) \ 163 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 164 #define MODIFY_PHY54XX_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 165 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 166 (_val), (_mask)) 167 168 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 169 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 170 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 171 172 /* Auxiliary Control Register for Normal Operation (Addr 18h Shadow 000) */ 173 #define READ_PHY54XX_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 174 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 175 #define WRITE_PHY54XX_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 176 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 177 #define MODIFY_PHY54XX_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 178 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 179 (_val), (_mask)) 180 181 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 182 #define READ_PHY54XX_10BASE_Tr(_unit, _phy_ctrl, _val) \ 183 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 184 #define WRITE_PHY54XX_10BASE_Tr(_unit, _phy_ctrl, _val) \ 185 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 186 #define MODIFY_PHY54XX_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 187 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 188 (_val), (_mask)) 189 190 /* Power Control Reg (ADDR 18h Shadow 010)*/ 191 #define READ_PHY54XX_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 192 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 193 #define WRITE_PHY54XX_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 194 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 195 #define MODIFY_PHY54XX_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 196 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 197 (_val), (_mask)) 198 199 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 200 #define READ_PHY54XX_MISC_TESTr(_unit, _phy_ctrl, _val) \ 201 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 202 #define WRITE_PHY54XX_MISC_TESTr(_unit, _phy_ctrl, _val) \ 203 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 204 #define MODIFY_PHY54XX_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 205 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 206 (_val), (_mask)) 207 208 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 209 #define READ_PHY54XX_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 210 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 211 #define WRITE_PHY54XX_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 212 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 213 #define MODIFY_PHY54XX_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 214 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 215 (_val), (_mask)) 216 217 /* Auxiliary Status Summary Register (ADDR 19h) */ 218 /* Interrupt Status Register (ADDR 1ah) */ 219 /* Interrupt Mask Register (ADDR 1bh) */ 220 221 /* Spare Ctrl 1 Reg (ADDR 1ch shadow 00010) */ 222 #define READ_PHY54XX_SPARE_CTRL1r(_unit, _phy_ctrl, _val) \ 223 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 224 #define WRITE_PHY54XX_SPARE_CTRL1r(_unit, _phy_ctrl, _val) \ 225 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 226 #define MODIFY_PHY54XX_SPARE_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 227 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 228 (_val), (_mask)) 229 230 /* Spare Control 2 Reg (Addr 1ch shadow 00100) */ 231 #define READ_PHY54XX_SPARE_CTRL2r(_unit, _phy_ctrl, _val) \ 232 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 233 #define WRITE_PHY54XX_SPARE_CTRL2r(_unit, _phy_ctrl, _val) \ 234 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 235 #define MODIFY_PHY54XX_SPARE_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 236 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 237 (_val), (_mask)) 238 239 /* Spare Control 3 Reg (Addr 1ch shadow 00101) */ 240 #define READ_PHY54XX_SPARE_CTRL3r(_unit, _phy_ctrl, _val) \ 241 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 242 #define WRITE_PHY54XX_SPARE_CTRL3r(_unit, _phy_ctrl, _val) \ 243 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 244 #define MODIFY_PHY54XX_SPARE_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 245 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 246 (_val), (_mask)) 247 248 /* LED Status Register (Addr 1ch shadow 01000) */ 249 #define READ_PHY54XX_LED_STATr(_unit, _phy_ctrl, _val) \ 250 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 251 #define WRITE_PHY54XX_LED_STATr(_unit, _phy_ctrl, _val) \ 252 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 253 #define MODIFY_PHY54XX_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 254 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 255 (_val), (_mask)) 256 257 /* LED Control Register (Addr 1ch shadow 01001) */ 258 #define READ_PHY54XX_LED_CTRLr(_unit, _phy_ctrl, _val) \ 259 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 260 #define WRITE_PHY54XX_LED_CTRL3r(_unit, _phy_ctrl, _val) \ 261 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 262 #define MODIFY_PHY54XX_LED_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 263 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 264 (_val), (_mask)) 265 266 /* Auto Power-Down Register (Addr 1ch shadow 01010) */ 267 268 /* Master/Slave Seed Register (Addr 1dh) */ 269 270 /* HCD Status Register (Addr 1dh) */ 271 272 /* Test Register 1 (Addr 1eh) */ 273 #define READ_PHY54XX_TEST1r(_unit, _phy_ctrl, _val) \ 274 PHY54XX_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 275 #define WRITE_PHY54XX_TEST1r(_unit, _phy_ctrl, _val) \ 276 PHY54XX_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 277 #define MODIFY_PHY54XX_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 278 PHY54XX_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 279 (_val), (_mask)) 280 281 #endif /* _PHY54XX_H_ */