phy54880.h (43918B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy54880.h 8 * 9 * This driver applies to both BCM54880 and BCM54880S. 10 * Both parts support driving Copper or SERDES interfaces. 11 * 12 * The BCM54880S also has a SERDES pass-through mode, making it possible 13 * to auto-select copper or fiber based on signal detects. 14 */ 15 16 #ifndef _PHY54880_H_ 17 #define _PHY54880_H_ 18 19 #include <soc/phy.h> 20 21 /* PHY register access */ 22 #define PHY54880_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHY54880_REG_WRITE(_unit, _phy_ctrl, _flags, \ 26 _reg_bank, _reg_addr, _val) \ 27 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val)) 29 #define PHY54880_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 30 _reg_addr, _val, _mask) \ 31 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 32 (_reg_addr), (_val), (_mask)) 33 34 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 35 #define READ_PHY54880_MII_CTRLr(_unit, _phy_ctrl, _val) \ 36 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 37 #define WRITE_PHY54880_MII_CTRLr(_unit, _phy_ctrl, _val) \ 38 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 39 #define MODIFY_PHY54880_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 40 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 41 (_val), (_mask)) 42 43 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 44 #define READ_PHY54880_MII_STATr(_unit, _phy_ctrl, _val) \ 45 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 46 #define WRITE_PHY54880_MII_STATr(_unit, _phy_ctrl, _val) \ 47 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 48 #define MODIFY_PHY54880_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 49 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 50 (_val), (_mask)) 51 52 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 53 #define READ_PHY54880_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 54 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 55 #define WRITE_PHY54880_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 56 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 57 #define MODIFY_PHY54880_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 58 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 59 (_val), (_mask)) 60 61 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 62 #define READ_PHY54880_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 63 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 64 #define WRITE_PHY54880_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 65 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 66 #define MODIFY_PHY54880_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 67 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 68 (_val), (_mask)) 69 70 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 71 #define READ_PHY54880_MII_ANAr(_unit, _phy_ctrl, _val) \ 72 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 73 #define WRITE_PHY54880_MII_ANAr(_unit, _phy_ctrl, _val) \ 74 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 75 #define MODIFY_PHY54880_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 76 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 77 (_val), (_mask)) 78 79 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 80 #define READ_PHY54880_MII_ANPr(_unit, _phy_ctrl, _val) \ 81 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 82 #define WRITE_PHY54880_MII_ANPr(_unit, _phy_ctrl, _val) \ 83 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 84 #define MODIFY_PHY54880_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 85 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 86 (_val), (_mask)) 87 88 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 89 #define READ_PHY54880_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 90 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 91 #define WRITE_PHY54880_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 92 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 93 #define MODIFY_PHY54880_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 94 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 95 (_val), (_mask)) 96 97 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 98 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 99 100 /* 1000BASE-T Control Register (ADDR 09h) */ 101 #define READ_PHY54880_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 102 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 103 #define WRITE_PHY54880_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 104 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 105 #define MODIFY_PHY54880_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 106 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 107 (_val), (_mask)) 108 109 /* 1000BASE-T Status Register (ADDR 0ah) */ 110 #define READ_PHY54880_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 111 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 112 #define WRITE_PHY54880_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 113 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 114 #define MODIFY_PHY54880_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 115 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 116 (_val), (_mask)) 117 118 /* (Addr 0ch-0eh) Reserved (Do not read/write to reserved registers. */ 119 120 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 121 122 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 123 #define READ_PHY54880_MII_ECRr(_unit, _phy_ctrl, _val) \ 124 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 125 #define WRITE_PHY54880_MII_ECRr(_unit, _phy_ctrl, _val) \ 126 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 127 #define MODIFY_PHY54880_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 128 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 129 (_val), (_mask)) 130 131 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 132 #define READ_PHY54880_MII_ESRr(_unit, _phy_ctrl, _val) \ 133 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 134 #define WRITE_PHY54880_MII_ESRr(_unit, _phy_ctrl, _val) \ 135 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 136 #define MODIFY_PHY54880_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 137 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 138 (_val), (_mask)) 139 140 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 141 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 142 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 143 144 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 145 #define READ_PHY54880_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 146 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 147 #define WRITE_PHY54880_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 148 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 149 #define MODIFY_PHY54880_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 150 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 151 (_val), (_mask)) 152 153 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 154 #define READ_PHY54880_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 155 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 156 #define WRITE_PHY54880_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 157 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 158 #define MODIFY_PHY54880_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 159 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 160 (_val), (_mask)) 161 162 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 163 #define READ_PHY54880_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 164 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 165 #define WRITE_PHY54880_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 166 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 167 #define MODIFY_PHY54880_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 168 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 169 (_val), (_mask)) 170 171 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 172 #define READ_PHY54880_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 173 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 174 #define WRITE_PHY54880_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 175 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 176 #define MODIFY_PHY54880_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 177 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 178 (_val), (_mask)) 179 180 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 181 #define READ_PHY54880_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 182 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 183 #define WRITE_PHY54880_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 184 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 185 #define MODIFY_PHY54880_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 186 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 187 (_val), (_mask)) 188 189 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 190 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 191 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 192 193 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 194 #define READ_PHY54880_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 195 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 196 #define WRITE_PHY54880_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 197 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 198 #define MODIFY_PHY54880_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 199 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 200 (_val), (_mask)) 201 202 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 203 #define READ_PHY54880_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 204 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 205 #define WRITE_PHY54880_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 206 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 207 #define MODIFY_PHY54880_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 208 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 209 (_val), (_mask)) 210 211 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 212 #define READ_PHY54880_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 213 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 214 #define WRITE_PHY54880_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 215 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 216 #define MODIFY_PHY54880_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 217 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 218 (_val), (_mask)) 219 220 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 221 #define READ_PHY54880_LED_STATr(_unit, _phy_ctrl, _val) \ 222 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 223 #define WRITE_PHY54880_LED_STATr(_unit, _phy_ctrl, _val) \ 224 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 225 #define MODIFY_PHY54880_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 226 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 227 (_val), (_mask)) 228 229 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 230 #define READ_PHY54880_LED_CTRLr(_unit, _phy_ctrl, _val) \ 231 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 232 #define WRITE_PHY54880_LED_CTRLr(_unit, _phy_ctrl, _val) \ 233 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 234 #define MODIFY_PHY54880_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 235 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 236 (_val), (_mask)) 237 238 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 239 #define READ_PHY54880_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 240 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 241 #define WRITE_PHY54880_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 242 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 243 #define MODIFY_PHY54880_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 244 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 245 (_val), (_mask)) 246 247 #define PHY_54880_AUTO_PWRDWN_EN (1 << 5) 248 #define PHY_54880_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 249 #define PHY_54880_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 250 #define PHY_54880_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 251 #define PHY_54880_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 252 #define PHY_54880_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 253 254 /* SLED_1 Reg (ADDR 1ch shadow 01011) */ 255 #define READ_PHY54880_SLED_1r(_unit, _phy_ctrl, _val) \ 256 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, (_val)) 257 #define WRITE_PHY54880_SLED_1r(_unit, _phy_ctrl, _val) \ 258 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, (_val)) 259 #define MODIFY_PHY54880_SLED_1r(_unit, _phy_ctrl, _val, _mask) \ 260 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, \ 261 (_val), (_mask)) 262 263 /* SLED_2 Reg (ADDR 1ch shadow 01100) */ 264 #define READ_PHY54880_SLED_2r(_unit, _phy_ctrl, _val) \ 265 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, (_val)) 266 #define WRITE_PHY54880_SLED_2r(_unit, _phy_ctrl, _val) \ 267 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, (_val)) 268 #define MODIFY_PHY54880_SLED_2r(_unit, _phy_ctrl, _val, _mask) \ 269 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, \ 270 (_val), (_mask)) 271 272 273 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 274 #define READ_PHY54880_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 275 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 276 #define WRITE_PHY54880_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 277 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 278 #define MODIFY_PHY54880_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 279 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 280 (_val), (_mask)) 281 282 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 283 #define READ_PHY54880_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 284 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 285 #define WRITE_PHY54880_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 286 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 287 #define MODIFY_PHY54880_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 288 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 289 (_val), (_mask)) 290 291 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 292 #define READ_PHY54880_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 293 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, (_val)) 294 #define WRITE_PHY54880_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 295 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, (_val)) 296 #define MODIFY_PHY54880_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 297 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, \ 298 (_val), (_mask)) 299 300 /* SGMII SLAVE Reg (ADDR 1ch shadow 10101) */ 301 #define READ_PHY54880_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 302 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 303 #define WRITE_PHY54880_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 304 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 305 #define MODIFY_PHY54880_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 306 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, \ 307 (_val), (_mask)) 308 309 /* Misc. 1000BASE-X Control 2 Reg (ADDR 1ch shadow 10110) */ 310 #define READ_PHY54880_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 311 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 312 #define WRITE_PHY54880_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 313 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 314 #define MODIFY_PHY54880_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 315 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 316 (_val), (_mask)) 317 318 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 319 #define READ_PHY54880_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 320 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 321 #define WRITE_PHY54880_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 322 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 323 #define MODIFY_PHY54880_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 324 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 325 (_val), (_mask)) 326 327 /* Auxiliary Control Reg (ADDR 1ch shadow 11011) */ 328 #define READ_PHY54880_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 329 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, (_val)) 330 #define WRITE_PHY54880_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 331 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, (_val)) 332 #define MODIFY_PHY54880_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 333 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, \ 334 (_val), (_mask)) 335 336 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 337 #define READ_PHY54880_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 338 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, (_val)) 339 #define WRITE_PHY54880_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 340 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, (_val)) 341 #define MODIFY_PHY54880_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 342 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, \ 343 (_val), (_mask)) 344 345 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 346 #define READ_PHY54880_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 347 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, (_val)) 348 #define WRITE_PHY54880_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 349 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, (_val)) 350 #define MODIFY_PHY54880_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 351 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, \ 352 (_val), (_mask)) 353 354 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 355 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 356 357 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 358 #define READ_PHY54880_TEST1r(_unit, _phy_ctrl, _val) \ 359 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 360 #define WRITE_PHY54880_TEST1r(_unit, _phy_ctrl, _val) \ 361 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 362 #define MODIFY_PHY54880_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 363 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 364 (_val), (_mask)) 365 366 /* +---------------------+ 367 * | | 368 * | SGMII Registers | 369 * | | 370 * +---------------------+ 371 */ 372 /* SGMII Control Register (Addr 00h) */ 373 #define READ_PHY54880_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 374 PHY54880_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 375 0x0000, 0x00, (_val)) 376 #define WRITE_PHY54880_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 377 PHY54880_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 378 0x0000, 0x00, (_val)) 379 #define MODIFY_PHY54880_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 380 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 381 0x0000, 0x00, (_val), (_mask)) 382 383 /* SGMII Status Register (Addr 01h) */ 384 #define READ_PHY54880_SGMII_STATr(_unit, _phy_ctrl, _val) \ 385 PHY54880_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 386 0x0000, 0x01, (_val)) 387 #define WRITE_PHY54880_SGMII_STATr(_unit, _phy_ctrl, _val) \ 388 PHY54880_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 389 0x0000, 0x01, (_val)) 390 #define MODIFY_PHY54880_SGMII_STATr(_unit, _phy_ctrl, _val, _mask) \ 391 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 392 0x0000, 0x01, (_val), (_mask)) 393 394 /* SGMII Auto-neg Advertise Register (Addr 04h) */ 395 #define READ_PHY54880_SGMII_ANAr(_unit, _phy_ctrl, _val) \ 396 PHY54880_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 397 0x0000, 0x04, (_val)) 398 #define WRITE_PHY54880_SGMII_ANAr(_unit, _phy_ctrl, _val) \ 399 PHY54880_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 400 0x0000, 0x04, (_val)) 401 #define MODIFY_PHY54880_SGMII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 402 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 403 0x0000, 0x04, (_val), (_mask)) 404 405 /* SGMII Auto-neg Link Partner Ability Register (Addr 05h) */ 406 #define READ_PHY54880_SGMII_ANPr(_unit, _phy_ctrl, _val) \ 407 PHY54880_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 408 0x0000, 0x05, (_val)) 409 #define WRITE_PHY54880_SGMII_ANPr(_unit, _phy_ctrl, _val) \ 410 PHY54880_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 411 0x0000, 0x05, (_val)) 412 #define MODIFY_PHY54880_SGMII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 413 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 414 0x0000, 0x05, (_val), (_mask)) 415 416 /* +-------------------------+ 417 * | | 418 * | Expansion Registers | 419 * | | 420 * +-------------------------+ 421 */ 422 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 423 #define READ_PHY54880_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 424 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F00, 0x15, (_val)) 425 #define WRITE_PHY54880_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 426 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F00, \ 427 0x15, (_val)) 428 #define MODIFY_PHY54880_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 429 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F00, \ 430 0x15, (_val), (_mask)) 431 432 /* Multicolor LED Selector Register (Addr 04h) */ 433 #define READ_PHY54880_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 434 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F04, 0x15, (_val)) 435 #define WRITE_PHY54880_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 436 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F04, \ 437 0x15, (_val)) 438 #define MODIFY_PHY54880_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 439 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F04, \ 440 0x15, (_val), (_mask)) 441 442 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 443 #define READ_PHY54880_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 444 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F05, 0x15, (_val)) 445 #define WRITE_PHY54880_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 446 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F05, \ 447 0x15, (_val)) 448 #define MODIFY_PHY54880_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 449 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F05, \ 450 0x15, (_val), (_mask)) 451 452 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 453 #define READ_PHY54880_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 454 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F06, 0x15, (_val)) 455 #define WRITE_PHY54880_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 456 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F06, \ 457 0x15, (_val)) 458 #define MODIFY_PHY54880_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 459 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F06, \ 460 0x15, (_val), (_mask)) 461 462 /* 100Base-FX Far End Fault egister (Addr 07h) */ 463 #define READ_PHY54880_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val) \ 464 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F07, 0x15, (_val)) 465 #define WRITE_PHY54880_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val) \ 466 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F07, \ 467 0x15, (_val)) 468 #define MODIFY_PHY54880_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val, _mask) \ 469 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F07, \ 470 0x15, (_val), (_mask)) 471 472 /* Port Interrupt Status Register (Addr 0bh) */ 473 #define READ_PHY54880_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 474 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F0B, 0x15, (_val)) 475 #define WRITE_PHY54880_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 476 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F0B, \ 477 0x15, (_val)) 478 #define MODIFY_PHY54880_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val, _mask) \ 479 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F0B, \ 480 0x15, (_val), (_mask)) 481 /* Cable Diag Control Register (Addr 10h) */ 482 #define READ_PHY54880_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val) \ 483 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F10, 0x15, (_val)) 484 #define WRITE_PHY54880_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val) \ 485 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F10, \ 486 0x15, (_val)) 487 #define MODIFY_PHY54880_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 488 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F10, \ 489 0x15, (_val), (_mask)) 490 491 /* Cable Diag Result Register (Addr 11h) */ 492 #define READ_PHY54880_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val) \ 493 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F11, 0x15, (_val)) 494 #define WRITE_PHY54880_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val) \ 495 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F11, \ 496 0x15, (_val)) 497 #define MODIFY_PHY54880_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val, _mask) \ 498 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F11, \ 499 0x15, (_val), (_mask)) 500 501 /* Cable Diag Length Register (Addr 12h) */ 502 #define READ_PHY54880_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val) \ 503 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F12, 0x15, (_val)) 504 #define WRITE_PHY54880_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val) \ 505 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F12, \ 506 0x15, (_val)) 507 #define MODIFY_PHY54880_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val, _mask) \ 508 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F12, \ 509 0x15, (_val), (_mask)) 510 511 512 /* Operating Mode Status Register (Addr 42h) */ 513 #define READ_PHY54880_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 514 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F42, 0x15, (_val)) 515 #define WRITE_PHY54880_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 516 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F42, \ 517 0x15, (_val)) 518 #define MODIFY_PHY54880_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val, _mask) \ 519 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F42, \ 520 0x15, (_val), (_mask)) 521 522 /* SerDes/SGMII Control Register (Addr 52h) */ 523 #define READ_PHY54880_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 524 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 525 #define WRITE_PHY54880_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 526 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 527 #define MODIFY_PHY54880_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 528 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, \ 529 (_val), (_mask)) 530 531 /* BroadR-Reach LRE */ 532 533 /* LRE Control Register (Addr 00h) */ 534 #define READ_PHY54880_LRE_CTRLr(_unit, _phy_ctrl, _val) \ 535 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 536 #define WRITE_PHY54880_LRE_CTRLr(_unit, _phy_ctrl, _val) \ 537 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 538 #define MODIFY_PHY54880_LRE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 539 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 540 (_val), (_mask)) 541 542 /* LRE Status Register (ADDR 01h) */ 543 #define READ_PHY54880_LRE_STATr(_unit, _phy_ctrl, _val) \ 544 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 545 #define WRITE_PHY54880_LRE_STATr(_unit, _phy_ctrl, _val) \ 546 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 547 #define MODIFY_PHY54880_LRE_STATr(_unit, _phy_ctrl, _val, _mask) \ 548 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 549 (_val), (_mask)) 550 551 /* LRE PHY Identifier Register (ADDR 02h) */ 552 #define READ_PHY54880_LRE_PHY_ID0r(_unit, _phy_ctrl, _val) \ 553 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 554 #define WRITE_PHY54880_LRE_PHY_ID0r(_unit, _phy_ctrl, _val) \ 555 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 556 #define MODIFY_PHY54880_LRE_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 557 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 558 (_val), (_mask)) 559 560 /* LRE PHY Identifier Register (ADDR 03h) */ 561 #define READ_PHY54880_LRE_PHY_ID1r(_unit, _phy_ctrl, _val) \ 562 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 563 #define WRITE_PHY54880_LRE_PHY_ID1r(_unit, _phy_ctrl, _val) \ 564 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 565 #define MODIFY_PHY54880_LRE_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 566 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 567 (_val), (_mask)) 568 569 /* LDS Advertised Ability Register (ADDR 04h) */ 570 #define READ_PHY54880_LDS_ADVAr(_unit, _phy_ctrl, _val) \ 571 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 572 #define WRITE_PHY54880_LDS_ADVAr(_unit, _phy_ctrl, _val) \ 573 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 574 #define MODIFY_PHY54880_LDS_ADVAr(_unit, _phy_ctrl, _val, _mask) \ 575 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 576 (_val), (_mask)) 577 578 /* LDS Advertised Control Register (ADDR 05h) */ 579 #define READ_PHY54880_LDS_ADVCr(_unit, _phy_ctrl, _val) \ 580 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 581 #define WRITE_PHY54880_LDS_ADVCr(_unit, _phy_ctrl, _val) \ 582 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 583 #define MODIFY_PHY54880_LDS_ADVCr(_unit, _phy_ctrl, _val, _mask) \ 584 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 585 (_val), (_mask)) 586 587 /* LDS Ability Next Page Register (ADDR 06h) */ 588 #define READ_PHY54880_LDS_ABNPr(_unit, _phy_ctrl, _val) \ 589 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 590 #define WRITE_PHY54880_LDS_ABNPr(_unit, _phy_ctrl, _val) \ 591 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 592 #define MODIFY_PHY54880_LDS_ABNPr(_unit, _phy_ctrl, _val, _mask) \ 593 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 594 (_val), (_mask)) 595 596 /* LDS Link Partner Ability Register (ADDR 07h) */ 597 #define READ_PHY54880_LDS_LPABr(_unit, _phy_ctrl, _val) \ 598 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x07, (_val)) 599 #define WRITE_PHY54880_LDS_LPABr(_unit, _phy_ctrl, _val) \ 600 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x07, (_val)) 601 #define MODIFY_PHY54880_LDS_LPABr(_unit, _phy_ctrl, _val, _mask) \ 602 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x07, \ 603 (_val), (_mask)) 604 605 /* LDS Link Partner Next Page Message Register (ADDR 08h) */ 606 #define READ_PHY54880_LDS_LPNPMr(_unit, _phy_ctrl, _val) \ 607 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x08, (_val)) 608 #define WRITE_PHY54880_LDS_LPNPMr(_unit, _phy_ctrl, _val) \ 609 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x08, (_val)) 610 #define MODIFY_PHY54880_LDS_LPNPMr(_unit, _phy_ctrl, _val, _mask) \ 611 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x08, \ 612 (_val), (_mask)) 613 614 /* LDS Ability Next Page Register (ADDR 09h) */ 615 #define READ_PHY54880_LDS_LPABNPr(_unit, _phy_ctrl, _val) \ 616 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 617 #define WRITE_PHY54880_LDS_LPABNPr(_unit, _phy_ctrl, _val) \ 618 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 619 #define MODIFY_PHY54880_LDS_LPABNPr(_unit, _phy_ctrl, _val, _mask) \ 620 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 621 (_val), (_mask)) 622 623 /* LDS Expansion Register (ADDR 0ah) */ 624 #define READ_PHY54880_LDS_EXPr(_unit, _phy_ctrl, _val) \ 625 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 626 #define WRITE_PHY54880_LDS_EXPr(_unit, _phy_ctrl, _val) \ 627 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 628 #define MODIFY_PHY54880_LDS_EXPr(_unit, _phy_ctrl, _val, _mask) \ 629 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 630 (_val), (_mask)) 631 632 /* LDS Access Register (ADDR 0eh) */ 633 #define READ_PHY54880_LDS_ACCr(_unit, _phy_ctrl, _val) \ 634 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0e, (_val)) 635 #define WRITE_PHY54880_LDS_ACCr(_unit, _phy_ctrl, _val) \ 636 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0e, (_val)) 637 #define MODIFY_PHY54880_LDS_ACCr(_unit, _phy_ctrl, _val, _mask) \ 638 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0e, \ 639 (_val), (_mask)) 640 641 /* LRE Extended Status Register (ADDR 0fh) */ 642 #define READ_PHY54880_LRE_EXTEN_STATr(_unit, _phy_ctrl, _val) \ 643 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0f, (_val)) 644 #define WRITE_PHY54880_LRE_EXTEN_STATr(_unit, _phy_ctrl, _val) \ 645 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0f, (_val)) 646 #define MODIFY_PHY54880_LRE_EXTEN_STATr(_unit, _phy_ctrl, _val, _mask) \ 647 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0f, \ 648 (_val), (_mask)) 649 650 /* BroadR-Reach LRE Misc Control Register1 (Addr 90h) */ 651 #define READ_PHY54880_EXP_BR_LRE_MISC_CTRL1r(_unit, _phy_ctrl, _val) \ 652 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f90, 0x15, (_val)) 653 #define WRITE_PHY54880_EXP_BR_LRE_MISC_CTRL1r(_unit, _phy_ctrl, _val) \ 654 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f90, 0x15, (_val)) 655 #define MODIFY_PHY54880_EXP_BR_LRE_MISC_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 656 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f90, 0x15, \ 657 (_val), (_mask)) 658 659 /* BroadR-Reach LRE Misc Control Register2 (Addr 91h) */ 660 #define READ_PHY54880_EXP_BR_LRE_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 661 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f91, 0x15, (_val)) 662 #define WRITE_PHY54880_EXP_BR_LRE_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 663 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f91, 0x15, (_val)) 664 #define MODIFY_PHY54880_EXP_BR_LRE_MISC_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 665 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f91, 0x15, \ 666 (_val), (_mask)) 667 668 /* BroadR-Reach LRE Misc Control Register3 (Addr 92h) */ 669 #define READ_PHY54880_EXP_BR_LRE_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 670 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f92, 0x15, (_val)) 671 #define WRITE_PHY54880_EXP_BR_LRE_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 672 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f92, 0x15, (_val)) 673 #define MODIFY_PHY54880_EXP_BR_LRE_MISC_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 674 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f92, 0x15, \ 675 (_val), (_mask)) 676 677 /* BroadR-Reach LDS Control Register (Addr 93h) */ 678 #define READ_PHY54880_EXP_BR_LDS_CTRLr(_unit, _phy_ctrl, _val) \ 679 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f93, 0x15, (_val)) 680 #define WRITE_PHY54880_EXP_BR_LDS_CTRLr(_unit, _phy_ctrl, _val) \ 681 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f93, 0x15, (_val)) 682 #define MODIFY_PHY54880_EXP_BR_LDS_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 683 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f93, 0x15, \ 684 (_val), (_mask)) 685 686 /* BroadR-Reach LDS RX Control Register1 (Addr 94h) */ 687 #define READ_PHY54880_EXP_BR_LDS_RX_CTRL1r(_unit, _phy_ctrl, _val) \ 688 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f94, 0x15, (_val)) 689 #define WRITE_PHY54880_EXP_BR_LDS_RX_CTRL1r(_unit, _phy_ctrl, _val) \ 690 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f94, 0x15, (_val)) 691 #define MODIFY_PHY54880_EXP_BR_LDS_RX_CTRL1r(_unit, _phy_ctrl, _val, _mask) \ 692 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f94, 0x15, \ 693 (_val), (_mask)) 694 695 /* BroadR-Reach LDS Scan Register (Addr 96h) */ 696 #define READ_PHY54880_EXP_BR_LDS_SCANr(_unit, _phy_ctrl, _val) \ 697 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f96, 0x15, (_val)) 698 #define WRITE_PHY54880_EXP_BR_LDS_SCANr(_unit, _phy_ctrl, _val) \ 699 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f96, 0x15, (_val)) 700 #define MODIFY_PHY54880_EXP_BR_LDS_SCANr(_unit, _phy_ctrl, _val, _mask) \ 701 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f96, 0x15, \ 702 (_val), (_mask)) 703 704 #define PHY54880_EXP_BR_LDS_SCAN_SS_MASK 0xf /* Speed Selection Mask */ 705 #define PHY54880_EXP_BR_LDS_SCAN_SS_10 0x0 /* 10Mbps */ 706 #define PHY54880_EXP_BR_LDS_SCAN_SS_50 0x1 /* 50Mbps */ 707 #define PHY54880_EXP_BR_LDS_SCAN_SS_33 0x2 /* 33Mbps */ 708 #define PHY54880_EXP_BR_LDS_SCAN_SS_25 0x3 /* 25Mbps */ 709 #define PHY54880_EXP_BR_LDS_SCAN_SS_20 0x4 /* 20Mbps */ 710 #define PHY54880_EXP_BR_LDS_SCAN_SS_100 0x8 /* 100Mbps */ 711 712 /* BroadR-Reach LDS RX Control Register2 (Addr 9fh) */ 713 #define READ_PHY54880_EXP_BR_LDS_RX_CTRL2r(_unit, _phy_ctrl, _val) \ 714 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f9f, 0x15, (_val)) 715 #define WRITE_PHY54880_EXP_BR_LDS_RX_CTRL2r(_unit, _phy_ctrl, _val) \ 716 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f9f, 0x15, (_val)) 717 #define MODIFY_PHY54880_EXP_BR_LDS_RX_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 718 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f9f, 0x15, \ 719 (_val), (_mask)) 720 721 722 723 724 /* 725 * 726 * BCM54811 specific regs 727 */ 728 729 730 /* BroadR-Reach LRE Misc Control (Addr 90h) */ 731 #define READ_PHY54811_EXP_BR_LRE_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 732 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f90, 0x15, (_val)) 733 #define WRITE_PHY54811_EXP_BR_LRE_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 734 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f90, 0x15, (_val)) 735 #define MODIFY_PHY54811_EXP_BR_LRE_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 736 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f90, 0x15, \ 737 (_val), (_mask)) 738 739 740 /* BroadR-Reach LDS Misc Control 2 (Addr 91h) */ 741 #define READ_PHY54811_EXP_BR_LRE_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 742 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f91, 0x15, (_val)) 743 #define WRITE_PHY54811_EXP_BR_LRE_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 744 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f91, 0x15, (_val)) 745 #define MODIFY_PHY54811_EXP_BR_LRE_MISC_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 746 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f91, 0x15, \ 747 (_val), (_mask)) 748 749 /* BroadR-Reach LDS Timer Control (Addr 99h) */ 750 #define READ_PHY54811_EXP_BR_LDS_TIMER_CTRLr(_unit, _phy_ctrl, _val) \ 751 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f99, 0x15, (_val)) 752 #define WRITE_PHY54811_EXP_BR_LDS_TIMER_CTRLr(_unit, _phy_ctrl, _val) \ 753 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f99, 0x15, (_val)) 754 #define MODIFY_PHY54811_EXP_BR_LDS_TIMER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 755 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f99, 0x15, \ 756 (_val), (_mask)) 757 758 /* BroadR-Reach LDS Channel Status (Addr 9Ah) */ 759 #define READ_PHY54811_EXP_BR_LDS_CHAN_STATUSr(_unit, _phy_ctrl, _val) \ 760 PHY54880_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f9a, 0x15, (_val)) 761 #define WRITE_PHY54811_EXP_BR_LDS_CHAN_STATUSr(_unit, _phy_ctrl, _val) \ 762 PHY54880_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f9a, 0x15, (_val)) 763 #define MODIFY_PHY54811_EXP_BR_LDS_CHAN_STATUSr(_unit, _phy_ctrl, _val, _mask) \ 764 PHY54880_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f9a, 0x15, \ 765 (_val), (_mask)) 766 #define PHY54811_LDS_BR_IEEE_REG_ACCESS_OVERRIDE_EN (0x8000) 767 #define PHY54811_LDS_BR_IEEE_REG_ACCESS_OVERRIDE_VAL (0x4000) 768 #define PHY54811_LDS_BR_IEEE_REG_ACCESS_CTRL_STATUS (0x2000) 769 770 771 772 #endif /* _PHY54880_H_ */