phy5482.h (47228B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy5482.h 8 * 9 * This driver applies to both BCM5482 and BCM5482S. 10 * Both parts support driving Copper or SERDES interfaces. 11 */ 12 13 #ifndef _PHY5482_H_ 14 #define _PHY5482_H_ 15 16 #include <soc/phy.h> 17 18 /* PHY register access */ 19 #define PHY5482_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 20 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 21 (_reg_addr), (_val)) 22 #define PHY5482_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHY5482_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, \ 26 _val, _mask) \ 27 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val), (_mask)) 29 30 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 31 #define READ_PHY5482_MII_CTRLr(_unit, _phy_ctrl, _val) \ 32 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 33 #define WRITE_PHY5482_MII_CTRLr(_unit, _phy_ctrl, _val) \ 34 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 35 #define MODIFY_PHY5482_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 36 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 37 (_val), (_mask)) 38 39 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 40 #define READ_PHY5482_MII_STATr(_unit, _phy_ctrl, _val) \ 41 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 42 #define WRITE_PHY5482_MII_STATr(_unit, _phy_ctrl, _val) \ 43 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 44 #define MODIFY_PHY5482_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 45 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 46 (_val), (_mask)) 47 48 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 49 #define READ_PHY5482_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 50 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 51 #define WRITE_PHY5482_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 52 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 53 #define MODIFY_PHY5482_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 54 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 55 (_val), (_mask)) 56 57 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 58 #define READ_PHY5482_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 59 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 60 #define WRITE_PHY5482_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 61 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 62 #define MODIFY_PHY5482_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 63 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 64 (_val), (_mask)) 65 66 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 67 #define READ_PHY5482_MII_ANAr(_unit, _phy_ctrl, _val) \ 68 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 69 #define WRITE_PHY5482_MII_ANAr(_unit, _phy_ctrl, _val) \ 70 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 71 #define MODIFY_PHY5482_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 72 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 73 (_val), (_mask)) 74 75 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 76 #define READ_PHY5482_MII_ANPr(_unit, _phy_ctrl, _val) \ 77 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 78 #define WRITE_PHY5482_MII_ANPr(_unit, _phy_ctrl, _val) \ 79 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 80 #define MODIFY_PHY5482_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 81 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 82 (_val), (_mask)) 83 84 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 85 #define READ_PHY5482_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 86 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 87 #define WRITE_PHY5482_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 88 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 89 #define MODIFY_PHY5482_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 90 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 91 (_val), (_mask)) 92 93 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 94 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 95 96 /* 1000BASE-T Control Register (ADDR 09h) */ 97 #define READ_PHY5482_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 98 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 99 #define WRITE_PHY5482_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 100 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 101 #define MODIFY_PHY5482_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 102 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 103 (_val), (_mask)) 104 105 /* 1000BASE-T Status Register (ADDR 0ah) */ 106 #define READ_PHY5482_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 107 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 108 #define WRITE_PHY5482_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 109 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 110 #define MODIFY_PHY5482_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 111 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 112 (_val), (_mask)) 113 114 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 115 116 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 117 #define READ_PHY5482_MII_ECRr(_unit, _phy_ctrl, _val) \ 118 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 119 #define WRITE_PHY5482_MII_ECRr(_unit, _phy_ctrl, _val) \ 120 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 121 #define MODIFY_PHY5482_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 122 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 123 (_val), (_mask)) 124 125 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 126 #define READ_PHY5482_MII_ESRr(_unit, _phy_ctrl, _val) \ 127 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 128 #define WRITE_PHY5482_MII_ESRr(_unit, _phy_ctrl, _val) \ 129 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 130 #define MODIFY_PHY5482_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 131 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 132 (_val), (_mask)) 133 134 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 135 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 136 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 137 138 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 139 #define READ_PHY5482_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 140 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 141 #define WRITE_PHY5482_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 142 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 143 #define MODIFY_PHY5482_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 144 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 145 (_val), (_mask)) 146 147 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 148 #define READ_PHY5482_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 149 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 150 #define WRITE_PHY5482_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 151 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 152 #define MODIFY_PHY5482_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 153 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 154 (_val), (_mask)) 155 156 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 157 #define READ_PHY5482_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 158 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 159 #define WRITE_PHY5482_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 160 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 161 #define MODIFY_PHY5482_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 162 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 163 (_val), (_mask)) 164 165 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 166 #define READ_PHY5482_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 167 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 168 #define WRITE_PHY5482_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 169 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 170 #define MODIFY_PHY5482_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 171 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 172 (_val), (_mask)) 173 174 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 175 #define READ_PHY5482_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 176 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 177 #define WRITE_PHY5482_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 178 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 179 #define MODIFY_PHY5482_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 180 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 181 (_val), (_mask)) 182 183 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 184 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 185 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 186 187 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 188 #define READ_PHY5482_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 189 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 190 #define WRITE_PHY5482_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 191 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 192 #define MODIFY_PHY5482_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 193 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 194 (_val), (_mask)) 195 196 /* 1000BASE-T/100BASE-TX/10BASE-T Clk Alignment Ctrl (ADDR 1ch shadow 00011) */ 197 #define READ_PHY5482_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 198 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 199 #define WRITE_PHY5482_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 200 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 201 #define MODIFY_PHY5482_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 202 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, \ 203 (_val), (_mask)) 204 205 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 206 #define READ_PHY5482_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 207 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 208 #define WRITE_PHY5482_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 209 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 210 #define MODIFY_PHY5482_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 211 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 212 (_val), (_mask)) 213 214 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 215 #define READ_PHY5482_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 216 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 217 #define WRITE_PHY5482_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 218 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 219 #define MODIFY_PHY5482_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 220 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 221 (_val), (_mask)) 222 223 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 224 #define READ_PHY5482_LED_STATr(_unit, _phy_ctrl, _val) \ 225 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 226 #define WRITE_PHY5482_LED_STATr(_unit, _phy_ctrl, _val) \ 227 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 228 #define MODIFY_PHY5482_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 229 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 230 (_val), (_mask)) 231 232 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 233 #define READ_PHY5482_LED_CTRLr(_unit, _phy_ctrl, _val) \ 234 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 235 #define WRITE_PHY5482_LED_CTRLr(_unit, _phy_ctrl, _val) \ 236 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 237 #define MODIFY_PHY5482_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 238 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 239 (_val), (_mask)) 240 241 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 242 #define READ_PHY5482_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 243 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 244 #define WRITE_PHY5482_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 245 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 246 #define MODIFY_PHY5482_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 247 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 248 (_val), (_mask)) 249 250 #define PHY_5482_AUTO_PWRDWN_EN (1 << 5) 251 #define PHY_5482_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 252 #define PHY_5482_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 253 #define PHY_5482_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 254 #define PHY_5482_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 255 #define PHY_5482_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 256 257 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 258 #define READ_PHY5482_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 259 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 260 #define WRITE_PHY5482_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 261 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 262 #define MODIFY_PHY5482_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 263 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 264 (_val), (_mask)) 265 266 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 267 #define READ_PHY5482_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 268 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 269 #define WRITE_PHY5482_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 270 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 271 #define MODIFY_PHY5482_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 272 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 273 (_val), (_mask)) 274 275 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 276 #define READ_PHY5482_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 277 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 278 #define WRITE_PHY5482_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 279 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 280 #define MODIFY_PHY5482_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 281 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, \ 282 (_val), (_mask)) 283 284 /* SerDes 100BASE-FX Status Reg (ADDR 1ch shadow 10001) */ 285 #define READ_PHY5482_100FX_STATr(_unit, _phy_ctrl, _val) \ 286 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 287 #define WRITE_PHY5482_100FX_STATr(_unit, _phy_ctrl, _val) \ 288 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 289 #define MODIFY_PHY5482_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 290 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, \ 291 (_val), (_mask)) 292 293 /* SerDes 100BASE-FX Control Reg (ADDR 1ch shadow 10011) */ 294 #define READ_PHY5482_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 295 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 296 #define WRITE_PHY5482_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 297 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 298 #define MODIFY_PHY5482_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 299 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, \ 300 (_val), (_mask)) 301 302 /* Secondary SerDes Control Reg (ADDR 1ch shadow 10100) */ 303 #define READ_PHY5482_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 304 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 305 #define WRITE_PHY5482_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 306 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 307 #define MODIFY_PHY5482_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 308 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, \ 309 (_val), (_mask)) 310 311 /* SGMII Slave Reg (ADDR 1ch shadow 10101) */ 312 #define READ_PHY5482_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 313 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 314 #define WRITE_PHY5482_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 315 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 316 #define MODIFY_PHY5482_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 317 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, \ 318 (_val), (_mask)) 319 320 /* Primary SerDes Control Reg (ADDR 1ch shadow 10110) */ 321 #define READ_PHY5482_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 322 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 323 #define WRITE_PHY5482_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 324 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 325 #define MODIFY_PHY5482_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 326 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 327 (_val), (_mask)) 328 329 330 /* Misc 1000X Control 2 Reg (ADDR 1ch shadow 10111) */ 331 #define READ_PHY5482_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 332 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 333 #define WRITE_PHY5482_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 334 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 335 #define MODIFY_PHY5482_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 336 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, \ 337 (_val), (_mask)) 338 339 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 340 #define READ_PHY5482_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 341 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 342 #define WRITE_PHY5482_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 343 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 344 #define MODIFY_PHY5482_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 345 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 346 (_val), (_mask)) 347 348 /* 1000BASE-X Auto-neg Debug Reg (ADDR 1ch shadow 11010) */ 349 #define READ_PHY5482_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 350 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 351 #define WRITE_PHY5482_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 352 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 353 #define MODIFY_PHY5482_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 354 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, \ 355 (_val), (_mask)) 356 357 /* Auxiliary 1000BASE-X Control Reg (ADDR 1ch shadow 11011) */ 358 #define READ_PHY5482_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 359 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 360 #define WRITE_PHY5482_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 361 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 362 #define MODIFY_PHY5482_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 363 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, \ 364 (_val), (_mask)) 365 366 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 367 #define READ_PHY5482_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 368 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 369 #define WRITE_PHY5482_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 370 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 371 #define MODIFY_PHY5482_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 372 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, \ 373 (_val), (_mask)) 374 375 /* Misc 1000BASE-X Status Reg (ADDR 1ch shadow 11101) */ 376 #define READ_PHY5482_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 377 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 378 #define WRITE_PHY5482_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 379 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 380 #define MODIFY_PHY5482_MISC_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 381 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, \ 382 (_val), (_mask)) 383 384 /* Copper/Fiber Auto-Detect Medium Reg (ADDR 1ch shadow 11110) */ 385 #define READ_PHY5482_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 386 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 387 #define WRITE_PHY5482_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 388 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 389 #define MODIFY_PHY5482_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val, _mask) \ 390 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, \ 391 (_val), (_mask)) 392 393 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 394 #define READ_PHY5482_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 395 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 396 #define WRITE_PHY5482_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 397 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 398 #define MODIFY_PHY5482_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 399 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, \ 400 (_val), (_mask)) 401 402 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 403 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 404 405 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 406 #define READ_PHY5482_TEST1r(_unit, _phy_ctrl, _val) \ 407 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 408 #define WRITE_PHY5482_TEST1r(_unit, _phy_ctrl, _val) \ 409 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 410 #define MODIFY_PHY5482_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 411 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 412 (_val), (_mask)) 413 414 415 /* +------------------------------+ 416 * | | 417 * | Primary SerDes Registers | 418 * | | 419 * +------------------------------+ 420 */ 421 /* 1000BASE-X MII Control Register (Addr 00h) */ 422 #define READ_PHY5482_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 423 PHY5482_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 424 0x0000, 0x00, (_val)) 425 #define WRITE_PHY5482_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 426 PHY5482_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 427 0x0000, 0x00, (_val)) 428 #define MODIFY_PHY5482_1000X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 429 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 430 0x0000, 0x00, (_val), (_mask)) 431 432 /* 1000BASE-X MII Status Register (Addr 01h) */ 433 #define READ_PHY5482_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 434 PHY5482_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 435 0x0000, 0x01, (_val)) 436 #define WRITE_PHY5482_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 437 PHY5482_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 438 0x0000, 0x01, (_val)) 439 #define MODIFY_PHY5482_1000X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 440 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 441 0x0000, 0x01, (_val), (_mask)) 442 443 /* 1000BASE-X MII Auto-neg Advertise Register (Addr 04h) */ 444 #define READ_PHY5482_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 445 PHY5482_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 446 0x0000, 0x04, (_val)) 447 #define WRITE_PHY5482_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 448 PHY5482_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 449 0x0000, 0x04, (_val)) 450 #define MODIFY_PHY5482_1000X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 451 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 452 0x0000, 0x04, (_val), (_mask)) 453 454 /* 1000BASE-X MII Auto-neg Link Partner Ability Register (Addr 05h) */ 455 #define READ_PHY5482_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 456 PHY5482_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 457 0x0000, 0x05, (_val)) 458 #define WRITE_PHY5482_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 459 PHY5482_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 460 0x0000, 0x05, (_val)) 461 #define MODIFY_PHY5482_1000X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 462 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 463 0x0000, 0x05, (_val), (_mask)) 464 465 /* 1000BASE-X MII Auto-neg Extended Status Register (Addr 06h) */ 466 #define READ_PHY5482_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 467 PHY5482_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 468 0x0000, 0x06, (_val)) 469 #define WRITE_PHY5482_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 470 PHY5482_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 471 0x0000, 0x06, (_val)) 472 #define MODIFY_PHY5482_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 473 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 474 0x0000, 0x06, (_val), (_mask)) 475 476 /* 1000BASE-X MII IEEE Extended Status Register (Addr 0fh) */ 477 #define READ_PHY5482_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 478 PHY5482_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 479 0x0000, 0x0f, (_val)) 480 #define WRITE_PHY5482_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 481 PHY5482_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 482 0x0000, 0x0f, (_val)) 483 #define MODIFY_PHY5482_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 484 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 485 0x0000, 0x0f, (_val), (_mask)) 486 487 /* +-------------------------+ 488 * | | 489 * | Expansion Registers | 490 * | | 491 * +-------------------------+ 492 */ 493 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 494 #define READ_PHY5482_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 495 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 496 #define WRITE_PHY5482_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 497 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 498 #define MODIFY_PHY5482_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 499 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, \ 500 (_val), (_mask)) 501 502 /* Expansion Interrupt Status Register (Addr 01h) */ 503 #define READ_PHY5482_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 504 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 505 #define WRITE_PHY5482_EXP_r(_unit, _phy_ctrl, _val) \ 506 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 507 #define MODIFY_PHY5482_EXP_r(_unit, _phy_ctrl, _val, _mask) \ 508 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, \ 509 (_val), (_mask)) 510 511 /* Expansion Interrupt Mask Register (Addr 02h) */ 512 #define READ_PHY5482_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 513 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 514 #define WRITE_PHY5482_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 515 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 516 #define MODIFY_PHY5482_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 517 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, \ 518 (_val), (_mask)) 519 520 /* Multicolor LED Selector Register (Addr 04h) */ 521 #define READ_PHY5482_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 522 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 523 #define WRITE_PHY5482_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 524 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 525 #define MODIFY_PHY5482_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 526 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, \ 527 (_val), (_mask)) 528 529 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 530 #define READ_PHY5482_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 531 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 532 #define WRITE_PHY5482_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 533 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 534 #define MODIFY_PHY5482_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 535 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, \ 536 (_val), (_mask)) 537 538 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 539 #define READ_PHY5482_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 540 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 541 #define WRITE_PHY5482_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 542 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 543 #define MODIFY_PHY5482_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 544 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f, 0x15, \ 545 0x06, (_val), (_mask)) 546 547 /* Operating Mode Status Register (Addr 42h) */ 548 #define READ_PHY5482_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 549 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 550 #define WRITE_PHY5482_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 551 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 552 #define MODIFY_PHY5482_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val, _mask) \ 553 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, \ 554 (_val), (_mask)) 555 556 /* Operating Mode Status Register (Addr 44h) */ 557 #define READ_PHY5482_EXP_SGMII_REC_CTRLr(_unit, _phy_ctrl, _val) \ 558 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, (_val)) 559 #define WRITE_PHY5482_EXP_SGMII_REC_CTRLr(_unit, _phy_ctrl, _val) \ 560 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, (_val)) 561 #define MODIFY_PHY5482_EXP_SGMII_REC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 562 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, \ 563 (_val), (_mask)) 564 565 /* SerDes/SGMII Control Register (Addr 52h) */ 566 #define READ_PHY5482_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 567 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 568 #define WRITE_PHY5482_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 569 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 570 #define MODIFY_PHY5482_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 571 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, \ 572 (_val), (_mask)) 573 574 /* +--------------------------------+ 575 * | | 576 * | Secondary SerDes Registers | 577 * | | 578 * +--------------------------------+ 579 */ 580 /* 1000BASE-X Control Register (Addr 00h) */ 581 #define READ_PHY5482_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 582 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, (_val)) 583 #define WRITE_PHY5482_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 584 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, (_val)) 585 #define MODIFY_PHY5482_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 586 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, \ 587 (_val), (_mask)) 588 589 /* 1000BASE-X Status Register (Addr 01h) */ 590 #define READ_PHY5482_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val) \ 591 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, (_val)) 592 #define WRITE_PHY5482_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val) \ 593 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, (_val)) 594 #define MODIFY_PHY5482_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 595 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, \ 596 (_val), (_mask)) 597 598 /* Auto-neg Advertise Register (Addr 04h) */ 599 #define READ_PHY5482_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val) \ 600 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, (_val)) 601 #define WRITE_PHY5482_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val) \ 602 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, (_val)) 603 #define MODIFY_PHY5482_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val, _mask) \ 604 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, \ 605 (_val), (_mask)) 606 607 /* 1000BASE-X Auto-neg Link Partner Ability Register (Addr 05h) */ 608 #define READ_PHY5482_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val) \ 609 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, (_val)) 610 #define WRITE_PHY5482_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val) \ 611 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, (_val)) 612 #define MODIFY_PHY5482_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val, _mask) \ 613 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, \ 614 (_val), (_mask)) 615 616 /* 1000BASE-X Auto-neg Secondary SerDes Register (Addr 06h) */ 617 #define READ_PHY5482_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val) \ 618 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, (_val)) 619 #define WRITE_PHY5482_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val) \ 620 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, (_val)) 621 #define MODIFY_PHY5482_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 622 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, \ 623 (_val), (_mask)) 624 625 /* 1000BASE-X Auto-neg Next Page Transmit Register (Addr 07h) */ 626 #define READ_PHY5482_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 627 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, (_val)) 628 #define WRITE_PHY5482_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 629 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, (_val)) 630 #define MODIFY_PHY5482_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val, _mask) \ 631 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, \ 632 (_val), (_mask)) 633 634 /* 1000BASE-X Auto-neg Link Partner Next Page Register (Addr 08h) */ 635 #define READ_PHY5482_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 636 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, (_val)) 637 #define WRITE_PHY5482_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 638 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, (_val)) 639 #define MODIFY_PHY5482_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val, _mask) \ 640 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, \ 641 (_val), (_mask)) 642 643 /* 1000BASE-X Extended Status Register (Addr 0fh) */ 644 #define READ_PHY5482_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val) \ 645 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, (_val)) 646 #define WRITE_PHY5482_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val) \ 647 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, (_val)) 648 #define MODIFY_PHY5482_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 649 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, \ 650 (_val), (_mask)) 651 652 /* Misc 1 Register (Addr 10h) */ 653 #define READ_PHY5482_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val) \ 654 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, (_val)) 655 #define WRITE_PHY5482_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val) \ 656 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, (_val)) 657 #define MODIFY_PHY5482_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 658 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, \ 659 (_val), (_mask)) 660 661 /* 100BASE-FX Status Register (Addr 11h) */ 662 #define READ_PHY5482_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val) \ 663 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, (_val)) 664 #define WRITE_PHY5482_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val) \ 665 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, (_val)) 666 #define MODIFY_PHY5482_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 667 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, \ 668 (_val), (_mask)) 669 670 /* 100BASE-FX Test Register (Addr 12h) */ 671 #define READ_PHY5482_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val) \ 672 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, (_val)) 673 #define WRITE_PHY5482_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val) \ 674 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, (_val)) 675 #define MODIFY_PHY5482_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val, _mask) \ 676 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, \ 677 (_val), (_mask)) 678 679 /* Packet Counter Register (Addr 13h) */ 680 #define READ_PHY5482_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val) \ 681 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, (_val)) 682 #define WRITE_PHY5482_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val) \ 683 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, (_val)) 684 #define MODIFY_PHY5482_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 685 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, \ 686 (_val), (_mask)) 687 688 /* Error Counter Register (Addr 14h) */ 689 #define READ_PHY5482_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 690 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, (_val)) 691 #define WRITE_PHY5482_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 692 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, (_val)) 693 #define MODIFY_PHY5482_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 694 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, \ 695 (_val), (_mask)) 696 697 /* SGMII Slave Register (Addr 15h) */ 698 #define READ_PHY5482_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 699 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, (_val)) 700 #define WRITE_PHY5482_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 701 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, (_val)) 702 #define MODIFY_PHY5482_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 703 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, \ 704 (_val), (_mask)) 705 706 /* Secondary SerDes Control Register (Addr 16h) */ 707 #define READ_PHY5482_EXP_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 708 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, (_val)) 709 #define WRITE_PHY5482_EXP_2ND_SERDES_CTRL_SLAVEr(_unit, _phy_ctrl, _val) \ 710 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, (_val)) 711 #define MODIFY_PHY5482_EXP_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 712 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, \ 713 (_val), (_mask)) 714 715 /* Misc 1000BASE-X Control 2 Register (Addr 17h) */ 716 #define READ_PHY5482_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 717 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, (_val)) 718 #define WRITE_PHY5482_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 719 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, (_val)) 720 #define MODIFY_PHY5482_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 721 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, \ 722 (_val), (_mask)) 723 724 /* Misc 1000BASE-X Control 3 Register (Addr 18h) */ 725 #define READ_PHY5482_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 726 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, (_val)) 727 #define WRITE_PHY5482_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 728 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, (_val)) 729 #define MODIFY_PHY5482_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 730 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, \ 731 (_val), (_mask)) 732 733 /* Auto-neg 1000BASE-X Debug Register (Addr 1ah) */ 734 #define READ_PHY5482_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 735 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, (_val)) 736 #define WRITE_PHY5482_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 737 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, (_val)) 738 #define MODIFY_PHY5482_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 739 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, \ 740 (_val), (_mask)) 741 742 /* Secondary SerDes Auxiliary 1000BASE-X Control Register (Addr 1bh) */ 743 #define READ_PHY5482_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 744 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, (_val)) 745 #define WRITE_PHY5482_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 746 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, (_val)) 747 #define MODIFY_PHY5482_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 748 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, \ 749 (_val), (_mask)) 750 751 /* Auxilary 1000BASE-X Status Register (Addr 1ch) */ 752 #define READ_PHY5482_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val) \ 753 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, (_val)) 754 #define WRITE_PHY5482_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val) \ 755 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, (_val)) 756 #define MODIFY_PHY5482_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val, _mask) \ 757 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, \ 758 (_val), (_mask)) 759 760 /* Misc 1000BASE-X Status Register (Addr 1dh) */ 761 #define READ_PHY5482_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val) \ 762 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, (_val)) 763 #define WRITE_PHY5482_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val) \ 764 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, (_val)) 765 #define MODIFY_PHY5482_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val, _mask) \ 766 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, \ 767 (_val), (_mask)) 768 769 /* Spare Register (Addr 21h) */ 770 #define READ_PHY5482_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val) \ 771 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, (_val)) 772 #define WRITE_PHY5482_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val) \ 773 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, (_val)) 774 #define MODIFY_PHY5482_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val, _mask) \ 775 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, \ 776 (_val), (_mask)) 777 778 /* Secondary SerDes Interrupt Status Register (Addr 30h) */ 779 #define READ_PHY5482_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 780 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, (_val)) 781 #define WRITE_PHY5482_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 782 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, (_val)) 783 #define MODIFY_PHY5482_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val, _mask) \ 784 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, \ 785 (_val), (_mask)) 786 787 /* Secondary SerDes Interrupt Mask Register (Addr 31h) */ 788 #define READ_PHY5482_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 789 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, (_val)) 790 #define WRITE_PHY5482_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 791 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, (_val)) 792 #define MODIFY_PHY5482_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 793 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, \ 794 (_val), (_mask)) 795 796 /* Secondary SerDes Lineside Loopback Control Register (Addr 44h) */ 797 #define READ_PHY5482_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val) \ 798 PHY5482_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, (_val)) 799 #define WRITE_PHY5482_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val) \ 800 PHY5482_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, (_val)) 801 #define MODIFY_PHY5482_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 802 PHY5482_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, \ 803 (_val), (_mask)) 804 805 /* 100FX full-duplex bit */ 806 #define PHY_5482_2ND_SERDES_100FX_FD (1 << 5) 807 #define PHY_5482_PRIMARY_SERDES_100FX_FD (1 << 1) 808 #endif /* _PHY5482_H_ */