phy54684.h (48108B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy54684.h 8 * 9 * This driver applies to BCM54684. 10 * It support driving Copper or SERDES interfaces. 11 */ 12 13 #ifndef _PHY54684_H_ 14 #define _PHY54684_H_ 15 16 #include <soc/phy.h> 17 18 /* PHY register access */ 19 #define PHY54684_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 20 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 21 (_reg_addr), (_val)) 22 #define PHY54684_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHY54684_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, \ 26 _val, _mask) \ 27 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val), (_mask)) 29 30 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 31 #define READ_PHY54684_MII_CTRLr(_unit, _phy_ctrl, _val) \ 32 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 33 #define WRITE_PHY54684_MII_CTRLr(_unit, _phy_ctrl, _val) \ 34 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 35 #define MODIFY_PHY54684_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 36 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 37 (_val), (_mask)) 38 39 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 40 #define READ_PHY54684_MII_STATr(_unit, _phy_ctrl, _val) \ 41 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 42 #define WRITE_PHY54684_MII_STATr(_unit, _phy_ctrl, _val) \ 43 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 44 #define MODIFY_PHY54684_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 45 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 46 (_val), (_mask)) 47 48 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 49 #define READ_PHY54684_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 50 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 51 #define WRITE_PHY54684_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 52 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 53 #define MODIFY_PHY54684_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 54 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 55 (_val), (_mask)) 56 57 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 58 #define READ_PHY54684_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 59 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 60 #define WRITE_PHY54684_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 61 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 62 #define MODIFY_PHY54684_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 63 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 64 (_val), (_mask)) 65 66 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 67 #define READ_PHY54684_MII_ANAr(_unit, _phy_ctrl, _val) \ 68 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 69 #define WRITE_PHY54684_MII_ANAr(_unit, _phy_ctrl, _val) \ 70 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 71 #define MODIFY_PHY54684_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 72 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 73 (_val), (_mask)) 74 75 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 76 #define READ_PHY54684_MII_ANPr(_unit, _phy_ctrl, _val) \ 77 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 78 #define WRITE_PHY54684_MII_ANPr(_unit, _phy_ctrl, _val) \ 79 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 80 #define MODIFY_PHY54684_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 81 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 82 (_val), (_mask)) 83 84 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 85 #define READ_PHY54684_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 86 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 87 #define WRITE_PHY54684_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 88 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 89 #define MODIFY_PHY54684_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 90 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 91 (_val), (_mask)) 92 93 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 94 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 95 96 /* 1000BASE-T Control Register (ADDR 09h) */ 97 #define READ_PHY54684_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 98 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 99 #define WRITE_PHY54684_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 100 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 101 #define MODIFY_PHY54684_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 102 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 103 (_val), (_mask)) 104 105 /* 1000BASE-T Status Register (ADDR 0ah) */ 106 #define READ_PHY54684_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 107 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 108 #define WRITE_PHY54684_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 109 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 110 #define MODIFY_PHY54684_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 111 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 112 (_val), (_mask)) 113 114 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 115 116 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 117 #define READ_PHY54684_MII_ECRr(_unit, _phy_ctrl, _val) \ 118 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 119 #define WRITE_PHY54684_MII_ECRr(_unit, _phy_ctrl, _val) \ 120 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 121 #define MODIFY_PHY54684_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 122 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 123 (_val), (_mask)) 124 125 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 126 #define READ_PHY54684_MII_ESRr(_unit, _phy_ctrl, _val) \ 127 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 128 #define WRITE_PHY54684_MII_ESRr(_unit, _phy_ctrl, _val) \ 129 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 130 #define MODIFY_PHY54684_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 131 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 132 (_val), (_mask)) 133 134 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 135 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 136 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 137 138 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 139 #define READ_PHY54684_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 140 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 141 #define WRITE_PHY54684_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 142 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 143 #define MODIFY_PHY54684_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 144 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 145 (_val), (_mask)) 146 147 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 148 #define READ_PHY54684_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 149 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 150 #define WRITE_PHY54684_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 151 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 152 #define MODIFY_PHY54684_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 153 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 154 (_val), (_mask)) 155 156 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 157 #define READ_PHY54684_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 158 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 159 #define WRITE_PHY54684_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 160 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 161 #define MODIFY_PHY54684_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 162 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 163 (_val), (_mask)) 164 165 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 166 #define READ_PHY54684_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 167 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 168 #define WRITE_PHY54684_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 169 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 170 #define MODIFY_PHY54684_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 171 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 172 (_val), (_mask)) 173 174 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 175 #define READ_PHY54684_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 176 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 177 #define WRITE_PHY54684_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 178 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 179 #define MODIFY_PHY54684_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 180 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 181 (_val), (_mask)) 182 183 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 184 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 185 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 186 187 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 188 #define READ_PHY54684_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 189 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 190 #define WRITE_PHY54684_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 191 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 192 #define MODIFY_PHY54684_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 193 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 194 (_val), (_mask)) 195 196 /* 1000BASE-T/100BASE-TX/10BASE-T Clk Alignment Ctrl (ADDR 1ch shadow 00011) */ 197 #define READ_PHY54684_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 198 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 199 #define WRITE_PHY54684_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 200 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 201 #define MODIFY_PHY54684_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 202 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, \ 203 (_val), (_mask)) 204 205 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 206 #define READ_PHY54684_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 207 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 208 #define WRITE_PHY54684_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 209 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 210 #define MODIFY_PHY54684_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 211 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 212 (_val), (_mask)) 213 214 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 215 #define READ_PHY54684_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 216 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 217 #define WRITE_PHY54684_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 218 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 219 #define MODIFY_PHY54684_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 220 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 221 (_val), (_mask)) 222 223 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 224 #define READ_PHY54684_LED_STATr(_unit, _phy_ctrl, _val) \ 225 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 226 #define WRITE_PHY54684_LED_STATr(_unit, _phy_ctrl, _val) \ 227 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 228 #define MODIFY_PHY54684_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 229 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 230 (_val), (_mask)) 231 232 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 233 #define READ_PHY54684_LED_CTRLr(_unit, _phy_ctrl, _val) \ 234 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 235 #define WRITE_PHY54684_LED_CTRLr(_unit, _phy_ctrl, _val) \ 236 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 237 #define MODIFY_PHY54684_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 238 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 239 (_val), (_mask)) 240 241 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 242 #define READ_PHY54684_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 243 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 244 #define WRITE_PHY54684_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 245 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 246 #define MODIFY_PHY54684_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 247 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 248 (_val), (_mask)) 249 250 #define PHY_54684_AUTO_PWRDWN_EN (1 << 5) 251 #define PHY_54684_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 252 #define PHY_54684_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 253 #define PHY_54684_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 254 #define PHY_54684_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 255 #define PHY_54684_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 256 257 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 258 #define READ_PHY54684_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 259 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 260 #define WRITE_PHY54684_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 261 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 262 #define MODIFY_PHY54684_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 263 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 264 (_val), (_mask)) 265 266 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 267 #define READ_PHY54684_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 268 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 269 #define WRITE_PHY54684_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 270 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 271 #define MODIFY_PHY54684_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 272 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 273 (_val), (_mask)) 274 275 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 276 #define READ_PHY54684_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 277 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 278 #define WRITE_PHY54684_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 279 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 280 #define MODIFY_PHY54684_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 281 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, \ 282 (_val), (_mask)) 283 284 /* SerDes 100BASE-FX Status Reg (ADDR 1ch shadow 10001) */ 285 #define READ_PHY54684_100FX_STATr(_unit, _phy_ctrl, _val) \ 286 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 287 #define WRITE_PHY54684_100FX_STATr(_unit, _phy_ctrl, _val) \ 288 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 289 #define MODIFY_PHY54684_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 290 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, \ 291 (_val), (_mask)) 292 293 /* SerDes 100BASE-FX Control Reg (ADDR 1ch shadow 10011) */ 294 #define READ_PHY54684_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 295 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 296 #define WRITE_PHY54684_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 297 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 298 #define MODIFY_PHY54684_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 299 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, \ 300 (_val), (_mask)) 301 302 /* SERDES 100-FX Control Register (ADDR 1ch shadow 10011) */ 303 #define READ_PHY54684_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 304 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 305 #define WRITE_PHY54684_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 306 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 307 #define MODIFY_PHY54684_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 308 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, \ 309 (_val), (_mask)) 310 311 /* SGMII Slave Reg (ADDR 1ch shadow 10101) */ 312 #define READ_PHY54684_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 313 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 314 #define WRITE_PHY54684_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 315 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 316 #define MODIFY_PHY54684_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 317 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, \ 318 (_val), (_mask)) 319 320 /* Primary SerDes Control Reg (ADDR 1ch shadow 10110) */ 321 #define READ_PHY54684_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 322 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 323 #define WRITE_PHY54684_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 324 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 325 #define MODIFY_PHY54684_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 326 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 327 (_val), (_mask)) 328 329 /* Misc 1000BASE-X Control (ADDR 1ch shadow 10111) */ 330 #define READ_PHY54684_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val) \ 331 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 332 #define WRITE_PHY54684_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val) \ 333 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 334 #define MODIFY_PHY54684_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val, _mask) \ 335 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, \ 336 (_val), (_mask)) 337 338 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 339 #define READ_PHY54684_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 340 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 341 #define WRITE_PHY54684_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 342 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 343 #define MODIFY_PHY54684_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 344 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 345 (_val), (_mask)) 346 347 /* 1000BASE-X Auto-neg Debug Reg (ADDR 1ch shadow 11010) */ 348 #define READ_PHY54684_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 349 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 350 #define WRITE_PHY54684_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 351 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 352 #define MODIFY_PHY54684_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 353 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, \ 354 (_val), (_mask)) 355 356 /* Auxiliary 1000BASE-X Control Reg (ADDR 1ch shadow 11011) */ 357 #define READ_PHY54684_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 358 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 359 #define WRITE_PHY54684_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 360 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 361 #define MODIFY_PHY54684_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 362 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, \ 363 (_val), (_mask)) 364 365 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 366 #define READ_PHY54684_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 367 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 368 #define WRITE_PHY54684_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 369 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 370 #define MODIFY_PHY54684_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 371 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, \ 372 (_val), (_mask)) 373 374 /* Misc 1000BASE-X Status Reg (ADDR 1ch shadow 11101) */ 375 #define READ_PHY54684_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 376 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 377 #define WRITE_PHY54684_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 378 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 379 #define MODIFY_PHY54684_MISC_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 380 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, \ 381 (_val), (_mask)) 382 383 /* Copper/Fiber Auto-Detect Medium Reg (ADDR 1ch shadow 11110) */ 384 #define READ_PHY54684_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 385 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 386 #define WRITE_PHY54684_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 387 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 388 #define MODIFY_PHY54684_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val, _mask) \ 389 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, \ 390 (_val), (_mask)) 391 392 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 393 #define READ_PHY54684_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 394 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 395 #define WRITE_PHY54684_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 396 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 397 #define MODIFY_PHY54684_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 398 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, \ 399 (_val), (_mask)) 400 401 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 402 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 403 404 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 405 #define READ_PHY54684_TEST1r(_unit, _phy_ctrl, _val) \ 406 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 407 #define WRITE_PHY54684_TEST1r(_unit, _phy_ctrl, _val) \ 408 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 409 #define MODIFY_PHY54684_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 410 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 411 (_val), (_mask)) 412 413 414 /* +------------------------------+ 415 * | | 416 * | Primary SerDes Registers | 417 * | | 418 * +------------------------------+ 419 */ 420 /* 1000BASE-X MII Control Register (Addr 00h) */ 421 #define READ_PHY54684_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 422 PHY54684_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 423 0x0000, 0x00, (_val)) 424 #define WRITE_PHY54684_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 425 PHY54684_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 426 0x0000, 0x00, (_val)) 427 #define MODIFY_PHY54684_1000X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 428 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 429 0x0000, 0x00, (_val), (_mask)) 430 431 /* 1000BASE-X MII Status Register (Addr 01h) */ 432 #define READ_PHY54684_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 433 PHY54684_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 434 0x0000, 0x01, (_val)) 435 #define WRITE_PHY54684_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 436 PHY54684_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 437 0x0000, 0x01, (_val)) 438 #define MODIFY_PHY54684_1000X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 439 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 440 0x0000, 0x01, (_val), (_mask)) 441 442 /* 1000BASE-X MII Auto-neg Advertise Register (Addr 04h) */ 443 #define READ_PHY54684_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 444 PHY54684_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 445 0x0000, 0x04, (_val)) 446 #define WRITE_PHY54684_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 447 PHY54684_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 448 0x0000, 0x04, (_val)) 449 #define MODIFY_PHY54684_1000X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 450 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 451 0x0000, 0x04, (_val), (_mask)) 452 453 /* 1000BASE-X MII Auto-neg Link Partner Ability Register (Addr 05h) */ 454 #define READ_PHY54684_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 455 PHY54684_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 456 0x0000, 0x05, (_val)) 457 #define WRITE_PHY54684_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 458 PHY54684_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 459 0x0000, 0x05, (_val)) 460 #define MODIFY_PHY54684_1000X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 461 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 462 0x0000, 0x05, (_val), (_mask)) 463 464 /* 1000BASE-X MII Auto-neg Extended Status Register (Addr 06h) */ 465 #define READ_PHY54684_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 466 PHY54684_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 467 0x0000, 0x06, (_val)) 468 #define WRITE_PHY54684_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 469 PHY54684_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 470 0x0000, 0x06, (_val)) 471 #define MODIFY_PHY54684_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 472 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 473 0x0000, 0x06, (_val), (_mask)) 474 475 /* 1000BASE-X MII IEEE Extended Status Register (Addr 0fh) */ 476 #define READ_PHY54684_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 477 PHY54684_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 478 0x0000, 0x0f, (_val)) 479 #define WRITE_PHY54684_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 480 PHY54684_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 481 0x0000, 0x0f, (_val)) 482 #define MODIFY_PHY54684_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 483 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 484 0x0000, 0x0f, (_val), (_mask)) 485 486 /* +-------------------------+ 487 * | | 488 * | Expansion Registers | 489 * | | 490 * +-------------------------+ 491 */ 492 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 493 #define READ_PHY54684_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 494 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 495 #define WRITE_PHY54684_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 496 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 497 #define MODIFY_PHY54684_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 498 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, \ 499 (_val), (_mask)) 500 501 /* Expansion Interrupt Status Register (Addr 01h) */ 502 #define READ_PHY54684_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 503 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 504 #define WRITE_PHY54684_EXP_r(_unit, _phy_ctrl, _val) \ 505 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 506 #define MODIFY_PHY54684_EXP_r(_unit, _phy_ctrl, _val, _mask) \ 507 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, \ 508 (_val), (_mask)) 509 510 /* Expansion Interrupt Mask Register (Addr 02h) */ 511 #define READ_PHY54684_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 512 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 513 #define WRITE_PHY54684_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 514 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 515 #define MODIFY_PHY54684_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 516 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, \ 517 (_val), (_mask)) 518 519 /* Multicolor LED Selector Register (Addr 04h) */ 520 #define READ_PHY54684_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 521 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 522 #define WRITE_PHY54684_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 523 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 524 #define MODIFY_PHY54684_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 525 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, \ 526 (_val), (_mask)) 527 528 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 529 #define READ_PHY54684_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 530 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 531 #define WRITE_PHY54684_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 532 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 533 #define MODIFY_PHY54684_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 534 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, \ 535 (_val), (_mask)) 536 537 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 538 #define READ_PHY54684_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 539 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 540 #define WRITE_PHY54684_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 541 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 542 #define MODIFY_PHY54684_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 543 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, \ 544 (_val), (_mask)) 545 546 /* 10BT Controls Register (Addr 08h) */ 547 #define READ_PHY54684_10BT_CTRLr(_unit, _phy_ctrl, _val) \ 548 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, (_val)) 549 #define WRITE_PHY54684_10BT_CTRLr(_unit, _phy_ctrl, _val) \ 550 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, (_val)) 551 #define MODIFY_PHY54684_10BT_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 552 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, \ 553 (_val), (_mask)) 554 555 /* Operating Mode Status Register (Addr 42h) */ 556 #define READ_PHY54684_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 557 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 558 #define WRITE_PHY54684_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 559 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 560 #define MODIFY_PHY54684_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val, _mask) \ 561 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, \ 562 (_val), (_mask)) 563 564 /* SerDes/SGMII Control Register (Addr 50h) */ 565 #define READ_PHY54684_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val) \ 566 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, (_val)) 567 #define WRITE_PHY54684_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val) \ 568 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, (_val)) 569 #define MODIFY_PHY54684_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 570 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, \ 571 (_val), (_mask)) 572 573 /* SerDes/SGMII Control Register (Addr 52h) */ 574 #define READ_PHY54684_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 575 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 576 #define WRITE_PHY54684_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 577 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 578 #define MODIFY_PHY54684_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 579 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, \ 580 (_val), (_mask)) 581 582 /* +--------------------------------+ 583 * | | 584 * | Secondary SerDes Registers | 585 * | | 586 * +--------------------------------+ 587 */ 588 /* 1000BASE-X Control Register (Addr 00h) */ 589 #define READ_PHY54684_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 590 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, (_val)) 591 #define WRITE_PHY54684_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 592 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, (_val)) 593 #define MODIFY_PHY54684_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 594 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, \ 595 (_val), (_mask)) 596 597 /* 1000BASE-X Status Register (Addr 01h) */ 598 #define READ_PHY54684_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val) \ 599 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, (_val)) 600 #define WRITE_PHY54684_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val) \ 601 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, (_val)) 602 #define MODIFY_PHY54684_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 603 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, \ 604 (_val), (_mask)) 605 606 /* Auto-neg Advertise Register (Addr 04h) */ 607 #define READ_PHY54684_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val) \ 608 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, (_val)) 609 #define WRITE_PHY54684_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val) \ 610 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, (_val)) 611 #define MODIFY_PHY54684_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val, _mask) \ 612 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, \ 613 (_val), (_mask)) 614 615 /* 1000BASE-X Auto-neg Link Partner Ability Register (Addr 05h) */ 616 #define READ_PHY54684_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val) \ 617 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, (_val)) 618 #define WRITE_PHY54684_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val) \ 619 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, (_val)) 620 #define MODIFY_PHY54684_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val, _mask) \ 621 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, \ 622 (_val), (_mask)) 623 624 /* 1000BASE-X Auto-neg Secondary SerDes Register (Addr 06h) */ 625 #define READ_PHY54684_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val) \ 626 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, (_val)) 627 #define WRITE_PHY54684_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val) \ 628 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, (_val)) 629 #define MODIFY_PHY54684_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 630 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, \ 631 (_val), (_mask)) 632 633 /* 1000BASE-X Auto-neg Next Page Transmit Register (Addr 07h) */ 634 #define READ_PHY54684_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 635 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, (_val)) 636 #define WRITE_PHY54684_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 637 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, (_val)) 638 #define MODIFY_PHY54684_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val, _mask) \ 639 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, \ 640 (_val), (_mask)) 641 642 /* 1000BASE-X Auto-neg Link Partner Next Page Register (Addr 08h) */ 643 #define READ_PHY54684_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 644 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, (_val)) 645 #define WRITE_PHY54684_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 646 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, (_val)) 647 #define MODIFY_PHY54684_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val, _mask) \ 648 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, \ 649 (_val), (_mask)) 650 651 /* 1000BASE-X Extended Status Register (Addr 0fh) */ 652 #define READ_PHY54684_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val) \ 653 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, (_val)) 654 #define WRITE_PHY54684_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val) \ 655 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, (_val)) 656 #define MODIFY_PHY54684_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 657 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, \ 658 (_val), (_mask)) 659 660 /* Misc 1 Register (Addr 10h) */ 661 #define READ_PHY54684_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val) \ 662 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, (_val)) 663 #define WRITE_PHY54684_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val) \ 664 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, (_val)) 665 #define MODIFY_PHY54684_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 666 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, \ 667 (_val), (_mask)) 668 669 /* 100BASE-FX Status Register (Addr 11h) */ 670 #define READ_PHY54684_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val) \ 671 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, (_val)) 672 #define WRITE_PHY54684_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val) \ 673 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, (_val)) 674 #define MODIFY_PHY54684_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 675 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, \ 676 (_val), (_mask)) 677 678 /* 100BASE-FX Test Register (Addr 12h) */ 679 #define READ_PHY54684_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val) \ 680 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, (_val)) 681 #define WRITE_PHY54684_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val) \ 682 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, (_val)) 683 #define MODIFY_PHY54684_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val, _mask) \ 684 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, \ 685 (_val), (_mask)) 686 687 /* Packet Counter Register (Addr 13h) */ 688 #define READ_PHY54684_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val) \ 689 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, (_val)) 690 #define WRITE_PHY54684_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val) \ 691 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, (_val)) 692 #define MODIFY_PHY54684_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 693 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, \ 694 (_val), (_mask)) 695 696 /* Error Counter Register (Addr 14h) */ 697 #define READ_PHY54684_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 698 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, (_val)) 699 #define WRITE_PHY54684_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 700 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, (_val)) 701 #define MODIFY_PHY54684_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 702 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, \ 703 (_val), (_mask)) 704 705 /* SGMII Slave Register (Addr 15h) */ 706 #define READ_PHY54684_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 707 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, (_val)) 708 #define WRITE_PHY54684_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 709 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, (_val)) 710 #define MODIFY_PHY54684_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 711 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, \ 712 (_val), (_mask)) 713 714 /* Secondary SerDes Control Register (Addr 16h) */ 715 #define READ_PHY54684_EXP_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 716 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, (_val)) 717 #define WRITE_PHY54684_EXP_2ND_SERDES_CTRL_SLAVEr(_unit, _phy_ctrl, _val) \ 718 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, (_val)) 719 #define MODIFY_PHY54684_EXP_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 720 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, \ 721 (_val), (_mask)) 722 723 /* Misc 1000BASE-X Control 2 Register (Addr 17h) */ 724 #define READ_PHY54684_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 725 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, (_val)) 726 #define WRITE_PHY54684_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 727 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, (_val)) 728 #define MODIFY_PHY54684_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 729 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, \ 730 (_val), (_mask)) 731 732 /* Misc 1000BASE-X Control 3 Register (Addr 18h) */ 733 #define READ_PHY54684_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 734 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, (_val)) 735 #define WRITE_PHY54684_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 736 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, (_val)) 737 #define MODIFY_PHY54684_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 738 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, \ 739 (_val), (_mask)) 740 741 /* Auto-neg 1000BASE-X Debug Register (Addr 1ah) */ 742 #define READ_PHY54684_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 743 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, (_val)) 744 #define WRITE_PHY54684_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 745 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, (_val)) 746 #define MODIFY_PHY54684_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 747 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, \ 748 (_val), (_mask)) 749 750 /* Secondary SerDes Auxiliary 1000BASE-X Control Register (Addr 1bh) */ 751 #define READ_PHY54684_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 752 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, (_val)) 753 #define WRITE_PHY54684_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 754 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, (_val)) 755 #define MODIFY_PHY54684_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 756 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, \ 757 (_val), (_mask)) 758 759 /* Auxilary 1000BASE-X Status Register (Addr 1ch) */ 760 #define READ_PHY54684_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val) \ 761 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, (_val)) 762 #define WRITE_PHY54684_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val) \ 763 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, (_val)) 764 #define MODIFY_PHY54684_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val, _mask) \ 765 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, \ 766 (_val), (_mask)) 767 768 /* Misc 1000BASE-X Status Register (Addr 1dh) */ 769 #define READ_PHY54684_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val) \ 770 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, (_val)) 771 #define WRITE_PHY54684_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val) \ 772 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, (_val)) 773 #define MODIFY_PHY54684_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val, _mask) \ 774 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, \ 775 (_val), (_mask)) 776 777 /* Spare Register (Addr 21h) */ 778 #define READ_PHY54684_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val) \ 779 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, (_val)) 780 #define WRITE_PHY54684_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val) \ 781 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, (_val)) 782 #define MODIFY_PHY54684_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val, _mask) \ 783 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, \ 784 (_val), (_mask)) 785 786 /* Secondary SerDes Interrupt Status Register (Addr 30h) */ 787 #define READ_PHY54684_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 788 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, (_val)) 789 #define WRITE_PHY54684_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 790 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, (_val)) 791 #define MODIFY_PHY54684_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val, _mask) \ 792 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, \ 793 (_val), (_mask)) 794 795 /* Secondary SerDes Interrupt Mask Register (Addr 31h) */ 796 #define READ_PHY54684_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 797 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, (_val)) 798 #define WRITE_PHY54684_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 799 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, (_val)) 800 #define MODIFY_PHY54684_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 801 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, \ 802 (_val), (_mask)) 803 804 /* Secondary SerDes Lineside Loopback Control Register (Addr 44h) */ 805 #define READ_PHY54684_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val) \ 806 PHY54684_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, (_val)) 807 #define WRITE_PHY54684_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val) \ 808 PHY54684_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, (_val)) 809 #define MODIFY_PHY54684_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 810 PHY54684_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, \ 811 (_val), (_mask)) 812 813 #endif /* _PHY54684_H_ */