phy54682.h (56628B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy54682.h 8 * 9 * This driver applies to BCM54682. 10 * It support driving Copper or SERDES interfaces. 11 */ 12 13 #ifndef _PHY54682_H_ 14 #define _PHY54682_H_ 15 16 #include <soc/phy.h> 17 18 /* PHY register access */ 19 #define PHY54682_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 20 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 21 (_reg_addr), (_val)) 22 #define PHY54682_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHY54682_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, \ 26 _val, _mask) \ 27 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val), (_mask)) 29 30 /* Clause 45 Registers access using Clause 22 register access */ 31 #define PHY54682E_CL45_REG_READ(_unit, _phy_ctrl, _flags, _dev_addr, _reg_addr, _val) \ 32 _phy_54682e_cl45_reg_read((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 33 (_reg_addr), (_val)) 34 #define PHY54682E_CL45_REG_WRITE(_unit, _phy_ctrl, _flags, \ 35 _dev_addr, _reg_addr, _val) \ 36 _phy_54682e_cl45_reg_write((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 37 (_reg_addr), (_val)) 38 #define PHY54682E_CL45_REG_MODIFY(_unit, _phy_ctrl, _flags, _dev_addr, \ 39 _reg_addr, _val, _mask) \ 40 _phy_54682e_cl45_reg_modify((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 41 (_reg_addr), (_val), (_mask)) 42 43 44 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 45 #define READ_PHY54682_MII_CTRLr(_unit, _phy_ctrl, _val) \ 46 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 47 #define WRITE_PHY54682_MII_CTRLr(_unit, _phy_ctrl, _val) \ 48 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 49 #define MODIFY_PHY54682_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 50 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 51 (_val), (_mask)) 52 53 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 54 #define READ_PHY54682_MII_STATr(_unit, _phy_ctrl, _val) \ 55 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 56 #define WRITE_PHY54682_MII_STATr(_unit, _phy_ctrl, _val) \ 57 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 58 #define MODIFY_PHY54682_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 59 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 60 (_val), (_mask)) 61 62 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 63 #define READ_PHY54682_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 64 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 65 #define WRITE_PHY54682_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 66 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 67 #define MODIFY_PHY54682_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 68 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 69 (_val), (_mask)) 70 71 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 72 #define READ_PHY54682_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 73 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 74 #define WRITE_PHY54682_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 75 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 76 #define MODIFY_PHY54682_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 77 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 78 (_val), (_mask)) 79 80 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 81 #define READ_PHY54682_MII_ANAr(_unit, _phy_ctrl, _val) \ 82 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 83 #define WRITE_PHY54682_MII_ANAr(_unit, _phy_ctrl, _val) \ 84 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 85 #define MODIFY_PHY54682_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 86 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 87 (_val), (_mask)) 88 89 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 90 #define READ_PHY54682_MII_ANPr(_unit, _phy_ctrl, _val) \ 91 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 92 #define WRITE_PHY54682_MII_ANPr(_unit, _phy_ctrl, _val) \ 93 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 94 #define MODIFY_PHY54682_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 95 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 96 (_val), (_mask)) 97 98 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 99 #define READ_PHY54682_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 100 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 101 #define WRITE_PHY54682_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 102 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 103 #define MODIFY_PHY54682_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 104 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 105 (_val), (_mask)) 106 107 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 108 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 109 110 /* 1000BASE-T Control Register (ADDR 09h) */ 111 #define READ_PHY54682_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 112 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 113 #define WRITE_PHY54682_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 114 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 115 #define MODIFY_PHY54682_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 116 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 117 (_val), (_mask)) 118 119 /* 1000BASE-T Status Register (ADDR 0ah) */ 120 #define READ_PHY54682_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 121 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 122 #define WRITE_PHY54682_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 123 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 124 #define MODIFY_PHY54682_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 125 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 126 (_val), (_mask)) 127 128 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 129 130 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 131 #define READ_PHY54682_MII_ECRr(_unit, _phy_ctrl, _val) \ 132 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 133 #define WRITE_PHY54682_MII_ECRr(_unit, _phy_ctrl, _val) \ 134 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 135 #define MODIFY_PHY54682_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 136 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 137 (_val), (_mask)) 138 139 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 140 #define READ_PHY54682_MII_ESRr(_unit, _phy_ctrl, _val) \ 141 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 142 #define WRITE_PHY54682_MII_ESRr(_unit, _phy_ctrl, _val) \ 143 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 144 #define MODIFY_PHY54682_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 145 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 146 (_val), (_mask)) 147 148 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 149 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 150 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 151 152 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 153 #define READ_PHY54682_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 154 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 155 #define WRITE_PHY54682_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 156 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 157 #define MODIFY_PHY54682_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 158 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 159 (_val), (_mask)) 160 161 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 162 #define READ_PHY54682_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 163 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 164 #define WRITE_PHY54682_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 165 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 166 #define MODIFY_PHY54682_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 167 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 168 (_val), (_mask)) 169 170 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 171 #define READ_PHY54682_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 172 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 173 #define WRITE_PHY54682_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 174 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 175 #define MODIFY_PHY54682_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 176 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 177 (_val), (_mask)) 178 179 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 180 #define READ_PHY54682_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 181 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 182 #define WRITE_PHY54682_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 183 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 184 #define MODIFY_PHY54682_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 185 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 186 (_val), (_mask)) 187 188 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 189 #define READ_PHY54682_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 190 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 191 #define WRITE_PHY54682_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 192 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 193 #define MODIFY_PHY54682_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 194 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 195 (_val), (_mask)) 196 197 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 198 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 199 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 200 201 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 202 #define READ_PHY54682_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 203 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 204 #define WRITE_PHY54682_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 205 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 206 #define MODIFY_PHY54682_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 207 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 208 (_val), (_mask)) 209 210 /* 1000BASE-T/100BASE-TX/10BASE-T Clk Alignment Ctrl (ADDR 1ch shadow 00011) */ 211 #define READ_PHY54682_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 212 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 213 #define WRITE_PHY54682_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 214 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 215 #define MODIFY_PHY54682_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 216 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, \ 217 (_val), (_mask)) 218 219 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 220 #define READ_PHY54682_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 221 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 222 #define WRITE_PHY54682_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 223 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 224 #define MODIFY_PHY54682_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 225 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 226 (_val), (_mask)) 227 228 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 229 #define READ_PHY54682_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 230 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 231 #define WRITE_PHY54682_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 232 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 233 #define MODIFY_PHY54682_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 234 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 235 (_val), (_mask)) 236 237 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 238 #define READ_PHY54682_LED_STATr(_unit, _phy_ctrl, _val) \ 239 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 240 #define WRITE_PHY54682_LED_STATr(_unit, _phy_ctrl, _val) \ 241 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 242 #define MODIFY_PHY54682_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 243 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 244 (_val), (_mask)) 245 246 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 247 #define READ_PHY54682_LED_CTRLr(_unit, _phy_ctrl, _val) \ 248 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 249 #define WRITE_PHY54682_LED_CTRLr(_unit, _phy_ctrl, _val) \ 250 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 251 #define MODIFY_PHY54682_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 252 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 253 (_val), (_mask)) 254 255 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 256 #define READ_PHY54682_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 257 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 258 #define WRITE_PHY54682_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 259 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 260 #define MODIFY_PHY54682_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 261 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 262 (_val), (_mask)) 263 264 #define PHY_54682_AUTO_PWRDWN_EN (1 << 5) 265 #define PHY_54682_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 266 #define PHY_54682_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 267 #define PHY_54682_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 268 #define PHY_54682_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 269 #define PHY_54682_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 270 271 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 272 #define READ_PHY54682_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 273 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 274 #define WRITE_PHY54682_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 275 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 276 #define MODIFY_PHY54682_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 277 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 278 (_val), (_mask)) 279 280 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 281 #define READ_PHY54682_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 282 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 283 #define WRITE_PHY54682_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 284 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 285 #define MODIFY_PHY54682_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 286 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 287 (_val), (_mask)) 288 289 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 290 #define READ_PHY54682_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 291 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 292 #define WRITE_PHY54682_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 293 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 294 #define MODIFY_PHY54682_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 295 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, \ 296 (_val), (_mask)) 297 298 /* SerDes 100BASE-FX Status Reg (ADDR 1ch shadow 10001) */ 299 #define READ_PHY54682_100FX_STATr(_unit, _phy_ctrl, _val) \ 300 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 301 #define WRITE_PHY54682_100FX_STATr(_unit, _phy_ctrl, _val) \ 302 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 303 #define MODIFY_PHY54682_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 304 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, \ 305 (_val), (_mask)) 306 307 /* SerDes 100BASE-FX Control Reg (ADDR 1ch shadow 10011) */ 308 #define READ_PHY54682_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 309 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 310 #define WRITE_PHY54682_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 311 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 312 #define MODIFY_PHY54682_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 313 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, \ 314 (_val), (_mask)) 315 316 /* SERDES 100-FX Control Register (ADDR 1ch shadow 10011) */ 317 #define READ_PHY54682_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 318 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 319 #define WRITE_PHY54682_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 320 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 321 #define MODIFY_PHY54682_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 322 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, \ 323 (_val), (_mask)) 324 325 /* External SerDes Control Reg (ADDR 1ch shadow 10100) */ 326 #define READ_PHY54682_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 327 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 328 #define WRITE_PHY54682_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 329 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 330 #define MODIFY_PHY54682_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 331 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, \ 332 (_val), (_mask)) 333 334 /* SGMII Slave Reg (ADDR 1ch shadow 10101) */ 335 #define READ_PHY54682_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 336 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 337 #define WRITE_PHY54682_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 338 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 339 #define MODIFY_PHY54682_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 340 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, \ 341 (_val), (_mask)) 342 343 /* Misc. 1000BASE-X Control 2 Reg (ADDR 1ch shadow 10110) */ 344 #define READ_PHY54682_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 345 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 346 #define WRITE_PHY54682_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 347 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 348 #define MODIFY_PHY54682_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 349 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 350 (_val), (_mask)) 351 352 #define PHY_54682_MISC_1000X_SERDES_TX_MASK ((1U<<5)|(1U<<6)) 353 #define PHY_54682_MISC_1000X_SERDES_TX_ENABLE (1U<<5) 354 #define PHY_54682_MISC_1000X_SERDES_TX_DISABLE \ 355 PHY_54682_MISC_1000X_SERDES_TX_MASK 356 /* Misc 1000BASE-X Control (ADDR 1ch shadow 10111) */ 357 #define READ_PHY54682_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val) \ 358 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 359 #define WRITE_PHY54682_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val) \ 360 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 361 #define MODIFY_PHY54682_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val, _mask) \ 362 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, \ 363 (_val), (_mask)) 364 365 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 366 #define READ_PHY54682_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 367 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 368 #define WRITE_PHY54682_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 369 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 370 #define MODIFY_PHY54682_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 371 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 372 (_val), (_mask)) 373 374 /* 1000BASE-X Auto-neg Debug Reg (ADDR 1ch shadow 11010) */ 375 #define READ_PHY54682_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 376 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 377 #define WRITE_PHY54682_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 378 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 379 #define MODIFY_PHY54682_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 380 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, \ 381 (_val), (_mask)) 382 383 /* Auxiliary Control Reg (ADDR 1ch shadow 11011) */ 384 #define READ_PHY54682_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 385 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 386 #define WRITE_PHY54682_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 387 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 388 #define MODIFY_PHY54682_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 389 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, \ 390 (_val), (_mask)) 391 392 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 393 #define READ_PHY54682_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 394 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 395 #define WRITE_PHY54682_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 396 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 397 #define MODIFY_PHY54682_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 398 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, \ 399 (_val), (_mask)) 400 401 /* Misc 1000BASE-X Status Reg (ADDR 1ch shadow 11101) */ 402 #define READ_PHY54682_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 403 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 404 #define WRITE_PHY54682_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 405 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 406 #define MODIFY_PHY54682_MISC_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 407 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, \ 408 (_val), (_mask)) 409 410 #define PHY_54682_AUTO_DETECT_MEDIUM_INVERT_SD (1U << 8) 411 /* Copper/Fiber Auto-Detect Medium Reg (ADDR 1ch shadow 11110) */ 412 #define READ_PHY54682_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 413 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 414 #define WRITE_PHY54682_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 415 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 416 #define MODIFY_PHY54682_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val, _mask) \ 417 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, \ 418 (_val), (_mask)) 419 420 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 421 #define READ_PHY54682_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 422 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 423 #define WRITE_PHY54682_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 424 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 425 #define MODIFY_PHY54682_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 426 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, \ 427 (_val), (_mask)) 428 429 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 430 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 431 432 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 433 #define READ_PHY54682_TEST1r(_unit, _phy_ctrl, _val) \ 434 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 435 #define WRITE_PHY54682_TEST1r(_unit, _phy_ctrl, _val) \ 436 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 437 #define MODIFY_PHY54682_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 438 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 439 (_val), (_mask)) 440 441 442 /* +------------------------------+ 443 * | | 444 * | Primary SerDes Registers | 445 * | | 446 * +------------------------------+ 447 */ 448 /* 1000BASE-X MII Control Register (Addr 00h) */ 449 #define READ_PHY54682_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 450 PHY54682_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 451 0x0000, 0x00, (_val)) 452 #define WRITE_PHY54682_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 453 PHY54682_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 454 0x0000, 0x00, (_val)) 455 #define MODIFY_PHY54682_1000X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 456 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 457 0x0000, 0x00, (_val), (_mask)) 458 459 /* 1000BASE-X MII Status Register (Addr 01h) */ 460 #define READ_PHY54682_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 461 PHY54682_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 462 0x0000, 0x01, (_val)) 463 #define WRITE_PHY54682_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 464 PHY54682_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 465 0x0000, 0x01, (_val)) 466 #define MODIFY_PHY54682_1000X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 467 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 468 0x0000, 0x01, (_val), (_mask)) 469 470 /* 1000BASE-X MII Auto-neg Advertise Register (Addr 04h) */ 471 #define READ_PHY54682_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 472 PHY54682_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 473 0x0000, 0x04, (_val)) 474 #define WRITE_PHY54682_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 475 PHY54682_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 476 0x0000, 0x04, (_val)) 477 #define MODIFY_PHY54682_1000X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 478 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 479 0x0000, 0x04, (_val), (_mask)) 480 481 /* 1000BASE-X MII Auto-neg Link Partner Ability Register (Addr 05h) */ 482 #define READ_PHY54682_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 483 PHY54682_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 484 0x0000, 0x05, (_val)) 485 #define WRITE_PHY54682_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 486 PHY54682_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 487 0x0000, 0x05, (_val)) 488 #define MODIFY_PHY54682_1000X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 489 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 490 0x0000, 0x05, (_val), (_mask)) 491 492 /* 1000BASE-X MII Auto-neg Extended Status Register (Addr 06h) */ 493 #define READ_PHY54682_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 494 PHY54682_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 495 0x0000, 0x06, (_val)) 496 #define WRITE_PHY54682_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 497 PHY54682_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 498 0x0000, 0x06, (_val)) 499 #define MODIFY_PHY54682_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 500 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 501 0x0000, 0x06, (_val), (_mask)) 502 503 /* 1000BASE-X MII IEEE Extended Status Register (Addr 0fh) */ 504 #define READ_PHY54682_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 505 PHY54682_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 506 0x0000, 0x0f, (_val)) 507 #define WRITE_PHY54682_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 508 PHY54682_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 509 0x0000, 0x0f, (_val)) 510 #define MODIFY_PHY54682_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 511 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 512 0x0000, 0x0f, (_val), (_mask)) 513 514 /* +-------------------------+ 515 * | | 516 * | Expansion Registers | 517 * | | 518 * +-------------------------+ 519 */ 520 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 521 #define READ_PHY54682_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 522 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 523 #define WRITE_PHY54682_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 524 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 525 #define MODIFY_PHY54682_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 526 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, \ 527 (_val), (_mask)) 528 529 /* Expansion Interrupt Status Register (Addr 01h) */ 530 #define READ_PHY54682_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 531 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 532 #define WRITE_PHY54682_EXP_r(_unit, _phy_ctrl, _val) \ 533 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 534 #define MODIFY_PHY54682_EXP_r(_unit, _phy_ctrl, _val, _mask) \ 535 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, \ 536 (_val), (_mask)) 537 538 /* Expansion Interrupt Mask Register (Addr 02h) */ 539 #define READ_PHY54682_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 540 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 541 #define WRITE_PHY54682_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 542 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 543 #define MODIFY_PHY54682_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 544 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, \ 545 (_val), (_mask)) 546 547 /* Multicolor LED Selector Register (Addr 04h) */ 548 #define READ_PHY54682_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 549 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 550 #define WRITE_PHY54682_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 551 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 552 #define MODIFY_PHY54682_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 553 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, \ 554 (_val), (_mask)) 555 556 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 557 #define READ_PHY54682_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 558 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 559 #define WRITE_PHY54682_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 560 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 561 #define MODIFY_PHY54682_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 562 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, \ 563 (_val), (_mask)) 564 565 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 566 #define READ_PHY54682_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 567 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 568 #define WRITE_PHY54682_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 569 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 570 #define MODIFY_PHY54682_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 571 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, \ 572 (_val), (_mask)) 573 574 /* 10BT Controls Register (Addr 08h) */ 575 #define READ_PHY54682_10BT_CTRLr(_unit, _phy_ctrl, _val) \ 576 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, (_val)) 577 #define WRITE_PHY54682_10BT_CTRLr(_unit, _phy_ctrl, _val) \ 578 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, (_val)) 579 #define MODIFY_PHY54682_10BT_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 580 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, \ 581 (_val), (_mask)) 582 583 /* Operating Mode Status Register (Addr 42h) */ 584 #define READ_PHY54682_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 585 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 586 #define WRITE_PHY54682_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 587 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 588 #define MODIFY_PHY54682_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val, _mask) \ 589 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, \ 590 (_val), (_mask)) 591 592 /* SerDes/SGMII Control Register (Addr 50h) */ 593 #define READ_PHY54682_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val) \ 594 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, (_val)) 595 #define WRITE_PHY54682_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val) \ 596 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, (_val)) 597 #define MODIFY_PHY54682_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 598 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, \ 599 (_val), (_mask)) 600 601 /* SerDes/SGMII Control Register (Addr 52h) */ 602 #define READ_PHY54682_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 603 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 604 #define WRITE_PHY54682_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 605 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 606 #define MODIFY_PHY54682_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 607 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, \ 608 (_val), (_mask)) 609 610 /* SerDes Multiplier Control Register (Addr 55h) */ 611 #define READ_PHY54682_EXP_SERDES_MULTIPLIER_CTRLr(_unit, _phy_ctrl, _val) \ 612 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f55, 0x15, (_val)) 613 #define WRITE_PHY54682_EXP_SERDES_MULTIPLIER_CTRLr(_unit, _phy_ctrl, _val) \ 614 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f55, 0x15, (_val)) 615 #define MODIFY_PHY54682_EXP_SERDES_MULTIPLIER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 616 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f55, 0x15, \ 617 (_val), (_mask)) 618 619 /* +--------------------------------+ 620 * | | 621 * | Secondary SerDes Registers | 622 * | | 623 * +--------------------------------+ 624 */ 625 /* 1000BASE-X Control Register (Addr 00h) */ 626 #define READ_PHY54682_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 627 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, (_val)) 628 #define WRITE_PHY54682_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 629 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, (_val)) 630 #define MODIFY_PHY54682_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 631 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, \ 632 (_val), (_mask)) 633 634 /* 1000BASE-X Status Register (Addr 01h) */ 635 #define READ_PHY54682_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val) \ 636 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, (_val)) 637 #define WRITE_PHY54682_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val) \ 638 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, (_val)) 639 #define MODIFY_PHY54682_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 640 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, \ 641 (_val), (_mask)) 642 643 /* Auto-neg Advertise Register (Addr 04h) */ 644 #define READ_PHY54682_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val) \ 645 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, (_val)) 646 #define WRITE_PHY54682_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val) \ 647 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, (_val)) 648 #define MODIFY_PHY54682_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val, _mask) \ 649 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, \ 650 (_val), (_mask)) 651 652 /* 1000BASE-X Auto-neg Link Partner Ability Register (Addr 05h) */ 653 #define READ_PHY54682_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val) \ 654 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, (_val)) 655 #define WRITE_PHY54682_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val) \ 656 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, (_val)) 657 #define MODIFY_PHY54682_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val, _mask) \ 658 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, \ 659 (_val), (_mask)) 660 661 /* 1000BASE-X Auto-neg Secondary SerDes Register (Addr 06h) */ 662 #define READ_PHY54682_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val) \ 663 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, (_val)) 664 #define WRITE_PHY54682_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val) \ 665 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, (_val)) 666 #define MODIFY_PHY54682_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 667 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, \ 668 (_val), (_mask)) 669 670 /* 1000BASE-X Auto-neg Next Page Transmit Register (Addr 07h) */ 671 #define READ_PHY54682_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 672 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, (_val)) 673 #define WRITE_PHY54682_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 674 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, (_val)) 675 #define MODIFY_PHY54682_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val, _mask) \ 676 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, \ 677 (_val), (_mask)) 678 679 /* 1000BASE-X Auto-neg Link Partner Next Page Register (Addr 08h) */ 680 #define READ_PHY54682_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 681 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, (_val)) 682 #define WRITE_PHY54682_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 683 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, (_val)) 684 #define MODIFY_PHY54682_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val, _mask) \ 685 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, \ 686 (_val), (_mask)) 687 688 /* 1000BASE-X Extended Status Register (Addr 0fh) */ 689 #define READ_PHY54682_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val) \ 690 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, (_val)) 691 #define WRITE_PHY54682_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val) \ 692 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, (_val)) 693 #define MODIFY_PHY54682_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 694 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, \ 695 (_val), (_mask)) 696 697 /* Misc 1 Register (Addr 10h) */ 698 #define READ_PHY54682_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val) \ 699 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, (_val)) 700 #define WRITE_PHY54682_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val) \ 701 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, (_val)) 702 #define MODIFY_PHY54682_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 703 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, \ 704 (_val), (_mask)) 705 706 /* 100BASE-FX Status Register (Addr 11h) */ 707 #define READ_PHY54682_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val) \ 708 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, (_val)) 709 #define WRITE_PHY54682_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val) \ 710 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, (_val)) 711 #define MODIFY_PHY54682_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 712 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, \ 713 (_val), (_mask)) 714 715 /* 100BASE-FX Test Register (Addr 12h) */ 716 #define READ_PHY54682_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val) \ 717 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, (_val)) 718 #define WRITE_PHY54682_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val) \ 719 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, (_val)) 720 #define MODIFY_PHY54682_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val, _mask) \ 721 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, \ 722 (_val), (_mask)) 723 724 /* Packet Counter Register (Addr 13h) */ 725 #define READ_PHY54682_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val) \ 726 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, (_val)) 727 #define WRITE_PHY54682_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val) \ 728 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, (_val)) 729 #define MODIFY_PHY54682_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 730 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, \ 731 (_val), (_mask)) 732 733 /* Error Counter Register (Addr 14h) */ 734 #define READ_PHY54682_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 735 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, (_val)) 736 #define WRITE_PHY54682_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 737 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, (_val)) 738 #define MODIFY_PHY54682_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 739 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, \ 740 (_val), (_mask)) 741 742 /* SGMII Slave Register (Addr 15h) */ 743 #define READ_PHY54682_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 744 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, (_val)) 745 #define WRITE_PHY54682_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 746 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, (_val)) 747 #define MODIFY_PHY54682_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 748 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, \ 749 (_val), (_mask)) 750 751 /* Secondary SerDes Control Register (Addr 16h) */ 752 #define READ_PHY54682_EXP_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 753 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, (_val)) 754 #define WRITE_PHY54682_EXP_2ND_SERDES_CTRL_SLAVEr(_unit, _phy_ctrl, _val) \ 755 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, (_val)) 756 #define MODIFY_PHY54682_EXP_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 757 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, \ 758 (_val), (_mask)) 759 760 /* Misc 1000BASE-X Control 2 Register (Addr 17h) */ 761 #define READ_PHY54682_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 762 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, (_val)) 763 #define WRITE_PHY54682_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 764 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, (_val)) 765 #define MODIFY_PHY54682_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 766 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, \ 767 (_val), (_mask)) 768 769 /* Misc 1000BASE-X Control 3 Register (Addr 18h) */ 770 #define READ_PHY54682_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 771 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, (_val)) 772 #define WRITE_PHY54682_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 773 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, (_val)) 774 #define MODIFY_PHY54682_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 775 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, \ 776 (_val), (_mask)) 777 778 /* Auto-neg 1000BASE-X Debug Register (Addr 1ah) */ 779 #define READ_PHY54682_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 780 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, (_val)) 781 #define WRITE_PHY54682_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 782 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, (_val)) 783 #define MODIFY_PHY54682_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 784 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, \ 785 (_val), (_mask)) 786 787 /* Secondary SerDes Auxiliary 1000BASE-X Control Register (Addr 1bh) */ 788 #define READ_PHY54682_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 789 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, (_val)) 790 #define WRITE_PHY54682_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 791 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, (_val)) 792 #define MODIFY_PHY54682_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 793 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, \ 794 (_val), (_mask)) 795 796 /* Auxilary 1000BASE-X Status Register (Addr 1ch) */ 797 #define READ_PHY54682_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val) \ 798 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, (_val)) 799 #define WRITE_PHY54682_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val) \ 800 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, (_val)) 801 #define MODIFY_PHY54682_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val, _mask) \ 802 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, \ 803 (_val), (_mask)) 804 805 /* Misc 1000BASE-X Status Register (Addr 1dh) */ 806 #define READ_PHY54682_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val) \ 807 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, (_val)) 808 #define WRITE_PHY54682_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val) \ 809 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, (_val)) 810 #define MODIFY_PHY54682_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val, _mask) \ 811 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, \ 812 (_val), (_mask)) 813 814 /* Spare Register (Addr 21h) */ 815 #define READ_PHY54682_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val) \ 816 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, (_val)) 817 #define WRITE_PHY54682_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val) \ 818 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, (_val)) 819 #define MODIFY_PHY54682_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val, _mask) \ 820 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, \ 821 (_val), (_mask)) 822 823 /* Secondary SerDes Interrupt Status Register (Addr 30h) */ 824 #define READ_PHY54682_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 825 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, (_val)) 826 #define WRITE_PHY54682_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 827 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, (_val)) 828 #define MODIFY_PHY54682_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val, _mask) \ 829 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, \ 830 (_val), (_mask)) 831 832 /* Secondary SerDes Interrupt Mask Register (Addr 31h) */ 833 #define READ_PHY54682_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 834 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, (_val)) 835 #define WRITE_PHY54682_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 836 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, (_val)) 837 #define MODIFY_PHY54682_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 838 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, \ 839 (_val), (_mask)) 840 841 /* Secondary SerDes Lineside Loopback Control Register (Addr 44h) */ 842 #define READ_PHY54682_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val) \ 843 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, (_val)) 844 #define WRITE_PHY54682_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val) \ 845 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, (_val)) 846 #define MODIFY_PHY54682_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 847 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, \ 848 (_val), (_mask)) 849 850 /* IEEE 1588 read start/end control Register (Addr f3h) */ 851 #define READ_PHY54682_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 852 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 853 #define WRITE_PHY54682_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 854 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 855 #define MODIFY_PHY54682_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 856 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, \ 857 (_val), (_mask)) 858 859 /* EEE related */ 860 861 /* Auto EEE MII_Buffer CNTL/Status 2 Register (Addr AEh) */ 862 #define READ_PHY54682_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 863 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAE, 0x15, (_val)) 864 #define WRITE_PHY54682_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 865 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 866 0x15, (_val)) 867 #define MODIFY_PHY54682_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 868 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 869 0x15, (_val), (_mask)) 870 871 /* Auto EEE MII_Buffer CNTL/Status 1 Register (Addr AEh) */ 872 #define READ_PHY54682_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 873 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAF, 0x15, (_val)) 874 #define WRITE_PHY54682_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 875 PHY54682_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 876 0x15, (_val)) 877 #define MODIFY_PHY54682_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 878 PHY54682_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 879 0x15, (_val), (_mask)) 880 881 /* EEE Statistics related */ 882 /* Local LPI request Counter Reg (Addr ach) */ 883 #define READ_PHY54682_EXP_EEE_TX_EVENTSr(_unit, _phy_ctrl, _val) \ 884 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAC, 0x15, (_val)) 885 886 /* Remote LPI request Counter Reg (Addr adh) */ 887 #define READ_PHY54682_EXP_EEE_RX_EVENTSr(_unit, _phy_ctrl, _val) \ 888 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAD, 0x15, (_val)) 889 890 /* Statistic Timer_12_hours_lpi remote Reg (Addr aah) */ 891 #define READ_PHY54682_EXP_EEE_TX_DURATIONr(_unit, _phy_ctrl, _val) \ 892 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAA, 0x15, (_val)) 893 894 /* Statistic Timer_12_hours_lpi_local Local Reg (Addr abh) */ 895 #define READ_PHY54682_EXP_EEE_RX_DURATIONr(_unit, _phy_ctrl, _val) \ 896 PHY54682_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAB, 0x15, (_val)) 897 898 899 /* EEE Capability Register */ 900 #define READ_PHY54682_EEE_CAPr(_unit, _phy_ctrl, _val) \ 901 PHY54682E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x3, 0x14, _val) 902 903 /* EEE Advertisement Register */ 904 #define READ_PHY54682_EEE_ADVr(_unit, _phy_ctrl, _val) \ 905 PHY54682E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 906 #define WRITE_PHY54682_EEE_ADVr(_unit, _phy_ctrl, _val) \ 907 PHY54682E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 908 #define MODIFY_PHY54682_EEE_ADVr(_unit, _phy_ctrl, _val, _mask) \ 909 PHY54682E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val, _mask) 910 911 #define READ_PHY54682_EEE_803Dr(_unit, _phy_ctrl, _val) \ 912 PHY54682E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 913 #define WRITE_PHY54682_EEE_803Dr(_unit, _phy_ctrl, _val) \ 914 PHY54682E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 915 #define MODIFY_PHY54682_EEE_803Dr(_unit, _phy_ctrl, _val, _mask) \ 916 PHY54682E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val, _mask) 917 918 /* EEE Resolution Status Register */ 919 #define READ_PHY54682_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 920 PHY54682E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 921 #define WRITE_PHY54682_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 922 PHY54682E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 923 #define MODIFY_PHY54682_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val, _mask) \ 924 PHY54682E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val, _mask) 925 926 #define READ_PHY54682_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 927 PHY54682E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 928 #define WRITE_PHY54682_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 929 PHY54682E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 930 #define MODIFY_PHY54682_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val, _mask) \ 931 PHY54682E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val, _mask) 932 933 /* EEE TEST Control Register B*/ 934 #define READ_PHY54682_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 935 PHY54682E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 936 #define WRITE_PHY54682_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 937 PHY54682E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 938 #define MODIFY_PHY54682_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val, _mask) \ 939 PHY54682E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val, _mask) 940 941 typedef struct { 942 uint32 flags; 943 uint16 phy_id_orig; 944 uint16 phy_id_base; /* port 0 addr */ 945 uint16 phy_slice; 946 } PHY54682_DEV_DESC_t; 947 948 #define PHY54682_DEV_PHY_ID_ORIG(_pc) (((PHY54682_DEV_DESC_t *)((_pc) + 1))->phy_id_orig) 949 #define PHY54682_DEV_PHY_ID_BASE(_pc) (((PHY54682_DEV_DESC_t *)((_pc) + 1))->phy_id_base) 950 #define PHY54682_DEV_PHY_SLICE(_pc) (((PHY54682_DEV_DESC_t *)((_pc) + 1))->phy_slice) 951 #define PHY54682_DEV_PHY_SLICE_IS_LAST2(_pc) (PHY54682_DEV_PHY_SLICE(_pc) > 5) 952 953 #define PHY54682_FLAGS(_pc) (((PHY54682_DEV_DESC_t *)((_pc) + 1))->flags) 954 #define PHY54682_DEV_PHY_SLICE_MASK 0x07 955 #define PHY54682_PHYA_REV (1U << 0) 956 957 #define PHY54682_DEV_SET_BASE_ADDR(_pc) \ 958 PHY54682_DEV_PHY_ID_BASE(_pc) = (PHY54682_FLAGS((_pc)) & PHY54682_PHYA_REV) ?\ 959 PHY54682_DEV_PHY_ID_ORIG(_pc) + PHY54682_DEV_PHY_SLICE(_pc) : \ 960 PHY54682_DEV_PHY_ID_ORIG(_pc) - PHY54682_DEV_PHY_SLICE(_pc) 961 962 #define PHY54682_SLICE_ADDR(_pc, _slice) \ 963 (PHY54682_FLAGS((_pc)) & PHY54682_PHYA_REV) ? (PHY54682_DEV_PHY_ID_BASE(_pc) - (_slice)) : \ 964 (PHY54682_DEV_PHY_ID_BASE(_pc) + (_slice)) 965 966 #endif /* _PHY54682_H_ */