phy54680.h (38574B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy54680.h 8 * 9 * This driver applies to both BCM54680 and BCM54680S. 10 * Both parts support driving Copper or SERDES interfaces. 11 * 12 * The BCM54680S also has a SERDES pass-through mode, making it possible 13 * to auto-select copper or fiber based on signal detects. 14 */ 15 16 #ifndef _PHY54680_H_ 17 #define _PHY54680_H_ 18 19 #include <soc/phy.h> 20 21 /* PHY register access */ 22 #define PHY54680_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHY54680_REG_WRITE(_unit, _phy_ctrl, _flags, \ 26 _reg_bank, _reg_addr, _val) \ 27 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val)) 29 #define PHY54680_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 30 _reg_addr, _val, _mask) \ 31 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 32 (_reg_addr), (_val), (_mask)) 33 34 35 /* Clause 45 Registers access using Clause 22 register access */ 36 #define PHY54680E_CL45_REG_READ(_unit, _phy_ctrl, _flags, _dev_addr, _reg_addr, _val) \ 37 _phy_54680e_cl45_reg_read((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 38 (_reg_addr), (_val)) 39 #define PHY54680E_CL45_REG_WRITE(_unit, _phy_ctrl, _flags, \ 40 _dev_addr, _reg_addr, _val) \ 41 _phy_54680e_cl45_reg_write((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 42 (_reg_addr), (_val)) 43 #define PHY54680E_CL45_REG_MODIFY(_unit, _phy_ctrl, _flags, _dev_addr, \ 44 _reg_addr, _val, _mask) \ 45 _phy_54680e_cl45_reg_modify((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 46 (_reg_addr), (_val), (_mask)) 47 48 49 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 50 #define READ_PHY54680_MII_CTRLr(_unit, _phy_ctrl, _val) \ 51 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 52 #define WRITE_PHY54680_MII_CTRLr(_unit, _phy_ctrl, _val) \ 53 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 54 #define MODIFY_PHY54680_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 55 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 56 (_val), (_mask)) 57 58 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 59 #define READ_PHY54680_MII_STATr(_unit, _phy_ctrl, _val) \ 60 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 61 #define WRITE_PHY54680_MII_STATr(_unit, _phy_ctrl, _val) \ 62 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 63 #define MODIFY_PHY54680_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 64 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 65 (_val), (_mask)) 66 67 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 68 #define READ_PHY54680_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 69 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 70 #define WRITE_PHY54680_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 71 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 72 #define MODIFY_PHY54680_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 73 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 74 (_val), (_mask)) 75 76 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 77 #define READ_PHY54680_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 78 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 79 #define WRITE_PHY54680_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 80 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 81 #define MODIFY_PHY54680_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 82 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 83 (_val), (_mask)) 84 85 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 86 #define READ_PHY54680_MII_ANAr(_unit, _phy_ctrl, _val) \ 87 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 88 #define WRITE_PHY54680_MII_ANAr(_unit, _phy_ctrl, _val) \ 89 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 90 #define MODIFY_PHY54680_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 91 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 92 (_val), (_mask)) 93 94 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 95 #define READ_PHY54680_MII_ANPr(_unit, _phy_ctrl, _val) \ 96 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 97 #define WRITE_PHY54680_MII_ANPr(_unit, _phy_ctrl, _val) \ 98 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 99 #define MODIFY_PHY54680_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 100 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 101 (_val), (_mask)) 102 103 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 104 #define READ_PHY54680_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 105 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 106 #define WRITE_PHY54680_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 107 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 108 #define MODIFY_PHY54680_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 109 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 110 (_val), (_mask)) 111 112 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 113 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 114 115 /* 1000BASE-T Control Register (ADDR 09h) */ 116 #define READ_PHY54680_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 117 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 118 #define WRITE_PHY54680_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 119 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 120 #define MODIFY_PHY54680_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 121 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 122 (_val), (_mask)) 123 124 /* 1000BASE-T Status Register (ADDR 0ah) */ 125 #define READ_PHY54680_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 126 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 127 #define WRITE_PHY54680_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 128 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 129 #define MODIFY_PHY54680_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 130 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 131 (_val), (_mask)) 132 133 /* (Addr 0ch-0eh) Reserved (Do not read/write to reserved registers. */ 134 135 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 136 137 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 138 #define READ_PHY54680_MII_ECRr(_unit, _phy_ctrl, _val) \ 139 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 140 #define WRITE_PHY54680_MII_ECRr(_unit, _phy_ctrl, _val) \ 141 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 142 #define MODIFY_PHY54680_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 143 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 144 (_val), (_mask)) 145 146 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 147 #define READ_PHY54680_MII_ESRr(_unit, _phy_ctrl, _val) \ 148 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 149 #define WRITE_PHY54680_MII_ESRr(_unit, _phy_ctrl, _val) \ 150 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 151 #define MODIFY_PHY54680_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 152 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 153 (_val), (_mask)) 154 155 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 156 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 157 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 158 159 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 160 #define READ_PHY54680_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 161 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 162 #define WRITE_PHY54680_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 163 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 164 #define MODIFY_PHY54680_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 165 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 166 (_val), (_mask)) 167 168 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 169 #define READ_PHY54680_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 170 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 171 #define WRITE_PHY54680_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 172 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 173 #define MODIFY_PHY54680_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 174 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 175 (_val), (_mask)) 176 177 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 178 #define READ_PHY54680_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 179 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 180 #define WRITE_PHY54680_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 181 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 182 #define MODIFY_PHY54680_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 183 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 184 (_val), (_mask)) 185 186 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 187 #define READ_PHY54680_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 188 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 189 #define WRITE_PHY54680_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 190 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 191 #define MODIFY_PHY54680_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 192 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 193 (_val), (_mask)) 194 195 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 196 #define READ_PHY54680_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 197 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 198 #define WRITE_PHY54680_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 199 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 200 #define MODIFY_PHY54680_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 201 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 202 (_val), (_mask)) 203 204 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 205 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 206 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 207 208 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 209 #define READ_PHY54680_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 210 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 211 #define WRITE_PHY54680_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 212 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 213 #define MODIFY_PHY54680_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 214 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 215 (_val), (_mask)) 216 217 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 218 #define READ_PHY54680_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 219 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 220 #define WRITE_PHY54680_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 221 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 222 #define MODIFY_PHY54680_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 223 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 224 (_val), (_mask)) 225 226 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 227 #define READ_PHY54680_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 228 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 229 #define WRITE_PHY54680_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 230 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 231 #define MODIFY_PHY54680_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 232 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 233 (_val), (_mask)) 234 #define PHY_54680_SPARE_CTRL3_REG_DLL_AUTO_PWR_DOWN (0x1 << 1) 235 236 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 237 #define READ_PHY54680_LED_STATr(_unit, _phy_ctrl, _val) \ 238 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 239 #define WRITE_PHY54680_LED_STATr(_unit, _phy_ctrl, _val) \ 240 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 241 #define MODIFY_PHY54680_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 242 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 243 (_val), (_mask)) 244 245 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 246 #define READ_PHY54680_LED_CTRLr(_unit, _phy_ctrl, _val) \ 247 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 248 #define WRITE_PHY54680_LED_CTRLr(_unit, _phy_ctrl, _val) \ 249 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 250 #define MODIFY_PHY54680_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 251 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 252 (_val), (_mask)) 253 254 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 255 #define READ_PHY54680_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 256 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 257 #define WRITE_PHY54680_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 258 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 259 #define MODIFY_PHY54680_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 260 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 261 (_val), (_mask)) 262 263 #define PHY_54680_AUTO_PWRDWN_EN (1 << 5) 264 #define PHY_54680_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 265 #define PHY_54680_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 266 #define PHY_54680_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 267 #define PHY_54680_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 268 #define PHY_54680_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 269 270 /* SLED_1 Reg (ADDR 1ch shadow 01011) */ 271 #define READ_PHY54680_SLED_1r(_unit, _phy_ctrl, _val) \ 272 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, (_val)) 273 #define WRITE_PHY54680_SLED_1r(_unit, _phy_ctrl, _val) \ 274 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, (_val)) 275 #define MODIFY_PHY54680_SLED_1r(_unit, _phy_ctrl, _val, _mask) \ 276 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000b, 0x1c, \ 277 (_val), (_mask)) 278 279 /* SLED_2 Reg (ADDR 1ch shadow 01100) */ 280 #define READ_PHY54680_SLED_2r(_unit, _phy_ctrl, _val) \ 281 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, (_val)) 282 #define WRITE_PHY54680_SLED_2r(_unit, _phy_ctrl, _val) \ 283 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, (_val)) 284 #define MODIFY_PHY54680_SLED_2r(_unit, _phy_ctrl, _val, _mask) \ 285 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000c, 0x1c, \ 286 (_val), (_mask)) 287 288 289 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 290 #define READ_PHY54680_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 291 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 292 #define WRITE_PHY54680_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 293 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 294 #define MODIFY_PHY54680_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 295 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 296 (_val), (_mask)) 297 298 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 299 #define READ_PHY54680_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 300 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 301 #define WRITE_PHY54680_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 302 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 303 #define MODIFY_PHY54680_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 304 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 305 (_val), (_mask)) 306 307 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 308 #define READ_PHY54680_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 309 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, (_val)) 310 #define WRITE_PHY54680_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 311 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, (_val)) 312 #define MODIFY_PHY54680_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 313 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, \ 314 (_val), (_mask)) 315 316 /* External SerDes Control Reg (ADDR 1ch shadow 10100) */ 317 #define READ_PHY54680_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 318 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 319 #define WRITE_PHY54680_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 320 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 321 #define MODIFY_PHY54680_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 322 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, \ 323 (_val), (_mask)) 324 325 /* SGMII SLAVE Reg (ADDR 1ch shadow 10101) */ 326 #define READ_PHY54680_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 327 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 328 #define WRITE_PHY54680_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 329 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 330 #define MODIFY_PHY54680_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 331 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, \ 332 (_val), (_mask)) 333 334 /* Misc. 1000BASE-X Control 2 Reg (ADDR 1ch shadow 10110) */ 335 #define READ_PHY54680_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 336 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 337 #define WRITE_PHY54680_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 338 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 339 #define MODIFY_PHY54680_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 340 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 341 (_val), (_mask)) 342 343 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 344 #define READ_PHY54680_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 345 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 346 #define WRITE_PHY54680_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 347 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 348 #define MODIFY_PHY54680_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 349 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 350 (_val), (_mask)) 351 352 /* Auxiliary Control Reg (ADDR 1ch shadow 11011) */ 353 #define READ_PHY54680_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 354 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, (_val)) 355 #define WRITE_PHY54680_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 356 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, (_val)) 357 #define MODIFY_PHY54680_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 358 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, \ 359 (_val), (_mask)) 360 361 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 362 #define READ_PHY54680_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 363 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, (_val)) 364 #define WRITE_PHY54680_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 365 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, (_val)) 366 #define MODIFY_PHY54680_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 367 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, \ 368 (_val), (_mask)) 369 370 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 371 #define READ_PHY54680_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 372 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, (_val)) 373 #define WRITE_PHY54680_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 374 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, (_val)) 375 #define MODIFY_PHY54680_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 376 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, \ 377 (_val), (_mask)) 378 379 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 380 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 381 382 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 383 #define READ_PHY54680_TEST1r(_unit, _phy_ctrl, _val) \ 384 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 385 #define WRITE_PHY54680_TEST1r(_unit, _phy_ctrl, _val) \ 386 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 387 #define MODIFY_PHY54680_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 388 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 389 (_val), (_mask)) 390 391 /* +---------------------+ 392 * | | 393 * | SGMII Registers | 394 * | | 395 * +---------------------+ 396 */ 397 /* SGMII Control Register (Addr 00h) */ 398 #define READ_PHY54680_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 399 PHY54680_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 400 0x0000, 0x00, (_val)) 401 #define WRITE_PHY54680_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 402 PHY54680_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 403 0x0000, 0x00, (_val)) 404 #define MODIFY_PHY54680_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 405 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 406 0x0000, 0x00, (_val), (_mask)) 407 408 /* SGMII Status Register (Addr 01h) */ 409 #define READ_PHY54680_SGMII_STATr(_unit, _phy_ctrl, _val) \ 410 PHY54680_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 411 0x0000, 0x01, (_val)) 412 #define WRITE_PHY54680_SGMII_STATr(_unit, _phy_ctrl, _val) \ 413 PHY54680_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 414 0x0000, 0x01, (_val)) 415 #define MODIFY_PHY54680_SGMII_STATr(_unit, _phy_ctrl, _val, _mask) \ 416 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 417 0x0000, 0x01, (_val), (_mask)) 418 419 /* SGMII Auto-neg Advertise Register (Addr 04h) */ 420 #define READ_PHY54680_SGMII_ANAr(_unit, _phy_ctrl, _val) \ 421 PHY54680_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 422 0x0000, 0x04, (_val)) 423 #define WRITE_PHY54680_SGMII_ANAr(_unit, _phy_ctrl, _val) \ 424 PHY54680_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 425 0x0000, 0x04, (_val)) 426 #define MODIFY_PHY54680_SGMII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 427 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 428 0x0000, 0x04, (_val), (_mask)) 429 430 /* SGMII Auto-neg Link Partner Ability Register (Addr 05h) */ 431 #define READ_PHY54680_SGMII_ANPr(_unit, _phy_ctrl, _val) \ 432 PHY54680_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 433 0x0000, 0x05, (_val)) 434 #define WRITE_PHY54680_SGMII_ANPr(_unit, _phy_ctrl, _val) \ 435 PHY54680_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 436 0x0000, 0x05, (_val)) 437 #define MODIFY_PHY54680_SGMII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 438 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 439 0x0000, 0x05, (_val), (_mask)) 440 441 /* +-------------------------+ 442 * | | 443 * | Expansion Registers | 444 * | | 445 * +-------------------------+ 446 */ 447 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 448 #define READ_PHY54680_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 449 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F00, 0x15, (_val)) 450 #define WRITE_PHY54680_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 451 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F00, \ 452 0x15, (_val)) 453 #define MODIFY_PHY54680_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 454 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F00, \ 455 0x15, (_val), (_mask)) 456 457 /* Multicolor LED Selector Register (Addr 04h) */ 458 #define READ_PHY54680_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 459 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F04, 0x15, (_val)) 460 #define WRITE_PHY54680_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 461 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F04, \ 462 0x15, (_val)) 463 #define MODIFY_PHY54680_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 464 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F04, \ 465 0x15, (_val), (_mask)) 466 467 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 468 #define READ_PHY54680_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 469 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F05, 0x15, (_val)) 470 #define WRITE_PHY54680_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 471 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F05, \ 472 0x15, (_val)) 473 #define MODIFY_PHY54680_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 474 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F05, \ 475 0x15, (_val), (_mask)) 476 477 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 478 #define READ_PHY54680_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 479 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F06, 0x15, (_val)) 480 #define WRITE_PHY54680_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 481 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F06, \ 482 0x15, (_val)) 483 #define MODIFY_PHY54680_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 484 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F06, \ 485 0x15, (_val), (_mask)) 486 487 /* 100Base-FX Far End Fault egister (Addr 07h) */ 488 #define READ_PHY54680_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val) \ 489 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F07, 0x15, (_val)) 490 #define WRITE_PHY54680_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val) \ 491 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F07, \ 492 0x15, (_val)) 493 #define MODIFY_PHY54680_EXP_100FX_FAR_END_FAULTr(_unit, _phy_ctrl, _val, _mask) \ 494 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F07, \ 495 0x15, (_val), (_mask)) 496 497 /* Port Interrupt Status Register (Addr 0bh) */ 498 #define READ_PHY54680_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 499 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F0B, 0x15, (_val)) 500 #define WRITE_PHY54680_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 501 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F0B, \ 502 0x15, (_val)) 503 #define MODIFY_PHY54680_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val, _mask) \ 504 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F0B, \ 505 0x15, (_val), (_mask)) 506 /* Cable Diag Control Register (Addr 10h) */ 507 #define READ_PHY54680_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val) \ 508 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F10, 0x15, (_val)) 509 #define WRITE_PHY54680_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val) \ 510 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F10, \ 511 0x15, (_val)) 512 #define MODIFY_PHY54680_EXP_CABLE_DIAG_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 513 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F10, \ 514 0x15, (_val), (_mask)) 515 516 /* Cable Diag Result Register (Addr 11h) */ 517 #define READ_PHY54680_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val) \ 518 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F11, 0x15, (_val)) 519 #define WRITE_PHY54680_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val) \ 520 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F11, \ 521 0x15, (_val)) 522 #define MODIFY_PHY54680_EXP_CABLE_DIAG_RESULTr(_unit, _phy_ctrl, _val, _mask) \ 523 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F11, \ 524 0x15, (_val), (_mask)) 525 526 /* Cable Diag Length Register (Addr 12h) */ 527 #define READ_PHY54680_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val) \ 528 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F12, 0x15, (_val)) 529 #define WRITE_PHY54680_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val) \ 530 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F12, \ 531 0x15, (_val)) 532 #define MODIFY_PHY54680_EXP_CABLE_DIAG_LENGTHr(_unit, _phy_ctrl, _val, _mask) \ 533 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F12, \ 534 0x15, (_val), (_mask)) 535 536 537 /* Operating Mode Status Register (Addr 42h) */ 538 #define READ_PHY54680_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 539 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F42, 0x15, (_val)) 540 #define WRITE_PHY54680_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 541 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F42, \ 542 0x15, (_val)) 543 #define MODIFY_PHY54680_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val, _mask) \ 544 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F42, \ 545 0x15, (_val), (_mask)) 546 547 /* SGMII/Lineside Loopback Control Register (Addr 44h) */ 548 #define READ_PHY54680_EXP_SGMII_LINESIDE_LOOPBACK_CTRLr(_unit, _phy_ctrl, _val) \ 549 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, (_val)) 550 #define WRITE_PHY54680_EXP_SGMII_LINESIDE_LOOPBACK_CTRLr(_unit, _phy_ctrl, _val) \ 551 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, (_val)) 552 #define MODIFY_PHY54680_EXP_SGMII_LINESIDE_LOOPBACK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 553 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, \ 554 (_val), (_mask)) 555 556 /* SerDes/SGMII Control Register (Addr 52h) */ 557 #define READ_PHY54680_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 558 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 559 #define WRITE_PHY54680_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 560 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 561 #define MODIFY_PHY54680_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 562 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, \ 563 (_val), (_mask)) 564 565 566 /* EEE related */ 567 568 /* Auto EEE MII_Buffer CNTL/Status 2 Register (Addr AEh) */ 569 #define READ_PHY54680_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 570 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAE, 0x15, (_val)) 571 #define WRITE_PHY54680_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 572 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 573 0x15, (_val)) 574 #define MODIFY_PHY54680_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 575 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 576 0x15, (_val), (_mask)) 577 578 /* Auto EEE MII_Buffer CNTL/Status 1 Register (Addr AFh) */ 579 #define READ_PHY54680_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 580 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAF, 0x15, (_val)) 581 #define WRITE_PHY54680_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 582 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 583 0x15, (_val)) 584 #define MODIFY_PHY54680_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 585 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 586 0x15, (_val), (_mask)) 587 588 /* EEE Statistics related */ 589 /* Local LPI request Counter Reg (Addr ach) */ 590 #define READ_PHY54680_EXP_EEE_TX_EVENTSr(_unit, _phy_ctrl, _val) \ 591 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAC, 0x15, (_val)) 592 593 /* Remote LPI request Counter Reg (Addr adh) */ 594 #define READ_PHY54680_EXP_EEE_RX_EVENTSr(_unit, _phy_ctrl, _val) \ 595 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAD, 0x15, (_val)) 596 597 /* Statistic Timer_12_hours_lpi remote Reg (Addr aah) */ 598 #define READ_PHY54680_EXP_EEE_TX_DURATIONr(_unit, _phy_ctrl, _val) \ 599 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAA, 0x15, (_val)) 600 601 /* Statistic Timer_12_hours_lpi_local Local Reg (Addr abh) */ 602 #define READ_PHY54680_EXP_EEE_RX_DURATIONr(_unit, _phy_ctrl, _val) \ 603 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAB, 0x15, (_val)) 604 605 /* IEEE 1588 read start/end control Register (Addr f3h) */ 606 #define READ_PHY54680_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 607 PHY54680_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 608 #define WRITE_PHY54680_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 609 PHY54680_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 610 #define MODIFY_PHY54680_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 611 PHY54680_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, \ 612 (_val), (_mask)) 613 614 /* EEE Capability Register */ 615 #define READ_PHY54680_EEE_CAPr(_unit, _phy_ctrl, _val) \ 616 PHY54680E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x3, 0x14, _val) 617 618 /* EEE Advertisement Register */ 619 #define READ_PHY54680_EEE_ADVr(_unit, _phy_ctrl, _val) \ 620 PHY54680E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 621 #define WRITE_PHY54680_EEE_ADVr(_unit, _phy_ctrl, _val) \ 622 PHY54680E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 623 #define MODIFY_PHY54680_EEE_ADVr(_unit, _phy_ctrl, _val, _mask) \ 624 PHY54680E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val, _mask) 625 626 #define READ_PHY54680_EEE_803Dr(_unit, _phy_ctrl, _val) \ 627 PHY54680E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 628 #define WRITE_PHY54680_EEE_803Dr(_unit, _phy_ctrl, _val) \ 629 PHY54680E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 630 #define MODIFY_PHY54680_EEE_803Dr(_unit, _phy_ctrl, _val, _mask) \ 631 PHY54680E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val, _mask) 632 633 /* EEE Resolution Status Register */ 634 #define READ_PHY54680_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 635 PHY54680E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 636 #define WRITE_PHY54680_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 637 PHY54680E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 638 #define MODIFY_PHY54680_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val, _mask) \ 639 PHY54680E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val, _mask) 640 641 #define READ_PHY54680_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 642 PHY54680E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 643 #define WRITE_PHY54680_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 644 PHY54680E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 645 #define MODIFY_PHY54680_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val, _mask) \ 646 PHY54680E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val, _mask) 647 648 /* EEE TEST Control Register B*/ 649 #define READ_PHY54680_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 650 PHY54680E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 651 #define WRITE_PHY54680_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 652 PHY54680E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 653 #define MODIFY_PHY54680_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val, _mask) \ 654 PHY54680E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val, _mask) 655 656 typedef struct { 657 uint32 flags; 658 uint16 phy_id_orig; 659 uint16 phy_id_base; /* port 0 addr */ 660 uint16 phy_slice; 661 } PHY54680_DEV_DESC_t; 662 663 #define PHY54680_DEV_PHY_ID_ORIG(_pc) (((PHY54680_DEV_DESC_t *)((_pc) + 1))->phy_id_orig) 664 #define PHY54680_DEV_PHY_ID_BASE(_pc) (((PHY54680_DEV_DESC_t *)((_pc) + 1))->phy_id_base) 665 #define PHY54680_DEV_PHY_SLICE(_pc) (((PHY54680_DEV_DESC_t *)((_pc) + 1))->phy_slice) 666 #define PHY54680_FLAGS(_pc) (((PHY54680_DEV_DESC_t *)((_pc) + 1))->flags) 667 #define PHY54680_DEV_PHY_SLICE_MASK 0x07 668 #define PHY54680_PHYA_REV (1U << 0) 669 670 #define PHY54680_DEV_SET_BASE_ADDR(_pc) \ 671 PHY54680_DEV_PHY_ID_BASE(_pc) = (PHY54680_FLAGS((_pc)) & PHY54680_PHYA_REV) ?\ 672 PHY54680_DEV_PHY_ID_ORIG(_pc) + PHY54680_DEV_PHY_SLICE(_pc) : \ 673 PHY54680_DEV_PHY_ID_ORIG(_pc) - PHY54680_DEV_PHY_SLICE(_pc) 674 675 #define PHY54680_SLICE_ADDR(_pc, _slice) \ 676 (PHY54680_FLAGS((_pc)) & PHY54680_PHYA_REV) ? (PHY54680_DEV_PHY_ID_BASE(_pc) - (_slice)) : \ 677 (PHY54680_DEV_PHY_ID_BASE(_pc) + (_slice)) 678 679 #endif /* _PHY54680_H_ */