phy54640.h (55981B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy54640.h 8 * 9 * This driver applies to BCM54640. 10 * It support driving Copper or SERDES interfaces. 11 */ 12 13 #ifndef _PHY54640_H_ 14 #define _PHY54640_H_ 15 16 #include <soc/phy.h> 17 18 /* PHY register access */ 19 #define PHY54640_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 20 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 21 (_reg_addr), (_val)) 22 #define PHY54640_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHY54640_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, \ 26 _val, _mask) \ 27 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val), (_mask)) 29 30 /* Clause 45 Registers access using Clause 22 register access */ 31 #define PHY54640E_CL45_REG_READ(_unit, _phy_ctrl, _flags, _dev_addr, _reg_addr, _val) \ 32 _phy_54640e_cl45_reg_read((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 33 (_reg_addr), (_val)) 34 #define PHY54640E_CL45_REG_WRITE(_unit, _phy_ctrl, _flags, \ 35 _dev_addr, _reg_addr, _val) \ 36 _phy_54640e_cl45_reg_write((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 37 (_reg_addr), (_val)) 38 #define PHY54640E_CL45_REG_MODIFY(_unit, _phy_ctrl, _flags, _dev_addr, \ 39 _reg_addr, _val, _mask) \ 40 _phy_54640e_cl45_reg_modify((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 41 (_reg_addr), (_val), (_mask)) 42 43 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 44 #define READ_PHY54640_MII_CTRLr(_unit, _phy_ctrl, _val) \ 45 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 46 #define WRITE_PHY54640_MII_CTRLr(_unit, _phy_ctrl, _val) \ 47 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 48 #define MODIFY_PHY54640_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 49 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 50 (_val), (_mask)) 51 52 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 53 #define READ_PHY54640_MII_STATr(_unit, _phy_ctrl, _val) \ 54 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 55 #define WRITE_PHY54640_MII_STATr(_unit, _phy_ctrl, _val) \ 56 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 57 #define MODIFY_PHY54640_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 58 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 59 (_val), (_mask)) 60 61 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 62 #define READ_PHY54640_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 63 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 64 #define WRITE_PHY54640_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 65 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 66 #define MODIFY_PHY54640_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 67 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 68 (_val), (_mask)) 69 70 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 71 #define READ_PHY54640_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 72 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 73 #define WRITE_PHY54640_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 74 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 75 #define MODIFY_PHY54640_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 76 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 77 (_val), (_mask)) 78 79 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 80 #define READ_PHY54640_MII_ANAr(_unit, _phy_ctrl, _val) \ 81 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 82 #define WRITE_PHY54640_MII_ANAr(_unit, _phy_ctrl, _val) \ 83 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 84 #define MODIFY_PHY54640_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 85 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 86 (_val), (_mask)) 87 88 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 89 #define READ_PHY54640_MII_ANPr(_unit, _phy_ctrl, _val) \ 90 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 91 #define WRITE_PHY54640_MII_ANPr(_unit, _phy_ctrl, _val) \ 92 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 93 #define MODIFY_PHY54640_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 94 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 95 (_val), (_mask)) 96 97 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 98 #define READ_PHY54640_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 99 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 100 #define WRITE_PHY54640_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 101 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 102 #define MODIFY_PHY54640_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 103 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 104 (_val), (_mask)) 105 106 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 107 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 108 109 /* 1000BASE-T Control Register (ADDR 09h) */ 110 #define READ_PHY54640_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 111 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 112 #define WRITE_PHY54640_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 113 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 114 #define MODIFY_PHY54640_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 115 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 116 (_val), (_mask)) 117 118 /* 1000BASE-T Status Register (ADDR 0ah) */ 119 #define READ_PHY54640_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 120 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 121 #define WRITE_PHY54640_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 122 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 123 #define MODIFY_PHY54640_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 124 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 125 (_val), (_mask)) 126 127 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 128 129 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 130 #define READ_PHY54640_MII_ECRr(_unit, _phy_ctrl, _val) \ 131 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 132 #define WRITE_PHY54640_MII_ECRr(_unit, _phy_ctrl, _val) \ 133 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 134 #define MODIFY_PHY54640_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 135 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 136 (_val), (_mask)) 137 138 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 139 #define READ_PHY54640_MII_ESRr(_unit, _phy_ctrl, _val) \ 140 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 141 #define WRITE_PHY54640_MII_ESRr(_unit, _phy_ctrl, _val) \ 142 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 143 #define MODIFY_PHY54640_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 144 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 145 (_val), (_mask)) 146 147 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 148 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 149 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 150 151 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 152 #define READ_PHY54640_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 153 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 154 #define WRITE_PHY54640_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 155 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 156 #define MODIFY_PHY54640_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 157 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 158 (_val), (_mask)) 159 160 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 161 #define READ_PHY54640_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 162 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 163 #define WRITE_PHY54640_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 164 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 165 #define MODIFY_PHY54640_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 166 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 167 (_val), (_mask)) 168 169 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 170 #define READ_PHY54640_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 171 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 172 #define WRITE_PHY54640_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 173 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 174 #define MODIFY_PHY54640_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 175 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 176 (_val), (_mask)) 177 178 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 179 #define READ_PHY54640_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 180 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 181 #define WRITE_PHY54640_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 182 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 183 #define MODIFY_PHY54640_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 184 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 185 (_val), (_mask)) 186 187 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 188 #define READ_PHY54640_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 189 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 190 #define WRITE_PHY54640_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 191 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 192 #define MODIFY_PHY54640_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 193 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 194 (_val), (_mask)) 195 196 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 197 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 198 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 199 200 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 201 #define READ_PHY54640_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 202 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 203 #define WRITE_PHY54640_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 204 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 205 #define MODIFY_PHY54640_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 206 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 207 (_val), (_mask)) 208 209 /* 1000BASE-T/100BASE-TX/10BASE-T Clk Alignment Ctrl (ADDR 1ch shadow 00011) */ 210 #define READ_PHY54640_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 211 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 212 #define WRITE_PHY54640_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 213 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 214 #define MODIFY_PHY54640_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 215 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, \ 216 (_val), (_mask)) 217 218 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 219 #define READ_PHY54640_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 220 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 221 #define WRITE_PHY54640_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 222 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 223 #define MODIFY_PHY54640_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 224 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 225 (_val), (_mask)) 226 227 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 228 #define READ_PHY54640_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 229 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 230 #define WRITE_PHY54640_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 231 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 232 #define MODIFY_PHY54640_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 233 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 234 (_val), (_mask)) 235 236 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 237 #define READ_PHY54640_LED_STATr(_unit, _phy_ctrl, _val) \ 238 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 239 #define WRITE_PHY54640_LED_STATr(_unit, _phy_ctrl, _val) \ 240 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 241 #define MODIFY_PHY54640_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 242 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 243 (_val), (_mask)) 244 245 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 246 #define READ_PHY54640_LED_CTRLr(_unit, _phy_ctrl, _val) \ 247 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 248 #define WRITE_PHY54640_LED_CTRLr(_unit, _phy_ctrl, _val) \ 249 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 250 #define MODIFY_PHY54640_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 251 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 252 (_val), (_mask)) 253 254 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 255 #define READ_PHY54640_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 256 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 257 #define WRITE_PHY54640_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 258 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 259 #define MODIFY_PHY54640_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 260 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 261 (_val), (_mask)) 262 263 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 264 #define READ_PHY54640_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 265 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 266 #define WRITE_PHY54640_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 267 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 268 #define MODIFY_PHY54640_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 269 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 270 (_val), (_mask)) 271 272 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 273 #define READ_PHY54640_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 274 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 275 #define WRITE_PHY54640_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 276 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 277 #define MODIFY_PHY54640_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 278 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 279 (_val), (_mask)) 280 281 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 282 #define READ_PHY54640_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 283 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 284 #define WRITE_PHY54640_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 285 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 286 #define MODIFY_PHY54640_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 287 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, \ 288 (_val), (_mask)) 289 290 /* SerDes 100BASE-FX Status Reg (ADDR 1ch shadow 10001) */ 291 #define READ_PHY54640_100FX_STATr(_unit, _phy_ctrl, _val) \ 292 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 293 #define WRITE_PHY54640_100FX_STATr(_unit, _phy_ctrl, _val) \ 294 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 295 #define MODIFY_PHY54640_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 296 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, \ 297 (_val), (_mask)) 298 299 /* SerDes 100BASE-FX Control Reg (ADDR 1ch shadow 10011) */ 300 #define READ_PHY54640_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 301 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 302 #define WRITE_PHY54640_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 303 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 304 #define MODIFY_PHY54640_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 305 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, \ 306 (_val), (_mask)) 307 308 /* SERDES 100-FX Control Register (ADDR 1ch shadow 10011) */ 309 #define READ_PHY54640_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 310 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 311 #define WRITE_PHY54640_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 312 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 313 #define MODIFY_PHY54640_SERDES_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 314 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, \ 315 (_val), (_mask)) 316 317 /* External SerDes Control Reg (ADDR 1ch shadow 10100) */ 318 #define READ_PHY54640_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 319 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 320 #define WRITE_PHY54640_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 321 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 322 #define MODIFY_PHY54640_EXT_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 323 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, \ 324 (_val), (_mask)) 325 326 /* External Serdes Control Reg., DIGX_SHD_1C_14, RDB_0x234 */ 327 #define PHY_BCM54640_EXT_SERDES_REG_OFFSET 0x234 328 #define PHY_BCM54640_EXT_SERDES_AUTO_FX (1 << 6) 329 #define PHY_BCM54640_EXT_SERDES_FX_FD (1 << 5) 330 #define PHY_BCM54640_EXT_SERDES_FX (1 << 4) 331 #define PHY_BCM54640_EXT_SERDES_LED (1 << 3) 332 #define PHY_BCM54640_EXT_SEL_SYNC_ST (1 << 2) 333 #define PHY_BCM54640_EXT_SELECT_SD (1 << 1) 334 #define PHY_BCM54640_EXT_SERDES_SEL (1 << 0) 335 #define PHY_BCM54640_EXT_SERDES_FX_MASK (PHY_BCM54640_EXT_SERDES_FX | \ 336 PHY_BCM54640_EXT_SERDES_AUTO_FX) 337 338 339 /* SGMII Slave Reg (ADDR 1ch shadow 10101) */ 340 #define READ_PHY54640_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 341 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 342 #define WRITE_PHY54640_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 343 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 344 #define MODIFY_PHY54640_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 345 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, \ 346 (_val), (_mask)) 347 348 /* Misc. 1000BASE-X Control 2 Reg (ADDR 1ch shadow 10110) */ 349 #define READ_PHY54640_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 350 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 351 #define WRITE_PHY54640_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 352 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 353 #define MODIFY_PHY54640_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 354 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 355 (_val), (_mask)) 356 357 /* Misc 1000BASE-X Control (ADDR 1ch shadow 10111) */ 358 #define READ_PHY54640_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val) \ 359 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 360 #define WRITE_PHY54640_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val) \ 361 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 362 #define MODIFY_PHY54640_MISC_1000X_CONTROLr(_unit, _phy_ctrl, _val, _mask) \ 363 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, \ 364 (_val), (_mask)) 365 366 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 367 #define READ_PHY54640_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 368 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 369 #define WRITE_PHY54640_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 370 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 371 #define MODIFY_PHY54640_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 372 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 373 (_val), (_mask)) 374 375 /* 1000BASE-X Auto-neg Debug Reg (ADDR 1ch shadow 11010) */ 376 #define READ_PHY54640_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 377 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 378 #define WRITE_PHY54640_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 379 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 380 #define MODIFY_PHY54640_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 381 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, \ 382 (_val), (_mask)) 383 384 /* Auxiliary Control Reg (ADDR 1ch shadow 11011) */ 385 #define READ_PHY54640_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 386 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 387 #define WRITE_PHY54640_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 388 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 389 #define MODIFY_PHY54640_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 390 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, \ 391 (_val), (_mask)) 392 393 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 394 #define READ_PHY54640_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 395 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 396 #define WRITE_PHY54640_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 397 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 398 #define MODIFY_PHY54640_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 399 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, \ 400 (_val), (_mask)) 401 402 /* Misc 1000BASE-X Status Reg (ADDR 1ch shadow 11101) */ 403 #define READ_PHY54640_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 404 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 405 #define WRITE_PHY54640_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 406 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 407 #define MODIFY_PHY54640_MISC_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 408 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, \ 409 (_val), (_mask)) 410 411 /* Copper/Fiber Auto-Detect Medium Reg (ADDR 1ch shadow 11110) */ 412 #define READ_PHY54640_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 413 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 414 #define WRITE_PHY54640_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 415 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 416 #define MODIFY_PHY54640_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val, _mask) \ 417 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, \ 418 (_val), (_mask)) 419 420 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 421 #define READ_PHY54640_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 422 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 423 #define WRITE_PHY54640_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 424 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 425 #define MODIFY_PHY54640_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 426 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, \ 427 (_val), (_mask)) 428 429 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 430 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 431 432 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 433 #define READ_PHY54640_TEST1r(_unit, _phy_ctrl, _val) \ 434 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 435 #define WRITE_PHY54640_TEST1r(_unit, _phy_ctrl, _val) \ 436 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 437 #define MODIFY_PHY54640_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 438 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 439 (_val), (_mask)) 440 441 442 /* +------------------------------+ 443 * | | 444 * | Primary SerDes Registers | 445 * | | 446 * +------------------------------+ 447 */ 448 /* 1000BASE-X MII Control Register (Addr 00h) */ 449 #define READ_PHY54640_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 450 PHY54640_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 451 0x0000, 0x00, (_val)) 452 #define WRITE_PHY54640_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 453 PHY54640_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 454 0x0000, 0x00, (_val)) 455 #define MODIFY_PHY54640_1000X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 456 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 457 0x0000, 0x00, (_val), (_mask)) 458 459 /* 1000BASE-X MII Status Register (Addr 01h) */ 460 #define READ_PHY54640_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 461 PHY54640_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 462 0x0000, 0x01, (_val)) 463 #define WRITE_PHY54640_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 464 PHY54640_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 465 0x0000, 0x01, (_val)) 466 #define MODIFY_PHY54640_1000X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 467 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 468 0x0000, 0x01, (_val), (_mask)) 469 470 /* 1000BASE-X MII Auto-neg Advertise Register (Addr 04h) */ 471 #define READ_PHY54640_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 472 PHY54640_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 473 0x0000, 0x04, (_val)) 474 #define WRITE_PHY54640_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 475 PHY54640_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 476 0x0000, 0x04, (_val)) 477 #define MODIFY_PHY54640_1000X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 478 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 479 0x0000, 0x04, (_val), (_mask)) 480 481 /* 1000BASE-X MII Auto-neg Link Partner Ability Register (Addr 05h) */ 482 #define READ_PHY54640_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 483 PHY54640_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 484 0x0000, 0x05, (_val)) 485 #define WRITE_PHY54640_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 486 PHY54640_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 487 0x0000, 0x05, (_val)) 488 #define MODIFY_PHY54640_1000X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 489 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 490 0x0000, 0x05, (_val), (_mask)) 491 492 /* 1000BASE-X MII Auto-neg Extended Status Register (Addr 06h) */ 493 #define READ_PHY54640_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 494 PHY54640_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 495 0x0000, 0x06, (_val)) 496 #define WRITE_PHY54640_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 497 PHY54640_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 498 0x0000, 0x06, (_val)) 499 #define MODIFY_PHY54640_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 500 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 501 0x0000, 0x06, (_val), (_mask)) 502 503 /* 1000BASE-X MII IEEE Extended Status Register (Addr 0fh) */ 504 #define READ_PHY54640_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 505 PHY54640_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 506 0x0000, 0x0f, (_val)) 507 #define WRITE_PHY54640_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 508 PHY54640_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 509 0x0000, 0x0f, (_val)) 510 #define MODIFY_PHY54640_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 511 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 512 0x0000, 0x0f, (_val), (_mask)) 513 514 /* +-------------------------+ 515 * | | 516 * | Expansion Registers | 517 * | | 518 * +-------------------------+ 519 */ 520 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 521 #define READ_PHY54640_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 522 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 523 #define WRITE_PHY54640_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 524 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 525 #define MODIFY_PHY54640_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 526 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, \ 527 (_val), (_mask)) 528 529 /* Expansion Interrupt Status Register (Addr 01h) */ 530 #define READ_PHY54640_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 531 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 532 #define WRITE_PHY54640_EXP_r(_unit, _phy_ctrl, _val) \ 533 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 534 #define MODIFY_PHY54640_EXP_r(_unit, _phy_ctrl, _val, _mask) \ 535 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, \ 536 (_val), (_mask)) 537 538 /* Expansion Interrupt Mask Register (Addr 02h) */ 539 #define READ_PHY54640_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 540 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 541 #define WRITE_PHY54640_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 542 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 543 #define MODIFY_PHY54640_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 544 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, \ 545 (_val), (_mask)) 546 547 /* Multicolor LED Selector Register (Addr 04h) */ 548 #define READ_PHY54640_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 549 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 550 #define WRITE_PHY54640_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 551 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 552 #define MODIFY_PHY54640_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 553 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, \ 554 (_val), (_mask)) 555 556 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 557 #define READ_PHY54640_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 558 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 559 #define WRITE_PHY54640_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 560 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 561 #define MODIFY_PHY54640_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 562 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, \ 563 (_val), (_mask)) 564 565 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 566 #define READ_PHY54640_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 567 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 568 #define WRITE_PHY54640_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 569 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 570 #define MODIFY_PHY54640_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 571 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, \ 572 (_val), (_mask)) 573 574 /* 10BT Controls Register (Addr 08h) */ 575 #define READ_PHY54640_10BT_CTRLr(_unit, _phy_ctrl, _val) \ 576 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, (_val)) 577 #define WRITE_PHY54640_10BT_CTRLr(_unit, _phy_ctrl, _val) \ 578 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, (_val)) 579 #define MODIFY_PHY54640_10BT_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 580 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f08, 0x15, \ 581 (_val), (_mask)) 582 583 /* Operating Mode Status Register (Addr 42h) */ 584 #define READ_PHY54640_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 585 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 586 #define WRITE_PHY54640_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 587 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 588 #define MODIFY_PHY54640_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val, _mask) \ 589 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, \ 590 (_val), (_mask)) 591 592 /* SerDes/SGMII Control Register (Addr 50h) */ 593 #define READ_PHY54640_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val) \ 594 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, (_val)) 595 #define WRITE_PHY54640_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val) \ 596 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, (_val)) 597 #define MODIFY_PHY54640_EXP_SERDES_SGMII_RX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 598 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f50, 0x15, \ 599 (_val), (_mask)) 600 601 /* SerDes/SGMII Control Register (Addr 52h) */ 602 #define READ_PHY54640_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 603 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 604 #define WRITE_PHY54640_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 605 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 606 #define MODIFY_PHY54640_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 607 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, \ 608 (_val), (_mask)) 609 610 /* +--------------------------------+ 611 * | | 612 * | Secondary SerDes Registers | 613 * | | 614 * +--------------------------------+ 615 */ 616 /* 1000BASE-X Control Register (Addr 00h) */ 617 #define READ_PHY54640_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 618 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, (_val)) 619 #define WRITE_PHY54640_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 620 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, (_val)) 621 #define MODIFY_PHY54640_2ND_SERDES_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 622 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e00, 0x15, \ 623 (_val), (_mask)) 624 625 /* 1000BASE-X Status Register (Addr 01h) */ 626 #define READ_PHY54640_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val) \ 627 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, (_val)) 628 #define WRITE_PHY54640_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val) \ 629 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, (_val)) 630 #define MODIFY_PHY54640_2ND_SERDES_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 631 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e01, 0x15, \ 632 (_val), (_mask)) 633 634 /* Auto-neg Advertise Register (Addr 04h) */ 635 #define READ_PHY54640_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val) \ 636 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, (_val)) 637 #define WRITE_PHY54640_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val) \ 638 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, (_val)) 639 #define MODIFY_PHY54640_2ND_SERDES_ANAr(_unit, _phy_ctrl, _val, _mask) \ 640 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e04, 0x15, \ 641 (_val), (_mask)) 642 643 /* 1000BASE-X Auto-neg Link Partner Ability Register (Addr 05h) */ 644 #define READ_PHY54640_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val) \ 645 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, (_val)) 646 #define WRITE_PHY54640_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val) \ 647 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, (_val)) 648 #define MODIFY_PHY54640_2ND_SERDES_ANPr(_unit, _phy_ctrl, _val, _mask) \ 649 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e05, 0x15, \ 650 (_val), (_mask)) 651 652 /* 1000BASE-X Auto-neg Secondary SerDes Register (Addr 06h) */ 653 #define READ_PHY54640_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val) \ 654 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, (_val)) 655 #define WRITE_PHY54640_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val) \ 656 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, (_val)) 657 #define MODIFY_PHY54640_2ND_SERDES_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 658 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e06, 0x15, \ 659 (_val), (_mask)) 660 661 /* 1000BASE-X Auto-neg Next Page Transmit Register (Addr 07h) */ 662 #define READ_PHY54640_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 663 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, (_val)) 664 #define WRITE_PHY54640_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 665 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, (_val)) 666 #define MODIFY_PHY54640_2ND_SERDES_AN_NXT_PAGEr(_unit, _phy_ctrl, _val, _mask) \ 667 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e07, 0x15, \ 668 (_val), (_mask)) 669 670 /* 1000BASE-X Auto-neg Link Partner Next Page Register (Addr 08h) */ 671 #define READ_PHY54640_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 672 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, (_val)) 673 #define WRITE_PHY54640_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val) \ 674 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, (_val)) 675 #define MODIFY_PHY54640_2ND_SERDES_ANP_NXT_PAGEr(_unit, _phy_ctrl, _val, _mask) \ 676 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e08, 0x15, \ 677 (_val), (_mask)) 678 679 /* 1000BASE-X Extended Status Register (Addr 0fh) */ 680 #define READ_PHY54640_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val) \ 681 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, (_val)) 682 #define WRITE_PHY54640_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val) \ 683 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, (_val)) 684 #define MODIFY_PHY54640_2ND_SERDES_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 685 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e0f, 0x15, \ 686 (_val), (_mask)) 687 688 /* Misc 1 Register (Addr 10h) */ 689 #define READ_PHY54640_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val) \ 690 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, (_val)) 691 #define WRITE_PHY54640_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val) \ 692 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, (_val)) 693 #define MODIFY_PHY54640_2ND_SERDES_MISC1r(_unit, _phy_ctrl, _val, _mask) \ 694 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e10, 0x15, \ 695 (_val), (_mask)) 696 697 /* 100BASE-FX Status Register (Addr 11h) */ 698 #define READ_PHY54640_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val) \ 699 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, (_val)) 700 #define WRITE_PHY54640_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val) \ 701 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, (_val)) 702 #define MODIFY_PHY54640_2ND_SERDES_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 703 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e11, 0x15, \ 704 (_val), (_mask)) 705 706 /* 100BASE-FX Test Register (Addr 12h) */ 707 #define READ_PHY54640_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val) \ 708 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, (_val)) 709 #define WRITE_PHY54640_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val) \ 710 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, (_val)) 711 #define MODIFY_PHY54640_2ND_SERDES_100FX_TESTr(_unit, _phy_ctrl, _val, _mask) \ 712 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e12, 0x15, \ 713 (_val), (_mask)) 714 715 /* Packet Counter Register (Addr 13h) */ 716 #define READ_PHY54640_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val) \ 717 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, (_val)) 718 #define WRITE_PHY54640_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val) \ 719 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, (_val)) 720 #define MODIFY_PHY54640_2ND_SERDES_PACKET_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 721 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e13, 0x15, \ 722 (_val), (_mask)) 723 724 /* Error Counter Register (Addr 14h) */ 725 #define READ_PHY54640_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 726 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, (_val)) 727 #define WRITE_PHY54640_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 728 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, (_val)) 729 #define MODIFY_PHY54640_2ND_SERDES_ERR_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 730 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e14, 0x15, \ 731 (_val), (_mask)) 732 733 /* SGMII Slave Register (Addr 15h) */ 734 #define READ_PHY54640_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 735 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, (_val)) 736 #define WRITE_PHY54640_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 737 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, (_val)) 738 #define MODIFY_PHY54640_2ND_SERDES_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 739 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e15, 0x15, \ 740 (_val), (_mask)) 741 742 /* Secondary SerDes Control Register (Addr 16h) */ 743 #define READ_PHY54640_EXP_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 744 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, (_val)) 745 #define WRITE_PHY54640_EXP_2ND_SERDES_CTRL_SLAVEr(_unit, _phy_ctrl, _val) \ 746 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, (_val)) 747 #define MODIFY_PHY54640_EXP_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 748 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e16, 0x15, \ 749 (_val), (_mask)) 750 751 /* Misc 1000BASE-X Control 2 Register (Addr 17h) */ 752 #define READ_PHY54640_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 753 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, (_val)) 754 #define WRITE_PHY54640_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val) \ 755 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, (_val)) 756 #define MODIFY_PHY54640_2ND_SERDES_MISC_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 757 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e17, 0x15, \ 758 (_val), (_mask)) 759 760 /* Misc 1000BASE-X Control 3 Register (Addr 18h) */ 761 #define READ_PHY54640_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 762 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, (_val)) 763 #define WRITE_PHY54640_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val) \ 764 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, (_val)) 765 #define MODIFY_PHY54640_2ND_SERDES_MISC_CTRL3r(_unit, _phy_ctrl, _val, _mask) \ 766 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e18, 0x15, \ 767 (_val), (_mask)) 768 769 /* Auto-neg 1000BASE-X Debug Register (Addr 1ah) */ 770 #define READ_PHY54640_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 771 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, (_val)) 772 #define WRITE_PHY54640_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 773 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, (_val)) 774 #define MODIFY_PHY54640_2ND_SERDES_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 775 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1a, 0x15, \ 776 (_val), (_mask)) 777 778 /* Secondary SerDes Auxiliary 1000BASE-X Control Register (Addr 1bh) */ 779 #define READ_PHY54640_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 780 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, (_val)) 781 #define WRITE_PHY54640_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 782 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, (_val)) 783 #define MODIFY_PHY54640_2ND_SERDES_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 784 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1b, 0x15, \ 785 (_val), (_mask)) 786 787 /* Auxilary 1000BASE-X Status Register (Addr 1ch) */ 788 #define READ_PHY54640_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val) \ 789 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, (_val)) 790 #define WRITE_PHY54640_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val) \ 791 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, (_val)) 792 #define MODIFY_PHY54640_2ND_SERDES_AUX_STATr(_unit, _phy_ctrl, _val, _mask) \ 793 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1c, 0x15, \ 794 (_val), (_mask)) 795 796 /* Misc 1000BASE-X Status Register (Addr 1dh) */ 797 #define READ_PHY54640_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val) \ 798 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, (_val)) 799 #define WRITE_PHY54640_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val) \ 800 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, (_val)) 801 #define MODIFY_PHY54640_2ND_SERDES_MISC_STATr(_unit, _phy_ctrl, _val, _mask) \ 802 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e1d, 0x15, \ 803 (_val), (_mask)) 804 805 /* Spare Register (Addr 21h) */ 806 #define READ_PHY54640_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val) \ 807 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, (_val)) 808 #define WRITE_PHY54640_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val) \ 809 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, (_val)) 810 #define MODIFY_PHY54640_2ND_SERDES_SPAREr(_unit, _phy_ctrl, _val, _mask) \ 811 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e21, 0x15, \ 812 (_val), (_mask)) 813 814 /* Secondary SerDes Interrupt Status Register (Addr 30h) */ 815 #define READ_PHY54640_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 816 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, (_val)) 817 #define WRITE_PHY54640_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 818 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, (_val)) 819 #define MODIFY_PHY54640_2ND_SERDES_INTERRUPT_STATr(_unit, _phy_ctrl, _val, _mask) \ 820 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e30, 0x15, \ 821 (_val), (_mask)) 822 823 /* Secondary SerDes Interrupt Mask Register (Addr 31h) */ 824 #define READ_PHY54640_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 825 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, (_val)) 826 #define WRITE_PHY54640_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 827 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, (_val)) 828 #define MODIFY_PHY54640_2ND_SERDES_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 829 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e31, 0x15, \ 830 (_val), (_mask)) 831 832 /* Secondary SerDes Lineside Loopback Control Register (Addr 44h) */ 833 #define READ_PHY54640_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val) \ 834 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, (_val)) 835 #define WRITE_PHY54640_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val) \ 836 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, (_val)) 837 #define MODIFY_PHY54640_2ND_SERDES_LINESIDE_LB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 838 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0e44, 0x15, \ 839 (_val), (_mask)) 840 841 /* IEEE 1588 read start/end control Register (Addr f3h) */ 842 #define READ_PHY54640_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 843 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 844 #define WRITE_PHY54640_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 845 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 846 #define MODIFY_PHY54640_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 847 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, \ 848 (_val), (_mask)) 849 850 /* EEE related */ 851 852 /* Auto EEE MII_Buffer CNTL/Status 2 Register (Addr AEh) */ 853 #define READ_PHY54640_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 854 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAE, 0x15, (_val)) 855 #define WRITE_PHY54640_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 856 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 857 0x15, (_val)) 858 #define MODIFY_PHY54640_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 859 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 860 0x15, (_val), (_mask)) 861 862 /* Auto EEE MII_Buffer CNTL/Status 1 Register (Addr AFh) */ 863 #define READ_PHY54640_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 864 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAF, 0x15, (_val)) 865 #define WRITE_PHY54640_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 866 PHY54640_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 867 0x15, (_val)) 868 #define MODIFY_PHY54640_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 869 PHY54640_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 870 0x15, (_val), (_mask)) 871 872 /* EEE Statistics related */ 873 /* Local LPI request Counter Reg (Addr ach) */ 874 #define READ_PHY54640_EXP_EEE_TX_EVENTSr(_unit, _phy_ctrl, _val) \ 875 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAC, 0x15, (_val)) 876 877 /* Remote LPI request Counter Reg (Addr adh) */ 878 #define READ_PHY54640_EXP_EEE_RX_EVENTSr(_unit, _phy_ctrl, _val) \ 879 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAD, 0x15, (_val)) 880 881 /* Statistic Timer_12_hours_lpi remote Reg (Addr aah) */ 882 #define READ_PHY54640_EXP_EEE_TX_DURATIONr(_unit, _phy_ctrl, _val) \ 883 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAA, 0x15, (_val)) 884 885 /* Statistic Timer_12_hours_lpi_local Local Reg (Addr abh) */ 886 #define READ_PHY54640_EXP_EEE_RX_DURATIONr(_unit, _phy_ctrl, _val) \ 887 PHY54640_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAB, 0x15, (_val)) 888 889 890 /* EEE Capability Register */ 891 #define READ_PHY54640_EEE_CAPr(_unit, _phy_ctrl, _val) \ 892 PHY54640E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x3, 0x14, _val) 893 894 /* EEE Advertisement Register */ 895 #define READ_PHY54640_EEE_ADVr(_unit, _phy_ctrl, _val) \ 896 PHY54640E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 897 #define WRITE_PHY54640_EEE_ADVr(_unit, _phy_ctrl, _val) \ 898 PHY54640E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 899 #define MODIFY_PHY54640_EEE_ADVr(_unit, _phy_ctrl, _val, _mask) \ 900 PHY54640E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val, _mask) 901 902 903 /* EEE Resolution Status Register */ 904 #define READ_PHY54640_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 905 PHY54640E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 906 #define WRITE_PHY54640_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 907 PHY54640E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 908 #define MODIFY_PHY54640_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val, _mask) \ 909 PHY54640E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val, _mask) 910 911 #define READ_PHY54640_EEE_803Dr(_unit, _phy_ctrl, _val) \ 912 PHY54640E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 913 #define WRITE_PHY54640_EEE_803Dr(_unit, _phy_ctrl, _val) \ 914 PHY54640E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 915 #define MODIFY_PHY54640_EEE_803Dr(_unit, _phy_ctrl, _val, _mask) \ 916 PHY54640E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val, _mask) 917 918 #define READ_PHY54640_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 919 PHY54640E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 920 #define WRITE_PHY54640_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 921 PHY54640E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 922 #define MODIFY_PHY54640_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val, _mask) \ 923 PHY54640E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val, _mask) 924 925 /* EEE TEST Control Register B*/ 926 #define READ_PHY54640_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 927 PHY54640E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 928 #define WRITE_PHY54640_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 929 PHY54640E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 930 #define MODIFY_PHY54640_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val, _mask) \ 931 PHY54640E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val, _mask) 932 933 typedef struct { 934 uint32 flags; 935 uint16 phy_id_orig; 936 uint16 phy_id_base; /* port 0 addr */ 937 uint16 phy_slice; 938 } PHY54640_DEV_DESC_t; 939 940 #define PHY54640_DEV_PHY_ID_ORIG(_pc) (((PHY54640_DEV_DESC_t *)((_pc) + 1))->phy_id_orig) 941 #define PHY54640_DEV_PHY_ID_BASE(_pc) (((PHY54640_DEV_DESC_t *)((_pc) + 1))->phy_id_base) 942 #define PHY54640_DEV_PHY_SLICE(_pc) (((PHY54640_DEV_DESC_t *)((_pc) + 1))->phy_slice) 943 #define PHY54640_DEV_PHY_SLICE_MASK 0x3 944 #define PHY54640_FLAGS(_pc) (((PHY54640_DEV_DESC_t *)((_pc) + 1))->flags) 945 #define PHY54640_PHYA_REV (1U << 0) 946 947 #define PHY54640_DEV_SET_BASE_ADDR(_pc) \ 948 PHY54640_DEV_PHY_ID_BASE(_pc) = (PHY54640_FLAGS((_pc)) & PHY54640_PHYA_REV) ?\ 949 PHY54640_DEV_PHY_ID_ORIG(_pc) + PHY54640_DEV_PHY_SLICE(_pc) : \ 950 PHY54640_DEV_PHY_ID_ORIG(_pc) - PHY54640_DEV_PHY_SLICE(_pc) 951 952 #define PHY54640_SLICE_ADDR(_pc, _slice) \ 953 (PHY54640_FLAGS((_pc)) & PHY54640_PHYA_REV) ? (PHY54640_DEV_PHY_ID_BASE(_pc) - (_slice)) : \ 954 (PHY54640_DEV_PHY_ID_BASE(_pc) + (_slice)) 955 956 #endif /* _PHY54640_H_ */