phy5464.h (32143B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy5464.h 8 * 9 * This driver applies to both BCM5464 and BCM5464S. 10 * Both parts support driving Copper or SERDES interfaces. 11 * 12 * The BCM5464S also has a SERDES pass-through mode, making it possible 13 * to auto-select copper or fiber based on signal detects. 14 */ 15 16 #ifndef _PHY5464_H_ 17 #define _PHY5464_H_ 18 19 #include <soc/phy.h> 20 21 /* PHY register access */ 22 #define PHY5464_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHY5464_REG_WRITE(_unit, _phy_ctrl, _flags, \ 26 _reg_bank, _reg_addr, _val) \ 27 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val)) 29 #define PHY5464_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, \ 30 _reg_addr, _val, _mask) \ 31 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 32 (_reg_addr), (_val), (_mask)) 33 34 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 35 #define READ_PHY5464_MII_CTRLr(_unit, _phy_ctrl, _val) \ 36 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 37 #define WRITE_PHY5464_MII_CTRLr(_unit, _phy_ctrl, _val) \ 38 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 39 #define MODIFY_PHY5464_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 40 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 41 (_val), (_mask)) 42 43 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 44 #define READ_PHY5464_MII_STATr(_unit, _phy_ctrl, _val) \ 45 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 46 #define WRITE_PHY5464_MII_STATr(_unit, _phy_ctrl, _val) \ 47 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 48 #define MODIFY_PHY5464_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 49 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 50 (_val), (_mask)) 51 52 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 53 #define READ_PHY5464_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 54 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 55 #define WRITE_PHY5464_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 56 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 57 #define MODIFY_PHY5464_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 58 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 59 (_val), (_mask)) 60 61 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 62 #define READ_PHY5464_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 63 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 64 #define WRITE_PHY5464_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 65 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 66 #define MODIFY_PHY5464_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 67 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 68 (_val), (_mask)) 69 70 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 71 #define READ_PHY5464_MII_ANAr(_unit, _phy_ctrl, _val) \ 72 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 73 #define WRITE_PHY5464_MII_ANAr(_unit, _phy_ctrl, _val) \ 74 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 75 #define MODIFY_PHY5464_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 76 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 77 (_val), (_mask)) 78 79 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 80 #define READ_PHY5464_MII_ANPr(_unit, _phy_ctrl, _val) \ 81 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 82 #define WRITE_PHY5464_MII_ANPr(_unit, _phy_ctrl, _val) \ 83 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 84 #define MODIFY_PHY5464_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 85 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 86 (_val), (_mask)) 87 88 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 89 #define READ_PHY5464_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 90 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 91 #define WRITE_PHY5464_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 92 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 93 #define MODIFY_PHY5464_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 94 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 95 (_val), (_mask)) 96 97 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 98 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 99 100 /* 1000BASE-T Control Register (ADDR 09h) */ 101 #define READ_PHY5464_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 102 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 103 #define WRITE_PHY5464_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 104 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 105 #define MODIFY_PHY5464_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 106 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 107 (_val), (_mask)) 108 109 /* 1000BASE-T Status Register (ADDR 0ah) */ 110 #define READ_PHY5464_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 111 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 112 #define WRITE_PHY5464_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 113 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 114 #define MODIFY_PHY5464_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 115 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 116 (_val), (_mask)) 117 118 /* (Addr 0ch-0eh) Reserved (Do not read/write to reserved registers. */ 119 120 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 121 122 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 123 #define READ_PHY5464_MII_ECRr(_unit, _phy_ctrl, _val) \ 124 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 125 #define WRITE_PHY5464_MII_ECRr(_unit, _phy_ctrl, _val) \ 126 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 127 #define MODIFY_PHY5464_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 128 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 129 (_val), (_mask)) 130 131 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 132 #define READ_PHY5464_MII_ESRr(_unit, _phy_ctrl, _val) \ 133 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 134 #define WRITE_PHY5464_MII_ESRr(_unit, _phy_ctrl, _val) \ 135 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 136 #define MODIFY_PHY5464_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 137 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 138 (_val), (_mask)) 139 140 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 141 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 142 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 143 144 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 145 #define READ_PHY5464_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 146 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 147 #define WRITE_PHY5464_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 148 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 149 #define MODIFY_PHY5464_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 150 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 151 (_val), (_mask)) 152 153 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 154 #define READ_PHY5464_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 155 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 156 #define WRITE_PHY5464_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 157 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 158 #define MODIFY_PHY5464_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 159 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 160 (_val), (_mask)) 161 162 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 163 #define READ_PHY5464_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 164 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 165 #define WRITE_PHY5464_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 166 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 167 #define MODIFY_PHY5464_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 168 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 169 (_val), (_mask)) 170 171 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 172 #define READ_PHY5464_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 173 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 174 #define WRITE_PHY5464_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 175 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 176 #define MODIFY_PHY5464_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 177 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 178 (_val), (_mask)) 179 180 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 181 #define READ_PHY5464_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 182 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 183 #define WRITE_PHY5464_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 184 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 185 #define MODIFY_PHY5464_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 186 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 187 (_val), (_mask)) 188 189 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 190 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 191 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 192 193 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 194 #define READ_PHY5464_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 195 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 196 #define WRITE_PHY5464_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 197 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 198 #define MODIFY_PHY5464_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 199 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 200 (_val), (_mask)) 201 202 /* 1000BASE-T/100BASE-TX/10BASE-T Clk Alignment Ctrl (ADDR 1ch shadow 00011) */ 203 #define READ_PHY5464_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 204 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 205 #define WRITE_PHY5464_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 206 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 207 #define MODIFY_PHY5464_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 208 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, \ 209 (_val), (_mask)) 210 211 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 212 #define READ_PHY5464_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 213 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 214 #define WRITE_PHY5464_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 215 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 216 #define MODIFY_PHY5464_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 217 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 218 (_val), (_mask)) 219 220 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 221 #define READ_PHY5464_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 222 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 223 #define WRITE_PHY5464_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 224 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 225 #define MODIFY_PHY5464_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 226 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 227 (_val), (_mask)) 228 229 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 230 #define READ_PHY5464_LED_STATr(_unit, _phy_ctrl, _val) \ 231 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 232 #define WRITE_PHY5464_LED_STATr(_unit, _phy_ctrl, _val) \ 233 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 234 #define MODIFY_PHY5464_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 235 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 236 (_val), (_mask)) 237 238 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 239 #define READ_PHY5464_LED_CTRLr(_unit, _phy_ctrl, _val) \ 240 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 241 #define WRITE_PHY5464_LED_CTRLr(_unit, _phy_ctrl, _val) \ 242 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 243 #define MODIFY_PHY5464_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 244 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 245 (_val), (_mask)) 246 247 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 248 #define READ_PHY5464_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 249 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 250 #define WRITE_PHY5464_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 251 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 252 #define MODIFY_PHY5464_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 253 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 254 (_val), (_mask)) 255 256 #define PHY_5464_AUTO_PWRDWN_EN (1 << 5) 257 #define PHY_5464_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 258 #define PHY_5464_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 259 #define PHY_5464_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 260 #define PHY_5464_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 261 #define PHY_5464_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 262 263 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 264 #define READ_PHY5464_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 265 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 266 #define WRITE_PHY5464_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 267 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 268 #define MODIFY_PHY5464_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 269 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 270 (_val), (_mask)) 271 272 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 273 #define READ_PHY5464_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 274 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 275 #define WRITE_PHY5464_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 276 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 277 #define MODIFY_PHY5464_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 278 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 279 (_val), (_mask)) 280 281 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 282 #define READ_PHY5464_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 283 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, (_val)) 284 #define WRITE_PHY5464_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 285 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, (_val)) 286 #define MODIFY_PHY5464_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 287 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000F, 0x1c, \ 288 (_val), (_mask)) 289 290 /* Misc 1000BASE-X Control2 Reg (ADDR 1ch shadow 10110), for 54980 */ 291 #define READ_PHY5464_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 292 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 293 #define WRITE_PHY5464_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 294 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 295 #define MODIFY_PHY5464_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 296 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 297 (_val), (_mask)) 298 299 /* 1000BASE-X Misc 1000BASE-X Control Reg (ADDR 1ch shadow 10111) */ 300 #define READ_PHY5464_MISC_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 301 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 302 #define WRITE_PHY5464_MISC_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 303 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 304 #define MODIFY_PHY5464_MISC_1000Xr(_unit, _phy_ctrl, _val, _mask) \ 305 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, \ 306 (_val), (_mask)) 307 308 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 309 #define READ_PHY5464_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 310 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 311 #define WRITE_PHY5464_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 312 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 313 #define MODIFY_PHY5464_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 314 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 315 (_val), (_mask)) 316 317 /* 1000BASE-X Auto-neg Debug Reg (ADDR 1ch shadow 11010) */ 318 #define READ_PHY5464_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 319 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 320 #define WRITE_PHY5464_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 321 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 322 #define MODIFY_PHY5464_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 323 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, \ 324 (_val), (_mask)) 325 326 /* Auxiliary 1000BASE-X Control Reg (ADDR 1ch shadow 11011) */ 327 #define READ_PHY5464_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 328 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, (_val)) 329 #define WRITE_PHY5464_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 330 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, (_val)) 331 #define MODIFY_PHY5464_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 332 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001B, 0x1c, \ 333 (_val), (_mask)) 334 335 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 336 #define READ_PHY5464_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 337 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, (_val)) 338 #define WRITE_PHY5464_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 339 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, (_val)) 340 #define MODIFY_PHY5464_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 341 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001C, 0x1c, \ 342 (_val), (_mask)) 343 344 /* Misc 1000BASE-X Status Reg (ADDR 1ch shadow 11101) */ 345 #define READ_PHY5464_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 346 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001D, 0x1c, (_val)) 347 #define WRITE_PHY5464_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 348 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001D, 0x1c, (_val)) 349 #define MODIFY_PHY5464_MISC_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 350 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001D, 0x1c, \ 351 (_val), (_mask)) 352 353 /* Copper/Fiber Auto-Detect Medium Reg (ADDR 1ch shadow 11110) */ 354 #define READ_PHY5464_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 355 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001E, 0x1c, (_val)) 356 #define WRITE_PHY5464_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 357 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001E, 0x1c, (_val)) 358 #define MODIFY_PHY5464_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val, _mask) \ 359 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001E, 0x1c, \ 360 (_val), (_mask)) 361 362 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 363 #define READ_PHY5464_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 364 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, (_val)) 365 #define WRITE_PHY5464_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 366 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, (_val)) 367 #define MODIFY_PHY5464_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 368 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001F, 0x1c, \ 369 (_val), (_mask)) 370 371 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 372 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 373 374 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 375 #define READ_PHY5464_TEST1r(_unit, _phy_ctrl, _val) \ 376 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 377 #define WRITE_PHY5464_TEST1r(_unit, _phy_ctrl, _val) \ 378 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 379 #define MODIFY_PHY5464_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 380 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 381 (_val), (_mask)) 382 383 384 /* +------------------------------+ 385 * | | 386 * | Primary SerDes Registers | 387 * | | 388 * +------------------------------+ 389 */ 390 /* 1000BASE-X MII Control Register (Addr 00h) */ 391 #define READ_PHY5464_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 392 PHY5464_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 393 0x0000, 0x00, (_val)) 394 #define WRITE_PHY5464_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 395 PHY5464_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 396 0x0000, 0x00, (_val)) 397 #define MODIFY_PHY5464_1000X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 398 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 399 0x0000, 0x00, (_val), (_mask)) 400 401 /* 1000BASE-X MII Status Register (Addr 01h) */ 402 #define READ_PHY5464_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 403 PHY5464_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 404 0x0000, 0x01, (_val)) 405 #define WRITE_PHY5464_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 406 PHY5464_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 407 0x0000, 0x01, (_val)) 408 #define MODIFY_PHY5464_1000X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 409 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 410 0x0000, 0x01, (_val), (_mask)) 411 412 /* 1000BASE-X MII Auto-neg Advertise Register (Addr 04h) */ 413 #define READ_PHY5464_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 414 PHY5464_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 415 0x0000, 0x04, (_val)) 416 #define WRITE_PHY5464_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 417 PHY5464_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 418 0x0000, 0x04, (_val)) 419 #define MODIFY_PHY5464_1000X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 420 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 421 0x0000, 0x04, (_val), (_mask)) 422 423 /* 1000BASE-X MII Auto-neg Link Partner Ability Register (Addr 05h) */ 424 #define READ_PHY5464_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 425 PHY5464_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 426 0x0000, 0x05, (_val)) 427 #define WRITE_PHY5464_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 428 PHY5464_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 429 0x0000, 0x05, (_val)) 430 #define MODIFY_PHY5464_1000X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 431 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 432 0x0000, 0x05, (_val), (_mask)) 433 434 /* 1000BASE-X MII Auto-neg Extended Status Register (Addr 06h) */ 435 #define READ_PHY5464_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 436 PHY5464_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 437 0x0000, 0x06, (_val)) 438 #define WRITE_PHY5464_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 439 PHY5464_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 440 0x0000, 0x06, (_val)) 441 #define MODIFY_PHY5464_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 442 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 443 0x0000, 0x06, (_val), (_mask)) 444 445 /* 1000BASE-X MII IEEE Extended Status Register (Addr 0fh) */ 446 #define READ_PHY5464_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 447 PHY5464_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 448 0x0000, 0x0f, (_val)) 449 #define WRITE_PHY5464_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 450 PHY5464_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 451 0x0000, 0x0f, (_val)) 452 #define MODIFY_PHY5464_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 453 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 454 0x0000, 0x0f, (_val), (_mask)) 455 456 /* +-------------------------+ 457 * | | 458 * | Expansion Registers | 459 * | | 460 * +-------------------------+ 461 */ 462 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 463 #define READ_PHY5464_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 464 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F00, 0x15, (_val)) 465 #define WRITE_PHY5464_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 466 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F00, \ 467 0x15, (_val)) 468 #define MODIFY_PHY5464_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 469 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F00, \ 470 0x15, (_val), (_mask)) 471 472 /* Expansion Interrupt Status Register (Addr 01h) */ 473 #define READ_PHY5464_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 474 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F01, 0x15, (_val)) 475 #define WRITE_PHY5464_EXP_r(_unit, _phy_ctrl, _val) \ 476 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F01, \ 477 0x15, (_val)) 478 #define MODIFY_PHY5464_EXP_r(_unit, _phy_ctrl, _val, _mask) \ 479 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F01, \ 480 0x15, (_val), (_mask)) 481 482 /* Expansion Interrupt Mask Register (Addr 02h) */ 483 #define READ_PHY5464_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 484 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F02, 0x15, (_val)) 485 #define WRITE_PHY5464_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 486 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F02, \ 487 0x15, (_val)) 488 #define MODIFY_PHY5464_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 489 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F02, \ 490 0x15, (_val), (_mask)) 491 492 /* Expansion SerDes Pass-Through Enable (Addr 03h) */ 493 #define READ_PHY5464_EXP_SERDES_PASSTHRU_ENr(_unit, _phy_ctrl, _val) \ 494 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F03, 0x15, (_val)) 495 #define WRITE_PHY5464_EXP_SERDES_PASSTHRU_ENr(_unit, _phy_ctrl, _val) \ 496 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F03, \ 497 0x15, (_val)) 498 #define MODIFY_PHY5464_EXP_SERDES_PASSTHRU_ENr(_unit, _phy_ctrl, _val, _mask) \ 499 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F03, \ 500 0x15, (_val), (_mask)) 501 502 /* Multicolor LED Selector Register (Addr 04h) */ 503 #define READ_PHY5464_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 504 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F04, 0x15, (_val)) 505 #define WRITE_PHY5464_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 506 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F04, \ 507 0x15, (_val)) 508 #define MODIFY_PHY5464_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 509 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F04, \ 510 0x15, (_val), (_mask)) 511 512 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 513 #define READ_PHY5464_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 514 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F05, 0x15, (_val)) 515 #define WRITE_PHY5464_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 516 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F05, \ 517 0x15, (_val)) 518 #define MODIFY_PHY5464_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 519 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F05, \ 520 0x15, (_val), (_mask)) 521 522 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 523 #define READ_PHY5464_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 524 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F06, 0x15, (_val)) 525 #define WRITE_PHY5464_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 526 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F06, \ 527 0x15, (_val)) 528 #define MODIFY_PHY5464_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 529 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F06, \ 530 0x15, (_val), (_mask)) 531 532 /* 10BT Controls Register (Addr 08h) */ 533 #define READ_PHY5464_10BT_CTRLr(_unit, _phy_ctrl, _val) \ 534 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F08, 0x15, (_val)) 535 #define WRITE_PHY5464_10BT_CTRLr(_unit, _phy_ctrl, _val) \ 536 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F08, 0x15, (_val)) 537 #define MODIFY_PHY5464_10BT_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 538 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F08, 0x15, \ 539 (_val), (_mask)) 540 541 /* Register 76h,related to the 10BASE-T LOW TRANSMITTER AMPLITUDE workaround*/ 542 #define READ_PHY5464_EXP_10BaseT_TxAMPr(_unit, _phy_ctrl, _val) \ 543 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0F76, 0x15, (_val)) 544 #define WRITE_PHY5464_EXP_10BaseT_TxAMPr(_unit, _phy_ctrl, _val) \ 545 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0F76, \ 546 0x15, (_val)) 547 #define MODIFY_PHY5464_EXP_10BaseT_TxAMPr(_unit, _phy_ctrl, _val, _mask) \ 548 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0F76, \ 549 0x15, (_val), (_mask)) 550 551 /* SerDes Passthrough LED Mode Reg (Addr fdh) */ 552 #define READ_PHY5464_EXP_PASSTHRU_LED_MODEr(_unit, _phy_ctrl, _val) \ 553 PHY5464_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FF9, 0x15, (_val)) 554 #define WRITE_PHY5464_EXP_PASSTHRU_LED_MODEr(_unit, _phy_ctrl, _val) \ 555 PHY5464_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FF9, \ 556 0x15, (_val)) 557 #define MODIFY_PHY5464_EXP_PASSTHRU_LED_MODEr(_unit, _phy_ctrl, _val, _mask) \ 558 PHY5464_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FF9, \ 559 0x15, (_val), (_mask)) 560 561 #endif /* _PHY5464_H_ */