phy54616.h (42543B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy54616.h 8 * 9 * This driver applies to both BCM54616 and BCM54616S. 10 * Both parts support driving Copper or SERDES interfaces. 11 */ 12 13 #ifndef _PHY54616_H_ 14 #define _PHY54616_H_ 15 16 #include <soc/phy.h> 17 18 /* PHY register access */ 19 #define PHY54616_REG_READ(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 20 phy_reg_ge_read((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 21 (_reg_addr), (_val)) 22 #define PHY54616_REG_WRITE(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, _val) \ 23 phy_reg_ge_write((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 24 (_reg_addr), (_val)) 25 #define PHY54616_REG_MODIFY(_unit, _phy_ctrl, _flags, _reg_bank, _reg_addr, \ 26 _val, _mask) \ 27 phy_reg_ge_modify((_unit), (_phy_ctrl), (_flags), (_reg_bank), \ 28 (_reg_addr), (_val), (_mask)) 29 30 31 /* Clause 45 Registers access using Clause 22 register access */ 32 #define PHY54618E_CL45_REG_READ(_unit, _phy_ctrl, _flags, _dev_addr, _reg_addr, _val) \ 33 _phy_54618e_cl45_reg_read((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 34 (_reg_addr), (_val)) 35 #define PHY54618E_CL45_REG_WRITE(_unit, _phy_ctrl, _flags, \ 36 _dev_addr, _reg_addr, _val) \ 37 _phy_54618e_cl45_reg_write((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 38 (_reg_addr), (_val)) 39 #define PHY54618E_CL45_REG_MODIFY(_unit, _phy_ctrl, _flags, _dev_addr, \ 40 _reg_addr, _val, _mask) \ 41 _phy_54618e_cl45_reg_modify((_unit), (_phy_ctrl), (_flags), (_dev_addr), \ 42 (_reg_addr), (_val), (_mask)) 43 44 45 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 46 #define READ_PHY54616_MII_CTRLr(_unit, _phy_ctrl, _val) \ 47 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 48 #define WRITE_PHY54616_MII_CTRLr(_unit, _phy_ctrl, _val) \ 49 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, (_val)) 50 #define MODIFY_PHY54616_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 51 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x00, \ 52 (_val), (_mask)) 53 54 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 55 #define READ_PHY54616_MII_STATr(_unit, _phy_ctrl, _val) \ 56 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 57 #define WRITE_PHY54616_MII_STATr(_unit, _phy_ctrl, _val) \ 58 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, (_val)) 59 #define MODIFY_PHY54616_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 60 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x01, \ 61 (_val), (_mask)) 62 63 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 64 #define READ_PHY54616_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 65 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 66 #define WRITE_PHY54616_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 67 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, (_val)) 68 #define MODIFY_PHY54616_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 69 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x02, \ 70 (_val), (_mask)) 71 72 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 73 #define READ_PHY54616_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 74 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 75 #define WRITE_PHY54616_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 76 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, (_val)) 77 #define MODIFY_PHY54616_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 78 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x03, \ 79 (_val), (_mask)) 80 81 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 82 #define READ_PHY54616_MII_ANAr(_unit, _phy_ctrl, _val) \ 83 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 84 #define WRITE_PHY54616_MII_ANAr(_unit, _phy_ctrl, _val) \ 85 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, (_val)) 86 #define MODIFY_PHY54616_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 87 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x04, \ 88 (_val), (_mask)) 89 90 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 91 #define READ_PHY54616_MII_ANPr(_unit, _phy_ctrl, _val) \ 92 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 93 #define WRITE_PHY54616_MII_ANPr(_unit, _phy_ctrl, _val) \ 94 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, (_val)) 95 #define MODIFY_PHY54616_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 96 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x05, \ 97 (_val), (_mask)) 98 99 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 100 #define READ_PHY54616_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 101 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 102 #define WRITE_PHY54616_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 103 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, (_val)) 104 #define MODIFY_PHY54616_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 105 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x06, \ 106 (_val), (_mask)) 107 108 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 109 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 110 111 /* 1000BASE-T Control Register (ADDR 09h) */ 112 #define READ_PHY54616_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 113 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 114 #define WRITE_PHY54616_MII_GB_CTRLr(_unit, _phy_ctrl, _val) \ 115 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, (_val)) 116 #define MODIFY_PHY54616_MII_GB_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 117 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x09, \ 118 (_val), (_mask)) 119 120 /* 1000BASE-T Status Register (ADDR 0ah) */ 121 #define READ_PHY54616_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 122 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 123 #define WRITE_PHY54616_MII_GB_STATr(_unit, _phy_ctrl, _val) \ 124 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, (_val)) 125 #define MODIFY_PHY54616_MII_GB_STATr(_unit, _phy_ctrl, _val, _mask) \ 126 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x0a, \ 127 (_val), (_mask)) 128 129 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 130 131 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (ADDR 10h) */ 132 #define READ_PHY54616_MII_ECRr(_unit, _phy_ctrl, _val) \ 133 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 134 #define WRITE_PHY54616_MII_ECRr(_unit, _phy_ctrl, _val) \ 135 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, (_val)) 136 #define MODIFY_PHY54616_MII_ECRr(_unit, _phy_ctrl, _val, _mask) \ 137 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x10, \ 138 (_val), (_mask)) 139 140 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (ADDR 11h) */ 141 #define READ_PHY54616_MII_ESRr(_unit, _phy_ctrl, _val) \ 142 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 143 #define WRITE_PHY54616_MII_ESRr(_unit, _phy_ctrl, _val) \ 144 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, (_val)) 145 #define MODIFY_PHY54616_MII_ESRr(_unit, _phy_ctrl, _val, _mask) \ 146 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x11, \ 147 (_val), (_mask)) 148 149 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 150 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 151 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 152 153 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Reg (ADDR 18h Shadow 000)*/ 154 #define READ_PHY54616_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 155 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 156 #define WRITE_PHY54616_MII_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 157 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, (_val)) 158 #define MODIFY_PHY54616_MII_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 159 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x18, \ 160 (_val), (_mask)) 161 162 /* 10BASE-T Register (ADDR 18h Shadow 001) */ 163 #define READ_PHY54616_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 164 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 165 #define WRITE_PHY54616_MII_10BASE_Tr(_unit, _phy_ctrl, _val) \ 166 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, (_val)) 167 #define MODIFY_PHY54616_MII_10BASE_Tr(_unit, _phy_ctrl, _val, _mask) \ 168 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0001, 0x18, \ 169 (_val), (_mask)) 170 171 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg (ADDR 18h Shadow 010)*/ 172 #define READ_PHY54616_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 173 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 174 #define WRITE_PHY54616_MII_POWER_CTRLr(_unit, _phy_ctrl, _val) \ 175 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, (_val)) 176 #define MODIFY_PHY54616_MII_POWER_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 177 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x18, \ 178 (_val), (_mask)) 179 180 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register (ADDR 18h Shadow 100) */ 181 #define READ_PHY54616_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 182 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 183 #define WRITE_PHY54616_MII_MISC_TESTr(_unit, _phy_ctrl, _val) \ 184 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, (_val)) 185 #define MODIFY_PHY54616_MII_MISC_TESTr(_unit, _phy_ctrl, _val, _mask) \ 186 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x18, \ 187 (_val), (_mask)) 188 189 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register (ADDR 18h Shadow 111)*/ 190 #define READ_PHY54616_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 191 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 192 #define WRITE_PHY54616_MII_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 193 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, (_val)) 194 #define MODIFY_PHY54616_MII_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 195 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0007, 0x18, \ 196 (_val), (_mask)) 197 198 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 199 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 200 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 201 202 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 203 #define READ_PHY54616_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 204 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 205 #define WRITE_PHY54616_SPARE_CTRLr(_unit, _phy_ctrl, _val) \ 206 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, (_val)) 207 #define MODIFY_PHY54616_SPARE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 208 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0002, 0x1c, \ 209 (_val), (_mask)) 210 211 /* 1000BASE-T/100BASE-TX/10BASE-T Clk Alignment Ctrl (ADDR 1ch shadow 00011) */ 212 #define READ_PHY54616_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 213 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 214 #define WRITE_PHY54616_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val) \ 215 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, (_val)) 216 #define MODIFY_PHY54616_CLK_ALIGN_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 217 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0003, 0x1c, \ 218 (_val), (_mask)) 219 220 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 221 #define READ_PHY54616_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 222 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 223 #define WRITE_PHY54616_SPARE_CTRL_2r(_unit, _phy_ctrl, _val) \ 224 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, (_val)) 225 #define MODIFY_PHY54616_SPARE_CTRL_2r(_unit, _phy_ctrl, _val, _mask) \ 226 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0004, 0x1c, \ 227 (_val), (_mask)) 228 229 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 230 #define READ_PHY54616_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 231 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 232 #define WRITE_PHY54616_SPARE_CTRL_3r(_unit, _phy_ctrl, _val) \ 233 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, (_val)) 234 #define MODIFY_PHY54616_SPARE_CTRL_3r(_unit, _phy_ctrl, _val, _mask) \ 235 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0005, 0x1c, \ 236 (_val), (_mask)) 237 238 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 239 #define READ_PHY54616_LED_STATr(_unit, _phy_ctrl, _val) \ 240 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 241 #define WRITE_PHY54616_LED_STATr(_unit, _phy_ctrl, _val) \ 242 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, (_val)) 243 #define MODIFY_PHY54616_LED_STATr(_unit, _phy_ctrl, _val, _mask) \ 244 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0008, 0x1c, \ 245 (_val), (_mask)) 246 247 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 248 #define READ_PHY54616_LED_CTRLr(_unit, _phy_ctrl, _val) \ 249 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 250 #define WRITE_PHY54616_LED_CTRLr(_unit, _phy_ctrl, _val) \ 251 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, (_val)) 252 #define MODIFY_PHY54616_LED_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 253 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0009, 0x1c, \ 254 (_val), (_mask)) 255 256 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 257 #define READ_PHY54616_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 258 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 259 #define WRITE_PHY54616_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val) \ 260 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, (_val)) 261 #define MODIFY_PHY54616_AUTO_POWER_DOWNr(_unit, _phy_ctrl, _val, _mask) \ 262 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000a, 0x1c, \ 263 (_val), (_mask)) 264 #define PHY_54616_AUTO_PWRDWN_EN (1 << 5) 265 #define PHY_54616_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 266 #define PHY_54616_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 267 #define PHY_54616_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 268 #define PHY_54616_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 269 #define PHY_54616_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 270 271 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 272 #define READ_PHY54616_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 273 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 274 #define WRITE_PHY54616_LED_SELECTOR_1r(_unit, _phy_ctrl, _val) \ 275 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, (_val)) 276 #define MODIFY_PHY54616_LED_SELECTOR_1r(_unit, _phy_ctrl, _val, _mask) \ 277 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000d, 0x1c, \ 278 (_val), (_mask)) 279 280 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 281 #define READ_PHY54616_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 282 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 283 #define WRITE_PHY54616_LED_SELECTOR_2r(_unit, _phy_ctrl, _val) \ 284 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, (_val)) 285 #define MODIFY_PHY54616_LED_SELECTOR_2r(_unit, _phy_ctrl, _val, _mask) \ 286 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000e, 0x1c, \ 287 (_val), (_mask)) 288 289 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 290 #define READ_PHY54616_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 291 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 292 #define WRITE_PHY54616_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val) \ 293 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, (_val)) 294 #define MODIFY_PHY54616_LED_GPIO_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 295 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x000f, 0x1c, \ 296 (_val), (_mask)) 297 298 /* SerDes 100BASE-FX Status Reg (ADDR 1ch shadow 10001) */ 299 #define READ_PHY54616_100FX_STATr(_unit, _phy_ctrl, _val) \ 300 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 301 #define WRITE_PHY54616_100FX_STATr(_unit, _phy_ctrl, _val) \ 302 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, (_val)) 303 #define MODIFY_PHY54616_100FX_STATr(_unit, _phy_ctrl, _val, _mask) \ 304 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0011, 0x1c, \ 305 (_val), (_mask)) 306 307 /* SerDes 100BASE-FX Control Reg (ADDR 1ch shadow 10011) */ 308 #define READ_PHY54616_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 309 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 310 #define WRITE_PHY54616_100FX_CTRLr(_unit, _phy_ctrl, _val) \ 311 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, (_val)) 312 #define MODIFY_PHY54616_100FX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 313 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0013, 0x1c, \ 314 (_val), (_mask)) 315 316 /* Secondary SerDes Control Reg (ADDR 1ch shadow 10100) */ 317 #define READ_PHY54616_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 318 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 319 #define WRITE_PHY54616_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 320 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, (_val)) 321 #define MODIFY_PHY54616_2ND_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 322 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0014, 0x1c, \ 323 (_val), (_mask)) 324 325 /* SGMII Slave Reg (ADDR 1ch shadow 10101) */ 326 #define READ_PHY54616_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 327 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 328 #define WRITE_PHY54616_SGMII_SLAVEr(_unit, _phy_ctrl, _val) \ 329 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, (_val)) 330 #define MODIFY_PHY54616_SGMII_SLAVEr(_unit, _phy_ctrl, _val, _mask) \ 331 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0015, 0x1c, \ 332 (_val), (_mask)) 333 334 /* Primary SerDes Control Reg (ADDR 1ch shadow 10110) */ 335 #define READ_PHY54616_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 336 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 337 #define WRITE_PHY54616_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val) \ 338 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, (_val)) 339 #define MODIFY_PHY54616_1ST_SERDES_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 340 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0016, 0x1c, \ 341 (_val), (_mask)) 342 343 344 /* Misc 1000X Control 2 Reg (ADDR 1ch shadow 10111) */ 345 #define READ_PHY54616_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 346 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 347 #define WRITE_PHY54616_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val) \ 348 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, (_val)) 349 #define MODIFY_PHY54616_MISC_1000X_CTRL2r(_unit, _phy_ctrl, _val, _mask) \ 350 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0017, 0x1c, \ 351 (_val), (_mask)) 352 353 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 354 #define READ_PHY54616_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 355 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 356 #define WRITE_PHY54616_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val) \ 357 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, (_val)) 358 #define MODIFY_PHY54616_AUTO_DETECT_SGMII_MEDIAr(_unit, _phy_ctrl, _val, _mask) \ 359 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0018, 0x1c, \ 360 (_val), (_mask)) 361 362 /* 1000BASE-X Auto-neg Debug Reg (ADDR 1ch shadow 11010) */ 363 #define READ_PHY54616_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 364 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 365 #define WRITE_PHY54616_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val) \ 366 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, (_val)) 367 #define MODIFY_PHY54616_1000X_AN_DEBUGr(_unit, _phy_ctrl, _val, _mask) \ 368 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001a, 0x1c, \ 369 (_val), (_mask)) 370 371 /* Auxiliary 1000BASE-X Control Reg (ADDR 1ch shadow 11011) */ 372 #define READ_PHY54616_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 373 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 374 #define WRITE_PHY54616_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val) \ 375 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, (_val)) 376 #define MODIFY_PHY54616_AUX_1000X_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 377 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001b, 0x1c, \ 378 (_val), (_mask)) 379 380 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 381 #define READ_PHY54616_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 382 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 383 #define WRITE_PHY54616_AUX_1000X_STATr(_unit, _phy_ctrl, _val) \ 384 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, (_val)) 385 #define MODIFY_PHY54616_AUX_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 386 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001c, 0x1c, \ 387 (_val), (_mask)) 388 389 /* Misc 1000BASE-X Status Reg (ADDR 1ch shadow 11101) */ 390 #define READ_PHY54616_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 391 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 392 #define WRITE_PHY54616_MISC_1000X_STATr(_unit, _phy_ctrl, _val) \ 393 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, (_val)) 394 #define MODIFY_PHY54616_MISC_1000X_STATr(_unit, _phy_ctrl, _val, _mask) \ 395 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001d, 0x1c, \ 396 (_val), (_mask)) 397 398 /* Copper/Fiber Auto-Detect Medium Reg (ADDR 1ch shadow 11110) */ 399 #define READ_PHY54616_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 400 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 401 #define WRITE_PHY54616_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val) \ 402 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, (_val)) 403 #define MODIFY_PHY54616_AUTO_DETECT_MEDIUMr(_unit, _phy_ctrl, _val, _mask) \ 404 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001e, 0x1c, \ 405 (_val), (_mask)) 406 #define PHY_54616_FiBER_AUTO_PWRDWN_EN (1 << 4) 407 408 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 409 #define READ_PHY54616_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 410 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 411 #define WRITE_PHY54616_MODE_CTRLr(_unit, _phy_ctrl, _val) \ 412 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, (_val)) 413 #define MODIFY_PHY54616_MODE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 414 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x001f, 0x1c, \ 415 (_val), (_mask)) 416 417 /* 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Reg (ADDR 1dh bit 15 = 0) */ 418 /* 1000BASE-T/100BASE-TX/10BASE-T HDC Status Reg (ADDR 1dh bit 15 = 1) */ 419 420 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (ADDR 1eh) */ 421 #define READ_PHY54616_TEST1r(_unit, _phy_ctrl, _val) \ 422 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 423 #define WRITE_PHY54616_TEST1r(_unit, _phy_ctrl, _val) \ 424 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, (_val)) 425 #define MODIFY_PHY54616_TEST1r(_unit, _phy_ctrl, _val, _mask) \ 426 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0000, 0x1e, \ 427 (_val), (_mask)) 428 429 430 /* +------------------------------+ 431 * | | 432 * | Primary SerDes Registers | 433 * | | 434 * +------------------------------+ 435 */ 436 /* 1000BASE-X MII Control Register (Addr 00h) */ 437 #define READ_PHY54616_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 438 PHY54616_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 439 0x0000, 0x00, (_val)) 440 #define WRITE_PHY54616_1000X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 441 PHY54616_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 442 0x0000, 0x00, (_val)) 443 #define MODIFY_PHY54616_1000X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 444 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 445 0x0000, 0x00, (_val), (_mask)) 446 447 /* 1000BASE-X MII Status Register (Addr 01h) */ 448 #define READ_PHY54616_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 449 PHY54616_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 450 0x0000, 0x01, (_val)) 451 #define WRITE_PHY54616_1000X_MII_STATr(_unit, _phy_ctrl, _val) \ 452 PHY54616_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 453 0x0000, 0x01, (_val)) 454 #define MODIFY_PHY54616_1000X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 455 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 456 0x0000, 0x01, (_val), (_mask)) 457 458 /* 1000BASE-X MII Auto-neg Advertise Register (Addr 04h) */ 459 #define READ_PHY54616_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 460 PHY54616_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 461 0x0000, 0x04, (_val)) 462 #define WRITE_PHY54616_1000X_MII_ANAr(_unit, _phy_ctrl, _val) \ 463 PHY54616_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 464 0x0000, 0x04, (_val)) 465 #define MODIFY_PHY54616_1000X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 466 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 467 0x0000, 0x04, (_val), (_mask)) 468 469 /* 1000BASE-X MII Auto-neg Link Partner Ability Register (Addr 05h) */ 470 #define READ_PHY54616_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 471 PHY54616_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 472 0x0000, 0x05, (_val)) 473 #define WRITE_PHY54616_1000X_MII_ANPr(_unit, _phy_ctrl, _val) \ 474 PHY54616_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 475 0x0000, 0x05, (_val)) 476 #define MODIFY_PHY54616_1000X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 477 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 478 0x0000, 0x05, (_val), (_mask)) 479 480 /* 1000BASE-X MII Auto-neg Extended Status Register (Addr 06h) */ 481 #define READ_PHY54616_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 482 PHY54616_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 483 0x0000, 0x06, (_val)) 484 #define WRITE_PHY54616_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 485 PHY54616_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 486 0x0000, 0x06, (_val)) 487 #define MODIFY_PHY54616_1000X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 488 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 489 0x0000, 0x06, (_val), (_mask)) 490 491 /* 1000BASE-X MII IEEE Extended Status Register (Addr 0fh) */ 492 #define READ_PHY54616_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 493 PHY54616_REG_READ((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 494 0x0000, 0x0f, (_val)) 495 #define WRITE_PHY54616_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val) \ 496 PHY54616_REG_WRITE((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 497 0x0000, 0x0f, (_val)) 498 #define MODIFY_PHY54616_1000X_MII_EXT_STATr(_unit, _phy_ctrl, _val, _mask) \ 499 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), SOC_PHY_REG_1000X, \ 500 0x0000, 0x0f, (_val), (_mask)) 501 502 /* 100FX full-duplex bit */ 503 #define PHY_54616_2ND_SERDES_100FX_FD (1 << 5) 504 #define PHY_54616_PRIMARY_SERDES_100FX_FD (1 << 1) 505 506 507 /* +-------------------------+ 508 * | | 509 * | Expansion Registers | 510 * | | 511 * +-------------------------+ 512 */ 513 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 514 #define READ_PHY54616_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 515 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 516 #define WRITE_PHY54616_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val) \ 517 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, (_val)) 518 #define MODIFY_PHY54616_EXP_PKT_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 519 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f00, 0x15, \ 520 (_val), (_mask)) 521 522 /* Expansion Interrupt Status Register (Addr 01h) */ 523 #define READ_PHY54616_EXP_INTERRUPT_STATr(_unit, _phy_ctrl, _val) \ 524 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 525 #define WRITE_PHY54616_EXP_r(_unit, _phy_ctrl, _val) \ 526 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, (_val)) 527 #define MODIFY_PHY54616_EXP_r(_unit, _phy_ctrl, _val, _mask) \ 528 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f01, 0x15, \ 529 (_val), (_mask)) 530 531 /* Expansion Interrupt Mask Register (Addr 02h) */ 532 #define READ_PHY54616_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 533 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 534 #define WRITE_PHY54616_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val) \ 535 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, (_val)) 536 #define MODIFY_PHY54616_EXP_INTERRUPT_MASKr(_unit, _phy_ctrl, _val, _mask) \ 537 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f02, 0x15, \ 538 (_val), (_mask)) 539 540 /* Multicolor LED Selector Register (Addr 04h) */ 541 #define READ_PHY54616_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 542 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 543 #define WRITE_PHY54616_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val) \ 544 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, (_val)) 545 #define MODIFY_PHY54616_EXP_LED_SELECTORr(_unit, _phy_ctrl, _val, _mask) \ 546 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f04, 0x15, \ 547 (_val), (_mask)) 548 549 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 550 #define READ_PHY54616_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 551 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 552 #define WRITE_PHY54616_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val) \ 553 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, (_val)) 554 #define MODIFY_PHY54616_EXP_LED_FLASH_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 555 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f05, 0x15, \ 556 (_val), (_mask)) 557 558 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 559 #define READ_PHY54616_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 560 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 561 #define WRITE_PHY54616_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val) \ 562 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f06, 0x15, (_val)) 563 #define MODIFY_PHY54616_EXP_LED_BLINK_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 564 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f, 0x15, \ 565 (_val), (_mask)) 566 567 /* Synchronous Ethernet Controls Register (Addr 0Eh) */ 568 #define READ_PHY54616_EXP_SYNCE_CTRLr(_unit, _phy_ctrl, _val) \ 569 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f0e, 0x15, (_val)) 570 #define WRITE_PHY54616_EXP_SYNCE_CTRLr(_unit, _phy_ctrl, _val) \ 571 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f0e, 0x15, (_val)) 572 #define MODIFY_PHY54616_EXP_SYNCE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 573 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f0e, 0x15, \ 574 (_val), (_mask)) 575 576 /* Operating Mode Status Register (Addr 42h) */ 577 #define READ_PHY54616_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 578 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 579 #define WRITE_PHY54616_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val) \ 580 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, (_val)) 581 #define MODIFY_PHY54616_EXP_OPT_MODE_STATr(_unit, _phy_ctrl, _val, _mask) \ 582 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f42, 0x15, \ 583 (_val), (_mask)) 584 585 /* Operating Mode Status Register (Addr 44h) */ 586 #define READ_PHY54616_EXP_SGMII_REC_CTRLr(_unit, _phy_ctrl, _val) \ 587 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, (_val)) 588 #define WRITE_PHY54616_EXP_SGMII_REC_CTRLr(_unit, _phy_ctrl, _val) \ 589 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, (_val)) 590 #define MODIFY_PHY54616_EXP_SGMII_REC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 591 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f44, 0x15, \ 592 (_val), (_mask)) 593 594 /* SerDes/SGMII Control Register (Addr 52h) */ 595 #define READ_PHY54616_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 596 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 597 #define WRITE_PHY54616_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val) \ 598 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, (_val)) 599 #define MODIFY_PHY54616_EXP_SERDES_SGMII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 600 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0f52, 0x15, \ 601 (_val), (_mask)) 602 603 /* +-----------------------------------+ 604 * | | 605 * | Top-Level Expansion Registers | 606 * | | 607 * +-----------------------------------+ 608 */ 609 /* Spare Register 0 - SyncE CLK125 & ADC monitor (Addr 34h) */ 610 #define READ_PHY54616_TOPLVL_CLK125_ADCr(_unit, _phy_ctrl, _val) \ 611 PHY54616_REG_READ( (_unit), (_phy_ctrl), 0x00, 0x0d34, 0x15, (_val)) 612 #define WRITE_PHY54616_TOPLVL_CLK125_ADCr(_unit, _phy_ctrl, _val) \ 613 PHY54616_REG_WRITE( (_unit), (_phy_ctrl), 0x00, 0x0d34, 0x15, (_val)) 614 #define MODIFY_PHY54616_TOPLVL_CLK125_ADCr(_unit, _phy_ctrl, _val, _mask) \ 615 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0d34, 0x15, \ 616 (_val), (_mask)) 617 618 #define _phy_54618e_toplvl_exp_reg_read(_unit, _phy_ctrl, _flags, \ 619 reg_offset, _val) \ 620 PHY54616_REG_READ((_unit), (_phy_ctrl), _flags, \ 621 (0x0d00 | (reg_offset & 0xff)), 0x15, (_val)) 622 623 #define _phy_54618e_toplvl_exp_reg_write(_unit, _phy_ctrl, _flags, \ 624 reg_offset, _val) \ 625 PHY54616_REG_WRITE((_unit), (_phy_ctrl), _flags, \ 626 (0x0d00 | (reg_offset & 0xff)), 0x15, (_val)) 627 628 #define _phy_54618e_toplvl_exp_reg_modify(_unit, _phy_ctrl, _flags, \ 629 reg_offset, _val, _mask) \ 630 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), _flags, \ 631 (0x0d00 | (reg_offset & 0xff)), 0x15, (_val), (_mask)) 632 633 /*************** 634 * * 635 * EEE related * 636 */ 637 638 /* Auto EEE MII_Buffer CNTL/Status 2 Register (Addr AEh) */ 639 #define READ_PHY54618_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 640 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAE, 0x15, (_val)) 641 #define WRITE_PHY54618_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val) \ 642 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 643 0x15, (_val)) 644 #define MODIFY_PHY54618_EXP_MII_BUF_CNTL_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 645 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAE, \ 646 0x15, (_val), (_mask)) 647 648 /* Auto EEE MII_Buffer CNTL/Status 1 Register (Addr AFh) */ 649 #define READ_PHY54618_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 650 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAF, 0x15, (_val)) 651 #define WRITE_PHY54618_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val) \ 652 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 653 0x15, (_val)) 654 #define MODIFY_PHY54618_EXP_MII_BUF_CNTL_STAT1r(_unit, _phy_ctrl, _val, _mask) \ 655 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0FAF, \ 656 0x15, (_val), (_mask)) 657 658 /* EEE Statistics related */ 659 /* Local LPI request Counter Reg (Addr ach) */ 660 #define READ_PHY54618_EXP_EEE_TX_EVENTSr(_unit, _phy_ctrl, _val) \ 661 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAC, 0x15, (_val)) 662 663 /* Remote LPI request Counter Reg (Addr adh) */ 664 #define READ_PHY54618_EXP_EEE_RX_EVENTSr(_unit, _phy_ctrl, _val) \ 665 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAD, 0x15, (_val)) 666 667 /* Statistic Timer_12_hours_lpi remote Reg (Addr aah) */ 668 #define READ_PHY54618_EXP_EEE_TX_DURATIONr(_unit, _phy_ctrl, _val) \ 669 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAA, 0x15, (_val)) 670 671 /* Statistic Timer_12_hours_lpi_local Local Reg (Addr abh) */ 672 #define READ_PHY54618_EXP_EEE_RX_DURATIONr(_unit, _phy_ctrl, _val) \ 673 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0FAB, 0x15, (_val)) 674 675 /* IEEE 1588 read start/end control Register (Addr f3h) */ 676 #define READ_PHY54618_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 677 PHY54616_REG_READ((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 678 #define WRITE_PHY54618_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val) \ 679 PHY54616_REG_WRITE((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, (_val)) 680 #define MODIFY_PHY54618_EXP_READ_START_END_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 681 PHY54616_REG_MODIFY((_unit), (_phy_ctrl), 0x00, 0x0ff3, 0x15, \ 682 (_val), (_mask)) 683 684 /* EEE Control Register 1 (Clause45 Device7 0x803d) */ 685 #define READ_PHY54618_EEE_CTRLr(_unit, _phy_ctrl, _val) \ 686 PHY54618E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 687 #define WRITE_PHY54618_EEE_CTRLr(_unit, _phy_ctrl, _val) \ 688 PHY54618E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 689 #define MODIFY_PHY54618_EEE_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 690 PHY54618E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val, _mask) 691 692 /* EEE 2K Buffer Register 1 (Top-Level Expension 0x40) */ 693 #define MODIFY_PHY54618_EEE_AUTOEEECTRLr(_unit, _phy_ctrl, _val, _mask) \ 694 PHY54616_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x0d40, 0x15, _val, _mask) 695 696 /* EEE Capability Register */ 697 /* 698 #define READ_PHY54618_EEE_CAPr(_unit, _phy_ctrl, _val) \ 699 PHY54618E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x3, 0x14, _val) 700 */ 701 702 /* EEE Advertisement Register */ 703 #define READ_PHY54618_EEE_ADVr(_unit, _phy_ctrl, _val) \ 704 PHY54618E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 705 #define WRITE_PHY54618_EEE_ADVr(_unit, _phy_ctrl, _val) \ 706 PHY54618E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val) 707 #define MODIFY_PHY54618_EEE_ADVr(_unit, _phy_ctrl, _val, _mask) \ 708 PHY54618E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x3c, _val, _mask) 709 /* 710 #define READ_PHY54618_EEE_803Dr(_unit, _phy_ctrl, _val) \ 711 PHY54618E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 712 #define WRITE_PHY54618_EEE_803Dr(_unit, _phy_ctrl, _val) \ 713 PHY54618E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val) 714 #define MODIFY_PHY54618_EEE_803Dr(_unit, _phy_ctrl, _val, _mask) \ 715 PHY54618E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803d, _val, _mask) 716 */ 717 718 /* EEE Resolution Status Register */ 719 #define READ_PHY54618_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 720 PHY54618E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 721 #define WRITE_PHY54618_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val) \ 722 PHY54618E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val) 723 #define MODIFY_PHY54618_EEE_RESOLUTION_STATr(_unit, _phy_ctrl, _val, _mask) \ 724 PHY54618E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x803e, _val, _mask) 725 726 #define READ_PHY54618_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 727 PHY54618E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 728 #define WRITE_PHY54618_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val) \ 729 PHY54618E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val) 730 #define MODIFY_PHY54618_EEE_TEST_CTRL_Ar(_unit, _phy_ctrl, _val, _mask) \ 731 PHY54618E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8030, _val, _mask) 732 733 /* EEE TEST Control Register B*/ 734 #define READ_PHY54618_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 735 PHY54618E_CL45_REG_READ(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 736 #define WRITE_PHY54618_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val) \ 737 PHY54618E_CL45_REG_WRITE(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val) 738 #define MODIFY_PHY54618_EEE_TEST_CTRL_Br(_unit, _phy_ctrl, _val, _mask) \ 739 PHY54618E_CL45_REG_MODIFY(_unit, _phy_ctrl, 0x00, 0x7, 0x8031, _val, _mask) 740 741 #endif /* _PHY54616_H_ */