phy542xx_regdefs.h (40558B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 8 #ifndef _PHY542XX_REGDEFS_H 9 #define _PHY542XX_REGDEFS_H 10 11 /* RV: MOVE TO A COMMON AREA FOR UTILITIES */ 12 #define BIT15 (1U << 15) 13 #define BIT14 (1U << 14) 14 #define BIT13 (1U << 13) 15 #define BIT12 (1U << 12) 16 #define BIT11 (1U << 11) 17 #define BIT10 (1U << 10) 18 #define BIT9 (1U << 9) 19 #define BIT8 (1U << 8) 20 #define BIT7 (1U << 7) 21 #define BIT6 (1U << 6) 22 #define BIT5 (1U << 5) 23 #define BIT4 (1U << 4) 24 #define BIT3 (1U << 3) 25 #define BIT2 (1U << 2) 26 #define BIT1 (1U << 1) 27 #define BIT0 (1U << 0) 28 29 #undef BIT 30 #define BIT(_n_) (1U << (_n_)) 31 32 33 /********************************************************** 34 * 35 * Register offset address & fields 36 */ 37 38 /* 39 * PHY_EXT_STATUS_REG 40 */ 41 #define PHY_BCM542XX_PHY_EXT_STATUS_REG_OFFSET 0x001 42 #define PHY_BCM542XX_PHY_EXT_STATUS_REG_MDIX_STATE (BIT13) 43 44 /* 45 * PATT_GEN_CTRL_REG 46 */ 47 #define PHY_BCM542XX_PATT_GEN_CTRL_REG_OFFSET 0x005 48 #define PHY_BCM542XX_PATT_GEN_CTRL_REG_TX_CRC_CHECK_EN (BIT12) 49 50 /* 51 * PHY_TEST1_REGISTER 52 */ 53 #define PHY_BCM542XX_TEST1_REG_OFFSET 0x00E 54 #define PHY_BCM542XX_TEST1_REG_FORCE_LINK (BIT12) 55 56 /* 57 * COPPER AUTO POWER DOWN 58 */ 59 #define PHY_BCM542XX_POWER_AUTO_DOWN_REG_OFFSET 0x01A 60 61 #define PHY_BCM542XX_POWER_AUTO_DOWN_REG_APD_IGNORE_AN (BIT6) 62 #define PHY_BCM542XX_POWER_AUTO_DOWN_REG_APD_MODE (BIT5) 63 #define PHY_BCM542XX_POWER_AUTO_DOWN_REG_SLEEP_TIMER_SEL (BIT4) 64 #define PHY_BCM542XX_POWER_AUTO_DOWN_REG_WAKE_UP_TIMER_SEL (BIT3 | BIT2 | BIT1 | BIT0) 65 66 #define PHY_BCM542XX_AUTO_PWRDWN_WAKEUP_UNIT 84 /* ms */ 67 #define PHY_BCM542XX_AUTO_PWRDWN_WAKEUP_MAX 1260 /* ms */ 68 #define PHY_BCM542XX_AUTO_PWRDWN_SLEEP_MAX 5400 /* ms */ 69 #define PHY_BCM542XX_AUTO_PWRDWN_SLEEP_MIN 2700 /* ms */ 70 71 /* 72 * LED SEL 1 73 */ 74 #define PHY_BCM542XX_LED_1_SEL_REG_OFFSET 0x01D 75 76 /* 77 * LED SEL 2 78 */ 79 #define PHY_BCM542XX_LED_2_SEL_REG_OFFSET 0x01E 80 81 /* 82 * LED GPIO CTRL_STATUS 83 */ 84 #define PHY_BCM542XX_LED_GPIO_CTRL_STATUS_REG_OFFSET 0x01F 85 86 /* 87 * MODE CONTROL 88 */ 89 #define PHY_BCM542XX_MODE_CONTROL_REG_OFFSET 0x021 90 91 #define PHY_BCM542XX_MODE_CONTROL_REG_COPPER_LINK (BIT7) 92 #define PHY_BCM542XX_MODE_CONTROL_REG_SERDES_LINK (BIT6) 93 #define PHY_BCM542XX_MODE_CONTROL_REG_COPPER_ENERGY_DET (BIT5) 94 #define PHY_BCM542XX_MODE_CONTROL_REG_MODE_SEL (BIT2 | BIT1) 95 #define PHY_BCM542XX_MODE_CONTROL_REG_1000X_EN (BIT0) 96 #define PHY_BCM542XX_MODE_CONTROL_REG_1000X_DIS 0 97 98 #define MODE_SELECT_COPPER_2_QSGMII (0x0 << 1) 99 #define MODE_SELECT_FIBER_2_QSGMII (0x1 << 1) 100 #define MODE_SELECT_SGMII_2_COPPER (0x2 << 1) 101 #define MODE_SELECT_GBIC (0x3 << 1) 102 103 /* 104 * AUXILIARY CONTROL REG 105 */ 106 #define PHY_BCM542XX_AUX_CTRL_REG_OFFSET 0x028 107 108 /* 109 * COPPER_POWER_MII_CTRL Register 110 */ 111 #define PHY_BCM542XX_POWER_MII_CTRL_REG_OFFSET 0x02A 112 #define PHY_BCM542XX_POWER_MII_CTRL_SUPER_ISOLATE (BIT5) 113 114 /* 115 * SOFT_RESET Register 116 */ 117 #define PHY_BCM542XX_SOFT_RESET_REG_OFFSET 0x070 118 #define PHY_BCM542XX_SOFT_RESET_ISSUE_RESET (BIT0) 119 120 /* 121 * EEE Statistics Timers & Counters 122 */ 123 #define PHY_BCM542XX_EEE_STAT_RX_DURATION_REG_OFFSET 0x0AA 124 #define PHY_BCM542XX_EEE_STAT_TX_DURATION_REG_OFFSET 0x0AB 125 #define PHY_BCM542XX_EEE_STAT_TX_EVENTS_REG_OFFSET 0x0AC 126 #define PHY_BCM542XX_EEE_STAT_RX_EVENTS_REG_OFFSET 0x0AD 127 #define PHY_BCM542XX_EEE_STAT_CTRL_REG_OFFSET 0x0AF 128 #define PHY_BCM542XX_EEE_STAT_CTRL_COUNTERS_EN (BIT0) 129 #define PHY_BCM542XX_EEE_STAT_CTRL_COUNTERS_RESET (BIT1) 130 #define PHY_BCM542XX_EEE_STAT_CTRL_ACCESS_MODE (BIT12) 131 #define PHY_BCM542XX_EEE_STAT_CTRL_SATURATE_MODE (BIT13) 132 #define PHY_BCM542XX_EEE_STAT_CTRL_16U_BIT_SEL (BIT14) 133 134 /* 135 * HALT AGC ENC CTRL REG 136 */ 137 #define PHY_BCM542XX_HALT_AGC_CTRL_REG_OFFSET 0x0D8 138 139 /* 140 * EXPF5_TIME_SYNC 141 */ 142 #define PHY_BCM542XX_EXPF5_TIME_SYNC_REG_OFFSET 0x0F5 143 #define PHY_BCM542XX_EXPF5_TIME_SYNC_TX_SOP_10BT_EN (BIT8) 144 #define PHY_BCM542XX_EXPF5_TIME_SYNC_RX_SOP_10BT_EN (BIT7) 145 #define PHY_BCM542XX_EXPF5_TIME_SYNC_ENABLE (BIT0) 146 147 /* 148 * CORE_EXPFA Hidden Identifier 149 */ 150 #define PHY_BCM542XX_HIDDEN_IDENTIFIER_REG_OFFSET 0x0FA 151 #define PHY_BCM542XX_HIDDEN_REV_NUM_MASK (0x0F) 152 153 /* 154 * TDR_OVRIDE_VAL 155 */ 156 #define PHY_BCM542XX_TDR_OVRIDE_VAL_REG_OFFSET 0x0FB 157 158 /* 159 * ANLOG_PWR_CTRL_OVRIDE 160 */ 161 #define PHY_BCM542XX_ANLOG_PWR_CTRL_OVRIDE_REG_OFFSET 0x0FF 162 163 /* 164 * DSP_TAP10 165 */ 166 #define PHY_BCM542XX_DSP_TAP10_REG_OFFSET 0x125 167 168 /* 169 * DSP_TAP17_C0 170 */ 171 #define PHY_BCM542XX_DSP_TAP17_C0_REG_OFFSET 0x134 172 173 /* 174 * DSP_TAP17_C1 175 */ 176 #define PHY_BCM542XX_DSP_TAP17_C1_REG_OFFSET 0x135 177 178 /* 179 * DSP_TAP33_C2 180 */ 181 #define PHY_BCM542XX_DSP_TAP33_C2_REG_OFFSET 0x152 182 183 /* 184 * DSP_TAP34_C2 185 */ 186 #define PHY_BCM542XX_DSP_TAP34_C2_REG_OFFSET 0x156 187 188 /* 189 * AFE_RXCONFIG_0 190 */ 191 #define PHY_BCM542XX_AFE_RXCONFIG_0_REG_OFFSET 0x1C0 192 193 /* 194 * AFE_RXCONFIG_2 195 */ 196 #define PHY_BCM542XX_AFE_RXCONFIG_2_REG_OFFSET 0x1C2 197 198 /* 199 * AFE_VDACCTRL_1 200 */ 201 #define PHY_BCM542XX_AFE_VDACCTRL_1_REG_OFFSET 0x1C5 202 203 /* 204 * AFE_VDACCTRL_2 205 */ 206 #define PHY_BCM542XX_AFE_VDACCTRL_2_REG_OFFSET 0x1C6 207 208 /* 209 * AFE_PLLCTRL_4 210 */ 211 #define PHY_BCM542XX_AFE_AFE_PLLCTRL_4_REG_OFFSET 0x1CC 212 213 /* 214 * AFE_HPF_TRIM 215 */ 216 #define PHY_BCM542XX_AFE_HPF_TRIM_REG_OFFSET 0x1Cf 217 218 219 /* * 220 * * DIGX: DIG1000X/SERDES/SGMII Control Registers 221 */ 222 223 /* 224 * OPERATING MODE REGISTER 225 */ 226 #define PHY_BCM542XX_OPER_MODE_STATUS_REG_OFFSET 0x202 227 #define PHY_BCM542XX_OPER_MODE_STATUS_REG_SERDES_SPEED (BIT14 | BIT13) 228 #define PHY_BCM542XX_OPER_MODE_STATUS_SERDES_SPEED_1000 (2 << 13) 229 #define PHY_BCM542XX_OPER_MODE_STATUS_SERDES_SPEED_100 (1 << 13) 230 #define PHY_BCM542XX_OPER_MODE_STATUS_SERDES_SPEED_10 (0 << 13) 231 #define PHY_BCM542XX_OPER_MODE_STATUS_SERDES_DUPLEX (BIT12) 232 233 /* 234 * SERDES 100-FX CONTROL REGISTER 235 */ 236 #define PHY_BCM542XX_100FX_CTRL_REG_OFFSET 0x233 237 #define PHY_BCM542XX_100FX_CTRL_REG_RX_QUALIFY_DIS (BIT5) 238 #define PHY_BCM542XX_100FX_CTRL_REG_FD_FX_SERDES (BIT1) 239 #define PHY_BCM542XX_100FX_CTRL_REG_FX_SERDES_EN (BIT0) 240 241 242 /* External Serdes Control Reg., DIGX_SHD_1C_14, RDB_0x234 */ 243 #define PHY_BCM542XX_EXT_SERDES_REG_OFFSET 0x234 244 #define PHY_BCM542XX_EXT_SERDES_AUTO_FX (BIT6) 245 #define PHY_BCM542XX_EXT_SERDES_FX_FD (BIT5) 246 #define PHY_BCM542XX_EXT_SERDES_FX (BIT4) 247 #define PHY_BCM542XX_EXT_SERDES_LED (BIT3) 248 #define PHY_BCM542XX_EXT_SEL_SYNC_ST (BIT2) 249 #define PHY_BCM542XX_EXT_SELECT_SD (BIT1) 250 #define PHY_BCM542XX_EXT_SERDES_SEL (BIT0) 251 #define PHY_BCM542XX_EXT_SERDES_FX_MASK (PHY_BCM542XX_EXT_SERDES_FX | \ 252 PHY_BCM542XX_EXT_SERDES_AUTO_FX) 253 254 /* SGMII Slave Reg., DIGX_SHD_1C_15, RDB_0x235 */ 255 #define PHY_BCM542XX_SGMII_SLAVE_REG_OFFSET 0x235 256 257 258 #define PHY_BCM542XX_SGMII_SLAVE_AUTO (BIT0) 259 #define PHY_BCM542XX_SGMII_SLAVE_EN (BIT1) 260 #define PHY_BCM542XX_SGMII_DUPLEX (BIT8) 261 #define PHY_BCM542XX_SGMII_SPEED (BIT7 | BIT6) 262 #define PHY_BCM542XX_SGMII_SPEED_1000 (2 << 6) 263 #define PHY_BCM542XX_SGMII_SPEED_100 (1 << 6) 264 #define PHY_BCM542XX_SGMII_SPEED_10 (0 << 6) 265 266 /* AUTO Detect SGMII MC Reg., RDB_0x238 */ 267 #define PHY_BCM542XX_AUTO_DETECT_SGMII_MC_REG_OFFSET 0x238 268 #define PHY_BCM542XX_AUTO_DETECT_GMII_FIFO_JUMBO_LSB (BIT2) 269 270 /* * 271 * * SGMII REGISTERS 272 */ 273 274 /* 275 * SGMII CONTROL 276 * 277 * Note: Enabled by writing to Reg 0x1c, shadow 0x1f, bits[2:0] = 3'b'101 278 */ 279 #define PHY_BCM542XX_SGMII_CONTROL_REG_OFFSET 0x00 280 #define PHY_BCM542XX_SGMII_CONTROL_REG_RESET (BIT15) 281 #define PHY_BCM542XX_SGMII_CONTROL_REG_LOOPBACK (BIT14) 282 #define PHY_BCM542XX_SGMII_CONTROL_REG_SGMII_AN_EN (BIT12) 283 #define PHY_BCM542XX_SGMII_CONTROL_REG_POWER_DOWN (BIT11) 284 #define PHY_BCM542XX_SGMII_CONTROL_REG_RESTART_AN (BIT9) 285 #define PHY_BCM542XX_SGMII_CONTROL_REG_DUPLEX (BIT8) 286 287 288 /* * 289 * * TOP LVL RDB REGISTERS 290 */ 291 292 /* TOP level registers map into rdb address space of 0x0800 to 0x0fff 293 ADD 0x800 to top level regs 294 */ 295 296 #define BMACSEC_TOP_MISC_REG_SIZE 1 297 298 /* 299 * Top level regs: AutogrEEEn 300 */ 301 #define PHY_BCM542XX_TOP_MISC_MII_BUFF_CNTL_PHY0 0x800 302 #define PHY_BCM542XX_TOP_MISC_MII_BUFF_CNTL_PHYN(n) \ 303 (PHY_BCM542XX_TOP_MISC_MII_BUFF_CNTL_PHY0 + \ 304 BMACSEC_TOP_MISC_REG_SIZE*(n)*2/*skip one reg*/) 305 306 #define PHY_BCM542XX_TOP_MISC_MII_BUFF_WAKE_STATE_TIMER \ 307 (BIT13 | BIT12 | BIT11) 308 #define PHY_BCM542XX_TOP_MISC_MII_BUFF_WAIT_IFG_LEN \ 309 (BIT10 | BIT9 | BIT8) 310 #define PHY_BCM542XX_TOP_MISC_MII_BUFF_VAR_IFG_LEN \ 311 (BIT7 | BIT6 | BIT5 | BIT4 | BIT3) 312 #define PHY_BCM542XX_TOP_MISC_MII_BUFF_VAR_LAT_EN (BIT2) 313 #define PHY_BCM542XX_TOP_MISC_MII_BUFF_EN (BIT0) 314 315 /* 316 * Top Misc Top Cfg 317 */ 318 319 #define PHY_BCM542XX_TOP_MISC_TOP_CFG_REG_OFFSET 0x810 320 #define PHY_BCM542XX_TOP_MISC_CFG_REG_QSGMII_PHYA (BIT3) 321 #define PHY_BCM542XX_TOP_MISC_CFG_REG_QSGMII_SEL (BIT2) 322 323 /* 324 * Top Misc Boot Reg_0 325 */ 326 #define PHY_BCM542XX_TOP_MISC_BOOT_REG_0_OFFSET 0x818 327 328 /* 329 * Top Misc Boot Reg_1 330 */ 331 #define PHY_BCM542XX_TOP_MISC_BOOT_REG_1_OFFSET 0x819 332 333 /* 334 * Top Misc Global Reset 335 */ 336 #define PHY_BCM542XX_TOP_MISC_GLOBAL_RESET_OFFSET 0x82b 337 #define PHY_BCM542XX_TOP_MISC_GLOBAL_RESET_TOP_MII_SOFT (BIT15) 338 #define PHY_BCM542XX_TOP_MISC_GLOBAL_RESET_TIMESYNC (BIT10) 339 340 /* 341 * Top Interrupt Status 342 */ 343 #define PHY_BCM542XX_TOP_INTERRUPT_STATUS_OFFSET 0x82c 344 345 /* 346 * Top Interrupt Mask 347 */ 348 #define PHY_BCM542XX_TOP_INTERRUPT_MASK_OFFSET 0x82d 349 #define PHY_BCM542XX_TOP_INTERRUPT_MASK 0xff1 350 351 /* 352 * SYNCHRONOUS ETHERNET : SYNCE 353 */ 354 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_OFFSET 0x83C 355 356 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_AUTO_SW_STS (BIT15) 357 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_AUTO_SW_MODE (BIT9) 358 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_AUTO_CLK_DIS (BIT8) 359 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK2_DIS (BIT7) 360 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK2_SEL (BIT6 | BIT5 | BIT4) 361 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_DIS (BIT3) 362 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_SEL (BIT2 | BIT1 | BIT0) 363 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK1_EN (BIT14) 364 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK2_EN (BIT13) 365 366 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK_ENABLE (0) 367 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK_DIS \ 368 PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_DIS 369 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK_SEL \ 370 PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_SEL 371 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK_MASK \ 372 PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_MASK 373 374 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK2_SHIFT (4) 375 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK2_MASK \ 376 (PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK2_DIS | \ 377 PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK2_SEL) 378 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_SHIFT (0) 379 #define PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_MASK \ 380 (PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_DIS | \ 381 PHY_BCM542XX_SYNCE_RECOVERY_CLK_REG_REC_CLK1_SEL) 382 383 384 /* 385 * TOP_MISC_DATAPATH_SELECT 386 */ 387 #define PHY_BCM542XX_TOP_MISC_DPATH_SEL_REG_OFFSET 0x84a 388 389 #define PHY_BCM542XX_TOP_MISC_DPATH_SEL_REG_MACSEC_BPASS_PORT0 (BIT8) 390 #define PHY_BCM542XX_TOP_MISC_DPATH_SEL_REG_MACSEC_BPASS_PORTN(n) \ 391 ((PHY_BCM542XX_TOP_MISC_DPATH_SEL_REG_MACSEC_BPASS_PORT0) << (n)) 392 393 /* 394 * TOP_MISC_MACSEC_PWRDN 395 */ 396 #define PHY_BCM542XX_TOP_MISC_MACSEC_PWRDN_REG_OFFSET 0x84b 397 398 #define PHY_BCM542XX_TOP_MISC_MACSEC_PWRDN_REG_MDIO_EN (BIT15) 399 #define PHY_BCM542XX_TOP_MISC_MACSEC_PWRDN_REG_PHY_ADDR (0x1f << 10) 400 #define PHY_BCM542XX_TOP_MISC_MACSEC_PWRDN_REG_QUAD_PWRDN (BIT9 | BIT8) 401 #define PHY_BCM542XX_TOP_MISC_MACSEC_PWRDN_REG_SP_PWRDN_PORT0 (BIT0) 402 #define PHY_BCM542XX_TOP_MISC_MACSEC_PWRDN_REG_SP_PWRDN_PORTN(n) \ 403 ((PHY_BCM542XX_TOP_MISC_MACSEC_PWRDN_REG_SP_PWRDN_PORT0) << (n)) 404 405 /* 406 * TOP_MISC_MACSEC_RESET 407 */ 408 #define PHY_BCM542XX_TOP_MISC_MACSEC_RESET_REG_OFFSET 0x84c 409 410 #define PHY_BCM542XX_TOP_MISC_MACSEC_RESET_REG_QUAD_RST_1 (BIT9) 411 #define PHY_BCM542XX_TOP_MISC_MACSEC_RESET_REG_QUAD_RST_0 (BIT8) 412 #define PHY_BCM542XX_TOP_MISC_MACSEC_RESET_REG_RST_PORT0 (BIT0) 413 #define PHY_BCM542XX_TOP_MISC_MACSEC_RESET_REG_RST_PORTN(n) \ 414 (PHY_BCM542XX_TOP_MISC_MACSEC_RESET_REG_RST_PORT0 << (n)) 415 416 417 #define PHY_BCM542XX_TOP_MISC_MACSEC_PHYA_DUPLEX_CFG 0x84d 418 #define PHY_BCM542XX_TOP_MISC_MACSEC_PHYA_DUPLEX_CFG_REG_PHY_ADDR0 (0x1f << 8) 419 #define PHY_BCM542XX_TOP_MISC_MACSEC_PHYA_DUPLEX_CFG_REG_SP_SW_DUPLEX_PORT0 (BIT0) 420 #define PHY_BCM542XX_TOP_MISC_MACSEC_PHYA_DUPLEX_CFG_REG_SP_SW_DUPLEX_PORTN(n) \ 421 (PHY_BCM542XX_TOP_MISC_MACSEC_PHYA_DUPLEX_CFG_REG_SP_SW_DUPLEX_PORT0 << (n)) 422 423 424 #define PHY_BCM542XX_TOP_MISC_MACSEC_QSP_PORT_REG_OFFSET 0x872 425 #define PHY_BCM542XX_TOP_MISC_MACSEC_QSP_PORT_REG_QSP1_PORT_ADDR (0x1f << 5) 426 #define PHY_BCM542XX_TOP_MISC_MACSEC_QSP_PORT_REG_QSP0_PORT_ADDR (0x1f) 427 428 /* * 429 * * IEEE 1588 : Time Sync 430 */ 431 432 433 /* 434 * TOP_1588_SLICE_ENABLE 435 */ 436 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_REG_OFFSET 0xA10 437 438 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_RX_PORT7 (BIT15) 439 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_RX_PORT6 (BIT14) 440 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_RX_PORT5 (BIT13) 441 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_RX_PORT4 (BIT12) 442 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_RX_PORT3 (BIT11) 443 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_RX_PORT2 (BIT10) 444 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_RX_PORT1 (BIT9) 445 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_RX_PORT0 (BIT8) 446 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_TX_PORT7 (BIT7) 447 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_TX_PORT6 (BIT6) 448 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_TX_PORT5 (BIT5) 449 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_TX_PORT4 (BIT4) 450 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_TX_PORT3 (BIT3) 451 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_TX_PORT2 (BIT2) 452 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_TX_PORT1 (BIT1) 453 #define PHY_BCM542XX_TOP_1588_SLICE_EN_CTRL_TX_PORT0 (BIT0) 454 455 456 /* 457 * TOP_1588_TX_MODE_PORT_X 458 */ 459 #define SIZE_OF_PHY_BCM542XX_TOP_1588_REGS (0x01) 460 #define PHY_BCM542XX_TOP_1588_TX_MODE_PORT_0_OFFSET (0xA11) 461 #define PHY_BCM542XX_TOP_1588_TX_MODE_PORT_N_OFFSET(n) \ 462 (PHY_BCM542XX_TOP_1588_TX_MODE_PORT_0_OFFSET + \ 463 (SIZE_OF_PHY_BCM542XX_TOP_1588_REGS * (n))) 464 465 466 467 /* 468 * TOP_1588_RX_MODE_PORT_X 469 */ 470 #define PHY_BCM542XX_TOP_1588_RX_MODE_PORT_0_OFFSET (0xA19) 471 #define PHY_BCM542XX_TOP_1588_RX_MODE_PORT_N_OFFSET(n) \ 472 (PHY_BCM542XX_TOP_1588_RX_MODE_PORT_0_OFFSET + \ 473 (SIZE_OF_PHY_BCM542XX_TOP_1588_REGS * (n))) 474 475 476 /* 477 * TOP_1588_TX_TS_CAP 478 */ 479 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_REG_OFFSET (0xA21) 480 481 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_PORT7 (BIT7) 482 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_PORT6 (BIT6) 483 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_PORT5 (BIT5) 484 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_PORT4 (BIT4) 485 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_PORT3 (BIT3) 486 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_PORT2 (BIT2) 487 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_PORT1 (BIT1) 488 #define PHY_BCM542XX_TOP_1588_TX_TS_CAP_PORT0 (BIT0) 489 490 /* 491 * TOP_1588_RX_TS_CAP 492 */ 493 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_REG_OFFSET (0xA22) 494 495 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_PORT7 (BIT7) 496 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_PORT6 (BIT6) 497 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_PORT5 (BIT5) 498 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_PORT4 (BIT4) 499 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_PORT3 (BIT3) 500 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_PORT2 (BIT2) 501 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_PORT1 (BIT1) 502 #define PHY_BCM542XX_TOP_1588_RX_TS_CAP_PORT0 (BIT0) 503 504 505 /* 506 * TOP_1588_RX_PORT_N_LINK_DELAY_LSB 507 */ 508 #define PHY_BCM542XX_TOP_1588_RX_PORT0_LINK_DELAY_LSB_OFFSET (0xA24) 509 #define PHY_BCM542XX_TOP_1588_RX_PORTN_LINK_DELAY_LSB(N) \ 510 (PHY_BCM542XX_TOP_1588_RX_PORT0_LINK_DELAY_LSB_OFFSET \ 511 + (N) * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS \ 512 * (2) /*skip one MSB register*/) 513 514 515 /* 516 * TOP_1588_RX_PORT_N_LINK_DELAY_MSB 517 */ 518 #define PHY_BCM542XX_TOP_1588_RX_PORT0_LINK_DELAY_MSB_OFFSET (0xA25) 519 #define PHY_BCM542XX_TOP_1588_RX_PORTN_LINK_DELAY_MSB(N) \ 520 (PHY_BCM542XX_TOP_1588_RX_PORT0_LINK_DELAY_MSB_OFFSET \ 521 + (N) * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS \ 522 * (2) /*skip one MSB register*/) 523 524 525 /* 526 * TOP_1588_TX_PORT_N_TS_OFFSET_LSB 527 */ 528 #define PHY_BCM542XX_TOP_1588_TX_PORT_0_TS_OFFSET_LSB (0xA34) 529 #define PHY_BCM542XX_TOP_1588_TX_PORT_N_TS_OFFSET_LSB(N) \ 530 ( ((PHY_IS_BCM5428x(pc) || PHY_IS_BCM54210_220(pc)) \ 531 ? PHY_BCM542XX_TOP_1588_RX_PORT_0_TS_OFFSET_LSB \ 532 : PHY_BCM542XX_TOP_1588_TX_PORT_0_TS_OFFSET_LSB) \ 533 + (N) * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS \ 534 * (2) /*skip one MSB register*/ ) 535 /* 536 * TOP_1588_TX_PORT_N_TS_OFFSET_MSB 537 */ 538 #define PHY_BCM542XX_TOP_1588_TX_PORT_0_TS_OFFSET_MSB (0xA35) 539 #define PHY_BCM542XX_TOP_1588_TX_PORT_N_TS_OFFSET_MSB(N) \ 540 ( ((PHY_IS_BCM5428x(pc) || PHY_IS_BCM54210_220(pc)) \ 541 ? PHY_BCM542XX_TOP_1588_RX_PORT_0_TS_OFFSET_MSB \ 542 : PHY_BCM542XX_TOP_1588_TX_PORT_0_TS_OFFSET_MSB) \ 543 + (N) * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS \ 544 * (2) /*skip one LSB register*/ ) 545 546 #define PHY_BCM542XX_TOP_1588_TX_PORT_N_TS_OFFSET_TX_MSB (BIT3 | BIT2 | BIT1 | BIT0) 547 548 549 /* 550 * TOP_1588_RX_PORT_N_TS_OFFSET_LSB 551 */ 552 #define PHY_BCM542XX_TOP_1588_RX_PORT_0_TS_OFFSET_LSB (0xA44) 553 #define PHY_BCM542XX_TOP_1588_RX_PORT_N_TS_OFFSET_LSB(N) \ 554 ( ((PHY_IS_BCM5428x(pc) || PHY_IS_BCM54210_220(pc)) \ 555 ? PHY_BCM542XX_TOP_1588_TX_PORT_0_TS_OFFSET_LSB \ 556 : PHY_BCM542XX_TOP_1588_RX_PORT_0_TS_OFFSET_LSB) \ 557 + (N) * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS \ 558 * (2) /*skip one MSB register*/ ) 559 /* 560 * TOP_1588_RX_PORT_N_TS_OFFSET_MSB 561 */ 562 #define PHY_BCM542XX_TOP_1588_RX_PORT_0_TS_OFFSET_MSB (0xA45) 563 #define PHY_BCM542XX_TOP_1588_RX_PORT_N_TS_OFFSET_MSB(N) \ 564 ( ((PHY_IS_BCM5428x(pc) || PHY_IS_BCM54210_220(pc)) \ 565 ? PHY_BCM542XX_TOP_1588_TX_PORT_0_TS_OFFSET_MSB \ 566 : PHY_BCM542XX_TOP_1588_RX_PORT_0_TS_OFFSET_MSB) \ 567 + (N) * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS \ 568 * (2) /*skip one LSB register*/ ) 569 570 #define PHY_BCM542XX_TOP_1588_RX_PORT_N_TS_OFFSET_RX_MSB (BIT3 | BIT2 | BIT1 | BIT0) 571 572 573 /* 574 * TOP_1588_TIME_CODE_0 575 */ 576 #define PHY_BCM542XX_TOP_1588_TIME_CODE_0_REG_OFFSET (0xA54) 577 578 579 /* 580 * TOP_1588_TIME_CODE_1 581 */ 582 #define PHY_BCM542XX_TOP_1588_TIME_CODE_1_REG_OFFSET (0xA55) 583 584 585 /* 586 * TOP_1588_TIME_CODE_2 587 */ 588 #define PHY_BCM542XX_TOP_1588_TIME_CODE_2_REG_OFFSET (0xA56) 589 590 591 /* 592 * TOP_1588_TIME_CODE_3 593 */ 594 #define PHY_BCM542XX_TOP_1588_TIME_CODE_3_REG_OFFSET (0xA57) 595 596 597 /* 598 * TOP_1588_TIME_CODE_4 599 */ 600 #define PHY_BCM542XX_TOP_1588_TIME_CODE_4_REG_OFFSET (0xA58) 601 602 /* 603 * TOP_1588_DPLL_DB_SEL 604 */ 605 #define PHY_BCM542XX_TOP_1588_DPLL_DB_SEL_REG_OFFSET (0xA5B) 606 #define PHY_BCM542XX_TOP_1588_DPLL_DB_SEL_RSVD (BIT8) 607 608 /* 609 * TOP_1588_SHD_CTL 610 */ 611 #define PHY_BCM542XX_TOP_1588_SHD_CTL_REG_OFFSET (0xA5C) 612 613 614 /* 615 * TOP_1588_SHD_LD 616 */ 617 #define PHY_BCM542XX_TOP_1588_SHD_LD_REG_OFFSET (0xA5D) 618 619 620 /* 621 * TOP_1588_INT_MASK 622 */ 623 #define PHY_BCM542XX_TOP_1588_INT_MASK_REG_OFFSET (0xA5E) 624 625 626 /* 627 * TOP_1588_INT 628 */ 629 #define PHY_BCM542XX_TOP_1588_INT_STATUS_REG_OFFSET (0xA5F) 630 631 632 /* 633 * TOP_1588_TX_CTL 634 */ 635 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_OFFSET (0xA60) 636 637 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_RX_AS_DS_EN (BIT7) 638 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_RX_L2_DS_EN (BIT6) 639 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_RX_L4_IP_ADDR_EN (BIT5) 640 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_RX_L4_IPV6_ADDR_EN (BIT4) 641 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_TX_AS_EN (BIT3) 642 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_TX_L2_EN (BIT2) 643 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_TX_IPV4_UDP_EN (BIT1) 644 #define PHY_BCM542XX_TOP_1588_TX_CTL_REG_TX_IPV6_UDP_EN (BIT0) 645 646 /* 647 * TOP_1588_RX_CTL 648 */ 649 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_OFFSET (0xA61) 650 651 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_RX_AS_DS_EN (BIT7) 652 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_RX_L2_DS_EN (BIT6) 653 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_RX_L4_IP_ADDR_EN (BIT5) 654 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_RX_L4_IPV6_ADDR_EN (BIT4) 655 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_RX_AS_EN (BIT3) 656 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_RX_L2_EN (BIT2) 657 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_RX_IPV4_UDP_EN (BIT1) 658 #define PHY_BCM542XX_TOP_1588_RX_CTL_REG_RX_IPV6_UDP_EN (BIT0) 659 660 661 /* 662 * TOP_1588_RX_TX_CTL 663 */ 664 #define PHY_BCM542XX_TOP_1588_RX_TX_CTL_REG_OFFSET (0xA62) 665 666 #define PHY_BCM542XX_TOP_1588_RX_TX_CTL_REG_TX_CRC_EN (BIT7) 667 #define PHY_BCM542XX_TOP_1588_RX_TX_CTL_REG_RX_CRC_EN (BIT3) 668 669 670 671 /* 672 * TOP_1588_VLAN_ITPID 673 */ 674 #define PHY_BCM542XX_TOP_1588_VLAN_ITPID_REG_OFFSET (0xA63) 675 676 /* 677 * TOP_1588_VLAN_OTPID 678 */ 679 #define PHY_BCM542XX_TOP_1588_VLAN_OTPID_REG_OFFSET (0xA64) 680 681 /* 682 * TOP_1588_OTHER_OTPID 683 */ 684 #define PHY_BCM542XX_TOP_1588_OTHER_OTPID_REG_OFFSET (0xA65) 685 686 /* 687 * TOP_1588_NSE_DPLL_2_0 688 */ 689 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_2_0_REG_OFFSET (0xA67) 690 691 /* 692 * TOP_1588_NSE_DPLL_2_1 693 */ 694 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_2_1_REG_OFFSET (0xA68) 695 696 697 /* 698 * TOP_1588_NSE_DPLL_2_2 699 */ 700 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_2_2_REG_OFFSET (0xA69) 701 702 /* 703 * TOP_1588_NSE_DPLL_3_LSB 704 */ 705 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_3_LSB_REG_OFFSET (0xA6A) 706 707 /* 708 * TOP_1588_NSE_DPLL_3_MSB 709 */ 710 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_3_MSB_REG_OFFSET (0xA6B) 711 712 713 714 /* 715 * TOP_1588_NSE_DPLL_4 716 */ 717 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_4_REG_OFFSET (0xA6C) 718 719 /* 720 * TOP_1588_NSE_DPLL_5 721 */ 722 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_5_REG_OFFSET (0xA6D) 723 724 /* 725 * TOP_1588_NSE_DPLL_6 726 */ 727 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_6_REG_OFFSET (0xA6E) 728 729 730 /* 731 * TOP_1588_NSE_DPLL_7_0 732 */ 733 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_7_0_REG_OFFSET (0xA6F) 734 735 736 /* 737 * TOP_1588_NSE_DPLL_7_1 738 */ 739 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_7_1_REG_OFFSET (0xA70) 740 741 742 /* 743 * TOP_1588_NSE_DPLL_7_2 744 */ 745 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_7_2_REG_OFFSET (0xA71) 746 747 748 /* 749 * TOP_1588_NSE_DPLL_7_3 750 */ 751 #define PHY_BCM542XX_TOP_1588_NSE_DPLL_7_3_REG_OFFSET (0xA72) 752 753 754 /* TOP_1588_NSE_NCO_1_0 -- TOP_1588_NSE_NCO_1_1 */ 755 #define PHY_BCM542XX_TOP_1588_NSE_NCO_1_0_REG_OFFSET (0xA73) 756 #define PHY_BCM542XX_TOP_1588_NSE_NCO_1_1_REG_OFFSET (0xA74) 757 758 /* TOP_1588_NSE_NCO_2_0 -- TOP_1588_NSE_NCO_2_2 */ 759 #define PHY_BCM542XX_TOP_1588_NSE_NCO_2_0_REG_OFFSET (0xA75) 760 #define PHY_BCM542XX_TOP_1588_NSE_NCO_2_1_REG_OFFSET (0xA76) 761 #define PHY_BCM542XX_TOP_1588_NSE_NCO_2_2_REG_OFFSET (0xA77) 762 763 #define PHY_BCM542XX_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL (BIT14) 764 765 /* 766 * TOP_1588_NSE_NCO_3_0 767 */ 768 #define PHY_BCM542XX_TOP_1588_NSE_NCO_3_0_REG_OFFSET (0xA78) 769 770 /* 771 * TOP_1588_NSE_NCO_3_1 772 */ 773 #define PHY_BCM542XX_TOP_1588_NSE_NCO_3_1_REG_OFFSET (0xA79) 774 775 776 /* 777 * TOP_1588_NSE_NCO_3_2 778 */ 779 #define PHY_BCM542XX_TOP_1588_NSE_NCO_3_2_REG_OFFSET (0xA7A) 780 781 782 /* 783 * TOP_1588_NSE_NCO_4 784 */ 785 #define PHY_BCM542XX_TOP_1588_NSE_NCO_4_REG_OFFSET (0xA7B) 786 787 /* 788 * TOP_1588_NSE_NCO_5_0 789 */ 790 #define PHY_BCM542XX_TOP_1588_NSE_NCO_5_0_REG_OFFSET (0xA7C) 791 792 793 /* 794 * TOP_1588_NSE_NCO_5_1 795 */ 796 #define PHY_BCM542XX_TOP_1588_NSE_NCO_5_1_REG_OFFSET (0xA7D) 797 798 799 /* 800 * TOP_1588_NSE_NCO_5_2 801 */ 802 #define PHY_BCM542XX_TOP_1588_NSE_NCO_5_2_REG_OFFSET (0xA7E) 803 804 /* 805 * DISABLE_USGMII 806 */ 807 #define PHY_BCM542XX_DISABLE_USGMII (0x0810) 808 #define PHY_BCM542XX_DISABLE_USGMII_6U_BIT_SEL (BIT6) 809 810 /* 811 * TOP_1588_NSE_NCO_6 812 */ 813 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_REG_OFFSET (0xA7f) 814 815 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_GMODE (BIT15 | BIT14) 816 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_GMODE_SHIFT (14) 817 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_TS_CAP (BIT13) 818 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_FRMSYN_EN (BIT12) 819 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_FRMSYN_MODE (BIT5 | BIT4 | BIT3 | BIT2) 820 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_FRMSYN_MODE_SHIFT (2) 821 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_SYNCOUT_MODE (BIT1 | BIT0) 822 #define PHY_BCM542XX_TOP_1588_NSE_NCO_6_SYNCOUT_MODE_SHIFT (0) 823 824 /* 825 * 1588_NSE_DPLL_NCO_7_0 826 */ 827 #define PHY_BCM542XX_1588_NSE_DPLL_NCO_7_0_REG_OFFSET (0xA80) 828 829 /* 830 * 1588_NSE_DPLL_NCO_7_1 831 */ 832 #define PHY_BCM542XX_1588_NSE_DPLL_NCO_7_1_REG_OFFSET (0xA81) 833 834 835 /* 836 * TOP_1588_TS_HB_RD_START_END 837 */ 838 #define PHY_BCM542XX_TOP_1588_TS_RD_START_END_REG_OFFSET (0xA85) 839 840 #define PHY_BCM542XX_TOP_1588_TS_RD_END(n) (BIT1 << (2*n)) 841 #define PHY_BCM542XX_TOP_1588_TS_RD_START(n) (BIT0 << (2*n)) 842 #define PHY_BCM542XX_TOP_1588_TS_RD_START_END_ALL (0xffff) 843 /* 844 * TOP_1588_HEARTBEAT_0 845 */ 846 #define PHY_BCM542XX_TOP_1588_HEARTBEAT_0_REG_OFFSET (0xA86) 847 848 /* 849 * TOP_1588_HEARTBEAT_1 850 */ 851 #define PHY_BCM542XX_TOP_1588_HEARTBEAT_1_REG_OFFSET (0xA87) 852 853 854 /* 855 * TOP_1588_HEARTBEAT_2 856 */ 857 #define PHY_BCM542XX_TOP_1588_HEARTBEAT_2_REG_OFFSET (0xA88) 858 859 /* 860 * TOP_1588_TIMESTAMP_0 861 */ 862 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_0_REG_OFFSET (0xA89) 863 864 865 /* 866 * TOP_1588_TIMESTAMP_1 867 */ 868 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_1_REG_OFFSET (0xA8A) 869 870 /* 871 * TOP_1588_TIMESTAMP_2 872 */ 873 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_2_REG_OFFSET (0xA8B) 874 875 /* 876 * TOP_1588_TIMESTAMP_INFO_1 877 */ 878 #define PHY_BCM542XX_TOP_1588_TS_INFO_1_REG_OFFSET (0xA8C) 879 #define PHY_BCM542XX_TOP_1588_TS_INFO_DOMAIN_NUM (0x1fe0) 880 #define PHY_BCM542XX_TOP_1588_TS_INFO_DOMAIN_NUM_SHIFT 3 881 #define PHY_BCM542XX_TOP_1588_TS_INFO_MSG_TYPE (0x001e) 882 #define PHY_BCM542XX_TOP_1588_TS_INFO_MSG_TYPE_SHIFT 1 883 #define PHY_BCM542XX_TOP_1588_TS_INFO_DIR (0x0001) 884 #define PHY_BCM542XX_TOP_1588_TS_INFO_DIR_SHIFT 0 885 886 /* 887 * TOP_1588_TIMESTAMP_INFO_2 888 */ 889 #define PHY_BCM542XX_TOP_1588_TS_INFO_2_REG_OFFSET (0xA8D) 890 #define PHY_BCM542XX_TOP_1588_TS_INFO_SEQ_ID (0xffff) 891 #define PHY_BCM542XX_TOP_1588_TS_INFO_SEQ_ID_SHIFT (0) 892 893 /* 894 * TOP_1588_CNTR_DBG 895 */ 896 #define PHY_BCM542XX_TOP_1588_CNTR_DBG_REG_OFFSET (0xA8E) 897 #define PHY_BCM542XX_TOP_1588_CNTR_DBG_TS_SLICE_SEL (BIT9|BIT8|BIT7) 898 #define PHY_BCM542XX_TOP_1588_CNTR_DBG_CTRL_SLICE_SEL (BIT4|BIT3|BIT2) 899 #define CNTR_DBG_TS_SLICE_SEL_SHIFT (7) 900 #define PHY_BCM542XX_TOP_1588_CNTR_DBG_HB_RD_START (BIT10) 901 #define PHY_BCM542XX_TOP_1588_CNTR_DBG_HB_RD_END (BIT11) 902 #define PHY_BCM542XX_TOP_1588_CNTR_DBG_HB_CNTL \ 903 (PHY_BCM542XX_TOP_1588_CNTR_DBG_HB_RD_START | \ 904 PHY_BCM542XX_TOP_1588_CNTR_DBG_HB_RD_END) 905 906 907 /* 908 * TOP_1588_MPLS_SPARE5 909 */ 910 #define PHY_BCM542XX_TOP_1588_MPLS_SPARE5_REG_OFFSET (0xA93) 911 912 913 914 /* 915 * TOP_1588_MPLS_SPARE6 916 */ 917 #define PHY_BCM542XX_TOP_1588_MPLS_SPARE6_REG_OFFSET (0xA94) 918 919 #define PHY_BCM542XX_TOP_1588_MPLS_SPARE6_SP_LBL (BIT3 | BIT2 | BIT1 | BIT0) 920 921 /* 922 * TOP_1588_MPLS_TX_CNTL 923 */ 924 #define PHY_BCM542XX_TOP_1588_MPLS_TX_CNTL_REG_OFFSET (0xA95) 925 926 #define PHY_BCM542XX_TOP_1588_MPLS_TX_CNTL_REG_ENTROPY_EN (BIT4) 927 #define PHY_BCM542XX_TOP_1588_MPLS_TX_CNTL_REG_CW_DIS (BIT3) 928 #define PHY_BCM542XX_TOP_1588_MPLS_TX_CNTL_REG_MPLS_EN (BIT2) 929 #define PHY_BCM542XX_TOP_1588_MPLS_TX_CNTL_REG_MPLS_SP_LBL_EN (BIT1) 930 931 /* 932 * TOP_1588_MPLS_RX_CNTL 933 */ 934 #define PHY_BCM542XX_TOP_1588_MPLS_RX_CNTL_REG_OFFSET (0xA96) 935 936 #define PHY_BCM542XX_TOP_1588_MPLS_RX_CNTL_REG_ENTROPY_EN (BIT4) 937 #define PHY_BCM542XX_TOP_1588_MPLS_RX_CNTL_REG_CW_DIS (BIT3) 938 #define PHY_BCM542XX_TOP_1588_MPLS_RX_CNTL_REG_MPLS_EN (BIT2) 939 #define PHY_BCM542XX_TOP_1588_MPLS_RX_CNTL_REG_MPLS_SP_LBL_EN (BIT1) 940 941 942 943 944 /* 945 * TOP_1588_MPLS_LABEL_N_LSB_MASK 946 */ 947 948 #define PHY_BCM542XX_TOP_1588_NEXT_LABEL_OFFSET 4 949 950 #define PHY_BCM542XX_TOP_1588_LABEL1_LSB_MASK_REG_OFFSET (0xA97) 951 #define PHY_BCM542XX_TOP_1588_LABEL_N_LSB_MASK_REG_OFFSET(n) \ 952 (PHY_BCM542XX_TOP_1588_LABEL1_LSB_MASK_REG_OFFSET \ 953 + (n) * PHY_BCM542XX_TOP_1588_NEXT_LABEL_OFFSET \ 954 * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS) 955 956 /* 957 * TOP_1588_MPLS_LABEL_N_MSB_MASK 958 */ 959 #define PHY_BCM542XX_TOP_1588_LABEL1_MSB_MASK_REG_OFFSET (0xA98) 960 #define PHY_BCM542XX_TOP_1588_LABEL_N_MSB_MASK_REG_OFFSET(n) \ 961 (PHY_BCM542XX_TOP_1588_LABEL1_MSB_MASK_REG_OFFSET \ 962 + (n) * PHY_BCM542XX_TOP_1588_NEXT_LABEL_OFFSET \ 963 * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS) 964 #define PHY_BCM542XX_TOP_1588_CAP_SRC_PORT_CLK_ID (BIT13) 965 #define PHY_BCM542XX_TOP_1588_MATCH_SRC_PORT_NUM (BIT14) 966 #define PHY_BCM542XX_TOP_1588_MATCH_VLAN_ID (BIT15) 967 968 /* 969 * TOP_1588_MPLS_LABEL_N_LSB_VAL 970 */ 971 #define PHY_BCM542XX_TOP_1588_LABEL1_LSB_VAL_REG_OFFSET (0xA99) 972 #define PHY_BCM542XX_TOP_1588_LABEL_N_LSB_VAL_REG_OFFSET(n) \ 973 (PHY_BCM542XX_TOP_1588_LABEL1_LSB_VAL_REG_OFFSET \ 974 + (n) * PHY_BCM542XX_TOP_1588_NEXT_LABEL_OFFSET \ 975 * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS) 976 977 /* 978 * TOP_1588_MPLS_LABEL_N_MSB_VAL 979 */ 980 #define PHY_BCM542XX_TOP_1588_LABEL1_MSB_VAL_REG_OFFSET (0xA9A) 981 #define PHY_BCM542XX_TOP_1588_LABEL_N_MSB_VAL_REG_OFFSET(n) \ 982 (PHY_BCM542XX_TOP_1588_LABEL1_MSB_VAL_REG_OFFSET \ 983 + (n) * PHY_BCM542XX_TOP_1588_NEXT_LABEL_OFFSET \ 984 * SIZE_OF_PHY_BCM542XX_TOP_1588_REGS) 985 986 /* 987 * TOP_1588_MPLS_LABEL10_LSB_MASK 988 */ 989 #define PHY_BCM542XX_TOP_1588_LABEL10_LSB_MASK_REG_OFFSET (0xABB) 990 #define PHY_BCM542XX_TOP_1588_PORT_N_TX_HSR_EN(port) (BIT0 << port) 991 #define PHY_BCM542XX_TOP_1588_PORT_N_RX_HSR_EN(port) (BIT8 << port) 992 993 /* 994 * TOP_1588_RX_CF 995 */ 996 #define PHY_BCM542XX_TOP_1588_RX_CF_REG_OFFSET (0xAC0) 997 #define PHY_BCM542XX_TOP_1588_RX_CF_UPD(dev_port) (1 << ((dev_port)<<1)) 998 #define PHY_BCM542XX_TOP_1588_RX_CS_UPD(dev_port) (2 << ((dev_port)<<1)) 999 /* (x << ((dev_port)*2)) */ 1000 /* 1001 * TOP_1588_TX_CS_UPD 1002 */ 1003 #define PHY_BCM542XX_TOP_1588_TX_CS_UPD_REG_OFFSET (0xAC1) 1004 #define PHY_BCM542XX_TOP_1588_TX_CS_UPD_MODE2(dev_port) (1 << ((dev_port)<<1)) 1005 #define PHY_BCM542XX_TOP_1588_TX_CS_UPD_MODE3(dev_port) (2 << ((dev_port)<<1)) 1006 /* (x << ((dev_port)*2)) */ 1007 1008 /* 1009 * TOP_1588_TIMECODE_SEL 1010 */ 1011 #define PHY_BCM542XX_TOP_1588_64b_TIMECODE_SEL_REG_OFFSET (0xAC3) 1012 #define PHY_BCM542XX_TOP_1588_64b_TIMECODE_SEL_RX_0 (BIT8) 1013 #define PHY_BCM542XX_TOP_1588_64b_TIMECODE_SEL_RX_N(port) \ 1014 (PHY_BCM542XX_TOP_1588_64b_TIMECODE_SEL_RX_0 << port) 1015 #define PHY_BCM542XX_TOP_1588_64b_TIMECODE_SEL_TX_0 (BIT0) 1016 #define PHY_BCM542XX_TOP_1588_64b_TIMECODE_SEL_TX_N(port) \ 1017 (PHY_BCM542XX_TOP_1588_64b_TIMECODE_SEL_TX_0 << port) 1018 1019 /* 1020 * TOP_1588_DM_TX_CNTL 1021 */ 1022 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_REG_OFFSET (0xAC6) 1023 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_EN (BIT0) 1024 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_MAC_EN (BIT1) 1025 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_CW_EN (BIT2) 1026 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_ENTROPY_EN (BIT3) 1027 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL (BIT4) 1028 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_BHH_TS_SEL (BIT5) 1029 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_IETF_EN (BIT14) 1030 #define PHY_BCM542XX_TOP_1588_DM_TX_CNTL_1588_CNT_EN (BIT15) 1031 1032 /* 1033 * TOP_1588_DM_RX_CNTL 1034 */ 1035 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_REG_OFFSET (0xAC7) 1036 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_EN (BIT0) 1037 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_MAC_EN (BIT1) 1038 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_CW_EN (BIT2) 1039 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_ENTROPY_EN (BIT3) 1040 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL (BIT4) 1041 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_BHH_TS_SEL (BIT5) 1042 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_IETF_EN (BIT14) 1043 #define PHY_BCM542XX_TOP_1588_DM_RX_CNTL_1588_CNT_EN (BIT15) 1044 1045 /* 1046 * TOP_1588_DM_ETHTYPE1 1047 */ 1048 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE1_REG_OFFSET (0xAC8) 1049 1050 /* 1051 * TOP_1588_DM_ETHTYPE2 1052 */ 1053 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE2_REG_OFFSET (0xAC9) 1054 1055 /* 1056 * TOP_1588_DM_ETHTYPE3 1057 */ 1058 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE3_REG_OFFSET (0xACA) 1059 1060 /* 1061 * TOP_1588_DM_ETHTYPE4 1062 */ 1063 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE4_REG_OFFSET (0xACB) 1064 1065 /* 1066 * TOP_1588_DM_ETHTYPE5 1067 */ 1068 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE5_REG_OFFSET (0xACC) 1069 1070 /* 1071 * TOP_1588_DM_ETHTYPE6 1072 */ 1073 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE6_REG_OFFSET (0xACD) 1074 1075 /* 1076 * TOP_1588_DM_ETHTYPE7 1077 */ 1078 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE7_REG_OFFSET (0xACE) 1079 1080 /* 1081 * TOP_1588_DM_ETHTYPE8 1082 */ 1083 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE8_REG_OFFSET (0xACF) 1084 1085 /* 1086 * TOP_1588_DM_ETHTYPE9 1087 */ 1088 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE9_REG_OFFSET (0xAD0) 1089 1090 /* 1091 * TOP_1588_DM_ETHTYPE10 1092 */ 1093 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE10_REG_OFFSET (0xAD1) 1094 1095 /* 1096 * TOP_1588_DM_ETHTYPE11 1097 */ 1098 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE11_REG_OFFSET (0xAD2) 1099 1100 /* 1101 * TOP_1588_DM_ETHTYPE12 1102 */ 1103 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE12_REG_OFFSET (0xAD3) 1104 1105 /* 1106 * TOP_1588_DM_ETHTYPE13 1107 */ 1108 #define PHY_BCM542XX_TOP_1588_DM_ETHTYPE13_REG_OFFSET (0xAD4) 1109 1110 /* 1111 * TOP_1588_DM_MAC_L1_0 1112 */ 1113 #define PHY_BCM542XX_TOP_1588_DM_MAC_L1_0_REG_OFFSET (0xAE0) 1114 1115 /* 1116 * TOP_1588_DM_MAC_L1_1 1117 */ 1118 #define PHY_BCM542XX_TOP_1588_DM_MAC_L1_1_REG_OFFSET (0xAE1) 1119 1120 /* 1121 * TOP_1588_DM_MAC_L1_2 1122 */ 1123 #define PHY_BCM542XX_TOP_1588_DM_MAC_L1_2_REG_OFFSET (0xAE2) 1124 1125 1126 /* 1127 * TOP_1588_DM_MAC_L2_0 1128 */ 1129 #define PHY_BCM542XX_TOP_1588_DM_MAC_L2_0_REG_OFFSET (0xAE3) 1130 1131 1132 /* 1133 * TOP_1588_DM_MAC_L2_1 1134 */ 1135 #define PHY_BCM542XX_TOP_1588_DM_MAC_L2_1_REG_OFFSET (0xAE4) 1136 1137 1138 /* 1139 * TOP_1588_DM_MAC_L2_2 1140 */ 1141 #define PHY_BCM542XX_TOP_1588_DM_MAC_L2_2_REG_OFFSET (0xAE5) 1142 1143 1144 /* 1145 * TOP_1588_DM_MAC_L3_0 1146 */ 1147 #define PHY_BCM542XX_TOP_1588_DM_MAC_L3_0_REG_OFFSET (0xAE6) 1148 1149 1150 /* 1151 * TOP_1588_DM_MAC_L3_1 1152 */ 1153 #define PHY_BCM542XX_TOP_1588_DM_MAC_L3_1_REG_OFFSET (0xAE7) 1154 1155 1156 /* 1157 * TOP_1588_DM_MAC_L3_2 1158 */ 1159 #define PHY_BCM542XX_TOP_1588_DM_MAC_L3_2_REG_OFFSET (0xAE8) 1160 1161 1162 /* 1163 * TOP_1588_DM_MAC_CTL_0 1164 */ 1165 #define PHY_BCM542XX_TOP_1588_DM_MAC_CTL_0_REG_OFFSET (0xAE9) 1166 1167 /* 1168 * TOP_1588_DM_MAC_CTL_1 1169 */ 1170 #define PHY_BCM542XX_TOP_1588_DM_MAC_CTL_1_REG_OFFSET (0xAEA) 1171 1172 /* 1173 * TOP_1588_SOP_SEL 1174 */ 1175 #define PHY_BCM542XX_TOP_1588_SOP_SEL_REG_OFFSET (0xAF8) 1176 1177 #define PHY_BCM542XX_TOP_1588_SOP_SEL_TX_PORT_0_SHIFT (0) 1178 #define PHY_BCM542XX_TOP_1588_SOP_SEL_RX_PORT_0_SHIFT (8) 1179 #define PHY_BCM542XX_TOP_1588_SOP_SEL_TX_PORT_N(port) \ 1180 ((port) << PHY_BCM542XX_TOP_1588_SOP_SEL_TX_PORT_0_SHIFT) 1181 #define PHY_BCM542XX_TOP_1588_SOP_SEL_RX_PORT_N(port) \ 1182 ((port) << PHY_BCM542XX_TOP_1588_SOP_SEL_RX_PORT_0_SHIFT) 1183 1184 /* 1185 * TOP_1588_INBAND_CNTL_n 1186 */ 1187 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_0_REG_OFFSET (0xAEE) 1188 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_N_REG_OFFSET(port_offset) \ 1189 (PHY_BCM542XX_TOP_1588_INBAND_CNTL_0_REG_OFFSET + (port_offset)) 1190 1191 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_IP_ADDR_EN (BIT15) 1192 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_IP_MAC_SEL (BIT14) 1193 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_TS_SEL (BIT13) 1194 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_TS_UPD_DELAY_RSP (BIT12) 1195 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_TS_UPD_FOLLOW_UP (BIT11) 1196 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_TS_CAP_MODE (BIT10) 1197 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_RESV0_ID_UPDATE (BIT9) 1198 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_RESV0_ID_CHECK (BIT8) 1199 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_RESV0_ID (BIT4|BIT5|BIT6|BIT7) 1200 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_PDELAY_RESP_EN (BIT3) 1201 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_PDELAY_REQ_EN (BIT2) 1202 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_DELAY_REQ_EN (BIT1) 1203 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_SYNC_EN (BIT0) 1204 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_EN (BIT0|BIT1|BIT2|BIT3) 1205 1206 #define PHY_BCM542XX_TOP_1588_INBAND_CNTL_RESV0_ID_SHIFT (4) 1207 /* 1208 * TOP_1588_MEM_COUNTER 1209 */ 1210 #define PHY_BCM542XX_TOP_1588_MEM_COUNTER_REG_OFFSET (0xAF6) 1211 #define PHY_BCM542XX_TOP_1588_MEM_COUNTER (0xffff) 1212 1213 /* 1214 * TOP_1588_TIMESTAMP_DELTA 1215 */ 1216 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_REG_OFFSET (0xAF7) 1217 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_80BIT (BIT15) 1218 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_48BIT (BIT14) 1219 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_VALUE_SIGN (BIT13) 1220 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_VALUE_MASK (0x3fff) 1221 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_VALUE_SIGN_EXT \ 1222 (~PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_VALUE_MASK) 1223 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_VALUE_MAX (8191) 1224 #define PHY_BCM542XX_TOP_1588_TIMESTAMP_DELTA_VALUE_MIN (-8192) 1225 1226 /* 1227 * TOP_1588_SOP_SEL 1228 */ 1229 #define PHY_BCM542XX_TOP_1588_SOP_SEL_REG_OFFSET (0xAF8) 1230 #define PHY_BCM542XX_TOP_1588_SOP_SEL_RX_PORTN(port) (BIT8 << (port)) 1231 #define PHY_BCM542XX_TOP_1588_SOP_SEL_TX_PORTN(port) (BIT0 << (port)) 1232 1233 /* 1234 * TOP_1588_TIMESTAMP_INFO_3 1235 */ 1236 #define PHY_BCM542XX_TOP_1588_TS_INFO_3_REG_OFFSET (0xAF9) 1237 #define PHY_BCM542XX_TOP_1588_TS_INFO_MAC_DA_1 (0xffff) 1238 #define PHY_BCM542XX_TOP_1588_TS_INFO_SRC_PORT_CLK_ID_1 (0xffff) 1239 1240 /* 1241 * TOP_1588_TIMESTAMP_INFO_4 1242 */ 1243 #define PHY_BCM542XX_TOP_1588_TS_INFO_4_REG_OFFSET (0xAFA) 1244 #define PHY_BCM542XX_TOP_1588_TS_INFO_MAC_DA_2 (0xffff) 1245 #define PHY_BCM542XX_TOP_1588_TS_INFO_SRC_PORT_CLK_ID_2 (0xffff) 1246 1247 /* 1248 * TOP_1588_TIMESTAMP_INFO_5 1249 */ 1250 #define PHY_BCM542XX_TOP_1588_TS_INFO_5_REG_OFFSET (0xAFB) 1251 #define PHY_BCM542XX_TOP_1588_TS_INFO_MAC_DA_3 (0xffff) 1252 #define PHY_BCM542XX_TOP_1588_TS_INFO_SRC_PORT_CLK_ID_3 (0xffff) 1253 1254 /* 1255 * TOP_1588_TIMESTAMP_INFO_6 1256 */ 1257 #define PHY_BCM542XX_TOP_1588_TS_INFO_6_REG_OFFSET (0xAFC) 1258 #define PHY_BCM542XX_TOP_1588_TS_INFO_SRC_PORT_CLK_ID_4 (0xffff) 1259 1260 /* 1261 * TOP_1588_TIMESTAMP_INFO_7 1262 */ 1263 #define PHY_BCM542XX_TOP_1588_TS_INFO_7_REG_OFFSET (0xAFD) 1264 #define PHY_BCM542XX_TOP_1588_TS_INFO_SRC_PORT_NUM (0xffff) 1265 1266 /* 1267 * TOP_1588_TIMESTAMP_INFO_8 1268 */ 1269 #define PHY_BCM542XX_TOP_1588_TS_INFO_8_REG_OFFSET (0xAFE) 1270 #define PHY_BCM542XX_TOP_1588_TS_INFO_VLAN_ID (0x0fff) 1271 1272 /* * 1273 * * S2S: Second Serdes Registers 1274 */ 1275 #define PHY_BCM542XX_2ND_SERDES_BASE_OFFSET (0xb00) 1276 1277 /* 1278 * Second SERDES MII CONTROL REGISTER 1279 */ 1280 #define PHY_BCM542XX_2ND_SERDES_MII_CTRL_REG_OFFSET \ 1281 (PHY_BCM542XX_2ND_SERDES_BASE_OFFSET + 0x00) 1282 #define PHY_BCM542XX_2ND_SERDES_MII_CTRL_INIT (0x1140) 1283 1284 /* 1285 * Second SERDES 100-FX CONTROL REGISTER 1286 */ 1287 #define PHY_BCM542XX_2ND_SERDES_MISC_1000x_REG_OFFSET \ 1288 (PHY_BCM542XX_2ND_SERDES_BASE_OFFSET + 0x17) 1289 #define PHY_BCM542XX_2ND_SERDES_MISC_1000x_INIT (0x0000) 1290 1291 /* 1292 * Second SERDES MISC 1000-X CONTROL 2 REGISTER 1293 */ 1294 #define PHY_BCM542XX_2ND_SERDES_MISC_1000x_CTL_2_REG_OFFSET \ 1295 (PHY_BCM542XX_2ND_SERDES_BASE_OFFSET + 0x16) 1296 #define PHY_BCM542XX_2ND_SERDES_MISC_1000x_CTL_2_2ND_SERDES_MSB BIT(0) 1297 1298 /* 1299 * Second SERDES AUXILIARY 1000-X CONTROL REGISTER 1300 */ 1301 #define PHY_BCM542XX_2ND_SERDES_AUX_1000x_CTL_REG_OFFSET \ 1302 (PHY_BCM542XX_2ND_SERDES_BASE_OFFSET + 0x1B) 1303 #define PHY_BCM542XX_2ND_SERDES_AUX_1000x_CTL_2ND_SERDES_LSB BIT(1) 1304 1305 /* 1306 * Second SERDES 1000-X ERROR COUNTER SETTING REGISTER 1307 */ 1308 #define PHY_BCM542XX_2ND_SERDES_1000x_ERR_CNT_SET_REG_OFFSET \ 1309 (PHY_BCM542XX_2ND_SERDES_BASE_OFFSET + 0x10) 1310 #define PHY_BCM542XX_2ND_SERDES_1000x_ERR_CNT_SET_EXT_PKT_LEN BIT(0) 1311 #endif /* _PHY542XX_REGDEFS_H */