phy542xx_int.h (87643B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 8 #ifndef _PHY542XX_INT_H 9 #define _PHY542XX_INT_H 10 11 /* Standard MII Registers */ 12 13 #define PHY_BCM542XX_MII_CTRL_REG 0x00 /* MII Control Register : r/w */ 14 #define PHY_BCM542XX_MII_STAT_REG 0x01 /* MII Status Register: ro */ 15 #define PHY_BCM542XX_MII_PHY_ID0_REG 0x02 /* MII PHY ID register: r/w */ 16 #define PHY_BCM542XX_MII_ANA_REG 0x04 /* MII Auto-Neg Advertisement: r/w */ 17 #define PHY_BCM542XX_MII_ANP_REG 0x05 /* MII Auto-Neg Link Partner: ro */ 18 #define PHY_BCM542XX_MII_AN_EXP_REG 0x06 /* MII Auti-Neg Expansion: ro */ 19 #define PHY_BCM542XX_MII_GB_CTRL_REG 0x09 /* MII 1000Base-T control register */ 20 #define PHY_BCM542XX_MII_GB_STAT_REG 0x0a /* MII 1000Base-T Status register */ 21 #define PHY_BCM542XX_MII_ESR_REG 0x0f /* MII Extended Status register */ 22 23 /* Non-standard MII Registers */ 24 25 #define PHY_BCM542XX_MII_ECR_REG 0x10 /* MII Extended Control Register */ 26 #define PHY_BCM542XX_MII_AUX_REG 0x18 /* MII Auxiliary Control/Status Reg */ 27 #define PHY_BCM542XX_MII_ASSR_REG 0x19 /* MII Auxiliary Status Summary Reg */ 28 #define PHY_BCM542XX_MII_GSR_REG 0x1c /* MII General status (BROADCOM) */ 29 30 /* MII Control Register: bit definitions */ 31 32 #define PHY_BCM542XX_MII_CTRL_UNIDIR_EN (BIT5) /* Force speed to 2500 Mbps */ 33 #define PHY_BCM542XX_MII_CTRL_SS_MSB (BIT6) /* Speed select, MSb */ 34 #define PHY_BCM542XX_MII_CTRL_FD (BIT8) /* Full Duplex */ 35 #define PHY_BCM542XX_MII_CTRL_RST_AN (BIT9) /* Restart Autonegotiation */ 36 #define PHY_BCM542XX_MII_CTRL_PWR_DOWN (BIT11) /* Power Down */ 37 #define PHY_BCM542XX_MII_CTRL_AN_EN (BIT12) /* Autonegotiation enable */ 38 #define PHY_BCM542XX_MII_CTRL_SS_LSB (BIT13) /* Speed select, LSb */ 39 #define PHY_BCM542XX_MII_CTRL_LPBK_EN (BIT14) /* Loopback enable */ 40 #define PHY_BCM542XX_MII_CTRL_RESET (BIT15) /* PHY reset */ 41 42 #define PHY_BCM542XX_MII_CTRL_SS(_x) ((_x) & \ 43 (PHY_BCM542XX_MII_CTRL_SS_LSB|PHY_BCM542XX_MII_CTRL_SS_MSB)) 44 #define PHY_BCM542XX_MII_CTRL_SS_10 0 45 #define PHY_BCM542XX_MII_CTRL_SS_100 (PHY_BCM542XX_MII_CTRL_SS_LSB) 46 #define PHY_BCM542XX_MII_CTRL_SS_1000 (PHY_BCM542XX_MII_CTRL_SS_MSB) 47 #define PHY_BCM542XX_MII_CTRL_SS_INVALID (PHY_BCM542XX_MII_CTRL_SS_LSB | \ 48 PHY_BCM542XX_MII_CTRL_SS_MSB) 49 #define PHY_BCM542XX_MII_CTRL_SS_MASK (PHY_BCM542XX_MII_CTRL_SS_LSB | \ 50 PHY_BCM542XX_MII_CTRL_SS_MSB) 51 /* 52 * MII Status Register: See 802.3, 1998 pg 544 53 */ 54 #define PHY_BCM542XX_MII_STAT_EXT (BIT0) /* Extended Registers */ 55 #define PHY_BCM542XX_MII_STAT_JBBR (BIT1) /* Jabber Detected */ 56 #define PHY_BCM542XX_MII_STAT_LA (BIT2) /* Link Active */ 57 #define PHY_BCM542XX_MII_STAT_AN_CAP (BIT3) /* Autoneg capable */ 58 #define PHY_BCM542XX_MII_STAT_RF (BIT4) /* Remote Fault */ 59 #define PHY_BCM542XX_MII_STAT_AN_DONE (BIT5) /* Autoneg complete */ 60 #define PHY_BCM542XX_MII_STAT_MF_PS (BIT6) /* Preamble suppression */ 61 #define PHY_BCM542XX_MII_STAT_ES (BIT8) /* Extended status (R15) */ 62 #define PHY_BCM542XX_MII_STAT_HD_100_T2 (BIT9) /* Half duplex 100Mb/s supported */ 63 #define PHY_BCM542XX_MII_STAT_FD_100_T2 (BIT10)/* Full duplex 100Mb/s supported */ 64 #define PHY_BCM542XX_MII_STAT_HD_10 (BIT11)/* Half duplex 100Mb/s supported */ 65 #define PHY_BCM542XX_MII_STAT_FD_10 (BIT12)/* Full duplex 100Mb/s supported */ 66 #define PHY_BCM542XX_MII_STAT_HD_100 (BIT13)/* Half duplex 100Mb/s supported */ 67 #define PHY_BCM542XX_MII_STAT_FD_100 (BIT14)/* Full duplex 100Mb/s supported */ 68 #define PHY_BCM542XX_MII_STAT_100_T4 (BIT15)/* Full duplex 100Mb/s supported */ 69 70 /* 71 * MII Link Advertisment 72 */ 73 #define PHY_BCM542XX_MII_ANA_ASF (BIT0) /* Advertise Selector Field */ 74 #define PHY_BCM542XX_MII_ANA_HD_10 (BIT5) /* Half duplex 10Mb/s supported */ 75 #define PHY_BCM542XX_MII_ANA_FD_10 (BIT6) /* Full duplex 10Mb/s supported */ 76 #define PHY_BCM542XX_MII_ANA_HD_100 (BIT7) /* Half duplex 100Mb/s supported */ 77 #define PHY_BCM542XX_MII_ANA_FD_100 (BIT8) /* Full duplex 100Mb/s supported */ 78 #define PHY_BCM542XX_MII_ANA_T4 (BIT9) /* T4 */ 79 #define PHY_BCM542XX_MII_ANA_PAUSE (BIT10) /* Pause supported */ 80 #define PHY_BCM542XX_MII_ANA_ASYM_PAUSE (BIT11) /* Asymmetric pause supported */ 81 #define PHY_BCM542XX_MII_ANA_RF (BIT13) /* Remote fault */ 82 #define PHY_BCM542XX_MII_ANA_NP (BIT15) /* Next Page */ 83 84 #define PHY_BCM542XX_MII_ANA_ASF_802_3 (1) /* 802.3 PHY */ 85 86 /* 87 * 1000X MII Link Advertisment 88 */ 89 #define PHY_BCM542XX_1000X_MII_ANA_FD (BIT5) /* Full duplex supported */ 90 #define PHY_BCM542XX_1000X_MII_ANA_HD (BIT6) /* Half duplex supported */ 91 #define PHY_BCM542XX_1000X_MII_ANA_PAUSE (BIT7) /* Symmetric Pause supported */ 92 #define PHY_BCM542XX_1000X_MII_ANA_ASYM_PAUSE (BIT8) /* Asymmetric pause supported */ 93 #define PHY_BCM542XX_1000X_MII_ANA_NP (BIT15)/* Next Page */ 94 /* 95 * MII Link Advertisment (Clause 37) 96 */ 97 #define PHY_BCM542XX_MII_ANA_C37_NP (1 << 15) /* Next Page */ 98 #define PHY_BCM542XX_MII_ANA_C37_RF_OK (0 << 12) /* No error, link OK */ 99 #define PHY_BCM542XX_MII_ANA_C37_RF_LINK_FAIL (1 << 12) /* Offline */ 100 #define PHY_BCM542XX_MII_ANA_C37_RF_OFFLINE (2 << 12) /* Link failure */ 101 #define PHY_BCM542XX_MII_ANA_C37_RF_AN_ERR (3 << 12) /* Auto-Negotiation Error */ 102 #define PHY_BCM542XX_MII_ANA_C37_PAUSE (1 << 7) /* Symmetric Pause */ 103 #define PHY_BCM542XX_MII_ANA_C37_ASYM_PAUSE (1 << 8) /* Asymmetric Pause */ 104 #define PHY_BCM542XX_MII_ANA_C37_HD (1 << 6) /* Half duplex */ 105 #define PHY_BCM542XX_MII_ANA_C37_FD (1 << 5) /* Full duplex */ 106 107 /* 108 * MII Link Partner Ability (Clause 37) 109 */ 110 #define PHY_BCM542XX_MII_ANP_C37_NP (1 << 15) /* Next Page */ 111 #define PHY_BCM542XX_MII_ANP_C37_ACK (1 << 14) /* Acknowledge */ 112 #define PHY_BCM542XX_MII_ANP_C37_RF_OK (0 << 12) /* No error, link OK */ 113 #define PHY_BCM542XX_MII_ANP_C37_RF_LINK_FAIL (1 << 12) /* Offline */ 114 #define PHY_BCM542XX_MII_ANP_C37_RF_OFFLINE (2 << 12) /* Link failure */ 115 #define PHY_BCM542XX_MII_ANP_C37_RF_AN_ERR (3 << 12) /* Auto-Negotiation Error */ 116 #define PHY_BCM542XX_MII_ANP_C37_PAUSE (1 << 7) /* Symmetric Pause */ 117 #define PHY_BCM542XX_MII_ANP_C37_ASYM_PAUSE (1 << 8) /* Asymmetric Pause */ 118 #define PHY_BCM542XX_MII_ANP_C37_HD (1 << 6) /* Half duplex */ 119 #define PHY_BCM542XX_MII_ANP_C37_FD (1 << 5) /* Full duplex */ 120 121 /* 122 * MII Link Partner Ability (SGMII) 123 */ 124 #define PHY_BCM542XX_MII_ANP_SGMII_MODE (1 << 0) /* Link parneter in SGMII mode */ 125 #define PHY_BCM542XX_MII_ANP_SGMII_FD (1 << 12) /* SGMII duplex */ 126 #define PHY_BCM542XX_MII_ANP_SGMII_SS_10 (0 << 10) /* 10Mbps SGMII */ 127 #define PHY_BCM542XX_MII_ANP_SGMII_SS_100 (1 << 10) /* 100Mbps SGMII */ 128 #define PHY_BCM542XX_MII_ANP_SGMII_SS_1000 (2 << 10) /* 1000Mbps SGMII */ 129 #define PHY_BCM542XX_MII_ANP_SGMII_SS_MASK (3 << 10) /* SGMII speed mask */ 130 #define PHY_BCM542XX_MII_ANP_SGMII_ACK (1 << 14) /* SGMII Ackonwledge */ 131 #define PHY_BCM542XX_MII_ANP_SGMII_LINK (1 << 15) /* SGMII Link */ 132 133 /* 134 * 1000Base-T Control Register 135 */ 136 #define PHY_BCM542XX_MII_GB_CTRL_MS_MAN (BIT12) /* Manual Master/Slave mode */ 137 #define PHY_BCM542XX_MII_GB_CTRL_MS (BIT11) /* Master/Slave negotiation mode */ 138 #define PHY_BCM542XX_MII_GB_CTRL_PT (BIT10) /* Port type */ 139 #define PHY_BCM542XX_MII_GB_CTRL_ADV_1000FD (BIT9) /* Advertise 1000Base-T FD */ 140 #define PHY_BCM542XX_MII_GB_CTRL_ADV_1000HD (BIT8) /* Advertise 1000Base-T HD */ 141 142 /* 143 * 1000Base-T Status Register 144 */ 145 #define PHY_BCM542XX_MII_GB_STAT_MS_FAULT (BIT15) /* Master/Slave Fault */ 146 #define PHY_BCM542XX_MII_GB_STAT_MS (BIT14) /* Master/Slave, 1 == Master */ 147 #define PHY_BCM542XX_MII_GB_STAT_LRS (BIT13) /* Local receiver status */ 148 #define PHY_BCM542XX_MII_GB_STAT_RRS (BIT12) /* Remote receiver status */ 149 #define PHY_BCM542XX_MII_GB_STAT_LP_1000FD (BIT11) /* Link partner 1000FD capable */ 150 #define PHY_BCM542XX_MII_GB_STAT_LP_1000HD (BIT10) /* Link partner 1000HD capable */ 151 #define PHY_BCM542XX_MII_GB_STAT_IDE (0xff << 0) /* Idle error count */ 152 153 /* 154 * IEEE Extended Status Register 155 */ 156 #define PHY_BCM542XX_MII_ESR_1000_X_FD (BIT15) /* 1000Base-T FD capable */ 157 #define PHY_BCM542XX_MII_ESR_1000_X_HD (BIT14) /* 1000Base-T HD capable */ 158 #define PHY_BCM542XX_MII_ESR_1000_T_FD (BIT13) /* 1000Base-T FD capable */ 159 #define PHY_BCM542XX_MII_ESR_1000_T_HD (BIT12) /* 1000Base-T FD capable */ 160 161 /* 162 * MII Extended Control Register (BROADCOM) 163 */ 164 #define PHY_BCM542XX_MII_ECR_FIFO_ELAST_0 (BIT0) /* FIFO Elasticity[0], MSB 165 at exp reg 46[14]*/ 166 #define PHY_BCM542XX_MII_ECR_LED_OFF_F (BIT3) /* Force LED off */ 167 #define PHY_BCM542XX_MII_ECR_LED_ON_F (BIT4) /* Force LED on */ 168 #define PHY_BCM542XX_MII_ECR_EN_LEDT (BIT5) /* Enable LED traffic */ 169 #define PHY_BCM542XX_MII_ECR_RST_SCR (BIT6) /* Reset Scrambler */ 170 #define PHY_BCM542XX_MII_ECR_BYPASS_ALGN (BIT7) /* Bypass Receive Sym. align */ 171 #define PHY_BCM542XX_MII_ECR_BPASS_MLT3 (BIT8) /* Bypass MLT3 Encoder/Decoder */ 172 #define PHY_BCM542XX_MII_ECR_BPASS_SCR (BIT9) /* Bypass Scramble/Descramble */ 173 #define PHY_BCM542XX_MII_ECR_BPASS_ENC (BIT10) /* Bypass 4B/5B Encode/Decode */ 174 #define PHY_BCM542XX_MII_ECR_FORCE_INT (BIT11) /* Force Interrupt */ 175 #define PHY_BCM542XX_MII_ECR_INT_DIS (BIT12) /* Interrupt Disable */ 176 #define PHY_BCM542XX_MII_ECR_TX_DIS (BIT13) /* XMIT Disable */ 177 #define PHY_BCM542XX_MII_ECR_DAMC (BIT14) /* Disable Auto-MDI Crossover */ 178 179 /* 180 * Auxiliary Status Summary Register (ASSR - Broadcom BCM542xx) 181 */ 182 #define PHY_BCM542XX_MII_ASSR_PRTD (1 << 0) /* Pause resolution/XMIT direction */ 183 #define PHY_BCM542XX_MII_ASSR_PRRD (1 << 1) /* Pause resolution/RCV direction */ 184 #define PHY_BCM542XX_MII_ASSR_LS (1 << 2) /* Link Status (1 == link up) */ 185 #define PHY_BCM542XX_MII_ASSR_LPNPA (1 << 3) /* Link partner next page cap */ 186 #define PHY_BCM542XX_MII_ASSR_LPANA (1 << 4) /* Link Partner AN capable */ 187 #define PHY_BCM542XX_MII_ASSR_ANPR (1 << 5) /* Autoneg page received */ 188 #define PHY_BCM542XX_MII_ASSR_RF (1 << 6) /* Remote Fault */ 189 #define PHY_BCM542XX_MII_ASSR_PDF (1 << 7) /* Parallel detection fault */ 190 #define PHY_BCM542XX_MII_ASSR_HCD (7 << 8) /* Current operating speed */ 191 #define PHY_BCM542XX_MII_ASSR_ANNPW (1 << 11) /* Auto-neg next page wait */ 192 #define PHY_BCM542XX_MII_ASSR_ANABD (1 << 12) /* Auto-neg Ability detected */ 193 #define PHY_BCM542XX_MII_ASSR_ANAD (1 << 13) /* Auto-neg ACK detect */ 194 #define PHY_BCM542XX_MII_ASSR_ANCA (1 << 14) /* Auto-neg complete ACK */ 195 #define PHY_BCM542XX_MII_ASSR_ANC (1 << 15) /* AUto-neg complete */ 196 #define PHY_BCM542XX_MII_ASSR_HCD_FD_1000 (7 << 8) 197 #define PHY_BCM542XX_MII_ASSR_HCD_HD_1000 (6 << 8) 198 #define PHY_BCM542XX_MII_ASSR_HCD_FD_100 (5 << 8) 199 #define PHY_BCM542XX_MII_ASSR_HCD_T4_100 (4 << 8) 200 #define PHY_BCM542XX_MII_ASSR_HCD_HD_100 (3 << 8) 201 #define PHY_BCM542XX_MII_ASSR_HCD_FD_10 (2 << 8) 202 #define PHY_BCM542XX_MII_ASSR_HCD_HD_10 (1 << 8) 203 #define PHY_BCM542XX_MII_ASSR_HCD_NC (0 << 8) /* Not complete */ 204 #define PHY_BCM542XX_MII_ASSR_AUTONEG_HCD_MASK (0x0700) 205 206 /* 207 * Auto Detect Medium Register 208 */ 209 #define PHY_BCM542XX_MII_AUTO_DET_MED_2ND_SERDES (BIT9) 210 #define PHY_BCM542XX_MII_INV_FIBER_SD (BIT8) 211 #define PHY_BCM542XX_MII_FIBER_IN_USE_LED (BIT7) 212 #define PHY_BCM542XX_MII_FIBER_LED (BIT6) 213 #define PHY_BCM542XX_MII_FIBER_SD_SYNC (BIT5) 214 #define PHY_BCM542XX_MII_FIBER_AUTO_PWRDN (BIT4) 215 #define PHY_BCM542XX_MII_SD_en_ov (BIT3) 216 #define PHY_BCM542XX_MII_AUTO_DET_MED_DEFAULT (BIT2) 217 #define PHY_BCM542XX_MII_AUTO_DET_MED_PRI (BIT1) 218 #define PHY_BCM542XX_MII_AUTO_DET_MED_EN (BIT0) 219 #define PHY_BCM542XX_MII_AUTO_DET_MASK (0x033F) 220 221 /* 222 * Mode Control Register 223 */ 224 #define PHY_BCM542XX_MODE_CNTL_CU_LINK (BIT7) /* Copper link */ 225 #define PHY_BCM542XX_MODE_CNTL_SERDES_LINK (BIT6) /* Fiber, SGMII link */ 226 #define PHY_BCM542XX_MODE_CNTL_CU_ENG_DET (BIT5) /* Copper energy detected */ 227 #define PHY_BCM542XX_MODE_CNTL_FBER_SIG_DET (BIT4) /* Fiber signal detected */ 228 #define PHY_BCM542XX_MODE_CNTL_SERDES_CAPABLE (BIT3) /* SerDes capable device */ 229 #define PHY_BCM542XX_MODE_CNTL_MODE_SEL_2 (BIT2) /* Mode select [2] */ 230 #define PHY_BCM542XX_MODE_CNTL_MODE_SEL_1 (BIT1) /* Mode select [1] */ 231 #define PHY_BCM542XX_MODE_CNTL_1000X_EN (BIT0) /* Select 1000-X (fiber) regs 232 vs. Copper regs */ 233 #define PHY_BCM542XX_MODE_CNTL_MODE_SEL_MASK (PHY_BCM542XX_MODE_CNTL_MODE_SEL_1 | \ 234 PHY_BCM542XX_MODE_CNTL_MODE_SEL_2) 235 236 #define PHY_BCM542XX_MODE_SEL_COPPER_2_SGMII (0x0) 237 #define PHY_BCM542XX_MODE_SEL_FIBER_2_SGMII (PHY_BCM542XX_MODE_CNTL_MODE_SEL_1) 238 #define PHY_BCM542XX_MODE_SEL_SGMII_2_COPPER (PHY_BCM542XX_MODE_CNTL_MODE_SEL_2) 239 #define PHY_BCM542XX_MODE_SEL_GBIC (PHY_BCM542XX_MODE_CNTL_MODE_SEL_1 | \ 240 PHY_BCM542XX_MODE_CNTL_MODE_SEL_2) 241 242 /* 1000 BASE X CONTROL REG */ 243 #define PHY_BCM542XX_1000BASE_X_CTRL_REG_LE (BIT14) 244 #define PHY_BCM542XX_1000BASE_X_CTRL_REG_AE (BIT12) 245 246 /* 1000 BASE X STATUS REG */ 247 #define PHY_BCM542XX_1000BASE_X_STAT_REG_LA (BIT2) 248 249 /* 250 * MII Broadcom MISC Control Register(PHY_BCM542XX_MII_MISC_CTRL_REG) 251 */ 252 #define PHY_BCM542XX_MII_FORCE_AUTO_MDIX_MODE (BIT9) 253 #define PHY_BCM542XX_MII_BP_WIRESPEED_TIMER (BIT10) 254 #define PHY_BCM542XX_MII_WIRESPEED_EN (BIT4) 255 #define PHY_BCM542XX_MII_MISC_CTRL_ALL (0x0FF8) 256 #define PHY_BCM542XX_MII_MISC_CTRL_CLEARALL (0x2007) 257 258 /* 259 * MII Broadcom Test Register(PHY_BCM542XX_MII_SHA_AUX_STAT2_REG) 260 */ /* Enable Shadow registers */ 261 #define PHY_BCM542XX_MII_SHA_AUX_STAT2_LEN (0x7 << 12) 262 263 /* Miscellaneous registers */ 264 #define PHY_BCM542XX_SPARE_CTRL_REG_LINK_LED (BIT0) 265 #define PHY_BCM542XX_SPARE_CTRL_REG_LINK_SPEED_LED (BIT2) 266 267 268 /* Flag indicating that its a SerDes register */ 269 270 #define PHY_BCM542XX_REG_1000X (BIT0) 271 #define PHY_BCM542XX_REG_PRI_SERDES (BIT1) 272 #define PHY_BCM542XX_REG_QSGMII (BIT4) 273 #define PHY_BCM542XX_REG_FIBER (PHY_BCM542XX_REG_1000X | \ 274 PHY_BCM542XX_REG_PRI_SERDES) 275 276 277 /*********************************************** 278 * 279 * Generic register accessing macros/functions 280 */ 281 282 int phy_bcm542xx_reg_read(int unit, phy_ctrl_t *pc, uint32 flags, 283 uint16 reg_bank, uint8 reg_addr, uint16 *data); 284 int phy_bcm542xx_reg_write(int unit, phy_ctrl_t *pc, uint32 flags, uint16 reg_bank, 285 uint8 reg_addr, uint16 data); 286 int phy_bcm542xx_reg_modify(int unit, phy_ctrl_t *pc, uint32 flags, uint16 reg_bank, 287 uint8 reg_addr, uint16 data, uint16 mask); 288 int phy_bcm542xx_reg_read_modify_write(int unit, phy_ctrl_t *pc, uint32 reg_addr, 289 uint16 reg_data, uint16 reg_mask); 290 291 int phy_bcm542xx_qsgmii_reg_read(int unit, phy_ctrl_t *pc, int dev_port, 292 uint16 block, uint8 reg, uint16 *data); 293 int phy_bcm542xx_qsgmii_reg_write(int unit, phy_ctrl_t *pc, int dev_port, 294 uint16 block, uint8 reg, uint16 data); 295 int phy_bcm542xx_qsgmii_reg_modify(int unit, phy_ctrl_t *pc, int dev_port, 296 uint16 block, uint8 reg_addr, uint16 reg_data, uint16 reg_mask); 297 298 int phy_bcm542xx_cl45_reg_read(int unit, phy_ctrl_t *pc, uint8 dev_addr, 299 uint16 reg_addr, uint16 *val); 300 int phy_bcm542xx_cl45_reg_write(int unit, phy_ctrl_t *pc, uint8 dev_addr, 301 uint16 reg_addr, uint16 val); 302 int phy_bcm542xx_cl45_reg_modify(int unit, phy_ctrl_t *pc, uint8 dev_addr, 303 uint16 reg_addr, uint16 val, uint16 mask); 304 305 /* PHY register access */ 306 #define PHY_BCM542XX_READ_PHY_REG(_unit, _phy_ctrl, _reg_addr, _val) \ 307 READ_PHY_REG((_unit), (_phy_ctrl), (_reg_addr), (_val)) 308 #define PHY_BCM542XX_WRITE_PHY_REG(_unit, _phy_ctrl, _reg_addr, _val) \ 309 WRITE_PHY_REG((_unit), (_phy_ctrl), (_reg_addr), (_val)) 310 #define PHY_BCM542XX_MODIFY_PHY_REG(_unit, _phy_ctrl, _reg_addr, _val, _mask) \ 311 MODIFY_PHY_REG((_unit), (_phy_ctrl), (_reg_addr), (_val), (_mask)) 312 313 /* General - PHY register access */ 314 #define PHY_BCM542XX_REG_RD(_unit, _pc, _flags, _reg_bank, _reg_addr, _val) \ 315 phy_bcm542xx_reg_read((_unit), (_pc), (_flags), (_reg_bank), \ 316 (_reg_addr), (_val)) 317 #define PHY_BCM542XX_REG_WR(_unit, _pc, _flags, _reg_bank, _reg_addr, _val) \ 318 phy_bcm542xx_reg_write((_unit), (_pc), (_flags), (_reg_bank), \ 319 (_reg_addr), (_val)) 320 #define PHY_BCM542XX_REG_MOD(_unit, _pc, _flags, _reg_bank, _reg_addr, _val, _mask) \ 321 phy_bcm542xx_reg_modify((_unit), (_pc), (_flags), (_reg_bank), \ 322 (_reg_addr), (_val), (_mask)) 323 324 /* Clause 45 Registers access using Clause 22 register access */ 325 #define PHY_BCM542XX_CL45_REG_READ(_unit, _pc, _dev_addr, _reg_addr, _val) \ 326 phy_bcm542xx_cl45_reg_read((_unit), (_pc), (_dev_addr), \ 327 (_reg_addr), (_val)) 328 #define PHY_BCM542XX_CL45_REG_WRITE(_unit, _pc, _dev_addr, _reg_addr, _val) \ 329 phy_bcm542xx_cl45_reg_write((_unit), (_pc), (_dev_addr), \ 330 (_reg_addr), (_val)) 331 #define PHY_BCM542XX_CL45_REG_MODIFY(_unit, _pc, _dev_addr, _reg_addr, _val, _mask) \ 332 phy_bcm542xx_cl45_reg_modify((_unit), (_pc), (_dev_addr), \ 333 (_reg_addr), (_val), (_mask)) 334 335 /************************************************** 336 * 337 * RDB/Legacy register accessing macros/functions 338 */ 339 #undef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* default to RDB mode */ 340 341 /* Registers used to Rd/Wr using RDB mode */ 342 #define PHY_BCM542XX_RDB_ADDR_REG_OFFSET (0x1E) 343 #define PHY_BCM542XX_RDB_ADDR_REG_ADDR (0xffff) 344 #define PHY_BCM542XX_RDB_DATA_REG_OFFSET (0x1F) 345 #define PHY_BCM542XX_RDB_DATA_REG_DATA (0xffff) 346 /* Registers used to enable RDB register access mode */ 347 #define PHY_BCM542XX_REG_17_OFFSET (0x17) 348 #define PHY_BCM542XX_REG_17_SELECT_EXP_7E (0x0F7E) 349 #define PHY_BCM542XX_REG_15_OFFSET (0x15) 350 #define PHY_BCM542XX_REG_15_RDB_EN (0x0000) 351 #define PHY_BCM542XX_REG_15_RDB_DIS (0x8000) 352 #define PHY_BCM542XX_REG_1E_SELECT_RDB (0x0087) 353 354 /* 355 * Macro for activating the RDB Register Addressing mode * 356 * Enable direct RDB addressing mode, write to Expansion register 0x7E = 0x0000 357 * - MDIO write to reg 0x17 = 0x0F7E 358 * - MDIO write to reg 0x15 = 0x0000 359 */ 360 #define PHY_BCM542XX_RDB_ACCESS_MODE(_u, _pc) do { \ 361 SOC_IF_ERROR_RETURN( \ 362 PHY_BCM542XX_WRITE_PHY_REG((_u), (_pc), PHY_BCM542XX_REG_17_OFFSET, \ 363 PHY_BCM542XX_REG_17_SELECT_EXP_7E) ); \ 364 SOC_IF_ERROR_RETURN( \ 365 PHY_BCM542XX_WRITE_PHY_REG((_u), (_pc), PHY_BCM542XX_REG_15_OFFSET, \ 366 PHY_BCM542XX_REG_15_RDB_EN) ); \ 367 } while ( 0 ) 368 369 /* 370 * Macro for activating the Legacy Register Addressing mode * 371 * Disable direct RDB addressing mode, write to RDB register 0x87 = 0x8000 372 * - MDIO write to reg 0x1E = 0x0087 373 * - MDIO write to reg 0x1F = 0x8000 374 */ 375 #define PHY_BCM542XX_LEGACY_ACCESS_MODE(_u, _pc) do { \ 376 SOC_IF_ERROR_RETURN( \ 377 PHY_BCM542XX_WRITE_PHY_REG((_u), (_pc), PHY_BCM542XX_RDB_ADDR_REG_OFFSET, \ 378 PHY_BCM542XX_REG_1E_SELECT_RDB) );\ 379 SOC_IF_ERROR_RETURN( \ 380 PHY_BCM542XX_WRITE_PHY_REG((_u), (_pc), PHY_BCM542XX_RDB_DATA_REG_OFFSET, \ 381 PHY_BCM542XX_REG_15_RDB_DIS) ); \ 382 } while ( 0 ) 383 384 385 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING 386 387 /* RDB register accessing funtions from Legacy mode */ 388 int phy_bcm542xx_direct_reg_read( int unit, phy_ctrl_t *pc, uint16 reg_addr, 389 uint16 *data); 390 int phy_bcm542xx_direct_reg_write( int unit, phy_ctrl_t *pc, uint16 reg_addr, 391 uint16 data); 392 int phy_bcm542xx_direct_reg_modify(int unit, phy_ctrl_t *pc, uint16 reg_addr, 393 uint16 data, uint16 mask); 394 #define PHY_BCM542XX_DEFAULT_REG_ACCESS_MODE PHY_BCM542XX_LEGACY_ACCESS_MODE 395 396 #else /* default to RDB register addressing mode */ 397 398 #define PHY_BCM542XX_DEFAULT_REG_ACCESS_MODE PHY_BCM542XX_RDB_ACCESS_MODE 399 400 /* RDB register accessing funtions */ 401 int phy_bcm542xx_rdb_reg_read( int unit, phy_ctrl_t *pc, uint16 reg_addr, 402 uint16 *data); 403 int phy_bcm542xx_rdb_reg_write( int unit, phy_ctrl_t *pc, uint16 reg_addr, 404 uint16 data); 405 int phy_bcm542xx_rdb_reg_modify(int unit, phy_ctrl_t *pc, uint16 reg_addr, 406 uint16 data, uint16 mask); 407 #define phy_bcm542xx_direct_reg_read phy_bcm542xx_rdb_reg_read 408 #define phy_bcm542xx_direct_reg_write phy_bcm542xx_rdb_reg_write 409 #define phy_bcm542xx_direct_reg_modify phy_bcm542xx_rdb_reg_modify 410 411 #endif /* PHY_BCM542XX_DEFAULT_TO_LEGACY_ACCESS */ 412 413 #define PHY_BCM542XX_RDB_RD phy_bcm542xx_direct_reg_read 414 #define PHY_BCM542XX_RDB_WR phy_bcm542xx_direct_reg_write 415 #define PHY_BCM542XX_RDB_MO phy_bcm542xx_direct_reg_modify 416 417 418 /*********************************************** 419 * 420 * Specific register accessing macros 421 */ 422 423 /* 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 424 #define PHY_READ_BCM542XX_MII_CTRLr(_unit, _pc, _val) \ 425 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, \ 426 PHY_BCM542XX_MII_CTRL_REG, (_val)) 427 #define PHY_WRITE_BCM542XX_MII_CTRLr(_unit, _pc, _val) \ 428 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, \ 429 PHY_BCM542XX_MII_CTRL_REG, (_val)) 430 #define PHY_MODIFY_BCM542XX_MII_CTRLr(_unit, _pc, _val, _mask) \ 431 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, \ 432 PHY_BCM542XX_MII_CTRL_REG, (_val), (_mask)) 433 434 /* 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 435 #define PHY_READ_BCM542XX_MII_STATr(_unit, _pc, _val) \ 436 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x01, (_val)) 437 #define PHY_WRITE_BCM542XX_MII_STATr(_unit, _pc, _val) \ 438 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x01, (_val)) 439 #define PHY_MODIFY_BCM542XX_MII_STATr(_unit, _pc, _val, _mask) \ 440 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x01, \ 441 (_val), (_mask)) 442 443 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 444 #define PHY_READ_BCM542XX_MII_PHY_ID0r(_unit, _pc, _val) \ 445 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x02, (_val)) 446 #define PHY_WRITE_BCM542XX_MII_PHY_ID0r(_unit, _pc, _val) \ 447 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x02, (_val)) 448 #define PHY_MODIFY_BCM542XX_MII_PHY_ID0r(_unit, _pc, _val, _mask) \ 449 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x02, \ 450 (_val), (_mask)) 451 452 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 453 #define PHY_READ_BCM542XX_MII_PHY_ID1r(_unit, _pc, _val) \ 454 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x03, (_val)) 455 #define PHY_WRITE_BCM542XX_MII_PHY_ID1r(_unit, _pc, _val) \ 456 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x03, (_val)) 457 #define PHY_MODIFY_BCM542XX_MII_PHY_ID1r(_unit, _pc, _val, _mask) \ 458 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x03, \ 459 (_val), (_mask)) 460 461 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 462 #define PHY_READ_BCM542XX_MII_ANAr(_unit, _pc, _val) \ 463 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x04, (_val)) 464 #define PHY_WRITE_BCM542XX_MII_ANAr(_unit, _pc, _val) \ 465 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x04, (_val)) 466 #define PHY_MODIFY_BCM542XX_MII_ANAr(_unit, _pc, _val, _mask) \ 467 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x04, \ 468 (_val), (_mask)) 469 470 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 471 #define PHY_READ_BCM542XX_MII_ANPr(_unit, _pc, _val) \ 472 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x05, (_val)) 473 #define PHY_WRITE_BCM542XX_MII_ANPr(_unit, _pc, _val) \ 474 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x05, (_val)) 475 #define PHY_MODIFY_BCM542XX_MII_ANPr(_unit, _pc, _val, _mask) \ 476 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x05, \ 477 (_val), (_mask)) 478 479 /* 1000BASE-T/100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 480 #define PHY_READ_BCM542XX_MII_AN_EXPr(_unit, _pc, _val) \ 481 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x06, (_val)) 482 #define PHY_WRITE_BCM542XX_MII_AN_EXPr(_unit, _pc, _val) \ 483 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x06, (_val)) 484 #define PHY_MODIFY_BCM542XX_MII_AN_EXPr(_unit, _pc, _val, _mask) \ 485 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x06, \ 486 (_val), (_mask)) 487 488 /* 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 489 /* 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 490 491 /* 1000BASE-T Control Register (ADDR 09h) */ 492 #define PHY_READ_BCM542XX_MII_GB_CTRLr(_unit, _pc, _val) \ 493 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x09, (_val)) 494 #define PHY_WRITE_BCM542XX_MII_GB_CTRLr(_unit, _pc, _val) \ 495 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x09, (_val)) 496 #define PHY_MODIFY_BCM542XX_MII_GB_CTRLr(_unit, _pc, _val, _mask) \ 497 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x09, \ 498 (_val), (_mask)) 499 500 /* 1000BASE-T Status Register (ADDR 0ah) */ 501 #define PHY_READ_BCM542XX_MII_GB_STATr(_unit, _pc, _val) \ 502 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x0a, (_val)) 503 #define PHY_WRITE_BCM542XX_MII_GB_STATr(_unit, _pc, _val) \ 504 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x0a, (_val)) 505 #define PHY_MODIFY_BCM542XX_MII_GB_STATr(_unit, _pc, _val, _mask) \ 506 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x0a, \ 507 (_val), (_mask)) 508 509 /* 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (ADDR 0fh) */ 510 #define PHY_READ_BCM542XX_MII_ESRr(_unit, _pc, _val) \ 511 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x0f, (_val)) 512 #define PHY_WRITE_BCM542XX_MII_ESRr(_unit, _pc, _val) \ 513 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x0f, (_val)) 514 #define PHY_MODIFY_BCM542XX_MII_ESRr(_unit, _pc, _val, _mask) \ 515 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x0f, \ 516 (_val), (_mask)) 517 518 /*****************************************************************************/ 519 520 /* 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register */ 521 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 10h */ 522 #define PHY_READ_BCM542XX_MII_ECRr(_unit, _pc, _val) \ 523 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, \ 524 PHY_BCM542XX_MII_ECR_REG, (_val)) 525 #define PHY_WRITE_BCM542XX_MII_ECRr(_unit, _pc, _val) \ 526 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, \ 527 PHY_BCM542XX_MII_ECR_REG, (_val)) 528 #define PHY_MODIFY_BCM542XX_MII_ECRr(_unit, _pc, _val, _mask) \ 529 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, \ 530 PHY_BCM542XX_MII_ECR_REG, (_val), (_mask)) 531 #else /* RDB_Reg. 0x000 */ 532 #define PHY_READ_BCM542XX_MII_ECRr(_unit, _pc, _val) \ 533 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x000, _val) 534 #define PHY_WRITE_BCM542XX_MII_ECRr(_unit, _pc, _val) \ 535 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x000, _val) 536 #define PHY_MODIFY_BCM542XX_MII_ECRr(_unit, _pc, _val, _mask) \ 537 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x000, _val, _mask) 538 #endif 539 540 /* 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (ADDR 12h) */ 541 /* 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter (ADDR 13h) */ 542 /* 1000BASE-T/100BASE-TX/10BASE-T Receive NOT_OK Counter Register (ADDR 14h) */ 543 544 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Register */ 545 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 18h Shadow 000) */ 546 #define PHY_READ_BCM542XX_MII_AUX_CTRLr(_unit, _pc, _val) \ 547 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x18, (_val)) 548 #define PHY_WRITE_BCM542XX_MII_AUX_CTRLr(_unit, _pc, _val) \ 549 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x18, (_val)) 550 #define PHY_MODIFY_BCM542XX_MII_AUX_CTRLr(_unit, _pc, _val, _mask) \ 551 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x18, \ 552 (_val), (_mask)) 553 #else /* RDB_Reg. 0x028 */ 554 #define PHY_READ_BCM542XX_MII_AUX_CTRLr(_unit, _pc, _val) \ 555 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x028, _val) 556 #define PHY_WRITE_BCM542XX_MII_AUX_CTRLr(_unit, _pc, _val) \ 557 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x028, _val) 558 #define PHY_MODIFY_BCM542XX_MII_AUX_CTRLr(_unit, _pc, _val, _mask) \ 559 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x028, _val, _mask) 560 #endif 561 562 #define PHY_BCM542XX_MII_AUX_CTRL_REG_EXT_PKT_LEN BIT(14) 563 #define PHY_BCM542XX_MII_AUX_CTRL_REG_EN_DSP_CLK BIT(11) 564 /* 10BASE-T Register */ 565 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 18h Shadow 001) */ 566 #define PHY_READ_BCM542XX_MII_10BASE_Tr(_unit, _pc, _val) \ 567 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0001, 0x18, (_val)) 568 #define PHY_WRITE_BCM542XX_MII_10BASE_Tr(_unit, _pc, _val) \ 569 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0001, 0x18, (_val)) 570 #define PHY_MODIFY_BCM542XX_MII_10BASE_Tr(_unit, _pc, _val, _mask) \ 571 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0001, 0x18, \ 572 (_val), (_mask)) 573 #else /* RDB_Reg. 0x029 */ 574 #define PHY_READ_BCM542XX_MII_10BASE_Tr(_unit, _pc, _val) \ 575 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x029, _val) 576 #define PHY_WRITE_BCM542XX_MII_10BASE_Tr(_unit, _pc, _val) \ 577 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x029, _val) 578 #define PHY_MODIFY_BCM542XX_MII_10BASE_Tr(_unit, _pc, _val, _mask) \ 579 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x029, _val, _mask) 580 #endif 581 582 /* 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Reg */ 583 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 18h Shadow 010) */ 584 #define PHY_READ_BCM542XX_MII_POWER_CTRLr(_unit, _pc, _val) \ 585 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0002, 0x18, (_val)) 586 #define PHY_WRITE_BCM542XX_MII_POWER_CTRLr(_unit, _pc, _val) \ 587 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0002, 0x18, (_val)) 588 #define PHY_MODIFY_BCM542XX_MII_POWER_CTRLr(_unit, _pc, _val, _mask) \ 589 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0002, 0x18, \ 590 (_val), (_mask)) 591 #else /* RDB_Reg. 0x02A */ 592 #define PHY_READ_BCM542XX_MII_POWER_CTRLr(_unit, _pc, _val) \ 593 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x02a, _val) 594 #define PHY_WRITE_BCM542XX_MII_POWER_CTRLr(_unit, _pc, _val) \ 595 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x02a, _val) 596 #define PHY_MODIFY_BCM542XX_MII_POWER_CTRLr(_unit, _pc, _val, _mask) \ 597 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x02a, _val, _mask) 598 #endif 599 600 #define PHY_BCM542XX_MII_MISC_TEST_RMT_LB BIT(15) /* Remote Loopback */ 601 602 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Test Register */ 603 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 18h Shadow 100) */ 604 #define PHY_READ_BCM542XX_MII_MISC_TESTr(_unit, _pc, _val) \ 605 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0004, 0x18, (_val)) 606 #define PHY_WRITE_BCM542XX_MII_MISC_TESTr(_unit, _pc, _val) \ 607 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0004, 0x18, (_val)) 608 #define PHY_MODIFY_BCM542XX_MII_MISC_TESTr(_unit, _pc, _val, _mask) \ 609 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0004, 0x18, \ 610 (_val), (_mask)) 611 #else /* RDB_Reg. 0x02C */ 612 #define PHY_READ_BCM542XX_MII_MISC_TESTr(_unit, _pc, _val) \ 613 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x02c, _val) 614 #define PHY_WRITE_BCM542XX_MII_MISC_TESTr(_unit, _pc, _val) \ 615 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x02c, _val) 616 #define PHY_MODIFY_BCM542XX_MII_MISC_TESTr(_unit, _pc, _val, _mask) \ 617 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x02c, _val, _mask) 618 #endif 619 620 /* 1000BASE-T/100BASE-TX/10BASE-T Misc Control Register */ 621 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 18h Shadow 111) */ 622 #define PHY_READ_BCM542XX_MII_MISC_CTRLr(_unit, _pc, _val) \ 623 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0007, 0x18, (_val)) 624 #define PHY_WRITE_BCM542XX_MII_MISC_CTRLr(_unit, _pc, _val) \ 625 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0007, 0x18, (_val)) 626 #define PHY_MODIFY_BCM542XX_MII_MISC_CTRLr(_unit, _pc, _val, _mask) \ 627 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0007, 0x18, \ 628 (_val), (_mask)) 629 #else /* RDB_Reg. 0x02F */ 630 #define PHY_READ_BCM542XX_MII_MISC_CTRLr(_unit, _pc, _val) \ 631 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x02f, _val) 632 #define PHY_WRITE_BCM542XX_MII_MISC_CTRLr(_unit, _pc, _val) \ 633 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x02f, _val) 634 #define PHY_MODIFY_BCM542XX_MII_MISC_CTRLr(_unit, _pc, _val, _mask) \ 635 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x02f, _val, _mask) 636 #endif 637 638 /* 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Register (ADDR 19h) */ 639 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 19h */ 640 #define PHY_READ_BCM542XX_MII_AUX_STATUSr(_unit, _pc, _val) \ 641 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x19, (_val)) 642 #define PHY_WRITE_BCM542XX_MII_AUX_STATUSr(_unit, _pc, _val) \ 643 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x19, (_val)) 644 #define PHY_MODIFY_BCM542XX_MII_AUX_STATUSr(_unit, _pc, _val, _mask) \ 645 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x19, \ 646 (_val), (_mask)) 647 #else /* RDB_Reg. 0x009 */ 648 #define PHY_READ_BCM542XX_MII_AUX_STATUSr(_unit, _pc, _val) \ 649 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x009, _val) 650 #define PHY_WRITE_BCM542XX_MII_AUX_STATUSr(_unit, _pc, _val) \ 651 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x009, _val) 652 #define PHY_MODIFY_BCM542XX_MII_AUX_STATUSr(_unit, _pc, _val, _mask) \ 653 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x009, _val, _mask) 654 #endif 655 656 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (ADDR 1ah) */ 657 /* 1000BASE-T/100BASE-TX/10BASE-T Interrupt Control Register (ADDR 1bh) */ 658 659 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl Reg (ADDR 1ch shadow 00010) */ 660 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 02h) */ 661 #define PHY_READ_BCM542XX_SPARE_CTRLr(_unit, _pc, _val) \ 662 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0002, 0x1c, (_val)) 663 #define PHY_WRITE_BCM542XX_SPARE_CTRLr(_unit, _pc, _val) \ 664 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0002, 0x1c, (_val)) 665 #define PHY_MODIFY_BCM542XX_SPARE_CTRLr(_unit, _pc, _val, _mask) \ 666 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0002, 0x1c, \ 667 (_val), (_mask)) 668 #else /* RDB_Reg. 0x012 */ 669 #define PHY_READ_BCM542XX_SPARE_CTRLr(_unit, _pc, _val) \ 670 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x012, _val) 671 #define PHY_WRITE_BCM542XX_SPARE_CTRLr(_unit, _pc, _val) \ 672 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x012, _val) 673 #define PHY_MODIFY_BCM542XX_SPARE_CTRLr(_unit, _pc, _val, _mask) \ 674 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x012, _val, _mask) 675 #endif 676 677 /* 1000BASE-T/100BASE-TX/10BASE-T Clk Alignment Ctrl (ADDR 1ch shadow 00011) */ 678 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 03h) */ 679 #define PHY_READ_BCM542XX_CLK_ALIGN_CTRLr(_unit, _pc, _val) \ 680 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0003, 0x1c, (_val)) 681 #define PHY_WRITE_BCM542XX_CLK_ALIGN_CTRLr(_unit, _pc, _val) \ 682 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0003, 0x1c, (_val)) 683 #define PHY_MODIFY_BCM542XX_CLK_ALIGN_CTRLr(_unit, _pc, _val, _mask) \ 684 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0003, 0x1c, \ 685 (_val), (_mask)) 686 #else /* RDB_Reg. 0x013 */ 687 #define PHY_READ_BCM542XX_CLK_ALIGN_CTRLr(_unit, _pc, _val) \ 688 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x013, _val) 689 #define PHY_WRITE_BCM542XX_CLK_ALIGN_CTRLr(_unit, _pc, _val) \ 690 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x013, _val) 691 #define PHY_MODIFY_BCM542XX_CLK_ALIGN_CTRLr(_unit, _pc, _val, _mask) \ 692 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x013, _val, _mask) 693 #endif 694 695 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 2 Reg (ADDR 1ch shadow 00100) */ 696 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 04h) */ 697 #define PHY_READ_BCM542XX_SPARE_CTRL_2r(_unit, _pc, _val) \ 698 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0004, 0x1c, (_val)) 699 #define PHY_WRITE_BCM542XX_SPARE_CTRL_2r(_unit, _pc, _val) \ 700 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0004, 0x1c, (_val)) 701 #define PHY_MODIFY_BCM542XX_SPARE_CTRL_2r(_unit, _pc, _val, _mask) \ 702 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0004, 0x1c, \ 703 (_val), (_mask)) 704 #else /* RDB_Reg. 0x014 */ 705 #define PHY_READ_BCM542XX_SPARE_CTRL_2r(_unit, _pc, _val) \ 706 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x014, _val) 707 #define PHY_WRITE_BCM542XX_SPARE_CTRL_2r(_unit, _pc, _val) \ 708 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x014, _val) 709 #define PHY_MODIFY_BCM542XX_SPARE_CTRL_2r(_unit, _pc, _val, _mask) \ 710 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x014, _val, _mask) 711 #endif 712 713 /* 1000BASE-T/100BASE-TX/10BASE-T Spare Ctrl 3 Reg (ADDR 1ch shadow 00101) */ 714 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 05h) */ 715 #define PHY_READ_BCM542XX_SPARE_CTRL_3r(_unit, _pc, _val) \ 716 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0005, 0x1c, (_val)) 717 #define PHY_WRITE_BCM542XX_SPARE_CTRL_3r(_unit, _pc, _val) \ 718 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0005, 0x1c, (_val)) 719 #define PHY_MODIFY_BCM542XX_SPARE_CTRL_3r(_unit, _pc, _val, _mask) \ 720 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0005, 0x1c, \ 721 (_val), (_mask)) 722 #else /* RDB_Reg. 0x015 */ 723 #define PHY_READ_BCM542XX_SPARE_CTRL_3r(_unit, _pc, _val) \ 724 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x015, _val) 725 #define PHY_WRITE_BCM542XX_SPARE_CTRL_3r(_unit, _pc, _val) \ 726 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x015, _val) 727 #define PHY_MODIFY_BCM542XX_SPARE_CTRL_3r(_unit, _pc, _val, _mask) \ 728 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x015, _val, _mask) 729 #endif 730 731 /* 1000BASE-T/100BASE-TX/10BASE-T LED Status Reg (ADDR 1ch shadow 01000) */ 732 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 08h) */ 733 #define PHY_READ_BCM542XX_LED_STATr(_unit, _pc, _val) \ 734 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0008, 0x1c, (_val)) 735 #define PHY_WRITE_BCM542XX_LED_STATr(_unit, _pc, _val) \ 736 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0008, 0x1c, (_val)) 737 #define PHY_MODIFY_BCM542XX_LED_STATr(_unit, _pc, _val, _mask) \ 738 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0008, 0x1c, \ 739 (_val), (_mask)) 740 #else /* RDB_Reg. 0x018 */ 741 #define PHY_READ_BCM542XX_LED_STATr(_unit, _pc, _val) \ 742 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x018, _val) 743 #define PHY_WRITE_BCM542XX_LED_STATr(_unit, _pc, _val) \ 744 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x018, _val) 745 #define PHY_MODIFY_BCM542XX_LED_STATr(_unit, _pc, _val, _mask) \ 746 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x018, _val, _mask) 747 #endif 748 749 /* 1000BASE-T/100BASE-TX/10BASE-T LED Ctrl Reg (ADDR 1ch shadow 01001) */ 750 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 09h) */ 751 #define PHY_READ_BCM542XX_LED_CTRLr(_unit, _pc, _val) \ 752 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0009, 0x1c, (_val)) 753 #define PHY_WRITE_BCM542XX_LED_CTRLr(_unit, _pc, _val) \ 754 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0009, 0x1c, (_val)) 755 #define PHY_MODIFY_BCM542XX_LED_CTRLr(_unit, _pc, _val, _mask) \ 756 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0009, 0x1c, \ 757 (_val), (_mask)) 758 #else /* RDB_Reg. 0x019 */ 759 #define PHY_READ_BCM542XX_LED_CTRLr(_unit, _pc, _val) \ 760 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x019, _val) 761 #define PHY_WRITE_BCM542XX_LED_CTRLr(_unit, _pc, _val) \ 762 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x019, _val) 763 #define PHY_MODIFY_BCM542XX_LED_CTRLr(_unit, _pc, _val, _mask) \ 764 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x019, _val, _mask) 765 #endif 766 767 /* Auto Power-Down Reg (ADDR 1ch shadow 01010) */ 768 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 0Ah) */ 769 #define PHY_READ_BCM542XX_AUTO_POWER_DOWNr(_unit, _pc, _val) \ 770 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x000a, 0x1c, (_val)) 771 #define PHY_WRITE_BCM542XX_AUTO_POWER_DOWNr(_unit, _pc, _val) \ 772 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x000a, 0x1c, (_val)) 773 #define PHY_MODIFY_BCM542XX_AUTO_POWER_DOWNr(_unit, _pc, _val, _mask) \ 774 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x000a, 0x1c, \ 775 (_val), (_mask)) 776 #else /* RDB_Reg. 0x01A */ 777 #define PHY_READ_BCM542XX_AUTO_POWER_DOWNr(_unit, _pc, _val) \ 778 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x01a, _val) 779 #define PHY_WRITE_BCM542XX_AUTO_POWER_DOWNr(_unit, _pc, _val) \ 780 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x01a, _val) 781 #define PHY_MODIFY_BCM542XX_AUTO_POWER_DOWNr(_unit, _pc, _val, _mask) \ 782 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x01a, _val, _mask) 783 #endif 784 785 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Reg (ADDR 1ch shadow 01101) */ 786 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 0Dh) */ 787 #define PHY_READ_BCM542XX_LED_SELECTOR_1r(_unit, _pc, _val) \ 788 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x000d, 0x1c, (_val)) 789 #define PHY_WRITE_BCM542XX_LED_SELECTOR_1r(_unit, _pc, _val) \ 790 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x000d, 0x1c, (_val)) 791 #define PHY_MODIFY_BCM542XX_LED_SELECTOR_1r(_unit, _pc, _val, _mask) \ 792 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x000d, 0x1c, \ 793 (_val), (_mask)) 794 #else /* RDB_Reg. 0x01D */ 795 #define PHY_READ_BCM542XX_LED_SELECTOR_1r(_unit, _pc, _val) \ 796 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x01d, _val) 797 #define PHY_WRITE_BCM542XX_LED_SELECTOR_1r(_unit, _pc, _val) \ 798 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x01d, _val) 799 #define PHY_MODIFY_BCM542XX_LED_SELECTOR_1r(_unit, _pc, _val, _mask) \ 800 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x01d, _val, _mask) 801 #endif 802 803 /* 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Reg (ADDR 1ch shadow 01110) */ 804 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 0Eh) */ 805 #define PHY_READ_BCM542XX_LED_SELECTOR_2r(_unit, _pc, _val) \ 806 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x000e, 0x1c, (_val)) 807 #define PHY_WRITE_BCM542XX_LED_SELECTOR_2r(_unit, _pc, _val) \ 808 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x000e, 0x1c, (_val)) 809 #define PHY_MODIFY_BCM542XX_LED_SELECTOR_2r(_unit, _pc, _val, _mask) \ 810 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x000e, 0x1c, \ 811 (_val), (_mask)) 812 #else /* RDB_Reg. 0x01E */ 813 #define PHY_READ_BCM542XX_LED_SELECTOR_2r(_unit, _pc, _val) \ 814 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x01e, _val) 815 #define PHY_WRITE_BCM542XX_LED_SELECTOR_2r(_unit, _pc, _val) \ 816 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x01e, _val) 817 #define PHY_MODIFY_BCM542XX_LED_SELECTOR_2r(_unit, _pc, _val, _mask) \ 818 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x01e, _val, _mask) 819 #endif 820 821 /* 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Ctrl/Stat (ADDR 1ch shadow 01111) */ 822 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 0Fh) */ 823 #define PHY_READ_BCM542XX_LED_GPIO_CTRLr(_unit, _pc, _val) \ 824 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x000f, 0x1c, (_val)) 825 #define PHY_WRITE_BCM542XX_LED_GPIO_CTRLr(_unit, _pc, _val) \ 826 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x000f, 0x1c, (_val)) 827 #define PHY_MODIFY_BCM542XX_LED_GPIO_CTRLr(_unit, _pc, _val, _mask) \ 828 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x000f, 0x1c, \ 829 (_val), (_mask)) 830 #else /* RDB_Reg. 0x01F */ 831 #define PHY_READ_BCM542XX_LED_GPIO_CTRLr(_unit, _pc, _val) \ 832 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x01f, _val) 833 #define PHY_WRITE_BCM542XX_LED_GPIO_CTRLr(_unit, _pc, _val) \ 834 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x01f, _val) 835 #define PHY_MODIFY_BCM542XX_LED_GPIO_CTRLr(_unit, _pc, _val, _mask) \ 836 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x01f, _val, _mask) 837 #endif 838 839 840 /* SerDes 100BASE-FX Status Reg (ADDR 1ch shadow 10001) */ 841 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 11h) */ 842 #define PHY_READ_BCM542XX_100FX_STATr(_unit, _pc, _val) \ 843 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0011, 0x1c, (_val)) 844 #define PHY_WRITE_BCM542XX_100FX_STATr(_unit, _pc, _val) \ 845 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0011, 0x1c, (_val)) 846 #define PHY_MODIFY_BCM542XX_100FX_STATr(_unit, _pc, _val, _mask) \ 847 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0011, 0x1c, \ 848 (_val), (_mask)) 849 #else /* RDB_Reg. 0x231 */ 850 #define PHY_READ_BCM542XX_100FX_STATr(_unit, _pc, _val) \ 851 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x231, _val) 852 #define PHY_WRITE_BCM542XX_100FX_STATr(_unit, _pc, _val) \ 853 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x231, _val) 854 #define PHY_MODIFY_BCM542XX_100FX_STATr(_unit, _pc, _val, _mask) \ 855 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x231, _val, _mask) 856 #endif 857 858 859 /* SerDes 100BASE-FX Control Reg (ADDR 1ch shadow 10011) */ 860 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 13h) */ 861 #define PHY_READ_BCM542XX_100FX_CTRLr(_unit, _pc, _val) \ 862 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0013, 0x1c, (_val)) 863 #define PHY_WRITE_BCM542XX_100FX_CTRLr(_unit, _pc, _val) \ 864 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0013, 0x1c, (_val)) 865 #define PHY_MODIFY_BCM542XX_100FX_CTRLr(_unit, _pc, _val, _mask) \ 866 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0013, 0x1c, \ 867 (_val), (_mask)) 868 #else /* RDB_Reg. 0x233 */ 869 #define PHY_READ_BCM542XX_100FX_CTRLr(_unit, _pc, _val) \ 870 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x233, _val) 871 #define PHY_WRITE_BCM542XX_100FX_CTRLr(_unit, _pc, _val) \ 872 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x233, _val) 873 #define PHY_MODIFY_BCM542XX_100FX_CTRLr(_unit, _pc, _val, _mask) \ 874 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x233, _val, _mask) 875 #endif 876 877 878 /* External SerDes Control Reg (ADDR 1ch shadow 10100) */ 879 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 14h) */ 880 #define PHY_READ_BCM542XX_EXT_SERDES_CTRLr(_unit, _pc, _val) \ 881 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0014, 0x1c, (_val)) 882 #define PHY_WRITE_BCM542XX_EXT_SERDES_CTRLr(_unit, _pc, _val) \ 883 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0014, 0x1c, (_val)) 884 #define PHY_MODIFY_BCM542XX_EXT_SERDES_CTRLr(_unit, _pc, _val, _mask) \ 885 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0014, 0x1c, \ 886 (_val), (_mask)) 887 #else /* RDB_Reg. 0x234 */ 888 #define PHY_READ_BCM542XX_EXT_SERDES_CTRLr(_unit, _pc, _val) \ 889 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x234, _val) 890 #define PHY_WRITE_BCM542XX_EXT_SERDES_CTRLr(_unit, _pc, _val) \ 891 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x234, _val) 892 #define PHY_MODIFY_BCM542XX_EXT_SERDES_CTRLr(_unit, _pc, _val, _mask) \ 893 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x234, _val, _mask) 894 #endif 895 896 /* SGMII Slave Reg (ADDR 1ch shadow 10101) */ 897 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 15h) */ 898 #define PHY_READ_BCM542XX_SGMII_SLAVEr(_unit, _pc, _val) \ 899 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0015, 0x1c, (_val)) 900 #define PHY_WRITE_BCM542XX_SGMII_SLAVEr(_unit, _pc, _val) \ 901 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0015, 0x1c, (_val)) 902 #define PHY_MODIFY_BCM542XX_SGMII_SLAVEr(_unit, _pc, _val, _mask) \ 903 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0015, 0x1c, \ 904 (_val), (_mask)) 905 #else /* RDB_Reg. 0x235 */ 906 #define PHY_READ_BCM542XX_SGMII_SLAVEr(_unit, _pc, _val) \ 907 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x235, _val) 908 #define PHY_WRITE_BCM542XX_SGMII_SLAVEr(_unit, _pc, _val) \ 909 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x235, _val) 910 #define PHY_MODIFY_BCM542XX_SGMII_SLAVEr(_unit, _pc, _val, _mask) \ 911 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x235, _val, _mask) 912 #endif 913 914 /* Primary SerDes Control Reg (ADDR 1ch shadow 10110) */ 915 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 16h) */ 916 #define PHY_READ_BCM542XX_1ST_SERDES_CTRLr(_unit, _pc, _val) \ 917 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0016, 0x1c, (_val)) 918 #define PHY_WRITE_BCM542XX_1ST_SERDES_CTRLr(_unit, _pc, _val) \ 919 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0016, 0x1c, (_val)) 920 #define PHY_MODIFY_BCM542XX_1ST_SERDES_CTRLr(_unit, _pc, _val, _mask) \ 921 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0016, 0x1c, \ 922 (_val), (_mask)) 923 #else /* RDB_Reg. 0x236 */ 924 #define PHY_READ_BCM542XX_1ST_SERDES_CTRLr(_unit, _pc, _val) \ 925 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x236, _val) 926 #define PHY_WRITE_BCM542XX_1ST_SERDES_CTRLr(_unit, _pc, _val) \ 927 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x236, _val) 928 #define PHY_MODIFY_BCM542XX_1ST_SERDES_CTRLr(_unit, _pc, _val, _mask) \ 929 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x236, _val, _mask) 930 #endif 931 #define PHY_BCM542XX_SERDES_CTRL_JUMBO_MSB BIT(0) 932 #define PHY_BCM542XX_SERDES_CTRL_AN_PD_EN BIT(1) 933 934 /* Misc 1000BASE-X Control (ADDR 1ch shadow 10111) */ 935 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 17h) */ 936 #define PHY_READ_BCM542XX_MISC_1000X_CONTROLr(_unit, _pc, _val) \ 937 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0017, 0x1c, (_val)) 938 #define PHY_WRITE_BCM542XX_MISC_1000X_CONTROLr(_unit, _pc, _val) \ 939 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0017, 0x1c, (_val)) 940 #define PHY_MODIFY_BCM542XX_MISC_1000X_CONTROLr(_unit, _pc, _val, _mask) \ 941 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0017, 0x1c, \ 942 (_val), (_mask)) 943 #else /* RDB_Reg. 0x237 */ 944 #define PHY_READ_BCM542XX_MISC_1000X_CONTROLr(_unit, _pc, _val) \ 945 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x237, _val) 946 #define PHY_WRITE_BCM542XX_MISC_1000X_CONTROLr(_unit, _pc, _val) \ 947 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x237, _val) 948 #define PHY_MODIFY_BCM542XX_MISC_1000X_CONTROLr(_unit, _pc, _val, _mask) \ 949 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x237, _val, _mask) 950 #endif 951 952 /* 1000BASE-X Auto-Detect SGMII/Media Converter Reg (ADDR 1ch shadow 11000) */ 953 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 18h) */ 954 #define PHY_READ_BCM542XX_AUTO_DETECT_SGMII_MEDIAr(_unit, _pc, _val) \ 955 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0018, 0x1c, (_val)) 956 #define PHY_WRITE_BCM542XX_AUTO_DETECT_SGMII_MEDIAr(_unit, _pc, _val) \ 957 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0018, 0x1c, (_val)) 958 #define PHY_MODIFY_BCM542XX_AUTO_DETECT_SGMII_MEDIAr(_unit, _pc, _val, _mask) \ 959 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0018, 0x1c, \ 960 (_val), (_mask)) 961 #else /* RDB_Reg. 0x238 */ 962 #define PHY_READ_BCM542XX_AUTO_DETECT_SGMII_MEDIAr(_unit, _pc, _val) \ 963 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x238, _val) 964 #define PHY_WRITE_BCM542XX_AUTO_DETECT_SGMII_MEDIAr(_unit, _pc, _val) \ 965 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x238, _val) 966 #define PHY_MODIFY_BCM542XX_AUTO_DETECT_SGMII_MEDIAr(_unit, _pc, _val, _mask) \ 967 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x238, _val, _mask) 968 #endif 969 970 /* 1000BASE-X Auto-neg Debug Reg (ADDR 1ch shadow 11010) */ 971 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 1Ah) */ 972 #define PHY_READ_BCM542XX_1000X_AN_DEBUGr(_unit, _pc, _val) \ 973 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x001a, 0x1c, (_val)) 974 #define PHY_WRITE_BCM542XX_1000X_AN_DEBUGr(_unit, _pc, _val) \ 975 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x001a, 0x1c, (_val)) 976 #define PHY_MODIFY_BCM542XX_1000X_AN_DEBUGr(_unit, _pc, _val, _mask) \ 977 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x001a, 0x1c, \ 978 (_val), (_mask)) 979 #else /* RDB_Reg. 0x23A */ 980 #define PHY_READ_BCM542XX_1000X_AN_DEBUGr(_unit, _pc, _val) \ 981 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x23a, _val) 982 #define PHY_WRITE_BCM542XX_1000X_AN_DEBUGr(_unit, _pc, _val) \ 983 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x23a, _val) 984 #define PHY_MODIFY_BCM542XX_1000X_AN_DEBUGr(_unit, _pc, _val, _mask) \ 985 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x23a, _val, _mask) 986 #endif 987 988 #define PHY_MODIFY_BCM542XX_AUTO_DETECT_GMII_FIFO_JUMBO_LSB BIT(2) 989 990 /* Auxiliary 1000BASE-X Control Reg (ADDR 1ch shadow 11011) */ 991 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 1Bh) */ 992 #define PHY_READ_BCM542XX_AUX_1000X_CTRLr(_unit, _pc, _val) \ 993 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x001b, 0x1c, (_val)) 994 #define PHY_WRITE_BCM542XX_AUX_1000X_CTRLr(_unit, _pc, _val) \ 995 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x001b, 0x1c, (_val)) 996 #define PHY_MODIFY_BCM542XX_AUX_1000X_CTRLr(_unit, _pc, _val, _mask) \ 997 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x001b, 0x1c, \ 998 (_val), (_mask)) 999 #else /* RDB_Reg. 0x23B */ 1000 #define PHY_READ_BCM542XX_AUX_1000X_CTRLr(_unit, _pc, _val) \ 1001 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x23b, _val) 1002 #define PHY_WRITE_BCM542XX_AUX_1000X_CTRLr(_unit, _pc, _val) \ 1003 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x23b, _val) 1004 #define PHY_MODIFY_BCM542XX_AUX_1000X_CTRLr(_unit, _pc, _val, _mask) \ 1005 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x23b, _val, _mask) 1006 #endif 1007 #define PHY_BCM542XX_SERDES_CTRL_JUMBO_LSB BIT(1) 1008 1009 /* Auxiliary 1000BASE-X Status Reg (ADDR 1ch shadow 11100) */ 1010 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 1Ch) */ 1011 #define PHY_READ_BCM542XX_AUX_1000X_STATr(_unit, _pc, _val) \ 1012 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x001c, 0x1c, (_val)) 1013 #define PHY_WRITE_BCM542XX_AUX_1000X_STATr(_unit, _pc, _val) \ 1014 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x001c, 0x1c, (_val)) 1015 #define PHY_MODIFY_BCM542XX_AUX_1000X_STATr(_unit, _pc, _val, _mask) \ 1016 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x001c, 0x1c, \ 1017 (_val), (_mask)) 1018 #else /* RDB_Reg. 0x23C */ 1019 #define PHY_READ_BCM542XX_AUX_1000X_STATr(_unit, _pc, _val) \ 1020 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x23c, _val) 1021 #define PHY_WRITE_BCM542XX_AUX_1000X_STATr(_unit, _pc, _val) \ 1022 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x23c, _val) 1023 #define PHY_MODIFY_BCM542XX_AUX_1000X_STATr(_unit, _pc, _val, _mask) \ 1024 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x23c, _val, _mask) 1025 #endif 1026 1027 /* Misc 1000BASE-X Status Reg (ADDR 1ch shadow 11101) */ 1028 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 1Dh) */ 1029 #define PHY_READ_BCM542XX_MISC_1000X_STATr(_unit, _pc, _val) \ 1030 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x001d, 0x1c, (_val)) 1031 #define PHY_WRITE_BCM542XX_MISC_1000X_STATr(_unit, _pc, _val) \ 1032 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x001d, 0x1c, (_val)) 1033 #define PHY_MODIFY_BCM542XX_MISC_1000X_STATr(_unit, _pc, _val, _mask) \ 1034 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x001d, 0x1c, \ 1035 (_val), (_mask)) 1036 #else /* RDB_Reg. 0x23D */ 1037 #define PHY_READ_BCM542XX_MISC_1000X_STATr(_unit, _pc, _val) \ 1038 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x23d, _val) 1039 #define PHY_WRITE_BCM542XX_MISC_1000X_STATr(_unit, _pc, _val) \ 1040 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x23d, _val) 1041 #define PHY_MODIFY_BCM542XX_MISC_1000X_STATr(_unit, _pc, _val, _mask) \ 1042 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x23d, _val, _mask) 1043 #endif 1044 1045 /* Copper/Fiber Auto-Detect Medium Reg (ADDR 1ch shadow 11110) */ 1046 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 1Eh) */ 1047 #define PHY_READ_BCM542XX_AUTO_DETECT_MEDIUMr(_unit, _pc, _val) \ 1048 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x001e, 0x1c, (_val)) 1049 #define PHY_WRITE_BCM542XX_AUTO_DETECT_MEDIUMr(_unit, _pc, _val) \ 1050 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x001e, 0x1c, (_val)) 1051 #define PHY_MODIFY_BCM542XX_AUTO_DETECT_MEDIUMr(_unit, _pc, _val, _mask) \ 1052 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x001e, 0x1c, \ 1053 (_val), (_mask)) 1054 #else /* RDB_Reg. 0x23E */ 1055 #define PHY_READ_BCM542XX_AUTO_DETECT_MEDIUMr(_unit, _pc, _val) \ 1056 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x23e, _val) 1057 #define PHY_WRITE_BCM542XX_AUTO_DETECT_MEDIUMr(_unit, _pc, _val) \ 1058 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x23e, _val) 1059 #define PHY_MODIFY_BCM542XX_AUTO_DETECT_MEDIUMr(_unit, _pc, _val, _mask) \ 1060 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x23e, _val, _mask) 1061 #endif 1062 1063 1064 /* Mode Control Reg (ADDR 1ch shadow 11111) */ 1065 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Ch Shadow 1Fh) */ 1066 #define PHY_READ_BCM542XX_MODE_CTRLr(_unit, _pc, _val) \ 1067 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x001f, 0x1c, (_val)) 1068 #define PHY_WRITE_BCM542XX_MODE_CTRLr(_unit, _pc, _val) \ 1069 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x001f, 0x1c, (_val)) 1070 #define PHY_MODIFY_BCM542XX_MODE_CTRLr(_unit, _pc, _val, _mask) \ 1071 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x001f, 0x1c, \ 1072 (_val), (_mask)) 1073 #else /* RDB_Reg. 0x021 */ 1074 #define PHY_READ_BCM542XX_MODE_CTRLr(_unit, _pc, _val) \ 1075 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x021, _val) 1076 #define PHY_WRITE_BCM542XX_MODE_CTRLr(_unit, _pc, _val) \ 1077 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x021, _val) 1078 #define PHY_MODIFY_BCM542XX_MODE_CTRLr(_unit, _pc, _val, _mask) \ 1079 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x021, _val, _mask) 1080 #endif 1081 1082 1083 /* 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 */ 1084 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Legacy Addr 1Eh */ 1085 #define PHY_READ_BCM542XX_TEST1r(_unit, _pc, _val) \ 1086 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0000, 0x1e, (_val)) 1087 #define PHY_WRITE_BCM542XX_TEST1r(_unit, _pc, _val) \ 1088 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0000, 0x1e, (_val)) 1089 #define PHY_MODIFY_BCM542XX_TEST1r(_unit, _pc, _val, _mask) \ 1090 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0000, 0x1e, \ 1091 (_val), (_mask)) 1092 #else /* RDB_Reg. 0x00E */ 1093 #define PHY_READ_BCM542XX_TEST1r(_unit, _pc, _val) \ 1094 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x00e, _val) 1095 #define PHY_WRITE_BCM542XX_TEST1r(_unit, _pc, _val) \ 1096 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x00e, _val) 1097 #define PHY_MODIFY_BCM542XX_TEST1r(_unit, _pc, _val, _mask) \ 1098 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x00e, _val, _mask) 1099 #endif 1100 1101 /* Top Level Configuration Register RDB_Reg. 0x810 */ 1102 #define PHY_READ_BCM542XX_TOP_LVL_CONFGr(_unit, _pc, _val) \ 1103 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x810, _val) 1104 #define PHY_WRITE_BCM542XX_TOP_LVL_CONFGr(_unit, _pc, _val) \ 1105 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x810, _val) 1106 #define PHY_MODIFY_BCM542XX_TOP_LVL_CONFGr(_unit, _pc, _val, _mask) \ 1107 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x810, _val, _mask) 1108 1109 1110 /* +------------------------------+ 1111 * | | 1112 * | Primary SerDes Registers | 1113 * | | 1114 * +------------------------------+ 1115 */ 1116 /* 1000BASE-X MII Control Register (Addr 00h) */ 1117 #define PHY_READ_BCM542XX_1000X_MII_CTRLr(_unit, _pc, _val) \ 1118 PHY_BCM542XX_REG_RD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1119 0x0000, 0x00, (_val)) 1120 #define PHY_WRITE_BCM542XX_1000X_MII_CTRLr(_unit, _pc, _val) \ 1121 PHY_BCM542XX_REG_WR((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1122 0x0000, 0x00, (_val)) 1123 #define PHY_MODIFY_BCM542XX_1000X_MII_CTRLr(_unit, _pc, _val, _mask) \ 1124 PHY_BCM542XX_REG_MOD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1125 0x0000, 0x00, (_val), (_mask)) 1126 #define PHY_MODIFY_BCM542XX_PRI_SERDES_MII_CTRLr(_unit, _pc, _val, _mask) \ 1127 PHY_BCM542XX_REG_MOD((_unit), (_pc), PHY_BCM542XX_REG_PRI_SERDES, \ 1128 0x0000, 0x00, (_val), (_mask)) 1129 1130 /* 1000BASE-X MII Status Register (Addr 01h) */ 1131 #define PHY_READ_BCM542XX_1000X_MII_STATr(_unit, _pc, _val) \ 1132 PHY_BCM542XX_REG_RD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1133 0x0000, 0x01, (_val)) 1134 #define PHY_WRITE_BCM542XX_1000X_MII_STATr(_unit, _pc, _val) \ 1135 PHY_BCM542XX_REG_WR((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1136 0x0000, 0x01, (_val)) 1137 #define PHY_MODIFY_BCM542XX_1000X_MII_STATr(_unit, _pc, _val, _mask) \ 1138 PHY_BCM542XX_REG_MOD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1139 0x0000, 0x01, (_val), (_mask)) 1140 1141 /* 1000BASE-X MII Auto-neg Advertise Register (Addr 04h) */ 1142 #define PHY_READ_BCM542XX_1000X_MII_ANAr(_unit, _pc, _val) \ 1143 PHY_BCM542XX_REG_RD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1144 0x0000, 0x04, (_val)) 1145 #define PHY_WRITE_BCM542XX_1000X_MII_ANAr(_unit, _pc, _val) \ 1146 PHY_BCM542XX_REG_WR((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1147 0x0000, 0x04, (_val)) 1148 #define PHY_MODIFY_BCM542XX_1000X_MII_ANAr(_unit, _pc, _val, _mask) \ 1149 PHY_BCM542XX_REG_MOD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1150 0x0000, 0x04, (_val), (_mask)) 1151 1152 /* 1000BASE-X MII Auto-neg Link Partner Ability Register (Addr 05h) */ 1153 #define PHY_READ_BCM542XX_1000X_MII_ANPr(_unit, _pc, _val) \ 1154 PHY_BCM542XX_REG_RD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1155 0x0000, 0x05, (_val)) 1156 #define PHY_WRITE_BCM542XX_1000X_MII_ANPr(_unit, _pc, _val) \ 1157 PHY_BCM542XX_REG_WR((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1158 0x0000, 0x05, (_val)) 1159 #define PHY_MODIFY_BCM542XX_1000X_MII_ANPr(_unit, _pc, _val, _mask) \ 1160 PHY_BCM542XX_REG_MOD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1161 0x0000, 0x05, (_val), (_mask)) 1162 1163 /* 1000BASE-X MII Auto-neg Extended Status Register (Addr 06h) */ 1164 #define PHY_READ_BCM542XX_1000X_MII_AN_EXPr(_unit, _pc, _val) \ 1165 PHY_BCM542XX_REG_RD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1166 0x0000, 0x06, (_val)) 1167 #define PHY_WRITE_BCM542XX_1000X_MII_AN_EXPr(_unit, _pc, _val) \ 1168 PHY_BCM542XX_REG_WR((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1169 0x0000, 0x06, (_val)) 1170 #define PHY_MODIFY_BCM542XX_1000X_MII_AN_EXPr(_unit, _pc, _val, _mask) \ 1171 PHY_BCM542XX_REG_MOD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1172 0x0000, 0x06, (_val), (_mask)) 1173 1174 /* 1000BASE-X MII IEEE Extended Status Register (Addr 0fh) */ 1175 #define PHY_READ_BCM542XX_1000X_MII_EXT_STATr(_unit, _pc, _val) \ 1176 PHY_BCM542XX_REG_RD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1177 0x0000, 0x0f, (_val)) 1178 #define PHY_WRITE_BCM542XX_1000X_MII_EXT_STATr(_unit, _pc, _val) \ 1179 PHY_BCM542XX_REG_WR((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1180 0x0000, 0x0f, (_val)) 1181 #define PHY_MODIFY_BCM542XX_1000X_MII_EXT_STATr(_unit, _pc, _val, _mask) \ 1182 PHY_BCM542XX_REG_MOD((_unit), (_pc), PHY_BCM542XX_REG_1000X, \ 1183 0x0000, 0x0f, (_val), (_mask)) 1184 1185 /* +-------------------------+ 1186 * | | 1187 * | Expansion Registers | 1188 * | | 1189 * +-------------------------+ 1190 */ 1191 /* Receive/Transmit Packet Counter Register (Addr 00h) */ 1192 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 00h */ 1193 #define PHY_READ_BCM542XX_EXP_PKT_COUNTERr(_unit, _pc, _val) \ 1194 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f00, 0x15, (_val)) 1195 #define PHY_WRITE_BCM542XX_EXP_PKT_COUNTERr(_unit, _pc, _val) \ 1196 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f00, 0x15, (_val)) 1197 #define PHY_MODIFY_BCM542XX_EXP_PKT_COUNTERr(_unit, _pc, _val, _mask) \ 1198 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f00, 0x15, (_val), (_mask)) 1199 #else /* RDB_Reg. 0x030 */ 1200 #define PHY_READ_BCM542XX_EXP_PKT_COUNTERr(_unit, _pc, _val) \ 1201 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x030, _val) 1202 #define PHY_WRITE_BCM542XX_EXP_PKT_COUNTERr(_unit, _pc, _val) \ 1203 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x030, _val) 1204 #define PHY_MODIFY_BCM542XX_EXP_PKT_COUNTERr(_unit, _pc, _val, _mask) \ 1205 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x030, _val, _mask) 1206 #endif 1207 1208 /* Expansion Interrupt Status Register (Addr 01h) */ 1209 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 01h */ 1210 #define PHY_READ_BCM542XX_EXP_INTERRUPT_STATr(_unit, _pc, _val) \ 1211 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f01, 0x15, (_val)) 1212 #define PHY_WRITE_BCM542XX_EXP_r(_unit, _pc, _val) \ 1213 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f01, 0x15, (_val)) 1214 #define PHY_MODIFY_BCM542XX_EXP_r(_unit, _pc, _val, _mask) \ 1215 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f01, 0x15, (_val), (_mask)) 1216 #else /* RDB_Reg. 0x031 */ 1217 #define PHY_READ_BCM542XX_EXP_INTERRUPT_STATr(_unit, _pc, _val) \ 1218 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x031, _val) 1219 #define PHY_WRITE_BCM542XX_EXP_r(_unit, _pc, _val) \ 1220 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x031, _val) 1221 #define PHY_MODIFY_BCM542XX_EXP_r(_unit, _pc, _val, _mask) \ 1222 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x031, _val, _mask) 1223 #endif 1224 1225 /* Expansion Interrupt Mask Register (Addr 02h) */ 1226 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 02h */ 1227 #define PHY_READ_BCM542XX_EXP_INTERRUPT_MASKr(_unit, _pc, _val) \ 1228 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f02, 0x15, (_val)) 1229 #define PHY_WRITE_BCM542XX_EXP_INTERRUPT_MASKr(_unit, _pc, _val) \ 1230 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f02, 0x15, (_val)) 1231 #define PHY_MODIFY_BCM542XX_EXP_INTERRUPT_MASKr(_unit, _pc, _val, _mask) \ 1232 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f02, 0x15, (_val), (_mask)) 1233 #else /* RDB_Reg. 0x032 */ 1234 #define PHY_READ_BCM542XX_EXP_INTERRUPT_MASKr(_unit, _pc, _val) \ 1235 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x032, _val) 1236 #define PHY_WRITE_BCM542XX_EXP_INTERRUPT_MASKr(_unit, _pc, _val) \ 1237 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x032, _val) 1238 #define PHY_MODIFY_BCM542XX_EXP_INTERRUPT_MASKr(_unit, _pc, _val, _mask) \ 1239 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x032, _val, _mask) 1240 #endif 1241 1242 /* Multicolor LED Selector Register (Addr 04h) */ 1243 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 04h */ 1244 #define PHY_READ_BCM542XX_EXP_LED_SELECTORr(_unit, _pc, _val) \ 1245 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f04, 0x15, (_val)) 1246 #define PHY_WRITE_BCM542XX_EXP_LED_SELECTORr(_unit, _pc, _val) \ 1247 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f04, 0x15, (_val)) 1248 #define PHY_MODIFY_BCM542XX_EXP_LED_SELECTORr(_unit, _pc, _val, _mask) \ 1249 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f04, 0x15, (_val), (_mask)) 1250 #else /* RDB_Reg. 0x034 */ 1251 #define PHY_READ_BCM542XX_EXP_LED_SELECTORr(_unit, _pc, _val) \ 1252 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x034, _val) 1253 #define PHY_WRITE_BCM542XX_EXP_LED_SELECTORr(_unit, _pc, _val) \ 1254 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x034, _val) 1255 #define PHY_MODIFY_BCM542XX_EXP_LED_SELECTORr(_unit, _pc, _val, _mask) \ 1256 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x034, _val, _mask) 1257 #endif 1258 1259 /* Multicolor LED Flash Rate Controls Register (Addr 05h) */ 1260 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 05h */ 1261 #define PHY_READ_BCM542XX_EXP_LED_FLASH_CTRLr(_unit, _pc, _val) \ 1262 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f05, 0x15, (_val)) 1263 #define PHY_WRITE_BCM542XX_EXP_LED_FLASH_CTRLr(_unit, _pc, _val) \ 1264 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f05, 0x15, (_val)) 1265 #define PHY_MODIFY_BCM542XX_EXP_LED_FLASH_CTRLr(_unit, _pc, _val, _mask) \ 1266 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f05, 0x15, (_val), (_mask)) 1267 #else /* RDB_Reg. 0x035 */ 1268 #define PHY_READ_BCM542XX_EXP_LED_FLASH_CTRLr(_unit, _pc, _val) \ 1269 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x035, _val) 1270 #define PHY_WRITE_BCM542XX_EXP_LED_FLASH_CTRLr(_unit, _pc, _val) \ 1271 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x035, _val) 1272 #define PHY_MODIFY_BCM542XX_EXP_LED_FLASH_CTRLr(_unit, _pc, _val, _mask) \ 1273 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x035, _val, _mask) 1274 #endif 1275 1276 /* Multicolor LED Programmable Blink Controls Register (Addr 06h) */ 1277 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 06h */ 1278 #define PHY_READ_BCM542XX_EXP_LED_BLINK_CTRLr(_unit, _pc, _val) \ 1279 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f06, 0x15, (_val)) 1280 #define PHY_WRITE_BCM542XX_EXP_LED_BLINK_CTRLr(_unit, _pc, _val) \ 1281 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f06, 0x15, (_val)) 1282 #define PHY_MODIFY_BCM542XX_EXP_LED_BLINK_CTRLr(_unit, _pc, _val, _mask) \ 1283 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f06, 0x15, (_val), (_mask)) 1284 #else /* RDB_Reg. 0x036 */ 1285 #define PHY_READ_BCM542XX_EXP_LED_BLINK_CTRLr(_unit, _pc, _val) \ 1286 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x036, _val) 1287 #define PHY_WRITE_BCM542XX_EXP_LED_BLINK_CTRLr(_unit, _pc, _val) \ 1288 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x036, _val) 1289 #define PHY_MODIFY_BCM542XX_EXP_LED_BLINK_CTRLr(_unit, _pc, _val, _mask) \ 1290 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x036, _val, _mask) 1291 #endif 1292 1293 /* Expansion register 0x8 (For auto_early_dac_wake)*/ 1294 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 08h */ 1295 #define PHY_READ_BCM542XX_EXP_EIGHTr(_unit, _pc, _val) \ 1296 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f08, 0x15, (_val)) 1297 #define PHY_WRITE_BCM542XX_EXP_EIGHTr(_unit, _pc, _val) \ 1298 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f08, 0x15, (_val)) 1299 #define PHY_MODIFY_BCM542XX_EXP_EIGHTr(_unit, _pc, _val, _mask) \ 1300 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f08, 0x15, (_val), (_mask)) 1301 #else /* RDB_Reg. 0x038 */ 1302 #define PHY_READ_BCM542XX_EXP_EIGHTr(_unit, _pc, _val) \ 1303 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x038, _val) 1304 #define PHY_WRITE_BCM542XX_EXP_EIGHTr(_unit, _pc, _val) \ 1305 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x038, _val) 1306 #define PHY_MODIFY_BCM542XX_EXP_EIGHTr(_unit, _pc, _val, _mask) \ 1307 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x038, _val, _mask) 1308 #endif 1309 1310 /* Operating Mode Status Register (Addr 42h) */ 1311 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 42h */ 1312 #define PHY_READ_BCM542XX_EXP_OPT_MODE_STATr(_unit, _pc, _val) \ 1313 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f42, 0x15, (_val)) 1314 #define PHY_WRITE_BCM542XX_EXP_OPT_MODE_STATr(_unit, _pc, _val) \ 1315 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f42, 0x15, (_val)) 1316 #define PHY_MODIFY_BCM542XX_EXP_OPT_MODE_STATr(_unit, _pc, _val, _mask) \ 1317 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f42, 0x15, (_val), (_mask)) 1318 #else /* RDB_Reg. 0x051 */ 1319 #define PHY_READ_BCM542XX_EXP_OPT_MODE_STATr(_unit, _pc, _val) \ 1320 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x051, _val) 1321 #define PHY_WRITE_BCM542XX_EXP_OPT_MODE_STATr(_unit, _pc, _val) \ 1322 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x051, _val) 1323 #define PHY_MODIFY_BCM542XX_EXP_OPT_MODE_STATr(_unit, _pc, _val, _mask) \ 1324 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x051, _val, _mask) 1325 #endif 1326 1327 /* Pattern Generator Status Register (Addr 46h) */ 1328 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr */ 1329 #define PHY_READ_BCM542XX_EXP_PATT_GEN_STATr(_unit, _pc, _val) \ 1330 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f46, 0x15, (_val)) 1331 #define PHY_WRITE_BCM542XX_EXP_PATT_GEN_STATr(_unit, _pc, _val) \ 1332 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f46, 0x15, (_val)) 1333 #define PHY_MODIFY_BCM542XX_EXP_PATT_GEN_STATr(_unit, _pc, _val, _mask) \ 1334 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f46, 0x15, (_val), (_mask)) 1335 #else /* RDB_Reg. 0x006 */ 1336 #define PHY_READ_BCM542XX_EXP_PATT_GEN_STATr(_unit, _pc, _val) \ 1337 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x006, _val) 1338 #define PHY_WRITE_BCM542XX_EXP_PATT_GEN_STATr(_unit, _pc, _val) \ 1339 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x006, _val) 1340 #define PHY_MODIFY_BCM542XX_EXP_PATT_GEN_STATr(_unit, _pc, _val, _mask) \ 1341 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x006, _val, _mask) 1342 #endif 1343 #define PHY_BCM542XX_PATT_GEN_STAT_FIFO_ELAST_1 BIT(14) 1344 #define PHY_BCM542XX_PATT_GEN_STAT_GMII_FIFO_JUMBO_MSB BIT(15) 1345 1346 /* SerDes/SGMII RX Control Register (Addr 50h) */ 1347 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr */ 1348 #define PHY_READ_BCM542XX_EXP_SERDES_SGMII_RXCTRLr(_unit, _pc, _val) \ 1349 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f50, 0x15, (_val)) 1350 #define PHY_WRITE_BCM542XX_EXP_SERDES_SGMII_RXCTRLr(_unit, _pc, _val) \ 1351 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f50, 0x15, (_val)) 1352 #define PHY_MODIFY_BCM542XX_EXP_SERDES_SGMII_RXCTRLr(_unit, _pc, _val, _mask) \ 1353 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f50, 0x15, (_val), (_mask)) 1354 #else /* RDB_Reg. [unknown] */ 1355 #define PHY_READ_BCM542XX_EXP_SERDES_SGMII_RXCTRLr(_unit, _pc, _val) \ 1356 PHY_BCM542XX_RDB_RD(_unit, _pc, 0xfff, _val) 1357 #define PHY_WRITE_BCM542XX_EXP_SERDES_SGMII_RXCTRLr(_unit, _pc, _val) \ 1358 PHY_BCM542XX_RDB_WR(_unit, _pc, 0xfff, _val) 1359 #define PHY_MODIFY_BCM542XX_EXP_SERDES_SGMII_RXCTRLr(_unit, _pc, _val, _mask) \ 1360 PHY_BCM542XX_RDB_MO(_unit, _pc, 0xfff, _val, _mask) 1361 #endif 1362 1363 /* SerDes/SGMII RX/TX Control Register (Addr 52h) */ 1364 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr */ 1365 #define PHY_READ_BCM542XX_EXP_SERDES_SGMII_CTRLr(_unit, _pc, _val) \ 1366 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f52, 0x15, (_val)) 1367 #define PHY_WRITE_BCM542XX_EXP_SERDES_SGMII_CTRLr(_unit, _pc, _val) \ 1368 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f52, 0x15, (_val)) 1369 #define PHY_MODIFY_BCM542XX_EXP_SERDES_SGMII_CTRLr(_unit, _pc, _val, _mask) \ 1370 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f52, 0x15, (_val), (_mask)) 1371 #else /* RDB_Reg. [unknown] */ 1372 #define PHY_READ_BCM542XX_EXP_SERDES_SGMII_CTRLr(_unit, _pc, _val) \ 1373 PHY_BCM542XX_RDB_RD(_unit, _pc, 0xfff, _val) 1374 #define PHY_WRITE_BCM542XX_EXP_SERDES_SGMII_CTRLr(_unit, _pc, _val) \ 1375 PHY_BCM542XX_RDB_WR(_unit, _pc, 0xfff, _val) 1376 #define PHY_MODIFY_BCM542XX_EXP_SERDES_SGMII_CTRLr(_unit, _pc, _val, _mask) \ 1377 PHY_BCM542XX_RDB_MO(_unit, _pc, 0xfff, _val, _mask) 1378 #endif 1379 1380 /* External MACSec Interface Control Register (Addr 7fh) */ 1381 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr 7Fh */ 1382 #define PHY_READ_BCM542XX_EXP_EXT_MACSEC_IF_CTRLr(_unit, _pc, _val) \ 1383 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0f7f, 0x15, (_val)) 1384 #define PHY_WRITE_BCM542XX_EXP_EXT_MACSEC_IF_CTRLr(_unit, _pc, _val) \ 1385 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0f7f, 0x15, (_val)) 1386 #define PHY_MODIFY_BCM542XX_EXP_EXT_MACSEC_IF_CTRLr(_unit, _pc, _val, _mask) \ 1387 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0f7f, 0x15, (_val), (_mask)) 1388 #else /* RDB_Reg. 0x07F */ 1389 #define PHY_READ_BCM542XX_EXP_EXT_MACSEC_IF_CTRLr(_unit, _pc, _val) \ 1390 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x07f, _val) 1391 #define PHY_WRITE_BCM542XX_EXP_EXT_MACSEC_IF_CTRLr(_unit, _pc, _val) \ 1392 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x07f, _val) 1393 #define PHY_MODIFY_BCM542XX_EXP_EXT_MACSEC_IF_CTRLr(_unit, _pc, _val, _mask) \ 1394 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x07f, _val, _mask) 1395 #endif 1396 1397 /* Time Sync */ 1398 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr F5h */ 1399 #define PHY_READ_BCM542XX_TIME_SYNC_CTRLr(_unit, _pc, _val) \ 1400 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0ff5, 0x15, (_val)) 1401 #define PHY_WRITE_BCM542XX_TIME_SYNC_CTRLr(_unit, _pc, _val) \ 1402 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0ff5, 0x15, (_val)) 1403 #define PHY_MODIFY_BCM542XX_TIME_SYNC_CTRLr(_unit, _pc, _val, _mask) \ 1404 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0ff5, 0x15, (_val), (_mask)) 1405 #else /* RDB_Reg. 0x0F5 */ 1406 #define PHY_READ_BCM542XX_TIME_SYNC_CTRLr(_unit, _pc, _val) \ 1407 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x0f5, _val) 1408 #define PHY_WRITE_BCM542XX_TIME_SYNC_CTRLr(_unit, _pc, _val) \ 1409 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x0f5, _val) 1410 #define PHY_MODIFY_BCM542XX_TIME_SYNC_CTRLr(_unit, _pc, _val, _mask) \ 1411 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x0f5, _val, _mask) 1412 #endif 1413 1414 /* EEE Statistics Registers*/ 1415 1416 /* EEE Statistic Timer_12_hours_lpi remote Reg (Addr aah) */ 1417 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr AAh */ 1418 #define PHY_READ_BCM542XX_EEE_STAT_TX_DURATIONr(_unit, _pc, _val) \ 1419 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0faa, 0x15, (_val)) 1420 #define PHY_WRITE_BCM542XX_EEE_STAT_TX_DURATIONr(_unit, _pc, _val) \ 1421 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0faa, 0x15, (_val)) 1422 #define PHY_MODIFY_BCM542XX__EEE_STAT_TX_DURATIONr(_unit, _pc, _val, _mask) \ 1423 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0faa, 0x15, (_val), (_mask)) 1424 #else /* RDB_Reg. 0x0AA */ 1425 #define PHY_READ_BCM542XX_EEE_STAT_TX_DURATIONr(_unit, _pc, _val) \ 1426 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x0aa, _val) 1427 #define PHY_WRITE_BCM542XX_EEE_STAT_TX_DURATIONr(_unit, _pc, _val) \ 1428 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x0aa, _val) 1429 #define PHY_MODIFY_BCM542XX__EEE_STAT_TX_DURATIONr(_unit, _pc, _val, _mask) \ 1430 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x0aa, _val, _mask) 1431 #endif 1432 1433 /* EEE Statistic Timer_12_hours_lpi local Reg (Addr abh) */ 1434 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr ABh */ 1435 #define PHY_READ_BCM542XX_EEE_STAT_RX_DURATIONr(_unit, _pc, _val) \ 1436 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0fab, 0x15, (_val)) 1437 #define PHY_WRITE_BCM542XX_EEE_STAT_RX_DURATIONr(_unit, _pc, _val) \ 1438 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0fab, 0x15, (_val)) 1439 #define PHY_MODIFY_BCM542XX__EEE_STAT_RX_DURATIONr(_unit, _pc, _val, _mask) \ 1440 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0fab, 0x15, (_val), (_mask)) 1441 #else /* RDB_Reg. 0x0AB */ 1442 #define PHY_READ_BCM542XX_EEE_STAT_RX_DURATIONr(_unit, _pc, _val) \ 1443 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x0ab, _val) 1444 #define PHY_WRITE_BCM542XX_EEE_STAT_RX_DURATIONr(_unit, _pc, _val) \ 1445 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x0ab, _val) 1446 #define PHY_MODIFY_BCM542XX__EEE_STAT_RX_DURATIONr(_unit, _pc, _val, _mask) \ 1447 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x0ab, _val, _mask) 1448 #endif 1449 1450 /* EEE Local LPI request Counter Reg (Addr ACh) */ 1451 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr ACh */ 1452 #define PHY_READ_BCM542XX_EEE_STAT_TX_EVENTSr(_unit, _pc, _val) \ 1453 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0fac, 0x15, (_val)) 1454 #define PHY_WRITE_BCM542XX_EEE_STAT_TX_EVENTSr(_unit, _pc, _val) \ 1455 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0fac, 0x15, (_val)) 1456 #define PHY_MODIFY_BCM542XX__EEE_STAT_TX_EVENTSr(_unit, _pc, _val, _mask) \ 1457 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0fac, 0x15, (_val), (_mask)) 1458 #else /* RDB_Reg. 0x0AC */ 1459 #define PHY_READ_BCM542XX_EEE_STAT_TX_EVENTSr(_unit, _pc, _val) \ 1460 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x0ac, _val) 1461 #define PHY_WRITE_BCM542XX_EEE_STAT_TX_EVENTSr(_unit, _pc, _val) \ 1462 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x0ac, _val) 1463 #define PHY_MODIFY_BCM542XX__EEE_STAT_TX_EVENTSr(_unit, _pc, _val, _mask) \ 1464 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x0ac, _val, _mask) 1465 #endif 1466 1467 /* EEE Remote LPI request Counter Reg (Addr ADh) */ 1468 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr ADh */ 1469 #define PHY_READ_BCM542XX_EEE_STAT_RX_EVENTSr(_unit, _pc, _val) \ 1470 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0fad, 0x15, (_val)) 1471 #define PHY_WRITE_BCM542XX_EEE_STAT_RX_EVENTSr(_unit, _pc, _val) \ 1472 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0fad, 0x15, (_val)) 1473 #define PHY_MODIFY_BCM542XX_EEE_STAT_RX_EVENTSr(_unit, _pc, _val, _mask) \ 1474 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0fad, 0x15, (_val), (_mask)) 1475 #else /* RDB_Reg. 0x0AD */ 1476 #define PHY_READ_BCM542XX_EEE_STAT_RX_EVENTSr(_unit, _pc, _val) \ 1477 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x0ad, _val) 1478 #define PHY_WRITE_BCM542XX_EEE_STAT_RX_EVENTSr(_unit, _pc, _val) \ 1479 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x0ad, _val) 1480 #define PHY_MODIFY_BCM542XX_EEE_STAT_RX_EVENTSr(_unit, _pc, _val, _mask) \ 1481 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x0ad, _val, _mask) 1482 #endif 1483 1484 /* EEE Statistic counters ctrl/status (Addr AFh) */ 1485 #ifdef PHY_BCM542XX_DEFAULT_TO_LEGACY_ADDRESSING /* Exp.Addr AFh */ 1486 #define PHY_READ_BCM542XX_EEE_STAT_CTRLr(_unit, _pc, _val) \ 1487 PHY_BCM542XX_REG_RD((_unit), (_pc), 0x00, 0x0faf, 0x15, (_val)) 1488 #define PHY_WRITE_BCM542XX_EEE_STAT_CTRLr(_unit, _pc, _val) \ 1489 PHY_BCM542XX_REG_WR((_unit), (_pc), 0x00, 0x0faf, 0x15, (_val)) 1490 #define PHY_MODIFY_BCM542XX_EEE_STAT_CTRLr(_unit, _pc, _val, _mask) \ 1491 PHY_BCM542XX_REG_MOD((_unit), (_pc), 0x00, 0x0faf, 0x15, (_val), (_mask)) 1492 #else /* RDB_Reg. 0x0AF */ 1493 #define PHY_READ_BCM542XX_EEE_STAT_CTRLr(_unit, _pc, _val) \ 1494 PHY_BCM542XX_RDB_RD(_unit, _pc, 0x0af, _val) 1495 #define PHY_WRITE_BCM542XX_EEE_STAT_CTRLr(_unit, _pc, _val) \ 1496 PHY_BCM542XX_RDB_WR(_unit, _pc, 0x0af, _val) 1497 #define PHY_MODIFY_BCM542XX_EEE_STAT_CTRLr(_unit, _pc, _val, _mask) \ 1498 PHY_BCM542XX_RDB_MO(_unit, _pc, 0x0af, _val, _mask) 1499 #endif 1500 1501 /* 1502 * 1503 * CL45 Registers: EEE 1504 */ 1505 /* EEE Capability Register */ 1506 #define PHY_READ_BCM542XX_EEE_CAPr( _unit, _pc, _val) \ 1507 PHY_BCM542XX_CL45_REG_READ( (_unit), (_pc), 0x3, 0x14, (_val)) 1508 1509 /* EEE Advertisement Register */ 1510 #define PHY_READ_BCM542XX_EEE_ADVr(_unit, _pc, _val) \ 1511 PHY_BCM542XX_CL45_REG_READ( (_unit), (_pc), 0x7, 0x3c, _val) 1512 #define PHY_WRITE_BCM542XX_EEE_ADVr(_unit, _pc, _val) \ 1513 PHY_BCM542XX_CL45_REG_WRITE((_unit), (_pc), 0x7, 0x3c, (_val)) 1514 #define PHY_MODIFY_BCM542XX_EEE_ADVr(_unit, _pc, _val, _mask) \ 1515 PHY_BCM542XX_CL45_REG_MODIFY((_unit), (_pc), 0x7, 0x3c, (_val), (_mask)) 1516 1517 #define PHY_READ_BCM542XX_EEE_803Dr(_unit, _pc, _val) \ 1518 PHY_BCM542XX_CL45_REG_READ(_unit, _pc, 0x7, 0x803d, _val) 1519 #define PHY_WRITE_BCM542XX_EEE_803Dr(_unit, _pc, _val) \ 1520 PHY_BCM542XX_CL45_REG_WRITE(_unit, _pc, 0x7, 0x803d, _val) 1521 #define PHY_MODIFY_BCM542XX_EEE_803Dr(_unit, _pc, _val, _mask) \ 1522 PHY_BCM542XX_CL45_REG_MODIFY(_unit, _pc, 0x7, 0x803d, _val, _mask) 1523 1524 /* EEE Resolution Status Register */ 1525 #define PHY_READ_BCM542XX_EEE_RESOLUTION_STATr( _unit, _pc, _val) \ 1526 PHY_BCM542XX_CL45_REG_READ(_unit, _pc, 0x7, 0x803e, _val) 1527 #define PHY_WRITE_BCM542XX_EEE_RESOLUTION_STATr(_unit, _pc, _val) \ 1528 PHY_BCM542XX_CL45_REG_WRITE(_unit, _pc, 0x7, 0x803e, _val) 1529 #define PHY_MODIFY_BCM542XX_EEE_RESOLUTION_STATr(_unit, _pc, _val, _mask) \ 1530 PHY_BCM542XX_CL45_REG_MODIFY(_unit, _pc,, 0x7, 0x803e, _val, _mask) 1531 1532 #define PHY_READ_BCM542XX_EEE_TEST_CTRL_Ar(_unit, _pc, _val) \ 1533 PHY_BCM542XX_CL45_REG_READ( _unit, _pc, 0x7, 0x8031, _val) 1534 #define PHY_WRITE_BCM542XX_EEE_TEST_CTRL_Ar(_unit, _pc, _val) \ 1535 PHY_BCM542XX_CL45_REG_WRITE( _unit, _pc, 0x7, 0x8031, _val) 1536 #define PHY_MODIFY_BCM542XX_EEE_TEST_CTRL_Ar(_unit, _pc, _val, _mask) \ 1537 PHY_BCM542XX_CL45_REG_MODIFY(_unit, _pc, 0x7, 0x8031, _val, _mask) 1538 1539 /* EEE capability advertisement */ 1540 #define PHY_BCM542XX_EEE_ADV_10G (BIT3) /* EEE advertise for 10GBASE-T */ 1541 #define PHY_BCM542XX_EEE_ADV_1000 (BIT2) /* EEE advertise for 1000BASE-T */ 1542 #define PHY_BCM542XX_EEE_ADV_100 (BIT1) /* EEE advertise for 100BASE-T */ 1543 #define PHY_BCM542XX_EEE_ADV_MASK (BIT3 | BIT2 | BIT1) 1544 1545 /* *\ 1546 |* PHY Device Descriptor *| 1547 \* */ 1548 typedef struct { 1549 soc_port_config_phy_oam_t oam_config; 1550 uint32 flags; 1551 uint16 phy_id_orig; 1552 uint16 phy_id_base; /* port 0 addr */ 1553 uint16 phy_slice; 1554 int32 port_pre_speed; 1555 } PHY_BCM542XX_DEV_DESC_t; 1556 1557 #define PHY_BCM542XX_DEV_OAM_CONFIG_PTR(_pc) \ 1558 (&(((PHY_BCM542XX_DEV_DESC_t *)((_pc) + 1))->oam_config)) 1559 #define PHY_BCM542XX_DEV_PHY_ID_ORIG(_pc) \ 1560 (((PHY_BCM542XX_DEV_DESC_t *)((_pc) + 1))->phy_id_orig) 1561 #define PHY_BCM542XX_DEV_PHY_ID_BASE(_pc) \ 1562 (((PHY_BCM542XX_DEV_DESC_t *)((_pc) + 1))->phy_id_base) 1563 #define PHY_BCM542XX_DEV_PHY_SLICE(_pc) \ 1564 (((PHY_BCM542XX_DEV_DESC_t *)((_pc) + 1))->phy_slice) 1565 #define PHY_BCM542XX_FLAGS(_pc) \ 1566 (((PHY_BCM542XX_DEV_DESC_t *)((_pc) + 1))->flags) 1567 #define PHY_BCM542XX_PHYADDR_REVERSE (BIT0) 1568 #define PHY_BCM542XX_REAR_HALF (BIT1) 1569 #define PHY_BCM542XX_IS_REAR_HALF(_pc) \ 1570 (PHY_BCM542XX_FLAGS(_pc) & PHY_BCM542XX_REAR_HALF) 1571 #define PHY_BCM542XX_SET_REAR_HALF(_pc) \ 1572 do { PHY_BCM542XX_FLAGS(_pc) |= PHY_BCM542XX_REAR_HALF; } while (0) 1573 1574 #define PHY_BCM542XX_DEV_SET_BASE_ADDR(_pc) \ 1575 PHY_BCM542XX_DEV_PHY_ID_BASE(_pc) = \ 1576 (PHY_BCM542XX_FLAGS((_pc)) & PHY_BCM542XX_PHYADDR_REVERSE) \ 1577 ? PHY_BCM542XX_DEV_PHY_ID_ORIG(_pc) + PHY_BCM542XX_DEV_PHY_SLICE(_pc) \ 1578 : PHY_BCM542XX_DEV_PHY_ID_ORIG(_pc) - PHY_BCM542XX_DEV_PHY_SLICE(_pc) 1579 1580 #define PHY_BCM542XX_SLICE_ADDR(_pc, _slice) \ 1581 (PHY_BCM542XX_FLAGS((_pc)) & PHY_BCM542XX_PHYADDR_REVERSE) \ 1582 ? (PHY_BCM542XX_DEV_PHY_ID_BASE(_pc) - (_slice)) \ 1583 : (PHY_BCM542XX_DEV_PHY_ID_BASE(_pc) + (_slice)) 1584 1585 #endif /* _PHY542XX_INT_H */