phy53xxx.h (3292B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy53xxx.h 8 * Purpose: Fiber driver for 53xxx using internal QuadSerdes PHY. 9 */ 10 11 #ifndef _PHY_53XXX_H 12 #define _PHY_53XXX_H 13 /* QS: MII Control bit definitions, same as Standard 10/100 PHY */ 14 #define QS_MII_CTRL_RESET MII_CTRL_RESET /* Self clearing SW reset */ 15 #define QS_MII_CTRL_SS_LSB MII_CTRL_SS_LSB /* Speed Select, LSB */ 16 #define QS_MII_CTRL_SS_MSB MII_CTRL_SS_MSB /* Speed Select, MSB */ 17 #define QS_MII_CTRL_SS(_x) MII_CTRL_SS(_x) 18 #define QS_MII_CTRL_SS_10 MII_CTRL_SS_10 19 #define QS_MII_CTRL_SS_100 MII_CTRL_SS_100 20 #define QS_MII_CTRL_SS_1000 MII_CTRL_SS_1000 21 #define QS_MII_CTRL_SS_INVALID MII_CTRL_SS_INVALID 22 #define QS_MII_CTRL_SS_MASK MII_CTRL_SS_MASK 23 #define QS_MII_CTRL_FD MII_CTRL_FD /* Full Duplex */ 24 #define QS_MII_CTRL_AN_RESTART (1 << 9) /* Auto Negotiation Enable */ 25 #define QS_MII_CTRL_AN_ENABLE (1 << 12) /* Auto Negotiation Enable */ 26 #define QS_MII_CTRL_PD MII_CTRL_PD /* Power Down Enable */ 27 #define QS_MII_CTRL_LOOPBACK (1 << 14) /* Loopback Enable */ 28 29 30 /* Auto-Negotiation Link-Partner Ability Register */ 31 #define QS_MII_ANP_SGMII (1 << 0) 32 #define QS_MII_ANP_SGMII_DUPLEX (1 << 12) 33 #define QS_MII_ANP_SGMII_SPEED (3 << 10) 34 #define QS_MII_ANP_SGMII_SPEED_10 (0) 35 #define QS_MII_ANP_SGMII_SPEED_100 (1 << 10) 36 #define QS_MII_ANP_SGMII_SPEED_1000 (1 << 11) 37 38 39 40 41 42 /* 1000X Control #1 Register: Controls 10B/SGMII mode */ 43 #define QS_1000X_FIBER_MODE (1 << 0) /* Enable SGMII fiber mode */ 44 #define QS_1000X_EN10B_MODE (1 << 1) /* Enable TBI 10B interface */ 45 #define QS_1000X_INVERT_SD (1 << 3) /* Invert Signal Detect */ 46 #define QS_1000X_AUTO_DETECT (1 << 4) /* Auto-detect SGMII and 1000X */ 47 #define QS_1000X_RX_PKTS_CNTR_SEL (1 << 11) /* Select receive counter for 17h*/ 48 #define QS_1000X_TX_AMPLITUDE_OVRD (1 << 12) 49 50 /* 1000X Control #2 Register Fields */ 51 #define QS_1000X_PAR_DET_EN (1 << 0) /* Enable Parallel Detect */ 52 #define QS_1000X_FALSE_LNK_DIS (1 << 1) /* Disable false link */ 53 #define QS_1000X_FLT_FORCE_EN (1 << 2) /* Enable filter force link */ 54 #define QS_1000X_CLRAR_BER_CNTR (1 << 14) /* Clear bit-err-rate counter */ 55 56 /* 1000X Control #3 Register Fields */ 57 #define QS_1000X_TX_FIFO_RST (1 << 0) /* Reset TX FIFO */ 58 #define QS_1000X_FIFO_ELASTICITY_MASK (0x3 << 1) /* Fifo Elasticity */ 59 #define QS_1000X_FIFO_ELASTICITY_5K (0x0 << 1) /* 5 Kbytes */ 60 #define QS_1000X_FIFO_ELASTICITY_10K (0x1 << 1) /* 10 Kbytes */ 61 #define QS_1000X_FIFO_ELASTICITY_13_5K (0x2 << 1) /* 13.5 Kbytes */ 62 #define QS_1000X_RX_FIFO_RST (1 << 14) /* Reset RX FIFO */ 63 64 /* 1000X Control #4 Register Fields */ 65 #define QS_1000X_DIG_RESET (1 << 6) /* Reset Datapath */ 66 67 /* 1000X Status #1 Register Fields */ 68 #define QS_1000X_STATUS1_SGMII_MODE (1 << 0) 69 #define QS_1000X_STATUS1_SPEED (3 << 3) 70 #define QS_1000X_STATUS1_SPEED_10 (0) 71 #define QS_1000X_STATUS1_SPEED_100 (1 << 3) 72 #define QS_1000X_STATUS1_SPEED_1000 (1 << 4) 73 74 75 #endif /* _PHY_53XXX_H*/ 76