phy522x.h (11515B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phy54xx.h 8 * Purpose: 9 */ 10 11 #ifndef _PHY522X_H_ 12 #define _PHY522X_H_ 13 14 /* If application want to use this header file for accessing PHY registers, 15 * simply redefine PHY522X_REG macros to use BCM API as follows. 16 * 17 * #define PHY522X_REG_READ(_unit, _port, _flags, _reg_bank, \ 18 * _reg_addr, _val) \ 19 * bcm_port_phy_get((_unit), (_port), 0, 20 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 21 * (_val)) 22 * 23 * #define PHY522X_REG_WRITE(_unit, _port, _flags, _reg_bank, \ 24 * _reg_addr, _val) \ 25 * bcm_port_phy_set((_unit), (_port), 0, 26 * BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr), 27 * (_val)) 28 * 29 * #define PHY522X_REG_MODIFY(_unit, _port, _flags, _reg_bank, \ 30 * _reg_addr, _val)\ 31 * do { \ 32 * return BCM_E_UNAVAIL; \ 33 * } while(0) 34 */ 35 36 /* PHY register access */ 37 #define PHY522X_REG_READ(_unit, _phy_ctrl, _reg_bank, _reg_addr, _val) \ 38 phy_reg_fe_read((_unit), (_phy_ctrl), (_reg_bank), \ 39 (_reg_addr), (_val)) 40 #define PHY522X_REG_WRITE(_unit, _phy_ctrl, _reg_bank, _reg_addr, _val) \ 41 phy_reg_fe_write((_unit), (_phy_ctrl), (_reg_bank), \ 42 (_reg_addr), (_val)) 43 #define PHY522X_REG_MODIFY(_unit, _phy_ctrl, _reg_bank, \ 44 _reg_addr, _val, _mask) \ 45 phy_reg_fe_modify((_unit), (_phy_ctrl), (_reg_bank), (_reg_addr), \ 46 (_val), (_mask)) 47 48 49 /* 100BASE-TX/10BASE-T MII Control Register (Addr 00h) */ 50 #define READ_PHY522X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 51 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x00, (_val)) 52 #define WRITE_PHY522X_MII_CTRLr(_unit, _phy_ctrl, _val) \ 53 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x00, (_val)) 54 #define MODIFY_PHY522X_MII_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 55 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x00, \ 56 (_val), (_mask)) 57 58 /* 100BASE-TX/10BASE-T MII Status Register (ADDR 01h) */ 59 #define READ_PHY522X_MII_STATr(_unit, _phy_ctrl, _val) \ 60 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x01, (_val)) 61 #define WRITE_PHY522X_MII_STATr(_unit, _phy_ctrl, _val) \ 62 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x01, (_val)) 63 #define MODIFY_PHY522X_MII_STATr(_unit, _phy_ctrl, _val, _mask) \ 64 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x01, \ 65 (_val), (_mask)) 66 67 /* 100BASE-TX/10BASE-T PHY Identifier Register (ADDR 02h) */ 68 #define READ_PHY522X_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 69 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x02, (_val)) 70 #define WRITE_PHY522X_MII_PHY_ID0r(_unit, _phy_ctrl, _val) \ 71 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x02, (_val)) 72 #define MODIFY_PHY522X_MII_PHY_ID0r(_unit, _phy_ctrl, _val, _mask) \ 73 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x02, \ 74 (_val), (_mask)) 75 76 /* 100BASE-TX/10BASE-T PHY Identifier Register (ADDR 03h) */ 77 #define READ_PHY522X_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 78 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x03, (_val)) 79 #define WRITE_PHY522X_MII_PHY_ID1r(_unit, _phy_ctrl, _val) \ 80 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x03, (_val)) 81 #define MODIFY_PHY522X_MII_PHY_ID1r(_unit, _phy_ctrl, _val, _mask) \ 82 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x03, \ 83 (_val), (_mask)) 84 85 /* 100BASE-TX/10BASE-T Auto-neg Advertisment Register (ADDR 04h) */ 86 #define READ_PHY522X_MII_ANAr(_unit, _phy_ctrl, _val) \ 87 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x04, (_val) 88 #define WRITE_PHY522X_MII_ANAr(_unit, _phy_ctrl, _val) \ 89 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x04, (_val) 90 #define MODIFY_PHY522X_MII_ANAr(_unit, _phy_ctrl, _val, _mask) \ 91 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x04, \ 92 (_val), (_mask)) 93 94 /* 100BASE-TX/10BASE-T Auto-neg Link Partner Ability (ADDR 05h) */ 95 #define READ_PHY522X_MII_ANPr(_unit, _phy_ctrl, _val) \ 96 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x05, (_val)) 97 #define WRITE_PHY522X_MII_ANPr(_unit, _phy_ctrl, _val) \ 98 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x05, (_val)) 99 #define MODIFY_PHY522X_MII_ANPr(_unit, _phy_ctrl, _val, _mask) \ 100 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x05, \ 101 (_val), (_mask)) 102 103 /* 100BASE-TX/10BASE-T Auto-neg Expansion Register (ADDR 06h) */ 104 #define READ_PHY522X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 105 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x06, (_val)) 106 #define WRITE_PHY522X_MII_AN_EXPr(_unit, _phy_ctrl, _val) \ 107 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x06, (_val)) 108 #define MODIFY_PHY522X_MII_AN_EXPr(_unit, _phy_ctrl, _val, _mask) \ 109 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x06, \ 110 (_val), (_mask)) 111 112 /* 100BASE-TX/10BASE-T Next Page Transmit Register (ADDR 07h) */ 113 /* 100BASE-TX/10BASE-T Link Partner Received Next Page (ADDR 08h) */ 114 115 /* 100BASE-X Auxiliary Control Register (Addr 10h) */ 116 #define READ_PHY522X_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 117 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x10, (_val)) 118 #define WRITE_PHY522X_AUX_CTRLr(_unit, _phy_ctrl, _val) \ 119 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x10, (_val)) 120 #define MODIFY_PHY522X_AUX_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 121 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x10, \ 122 (_val), (_mask)) 123 124 /* Misc Control Register (Shadow Addr 10h) */ 125 #define READ_PHY522X_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 126 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0001, 0x10, (_val)) 127 #define WRITE_PHY522X_MISC_CTRLr(_unit, _phy_ctrl, _val) \ 128 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0001, 0x10 (_val)) 129 #define MODIFY_PHY522X_MISC_CTRLr(_unit, _phy_ctrl, _val, _mask) \ 130 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0001, 0x10, \ 131 (_val), (_mask)) 132 133 /* 100BASE-X Auxiliary Status Register (ADDR 11h) */ 134 #define READ_PHY522X_AUX_STATr(_unit, _phy_ctrl, _val) \ 135 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x11, (_val)) 136 #define WRITE_PHY522X_AUX_STATr(_unit, _phy_ctrl, _val) \ 137 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x11, (_val)) 138 #define MODIFY_PHY522X_AUX_STATr(_unit, _phy_ctrl, _val, _mask) \ 139 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x11, \ 140 (_val), (_mask)) 141 142 /* 100BASE-X Receiver Error Counter Register (Addr 12h) */ 143 #define READ_PHY522X_RECV_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 144 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x12, (_val)) 145 #define WRITE_PHY522X_RECV_ERR_COUNTERr(_unit, _phy_ctrl, _val) \ 146 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x12, (_val)) 147 #define MODIFY_PHY522X_RECV_ERR_COUNTERr(_unit, _phy_ctrl, _val, _mask) \ 148 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x12, \ 149 (_val), (_mask)) 150 151 /* 100BASE-X False Carrier Sense Counter (Addr 13h) */ 152 153 /* 100BASE-X Disconnect Counter (Addr 14h) */ 154 155 /* Ptest Register (Addr 17h) */ 156 157 /* Auxiliary Control/Status Register (Addr 18h) */ 158 159 /* Auxiliary Status Summary Register (Addr 19h) */ 160 161 /* Interrupt Register (Addr 1ah) */ 162 163 /* Auxiliary Mode 4 Register (Shadow Addr 1ah) */ 164 #define READ_PHY522X_AUX_MODE4r(_unit, _phy_ctrl, _val) \ 165 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0001, 0x1a, (_val)) 166 #define WRITE_PHY522X_AUX_MODE4r(_unit, _phy_ctrl, _val) \ 167 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0001, 0x1a, (_val)) 168 #define MODIFY_PHY522X_AUX_MODE4r(_unit, _phy_ctrl, _val, _mask) \ 169 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0001, 0x1a, \ 170 (_val), (_mask)) 171 172 /* Auxiliary Mode 2 Register (Addr 1bh) */ 173 #define READ_PHY522X_AUX_MODE2r(_unit, _phy_ctrl, _val) \ 174 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x1b, (_val)) 175 #define WRITE_PHY522X_AUX_MODE2r(_unit, _phy_ctrl, _val) \ 176 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x1b, (_val)) 177 #define MODIFY_PHY522X_AUX_MODE2r(_unit, _phy_ctrl, _val, _mask) \ 178 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x1b, \ 179 (_val), (_mask)) 180 181 /* Auxiliary Status 2 Register (Shadow Addr 1bh) */ 182 #define READ_PHY522X_AUX_STAT2r(_unit, _phy_ctrl, _val) \ 183 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0001, 0x1B, (_val)) 184 #define WRITE_PHY522X_AUX_STAT2r(_unit, _phy_ctrl, _val) \ 185 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0001, 0x1B, (_val)) 186 #define MODIFY_PHY522X_AUX_STAT2r(_unit, _phy_ctrl, _val, _mask) \ 187 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0001, 0x1B, \ 188 (_val), (_mask)) 189 190 #define PHY_522X_AUTO_PWRDWN_EN (1 << 5) 191 #define PHY_522X_AUTO_PWRDWN_WAKEUP_MASK (0xF << 0) 192 #define PHY_522X_AUTO_PWRDWN_WAKEUP_UNIT 40 /* ms */ 193 #define PHY_522X_AUTO_PWRDWN_WAKEUP_MAX 600 /* ms */ 194 #define PHY_522X_AUTO_PWRDWN_SLEEP_MASK (1 << 4) 195 #define PHY_522X_AUTO_PWRDWN_SLEEP_MAX 5000 /* ms */ 196 197 /* Auxiliary Error & General Status Register (Addr 1ch) */ 198 #define READ_PHY522X_AUX_ERR_GENERAL_STATr(_unit, _phy_ctrl, _val) \ 199 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x1c, (_val)) 200 #define WRITE_PHY522X__AUX_ERR_GENERAL_STATr(_unit, _phy_ctrl, _val) \ 201 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x1c (_val)) 202 #define MODIFY_PHY522X_AUX_ERR_GENERAL_STATr(_unit, _phy_ctrl, _val, _mask) \ 203 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x1c, \ 204 (_val), (_mask)) 205 206 /* Auxiliary Status Register (Shadow Addr 1ch) */ 207 208 /* Auxiliary Mode Register (Addr 1dh) */ 209 210 /* Auxiliary Mode 3 Register (Shadow Addr 1dh) */ 211 #define READ_PHY522X_AUX_MODE3r(_unit, _phy_ctrl, _val) \ 212 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0001, 0x1d, (_val)) 213 #define WRITE_PHY522X__AUX_MODE3r(_unit, _phy_ctrl, _val) \ 214 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0001, 0x1d (_val)) 215 #define MODIFY_PHY522X_AUX_MODE3r(_unit, _phy_ctrl, _val, _mask) \ 216 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0001, 0x1d, \ 217 (_val), (_mask)) 218 219 /* Auxiliary Multiple PHY Register (Addr 1eh) */ 220 221 #define READ_PHY522X_AUX_MULTIPLE_PHYr(_unit, _phy_ctrl, _val) \ 222 PHY522X_REG_READ((_unit), (_phy_ctrl), 0x0000, 0x1e, (_val)) 223 #define WRITE_PHY522X_AUX_MULTIPLE_PHYr(_unit, _phy_ctrl, _val) \ 224 PHY522X_REG_WRITE((_unit), (_phy_ctrl), 0x0000, 0x1e (_val)) 225 #define MODIFY_PHY522X_AUX_MULTIPLE_PHYr(_unit, _phy_ctrl, _val, _mask) \ 226 PHY522X_REG_MODIFY((_unit), (_phy_ctrl), 0x0000, 0x1e, \ 227 (_val), (_mask)) 228 #define PHY522X_SUPER_ISOLATE_MODE (1<<3) 229 230 /* Auxiliary Status 4 Register (Shadow Addr 1eh) */ 231 232 /* Broadcom Test (Addr 1fh) */ 233 234 #endif /* _PHY522X_H_ */