hl65.h (1944306B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: hl65.h 8 * Purpose: Hyperlite/Hypercore driver header file, auto-generated. 9 */ 10 11 /*************************************************************************** 12 * Copyright (c) 1999-2008, Broadcom Corporation 13 * All Rights Reserved 14 * Confidential Property of Broadcom Corporation 15 * 16 * 17 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 18 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 19 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 20 * 21 * $brcm_Workfile: $ 22 * $brcm_Revision: $ 23 * $brcm_Date: $ 24 * 25 * Module Description: 26 * DO NOT EDIT THIS FILE DIRECTLY 27 * 28 * This module was generated magically with RDB from a source description 29 * file. You must edit the source file for changes to be made to this file. 30 * 31 * 32 * Date: Generated on Mon Sep 22 12:04:36 2008 33 * MD5 Checksum 70565ec876bdd0354d6a4398fcc61be3 34 * 35 * Compiled with: RDB Utility 5.0 36 * RDB Parser 3.0 37 * rdb2macro.pm 4.0 38 * Perl Interpreter 5.008008 39 * Operating System linux 40 * 41 * Spec Versions: aer 1 42 * combo 1 43 * dsc_1 1 44 * dsc_2 1 45 * dsc_3 1 46 * dsc_4 1 47 * ieee 1 48 * rx66 1 49 * tx66 1 50 * xgxs 1 51 * 52 * Revision History: 53 * 54 * $brcm_Log: $ 55 */ 56 57 #ifndef HC65_H__ 58 #define HC65_H__ 59 60 /** 61 * m = memory, c = core, r = register, f = field, d = data. 62 */ 63 #if !defined(GET_FIELD) && !defined(SET_FIELD) 64 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 65 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 66 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 67 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 68 69 #define GET_FIELD(m,c,r,f) \ 70 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 71 72 #define SET_FIELD(m,c,r,f,d) \ 73 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 74 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 75 ) 76 77 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 78 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 79 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 80 81 #endif /* GET & SET */ 82 83 /**************************************************************************** 84 * Core Enums. 85 */ 86 /**************************************************************************** 87 * Enums: combo_operationModes 88 */ 89 #define combo_operationModes_XGXS 0 90 #define combo_operationModes_XGXG_nCC 1 91 #define combo_operationModes_IndLane_OS5 5 92 #define combo_operationModes_Indlanes 6 93 #define combo_operationModes_PCI 7 94 #define combo_operationModes_XGXS_nLQ 8 95 #define combo_operationModes_XGXS_nLQnCC 9 96 #define combo_operationModes_PBypass 10 97 #define combo_operationModes_PBypass_nDSK 11 98 #define combo_operationModes_ComboCoreMode 12 99 #define combo_operationModes_Clocks_off 15 100 101 /**************************************************************************** 102 * Enums: combo_actualSpeeds4 103 */ 104 #define combo_actualSpeeds4_dr_10M 0 105 #define combo_actualSpeeds4_dr_100M 1 106 #define combo_actualSpeeds4_dr_1G 2 107 #define combo_actualSpeeds4_dr_2p5G 3 108 #define combo_actualSpeeds4_dr_5G_X4 4 109 #define combo_actualSpeeds4_dr_6G_X4 5 110 #define combo_actualSpeeds4_dr_10G_HiG 6 111 #define combo_actualSpeeds4_dr_10G_CX4 7 112 #define combo_actualSpeeds4_dr_12G_HiG 8 113 #define combo_actualSpeeds4_dr_12p5G_X4 9 114 #define combo_actualSpeeds4_dr_13G_X4 10 115 #define combo_actualSpeeds4_dr_15G_X4 11 116 #define combo_actualSpeeds4_dr_16G_X4 12 117 118 /**************************************************************************** 119 * Enums: combo_actualSpeeds5 120 */ 121 #define combo_actualSpeeds5_dr_10M 0 122 #define combo_actualSpeeds5_dr_100M 1 123 #define combo_actualSpeeds5_dr_1G 2 124 #define combo_actualSpeeds5_dr_2p5G 3 125 #define combo_actualSpeeds5_dr_5G_X4 4 126 #define combo_actualSpeeds5_dr_6G_X4 5 127 #define combo_actualSpeeds5_dr_10G_HiG 6 128 #define combo_actualSpeeds5_dr_10G_CX4 7 129 #define combo_actualSpeeds5_dr_12G_HiG 8 130 #define combo_actualSpeeds5_dr_12p5G_X4 9 131 #define combo_actualSpeeds5_dr_13G_X4 10 132 #define combo_actualSpeeds5_dr_15G_X4 11 133 #define combo_actualSpeeds5_dr_16G_X4 12 134 #define combo_actualSpeeds5_dr_5G 16 135 #define combo_actualSpeeds5_dr_6p4G 17 136 #define combo_actualSpeeds5_dr_20G_X4 18 137 #define combo_actualSpeeds5_dr_21G_X4 19 138 #define combo_actualSpeeds5_dr_25G_X4 20 139 140 /**************************************************************************** 141 * Enums: combo_actualSpeedsMisc1 142 */ 143 #define combo_actualSpeedsMisc1_dr_2500BRCM_X1 16 144 #define combo_actualSpeedsMisc1_dr_5000BRCM_X4 17 145 #define combo_actualSpeedsMisc1_dr_6000BRCM_X4 18 146 #define combo_actualSpeedsMisc1_dr_10GHiGig_X4 19 147 #define combo_actualSpeedsMisc1_dr_10GBASE_CX4 20 148 #define combo_actualSpeedsMisc1_dr_12GHiGig_X4 21 149 #define combo_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 150 #define combo_actualSpeedsMisc1_dr_13GHiGig_X4 23 151 #define combo_actualSpeedsMisc1_dr_15GHiGig_X4 24 152 #define combo_actualSpeedsMisc1_dr_16GHiGig_X4 25 153 #define combo_actualSpeedsMisc1_dr_5000BRCM_X1 26 154 #define combo_actualSpeedsMisc1_dr_6363BRCM_X1 27 155 #define combo_actualSpeedsMisc1_dr_20GHiGig_X4 28 156 #define combo_actualSpeedsMisc1_dr_21GHiGig_X4 29 157 #define combo_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 158 159 /**************************************************************************** 160 * Enums: combo_IndLaneModes 161 */ 162 #define combo_IndLaneModes_SWSDR_div2 0 163 #define combo_IndLaneModes_SWSDR_div1 1 164 #define combo_IndLaneModes_DWSDR_div2 2 165 #define combo_IndLaneModes_DWSDR_div1 3 166 167 /**************************************************************************** 168 * Enums: combo_prbsSelect 169 */ 170 #define combo_prbsSelect_prbs7 0 171 #define combo_prbsSelect_prbs15 1 172 #define combo_prbsSelect_prbs23 2 173 #define combo_prbsSelect_prbs31 3 174 175 /**************************************************************************** 176 * Enums: combo_vcoDivider 177 */ 178 #define combo_vcoDivider_div16 0 179 #define combo_vcoDivider_div20 1 180 #define combo_vcoDivider_div24 2 181 #define combo_vcoDivider_div26 3 182 #define combo_vcoDivider_div30 4 183 #define combo_vcoDivider_div32 5 184 #define combo_vcoDivider_div36 6 185 #define combo_vcoDivider_div40 7 186 #define combo_vcoDivider_div42 8 187 #define combo_vcoDivider_div48 9 188 #define combo_vcoDivider_div50 10 189 #define combo_vcoDivider_div52 11 190 #define combo_vcoDivider_div60 12 191 #define combo_vcoDivider_div64 13 192 193 /**************************************************************************** 194 * Enums: combo_refClkSelect 195 */ 196 #define combo_refClkSelect_clk_25MHz 0 197 #define combo_refClkSelect_clk_100MHz 1 198 #define combo_refClkSelect_clk_125MHz 2 199 #define combo_refClkSelect_clk_156p25MHz 3 200 #define combo_refClkSelect_clk_187p5MHz 4 201 202 /**************************************************************************** 203 * Enums: ieee_operationModes 204 */ 205 #define ieee_operationModes_XGXS 0 206 #define ieee_operationModes_XGXG_nCC 1 207 #define ieee_operationModes_IndLane_OS5 5 208 #define ieee_operationModes_Indlanes 6 209 #define ieee_operationModes_PCI 7 210 #define ieee_operationModes_XGXS_nLQ 8 211 #define ieee_operationModes_XGXS_nLQnCC 9 212 #define ieee_operationModes_PBypass 10 213 #define ieee_operationModes_PBypass_nDSK 11 214 #define ieee_operationModes_ComboCoreMode 12 215 #define ieee_operationModes_Clocks_off 15 216 217 /**************************************************************************** 218 * Enums: ieee_actualSpeeds4 219 */ 220 #define ieee_actualSpeeds4_dr_10M 0 221 #define ieee_actualSpeeds4_dr_100M 1 222 #define ieee_actualSpeeds4_dr_1G 2 223 #define ieee_actualSpeeds4_dr_2p5G 3 224 #define ieee_actualSpeeds4_dr_5G_X4 4 225 #define ieee_actualSpeeds4_dr_6G_X4 5 226 #define ieee_actualSpeeds4_dr_10G_HiG 6 227 #define ieee_actualSpeeds4_dr_10G_CX4 7 228 #define ieee_actualSpeeds4_dr_12G_HiG 8 229 #define ieee_actualSpeeds4_dr_12p5G_X4 9 230 #define ieee_actualSpeeds4_dr_13G_X4 10 231 #define ieee_actualSpeeds4_dr_15G_X4 11 232 #define ieee_actualSpeeds4_dr_16G_X4 12 233 234 /**************************************************************************** 235 * Enums: ieee_actualSpeeds5 236 */ 237 #define ieee_actualSpeeds5_dr_10M 0 238 #define ieee_actualSpeeds5_dr_100M 1 239 #define ieee_actualSpeeds5_dr_1G 2 240 #define ieee_actualSpeeds5_dr_2p5G 3 241 #define ieee_actualSpeeds5_dr_5G_X4 4 242 #define ieee_actualSpeeds5_dr_6G_X4 5 243 #define ieee_actualSpeeds5_dr_10G_HiG 6 244 #define ieee_actualSpeeds5_dr_10G_CX4 7 245 #define ieee_actualSpeeds5_dr_12G_HiG 8 246 #define ieee_actualSpeeds5_dr_12p5G_X4 9 247 #define ieee_actualSpeeds5_dr_13G_X4 10 248 #define ieee_actualSpeeds5_dr_15G_X4 11 249 #define ieee_actualSpeeds5_dr_16G_X4 12 250 #define ieee_actualSpeeds5_dr_5G 16 251 #define ieee_actualSpeeds5_dr_6p4G 17 252 #define ieee_actualSpeeds5_dr_20G_X4 18 253 #define ieee_actualSpeeds5_dr_21G_X4 19 254 #define ieee_actualSpeeds5_dr_25G_X4 20 255 256 /**************************************************************************** 257 * Enums: ieee_actualSpeedsMisc1 258 */ 259 #define ieee_actualSpeedsMisc1_dr_2500BRCM_X1 16 260 #define ieee_actualSpeedsMisc1_dr_5000BRCM_X4 17 261 #define ieee_actualSpeedsMisc1_dr_6000BRCM_X4 18 262 #define ieee_actualSpeedsMisc1_dr_10GHiGig_X4 19 263 #define ieee_actualSpeedsMisc1_dr_10GBASE_CX4 20 264 #define ieee_actualSpeedsMisc1_dr_12GHiGig_X4 21 265 #define ieee_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 266 #define ieee_actualSpeedsMisc1_dr_13GHiGig_X4 23 267 #define ieee_actualSpeedsMisc1_dr_15GHiGig_X4 24 268 #define ieee_actualSpeedsMisc1_dr_16GHiGig_X4 25 269 #define ieee_actualSpeedsMisc1_dr_5000BRCM_X1 26 270 #define ieee_actualSpeedsMisc1_dr_6363BRCM_X1 27 271 #define ieee_actualSpeedsMisc1_dr_20GHiGig_X4 28 272 #define ieee_actualSpeedsMisc1_dr_21GHiGig_X4 29 273 #define ieee_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 274 275 /**************************************************************************** 276 * Enums: ieee_IndLaneModes 277 */ 278 #define ieee_IndLaneModes_SWSDR_div2 0 279 #define ieee_IndLaneModes_SWSDR_div1 1 280 #define ieee_IndLaneModes_DWSDR_div2 2 281 #define ieee_IndLaneModes_DWSDR_div1 3 282 283 /**************************************************************************** 284 * Enums: ieee_prbsSelect 285 */ 286 #define ieee_prbsSelect_prbs7 0 287 #define ieee_prbsSelect_prbs15 1 288 #define ieee_prbsSelect_prbs23 2 289 #define ieee_prbsSelect_prbs31 3 290 291 /**************************************************************************** 292 * Enums: ieee_vcoDivider 293 */ 294 #define ieee_vcoDivider_div16 0 295 #define ieee_vcoDivider_div20 1 296 #define ieee_vcoDivider_div24 2 297 #define ieee_vcoDivider_div26 3 298 #define ieee_vcoDivider_div30 4 299 #define ieee_vcoDivider_div32 5 300 #define ieee_vcoDivider_div36 6 301 #define ieee_vcoDivider_div40 7 302 #define ieee_vcoDivider_div42 8 303 #define ieee_vcoDivider_div48 9 304 #define ieee_vcoDivider_div50 10 305 #define ieee_vcoDivider_div52 11 306 #define ieee_vcoDivider_div60 12 307 #define ieee_vcoDivider_div64 13 308 309 /**************************************************************************** 310 * Enums: ieee_refClkSelect 311 */ 312 #define ieee_refClkSelect_clk_25MHz 0 313 #define ieee_refClkSelect_clk_100MHz 1 314 #define ieee_refClkSelect_clk_125MHz 2 315 #define ieee_refClkSelect_clk_156p25MHz 3 316 #define ieee_refClkSelect_clk_187p5MHz 4 317 318 /**************************************************************************** 319 * Enums: xgxs_operationModes 320 */ 321 #define xgxs_operationModes_XGXS 0 322 #define xgxs_operationModes_XGXG_nCC 1 323 #define xgxs_operationModes_IndLane_OS5 5 324 #define xgxs_operationModes_Indlanes 6 325 #define xgxs_operationModes_PCI 7 326 #define xgxs_operationModes_XGXS_nLQ 8 327 #define xgxs_operationModes_XGXS_nLQnCC 9 328 #define xgxs_operationModes_PBypass 10 329 #define xgxs_operationModes_PBypass_nDSK 11 330 #define xgxs_operationModes_ComboCoreMode 12 331 #define xgxs_operationModes_Clocks_off 15 332 333 /**************************************************************************** 334 * Enums: xgxs_actualSpeeds4 335 */ 336 #define xgxs_actualSpeeds4_dr_10M 0 337 #define xgxs_actualSpeeds4_dr_100M 1 338 #define xgxs_actualSpeeds4_dr_1G 2 339 #define xgxs_actualSpeeds4_dr_2p5G 3 340 #define xgxs_actualSpeeds4_dr_5G_X4 4 341 #define xgxs_actualSpeeds4_dr_6G_X4 5 342 #define xgxs_actualSpeeds4_dr_10G_HiG 6 343 #define xgxs_actualSpeeds4_dr_10G_CX4 7 344 #define xgxs_actualSpeeds4_dr_12G_HiG 8 345 #define xgxs_actualSpeeds4_dr_12p5G_X4 9 346 #define xgxs_actualSpeeds4_dr_13G_X4 10 347 #define xgxs_actualSpeeds4_dr_15G_X4 11 348 #define xgxs_actualSpeeds4_dr_16G_X4 12 349 350 /**************************************************************************** 351 * Enums: xgxs_actualSpeeds5 352 */ 353 #define xgxs_actualSpeeds5_dr_10M 0 354 #define xgxs_actualSpeeds5_dr_100M 1 355 #define xgxs_actualSpeeds5_dr_1G 2 356 #define xgxs_actualSpeeds5_dr_2p5G 3 357 #define xgxs_actualSpeeds5_dr_5G_X4 4 358 #define xgxs_actualSpeeds5_dr_6G_X4 5 359 #define xgxs_actualSpeeds5_dr_10G_HiG 6 360 #define xgxs_actualSpeeds5_dr_10G_CX4 7 361 #define xgxs_actualSpeeds5_dr_12G_HiG 8 362 #define xgxs_actualSpeeds5_dr_12p5G_X4 9 363 #define xgxs_actualSpeeds5_dr_13G_X4 10 364 #define xgxs_actualSpeeds5_dr_15G_X4 11 365 #define xgxs_actualSpeeds5_dr_16G_X4 12 366 #define xgxs_actualSpeeds5_dr_5G 16 367 #define xgxs_actualSpeeds5_dr_6p4G 17 368 #define xgxs_actualSpeeds5_dr_20G_X4 18 369 #define xgxs_actualSpeeds5_dr_21G_X4 19 370 #define xgxs_actualSpeeds5_dr_25G_X4 20 371 372 /**************************************************************************** 373 * Enums: xgxs_actualSpeedsMisc1 374 */ 375 #define xgxs_actualSpeedsMisc1_dr_2500BRCM_X1 16 376 #define xgxs_actualSpeedsMisc1_dr_5000BRCM_X4 17 377 #define xgxs_actualSpeedsMisc1_dr_6000BRCM_X4 18 378 #define xgxs_actualSpeedsMisc1_dr_10GHiGig_X4 19 379 #define xgxs_actualSpeedsMisc1_dr_10GBASE_CX4 20 380 #define xgxs_actualSpeedsMisc1_dr_12GHiGig_X4 21 381 #define xgxs_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 382 #define xgxs_actualSpeedsMisc1_dr_13GHiGig_X4 23 383 #define xgxs_actualSpeedsMisc1_dr_15GHiGig_X4 24 384 #define xgxs_actualSpeedsMisc1_dr_16GHiGig_X4 25 385 #define xgxs_actualSpeedsMisc1_dr_5000BRCM_X1 26 386 #define xgxs_actualSpeedsMisc1_dr_6363BRCM_X1 27 387 #define xgxs_actualSpeedsMisc1_dr_20GHiGig_X4 28 388 #define xgxs_actualSpeedsMisc1_dr_21GHiGig_X4 29 389 #define xgxs_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 390 391 /**************************************************************************** 392 * Enums: xgxs_IndLaneModes 393 */ 394 #define xgxs_IndLaneModes_SWSDR_div2 0 395 #define xgxs_IndLaneModes_SWSDR_div1 1 396 #define xgxs_IndLaneModes_DWSDR_div2 2 397 #define xgxs_IndLaneModes_DWSDR_div1 3 398 399 /**************************************************************************** 400 * Enums: xgxs_prbsSelect 401 */ 402 #define xgxs_prbsSelect_prbs7 0 403 #define xgxs_prbsSelect_prbs15 1 404 #define xgxs_prbsSelect_prbs23 2 405 #define xgxs_prbsSelect_prbs31 3 406 407 /**************************************************************************** 408 * Enums: xgxs_vcoDivider 409 */ 410 #define xgxs_vcoDivider_div16 0 411 #define xgxs_vcoDivider_div20 1 412 #define xgxs_vcoDivider_div24 2 413 #define xgxs_vcoDivider_div26 3 414 #define xgxs_vcoDivider_div30 4 415 #define xgxs_vcoDivider_div32 5 416 #define xgxs_vcoDivider_div36 6 417 #define xgxs_vcoDivider_div40 7 418 #define xgxs_vcoDivider_div42 8 419 #define xgxs_vcoDivider_div48 9 420 #define xgxs_vcoDivider_div50 10 421 #define xgxs_vcoDivider_div52 11 422 #define xgxs_vcoDivider_div60 12 423 #define xgxs_vcoDivider_div64 13 424 425 /**************************************************************************** 426 * Enums: xgxs_refClkSelect 427 */ 428 #define xgxs_refClkSelect_clk_25MHz 0 429 #define xgxs_refClkSelect_clk_100MHz 1 430 #define xgxs_refClkSelect_clk_125MHz 2 431 #define xgxs_refClkSelect_clk_156p25MHz 3 432 #define xgxs_refClkSelect_clk_187p5MHz 4 433 434 /**************************************************************************** 435 * Hypercore_IEEE_CL22_ieee0Blk 436 */ 437 438 /* IEEE MII control register */ 439 #define READ_HL65_IEEE0BLK_MIICNTLr(_unit, _pc, _val) \ 440 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val)) 441 #define WRITE_HL65_IEEE0BLK_MIICNTLr(_unit, _pc, _val) \ 442 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val)) 443 #define MODIFY_HL65_IEEE0BLK_MIICNTLr(_unit, _pc, _val, _mask) \ 444 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask)) 445 446 /* IEEE MII status register */ 447 #define READ_HL65_IEEE0BLK_MIISTATr(_unit, _pc, _val) \ 448 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000001, (_val)) 449 #define WRITE_HL65_IEEE0BLK_MIISTATr(_unit, _pc, _val) \ 450 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000001, (_val)) 451 #define MODIFY_HL65_IEEE0BLK_MIISTATr(_unit, _pc, _val, _mask) \ 452 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000001, (_val), (_mask)) 453 454 /* IEEE phy ID LSByte register */ 455 #define READ_HL65_IEEE0BLK_ID1r(_unit, _pc, _val) \ 456 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000002, (_val)) 457 #define WRITE_HL65_IEEE0BLK_ID1r(_unit, _pc, _val) \ 458 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000002, (_val)) 459 #define MODIFY_HL65_IEEE0BLK_ID1r(_unit, _pc, _val, _mask) \ 460 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000002, (_val), (_mask)) 461 462 /* IEEE phy ID MSByte register */ 463 #define READ_HL65_IEEE0BLK_ID2r(_unit, _pc, _val) \ 464 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000003, (_val)) 465 #define WRITE_HL65_IEEE0BLK_ID2r(_unit, _pc, _val) \ 466 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000003, (_val)) 467 #define MODIFY_HL65_IEEE0BLK_ID2r(_unit, _pc, _val, _mask) \ 468 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000003, (_val), (_mask)) 469 470 /* IEEE auto-negotiation advertised abilities register */ 471 #define READ_HL65_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val) \ 472 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000004, (_val)) 473 #define WRITE_HL65_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val) \ 474 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000004, (_val)) 475 #define MODIFY_HL65_IEEE0BLK_AUTONEGADVr(_unit, _pc, _val, _mask) \ 476 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000004, (_val), (_mask)) 477 478 /* IEEE auto-negotiation link partner abilities register */ 479 #define READ_HL65_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val) \ 480 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000005, (_val)) 481 #define WRITE_HL65_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val) \ 482 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000005, (_val)) 483 #define MODIFY_HL65_IEEE0BLK_AUTONEGLPABILr(_unit, _pc, _val, _mask) \ 484 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000005, (_val), (_mask)) 485 486 /* IEEE auto-negotiation expansion register */ 487 #define READ_HL65_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val) \ 488 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000006, (_val)) 489 #define WRITE_HL65_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val) \ 490 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000006, (_val)) 491 #define MODIFY_HL65_IEEE0BLK_AUTONEGEXPr(_unit, _pc, _val, _mask) \ 492 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000006, (_val), (_mask)) 493 494 /* IEEE auto-negotiation next page register */ 495 #define READ_HL65_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val) \ 496 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000007, (_val)) 497 #define WRITE_HL65_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val) \ 498 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000007, (_val)) 499 #define MODIFY_HL65_IEEE0BLK_AUTONEGNPr(_unit, _pc, _val, _mask) \ 500 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000007, (_val), (_mask)) 501 502 /* IEEE auto-negotiation link partner next page register */ 503 #define READ_HL65_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val) \ 504 HL65_REG_READ((_unit), (_pc), 0x00, 0x00000008, (_val)) 505 #define WRITE_HL65_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val) \ 506 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00000008, (_val)) 507 #define MODIFY_HL65_IEEE0BLK_AUTONEGLPABIL2r(_unit, _pc, _val, _mask) \ 508 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00000008, (_val), (_mask)) 509 510 /* IEEE MII extended status register */ 511 #define READ_HL65_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val) \ 512 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000000f, (_val)) 513 #define WRITE_HL65_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val) \ 514 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000000f, (_val)) 515 #define MODIFY_HL65_IEEE0BLK_MIIEXTSTATr(_unit, _pc, _val, _mask) \ 516 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000000f, (_val), (_mask)) 517 518 519 /**************************************************************************** 520 * Hypercore_USER_XgxsBlk0 521 */ 522 523 /* XGXS control register */ 524 #define READ_HL65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 525 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008000, (_val)) 526 #define WRITE_HL65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val) \ 527 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008000, (_val)) 528 #define MODIFY_HL65_XGXSBLK0_XGXSCONTROLr(_unit, _pc, _val, _mask) \ 529 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008000, (_val), (_mask)) 530 531 /* XGXS status register */ 532 #define READ_HL65_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 533 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008001, (_val)) 534 #define WRITE_HL65_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val) \ 535 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008001, (_val)) 536 #define MODIFY_HL65_XGXSBLK0_XGXSSTATUSr(_unit, _pc, _val, _mask) \ 537 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008001, (_val), (_mask)) 538 539 /* XGMII idle control character register */ 540 #define READ_HL65_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \ 541 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008002, (_val)) 542 #define WRITE_HL65_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val) \ 543 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008002, (_val)) 544 #define MODIFY_HL65_XGXSBLK0_XGMIIIDLEr(_unit, _pc, _val, _mask) \ 545 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008002, (_val), (_mask)) 546 547 /* XGMII sync control character register */ 548 #define READ_HL65_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \ 549 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008003, (_val)) 550 #define WRITE_HL65_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val) \ 551 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008003, (_val)) 552 #define MODIFY_HL65_XGXSBLK0_XGMIISYNCr(_unit, _pc, _val, _mask) \ 553 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008003, (_val), (_mask)) 554 555 /* XGMII skip control character register */ 556 #define READ_HL65_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \ 557 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008004, (_val)) 558 #define WRITE_HL65_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val) \ 559 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008004, (_val)) 560 #define MODIFY_HL65_XGXSBLK0_XGMIISKIPr(_unit, _pc, _val, _mask) \ 561 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008004, (_val), (_mask)) 562 563 /* XGMII sop & eop control character register */ 564 #define READ_HL65_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \ 565 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008005, (_val)) 566 #define WRITE_HL65_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val) \ 567 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008005, (_val)) 568 #define MODIFY_HL65_XGXSBLK0_XGMIISOPEOPr(_unit, _pc, _val, _mask) \ 569 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008005, (_val), (_mask)) 570 571 /* XGMII alignment & eror control character register */ 572 #define READ_HL65_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \ 573 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008006, (_val)) 574 #define WRITE_HL65_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val) \ 575 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008006, (_val)) 576 #define MODIFY_HL65_XGXSBLK0_XGMIIALIGNr(_unit, _pc, _val, _mask) \ 577 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008006, (_val), (_mask)) 578 579 /* XGMII receive control register */ 580 #define READ_HL65_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \ 581 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008007, (_val)) 582 #define WRITE_HL65_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val) \ 583 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008007, (_val)) 584 #define MODIFY_HL65_XGXSBLK0_XGMIIRCONTROLr(_unit, _pc, _val, _mask) \ 585 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008007, (_val), (_mask)) 586 587 /* XGMII transmit control register */ 588 #define READ_HL65_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \ 589 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008008, (_val)) 590 #define WRITE_HL65_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val) \ 591 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008008, (_val)) 592 #define MODIFY_HL65_XGXSBLK0_XGMIITCONTROLr(_unit, _pc, _val, _mask) \ 593 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008008, (_val), (_mask)) 594 595 /* XGMII ||A|| minimum swap spacing */ 596 #define READ_HL65_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \ 597 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008009, (_val)) 598 #define WRITE_HL65_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val) \ 599 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008009, (_val)) 600 #define MODIFY_HL65_XGXSBLK0_XGMIISWAPr(_unit, _pc, _val, _mask) \ 601 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008009, (_val), (_mask)) 602 603 /* LSS information byte register */ 604 #define READ_HL65_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \ 605 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800a, (_val)) 606 #define WRITE_HL65_XGXSBLK0_LSSLSIDr(_unit, _pc, _val) \ 607 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800a, (_val)) 608 #define MODIFY_HL65_XGXSBLK0_LSSLSIDr(_unit, _pc, _val, _mask) \ 609 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800a, (_val), (_mask)) 610 611 /* LSS transmit information byte register */ 612 #define READ_HL65_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \ 613 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800b, (_val)) 614 #define WRITE_HL65_XGXSBLK0_LSSTINFOr(_unit, _pc, _val) \ 615 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800b, (_val)) 616 #define MODIFY_HL65_XGXSBLK0_LSSTINFOr(_unit, _pc, _val, _mask) \ 617 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800b, (_val), (_mask)) 618 619 /* LSS receive information byte register */ 620 #define READ_HL65_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \ 621 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800c, (_val)) 622 #define WRITE_HL65_XGXSBLK0_LSSRINFOr(_unit, _pc, _val) \ 623 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800c, (_val)) 624 #define MODIFY_HL65_XGXSBLK0_LSSRINFOr(_unit, _pc, _val, _mask) \ 625 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800c, (_val), (_mask)) 626 627 /* MMD select register */ 628 #define READ_HL65_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \ 629 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800d, (_val)) 630 #define WRITE_HL65_XGXSBLK0_MMDSELECTr(_unit, _pc, _val) \ 631 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800d, (_val)) 632 #define MODIFY_HL65_XGXSBLK0_MMDSELECTr(_unit, _pc, _val, _mask) \ 633 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800d, (_val), (_mask)) 634 635 /* Miscellaneous control 1 register */ 636 #define READ_HL65_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 637 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800e, (_val)) 638 #define WRITE_HL65_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val) \ 639 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800e, (_val)) 640 #define MODIFY_HL65_XGXSBLK0_MISCCONTROL1r(_unit, _pc, _val, _mask) \ 641 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800e, (_val), (_mask)) 642 643 /* Block Address register */ 644 #define READ_HL65_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \ 645 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000800f, (_val)) 646 #define WRITE_HL65_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val) \ 647 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000800f, (_val)) 648 #define MODIFY_HL65_XGXSBLK0_BLOCKADDRESSr(_unit, _pc, _val, _mask) \ 649 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000800f, (_val), (_mask)) 650 651 652 /**************************************************************************** 653 * Hypercore_USER_XgxsBlk1 654 */ 655 656 /* Lane deskew register */ 657 #define READ_HL65_XGXSBLK1_DESKEWr(_unit, _pc, _val) \ 658 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008010, (_val)) 659 #define WRITE_HL65_XGXSBLK1_DESKEWr(_unit, _pc, _val) \ 660 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008010, (_val)) 661 #define MODIFY_HL65_XGXSBLK1_DESKEWr(_unit, _pc, _val, _mask) \ 662 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008010, (_val), (_mask)) 663 664 /* Link ||A|| column timeout value register */ 665 #define READ_HL65_XGXSBLK1_LINKr(_unit, _pc, _val) \ 666 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008011, (_val)) 667 #define WRITE_HL65_XGXSBLK1_LINKr(_unit, _pc, _val) \ 668 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008011, (_val)) 669 #define MODIFY_HL65_XGXSBLK1_LINKr(_unit, _pc, _val, _mask) \ 670 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008011, (_val), (_mask)) 671 672 /* Receive test control register */ 673 #define READ_HL65_XGXSBLK1_TESTRXr(_unit, _pc, _val) \ 674 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008012, (_val)) 675 #define WRITE_HL65_XGXSBLK1_TESTRXr(_unit, _pc, _val) \ 676 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008012, (_val)) 677 #define MODIFY_HL65_XGXSBLK1_TESTRXr(_unit, _pc, _val, _mask) \ 678 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008012, (_val), (_mask)) 679 680 /* Transmit test control register */ 681 #define READ_HL65_XGXSBLK1_TESTTXr(_unit, _pc, _val) \ 682 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008013, (_val)) 683 #define WRITE_HL65_XGXSBLK1_TESTTXr(_unit, _pc, _val) \ 684 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008013, (_val)) 685 #define MODIFY_HL65_XGXSBLK1_TESTTXr(_unit, _pc, _val, _mask) \ 686 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008013, (_val), (_mask)) 687 688 /* XGXS test control register */ 689 #define READ_HL65_XGXSBLK1_TESTXGr(_unit, _pc, _val) \ 690 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008014, (_val)) 691 #define WRITE_HL65_XGXSBLK1_TESTXGr(_unit, _pc, _val) \ 692 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008014, (_val)) 693 #define MODIFY_HL65_XGXSBLK1_TESTXGr(_unit, _pc, _val, _mask) \ 694 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008014, (_val), (_mask)) 695 696 /* Lane control 0 register */ 697 #define READ_HL65_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \ 698 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008015, (_val)) 699 #define WRITE_HL65_XGXSBLK1_LANECTRL0r(_unit, _pc, _val) \ 700 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008015, (_val)) 701 #define MODIFY_HL65_XGXSBLK1_LANECTRL0r(_unit, _pc, _val, _mask) \ 702 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008015, (_val), (_mask)) 703 704 /* Lane control 1 register */ 705 #define READ_HL65_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \ 706 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008016, (_val)) 707 #define WRITE_HL65_XGXSBLK1_LANECTRL1r(_unit, _pc, _val) \ 708 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008016, (_val)) 709 #define MODIFY_HL65_XGXSBLK1_LANECTRL1r(_unit, _pc, _val, _mask) \ 710 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008016, (_val), (_mask)) 711 712 /* Lane control 2 register */ 713 #define READ_HL65_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \ 714 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008017, (_val)) 715 #define WRITE_HL65_XGXSBLK1_LANECTRL2r(_unit, _pc, _val) \ 716 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008017, (_val)) 717 #define MODIFY_HL65_XGXSBLK1_LANECTRL2r(_unit, _pc, _val, _mask) \ 718 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008017, (_val), (_mask)) 719 720 /* Lane control 3 register */ 721 #define READ_HL65_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \ 722 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008018, (_val)) 723 #define WRITE_HL65_XGXSBLK1_LANECTRL3r(_unit, _pc, _val) \ 724 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008018, (_val)) 725 #define MODIFY_HL65_XGXSBLK1_LANECTRL3r(_unit, _pc, _val, _mask) \ 726 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008018, (_val), (_mask)) 727 728 /* Lane PRBS control register */ 729 #define READ_HL65_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \ 730 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008019, (_val)) 731 #define WRITE_HL65_XGXSBLK1_LANEPRBSr(_unit, _pc, _val) \ 732 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008019, (_val)) 733 #define MODIFY_HL65_XGXSBLK1_LANEPRBSr(_unit, _pc, _val, _mask) \ 734 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008019, (_val), (_mask)) 735 736 /* Lane test control register */ 737 #define READ_HL65_XGXSBLK1_LANETESTr(_unit, _pc, _val) \ 738 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801a, (_val)) 739 #define WRITE_HL65_XGXSBLK1_LANETESTr(_unit, _pc, _val) \ 740 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801a, (_val)) 741 #define MODIFY_HL65_XGXSBLK1_LANETESTr(_unit, _pc, _val, _mask) \ 742 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801a, (_val), (_mask)) 743 744 /* LSS, ||Q|| column count register */ 745 #define READ_HL65_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \ 746 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801b, (_val)) 747 #define WRITE_HL65_XGXSBLK1_LSSREVNTr(_unit, _pc, _val) \ 748 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801b, (_val)) 749 #define MODIFY_HL65_XGXSBLK1_LSSREVNTr(_unit, _pc, _val, _mask) \ 750 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801b, (_val), (_mask)) 751 752 /* Lane deskew event count register */ 753 #define READ_HL65_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \ 754 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801c, (_val)) 755 #define WRITE_HL65_XGXSBLK1_DSKEVNTr(_unit, _pc, _val) \ 756 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801c, (_val)) 757 #define MODIFY_HL65_XGXSBLK1_DSKEVNTr(_unit, _pc, _val, _mask) \ 758 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801c, (_val), (_mask)) 759 760 /* Bad ||A|| column count register */ 761 #define READ_HL65_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \ 762 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801d, (_val)) 763 #define WRITE_HL65_XGXSBLK1_AERREVNTr(_unit, _pc, _val) \ 764 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801d, (_val)) 765 #define MODIFY_HL65_XGXSBLK1_AERREVNTr(_unit, _pc, _val, _mask) \ 766 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801d, (_val), (_mask)) 767 768 /* Clock compensation event count register */ 769 #define READ_HL65_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \ 770 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000801e, (_val)) 771 #define WRITE_HL65_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val) \ 772 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000801e, (_val)) 773 #define MODIFY_HL65_XGXSBLK1_CKCMPEVNTr(_unit, _pc, _val, _mask) \ 774 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000801e, (_val), (_mask)) 775 776 777 /**************************************************************************** 778 * Hypercore_USER_TxBert 779 */ 780 781 /* Tx Bert control register */ 782 #define READ_HL65_TXBERT_TXBERTCTRLr(_unit, _pc, _val) \ 783 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008020, (_val)) 784 #define WRITE_HL65_TXBERT_TXBERTCTRLr(_unit, _pc, _val) \ 785 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008020, (_val)) 786 #define MODIFY_HL65_TXBERT_TXBERTCTRLr(_unit, _pc, _val, _mask) \ 787 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008020, (_val), (_mask)) 788 789 /* Tx Bert SOP, EOP definition register */ 790 #define READ_HL65_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val) \ 791 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008021, (_val)) 792 #define WRITE_HL65_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val) \ 793 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008021, (_val)) 794 #define MODIFY_HL65_TXBERT_TXBERTSOPEOPr(_unit, _pc, _val, _mask) \ 795 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008021, (_val), (_mask)) 796 797 /* Packet size configuration 0 register */ 798 #define READ_HL65_TXBERT_TXBERTSIZE0r(_unit, _pc, _val) \ 799 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008022, (_val)) 800 #define WRITE_HL65_TXBERT_TXBERTSIZE0r(_unit, _pc, _val) \ 801 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008022, (_val)) 802 #define MODIFY_HL65_TXBERT_TXBERTSIZE0r(_unit, _pc, _val, _mask) \ 803 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008022, (_val), (_mask)) 804 805 /* Packet size configuration 1 register */ 806 #define READ_HL65_TXBERT_TXBERTSIZE1r(_unit, _pc, _val) \ 807 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008023, (_val)) 808 #define WRITE_HL65_TXBERT_TXBERTSIZE1r(_unit, _pc, _val) \ 809 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008023, (_val)) 810 #define MODIFY_HL65_TXBERT_TXBERTSIZE1r(_unit, _pc, _val, _mask) \ 811 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008023, (_val), (_mask)) 812 813 /* Packet size configuration 2 register */ 814 #define READ_HL65_TXBERT_TXBERTSIZE2r(_unit, _pc, _val) \ 815 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008024, (_val)) 816 #define WRITE_HL65_TXBERT_TXBERTSIZE2r(_unit, _pc, _val) \ 817 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008024, (_val)) 818 #define MODIFY_HL65_TXBERT_TXBERTSIZE2r(_unit, _pc, _val, _mask) \ 819 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008024, (_val), (_mask)) 820 821 /* IPG 0 definition register */ 822 #define READ_HL65_TXBERT_TXBERTIPG0r(_unit, _pc, _val) \ 823 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008025, (_val)) 824 #define WRITE_HL65_TXBERT_TXBERTIPG0r(_unit, _pc, _val) \ 825 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008025, (_val)) 826 #define MODIFY_HL65_TXBERT_TXBERTIPG0r(_unit, _pc, _val, _mask) \ 827 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008025, (_val), (_mask)) 828 829 /* IPG 1 definition register */ 830 #define READ_HL65_TXBERT_TXBERTIPG1r(_unit, _pc, _val) \ 831 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008026, (_val)) 832 #define WRITE_HL65_TXBERT_TXBERTIPG1r(_unit, _pc, _val) \ 833 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008026, (_val)) 834 #define MODIFY_HL65_TXBERT_TXBERTIPG1r(_unit, _pc, _val, _mask) \ 835 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008026, (_val), (_mask)) 836 837 /* Transmitted byte count upper 16 bits register */ 838 #define READ_HL65_TXBERT_TXBERTBYTEUr(_unit, _pc, _val) \ 839 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008027, (_val)) 840 #define WRITE_HL65_TXBERT_TXBERTBYTEUr(_unit, _pc, _val) \ 841 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008027, (_val)) 842 #define MODIFY_HL65_TXBERT_TXBERTBYTEUr(_unit, _pc, _val, _mask) \ 843 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008027, (_val), (_mask)) 844 845 /* Transmitted byte count lower 16 bits register */ 846 #define READ_HL65_TXBERT_TXBERTBYTELr(_unit, _pc, _val) \ 847 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008028, (_val)) 848 #define WRITE_HL65_TXBERT_TXBERTBYTELr(_unit, _pc, _val) \ 849 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008028, (_val)) 850 #define MODIFY_HL65_TXBERT_TXBERTBYTELr(_unit, _pc, _val, _mask) \ 851 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008028, (_val), (_mask)) 852 853 /* Transmitted packet count upper 16 bits register */ 854 #define READ_HL65_TXBERT_TXBERTPACKETUr(_unit, _pc, _val) \ 855 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008029, (_val)) 856 #define WRITE_HL65_TXBERT_TXBERTPACKETUr(_unit, _pc, _val) \ 857 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008029, (_val)) 858 #define MODIFY_HL65_TXBERT_TXBERTPACKETUr(_unit, _pc, _val, _mask) \ 859 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008029, (_val), (_mask)) 860 861 /* Transmitted packet count lower 16 bits register */ 862 #define READ_HL65_TXBERT_TXBERTPACKETLr(_unit, _pc, _val) \ 863 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000802a, (_val)) 864 #define WRITE_HL65_TXBERT_TXBERTPACKETLr(_unit, _pc, _val) \ 865 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000802a, (_val)) 866 #define MODIFY_HL65_TXBERT_TXBERTPACKETLr(_unit, _pc, _val, _mask) \ 867 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000802a, (_val), (_mask)) 868 869 870 /**************************************************************************** 871 * Hypercore_USER_RxBert 872 */ 873 874 /* Rx Bert control register */ 875 #define READ_HL65_RXBERT_RXBERTCTRLr(_unit, _pc, _val) \ 876 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008030, (_val)) 877 #define WRITE_HL65_RXBERT_RXBERTCTRLr(_unit, _pc, _val) \ 878 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008030, (_val)) 879 #define MODIFY_HL65_RXBERT_RXBERTCTRLr(_unit, _pc, _val, _mask) \ 880 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008030, (_val), (_mask)) 881 882 /* Rx Bert SOP, EOP definition register */ 883 #define READ_HL65_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val) \ 884 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008031, (_val)) 885 #define WRITE_HL65_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val) \ 886 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008031, (_val)) 887 #define MODIFY_HL65_RXBERT_RXBERTSOPEOPr(_unit, _pc, _val, _mask) \ 888 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008031, (_val), (_mask)) 889 890 /* Received byte count upper 16 bits register */ 891 #define READ_HL65_RXBERT_RXBERTBYTEUr(_unit, _pc, _val) \ 892 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008037, (_val)) 893 #define WRITE_HL65_RXBERT_RXBERTBYTEUr(_unit, _pc, _val) \ 894 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008037, (_val)) 895 #define MODIFY_HL65_RXBERT_RXBERTBYTEUr(_unit, _pc, _val, _mask) \ 896 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008037, (_val), (_mask)) 897 898 /* Received bytes count lower 16 bits register */ 899 #define READ_HL65_RXBERT_RXBERTBYTELr(_unit, _pc, _val) \ 900 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008038, (_val)) 901 #define WRITE_HL65_RXBERT_RXBERTBYTELr(_unit, _pc, _val) \ 902 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008038, (_val)) 903 #define MODIFY_HL65_RXBERT_RXBERTBYTELr(_unit, _pc, _val, _mask) \ 904 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008038, (_val), (_mask)) 905 906 /* Received packet count upper 16 bits register */ 907 #define READ_HL65_RXBERT_RXBERTPACKETUr(_unit, _pc, _val) \ 908 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008039, (_val)) 909 #define WRITE_HL65_RXBERT_RXBERTPACKETUr(_unit, _pc, _val) \ 910 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008039, (_val)) 911 #define MODIFY_HL65_RXBERT_RXBERTPACKETUr(_unit, _pc, _val, _mask) \ 912 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008039, (_val), (_mask)) 913 914 /* Received packet count lower 16 bits register */ 915 #define READ_HL65_RXBERT_RXBERTPACKETLr(_unit, _pc, _val) \ 916 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803a, (_val)) 917 #define WRITE_HL65_RXBERT_RXBERTPACKETLr(_unit, _pc, _val) \ 918 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803a, (_val)) 919 #define MODIFY_HL65_RXBERT_RXBERTPACKETLr(_unit, _pc, _val, _mask) \ 920 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803a, (_val), (_mask)) 921 922 /* Received bits error count */ 923 #define READ_HL65_RXBERT_RXBERTBITERRr(_unit, _pc, _val) \ 924 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803b, (_val)) 925 #define WRITE_HL65_RXBERT_RXBERTBITERRr(_unit, _pc, _val) \ 926 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803b, (_val)) 927 #define MODIFY_HL65_RXBERT_RXBERTBITERRr(_unit, _pc, _val, _mask) \ 928 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803b, (_val), (_mask)) 929 930 /* Received bytes error count */ 931 #define READ_HL65_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val) \ 932 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803c, (_val)) 933 #define WRITE_HL65_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val) \ 934 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803c, (_val)) 935 #define MODIFY_HL65_RXBERT_RXBERTBYTEERRr(_unit, _pc, _val, _mask) \ 936 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803c, (_val), (_mask)) 937 938 /* Received packets error count */ 939 #define READ_HL65_RXBERT_RXBERTPKTERRr(_unit, _pc, _val) \ 940 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803d, (_val)) 941 #define WRITE_HL65_RXBERT_RXBERTPKTERRr(_unit, _pc, _val) \ 942 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803d, (_val)) 943 #define MODIFY_HL65_RXBERT_RXBERTPKTERRr(_unit, _pc, _val, _mask) \ 944 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803d, (_val), (_mask)) 945 946 /* Receive Status */ 947 #define READ_HL65_RXBERT_RXBERTSTATUSr(_unit, _pc, _val) \ 948 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000803e, (_val)) 949 #define WRITE_HL65_RXBERT_RXBERTSTATUSr(_unit, _pc, _val) \ 950 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000803e, (_val)) 951 #define MODIFY_HL65_RXBERT_RXBERTSTATUSr(_unit, _pc, _val, _mask) \ 952 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000803e, (_val), (_mask)) 953 954 955 /**************************************************************************** 956 * Hypercore_USER_TxPll 957 */ 958 959 /* PLL status register */ 960 #define READ_HL65_TXPLL_ANAPLLSTATUSr(_unit, _pc, _val) \ 961 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008050, (_val)) 962 #define WRITE_HL65_TXPLL_ANAPLLSTATUSr(_unit, _pc, _val) \ 963 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008050, (_val)) 964 #define MODIFY_HL65_TXPLL_ANAPLLSTATUSr(_unit, _pc, _val, _mask) \ 965 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008050, (_val), (_mask)) 966 967 /* PLL control register */ 968 #define READ_HL65_TXPLL_ANAPLLCONTROLr(_unit, _pc, _val) \ 969 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008051, (_val)) 970 #define WRITE_HL65_TXPLL_ANAPLLCONTROLr(_unit, _pc, _val) \ 971 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008051, (_val)) 972 #define MODIFY_HL65_TXPLL_ANAPLLCONTROLr(_unit, _pc, _val, _mask) \ 973 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008051, (_val), (_mask)) 974 975 /* PLL start up state machine vco timers */ 976 #define READ_HL65_TXPLL_ANAPLLTIMER1r(_unit, _pc, _val) \ 977 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008052, (_val)) 978 #define WRITE_HL65_TXPLL_ANAPLLTIMER1r(_unit, _pc, _val) \ 979 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008052, (_val)) 980 #define MODIFY_HL65_TXPLL_ANAPLLTIMER1r(_unit, _pc, _val, _mask) \ 981 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008052, (_val), (_mask)) 982 983 /* PLL start up state machine retry timer */ 984 #define READ_HL65_TXPLL_ANAPLLTIMER2r(_unit, _pc, _val) \ 985 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008053, (_val)) 986 #define WRITE_HL65_TXPLL_ANAPLLTIMER2r(_unit, _pc, _val) \ 987 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008053, (_val)) 988 #define MODIFY_HL65_TXPLL_ANAPLLTIMER2r(_unit, _pc, _val, _mask) \ 989 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008053, (_val), (_mask)) 990 991 /* PLL start up state machine freq. detect timer */ 992 #define READ_HL65_TXPLL_ANAPLLTIMER3r(_unit, _pc, _val) \ 993 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008054, (_val)) 994 #define WRITE_HL65_TXPLL_ANAPLLTIMER3r(_unit, _pc, _val) \ 995 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008054, (_val)) 996 #define MODIFY_HL65_TXPLL_ANAPLLTIMER3r(_unit, _pc, _val, _mask) \ 997 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008054, (_val), (_mask)) 998 999 /* PLL vco range control state machine */ 1000 #define READ_HL65_TXPLL_ANACAPCONTROLr(_unit, _pc, _val) \ 1001 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008055, (_val)) 1002 #define WRITE_HL65_TXPLL_ANACAPCONTROLr(_unit, _pc, _val) \ 1003 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008055, (_val)) 1004 #define MODIFY_HL65_TXPLL_ANACAPCONTROLr(_unit, _pc, _val, _mask) \ 1005 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008055, (_val), (_mask)) 1006 1007 /* Frequency detector control */ 1008 #define READ_HL65_TXPLL_ANAFREQDETCNTRr(_unit, _pc, _val) \ 1009 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008057, (_val)) 1010 #define WRITE_HL65_TXPLL_ANAFREQDETCNTRr(_unit, _pc, _val) \ 1011 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008057, (_val)) 1012 #define MODIFY_HL65_TXPLL_ANAFREQDETCNTRr(_unit, _pc, _val, _mask) \ 1013 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008057, (_val), (_mask)) 1014 1015 /* PLL analog status */ 1016 #define READ_HL65_TXPLL_ANAPLLASTATUS1r(_unit, _pc, _val) \ 1017 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008058, (_val)) 1018 #define WRITE_HL65_TXPLL_ANAPLLASTATUS1r(_unit, _pc, _val) \ 1019 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008058, (_val)) 1020 #define MODIFY_HL65_TXPLL_ANAPLLASTATUS1r(_unit, _pc, _val, _mask) \ 1021 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008058, (_val), (_mask)) 1022 1023 /* PLL analog controls */ 1024 #define READ_HL65_TXPLL_ANAPLLACONTROL0r(_unit, _pc, _val) \ 1025 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805a, (_val)) 1026 #define WRITE_HL65_TXPLL_ANAPLLACONTROL0r(_unit, _pc, _val) \ 1027 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805a, (_val)) 1028 #define MODIFY_HL65_TXPLL_ANAPLLACONTROL0r(_unit, _pc, _val, _mask) \ 1029 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805a, (_val), (_mask)) 1030 1031 /* PLL analog controls */ 1032 #define READ_HL65_TXPLL_ANAPLLACONTROL1r(_unit, _pc, _val) \ 1033 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805b, (_val)) 1034 #define WRITE_HL65_TXPLL_ANAPLLACONTROL1r(_unit, _pc, _val) \ 1035 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805b, (_val)) 1036 #define MODIFY_HL65_TXPLL_ANAPLLACONTROL1r(_unit, _pc, _val, _mask) \ 1037 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805b, (_val), (_mask)) 1038 1039 /* PLL analog controls */ 1040 #define READ_HL65_TXPLL_ANAPLLACONTROL2r(_unit, _pc, _val) \ 1041 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805c, (_val)) 1042 #define WRITE_HL65_TXPLL_ANAPLLACONTROL2r(_unit, _pc, _val) \ 1043 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805c, (_val)) 1044 #define MODIFY_HL65_TXPLL_ANAPLLACONTROL2r(_unit, _pc, _val, _mask) \ 1045 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805c, (_val), (_mask)) 1046 1047 /* PLL analog controls */ 1048 #define READ_HL65_TXPLL_ANAPLLACONTROL3r(_unit, _pc, _val) \ 1049 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805d, (_val)) 1050 #define WRITE_HL65_TXPLL_ANAPLLACONTROL3r(_unit, _pc, _val) \ 1051 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805d, (_val)) 1052 #define MODIFY_HL65_TXPLL_ANAPLLACONTROL3r(_unit, _pc, _val, _mask) \ 1053 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805d, (_val), (_mask)) 1054 1055 /* PLL analog controls */ 1056 #define READ_HL65_TXPLL_ANAPLLACONTROL4r(_unit, _pc, _val) \ 1057 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000805e, (_val)) 1058 #define WRITE_HL65_TXPLL_ANAPLLACONTROL4r(_unit, _pc, _val) \ 1059 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000805e, (_val)) 1060 #define MODIFY_HL65_TXPLL_ANAPLLACONTROL4r(_unit, _pc, _val, _mask) \ 1061 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000805e, (_val), (_mask)) 1062 1063 1064 /**************************************************************************** 1065 * Hypercore_USER_Tx0 1066 */ 1067 1068 /* Tx analog status 0 register */ 1069 #define READ_HL65_TX0_ANATXASTATUS0r(_unit, _pc, _val) \ 1070 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008060, (_val)) 1071 #define WRITE_HL65_TX0_ANATXASTATUS0r(_unit, _pc, _val) \ 1072 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008060, (_val)) 1073 #define MODIFY_HL65_TX0_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 1074 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008060, (_val), (_mask)) 1075 1076 /* Tx analog control 0 register */ 1077 #define READ_HL65_TX0_ANATXACONTROL0r(_unit, _pc, _val) \ 1078 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008061, (_val)) 1079 #define WRITE_HL65_TX0_ANATXACONTROL0r(_unit, _pc, _val) \ 1080 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008061, (_val)) 1081 #define MODIFY_HL65_TX0_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 1082 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008061, (_val), (_mask)) 1083 1084 /* Tx test mux data 0 register */ 1085 #define READ_HL65_TX0_ANATXMDATA0r(_unit, _pc, _val) \ 1086 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008062, (_val)) 1087 #define WRITE_HL65_TX0_ANATXMDATA0r(_unit, _pc, _val) \ 1088 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008062, (_val)) 1089 #define MODIFY_HL65_TX0_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 1090 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008062, (_val), (_mask)) 1091 1092 /* Tx test mux data 1 register */ 1093 #define READ_HL65_TX0_ANATXMDATA1r(_unit, _pc, _val) \ 1094 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008063, (_val)) 1095 #define WRITE_HL65_TX0_ANATXMDATA1r(_unit, _pc, _val) \ 1096 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008063, (_val)) 1097 #define MODIFY_HL65_TX0_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 1098 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008063, (_val), (_mask)) 1099 1100 /* Tx analog status 1 register */ 1101 #define READ_HL65_TX0_ANATXASTATUS1r(_unit, _pc, _val) \ 1102 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008064, (_val)) 1103 #define WRITE_HL65_TX0_ANATXASTATUS1r(_unit, _pc, _val) \ 1104 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008064, (_val)) 1105 #define MODIFY_HL65_TX0_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 1106 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008064, (_val), (_mask)) 1107 1108 /* Tx reserved analog control register */ 1109 #define READ_HL65_TX0_ANATXACONTROL1r(_unit, _pc, _val) \ 1110 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008065, (_val)) 1111 #define WRITE_HL65_TX0_ANATXACONTROL1r(_unit, _pc, _val) \ 1112 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008065, (_val)) 1113 #define MODIFY_HL65_TX0_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 1114 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008065, (_val), (_mask)) 1115 1116 /* Tx reserved analog control register */ 1117 #define READ_HL65_TX0_ANATXACONTROL2r(_unit, _pc, _val) \ 1118 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008066, (_val)) 1119 #define WRITE_HL65_TX0_ANATXACONTROL2r(_unit, _pc, _val) \ 1120 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008066, (_val)) 1121 #define MODIFY_HL65_TX0_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 1122 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008066, (_val), (_mask)) 1123 1124 /* Tx reserved OS analog control register */ 1125 #define READ_HL65_TX0_TX_OS_DRIVERr(_unit, _pc, _val) \ 1126 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008067, (_val)) 1127 #define WRITE_HL65_TX0_TX_OS_DRIVERr(_unit, _pc, _val) \ 1128 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008067, (_val)) 1129 #define MODIFY_HL65_TX0_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \ 1130 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008067, (_val), (_mask)) 1131 1132 /* Tx reserved BR analog control register */ 1133 #define READ_HL65_TX0_TX_BR_DRIVERr(_unit, _pc, _val) \ 1134 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008068, (_val)) 1135 #define WRITE_HL65_TX0_TX_BR_DRIVERr(_unit, _pc, _val) \ 1136 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008068, (_val)) 1137 #define MODIFY_HL65_TX0_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \ 1138 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008068, (_val), (_mask)) 1139 1140 1141 /**************************************************************************** 1142 * Hypercore_USER_Tx1 1143 */ 1144 1145 /* Tx analog status 0 register */ 1146 #define READ_HL65_TX1_ANATXASTATUS0r(_unit, _pc, _val) \ 1147 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008070, (_val)) 1148 #define WRITE_HL65_TX1_ANATXASTATUS0r(_unit, _pc, _val) \ 1149 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008070, (_val)) 1150 #define MODIFY_HL65_TX1_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 1151 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008070, (_val), (_mask)) 1152 1153 /* Tx analog control 0 register */ 1154 #define READ_HL65_TX1_ANATXACONTROL0r(_unit, _pc, _val) \ 1155 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008071, (_val)) 1156 #define WRITE_HL65_TX1_ANATXACONTROL0r(_unit, _pc, _val) \ 1157 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008071, (_val)) 1158 #define MODIFY_HL65_TX1_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 1159 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008071, (_val), (_mask)) 1160 1161 /* Tx test mux data 0 register */ 1162 #define READ_HL65_TX1_ANATXMDATA0r(_unit, _pc, _val) \ 1163 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008072, (_val)) 1164 #define WRITE_HL65_TX1_ANATXMDATA0r(_unit, _pc, _val) \ 1165 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008072, (_val)) 1166 #define MODIFY_HL65_TX1_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 1167 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008072, (_val), (_mask)) 1168 1169 /* Tx test mux data 1 register */ 1170 #define READ_HL65_TX1_ANATXMDATA1r(_unit, _pc, _val) \ 1171 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008073, (_val)) 1172 #define WRITE_HL65_TX1_ANATXMDATA1r(_unit, _pc, _val) \ 1173 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008073, (_val)) 1174 #define MODIFY_HL65_TX1_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 1175 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008073, (_val), (_mask)) 1176 1177 /* Tx analog status 1 register */ 1178 #define READ_HL65_TX1_ANATXASTATUS1r(_unit, _pc, _val) \ 1179 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008074, (_val)) 1180 #define WRITE_HL65_TX1_ANATXASTATUS1r(_unit, _pc, _val) \ 1181 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008074, (_val)) 1182 #define MODIFY_HL65_TX1_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 1183 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008074, (_val), (_mask)) 1184 1185 /* Tx reserved analog control register */ 1186 #define READ_HL65_TX1_ANATXACONTROL1r(_unit, _pc, _val) \ 1187 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008075, (_val)) 1188 #define WRITE_HL65_TX1_ANATXACONTROL1r(_unit, _pc, _val) \ 1189 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008075, (_val)) 1190 #define MODIFY_HL65_TX1_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 1191 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008075, (_val), (_mask)) 1192 1193 /* Tx reserved analog control register */ 1194 #define READ_HL65_TX1_ANATXACONTROL2r(_unit, _pc, _val) \ 1195 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008076, (_val)) 1196 #define WRITE_HL65_TX1_ANATXACONTROL2r(_unit, _pc, _val) \ 1197 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008076, (_val)) 1198 #define MODIFY_HL65_TX1_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 1199 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008076, (_val), (_mask)) 1200 1201 /* Tx reserved OS analog control register */ 1202 #define READ_HL65_TX1_TX_OS_DRIVERr(_unit, _pc, _val) \ 1203 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008077, (_val)) 1204 #define WRITE_HL65_TX1_TX_OS_DRIVERr(_unit, _pc, _val) \ 1205 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008077, (_val)) 1206 #define MODIFY_HL65_TX1_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \ 1207 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008077, (_val), (_mask)) 1208 1209 /* Tx reserved BR analog control register */ 1210 #define READ_HL65_TX1_TX_BR_DRIVERr(_unit, _pc, _val) \ 1211 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008078, (_val)) 1212 #define WRITE_HL65_TX1_TX_BR_DRIVERr(_unit, _pc, _val) \ 1213 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008078, (_val)) 1214 #define MODIFY_HL65_TX1_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \ 1215 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008078, (_val), (_mask)) 1216 1217 1218 /**************************************************************************** 1219 * Hypercore_USER_Tx2 1220 */ 1221 1222 /* Tx analog status 0 register */ 1223 #define READ_HL65_TX2_ANATXASTATUS0r(_unit, _pc, _val) \ 1224 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008080, (_val)) 1225 #define WRITE_HL65_TX2_ANATXASTATUS0r(_unit, _pc, _val) \ 1226 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008080, (_val)) 1227 #define MODIFY_HL65_TX2_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 1228 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008080, (_val), (_mask)) 1229 1230 /* Tx analog control 0 register */ 1231 #define READ_HL65_TX2_ANATXACONTROL0r(_unit, _pc, _val) \ 1232 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008081, (_val)) 1233 #define WRITE_HL65_TX2_ANATXACONTROL0r(_unit, _pc, _val) \ 1234 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008081, (_val)) 1235 #define MODIFY_HL65_TX2_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 1236 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008081, (_val), (_mask)) 1237 1238 /* Tx test mux data 0 register */ 1239 #define READ_HL65_TX2_ANATXMDATA0r(_unit, _pc, _val) \ 1240 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008082, (_val)) 1241 #define WRITE_HL65_TX2_ANATXMDATA0r(_unit, _pc, _val) \ 1242 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008082, (_val)) 1243 #define MODIFY_HL65_TX2_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 1244 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008082, (_val), (_mask)) 1245 1246 /* Tx test mux data 1 register */ 1247 #define READ_HL65_TX2_ANATXMDATA1r(_unit, _pc, _val) \ 1248 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008083, (_val)) 1249 #define WRITE_HL65_TX2_ANATXMDATA1r(_unit, _pc, _val) \ 1250 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008083, (_val)) 1251 #define MODIFY_HL65_TX2_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 1252 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008083, (_val), (_mask)) 1253 1254 /* Tx analog status 1 register */ 1255 #define READ_HL65_TX2_ANATXASTATUS1r(_unit, _pc, _val) \ 1256 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008084, (_val)) 1257 #define WRITE_HL65_TX2_ANATXASTATUS1r(_unit, _pc, _val) \ 1258 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008084, (_val)) 1259 #define MODIFY_HL65_TX2_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 1260 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008084, (_val), (_mask)) 1261 1262 /* Tx reserved analog control register */ 1263 #define READ_HL65_TX2_ANATXACONTROL1r(_unit, _pc, _val) \ 1264 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008085, (_val)) 1265 #define WRITE_HL65_TX2_ANATXACONTROL1r(_unit, _pc, _val) \ 1266 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008085, (_val)) 1267 #define MODIFY_HL65_TX2_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 1268 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008085, (_val), (_mask)) 1269 1270 /* Tx reserved analog control register */ 1271 #define READ_HL65_TX2_ANATXACONTROL2r(_unit, _pc, _val) \ 1272 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008086, (_val)) 1273 #define WRITE_HL65_TX2_ANATXACONTROL2r(_unit, _pc, _val) \ 1274 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008086, (_val)) 1275 #define MODIFY_HL65_TX2_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 1276 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008086, (_val), (_mask)) 1277 1278 /* Tx reserved OS analog control register */ 1279 #define READ_HL65_TX2_TX_OS_DRIVERr(_unit, _pc, _val) \ 1280 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008087, (_val)) 1281 #define WRITE_HL65_TX2_TX_OS_DRIVERr(_unit, _pc, _val) \ 1282 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008087, (_val)) 1283 #define MODIFY_HL65_TX2_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \ 1284 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008087, (_val), (_mask)) 1285 1286 /* Tx reserved BR analog control register */ 1287 #define READ_HL65_TX2_TX_BR_DRIVERr(_unit, _pc, _val) \ 1288 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008088, (_val)) 1289 #define WRITE_HL65_TX2_TX_BR_DRIVERr(_unit, _pc, _val) \ 1290 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008088, (_val)) 1291 #define MODIFY_HL65_TX2_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \ 1292 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008088, (_val), (_mask)) 1293 1294 1295 /**************************************************************************** 1296 * Hypercore_USER_Tx3 1297 */ 1298 1299 /* Tx analog status 0 register */ 1300 #define READ_HL65_TX3_ANATXASTATUS0r(_unit, _pc, _val) \ 1301 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008090, (_val)) 1302 #define WRITE_HL65_TX3_ANATXASTATUS0r(_unit, _pc, _val) \ 1303 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008090, (_val)) 1304 #define MODIFY_HL65_TX3_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 1305 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008090, (_val), (_mask)) 1306 1307 /* Tx analog control 0 register */ 1308 #define READ_HL65_TX3_ANATXACONTROL0r(_unit, _pc, _val) \ 1309 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008091, (_val)) 1310 #define WRITE_HL65_TX3_ANATXACONTROL0r(_unit, _pc, _val) \ 1311 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008091, (_val)) 1312 #define MODIFY_HL65_TX3_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 1313 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008091, (_val), (_mask)) 1314 1315 /* Tx test mux data 0 register */ 1316 #define READ_HL65_TX3_ANATXMDATA0r(_unit, _pc, _val) \ 1317 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008092, (_val)) 1318 #define WRITE_HL65_TX3_ANATXMDATA0r(_unit, _pc, _val) \ 1319 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008092, (_val)) 1320 #define MODIFY_HL65_TX3_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 1321 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008092, (_val), (_mask)) 1322 1323 /* Tx test mux data 1 register */ 1324 #define READ_HL65_TX3_ANATXMDATA1r(_unit, _pc, _val) \ 1325 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008093, (_val)) 1326 #define WRITE_HL65_TX3_ANATXMDATA1r(_unit, _pc, _val) \ 1327 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008093, (_val)) 1328 #define MODIFY_HL65_TX3_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 1329 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008093, (_val), (_mask)) 1330 1331 /* Tx analog status 1 register */ 1332 #define READ_HL65_TX3_ANATXASTATUS1r(_unit, _pc, _val) \ 1333 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008094, (_val)) 1334 #define WRITE_HL65_TX3_ANATXASTATUS1r(_unit, _pc, _val) \ 1335 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008094, (_val)) 1336 #define MODIFY_HL65_TX3_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 1337 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008094, (_val), (_mask)) 1338 1339 /* Tx reserved analog control register */ 1340 #define READ_HL65_TX3_ANATXACONTROL1r(_unit, _pc, _val) \ 1341 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008095, (_val)) 1342 #define WRITE_HL65_TX3_ANATXACONTROL1r(_unit, _pc, _val) \ 1343 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008095, (_val)) 1344 #define MODIFY_HL65_TX3_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 1345 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008095, (_val), (_mask)) 1346 1347 /* Tx reserved analog control register */ 1348 #define READ_HL65_TX3_ANATXACONTROL2r(_unit, _pc, _val) \ 1349 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008096, (_val)) 1350 #define WRITE_HL65_TX3_ANATXACONTROL2r(_unit, _pc, _val) \ 1351 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008096, (_val)) 1352 #define MODIFY_HL65_TX3_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 1353 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008096, (_val), (_mask)) 1354 1355 /* Tx reserved OS analog control register */ 1356 #define READ_HL65_TX3_TX_OS_DRIVERr(_unit, _pc, _val) \ 1357 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008097, (_val)) 1358 #define WRITE_HL65_TX3_TX_OS_DRIVERr(_unit, _pc, _val) \ 1359 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008097, (_val)) 1360 #define MODIFY_HL65_TX3_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \ 1361 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008097, (_val), (_mask)) 1362 1363 /* Tx reserved BR analog control register */ 1364 #define READ_HL65_TX3_TX_BR_DRIVERr(_unit, _pc, _val) \ 1365 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008098, (_val)) 1366 #define WRITE_HL65_TX3_TX_BR_DRIVERr(_unit, _pc, _val) \ 1367 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008098, (_val)) 1368 #define MODIFY_HL65_TX3_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \ 1369 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008098, (_val), (_mask)) 1370 1371 1372 /**************************************************************************** 1373 * Hypercore_USER_TxB 1374 */ 1375 1376 /* Tx analog status 0 register */ 1377 #define READ_HL65_TXB_ANATXASTATUS0r(_unit, _pc, _val) \ 1378 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a0, (_val)) 1379 #define WRITE_HL65_TXB_ANATXASTATUS0r(_unit, _pc, _val) \ 1380 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a0, (_val)) 1381 #define MODIFY_HL65_TXB_ANATXASTATUS0r(_unit, _pc, _val, _mask) \ 1382 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a0, (_val), (_mask)) 1383 1384 /* Tx analog control 0 register */ 1385 #define READ_HL65_TXB_ANATXACONTROL0r(_unit, _pc, _val) \ 1386 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a1, (_val)) 1387 #define WRITE_HL65_TXB_ANATXACONTROL0r(_unit, _pc, _val) \ 1388 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a1, (_val)) 1389 #define MODIFY_HL65_TXB_ANATXACONTROL0r(_unit, _pc, _val, _mask) \ 1390 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a1, (_val), (_mask)) 1391 1392 /* Tx test mux data 0 register */ 1393 #define READ_HL65_TXB_ANATXMDATA0r(_unit, _pc, _val) \ 1394 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a2, (_val)) 1395 #define WRITE_HL65_TXB_ANATXMDATA0r(_unit, _pc, _val) \ 1396 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a2, (_val)) 1397 #define MODIFY_HL65_TXB_ANATXMDATA0r(_unit, _pc, _val, _mask) \ 1398 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a2, (_val), (_mask)) 1399 1400 /* Tx test mux data 1 register */ 1401 #define READ_HL65_TXB_ANATXMDATA1r(_unit, _pc, _val) \ 1402 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a3, (_val)) 1403 #define WRITE_HL65_TXB_ANATXMDATA1r(_unit, _pc, _val) \ 1404 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a3, (_val)) 1405 #define MODIFY_HL65_TXB_ANATXMDATA1r(_unit, _pc, _val, _mask) \ 1406 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a3, (_val), (_mask)) 1407 1408 /* Tx analog status 1 register */ 1409 #define READ_HL65_TXB_ANATXASTATUS1r(_unit, _pc, _val) \ 1410 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a4, (_val)) 1411 #define WRITE_HL65_TXB_ANATXASTATUS1r(_unit, _pc, _val) \ 1412 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a4, (_val)) 1413 #define MODIFY_HL65_TXB_ANATXASTATUS1r(_unit, _pc, _val, _mask) \ 1414 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a4, (_val), (_mask)) 1415 1416 /* Tx reserved analog control register */ 1417 #define READ_HL65_TXB_ANATXACONTROL1r(_unit, _pc, _val) \ 1418 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a5, (_val)) 1419 #define WRITE_HL65_TXB_ANATXACONTROL1r(_unit, _pc, _val) \ 1420 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a5, (_val)) 1421 #define MODIFY_HL65_TXB_ANATXACONTROL1r(_unit, _pc, _val, _mask) \ 1422 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a5, (_val), (_mask)) 1423 1424 /* Tx reserved analog control register */ 1425 #define READ_HL65_TXB_ANATXACONTROL2r(_unit, _pc, _val) \ 1426 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a6, (_val)) 1427 #define WRITE_HL65_TXB_ANATXACONTROL2r(_unit, _pc, _val) \ 1428 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a6, (_val)) 1429 #define MODIFY_HL65_TXB_ANATXACONTROL2r(_unit, _pc, _val, _mask) \ 1430 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a6, (_val), (_mask)) 1431 1432 /* Tx reserved OS analog control register */ 1433 #define READ_HL65_TXB_TX_OS_DRIVERr(_unit, _pc, _val) \ 1434 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a7, (_val)) 1435 #define WRITE_HL65_TXB_TX_OS_DRIVERr(_unit, _pc, _val) \ 1436 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a7, (_val)) 1437 #define MODIFY_HL65_TXB_TX_OS_DRIVERr(_unit, _pc, _val, _mask) \ 1438 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a7, (_val), (_mask)) 1439 1440 /* Tx reserved BR analog control register */ 1441 #define READ_HL65_TXB_TX_BR_DRIVERr(_unit, _pc, _val) \ 1442 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080a8, (_val)) 1443 #define WRITE_HL65_TXB_TX_BR_DRIVERr(_unit, _pc, _val) \ 1444 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080a8, (_val)) 1445 #define MODIFY_HL65_TXB_TX_BR_DRIVERr(_unit, _pc, _val, _mask) \ 1446 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080a8, (_val), (_mask)) 1447 1448 1449 /**************************************************************************** 1450 * Hypercore_USER_Rx0 1451 */ 1452 1453 /* Rx lane status register */ 1454 #define READ_HL65_RX0_ANARXSTATUSr(_unit, _pc, _val) \ 1455 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080b0, (_val)) 1456 #define WRITE_HL65_RX0_ANARXSTATUSr(_unit, _pc, _val) \ 1457 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080b0, (_val)) 1458 #define MODIFY_HL65_RX0_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 1459 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b0, (_val), (_mask)) 1460 1461 /* Rx lane control register */ 1462 #define READ_HL65_RX0_ANARXCONTROLr(_unit, _pc, _val) \ 1463 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080b1, (_val)) 1464 #define WRITE_HL65_RX0_ANARXCONTROLr(_unit, _pc, _val) \ 1465 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080b1, (_val)) 1466 #define MODIFY_HL65_RX0_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 1467 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b1, (_val), (_mask)) 1468 1469 /* Rx lane control register */ 1470 #define READ_HL65_RX0_ANARXTESTr(_unit, _pc, _val) \ 1471 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080b8, (_val)) 1472 #define WRITE_HL65_RX0_ANARXTESTr(_unit, _pc, _val) \ 1473 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080b8, (_val)) 1474 #define MODIFY_HL65_RX0_ANARXTESTr(_unit, _pc, _val, _mask) \ 1475 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b8, (_val), (_mask)) 1476 1477 /* Rx 1G Control register */ 1478 #define READ_HL65_RX0_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1479 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080b9, (_val)) 1480 #define WRITE_HL65_RX0_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1481 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080b9, (_val)) 1482 #define MODIFY_HL65_RX0_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 1483 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080b9, (_val), (_mask)) 1484 1485 /* Rx PCI Control register */ 1486 #define READ_HL65_RX0_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1487 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ba, (_val)) 1488 #define WRITE_HL65_RX0_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1489 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ba, (_val)) 1490 #define MODIFY_HL65_RX0_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 1491 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ba, (_val), (_mask)) 1492 1493 /* Rx analog status register */ 1494 #define READ_HL65_RX0_ANARXASTATUSr(_unit, _pc, _val) \ 1495 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080bb, (_val)) 1496 #define WRITE_HL65_RX0_ANARXASTATUSr(_unit, _pc, _val) \ 1497 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080bb, (_val)) 1498 #define MODIFY_HL65_RX0_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 1499 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bb, (_val), (_mask)) 1500 1501 /* Rx reserved analog control register */ 1502 #define READ_HL65_RX0_ANARXACONTROL1r(_unit, _pc, _val) \ 1503 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080bc, (_val)) 1504 #define WRITE_HL65_RX0_ANARXACONTROL1r(_unit, _pc, _val) \ 1505 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080bc, (_val)) 1506 #define MODIFY_HL65_RX0_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 1507 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bc, (_val), (_mask)) 1508 1509 /* Rx reserved analog control register */ 1510 #define READ_HL65_RX0_ANARXACONTROL2r(_unit, _pc, _val) \ 1511 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080bd, (_val)) 1512 #define WRITE_HL65_RX0_ANARXACONTROL2r(_unit, _pc, _val) \ 1513 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080bd, (_val)) 1514 #define MODIFY_HL65_RX0_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 1515 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080bd, (_val), (_mask)) 1516 1517 /* Rx reserved analog control register */ 1518 #define READ_HL65_RX0_ANARXACONTROL3r(_unit, _pc, _val) \ 1519 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080be, (_val)) 1520 #define WRITE_HL65_RX0_ANARXACONTROL3r(_unit, _pc, _val) \ 1521 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080be, (_val)) 1522 #define MODIFY_HL65_RX0_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 1523 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080be, (_val), (_mask)) 1524 1525 1526 /**************************************************************************** 1527 * Hypercore_USER_Rx1 1528 */ 1529 1530 /* Rx lane status register */ 1531 #define READ_HL65_RX1_ANARXSTATUSr(_unit, _pc, _val) \ 1532 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080c0, (_val)) 1533 #define WRITE_HL65_RX1_ANARXSTATUSr(_unit, _pc, _val) \ 1534 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080c0, (_val)) 1535 #define MODIFY_HL65_RX1_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 1536 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c0, (_val), (_mask)) 1537 1538 /* Rx lane control register */ 1539 #define READ_HL65_RX1_ANARXCONTROLr(_unit, _pc, _val) \ 1540 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080c1, (_val)) 1541 #define WRITE_HL65_RX1_ANARXCONTROLr(_unit, _pc, _val) \ 1542 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080c1, (_val)) 1543 #define MODIFY_HL65_RX1_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 1544 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c1, (_val), (_mask)) 1545 1546 /* Rx lane control register */ 1547 #define READ_HL65_RX1_ANARXTESTr(_unit, _pc, _val) \ 1548 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080c8, (_val)) 1549 #define WRITE_HL65_RX1_ANARXTESTr(_unit, _pc, _val) \ 1550 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080c8, (_val)) 1551 #define MODIFY_HL65_RX1_ANARXTESTr(_unit, _pc, _val, _mask) \ 1552 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c8, (_val), (_mask)) 1553 1554 /* Rx 1G Control register */ 1555 #define READ_HL65_RX1_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1556 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080c9, (_val)) 1557 #define WRITE_HL65_RX1_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1558 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080c9, (_val)) 1559 #define MODIFY_HL65_RX1_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 1560 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080c9, (_val), (_mask)) 1561 1562 /* Rx PCI Control register */ 1563 #define READ_HL65_RX1_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1564 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ca, (_val)) 1565 #define WRITE_HL65_RX1_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1566 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ca, (_val)) 1567 #define MODIFY_HL65_RX1_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 1568 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ca, (_val), (_mask)) 1569 1570 /* Rx analog status register */ 1571 #define READ_HL65_RX1_ANARXASTATUSr(_unit, _pc, _val) \ 1572 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080cb, (_val)) 1573 #define WRITE_HL65_RX1_ANARXASTATUSr(_unit, _pc, _val) \ 1574 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080cb, (_val)) 1575 #define MODIFY_HL65_RX1_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 1576 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cb, (_val), (_mask)) 1577 1578 /* Rx reserved analog control register */ 1579 #define READ_HL65_RX1_ANARXACONTROL1r(_unit, _pc, _val) \ 1580 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080cc, (_val)) 1581 #define WRITE_HL65_RX1_ANARXACONTROL1r(_unit, _pc, _val) \ 1582 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080cc, (_val)) 1583 #define MODIFY_HL65_RX1_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 1584 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cc, (_val), (_mask)) 1585 1586 /* Rx reserved analog control register */ 1587 #define READ_HL65_RX1_ANARXACONTROL2r(_unit, _pc, _val) \ 1588 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080cd, (_val)) 1589 #define WRITE_HL65_RX1_ANARXACONTROL2r(_unit, _pc, _val) \ 1590 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080cd, (_val)) 1591 #define MODIFY_HL65_RX1_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 1592 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080cd, (_val), (_mask)) 1593 1594 /* Rx reserved analog control register */ 1595 #define READ_HL65_RX1_ANARXACONTROL3r(_unit, _pc, _val) \ 1596 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ce, (_val)) 1597 #define WRITE_HL65_RX1_ANARXACONTROL3r(_unit, _pc, _val) \ 1598 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ce, (_val)) 1599 #define MODIFY_HL65_RX1_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 1600 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ce, (_val), (_mask)) 1601 1602 1603 /**************************************************************************** 1604 * Hypercore_USER_Rx2 1605 */ 1606 1607 /* Rx lane status register */ 1608 #define READ_HL65_RX2_ANARXSTATUSr(_unit, _pc, _val) \ 1609 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080d0, (_val)) 1610 #define WRITE_HL65_RX2_ANARXSTATUSr(_unit, _pc, _val) \ 1611 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080d0, (_val)) 1612 #define MODIFY_HL65_RX2_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 1613 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d0, (_val), (_mask)) 1614 1615 /* Rx lane control register */ 1616 #define READ_HL65_RX2_ANARXCONTROLr(_unit, _pc, _val) \ 1617 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080d1, (_val)) 1618 #define WRITE_HL65_RX2_ANARXCONTROLr(_unit, _pc, _val) \ 1619 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080d1, (_val)) 1620 #define MODIFY_HL65_RX2_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 1621 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d1, (_val), (_mask)) 1622 1623 /* Rx lane control register */ 1624 #define READ_HL65_RX2_ANARXTESTr(_unit, _pc, _val) \ 1625 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080d8, (_val)) 1626 #define WRITE_HL65_RX2_ANARXTESTr(_unit, _pc, _val) \ 1627 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080d8, (_val)) 1628 #define MODIFY_HL65_RX2_ANARXTESTr(_unit, _pc, _val, _mask) \ 1629 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d8, (_val), (_mask)) 1630 1631 /* Rx 1G Control register */ 1632 #define READ_HL65_RX2_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1633 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080d9, (_val)) 1634 #define WRITE_HL65_RX2_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1635 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080d9, (_val)) 1636 #define MODIFY_HL65_RX2_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 1637 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080d9, (_val), (_mask)) 1638 1639 /* Rx PCI Control register */ 1640 #define READ_HL65_RX2_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1641 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080da, (_val)) 1642 #define WRITE_HL65_RX2_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1643 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080da, (_val)) 1644 #define MODIFY_HL65_RX2_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 1645 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080da, (_val), (_mask)) 1646 1647 /* Rx analog status register */ 1648 #define READ_HL65_RX2_ANARXASTATUSr(_unit, _pc, _val) \ 1649 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080db, (_val)) 1650 #define WRITE_HL65_RX2_ANARXASTATUSr(_unit, _pc, _val) \ 1651 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080db, (_val)) 1652 #define MODIFY_HL65_RX2_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 1653 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080db, (_val), (_mask)) 1654 1655 /* Rx reserved analog control register */ 1656 #define READ_HL65_RX2_ANARXACONTROL1r(_unit, _pc, _val) \ 1657 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080dc, (_val)) 1658 #define WRITE_HL65_RX2_ANARXACONTROL1r(_unit, _pc, _val) \ 1659 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080dc, (_val)) 1660 #define MODIFY_HL65_RX2_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 1661 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dc, (_val), (_mask)) 1662 1663 /* Rx reserved analog control register */ 1664 #define READ_HL65_RX2_ANARXACONTROL2r(_unit, _pc, _val) \ 1665 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080dd, (_val)) 1666 #define WRITE_HL65_RX2_ANARXACONTROL2r(_unit, _pc, _val) \ 1667 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080dd, (_val)) 1668 #define MODIFY_HL65_RX2_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 1669 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080dd, (_val), (_mask)) 1670 1671 /* Rx reserved analog control register */ 1672 #define READ_HL65_RX2_ANARXACONTROL3r(_unit, _pc, _val) \ 1673 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080de, (_val)) 1674 #define WRITE_HL65_RX2_ANARXACONTROL3r(_unit, _pc, _val) \ 1675 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080de, (_val)) 1676 #define MODIFY_HL65_RX2_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 1677 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080de, (_val), (_mask)) 1678 1679 1680 /**************************************************************************** 1681 * Hypercore_USER_Rx3 1682 */ 1683 1684 /* Rx lane status register */ 1685 #define READ_HL65_RX3_ANARXSTATUSr(_unit, _pc, _val) \ 1686 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080e0, (_val)) 1687 #define WRITE_HL65_RX3_ANARXSTATUSr(_unit, _pc, _val) \ 1688 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080e0, (_val)) 1689 #define MODIFY_HL65_RX3_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 1690 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e0, (_val), (_mask)) 1691 1692 /* Rx lane control register */ 1693 #define READ_HL65_RX3_ANARXCONTROLr(_unit, _pc, _val) \ 1694 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080e1, (_val)) 1695 #define WRITE_HL65_RX3_ANARXCONTROLr(_unit, _pc, _val) \ 1696 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080e1, (_val)) 1697 #define MODIFY_HL65_RX3_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 1698 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e1, (_val), (_mask)) 1699 1700 /* Rx lane control register */ 1701 #define READ_HL65_RX3_ANARXTESTr(_unit, _pc, _val) \ 1702 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080e8, (_val)) 1703 #define WRITE_HL65_RX3_ANARXTESTr(_unit, _pc, _val) \ 1704 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080e8, (_val)) 1705 #define MODIFY_HL65_RX3_ANARXTESTr(_unit, _pc, _val, _mask) \ 1706 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e8, (_val), (_mask)) 1707 1708 /* Rx 1G Control register */ 1709 #define READ_HL65_RX3_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1710 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080e9, (_val)) 1711 #define WRITE_HL65_RX3_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1712 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080e9, (_val)) 1713 #define MODIFY_HL65_RX3_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 1714 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080e9, (_val), (_mask)) 1715 1716 /* Rx PCI Control register */ 1717 #define READ_HL65_RX3_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1718 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ea, (_val)) 1719 #define WRITE_HL65_RX3_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1720 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ea, (_val)) 1721 #define MODIFY_HL65_RX3_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 1722 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ea, (_val), (_mask)) 1723 1724 /* Rx analog status register */ 1725 #define READ_HL65_RX3_ANARXASTATUSr(_unit, _pc, _val) \ 1726 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080eb, (_val)) 1727 #define WRITE_HL65_RX3_ANARXASTATUSr(_unit, _pc, _val) \ 1728 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080eb, (_val)) 1729 #define MODIFY_HL65_RX3_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 1730 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080eb, (_val), (_mask)) 1731 1732 /* Rx reserved analog control register */ 1733 #define READ_HL65_RX3_ANARXACONTROL1r(_unit, _pc, _val) \ 1734 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ec, (_val)) 1735 #define WRITE_HL65_RX3_ANARXACONTROL1r(_unit, _pc, _val) \ 1736 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ec, (_val)) 1737 #define MODIFY_HL65_RX3_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 1738 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ec, (_val), (_mask)) 1739 1740 /* Rx reserved analog control register */ 1741 #define READ_HL65_RX3_ANARXACONTROL2r(_unit, _pc, _val) \ 1742 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ed, (_val)) 1743 #define WRITE_HL65_RX3_ANARXACONTROL2r(_unit, _pc, _val) \ 1744 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ed, (_val)) 1745 #define MODIFY_HL65_RX3_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 1746 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ed, (_val), (_mask)) 1747 1748 /* Rx reserved analog control register */ 1749 #define READ_HL65_RX3_ANARXACONTROL3r(_unit, _pc, _val) \ 1750 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080ee, (_val)) 1751 #define WRITE_HL65_RX3_ANARXACONTROL3r(_unit, _pc, _val) \ 1752 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080ee, (_val)) 1753 #define MODIFY_HL65_RX3_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 1754 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080ee, (_val), (_mask)) 1755 1756 1757 /**************************************************************************** 1758 * Hypercore_USER_RxB 1759 */ 1760 1761 /* Rx lane status register */ 1762 #define READ_HL65_RXB_ANARXSTATUSr(_unit, _pc, _val) \ 1763 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080f0, (_val)) 1764 #define WRITE_HL65_RXB_ANARXSTATUSr(_unit, _pc, _val) \ 1765 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080f0, (_val)) 1766 #define MODIFY_HL65_RXB_ANARXSTATUSr(_unit, _pc, _val, _mask) \ 1767 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f0, (_val), (_mask)) 1768 1769 /* Rx lane control register */ 1770 #define READ_HL65_RXB_ANARXCONTROLr(_unit, _pc, _val) \ 1771 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080f1, (_val)) 1772 #define WRITE_HL65_RXB_ANARXCONTROLr(_unit, _pc, _val) \ 1773 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080f1, (_val)) 1774 #define MODIFY_HL65_RXB_ANARXCONTROLr(_unit, _pc, _val, _mask) \ 1775 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f1, (_val), (_mask)) 1776 1777 /* Rx lane control register */ 1778 #define READ_HL65_RXB_ANARXTESTr(_unit, _pc, _val) \ 1779 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080f8, (_val)) 1780 #define WRITE_HL65_RXB_ANARXTESTr(_unit, _pc, _val) \ 1781 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080f8, (_val)) 1782 #define MODIFY_HL65_RXB_ANARXTESTr(_unit, _pc, _val, _mask) \ 1783 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f8, (_val), (_mask)) 1784 1785 /* Rx 1G Control register */ 1786 #define READ_HL65_RXB_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1787 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080f9, (_val)) 1788 #define WRITE_HL65_RXB_ANARXCONTROL1Gr(_unit, _pc, _val) \ 1789 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080f9, (_val)) 1790 #define MODIFY_HL65_RXB_ANARXCONTROL1Gr(_unit, _pc, _val, _mask) \ 1791 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080f9, (_val), (_mask)) 1792 1793 /* Rx PCI Control register */ 1794 #define READ_HL65_RXB_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1795 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fa, (_val)) 1796 #define WRITE_HL65_RXB_ANARXCONTROLPCIr(_unit, _pc, _val) \ 1797 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fa, (_val)) 1798 #define MODIFY_HL65_RXB_ANARXCONTROLPCIr(_unit, _pc, _val, _mask) \ 1799 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fa, (_val), (_mask)) 1800 1801 /* Rx analog status register */ 1802 #define READ_HL65_RXB_ANARXASTATUSr(_unit, _pc, _val) \ 1803 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fb, (_val)) 1804 #define WRITE_HL65_RXB_ANARXASTATUSr(_unit, _pc, _val) \ 1805 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fb, (_val)) 1806 #define MODIFY_HL65_RXB_ANARXASTATUSr(_unit, _pc, _val, _mask) \ 1807 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fb, (_val), (_mask)) 1808 1809 /* Rx reserved analog control register */ 1810 #define READ_HL65_RXB_ANARXACONTROL1r(_unit, _pc, _val) \ 1811 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fc, (_val)) 1812 #define WRITE_HL65_RXB_ANARXACONTROL1r(_unit, _pc, _val) \ 1813 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fc, (_val)) 1814 #define MODIFY_HL65_RXB_ANARXACONTROL1r(_unit, _pc, _val, _mask) \ 1815 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fc, (_val), (_mask)) 1816 1817 /* Rx reserved analog control register */ 1818 #define READ_HL65_RXB_ANARXACONTROL2r(_unit, _pc, _val) \ 1819 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fd, (_val)) 1820 #define WRITE_HL65_RXB_ANARXACONTROL2r(_unit, _pc, _val) \ 1821 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fd, (_val)) 1822 #define MODIFY_HL65_RXB_ANARXACONTROL2r(_unit, _pc, _val, _mask) \ 1823 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fd, (_val), (_mask)) 1824 1825 /* Rx reserved analog control register */ 1826 #define READ_HL65_RXB_ANARXACONTROL3r(_unit, _pc, _val) \ 1827 HL65_REG_READ((_unit), (_pc), 0x00, 0x000080fe, (_val)) 1828 #define WRITE_HL65_RXB_ANARXACONTROL3r(_unit, _pc, _val) \ 1829 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000080fe, (_val)) 1830 #define MODIFY_HL65_RXB_ANARXACONTROL3r(_unit, _pc, _val, _mask) \ 1831 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000080fe, (_val), (_mask)) 1832 1833 1834 /**************************************************************************** 1835 * Hypercore_USER_XgxsBlk2 1836 */ 1837 1838 /* Receiver lane swap control register */ 1839 #define READ_HL65_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \ 1840 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008100, (_val)) 1841 #define WRITE_HL65_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val) \ 1842 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008100, (_val)) 1843 #define MODIFY_HL65_XGXSBLK2_RXLNSWAPr(_unit, _pc, _val, _mask) \ 1844 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008100, (_val), (_mask)) 1845 1846 /* Transmit lane swap control register */ 1847 #define READ_HL65_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \ 1848 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008101, (_val)) 1849 #define WRITE_HL65_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val) \ 1850 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008101, (_val)) 1851 #define MODIFY_HL65_XGXSBLK2_TXLNSWAPr(_unit, _pc, _val, _mask) \ 1852 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008101, (_val), (_mask)) 1853 1854 /* ||Q|| ordered set, lanes 0 & 1 register */ 1855 #define READ_HL65_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \ 1856 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008102, (_val)) 1857 #define WRITE_HL65_XGXSBLK2_QSETLNS01r(_unit, _pc, _val) \ 1858 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008102, (_val)) 1859 #define MODIFY_HL65_XGXSBLK2_QSETLNS01r(_unit, _pc, _val, _mask) \ 1860 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008102, (_val), (_mask)) 1861 1862 /* ||Q|| ordered set, lanes 2 & 3 register */ 1863 #define READ_HL65_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \ 1864 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008103, (_val)) 1865 #define WRITE_HL65_XGXSBLK2_QSETLNS23r(_unit, _pc, _val) \ 1866 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008103, (_val)) 1867 #define MODIFY_HL65_XGXSBLK2_QSETLNS23r(_unit, _pc, _val, _mask) \ 1868 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008103, (_val), (_mask)) 1869 1870 /* AN 10G resolution mode control register */ 1871 #define READ_HL65_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \ 1872 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008104, (_val)) 1873 #define WRITE_HL65_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val) \ 1874 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008104, (_val)) 1875 #define MODIFY_HL65_XGXSBLK2_UNICOREMODE10Gr(_unit, _pc, _val, _mask) \ 1876 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008104, (_val), (_mask)) 1877 1878 /* Independent Combo Control register */ 1879 #define READ_HL65_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \ 1880 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008105, (_val)) 1881 #define WRITE_HL65_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val) \ 1882 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008105, (_val)) 1883 #define MODIFY_HL65_XGXSBLK2_INDCOMBCTRLr(_unit, _pc, _val, _mask) \ 1884 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008105, (_val), (_mask)) 1885 1886 /* Test mode lane select register */ 1887 #define READ_HL65_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \ 1888 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008106, (_val)) 1889 #define WRITE_HL65_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val) \ 1890 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008106, (_val)) 1891 #define MODIFY_HL65_XGXSBLK2_TESTMODELANEr(_unit, _pc, _val, _mask) \ 1892 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008106, (_val), (_mask)) 1893 1894 /* Test mode monitor control register */ 1895 #define READ_HL65_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \ 1896 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008107, (_val)) 1897 #define WRITE_HL65_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val) \ 1898 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008107, (_val)) 1899 #define MODIFY_HL65_XGXSBLK2_TESTMODECOMBOr(_unit, _pc, _val, _mask) \ 1900 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008107, (_val), (_mask)) 1901 1902 /* Test mode mux control register */ 1903 #define READ_HL65_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \ 1904 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008108, (_val)) 1905 #define WRITE_HL65_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val) \ 1906 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008108, (_val)) 1907 #define MODIFY_HL65_XGXSBLK2_TESTMODEMUXr(_unit, _pc, _val, _mask) \ 1908 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008108, (_val), (_mask)) 1909 1910 /* 10GBASE-CX4 signal detect timeout value */ 1911 #define READ_HL65_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \ 1912 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008109, (_val)) 1913 #define WRITE_HL65_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val) \ 1914 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008109, (_val)) 1915 #define MODIFY_HL65_XGXSBLK2_CX4SIGDETCNTr(_unit, _pc, _val, _mask) \ 1916 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008109, (_val), (_mask)) 1917 1918 /* Lane reset register */ 1919 #define READ_HL65_XGXSBLK2_LANERESETr(_unit, _pc, _val) \ 1920 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000810a, (_val)) 1921 #define WRITE_HL65_XGXSBLK2_LANERESETr(_unit, _pc, _val) \ 1922 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000810a, (_val)) 1923 #define MODIFY_HL65_XGXSBLK2_LANERESETr(_unit, _pc, _val, _mask) \ 1924 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810a, (_val), (_mask)) 1925 1926 /* XGXS Status 6 register */ 1927 #define READ_HL65_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val) \ 1928 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000810b, (_val)) 1929 #define WRITE_HL65_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val) \ 1930 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000810b, (_val)) 1931 #define MODIFY_HL65_XGXSBLK2_XGXSSTATUS6r(_unit, _pc, _val, _mask) \ 1932 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810b, (_val), (_mask)) 1933 1934 /* Clause 73 control 7 register */ 1935 #define READ_HL65_XGXSBLK2_CL73CONTROL7r(_unit, _pc, _val) \ 1936 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000810d, (_val)) 1937 #define WRITE_HL65_XGXSBLK2_CL73CONTROL7r(_unit, _pc, _val) \ 1938 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000810d, (_val)) 1939 #define MODIFY_HL65_XGXSBLK2_CL73CONTROL7r(_unit, _pc, _val, _mask) \ 1940 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810d, (_val), (_mask)) 1941 1942 /* Clause 73 control 8 register */ 1943 #define READ_HL65_XGXSBLK2_CL73CONTROL8r(_unit, _pc, _val) \ 1944 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000810e, (_val)) 1945 #define WRITE_HL65_XGXSBLK2_CL73CONTROL8r(_unit, _pc, _val) \ 1946 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000810e, (_val)) 1947 #define MODIFY_HL65_XGXSBLK2_CL73CONTROL8r(_unit, _pc, _val, _mask) \ 1948 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000810e, (_val), (_mask)) 1949 1950 1951 /**************************************************************************** 1952 * Hypercore_USER_XgxsBlk3 1953 */ 1954 1955 /* In Band MDIO - local status register */ 1956 #define READ_HL65_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val) \ 1957 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008110, (_val)) 1958 #define WRITE_HL65_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val) \ 1959 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008110, (_val)) 1960 #define MODIFY_HL65_XGXSBLK3_LOCALSTATUSr(_unit, _pc, _val, _mask) \ 1961 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008110, (_val), (_mask)) 1962 1963 /* In Band MDIO - local control 0 register */ 1964 #define READ_HL65_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val) \ 1965 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008111, (_val)) 1966 #define WRITE_HL65_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val) \ 1967 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008111, (_val)) 1968 #define MODIFY_HL65_XGXSBLK3_LOCALCONTROL0r(_unit, _pc, _val, _mask) \ 1969 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008111, (_val), (_mask)) 1970 1971 /* In Band MDIO - local control 1 register */ 1972 #define READ_HL65_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val) \ 1973 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008112, (_val)) 1974 #define WRITE_HL65_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val) \ 1975 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008112, (_val)) 1976 #define MODIFY_HL65_XGXSBLK3_LOCALCONTROL1r(_unit, _pc, _val, _mask) \ 1977 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008112, (_val), (_mask)) 1978 1979 /* In Band MDIO - remote write ln 0 & 3 register */ 1980 #define READ_HL65_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val) \ 1981 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008113, (_val)) 1982 #define WRITE_HL65_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val) \ 1983 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008113, (_val)) 1984 #define MODIFY_HL65_XGXSBLK3_REMOTEWRITE03r(_unit, _pc, _val, _mask) \ 1985 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008113, (_val), (_mask)) 1986 1987 /* In Band MDIO - remote write ln 1 & 2 register */ 1988 #define READ_HL65_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val) \ 1989 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008114, (_val)) 1990 #define WRITE_HL65_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val) \ 1991 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008114, (_val)) 1992 #define MODIFY_HL65_XGXSBLK3_REMOTEWRITE12r(_unit, _pc, _val, _mask) \ 1993 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008114, (_val), (_mask)) 1994 1995 /* In Band MDIO - remote read ln 1 & 2 register */ 1996 #define READ_HL65_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val) \ 1997 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008115, (_val)) 1998 #define WRITE_HL65_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val) \ 1999 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008115, (_val)) 2000 #define MODIFY_HL65_XGXSBLK3_REMOTEREAD12r(_unit, _pc, _val, _mask) \ 2001 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008115, (_val), (_mask)) 2002 2003 /* In Band MDIO - remote read ln 0 & 3 register */ 2004 #define READ_HL65_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val) \ 2005 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008116, (_val)) 2006 #define WRITE_HL65_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val) \ 2007 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008116, (_val)) 2008 #define MODIFY_HL65_XGXSBLK3_REMOTEREADX3r(_unit, _pc, _val, _mask) \ 2009 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008116, (_val), (_mask)) 2010 2011 /* In Band MDIO - status register */ 2012 #define READ_HL65_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val) \ 2013 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008117, (_val)) 2014 #define WRITE_HL65_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val) \ 2015 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008117, (_val)) 2016 #define MODIFY_HL65_XGXSBLK3_RX_INBANDMDIOSTATr(_unit, _pc, _val, _mask) \ 2017 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008117, (_val), (_mask)) 2018 2019 /* In Band MDIO - local IAC register */ 2020 #define READ_HL65_XGXSBLK3_LOCALIACr(_unit, _pc, _val) \ 2021 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008118, (_val)) 2022 #define WRITE_HL65_XGXSBLK3_LOCALIACr(_unit, _pc, _val) \ 2023 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008118, (_val)) 2024 #define MODIFY_HL65_XGXSBLK3_LOCALIACr(_unit, _pc, _val, _mask) \ 2025 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008118, (_val), (_mask)) 2026 2027 /* In Band MDIO - remote IAC register */ 2028 #define READ_HL65_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val) \ 2029 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008119, (_val)) 2030 #define WRITE_HL65_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val) \ 2031 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008119, (_val)) 2032 #define MODIFY_HL65_XGXSBLK3_REMOTEIACNr(_unit, _pc, _val, _mask) \ 2033 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008119, (_val), (_mask)) 2034 2035 2036 /**************************************************************************** 2037 * Hypercore_USER_GP_Status 2038 */ 2039 2040 /* Miscellaneous Rx status register */ 2041 #define READ_HL65_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val) \ 2042 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008120, (_val)) 2043 #define WRITE_HL65_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val) \ 2044 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008120, (_val)) 2045 #define MODIFY_HL65_GP_STATUS_MISCRXSTATUSr(_unit, _pc, _val, _mask) \ 2046 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008120, (_val), (_mask)) 2047 2048 /* XGXS status register */ 2049 #define READ_HL65_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val) \ 2050 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008121, (_val)) 2051 #define WRITE_HL65_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val) \ 2052 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008121, (_val)) 2053 #define MODIFY_HL65_GP_STATUS_XGXSSTATUS0r(_unit, _pc, _val, _mask) \ 2054 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008121, (_val), (_mask)) 2055 2056 /* XGXS status 1 register */ 2057 #define READ_HL65_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \ 2058 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008122, (_val)) 2059 #define WRITE_HL65_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val) \ 2060 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008122, (_val)) 2061 #define MODIFY_HL65_GP_STATUS_XGXSSTATUS1r(_unit, _pc, _val, _mask) \ 2062 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008122, (_val), (_mask)) 2063 2064 /* XGXS status 2 register */ 2065 #define READ_HL65_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val) \ 2066 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008123, (_val)) 2067 #define WRITE_HL65_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val) \ 2068 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008123, (_val)) 2069 #define MODIFY_HL65_GP_STATUS_XGXSSTATUS2r(_unit, _pc, _val, _mask) \ 2070 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008123, (_val), (_mask)) 2071 2072 /* 1000X status 1 register */ 2073 #define READ_HL65_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \ 2074 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008124, (_val)) 2075 #define WRITE_HL65_GP_STATUS_STATUS1000X1r(_unit, _pc, _val) \ 2076 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008124, (_val)) 2077 #define MODIFY_HL65_GP_STATUS_STATUS1000X1r(_unit, _pc, _val, _mask) \ 2078 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008124, (_val), (_mask)) 2079 2080 /* 1000X status 2 register */ 2081 #define READ_HL65_GP_STATUS_STATUS1000X2r(_unit, _pc, _val) \ 2082 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008125, (_val)) 2083 #define WRITE_HL65_GP_STATUS_STATUS1000X2r(_unit, _pc, _val) \ 2084 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008125, (_val)) 2085 #define MODIFY_HL65_GP_STATUS_STATUS1000X2r(_unit, _pc, _val, _mask) \ 2086 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008125, (_val), (_mask)) 2087 2088 /* 1000X status 3 register */ 2089 #define READ_HL65_GP_STATUS_STATUS1000X3r(_unit, _pc, _val) \ 2090 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008126, (_val)) 2091 #define WRITE_HL65_GP_STATUS_STATUS1000X3r(_unit, _pc, _val) \ 2092 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008126, (_val)) 2093 #define MODIFY_HL65_GP_STATUS_STATUS1000X3r(_unit, _pc, _val, _mask) \ 2094 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008126, (_val), (_mask)) 2095 2096 /* Test port out bits 15:0, tpout[15:0] */ 2097 #define READ_HL65_GP_STATUS_TPOUT_1r(_unit, _pc, _val) \ 2098 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008127, (_val)) 2099 #define WRITE_HL65_GP_STATUS_TPOUT_1r(_unit, _pc, _val) \ 2100 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008127, (_val)) 2101 #define MODIFY_HL65_GP_STATUS_TPOUT_1r(_unit, _pc, _val, _mask) \ 2102 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008127, (_val), (_mask)) 2103 2104 /* Test port out bits 23:8, tpout[23:8] */ 2105 #define READ_HL65_GP_STATUS_TPOUT_2r(_unit, _pc, _val) \ 2106 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008128, (_val)) 2107 #define WRITE_HL65_GP_STATUS_TPOUT_2r(_unit, _pc, _val) \ 2108 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008128, (_val)) 2109 #define MODIFY_HL65_GP_STATUS_TPOUT_2r(_unit, _pc, _val, _mask) \ 2110 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008128, (_val), (_mask)) 2111 2112 /* XGXS status 3 register */ 2113 #define READ_HL65_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \ 2114 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008129, (_val)) 2115 #define WRITE_HL65_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val) \ 2116 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008129, (_val)) 2117 #define MODIFY_HL65_GP_STATUS_XGXSSTATUS3r(_unit, _pc, _val, _mask) \ 2118 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008129, (_val), (_mask)) 2119 2120 /* 2500X status register */ 2121 #define READ_HL65_GP_STATUS_X2500STATUS1r(_unit, _pc, _val) \ 2122 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812a, (_val)) 2123 #define WRITE_HL65_GP_STATUS_X2500STATUS1r(_unit, _pc, _val) \ 2124 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812a, (_val)) 2125 #define MODIFY_HL65_GP_STATUS_X2500STATUS1r(_unit, _pc, _val, _mask) \ 2126 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812a, (_val), (_mask)) 2127 2128 /* CL73 AN status 1 register */ 2129 #define READ_HL65_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \ 2130 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812b, (_val)) 2131 #define WRITE_HL65_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val) \ 2132 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812b, (_val)) 2133 #define MODIFY_HL65_GP_STATUS_TOPANSTATUS1r(_unit, _pc, _val, _mask) \ 2134 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812b, (_val), (_mask)) 2135 2136 /* AN link partner user page 1 */ 2137 #define READ_HL65_GP_STATUS_LP_UP1r(_unit, _pc, _val) \ 2138 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812c, (_val)) 2139 #define WRITE_HL65_GP_STATUS_LP_UP1r(_unit, _pc, _val) \ 2140 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812c, (_val)) 2141 #define MODIFY_HL65_GP_STATUS_LP_UP1r(_unit, _pc, _val, _mask) \ 2142 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812c, (_val), (_mask)) 2143 2144 /* AN link partner user page 2 */ 2145 #define READ_HL65_GP_STATUS_LP_UP2r(_unit, _pc, _val) \ 2146 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812d, (_val)) 2147 #define WRITE_HL65_GP_STATUS_LP_UP2r(_unit, _pc, _val) \ 2148 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812d, (_val)) 2149 #define MODIFY_HL65_GP_STATUS_LP_UP2r(_unit, _pc, _val, _mask) \ 2150 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812d, (_val), (_mask)) 2151 2152 /* AN link partner user page 3 */ 2153 #define READ_HL65_GP_STATUS_LP_UP3r(_unit, _pc, _val) \ 2154 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000812e, (_val)) 2155 #define WRITE_HL65_GP_STATUS_LP_UP3r(_unit, _pc, _val) \ 2156 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000812e, (_val)) 2157 #define MODIFY_HL65_GP_STATUS_LP_UP3r(_unit, _pc, _val, _mask) \ 2158 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000812e, (_val), (_mask)) 2159 2160 2161 /**************************************************************************** 2162 * Hypercore_USER_AN73_pdet 2163 */ 2164 2165 /* 10G parallel detect status register */ 2166 #define READ_HL65_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val) \ 2167 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008130, (_val)) 2168 #define WRITE_HL65_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val) \ 2169 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008130, (_val)) 2170 #define MODIFY_HL65_AN73_PDET_PARDET10GSTATUSr(_unit, _pc, _val, _mask) \ 2171 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008130, (_val), (_mask)) 2172 2173 /* 10G parallel detect control register */ 2174 #define READ_HL65_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \ 2175 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008131, (_val)) 2176 #define WRITE_HL65_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val) \ 2177 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008131, (_val)) 2178 #define MODIFY_HL65_AN73_PDET_PARDET10GCONTROLr(_unit, _pc, _val, _mask) \ 2179 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008131, (_val), (_mask)) 2180 2181 /* 10G parallel detect signal detect register */ 2182 #define READ_HL65_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val) \ 2183 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008132, (_val)) 2184 #define WRITE_HL65_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val) \ 2185 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008132, (_val)) 2186 #define MODIFY_HL65_AN73_PDET_PARDET10GSIGDETr(_unit, _pc, _val, _mask) \ 2187 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008132, (_val), (_mask)) 2188 2189 /* 10G parallel detect link register */ 2190 #define READ_HL65_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val) \ 2191 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008133, (_val)) 2192 #define WRITE_HL65_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val) \ 2193 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008133, (_val)) 2194 #define MODIFY_HL65_AN73_PDET_PARDET10GLINKr(_unit, _pc, _val, _mask) \ 2195 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008133, (_val), (_mask)) 2196 2197 /* 10G parallel detect lost link register */ 2198 #define READ_HL65_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val) \ 2199 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008134, (_val)) 2200 #define WRITE_HL65_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val) \ 2201 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008134, (_val)) 2202 #define MODIFY_HL65_AN73_PDET_PARDET10GLOSTLINKr(_unit, _pc, _val, _mask) \ 2203 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008134, (_val), (_mask)) 2204 2205 /* Clause 73 auto-negotiation control register 1 */ 2206 #define READ_HL65_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val) \ 2207 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008135, (_val)) 2208 #define WRITE_HL65_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val) \ 2209 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008135, (_val)) 2210 #define MODIFY_HL65_AN73_PDET_CL73CONTROL1r(_unit, _pc, _val, _mask) \ 2211 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008135, (_val), (_mask)) 2212 2213 /* Clause 73 auto-negotiation control register 2 */ 2214 #define READ_HL65_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val) \ 2215 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008136, (_val)) 2216 #define WRITE_HL65_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val) \ 2217 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008136, (_val)) 2218 #define MODIFY_HL65_AN73_PDET_CL73CONTROL2r(_unit, _pc, _val, _mask) \ 2219 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008136, (_val), (_mask)) 2220 2221 /* Clause 73 auto-negotiation control register 3 */ 2222 #define READ_HL65_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val) \ 2223 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008137, (_val)) 2224 #define WRITE_HL65_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val) \ 2225 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008137, (_val)) 2226 #define MODIFY_HL65_AN73_PDET_CL73CONTROL3r(_unit, _pc, _val, _mask) \ 2227 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008137, (_val), (_mask)) 2228 2229 /* Clause 73 auto-negotiation control register 4 */ 2230 #define READ_HL65_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val) \ 2231 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008138, (_val)) 2232 #define WRITE_HL65_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val) \ 2233 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008138, (_val)) 2234 #define MODIFY_HL65_AN73_PDET_CL73CONTROL4r(_unit, _pc, _val, _mask) \ 2235 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008138, (_val), (_mask)) 2236 2237 /* Clause 73 auto-negotiation control register 5 */ 2238 #define READ_HL65_AN73_PDET_CL73CONTROL5r(_unit, _pc, _val) \ 2239 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008139, (_val)) 2240 #define WRITE_HL65_AN73_PDET_CL73CONTROL5r(_unit, _pc, _val) \ 2241 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008139, (_val)) 2242 #define MODIFY_HL65_AN73_PDET_CL73CONTROL5r(_unit, _pc, _val, _mask) \ 2243 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008139, (_val), (_mask)) 2244 2245 /* Clause 73 auto-negotiation control register 6 */ 2246 #define READ_HL65_AN73_PDET_CL73CONTROL6r(_unit, _pc, _val) \ 2247 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813a, (_val)) 2248 #define WRITE_HL65_AN73_PDET_CL73CONTROL6r(_unit, _pc, _val) \ 2249 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813a, (_val)) 2250 #define MODIFY_HL65_AN73_PDET_CL73CONTROL6r(_unit, _pc, _val, _mask) \ 2251 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813a, (_val), (_mask)) 2252 2253 /* Clause 73 auto-negotiation DME Timers Register */ 2254 #define READ_HL65_AN73_PDET_CL73DMETMRSr(_unit, _pc, _val) \ 2255 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813b, (_val)) 2256 #define WRITE_HL65_AN73_PDET_CL73DMETMRSr(_unit, _pc, _val) \ 2257 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813b, (_val)) 2258 #define MODIFY_HL65_AN73_PDET_CL73DMETMRSr(_unit, _pc, _val, _mask) \ 2259 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813b, (_val), (_mask)) 2260 2261 /* XGXS Status 4 Register */ 2262 #define READ_HL65_AN73_PDET_XGXSSTATUS4r(_unit, _pc, _val) \ 2263 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813c, (_val)) 2264 #define WRITE_HL65_AN73_PDET_XGXSSTATUS4r(_unit, _pc, _val) \ 2265 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813c, (_val)) 2266 #define MODIFY_HL65_AN73_PDET_XGXSSTATUS4r(_unit, _pc, _val, _mask) \ 2267 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813c, (_val), (_mask)) 2268 2269 /* XGXS Status 5 Register */ 2270 #define READ_HL65_AN73_PDET_XGXSSTATUS5r(_unit, _pc, _val) \ 2271 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813d, (_val)) 2272 #define WRITE_HL65_AN73_PDET_XGXSSTATUS5r(_unit, _pc, _val) \ 2273 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813d, (_val)) 2274 #define MODIFY_HL65_AN73_PDET_XGXSSTATUS5r(_unit, _pc, _val, _mask) \ 2275 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813d, (_val), (_mask)) 2276 2277 /* 10G parallel detect control 2 register */ 2278 #define READ_HL65_AN73_PDET_PARDET10GCONTROL2r(_unit, _pc, _val) \ 2279 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000813e, (_val)) 2280 #define WRITE_HL65_AN73_PDET_PARDET10GCONTROL2r(_unit, _pc, _val) \ 2281 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000813e, (_val)) 2282 #define MODIFY_HL65_AN73_PDET_PARDET10GCONTROL2r(_unit, _pc, _val, _mask) \ 2283 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000813e, (_val), (_mask)) 2284 2285 2286 /**************************************************************************** 2287 * Hypercore_USER_tx66_0 2288 */ 2289 2290 /* 64/66 Encoder Control Register */ 2291 #define READ_HL65_TX66_0_CONTROLr(_unit, _pc, _val) \ 2292 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008160, (_val)) 2293 #define WRITE_HL65_TX66_0_CONTROLr(_unit, _pc, _val) \ 2294 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008160, (_val)) 2295 #define MODIFY_HL65_TX66_0_CONTROLr(_unit, _pc, _val, _mask) \ 2296 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008160, (_val), (_mask)) 2297 2298 /* 64/66 Encoder Status Register */ 2299 #define READ_HL65_TX66_0_STATUSr(_unit, _pc, _val) \ 2300 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008161, (_val)) 2301 #define WRITE_HL65_TX66_0_STATUSr(_unit, _pc, _val) \ 2302 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008161, (_val)) 2303 #define MODIFY_HL65_TX66_0_STATUSr(_unit, _pc, _val, _mask) \ 2304 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008161, (_val), (_mask)) 2305 2306 2307 /**************************************************************************** 2308 * Hypercore_USER_tx66_1 2309 */ 2310 2311 /* 64/66 Encoder Control Register */ 2312 #define READ_HL65_TX66_1_CONTROLr(_unit, _pc, _val) \ 2313 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008170, (_val)) 2314 #define WRITE_HL65_TX66_1_CONTROLr(_unit, _pc, _val) \ 2315 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008170, (_val)) 2316 #define MODIFY_HL65_TX66_1_CONTROLr(_unit, _pc, _val, _mask) \ 2317 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008170, (_val), (_mask)) 2318 2319 /* 64/66 Encoder Status Register */ 2320 #define READ_HL65_TX66_1_STATUSr(_unit, _pc, _val) \ 2321 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008171, (_val)) 2322 #define WRITE_HL65_TX66_1_STATUSr(_unit, _pc, _val) \ 2323 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008171, (_val)) 2324 #define MODIFY_HL65_TX66_1_STATUSr(_unit, _pc, _val, _mask) \ 2325 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008171, (_val), (_mask)) 2326 2327 2328 /**************************************************************************** 2329 * Hypercore_USER_tx66_2 2330 */ 2331 2332 /* 64/66 Encoder Control Register */ 2333 #define READ_HL65_TX66_2_CONTROLr(_unit, _pc, _val) \ 2334 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008180, (_val)) 2335 #define WRITE_HL65_TX66_2_CONTROLr(_unit, _pc, _val) \ 2336 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008180, (_val)) 2337 #define MODIFY_HL65_TX66_2_CONTROLr(_unit, _pc, _val, _mask) \ 2338 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008180, (_val), (_mask)) 2339 2340 /* 64/66 Encoder Status Register */ 2341 #define READ_HL65_TX66_2_STATUSr(_unit, _pc, _val) \ 2342 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008181, (_val)) 2343 #define WRITE_HL65_TX66_2_STATUSr(_unit, _pc, _val) \ 2344 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008181, (_val)) 2345 #define MODIFY_HL65_TX66_2_STATUSr(_unit, _pc, _val, _mask) \ 2346 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008181, (_val), (_mask)) 2347 2348 2349 /**************************************************************************** 2350 * Hypercore_USER_tx66_3 2351 */ 2352 2353 /* 64/66 Encoder Control Register */ 2354 #define READ_HL65_TX66_3_CONTROLr(_unit, _pc, _val) \ 2355 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008190, (_val)) 2356 #define WRITE_HL65_TX66_3_CONTROLr(_unit, _pc, _val) \ 2357 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008190, (_val)) 2358 #define MODIFY_HL65_TX66_3_CONTROLr(_unit, _pc, _val, _mask) \ 2359 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008190, (_val), (_mask)) 2360 2361 /* 64/66 Encoder Status Register */ 2362 #define READ_HL65_TX66_3_STATUSr(_unit, _pc, _val) \ 2363 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008191, (_val)) 2364 #define WRITE_HL65_TX66_3_STATUSr(_unit, _pc, _val) \ 2365 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008191, (_val)) 2366 #define MODIFY_HL65_TX66_3_STATUSr(_unit, _pc, _val, _mask) \ 2367 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008191, (_val), (_mask)) 2368 2369 2370 /**************************************************************************** 2371 * Hypercore_USER_tx66_A 2372 */ 2373 2374 /* 64/66 Encoder Control Register */ 2375 #define READ_HL65_TX66_A_CONTROLr(_unit, _pc, _val) \ 2376 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081a0, (_val)) 2377 #define WRITE_HL65_TX66_A_CONTROLr(_unit, _pc, _val) \ 2378 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081a0, (_val)) 2379 #define MODIFY_HL65_TX66_A_CONTROLr(_unit, _pc, _val, _mask) \ 2380 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081a0, (_val), (_mask)) 2381 2382 /* 64/66 Encoder Status Register */ 2383 #define READ_HL65_TX66_A_STATUSr(_unit, _pc, _val) \ 2384 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081a1, (_val)) 2385 #define WRITE_HL65_TX66_A_STATUSr(_unit, _pc, _val) \ 2386 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081a1, (_val)) 2387 #define MODIFY_HL65_TX66_A_STATUSr(_unit, _pc, _val, _mask) \ 2388 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081a1, (_val), (_mask)) 2389 2390 2391 /**************************************************************************** 2392 * Hypercore_USER_rx66_0 2393 */ 2394 2395 /* 64/66 Decoder control register */ 2396 #define READ_HL65_RX66_0_CONTROLr(_unit, _pc, _val) \ 2397 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b0, (_val)) 2398 #define WRITE_HL65_RX66_0_CONTROLr(_unit, _pc, _val) \ 2399 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b0, (_val)) 2400 #define MODIFY_HL65_RX66_0_CONTROLr(_unit, _pc, _val, _mask) \ 2401 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b0, (_val), (_mask)) 2402 2403 /* 64/66 Decoder status register */ 2404 #define READ_HL65_RX66_0_STATUSr(_unit, _pc, _val) \ 2405 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b1, (_val)) 2406 #define WRITE_HL65_RX66_0_STATUSr(_unit, _pc, _val) \ 2407 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b1, (_val)) 2408 #define MODIFY_HL65_RX66_0_STATUSr(_unit, _pc, _val, _mask) \ 2409 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b1, (_val), (_mask)) 2410 2411 /* Sync code word bits 15:0 */ 2412 #define READ_HL65_RX66_0_SCW0r(_unit, _pc, _val) \ 2413 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b2, (_val)) 2414 #define WRITE_HL65_RX66_0_SCW0r(_unit, _pc, _val) \ 2415 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b2, (_val)) 2416 #define MODIFY_HL65_RX66_0_SCW0r(_unit, _pc, _val, _mask) \ 2417 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b2, (_val), (_mask)) 2418 2419 /* Sync code word bits 31;16 */ 2420 #define READ_HL65_RX66_0_SCW1r(_unit, _pc, _val) \ 2421 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b3, (_val)) 2422 #define WRITE_HL65_RX66_0_SCW1r(_unit, _pc, _val) \ 2423 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b3, (_val)) 2424 #define MODIFY_HL65_RX66_0_SCW1r(_unit, _pc, _val, _mask) \ 2425 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b3, (_val), (_mask)) 2426 2427 /* Sync code word bits 47:32 */ 2428 #define READ_HL65_RX66_0_SCW2r(_unit, _pc, _val) \ 2429 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b4, (_val)) 2430 #define WRITE_HL65_RX66_0_SCW2r(_unit, _pc, _val) \ 2431 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b4, (_val)) 2432 #define MODIFY_HL65_RX66_0_SCW2r(_unit, _pc, _val, _mask) \ 2433 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b4, (_val), (_mask)) 2434 2435 /* Sync code word bits 63:48 */ 2436 #define READ_HL65_RX66_0_SCW3r(_unit, _pc, _val) \ 2437 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b5, (_val)) 2438 #define WRITE_HL65_RX66_0_SCW3r(_unit, _pc, _val) \ 2439 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b5, (_val)) 2440 #define MODIFY_HL65_RX66_0_SCW3r(_unit, _pc, _val, _mask) \ 2441 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b5, (_val), (_mask)) 2442 2443 /* Sync code word mask bits 15:0 */ 2444 #define READ_HL65_RX66_0_SCW0_MASKr(_unit, _pc, _val) \ 2445 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b6, (_val)) 2446 #define WRITE_HL65_RX66_0_SCW0_MASKr(_unit, _pc, _val) \ 2447 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b6, (_val)) 2448 #define MODIFY_HL65_RX66_0_SCW0_MASKr(_unit, _pc, _val, _mask) \ 2449 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b6, (_val), (_mask)) 2450 2451 /* Sync code word mask bits 31;16 */ 2452 #define READ_HL65_RX66_0_SCW1_MASKr(_unit, _pc, _val) \ 2453 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b7, (_val)) 2454 #define WRITE_HL65_RX66_0_SCW1_MASKr(_unit, _pc, _val) \ 2455 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b7, (_val)) 2456 #define MODIFY_HL65_RX66_0_SCW1_MASKr(_unit, _pc, _val, _mask) \ 2457 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b7, (_val), (_mask)) 2458 2459 /* Sync code word mask bits 47:32 */ 2460 #define READ_HL65_RX66_0_SCW2_MASKr(_unit, _pc, _val) \ 2461 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b8, (_val)) 2462 #define WRITE_HL65_RX66_0_SCW2_MASKr(_unit, _pc, _val) \ 2463 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b8, (_val)) 2464 #define MODIFY_HL65_RX66_0_SCW2_MASKr(_unit, _pc, _val, _mask) \ 2465 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b8, (_val), (_mask)) 2466 2467 /* Sync code word mask bits 63:48 */ 2468 #define READ_HL65_RX66_0_SCW3_MASKr(_unit, _pc, _val) \ 2469 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081b9, (_val)) 2470 #define WRITE_HL65_RX66_0_SCW3_MASKr(_unit, _pc, _val) \ 2471 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081b9, (_val)) 2472 #define MODIFY_HL65_RX66_0_SCW3_MASKr(_unit, _pc, _val, _mask) \ 2473 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081b9, (_val), (_mask)) 2474 2475 /* Sync bits and sync mask bits */ 2476 #define READ_HL65_RX66_0_SYNCBITSr(_unit, _pc, _val) \ 2477 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ba, (_val)) 2478 #define WRITE_HL65_RX66_0_SYNCBITSr(_unit, _pc, _val) \ 2479 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ba, (_val)) 2480 #define MODIFY_HL65_RX66_0_SYNCBITSr(_unit, _pc, _val, _mask) \ 2481 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ba, (_val), (_mask)) 2482 2483 /* Sync code word statemachine control register */ 2484 #define READ_HL65_RX66_0_SCWCONTROLr(_unit, _pc, _val) \ 2485 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081bb, (_val)) 2486 #define WRITE_HL65_RX66_0_SCWCONTROLr(_unit, _pc, _val) \ 2487 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081bb, (_val)) 2488 #define MODIFY_HL65_RX66_0_SCWCONTROLr(_unit, _pc, _val, _mask) \ 2489 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081bb, (_val), (_mask)) 2490 2491 /* CW=SCW counter & skew position */ 2492 #define READ_HL65_RX66_0_SCWCOUNTr(_unit, _pc, _val) \ 2493 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081bd, (_val)) 2494 #define WRITE_HL65_RX66_0_SCWCOUNTr(_unit, _pc, _val) \ 2495 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081bd, (_val)) 2496 #define MODIFY_HL65_RX66_0_SCWCOUNTr(_unit, _pc, _val, _mask) \ 2497 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081bd, (_val), (_mask)) 2498 2499 /* scw & K-code group error counters */ 2500 #define READ_HL65_RX66_0_ERRCOUNTr(_unit, _pc, _val) \ 2501 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081be, (_val)) 2502 #define WRITE_HL65_RX66_0_ERRCOUNTr(_unit, _pc, _val) \ 2503 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081be, (_val)) 2504 #define MODIFY_HL65_RX66_0_ERRCOUNTr(_unit, _pc, _val, _mask) \ 2505 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081be, (_val), (_mask)) 2506 2507 2508 /**************************************************************************** 2509 * Hypercore_USER_rx66_1 2510 */ 2511 2512 /* 64/66 Decoder control register */ 2513 #define READ_HL65_RX66_1_CONTROLr(_unit, _pc, _val) \ 2514 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c0, (_val)) 2515 #define WRITE_HL65_RX66_1_CONTROLr(_unit, _pc, _val) \ 2516 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c0, (_val)) 2517 #define MODIFY_HL65_RX66_1_CONTROLr(_unit, _pc, _val, _mask) \ 2518 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c0, (_val), (_mask)) 2519 2520 /* 64/66 Decoder status register */ 2521 #define READ_HL65_RX66_1_STATUSr(_unit, _pc, _val) \ 2522 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c1, (_val)) 2523 #define WRITE_HL65_RX66_1_STATUSr(_unit, _pc, _val) \ 2524 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c1, (_val)) 2525 #define MODIFY_HL65_RX66_1_STATUSr(_unit, _pc, _val, _mask) \ 2526 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c1, (_val), (_mask)) 2527 2528 /* Sync code word bits 15:0 */ 2529 #define READ_HL65_RX66_1_SCW0r(_unit, _pc, _val) \ 2530 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c2, (_val)) 2531 #define WRITE_HL65_RX66_1_SCW0r(_unit, _pc, _val) \ 2532 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c2, (_val)) 2533 #define MODIFY_HL65_RX66_1_SCW0r(_unit, _pc, _val, _mask) \ 2534 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c2, (_val), (_mask)) 2535 2536 /* Sync code word bits 31;16 */ 2537 #define READ_HL65_RX66_1_SCW1r(_unit, _pc, _val) \ 2538 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c3, (_val)) 2539 #define WRITE_HL65_RX66_1_SCW1r(_unit, _pc, _val) \ 2540 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c3, (_val)) 2541 #define MODIFY_HL65_RX66_1_SCW1r(_unit, _pc, _val, _mask) \ 2542 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c3, (_val), (_mask)) 2543 2544 /* Sync code word bits 47:32 */ 2545 #define READ_HL65_RX66_1_SCW2r(_unit, _pc, _val) \ 2546 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c4, (_val)) 2547 #define WRITE_HL65_RX66_1_SCW2r(_unit, _pc, _val) \ 2548 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c4, (_val)) 2549 #define MODIFY_HL65_RX66_1_SCW2r(_unit, _pc, _val, _mask) \ 2550 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c4, (_val), (_mask)) 2551 2552 /* Sync code word bits 63:48 */ 2553 #define READ_HL65_RX66_1_SCW3r(_unit, _pc, _val) \ 2554 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c5, (_val)) 2555 #define WRITE_HL65_RX66_1_SCW3r(_unit, _pc, _val) \ 2556 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c5, (_val)) 2557 #define MODIFY_HL65_RX66_1_SCW3r(_unit, _pc, _val, _mask) \ 2558 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c5, (_val), (_mask)) 2559 2560 /* Sync code word mask bits 15:0 */ 2561 #define READ_HL65_RX66_1_SCW0_MASKr(_unit, _pc, _val) \ 2562 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c6, (_val)) 2563 #define WRITE_HL65_RX66_1_SCW0_MASKr(_unit, _pc, _val) \ 2564 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c6, (_val)) 2565 #define MODIFY_HL65_RX66_1_SCW0_MASKr(_unit, _pc, _val, _mask) \ 2566 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c6, (_val), (_mask)) 2567 2568 /* Sync code word mask bits 31;16 */ 2569 #define READ_HL65_RX66_1_SCW1_MASKr(_unit, _pc, _val) \ 2570 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c7, (_val)) 2571 #define WRITE_HL65_RX66_1_SCW1_MASKr(_unit, _pc, _val) \ 2572 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c7, (_val)) 2573 #define MODIFY_HL65_RX66_1_SCW1_MASKr(_unit, _pc, _val, _mask) \ 2574 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c7, (_val), (_mask)) 2575 2576 /* Sync code word mask bits 47:32 */ 2577 #define READ_HL65_RX66_1_SCW2_MASKr(_unit, _pc, _val) \ 2578 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c8, (_val)) 2579 #define WRITE_HL65_RX66_1_SCW2_MASKr(_unit, _pc, _val) \ 2580 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c8, (_val)) 2581 #define MODIFY_HL65_RX66_1_SCW2_MASKr(_unit, _pc, _val, _mask) \ 2582 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c8, (_val), (_mask)) 2583 2584 /* Sync code word mask bits 63:48 */ 2585 #define READ_HL65_RX66_1_SCW3_MASKr(_unit, _pc, _val) \ 2586 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081c9, (_val)) 2587 #define WRITE_HL65_RX66_1_SCW3_MASKr(_unit, _pc, _val) \ 2588 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081c9, (_val)) 2589 #define MODIFY_HL65_RX66_1_SCW3_MASKr(_unit, _pc, _val, _mask) \ 2590 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081c9, (_val), (_mask)) 2591 2592 /* Sync bits and sync mask bits */ 2593 #define READ_HL65_RX66_1_SYNCBITSr(_unit, _pc, _val) \ 2594 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ca, (_val)) 2595 #define WRITE_HL65_RX66_1_SYNCBITSr(_unit, _pc, _val) \ 2596 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ca, (_val)) 2597 #define MODIFY_HL65_RX66_1_SYNCBITSr(_unit, _pc, _val, _mask) \ 2598 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ca, (_val), (_mask)) 2599 2600 /* Sync code word statemachine control register */ 2601 #define READ_HL65_RX66_1_SCWCONTROLr(_unit, _pc, _val) \ 2602 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081cb, (_val)) 2603 #define WRITE_HL65_RX66_1_SCWCONTROLr(_unit, _pc, _val) \ 2604 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081cb, (_val)) 2605 #define MODIFY_HL65_RX66_1_SCWCONTROLr(_unit, _pc, _val, _mask) \ 2606 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081cb, (_val), (_mask)) 2607 2608 /* CW=SCW counter & skew position */ 2609 #define READ_HL65_RX66_1_SCWCOUNTr(_unit, _pc, _val) \ 2610 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081cd, (_val)) 2611 #define WRITE_HL65_RX66_1_SCWCOUNTr(_unit, _pc, _val) \ 2612 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081cd, (_val)) 2613 #define MODIFY_HL65_RX66_1_SCWCOUNTr(_unit, _pc, _val, _mask) \ 2614 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081cd, (_val), (_mask)) 2615 2616 /* scw & K-code group error counters */ 2617 #define READ_HL65_RX66_1_ERRCOUNTr(_unit, _pc, _val) \ 2618 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ce, (_val)) 2619 #define WRITE_HL65_RX66_1_ERRCOUNTr(_unit, _pc, _val) \ 2620 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ce, (_val)) 2621 #define MODIFY_HL65_RX66_1_ERRCOUNTr(_unit, _pc, _val, _mask) \ 2622 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ce, (_val), (_mask)) 2623 2624 2625 /**************************************************************************** 2626 * Hypercore_USER_rx66_2 2627 */ 2628 2629 /* 64/66 Decoder control register */ 2630 #define READ_HL65_RX66_2_CONTROLr(_unit, _pc, _val) \ 2631 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d0, (_val)) 2632 #define WRITE_HL65_RX66_2_CONTROLr(_unit, _pc, _val) \ 2633 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d0, (_val)) 2634 #define MODIFY_HL65_RX66_2_CONTROLr(_unit, _pc, _val, _mask) \ 2635 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d0, (_val), (_mask)) 2636 2637 /* 64/66 Decoder status register */ 2638 #define READ_HL65_RX66_2_STATUSr(_unit, _pc, _val) \ 2639 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d1, (_val)) 2640 #define WRITE_HL65_RX66_2_STATUSr(_unit, _pc, _val) \ 2641 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d1, (_val)) 2642 #define MODIFY_HL65_RX66_2_STATUSr(_unit, _pc, _val, _mask) \ 2643 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d1, (_val), (_mask)) 2644 2645 /* Sync code word bits 15:0 */ 2646 #define READ_HL65_RX66_2_SCW0r(_unit, _pc, _val) \ 2647 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d2, (_val)) 2648 #define WRITE_HL65_RX66_2_SCW0r(_unit, _pc, _val) \ 2649 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d2, (_val)) 2650 #define MODIFY_HL65_RX66_2_SCW0r(_unit, _pc, _val, _mask) \ 2651 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d2, (_val), (_mask)) 2652 2653 /* Sync code word bits 31;16 */ 2654 #define READ_HL65_RX66_2_SCW1r(_unit, _pc, _val) \ 2655 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d3, (_val)) 2656 #define WRITE_HL65_RX66_2_SCW1r(_unit, _pc, _val) \ 2657 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d3, (_val)) 2658 #define MODIFY_HL65_RX66_2_SCW1r(_unit, _pc, _val, _mask) \ 2659 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d3, (_val), (_mask)) 2660 2661 /* Sync code word bits 47:32 */ 2662 #define READ_HL65_RX66_2_SCW2r(_unit, _pc, _val) \ 2663 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d4, (_val)) 2664 #define WRITE_HL65_RX66_2_SCW2r(_unit, _pc, _val) \ 2665 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d4, (_val)) 2666 #define MODIFY_HL65_RX66_2_SCW2r(_unit, _pc, _val, _mask) \ 2667 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d4, (_val), (_mask)) 2668 2669 /* Sync code word bits 63:48 */ 2670 #define READ_HL65_RX66_2_SCW3r(_unit, _pc, _val) \ 2671 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d5, (_val)) 2672 #define WRITE_HL65_RX66_2_SCW3r(_unit, _pc, _val) \ 2673 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d5, (_val)) 2674 #define MODIFY_HL65_RX66_2_SCW3r(_unit, _pc, _val, _mask) \ 2675 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d5, (_val), (_mask)) 2676 2677 /* Sync code word mask bits 15:0 */ 2678 #define READ_HL65_RX66_2_SCW0_MASKr(_unit, _pc, _val) \ 2679 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d6, (_val)) 2680 #define WRITE_HL65_RX66_2_SCW0_MASKr(_unit, _pc, _val) \ 2681 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d6, (_val)) 2682 #define MODIFY_HL65_RX66_2_SCW0_MASKr(_unit, _pc, _val, _mask) \ 2683 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d6, (_val), (_mask)) 2684 2685 /* Sync code word mask bits 31;16 */ 2686 #define READ_HL65_RX66_2_SCW1_MASKr(_unit, _pc, _val) \ 2687 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d7, (_val)) 2688 #define WRITE_HL65_RX66_2_SCW1_MASKr(_unit, _pc, _val) \ 2689 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d7, (_val)) 2690 #define MODIFY_HL65_RX66_2_SCW1_MASKr(_unit, _pc, _val, _mask) \ 2691 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d7, (_val), (_mask)) 2692 2693 /* Sync code word mask bits 47:32 */ 2694 #define READ_HL65_RX66_2_SCW2_MASKr(_unit, _pc, _val) \ 2695 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d8, (_val)) 2696 #define WRITE_HL65_RX66_2_SCW2_MASKr(_unit, _pc, _val) \ 2697 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d8, (_val)) 2698 #define MODIFY_HL65_RX66_2_SCW2_MASKr(_unit, _pc, _val, _mask) \ 2699 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d8, (_val), (_mask)) 2700 2701 /* Sync code word mask bits 63:48 */ 2702 #define READ_HL65_RX66_2_SCW3_MASKr(_unit, _pc, _val) \ 2703 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081d9, (_val)) 2704 #define WRITE_HL65_RX66_2_SCW3_MASKr(_unit, _pc, _val) \ 2705 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081d9, (_val)) 2706 #define MODIFY_HL65_RX66_2_SCW3_MASKr(_unit, _pc, _val, _mask) \ 2707 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081d9, (_val), (_mask)) 2708 2709 /* Sync bits and sync mask bits */ 2710 #define READ_HL65_RX66_2_SYNCBITSr(_unit, _pc, _val) \ 2711 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081da, (_val)) 2712 #define WRITE_HL65_RX66_2_SYNCBITSr(_unit, _pc, _val) \ 2713 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081da, (_val)) 2714 #define MODIFY_HL65_RX66_2_SYNCBITSr(_unit, _pc, _val, _mask) \ 2715 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081da, (_val), (_mask)) 2716 2717 /* Sync code word statemachine control register */ 2718 #define READ_HL65_RX66_2_SCWCONTROLr(_unit, _pc, _val) \ 2719 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081db, (_val)) 2720 #define WRITE_HL65_RX66_2_SCWCONTROLr(_unit, _pc, _val) \ 2721 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081db, (_val)) 2722 #define MODIFY_HL65_RX66_2_SCWCONTROLr(_unit, _pc, _val, _mask) \ 2723 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081db, (_val), (_mask)) 2724 2725 /* CW=SCW counter & skew position */ 2726 #define READ_HL65_RX66_2_SCWCOUNTr(_unit, _pc, _val) \ 2727 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081dd, (_val)) 2728 #define WRITE_HL65_RX66_2_SCWCOUNTr(_unit, _pc, _val) \ 2729 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081dd, (_val)) 2730 #define MODIFY_HL65_RX66_2_SCWCOUNTr(_unit, _pc, _val, _mask) \ 2731 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081dd, (_val), (_mask)) 2732 2733 /* scw & K-code group error counters */ 2734 #define READ_HL65_RX66_2_ERRCOUNTr(_unit, _pc, _val) \ 2735 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081de, (_val)) 2736 #define WRITE_HL65_RX66_2_ERRCOUNTr(_unit, _pc, _val) \ 2737 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081de, (_val)) 2738 #define MODIFY_HL65_RX66_2_ERRCOUNTr(_unit, _pc, _val, _mask) \ 2739 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081de, (_val), (_mask)) 2740 2741 2742 /**************************************************************************** 2743 * Hypercore_USER_rx66_3 2744 */ 2745 2746 /* 64/66 Decoder control register */ 2747 #define READ_HL65_RX66_3_CONTROLr(_unit, _pc, _val) \ 2748 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e0, (_val)) 2749 #define WRITE_HL65_RX66_3_CONTROLr(_unit, _pc, _val) \ 2750 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e0, (_val)) 2751 #define MODIFY_HL65_RX66_3_CONTROLr(_unit, _pc, _val, _mask) \ 2752 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e0, (_val), (_mask)) 2753 2754 /* 64/66 Decoder status register */ 2755 #define READ_HL65_RX66_3_STATUSr(_unit, _pc, _val) \ 2756 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e1, (_val)) 2757 #define WRITE_HL65_RX66_3_STATUSr(_unit, _pc, _val) \ 2758 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e1, (_val)) 2759 #define MODIFY_HL65_RX66_3_STATUSr(_unit, _pc, _val, _mask) \ 2760 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e1, (_val), (_mask)) 2761 2762 /* Sync code word bits 15:0 */ 2763 #define READ_HL65_RX66_3_SCW0r(_unit, _pc, _val) \ 2764 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e2, (_val)) 2765 #define WRITE_HL65_RX66_3_SCW0r(_unit, _pc, _val) \ 2766 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e2, (_val)) 2767 #define MODIFY_HL65_RX66_3_SCW0r(_unit, _pc, _val, _mask) \ 2768 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e2, (_val), (_mask)) 2769 2770 /* Sync code word bits 31;16 */ 2771 #define READ_HL65_RX66_3_SCW1r(_unit, _pc, _val) \ 2772 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e3, (_val)) 2773 #define WRITE_HL65_RX66_3_SCW1r(_unit, _pc, _val) \ 2774 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e3, (_val)) 2775 #define MODIFY_HL65_RX66_3_SCW1r(_unit, _pc, _val, _mask) \ 2776 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e3, (_val), (_mask)) 2777 2778 /* Sync code word bits 47:32 */ 2779 #define READ_HL65_RX66_3_SCW2r(_unit, _pc, _val) \ 2780 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e4, (_val)) 2781 #define WRITE_HL65_RX66_3_SCW2r(_unit, _pc, _val) \ 2782 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e4, (_val)) 2783 #define MODIFY_HL65_RX66_3_SCW2r(_unit, _pc, _val, _mask) \ 2784 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e4, (_val), (_mask)) 2785 2786 /* Sync code word bits 63:48 */ 2787 #define READ_HL65_RX66_3_SCW3r(_unit, _pc, _val) \ 2788 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e5, (_val)) 2789 #define WRITE_HL65_RX66_3_SCW3r(_unit, _pc, _val) \ 2790 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e5, (_val)) 2791 #define MODIFY_HL65_RX66_3_SCW3r(_unit, _pc, _val, _mask) \ 2792 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e5, (_val), (_mask)) 2793 2794 /* Sync code word mask bits 15:0 */ 2795 #define READ_HL65_RX66_3_SCW0_MASKr(_unit, _pc, _val) \ 2796 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e6, (_val)) 2797 #define WRITE_HL65_RX66_3_SCW0_MASKr(_unit, _pc, _val) \ 2798 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e6, (_val)) 2799 #define MODIFY_HL65_RX66_3_SCW0_MASKr(_unit, _pc, _val, _mask) \ 2800 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e6, (_val), (_mask)) 2801 2802 /* Sync code word mask bits 31;16 */ 2803 #define READ_HL65_RX66_3_SCW1_MASKr(_unit, _pc, _val) \ 2804 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e7, (_val)) 2805 #define WRITE_HL65_RX66_3_SCW1_MASKr(_unit, _pc, _val) \ 2806 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e7, (_val)) 2807 #define MODIFY_HL65_RX66_3_SCW1_MASKr(_unit, _pc, _val, _mask) \ 2808 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e7, (_val), (_mask)) 2809 2810 /* Sync code word mask bits 47:32 */ 2811 #define READ_HL65_RX66_3_SCW2_MASKr(_unit, _pc, _val) \ 2812 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e8, (_val)) 2813 #define WRITE_HL65_RX66_3_SCW2_MASKr(_unit, _pc, _val) \ 2814 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e8, (_val)) 2815 #define MODIFY_HL65_RX66_3_SCW2_MASKr(_unit, _pc, _val, _mask) \ 2816 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e8, (_val), (_mask)) 2817 2818 /* Sync code word mask bits 63:48 */ 2819 #define READ_HL65_RX66_3_SCW3_MASKr(_unit, _pc, _val) \ 2820 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081e9, (_val)) 2821 #define WRITE_HL65_RX66_3_SCW3_MASKr(_unit, _pc, _val) \ 2822 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081e9, (_val)) 2823 #define MODIFY_HL65_RX66_3_SCW3_MASKr(_unit, _pc, _val, _mask) \ 2824 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081e9, (_val), (_mask)) 2825 2826 /* Sync bits and sync mask bits */ 2827 #define READ_HL65_RX66_3_SYNCBITSr(_unit, _pc, _val) \ 2828 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ea, (_val)) 2829 #define WRITE_HL65_RX66_3_SYNCBITSr(_unit, _pc, _val) \ 2830 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ea, (_val)) 2831 #define MODIFY_HL65_RX66_3_SYNCBITSr(_unit, _pc, _val, _mask) \ 2832 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ea, (_val), (_mask)) 2833 2834 /* Sync code word statemachine control register */ 2835 #define READ_HL65_RX66_3_SCWCONTROLr(_unit, _pc, _val) \ 2836 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081eb, (_val)) 2837 #define WRITE_HL65_RX66_3_SCWCONTROLr(_unit, _pc, _val) \ 2838 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081eb, (_val)) 2839 #define MODIFY_HL65_RX66_3_SCWCONTROLr(_unit, _pc, _val, _mask) \ 2840 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081eb, (_val), (_mask)) 2841 2842 /* CW=SCW counter & skew position */ 2843 #define READ_HL65_RX66_3_SCWCOUNTr(_unit, _pc, _val) \ 2844 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ed, (_val)) 2845 #define WRITE_HL65_RX66_3_SCWCOUNTr(_unit, _pc, _val) \ 2846 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ed, (_val)) 2847 #define MODIFY_HL65_RX66_3_SCWCOUNTr(_unit, _pc, _val, _mask) \ 2848 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ed, (_val), (_mask)) 2849 2850 /* scw & K-code group error counters */ 2851 #define READ_HL65_RX66_3_ERRCOUNTr(_unit, _pc, _val) \ 2852 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081ee, (_val)) 2853 #define WRITE_HL65_RX66_3_ERRCOUNTr(_unit, _pc, _val) \ 2854 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081ee, (_val)) 2855 #define MODIFY_HL65_RX66_3_ERRCOUNTr(_unit, _pc, _val, _mask) \ 2856 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081ee, (_val), (_mask)) 2857 2858 2859 /**************************************************************************** 2860 * Hypercore_USER_rx66_A 2861 */ 2862 2863 /* 64/66 Decoder control register */ 2864 #define READ_HL65_RX66_A_CONTROLr(_unit, _pc, _val) \ 2865 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f0, (_val)) 2866 #define WRITE_HL65_RX66_A_CONTROLr(_unit, _pc, _val) \ 2867 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f0, (_val)) 2868 #define MODIFY_HL65_RX66_A_CONTROLr(_unit, _pc, _val, _mask) \ 2869 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f0, (_val), (_mask)) 2870 2871 /* 64/66 Decoder status register */ 2872 #define READ_HL65_RX66_A_STATUSr(_unit, _pc, _val) \ 2873 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f1, (_val)) 2874 #define WRITE_HL65_RX66_A_STATUSr(_unit, _pc, _val) \ 2875 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f1, (_val)) 2876 #define MODIFY_HL65_RX66_A_STATUSr(_unit, _pc, _val, _mask) \ 2877 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f1, (_val), (_mask)) 2878 2879 /* Sync code word bits 15:0 */ 2880 #define READ_HL65_RX66_A_SCW0r(_unit, _pc, _val) \ 2881 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f2, (_val)) 2882 #define WRITE_HL65_RX66_A_SCW0r(_unit, _pc, _val) \ 2883 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f2, (_val)) 2884 #define MODIFY_HL65_RX66_A_SCW0r(_unit, _pc, _val, _mask) \ 2885 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f2, (_val), (_mask)) 2886 2887 /* Sync code word bits 31;16 */ 2888 #define READ_HL65_RX66_A_SCW1r(_unit, _pc, _val) \ 2889 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f3, (_val)) 2890 #define WRITE_HL65_RX66_A_SCW1r(_unit, _pc, _val) \ 2891 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f3, (_val)) 2892 #define MODIFY_HL65_RX66_A_SCW1r(_unit, _pc, _val, _mask) \ 2893 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f3, (_val), (_mask)) 2894 2895 /* Sync code word bits 47:32 */ 2896 #define READ_HL65_RX66_A_SCW2r(_unit, _pc, _val) \ 2897 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f4, (_val)) 2898 #define WRITE_HL65_RX66_A_SCW2r(_unit, _pc, _val) \ 2899 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f4, (_val)) 2900 #define MODIFY_HL65_RX66_A_SCW2r(_unit, _pc, _val, _mask) \ 2901 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f4, (_val), (_mask)) 2902 2903 /* Sync code word bits 63:48 */ 2904 #define READ_HL65_RX66_A_SCW3r(_unit, _pc, _val) \ 2905 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f5, (_val)) 2906 #define WRITE_HL65_RX66_A_SCW3r(_unit, _pc, _val) \ 2907 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f5, (_val)) 2908 #define MODIFY_HL65_RX66_A_SCW3r(_unit, _pc, _val, _mask) \ 2909 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f5, (_val), (_mask)) 2910 2911 /* Sync code word mask bits 15:0 */ 2912 #define READ_HL65_RX66_A_SCW0_MASKr(_unit, _pc, _val) \ 2913 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f6, (_val)) 2914 #define WRITE_HL65_RX66_A_SCW0_MASKr(_unit, _pc, _val) \ 2915 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f6, (_val)) 2916 #define MODIFY_HL65_RX66_A_SCW0_MASKr(_unit, _pc, _val, _mask) \ 2917 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f6, (_val), (_mask)) 2918 2919 /* Sync code word mask bits 31;16 */ 2920 #define READ_HL65_RX66_A_SCW1_MASKr(_unit, _pc, _val) \ 2921 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f7, (_val)) 2922 #define WRITE_HL65_RX66_A_SCW1_MASKr(_unit, _pc, _val) \ 2923 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f7, (_val)) 2924 #define MODIFY_HL65_RX66_A_SCW1_MASKr(_unit, _pc, _val, _mask) \ 2925 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f7, (_val), (_mask)) 2926 2927 /* Sync code word mask bits 47:32 */ 2928 #define READ_HL65_RX66_A_SCW2_MASKr(_unit, _pc, _val) \ 2929 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f8, (_val)) 2930 #define WRITE_HL65_RX66_A_SCW2_MASKr(_unit, _pc, _val) \ 2931 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f8, (_val)) 2932 #define MODIFY_HL65_RX66_A_SCW2_MASKr(_unit, _pc, _val, _mask) \ 2933 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f8, (_val), (_mask)) 2934 2935 /* Sync code word mask bits 63:48 */ 2936 #define READ_HL65_RX66_A_SCW3_MASKr(_unit, _pc, _val) \ 2937 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081f9, (_val)) 2938 #define WRITE_HL65_RX66_A_SCW3_MASKr(_unit, _pc, _val) \ 2939 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081f9, (_val)) 2940 #define MODIFY_HL65_RX66_A_SCW3_MASKr(_unit, _pc, _val, _mask) \ 2941 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081f9, (_val), (_mask)) 2942 2943 /* Sync bits and sync mask bits */ 2944 #define READ_HL65_RX66_A_SYNCBITSr(_unit, _pc, _val) \ 2945 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081fa, (_val)) 2946 #define WRITE_HL65_RX66_A_SYNCBITSr(_unit, _pc, _val) \ 2947 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081fa, (_val)) 2948 #define MODIFY_HL65_RX66_A_SYNCBITSr(_unit, _pc, _val, _mask) \ 2949 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fa, (_val), (_mask)) 2950 2951 /* Sync code word statemachine control register */ 2952 #define READ_HL65_RX66_A_SCWCONTROLr(_unit, _pc, _val) \ 2953 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081fb, (_val)) 2954 #define WRITE_HL65_RX66_A_SCWCONTROLr(_unit, _pc, _val) \ 2955 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081fb, (_val)) 2956 #define MODIFY_HL65_RX66_A_SCWCONTROLr(_unit, _pc, _val, _mask) \ 2957 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fb, (_val), (_mask)) 2958 2959 /* CW=SCW counter & skew position */ 2960 #define READ_HL65_RX66_A_SCWCOUNTr(_unit, _pc, _val) \ 2961 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081fd, (_val)) 2962 #define WRITE_HL65_RX66_A_SCWCOUNTr(_unit, _pc, _val) \ 2963 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081fd, (_val)) 2964 #define MODIFY_HL65_RX66_A_SCWCOUNTr(_unit, _pc, _val, _mask) \ 2965 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fd, (_val), (_mask)) 2966 2967 /* scw & K-code group error counters */ 2968 #define READ_HL65_RX66_A_ERRCOUNTr(_unit, _pc, _val) \ 2969 HL65_REG_READ((_unit), (_pc), 0x00, 0x000081fe, (_val)) 2970 #define WRITE_HL65_RX66_A_ERRCOUNTr(_unit, _pc, _val) \ 2971 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000081fe, (_val)) 2972 #define MODIFY_HL65_RX66_A_ERRCOUNTr(_unit, _pc, _val, _mask) \ 2973 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000081fe, (_val), (_mask)) 2974 2975 2976 /**************************************************************************** 2977 * Hypercore_USER_Dsc1b0 2978 */ 2979 2980 /* CDR Control 0 Register */ 2981 #define READ_HL65_DSC1B0_CDR_CTRL0r(_unit, _pc, _val) \ 2982 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008210, (_val)) 2983 #define WRITE_HL65_DSC1B0_CDR_CTRL0r(_unit, _pc, _val) \ 2984 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008210, (_val)) 2985 #define MODIFY_HL65_DSC1B0_CDR_CTRL0r(_unit, _pc, _val, _mask) \ 2986 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008210, (_val), (_mask)) 2987 2988 /* CDR Control 1 Register */ 2989 #define READ_HL65_DSC1B0_CDR_CTRL1r(_unit, _pc, _val) \ 2990 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008211, (_val)) 2991 #define WRITE_HL65_DSC1B0_CDR_CTRL1r(_unit, _pc, _val) \ 2992 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008211, (_val)) 2993 #define MODIFY_HL65_DSC1B0_CDR_CTRL1r(_unit, _pc, _val, _mask) \ 2994 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008211, (_val), (_mask)) 2995 2996 /* CDR Control 2 Register */ 2997 #define READ_HL65_DSC1B0_CDR_CTRL2r(_unit, _pc, _val) \ 2998 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008212, (_val)) 2999 #define WRITE_HL65_DSC1B0_CDR_CTRL2r(_unit, _pc, _val) \ 3000 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008212, (_val)) 3001 #define MODIFY_HL65_DSC1B0_CDR_CTRL2r(_unit, _pc, _val, _mask) \ 3002 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008212, (_val), (_mask)) 3003 3004 /* Phase Interpolator Control 0 Register */ 3005 #define READ_HL65_DSC1B0_PI_CTRL0r(_unit, _pc, _val) \ 3006 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008213, (_val)) 3007 #define WRITE_HL65_DSC1B0_PI_CTRL0r(_unit, _pc, _val) \ 3008 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008213, (_val)) 3009 #define MODIFY_HL65_DSC1B0_PI_CTRL0r(_unit, _pc, _val, _mask) \ 3010 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008213, (_val), (_mask)) 3011 3012 /* DFE VGA Control 0 Register */ 3013 #define READ_HL65_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3014 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008214, (_val)) 3015 #define WRITE_HL65_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3016 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008214, (_val)) 3017 #define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \ 3018 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008214, (_val), (_mask)) 3019 3020 /* DFE VGA Control 1 Register */ 3021 #define READ_HL65_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3022 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008215, (_val)) 3023 #define WRITE_HL65_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3024 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008215, (_val)) 3025 #define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \ 3026 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008215, (_val), (_mask)) 3027 3028 /* DFE VGA Control 2 Register */ 3029 #define READ_HL65_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3030 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008216, (_val)) 3031 #define WRITE_HL65_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3032 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008216, (_val)) 3033 #define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \ 3034 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008216, (_val), (_mask)) 3035 3036 /* DFE VGA Control 3 Register */ 3037 #define READ_HL65_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3038 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008217, (_val)) 3039 #define WRITE_HL65_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3040 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008217, (_val)) 3041 #define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \ 3042 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008217, (_val), (_mask)) 3043 3044 /* DFE VGA Control 4 Register */ 3045 #define READ_HL65_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3046 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008218, (_val)) 3047 #define WRITE_HL65_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3048 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008218, (_val)) 3049 #define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \ 3050 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008218, (_val), (_mask)) 3051 3052 /* DFE VGA Control 5 Register */ 3053 #define READ_HL65_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3054 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008219, (_val)) 3055 #define WRITE_HL65_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3056 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008219, (_val)) 3057 #define MODIFY_HL65_DSC1B0_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \ 3058 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008219, (_val), (_mask)) 3059 3060 /* DSC Analog Control 0 Register */ 3061 #define READ_HL65_DSC1B0_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3062 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821a, (_val)) 3063 #define WRITE_HL65_DSC1B0_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3064 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821a, (_val)) 3065 #define MODIFY_HL65_DSC1B0_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \ 3066 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821a, (_val), (_mask)) 3067 3068 /* DSC Analog Control 1 Register */ 3069 #define READ_HL65_DSC1B0_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3070 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821b, (_val)) 3071 #define WRITE_HL65_DSC1B0_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3072 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821b, (_val)) 3073 #define MODIFY_HL65_DSC1B0_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \ 3074 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821b, (_val), (_mask)) 3075 3076 /* DSC Analog Control 2 Register */ 3077 #define READ_HL65_DSC1B0_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3078 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821c, (_val)) 3079 #define WRITE_HL65_DSC1B0_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3080 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821c, (_val)) 3081 #define MODIFY_HL65_DSC1B0_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \ 3082 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821c, (_val), (_mask)) 3083 3084 /* DSC 100FX Control Register */ 3085 #define READ_HL65_DSC1B0_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3086 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821d, (_val)) 3087 #define WRITE_HL65_DSC1B0_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3088 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821d, (_val)) 3089 #define MODIFY_HL65_DSC1B0_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \ 3090 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821d, (_val), (_mask)) 3091 3092 /* DSC Analog Control 3 Register */ 3093 #define READ_HL65_DSC1B0_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3094 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000821e, (_val)) 3095 #define WRITE_HL65_DSC1B0_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3096 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000821e, (_val)) 3097 #define MODIFY_HL65_DSC1B0_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \ 3098 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000821e, (_val), (_mask)) 3099 3100 3101 /**************************************************************************** 3102 * Hypercore_USER_Dsc1b1 3103 */ 3104 3105 /* CDR Control 0 Register */ 3106 #define READ_HL65_DSC1B1_CDR_CTRL0r(_unit, _pc, _val) \ 3107 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008220, (_val)) 3108 #define WRITE_HL65_DSC1B1_CDR_CTRL0r(_unit, _pc, _val) \ 3109 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008220, (_val)) 3110 #define MODIFY_HL65_DSC1B1_CDR_CTRL0r(_unit, _pc, _val, _mask) \ 3111 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008220, (_val), (_mask)) 3112 3113 /* CDR Control 1 Register */ 3114 #define READ_HL65_DSC1B1_CDR_CTRL1r(_unit, _pc, _val) \ 3115 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008221, (_val)) 3116 #define WRITE_HL65_DSC1B1_CDR_CTRL1r(_unit, _pc, _val) \ 3117 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008221, (_val)) 3118 #define MODIFY_HL65_DSC1B1_CDR_CTRL1r(_unit, _pc, _val, _mask) \ 3119 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008221, (_val), (_mask)) 3120 3121 /* CDR Control 2 Register */ 3122 #define READ_HL65_DSC1B1_CDR_CTRL2r(_unit, _pc, _val) \ 3123 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008222, (_val)) 3124 #define WRITE_HL65_DSC1B1_CDR_CTRL2r(_unit, _pc, _val) \ 3125 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008222, (_val)) 3126 #define MODIFY_HL65_DSC1B1_CDR_CTRL2r(_unit, _pc, _val, _mask) \ 3127 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008222, (_val), (_mask)) 3128 3129 /* Phase Interpolator Control 0 Register */ 3130 #define READ_HL65_DSC1B1_PI_CTRL0r(_unit, _pc, _val) \ 3131 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008223, (_val)) 3132 #define WRITE_HL65_DSC1B1_PI_CTRL0r(_unit, _pc, _val) \ 3133 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008223, (_val)) 3134 #define MODIFY_HL65_DSC1B1_PI_CTRL0r(_unit, _pc, _val, _mask) \ 3135 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008223, (_val), (_mask)) 3136 3137 /* DFE VGA Control 0 Register */ 3138 #define READ_HL65_DSC1B1_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3139 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008224, (_val)) 3140 #define WRITE_HL65_DSC1B1_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3141 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008224, (_val)) 3142 #define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \ 3143 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008224, (_val), (_mask)) 3144 3145 /* DFE VGA Control 1 Register */ 3146 #define READ_HL65_DSC1B1_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3147 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008225, (_val)) 3148 #define WRITE_HL65_DSC1B1_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3149 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008225, (_val)) 3150 #define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \ 3151 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008225, (_val), (_mask)) 3152 3153 /* DFE VGA Control 2 Register */ 3154 #define READ_HL65_DSC1B1_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3155 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008226, (_val)) 3156 #define WRITE_HL65_DSC1B1_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3157 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008226, (_val)) 3158 #define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \ 3159 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008226, (_val), (_mask)) 3160 3161 /* DFE VGA Control 3 Register */ 3162 #define READ_HL65_DSC1B1_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3163 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008227, (_val)) 3164 #define WRITE_HL65_DSC1B1_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3165 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008227, (_val)) 3166 #define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \ 3167 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008227, (_val), (_mask)) 3168 3169 /* DFE VGA Control 4 Register */ 3170 #define READ_HL65_DSC1B1_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3171 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008228, (_val)) 3172 #define WRITE_HL65_DSC1B1_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3173 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008228, (_val)) 3174 #define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \ 3175 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008228, (_val), (_mask)) 3176 3177 /* DFE VGA Control 5 Register */ 3178 #define READ_HL65_DSC1B1_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3179 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008229, (_val)) 3180 #define WRITE_HL65_DSC1B1_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3181 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008229, (_val)) 3182 #define MODIFY_HL65_DSC1B1_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \ 3183 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008229, (_val), (_mask)) 3184 3185 /* DSC Analog Control 0 Register */ 3186 #define READ_HL65_DSC1B1_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3187 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822a, (_val)) 3188 #define WRITE_HL65_DSC1B1_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3189 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822a, (_val)) 3190 #define MODIFY_HL65_DSC1B1_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \ 3191 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822a, (_val), (_mask)) 3192 3193 /* DSC Analog Control 1 Register */ 3194 #define READ_HL65_DSC1B1_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3195 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822b, (_val)) 3196 #define WRITE_HL65_DSC1B1_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3197 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822b, (_val)) 3198 #define MODIFY_HL65_DSC1B1_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \ 3199 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822b, (_val), (_mask)) 3200 3201 /* DSC Analog Control 2 Register */ 3202 #define READ_HL65_DSC1B1_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3203 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822c, (_val)) 3204 #define WRITE_HL65_DSC1B1_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3205 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822c, (_val)) 3206 #define MODIFY_HL65_DSC1B1_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \ 3207 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822c, (_val), (_mask)) 3208 3209 /* DSC 100FX Control Register */ 3210 #define READ_HL65_DSC1B1_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3211 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822d, (_val)) 3212 #define WRITE_HL65_DSC1B1_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3213 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822d, (_val)) 3214 #define MODIFY_HL65_DSC1B1_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \ 3215 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822d, (_val), (_mask)) 3216 3217 /* DSC Analog Control 3 Register */ 3218 #define READ_HL65_DSC1B1_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3219 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000822e, (_val)) 3220 #define WRITE_HL65_DSC1B1_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3221 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000822e, (_val)) 3222 #define MODIFY_HL65_DSC1B1_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \ 3223 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000822e, (_val), (_mask)) 3224 3225 3226 /**************************************************************************** 3227 * Hypercore_USER_Dsc1b2 3228 */ 3229 3230 /* CDR Control 0 Register */ 3231 #define READ_HL65_DSC1B2_CDR_CTRL0r(_unit, _pc, _val) \ 3232 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008230, (_val)) 3233 #define WRITE_HL65_DSC1B2_CDR_CTRL0r(_unit, _pc, _val) \ 3234 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008230, (_val)) 3235 #define MODIFY_HL65_DSC1B2_CDR_CTRL0r(_unit, _pc, _val, _mask) \ 3236 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008230, (_val), (_mask)) 3237 3238 /* CDR Control 1 Register */ 3239 #define READ_HL65_DSC1B2_CDR_CTRL1r(_unit, _pc, _val) \ 3240 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008231, (_val)) 3241 #define WRITE_HL65_DSC1B2_CDR_CTRL1r(_unit, _pc, _val) \ 3242 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008231, (_val)) 3243 #define MODIFY_HL65_DSC1B2_CDR_CTRL1r(_unit, _pc, _val, _mask) \ 3244 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008231, (_val), (_mask)) 3245 3246 /* CDR Control 2 Register */ 3247 #define READ_HL65_DSC1B2_CDR_CTRL2r(_unit, _pc, _val) \ 3248 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008232, (_val)) 3249 #define WRITE_HL65_DSC1B2_CDR_CTRL2r(_unit, _pc, _val) \ 3250 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008232, (_val)) 3251 #define MODIFY_HL65_DSC1B2_CDR_CTRL2r(_unit, _pc, _val, _mask) \ 3252 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008232, (_val), (_mask)) 3253 3254 /* Phase Interpolator Control 0 Register */ 3255 #define READ_HL65_DSC1B2_PI_CTRL0r(_unit, _pc, _val) \ 3256 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008233, (_val)) 3257 #define WRITE_HL65_DSC1B2_PI_CTRL0r(_unit, _pc, _val) \ 3258 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008233, (_val)) 3259 #define MODIFY_HL65_DSC1B2_PI_CTRL0r(_unit, _pc, _val, _mask) \ 3260 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008233, (_val), (_mask)) 3261 3262 /* DFE VGA Control 0 Register */ 3263 #define READ_HL65_DSC1B2_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3264 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008234, (_val)) 3265 #define WRITE_HL65_DSC1B2_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3266 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008234, (_val)) 3267 #define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \ 3268 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008234, (_val), (_mask)) 3269 3270 /* DFE VGA Control 1 Register */ 3271 #define READ_HL65_DSC1B2_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3272 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008235, (_val)) 3273 #define WRITE_HL65_DSC1B2_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3274 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008235, (_val)) 3275 #define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \ 3276 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008235, (_val), (_mask)) 3277 3278 /* DFE VGA Control 2 Register */ 3279 #define READ_HL65_DSC1B2_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3280 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008236, (_val)) 3281 #define WRITE_HL65_DSC1B2_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3282 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008236, (_val)) 3283 #define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \ 3284 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008236, (_val), (_mask)) 3285 3286 /* DFE VGA Control 3 Register */ 3287 #define READ_HL65_DSC1B2_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3288 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008237, (_val)) 3289 #define WRITE_HL65_DSC1B2_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3290 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008237, (_val)) 3291 #define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \ 3292 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008237, (_val), (_mask)) 3293 3294 /* DFE VGA Control 4 Register */ 3295 #define READ_HL65_DSC1B2_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3296 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008238, (_val)) 3297 #define WRITE_HL65_DSC1B2_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3298 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008238, (_val)) 3299 #define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \ 3300 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008238, (_val), (_mask)) 3301 3302 /* DFE VGA Control 5 Register */ 3303 #define READ_HL65_DSC1B2_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3304 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008239, (_val)) 3305 #define WRITE_HL65_DSC1B2_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3306 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008239, (_val)) 3307 #define MODIFY_HL65_DSC1B2_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \ 3308 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008239, (_val), (_mask)) 3309 3310 /* DSC Analog Control 0 Register */ 3311 #define READ_HL65_DSC1B2_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3312 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823a, (_val)) 3313 #define WRITE_HL65_DSC1B2_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3314 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823a, (_val)) 3315 #define MODIFY_HL65_DSC1B2_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \ 3316 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823a, (_val), (_mask)) 3317 3318 /* DSC Analog Control 1 Register */ 3319 #define READ_HL65_DSC1B2_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3320 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823b, (_val)) 3321 #define WRITE_HL65_DSC1B2_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3322 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823b, (_val)) 3323 #define MODIFY_HL65_DSC1B2_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \ 3324 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823b, (_val), (_mask)) 3325 3326 /* DSC Analog Control 2 Register */ 3327 #define READ_HL65_DSC1B2_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3328 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823c, (_val)) 3329 #define WRITE_HL65_DSC1B2_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3330 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823c, (_val)) 3331 #define MODIFY_HL65_DSC1B2_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \ 3332 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823c, (_val), (_mask)) 3333 3334 /* DSC 100FX Control Register */ 3335 #define READ_HL65_DSC1B2_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3336 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823d, (_val)) 3337 #define WRITE_HL65_DSC1B2_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3338 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823d, (_val)) 3339 #define MODIFY_HL65_DSC1B2_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \ 3340 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823d, (_val), (_mask)) 3341 3342 /* DSC Analog Control 3 Register */ 3343 #define READ_HL65_DSC1B2_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3344 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000823e, (_val)) 3345 #define WRITE_HL65_DSC1B2_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3346 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000823e, (_val)) 3347 #define MODIFY_HL65_DSC1B2_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \ 3348 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000823e, (_val), (_mask)) 3349 3350 3351 /**************************************************************************** 3352 * Hypercore_USER_Dsc1b3 3353 */ 3354 3355 /* CDR Control 0 Register */ 3356 #define READ_HL65_DSC1B3_CDR_CTRL0r(_unit, _pc, _val) \ 3357 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008240, (_val)) 3358 #define WRITE_HL65_DSC1B3_CDR_CTRL0r(_unit, _pc, _val) \ 3359 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008240, (_val)) 3360 #define MODIFY_HL65_DSC1B3_CDR_CTRL0r(_unit, _pc, _val, _mask) \ 3361 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008240, (_val), (_mask)) 3362 3363 /* CDR Control 1 Register */ 3364 #define READ_HL65_DSC1B3_CDR_CTRL1r(_unit, _pc, _val) \ 3365 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008241, (_val)) 3366 #define WRITE_HL65_DSC1B3_CDR_CTRL1r(_unit, _pc, _val) \ 3367 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008241, (_val)) 3368 #define MODIFY_HL65_DSC1B3_CDR_CTRL1r(_unit, _pc, _val, _mask) \ 3369 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008241, (_val), (_mask)) 3370 3371 /* CDR Control 2 Register */ 3372 #define READ_HL65_DSC1B3_CDR_CTRL2r(_unit, _pc, _val) \ 3373 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008242, (_val)) 3374 #define WRITE_HL65_DSC1B3_CDR_CTRL2r(_unit, _pc, _val) \ 3375 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008242, (_val)) 3376 #define MODIFY_HL65_DSC1B3_CDR_CTRL2r(_unit, _pc, _val, _mask) \ 3377 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008242, (_val), (_mask)) 3378 3379 /* Phase Interpolator Control 0 Register */ 3380 #define READ_HL65_DSC1B3_PI_CTRL0r(_unit, _pc, _val) \ 3381 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008243, (_val)) 3382 #define WRITE_HL65_DSC1B3_PI_CTRL0r(_unit, _pc, _val) \ 3383 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008243, (_val)) 3384 #define MODIFY_HL65_DSC1B3_PI_CTRL0r(_unit, _pc, _val, _mask) \ 3385 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008243, (_val), (_mask)) 3386 3387 /* DFE VGA Control 0 Register */ 3388 #define READ_HL65_DSC1B3_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3389 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008244, (_val)) 3390 #define WRITE_HL65_DSC1B3_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3391 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008244, (_val)) 3392 #define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \ 3393 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008244, (_val), (_mask)) 3394 3395 /* DFE VGA Control 1 Register */ 3396 #define READ_HL65_DSC1B3_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3397 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008245, (_val)) 3398 #define WRITE_HL65_DSC1B3_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3399 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008245, (_val)) 3400 #define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \ 3401 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008245, (_val), (_mask)) 3402 3403 /* DFE VGA Control 2 Register */ 3404 #define READ_HL65_DSC1B3_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3405 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008246, (_val)) 3406 #define WRITE_HL65_DSC1B3_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3407 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008246, (_val)) 3408 #define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \ 3409 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008246, (_val), (_mask)) 3410 3411 /* DFE VGA Control 3 Register */ 3412 #define READ_HL65_DSC1B3_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3413 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008247, (_val)) 3414 #define WRITE_HL65_DSC1B3_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3415 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008247, (_val)) 3416 #define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \ 3417 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008247, (_val), (_mask)) 3418 3419 /* DFE VGA Control 4 Register */ 3420 #define READ_HL65_DSC1B3_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3421 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008248, (_val)) 3422 #define WRITE_HL65_DSC1B3_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3423 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008248, (_val)) 3424 #define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \ 3425 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008248, (_val), (_mask)) 3426 3427 /* DFE VGA Control 5 Register */ 3428 #define READ_HL65_DSC1B3_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3429 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008249, (_val)) 3430 #define WRITE_HL65_DSC1B3_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3431 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008249, (_val)) 3432 #define MODIFY_HL65_DSC1B3_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \ 3433 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008249, (_val), (_mask)) 3434 3435 /* DSC Analog Control 0 Register */ 3436 #define READ_HL65_DSC1B3_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3437 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824a, (_val)) 3438 #define WRITE_HL65_DSC1B3_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3439 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824a, (_val)) 3440 #define MODIFY_HL65_DSC1B3_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \ 3441 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824a, (_val), (_mask)) 3442 3443 /* DSC Analog Control 1 Register */ 3444 #define READ_HL65_DSC1B3_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3445 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824b, (_val)) 3446 #define WRITE_HL65_DSC1B3_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3447 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824b, (_val)) 3448 #define MODIFY_HL65_DSC1B3_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \ 3449 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824b, (_val), (_mask)) 3450 3451 /* DSC Analog Control 2 Register */ 3452 #define READ_HL65_DSC1B3_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3453 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824c, (_val)) 3454 #define WRITE_HL65_DSC1B3_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3455 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824c, (_val)) 3456 #define MODIFY_HL65_DSC1B3_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \ 3457 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824c, (_val), (_mask)) 3458 3459 /* DSC 100FX Control Register */ 3460 #define READ_HL65_DSC1B3_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3461 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824d, (_val)) 3462 #define WRITE_HL65_DSC1B3_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3463 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824d, (_val)) 3464 #define MODIFY_HL65_DSC1B3_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \ 3465 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824d, (_val), (_mask)) 3466 3467 /* DSC Analog Control 3 Register */ 3468 #define READ_HL65_DSC1B3_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3469 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000824e, (_val)) 3470 #define WRITE_HL65_DSC1B3_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3471 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000824e, (_val)) 3472 #define MODIFY_HL65_DSC1B3_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \ 3473 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000824e, (_val), (_mask)) 3474 3475 3476 /**************************************************************************** 3477 * Hypercore_USER_Dsc1bB 3478 */ 3479 3480 /* CDR Control 0 Register */ 3481 #define READ_HL65_DSC1BB_CDR_CTRL0r(_unit, _pc, _val) \ 3482 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008250, (_val)) 3483 #define WRITE_HL65_DSC1BB_CDR_CTRL0r(_unit, _pc, _val) \ 3484 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008250, (_val)) 3485 #define MODIFY_HL65_DSC1BB_CDR_CTRL0r(_unit, _pc, _val, _mask) \ 3486 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008250, (_val), (_mask)) 3487 3488 /* CDR Control 1 Register */ 3489 #define READ_HL65_DSC1BB_CDR_CTRL1r(_unit, _pc, _val) \ 3490 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008251, (_val)) 3491 #define WRITE_HL65_DSC1BB_CDR_CTRL1r(_unit, _pc, _val) \ 3492 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008251, (_val)) 3493 #define MODIFY_HL65_DSC1BB_CDR_CTRL1r(_unit, _pc, _val, _mask) \ 3494 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008251, (_val), (_mask)) 3495 3496 /* CDR Control 2 Register */ 3497 #define READ_HL65_DSC1BB_CDR_CTRL2r(_unit, _pc, _val) \ 3498 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008252, (_val)) 3499 #define WRITE_HL65_DSC1BB_CDR_CTRL2r(_unit, _pc, _val) \ 3500 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008252, (_val)) 3501 #define MODIFY_HL65_DSC1BB_CDR_CTRL2r(_unit, _pc, _val, _mask) \ 3502 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008252, (_val), (_mask)) 3503 3504 /* Phase Interpolator Control 0 Register */ 3505 #define READ_HL65_DSC1BB_PI_CTRL0r(_unit, _pc, _val) \ 3506 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008253, (_val)) 3507 #define WRITE_HL65_DSC1BB_PI_CTRL0r(_unit, _pc, _val) \ 3508 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008253, (_val)) 3509 #define MODIFY_HL65_DSC1BB_PI_CTRL0r(_unit, _pc, _val, _mask) \ 3510 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008253, (_val), (_mask)) 3511 3512 /* DFE VGA Control 0 Register */ 3513 #define READ_HL65_DSC1BB_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3514 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008254, (_val)) 3515 #define WRITE_HL65_DSC1BB_DFE_VGA_CTRL0r(_unit, _pc, _val) \ 3516 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008254, (_val)) 3517 #define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL0r(_unit, _pc, _val, _mask) \ 3518 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008254, (_val), (_mask)) 3519 3520 /* DFE VGA Control 1 Register */ 3521 #define READ_HL65_DSC1BB_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3522 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008255, (_val)) 3523 #define WRITE_HL65_DSC1BB_DFE_VGA_CTRL1r(_unit, _pc, _val) \ 3524 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008255, (_val)) 3525 #define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL1r(_unit, _pc, _val, _mask) \ 3526 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008255, (_val), (_mask)) 3527 3528 /* DFE VGA Control 2 Register */ 3529 #define READ_HL65_DSC1BB_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3530 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008256, (_val)) 3531 #define WRITE_HL65_DSC1BB_DFE_VGA_CTRL2r(_unit, _pc, _val) \ 3532 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008256, (_val)) 3533 #define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL2r(_unit, _pc, _val, _mask) \ 3534 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008256, (_val), (_mask)) 3535 3536 /* DFE VGA Control 3 Register */ 3537 #define READ_HL65_DSC1BB_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3538 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008257, (_val)) 3539 #define WRITE_HL65_DSC1BB_DFE_VGA_CTRL3r(_unit, _pc, _val) \ 3540 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008257, (_val)) 3541 #define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL3r(_unit, _pc, _val, _mask) \ 3542 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008257, (_val), (_mask)) 3543 3544 /* DFE VGA Control 4 Register */ 3545 #define READ_HL65_DSC1BB_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3546 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008258, (_val)) 3547 #define WRITE_HL65_DSC1BB_DFE_VGA_CTRL4r(_unit, _pc, _val) \ 3548 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008258, (_val)) 3549 #define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL4r(_unit, _pc, _val, _mask) \ 3550 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008258, (_val), (_mask)) 3551 3552 /* DFE VGA Control 5 Register */ 3553 #define READ_HL65_DSC1BB_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3554 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008259, (_val)) 3555 #define WRITE_HL65_DSC1BB_DFE_VGA_CTRL5r(_unit, _pc, _val) \ 3556 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008259, (_val)) 3557 #define MODIFY_HL65_DSC1BB_DFE_VGA_CTRL5r(_unit, _pc, _val, _mask) \ 3558 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008259, (_val), (_mask)) 3559 3560 /* DSC Analog Control 0 Register */ 3561 #define READ_HL65_DSC1BB_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3562 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825a, (_val)) 3563 #define WRITE_HL65_DSC1BB_DSC_ANA_CTRL0r(_unit, _pc, _val) \ 3564 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825a, (_val)) 3565 #define MODIFY_HL65_DSC1BB_DSC_ANA_CTRL0r(_unit, _pc, _val, _mask) \ 3566 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825a, (_val), (_mask)) 3567 3568 /* DSC Analog Control 1 Register */ 3569 #define READ_HL65_DSC1BB_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3570 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825b, (_val)) 3571 #define WRITE_HL65_DSC1BB_DSC_ANA_CTRL1r(_unit, _pc, _val) \ 3572 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825b, (_val)) 3573 #define MODIFY_HL65_DSC1BB_DSC_ANA_CTRL1r(_unit, _pc, _val, _mask) \ 3574 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825b, (_val), (_mask)) 3575 3576 /* DSC Analog Control 2 Register */ 3577 #define READ_HL65_DSC1BB_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3578 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825c, (_val)) 3579 #define WRITE_HL65_DSC1BB_DSC_ANA_CTRL2r(_unit, _pc, _val) \ 3580 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825c, (_val)) 3581 #define MODIFY_HL65_DSC1BB_DSC_ANA_CTRL2r(_unit, _pc, _val, _mask) \ 3582 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825c, (_val), (_mask)) 3583 3584 /* DSC 100FX Control Register */ 3585 #define READ_HL65_DSC1BB_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3586 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825d, (_val)) 3587 #define WRITE_HL65_DSC1BB_DSC_100FX_CTRLr(_unit, _pc, _val) \ 3588 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825d, (_val)) 3589 #define MODIFY_HL65_DSC1BB_DSC_100FX_CTRLr(_unit, _pc, _val, _mask) \ 3590 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825d, (_val), (_mask)) 3591 3592 /* DSC Analog Control 3 Register */ 3593 #define READ_HL65_DSC1BB_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3594 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000825e, (_val)) 3595 #define WRITE_HL65_DSC1BB_DSC_ANA_CTRL3r(_unit, _pc, _val) \ 3596 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000825e, (_val)) 3597 #define MODIFY_HL65_DSC1BB_DSC_ANA_CTRL3r(_unit, _pc, _val, _mask) \ 3598 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000825e, (_val), (_mask)) 3599 3600 3601 /**************************************************************************** 3602 * Hypercore_USER_Dsc2b0 3603 */ 3604 3605 /* State Machine Control 0 Register */ 3606 #define READ_HL65_DSC2B0_SM_CTRL0r(_unit, _pc, _val) \ 3607 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008260, (_val)) 3608 #define WRITE_HL65_DSC2B0_SM_CTRL0r(_unit, _pc, _val) \ 3609 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008260, (_val)) 3610 #define MODIFY_HL65_DSC2B0_SM_CTRL0r(_unit, _pc, _val, _mask) \ 3611 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008260, (_val), (_mask)) 3612 3613 /* State Machine Control 1 Register */ 3614 #define READ_HL65_DSC2B0_SM_CTRL1r(_unit, _pc, _val) \ 3615 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008261, (_val)) 3616 #define WRITE_HL65_DSC2B0_SM_CTRL1r(_unit, _pc, _val) \ 3617 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008261, (_val)) 3618 #define MODIFY_HL65_DSC2B0_SM_CTRL1r(_unit, _pc, _val, _mask) \ 3619 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008261, (_val), (_mask)) 3620 3621 /* State Machine Control 2 Register */ 3622 #define READ_HL65_DSC2B0_SM_CTRL2r(_unit, _pc, _val) \ 3623 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008262, (_val)) 3624 #define WRITE_HL65_DSC2B0_SM_CTRL2r(_unit, _pc, _val) \ 3625 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008262, (_val)) 3626 #define MODIFY_HL65_DSC2B0_SM_CTRL2r(_unit, _pc, _val, _mask) \ 3627 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008262, (_val), (_mask)) 3628 3629 /* State Machine Control 3 Register */ 3630 #define READ_HL65_DSC2B0_SM_CTRL3r(_unit, _pc, _val) \ 3631 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008263, (_val)) 3632 #define WRITE_HL65_DSC2B0_SM_CTRL3r(_unit, _pc, _val) \ 3633 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008263, (_val)) 3634 #define MODIFY_HL65_DSC2B0_SM_CTRL3r(_unit, _pc, _val, _mask) \ 3635 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008263, (_val), (_mask)) 3636 3637 /* State Machine Control 4 Register */ 3638 #define READ_HL65_DSC2B0_SM_CTRL4r(_unit, _pc, _val) \ 3639 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008264, (_val)) 3640 #define WRITE_HL65_DSC2B0_SM_CTRL4r(_unit, _pc, _val) \ 3641 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008264, (_val)) 3642 #define MODIFY_HL65_DSC2B0_SM_CTRL4r(_unit, _pc, _val, _mask) \ 3643 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008264, (_val), (_mask)) 3644 3645 /* State Machine Control 5 Register */ 3646 #define READ_HL65_DSC2B0_SM_CTRL5r(_unit, _pc, _val) \ 3647 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008265, (_val)) 3648 #define WRITE_HL65_DSC2B0_SM_CTRL5r(_unit, _pc, _val) \ 3649 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008265, (_val)) 3650 #define MODIFY_HL65_DSC2B0_SM_CTRL5r(_unit, _pc, _val, _mask) \ 3651 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008265, (_val), (_mask)) 3652 3653 /* State Machine Control 6 Register */ 3654 #define READ_HL65_DSC2B0_SM_CTRL6r(_unit, _pc, _val) \ 3655 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008266, (_val)) 3656 #define WRITE_HL65_DSC2B0_SM_CTRL6r(_unit, _pc, _val) \ 3657 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008266, (_val)) 3658 #define MODIFY_HL65_DSC2B0_SM_CTRL6r(_unit, _pc, _val, _mask) \ 3659 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008266, (_val), (_mask)) 3660 3661 /* State Machine Control 7 Register */ 3662 #define READ_HL65_DSC2B0_SM_CTRL7r(_unit, _pc, _val) \ 3663 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008267, (_val)) 3664 #define WRITE_HL65_DSC2B0_SM_CTRL7r(_unit, _pc, _val) \ 3665 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008267, (_val)) 3666 #define MODIFY_HL65_DSC2B0_SM_CTRL7r(_unit, _pc, _val, _mask) \ 3667 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008267, (_val), (_mask)) 3668 3669 /* State Machine Control 8 Register */ 3670 #define READ_HL65_DSC2B0_SM_CTRL8r(_unit, _pc, _val) \ 3671 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008268, (_val)) 3672 #define WRITE_HL65_DSC2B0_SM_CTRL8r(_unit, _pc, _val) \ 3673 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008268, (_val)) 3674 #define MODIFY_HL65_DSC2B0_SM_CTRL8r(_unit, _pc, _val, _mask) \ 3675 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008268, (_val), (_mask)) 3676 3677 /* State Machine Control 9 Register */ 3678 #define READ_HL65_DSC2B0_SM_CTRL9r(_unit, _pc, _val) \ 3679 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008269, (_val)) 3680 #define WRITE_HL65_DSC2B0_SM_CTRL9r(_unit, _pc, _val) \ 3681 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008269, (_val)) 3682 #define MODIFY_HL65_DSC2B0_SM_CTRL9r(_unit, _pc, _val, _mask) \ 3683 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008269, (_val), (_mask)) 3684 3685 /* State Machine Control 10 Register */ 3686 #define READ_HL65_DSC2B0_SM_CTRL10r(_unit, _pc, _val) \ 3687 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826a, (_val)) 3688 #define WRITE_HL65_DSC2B0_SM_CTRL10r(_unit, _pc, _val) \ 3689 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826a, (_val)) 3690 #define MODIFY_HL65_DSC2B0_SM_CTRL10r(_unit, _pc, _val, _mask) \ 3691 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826a, (_val), (_mask)) 3692 3693 /* State Machine Control 11 Register */ 3694 #define READ_HL65_DSC2B0_SM_CTRL11r(_unit, _pc, _val) \ 3695 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826b, (_val)) 3696 #define WRITE_HL65_DSC2B0_SM_CTRL11r(_unit, _pc, _val) \ 3697 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826b, (_val)) 3698 #define MODIFY_HL65_DSC2B0_SM_CTRL11r(_unit, _pc, _val, _mask) \ 3699 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826b, (_val), (_mask)) 3700 3701 /* State Machine Control 12 Register */ 3702 #define READ_HL65_DSC2B0_SM_CTRL12r(_unit, _pc, _val) \ 3703 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826c, (_val)) 3704 #define WRITE_HL65_DSC2B0_SM_CTRL12r(_unit, _pc, _val) \ 3705 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826c, (_val)) 3706 #define MODIFY_HL65_DSC2B0_SM_CTRL12r(_unit, _pc, _val, _mask) \ 3707 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826c, (_val), (_mask)) 3708 3709 /* DSC Diagnostics Control 0 Register */ 3710 #define READ_HL65_DSC2B0_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 3711 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826d, (_val)) 3712 #define WRITE_HL65_DSC2B0_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 3713 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826d, (_val)) 3714 #define MODIFY_HL65_DSC2B0_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \ 3715 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826d, (_val), (_mask)) 3716 3717 /* DSC Misc Control 0 Register */ 3718 #define READ_HL65_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 3719 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000826e, (_val)) 3720 #define WRITE_HL65_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 3721 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000826e, (_val)) 3722 #define MODIFY_HL65_DSC2B0_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \ 3723 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000826e, (_val), (_mask)) 3724 3725 3726 /**************************************************************************** 3727 * Hypercore_USER_Dsc2b1 3728 */ 3729 3730 /* State Machine Control 0 Register */ 3731 #define READ_HL65_DSC2B1_SM_CTRL0r(_unit, _pc, _val) \ 3732 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008270, (_val)) 3733 #define WRITE_HL65_DSC2B1_SM_CTRL0r(_unit, _pc, _val) \ 3734 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008270, (_val)) 3735 #define MODIFY_HL65_DSC2B1_SM_CTRL0r(_unit, _pc, _val, _mask) \ 3736 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008270, (_val), (_mask)) 3737 3738 /* State Machine Control 1 Register */ 3739 #define READ_HL65_DSC2B1_SM_CTRL1r(_unit, _pc, _val) \ 3740 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008271, (_val)) 3741 #define WRITE_HL65_DSC2B1_SM_CTRL1r(_unit, _pc, _val) \ 3742 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008271, (_val)) 3743 #define MODIFY_HL65_DSC2B1_SM_CTRL1r(_unit, _pc, _val, _mask) \ 3744 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008271, (_val), (_mask)) 3745 3746 /* State Machine Control 2 Register */ 3747 #define READ_HL65_DSC2B1_SM_CTRL2r(_unit, _pc, _val) \ 3748 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008272, (_val)) 3749 #define WRITE_HL65_DSC2B1_SM_CTRL2r(_unit, _pc, _val) \ 3750 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008272, (_val)) 3751 #define MODIFY_HL65_DSC2B1_SM_CTRL2r(_unit, _pc, _val, _mask) \ 3752 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008272, (_val), (_mask)) 3753 3754 /* State Machine Control 3 Register */ 3755 #define READ_HL65_DSC2B1_SM_CTRL3r(_unit, _pc, _val) \ 3756 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008273, (_val)) 3757 #define WRITE_HL65_DSC2B1_SM_CTRL3r(_unit, _pc, _val) \ 3758 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008273, (_val)) 3759 #define MODIFY_HL65_DSC2B1_SM_CTRL3r(_unit, _pc, _val, _mask) \ 3760 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008273, (_val), (_mask)) 3761 3762 /* State Machine Control 4 Register */ 3763 #define READ_HL65_DSC2B1_SM_CTRL4r(_unit, _pc, _val) \ 3764 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008274, (_val)) 3765 #define WRITE_HL65_DSC2B1_SM_CTRL4r(_unit, _pc, _val) \ 3766 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008274, (_val)) 3767 #define MODIFY_HL65_DSC2B1_SM_CTRL4r(_unit, _pc, _val, _mask) \ 3768 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008274, (_val), (_mask)) 3769 3770 /* State Machine Control 5 Register */ 3771 #define READ_HL65_DSC2B1_SM_CTRL5r(_unit, _pc, _val) \ 3772 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008275, (_val)) 3773 #define WRITE_HL65_DSC2B1_SM_CTRL5r(_unit, _pc, _val) \ 3774 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008275, (_val)) 3775 #define MODIFY_HL65_DSC2B1_SM_CTRL5r(_unit, _pc, _val, _mask) \ 3776 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008275, (_val), (_mask)) 3777 3778 /* State Machine Control 6 Register */ 3779 #define READ_HL65_DSC2B1_SM_CTRL6r(_unit, _pc, _val) \ 3780 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008276, (_val)) 3781 #define WRITE_HL65_DSC2B1_SM_CTRL6r(_unit, _pc, _val) \ 3782 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008276, (_val)) 3783 #define MODIFY_HL65_DSC2B1_SM_CTRL6r(_unit, _pc, _val, _mask) \ 3784 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008276, (_val), (_mask)) 3785 3786 /* State Machine Control 7 Register */ 3787 #define READ_HL65_DSC2B1_SM_CTRL7r(_unit, _pc, _val) \ 3788 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008277, (_val)) 3789 #define WRITE_HL65_DSC2B1_SM_CTRL7r(_unit, _pc, _val) \ 3790 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008277, (_val)) 3791 #define MODIFY_HL65_DSC2B1_SM_CTRL7r(_unit, _pc, _val, _mask) \ 3792 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008277, (_val), (_mask)) 3793 3794 /* State Machine Control 8 Register */ 3795 #define READ_HL65_DSC2B1_SM_CTRL8r(_unit, _pc, _val) \ 3796 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008278, (_val)) 3797 #define WRITE_HL65_DSC2B1_SM_CTRL8r(_unit, _pc, _val) \ 3798 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008278, (_val)) 3799 #define MODIFY_HL65_DSC2B1_SM_CTRL8r(_unit, _pc, _val, _mask) \ 3800 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008278, (_val), (_mask)) 3801 3802 /* State Machine Control 9 Register */ 3803 #define READ_HL65_DSC2B1_SM_CTRL9r(_unit, _pc, _val) \ 3804 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008279, (_val)) 3805 #define WRITE_HL65_DSC2B1_SM_CTRL9r(_unit, _pc, _val) \ 3806 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008279, (_val)) 3807 #define MODIFY_HL65_DSC2B1_SM_CTRL9r(_unit, _pc, _val, _mask) \ 3808 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008279, (_val), (_mask)) 3809 3810 /* State Machine Control 10 Register */ 3811 #define READ_HL65_DSC2B1_SM_CTRL10r(_unit, _pc, _val) \ 3812 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827a, (_val)) 3813 #define WRITE_HL65_DSC2B1_SM_CTRL10r(_unit, _pc, _val) \ 3814 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827a, (_val)) 3815 #define MODIFY_HL65_DSC2B1_SM_CTRL10r(_unit, _pc, _val, _mask) \ 3816 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827a, (_val), (_mask)) 3817 3818 /* State Machine Control 11 Register */ 3819 #define READ_HL65_DSC2B1_SM_CTRL11r(_unit, _pc, _val) \ 3820 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827b, (_val)) 3821 #define WRITE_HL65_DSC2B1_SM_CTRL11r(_unit, _pc, _val) \ 3822 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827b, (_val)) 3823 #define MODIFY_HL65_DSC2B1_SM_CTRL11r(_unit, _pc, _val, _mask) \ 3824 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827b, (_val), (_mask)) 3825 3826 /* State Machine Control 12 Register */ 3827 #define READ_HL65_DSC2B1_SM_CTRL12r(_unit, _pc, _val) \ 3828 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827c, (_val)) 3829 #define WRITE_HL65_DSC2B1_SM_CTRL12r(_unit, _pc, _val) \ 3830 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827c, (_val)) 3831 #define MODIFY_HL65_DSC2B1_SM_CTRL12r(_unit, _pc, _val, _mask) \ 3832 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827c, (_val), (_mask)) 3833 3834 /* DSC Diagnostics Control 0 Register */ 3835 #define READ_HL65_DSC2B1_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 3836 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827d, (_val)) 3837 #define WRITE_HL65_DSC2B1_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 3838 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827d, (_val)) 3839 #define MODIFY_HL65_DSC2B1_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \ 3840 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827d, (_val), (_mask)) 3841 3842 /* DSC Misc Control 0 Register */ 3843 #define READ_HL65_DSC2B1_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 3844 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000827e, (_val)) 3845 #define WRITE_HL65_DSC2B1_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 3846 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000827e, (_val)) 3847 #define MODIFY_HL65_DSC2B1_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \ 3848 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000827e, (_val), (_mask)) 3849 3850 3851 /**************************************************************************** 3852 * Hypercore_USER_Dsc2b2 3853 */ 3854 3855 /* State Machine Control 0 Register */ 3856 #define READ_HL65_DSC2B2_SM_CTRL0r(_unit, _pc, _val) \ 3857 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008280, (_val)) 3858 #define WRITE_HL65_DSC2B2_SM_CTRL0r(_unit, _pc, _val) \ 3859 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008280, (_val)) 3860 #define MODIFY_HL65_DSC2B2_SM_CTRL0r(_unit, _pc, _val, _mask) \ 3861 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008280, (_val), (_mask)) 3862 3863 /* State Machine Control 1 Register */ 3864 #define READ_HL65_DSC2B2_SM_CTRL1r(_unit, _pc, _val) \ 3865 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008281, (_val)) 3866 #define WRITE_HL65_DSC2B2_SM_CTRL1r(_unit, _pc, _val) \ 3867 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008281, (_val)) 3868 #define MODIFY_HL65_DSC2B2_SM_CTRL1r(_unit, _pc, _val, _mask) \ 3869 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008281, (_val), (_mask)) 3870 3871 /* State Machine Control 2 Register */ 3872 #define READ_HL65_DSC2B2_SM_CTRL2r(_unit, _pc, _val) \ 3873 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008282, (_val)) 3874 #define WRITE_HL65_DSC2B2_SM_CTRL2r(_unit, _pc, _val) \ 3875 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008282, (_val)) 3876 #define MODIFY_HL65_DSC2B2_SM_CTRL2r(_unit, _pc, _val, _mask) \ 3877 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008282, (_val), (_mask)) 3878 3879 /* State Machine Control 3 Register */ 3880 #define READ_HL65_DSC2B2_SM_CTRL3r(_unit, _pc, _val) \ 3881 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008283, (_val)) 3882 #define WRITE_HL65_DSC2B2_SM_CTRL3r(_unit, _pc, _val) \ 3883 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008283, (_val)) 3884 #define MODIFY_HL65_DSC2B2_SM_CTRL3r(_unit, _pc, _val, _mask) \ 3885 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008283, (_val), (_mask)) 3886 3887 /* State Machine Control 4 Register */ 3888 #define READ_HL65_DSC2B2_SM_CTRL4r(_unit, _pc, _val) \ 3889 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008284, (_val)) 3890 #define WRITE_HL65_DSC2B2_SM_CTRL4r(_unit, _pc, _val) \ 3891 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008284, (_val)) 3892 #define MODIFY_HL65_DSC2B2_SM_CTRL4r(_unit, _pc, _val, _mask) \ 3893 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008284, (_val), (_mask)) 3894 3895 /* State Machine Control 5 Register */ 3896 #define READ_HL65_DSC2B2_SM_CTRL5r(_unit, _pc, _val) \ 3897 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008285, (_val)) 3898 #define WRITE_HL65_DSC2B2_SM_CTRL5r(_unit, _pc, _val) \ 3899 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008285, (_val)) 3900 #define MODIFY_HL65_DSC2B2_SM_CTRL5r(_unit, _pc, _val, _mask) \ 3901 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008285, (_val), (_mask)) 3902 3903 /* State Machine Control 6 Register */ 3904 #define READ_HL65_DSC2B2_SM_CTRL6r(_unit, _pc, _val) \ 3905 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008286, (_val)) 3906 #define WRITE_HL65_DSC2B2_SM_CTRL6r(_unit, _pc, _val) \ 3907 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008286, (_val)) 3908 #define MODIFY_HL65_DSC2B2_SM_CTRL6r(_unit, _pc, _val, _mask) \ 3909 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008286, (_val), (_mask)) 3910 3911 /* State Machine Control 7 Register */ 3912 #define READ_HL65_DSC2B2_SM_CTRL7r(_unit, _pc, _val) \ 3913 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008287, (_val)) 3914 #define WRITE_HL65_DSC2B2_SM_CTRL7r(_unit, _pc, _val) \ 3915 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008287, (_val)) 3916 #define MODIFY_HL65_DSC2B2_SM_CTRL7r(_unit, _pc, _val, _mask) \ 3917 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008287, (_val), (_mask)) 3918 3919 /* State Machine Control 8 Register */ 3920 #define READ_HL65_DSC2B2_SM_CTRL8r(_unit, _pc, _val) \ 3921 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008288, (_val)) 3922 #define WRITE_HL65_DSC2B2_SM_CTRL8r(_unit, _pc, _val) \ 3923 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008288, (_val)) 3924 #define MODIFY_HL65_DSC2B2_SM_CTRL8r(_unit, _pc, _val, _mask) \ 3925 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008288, (_val), (_mask)) 3926 3927 /* State Machine Control 9 Register */ 3928 #define READ_HL65_DSC2B2_SM_CTRL9r(_unit, _pc, _val) \ 3929 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008289, (_val)) 3930 #define WRITE_HL65_DSC2B2_SM_CTRL9r(_unit, _pc, _val) \ 3931 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008289, (_val)) 3932 #define MODIFY_HL65_DSC2B2_SM_CTRL9r(_unit, _pc, _val, _mask) \ 3933 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008289, (_val), (_mask)) 3934 3935 /* State Machine Control 10 Register */ 3936 #define READ_HL65_DSC2B2_SM_CTRL10r(_unit, _pc, _val) \ 3937 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828a, (_val)) 3938 #define WRITE_HL65_DSC2B2_SM_CTRL10r(_unit, _pc, _val) \ 3939 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828a, (_val)) 3940 #define MODIFY_HL65_DSC2B2_SM_CTRL10r(_unit, _pc, _val, _mask) \ 3941 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828a, (_val), (_mask)) 3942 3943 /* State Machine Control 11 Register */ 3944 #define READ_HL65_DSC2B2_SM_CTRL11r(_unit, _pc, _val) \ 3945 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828b, (_val)) 3946 #define WRITE_HL65_DSC2B2_SM_CTRL11r(_unit, _pc, _val) \ 3947 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828b, (_val)) 3948 #define MODIFY_HL65_DSC2B2_SM_CTRL11r(_unit, _pc, _val, _mask) \ 3949 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828b, (_val), (_mask)) 3950 3951 /* State Machine Control 12 Register */ 3952 #define READ_HL65_DSC2B2_SM_CTRL12r(_unit, _pc, _val) \ 3953 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828c, (_val)) 3954 #define WRITE_HL65_DSC2B2_SM_CTRL12r(_unit, _pc, _val) \ 3955 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828c, (_val)) 3956 #define MODIFY_HL65_DSC2B2_SM_CTRL12r(_unit, _pc, _val, _mask) \ 3957 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828c, (_val), (_mask)) 3958 3959 /* DSC Diagnostics Control 0 Register */ 3960 #define READ_HL65_DSC2B2_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 3961 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828d, (_val)) 3962 #define WRITE_HL65_DSC2B2_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 3963 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828d, (_val)) 3964 #define MODIFY_HL65_DSC2B2_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \ 3965 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828d, (_val), (_mask)) 3966 3967 /* DSC Misc Control 0 Register */ 3968 #define READ_HL65_DSC2B2_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 3969 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000828e, (_val)) 3970 #define WRITE_HL65_DSC2B2_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 3971 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000828e, (_val)) 3972 #define MODIFY_HL65_DSC2B2_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \ 3973 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000828e, (_val), (_mask)) 3974 3975 3976 /**************************************************************************** 3977 * Hypercore_USER_Dsc2b3 3978 */ 3979 3980 /* State Machine Control 0 Register */ 3981 #define READ_HL65_DSC2B3_SM_CTRL0r(_unit, _pc, _val) \ 3982 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008290, (_val)) 3983 #define WRITE_HL65_DSC2B3_SM_CTRL0r(_unit, _pc, _val) \ 3984 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008290, (_val)) 3985 #define MODIFY_HL65_DSC2B3_SM_CTRL0r(_unit, _pc, _val, _mask) \ 3986 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008290, (_val), (_mask)) 3987 3988 /* State Machine Control 1 Register */ 3989 #define READ_HL65_DSC2B3_SM_CTRL1r(_unit, _pc, _val) \ 3990 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008291, (_val)) 3991 #define WRITE_HL65_DSC2B3_SM_CTRL1r(_unit, _pc, _val) \ 3992 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008291, (_val)) 3993 #define MODIFY_HL65_DSC2B3_SM_CTRL1r(_unit, _pc, _val, _mask) \ 3994 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008291, (_val), (_mask)) 3995 3996 /* State Machine Control 2 Register */ 3997 #define READ_HL65_DSC2B3_SM_CTRL2r(_unit, _pc, _val) \ 3998 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008292, (_val)) 3999 #define WRITE_HL65_DSC2B3_SM_CTRL2r(_unit, _pc, _val) \ 4000 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008292, (_val)) 4001 #define MODIFY_HL65_DSC2B3_SM_CTRL2r(_unit, _pc, _val, _mask) \ 4002 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008292, (_val), (_mask)) 4003 4004 /* State Machine Control 3 Register */ 4005 #define READ_HL65_DSC2B3_SM_CTRL3r(_unit, _pc, _val) \ 4006 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008293, (_val)) 4007 #define WRITE_HL65_DSC2B3_SM_CTRL3r(_unit, _pc, _val) \ 4008 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008293, (_val)) 4009 #define MODIFY_HL65_DSC2B3_SM_CTRL3r(_unit, _pc, _val, _mask) \ 4010 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008293, (_val), (_mask)) 4011 4012 /* State Machine Control 4 Register */ 4013 #define READ_HL65_DSC2B3_SM_CTRL4r(_unit, _pc, _val) \ 4014 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008294, (_val)) 4015 #define WRITE_HL65_DSC2B3_SM_CTRL4r(_unit, _pc, _val) \ 4016 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008294, (_val)) 4017 #define MODIFY_HL65_DSC2B3_SM_CTRL4r(_unit, _pc, _val, _mask) \ 4018 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008294, (_val), (_mask)) 4019 4020 /* State Machine Control 5 Register */ 4021 #define READ_HL65_DSC2B3_SM_CTRL5r(_unit, _pc, _val) \ 4022 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008295, (_val)) 4023 #define WRITE_HL65_DSC2B3_SM_CTRL5r(_unit, _pc, _val) \ 4024 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008295, (_val)) 4025 #define MODIFY_HL65_DSC2B3_SM_CTRL5r(_unit, _pc, _val, _mask) \ 4026 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008295, (_val), (_mask)) 4027 4028 /* State Machine Control 6 Register */ 4029 #define READ_HL65_DSC2B3_SM_CTRL6r(_unit, _pc, _val) \ 4030 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008296, (_val)) 4031 #define WRITE_HL65_DSC2B3_SM_CTRL6r(_unit, _pc, _val) \ 4032 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008296, (_val)) 4033 #define MODIFY_HL65_DSC2B3_SM_CTRL6r(_unit, _pc, _val, _mask) \ 4034 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008296, (_val), (_mask)) 4035 4036 /* State Machine Control 7 Register */ 4037 #define READ_HL65_DSC2B3_SM_CTRL7r(_unit, _pc, _val) \ 4038 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008297, (_val)) 4039 #define WRITE_HL65_DSC2B3_SM_CTRL7r(_unit, _pc, _val) \ 4040 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008297, (_val)) 4041 #define MODIFY_HL65_DSC2B3_SM_CTRL7r(_unit, _pc, _val, _mask) \ 4042 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008297, (_val), (_mask)) 4043 4044 /* State Machine Control 8 Register */ 4045 #define READ_HL65_DSC2B3_SM_CTRL8r(_unit, _pc, _val) \ 4046 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008298, (_val)) 4047 #define WRITE_HL65_DSC2B3_SM_CTRL8r(_unit, _pc, _val) \ 4048 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008298, (_val)) 4049 #define MODIFY_HL65_DSC2B3_SM_CTRL8r(_unit, _pc, _val, _mask) \ 4050 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008298, (_val), (_mask)) 4051 4052 /* State Machine Control 9 Register */ 4053 #define READ_HL65_DSC2B3_SM_CTRL9r(_unit, _pc, _val) \ 4054 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008299, (_val)) 4055 #define WRITE_HL65_DSC2B3_SM_CTRL9r(_unit, _pc, _val) \ 4056 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008299, (_val)) 4057 #define MODIFY_HL65_DSC2B3_SM_CTRL9r(_unit, _pc, _val, _mask) \ 4058 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008299, (_val), (_mask)) 4059 4060 /* State Machine Control 10 Register */ 4061 #define READ_HL65_DSC2B3_SM_CTRL10r(_unit, _pc, _val) \ 4062 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829a, (_val)) 4063 #define WRITE_HL65_DSC2B3_SM_CTRL10r(_unit, _pc, _val) \ 4064 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829a, (_val)) 4065 #define MODIFY_HL65_DSC2B3_SM_CTRL10r(_unit, _pc, _val, _mask) \ 4066 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829a, (_val), (_mask)) 4067 4068 /* State Machine Control 11 Register */ 4069 #define READ_HL65_DSC2B3_SM_CTRL11r(_unit, _pc, _val) \ 4070 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829b, (_val)) 4071 #define WRITE_HL65_DSC2B3_SM_CTRL11r(_unit, _pc, _val) \ 4072 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829b, (_val)) 4073 #define MODIFY_HL65_DSC2B3_SM_CTRL11r(_unit, _pc, _val, _mask) \ 4074 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829b, (_val), (_mask)) 4075 4076 /* State Machine Control 12 Register */ 4077 #define READ_HL65_DSC2B3_SM_CTRL12r(_unit, _pc, _val) \ 4078 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829c, (_val)) 4079 #define WRITE_HL65_DSC2B3_SM_CTRL12r(_unit, _pc, _val) \ 4080 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829c, (_val)) 4081 #define MODIFY_HL65_DSC2B3_SM_CTRL12r(_unit, _pc, _val, _mask) \ 4082 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829c, (_val), (_mask)) 4083 4084 /* DSC Diagnostics Control 0 Register */ 4085 #define READ_HL65_DSC2B3_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 4086 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829d, (_val)) 4087 #define WRITE_HL65_DSC2B3_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 4088 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829d, (_val)) 4089 #define MODIFY_HL65_DSC2B3_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \ 4090 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829d, (_val), (_mask)) 4091 4092 /* DSC Misc Control 0 Register */ 4093 #define READ_HL65_DSC2B3_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 4094 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000829e, (_val)) 4095 #define WRITE_HL65_DSC2B3_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 4096 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000829e, (_val)) 4097 #define MODIFY_HL65_DSC2B3_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \ 4098 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000829e, (_val), (_mask)) 4099 4100 4101 /**************************************************************************** 4102 * Hypercore_USER_Dsc2bB 4103 */ 4104 4105 /* State Machine Control 0 Register */ 4106 #define READ_HL65_DSC2BB_SM_CTRL0r(_unit, _pc, _val) \ 4107 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a0, (_val)) 4108 #define WRITE_HL65_DSC2BB_SM_CTRL0r(_unit, _pc, _val) \ 4109 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a0, (_val)) 4110 #define MODIFY_HL65_DSC2BB_SM_CTRL0r(_unit, _pc, _val, _mask) \ 4111 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a0, (_val), (_mask)) 4112 4113 /* State Machine Control 1 Register */ 4114 #define READ_HL65_DSC2BB_SM_CTRL1r(_unit, _pc, _val) \ 4115 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a1, (_val)) 4116 #define WRITE_HL65_DSC2BB_SM_CTRL1r(_unit, _pc, _val) \ 4117 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a1, (_val)) 4118 #define MODIFY_HL65_DSC2BB_SM_CTRL1r(_unit, _pc, _val, _mask) \ 4119 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a1, (_val), (_mask)) 4120 4121 /* State Machine Control 2 Register */ 4122 #define READ_HL65_DSC2BB_SM_CTRL2r(_unit, _pc, _val) \ 4123 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a2, (_val)) 4124 #define WRITE_HL65_DSC2BB_SM_CTRL2r(_unit, _pc, _val) \ 4125 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a2, (_val)) 4126 #define MODIFY_HL65_DSC2BB_SM_CTRL2r(_unit, _pc, _val, _mask) \ 4127 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a2, (_val), (_mask)) 4128 4129 /* State Machine Control 3 Register */ 4130 #define READ_HL65_DSC2BB_SM_CTRL3r(_unit, _pc, _val) \ 4131 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a3, (_val)) 4132 #define WRITE_HL65_DSC2BB_SM_CTRL3r(_unit, _pc, _val) \ 4133 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a3, (_val)) 4134 #define MODIFY_HL65_DSC2BB_SM_CTRL3r(_unit, _pc, _val, _mask) \ 4135 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a3, (_val), (_mask)) 4136 4137 /* State Machine Control 4 Register */ 4138 #define READ_HL65_DSC2BB_SM_CTRL4r(_unit, _pc, _val) \ 4139 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a4, (_val)) 4140 #define WRITE_HL65_DSC2BB_SM_CTRL4r(_unit, _pc, _val) \ 4141 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a4, (_val)) 4142 #define MODIFY_HL65_DSC2BB_SM_CTRL4r(_unit, _pc, _val, _mask) \ 4143 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a4, (_val), (_mask)) 4144 4145 /* State Machine Control 5 Register */ 4146 #define READ_HL65_DSC2BB_SM_CTRL5r(_unit, _pc, _val) \ 4147 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a5, (_val)) 4148 #define WRITE_HL65_DSC2BB_SM_CTRL5r(_unit, _pc, _val) \ 4149 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a5, (_val)) 4150 #define MODIFY_HL65_DSC2BB_SM_CTRL5r(_unit, _pc, _val, _mask) \ 4151 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a5, (_val), (_mask)) 4152 4153 /* State Machine Control 6 Register */ 4154 #define READ_HL65_DSC2BB_SM_CTRL6r(_unit, _pc, _val) \ 4155 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a6, (_val)) 4156 #define WRITE_HL65_DSC2BB_SM_CTRL6r(_unit, _pc, _val) \ 4157 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a6, (_val)) 4158 #define MODIFY_HL65_DSC2BB_SM_CTRL6r(_unit, _pc, _val, _mask) \ 4159 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a6, (_val), (_mask)) 4160 4161 /* State Machine Control 7 Register */ 4162 #define READ_HL65_DSC2BB_SM_CTRL7r(_unit, _pc, _val) \ 4163 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a7, (_val)) 4164 #define WRITE_HL65_DSC2BB_SM_CTRL7r(_unit, _pc, _val) \ 4165 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a7, (_val)) 4166 #define MODIFY_HL65_DSC2BB_SM_CTRL7r(_unit, _pc, _val, _mask) \ 4167 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a7, (_val), (_mask)) 4168 4169 /* State Machine Control 8 Register */ 4170 #define READ_HL65_DSC2BB_SM_CTRL8r(_unit, _pc, _val) \ 4171 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a8, (_val)) 4172 #define WRITE_HL65_DSC2BB_SM_CTRL8r(_unit, _pc, _val) \ 4173 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a8, (_val)) 4174 #define MODIFY_HL65_DSC2BB_SM_CTRL8r(_unit, _pc, _val, _mask) \ 4175 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a8, (_val), (_mask)) 4176 4177 /* State Machine Control 9 Register */ 4178 #define READ_HL65_DSC2BB_SM_CTRL9r(_unit, _pc, _val) \ 4179 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082a9, (_val)) 4180 #define WRITE_HL65_DSC2BB_SM_CTRL9r(_unit, _pc, _val) \ 4181 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082a9, (_val)) 4182 #define MODIFY_HL65_DSC2BB_SM_CTRL9r(_unit, _pc, _val, _mask) \ 4183 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082a9, (_val), (_mask)) 4184 4185 /* State Machine Control 10 Register */ 4186 #define READ_HL65_DSC2BB_SM_CTRL10r(_unit, _pc, _val) \ 4187 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082aa, (_val)) 4188 #define WRITE_HL65_DSC2BB_SM_CTRL10r(_unit, _pc, _val) \ 4189 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082aa, (_val)) 4190 #define MODIFY_HL65_DSC2BB_SM_CTRL10r(_unit, _pc, _val, _mask) \ 4191 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082aa, (_val), (_mask)) 4192 4193 /* State Machine Control 11 Register */ 4194 #define READ_HL65_DSC2BB_SM_CTRL11r(_unit, _pc, _val) \ 4195 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ab, (_val)) 4196 #define WRITE_HL65_DSC2BB_SM_CTRL11r(_unit, _pc, _val) \ 4197 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ab, (_val)) 4198 #define MODIFY_HL65_DSC2BB_SM_CTRL11r(_unit, _pc, _val, _mask) \ 4199 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ab, (_val), (_mask)) 4200 4201 /* State Machine Control 12 Register */ 4202 #define READ_HL65_DSC2BB_SM_CTRL12r(_unit, _pc, _val) \ 4203 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ac, (_val)) 4204 #define WRITE_HL65_DSC2BB_SM_CTRL12r(_unit, _pc, _val) \ 4205 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ac, (_val)) 4206 #define MODIFY_HL65_DSC2BB_SM_CTRL12r(_unit, _pc, _val, _mask) \ 4207 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ac, (_val), (_mask)) 4208 4209 /* DSC Diagnostics Control 0 Register */ 4210 #define READ_HL65_DSC2BB_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 4211 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ad, (_val)) 4212 #define WRITE_HL65_DSC2BB_DSC_DIAG_CTRL0r(_unit, _pc, _val) \ 4213 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ad, (_val)) 4214 #define MODIFY_HL65_DSC2BB_DSC_DIAG_CTRL0r(_unit, _pc, _val, _mask) \ 4215 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ad, (_val), (_mask)) 4216 4217 /* DSC Misc Control 0 Register */ 4218 #define READ_HL65_DSC2BB_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 4219 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ae, (_val)) 4220 #define WRITE_HL65_DSC2BB_DSC_MISC_CTRL0r(_unit, _pc, _val) \ 4221 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ae, (_val)) 4222 #define MODIFY_HL65_DSC2BB_DSC_MISC_CTRL0r(_unit, _pc, _val, _mask) \ 4223 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ae, (_val), (_mask)) 4224 4225 4226 /**************************************************************************** 4227 * Hypercore_USER_Dsc3b0 4228 */ 4229 4230 /* CDR Status 0 Register */ 4231 #define READ_HL65_DSC3B0_CDR_STATUS0r(_unit, _pc, _val) \ 4232 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b0, (_val)) 4233 #define WRITE_HL65_DSC3B0_CDR_STATUS0r(_unit, _pc, _val) \ 4234 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b0, (_val)) 4235 #define MODIFY_HL65_DSC3B0_CDR_STATUS0r(_unit, _pc, _val, _mask) \ 4236 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b0, (_val), (_mask)) 4237 4238 /* CDR Status 1 Register */ 4239 #define READ_HL65_DSC3B0_CDR_STATUS1r(_unit, _pc, _val) \ 4240 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b1, (_val)) 4241 #define WRITE_HL65_DSC3B0_CDR_STATUS1r(_unit, _pc, _val) \ 4242 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b1, (_val)) 4243 #define MODIFY_HL65_DSC3B0_CDR_STATUS1r(_unit, _pc, _val, _mask) \ 4244 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b1, (_val), (_mask)) 4245 4246 /* CDR Status 2 Register */ 4247 #define READ_HL65_DSC3B0_CDR_STATUS2r(_unit, _pc, _val) \ 4248 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b2, (_val)) 4249 #define WRITE_HL65_DSC3B0_CDR_STATUS2r(_unit, _pc, _val) \ 4250 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b2, (_val)) 4251 #define MODIFY_HL65_DSC3B0_CDR_STATUS2r(_unit, _pc, _val, _mask) \ 4252 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b2, (_val), (_mask)) 4253 4254 /* Phase Interpolator Status 0 Register */ 4255 #define READ_HL65_DSC3B0_PI_STATUS0r(_unit, _pc, _val) \ 4256 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b3, (_val)) 4257 #define WRITE_HL65_DSC3B0_PI_STATUS0r(_unit, _pc, _val) \ 4258 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b3, (_val)) 4259 #define MODIFY_HL65_DSC3B0_PI_STATUS0r(_unit, _pc, _val, _mask) \ 4260 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b3, (_val), (_mask)) 4261 4262 /* Phase Interpolator Status 1 Register */ 4263 #define READ_HL65_DSC3B0_PI_STATUS1r(_unit, _pc, _val) \ 4264 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b4, (_val)) 4265 #define WRITE_HL65_DSC3B0_PI_STATUS1r(_unit, _pc, _val) \ 4266 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b4, (_val)) 4267 #define MODIFY_HL65_DSC3B0_PI_STATUS1r(_unit, _pc, _val, _mask) \ 4268 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b4, (_val), (_mask)) 4269 4270 /* DFE VGA Status 0 Register */ 4271 #define READ_HL65_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4272 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b5, (_val)) 4273 #define WRITE_HL65_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4274 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b5, (_val)) 4275 #define MODIFY_HL65_DSC3B0_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \ 4276 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b5, (_val), (_mask)) 4277 4278 /* DFE VGA Status 1 Register */ 4279 #define READ_HL65_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4280 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b6, (_val)) 4281 #define WRITE_HL65_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4282 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b6, (_val)) 4283 #define MODIFY_HL65_DSC3B0_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \ 4284 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b6, (_val), (_mask)) 4285 4286 /* State Machine Status 0 Register */ 4287 #define READ_HL65_DSC3B0_SM_STATUS0r(_unit, _pc, _val) \ 4288 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b7, (_val)) 4289 #define WRITE_HL65_DSC3B0_SM_STATUS0r(_unit, _pc, _val) \ 4290 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b7, (_val)) 4291 #define MODIFY_HL65_DSC3B0_SM_STATUS0r(_unit, _pc, _val, _mask) \ 4292 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b7, (_val), (_mask)) 4293 4294 /* State Machine Status 1 Register */ 4295 #define READ_HL65_DSC3B0_SM_STATUS1r(_unit, _pc, _val) \ 4296 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b8, (_val)) 4297 #define WRITE_HL65_DSC3B0_SM_STATUS1r(_unit, _pc, _val) \ 4298 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b8, (_val)) 4299 #define MODIFY_HL65_DSC3B0_SM_STATUS1r(_unit, _pc, _val, _mask) \ 4300 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b8, (_val), (_mask)) 4301 4302 /* State Machine Status 2 Register */ 4303 #define READ_HL65_DSC3B0_SM_STATUS2r(_unit, _pc, _val) \ 4304 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082b9, (_val)) 4305 #define WRITE_HL65_DSC3B0_SM_STATUS2r(_unit, _pc, _val) \ 4306 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082b9, (_val)) 4307 #define MODIFY_HL65_DSC3B0_SM_STATUS2r(_unit, _pc, _val, _mask) \ 4308 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082b9, (_val), (_mask)) 4309 4310 /* State Machine Status 3 Register */ 4311 #define READ_HL65_DSC3B0_SM_STATUS3r(_unit, _pc, _val) \ 4312 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ba, (_val)) 4313 #define WRITE_HL65_DSC3B0_SM_STATUS3r(_unit, _pc, _val) \ 4314 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ba, (_val)) 4315 #define MODIFY_HL65_DSC3B0_SM_STATUS3r(_unit, _pc, _val, _mask) \ 4316 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ba, (_val), (_mask)) 4317 4318 /* State Machine Status 4 Register */ 4319 #define READ_HL65_DSC3B0_SM_STATUS4r(_unit, _pc, _val) \ 4320 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082bb, (_val)) 4321 #define WRITE_HL65_DSC3B0_SM_STATUS4r(_unit, _pc, _val) \ 4322 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082bb, (_val)) 4323 #define MODIFY_HL65_DSC3B0_SM_STATUS4r(_unit, _pc, _val, _mask) \ 4324 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082bb, (_val), (_mask)) 4325 4326 /* DSC Analog Status 0 Register */ 4327 #define READ_HL65_DSC3B0_ANA_STATUS0r(_unit, _pc, _val) \ 4328 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082bc, (_val)) 4329 #define WRITE_HL65_DSC3B0_ANA_STATUS0r(_unit, _pc, _val) \ 4330 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082bc, (_val)) 4331 #define MODIFY_HL65_DSC3B0_ANA_STATUS0r(_unit, _pc, _val, _mask) \ 4332 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082bc, (_val), (_mask)) 4333 4334 /* State Machine Status 5 Register */ 4335 #define READ_HL65_DSC3B0_SM_STATUS5r(_unit, _pc, _val) \ 4336 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082bd, (_val)) 4337 #define WRITE_HL65_DSC3B0_SM_STATUS5r(_unit, _pc, _val) \ 4338 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082bd, (_val)) 4339 #define MODIFY_HL65_DSC3B0_SM_STATUS5r(_unit, _pc, _val, _mask) \ 4340 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082bd, (_val), (_mask)) 4341 4342 /* State Machine Status 6 Register */ 4343 #define READ_HL65_DSC3B0_SM_STATUS6r(_unit, _pc, _val) \ 4344 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082be, (_val)) 4345 #define WRITE_HL65_DSC3B0_SM_STATUS6r(_unit, _pc, _val) \ 4346 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082be, (_val)) 4347 #define MODIFY_HL65_DSC3B0_SM_STATUS6r(_unit, _pc, _val, _mask) \ 4348 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082be, (_val), (_mask)) 4349 4350 4351 /**************************************************************************** 4352 * Hypercore_USER_Dsc3b1 4353 */ 4354 4355 /* CDR Status 0 Register */ 4356 #define READ_HL65_DSC3B1_CDR_STATUS0r(_unit, _pc, _val) \ 4357 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c0, (_val)) 4358 #define WRITE_HL65_DSC3B1_CDR_STATUS0r(_unit, _pc, _val) \ 4359 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c0, (_val)) 4360 #define MODIFY_HL65_DSC3B1_CDR_STATUS0r(_unit, _pc, _val, _mask) \ 4361 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c0, (_val), (_mask)) 4362 4363 /* CDR Status 1 Register */ 4364 #define READ_HL65_DSC3B1_CDR_STATUS1r(_unit, _pc, _val) \ 4365 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c1, (_val)) 4366 #define WRITE_HL65_DSC3B1_CDR_STATUS1r(_unit, _pc, _val) \ 4367 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c1, (_val)) 4368 #define MODIFY_HL65_DSC3B1_CDR_STATUS1r(_unit, _pc, _val, _mask) \ 4369 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c1, (_val), (_mask)) 4370 4371 /* CDR Status 2 Register */ 4372 #define READ_HL65_DSC3B1_CDR_STATUS2r(_unit, _pc, _val) \ 4373 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c2, (_val)) 4374 #define WRITE_HL65_DSC3B1_CDR_STATUS2r(_unit, _pc, _val) \ 4375 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c2, (_val)) 4376 #define MODIFY_HL65_DSC3B1_CDR_STATUS2r(_unit, _pc, _val, _mask) \ 4377 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c2, (_val), (_mask)) 4378 4379 /* Phase Interpolator Status 0 Register */ 4380 #define READ_HL65_DSC3B1_PI_STATUS0r(_unit, _pc, _val) \ 4381 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c3, (_val)) 4382 #define WRITE_HL65_DSC3B1_PI_STATUS0r(_unit, _pc, _val) \ 4383 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c3, (_val)) 4384 #define MODIFY_HL65_DSC3B1_PI_STATUS0r(_unit, _pc, _val, _mask) \ 4385 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c3, (_val), (_mask)) 4386 4387 /* Phase Interpolator Status 1 Register */ 4388 #define READ_HL65_DSC3B1_PI_STATUS1r(_unit, _pc, _val) \ 4389 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c4, (_val)) 4390 #define WRITE_HL65_DSC3B1_PI_STATUS1r(_unit, _pc, _val) \ 4391 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c4, (_val)) 4392 #define MODIFY_HL65_DSC3B1_PI_STATUS1r(_unit, _pc, _val, _mask) \ 4393 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c4, (_val), (_mask)) 4394 4395 /* DFE VGA Status 0 Register */ 4396 #define READ_HL65_DSC3B1_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4397 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c5, (_val)) 4398 #define WRITE_HL65_DSC3B1_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4399 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c5, (_val)) 4400 #define MODIFY_HL65_DSC3B1_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \ 4401 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c5, (_val), (_mask)) 4402 4403 /* DFE VGA Status 1 Register */ 4404 #define READ_HL65_DSC3B1_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4405 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c6, (_val)) 4406 #define WRITE_HL65_DSC3B1_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4407 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c6, (_val)) 4408 #define MODIFY_HL65_DSC3B1_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \ 4409 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c6, (_val), (_mask)) 4410 4411 /* State Machine Status 0 Register */ 4412 #define READ_HL65_DSC3B1_SM_STATUS0r(_unit, _pc, _val) \ 4413 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c7, (_val)) 4414 #define WRITE_HL65_DSC3B1_SM_STATUS0r(_unit, _pc, _val) \ 4415 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c7, (_val)) 4416 #define MODIFY_HL65_DSC3B1_SM_STATUS0r(_unit, _pc, _val, _mask) \ 4417 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c7, (_val), (_mask)) 4418 4419 /* State Machine Status 1 Register */ 4420 #define READ_HL65_DSC3B1_SM_STATUS1r(_unit, _pc, _val) \ 4421 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c8, (_val)) 4422 #define WRITE_HL65_DSC3B1_SM_STATUS1r(_unit, _pc, _val) \ 4423 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c8, (_val)) 4424 #define MODIFY_HL65_DSC3B1_SM_STATUS1r(_unit, _pc, _val, _mask) \ 4425 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c8, (_val), (_mask)) 4426 4427 /* State Machine Status 2 Register */ 4428 #define READ_HL65_DSC3B1_SM_STATUS2r(_unit, _pc, _val) \ 4429 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082c9, (_val)) 4430 #define WRITE_HL65_DSC3B1_SM_STATUS2r(_unit, _pc, _val) \ 4431 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082c9, (_val)) 4432 #define MODIFY_HL65_DSC3B1_SM_STATUS2r(_unit, _pc, _val, _mask) \ 4433 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082c9, (_val), (_mask)) 4434 4435 /* State Machine Status 3 Register */ 4436 #define READ_HL65_DSC3B1_SM_STATUS3r(_unit, _pc, _val) \ 4437 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ca, (_val)) 4438 #define WRITE_HL65_DSC3B1_SM_STATUS3r(_unit, _pc, _val) \ 4439 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ca, (_val)) 4440 #define MODIFY_HL65_DSC3B1_SM_STATUS3r(_unit, _pc, _val, _mask) \ 4441 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ca, (_val), (_mask)) 4442 4443 /* State Machine Status 4 Register */ 4444 #define READ_HL65_DSC3B1_SM_STATUS4r(_unit, _pc, _val) \ 4445 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082cb, (_val)) 4446 #define WRITE_HL65_DSC3B1_SM_STATUS4r(_unit, _pc, _val) \ 4447 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082cb, (_val)) 4448 #define MODIFY_HL65_DSC3B1_SM_STATUS4r(_unit, _pc, _val, _mask) \ 4449 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082cb, (_val), (_mask)) 4450 4451 /* DSC Analog Status 0 Register */ 4452 #define READ_HL65_DSC3B1_ANA_STATUS0r(_unit, _pc, _val) \ 4453 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082cc, (_val)) 4454 #define WRITE_HL65_DSC3B1_ANA_STATUS0r(_unit, _pc, _val) \ 4455 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082cc, (_val)) 4456 #define MODIFY_HL65_DSC3B1_ANA_STATUS0r(_unit, _pc, _val, _mask) \ 4457 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082cc, (_val), (_mask)) 4458 4459 /* State Machine Status 5 Register */ 4460 #define READ_HL65_DSC3B1_SM_STATUS5r(_unit, _pc, _val) \ 4461 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082cd, (_val)) 4462 #define WRITE_HL65_DSC3B1_SM_STATUS5r(_unit, _pc, _val) \ 4463 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082cd, (_val)) 4464 #define MODIFY_HL65_DSC3B1_SM_STATUS5r(_unit, _pc, _val, _mask) \ 4465 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082cd, (_val), (_mask)) 4466 4467 /* State Machine Status 6 Register */ 4468 #define READ_HL65_DSC3B1_SM_STATUS6r(_unit, _pc, _val) \ 4469 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ce, (_val)) 4470 #define WRITE_HL65_DSC3B1_SM_STATUS6r(_unit, _pc, _val) \ 4471 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ce, (_val)) 4472 #define MODIFY_HL65_DSC3B1_SM_STATUS6r(_unit, _pc, _val, _mask) \ 4473 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ce, (_val), (_mask)) 4474 4475 4476 /**************************************************************************** 4477 * Hypercore_USER_Dsc3b2 4478 */ 4479 4480 /* CDR Status 0 Register */ 4481 #define READ_HL65_DSC3B2_CDR_STATUS0r(_unit, _pc, _val) \ 4482 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d0, (_val)) 4483 #define WRITE_HL65_DSC3B2_CDR_STATUS0r(_unit, _pc, _val) \ 4484 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d0, (_val)) 4485 #define MODIFY_HL65_DSC3B2_CDR_STATUS0r(_unit, _pc, _val, _mask) \ 4486 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d0, (_val), (_mask)) 4487 4488 /* CDR Status 1 Register */ 4489 #define READ_HL65_DSC3B2_CDR_STATUS1r(_unit, _pc, _val) \ 4490 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d1, (_val)) 4491 #define WRITE_HL65_DSC3B2_CDR_STATUS1r(_unit, _pc, _val) \ 4492 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d1, (_val)) 4493 #define MODIFY_HL65_DSC3B2_CDR_STATUS1r(_unit, _pc, _val, _mask) \ 4494 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d1, (_val), (_mask)) 4495 4496 /* CDR Status 2 Register */ 4497 #define READ_HL65_DSC3B2_CDR_STATUS2r(_unit, _pc, _val) \ 4498 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d2, (_val)) 4499 #define WRITE_HL65_DSC3B2_CDR_STATUS2r(_unit, _pc, _val) \ 4500 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d2, (_val)) 4501 #define MODIFY_HL65_DSC3B2_CDR_STATUS2r(_unit, _pc, _val, _mask) \ 4502 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d2, (_val), (_mask)) 4503 4504 /* Phase Interpolator Status 0 Register */ 4505 #define READ_HL65_DSC3B2_PI_STATUS0r(_unit, _pc, _val) \ 4506 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d3, (_val)) 4507 #define WRITE_HL65_DSC3B2_PI_STATUS0r(_unit, _pc, _val) \ 4508 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d3, (_val)) 4509 #define MODIFY_HL65_DSC3B2_PI_STATUS0r(_unit, _pc, _val, _mask) \ 4510 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d3, (_val), (_mask)) 4511 4512 /* Phase Interpolator Status 1 Register */ 4513 #define READ_HL65_DSC3B2_PI_STATUS1r(_unit, _pc, _val) \ 4514 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d4, (_val)) 4515 #define WRITE_HL65_DSC3B2_PI_STATUS1r(_unit, _pc, _val) \ 4516 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d4, (_val)) 4517 #define MODIFY_HL65_DSC3B2_PI_STATUS1r(_unit, _pc, _val, _mask) \ 4518 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d4, (_val), (_mask)) 4519 4520 /* DFE VGA Status 0 Register */ 4521 #define READ_HL65_DSC3B2_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4522 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d5, (_val)) 4523 #define WRITE_HL65_DSC3B2_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4524 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d5, (_val)) 4525 #define MODIFY_HL65_DSC3B2_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \ 4526 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d5, (_val), (_mask)) 4527 4528 /* DFE VGA Status 1 Register */ 4529 #define READ_HL65_DSC3B2_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4530 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d6, (_val)) 4531 #define WRITE_HL65_DSC3B2_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4532 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d6, (_val)) 4533 #define MODIFY_HL65_DSC3B2_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \ 4534 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d6, (_val), (_mask)) 4535 4536 /* State Machine Status 0 Register */ 4537 #define READ_HL65_DSC3B2_SM_STATUS0r(_unit, _pc, _val) \ 4538 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d7, (_val)) 4539 #define WRITE_HL65_DSC3B2_SM_STATUS0r(_unit, _pc, _val) \ 4540 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d7, (_val)) 4541 #define MODIFY_HL65_DSC3B2_SM_STATUS0r(_unit, _pc, _val, _mask) \ 4542 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d7, (_val), (_mask)) 4543 4544 /* State Machine Status 1 Register */ 4545 #define READ_HL65_DSC3B2_SM_STATUS1r(_unit, _pc, _val) \ 4546 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d8, (_val)) 4547 #define WRITE_HL65_DSC3B2_SM_STATUS1r(_unit, _pc, _val) \ 4548 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d8, (_val)) 4549 #define MODIFY_HL65_DSC3B2_SM_STATUS1r(_unit, _pc, _val, _mask) \ 4550 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d8, (_val), (_mask)) 4551 4552 /* State Machine Status 2 Register */ 4553 #define READ_HL65_DSC3B2_SM_STATUS2r(_unit, _pc, _val) \ 4554 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082d9, (_val)) 4555 #define WRITE_HL65_DSC3B2_SM_STATUS2r(_unit, _pc, _val) \ 4556 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082d9, (_val)) 4557 #define MODIFY_HL65_DSC3B2_SM_STATUS2r(_unit, _pc, _val, _mask) \ 4558 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082d9, (_val), (_mask)) 4559 4560 /* State Machine Status 3 Register */ 4561 #define READ_HL65_DSC3B2_SM_STATUS3r(_unit, _pc, _val) \ 4562 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082da, (_val)) 4563 #define WRITE_HL65_DSC3B2_SM_STATUS3r(_unit, _pc, _val) \ 4564 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082da, (_val)) 4565 #define MODIFY_HL65_DSC3B2_SM_STATUS3r(_unit, _pc, _val, _mask) \ 4566 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082da, (_val), (_mask)) 4567 4568 /* State Machine Status 4 Register */ 4569 #define READ_HL65_DSC3B2_SM_STATUS4r(_unit, _pc, _val) \ 4570 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082db, (_val)) 4571 #define WRITE_HL65_DSC3B2_SM_STATUS4r(_unit, _pc, _val) \ 4572 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082db, (_val)) 4573 #define MODIFY_HL65_DSC3B2_SM_STATUS4r(_unit, _pc, _val, _mask) \ 4574 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082db, (_val), (_mask)) 4575 4576 /* DSC Analog Status 0 Register */ 4577 #define READ_HL65_DSC3B2_ANA_STATUS0r(_unit, _pc, _val) \ 4578 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082dc, (_val)) 4579 #define WRITE_HL65_DSC3B2_ANA_STATUS0r(_unit, _pc, _val) \ 4580 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082dc, (_val)) 4581 #define MODIFY_HL65_DSC3B2_ANA_STATUS0r(_unit, _pc, _val, _mask) \ 4582 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082dc, (_val), (_mask)) 4583 4584 /* State Machine Status 5 Register */ 4585 #define READ_HL65_DSC3B2_SM_STATUS5r(_unit, _pc, _val) \ 4586 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082dd, (_val)) 4587 #define WRITE_HL65_DSC3B2_SM_STATUS5r(_unit, _pc, _val) \ 4588 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082dd, (_val)) 4589 #define MODIFY_HL65_DSC3B2_SM_STATUS5r(_unit, _pc, _val, _mask) \ 4590 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082dd, (_val), (_mask)) 4591 4592 /* State Machine Status 6 Register */ 4593 #define READ_HL65_DSC3B2_SM_STATUS6r(_unit, _pc, _val) \ 4594 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082de, (_val)) 4595 #define WRITE_HL65_DSC3B2_SM_STATUS6r(_unit, _pc, _val) \ 4596 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082de, (_val)) 4597 #define MODIFY_HL65_DSC3B2_SM_STATUS6r(_unit, _pc, _val, _mask) \ 4598 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082de, (_val), (_mask)) 4599 4600 4601 /**************************************************************************** 4602 * Hypercore_USER_Dsc3b3 4603 */ 4604 4605 /* CDR Status 0 Register */ 4606 #define READ_HL65_DSC3B3_CDR_STATUS0r(_unit, _pc, _val) \ 4607 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e0, (_val)) 4608 #define WRITE_HL65_DSC3B3_CDR_STATUS0r(_unit, _pc, _val) \ 4609 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e0, (_val)) 4610 #define MODIFY_HL65_DSC3B3_CDR_STATUS0r(_unit, _pc, _val, _mask) \ 4611 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e0, (_val), (_mask)) 4612 4613 /* CDR Status 1 Register */ 4614 #define READ_HL65_DSC3B3_CDR_STATUS1r(_unit, _pc, _val) \ 4615 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e1, (_val)) 4616 #define WRITE_HL65_DSC3B3_CDR_STATUS1r(_unit, _pc, _val) \ 4617 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e1, (_val)) 4618 #define MODIFY_HL65_DSC3B3_CDR_STATUS1r(_unit, _pc, _val, _mask) \ 4619 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e1, (_val), (_mask)) 4620 4621 /* CDR Status 2 Register */ 4622 #define READ_HL65_DSC3B3_CDR_STATUS2r(_unit, _pc, _val) \ 4623 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e2, (_val)) 4624 #define WRITE_HL65_DSC3B3_CDR_STATUS2r(_unit, _pc, _val) \ 4625 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e2, (_val)) 4626 #define MODIFY_HL65_DSC3B3_CDR_STATUS2r(_unit, _pc, _val, _mask) \ 4627 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e2, (_val), (_mask)) 4628 4629 /* Phase Interpolator Status 0 Register */ 4630 #define READ_HL65_DSC3B3_PI_STATUS0r(_unit, _pc, _val) \ 4631 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e3, (_val)) 4632 #define WRITE_HL65_DSC3B3_PI_STATUS0r(_unit, _pc, _val) \ 4633 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e3, (_val)) 4634 #define MODIFY_HL65_DSC3B3_PI_STATUS0r(_unit, _pc, _val, _mask) \ 4635 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e3, (_val), (_mask)) 4636 4637 /* Phase Interpolator Status 1 Register */ 4638 #define READ_HL65_DSC3B3_PI_STATUS1r(_unit, _pc, _val) \ 4639 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e4, (_val)) 4640 #define WRITE_HL65_DSC3B3_PI_STATUS1r(_unit, _pc, _val) \ 4641 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e4, (_val)) 4642 #define MODIFY_HL65_DSC3B3_PI_STATUS1r(_unit, _pc, _val, _mask) \ 4643 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e4, (_val), (_mask)) 4644 4645 /* DFE VGA Status 0 Register */ 4646 #define READ_HL65_DSC3B3_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4647 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e5, (_val)) 4648 #define WRITE_HL65_DSC3B3_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4649 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e5, (_val)) 4650 #define MODIFY_HL65_DSC3B3_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \ 4651 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e5, (_val), (_mask)) 4652 4653 /* DFE VGA Status 1 Register */ 4654 #define READ_HL65_DSC3B3_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4655 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e6, (_val)) 4656 #define WRITE_HL65_DSC3B3_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4657 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e6, (_val)) 4658 #define MODIFY_HL65_DSC3B3_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \ 4659 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e6, (_val), (_mask)) 4660 4661 /* State Machine Status 0 Register */ 4662 #define READ_HL65_DSC3B3_SM_STATUS0r(_unit, _pc, _val) \ 4663 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e7, (_val)) 4664 #define WRITE_HL65_DSC3B3_SM_STATUS0r(_unit, _pc, _val) \ 4665 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e7, (_val)) 4666 #define MODIFY_HL65_DSC3B3_SM_STATUS0r(_unit, _pc, _val, _mask) \ 4667 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e7, (_val), (_mask)) 4668 4669 /* State Machine Status 1 Register */ 4670 #define READ_HL65_DSC3B3_SM_STATUS1r(_unit, _pc, _val) \ 4671 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e8, (_val)) 4672 #define WRITE_HL65_DSC3B3_SM_STATUS1r(_unit, _pc, _val) \ 4673 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e8, (_val)) 4674 #define MODIFY_HL65_DSC3B3_SM_STATUS1r(_unit, _pc, _val, _mask) \ 4675 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e8, (_val), (_mask)) 4676 4677 /* State Machine Status 2 Register */ 4678 #define READ_HL65_DSC3B3_SM_STATUS2r(_unit, _pc, _val) \ 4679 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082e9, (_val)) 4680 #define WRITE_HL65_DSC3B3_SM_STATUS2r(_unit, _pc, _val) \ 4681 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082e9, (_val)) 4682 #define MODIFY_HL65_DSC3B3_SM_STATUS2r(_unit, _pc, _val, _mask) \ 4683 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082e9, (_val), (_mask)) 4684 4685 /* State Machine Status 3 Register */ 4686 #define READ_HL65_DSC3B3_SM_STATUS3r(_unit, _pc, _val) \ 4687 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ea, (_val)) 4688 #define WRITE_HL65_DSC3B3_SM_STATUS3r(_unit, _pc, _val) \ 4689 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ea, (_val)) 4690 #define MODIFY_HL65_DSC3B3_SM_STATUS3r(_unit, _pc, _val, _mask) \ 4691 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ea, (_val), (_mask)) 4692 4693 /* State Machine Status 4 Register */ 4694 #define READ_HL65_DSC3B3_SM_STATUS4r(_unit, _pc, _val) \ 4695 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082eb, (_val)) 4696 #define WRITE_HL65_DSC3B3_SM_STATUS4r(_unit, _pc, _val) \ 4697 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082eb, (_val)) 4698 #define MODIFY_HL65_DSC3B3_SM_STATUS4r(_unit, _pc, _val, _mask) \ 4699 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082eb, (_val), (_mask)) 4700 4701 /* DSC Analog Status 0 Register */ 4702 #define READ_HL65_DSC3B3_ANA_STATUS0r(_unit, _pc, _val) \ 4703 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ec, (_val)) 4704 #define WRITE_HL65_DSC3B3_ANA_STATUS0r(_unit, _pc, _val) \ 4705 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ec, (_val)) 4706 #define MODIFY_HL65_DSC3B3_ANA_STATUS0r(_unit, _pc, _val, _mask) \ 4707 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ec, (_val), (_mask)) 4708 4709 /* State Machine Status 5 Register */ 4710 #define READ_HL65_DSC3B3_SM_STATUS5r(_unit, _pc, _val) \ 4711 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ed, (_val)) 4712 #define WRITE_HL65_DSC3B3_SM_STATUS5r(_unit, _pc, _val) \ 4713 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ed, (_val)) 4714 #define MODIFY_HL65_DSC3B3_SM_STATUS5r(_unit, _pc, _val, _mask) \ 4715 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ed, (_val), (_mask)) 4716 4717 /* State Machine Status 6 Register */ 4718 #define READ_HL65_DSC3B3_SM_STATUS6r(_unit, _pc, _val) \ 4719 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082ee, (_val)) 4720 #define WRITE_HL65_DSC3B3_SM_STATUS6r(_unit, _pc, _val) \ 4721 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082ee, (_val)) 4722 #define MODIFY_HL65_DSC3B3_SM_STATUS6r(_unit, _pc, _val, _mask) \ 4723 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082ee, (_val), (_mask)) 4724 4725 4726 /**************************************************************************** 4727 * Hypercore_USER_Dsc3bB 4728 */ 4729 4730 /* CDR Status 0 Register */ 4731 #define READ_HL65_DSC3BB_CDR_STATUS0r(_unit, _pc, _val) \ 4732 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f0, (_val)) 4733 #define WRITE_HL65_DSC3BB_CDR_STATUS0r(_unit, _pc, _val) \ 4734 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f0, (_val)) 4735 #define MODIFY_HL65_DSC3BB_CDR_STATUS0r(_unit, _pc, _val, _mask) \ 4736 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f0, (_val), (_mask)) 4737 4738 /* CDR Status 1 Register */ 4739 #define READ_HL65_DSC3BB_CDR_STATUS1r(_unit, _pc, _val) \ 4740 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f1, (_val)) 4741 #define WRITE_HL65_DSC3BB_CDR_STATUS1r(_unit, _pc, _val) \ 4742 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f1, (_val)) 4743 #define MODIFY_HL65_DSC3BB_CDR_STATUS1r(_unit, _pc, _val, _mask) \ 4744 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f1, (_val), (_mask)) 4745 4746 /* CDR Status 2 Register */ 4747 #define READ_HL65_DSC3BB_CDR_STATUS2r(_unit, _pc, _val) \ 4748 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f2, (_val)) 4749 #define WRITE_HL65_DSC3BB_CDR_STATUS2r(_unit, _pc, _val) \ 4750 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f2, (_val)) 4751 #define MODIFY_HL65_DSC3BB_CDR_STATUS2r(_unit, _pc, _val, _mask) \ 4752 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f2, (_val), (_mask)) 4753 4754 /* Phase Interpolator Status 0 Register */ 4755 #define READ_HL65_DSC3BB_PI_STATUS0r(_unit, _pc, _val) \ 4756 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f3, (_val)) 4757 #define WRITE_HL65_DSC3BB_PI_STATUS0r(_unit, _pc, _val) \ 4758 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f3, (_val)) 4759 #define MODIFY_HL65_DSC3BB_PI_STATUS0r(_unit, _pc, _val, _mask) \ 4760 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f3, (_val), (_mask)) 4761 4762 /* Phase Interpolator Status 1 Register */ 4763 #define READ_HL65_DSC3BB_PI_STATUS1r(_unit, _pc, _val) \ 4764 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f4, (_val)) 4765 #define WRITE_HL65_DSC3BB_PI_STATUS1r(_unit, _pc, _val) \ 4766 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f4, (_val)) 4767 #define MODIFY_HL65_DSC3BB_PI_STATUS1r(_unit, _pc, _val, _mask) \ 4768 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f4, (_val), (_mask)) 4769 4770 /* DFE VGA Status 0 Register */ 4771 #define READ_HL65_DSC3BB_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4772 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f5, (_val)) 4773 #define WRITE_HL65_DSC3BB_DFE_VGA_STATUS0r(_unit, _pc, _val) \ 4774 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f5, (_val)) 4775 #define MODIFY_HL65_DSC3BB_DFE_VGA_STATUS0r(_unit, _pc, _val, _mask) \ 4776 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f5, (_val), (_mask)) 4777 4778 /* DFE VGA Status 1 Register */ 4779 #define READ_HL65_DSC3BB_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4780 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f6, (_val)) 4781 #define WRITE_HL65_DSC3BB_DFE_VGA_STATUS1r(_unit, _pc, _val) \ 4782 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f6, (_val)) 4783 #define MODIFY_HL65_DSC3BB_DFE_VGA_STATUS1r(_unit, _pc, _val, _mask) \ 4784 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f6, (_val), (_mask)) 4785 4786 /* State Machine Status 0 Register */ 4787 #define READ_HL65_DSC3BB_SM_STATUS0r(_unit, _pc, _val) \ 4788 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f7, (_val)) 4789 #define WRITE_HL65_DSC3BB_SM_STATUS0r(_unit, _pc, _val) \ 4790 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f7, (_val)) 4791 #define MODIFY_HL65_DSC3BB_SM_STATUS0r(_unit, _pc, _val, _mask) \ 4792 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f7, (_val), (_mask)) 4793 4794 /* State Machine Status 1 Register */ 4795 #define READ_HL65_DSC3BB_SM_STATUS1r(_unit, _pc, _val) \ 4796 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f8, (_val)) 4797 #define WRITE_HL65_DSC3BB_SM_STATUS1r(_unit, _pc, _val) \ 4798 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f8, (_val)) 4799 #define MODIFY_HL65_DSC3BB_SM_STATUS1r(_unit, _pc, _val, _mask) \ 4800 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f8, (_val), (_mask)) 4801 4802 /* State Machine Status 2 Register */ 4803 #define READ_HL65_DSC3BB_SM_STATUS2r(_unit, _pc, _val) \ 4804 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082f9, (_val)) 4805 #define WRITE_HL65_DSC3BB_SM_STATUS2r(_unit, _pc, _val) \ 4806 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082f9, (_val)) 4807 #define MODIFY_HL65_DSC3BB_SM_STATUS2r(_unit, _pc, _val, _mask) \ 4808 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082f9, (_val), (_mask)) 4809 4810 /* State Machine Status 3 Register */ 4811 #define READ_HL65_DSC3BB_SM_STATUS3r(_unit, _pc, _val) \ 4812 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fa, (_val)) 4813 #define WRITE_HL65_DSC3BB_SM_STATUS3r(_unit, _pc, _val) \ 4814 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fa, (_val)) 4815 #define MODIFY_HL65_DSC3BB_SM_STATUS3r(_unit, _pc, _val, _mask) \ 4816 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fa, (_val), (_mask)) 4817 4818 /* State Machine Status 4 Register */ 4819 #define READ_HL65_DSC3BB_SM_STATUS4r(_unit, _pc, _val) \ 4820 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fb, (_val)) 4821 #define WRITE_HL65_DSC3BB_SM_STATUS4r(_unit, _pc, _val) \ 4822 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fb, (_val)) 4823 #define MODIFY_HL65_DSC3BB_SM_STATUS4r(_unit, _pc, _val, _mask) \ 4824 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fb, (_val), (_mask)) 4825 4826 /* DSC Analog Status 0 Register */ 4827 #define READ_HL65_DSC3BB_ANA_STATUS0r(_unit, _pc, _val) \ 4828 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fc, (_val)) 4829 #define WRITE_HL65_DSC3BB_ANA_STATUS0r(_unit, _pc, _val) \ 4830 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fc, (_val)) 4831 #define MODIFY_HL65_DSC3BB_ANA_STATUS0r(_unit, _pc, _val, _mask) \ 4832 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fc, (_val), (_mask)) 4833 4834 /* State Machine Status 5 Register */ 4835 #define READ_HL65_DSC3BB_SM_STATUS5r(_unit, _pc, _val) \ 4836 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fd, (_val)) 4837 #define WRITE_HL65_DSC3BB_SM_STATUS5r(_unit, _pc, _val) \ 4838 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fd, (_val)) 4839 #define MODIFY_HL65_DSC3BB_SM_STATUS5r(_unit, _pc, _val, _mask) \ 4840 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fd, (_val), (_mask)) 4841 4842 /* State Machine Status 6 Register */ 4843 #define READ_HL65_DSC3BB_SM_STATUS6r(_unit, _pc, _val) \ 4844 HL65_REG_READ((_unit), (_pc), 0x00, 0x000082fe, (_val)) 4845 #define WRITE_HL65_DSC3BB_SM_STATUS6r(_unit, _pc, _val) \ 4846 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000082fe, (_val)) 4847 #define MODIFY_HL65_DSC3BB_SM_STATUS6r(_unit, _pc, _val, _mask) \ 4848 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000082fe, (_val), (_mask)) 4849 4850 4851 /**************************************************************************** 4852 * Hypercore_USER_Digital 4853 */ 4854 4855 /* 1000X control 1 register */ 4856 #define READ_HL65_DIGITAL_CONTROL1000X1r(_unit, _pc, _val) \ 4857 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008300, (_val)) 4858 #define WRITE_HL65_DIGITAL_CONTROL1000X1r(_unit, _pc, _val) \ 4859 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008300, (_val)) 4860 #define MODIFY_HL65_DIGITAL_CONTROL1000X1r(_unit, _pc, _val, _mask) \ 4861 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008300, (_val), (_mask)) 4862 4863 /* 1000X control 2 register */ 4864 #define READ_HL65_DIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 4865 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008301, (_val)) 4866 #define WRITE_HL65_DIGITAL_CONTROL1000X2r(_unit, _pc, _val) \ 4867 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008301, (_val)) 4868 #define MODIFY_HL65_DIGITAL_CONTROL1000X2r(_unit, _pc, _val, _mask) \ 4869 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008301, (_val), (_mask)) 4870 4871 /* 1000X control 3 register */ 4872 #define READ_HL65_DIGITAL_CONTROL1000X3r(_unit, _pc, _val) \ 4873 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008302, (_val)) 4874 #define WRITE_HL65_DIGITAL_CONTROL1000X3r(_unit, _pc, _val) \ 4875 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008302, (_val)) 4876 #define MODIFY_HL65_DIGITAL_CONTROL1000X3r(_unit, _pc, _val, _mask) \ 4877 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008302, (_val), (_mask)) 4878 4879 /* 1000X control 4 register */ 4880 #define READ_HL65_DIGITAL_CONTROL1000X4r(_unit, _pc, _val) \ 4881 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008303, (_val)) 4882 #define WRITE_HL65_DIGITAL_CONTROL1000X4r(_unit, _pc, _val) \ 4883 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008303, (_val)) 4884 #define MODIFY_HL65_DIGITAL_CONTROL1000X4r(_unit, _pc, _val, _mask) \ 4885 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008303, (_val), (_mask)) 4886 4887 /* 1000X status 1 register */ 4888 #define READ_HL65_DIGITAL_STATUS1000X1r(_unit, _pc, _val) \ 4889 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008304, (_val)) 4890 #define WRITE_HL65_DIGITAL_STATUS1000X1r(_unit, _pc, _val) \ 4891 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008304, (_val)) 4892 #define MODIFY_HL65_DIGITAL_STATUS1000X1r(_unit, _pc, _val, _mask) \ 4893 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008304, (_val), (_mask)) 4894 4895 /* 1000X status 2 register */ 4896 #define READ_HL65_DIGITAL_STATUS1000X2r(_unit, _pc, _val) \ 4897 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008305, (_val)) 4898 #define WRITE_HL65_DIGITAL_STATUS1000X2r(_unit, _pc, _val) \ 4899 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008305, (_val)) 4900 #define MODIFY_HL65_DIGITAL_STATUS1000X2r(_unit, _pc, _val, _mask) \ 4901 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008305, (_val), (_mask)) 4902 4903 /* 1000X status 3 register */ 4904 #define READ_HL65_DIGITAL_STATUS1000X3r(_unit, _pc, _val) \ 4905 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008306, (_val)) 4906 #define WRITE_HL65_DIGITAL_STATUS1000X3r(_unit, _pc, _val) \ 4907 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008306, (_val)) 4908 #define MODIFY_HL65_DIGITAL_STATUS1000X3r(_unit, _pc, _val, _mask) \ 4909 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008306, (_val), (_mask)) 4910 4911 /* Invalid code group count register */ 4912 #define READ_HL65_DIGITAL_BADCODEGROUPr(_unit, _pc, _val) \ 4913 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008307, (_val)) 4914 #define WRITE_HL65_DIGITAL_BADCODEGROUPr(_unit, _pc, _val) \ 4915 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008307, (_val)) 4916 #define MODIFY_HL65_DIGITAL_BADCODEGROUPr(_unit, _pc, _val, _mask) \ 4917 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008307, (_val), (_mask)) 4918 4919 /* Miscellaneous 1 control register */ 4920 #define READ_HL65_DIGITAL_MISC1r(_unit, _pc, _val) \ 4921 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008308, (_val)) 4922 #define WRITE_HL65_DIGITAL_MISC1r(_unit, _pc, _val) \ 4923 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008308, (_val)) 4924 #define MODIFY_HL65_DIGITAL_MISC1r(_unit, _pc, _val, _mask) \ 4925 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008308, (_val), (_mask)) 4926 4927 /* Miscellaneous 2 control register */ 4928 #define READ_HL65_DIGITAL_MISC2r(_unit, _pc, _val) \ 4929 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008309, (_val)) 4930 #define WRITE_HL65_DIGITAL_MISC2r(_unit, _pc, _val) \ 4931 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008309, (_val)) 4932 #define MODIFY_HL65_DIGITAL_MISC2r(_unit, _pc, _val, _mask) \ 4933 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008309, (_val), (_mask)) 4934 4935 /* Pattern generator control register */ 4936 #define READ_HL65_DIGITAL_PATGENCTRLr(_unit, _pc, _val) \ 4937 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830a, (_val)) 4938 #define WRITE_HL65_DIGITAL_PATGENCTRLr(_unit, _pc, _val) \ 4939 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830a, (_val)) 4940 #define MODIFY_HL65_DIGITAL_PATGENCTRLr(_unit, _pc, _val, _mask) \ 4941 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830a, (_val), (_mask)) 4942 4943 /* Pattern generator status register */ 4944 #define READ_HL65_DIGITAL_PATGENSTATr(_unit, _pc, _val) \ 4945 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830b, (_val)) 4946 #define WRITE_HL65_DIGITAL_PATGENSTATr(_unit, _pc, _val) \ 4947 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830b, (_val)) 4948 #define MODIFY_HL65_DIGITAL_PATGENSTATr(_unit, _pc, _val, _mask) \ 4949 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830b, (_val), (_mask)) 4950 4951 /* Test mode register */ 4952 #define READ_HL65_DIGITAL_TESTMODEr(_unit, _pc, _val) \ 4953 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830c, (_val)) 4954 #define WRITE_HL65_DIGITAL_TESTMODEr(_unit, _pc, _val) \ 4955 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830c, (_val)) 4956 #define MODIFY_HL65_DIGITAL_TESTMODEr(_unit, _pc, _val, _mask) \ 4957 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830c, (_val), (_mask)) 4958 4959 /* Tx packet count register */ 4960 #define READ_HL65_DIGITAL_TXPKTCNTr(_unit, _pc, _val) \ 4961 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830d, (_val)) 4962 #define WRITE_HL65_DIGITAL_TXPKTCNTr(_unit, _pc, _val) \ 4963 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830d, (_val)) 4964 #define MODIFY_HL65_DIGITAL_TXPKTCNTr(_unit, _pc, _val, _mask) \ 4965 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830d, (_val), (_mask)) 4966 4967 /* Rx packet count register */ 4968 #define READ_HL65_DIGITAL_RXPKTCNTr(_unit, _pc, _val) \ 4969 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000830e, (_val)) 4970 #define WRITE_HL65_DIGITAL_RXPKTCNTr(_unit, _pc, _val) \ 4971 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000830e, (_val)) 4972 #define MODIFY_HL65_DIGITAL_RXPKTCNTr(_unit, _pc, _val, _mask) \ 4973 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000830e, (_val), (_mask)) 4974 4975 4976 /**************************************************************************** 4977 * Hypercore_USER_Test 4978 */ 4979 4980 /* Serdes ID 0 register */ 4981 #define READ_HL65_TEST_SERDESID0r(_unit, _pc, _val) \ 4982 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008310, (_val)) 4983 #define WRITE_HL65_TEST_SERDESID0r(_unit, _pc, _val) \ 4984 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008310, (_val)) 4985 #define MODIFY_HL65_TEST_SERDESID0r(_unit, _pc, _val, _mask) \ 4986 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008310, (_val), (_mask)) 4987 4988 /* Serdes ID 1 register */ 4989 #define READ_HL65_TEST_SERDESID1r(_unit, _pc, _val) \ 4990 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008311, (_val)) 4991 #define WRITE_HL65_TEST_SERDESID1r(_unit, _pc, _val) \ 4992 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008311, (_val)) 4993 #define MODIFY_HL65_TEST_SERDESID1r(_unit, _pc, _val, _mask) \ 4994 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008311, (_val), (_mask)) 4995 4996 /* Serdes ID 2 register */ 4997 #define READ_HL65_TEST_SERDESID2r(_unit, _pc, _val) \ 4998 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008312, (_val)) 4999 #define WRITE_HL65_TEST_SERDESID2r(_unit, _pc, _val) \ 5000 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008312, (_val)) 5001 #define MODIFY_HL65_TEST_SERDESID2r(_unit, _pc, _val, _mask) \ 5002 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008312, (_val), (_mask)) 5003 5004 /* Serdes ID 3 register */ 5005 #define READ_HL65_TEST_SERDESID3r(_unit, _pc, _val) \ 5006 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008313, (_val)) 5007 #define WRITE_HL65_TEST_SERDESID3r(_unit, _pc, _val) \ 5008 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008313, (_val)) 5009 #define MODIFY_HL65_TEST_SERDESID3r(_unit, _pc, _val, _mask) \ 5010 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008313, (_val), (_mask)) 5011 5012 5013 /**************************************************************************** 5014 * Hypercore_USER_Digital3 5015 */ 5016 5017 /* AN lost link count time, bits 15:0 */ 5018 #define READ_HL65_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val) \ 5019 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008320, (_val)) 5020 #define WRITE_HL65_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val) \ 5021 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008320, (_val)) 5022 #define MODIFY_HL65_DIGITAL3_DIGCTL_3_0r(_unit, _pc, _val, _mask) \ 5023 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008320, (_val), (_mask)) 5024 5025 /* AN switch count time, bits 15:0 */ 5026 #define READ_HL65_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val) \ 5027 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008321, (_val)) 5028 #define WRITE_HL65_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val) \ 5029 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008321, (_val)) 5030 #define MODIFY_HL65_DIGITAL3_DIGCTL_3_1r(_unit, _pc, _val, _mask) \ 5031 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008321, (_val), (_mask)) 5032 5033 /* AN link count time, bits 15:0 */ 5034 #define READ_HL65_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val) \ 5035 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008322, (_val)) 5036 #define WRITE_HL65_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val) \ 5037 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008322, (_val)) 5038 #define MODIFY_HL65_DIGITAL3_DIGCTL_3_2r(_unit, _pc, _val, _mask) \ 5039 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008322, (_val), (_mask)) 5040 5041 /* AN switch count & link count time, bits 23:16 */ 5042 #define READ_HL65_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val) \ 5043 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008323, (_val)) 5044 #define WRITE_HL65_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val) \ 5045 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008323, (_val)) 5046 #define MODIFY_HL65_DIGITAL3_DIGCTL_3_3r(_unit, _pc, _val, _mask) \ 5047 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008323, (_val), (_mask)) 5048 5049 /* Over 1G message page number & AN fail count timer */ 5050 #define READ_HL65_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val) \ 5051 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008324, (_val)) 5052 #define WRITE_HL65_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val) \ 5053 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008324, (_val)) 5054 #define MODIFY_HL65_DIGITAL3_DIGCTL_3_4r(_unit, _pc, _val, _mask) \ 5055 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008324, (_val), (_mask)) 5056 5057 /* AN ignore link count time, bits 15:0 */ 5058 #define READ_HL65_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val) \ 5059 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008325, (_val)) 5060 #define WRITE_HL65_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val) \ 5061 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008325, (_val)) 5062 #define MODIFY_HL65_DIGITAL3_DIGCTL_3_5r(_unit, _pc, _val, _mask) \ 5063 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008325, (_val), (_mask)) 5064 5065 /* AN lost link count & ignore link count time, bits 23:16 */ 5066 #define READ_HL65_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val) \ 5067 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008326, (_val)) 5068 #define WRITE_HL65_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val) \ 5069 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008326, (_val)) 5070 #define MODIFY_HL65_DIGITAL3_DIGCTL_3_6r(_unit, _pc, _val, _mask) \ 5071 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008326, (_val), (_mask)) 5072 5073 /* Test port out bits 15:0, tpout[15:0] */ 5074 #define READ_HL65_DIGITAL3_TPOUT_1r(_unit, _pc, _val) \ 5075 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008327, (_val)) 5076 #define WRITE_HL65_DIGITAL3_TPOUT_1r(_unit, _pc, _val) \ 5077 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008327, (_val)) 5078 #define MODIFY_HL65_DIGITAL3_TPOUT_1r(_unit, _pc, _val, _mask) \ 5079 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008327, (_val), (_mask)) 5080 5081 /* Test port out bits 23:8, tpout[23:8] */ 5082 #define READ_HL65_DIGITAL3_TPOUT_2r(_unit, _pc, _val) \ 5083 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008328, (_val)) 5084 #define WRITE_HL65_DIGITAL3_TPOUT_2r(_unit, _pc, _val) \ 5085 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008328, (_val)) 5086 #define MODIFY_HL65_DIGITAL3_TPOUT_2r(_unit, _pc, _val, _mask) \ 5087 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008328, (_val), (_mask)) 5088 5089 /* AN local device user page 1 */ 5090 #define READ_HL65_DIGITAL3_UP1r(_unit, _pc, _val) \ 5091 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008329, (_val)) 5092 #define WRITE_HL65_DIGITAL3_UP1r(_unit, _pc, _val) \ 5093 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008329, (_val)) 5094 #define MODIFY_HL65_DIGITAL3_UP1r(_unit, _pc, _val, _mask) \ 5095 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008329, (_val), (_mask)) 5096 5097 /* AN local device user page 2 */ 5098 #define READ_HL65_DIGITAL3_UP2r(_unit, _pc, _val) \ 5099 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832a, (_val)) 5100 #define WRITE_HL65_DIGITAL3_UP2r(_unit, _pc, _val) \ 5101 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832a, (_val)) 5102 #define MODIFY_HL65_DIGITAL3_UP2r(_unit, _pc, _val, _mask) \ 5103 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832a, (_val), (_mask)) 5104 5105 /* AN local device user page 3 */ 5106 #define READ_HL65_DIGITAL3_UP3r(_unit, _pc, _val) \ 5107 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832b, (_val)) 5108 #define WRITE_HL65_DIGITAL3_UP3r(_unit, _pc, _val) \ 5109 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832b, (_val)) 5110 #define MODIFY_HL65_DIGITAL3_UP3r(_unit, _pc, _val, _mask) \ 5111 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832b, (_val), (_mask)) 5112 5113 /* AN link partner user page 1 */ 5114 #define READ_HL65_DIGITAL3_LP_UP1r(_unit, _pc, _val) \ 5115 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832c, (_val)) 5116 #define WRITE_HL65_DIGITAL3_LP_UP1r(_unit, _pc, _val) \ 5117 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832c, (_val)) 5118 #define MODIFY_HL65_DIGITAL3_LP_UP1r(_unit, _pc, _val, _mask) \ 5119 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832c, (_val), (_mask)) 5120 5121 /* AN link partner user page 2 */ 5122 #define READ_HL65_DIGITAL3_LP_UP2r(_unit, _pc, _val) \ 5123 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832d, (_val)) 5124 #define WRITE_HL65_DIGITAL3_LP_UP2r(_unit, _pc, _val) \ 5125 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832d, (_val)) 5126 #define MODIFY_HL65_DIGITAL3_LP_UP2r(_unit, _pc, _val, _mask) \ 5127 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832d, (_val), (_mask)) 5128 5129 /* AN link partner user page 3 */ 5130 #define READ_HL65_DIGITAL3_LP_UP3r(_unit, _pc, _val) \ 5131 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000832e, (_val)) 5132 #define WRITE_HL65_DIGITAL3_LP_UP3r(_unit, _pc, _val) \ 5133 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000832e, (_val)) 5134 #define MODIFY_HL65_DIGITAL3_LP_UP3r(_unit, _pc, _val, _mask) \ 5135 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000832e, (_val), (_mask)) 5136 5137 5138 /**************************************************************************** 5139 * Hypercore_USER_Digital4 5140 */ 5141 5142 /* Miscellaneous Rx status register */ 5143 #define READ_HL65_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val) \ 5144 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008330, (_val)) 5145 #define WRITE_HL65_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val) \ 5146 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008330, (_val)) 5147 #define MODIFY_HL65_DIGITAL4_MISCRXSTATUSr(_unit, _pc, _val, _mask) \ 5148 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008330, (_val), (_mask)) 5149 5150 /* Link partner basepage register */ 5151 #define READ_HL65_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val) \ 5152 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008331, (_val)) 5153 #define WRITE_HL65_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val) \ 5154 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008331, (_val)) 5155 #define MODIFY_HL65_DIGITAL4_LP_BASEPAGEr(_unit, _pc, _val, _mask) \ 5156 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008331, (_val), (_mask)) 5157 5158 /* Link partner nextpage 0 register */ 5159 #define READ_HL65_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val) \ 5160 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008332, (_val)) 5161 #define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val) \ 5162 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008332, (_val)) 5163 #define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \ 5164 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008332, (_val), (_mask)) 5165 5166 /* Link partner nextpage 1 register */ 5167 #define READ_HL65_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val) \ 5168 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008333, (_val)) 5169 #define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val) \ 5170 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008333, (_val)) 5171 #define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \ 5172 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008333, (_val), (_mask)) 5173 5174 /* Link partner nextpage 2 register */ 5175 #define READ_HL65_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val) \ 5176 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008334, (_val)) 5177 #define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val) \ 5178 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008334, (_val)) 5179 #define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \ 5180 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008334, (_val), (_mask)) 5181 5182 /* Link partner nextpage 3 register */ 5183 #define READ_HL65_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val) \ 5184 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008335, (_val)) 5185 #define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val) \ 5186 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008335, (_val)) 5187 #define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \ 5188 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008335, (_val), (_mask)) 5189 5190 /* Link partner nextpage 4 register */ 5191 #define READ_HL65_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val) \ 5192 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008336, (_val)) 5193 #define WRITE_HL65_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val) \ 5194 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008336, (_val)) 5195 #define MODIFY_HL65_DIGITAL4_LP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \ 5196 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008336, (_val), (_mask)) 5197 5198 /* Remote phy nextpage 0 register */ 5199 #define READ_HL65_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val) \ 5200 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008337, (_val)) 5201 #define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val) \ 5202 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008337, (_val)) 5203 #define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_0r(_unit, _pc, _val, _mask) \ 5204 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008337, (_val), (_mask)) 5205 5206 /* Remote phy nextpage 1 register */ 5207 #define READ_HL65_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val) \ 5208 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008338, (_val)) 5209 #define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val) \ 5210 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008338, (_val)) 5211 #define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_1r(_unit, _pc, _val, _mask) \ 5212 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008338, (_val), (_mask)) 5213 5214 /* Remote phy nextpage 2 register */ 5215 #define READ_HL65_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val) \ 5216 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008339, (_val)) 5217 #define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val) \ 5218 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008339, (_val)) 5219 #define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_2r(_unit, _pc, _val, _mask) \ 5220 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008339, (_val), (_mask)) 5221 5222 /* Remote phy nextpage 3 register */ 5223 #define READ_HL65_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val) \ 5224 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000833a, (_val)) 5225 #define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val) \ 5226 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000833a, (_val)) 5227 #define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_3r(_unit, _pc, _val, _mask) \ 5228 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833a, (_val), (_mask)) 5229 5230 /* Remote phy nextpage 4 register */ 5231 #define READ_HL65_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val) \ 5232 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000833b, (_val)) 5233 #define WRITE_HL65_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val) \ 5234 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000833b, (_val)) 5235 #define MODIFY_HL65_DIGITAL4_RP_NEXTPAGE_4r(_unit, _pc, _val, _mask) \ 5236 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833b, (_val), (_mask)) 5237 5238 /* Miscellaneous 3 control register */ 5239 #define READ_HL65_DIGITAL4_MISC3r(_unit, _pc, _val) \ 5240 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000833c, (_val)) 5241 #define WRITE_HL65_DIGITAL4_MISC3r(_unit, _pc, _val) \ 5242 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000833c, (_val)) 5243 #define MODIFY_HL65_DIGITAL4_MISC3r(_unit, _pc, _val, _mask) \ 5244 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000833c, (_val), (_mask)) 5245 5246 5247 /**************************************************************************** 5248 * Hypercore_USER_Digital6 5249 */ 5250 5251 /* MP5, Message Page 5, next page control register */ 5252 #define READ_HL65_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \ 5253 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008350, (_val)) 5254 #define WRITE_HL65_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val) \ 5255 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008350, (_val)) 5256 #define MODIFY_HL65_DIGITAL6_MP5_NEXTPAGECTRLr(_unit, _pc, _val, _mask) \ 5257 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008350, (_val), (_mask)) 5258 5259 /* sgmii & max timer offsets */ 5260 #define READ_HL65_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \ 5261 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008351, (_val)) 5262 #define WRITE_HL65_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val) \ 5263 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008351, (_val)) 5264 #define MODIFY_HL65_DIGITAL6_LINK_TIMER_OFFSET1r(_unit, _pc, _val, _mask) \ 5265 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008351, (_val), (_mask)) 5266 5267 /* link up & link down timer offsets */ 5268 #define READ_HL65_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \ 5269 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008352, (_val)) 5270 #define WRITE_HL65_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val) \ 5271 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008352, (_val)) 5272 #define MODIFY_HL65_DIGITAL6_LINK_TIMER_OFFSET2r(_unit, _pc, _val, _mask) \ 5273 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008352, (_val), (_mask)) 5274 5275 /* break link & next page link timer offsets */ 5276 #define READ_HL65_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \ 5277 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008353, (_val)) 5278 #define WRITE_HL65_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val) \ 5279 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008353, (_val)) 5280 #define MODIFY_HL65_DIGITAL6_LINK_TIMER_OFFSET3r(_unit, _pc, _val, _mask) \ 5281 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008353, (_val), (_mask)) 5282 5283 /* 11 MSbits of the oui, oui[23:13] */ 5284 #define READ_HL65_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val) \ 5285 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008354, (_val)) 5286 #define WRITE_HL65_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val) \ 5287 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008354, (_val)) 5288 #define MODIFY_HL65_DIGITAL6_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \ 5289 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008354, (_val), (_mask)) 5290 5291 /* 11 middle bits of the oui, oui[12:2] */ 5292 #define READ_HL65_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val) \ 5293 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008355, (_val)) 5294 #define WRITE_HL65_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val) \ 5295 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008355, (_val)) 5296 #define MODIFY_HL65_DIGITAL6_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \ 5297 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008355, (_val), (_mask)) 5298 5299 /* 2 LSbits of the oui, oui[1:0] */ 5300 #define READ_HL65_DIGITAL6_BAM_FIELDr(_unit, _pc, _val) \ 5301 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008356, (_val)) 5302 #define WRITE_HL65_DIGITAL6_BAM_FIELDr(_unit, _pc, _val) \ 5303 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008356, (_val)) 5304 #define MODIFY_HL65_DIGITAL6_BAM_FIELDr(_unit, _pc, _val, _mask) \ 5305 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008356, (_val), (_mask)) 5306 5307 /* User defined field of MP5 */ 5308 #define READ_HL65_DIGITAL6_UD_FIELDr(_unit, _pc, _val) \ 5309 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008357, (_val)) 5310 #define WRITE_HL65_DIGITAL6_UD_FIELDr(_unit, _pc, _val) \ 5311 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008357, (_val)) 5312 #define MODIFY_HL65_DIGITAL6_UD_FIELDr(_unit, _pc, _val, _mask) \ 5313 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008357, (_val), (_mask)) 5314 5315 /* Link partner's 11 MSbits of the oui, oui[23:13] */ 5316 #define READ_HL65_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \ 5317 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008358, (_val)) 5318 #define WRITE_HL65_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val) \ 5319 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008358, (_val)) 5320 #define MODIFY_HL65_DIGITAL6_LP_OUI_MSB_FIELDr(_unit, _pc, _val, _mask) \ 5321 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008358, (_val), (_mask)) 5322 5323 /* Link partner's 11 middle bits of the oui, oui[12:2] */ 5324 #define READ_HL65_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \ 5325 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008359, (_val)) 5326 #define WRITE_HL65_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val) \ 5327 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008359, (_val)) 5328 #define MODIFY_HL65_DIGITAL6_LP_OUI_LSB_FIELDr(_unit, _pc, _val, _mask) \ 5329 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008359, (_val), (_mask)) 5330 5331 /* Link partner's 2 LSbits of the oui, oui[1:0] */ 5332 #define READ_HL65_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val) \ 5333 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000835a, (_val)) 5334 #define WRITE_HL65_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val) \ 5335 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000835a, (_val)) 5336 #define MODIFY_HL65_DIGITAL6_LP_BAM_FIELDr(_unit, _pc, _val, _mask) \ 5337 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835a, (_val), (_mask)) 5338 5339 /* Link partner's User defined field of MP5 */ 5340 #define READ_HL65_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val) \ 5341 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000835b, (_val)) 5342 #define WRITE_HL65_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val) \ 5343 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000835b, (_val)) 5344 #define MODIFY_HL65_DIGITAL6_LP_UD_FIELDr(_unit, _pc, _val, _mask) \ 5345 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000835b, (_val), (_mask)) 5346 5347 5348 /**************************************************************************** 5349 * Hypercore_USER_CL73_UserB0 5350 */ 5351 5352 /* Clause 73 user control */ 5353 #define READ_HL65_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \ 5354 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008370, (_val)) 5355 #define WRITE_HL65_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val) \ 5356 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008370, (_val)) 5357 #define MODIFY_HL65_CL73_USERB0_CL73_UCTRL1r(_unit, _pc, _val, _mask) \ 5358 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008370, (_val), (_mask)) 5359 5360 /* Clause 73 user status */ 5361 #define READ_HL65_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \ 5362 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008371, (_val)) 5363 #define WRITE_HL65_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val) \ 5364 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008371, (_val)) 5365 #define MODIFY_HL65_CL73_USERB0_CL73_USTAT1r(_unit, _pc, _val, _mask) \ 5366 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008371, (_val), (_mask)) 5367 5368 /* Clause 73 BAM control 1 */ 5369 #define READ_HL65_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \ 5370 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008372, (_val)) 5371 #define WRITE_HL65_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val) \ 5372 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008372, (_val)) 5373 #define MODIFY_HL65_CL73_USERB0_CL73_BAMCTRL1r(_unit, _pc, _val, _mask) \ 5374 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008372, (_val), (_mask)) 5375 5376 /* Clause 73 BAM control 2 */ 5377 #define READ_HL65_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \ 5378 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008373, (_val)) 5379 #define WRITE_HL65_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val) \ 5380 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008373, (_val)) 5381 #define MODIFY_HL65_CL73_USERB0_CL73_BAMCTRL2r(_unit, _pc, _val, _mask) \ 5382 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008373, (_val), (_mask)) 5383 5384 /* Clause 73 BAM control 3 */ 5385 #define READ_HL65_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \ 5386 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008374, (_val)) 5387 #define WRITE_HL65_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val) \ 5388 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008374, (_val)) 5389 #define MODIFY_HL65_CL73_USERB0_CL73_BAMCTRL3r(_unit, _pc, _val, _mask) \ 5390 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008374, (_val), (_mask)) 5391 5392 /* Clause 73 BAM status 1 */ 5393 #define READ_HL65_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \ 5394 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008375, (_val)) 5395 #define WRITE_HL65_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val) \ 5396 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008375, (_val)) 5397 #define MODIFY_HL65_CL73_USERB0_CL73_BAMSTAT1r(_unit, _pc, _val, _mask) \ 5398 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008375, (_val), (_mask)) 5399 5400 /* Clause 73 BAM status 2 */ 5401 #define READ_HL65_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \ 5402 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008376, (_val)) 5403 #define WRITE_HL65_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val) \ 5404 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008376, (_val)) 5405 #define MODIFY_HL65_CL73_USERB0_CL73_BAMSTAT2r(_unit, _pc, _val, _mask) \ 5406 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008376, (_val), (_mask)) 5407 5408 /* Clause 73 BAM status 3 */ 5409 #define READ_HL65_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \ 5410 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008377, (_val)) 5411 #define WRITE_HL65_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val) \ 5412 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008377, (_val)) 5413 #define MODIFY_HL65_CL73_USERB0_CL73_BAMSTAT3r(_unit, _pc, _val, _mask) \ 5414 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008377, (_val), (_mask)) 5415 5416 5417 /**************************************************************************** 5418 * Hypercore_USER_Dsc4b0 5419 */ 5420 5421 /* State Machine Control 13 Register */ 5422 #define READ_HL65_DSC4B0_SM_CTRL13r(_unit, _pc, _val) \ 5423 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008380, (_val)) 5424 #define WRITE_HL65_DSC4B0_SM_CTRL13r(_unit, _pc, _val) \ 5425 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008380, (_val)) 5426 #define MODIFY_HL65_DSC4B0_SM_CTRL13r(_unit, _pc, _val, _mask) \ 5427 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008380, (_val), (_mask)) 5428 5429 /* State Machine Control 14 Register */ 5430 #define READ_HL65_DSC4B0_SM_CTRL14r(_unit, _pc, _val) \ 5431 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008381, (_val)) 5432 #define WRITE_HL65_DSC4B0_SM_CTRL14r(_unit, _pc, _val) \ 5433 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008381, (_val)) 5434 #define MODIFY_HL65_DSC4B0_SM_CTRL14r(_unit, _pc, _val, _mask) \ 5435 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008381, (_val), (_mask)) 5436 5437 /* State Machine Control 15 Register */ 5438 #define READ_HL65_DSC4B0_SM_CTRL15r(_unit, _pc, _val) \ 5439 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008382, (_val)) 5440 #define WRITE_HL65_DSC4B0_SM_CTRL15r(_unit, _pc, _val) \ 5441 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008382, (_val)) 5442 #define MODIFY_HL65_DSC4B0_SM_CTRL15r(_unit, _pc, _val, _mask) \ 5443 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008382, (_val), (_mask)) 5444 5445 /* State Machine Control 16 Register */ 5446 #define READ_HL65_DSC4B0_SM_CTRL16r(_unit, _pc, _val) \ 5447 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008383, (_val)) 5448 #define WRITE_HL65_DSC4B0_SM_CTRL16r(_unit, _pc, _val) \ 5449 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008383, (_val)) 5450 #define MODIFY_HL65_DSC4B0_SM_CTRL16r(_unit, _pc, _val, _mask) \ 5451 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008383, (_val), (_mask)) 5452 5453 /* State Machine Control 17 Register */ 5454 #define READ_HL65_DSC4B0_SM_CTRL17r(_unit, _pc, _val) \ 5455 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008384, (_val)) 5456 #define WRITE_HL65_DSC4B0_SM_CTRL17r(_unit, _pc, _val) \ 5457 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008384, (_val)) 5458 #define MODIFY_HL65_DSC4B0_SM_CTRL17r(_unit, _pc, _val, _mask) \ 5459 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008384, (_val), (_mask)) 5460 5461 /* State Machine Status 7 Register */ 5462 #define READ_HL65_DSC4B0_SM_STATUS7r(_unit, _pc, _val) \ 5463 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008385, (_val)) 5464 #define WRITE_HL65_DSC4B0_SM_STATUS7r(_unit, _pc, _val) \ 5465 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008385, (_val)) 5466 #define MODIFY_HL65_DSC4B0_SM_STATUS7r(_unit, _pc, _val, _mask) \ 5467 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008385, (_val), (_mask)) 5468 5469 /* State Machine Status 8 Register */ 5470 #define READ_HL65_DSC4B0_SM_STATUS8r(_unit, _pc, _val) \ 5471 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008386, (_val)) 5472 #define WRITE_HL65_DSC4B0_SM_STATUS8r(_unit, _pc, _val) \ 5473 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008386, (_val)) 5474 #define MODIFY_HL65_DSC4B0_SM_STATUS8r(_unit, _pc, _val, _mask) \ 5475 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008386, (_val), (_mask)) 5476 5477 /* State Machine Status 9 Register */ 5478 #define READ_HL65_DSC4B0_SM_STATUS9r(_unit, _pc, _val) \ 5479 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008387, (_val)) 5480 #define WRITE_HL65_DSC4B0_SM_STATUS9r(_unit, _pc, _val) \ 5481 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008387, (_val)) 5482 #define MODIFY_HL65_DSC4B0_SM_STATUS9r(_unit, _pc, _val, _mask) \ 5483 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008387, (_val), (_mask)) 5484 5485 5486 /**************************************************************************** 5487 * Hypercore_USER_Dsc4b1 5488 */ 5489 5490 /* State Machine Control 13 Register */ 5491 #define READ_HL65_DSC4B1_SM_CTRL13r(_unit, _pc, _val) \ 5492 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008390, (_val)) 5493 #define WRITE_HL65_DSC4B1_SM_CTRL13r(_unit, _pc, _val) \ 5494 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008390, (_val)) 5495 #define MODIFY_HL65_DSC4B1_SM_CTRL13r(_unit, _pc, _val, _mask) \ 5496 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008390, (_val), (_mask)) 5497 5498 /* State Machine Control 14 Register */ 5499 #define READ_HL65_DSC4B1_SM_CTRL14r(_unit, _pc, _val) \ 5500 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008391, (_val)) 5501 #define WRITE_HL65_DSC4B1_SM_CTRL14r(_unit, _pc, _val) \ 5502 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008391, (_val)) 5503 #define MODIFY_HL65_DSC4B1_SM_CTRL14r(_unit, _pc, _val, _mask) \ 5504 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008391, (_val), (_mask)) 5505 5506 /* State Machine Control 15 Register */ 5507 #define READ_HL65_DSC4B1_SM_CTRL15r(_unit, _pc, _val) \ 5508 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008392, (_val)) 5509 #define WRITE_HL65_DSC4B1_SM_CTRL15r(_unit, _pc, _val) \ 5510 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008392, (_val)) 5511 #define MODIFY_HL65_DSC4B1_SM_CTRL15r(_unit, _pc, _val, _mask) \ 5512 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008392, (_val), (_mask)) 5513 5514 /* State Machine Control 16 Register */ 5515 #define READ_HL65_DSC4B1_SM_CTRL16r(_unit, _pc, _val) \ 5516 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008393, (_val)) 5517 #define WRITE_HL65_DSC4B1_SM_CTRL16r(_unit, _pc, _val) \ 5518 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008393, (_val)) 5519 #define MODIFY_HL65_DSC4B1_SM_CTRL16r(_unit, _pc, _val, _mask) \ 5520 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008393, (_val), (_mask)) 5521 5522 /* State Machine Control 17 Register */ 5523 #define READ_HL65_DSC4B1_SM_CTRL17r(_unit, _pc, _val) \ 5524 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008394, (_val)) 5525 #define WRITE_HL65_DSC4B1_SM_CTRL17r(_unit, _pc, _val) \ 5526 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008394, (_val)) 5527 #define MODIFY_HL65_DSC4B1_SM_CTRL17r(_unit, _pc, _val, _mask) \ 5528 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008394, (_val), (_mask)) 5529 5530 /* State Machine Status 7 Register */ 5531 #define READ_HL65_DSC4B1_SM_STATUS7r(_unit, _pc, _val) \ 5532 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008395, (_val)) 5533 #define WRITE_HL65_DSC4B1_SM_STATUS7r(_unit, _pc, _val) \ 5534 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008395, (_val)) 5535 #define MODIFY_HL65_DSC4B1_SM_STATUS7r(_unit, _pc, _val, _mask) \ 5536 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008395, (_val), (_mask)) 5537 5538 /* State Machine Status 8 Register */ 5539 #define READ_HL65_DSC4B1_SM_STATUS8r(_unit, _pc, _val) \ 5540 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008396, (_val)) 5541 #define WRITE_HL65_DSC4B1_SM_STATUS8r(_unit, _pc, _val) \ 5542 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008396, (_val)) 5543 #define MODIFY_HL65_DSC4B1_SM_STATUS8r(_unit, _pc, _val, _mask) \ 5544 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008396, (_val), (_mask)) 5545 5546 /* State Machine Status 9 Register */ 5547 #define READ_HL65_DSC4B1_SM_STATUS9r(_unit, _pc, _val) \ 5548 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008397, (_val)) 5549 #define WRITE_HL65_DSC4B1_SM_STATUS9r(_unit, _pc, _val) \ 5550 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008397, (_val)) 5551 #define MODIFY_HL65_DSC4B1_SM_STATUS9r(_unit, _pc, _val, _mask) \ 5552 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008397, (_val), (_mask)) 5553 5554 5555 /**************************************************************************** 5556 * Hypercore_USER_Dsc4b2 5557 */ 5558 5559 /* State Machine Control 13 Register */ 5560 #define READ_HL65_DSC4B2_SM_CTRL13r(_unit, _pc, _val) \ 5561 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a0, (_val)) 5562 #define WRITE_HL65_DSC4B2_SM_CTRL13r(_unit, _pc, _val) \ 5563 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a0, (_val)) 5564 #define MODIFY_HL65_DSC4B2_SM_CTRL13r(_unit, _pc, _val, _mask) \ 5565 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a0, (_val), (_mask)) 5566 5567 /* State Machine Control 14 Register */ 5568 #define READ_HL65_DSC4B2_SM_CTRL14r(_unit, _pc, _val) \ 5569 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a1, (_val)) 5570 #define WRITE_HL65_DSC4B2_SM_CTRL14r(_unit, _pc, _val) \ 5571 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a1, (_val)) 5572 #define MODIFY_HL65_DSC4B2_SM_CTRL14r(_unit, _pc, _val, _mask) \ 5573 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a1, (_val), (_mask)) 5574 5575 /* State Machine Control 15 Register */ 5576 #define READ_HL65_DSC4B2_SM_CTRL15r(_unit, _pc, _val) \ 5577 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a2, (_val)) 5578 #define WRITE_HL65_DSC4B2_SM_CTRL15r(_unit, _pc, _val) \ 5579 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a2, (_val)) 5580 #define MODIFY_HL65_DSC4B2_SM_CTRL15r(_unit, _pc, _val, _mask) \ 5581 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a2, (_val), (_mask)) 5582 5583 /* State Machine Control 16 Register */ 5584 #define READ_HL65_DSC4B2_SM_CTRL16r(_unit, _pc, _val) \ 5585 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a3, (_val)) 5586 #define WRITE_HL65_DSC4B2_SM_CTRL16r(_unit, _pc, _val) \ 5587 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a3, (_val)) 5588 #define MODIFY_HL65_DSC4B2_SM_CTRL16r(_unit, _pc, _val, _mask) \ 5589 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a3, (_val), (_mask)) 5590 5591 /* State Machine Control 17 Register */ 5592 #define READ_HL65_DSC4B2_SM_CTRL17r(_unit, _pc, _val) \ 5593 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a4, (_val)) 5594 #define WRITE_HL65_DSC4B2_SM_CTRL17r(_unit, _pc, _val) \ 5595 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a4, (_val)) 5596 #define MODIFY_HL65_DSC4B2_SM_CTRL17r(_unit, _pc, _val, _mask) \ 5597 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a4, (_val), (_mask)) 5598 5599 /* State Machine Status 7 Register */ 5600 #define READ_HL65_DSC4B2_SM_STATUS7r(_unit, _pc, _val) \ 5601 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a5, (_val)) 5602 #define WRITE_HL65_DSC4B2_SM_STATUS7r(_unit, _pc, _val) \ 5603 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a5, (_val)) 5604 #define MODIFY_HL65_DSC4B2_SM_STATUS7r(_unit, _pc, _val, _mask) \ 5605 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a5, (_val), (_mask)) 5606 5607 /* State Machine Status 8 Register */ 5608 #define READ_HL65_DSC4B2_SM_STATUS8r(_unit, _pc, _val) \ 5609 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a6, (_val)) 5610 #define WRITE_HL65_DSC4B2_SM_STATUS8r(_unit, _pc, _val) \ 5611 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a6, (_val)) 5612 #define MODIFY_HL65_DSC4B2_SM_STATUS8r(_unit, _pc, _val, _mask) \ 5613 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a6, (_val), (_mask)) 5614 5615 /* State Machine Status 9 Register */ 5616 #define READ_HL65_DSC4B2_SM_STATUS9r(_unit, _pc, _val) \ 5617 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083a7, (_val)) 5618 #define WRITE_HL65_DSC4B2_SM_STATUS9r(_unit, _pc, _val) \ 5619 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083a7, (_val)) 5620 #define MODIFY_HL65_DSC4B2_SM_STATUS9r(_unit, _pc, _val, _mask) \ 5621 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083a7, (_val), (_mask)) 5622 5623 5624 /**************************************************************************** 5625 * Hypercore_USER_Dsc4b3 5626 */ 5627 5628 /* State Machine Control 13 Register */ 5629 #define READ_HL65_DSC4B3_SM_CTRL13r(_unit, _pc, _val) \ 5630 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b0, (_val)) 5631 #define WRITE_HL65_DSC4B3_SM_CTRL13r(_unit, _pc, _val) \ 5632 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b0, (_val)) 5633 #define MODIFY_HL65_DSC4B3_SM_CTRL13r(_unit, _pc, _val, _mask) \ 5634 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b0, (_val), (_mask)) 5635 5636 /* State Machine Control 14 Register */ 5637 #define READ_HL65_DSC4B3_SM_CTRL14r(_unit, _pc, _val) \ 5638 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b1, (_val)) 5639 #define WRITE_HL65_DSC4B3_SM_CTRL14r(_unit, _pc, _val) \ 5640 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b1, (_val)) 5641 #define MODIFY_HL65_DSC4B3_SM_CTRL14r(_unit, _pc, _val, _mask) \ 5642 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b1, (_val), (_mask)) 5643 5644 /* State Machine Control 15 Register */ 5645 #define READ_HL65_DSC4B3_SM_CTRL15r(_unit, _pc, _val) \ 5646 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b2, (_val)) 5647 #define WRITE_HL65_DSC4B3_SM_CTRL15r(_unit, _pc, _val) \ 5648 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b2, (_val)) 5649 #define MODIFY_HL65_DSC4B3_SM_CTRL15r(_unit, _pc, _val, _mask) \ 5650 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b2, (_val), (_mask)) 5651 5652 /* State Machine Control 16 Register */ 5653 #define READ_HL65_DSC4B3_SM_CTRL16r(_unit, _pc, _val) \ 5654 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b3, (_val)) 5655 #define WRITE_HL65_DSC4B3_SM_CTRL16r(_unit, _pc, _val) \ 5656 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b3, (_val)) 5657 #define MODIFY_HL65_DSC4B3_SM_CTRL16r(_unit, _pc, _val, _mask) \ 5658 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b3, (_val), (_mask)) 5659 5660 /* State Machine Control 17 Register */ 5661 #define READ_HL65_DSC4B3_SM_CTRL17r(_unit, _pc, _val) \ 5662 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b4, (_val)) 5663 #define WRITE_HL65_DSC4B3_SM_CTRL17r(_unit, _pc, _val) \ 5664 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b4, (_val)) 5665 #define MODIFY_HL65_DSC4B3_SM_CTRL17r(_unit, _pc, _val, _mask) \ 5666 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b4, (_val), (_mask)) 5667 5668 /* State Machine Status 7 Register */ 5669 #define READ_HL65_DSC4B3_SM_STATUS7r(_unit, _pc, _val) \ 5670 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b5, (_val)) 5671 #define WRITE_HL65_DSC4B3_SM_STATUS7r(_unit, _pc, _val) \ 5672 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b5, (_val)) 5673 #define MODIFY_HL65_DSC4B3_SM_STATUS7r(_unit, _pc, _val, _mask) \ 5674 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b5, (_val), (_mask)) 5675 5676 /* State Machine Status 8 Register */ 5677 #define READ_HL65_DSC4B3_SM_STATUS8r(_unit, _pc, _val) \ 5678 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b6, (_val)) 5679 #define WRITE_HL65_DSC4B3_SM_STATUS8r(_unit, _pc, _val) \ 5680 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b6, (_val)) 5681 #define MODIFY_HL65_DSC4B3_SM_STATUS8r(_unit, _pc, _val, _mask) \ 5682 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b6, (_val), (_mask)) 5683 5684 /* State Machine Status 9 Register */ 5685 #define READ_HL65_DSC4B3_SM_STATUS9r(_unit, _pc, _val) \ 5686 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083b7, (_val)) 5687 #define WRITE_HL65_DSC4B3_SM_STATUS9r(_unit, _pc, _val) \ 5688 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083b7, (_val)) 5689 #define MODIFY_HL65_DSC4B3_SM_STATUS9r(_unit, _pc, _val, _mask) \ 5690 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083b7, (_val), (_mask)) 5691 5692 5693 /**************************************************************************** 5694 * Hypercore_USER_Dsc4bB 5695 */ 5696 5697 /* State Machine Control 13 Register */ 5698 #define READ_HL65_DSC4BB_SM_CTRL13r(_unit, _pc, _val) \ 5699 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c0, (_val)) 5700 #define WRITE_HL65_DSC4BB_SM_CTRL13r(_unit, _pc, _val) \ 5701 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c0, (_val)) 5702 #define MODIFY_HL65_DSC4BB_SM_CTRL13r(_unit, _pc, _val, _mask) \ 5703 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c0, (_val), (_mask)) 5704 5705 /* State Machine Control 14 Register */ 5706 #define READ_HL65_DSC4BB_SM_CTRL14r(_unit, _pc, _val) \ 5707 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c1, (_val)) 5708 #define WRITE_HL65_DSC4BB_SM_CTRL14r(_unit, _pc, _val) \ 5709 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c1, (_val)) 5710 #define MODIFY_HL65_DSC4BB_SM_CTRL14r(_unit, _pc, _val, _mask) \ 5711 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c1, (_val), (_mask)) 5712 5713 /* State Machine Control 15 Register */ 5714 #define READ_HL65_DSC4BB_SM_CTRL15r(_unit, _pc, _val) \ 5715 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c2, (_val)) 5716 #define WRITE_HL65_DSC4BB_SM_CTRL15r(_unit, _pc, _val) \ 5717 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c2, (_val)) 5718 #define MODIFY_HL65_DSC4BB_SM_CTRL15r(_unit, _pc, _val, _mask) \ 5719 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c2, (_val), (_mask)) 5720 5721 /* State Machine Control 16 Register */ 5722 #define READ_HL65_DSC4BB_SM_CTRL16r(_unit, _pc, _val) \ 5723 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c3, (_val)) 5724 #define WRITE_HL65_DSC4BB_SM_CTRL16r(_unit, _pc, _val) \ 5725 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c3, (_val)) 5726 #define MODIFY_HL65_DSC4BB_SM_CTRL16r(_unit, _pc, _val, _mask) \ 5727 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c3, (_val), (_mask)) 5728 5729 /* State Machine Control 17 Register */ 5730 #define READ_HL65_DSC4BB_SM_CTRL17r(_unit, _pc, _val) \ 5731 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c4, (_val)) 5732 #define WRITE_HL65_DSC4BB_SM_CTRL17r(_unit, _pc, _val) \ 5733 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c4, (_val)) 5734 #define MODIFY_HL65_DSC4BB_SM_CTRL17r(_unit, _pc, _val, _mask) \ 5735 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c4, (_val), (_mask)) 5736 5737 /* State Machine Status 7 Register */ 5738 #define READ_HL65_DSC4BB_SM_STATUS7r(_unit, _pc, _val) \ 5739 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c5, (_val)) 5740 #define WRITE_HL65_DSC4BB_SM_STATUS7r(_unit, _pc, _val) \ 5741 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c5, (_val)) 5742 #define MODIFY_HL65_DSC4BB_SM_STATUS7r(_unit, _pc, _val, _mask) \ 5743 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c5, (_val), (_mask)) 5744 5745 /* State Machine Status 8 Register */ 5746 #define READ_HL65_DSC4BB_SM_STATUS8r(_unit, _pc, _val) \ 5747 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c6, (_val)) 5748 #define WRITE_HL65_DSC4BB_SM_STATUS8r(_unit, _pc, _val) \ 5749 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c6, (_val)) 5750 #define MODIFY_HL65_DSC4BB_SM_STATUS8r(_unit, _pc, _val, _mask) \ 5751 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c6, (_val), (_mask)) 5752 5753 /* State Machine Status 9 Register */ 5754 #define READ_HL65_DSC4BB_SM_STATUS9r(_unit, _pc, _val) \ 5755 HL65_REG_READ((_unit), (_pc), 0x00, 0x000083c7, (_val)) 5756 #define WRITE_HL65_DSC4BB_SM_STATUS9r(_unit, _pc, _val) \ 5757 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x000083c7, (_val)) 5758 #define MODIFY_HL65_DSC4BB_SM_STATUS9r(_unit, _pc, _val, _mask) \ 5759 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x000083c7, (_val), (_mask)) 5760 5761 5762 /**************************************************************************** 5763 * Hypercore_USER_FX100 5764 */ 5765 5766 /* 100FX control register 1 */ 5767 #define READ_HL65_FX100_CONTROL1r(_unit, _pc, _val) \ 5768 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008400, (_val)) 5769 #define WRITE_HL65_FX100_CONTROL1r(_unit, _pc, _val) \ 5770 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008400, (_val)) 5771 #define MODIFY_HL65_FX100_CONTROL1r(_unit, _pc, _val, _mask) \ 5772 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008400, (_val), (_mask)) 5773 5774 /* 100FX control register 2 */ 5775 #define READ_HL65_FX100_CONTROL2r(_unit, _pc, _val) \ 5776 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008401, (_val)) 5777 #define WRITE_HL65_FX100_CONTROL2r(_unit, _pc, _val) \ 5778 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008401, (_val)) 5779 #define MODIFY_HL65_FX100_CONTROL2r(_unit, _pc, _val, _mask) \ 5780 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008401, (_val), (_mask)) 5781 5782 /* 100FX control register 3 */ 5783 #define READ_HL65_FX100_CONTROL3r(_unit, _pc, _val) \ 5784 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008402, (_val)) 5785 #define WRITE_HL65_FX100_CONTROL3r(_unit, _pc, _val) \ 5786 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008402, (_val)) 5787 #define MODIFY_HL65_FX100_CONTROL3r(_unit, _pc, _val, _mask) \ 5788 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008402, (_val), (_mask)) 5789 5790 /* 100FX status register 1 */ 5791 #define READ_HL65_FX100_STATUS1r(_unit, _pc, _val) \ 5792 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008403, (_val)) 5793 #define WRITE_HL65_FX100_STATUS1r(_unit, _pc, _val) \ 5794 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008403, (_val)) 5795 #define MODIFY_HL65_FX100_STATUS1r(_unit, _pc, _val, _mask) \ 5796 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008403, (_val), (_mask)) 5797 5798 /* 100FX status register 3 */ 5799 #define READ_HL65_FX100_STATUS3r(_unit, _pc, _val) \ 5800 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008405, (_val)) 5801 #define WRITE_HL65_FX100_STATUS3r(_unit, _pc, _val) \ 5802 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008405, (_val)) 5803 #define MODIFY_HL65_FX100_STATUS3r(_unit, _pc, _val, _mask) \ 5804 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008405, (_val), (_mask)) 5805 5806 /* 100FX status register 4 */ 5807 #define READ_HL65_FX100_STATUS4r(_unit, _pc, _val) \ 5808 HL65_REG_READ((_unit), (_pc), 0x00, 0x00008406, (_val)) 5809 #define WRITE_HL65_FX100_STATUS4r(_unit, _pc, _val) \ 5810 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x00008406, (_val)) 5811 #define MODIFY_HL65_FX100_STATUS4r(_unit, _pc, _val, _mask) \ 5812 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x00008406, (_val), (_mask)) 5813 5814 5815 /**************************************************************************** 5816 * Hypercore_USER_aerBlk 5817 */ 5818 5819 /* Address Expansion Register */ 5820 #define READ_HL65_AERBLK_AERr(_unit, _pc, _val) \ 5821 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffde, (_val)) 5822 #define WRITE_HL65_AERBLK_AERr(_unit, _pc, _val) \ 5823 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffde, (_val)) 5824 #define MODIFY_HL65_AERBLK_AERr(_unit, _pc, _val, _mask) \ 5825 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffde, (_val), (_mask)) 5826 5827 5828 /**************************************************************************** 5829 * Hypercore_USER_Combo_IEEE0 5830 */ 5831 5832 /* IEEE MII control register */ 5833 #define READ_HL65_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 5834 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe0, (_val)) 5835 #define WRITE_HL65_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val) \ 5836 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe0, (_val)) 5837 #define MODIFY_HL65_COMBO_IEEE0_MIICNTLr(_unit, _pc, _val, _mask) \ 5838 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe0, (_val), (_mask)) 5839 5840 /* IEEE MII status register */ 5841 #define READ_HL65_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \ 5842 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe1, (_val)) 5843 #define WRITE_HL65_COMBO_IEEE0_MIISTATr(_unit, _pc, _val) \ 5844 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe1, (_val)) 5845 #define MODIFY_HL65_COMBO_IEEE0_MIISTATr(_unit, _pc, _val, _mask) \ 5846 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe1, (_val), (_mask)) 5847 5848 /* IEEE phy ID LSByte register */ 5849 #define READ_HL65_COMBO_IEEE0_ID1r(_unit, _pc, _val) \ 5850 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe2, (_val)) 5851 #define WRITE_HL65_COMBO_IEEE0_ID1r(_unit, _pc, _val) \ 5852 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe2, (_val)) 5853 #define MODIFY_HL65_COMBO_IEEE0_ID1r(_unit, _pc, _val, _mask) \ 5854 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe2, (_val), (_mask)) 5855 5856 /* IEEE phy ID MSByte register */ 5857 #define READ_HL65_COMBO_IEEE0_ID2r(_unit, _pc, _val) \ 5858 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe3, (_val)) 5859 #define WRITE_HL65_COMBO_IEEE0_ID2r(_unit, _pc, _val) \ 5860 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe3, (_val)) 5861 #define MODIFY_HL65_COMBO_IEEE0_ID2r(_unit, _pc, _val, _mask) \ 5862 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe3, (_val), (_mask)) 5863 5864 /* IEEE auto-negotiation advertised abilities register */ 5865 #define READ_HL65_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \ 5866 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe4, (_val)) 5867 #define WRITE_HL65_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val) \ 5868 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe4, (_val)) 5869 #define MODIFY_HL65_COMBO_IEEE0_AUTONEGADVr(_unit, _pc, _val, _mask) \ 5870 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe4, (_val), (_mask)) 5871 5872 /* IEEE auto-negotiation link partner abilities register */ 5873 #define READ_HL65_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \ 5874 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe5, (_val)) 5875 #define WRITE_HL65_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val) \ 5876 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe5, (_val)) 5877 #define MODIFY_HL65_COMBO_IEEE0_AUTONEGLPABILr(_unit, _pc, _val, _mask) \ 5878 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe5, (_val), (_mask)) 5879 5880 /* IEEE auto-negotiation expansion register */ 5881 #define READ_HL65_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \ 5882 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe6, (_val)) 5883 #define WRITE_HL65_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val) \ 5884 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe6, (_val)) 5885 #define MODIFY_HL65_COMBO_IEEE0_AUTONEGEXPr(_unit, _pc, _val, _mask) \ 5886 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe6, (_val), (_mask)) 5887 5888 /* IEEE auto-negotiation next page register */ 5889 #define READ_HL65_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \ 5890 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe7, (_val)) 5891 #define WRITE_HL65_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val) \ 5892 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe7, (_val)) 5893 #define MODIFY_HL65_COMBO_IEEE0_AUTONEGNPr(_unit, _pc, _val, _mask) \ 5894 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe7, (_val), (_mask)) 5895 5896 /* IEEE auto-negotiation link partner next page register */ 5897 #define READ_HL65_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \ 5898 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffe8, (_val)) 5899 #define WRITE_HL65_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val) \ 5900 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffe8, (_val)) 5901 #define MODIFY_HL65_COMBO_IEEE0_AUTONEGLPABIL2r(_unit, _pc, _val, _mask) \ 5902 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffe8, (_val), (_mask)) 5903 5904 /* IEEE MII extended status register */ 5905 #define READ_HL65_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \ 5906 HL65_REG_READ((_unit), (_pc), 0x00, 0x0000ffef, (_val)) 5907 #define WRITE_HL65_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val) \ 5908 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0000ffef, (_val)) 5909 #define MODIFY_HL65_COMBO_IEEE0_MIIEXTSTATr(_unit, _pc, _val, _mask) \ 5910 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0000ffef, (_val), (_mask)) 5911 5912 5913 /**************************************************************************** 5914 * Hypercore_IEEE_PMD_PMD_ieee0Blk 5915 */ 5916 5917 /* PMD Control 1 */ 5918 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val) \ 5919 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000000, (_val)) 5920 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val) \ 5921 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000000, (_val)) 5922 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL1r(_unit, _pc, _val, _mask) \ 5923 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000000, (_val), (_mask)) 5924 5925 /* PMD Status 1 */ 5926 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val) \ 5927 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000001, (_val)) 5928 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val) \ 5929 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000001, (_val)) 5930 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS1r(_unit, _pc, _val, _mask) \ 5931 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000001, (_val), (_mask)) 5932 5933 /* PMD Device ID [15:0] */ 5934 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val) \ 5935 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000002, (_val)) 5936 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val) \ 5937 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000002, (_val)) 5938 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEEID1r(_unit, _pc, _val, _mask) \ 5939 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000002, (_val), (_mask)) 5940 5941 /* PMD Device ID [31:16] */ 5942 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val) \ 5943 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000003, (_val)) 5944 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val) \ 5945 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000003, (_val)) 5946 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEEID2r(_unit, _pc, _val, _mask) \ 5947 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000003, (_val), (_mask)) 5948 5949 /* PMD Speed Ability */ 5950 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val) \ 5951 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000004, (_val)) 5952 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val) \ 5953 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000004, (_val)) 5954 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEESPEEDABILITYr(_unit, _pc, _val, _mask) \ 5955 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000004, (_val), (_mask)) 5956 5957 /* PMD Devices in Package 1 */ 5958 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val) \ 5959 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000005, (_val)) 5960 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val) \ 5961 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000005, (_val)) 5962 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG2r(_unit, _pc, _val, _mask) \ 5963 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000005, (_val), (_mask)) 5964 5965 /* PMD Devices in Package 2 */ 5966 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val) \ 5967 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000006, (_val)) 5968 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val) \ 5969 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000006, (_val)) 5970 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEEDEVINPKG1r(_unit, _pc, _val, _mask) \ 5971 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000006, (_val), (_mask)) 5972 5973 /* PMD Control 2 */ 5974 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val) \ 5975 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000007, (_val)) 5976 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val) \ 5977 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000007, (_val)) 5978 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEECONTROL2r(_unit, _pc, _val, _mask) \ 5979 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000007, (_val), (_mask)) 5980 5981 /* PMD Status 2 */ 5982 #define READ_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val) \ 5983 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000008, (_val)) 5984 #define WRITE_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val) \ 5985 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000008, (_val)) 5986 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_IEEESTATUS2r(_unit, _pc, _val, _mask) \ 5987 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000008, (_val), (_mask)) 5988 5989 /* PMD Transmit Disable */ 5990 #define READ_HL65_PMD_IEEE0BLK_PMD_TXDISABLE_TYPEr(_unit, _pc, _val) \ 5991 HL65_REG_READ((_unit), (_pc), 0x00, 0x08000009, (_val)) 5992 #define WRITE_HL65_PMD_IEEE0BLK_PMD_TXDISABLE_TYPEr(_unit, _pc, _val) \ 5993 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x08000009, (_val)) 5994 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_TXDISABLE_TYPEr(_unit, _pc, _val, _mask) \ 5995 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x08000009, (_val), (_mask)) 5996 5997 /* PMD Receive Signal Detect */ 5998 #define READ_HL65_PMD_IEEE0BLK_PMD_RXSIGNALDETECTr(_unit, _pc, _val) \ 5999 HL65_REG_READ((_unit), (_pc), 0x00, 0x0800000a, (_val)) 6000 #define WRITE_HL65_PMD_IEEE0BLK_PMD_RXSIGNALDETECTr(_unit, _pc, _val) \ 6001 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0800000a, (_val)) 6002 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_RXSIGNALDETECTr(_unit, _pc, _val, _mask) \ 6003 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0800000a, (_val), (_mask)) 6004 6005 /* PMD Extended Ability */ 6006 #define READ_HL65_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val) \ 6007 HL65_REG_READ((_unit), (_pc), 0x00, 0x0800000b, (_val)) 6008 #define WRITE_HL65_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val) \ 6009 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x0800000b, (_val)) 6010 #define MODIFY_HL65_PMD_IEEE0BLK_PMD_EXTENDEDABILITYr(_unit, _pc, _val, _mask) \ 6011 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x0800000b, (_val), (_mask)) 6012 6013 6014 /**************************************************************************** 6015 * Hypercore_IEEE_PMD_PMD_ieee10Blk 6016 */ 6017 6018 /* PMD 1000BASE-KX control */ 6019 #define READ_HL65_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val) \ 6020 HL65_REG_READ((_unit), (_pc), 0x00, 0x080000a0, (_val)) 6021 #define WRITE_HL65_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val) \ 6022 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x080000a0, (_val)) 6023 #define MODIFY_HL65_PMD_IEEE10BLK_PMD_KX_CONTROLr(_unit, _pc, _val, _mask) \ 6024 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x080000a0, (_val), (_mask)) 6025 6026 /* PMD 1000BASE-KX status */ 6027 #define READ_HL65_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val) \ 6028 HL65_REG_READ((_unit), (_pc), 0x00, 0x080000a1, (_val)) 6029 #define WRITE_HL65_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val) \ 6030 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x080000a1, (_val)) 6031 #define MODIFY_HL65_PMD_IEEE10BLK_PMD_KX_STATUSr(_unit, _pc, _val, _mask) \ 6032 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x080000a1, (_val), (_mask)) 6033 6034 6035 /**************************************************************************** 6036 * Hypercore_IEEE_DTE_DTE_ieee0Blk 6037 */ 6038 6039 /* DTE-XS Control 1 */ 6040 #define READ_HL65_DTE_IEEE0BLK_DTE_IEEECONTROL1r(_unit, _pc, _val) \ 6041 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000000, (_val)) 6042 #define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEECONTROL1r(_unit, _pc, _val) \ 6043 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000000, (_val)) 6044 #define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEECONTROL1r(_unit, _pc, _val, _mask) \ 6045 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000000, (_val), (_mask)) 6046 6047 /* DTE-XS Status 1 */ 6048 #define READ_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS1r(_unit, _pc, _val) \ 6049 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000001, (_val)) 6050 #define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS1r(_unit, _pc, _val) \ 6051 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000001, (_val)) 6052 #define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS1r(_unit, _pc, _val, _mask) \ 6053 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000001, (_val), (_mask)) 6054 6055 /* DTE-XS Device ID [15:0] */ 6056 #define READ_HL65_DTE_IEEE0BLK_DTE_IEEEID1r(_unit, _pc, _val) \ 6057 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000002, (_val)) 6058 #define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEEID1r(_unit, _pc, _val) \ 6059 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000002, (_val)) 6060 #define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEEID1r(_unit, _pc, _val, _mask) \ 6061 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000002, (_val), (_mask)) 6062 6063 /* DTE-XS Device ID [31:16] */ 6064 #define READ_HL65_DTE_IEEE0BLK_DTE_IEEEID2r(_unit, _pc, _val) \ 6065 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000003, (_val)) 6066 #define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEEID2r(_unit, _pc, _val) \ 6067 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000003, (_val)) 6068 #define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEEID2r(_unit, _pc, _val, _mask) \ 6069 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000003, (_val), (_mask)) 6070 6071 /* DTE-XS Speed Ability */ 6072 #define READ_HL65_DTE_IEEE0BLK_DTE_IEEESPEEDABILITYr(_unit, _pc, _val) \ 6073 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000004, (_val)) 6074 #define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEESPEEDABILITYr(_unit, _pc, _val) \ 6075 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000004, (_val)) 6076 #define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEESPEEDABILITYr(_unit, _pc, _val, _mask) \ 6077 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000004, (_val), (_mask)) 6078 6079 /* DTE-XS Devices in Package 1 */ 6080 #define READ_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG2r(_unit, _pc, _val) \ 6081 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000005, (_val)) 6082 #define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG2r(_unit, _pc, _val) \ 6083 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000005, (_val)) 6084 #define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG2r(_unit, _pc, _val, _mask) \ 6085 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000005, (_val), (_mask)) 6086 6087 /* DTE-XS Devices in Package 2 */ 6088 #define READ_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG1r(_unit, _pc, _val) \ 6089 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000006, (_val)) 6090 #define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG1r(_unit, _pc, _val) \ 6091 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000006, (_val)) 6092 #define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEEDEVINPKG1r(_unit, _pc, _val, _mask) \ 6093 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000006, (_val), (_mask)) 6094 6095 /* DTE-XS Status 2 */ 6096 #define READ_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS2r(_unit, _pc, _val) \ 6097 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000008, (_val)) 6098 #define WRITE_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS2r(_unit, _pc, _val) \ 6099 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000008, (_val)) 6100 #define MODIFY_HL65_DTE_IEEE0BLK_DTE_IEEESTATUS2r(_unit, _pc, _val, _mask) \ 6101 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000008, (_val), (_mask)) 6102 6103 6104 /**************************************************************************** 6105 * Hypercore_IEEE_DTE_DTE_ieee1Blk 6106 */ 6107 6108 /* XGXS lane Status */ 6109 #define READ_HL65_DTE_IEEE1BLK_DTE_LANESTATUSr(_unit, _pc, _val) \ 6110 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000018, (_val)) 6111 #define WRITE_HL65_DTE_IEEE1BLK_DTE_LANESTATUSr(_unit, _pc, _val) \ 6112 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000018, (_val)) 6113 #define MODIFY_HL65_DTE_IEEE1BLK_DTE_LANESTATUSr(_unit, _pc, _val, _mask) \ 6114 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000018, (_val), (_mask)) 6115 6116 /* XGXS Test Control */ 6117 #define READ_HL65_DTE_IEEE1BLK_DTE_IEEETESTCONTROLr(_unit, _pc, _val) \ 6118 HL65_REG_READ((_unit), (_pc), 0x00, 0x28000019, (_val)) 6119 #define WRITE_HL65_DTE_IEEE1BLK_DTE_IEEETESTCONTROLr(_unit, _pc, _val) \ 6120 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x28000019, (_val)) 6121 #define MODIFY_HL65_DTE_IEEE1BLK_DTE_IEEETESTCONTROLr(_unit, _pc, _val, _mask) \ 6122 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x28000019, (_val), (_mask)) 6123 6124 6125 /**************************************************************************** 6126 * Hypercore_IEEE_CL73_AN_ieee0Blk 6127 */ 6128 6129 /* AN Control 1 */ 6130 #define READ_HL65_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val) \ 6131 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000000, (_val)) 6132 #define WRITE_HL65_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val) \ 6133 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000000, (_val)) 6134 #define MODIFY_HL65_AN_IEEE0BLK_AN_IEEECONTROL1r(_unit, _pc, _val, _mask) \ 6135 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000000, (_val), (_mask)) 6136 6137 /* AN Status 1 */ 6138 #define READ_HL65_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val) \ 6139 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000001, (_val)) 6140 #define WRITE_HL65_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val) \ 6141 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000001, (_val)) 6142 #define MODIFY_HL65_AN_IEEE0BLK_AN_IEEESTATUS1r(_unit, _pc, _val, _mask) \ 6143 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000001, (_val), (_mask)) 6144 6145 /* AN Device ID [15:0] */ 6146 #define READ_HL65_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val) \ 6147 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000002, (_val)) 6148 #define WRITE_HL65_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val) \ 6149 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000002, (_val)) 6150 #define MODIFY_HL65_AN_IEEE0BLK_AN_IEEEID1r(_unit, _pc, _val, _mask) \ 6151 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000002, (_val), (_mask)) 6152 6153 /* AN Device ID [31:16] */ 6154 #define READ_HL65_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val) \ 6155 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000003, (_val)) 6156 #define WRITE_HL65_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val) \ 6157 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000003, (_val)) 6158 #define MODIFY_HL65_AN_IEEE0BLK_AN_IEEEID2r(_unit, _pc, _val, _mask) \ 6159 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000003, (_val), (_mask)) 6160 6161 /* AN Devices in Package 1 */ 6162 #define READ_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val) \ 6163 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000005, (_val)) 6164 #define WRITE_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val) \ 6165 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000005, (_val)) 6166 #define MODIFY_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG2r(_unit, _pc, _val, _mask) \ 6167 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000005, (_val), (_mask)) 6168 6169 /* AN Devices in Package 2 */ 6170 #define READ_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val) \ 6171 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000006, (_val)) 6172 #define WRITE_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val) \ 6173 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000006, (_val)) 6174 #define MODIFY_HL65_AN_IEEE0BLK_AN_IEEEDEVINPKG1r(_unit, _pc, _val, _mask) \ 6175 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000006, (_val), (_mask)) 6176 6177 6178 /**************************************************************************** 6179 * Hypercore_IEEE_CL73_AN_ieee1Blk 6180 */ 6181 6182 /* AN advertisement 0 */ 6183 #define READ_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val) \ 6184 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000010, (_val)) 6185 #define WRITE_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val) \ 6186 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000010, (_val)) 6187 #define MODIFY_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT0r(_unit, _pc, _val, _mask) \ 6188 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000010, (_val), (_mask)) 6189 6190 /* AN advertisement 1 */ 6191 #define READ_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val) \ 6192 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000011, (_val)) 6193 #define WRITE_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val) \ 6194 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000011, (_val)) 6195 #define MODIFY_HL65_AN_IEEE1BLK_AN_ADVERTISEMENT1r(_unit, _pc, _val, _mask) \ 6196 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000011, (_val), (_mask)) 6197 6198 /* AN LP base page ability 0 */ 6199 #define READ_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val) \ 6200 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000013, (_val)) 6201 #define WRITE_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val) \ 6202 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000013, (_val)) 6203 #define MODIFY_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0r(_unit, _pc, _val, _mask) \ 6204 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000013, (_val), (_mask)) 6205 6206 /* AN LP base page ability 1 */ 6207 #define READ_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val) \ 6208 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000014, (_val)) 6209 #define WRITE_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val) \ 6210 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000014, (_val)) 6211 #define MODIFY_HL65_AN_IEEE1BLK_AN_LP_BASEPAGEABILITY1r(_unit, _pc, _val, _mask) \ 6212 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000014, (_val), (_mask)) 6213 6214 /* AN XNP transmit 0 */ 6215 #define READ_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val) \ 6216 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000016, (_val)) 6217 #define WRITE_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val) \ 6218 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000016, (_val)) 6219 #define MODIFY_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT0r(_unit, _pc, _val, _mask) \ 6220 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000016, (_val), (_mask)) 6221 6222 /* AN XNP transmit 1 */ 6223 #define READ_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val) \ 6224 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000017, (_val)) 6225 #define WRITE_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val) \ 6226 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000017, (_val)) 6227 #define MODIFY_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT1r(_unit, _pc, _val, _mask) \ 6228 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000017, (_val), (_mask)) 6229 6230 /* AN XNP transmit 2 */ 6231 #define READ_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val) \ 6232 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000018, (_val)) 6233 #define WRITE_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val) \ 6234 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000018, (_val)) 6235 #define MODIFY_HL65_AN_IEEE1BLK_AN_XNP_TRANSMIT2r(_unit, _pc, _val, _mask) \ 6236 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000018, (_val), (_mask)) 6237 6238 /* AN LP XNP ability 0 */ 6239 #define READ_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val) \ 6240 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000019, (_val)) 6241 #define WRITE_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val) \ 6242 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000019, (_val)) 6243 #define MODIFY_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY0r(_unit, _pc, _val, _mask) \ 6244 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000019, (_val), (_mask)) 6245 6246 /* AN LP XNP ability 1 */ 6247 #define READ_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val) \ 6248 HL65_REG_READ((_unit), (_pc), 0x00, 0x3800001a, (_val)) 6249 #define WRITE_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val) \ 6250 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x3800001a, (_val)) 6251 #define MODIFY_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY1r(_unit, _pc, _val, _mask) \ 6252 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x3800001a, (_val), (_mask)) 6253 6254 /* AN LP XNP ability 2 */ 6255 #define READ_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val) \ 6256 HL65_REG_READ((_unit), (_pc), 0x00, 0x3800001b, (_val)) 6257 #define WRITE_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val) \ 6258 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x3800001b, (_val)) 6259 #define MODIFY_HL65_AN_IEEE1BLK_AN_LP_XNP_ABILITY2r(_unit, _pc, _val, _mask) \ 6260 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x3800001b, (_val), (_mask)) 6261 6262 6263 /**************************************************************************** 6264 * Hypercore_IEEE_CL73_AN_ieee3Blk 6265 */ 6266 6267 /* Autonegotiation Backplane Ethernet status */ 6268 #define READ_HL65_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val) \ 6269 HL65_REG_READ((_unit), (_pc), 0x00, 0x38000030, (_val)) 6270 #define WRITE_HL65_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val) \ 6271 HL65_REG_WRITE((_unit), (_pc), 0x00, 0x38000030, (_val)) 6272 #define MODIFY_HL65_AN_IEEE3BLK_AN_BPSTATUSr(_unit, _pc, _val, _mask) \ 6273 HL65_REG_MODIFY((_unit), (_pc), 0x00, 0x38000030, (_val), (_mask)) 6274 6275 6276 /**************************************************************************** 6277 * Hypercore_IEEE_CL22_ieee0Blk 6278 */ 6279 /**************************************************************************** 6280 * ieee0Blk :: MIICntl 6281 */ 6282 /* ieee0Blk :: MIICntl :: rst_hw [15:15] */ 6283 #define IEEE0BLK_MIICNTL_RST_HW_MASK 0x8000 6284 #define IEEE0BLK_MIICNTL_RST_HW_ALIGN 0 6285 #define IEEE0BLK_MIICNTL_RST_HW_BITS 1 6286 #define IEEE0BLK_MIICNTL_RST_HW_SHIFT 15 6287 6288 /* ieee0Blk :: MIICntl :: gloopback [14:14] */ 6289 #define IEEE0BLK_MIICNTL_GLOOPBACK_MASK 0x4000 6290 #define IEEE0BLK_MIICNTL_GLOOPBACK_ALIGN 0 6291 #define IEEE0BLK_MIICNTL_GLOOPBACK_BITS 1 6292 #define IEEE0BLK_MIICNTL_GLOOPBACK_SHIFT 14 6293 6294 /* ieee0Blk :: MIICntl :: manual_speed0 [13:13] */ 6295 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_MASK 0x2000 6296 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_ALIGN 0 6297 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_BITS 1 6298 #define IEEE0BLK_MIICNTL_MANUAL_SPEED0_SHIFT 13 6299 6300 /* ieee0Blk :: MIICntl :: autoneg_enable [12:12] */ 6301 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_MASK 0x1000 6302 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_ALIGN 0 6303 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_BITS 1 6304 #define IEEE0BLK_MIICNTL_AUTONEG_ENABLE_SHIFT 12 6305 6306 /* ieee0Blk :: MIICntl :: pwrdwn_sw [11:11] */ 6307 #define IEEE0BLK_MIICNTL_PWRDWN_SW_MASK 0x0800 6308 #define IEEE0BLK_MIICNTL_PWRDWN_SW_ALIGN 0 6309 #define IEEE0BLK_MIICNTL_PWRDWN_SW_BITS 1 6310 #define IEEE0BLK_MIICNTL_PWRDWN_SW_SHIFT 11 6311 6312 /* ieee0Blk :: MIICntl :: reserved0 [10:10] */ 6313 #define IEEE0BLK_MIICNTL_RESERVED0_MASK 0x0400 6314 #define IEEE0BLK_MIICNTL_RESERVED0_ALIGN 0 6315 #define IEEE0BLK_MIICNTL_RESERVED0_BITS 1 6316 #define IEEE0BLK_MIICNTL_RESERVED0_SHIFT 10 6317 6318 /* ieee0Blk :: MIICntl :: restart_autoneg [09:09] */ 6319 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_MASK 0x0200 6320 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_ALIGN 0 6321 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_BITS 1 6322 #define IEEE0BLK_MIICNTL_RESTART_AUTONEG_SHIFT 9 6323 6324 /* ieee0Blk :: MIICntl :: full_duplex [08:08] */ 6325 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_MASK 0x0100 6326 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_ALIGN 0 6327 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_BITS 1 6328 #define IEEE0BLK_MIICNTL_FULL_DUPLEX_SHIFT 8 6329 6330 /* ieee0Blk :: MIICntl :: collision_test_en [07:07] */ 6331 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_MASK 0x0080 6332 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_ALIGN 0 6333 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_BITS 1 6334 #define IEEE0BLK_MIICNTL_COLLISION_TEST_EN_SHIFT 7 6335 6336 /* ieee0Blk :: MIICntl :: manual_speed1 [06:06] */ 6337 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_MASK 0x0040 6338 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_ALIGN 0 6339 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_BITS 1 6340 #define IEEE0BLK_MIICNTL_MANUAL_SPEED1_SHIFT 6 6341 6342 /* ieee0Blk :: MIICntl :: reserved1 [05:00] */ 6343 #define IEEE0BLK_MIICNTL_RESERVED1_MASK 0x003f 6344 #define IEEE0BLK_MIICNTL_RESERVED1_ALIGN 0 6345 #define IEEE0BLK_MIICNTL_RESERVED1_BITS 6 6346 #define IEEE0BLK_MIICNTL_RESERVED1_SHIFT 0 6347 6348 6349 /**************************************************************************** 6350 * ieee0Blk :: MIIStat 6351 */ 6352 /* ieee0Blk :: MIIStat :: s100BASE_T4_capable [15:15] */ 6353 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_MASK 0x8000 6354 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_ALIGN 0 6355 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_BITS 1 6356 #define IEEE0BLK_MIISTAT_S100BASE_T4_CAPABLE_SHIFT 15 6357 6358 /* ieee0Blk :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */ 6359 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000 6360 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 6361 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 6362 #define IEEE0BLK_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14 6363 6364 /* ieee0Blk :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */ 6365 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000 6366 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 6367 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 6368 #define IEEE0BLK_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13 6369 6370 /* ieee0Blk :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */ 6371 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x1000 6372 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 6373 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 6374 #define IEEE0BLK_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12 6375 6376 /* ieee0Blk :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */ 6377 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x0800 6378 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 6379 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 6380 #define IEEE0BLK_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11 6381 6382 /* ieee0Blk :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */ 6383 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400 6384 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0 6385 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1 6386 #define IEEE0BLK_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10 6387 6388 /* ieee0Blk :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */ 6389 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200 6390 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0 6391 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1 6392 #define IEEE0BLK_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9 6393 6394 /* ieee0Blk :: MIIStat :: extended_status [08:08] */ 6395 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_MASK 0x0100 6396 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_ALIGN 0 6397 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_BITS 1 6398 #define IEEE0BLK_MIISTAT_EXTENDED_STATUS_SHIFT 8 6399 6400 /* ieee0Blk :: MIIStat :: reserved0 [07:07] */ 6401 #define IEEE0BLK_MIISTAT_RESERVED0_MASK 0x0080 6402 #define IEEE0BLK_MIISTAT_RESERVED0_ALIGN 0 6403 #define IEEE0BLK_MIISTAT_RESERVED0_BITS 1 6404 #define IEEE0BLK_MIISTAT_RESERVED0_SHIFT 7 6405 6406 /* ieee0Blk :: MIIStat :: mf_preamble_supression [06:06] */ 6407 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK 0x0040 6408 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN 0 6409 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS 1 6410 #define IEEE0BLK_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT 6 6411 6412 /* ieee0Blk :: MIIStat :: autoneg_complete [05:05] */ 6413 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_MASK 0x0020 6414 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_ALIGN 0 6415 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_BITS 1 6416 #define IEEE0BLK_MIISTAT_AUTONEG_COMPLETE_SHIFT 5 6417 6418 /* ieee0Blk :: MIIStat :: remote_fault [04:04] */ 6419 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_MASK 0x0010 6420 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_ALIGN 0 6421 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_BITS 1 6422 #define IEEE0BLK_MIISTAT_REMOTE_FAULT_SHIFT 4 6423 6424 /* ieee0Blk :: MIIStat :: autoneg_ability [03:03] */ 6425 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_MASK 0x0008 6426 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_ALIGN 0 6427 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_BITS 1 6428 #define IEEE0BLK_MIISTAT_AUTONEG_ABILITY_SHIFT 3 6429 6430 /* ieee0Blk :: MIIStat :: link_status [02:02] */ 6431 #define IEEE0BLK_MIISTAT_LINK_STATUS_MASK 0x0004 6432 #define IEEE0BLK_MIISTAT_LINK_STATUS_ALIGN 0 6433 #define IEEE0BLK_MIISTAT_LINK_STATUS_BITS 1 6434 #define IEEE0BLK_MIISTAT_LINK_STATUS_SHIFT 2 6435 6436 /* ieee0Blk :: MIIStat :: jabber_detect [01:01] */ 6437 #define IEEE0BLK_MIISTAT_JABBER_DETECT_MASK 0x0002 6438 #define IEEE0BLK_MIISTAT_JABBER_DETECT_ALIGN 0 6439 #define IEEE0BLK_MIISTAT_JABBER_DETECT_BITS 1 6440 #define IEEE0BLK_MIISTAT_JABBER_DETECT_SHIFT 1 6441 6442 /* ieee0Blk :: MIIStat :: extended_capability [00:00] */ 6443 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_MASK 0x0001 6444 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_ALIGN 0 6445 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_BITS 1 6446 #define IEEE0BLK_MIISTAT_EXTENDED_CAPABILITY_SHIFT 0 6447 6448 6449 /**************************************************************************** 6450 * ieee0Blk :: Id1 6451 */ 6452 /* ieee0Blk :: Id1 :: regid [15:00] */ 6453 #define IEEE0BLK_ID1_REGID_MASK 0xffff 6454 #define IEEE0BLK_ID1_REGID_ALIGN 0 6455 #define IEEE0BLK_ID1_REGID_BITS 16 6456 #define IEEE0BLK_ID1_REGID_SHIFT 0 6457 6458 6459 /**************************************************************************** 6460 * ieee0Blk :: Id2 6461 */ 6462 /* ieee0Blk :: Id2 :: regid [15:00] */ 6463 #define IEEE0BLK_ID2_REGID_MASK 0xffff 6464 #define IEEE0BLK_ID2_REGID_ALIGN 0 6465 #define IEEE0BLK_ID2_REGID_BITS 16 6466 #define IEEE0BLK_ID2_REGID_SHIFT 0 6467 6468 6469 /**************************************************************************** 6470 * ieee0Blk :: AutoNegAdv 6471 */ 6472 /* ieee0Blk :: AutoNegAdv :: next_page [15:15] */ 6473 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_MASK 0x8000 6474 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_ALIGN 0 6475 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_BITS 1 6476 #define IEEE0BLK_AUTONEGADV_NEXT_PAGE_SHIFT 15 6477 6478 /* ieee0Blk :: AutoNegAdv :: reserved0 [14:14] */ 6479 #define IEEE0BLK_AUTONEGADV_RESERVED0_MASK 0x4000 6480 #define IEEE0BLK_AUTONEGADV_RESERVED0_ALIGN 0 6481 #define IEEE0BLK_AUTONEGADV_RESERVED0_BITS 1 6482 #define IEEE0BLK_AUTONEGADV_RESERVED0_SHIFT 14 6483 6484 /* ieee0Blk :: AutoNegAdv :: remote_fault [13:12] */ 6485 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_MASK 0x3000 6486 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_ALIGN 0 6487 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_BITS 2 6488 #define IEEE0BLK_AUTONEGADV_REMOTE_FAULT_SHIFT 12 6489 6490 /* ieee0Blk :: AutoNegAdv :: reserved1 [11:09] */ 6491 #define IEEE0BLK_AUTONEGADV_RESERVED1_MASK 0x0e00 6492 #define IEEE0BLK_AUTONEGADV_RESERVED1_ALIGN 0 6493 #define IEEE0BLK_AUTONEGADV_RESERVED1_BITS 3 6494 #define IEEE0BLK_AUTONEGADV_RESERVED1_SHIFT 9 6495 6496 /* ieee0Blk :: AutoNegAdv :: pause [08:07] */ 6497 #define IEEE0BLK_AUTONEGADV_PAUSE_MASK 0x0180 6498 #define IEEE0BLK_AUTONEGADV_PAUSE_ALIGN 0 6499 #define IEEE0BLK_AUTONEGADV_PAUSE_BITS 2 6500 #define IEEE0BLK_AUTONEGADV_PAUSE_SHIFT 7 6501 6502 /* ieee0Blk :: AutoNegAdv :: half_duplex [06:06] */ 6503 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_MASK 0x0040 6504 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_ALIGN 0 6505 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_BITS 1 6506 #define IEEE0BLK_AUTONEGADV_HALF_DUPLEX_SHIFT 6 6507 6508 /* ieee0Blk :: AutoNegAdv :: full_duplex [05:05] */ 6509 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_MASK 0x0020 6510 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_ALIGN 0 6511 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_BITS 1 6512 #define IEEE0BLK_AUTONEGADV_FULL_DUPLEX_SHIFT 5 6513 6514 /* ieee0Blk :: AutoNegAdv :: reserved2 [04:00] */ 6515 #define IEEE0BLK_AUTONEGADV_RESERVED2_MASK 0x001f 6516 #define IEEE0BLK_AUTONEGADV_RESERVED2_ALIGN 0 6517 #define IEEE0BLK_AUTONEGADV_RESERVED2_BITS 5 6518 #define IEEE0BLK_AUTONEGADV_RESERVED2_SHIFT 0 6519 6520 6521 /**************************************************************************** 6522 * ieee0Blk :: AutoNegLPAbil 6523 */ 6524 /* ieee0Blk :: AutoNegLPAbil :: next_page [15:15] */ 6525 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_MASK 0x8000 6526 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_ALIGN 0 6527 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_BITS 1 6528 #define IEEE0BLK_AUTONEGLPABIL_NEXT_PAGE_SHIFT 15 6529 6530 /* ieee0Blk :: AutoNegLPAbil :: acknowledge [14:14] */ 6531 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_MASK 0x4000 6532 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN 0 6533 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_BITS 1 6534 #define IEEE0BLK_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT 14 6535 6536 /* ieee0Blk :: AutoNegLPAbil :: remote_fault [13:12] */ 6537 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_MASK 0x3000 6538 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_ALIGN 0 6539 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_BITS 2 6540 #define IEEE0BLK_AUTONEGLPABIL_REMOTE_FAULT_SHIFT 12 6541 6542 /* ieee0Blk :: AutoNegLPAbil :: reserved0 [11:09] */ 6543 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_MASK 0x0e00 6544 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_ALIGN 0 6545 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_BITS 3 6546 #define IEEE0BLK_AUTONEGLPABIL_RESERVED0_SHIFT 9 6547 6548 /* ieee0Blk :: AutoNegLPAbil :: pause [08:07] */ 6549 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_MASK 0x0180 6550 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_ALIGN 0 6551 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_BITS 2 6552 #define IEEE0BLK_AUTONEGLPABIL_PAUSE_SHIFT 7 6553 6554 /* ieee0Blk :: AutoNegLPAbil :: half_duplex [06:06] */ 6555 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_MASK 0x0040 6556 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_ALIGN 0 6557 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_BITS 1 6558 #define IEEE0BLK_AUTONEGLPABIL_HALF_DUPLEX_SHIFT 6 6559 6560 /* ieee0Blk :: AutoNegLPAbil :: full_duplex [05:05] */ 6561 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_MASK 0x0020 6562 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_ALIGN 0 6563 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_BITS 1 6564 #define IEEE0BLK_AUTONEGLPABIL_FULL_DUPLEX_SHIFT 5 6565 6566 /* ieee0Blk :: AutoNegLPAbil :: reserved1 [04:01] */ 6567 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_MASK 0x001e 6568 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_ALIGN 0 6569 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_BITS 4 6570 #define IEEE0BLK_AUTONEGLPABIL_RESERVED1_SHIFT 1 6571 6572 /* ieee0Blk :: AutoNegLPAbil :: sgmii_mode [00:00] */ 6573 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_MASK 0x0001 6574 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_ALIGN 0 6575 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_BITS 1 6576 #define IEEE0BLK_AUTONEGLPABIL_SGMII_MODE_SHIFT 0 6577 6578 6579 /**************************************************************************** 6580 * ieee0Blk :: AutoNegExp 6581 */ 6582 /* ieee0Blk :: AutoNegExp :: reserved0 [15:03] */ 6583 #define IEEE0BLK_AUTONEGEXP_RESERVED0_MASK 0xfff8 6584 #define IEEE0BLK_AUTONEGEXP_RESERVED0_ALIGN 0 6585 #define IEEE0BLK_AUTONEGEXP_RESERVED0_BITS 13 6586 #define IEEE0BLK_AUTONEGEXP_RESERVED0_SHIFT 3 6587 6588 /* ieee0Blk :: AutoNegExp :: next_page_ability [02:02] */ 6589 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK 0x0004 6590 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN 0 6591 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS 1 6592 #define IEEE0BLK_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT 2 6593 6594 /* ieee0Blk :: AutoNegExp :: page_received [01:01] */ 6595 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_MASK 0x0002 6596 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_ALIGN 0 6597 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_BITS 1 6598 #define IEEE0BLK_AUTONEGEXP_PAGE_RECEIVED_SHIFT 1 6599 6600 /* ieee0Blk :: AutoNegExp :: reserved1 [00:00] */ 6601 #define IEEE0BLK_AUTONEGEXP_RESERVED1_MASK 0x0001 6602 #define IEEE0BLK_AUTONEGEXP_RESERVED1_ALIGN 0 6603 #define IEEE0BLK_AUTONEGEXP_RESERVED1_BITS 1 6604 #define IEEE0BLK_AUTONEGEXP_RESERVED1_SHIFT 0 6605 6606 6607 /**************************************************************************** 6608 * ieee0Blk :: AutoNegNP 6609 */ 6610 /* ieee0Blk :: AutoNegNP :: Next_Page [15:15] */ 6611 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_MASK 0x8000 6612 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_ALIGN 0 6613 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_BITS 1 6614 #define IEEE0BLK_AUTONEGNP_NEXT_PAGE_SHIFT 15 6615 6616 /* ieee0Blk :: AutoNegNP :: Ack [14:14] */ 6617 #define IEEE0BLK_AUTONEGNP_ACK_MASK 0x4000 6618 #define IEEE0BLK_AUTONEGNP_ACK_ALIGN 0 6619 #define IEEE0BLK_AUTONEGNP_ACK_BITS 1 6620 #define IEEE0BLK_AUTONEGNP_ACK_SHIFT 14 6621 6622 /* ieee0Blk :: AutoNegNP :: Message_Page [13:13] */ 6623 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_MASK 0x2000 6624 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_ALIGN 0 6625 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_BITS 1 6626 #define IEEE0BLK_AUTONEGNP_MESSAGE_PAGE_SHIFT 13 6627 6628 /* ieee0Blk :: AutoNegNP :: Ack2 [12:12] */ 6629 #define IEEE0BLK_AUTONEGNP_ACK2_MASK 0x1000 6630 #define IEEE0BLK_AUTONEGNP_ACK2_ALIGN 0 6631 #define IEEE0BLK_AUTONEGNP_ACK2_BITS 1 6632 #define IEEE0BLK_AUTONEGNP_ACK2_SHIFT 12 6633 6634 /* ieee0Blk :: AutoNegNP :: Toggle [11:11] */ 6635 #define IEEE0BLK_AUTONEGNP_TOGGLE_MASK 0x0800 6636 #define IEEE0BLK_AUTONEGNP_TOGGLE_ALIGN 0 6637 #define IEEE0BLK_AUTONEGNP_TOGGLE_BITS 1 6638 #define IEEE0BLK_AUTONEGNP_TOGGLE_SHIFT 11 6639 6640 /* ieee0Blk :: AutoNegNP :: Message [10:00] */ 6641 #define IEEE0BLK_AUTONEGNP_MESSAGE_MASK 0x07ff 6642 #define IEEE0BLK_AUTONEGNP_MESSAGE_ALIGN 0 6643 #define IEEE0BLK_AUTONEGNP_MESSAGE_BITS 11 6644 #define IEEE0BLK_AUTONEGNP_MESSAGE_SHIFT 0 6645 6646 6647 /**************************************************************************** 6648 * ieee0Blk :: AutoNegLPAbil2 6649 */ 6650 /* ieee0Blk :: AutoNegLPAbil2 :: Next_Page [15:15] */ 6651 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_MASK 0x8000 6652 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_ALIGN 0 6653 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_BITS 1 6654 #define IEEE0BLK_AUTONEGLPABIL2_NEXT_PAGE_SHIFT 15 6655 6656 /* ieee0Blk :: AutoNegLPAbil2 :: Ack [14:14] */ 6657 #define IEEE0BLK_AUTONEGLPABIL2_ACK_MASK 0x4000 6658 #define IEEE0BLK_AUTONEGLPABIL2_ACK_ALIGN 0 6659 #define IEEE0BLK_AUTONEGLPABIL2_ACK_BITS 1 6660 #define IEEE0BLK_AUTONEGLPABIL2_ACK_SHIFT 14 6661 6662 /* ieee0Blk :: AutoNegLPAbil2 :: Message_Page [13:13] */ 6663 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_MASK 0x2000 6664 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN 0 6665 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_BITS 1 6666 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT 13 6667 6668 /* ieee0Blk :: AutoNegLPAbil2 :: Ack2 [12:12] */ 6669 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_MASK 0x1000 6670 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_ALIGN 0 6671 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_BITS 1 6672 #define IEEE0BLK_AUTONEGLPABIL2_ACK2_SHIFT 12 6673 6674 /* ieee0Blk :: AutoNegLPAbil2 :: Toggle [11:11] */ 6675 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_MASK 0x0800 6676 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_ALIGN 0 6677 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_BITS 1 6678 #define IEEE0BLK_AUTONEGLPABIL2_TOGGLE_SHIFT 11 6679 6680 /* ieee0Blk :: AutoNegLPAbil2 :: Message [10:00] */ 6681 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_MASK 0x07ff 6682 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_ALIGN 0 6683 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_BITS 11 6684 #define IEEE0BLK_AUTONEGLPABIL2_MESSAGE_SHIFT 0 6685 6686 6687 /**************************************************************************** 6688 * ieee0Blk :: MIIextStat 6689 */ 6690 /* ieee0Blk :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */ 6691 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000 6692 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 6693 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 6694 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15 6695 6696 /* ieee0Blk :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */ 6697 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000 6698 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 6699 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 6700 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14 6701 6702 /* ieee0Blk :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */ 6703 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000 6704 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 6705 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 6706 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13 6707 6708 /* ieee0Blk :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */ 6709 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000 6710 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 6711 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 6712 #define IEEE0BLK_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12 6713 6714 /* ieee0Blk :: MIIextStat :: reserved0 [11:00] */ 6715 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_MASK 0x0fff 6716 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_ALIGN 0 6717 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_BITS 12 6718 #define IEEE0BLK_MIIEXTSTAT_RESERVED0_SHIFT 0 6719 6720 6721 /**************************************************************************** 6722 * Hypercore_USER_XgxsBlk0 6723 */ 6724 /**************************************************************************** 6725 * XgxsBlk0 :: xgxsControl 6726 */ 6727 /* XgxsBlk0 :: xgxsControl :: pgen_en [15:15] */ 6728 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_MASK 0x8000 6729 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_ALIGN 0 6730 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_BITS 1 6731 #define XGXSBLK0_XGXSCONTROL_PGEN_EN_SHIFT 15 6732 6733 /* XgxsBlk0 :: xgxsControl :: pcmp_en [14:14] */ 6734 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_MASK 0x4000 6735 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_ALIGN 0 6736 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_BITS 1 6737 #define XGXSBLK0_XGXSCONTROL_PCMP_EN_SHIFT 14 6738 6739 /* XgxsBlk0 :: xgxsControl :: start_sequencer [13:13] */ 6740 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_MASK 0x2000 6741 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_ALIGN 0 6742 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_BITS 1 6743 #define XGXSBLK0_XGXSCONTROL_START_SEQUENCER_SHIFT 13 6744 6745 /* XgxsBlk0 :: xgxsControl :: reset_anlg [12:12] */ 6746 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_MASK 0x1000 6747 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_ALIGN 0 6748 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_BITS 1 6749 #define XGXSBLK0_XGXSCONTROL_RESET_ANLG_SHIFT 12 6750 6751 /* XgxsBlk0 :: xgxsControl :: mode_10g [11:08] */ 6752 #define XGXSBLK0_XGXSCONTROL_MODE_10G_MASK 0x0f00 6753 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ALIGN 0 6754 #define XGXSBLK0_XGXSCONTROL_MODE_10G_BITS 4 6755 #define XGXSBLK0_XGXSCONTROL_MODE_10G_SHIFT 8 6756 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS 0 6757 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXG_nCC 1 6758 #define XGXSBLK0_XGXSCONTROL_MODE_10G_IndLane_OS5 5 6759 #define XGXSBLK0_XGXSCONTROL_MODE_10G_Indlanes 6 6760 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PCI 7 6761 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_nLQ 8 6762 #define XGXSBLK0_XGXSCONTROL_MODE_10G_XGXS_nLQnCC 9 6763 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PBypass 10 6764 #define XGXSBLK0_XGXSCONTROL_MODE_10G_PBypass_nDSK 11 6765 #define XGXSBLK0_XGXSCONTROL_MODE_10G_ComboCoreMode 12 6766 #define XGXSBLK0_XGXSCONTROL_MODE_10G_Clocks_off 15 6767 6768 /* XgxsBlk0 :: xgxsControl :: pll_bypass [07:07] */ 6769 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_MASK 0x0080 6770 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_ALIGN 0 6771 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_BITS 1 6772 #define XGXSBLK0_XGXSCONTROL_PLL_BYPASS_SHIFT 7 6773 6774 /* XgxsBlk0 :: xgxsControl :: rloop [06:06] */ 6775 #define XGXSBLK0_XGXSCONTROL_RLOOP_MASK 0x0040 6776 #define XGXSBLK0_XGXSCONTROL_RLOOP_ALIGN 0 6777 #define XGXSBLK0_XGXSCONTROL_RLOOP_BITS 1 6778 #define XGXSBLK0_XGXSCONTROL_RLOOP_SHIFT 6 6779 6780 /* XgxsBlk0 :: xgxsControl :: reserved0 [05:05] */ 6781 #define XGXSBLK0_XGXSCONTROL_RESERVED0_MASK 0x0020 6782 #define XGXSBLK0_XGXSCONTROL_RESERVED0_ALIGN 0 6783 #define XGXSBLK0_XGXSCONTROL_RESERVED0_BITS 1 6784 #define XGXSBLK0_XGXSCONTROL_RESERVED0_SHIFT 5 6785 6786 /* XgxsBlk0 :: xgxsControl :: mdio_cont_en [04:04] */ 6787 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_MASK 0x0010 6788 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_ALIGN 0 6789 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_BITS 1 6790 #define XGXSBLK0_XGXSCONTROL_MDIO_CONT_EN_SHIFT 4 6791 6792 /* XgxsBlk0 :: xgxsControl :: cdet_en [03:03] */ 6793 #define XGXSBLK0_XGXSCONTROL_CDET_EN_MASK 0x0008 6794 #define XGXSBLK0_XGXSCONTROL_CDET_EN_ALIGN 0 6795 #define XGXSBLK0_XGXSCONTROL_CDET_EN_BITS 1 6796 #define XGXSBLK0_XGXSCONTROL_CDET_EN_SHIFT 3 6797 6798 /* XgxsBlk0 :: xgxsControl :: eden [02:02] */ 6799 #define XGXSBLK0_XGXSCONTROL_EDEN_MASK 0x0004 6800 #define XGXSBLK0_XGXSCONTROL_EDEN_ALIGN 0 6801 #define XGXSBLK0_XGXSCONTROL_EDEN_BITS 1 6802 #define XGXSBLK0_XGXSCONTROL_EDEN_SHIFT 2 6803 6804 /* XgxsBlk0 :: xgxsControl :: afrst_en [01:01] */ 6805 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_MASK 0x0002 6806 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_ALIGN 0 6807 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_BITS 1 6808 #define XGXSBLK0_XGXSCONTROL_AFRST_EN_SHIFT 1 6809 6810 /* XgxsBlk0 :: xgxsControl :: txcko_div [00:00] */ 6811 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_MASK 0x0001 6812 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_ALIGN 0 6813 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_BITS 1 6814 #define XGXSBLK0_XGXSCONTROL_TXCKO_DIV_SHIFT 0 6815 6816 6817 /**************************************************************************** 6818 * XgxsBlk0 :: xgxsStatus 6819 */ 6820 /* XgxsBlk0 :: xgxsStatus :: status_en [15:15] */ 6821 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_MASK 0x8000 6822 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_ALIGN 0 6823 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_BITS 1 6824 #define XGXSBLK0_XGXSSTATUS_STATUS_EN_SHIFT 15 6825 6826 /* XgxsBlk0 :: xgxsStatus :: reserved0 [14:14] */ 6827 #define XGXSBLK0_XGXSSTATUS_RESERVED0_MASK 0x4000 6828 #define XGXSBLK0_XGXSSTATUS_RESERVED0_ALIGN 0 6829 #define XGXSBLK0_XGXSSTATUS_RESERVED0_BITS 1 6830 #define XGXSBLK0_XGXSSTATUS_RESERVED0_SHIFT 14 6831 6832 /* XgxsBlk0 :: xgxsStatus :: tx_remote_fault [13:13] */ 6833 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_MASK 0x2000 6834 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_ALIGN 0 6835 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_BITS 1 6836 #define XGXSBLK0_XGXSSTATUS_TX_REMOTE_FAULT_SHIFT 13 6837 6838 /* XgxsBlk0 :: xgxsStatus :: rx_remote_fault [12:12] */ 6839 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_MASK 0x1000 6840 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_ALIGN 0 6841 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_BITS 1 6842 #define XGXSBLK0_XGXSSTATUS_RX_REMOTE_FAULT_SHIFT 12 6843 6844 /* XgxsBlk0 :: xgxsStatus :: txpll_lock [11:11] */ 6845 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_MASK 0x0800 6846 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_ALIGN 0 6847 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_BITS 1 6848 #define XGXSBLK0_XGXSSTATUS_TXPLL_LOCK_SHIFT 11 6849 6850 /* XgxsBlk0 :: xgxsStatus :: txd_fifo_err [10:10] */ 6851 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_MASK 0x0400 6852 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_ALIGN 0 6853 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_BITS 1 6854 #define XGXSBLK0_XGXSSTATUS_TXD_FIFO_ERR_SHIFT 10 6855 6856 /* XgxsBlk0 :: xgxsStatus :: sequencer_done [09:09] */ 6857 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_MASK 0x0200 6858 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_ALIGN 0 6859 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_BITS 1 6860 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_DONE_SHIFT 9 6861 6862 /* XgxsBlk0 :: xgxsStatus :: sequencer_pass [08:08] */ 6863 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_MASK 0x0100 6864 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_ALIGN 0 6865 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_BITS 1 6866 #define XGXSBLK0_XGXSSTATUS_SEQUENCER_PASS_SHIFT 8 6867 6868 /* XgxsBlk0 :: xgxsStatus :: rxferr [07:04] */ 6869 #define XGXSBLK0_XGXSSTATUS_RXFERR_MASK 0x00f0 6870 #define XGXSBLK0_XGXSSTATUS_RXFERR_ALIGN 0 6871 #define XGXSBLK0_XGXSSTATUS_RXFERR_BITS 4 6872 #define XGXSBLK0_XGXSSTATUS_RXFERR_SHIFT 4 6873 6874 /* XgxsBlk0 :: xgxsStatus :: pll_mode_afe [03:03] */ 6875 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_MASK 0x0008 6876 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_ALIGN 0 6877 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_BITS 1 6878 #define XGXSBLK0_XGXSSTATUS_PLL_MODE_AFE_SHIFT 3 6879 6880 /* XgxsBlk0 :: xgxsStatus :: ckcmp_unflow [02:02] */ 6881 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_MASK 0x0004 6882 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_ALIGN 0 6883 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_BITS 1 6884 #define XGXSBLK0_XGXSSTATUS_CKCMP_UNFLOW_SHIFT 2 6885 6886 /* XgxsBlk0 :: xgxsStatus :: ckcmp_ovflow [01:01] */ 6887 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_MASK 0x0002 6888 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_ALIGN 0 6889 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_BITS 1 6890 #define XGXSBLK0_XGXSSTATUS_CKCMP_OVFLOW_SHIFT 1 6891 6892 /* XgxsBlk0 :: xgxsStatus :: skew_status [00:00] */ 6893 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_MASK 0x0001 6894 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_ALIGN 0 6895 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_BITS 1 6896 #define XGXSBLK0_XGXSSTATUS_SKEW_STATUS_SHIFT 0 6897 6898 6899 /**************************************************************************** 6900 * XgxsBlk0 :: xgmiiIdle 6901 */ 6902 /* XgxsBlk0 :: xgmiiIdle :: I [15:08] */ 6903 #define XGXSBLK0_XGMIIIDLE_I_MASK 0xff00 6904 #define XGXSBLK0_XGMIIIDLE_I_ALIGN 0 6905 #define XGXSBLK0_XGMIIIDLE_I_BITS 8 6906 #define XGXSBLK0_XGMIIIDLE_I_SHIFT 8 6907 6908 /* XgxsBlk0 :: xgmiiIdle :: Ib [07:00] */ 6909 #define XGXSBLK0_XGMIIIDLE_IB_MASK 0x00ff 6910 #define XGXSBLK0_XGMIIIDLE_IB_ALIGN 0 6911 #define XGXSBLK0_XGMIIIDLE_IB_BITS 8 6912 #define XGXSBLK0_XGMIIIDLE_IB_SHIFT 0 6913 6914 6915 /**************************************************************************** 6916 * XgxsBlk0 :: xgmiiSync 6917 */ 6918 /* XgxsBlk0 :: xgmiiSync :: K [15:08] */ 6919 #define XGXSBLK0_XGMIISYNC_K_MASK 0xff00 6920 #define XGXSBLK0_XGMIISYNC_K_ALIGN 0 6921 #define XGXSBLK0_XGMIISYNC_K_BITS 8 6922 #define XGXSBLK0_XGMIISYNC_K_SHIFT 8 6923 6924 /* XgxsBlk0 :: xgmiiSync :: Kb [07:00] */ 6925 #define XGXSBLK0_XGMIISYNC_KB_MASK 0x00ff 6926 #define XGXSBLK0_XGMIISYNC_KB_ALIGN 0 6927 #define XGXSBLK0_XGMIISYNC_KB_BITS 8 6928 #define XGXSBLK0_XGMIISYNC_KB_SHIFT 0 6929 6930 6931 /**************************************************************************** 6932 * XgxsBlk0 :: xgmiiSkip 6933 */ 6934 /* XgxsBlk0 :: xgmiiSkip :: R [15:08] */ 6935 #define XGXSBLK0_XGMIISKIP_R_MASK 0xff00 6936 #define XGXSBLK0_XGMIISKIP_R_ALIGN 0 6937 #define XGXSBLK0_XGMIISKIP_R_BITS 8 6938 #define XGXSBLK0_XGMIISKIP_R_SHIFT 8 6939 6940 /* XgxsBlk0 :: xgmiiSkip :: Rb [07:00] */ 6941 #define XGXSBLK0_XGMIISKIP_RB_MASK 0x00ff 6942 #define XGXSBLK0_XGMIISKIP_RB_ALIGN 0 6943 #define XGXSBLK0_XGMIISKIP_RB_BITS 8 6944 #define XGXSBLK0_XGMIISKIP_RB_SHIFT 0 6945 6946 6947 /**************************************************************************** 6948 * XgxsBlk0 :: xgmiiSopEop 6949 */ 6950 /* XgxsBlk0 :: xgmiiSopEop :: S [15:08] */ 6951 #define XGXSBLK0_XGMIISOPEOP_S_MASK 0xff00 6952 #define XGXSBLK0_XGMIISOPEOP_S_ALIGN 0 6953 #define XGXSBLK0_XGMIISOPEOP_S_BITS 8 6954 #define XGXSBLK0_XGMIISOPEOP_S_SHIFT 8 6955 6956 /* XgxsBlk0 :: xgmiiSopEop :: T [07:00] */ 6957 #define XGXSBLK0_XGMIISOPEOP_T_MASK 0x00ff 6958 #define XGXSBLK0_XGMIISOPEOP_T_ALIGN 0 6959 #define XGXSBLK0_XGMIISOPEOP_T_BITS 8 6960 #define XGXSBLK0_XGMIISOPEOP_T_SHIFT 0 6961 6962 6963 /**************************************************************************** 6964 * XgxsBlk0 :: xgmiiAlign 6965 */ 6966 /* XgxsBlk0 :: xgmiiAlign :: E [15:08] */ 6967 #define XGXSBLK0_XGMIIALIGN_E_MASK 0xff00 6968 #define XGXSBLK0_XGMIIALIGN_E_ALIGN 0 6969 #define XGXSBLK0_XGMIIALIGN_E_BITS 8 6970 #define XGXSBLK0_XGMIIALIGN_E_SHIFT 8 6971 6972 /* XgxsBlk0 :: xgmiiAlign :: A [07:00] */ 6973 #define XGXSBLK0_XGMIIALIGN_A_MASK 0x00ff 6974 #define XGXSBLK0_XGMIIALIGN_A_ALIGN 0 6975 #define XGXSBLK0_XGMIIALIGN_A_BITS 8 6976 #define XGXSBLK0_XGMIIALIGN_A_SHIFT 0 6977 6978 6979 /**************************************************************************** 6980 * XgxsBlk0 :: xgmiiRcontrol 6981 */ 6982 /* XgxsBlk0 :: xgmiiRcontrol :: reserved0 [15:15] */ 6983 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_MASK 0x8000 6984 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_ALIGN 0 6985 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_BITS 1 6986 #define XGXSBLK0_XGMIIRCONTROL_RESERVED0_SHIFT 15 6987 6988 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf0_en [14:14] */ 6989 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_MASK 0x4000 6990 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_ALIGN 0 6991 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_BITS 1 6992 #define XGXSBLK0_XGMIIRCONTROL_TX_LF0_EN_SHIFT 14 6993 6994 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf1_en [13:13] */ 6995 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_MASK 0x2000 6996 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_ALIGN 0 6997 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_BITS 1 6998 #define XGXSBLK0_XGMIIRCONTROL_TX_LF1_EN_SHIFT 13 6999 7000 /* XgxsBlk0 :: xgmiiRcontrol :: tx_lf2_en [12:12] */ 7001 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_MASK 0x1000 7002 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_ALIGN 0 7003 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_BITS 1 7004 #define XGXSBLK0_XGMIIRCONTROL_TX_LF2_EN_SHIFT 12 7005 7006 /* XgxsBlk0 :: xgmiiRcontrol :: force_inbndls_en [11:11] */ 7007 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_MASK 0x0800 7008 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_ALIGN 0 7009 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_BITS 1 7010 #define XGXSBLK0_XGMIIRCONTROL_FORCE_INBNDLS_EN_SHIFT 11 7011 7012 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_en [10:10] */ 7013 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_MASK 0x0400 7014 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_ALIGN 0 7015 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_BITS 1 7016 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_EN_SHIFT 10 7017 7018 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_std_en [09:09] */ 7019 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_MASK 0x0200 7020 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_ALIGN 0 7021 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_BITS 1 7022 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_STD_EN_SHIFT 9 7023 7024 /* XgxsBlk0 :: xgmiiRcontrol :: chk_end_force [08:08] */ 7025 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_MASK 0x0100 7026 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_ALIGN 0 7027 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_BITS 1 7028 #define XGXSBLK0_XGMIIRCONTROL_CHK_END_FORCE_SHIFT 8 7029 7030 /* XgxsBlk0 :: xgmiiRcontrol :: reserved1 [07:07] */ 7031 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_MASK 0x0080 7032 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_ALIGN 0 7033 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_BITS 1 7034 #define XGXSBLK0_XGMIIRCONTROL_RESERVED1_SHIFT 7 7035 7036 /* XgxsBlk0 :: xgmiiRcontrol :: scr_en_4lane [06:06] */ 7037 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_MASK 0x0040 7038 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_ALIGN 0 7039 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_BITS 1 7040 #define XGXSBLK0_XGMIIRCONTROL_SCR_EN_4LANE_SHIFT 6 7041 7042 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_noIPG_en [05:05] */ 7043 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_MASK 0x0020 7044 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_ALIGN 0 7045 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_BITS 1 7046 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_NOIPG_EN_SHIFT 5 7047 7048 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_afrst_en [04:04] */ 7049 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_MASK 0x0010 7050 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_ALIGN 0 7051 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_BITS 1 7052 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_AFRST_EN_SHIFT 4 7053 7054 /* XgxsBlk0 :: xgmiiRcontrol :: ckcmp_gt1_Icol_dis [03:03] */ 7055 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_MASK 0x0008 7056 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_ALIGN 0 7057 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_BITS 1 7058 #define XGXSBLK0_XGMIIRCONTROL_CKCMP_GT1_ICOL_DIS_SHIFT 3 7059 7060 /* XgxsBlk0 :: xgmiiRcontrol :: reserved2 [02:00] */ 7061 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_MASK 0x0007 7062 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_ALIGN 0 7063 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_BITS 3 7064 #define XGXSBLK0_XGMIIRCONTROL_RESERVED2_SHIFT 0 7065 7066 7067 /**************************************************************************** 7068 * XgxsBlk0 :: xgmiiTcontrol 7069 */ 7070 /* XgxsBlk0 :: xgmiiTcontrol :: swapen [15:15] */ 7071 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_MASK 0x8000 7072 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_ALIGN 0 7073 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_BITS 1 7074 #define XGXSBLK0_XGMIITCONTROL_SWAPEN_SHIFT 15 7075 7076 /* XgxsBlk0 :: xgmiiTcontrol :: swap_lane_ind [14:14] */ 7077 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_MASK 0x4000 7078 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_ALIGN 0 7079 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_BITS 1 7080 #define XGXSBLK0_XGMIITCONTROL_SWAP_LANE_IND_SHIFT 14 7081 7082 /* XgxsBlk0 :: xgmiiTcontrol :: pn_sel [13:13] */ 7083 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_MASK 0x2000 7084 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_ALIGN 0 7085 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_BITS 1 7086 #define XGXSBLK0_XGMIITCONTROL_PN_SEL_SHIFT 13 7087 7088 /* XgxsBlk0 :: xgmiiTcontrol :: reserved0 [12:09] */ 7089 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_MASK 0x1e00 7090 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_ALIGN 0 7091 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_BITS 4 7092 #define XGXSBLK0_XGMIITCONTROL_RESERVED0_SHIFT 9 7093 7094 /* XgxsBlk0 :: xgmiiTcontrol :: alignstat_rxlf_en [08:08] */ 7095 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_MASK 0x0100 7096 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_ALIGN 0 7097 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_BITS 1 7098 #define XGXSBLK0_XGMIITCONTROL_ALIGNSTAT_RXLF_EN_SHIFT 8 7099 7100 /* XgxsBlk0 :: xgmiiTcontrol :: flip_txrx_lf [07:07] */ 7101 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_MASK 0x0080 7102 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_ALIGN 0 7103 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_BITS 1 7104 #define XGXSBLK0_XGMIITCONTROL_FLIP_TXRX_LF_SHIFT 7 7105 7106 /* XgxsBlk0 :: xgmiiTcontrol :: xenpak_lfclr_en [06:06] */ 7107 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_MASK 0x0040 7108 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_ALIGN 0 7109 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_BITS 1 7110 #define XGXSBLK0_XGMIITCONTROL_XENPAK_LFCLR_EN_SHIFT 6 7111 7112 /* XgxsBlk0 :: xgmiiTcontrol :: tx_xgmii_Tcol_old_en [05:05] */ 7113 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_MASK 0x0020 7114 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_ALIGN 0 7115 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_BITS 1 7116 #define XGXSBLK0_XGMIITCONTROL_TX_XGMII_TCOL_OLD_EN_SHIFT 5 7117 7118 /* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_IorRF_en [04:04] */ 7119 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_MASK 0x0010 7120 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_ALIGN 0 7121 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_BITS 1 7122 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_IORRF_EN_SHIFT 4 7123 7124 /* XgxsBlk0 :: xgmiiTcontrol :: tx_force_dpath_I_en [03:03] */ 7125 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_MASK 0x0008 7126 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_ALIGN 0 7127 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_BITS 1 7128 #define XGXSBLK0_XGMIITCONTROL_TX_FORCE_DPATH_I_EN_SHIFT 3 7129 7130 /* XgxsBlk0 :: xgmiiTcontrol :: reserved1 [02:00] */ 7131 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_MASK 0x0007 7132 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_ALIGN 0 7133 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_BITS 3 7134 #define XGXSBLK0_XGMIITCONTROL_RESERVED1_SHIFT 0 7135 7136 7137 /**************************************************************************** 7138 * XgxsBlk0 :: xgmiiSwap 7139 */ 7140 /* XgxsBlk0 :: xgmiiSwap :: swap_count [15:00] */ 7141 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_MASK 0xffff 7142 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_ALIGN 0 7143 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_BITS 16 7144 #define XGXSBLK0_XGMIISWAP_SWAP_COUNT_SHIFT 0 7145 7146 7147 /**************************************************************************** 7148 * XgxsBlk0 :: lssLsid 7149 */ 7150 /* XgxsBlk0 :: lssLsid :: lss_ls_id [15:08] */ 7151 #define XGXSBLK0_LSSLSID_LSS_LS_ID_MASK 0xff00 7152 #define XGXSBLK0_LSSLSID_LSS_LS_ID_ALIGN 0 7153 #define XGXSBLK0_LSSLSID_LSS_LS_ID_BITS 8 7154 #define XGXSBLK0_LSSLSID_LSS_LS_ID_SHIFT 8 7155 7156 /* XgxsBlk0 :: lssLsid :: lss_domain_id [07:00] */ 7157 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_MASK 0x00ff 7158 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_ALIGN 0 7159 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_BITS 8 7160 #define XGXSBLK0_LSSLSID_LSS_DOMAIN_ID_SHIFT 0 7161 7162 7163 /**************************************************************************** 7164 * XgxsBlk0 :: lssTinfo 7165 */ 7166 /* XgxsBlk0 :: lssTinfo :: lss_function_id [15:08] */ 7167 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_MASK 0xff00 7168 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_ALIGN 0 7169 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_BITS 8 7170 #define XGXSBLK0_LSSTINFO_LSS_FUNCTION_ID_SHIFT 8 7171 7172 /* XgxsBlk0 :: lssTinfo :: lssL_info_byte [07:00] */ 7173 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_MASK 0x00ff 7174 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_ALIGN 0 7175 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_BITS 8 7176 #define XGXSBLK0_LSSTINFO_LSSL_INFO_BYTE_SHIFT 0 7177 7178 7179 /**************************************************************************** 7180 * XgxsBlk0 :: lssRinfo 7181 */ 7182 /* XgxsBlk0 :: lssRinfo :: control_en [15:15] */ 7183 #define XGXSBLK0_LSSRINFO_CONTROL_EN_MASK 0x8000 7184 #define XGXSBLK0_LSSRINFO_CONTROL_EN_ALIGN 0 7185 #define XGXSBLK0_LSSRINFO_CONTROL_EN_BITS 1 7186 #define XGXSBLK0_LSSRINFO_CONTROL_EN_SHIFT 15 7187 7188 /* XgxsBlk0 :: lssRinfo :: reserved0 [14:14] */ 7189 #define XGXSBLK0_LSSRINFO_RESERVED0_MASK 0x4000 7190 #define XGXSBLK0_LSSRINFO_RESERVED0_ALIGN 0 7191 #define XGXSBLK0_LSSRINFO_RESERVED0_BITS 1 7192 #define XGXSBLK0_LSSRINFO_RESERVED0_SHIFT 14 7193 7194 /* XgxsBlk0 :: lssRinfo :: lss_ls_id8 [13:13] */ 7195 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_MASK 0x2000 7196 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_ALIGN 0 7197 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_BITS 1 7198 #define XGXSBLK0_LSSRINFO_LSS_LS_ID8_SHIFT 13 7199 7200 /* XgxsBlk0 :: lssRinfo :: lss_domain_id8 [12:12] */ 7201 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_MASK 0x1000 7202 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_ALIGN 0 7203 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_BITS 1 7204 #define XGXSBLK0_LSSRINFO_LSS_DOMAIN_ID8_SHIFT 12 7205 7206 /* XgxsBlk0 :: lssRinfo :: lss_function_id8 [11:11] */ 7207 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_MASK 0x0800 7208 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_ALIGN 0 7209 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_BITS 1 7210 #define XGXSBLK0_LSSRINFO_LSS_FUNCTION_ID8_SHIFT 11 7211 7212 /* XgxsBlk0 :: lssRinfo :: lssL_info_byte8 [10:10] */ 7213 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_MASK 0x0400 7214 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_ALIGN 0 7215 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_BITS 1 7216 #define XGXSBLK0_LSSRINFO_LSSL_INFO_BYTE8_SHIFT 10 7217 7218 /* XgxsBlk0 :: lssRinfo :: reserved1 [09:09] */ 7219 #define XGXSBLK0_LSSRINFO_RESERVED1_MASK 0x0200 7220 #define XGXSBLK0_LSSRINFO_RESERVED1_ALIGN 0 7221 #define XGXSBLK0_LSSRINFO_RESERVED1_BITS 1 7222 #define XGXSBLK0_LSSRINFO_RESERVED1_SHIFT 9 7223 7224 /* XgxsBlk0 :: lssRinfo :: lssR_info_byte [08:00] */ 7225 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_MASK 0x01ff 7226 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_ALIGN 0 7227 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_BITS 9 7228 #define XGXSBLK0_LSSRINFO_LSSR_INFO_BYTE_SHIFT 0 7229 7230 7231 /**************************************************************************** 7232 * XgxsBlk0 :: mmdSelect 7233 */ 7234 /* XgxsBlk0 :: mmdSelect :: multiPRTs_en [15:15] */ 7235 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_MASK 0x8000 7236 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_ALIGN 0 7237 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_BITS 1 7238 #define XGXSBLK0_MMDSELECT_MULTIPRTS_EN_SHIFT 15 7239 7240 /* XgxsBlk0 :: mmdSelect :: multiMMDs_en [14:14] */ 7241 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_MASK 0x4000 7242 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_ALIGN 0 7243 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_BITS 1 7244 #define XGXSBLK0_MMDSELECT_MULTIMMDS_EN_SHIFT 14 7245 7246 /* XgxsBlk0 :: mmdSelect :: reserved0 [13:04] */ 7247 #define XGXSBLK0_MMDSELECT_RESERVED0_MASK 0x3ff0 7248 #define XGXSBLK0_MMDSELECT_RESERVED0_ALIGN 0 7249 #define XGXSBLK0_MMDSELECT_RESERVED0_BITS 10 7250 #define XGXSBLK0_MMDSELECT_RESERVED0_SHIFT 4 7251 7252 /* XgxsBlk0 :: mmdSelect :: devAN_en [03:03] */ 7253 #define XGXSBLK0_MMDSELECT_DEVAN_EN_MASK 0x0008 7254 #define XGXSBLK0_MMDSELECT_DEVAN_EN_ALIGN 0 7255 #define XGXSBLK0_MMDSELECT_DEVAN_EN_BITS 1 7256 #define XGXSBLK0_MMDSELECT_DEVAN_EN_SHIFT 3 7257 7258 /* XgxsBlk0 :: mmdSelect :: devPMD_en [02:02] */ 7259 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_MASK 0x0004 7260 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_ALIGN 0 7261 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_BITS 1 7262 #define XGXSBLK0_MMDSELECT_DEVPMD_EN_SHIFT 2 7263 7264 /* XgxsBlk0 :: mmdSelect :: devDEVAD_en [01:01] */ 7265 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_MASK 0x0002 7266 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_ALIGN 0 7267 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_BITS 1 7268 #define XGXSBLK0_MMDSELECT_DEVDEVAD_EN_SHIFT 1 7269 7270 /* XgxsBlk0 :: mmdSelect :: devCL22_en [00:00] */ 7271 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_MASK 0x0001 7272 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_ALIGN 0 7273 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_BITS 1 7274 #define XGXSBLK0_MMDSELECT_DEVCL22_EN_SHIFT 0 7275 7276 7277 /**************************************************************************** 7278 * XgxsBlk0 :: miscControl1 7279 */ 7280 /* XgxsBlk0 :: miscControl1 :: PMD_Lane3_tx_disable [15:15] */ 7281 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_MASK 0x8000 7282 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_ALIGN 0 7283 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_BITS 1 7284 #define XGXSBLK0_MISCCONTROL1_PMD_LANE3_TX_DISABLE_SHIFT 15 7285 7286 /* XgxsBlk0 :: miscControl1 :: PMD_Lane2_tx_disable [14:14] */ 7287 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_MASK 0x4000 7288 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_ALIGN 0 7289 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_BITS 1 7290 #define XGXSBLK0_MISCCONTROL1_PMD_LANE2_TX_DISABLE_SHIFT 14 7291 7292 /* XgxsBlk0 :: miscControl1 :: PMD_Lane1_tx_disable [13:13] */ 7293 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_MASK 0x2000 7294 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_ALIGN 0 7295 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_BITS 1 7296 #define XGXSBLK0_MISCCONTROL1_PMD_LANE1_TX_DISABLE_SHIFT 13 7297 7298 /* XgxsBlk0 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */ 7299 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK 0x1000 7300 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN 0 7301 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS 1 7302 #define XGXSBLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT 12 7303 7304 /* XgxsBlk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */ 7305 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK 0x0800 7306 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN 0 7307 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS 1 7308 #define XGXSBLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT 11 7309 7310 /* XgxsBlk0 :: miscControl1 :: PCS_dev_en_override_mask [10:10] */ 7311 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_MASK 0x0400 7312 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_ALIGN 0 7313 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_BITS 1 7314 #define XGXSBLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_SHIFT 10 7315 7316 /* XgxsBlk0 :: miscControl1 :: PMD_dev_en_override_mask [09:09] */ 7317 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_MASK 0x0200 7318 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_ALIGN 0 7319 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_BITS 1 7320 #define XGXSBLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_SHIFT 9 7321 7322 /* XgxsBlk0 :: miscControl1 :: reserved0 [08:08] */ 7323 #define XGXSBLK0_MISCCONTROL1_RESERVED0_MASK 0x0100 7324 #define XGXSBLK0_MISCCONTROL1_RESERVED0_ALIGN 0 7325 #define XGXSBLK0_MISCCONTROL1_RESERVED0_BITS 1 7326 #define XGXSBLK0_MISCCONTROL1_RESERVED0_SHIFT 8 7327 7328 /* XgxsBlk0 :: miscControl1 :: clear_linkdown [07:07] */ 7329 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_MASK 0x0080 7330 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_ALIGN 0 7331 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_BITS 1 7332 #define XGXSBLK0_MISCCONTROL1_CLEAR_LINKDOWN_SHIFT 7 7333 7334 /* XgxsBlk0 :: miscControl1 :: latch_linkdown_enable [06:06] */ 7335 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_MASK 0x0040 7336 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_ALIGN 0 7337 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_BITS 1 7338 #define XGXSBLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_SHIFT 6 7339 7340 /* XgxsBlk0 :: miscControl1 :: reserved1 [05:05] */ 7341 #define XGXSBLK0_MISCCONTROL1_RESERVED1_MASK 0x0020 7342 #define XGXSBLK0_MISCCONTROL1_RESERVED1_ALIGN 0 7343 #define XGXSBLK0_MISCCONTROL1_RESERVED1_BITS 1 7344 #define XGXSBLK0_MISCCONTROL1_RESERVED1_SHIFT 5 7345 7346 /* XgxsBlk0 :: miscControl1 :: force_div5_for_lxck25 [04:04] */ 7347 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK 0x0010 7348 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN 0 7349 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS 1 7350 #define XGXSBLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT 4 7351 7352 /* XgxsBlk0 :: miscControl1 :: pardet10g_pwrdnLink_en [03:03] */ 7353 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_MASK 0x0008 7354 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_ALIGN 0 7355 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_BITS 1 7356 #define XGXSBLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_SHIFT 3 7357 7358 /* XgxsBlk0 :: miscControl1 :: invert_rx_sigdet [02:02] */ 7359 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_MASK 0x0004 7360 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN 0 7361 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_BITS 1 7362 #define XGXSBLK0_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT 2 7363 7364 /* XgxsBlk0 :: miscControl1 :: ieee_blksel_autodet [01:01] */ 7365 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK 0x0002 7366 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN 0 7367 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS 1 7368 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT 1 7369 7370 /* XgxsBlk0 :: miscControl1 :: ieee_blksel_val [00:00] */ 7371 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK 0x0001 7372 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN 0 7373 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS 1 7374 #define XGXSBLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT 0 7375 7376 7377 /**************************************************************************** 7378 * XgxsBlk0 :: BlockAddress 7379 */ 7380 /* XgxsBlk0 :: BlockAddress :: reserved0 [15:15] */ 7381 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_MASK 0x8000 7382 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_ALIGN 0 7383 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_BITS 1 7384 #define XGXSBLK0_BLOCKADDRESS_RESERVED0_SHIFT 15 7385 7386 /* XgxsBlk0 :: BlockAddress :: BlockAddress [14:04] */ 7387 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_MASK 0x7ff0 7388 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_ALIGN 0 7389 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_BITS 11 7390 #define XGXSBLK0_BLOCKADDRESS_BLOCKADDRESS_SHIFT 4 7391 7392 /* XgxsBlk0 :: BlockAddress :: reserved1 [03:00] */ 7393 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_MASK 0x000f 7394 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_ALIGN 0 7395 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_BITS 4 7396 #define XGXSBLK0_BLOCKADDRESS_RESERVED1_SHIFT 0 7397 7398 7399 /**************************************************************************** 7400 * Hypercore_USER_XgxsBlk1 7401 */ 7402 /**************************************************************************** 7403 * XgxsBlk1 :: deskew 7404 */ 7405 /* XgxsBlk1 :: deskew :: link_en [15:15] */ 7406 #define XGXSBLK1_DESKEW_LINK_EN_MASK 0x8000 7407 #define XGXSBLK1_DESKEW_LINK_EN_ALIGN 0 7408 #define XGXSBLK1_DESKEW_LINK_EN_BITS 1 7409 #define XGXSBLK1_DESKEW_LINK_EN_SHIFT 15 7410 7411 /* XgxsBlk1 :: deskew :: deskew_hyst_en [14:14] */ 7412 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_MASK 0x4000 7413 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_ALIGN 0 7414 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_BITS 1 7415 #define XGXSBLK1_DESKEW_DESKEW_HYST_EN_SHIFT 14 7416 7417 /* XgxsBlk1 :: deskew :: dswin [13:09] */ 7418 #define XGXSBLK1_DESKEW_DSWIN_MASK 0x3e00 7419 #define XGXSBLK1_DESKEW_DSWIN_ALIGN 0 7420 #define XGXSBLK1_DESKEW_DSWIN_BITS 5 7421 #define XGXSBLK1_DESKEW_DSWIN_SHIFT 9 7422 7423 /* XgxsBlk1 :: deskew :: mpwin [08:00] */ 7424 #define XGXSBLK1_DESKEW_MPWIN_MASK 0x01ff 7425 #define XGXSBLK1_DESKEW_MPWIN_ALIGN 0 7426 #define XGXSBLK1_DESKEW_MPWIN_BITS 9 7427 #define XGXSBLK1_DESKEW_MPWIN_SHIFT 0 7428 7429 7430 /**************************************************************************** 7431 * XgxsBlk1 :: link 7432 */ 7433 /* XgxsBlk1 :: link :: Acolwin [15:00] */ 7434 #define XGXSBLK1_LINK_ACOLWIN_MASK 0xffff 7435 #define XGXSBLK1_LINK_ACOLWIN_ALIGN 0 7436 #define XGXSBLK1_LINK_ACOLWIN_BITS 16 7437 #define XGXSBLK1_LINK_ACOLWIN_SHIFT 0 7438 7439 7440 /**************************************************************************** 7441 * XgxsBlk1 :: testRx 7442 */ 7443 /* XgxsBlk1 :: testRx :: reserved0 [15:08] */ 7444 #define XGXSBLK1_TESTRX_RESERVED0_MASK 0xff00 7445 #define XGXSBLK1_TESTRX_RESERVED0_ALIGN 0 7446 #define XGXSBLK1_TESTRX_RESERVED0_BITS 8 7447 #define XGXSBLK1_TESTRX_RESERVED0_SHIFT 8 7448 7449 /* XgxsBlk1 :: testRx :: rx_inBandMdio_Qfltr_en [07:07] */ 7450 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_MASK 0x0080 7451 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_ALIGN 0 7452 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_BITS 1 7453 #define XGXSBLK1_TESTRX_RX_INBANDMDIO_QFLTR_EN_SHIFT 7 7454 7455 /* XgxsBlk1 :: testRx :: link_force [06:06] */ 7456 #define XGXSBLK1_TESTRX_LINK_FORCE_MASK 0x0040 7457 #define XGXSBLK1_TESTRX_LINK_FORCE_ALIGN 0 7458 #define XGXSBLK1_TESTRX_LINK_FORCE_BITS 1 7459 #define XGXSBLK1_TESTRX_LINK_FORCE_SHIFT 6 7460 7461 /* XgxsBlk1 :: testRx :: rxtm_modsel [05:03] */ 7462 #define XGXSBLK1_TESTRX_RXTM_MODSEL_MASK 0x0038 7463 #define XGXSBLK1_TESTRX_RXTM_MODSEL_ALIGN 0 7464 #define XGXSBLK1_TESTRX_RXTM_MODSEL_BITS 3 7465 #define XGXSBLK1_TESTRX_RXTM_MODSEL_SHIFT 3 7466 7467 /* XgxsBlk1 :: testRx :: rxtm_tstsel [02:00] */ 7468 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_MASK 0x0007 7469 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_ALIGN 0 7470 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_BITS 3 7471 #define XGXSBLK1_TESTRX_RXTM_TSTSEL_SHIFT 0 7472 7473 7474 /**************************************************************************** 7475 * XgxsBlk1 :: testTx 7476 */ 7477 /* XgxsBlk1 :: testTx :: reserved0 [15:08] */ 7478 #define XGXSBLK1_TESTTX_RESERVED0_MASK 0xff00 7479 #define XGXSBLK1_TESTTX_RESERVED0_ALIGN 0 7480 #define XGXSBLK1_TESTTX_RESERVED0_BITS 8 7481 #define XGXSBLK1_TESTTX_RESERVED0_SHIFT 8 7482 7483 /* XgxsBlk1 :: testTx :: rx_ck4x1muxsel [07:06] */ 7484 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_MASK 0x00c0 7485 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_ALIGN 0 7486 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_BITS 2 7487 #define XGXSBLK1_TESTTX_RX_CK4X1MUXSEL_SHIFT 6 7488 7489 /* XgxsBlk1 :: testTx :: txtm_modsel [05:03] */ 7490 #define XGXSBLK1_TESTTX_TXTM_MODSEL_MASK 0x0038 7491 #define XGXSBLK1_TESTTX_TXTM_MODSEL_ALIGN 0 7492 #define XGXSBLK1_TESTTX_TXTM_MODSEL_BITS 3 7493 #define XGXSBLK1_TESTTX_TXTM_MODSEL_SHIFT 3 7494 7495 /* XgxsBlk1 :: testTx :: txtm_tstsel [02:00] */ 7496 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_MASK 0x0007 7497 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_ALIGN 0 7498 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_BITS 3 7499 #define XGXSBLK1_TESTTX_TXTM_TSTSEL_SHIFT 0 7500 7501 7502 /**************************************************************************** 7503 * XgxsBlk1 :: testXg 7504 */ 7505 /* XgxsBlk1 :: testXg :: evnt_cntr_sel [15:15] */ 7506 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_MASK 0x8000 7507 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_ALIGN 0 7508 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_BITS 1 7509 #define XGXSBLK1_TESTXG_EVNT_CNTR_SEL_SHIFT 15 7510 7511 /* XgxsBlk1 :: testXg :: txdt_sel [14:14] */ 7512 #define XGXSBLK1_TESTXG_TXDT_SEL_MASK 0x4000 7513 #define XGXSBLK1_TESTXG_TXDT_SEL_ALIGN 0 7514 #define XGXSBLK1_TESTXG_TXDT_SEL_BITS 1 7515 #define XGXSBLK1_TESTXG_TXDT_SEL_SHIFT 14 7516 7517 /* XgxsBlk1 :: testXg :: slice_sel [13:12] */ 7518 #define XGXSBLK1_TESTXG_SLICE_SEL_MASK 0x3000 7519 #define XGXSBLK1_TESTXG_SLICE_SEL_ALIGN 0 7520 #define XGXSBLK1_TESTXG_SLICE_SEL_BITS 2 7521 #define XGXSBLK1_TESTXG_SLICE_SEL_SHIFT 12 7522 7523 /* XgxsBlk1 :: testXg :: reserved0 [11:08] */ 7524 #define XGXSBLK1_TESTXG_RESERVED0_MASK 0x0f00 7525 #define XGXSBLK1_TESTXG_RESERVED0_ALIGN 0 7526 #define XGXSBLK1_TESTXG_RESERVED0_BITS 4 7527 #define XGXSBLK1_TESTXG_RESERVED0_SHIFT 8 7528 7529 /* XgxsBlk1 :: testXg :: test_reg_sel [07:07] */ 7530 #define XGXSBLK1_TESTXG_TEST_REG_SEL_MASK 0x0080 7531 #define XGXSBLK1_TESTXG_TEST_REG_SEL_ALIGN 0 7532 #define XGXSBLK1_TESTXG_TEST_REG_SEL_BITS 1 7533 #define XGXSBLK1_TESTXG_TEST_REG_SEL_SHIFT 7 7534 7535 /* XgxsBlk1 :: testXg :: xg_txtstsel [06:04] */ 7536 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_MASK 0x0070 7537 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_ALIGN 0 7538 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_BITS 3 7539 #define XGXSBLK1_TESTXG_XG_TXTSTSEL_SHIFT 4 7540 7541 /* XgxsBlk1 :: testXg :: xg_rxtstsel [03:00] */ 7542 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_MASK 0x000f 7543 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_ALIGN 0 7544 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_BITS 4 7545 #define XGXSBLK1_TESTXG_XG_RXTSTSEL_SHIFT 0 7546 7547 7548 /**************************************************************************** 7549 * XgxsBlk1 :: laneCtrl0 7550 */ 7551 /* XgxsBlk1 :: laneCtrl0 :: ed66en [15:12] */ 7552 #define XGXSBLK1_LANECTRL0_ED66EN_MASK 0xf000 7553 #define XGXSBLK1_LANECTRL0_ED66EN_ALIGN 0 7554 #define XGXSBLK1_LANECTRL0_ED66EN_BITS 4 7555 #define XGXSBLK1_LANECTRL0_ED66EN_SHIFT 12 7556 7557 /* XgxsBlk1 :: laneCtrl0 :: reserved0 [11:08] */ 7558 #define XGXSBLK1_LANECTRL0_RESERVED0_MASK 0x0f00 7559 #define XGXSBLK1_LANECTRL0_RESERVED0_ALIGN 0 7560 #define XGXSBLK1_LANECTRL0_RESERVED0_BITS 4 7561 #define XGXSBLK1_LANECTRL0_RESERVED0_SHIFT 8 7562 7563 /* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_rx [07:04] */ 7564 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_MASK 0x00f0 7565 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_ALIGN 0 7566 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_BITS 4 7567 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_RX_SHIFT 4 7568 7569 /* XgxsBlk1 :: laneCtrl0 :: cl36_pcs_en_tx [03:00] */ 7570 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_MASK 0x000f 7571 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_ALIGN 0 7572 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_BITS 4 7573 #define XGXSBLK1_LANECTRL0_CL36_PCS_EN_TX_SHIFT 0 7574 7575 7576 /**************************************************************************** 7577 * XgxsBlk1 :: laneCtrl1 7578 */ 7579 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln3 [15:14] */ 7580 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_MASK 0xc000 7581 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_ALIGN 0 7582 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_BITS 2 7583 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SHIFT 14 7584 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div2 0 7585 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div1 1 7586 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div2 2 7587 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div1 3 7588 7589 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln2 [13:12] */ 7590 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_MASK 0x3000 7591 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_ALIGN 0 7592 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_BITS 2 7593 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SHIFT 12 7594 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div2 0 7595 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div1 1 7596 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div2 2 7597 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div1 3 7598 7599 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln1 [11:10] */ 7600 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_MASK 0x0c00 7601 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_ALIGN 0 7602 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_BITS 2 7603 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SHIFT 10 7604 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div2 0 7605 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div1 1 7606 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div2 2 7607 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div1 3 7608 7609 /* XgxsBlk1 :: laneCtrl1 :: rx1g_mode_ln0 [09:08] */ 7610 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_MASK 0x0300 7611 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_ALIGN 0 7612 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_BITS 2 7613 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SHIFT 8 7614 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div2 0 7615 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div1 1 7616 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div2 2 7617 #define XGXSBLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div1 3 7618 7619 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln3 [07:06] */ 7620 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_MASK 0x00c0 7621 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_ALIGN 0 7622 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_BITS 2 7623 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SHIFT 6 7624 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div2 0 7625 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div1 1 7626 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div2 2 7627 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div1 3 7628 7629 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln2 [05:04] */ 7630 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_MASK 0x0030 7631 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_ALIGN 0 7632 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_BITS 2 7633 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SHIFT 4 7634 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div2 0 7635 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div1 1 7636 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div2 2 7637 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div1 3 7638 7639 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln1 [03:02] */ 7640 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_MASK 0x000c 7641 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_ALIGN 0 7642 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_BITS 2 7643 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SHIFT 2 7644 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div2 0 7645 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div1 1 7646 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div2 2 7647 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div1 3 7648 7649 /* XgxsBlk1 :: laneCtrl1 :: tx1g_mode_ln0 [01:00] */ 7650 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_MASK 0x0003 7651 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_ALIGN 0 7652 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_BITS 2 7653 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SHIFT 0 7654 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div2 0 7655 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div1 1 7656 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div2 2 7657 #define XGXSBLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div1 3 7658 7659 7660 /**************************************************************************** 7661 * XgxsBlk1 :: laneCtrl2 7662 */ 7663 /* XgxsBlk1 :: laneCtrl2 :: cdet_en1g [15:12] */ 7664 #define XGXSBLK1_LANECTRL2_CDET_EN1G_MASK 0xf000 7665 #define XGXSBLK1_LANECTRL2_CDET_EN1G_ALIGN 0 7666 #define XGXSBLK1_LANECTRL2_CDET_EN1G_BITS 4 7667 #define XGXSBLK1_LANECTRL2_CDET_EN1G_SHIFT 12 7668 7669 /* XgxsBlk1 :: laneCtrl2 :: eden1g [11:08] */ 7670 #define XGXSBLK1_LANECTRL2_EDEN1G_MASK 0x0f00 7671 #define XGXSBLK1_LANECTRL2_EDEN1G_ALIGN 0 7672 #define XGXSBLK1_LANECTRL2_EDEN1G_BITS 4 7673 #define XGXSBLK1_LANECTRL2_EDEN1G_SHIFT 8 7674 7675 /* XgxsBlk1 :: laneCtrl2 :: rloop1g [07:04] */ 7676 #define XGXSBLK1_LANECTRL2_RLOOP1G_MASK 0x00f0 7677 #define XGXSBLK1_LANECTRL2_RLOOP1G_ALIGN 0 7678 #define XGXSBLK1_LANECTRL2_RLOOP1G_BITS 4 7679 #define XGXSBLK1_LANECTRL2_RLOOP1G_SHIFT 4 7680 7681 /* XgxsBlk1 :: laneCtrl2 :: gloop1g [03:00] */ 7682 #define XGXSBLK1_LANECTRL2_GLOOP1G_MASK 0x000f 7683 #define XGXSBLK1_LANECTRL2_GLOOP1G_ALIGN 0 7684 #define XGXSBLK1_LANECTRL2_GLOOP1G_BITS 4 7685 #define XGXSBLK1_LANECTRL2_GLOOP1G_SHIFT 0 7686 7687 7688 /**************************************************************************** 7689 * XgxsBlk1 :: laneCtrl3 7690 */ 7691 /* XgxsBlk1 :: laneCtrl3 :: lock_ref [15:12] */ 7692 #define XGXSBLK1_LANECTRL3_LOCK_REF_MASK 0xf000 7693 #define XGXSBLK1_LANECTRL3_LOCK_REF_ALIGN 0 7694 #define XGXSBLK1_LANECTRL3_LOCK_REF_BITS 4 7695 #define XGXSBLK1_LANECTRL3_LOCK_REF_SHIFT 12 7696 7697 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn_force [11:11] */ 7698 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_MASK 0x0800 7699 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_ALIGN 0 7700 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_BITS 1 7701 #define XGXSBLK1_LANECTRL3_PWRDWN_FORCE_SHIFT 11 7702 7703 /* XgxsBlk1 :: laneCtrl3 :: lock_ref_en [10:10] */ 7704 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_MASK 0x0400 7705 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_ALIGN 0 7706 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_BITS 1 7707 #define XGXSBLK1_LANECTRL3_LOCK_REF_EN_SHIFT 10 7708 7709 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn10g_pll_dis [09:09] */ 7710 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_MASK 0x0200 7711 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_ALIGN 0 7712 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_BITS 1 7713 #define XGXSBLK1_LANECTRL3_PWRDWN10G_PLL_DIS_SHIFT 9 7714 7715 /* XgxsBlk1 :: laneCtrl3 :: pwrdwn_pll [08:08] */ 7716 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_MASK 0x0100 7717 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_ALIGN 0 7718 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_BITS 1 7719 #define XGXSBLK1_LANECTRL3_PWRDWN_PLL_SHIFT 8 7720 7721 /* XgxsBlk1 :: laneCtrl3 :: pwrdn_tx [07:04] */ 7722 #define XGXSBLK1_LANECTRL3_PWRDN_TX_MASK 0x00f0 7723 #define XGXSBLK1_LANECTRL3_PWRDN_TX_ALIGN 0 7724 #define XGXSBLK1_LANECTRL3_PWRDN_TX_BITS 4 7725 #define XGXSBLK1_LANECTRL3_PWRDN_TX_SHIFT 4 7726 7727 /* XgxsBlk1 :: laneCtrl3 :: pwrdn_rx [03:00] */ 7728 #define XGXSBLK1_LANECTRL3_PWRDN_RX_MASK 0x000f 7729 #define XGXSBLK1_LANECTRL3_PWRDN_RX_ALIGN 0 7730 #define XGXSBLK1_LANECTRL3_PWRDN_RX_BITS 4 7731 #define XGXSBLK1_LANECTRL3_PWRDN_RX_SHIFT 0 7732 7733 7734 /**************************************************************************** 7735 * XgxsBlk1 :: lanePrbs 7736 */ 7737 /* XgxsBlk1 :: lanePrbs :: prbs_en3 [15:15] */ 7738 #define XGXSBLK1_LANEPRBS_PRBS_EN3_MASK 0x8000 7739 #define XGXSBLK1_LANEPRBS_PRBS_EN3_ALIGN 0 7740 #define XGXSBLK1_LANEPRBS_PRBS_EN3_BITS 1 7741 #define XGXSBLK1_LANEPRBS_PRBS_EN3_SHIFT 15 7742 7743 /* XgxsBlk1 :: lanePrbs :: prbs_inv3 [14:14] */ 7744 #define XGXSBLK1_LANEPRBS_PRBS_INV3_MASK 0x4000 7745 #define XGXSBLK1_LANEPRBS_PRBS_INV3_ALIGN 0 7746 #define XGXSBLK1_LANEPRBS_PRBS_INV3_BITS 1 7747 #define XGXSBLK1_LANEPRBS_PRBS_INV3_SHIFT 14 7748 7749 /* XgxsBlk1 :: lanePrbs :: prbs_order3 [13:12] */ 7750 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_MASK 0x3000 7751 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_ALIGN 0 7752 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_BITS 2 7753 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_SHIFT 12 7754 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs7 0 7755 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs15 1 7756 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs23 2 7757 #define XGXSBLK1_LANEPRBS_PRBS_ORDER3_prbs31 3 7758 7759 /* XgxsBlk1 :: lanePrbs :: prbs_en2 [11:11] */ 7760 #define XGXSBLK1_LANEPRBS_PRBS_EN2_MASK 0x0800 7761 #define XGXSBLK1_LANEPRBS_PRBS_EN2_ALIGN 0 7762 #define XGXSBLK1_LANEPRBS_PRBS_EN2_BITS 1 7763 #define XGXSBLK1_LANEPRBS_PRBS_EN2_SHIFT 11 7764 7765 /* XgxsBlk1 :: lanePrbs :: prbs_inv2 [10:10] */ 7766 #define XGXSBLK1_LANEPRBS_PRBS_INV2_MASK 0x0400 7767 #define XGXSBLK1_LANEPRBS_PRBS_INV2_ALIGN 0 7768 #define XGXSBLK1_LANEPRBS_PRBS_INV2_BITS 1 7769 #define XGXSBLK1_LANEPRBS_PRBS_INV2_SHIFT 10 7770 7771 /* XgxsBlk1 :: lanePrbs :: prbs_order2 [09:08] */ 7772 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_MASK 0x0300 7773 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_ALIGN 0 7774 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_BITS 2 7775 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_SHIFT 8 7776 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs7 0 7777 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs15 1 7778 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs23 2 7779 #define XGXSBLK1_LANEPRBS_PRBS_ORDER2_prbs31 3 7780 7781 /* XgxsBlk1 :: lanePrbs :: prbs_en1 [07:07] */ 7782 #define XGXSBLK1_LANEPRBS_PRBS_EN1_MASK 0x0080 7783 #define XGXSBLK1_LANEPRBS_PRBS_EN1_ALIGN 0 7784 #define XGXSBLK1_LANEPRBS_PRBS_EN1_BITS 1 7785 #define XGXSBLK1_LANEPRBS_PRBS_EN1_SHIFT 7 7786 7787 /* XgxsBlk1 :: lanePrbs :: prbs_inv1 [06:06] */ 7788 #define XGXSBLK1_LANEPRBS_PRBS_INV1_MASK 0x0040 7789 #define XGXSBLK1_LANEPRBS_PRBS_INV1_ALIGN 0 7790 #define XGXSBLK1_LANEPRBS_PRBS_INV1_BITS 1 7791 #define XGXSBLK1_LANEPRBS_PRBS_INV1_SHIFT 6 7792 7793 /* XgxsBlk1 :: lanePrbs :: prbs_order1 [05:04] */ 7794 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_MASK 0x0030 7795 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_ALIGN 0 7796 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_BITS 2 7797 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_SHIFT 4 7798 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs7 0 7799 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs15 1 7800 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs23 2 7801 #define XGXSBLK1_LANEPRBS_PRBS_ORDER1_prbs31 3 7802 7803 /* XgxsBlk1 :: lanePrbs :: prbs_en0 [03:03] */ 7804 #define XGXSBLK1_LANEPRBS_PRBS_EN0_MASK 0x0008 7805 #define XGXSBLK1_LANEPRBS_PRBS_EN0_ALIGN 0 7806 #define XGXSBLK1_LANEPRBS_PRBS_EN0_BITS 1 7807 #define XGXSBLK1_LANEPRBS_PRBS_EN0_SHIFT 3 7808 7809 /* XgxsBlk1 :: lanePrbs :: prbs_inv0 [02:02] */ 7810 #define XGXSBLK1_LANEPRBS_PRBS_INV0_MASK 0x0004 7811 #define XGXSBLK1_LANEPRBS_PRBS_INV0_ALIGN 0 7812 #define XGXSBLK1_LANEPRBS_PRBS_INV0_BITS 1 7813 #define XGXSBLK1_LANEPRBS_PRBS_INV0_SHIFT 2 7814 7815 /* XgxsBlk1 :: lanePrbs :: prbs_order0 [01:00] */ 7816 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_MASK 0x0003 7817 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_ALIGN 0 7818 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_BITS 2 7819 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_SHIFT 0 7820 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs7 0 7821 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs15 1 7822 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs23 2 7823 #define XGXSBLK1_LANEPRBS_PRBS_ORDER0_prbs31 3 7824 7825 7826 /**************************************************************************** 7827 * XgxsBlk1 :: laneTest 7828 */ 7829 /* XgxsBlk1 :: laneTest :: tmux_sel [15:12] */ 7830 #define XGXSBLK1_LANETEST_TMUX_SEL_MASK 0xf000 7831 #define XGXSBLK1_LANETEST_TMUX_SEL_ALIGN 0 7832 #define XGXSBLK1_LANETEST_TMUX_SEL_BITS 4 7833 #define XGXSBLK1_LANETEST_TMUX_SEL_SHIFT 12 7834 #define XGXSBLK1_LANETEST_TMUX_SEL_off 0 7835 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln0 1 7836 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln1 2 7837 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln2 3 7838 #define XGXSBLK1_LANETEST_TMUX_SEL_rx_ln3 4 7839 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln0 5 7840 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln1 6 7841 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln2 7 7842 #define XGXSBLK1_LANETEST_TMUX_SEL_tx_ln3 8 7843 #define XGXSBLK1_LANETEST_TMUX_SEL_pll 11 7844 #define XGXSBLK1_LANETEST_TMUX_SEL_mdio 12 7845 #define XGXSBLK1_LANETEST_TMUX_SEL_tMux1G 15 7846 7847 /* XgxsBlk1 :: laneTest :: inBandMdioRxRstEn [11:11] */ 7848 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_MASK 0x0800 7849 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_ALIGN 0 7850 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_BITS 1 7851 #define XGXSBLK1_LANETEST_INBANDMDIORXRSTEN_SHIFT 11 7852 7853 /* XgxsBlk1 :: laneTest :: pwrdn_ext_dis [10:10] */ 7854 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_MASK 0x0400 7855 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_ALIGN 0 7856 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_BITS 1 7857 #define XGXSBLK1_LANETEST_PWRDN_EXT_DIS_SHIFT 10 7858 7859 /* XgxsBlk1 :: laneTest :: pwrdn_safe_dis [09:09] */ 7860 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_MASK 0x0200 7861 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_ALIGN 0 7862 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_BITS 1 7863 #define XGXSBLK1_LANETEST_PWRDN_SAFE_DIS_SHIFT 9 7864 7865 /* XgxsBlk1 :: laneTest :: pwrdwn_clks_en [08:08] */ 7866 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_MASK 0x0100 7867 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN 0 7868 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_BITS 1 7869 #define XGXSBLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT 8 7870 7871 /* XgxsBlk1 :: laneTest :: rxSeqStart_ext_dis [07:07] */ 7872 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_MASK 0x0080 7873 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_ALIGN 0 7874 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_BITS 1 7875 #define XGXSBLK1_LANETEST_RXSEQSTART_EXT_DIS_SHIFT 7 7876 7877 /* XgxsBlk1 :: laneTest :: pll_lock_rstb_r [06:06] */ 7878 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_MASK 0x0040 7879 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_ALIGN 0 7880 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_BITS 1 7881 #define XGXSBLK1_LANETEST_PLL_LOCK_RSTB_R_SHIFT 6 7882 7883 /* XgxsBlk1 :: laneTest :: lfck_bypass [05:05] */ 7884 #define XGXSBLK1_LANETEST_LFCK_BYPASS_MASK 0x0020 7885 #define XGXSBLK1_LANETEST_LFCK_BYPASS_ALIGN 0 7886 #define XGXSBLK1_LANETEST_LFCK_BYPASS_BITS 1 7887 #define XGXSBLK1_LANETEST_LFCK_BYPASS_SHIFT 5 7888 7889 /* XgxsBlk1 :: laneTest :: rx_snoop_en [04:04] */ 7890 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_MASK 0x0010 7891 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_ALIGN 0 7892 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_BITS 1 7893 #define XGXSBLK1_LANETEST_RX_SNOOP_EN_SHIFT 4 7894 7895 /* XgxsBlk1 :: laneTest :: mode_10g_snoop [03:00] */ 7896 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_MASK 0x000f 7897 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ALIGN 0 7898 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_BITS 4 7899 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_SHIFT 0 7900 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS 0 7901 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXG_nCC 1 7902 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_IndLane_OS5 5 7903 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_Indlanes 6 7904 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PCI 7 7905 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS_nLQ 8 7906 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_XGXS_nLQnCC 9 7907 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PBypass 10 7908 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_PBypass_nDSK 11 7909 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_ComboCoreMode 12 7910 #define XGXSBLK1_LANETEST_MODE_10G_SNOOP_Clocks_off 15 7911 7912 7913 /**************************************************************************** 7914 * XgxsBlk1 :: lssRevnt 7915 */ 7916 /* union - case txActive [15:00] */ 7917 /* XgxsBlk1 :: lssRevnt :: txActive [15:00] */ 7918 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_MASK 0xffff 7919 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_ALIGN 0 7920 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_BITS 16 7921 #define XGXSBLK1_LSSREVNT_TXACTIVE_TXACTIVE_SHIFT 0 7922 7923 7924 /* union - case lssRevent [15:00] */ 7925 /* XgxsBlk1 :: lssRevnt :: lss_Revent [15:00] */ 7926 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_MASK 0xffff 7927 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_ALIGN 0 7928 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_BITS 16 7929 #define XGXSBLK1_LSSREVNT_LSSREVENT_LSS_REVENT_SHIFT 0 7930 7931 7932 7933 /**************************************************************************** 7934 * XgxsBlk1 :: dskevnt 7935 */ 7936 /* union - case rxActive [15:00] */ 7937 /* XgxsBlk1 :: dskevnt :: rxActive [15:00] */ 7938 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_MASK 0xffff 7939 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_ALIGN 0 7940 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_BITS 16 7941 #define XGXSBLK1_DSKEVNT_RXACTIVE_RXACTIVE_SHIFT 0 7942 7943 7944 /* union - case deskwevent [15:00] */ 7945 /* XgxsBlk1 :: dskevnt :: deskewEvent [15:00] */ 7946 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_MASK 0xffff 7947 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_ALIGN 0 7948 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_BITS 16 7949 #define XGXSBLK1_DSKEVNT_DESKWEVENT_DESKEWEVENT_SHIFT 0 7950 7951 7952 7953 /**************************************************************************** 7954 * XgxsBlk1 :: Aerrevnt 7955 */ 7956 /* XgxsBlk1 :: Aerrevnt :: Aerrevnt [15:00] */ 7957 #define XGXSBLK1_AERREVNT_AERREVNT_MASK 0xffff 7958 #define XGXSBLK1_AERREVNT_AERREVNT_ALIGN 0 7959 #define XGXSBLK1_AERREVNT_AERREVNT_BITS 16 7960 #define XGXSBLK1_AERREVNT_AERREVNT_SHIFT 0 7961 7962 7963 /**************************************************************************** 7964 * XgxsBlk1 :: ckcmpevnt 7965 */ 7966 /* XgxsBlk1 :: ckcmpevnt :: ckcmpevnt [15:00] */ 7967 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_MASK 0xffff 7968 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_ALIGN 0 7969 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_BITS 16 7970 #define XGXSBLK1_CKCMPEVNT_CKCMPEVNT_SHIFT 0 7971 7972 7973 /**************************************************************************** 7974 * Hypercore_USER_TxBert 7975 */ 7976 /**************************************************************************** 7977 * TxBert :: txBertCtrl 7978 */ 7979 /* TxBert :: txBertCtrl :: pkt_en [15:15] */ 7980 #define TXBERT_TXBERTCTRL_PKT_EN_MASK 0x8000 7981 #define TXBERT_TXBERTCTRL_PKT_EN_ALIGN 0 7982 #define TXBERT_TXBERTCTRL_PKT_EN_BITS 1 7983 #define TXBERT_TXBERTCTRL_PKT_EN_SHIFT 15 7984 7985 /* TxBert :: txBertCtrl :: seed_ld [14:14] */ 7986 #define TXBERT_TXBERTCTRL_SEED_LD_MASK 0x4000 7987 #define TXBERT_TXBERTCTRL_SEED_LD_ALIGN 0 7988 #define TXBERT_TXBERTCTRL_SEED_LD_BITS 1 7989 #define TXBERT_TXBERTCTRL_SEED_LD_SHIFT 14 7990 7991 /* TxBert :: txBertCtrl :: prbs_order [13:12] */ 7992 #define TXBERT_TXBERTCTRL_PRBS_ORDER_MASK 0x3000 7993 #define TXBERT_TXBERTCTRL_PRBS_ORDER_ALIGN 0 7994 #define TXBERT_TXBERTCTRL_PRBS_ORDER_BITS 2 7995 #define TXBERT_TXBERTCTRL_PRBS_ORDER_SHIFT 12 7996 7997 /* TxBert :: txBertCtrl :: ramp_en [11:11] */ 7998 #define TXBERT_TXBERTCTRL_RAMP_EN_MASK 0x0800 7999 #define TXBERT_TXBERTCTRL_RAMP_EN_ALIGN 0 8000 #define TXBERT_TXBERTCTRL_RAMP_EN_BITS 1 8001 #define TXBERT_TXBERTCTRL_RAMP_EN_SHIFT 11 8002 8003 /* TxBert :: txBertCtrl :: rndm_en [10:10] */ 8004 #define TXBERT_TXBERTCTRL_RNDM_EN_MASK 0x0400 8005 #define TXBERT_TXBERTCTRL_RNDM_EN_ALIGN 0 8006 #define TXBERT_TXBERTCTRL_RNDM_EN_BITS 1 8007 #define TXBERT_TXBERTCTRL_RNDM_EN_SHIFT 10 8008 8009 /* TxBert :: txBertCtrl :: Q_en [09:09] */ 8010 #define TXBERT_TXBERTCTRL_Q_EN_MASK 0x0200 8011 #define TXBERT_TXBERTCTRL_Q_EN_ALIGN 0 8012 #define TXBERT_TXBERTCTRL_Q_EN_BITS 1 8013 #define TXBERT_TXBERTCTRL_Q_EN_SHIFT 9 8014 8015 /* TxBert :: txBertCtrl :: Q_link_en [08:08] */ 8016 #define TXBERT_TXBERTCTRL_Q_LINK_EN_MASK 0x0100 8017 #define TXBERT_TXBERTCTRL_Q_LINK_EN_ALIGN 0 8018 #define TXBERT_TXBERTCTRL_Q_LINK_EN_BITS 1 8019 #define TXBERT_TXBERTCTRL_Q_LINK_EN_SHIFT 8 8020 8021 /* TxBert :: txBertCtrl :: skew_en [07:07] */ 8022 #define TXBERT_TXBERTCTRL_SKEW_EN_MASK 0x0080 8023 #define TXBERT_TXBERTCTRL_SKEW_EN_ALIGN 0 8024 #define TXBERT_TXBERTCTRL_SKEW_EN_BITS 1 8025 #define TXBERT_TXBERTCTRL_SKEW_EN_SHIFT 7 8026 8027 /* TxBert :: txBertCtrl :: cjpat_en [06:06] */ 8028 #define TXBERT_TXBERTCTRL_CJPAT_EN_MASK 0x0040 8029 #define TXBERT_TXBERTCTRL_CJPAT_EN_ALIGN 0 8030 #define TXBERT_TXBERTCTRL_CJPAT_EN_BITS 1 8031 #define TXBERT_TXBERTCTRL_CJPAT_EN_SHIFT 6 8032 8033 /* TxBert :: txBertCtrl :: crpat_en [05:05] */ 8034 #define TXBERT_TXBERTCTRL_CRPAT_EN_MASK 0x0020 8035 #define TXBERT_TXBERTCTRL_CRPAT_EN_ALIGN 0 8036 #define TXBERT_TXBERTCTRL_CRPAT_EN_BITS 1 8037 #define TXBERT_TXBERTCTRL_CRPAT_EN_SHIFT 5 8038 8039 /* TxBert :: txBertCtrl :: cjrmp_en [04:04] */ 8040 #define TXBERT_TXBERTCTRL_CJRMP_EN_MASK 0x0010 8041 #define TXBERT_TXBERTCTRL_CJRMP_EN_ALIGN 0 8042 #define TXBERT_TXBERTCTRL_CJRMP_EN_BITS 1 8043 #define TXBERT_TXBERTCTRL_CJRMP_EN_SHIFT 4 8044 8045 /* TxBert :: txBertCtrl :: txck_out_force [03:03] */ 8046 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_MASK 0x0008 8047 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_ALIGN 0 8048 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_BITS 1 8049 #define TXBERT_TXBERTCTRL_TXCK_OUT_FORCE_SHIFT 3 8050 8051 /* TxBert :: txBertCtrl :: fifo_rst [02:02] */ 8052 #define TXBERT_TXBERTCTRL_FIFO_RST_MASK 0x0004 8053 #define TXBERT_TXBERTCTRL_FIFO_RST_ALIGN 0 8054 #define TXBERT_TXBERTCTRL_FIFO_RST_BITS 1 8055 #define TXBERT_TXBERTCTRL_FIFO_RST_SHIFT 2 8056 8057 /* TxBert :: txBertCtrl :: countRst_dis [01:01] */ 8058 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_MASK 0x0002 8059 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_ALIGN 0 8060 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_BITS 1 8061 #define TXBERT_TXBERTCTRL_COUNTRST_DIS_SHIFT 1 8062 8063 /* TxBert :: txBertCtrl :: count_clr [00:00] */ 8064 #define TXBERT_TXBERTCTRL_COUNT_CLR_MASK 0x0001 8065 #define TXBERT_TXBERTCTRL_COUNT_CLR_ALIGN 0 8066 #define TXBERT_TXBERTCTRL_COUNT_CLR_BITS 1 8067 #define TXBERT_TXBERTCTRL_COUNT_CLR_SHIFT 0 8068 8069 8070 /**************************************************************************** 8071 * TxBert :: txBertSopEop 8072 */ 8073 /* TxBert :: txBertSopEop :: SOP [15:08] */ 8074 #define TXBERT_TXBERTSOPEOP_SOP_MASK 0xff00 8075 #define TXBERT_TXBERTSOPEOP_SOP_ALIGN 0 8076 #define TXBERT_TXBERTSOPEOP_SOP_BITS 8 8077 #define TXBERT_TXBERTSOPEOP_SOP_SHIFT 8 8078 8079 /* TxBert :: txBertSopEop :: EOP [07:00] */ 8080 #define TXBERT_TXBERTSOPEOP_EOP_MASK 0x00ff 8081 #define TXBERT_TXBERTSOPEOP_EOP_ALIGN 0 8082 #define TXBERT_TXBERTSOPEOP_EOP_BITS 8 8083 #define TXBERT_TXBERTSOPEOP_EOP_SHIFT 0 8084 8085 8086 /**************************************************************************** 8087 * TxBert :: txBertSize0 8088 */ 8089 /* TxBert :: txBertSize0 :: ipg_size [15:10] */ 8090 #define TXBERT_TXBERTSIZE0_IPG_SIZE_MASK 0xfc00 8091 #define TXBERT_TXBERTSIZE0_IPG_SIZE_ALIGN 0 8092 #define TXBERT_TXBERTSIZE0_IPG_SIZE_BITS 6 8093 #define TXBERT_TXBERTSIZE0_IPG_SIZE_SHIFT 10 8094 8095 /* TxBert :: txBertSize0 :: pkt_size [09:00] */ 8096 #define TXBERT_TXBERTSIZE0_PKT_SIZE_MASK 0x03ff 8097 #define TXBERT_TXBERTSIZE0_PKT_SIZE_ALIGN 0 8098 #define TXBERT_TXBERTSIZE0_PKT_SIZE_BITS 10 8099 #define TXBERT_TXBERTSIZE0_PKT_SIZE_SHIFT 0 8100 8101 8102 /**************************************************************************** 8103 * TxBert :: txBertSize1 8104 */ 8105 /* TxBert :: txBertSize1 :: awin_size [15:10] */ 8106 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_MASK 0xfc00 8107 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_ALIGN 0 8108 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_BITS 6 8109 #define TXBERT_TXBERTSIZE1_AWIN_SIZE_SHIFT 10 8110 8111 /* TxBert :: txBertSize1 :: PktStpCnt [09:00] */ 8112 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_MASK 0x03ff 8113 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_ALIGN 0 8114 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_BITS 10 8115 #define TXBERT_TXBERTSIZE1_PKTSTPCNT_SHIFT 0 8116 8117 8118 /**************************************************************************** 8119 * TxBert :: txBertSize2 8120 */ 8121 /* TxBert :: txBertSize2 :: skew3 [15:12] */ 8122 #define TXBERT_TXBERTSIZE2_SKEW3_MASK 0xf000 8123 #define TXBERT_TXBERTSIZE2_SKEW3_ALIGN 0 8124 #define TXBERT_TXBERTSIZE2_SKEW3_BITS 4 8125 #define TXBERT_TXBERTSIZE2_SKEW3_SHIFT 12 8126 8127 /* TxBert :: txBertSize2 :: skew2 [11:08] */ 8128 #define TXBERT_TXBERTSIZE2_SKEW2_MASK 0x0f00 8129 #define TXBERT_TXBERTSIZE2_SKEW2_ALIGN 0 8130 #define TXBERT_TXBERTSIZE2_SKEW2_BITS 4 8131 #define TXBERT_TXBERTSIZE2_SKEW2_SHIFT 8 8132 8133 /* TxBert :: txBertSize2 :: skew1 [07:04] */ 8134 #define TXBERT_TXBERTSIZE2_SKEW1_MASK 0x00f0 8135 #define TXBERT_TXBERTSIZE2_SKEW1_ALIGN 0 8136 #define TXBERT_TXBERTSIZE2_SKEW1_BITS 4 8137 #define TXBERT_TXBERTSIZE2_SKEW1_SHIFT 4 8138 8139 /* TxBert :: txBertSize2 :: skew0 [03:00] */ 8140 #define TXBERT_TXBERTSIZE2_SKEW0_MASK 0x000f 8141 #define TXBERT_TXBERTSIZE2_SKEW0_ALIGN 0 8142 #define TXBERT_TXBERTSIZE2_SKEW0_BITS 4 8143 #define TXBERT_TXBERTSIZE2_SKEW0_SHIFT 0 8144 8145 8146 /**************************************************************************** 8147 * TxBert :: txBertIpg0 8148 */ 8149 /* TxBert :: txBertIpg0 :: ipg1 [15:08] */ 8150 #define TXBERT_TXBERTIPG0_IPG1_MASK 0xff00 8151 #define TXBERT_TXBERTIPG0_IPG1_ALIGN 0 8152 #define TXBERT_TXBERTIPG0_IPG1_BITS 8 8153 #define TXBERT_TXBERTIPG0_IPG1_SHIFT 8 8154 8155 /* TxBert :: txBertIpg0 :: ipg0 [07:00] */ 8156 #define TXBERT_TXBERTIPG0_IPG0_MASK 0x00ff 8157 #define TXBERT_TXBERTIPG0_IPG0_ALIGN 0 8158 #define TXBERT_TXBERTIPG0_IPG0_BITS 8 8159 #define TXBERT_TXBERTIPG0_IPG0_SHIFT 0 8160 8161 8162 /**************************************************************************** 8163 * TxBert :: txBertIpg1 8164 */ 8165 /* TxBert :: txBertIpg1 :: ipg3 [15:08] */ 8166 #define TXBERT_TXBERTIPG1_IPG3_MASK 0xff00 8167 #define TXBERT_TXBERTIPG1_IPG3_ALIGN 0 8168 #define TXBERT_TXBERTIPG1_IPG3_BITS 8 8169 #define TXBERT_TXBERTIPG1_IPG3_SHIFT 8 8170 8171 /* TxBert :: txBertIpg1 :: ipg2 [07:00] */ 8172 #define TXBERT_TXBERTIPG1_IPG2_MASK 0x00ff 8173 #define TXBERT_TXBERTIPG1_IPG2_ALIGN 0 8174 #define TXBERT_TXBERTIPG1_IPG2_BITS 8 8175 #define TXBERT_TXBERTIPG1_IPG2_SHIFT 0 8176 8177 8178 /**************************************************************************** 8179 * TxBert :: txBertByteU 8180 */ 8181 /* TxBert :: txBertByteU :: byte_count_high [15:00] */ 8182 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_MASK 0xffff 8183 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN 0 8184 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_BITS 16 8185 #define TXBERT_TXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT 0 8186 8187 8188 /**************************************************************************** 8189 * TxBert :: txBertByteL 8190 */ 8191 /* TxBert :: txBertByteL :: byte_count_low [15:00] */ 8192 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_MASK 0xffff 8193 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_ALIGN 0 8194 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_BITS 16 8195 #define TXBERT_TXBERTBYTEL_BYTE_COUNT_LOW_SHIFT 0 8196 8197 8198 /**************************************************************************** 8199 * TxBert :: txBertPacketU 8200 */ 8201 /* TxBert :: txBertPacketU :: pkt_count_high [15:00] */ 8202 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_MASK 0xffff 8203 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_ALIGN 0 8204 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_BITS 16 8205 #define TXBERT_TXBERTPACKETU_PKT_COUNT_HIGH_SHIFT 0 8206 8207 8208 /**************************************************************************** 8209 * TxBert :: txBertPacketL 8210 */ 8211 /* TxBert :: txBertPacketL :: pkt_count_low [15:00] */ 8212 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_MASK 0xffff 8213 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_ALIGN 0 8214 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_BITS 16 8215 #define TXBERT_TXBERTPACKETL_PKT_COUNT_LOW_SHIFT 0 8216 8217 8218 /**************************************************************************** 8219 * Hypercore_USER_RxBert 8220 */ 8221 /**************************************************************************** 8222 * RxBert :: rxBertCtrl 8223 */ 8224 /* RxBert :: rxBertCtrl :: pkt_en [15:15] */ 8225 #define RXBERT_RXBERTCTRL_PKT_EN_MASK 0x8000 8226 #define RXBERT_RXBERTCTRL_PKT_EN_ALIGN 0 8227 #define RXBERT_RXBERTCTRL_PKT_EN_BITS 1 8228 #define RXBERT_RXBERTCTRL_PKT_EN_SHIFT 15 8229 8230 /* RxBert :: rxBertCtrl :: seed_ld [14:14] */ 8231 #define RXBERT_RXBERTCTRL_SEED_LD_MASK 0x4000 8232 #define RXBERT_RXBERTCTRL_SEED_LD_ALIGN 0 8233 #define RXBERT_RXBERTCTRL_SEED_LD_BITS 1 8234 #define RXBERT_RXBERTCTRL_SEED_LD_SHIFT 14 8235 8236 /* RxBert :: rxBertCtrl :: prbs_order [13:12] */ 8237 #define RXBERT_RXBERTCTRL_PRBS_ORDER_MASK 0x3000 8238 #define RXBERT_RXBERTCTRL_PRBS_ORDER_ALIGN 0 8239 #define RXBERT_RXBERTCTRL_PRBS_ORDER_BITS 2 8240 #define RXBERT_RXBERTCTRL_PRBS_ORDER_SHIFT 12 8241 8242 /* RxBert :: rxBertCtrl :: ramp_en [11:11] */ 8243 #define RXBERT_RXBERTCTRL_RAMP_EN_MASK 0x0800 8244 #define RXBERT_RXBERTCTRL_RAMP_EN_ALIGN 0 8245 #define RXBERT_RXBERTCTRL_RAMP_EN_BITS 1 8246 #define RXBERT_RXBERTCTRL_RAMP_EN_SHIFT 11 8247 8248 /* RxBert :: rxBertCtrl :: cgbad_tst_en [10:10] */ 8249 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_MASK 0x0400 8250 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_ALIGN 0 8251 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_BITS 1 8252 #define RXBERT_RXBERTCTRL_CGBAD_TST_EN_SHIFT 10 8253 8254 /* RxBert :: rxBertCtrl :: crcChk_en [09:09] */ 8255 #define RXBERT_RXBERTCTRL_CRCCHK_EN_MASK 0x0200 8256 #define RXBERT_RXBERTCTRL_CRCCHK_EN_ALIGN 0 8257 #define RXBERT_RXBERTCTRL_CRCCHK_EN_BITS 1 8258 #define RXBERT_RXBERTCTRL_CRCCHK_EN_SHIFT 9 8259 8260 /* RxBert :: rxBertCtrl :: countRst_dis [08:08] */ 8261 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_MASK 0x0100 8262 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_ALIGN 0 8263 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_BITS 1 8264 #define RXBERT_RXBERTCTRL_COUNTRST_DIS_SHIFT 8 8265 8266 /* RxBert :: rxBertCtrl :: rxStatSel [07:07] */ 8267 #define RXBERT_RXBERTCTRL_RXSTATSEL_MASK 0x0080 8268 #define RXBERT_RXBERTCTRL_RXSTATSEL_ALIGN 0 8269 #define RXBERT_RXBERTCTRL_RXSTATSEL_BITS 1 8270 #define RXBERT_RXBERTCTRL_RXSTATSEL_SHIFT 7 8271 8272 /* RxBert :: rxBertCtrl :: source_sel_r [06:06] */ 8273 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_MASK 0x0040 8274 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_ALIGN 0 8275 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_BITS 1 8276 #define RXBERT_RXBERTCTRL_SOURCE_SEL_R_SHIFT 6 8277 8278 /* RxBert :: rxBertCtrl :: source_sel [05:04] */ 8279 #define RXBERT_RXBERTCTRL_SOURCE_SEL_MASK 0x0030 8280 #define RXBERT_RXBERTCTRL_SOURCE_SEL_ALIGN 0 8281 #define RXBERT_RXBERTCTRL_SOURCE_SEL_BITS 2 8282 #define RXBERT_RXBERTCTRL_SOURCE_SEL_SHIFT 4 8283 8284 /* RxBert :: rxBertCtrl :: slice_sel [03:02] */ 8285 #define RXBERT_RXBERTCTRL_SLICE_SEL_MASK 0x000c 8286 #define RXBERT_RXBERTCTRL_SLICE_SEL_ALIGN 0 8287 #define RXBERT_RXBERTCTRL_SLICE_SEL_BITS 2 8288 #define RXBERT_RXBERTCTRL_SLICE_SEL_SHIFT 2 8289 8290 /* RxBert :: rxBertCtrl :: err_clr [01:01] */ 8291 #define RXBERT_RXBERTCTRL_ERR_CLR_MASK 0x0002 8292 #define RXBERT_RXBERTCTRL_ERR_CLR_ALIGN 0 8293 #define RXBERT_RXBERTCTRL_ERR_CLR_BITS 1 8294 #define RXBERT_RXBERTCTRL_ERR_CLR_SHIFT 1 8295 8296 /* RxBert :: rxBertCtrl :: count_clr [00:00] */ 8297 #define RXBERT_RXBERTCTRL_COUNT_CLR_MASK 0x0001 8298 #define RXBERT_RXBERTCTRL_COUNT_CLR_ALIGN 0 8299 #define RXBERT_RXBERTCTRL_COUNT_CLR_BITS 1 8300 #define RXBERT_RXBERTCTRL_COUNT_CLR_SHIFT 0 8301 8302 8303 /**************************************************************************** 8304 * RxBert :: rxBertSopEop 8305 */ 8306 /* RxBert :: rxBertSopEop :: SOP [15:08] */ 8307 #define RXBERT_RXBERTSOPEOP_SOP_MASK 0xff00 8308 #define RXBERT_RXBERTSOPEOP_SOP_ALIGN 0 8309 #define RXBERT_RXBERTSOPEOP_SOP_BITS 8 8310 #define RXBERT_RXBERTSOPEOP_SOP_SHIFT 8 8311 8312 /* RxBert :: rxBertSopEop :: EOP [07:00] */ 8313 #define RXBERT_RXBERTSOPEOP_EOP_MASK 0x00ff 8314 #define RXBERT_RXBERTSOPEOP_EOP_ALIGN 0 8315 #define RXBERT_RXBERTSOPEOP_EOP_BITS 8 8316 #define RXBERT_RXBERTSOPEOP_EOP_SHIFT 0 8317 8318 8319 /**************************************************************************** 8320 * RxBert :: rxBertByteU 8321 */ 8322 /* RxBert :: rxBertByteU :: byte_count_high [15:00] */ 8323 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_MASK 0xffff 8324 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_ALIGN 0 8325 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_BITS 16 8326 #define RXBERT_RXBERTBYTEU_BYTE_COUNT_HIGH_SHIFT 0 8327 8328 8329 /**************************************************************************** 8330 * RxBert :: rxBertByteL 8331 */ 8332 /* RxBert :: rxBertByteL :: byte_count_low [15:00] */ 8333 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_MASK 0xffff 8334 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_ALIGN 0 8335 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_BITS 16 8336 #define RXBERT_RXBERTBYTEL_BYTE_COUNT_LOW_SHIFT 0 8337 8338 8339 /**************************************************************************** 8340 * RxBert :: rxBertPacketU 8341 */ 8342 /* RxBert :: rxBertPacketU :: pkt_count_high [15:00] */ 8343 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_MASK 0xffff 8344 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_ALIGN 0 8345 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_BITS 16 8346 #define RXBERT_RXBERTPACKETU_PKT_COUNT_HIGH_SHIFT 0 8347 8348 8349 /**************************************************************************** 8350 * RxBert :: rxBertPacketL 8351 */ 8352 /* RxBert :: rxBertPacketL :: pkt_count_low [15:00] */ 8353 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_MASK 0xffff 8354 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_ALIGN 0 8355 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_BITS 16 8356 #define RXBERT_RXBERTPACKETL_PKT_COUNT_LOW_SHIFT 0 8357 8358 8359 /**************************************************************************** 8360 * RxBert :: rxBertBitErr 8361 */ 8362 /* RxBert :: rxBertBitErr :: bit_err_count [15:00] */ 8363 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_MASK 0xffff 8364 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_ALIGN 0 8365 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_BITS 16 8366 #define RXBERT_RXBERTBITERR_BIT_ERR_COUNT_SHIFT 0 8367 8368 8369 /**************************************************************************** 8370 * RxBert :: rxBertByteErr 8371 */ 8372 /* RxBert :: rxBertByteErr :: byte_err_count [15:00] */ 8373 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_MASK 0xffff 8374 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_ALIGN 0 8375 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_BITS 16 8376 #define RXBERT_RXBERTBYTEERR_BYTE_ERR_COUNT_SHIFT 0 8377 8378 8379 /**************************************************************************** 8380 * RxBert :: rxBertPktErr 8381 */ 8382 /* RxBert :: rxBertPktErr :: pkt_err_count [15:00] */ 8383 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_MASK 0xffff 8384 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_ALIGN 0 8385 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_BITS 16 8386 #define RXBERT_RXBERTPKTERR_PKT_ERR_COUNT_SHIFT 0 8387 8388 8389 /**************************************************************************** 8390 * RxBert :: rxBertStatus 8391 */ 8392 /* union - case rxStatSel [15:00] */ 8393 /* RxBert :: rxBertStatus :: reserved0 [15:08] */ 8394 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_MASK 0xff00 8395 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_ALIGN 0 8396 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_BITS 8 8397 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RESERVED0_SHIFT 8 8398 8399 /* RxBert :: rxBertStatus :: rx_10g_tmux [07:00] */ 8400 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_MASK 0x00ff 8401 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_ALIGN 0 8402 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_BITS 8 8403 #define RXBERT_RXBERTSTATUS_RXSTATSEL_RX_10G_TMUX_SHIFT 0 8404 8405 8406 /* union - case crcChk_en [15:00] */ 8407 /* RxBert :: rxBertStatus :: link [15:15] */ 8408 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_MASK 0x8000 8409 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_ALIGN 0 8410 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_BITS 1 8411 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_LINK_SHIFT 15 8412 8413 /* RxBert :: rxBertStatus :: prbs_stky [14:14] */ 8414 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_MASK 0x4000 8415 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_ALIGN 0 8416 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_BITS 1 8417 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_PRBS_STKY_SHIFT 14 8418 8419 /* RxBert :: rxBertStatus :: reserved0 [13:00] */ 8420 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_MASK 0x3fff 8421 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_ALIGN 0 8422 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_BITS 14 8423 #define RXBERT_RXBERTSTATUS_CRCCHK_EN_RESERVED0_SHIFT 0 8424 8425 8426 /* union - case rxBert [15:00] */ 8427 /* RxBert :: rxBertStatus :: prbs_lock [15:15] */ 8428 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_MASK 0x8000 8429 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_ALIGN 0 8430 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_BITS 1 8431 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_LOCK_SHIFT 15 8432 8433 /* RxBert :: rxBertStatus :: prbs_stky [14:14] */ 8434 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_MASK 0x4000 8435 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_ALIGN 0 8436 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_BITS 1 8437 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STKY_SHIFT 14 8438 8439 /* RxBert :: rxBertStatus :: prbs_state [13:11] */ 8440 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_MASK 0x3800 8441 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_ALIGN 0 8442 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_BITS 3 8443 #define RXBERT_RXBERTSTATUS_RXBERT_PRBS_STATE_SHIFT 11 8444 8445 /* RxBert :: rxBertStatus :: reserved0 [10:07] */ 8446 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_MASK 0x0780 8447 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_ALIGN 0 8448 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_BITS 4 8449 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED0_SHIFT 7 8450 8451 /* RxBert :: rxBertStatus :: bit_err_overflow [06:06] */ 8452 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_MASK 0x0040 8453 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_ALIGN 0 8454 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_BITS 1 8455 #define RXBERT_RXBERTSTATUS_RXBERT_BIT_ERR_OVERFLOW_SHIFT 6 8456 8457 /* RxBert :: rxBertStatus :: reserved1 [05:04] */ 8458 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_MASK 0x0030 8459 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_ALIGN 0 8460 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_BITS 2 8461 #define RXBERT_RXBERTSTATUS_RXBERT_RESERVED1_SHIFT 4 8462 8463 /* RxBert :: rxBertStatus :: onefe_det [03:03] */ 8464 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_MASK 0x0008 8465 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_ALIGN 0 8466 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_BITS 1 8467 #define RXBERT_RXBERTSTATUS_RXBERT_ONEFE_DET_SHIFT 3 8468 8469 /* RxBert :: rxBertStatus :: xor_comp [02:00] */ 8470 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_MASK 0x0007 8471 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_ALIGN 0 8472 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_BITS 3 8473 #define RXBERT_RXBERTSTATUS_RXBERT_XOR_COMP_SHIFT 0 8474 8475 8476 8477 /**************************************************************************** 8478 * Hypercore_USER_TxPll 8479 */ 8480 /**************************************************************************** 8481 * TxPll :: anaPllStatus 8482 */ 8483 /* TxPll :: anaPllStatus :: pllSeqDone [15:15] */ 8484 #define TXPLL_ANAPLLSTATUS_PLLSEQDONE_MASK 0x8000 8485 #define TXPLL_ANAPLLSTATUS_PLLSEQDONE_ALIGN 0 8486 #define TXPLL_ANAPLLSTATUS_PLLSEQDONE_BITS 1 8487 #define TXPLL_ANAPLLSTATUS_PLLSEQDONE_SHIFT 15 8488 8489 /* TxPll :: anaPllStatus :: freqDone [14:14] */ 8490 #define TXPLL_ANAPLLSTATUS_FREQDONE_MASK 0x4000 8491 #define TXPLL_ANAPLLSTATUS_FREQDONE_ALIGN 0 8492 #define TXPLL_ANAPLLSTATUS_FREQDONE_BITS 1 8493 #define TXPLL_ANAPLLSTATUS_FREQDONE_SHIFT 14 8494 8495 /* TxPll :: anaPllStatus :: vcoDone [13:13] */ 8496 #define TXPLL_ANAPLLSTATUS_VCODONE_MASK 0x2000 8497 #define TXPLL_ANAPLLSTATUS_VCODONE_ALIGN 0 8498 #define TXPLL_ANAPLLSTATUS_VCODONE_BITS 1 8499 #define TXPLL_ANAPLLSTATUS_VCODONE_SHIFT 13 8500 8501 /* TxPll :: anaPllStatus :: reserved0 [12:12] */ 8502 #define TXPLL_ANAPLLSTATUS_RESERVED0_MASK 0x1000 8503 #define TXPLL_ANAPLLSTATUS_RESERVED0_ALIGN 0 8504 #define TXPLL_ANAPLLSTATUS_RESERVED0_BITS 1 8505 #define TXPLL_ANAPLLSTATUS_RESERVED0_SHIFT 12 8506 8507 /* TxPll :: anaPllStatus :: pllSeqPass [11:11] */ 8508 #define TXPLL_ANAPLLSTATUS_PLLSEQPASS_MASK 0x0800 8509 #define TXPLL_ANAPLLSTATUS_PLLSEQPASS_ALIGN 0 8510 #define TXPLL_ANAPLLSTATUS_PLLSEQPASS_BITS 1 8511 #define TXPLL_ANAPLLSTATUS_PLLSEQPASS_SHIFT 11 8512 8513 /* TxPll :: anaPllStatus :: freqPass [10:10] */ 8514 #define TXPLL_ANAPLLSTATUS_FREQPASS_MASK 0x0400 8515 #define TXPLL_ANAPLLSTATUS_FREQPASS_ALIGN 0 8516 #define TXPLL_ANAPLLSTATUS_FREQPASS_BITS 1 8517 #define TXPLL_ANAPLLSTATUS_FREQPASS_SHIFT 10 8518 8519 /* TxPll :: anaPllStatus :: vcoPass [09:09] */ 8520 #define TXPLL_ANAPLLSTATUS_VCOPASS_MASK 0x0200 8521 #define TXPLL_ANAPLLSTATUS_VCOPASS_ALIGN 0 8522 #define TXPLL_ANAPLLSTATUS_VCOPASS_BITS 1 8523 #define TXPLL_ANAPLLSTATUS_VCOPASS_SHIFT 9 8524 8525 /* TxPll :: anaPllStatus :: reserved1 [08:08] */ 8526 #define TXPLL_ANAPLLSTATUS_RESERVED1_MASK 0x0100 8527 #define TXPLL_ANAPLLSTATUS_RESERVED1_ALIGN 0 8528 #define TXPLL_ANAPLLSTATUS_RESERVED1_BITS 1 8529 #define TXPLL_ANAPLLSTATUS_RESERVED1_SHIFT 8 8530 8531 /* TxPll :: anaPllStatus :: slowdn [07:07] */ 8532 #define TXPLL_ANAPLLSTATUS_SLOWDN_MASK 0x0080 8533 #define TXPLL_ANAPLLSTATUS_SLOWDN_ALIGN 0 8534 #define TXPLL_ANAPLLSTATUS_SLOWDN_BITS 1 8535 #define TXPLL_ANAPLLSTATUS_SLOWDN_SHIFT 7 8536 8537 /* TxPll :: anaPllStatus :: lostPllLock_SM [06:06] */ 8538 #define TXPLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_MASK 0x0040 8539 #define TXPLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_ALIGN 0 8540 #define TXPLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_BITS 1 8541 #define TXPLL_ANAPLLSTATUS_LOSTPLLLOCK_SM_SHIFT 6 8542 8543 /* TxPll :: anaPllStatus :: reserved2 [05:04] */ 8544 #define TXPLL_ANAPLLSTATUS_RESERVED2_MASK 0x0030 8545 #define TXPLL_ANAPLLSTATUS_RESERVED2_ALIGN 0 8546 #define TXPLL_ANAPLLSTATUS_RESERVED2_BITS 2 8547 #define TXPLL_ANAPLLSTATUS_RESERVED2_SHIFT 4 8548 8549 /* TxPll :: anaPllStatus :: pll_mode_afe [03:00] */ 8550 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_MASK 0x000f 8551 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_ALIGN 0 8552 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_BITS 4 8553 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_SHIFT 0 8554 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div16 0 8555 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div20 1 8556 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div24 2 8557 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div26 3 8558 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div30 4 8559 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div32 5 8560 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div36 6 8561 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div40 7 8562 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div42 8 8563 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div48 9 8564 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div50 10 8565 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div52 11 8566 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div60 12 8567 #define TXPLL_ANAPLLSTATUS_PLL_MODE_AFE_div64 13 8568 8569 8570 /**************************************************************************** 8571 * TxPll :: anaPllControl 8572 */ 8573 /* TxPll :: anaPllControl :: pllRestart [15:15] */ 8574 #define TXPLL_ANAPLLCONTROL_PLLRESTART_MASK 0x8000 8575 #define TXPLL_ANAPLLCONTROL_PLLRESTART_ALIGN 0 8576 #define TXPLL_ANAPLLCONTROL_PLLRESTART_BITS 1 8577 #define TXPLL_ANAPLLCONTROL_PLLRESTART_SHIFT 15 8578 8579 /* TxPll :: anaPllControl :: FreqDetRetry_en [14:14] */ 8580 #define TXPLL_ANAPLLCONTROL_FREQDETRETRY_EN_MASK 0x4000 8581 #define TXPLL_ANAPLLCONTROL_FREQDETRETRY_EN_ALIGN 0 8582 #define TXPLL_ANAPLLCONTROL_FREQDETRETRY_EN_BITS 1 8583 #define TXPLL_ANAPLLCONTROL_FREQDETRETRY_EN_SHIFT 14 8584 8585 /* TxPll :: anaPllControl :: FreqDetRestart_en [13:13] */ 8586 #define TXPLL_ANAPLLCONTROL_FREQDETRESTART_EN_MASK 0x2000 8587 #define TXPLL_ANAPLLCONTROL_FREQDETRESTART_EN_ALIGN 0 8588 #define TXPLL_ANAPLLCONTROL_FREQDETRESTART_EN_BITS 1 8589 #define TXPLL_ANAPLLCONTROL_FREQDETRESTART_EN_SHIFT 13 8590 8591 /* TxPll :: anaPllControl :: FreqMonitor_en [12:12] */ 8592 #define TXPLL_ANAPLLCONTROL_FREQMONITOR_EN_MASK 0x1000 8593 #define TXPLL_ANAPLLCONTROL_FREQMONITOR_EN_ALIGN 0 8594 #define TXPLL_ANAPLLCONTROL_FREQMONITOR_EN_BITS 1 8595 #define TXPLL_ANAPLLCONTROL_FREQMONITOR_EN_SHIFT 12 8596 8597 /* TxPll :: anaPllControl :: VcopRetry_en [11:11] */ 8598 #define TXPLL_ANAPLLCONTROL_VCOPRETRY_EN_MASK 0x0800 8599 #define TXPLL_ANAPLLCONTROL_VCOPRETRY_EN_ALIGN 0 8600 #define TXPLL_ANAPLLCONTROL_VCOPRETRY_EN_BITS 1 8601 #define TXPLL_ANAPLLCONTROL_VCOPRETRY_EN_SHIFT 11 8602 8603 /* TxPll :: anaPllControl :: VcoDone_en [10:10] */ 8604 #define TXPLL_ANAPLLCONTROL_VCODONE_EN_MASK 0x0400 8605 #define TXPLL_ANAPLLCONTROL_VCODONE_EN_ALIGN 0 8606 #define TXPLL_ANAPLLCONTROL_VCODONE_EN_BITS 1 8607 #define TXPLL_ANAPLLCONTROL_VCODONE_EN_SHIFT 10 8608 8609 /* TxPll :: anaPllControl :: LinkRestart_en [09:09] */ 8610 #define TXPLL_ANAPLLCONTROL_LINKRESTART_EN_MASK 0x0200 8611 #define TXPLL_ANAPLLCONTROL_LINKRESTART_EN_ALIGN 0 8612 #define TXPLL_ANAPLLCONTROL_LINKRESTART_EN_BITS 1 8613 #define TXPLL_ANAPLLCONTROL_LINKRESTART_EN_SHIFT 9 8614 8615 /* TxPll :: anaPllControl :: ByteSyncRestart_en [08:08] */ 8616 #define TXPLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_MASK 0x0100 8617 #define TXPLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_ALIGN 0 8618 #define TXPLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_BITS 1 8619 #define TXPLL_ANAPLLCONTROL_BYTESYNCRESTART_EN_SHIFT 8 8620 8621 /* TxPll :: anaPllControl :: PllForceDone_en [07:07] */ 8622 #define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_EN_MASK 0x0080 8623 #define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_EN_ALIGN 0 8624 #define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_EN_BITS 1 8625 #define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_EN_SHIFT 7 8626 8627 /* TxPll :: anaPllControl :: PllForceDone [06:06] */ 8628 #define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_MASK 0x0040 8629 #define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_ALIGN 0 8630 #define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_BITS 1 8631 #define TXPLL_ANAPLLCONTROL_PLLFORCEDONE_SHIFT 6 8632 8633 /* TxPll :: anaPllControl :: PllForcePass [05:05] */ 8634 #define TXPLL_ANAPLLCONTROL_PLLFORCEPASS_MASK 0x0020 8635 #define TXPLL_ANAPLLCONTROL_PLLFORCEPASS_ALIGN 0 8636 #define TXPLL_ANAPLLCONTROL_PLLFORCEPASS_BITS 1 8637 #define TXPLL_ANAPLLCONTROL_PLLFORCEPASS_SHIFT 5 8638 8639 /* TxPll :: anaPllControl :: PllForceVcoDone_en [04:04] */ 8640 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_MASK 0x0010 8641 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_ALIGN 0 8642 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_BITS 1 8643 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_EN_SHIFT 4 8644 8645 /* TxPll :: anaPllControl :: PllForceVcoDone [03:03] */ 8646 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_MASK 0x0008 8647 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_ALIGN 0 8648 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_BITS 1 8649 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCODONE_SHIFT 3 8650 8651 /* TxPll :: anaPllControl :: PllForceVcoPass_en [02:02] */ 8652 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_MASK 0x0004 8653 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_ALIGN 0 8654 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_BITS 1 8655 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_EN_SHIFT 2 8656 8657 /* TxPll :: anaPllControl :: PllForceVcoPass [01:01] */ 8658 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_MASK 0x0002 8659 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_ALIGN 0 8660 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_BITS 1 8661 #define TXPLL_ANAPLLCONTROL_PLLFORCEVCOPASS_SHIFT 1 8662 8663 /* TxPll :: anaPllControl :: PllForcePllLock [00:00] */ 8664 #define TXPLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_MASK 0x0001 8665 #define TXPLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_ALIGN 0 8666 #define TXPLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_BITS 1 8667 #define TXPLL_ANAPLLCONTROL_PLLFORCEPLLLOCK_SHIFT 0 8668 8669 8670 /**************************************************************************** 8671 * TxPll :: anaPllTimer1 8672 */ 8673 /* TxPll :: anaPllTimer1 :: VcoStepTime [15:08] */ 8674 #define TXPLL_ANAPLLTIMER1_VCOSTEPTIME_MASK 0xff00 8675 #define TXPLL_ANAPLLTIMER1_VCOSTEPTIME_ALIGN 0 8676 #define TXPLL_ANAPLLTIMER1_VCOSTEPTIME_BITS 8 8677 #define TXPLL_ANAPLLTIMER1_VCOSTEPTIME_SHIFT 8 8678 8679 /* TxPll :: anaPllTimer1 :: VcoStartTime [07:00] */ 8680 #define TXPLL_ANAPLLTIMER1_VCOSTARTTIME_MASK 0x00ff 8681 #define TXPLL_ANAPLLTIMER1_VCOSTARTTIME_ALIGN 0 8682 #define TXPLL_ANAPLLTIMER1_VCOSTARTTIME_BITS 8 8683 #define TXPLL_ANAPLLTIMER1_VCOSTARTTIME_SHIFT 0 8684 8685 8686 /**************************************************************************** 8687 * TxPll :: anaPllTimer2 8688 */ 8689 /* TxPll :: anaPllTimer2 :: reserved0 [15:15] */ 8690 #define TXPLL_ANAPLLTIMER2_RESERVED0_MASK 0x8000 8691 #define TXPLL_ANAPLLTIMER2_RESERVED0_ALIGN 0 8692 #define TXPLL_ANAPLLTIMER2_RESERVED0_BITS 1 8693 #define TXPLL_ANAPLLTIMER2_RESERVED0_SHIFT 15 8694 8695 /* TxPll :: anaPllTimer2 :: lfckSingleStep_en [14:14] */ 8696 #define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_MASK 0x4000 8697 #define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_ALIGN 0 8698 #define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_BITS 1 8699 #define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_EN_SHIFT 14 8700 8701 /* TxPll :: anaPllTimer2 :: lfckSingleStep [13:13] */ 8702 #define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_MASK 0x2000 8703 #define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_ALIGN 0 8704 #define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_BITS 1 8705 #define TXPLL_ANAPLLTIMER2_LFCKSINGLESTEP_SHIFT 13 8706 8707 /* TxPll :: anaPllTimer2 :: testMuxSel [12:08] */ 8708 #define TXPLL_ANAPLLTIMER2_TESTMUXSEL_MASK 0x1f00 8709 #define TXPLL_ANAPLLTIMER2_TESTMUXSEL_ALIGN 0 8710 #define TXPLL_ANAPLLTIMER2_TESTMUXSEL_BITS 5 8711 #define TXPLL_ANAPLLTIMER2_TESTMUXSEL_SHIFT 8 8712 8713 /* TxPll :: anaPllTimer2 :: retryTime [07:00] */ 8714 #define TXPLL_ANAPLLTIMER2_RETRYTIME_MASK 0x00ff 8715 #define TXPLL_ANAPLLTIMER2_RETRYTIME_ALIGN 0 8716 #define TXPLL_ANAPLLTIMER2_RETRYTIME_BITS 8 8717 #define TXPLL_ANAPLLTIMER2_RETRYTIME_SHIFT 0 8718 8719 8720 /**************************************************************************** 8721 * TxPll :: anaPllTimer3 8722 */ 8723 /* TxPll :: anaPllTimer3 :: reserved0 [15:08] */ 8724 #define TXPLL_ANAPLLTIMER3_RESERVED0_MASK 0xff00 8725 #define TXPLL_ANAPLLTIMER3_RESERVED0_ALIGN 0 8726 #define TXPLL_ANAPLLTIMER3_RESERVED0_BITS 8 8727 #define TXPLL_ANAPLLTIMER3_RESERVED0_SHIFT 8 8728 8729 /* TxPll :: anaPllTimer3 :: freqDetTime [07:00] */ 8730 #define TXPLL_ANAPLLTIMER3_FREQDETTIME_MASK 0x00ff 8731 #define TXPLL_ANAPLLTIMER3_FREQDETTIME_ALIGN 0 8732 #define TXPLL_ANAPLLTIMER3_FREQDETTIME_BITS 8 8733 #define TXPLL_ANAPLLTIMER3_FREQDETTIME_SHIFT 0 8734 8735 8736 /**************************************************************************** 8737 * TxPll :: anaCapControl 8738 */ 8739 /* TxPll :: anaCapControl :: StatusControl [15:15] */ 8740 #define TXPLL_ANACAPCONTROL_STATUSCONTROL_MASK 0x8000 8741 #define TXPLL_ANACAPCONTROL_STATUSCONTROL_ALIGN 0 8742 #define TXPLL_ANACAPCONTROL_STATUSCONTROL_BITS 1 8743 #define TXPLL_ANACAPCONTROL_STATUSCONTROL_SHIFT 15 8744 8745 /* TxPll :: anaCapControl :: vcoRestart [14:14] */ 8746 #define TXPLL_ANACAPCONTROL_VCORESTART_MASK 0x4000 8747 #define TXPLL_ANACAPCONTROL_VCORESTART_ALIGN 0 8748 #define TXPLL_ANACAPCONTROL_VCORESTART_BITS 1 8749 #define TXPLL_ANACAPCONTROL_VCORESTART_SHIFT 14 8750 8751 /* TxPll :: anaCapControl :: vcoForceRange_en [13:13] */ 8752 #define TXPLL_ANACAPCONTROL_VCOFORCERANGE_EN_MASK 0x2000 8753 #define TXPLL_ANACAPCONTROL_VCOFORCERANGE_EN_ALIGN 0 8754 #define TXPLL_ANACAPCONTROL_VCOFORCERANGE_EN_BITS 1 8755 #define TXPLL_ANACAPCONTROL_VCOFORCERANGE_EN_SHIFT 13 8756 8757 /* TxPll :: anaCapControl :: vcoForceSlowdn_en [12:12] */ 8758 #define TXPLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_MASK 0x1000 8759 #define TXPLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_ALIGN 0 8760 #define TXPLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_BITS 1 8761 #define TXPLL_ANACAPCONTROL_VCOFORCESLOWDN_EN_SHIFT 12 8762 8763 /* TxPll :: anaCapControl :: reserved0 [11:10] */ 8764 #define TXPLL_ANACAPCONTROL_RESERVED0_MASK 0x0c00 8765 #define TXPLL_ANACAPCONTROL_RESERVED0_ALIGN 0 8766 #define TXPLL_ANACAPCONTROL_RESERVED0_BITS 2 8767 #define TXPLL_ANACAPCONTROL_RESERVED0_SHIFT 10 8768 8769 /* TxPll :: anaCapControl :: slowdn_xor [09:09] */ 8770 #define TXPLL_ANACAPCONTROL_SLOWDN_XOR_MASK 0x0200 8771 #define TXPLL_ANACAPCONTROL_SLOWDN_XOR_ALIGN 0 8772 #define TXPLL_ANACAPCONTROL_SLOWDN_XOR_BITS 1 8773 #define TXPLL_ANACAPCONTROL_SLOWDN_XOR_SHIFT 9 8774 8775 /* union - case Status [08:00] */ 8776 /* TxPll :: anaCapControl :: Slowdn [08:08] */ 8777 #define TXPLL_ANACAPCONTROL_STATUS_SLOWDN_MASK 0x0100 8778 #define TXPLL_ANACAPCONTROL_STATUS_SLOWDN_ALIGN 0 8779 #define TXPLL_ANACAPCONTROL_STATUS_SLOWDN_BITS 1 8780 #define TXPLL_ANACAPCONTROL_STATUS_SLOWDN_SHIFT 8 8781 8782 /* TxPll :: anaCapControl :: reserved0 [07:07] */ 8783 #define TXPLL_ANACAPCONTROL_STATUS_RESERVED0_MASK 0x0080 8784 #define TXPLL_ANACAPCONTROL_STATUS_RESERVED0_ALIGN 0 8785 #define TXPLL_ANACAPCONTROL_STATUS_RESERVED0_BITS 1 8786 #define TXPLL_ANACAPCONTROL_STATUS_RESERVED0_SHIFT 7 8787 8788 /* TxPll :: anaCapControl :: vcoRange [06:00] */ 8789 #define TXPLL_ANACAPCONTROL_STATUS_VCORANGE_MASK 0x007f 8790 #define TXPLL_ANACAPCONTROL_STATUS_VCORANGE_ALIGN 0 8791 #define TXPLL_ANACAPCONTROL_STATUS_VCORANGE_BITS 7 8792 #define TXPLL_ANACAPCONTROL_STATUS_VCORANGE_SHIFT 0 8793 8794 8795 /* union - case Control [08:00] */ 8796 /* TxPll :: anaCapControl :: vcoForceSlowdn [08:08] */ 8797 #define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCESLOWDN_MASK 0x0100 8798 #define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCESLOWDN_ALIGN 0 8799 #define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCESLOWDN_BITS 1 8800 #define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCESLOWDN_SHIFT 8 8801 8802 /* TxPll :: anaCapControl :: reserved0 [07:07] */ 8803 #define TXPLL_ANACAPCONTROL_CONTROL_RESERVED0_MASK 0x0080 8804 #define TXPLL_ANACAPCONTROL_CONTROL_RESERVED0_ALIGN 0 8805 #define TXPLL_ANACAPCONTROL_CONTROL_RESERVED0_BITS 1 8806 #define TXPLL_ANACAPCONTROL_CONTROL_RESERVED0_SHIFT 7 8807 8808 /* TxPll :: anaCapControl :: vcoForceRange [06:00] */ 8809 #define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCERANGE_MASK 0x007f 8810 #define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCERANGE_ALIGN 0 8811 #define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCERANGE_BITS 7 8812 #define TXPLL_ANACAPCONTROL_CONTROL_VCOFORCERANGE_SHIFT 0 8813 8814 8815 8816 /**************************************************************************** 8817 * TxPll :: anaFreqDetCntr 8818 */ 8819 /* TxPll :: anaFreqDetCntr :: resolution [15:08] */ 8820 #define TXPLL_ANAFREQDETCNTR_RESOLUTION_MASK 0xff00 8821 #define TXPLL_ANAFREQDETCNTR_RESOLUTION_ALIGN 0 8822 #define TXPLL_ANAFREQDETCNTR_RESOLUTION_BITS 8 8823 #define TXPLL_ANAFREQDETCNTR_RESOLUTION_SHIFT 8 8824 8825 /* TxPll :: anaFreqDetCntr :: window [07:00] */ 8826 #define TXPLL_ANAFREQDETCNTR_WINDOW_MASK 0x00ff 8827 #define TXPLL_ANAFREQDETCNTR_WINDOW_ALIGN 0 8828 #define TXPLL_ANAFREQDETCNTR_WINDOW_BITS 8 8829 #define TXPLL_ANAFREQDETCNTR_WINDOW_SHIFT 0 8830 8831 8832 /**************************************************************************** 8833 * TxPll :: anaPllAStatus1 8834 */ 8835 /* TxPll :: anaPllAStatus1 :: reserved0 [15:14] */ 8836 #define TXPLL_ANAPLLASTATUS1_RESERVED0_MASK 0xc000 8837 #define TXPLL_ANAPLLASTATUS1_RESERVED0_ALIGN 0 8838 #define TXPLL_ANAPLLASTATUS1_RESERVED0_BITS 2 8839 #define TXPLL_ANAPLLASTATUS1_RESERVED0_SHIFT 14 8840 8841 /* TxPll :: anaPllAStatus1 :: kvh [13:12] */ 8842 #define TXPLL_ANAPLLASTATUS1_KVH_MASK 0x3000 8843 #define TXPLL_ANAPLLASTATUS1_KVH_ALIGN 0 8844 #define TXPLL_ANAPLLASTATUS1_KVH_BITS 2 8845 #define TXPLL_ANAPLLASTATUS1_KVH_SHIFT 12 8846 8847 /* TxPll :: anaPllAStatus1 :: pll_range [11:08] */ 8848 #define TXPLL_ANAPLLASTATUS1_PLL_RANGE_MASK 0x0f00 8849 #define TXPLL_ANAPLLASTATUS1_PLL_RANGE_ALIGN 0 8850 #define TXPLL_ANAPLLASTATUS1_PLL_RANGE_BITS 4 8851 #define TXPLL_ANAPLLASTATUS1_PLL_RANGE_SHIFT 8 8852 8853 /* TxPll :: anaPllAStatus1 :: pll_low [07:07] */ 8854 #define TXPLL_ANAPLLASTATUS1_PLL_LOW_MASK 0x0080 8855 #define TXPLL_ANAPLLASTATUS1_PLL_LOW_ALIGN 0 8856 #define TXPLL_ANAPLLASTATUS1_PLL_LOW_BITS 1 8857 #define TXPLL_ANAPLLASTATUS1_PLL_LOW_SHIFT 7 8858 8859 /* TxPll :: anaPllAStatus1 :: reserved1 [06:04] */ 8860 #define TXPLL_ANAPLLASTATUS1_RESERVED1_MASK 0x0070 8861 #define TXPLL_ANAPLLASTATUS1_RESERVED1_ALIGN 0 8862 #define TXPLL_ANAPLLASTATUS1_RESERVED1_BITS 3 8863 #define TXPLL_ANAPLLASTATUS1_RESERVED1_SHIFT 4 8864 8865 /* TxPll :: anaPllAStatus1 :: pll_Ndiv [03:00] */ 8866 #define TXPLL_ANAPLLASTATUS1_PLL_NDIV_MASK 0x000f 8867 #define TXPLL_ANAPLLASTATUS1_PLL_NDIV_ALIGN 0 8868 #define TXPLL_ANAPLLASTATUS1_PLL_NDIV_BITS 4 8869 #define TXPLL_ANAPLLASTATUS1_PLL_NDIV_SHIFT 0 8870 8871 8872 /**************************************************************************** 8873 * TxPll :: anaPllAControl0 8874 */ 8875 /* TxPll :: anaPllAControl0 :: refl_clkgen [15:15] */ 8876 #define TXPLL_ANAPLLACONTROL0_REFL_CLKGEN_MASK 0x8000 8877 #define TXPLL_ANAPLLACONTROL0_REFL_CLKGEN_ALIGN 0 8878 #define TXPLL_ANAPLLACONTROL0_REFL_CLKGEN_BITS 1 8879 #define TXPLL_ANAPLLACONTROL0_REFL_CLKGEN_SHIFT 15 8880 8881 /* TxPll :: anaPllAControl0 :: iclkidrv1 [14:12] */ 8882 #define TXPLL_ANAPLLACONTROL0_ICLKIDRV1_MASK 0x7000 8883 #define TXPLL_ANAPLLACONTROL0_ICLKIDRV1_ALIGN 0 8884 #define TXPLL_ANAPLLACONTROL0_ICLKIDRV1_BITS 3 8885 #define TXPLL_ANAPLLACONTROL0_ICLKIDRV1_SHIFT 12 8886 8887 /* TxPll :: anaPllAControl0 :: iclkodrv1 [11:09] */ 8888 #define TXPLL_ANAPLLACONTROL0_ICLKODRV1_MASK 0x0e00 8889 #define TXPLL_ANAPLLACONTROL0_ICLKODRV1_ALIGN 0 8890 #define TXPLL_ANAPLLACONTROL0_ICLKODRV1_BITS 3 8891 #define TXPLL_ANAPLLACONTROL0_ICLKODRV1_SHIFT 9 8892 8893 /* TxPll :: anaPllAControl0 :: iclkodrv2 [08:06] */ 8894 #define TXPLL_ANAPLLACONTROL0_ICLKODRV2_MASK 0x01c0 8895 #define TXPLL_ANAPLLACONTROL0_ICLKODRV2_ALIGN 0 8896 #define TXPLL_ANAPLLACONTROL0_ICLKODRV2_BITS 3 8897 #define TXPLL_ANAPLLACONTROL0_ICLKODRV2_SHIFT 6 8898 8899 /* TxPll :: anaPllAControl0 :: iclkdiv2 [05:03] */ 8900 #define TXPLL_ANAPLLACONTROL0_ICLKDIV2_MASK 0x0038 8901 #define TXPLL_ANAPLLACONTROL0_ICLKDIV2_ALIGN 0 8902 #define TXPLL_ANAPLLACONTROL0_ICLKDIV2_BITS 3 8903 #define TXPLL_ANAPLLACONTROL0_ICLKDIV2_SHIFT 3 8904 8905 /* TxPll :: anaPllAControl0 :: reserved0 [02:02] */ 8906 #define TXPLL_ANAPLLACONTROL0_RESERVED0_MASK 0x0004 8907 #define TXPLL_ANAPLLACONTROL0_RESERVED0_ALIGN 0 8908 #define TXPLL_ANAPLLACONTROL0_RESERVED0_BITS 1 8909 #define TXPLL_ANAPLLACONTROL0_RESERVED0_SHIFT 2 8910 8911 /* TxPll :: anaPllAControl0 :: vddr_bgb [01:01] */ 8912 #define TXPLL_ANAPLLACONTROL0_VDDR_BGB_MASK 0x0002 8913 #define TXPLL_ANAPLLACONTROL0_VDDR_BGB_ALIGN 0 8914 #define TXPLL_ANAPLLACONTROL0_VDDR_BGB_BITS 1 8915 #define TXPLL_ANAPLLACONTROL0_VDDR_BGB_SHIFT 1 8916 8917 /* TxPll :: anaPllAControl0 :: clksel_halfrate [00:00] */ 8918 #define TXPLL_ANAPLLACONTROL0_CLKSEL_HALFRATE_MASK 0x0001 8919 #define TXPLL_ANAPLLACONTROL0_CLKSEL_HALFRATE_ALIGN 0 8920 #define TXPLL_ANAPLLACONTROL0_CLKSEL_HALFRATE_BITS 1 8921 #define TXPLL_ANAPLLACONTROL0_CLKSEL_HALFRATE_SHIFT 0 8922 8923 8924 /**************************************************************************** 8925 * TxPll :: anaPllAControl1 8926 */ 8927 /* TxPll :: anaPllAControl1 :: kvhce [15:15] */ 8928 #define TXPLL_ANAPLLACONTROL1_KVHCE_MASK 0x8000 8929 #define TXPLL_ANAPLLACONTROL1_KVHCE_ALIGN 0 8930 #define TXPLL_ANAPLLACONTROL1_KVHCE_BITS 1 8931 #define TXPLL_ANAPLLACONTROL1_KVHCE_SHIFT 15 8932 8933 /* TxPll :: anaPllAControl1 :: reserved0 [14:11] */ 8934 #define TXPLL_ANAPLLACONTROL1_RESERVED0_MASK 0x7800 8935 #define TXPLL_ANAPLLACONTROL1_RESERVED0_ALIGN 0 8936 #define TXPLL_ANAPLLACONTROL1_RESERVED0_BITS 4 8937 #define TXPLL_ANAPLLACONTROL1_RESERVED0_SHIFT 11 8938 8939 /* TxPll :: anaPllAControl1 :: iclkibuf4 [10:08] */ 8940 #define TXPLL_ANAPLLACONTROL1_ICLKIBUF4_MASK 0x0700 8941 #define TXPLL_ANAPLLACONTROL1_ICLKIBUF4_ALIGN 0 8942 #define TXPLL_ANAPLLACONTROL1_ICLKIBUF4_BITS 3 8943 #define TXPLL_ANAPLLACONTROL1_ICLKIBUF4_SHIFT 8 8944 8945 /* TxPll :: anaPllAControl1 :: ibias_all [07:05] */ 8946 #define TXPLL_ANAPLLACONTROL1_IBIAS_ALL_MASK 0x00e0 8947 #define TXPLL_ANAPLLACONTROL1_IBIAS_ALL_ALIGN 0 8948 #define TXPLL_ANAPLLACONTROL1_IBIAS_ALL_BITS 3 8949 #define TXPLL_ANAPLLACONTROL1_IBIAS_ALL_SHIFT 5 8950 8951 /* TxPll :: anaPllAControl1 :: reserved1 [04:03] */ 8952 #define TXPLL_ANAPLLACONTROL1_RESERVED1_MASK 0x0018 8953 #define TXPLL_ANAPLLACONTROL1_RESERVED1_ALIGN 0 8954 #define TXPLL_ANAPLLACONTROL1_RESERVED1_BITS 2 8955 #define TXPLL_ANAPLLACONTROL1_RESERVED1_SHIFT 3 8956 8957 /* TxPll :: anaPllAControl1 :: pll2rx_clkbw [02:01] */ 8958 #define TXPLL_ANAPLLACONTROL1_PLL2RX_CLKBW_MASK 0x0006 8959 #define TXPLL_ANAPLLACONTROL1_PLL2RX_CLKBW_ALIGN 0 8960 #define TXPLL_ANAPLLACONTROL1_PLL2RX_CLKBW_BITS 2 8961 #define TXPLL_ANAPLLACONTROL1_PLL2RX_CLKBW_SHIFT 1 8962 8963 /* TxPll :: anaPllAControl1 :: refh_clkgen [00:00] */ 8964 #define TXPLL_ANAPLLACONTROL1_REFH_CLKGEN_MASK 0x0001 8965 #define TXPLL_ANAPLLACONTROL1_REFH_CLKGEN_ALIGN 0 8966 #define TXPLL_ANAPLLACONTROL1_REFH_CLKGEN_BITS 1 8967 #define TXPLL_ANAPLLACONTROL1_REFH_CLKGEN_SHIFT 0 8968 8969 8970 /**************************************************************************** 8971 * TxPll :: anaPllAControl2 8972 */ 8973 /* TxPll :: anaPllAControl2 :: ick2 [15:15] */ 8974 #define TXPLL_ANAPLLACONTROL2_ICK2_MASK 0x8000 8975 #define TXPLL_ANAPLLACONTROL2_ICK2_ALIGN 0 8976 #define TXPLL_ANAPLLACONTROL2_ICK2_BITS 1 8977 #define TXPLL_ANAPLLACONTROL2_ICK2_SHIFT 15 8978 8979 /* TxPll :: anaPllAControl2 :: ick0 [14:14] */ 8980 #define TXPLL_ANAPLLACONTROL2_ICK0_MASK 0x4000 8981 #define TXPLL_ANAPLLACONTROL2_ICK0_ALIGN 0 8982 #define TXPLL_ANAPLLACONTROL2_ICK0_BITS 1 8983 #define TXPLL_ANAPLLACONTROL2_ICK0_SHIFT 14 8984 8985 /* TxPll :: anaPllAControl2 :: ick1 [13:13] */ 8986 #define TXPLL_ANAPLLACONTROL2_ICK1_MASK 0x2000 8987 #define TXPLL_ANAPLLACONTROL2_ICK1_ALIGN 0 8988 #define TXPLL_ANAPLLACONTROL2_ICK1_BITS 1 8989 #define TXPLL_ANAPLLACONTROL2_ICK1_SHIFT 13 8990 8991 /* TxPll :: anaPllAControl2 :: icp2 [12:12] */ 8992 #define TXPLL_ANAPLLACONTROL2_ICP2_MASK 0x1000 8993 #define TXPLL_ANAPLLACONTROL2_ICP2_ALIGN 0 8994 #define TXPLL_ANAPLLACONTROL2_ICP2_BITS 1 8995 #define TXPLL_ANAPLLACONTROL2_ICP2_SHIFT 12 8996 8997 /* TxPll :: anaPllAControl2 :: icp0 [11:11] */ 8998 #define TXPLL_ANAPLLACONTROL2_ICP0_MASK 0x0800 8999 #define TXPLL_ANAPLLACONTROL2_ICP0_ALIGN 0 9000 #define TXPLL_ANAPLLACONTROL2_ICP0_BITS 1 9001 #define TXPLL_ANAPLLACONTROL2_ICP0_SHIFT 11 9002 9003 /* TxPll :: anaPllAControl2 :: icp1 [10:10] */ 9004 #define TXPLL_ANAPLLACONTROL2_ICP1_MASK 0x0400 9005 #define TXPLL_ANAPLLACONTROL2_ICP1_ALIGN 0 9006 #define TXPLL_ANAPLLACONTROL2_ICP1_BITS 1 9007 #define TXPLL_ANAPLLACONTROL2_ICP1_SHIFT 10 9008 9009 /* TxPll :: anaPllAControl2 :: ibmax [09:09] */ 9010 #define TXPLL_ANAPLLACONTROL2_IBMAX_MASK 0x0200 9011 #define TXPLL_ANAPLLACONTROL2_IBMAX_ALIGN 0 9012 #define TXPLL_ANAPLLACONTROL2_IBMAX_BITS 1 9013 #define TXPLL_ANAPLLACONTROL2_IBMAX_SHIFT 9 9014 9015 /* TxPll :: anaPllAControl2 :: ibmode [08:08] */ 9016 #define TXPLL_ANAPLLACONTROL2_IBMODE_MASK 0x0100 9017 #define TXPLL_ANAPLLACONTROL2_IBMODE_ALIGN 0 9018 #define TXPLL_ANAPLLACONTROL2_IBMODE_BITS 1 9019 #define TXPLL_ANAPLLACONTROL2_IBMODE_SHIFT 8 9020 9021 /* TxPll :: anaPllAControl2 :: ibmin [07:07] */ 9022 #define TXPLL_ANAPLLACONTROL2_IBMIN_MASK 0x0080 9023 #define TXPLL_ANAPLLACONTROL2_IBMIN_ALIGN 0 9024 #define TXPLL_ANAPLLACONTROL2_IBMIN_BITS 1 9025 #define TXPLL_ANAPLLACONTROL2_IBMIN_SHIFT 7 9026 9027 /* TxPll :: anaPllAControl2 :: refh_pll [06:06] */ 9028 #define TXPLL_ANAPLLACONTROL2_REFH_PLL_MASK 0x0040 9029 #define TXPLL_ANAPLLACONTROL2_REFH_PLL_ALIGN 0 9030 #define TXPLL_ANAPLLACONTROL2_REFH_PLL_BITS 1 9031 #define TXPLL_ANAPLLACONTROL2_REFH_PLL_SHIFT 6 9032 9033 /* TxPll :: anaPllAControl2 :: refl_pll [05:05] */ 9034 #define TXPLL_ANAPLLACONTROL2_REFL_PLL_MASK 0x0020 9035 #define TXPLL_ANAPLLACONTROL2_REFL_PLL_ALIGN 0 9036 #define TXPLL_ANAPLLACONTROL2_REFL_PLL_BITS 1 9037 #define TXPLL_ANAPLLACONTROL2_REFL_PLL_SHIFT 5 9038 9039 /* TxPll :: anaPllAControl2 :: iqp [04:02] */ 9040 #define TXPLL_ANAPLLACONTROL2_IQP_MASK 0x001c 9041 #define TXPLL_ANAPLLACONTROL2_IQP_ALIGN 0 9042 #define TXPLL_ANAPLLACONTROL2_IQP_BITS 3 9043 #define TXPLL_ANAPLLACONTROL2_IQP_SHIFT 2 9044 9045 /* TxPll :: anaPllAControl2 :: en_p3 [01:01] */ 9046 #define TXPLL_ANAPLLACONTROL2_EN_P3_MASK 0x0002 9047 #define TXPLL_ANAPLLACONTROL2_EN_P3_ALIGN 0 9048 #define TXPLL_ANAPLLACONTROL2_EN_P3_BITS 1 9049 #define TXPLL_ANAPLLACONTROL2_EN_P3_SHIFT 1 9050 9051 /* TxPll :: anaPllAControl2 :: enable_ftune [00:00] */ 9052 #define TXPLL_ANAPLLACONTROL2_ENABLE_FTUNE_MASK 0x0001 9053 #define TXPLL_ANAPLLACONTROL2_ENABLE_FTUNE_ALIGN 0 9054 #define TXPLL_ANAPLLACONTROL2_ENABLE_FTUNE_BITS 1 9055 #define TXPLL_ANAPLLACONTROL2_ENABLE_FTUNE_SHIFT 0 9056 9057 9058 /**************************************************************************** 9059 * TxPll :: anaPllAControl3 9060 */ 9061 /* TxPll :: anaPllAControl3 :: test_rx [15:15] */ 9062 #define TXPLL_ANAPLLACONTROL3_TEST_RX_MASK 0x8000 9063 #define TXPLL_ANAPLLACONTROL3_TEST_RX_ALIGN 0 9064 #define TXPLL_ANAPLLACONTROL3_TEST_RX_BITS 1 9065 #define TXPLL_ANAPLLACONTROL3_TEST_RX_SHIFT 15 9066 9067 /* TxPll :: anaPllAControl3 :: test_pll [14:14] */ 9068 #define TXPLL_ANAPLLACONTROL3_TEST_PLL_MASK 0x4000 9069 #define TXPLL_ANAPLLACONTROL3_TEST_PLL_ALIGN 0 9070 #define TXPLL_ANAPLLACONTROL3_TEST_PLL_BITS 1 9071 #define TXPLL_ANAPLLACONTROL3_TEST_PLL_SHIFT 14 9072 9073 /* TxPll :: anaPllAControl3 :: test_vc [13:13] */ 9074 #define TXPLL_ANAPLLACONTROL3_TEST_VC_MASK 0x2000 9075 #define TXPLL_ANAPLLACONTROL3_TEST_VC_ALIGN 0 9076 #define TXPLL_ANAPLLACONTROL3_TEST_VC_BITS 1 9077 #define TXPLL_ANAPLLACONTROL3_TEST_VC_SHIFT 13 9078 9079 /* TxPll :: anaPllAControl3 :: test_vref [12:12] */ 9080 #define TXPLL_ANAPLLACONTROL3_TEST_VREF_MASK 0x1000 9081 #define TXPLL_ANAPLLACONTROL3_TEST_VREF_ALIGN 0 9082 #define TXPLL_ANAPLLACONTROL3_TEST_VREF_BITS 1 9083 #define TXPLL_ANAPLLACONTROL3_TEST_VREF_SHIFT 12 9084 9085 /* TxPll :: anaPllAControl3 :: iop2 [11:11] */ 9086 #define TXPLL_ANAPLLACONTROL3_IOP2_MASK 0x0800 9087 #define TXPLL_ANAPLLACONTROL3_IOP2_ALIGN 0 9088 #define TXPLL_ANAPLLACONTROL3_IOP2_BITS 1 9089 #define TXPLL_ANAPLLACONTROL3_IOP2_SHIFT 11 9090 9091 /* TxPll :: anaPllAControl3 :: iop0 [10:10] */ 9092 #define TXPLL_ANAPLLACONTROL3_IOP0_MASK 0x0400 9093 #define TXPLL_ANAPLLACONTROL3_IOP0_ALIGN 0 9094 #define TXPLL_ANAPLLACONTROL3_IOP0_BITS 1 9095 #define TXPLL_ANAPLLACONTROL3_IOP0_SHIFT 10 9096 9097 /* TxPll :: anaPllAControl3 :: iop1 [09:09] */ 9098 #define TXPLL_ANAPLLACONTROL3_IOP1_MASK 0x0200 9099 #define TXPLL_ANAPLLACONTROL3_IOP1_ALIGN 0 9100 #define TXPLL_ANAPLLACONTROL3_IOP1_BITS 1 9101 #define TXPLL_ANAPLLACONTROL3_IOP1_SHIFT 9 9102 9103 /* TxPll :: anaPllAControl3 :: icomp2 [08:08] */ 9104 #define TXPLL_ANAPLLACONTROL3_ICOMP2_MASK 0x0100 9105 #define TXPLL_ANAPLLACONTROL3_ICOMP2_ALIGN 0 9106 #define TXPLL_ANAPLLACONTROL3_ICOMP2_BITS 1 9107 #define TXPLL_ANAPLLACONTROL3_ICOMP2_SHIFT 8 9108 9109 /* TxPll :: anaPllAControl3 :: icomp0 [07:07] */ 9110 #define TXPLL_ANAPLLACONTROL3_ICOMP0_MASK 0x0080 9111 #define TXPLL_ANAPLLACONTROL3_ICOMP0_ALIGN 0 9112 #define TXPLL_ANAPLLACONTROL3_ICOMP0_BITS 1 9113 #define TXPLL_ANAPLLACONTROL3_ICOMP0_SHIFT 7 9114 9115 /* TxPll :: anaPllAControl3 :: icomp1 [06:06] */ 9116 #define TXPLL_ANAPLLACONTROL3_ICOMP1_MASK 0x0040 9117 #define TXPLL_ANAPLLACONTROL3_ICOMP1_ALIGN 0 9118 #define TXPLL_ANAPLLACONTROL3_ICOMP1_BITS 1 9119 #define TXPLL_ANAPLLACONTROL3_ICOMP1_SHIFT 6 9120 9121 /* TxPll :: anaPllAControl3 :: icml2 [05:05] */ 9122 #define TXPLL_ANAPLLACONTROL3_ICML2_MASK 0x0020 9123 #define TXPLL_ANAPLLACONTROL3_ICML2_ALIGN 0 9124 #define TXPLL_ANAPLLACONTROL3_ICML2_BITS 1 9125 #define TXPLL_ANAPLLACONTROL3_ICML2_SHIFT 5 9126 9127 /* TxPll :: anaPllAControl3 :: icml0 [04:04] */ 9128 #define TXPLL_ANAPLLACONTROL3_ICML0_MASK 0x0010 9129 #define TXPLL_ANAPLLACONTROL3_ICML0_ALIGN 0 9130 #define TXPLL_ANAPLLACONTROL3_ICML0_BITS 1 9131 #define TXPLL_ANAPLLACONTROL3_ICML0_SHIFT 4 9132 9133 /* TxPll :: anaPllAControl3 :: icml1 [03:03] */ 9134 #define TXPLL_ANAPLLACONTROL3_ICML1_MASK 0x0008 9135 #define TXPLL_ANAPLLACONTROL3_ICML1_ALIGN 0 9136 #define TXPLL_ANAPLLACONTROL3_ICML1_BITS 1 9137 #define TXPLL_ANAPLLACONTROL3_ICML1_SHIFT 3 9138 9139 /* TxPll :: anaPllAControl3 :: ivco2 [02:02] */ 9140 #define TXPLL_ANAPLLACONTROL3_IVCO2_MASK 0x0004 9141 #define TXPLL_ANAPLLACONTROL3_IVCO2_ALIGN 0 9142 #define TXPLL_ANAPLLACONTROL3_IVCO2_BITS 1 9143 #define TXPLL_ANAPLLACONTROL3_IVCO2_SHIFT 2 9144 9145 /* TxPll :: anaPllAControl3 :: ivco0 [01:01] */ 9146 #define TXPLL_ANAPLLACONTROL3_IVCO0_MASK 0x0002 9147 #define TXPLL_ANAPLLACONTROL3_IVCO0_ALIGN 0 9148 #define TXPLL_ANAPLLACONTROL3_IVCO0_BITS 1 9149 #define TXPLL_ANAPLLACONTROL3_IVCO0_SHIFT 1 9150 9151 /* TxPll :: anaPllAControl3 :: ivco1 [00:00] */ 9152 #define TXPLL_ANAPLLACONTROL3_IVCO1_MASK 0x0001 9153 #define TXPLL_ANAPLLACONTROL3_IVCO1_ALIGN 0 9154 #define TXPLL_ANAPLLACONTROL3_IVCO1_BITS 1 9155 #define TXPLL_ANAPLLACONTROL3_IVCO1_SHIFT 0 9156 9157 9158 /**************************************************************************** 9159 * TxPll :: anaPllAControl4 9160 */ 9161 /* TxPll :: anaPllAControl4 :: en65g [15:15] */ 9162 #define TXPLL_ANAPLLACONTROL4_EN65G_MASK 0x8000 9163 #define TXPLL_ANAPLLACONTROL4_EN65G_ALIGN 0 9164 #define TXPLL_ANAPLLACONTROL4_EN65G_BITS 1 9165 #define TXPLL_ANAPLLACONTROL4_EN65G_SHIFT 15 9166 9167 /* TxPll :: anaPllAControl4 :: kvh_force [14:12] */ 9168 #define TXPLL_ANAPLLACONTROL4_KVH_FORCE_MASK 0x7000 9169 #define TXPLL_ANAPLLACONTROL4_KVH_FORCE_ALIGN 0 9170 #define TXPLL_ANAPLLACONTROL4_KVH_FORCE_BITS 3 9171 #define TXPLL_ANAPLLACONTROL4_KVH_FORCE_SHIFT 12 9172 9173 /* TxPll :: anaPllAControl4 :: vddr_bgb [11:11] */ 9174 #define TXPLL_ANAPLLACONTROL4_VDDR_BGB_MASK 0x0800 9175 #define TXPLL_ANAPLLACONTROL4_VDDR_BGB_ALIGN 0 9176 #define TXPLL_ANAPLLACONTROL4_VDDR_BGB_BITS 1 9177 #define TXPLL_ANAPLLACONTROL4_VDDR_BGB_SHIFT 11 9178 9179 /* TxPll :: anaPllAControl4 :: comp_vth [10:10] */ 9180 #define TXPLL_ANAPLLACONTROL4_COMP_VTH_MASK 0x0400 9181 #define TXPLL_ANAPLLACONTROL4_COMP_VTH_ALIGN 0 9182 #define TXPLL_ANAPLLACONTROL4_COMP_VTH_BITS 1 9183 #define TXPLL_ANAPLLACONTROL4_COMP_VTH_SHIFT 10 9184 9185 /* TxPll :: anaPllAControl4 :: actrl [09:08] */ 9186 #define TXPLL_ANAPLLACONTROL4_ACTRL_MASK 0x0300 9187 #define TXPLL_ANAPLLACONTROL4_ACTRL_ALIGN 0 9188 #define TXPLL_ANAPLLACONTROL4_ACTRL_BITS 2 9189 #define TXPLL_ANAPLLACONTROL4_ACTRL_SHIFT 8 9190 9191 /* TxPll :: anaPllAControl4 :: ctatadj [07:04] */ 9192 #define TXPLL_ANAPLLACONTROL4_CTATADJ_MASK 0x00f0 9193 #define TXPLL_ANAPLLACONTROL4_CTATADJ_ALIGN 0 9194 #define TXPLL_ANAPLLACONTROL4_CTATADJ_BITS 4 9195 #define TXPLL_ANAPLLACONTROL4_CTATADJ_SHIFT 4 9196 9197 /* TxPll :: anaPllAControl4 :: ptatadj [03:00] */ 9198 #define TXPLL_ANAPLLACONTROL4_PTATADJ_MASK 0x000f 9199 #define TXPLL_ANAPLLACONTROL4_PTATADJ_ALIGN 0 9200 #define TXPLL_ANAPLLACONTROL4_PTATADJ_BITS 4 9201 #define TXPLL_ANAPLLACONTROL4_PTATADJ_SHIFT 0 9202 9203 9204 /**************************************************************************** 9205 * Hypercore_USER_Tx0 9206 */ 9207 /**************************************************************************** 9208 * Tx0 :: anaTxAStatus0 9209 */ 9210 /* Tx0 :: anaTxAStatus0 :: reserved0 [15:07] */ 9211 #define TX0_ANATXASTATUS0_RESERVED0_MASK 0xff80 9212 #define TX0_ANATXASTATUS0_RESERVED0_ALIGN 0 9213 #define TX0_ANATXASTATUS0_RESERVED0_BITS 9 9214 #define TX0_ANATXASTATUS0_RESERVED0_SHIFT 7 9215 9216 /* Tx0 :: anaTxAStatus0 :: txdisable_ln [06:06] */ 9217 #define TX0_ANATXASTATUS0_TXDISABLE_LN_MASK 0x0040 9218 #define TX0_ANATXASTATUS0_TXDISABLE_LN_ALIGN 0 9219 #define TX0_ANATXASTATUS0_TXDISABLE_LN_BITS 1 9220 #define TX0_ANATXASTATUS0_TXDISABLE_LN_SHIFT 6 9221 9222 /* Tx0 :: anaTxAStatus0 :: txferr_stky [05:05] */ 9223 #define TX0_ANATXASTATUS0_TXFERR_STKY_MASK 0x0020 9224 #define TX0_ANATXASTATUS0_TXFERR_STKY_ALIGN 0 9225 #define TX0_ANATXASTATUS0_TXFERR_STKY_BITS 1 9226 #define TX0_ANATXASTATUS0_TXFERR_STKY_SHIFT 5 9227 9228 /* Tx0 :: anaTxAStatus0 :: tbi_mode [04:04] */ 9229 #define TX0_ANATXASTATUS0_TBI_MODE_MASK 0x0010 9230 #define TX0_ANATXASTATUS0_TBI_MODE_ALIGN 0 9231 #define TX0_ANATXASTATUS0_TBI_MODE_BITS 1 9232 #define TX0_ANATXASTATUS0_TBI_MODE_SHIFT 4 9233 9234 /* Tx0 :: anaTxAStatus0 :: tx_reset [03:03] */ 9235 #define TX0_ANATXASTATUS0_TX_RESET_MASK 0x0008 9236 #define TX0_ANATXASTATUS0_TX_RESET_ALIGN 0 9237 #define TX0_ANATXASTATUS0_TX_RESET_BITS 1 9238 #define TX0_ANATXASTATUS0_TX_RESET_SHIFT 3 9239 9240 /* Tx0 :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 9241 #define TX0_ANATXASTATUS0_TX_PWRDN_MASK 0x0004 9242 #define TX0_ANATXASTATUS0_TX_PWRDN_ALIGN 0 9243 #define TX0_ANATXASTATUS0_TX_PWRDN_BITS 1 9244 #define TX0_ANATXASTATUS0_TX_PWRDN_SHIFT 2 9245 9246 /* Tx0 :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 9247 #define TX0_ANATXASTATUS0_RLTXFERR_STKY_MASK 0x0002 9248 #define TX0_ANATXASTATUS0_RLTXFERR_STKY_ALIGN 0 9249 #define TX0_ANATXASTATUS0_RLTXFERR_STKY_BITS 1 9250 #define TX0_ANATXASTATUS0_RLTXFERR_STKY_SHIFT 1 9251 9252 /* Tx0 :: anaTxAStatus0 :: txpll_lock [00:00] */ 9253 #define TX0_ANATXASTATUS0_TXPLL_LOCK_MASK 0x0001 9254 #define TX0_ANATXASTATUS0_TXPLL_LOCK_ALIGN 0 9255 #define TX0_ANATXASTATUS0_TXPLL_LOCK_BITS 1 9256 #define TX0_ANATXASTATUS0_TXPLL_LOCK_SHIFT 0 9257 9258 9259 /**************************************************************************** 9260 * Tx0 :: anaTxAControl0 9261 */ 9262 /* Tx0 :: anaTxAControl0 :: reserved0 [15:15] */ 9263 #define TX0_ANATXACONTROL0_RESERVED0_MASK 0x8000 9264 #define TX0_ANATXACONTROL0_RESERVED0_ALIGN 0 9265 #define TX0_ANATXACONTROL0_RESERVED0_BITS 1 9266 #define TX0_ANATXACONTROL0_RESERVED0_SHIFT 15 9267 9268 /* Tx0 :: anaTxAControl0 :: force_txclk [14:14] */ 9269 #define TX0_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 9270 #define TX0_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 9271 #define TX0_ANATXACONTROL0_FORCE_TXCLK_BITS 1 9272 #define TX0_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 9273 9274 /* Tx0 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 9275 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 9276 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 9277 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 9278 #define TX0_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 9279 9280 /* Tx0 :: anaTxAControl0 :: gloopOutEn [12:12] */ 9281 #define TX0_ANATXACONTROL0_GLOOPOUTEN_MASK 0x1000 9282 #define TX0_ANATXACONTROL0_GLOOPOUTEN_ALIGN 0 9283 #define TX0_ANATXACONTROL0_GLOOPOUTEN_BITS 1 9284 #define TX0_ANATXACONTROL0_GLOOPOUTEN_SHIFT 12 9285 9286 /* Tx0 :: anaTxAControl0 :: reserved1 [11:09] */ 9287 #define TX0_ANATXACONTROL0_RESERVED1_MASK 0x0e00 9288 #define TX0_ANATXACONTROL0_RESERVED1_ALIGN 0 9289 #define TX0_ANATXACONTROL0_RESERVED1_BITS 3 9290 #define TX0_ANATXACONTROL0_RESERVED1_SHIFT 9 9291 9292 /* Tx0 :: anaTxAControl0 :: prbs_en [08:08] */ 9293 #define TX0_ANATXACONTROL0_PRBS_EN_MASK 0x0100 9294 #define TX0_ANATXACONTROL0_PRBS_EN_ALIGN 0 9295 #define TX0_ANATXACONTROL0_PRBS_EN_BITS 1 9296 #define TX0_ANATXACONTROL0_PRBS_EN_SHIFT 8 9297 9298 /* Tx0 :: anaTxAControl0 :: pckt_en [07:07] */ 9299 #define TX0_ANATXACONTROL0_PCKT_EN_MASK 0x0080 9300 #define TX0_ANATXACONTROL0_PCKT_EN_ALIGN 0 9301 #define TX0_ANATXACONTROL0_PCKT_EN_BITS 1 9302 #define TX0_ANATXACONTROL0_PCKT_EN_SHIFT 7 9303 9304 /* Tx0 :: anaTxAControl0 :: pckt_strt [06:06] */ 9305 #define TX0_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 9306 #define TX0_ANATXACONTROL0_PCKT_STRT_ALIGN 0 9307 #define TX0_ANATXACONTROL0_PCKT_STRT_BITS 1 9308 #define TX0_ANATXACONTROL0_PCKT_STRT_SHIFT 6 9309 9310 /* Tx0 :: anaTxAControl0 :: txpol_flip [05:05] */ 9311 #define TX0_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 9312 #define TX0_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 9313 #define TX0_ANATXACONTROL0_TXPOL_FLIP_BITS 1 9314 #define TX0_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 9315 9316 /* Tx0 :: anaTxAControl0 :: rtbi_flip [04:04] */ 9317 #define TX0_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 9318 #define TX0_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 9319 #define TX0_ANATXACONTROL0_RTBI_FLIP_BITS 1 9320 #define TX0_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 9321 9322 /* Tx0 :: anaTxAControl0 :: eden_r [03:03] */ 9323 #define TX0_ANATXACONTROL0_EDEN_R_MASK 0x0008 9324 #define TX0_ANATXACONTROL0_EDEN_R_ALIGN 0 9325 #define TX0_ANATXACONTROL0_EDEN_R_BITS 1 9326 #define TX0_ANATXACONTROL0_EDEN_R_SHIFT 3 9327 9328 /* Tx0 :: anaTxAControl0 :: eden_force_r [02:02] */ 9329 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 9330 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 9331 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 9332 #define TX0_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 9333 9334 /* Tx0 :: anaTxAControl0 :: txpat_en [01:01] */ 9335 #define TX0_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 9336 #define TX0_ANATXACONTROL0_TXPAT_EN_ALIGN 0 9337 #define TX0_ANATXACONTROL0_TXPAT_EN_BITS 1 9338 #define TX0_ANATXACONTROL0_TXPAT_EN_SHIFT 1 9339 9340 /* Tx0 :: anaTxAControl0 :: tx_mdata_en [00:00] */ 9341 #define TX0_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 9342 #define TX0_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 9343 #define TX0_ANATXACONTROL0_TX_MDATA_EN_BITS 1 9344 #define TX0_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 9345 9346 9347 /**************************************************************************** 9348 * Tx0 :: anaTxmdata0 9349 */ 9350 /* Tx0 :: anaTxmdata0 :: txTestMuxSel [15:13] */ 9351 #define TX0_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 9352 #define TX0_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 9353 #define TX0_ANATXMDATA0_TXTESTMUXSEL_BITS 3 9354 #define TX0_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 9355 9356 /* Tx0 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 9357 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 9358 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 9359 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 9360 #define TX0_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 9361 9362 /* Tx0 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 9363 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 9364 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 9365 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 9366 #define TX0_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 9367 9368 9369 /**************************************************************************** 9370 * Tx0 :: anaTxmdata1 9371 */ 9372 /* Tx0 :: anaTxmdata1 :: reserved0 [15:10] */ 9373 #define TX0_ANATXMDATA1_RESERVED0_MASK 0xfc00 9374 #define TX0_ANATXMDATA1_RESERVED0_ALIGN 0 9375 #define TX0_ANATXMDATA1_RESERVED0_BITS 6 9376 #define TX0_ANATXMDATA1_RESERVED0_SHIFT 10 9377 9378 /* Tx0 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 9379 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 9380 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 9381 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 9382 #define TX0_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 9383 9384 9385 /**************************************************************************** 9386 * Tx0 :: anaTxAStatus1 9387 */ 9388 /* Tx0 :: anaTxAStatus1 :: tx_id [15:14] */ 9389 #define TX0_ANATXASTATUS1_TX_ID_MASK 0xc000 9390 #define TX0_ANATXASTATUS1_TX_ID_ALIGN 0 9391 #define TX0_ANATXASTATUS1_TX_ID_BITS 2 9392 #define TX0_ANATXASTATUS1_TX_ID_SHIFT 14 9393 9394 /* Tx0 :: anaTxAStatus1 :: reserved0 [13:00] */ 9395 #define TX0_ANATXASTATUS1_RESERVED0_MASK 0x3fff 9396 #define TX0_ANATXASTATUS1_RESERVED0_ALIGN 0 9397 #define TX0_ANATXASTATUS1_RESERVED0_BITS 14 9398 #define TX0_ANATXASTATUS1_RESERVED0_SHIFT 0 9399 9400 9401 /**************************************************************************** 9402 * Tx0 :: anaTxAControl1 9403 */ 9404 /* Tx0 :: anaTxAControl1 :: id2c [15:13] */ 9405 #define TX0_ANATXACONTROL1_ID2C_MASK 0xe000 9406 #define TX0_ANATXACONTROL1_ID2C_ALIGN 0 9407 #define TX0_ANATXACONTROL1_ID2C_BITS 3 9408 #define TX0_ANATXACONTROL1_ID2C_SHIFT 13 9409 9410 /* Tx0 :: anaTxAControl1 :: refl_tx [12:12] */ 9411 #define TX0_ANATXACONTROL1_REFL_TX_MASK 0x1000 9412 #define TX0_ANATXACONTROL1_REFL_TX_ALIGN 0 9413 #define TX0_ANATXACONTROL1_REFL_TX_BITS 1 9414 #define TX0_ANATXACONTROL1_REFL_TX_SHIFT 12 9415 9416 /* Tx0 :: anaTxAControl1 :: refh_tx [11:11] */ 9417 #define TX0_ANATXACONTROL1_REFH_TX_MASK 0x0800 9418 #define TX0_ANATXACONTROL1_REFH_TX_ALIGN 0 9419 #define TX0_ANATXACONTROL1_REFH_TX_BITS 1 9420 #define TX0_ANATXACONTROL1_REFH_TX_SHIFT 11 9421 9422 /* Tx0 :: anaTxAControl1 :: newbias_en [10:10] */ 9423 #define TX0_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 9424 #define TX0_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 9425 #define TX0_ANATXACONTROL1_NEWBIAS_EN_BITS 1 9426 #define TX0_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 9427 9428 /* Tx0 :: anaTxAControl1 :: drivermode [09:09] */ 9429 #define TX0_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 9430 #define TX0_ANATXACONTROL1_DRIVERMODE_ALIGN 0 9431 #define TX0_ANATXACONTROL1_DRIVERMODE_BITS 1 9432 #define TX0_ANATXACONTROL1_DRIVERMODE_SHIFT 9 9433 9434 /* Tx0 :: anaTxAControl1 :: vddr_bgb [08:08] */ 9435 #define TX0_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 9436 #define TX0_ANATXACONTROL1_VDDR_BGB_ALIGN 0 9437 #define TX0_ANATXACONTROL1_VDDR_BGB_BITS 1 9438 #define TX0_ANATXACONTROL1_VDDR_BGB_SHIFT 8 9439 9440 /* Tx0 :: anaTxAControl1 :: ticksel [07:06] */ 9441 #define TX0_ANATXACONTROL1_TICKSEL_MASK 0x00c0 9442 #define TX0_ANATXACONTROL1_TICKSEL_ALIGN 0 9443 #define TX0_ANATXACONTROL1_TICKSEL_BITS 2 9444 #define TX0_ANATXACONTROL1_TICKSEL_SHIFT 6 9445 9446 /* Tx0 :: anaTxAControl1 :: driver_vcm [05:04] */ 9447 #define TX0_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 9448 #define TX0_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 9449 #define TX0_ANATXACONTROL1_DRIVER_VCM_BITS 2 9450 #define TX0_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 9451 9452 /* Tx0 :: anaTxAControl1 :: tx_sel_halfrate [03:03] */ 9453 #define TX0_ANATXACONTROL1_TX_SEL_HALFRATE_MASK 0x0008 9454 #define TX0_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN 0 9455 #define TX0_ANATXACONTROL1_TX_SEL_HALFRATE_BITS 1 9456 #define TX0_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT 3 9457 9458 /* Tx0 :: anaTxAControl1 :: ifullspd [02:00] */ 9459 #define TX0_ANATXACONTROL1_IFULLSPD_MASK 0x0007 9460 #define TX0_ANATXACONTROL1_IFULLSPD_ALIGN 0 9461 #define TX0_ANATXACONTROL1_IFULLSPD_BITS 3 9462 #define TX0_ANATXACONTROL1_IFULLSPD_SHIFT 0 9463 9464 9465 /**************************************************************************** 9466 * Tx0 :: anaTxAControl2 9467 */ 9468 /* Tx0 :: anaTxAControl2 :: icbuf1t [15:14] */ 9469 #define TX0_ANATXACONTROL2_ICBUF1T_MASK 0xc000 9470 #define TX0_ANATXACONTROL2_ICBUF1T_ALIGN 0 9471 #define TX0_ANATXACONTROL2_ICBUF1T_BITS 2 9472 #define TX0_ANATXACONTROL2_ICBUF1T_SHIFT 14 9473 9474 /* Tx0 :: anaTxAControl2 :: icbuf2t [13:11] */ 9475 #define TX0_ANATXACONTROL2_ICBUF2T_MASK 0x3800 9476 #define TX0_ANATXACONTROL2_ICBUF2T_ALIGN 0 9477 #define TX0_ANATXACONTROL2_ICBUF2T_BITS 3 9478 #define TX0_ANATXACONTROL2_ICBUF2T_SHIFT 11 9479 9480 /* Tx0 :: anaTxAControl2 :: imin_predrv [10:10] */ 9481 #define TX0_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 9482 #define TX0_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 9483 #define TX0_ANATXACONTROL2_IMIN_PREDRV_BITS 1 9484 #define TX0_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 9485 9486 /* Tx0 :: anaTxAControl2 :: imax_predrv [09:09] */ 9487 #define TX0_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 9488 #define TX0_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 9489 #define TX0_ANATXACONTROL2_IMAX_PREDRV_BITS 1 9490 #define TX0_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 9491 9492 /* Tx0 :: anaTxAControl2 :: imode_predrv [08:08] */ 9493 #define TX0_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 9494 #define TX0_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 9495 #define TX0_ANATXACONTROL2_IMODE_PREDRV_BITS 1 9496 #define TX0_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 9497 9498 /* Tx0 :: anaTxAControl2 :: i21mux [07:05] */ 9499 #define TX0_ANATXACONTROL2_I21MUX_MASK 0x00e0 9500 #define TX0_ANATXACONTROL2_I21MUX_ALIGN 0 9501 #define TX0_ANATXACONTROL2_I21MUX_BITS 3 9502 #define TX0_ANATXACONTROL2_I21MUX_SHIFT 5 9503 9504 /* Tx0 :: anaTxAControl2 :: imin_drvr [04:04] */ 9505 #define TX0_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 9506 #define TX0_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 9507 #define TX0_ANATXACONTROL2_IMIN_DRVR_BITS 1 9508 #define TX0_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 9509 9510 /* Tx0 :: anaTxAControl2 :: imax_drvr [03:03] */ 9511 #define TX0_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 9512 #define TX0_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 9513 #define TX0_ANATXACONTROL2_IMAX_DRVR_BITS 1 9514 #define TX0_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 9515 9516 /* Tx0 :: anaTxAControl2 :: imode_drvr [02:02] */ 9517 #define TX0_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 9518 #define TX0_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 9519 #define TX0_ANATXACONTROL2_IMODE_DRVR_BITS 1 9520 #define TX0_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 9521 9522 /* Tx0 :: anaTxAControl2 :: reserved0 [01:00] */ 9523 #define TX0_ANATXACONTROL2_RESERVED0_MASK 0x0003 9524 #define TX0_ANATXACONTROL2_RESERVED0_ALIGN 0 9525 #define TX0_ANATXACONTROL2_RESERVED0_BITS 2 9526 #define TX0_ANATXACONTROL2_RESERVED0_SHIFT 0 9527 9528 9529 /**************************************************************************** 9530 * Tx0 :: Tx_OS_Driver 9531 */ 9532 /* Tx0 :: Tx_OS_Driver :: preemphasis_post [15:12] */ 9533 #define TX0_TX_OS_DRIVER_PREEMPHASIS_POST_MASK 0xf000 9534 #define TX0_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN 0 9535 #define TX0_TX_OS_DRIVER_PREEMPHASIS_POST_BITS 4 9536 #define TX0_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT 12 9537 9538 /* Tx0 :: Tx_OS_Driver :: Idriver [11:08] */ 9539 #define TX0_TX_OS_DRIVER_IDRIVER_MASK 0x0f00 9540 #define TX0_TX_OS_DRIVER_IDRIVER_ALIGN 0 9541 #define TX0_TX_OS_DRIVER_IDRIVER_BITS 4 9542 #define TX0_TX_OS_DRIVER_IDRIVER_SHIFT 8 9543 9544 /* Tx0 :: Tx_OS_Driver :: Ipredriver [07:04] */ 9545 #define TX0_TX_OS_DRIVER_IPREDRIVER_MASK 0x00f0 9546 #define TX0_TX_OS_DRIVER_IPREDRIVER_ALIGN 0 9547 #define TX0_TX_OS_DRIVER_IPREDRIVER_BITS 4 9548 #define TX0_TX_OS_DRIVER_IPREDRIVER_SHIFT 4 9549 9550 /* Tx0 :: Tx_OS_Driver :: preemphasis_pre [03:01] */ 9551 #define TX0_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 9552 #define TX0_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN 0 9553 #define TX0_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS 3 9554 #define TX0_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT 1 9555 9556 /* Tx0 :: Tx_OS_Driver :: icbuf1t0 [00:00] */ 9557 #define TX0_TX_OS_DRIVER_ICBUF1T0_MASK 0x0001 9558 #define TX0_TX_OS_DRIVER_ICBUF1T0_ALIGN 0 9559 #define TX0_TX_OS_DRIVER_ICBUF1T0_BITS 1 9560 #define TX0_TX_OS_DRIVER_ICBUF1T0_SHIFT 0 9561 9562 9563 /**************************************************************************** 9564 * Tx0 :: Tx_BR_Driver 9565 */ 9566 /* Tx0 :: Tx_BR_Driver :: preemphasis_post [15:12] */ 9567 #define TX0_TX_BR_DRIVER_PREEMPHASIS_POST_MASK 0xf000 9568 #define TX0_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN 0 9569 #define TX0_TX_BR_DRIVER_PREEMPHASIS_POST_BITS 4 9570 #define TX0_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT 12 9571 9572 /* Tx0 :: Tx_BR_Driver :: Idriver [11:08] */ 9573 #define TX0_TX_BR_DRIVER_IDRIVER_MASK 0x0f00 9574 #define TX0_TX_BR_DRIVER_IDRIVER_ALIGN 0 9575 #define TX0_TX_BR_DRIVER_IDRIVER_BITS 4 9576 #define TX0_TX_BR_DRIVER_IDRIVER_SHIFT 8 9577 9578 /* Tx0 :: Tx_BR_Driver :: Ipredriver [07:04] */ 9579 #define TX0_TX_BR_DRIVER_IPREDRIVER_MASK 0x00f0 9580 #define TX0_TX_BR_DRIVER_IPREDRIVER_ALIGN 0 9581 #define TX0_TX_BR_DRIVER_IPREDRIVER_BITS 4 9582 #define TX0_TX_BR_DRIVER_IPREDRIVER_SHIFT 4 9583 9584 /* Tx0 :: Tx_BR_Driver :: preemphasis_pre [03:01] */ 9585 #define TX0_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 9586 #define TX0_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN 0 9587 #define TX0_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS 3 9588 #define TX0_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT 1 9589 9590 /* Tx0 :: Tx_BR_Driver :: icbuf1t0 [00:00] */ 9591 #define TX0_TX_BR_DRIVER_ICBUF1T0_MASK 0x0001 9592 #define TX0_TX_BR_DRIVER_ICBUF1T0_ALIGN 0 9593 #define TX0_TX_BR_DRIVER_ICBUF1T0_BITS 1 9594 #define TX0_TX_BR_DRIVER_ICBUF1T0_SHIFT 0 9595 9596 9597 /**************************************************************************** 9598 * Hypercore_USER_Tx1 9599 */ 9600 /**************************************************************************** 9601 * Tx1 :: anaTxAStatus0 9602 */ 9603 /* Tx1 :: anaTxAStatus0 :: reserved0 [15:07] */ 9604 #define TX1_ANATXASTATUS0_RESERVED0_MASK 0xff80 9605 #define TX1_ANATXASTATUS0_RESERVED0_ALIGN 0 9606 #define TX1_ANATXASTATUS0_RESERVED0_BITS 9 9607 #define TX1_ANATXASTATUS0_RESERVED0_SHIFT 7 9608 9609 /* Tx1 :: anaTxAStatus0 :: txdisable_ln [06:06] */ 9610 #define TX1_ANATXASTATUS0_TXDISABLE_LN_MASK 0x0040 9611 #define TX1_ANATXASTATUS0_TXDISABLE_LN_ALIGN 0 9612 #define TX1_ANATXASTATUS0_TXDISABLE_LN_BITS 1 9613 #define TX1_ANATXASTATUS0_TXDISABLE_LN_SHIFT 6 9614 9615 /* Tx1 :: anaTxAStatus0 :: txferr_stky [05:05] */ 9616 #define TX1_ANATXASTATUS0_TXFERR_STKY_MASK 0x0020 9617 #define TX1_ANATXASTATUS0_TXFERR_STKY_ALIGN 0 9618 #define TX1_ANATXASTATUS0_TXFERR_STKY_BITS 1 9619 #define TX1_ANATXASTATUS0_TXFERR_STKY_SHIFT 5 9620 9621 /* Tx1 :: anaTxAStatus0 :: tbi_mode [04:04] */ 9622 #define TX1_ANATXASTATUS0_TBI_MODE_MASK 0x0010 9623 #define TX1_ANATXASTATUS0_TBI_MODE_ALIGN 0 9624 #define TX1_ANATXASTATUS0_TBI_MODE_BITS 1 9625 #define TX1_ANATXASTATUS0_TBI_MODE_SHIFT 4 9626 9627 /* Tx1 :: anaTxAStatus0 :: tx_reset [03:03] */ 9628 #define TX1_ANATXASTATUS0_TX_RESET_MASK 0x0008 9629 #define TX1_ANATXASTATUS0_TX_RESET_ALIGN 0 9630 #define TX1_ANATXASTATUS0_TX_RESET_BITS 1 9631 #define TX1_ANATXASTATUS0_TX_RESET_SHIFT 3 9632 9633 /* Tx1 :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 9634 #define TX1_ANATXASTATUS0_TX_PWRDN_MASK 0x0004 9635 #define TX1_ANATXASTATUS0_TX_PWRDN_ALIGN 0 9636 #define TX1_ANATXASTATUS0_TX_PWRDN_BITS 1 9637 #define TX1_ANATXASTATUS0_TX_PWRDN_SHIFT 2 9638 9639 /* Tx1 :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 9640 #define TX1_ANATXASTATUS0_RLTXFERR_STKY_MASK 0x0002 9641 #define TX1_ANATXASTATUS0_RLTXFERR_STKY_ALIGN 0 9642 #define TX1_ANATXASTATUS0_RLTXFERR_STKY_BITS 1 9643 #define TX1_ANATXASTATUS0_RLTXFERR_STKY_SHIFT 1 9644 9645 /* Tx1 :: anaTxAStatus0 :: txpll_lock [00:00] */ 9646 #define TX1_ANATXASTATUS0_TXPLL_LOCK_MASK 0x0001 9647 #define TX1_ANATXASTATUS0_TXPLL_LOCK_ALIGN 0 9648 #define TX1_ANATXASTATUS0_TXPLL_LOCK_BITS 1 9649 #define TX1_ANATXASTATUS0_TXPLL_LOCK_SHIFT 0 9650 9651 9652 /**************************************************************************** 9653 * Tx1 :: anaTxAControl0 9654 */ 9655 /* Tx1 :: anaTxAControl0 :: reserved0 [15:15] */ 9656 #define TX1_ANATXACONTROL0_RESERVED0_MASK 0x8000 9657 #define TX1_ANATXACONTROL0_RESERVED0_ALIGN 0 9658 #define TX1_ANATXACONTROL0_RESERVED0_BITS 1 9659 #define TX1_ANATXACONTROL0_RESERVED0_SHIFT 15 9660 9661 /* Tx1 :: anaTxAControl0 :: force_txclk [14:14] */ 9662 #define TX1_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 9663 #define TX1_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 9664 #define TX1_ANATXACONTROL0_FORCE_TXCLK_BITS 1 9665 #define TX1_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 9666 9667 /* Tx1 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 9668 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 9669 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 9670 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 9671 #define TX1_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 9672 9673 /* Tx1 :: anaTxAControl0 :: gloopOutEn [12:12] */ 9674 #define TX1_ANATXACONTROL0_GLOOPOUTEN_MASK 0x1000 9675 #define TX1_ANATXACONTROL0_GLOOPOUTEN_ALIGN 0 9676 #define TX1_ANATXACONTROL0_GLOOPOUTEN_BITS 1 9677 #define TX1_ANATXACONTROL0_GLOOPOUTEN_SHIFT 12 9678 9679 /* Tx1 :: anaTxAControl0 :: reserved1 [11:09] */ 9680 #define TX1_ANATXACONTROL0_RESERVED1_MASK 0x0e00 9681 #define TX1_ANATXACONTROL0_RESERVED1_ALIGN 0 9682 #define TX1_ANATXACONTROL0_RESERVED1_BITS 3 9683 #define TX1_ANATXACONTROL0_RESERVED1_SHIFT 9 9684 9685 /* Tx1 :: anaTxAControl0 :: prbs_en [08:08] */ 9686 #define TX1_ANATXACONTROL0_PRBS_EN_MASK 0x0100 9687 #define TX1_ANATXACONTROL0_PRBS_EN_ALIGN 0 9688 #define TX1_ANATXACONTROL0_PRBS_EN_BITS 1 9689 #define TX1_ANATXACONTROL0_PRBS_EN_SHIFT 8 9690 9691 /* Tx1 :: anaTxAControl0 :: pckt_en [07:07] */ 9692 #define TX1_ANATXACONTROL0_PCKT_EN_MASK 0x0080 9693 #define TX1_ANATXACONTROL0_PCKT_EN_ALIGN 0 9694 #define TX1_ANATXACONTROL0_PCKT_EN_BITS 1 9695 #define TX1_ANATXACONTROL0_PCKT_EN_SHIFT 7 9696 9697 /* Tx1 :: anaTxAControl0 :: pckt_strt [06:06] */ 9698 #define TX1_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 9699 #define TX1_ANATXACONTROL0_PCKT_STRT_ALIGN 0 9700 #define TX1_ANATXACONTROL0_PCKT_STRT_BITS 1 9701 #define TX1_ANATXACONTROL0_PCKT_STRT_SHIFT 6 9702 9703 /* Tx1 :: anaTxAControl0 :: txpol_flip [05:05] */ 9704 #define TX1_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 9705 #define TX1_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 9706 #define TX1_ANATXACONTROL0_TXPOL_FLIP_BITS 1 9707 #define TX1_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 9708 9709 /* Tx1 :: anaTxAControl0 :: rtbi_flip [04:04] */ 9710 #define TX1_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 9711 #define TX1_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 9712 #define TX1_ANATXACONTROL0_RTBI_FLIP_BITS 1 9713 #define TX1_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 9714 9715 /* Tx1 :: anaTxAControl0 :: eden_r [03:03] */ 9716 #define TX1_ANATXACONTROL0_EDEN_R_MASK 0x0008 9717 #define TX1_ANATXACONTROL0_EDEN_R_ALIGN 0 9718 #define TX1_ANATXACONTROL0_EDEN_R_BITS 1 9719 #define TX1_ANATXACONTROL0_EDEN_R_SHIFT 3 9720 9721 /* Tx1 :: anaTxAControl0 :: eden_force_r [02:02] */ 9722 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 9723 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 9724 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 9725 #define TX1_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 9726 9727 /* Tx1 :: anaTxAControl0 :: txpat_en [01:01] */ 9728 #define TX1_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 9729 #define TX1_ANATXACONTROL0_TXPAT_EN_ALIGN 0 9730 #define TX1_ANATXACONTROL0_TXPAT_EN_BITS 1 9731 #define TX1_ANATXACONTROL0_TXPAT_EN_SHIFT 1 9732 9733 /* Tx1 :: anaTxAControl0 :: tx_mdata_en [00:00] */ 9734 #define TX1_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 9735 #define TX1_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 9736 #define TX1_ANATXACONTROL0_TX_MDATA_EN_BITS 1 9737 #define TX1_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 9738 9739 9740 /**************************************************************************** 9741 * Tx1 :: anaTxmdata0 9742 */ 9743 /* Tx1 :: anaTxmdata0 :: txTestMuxSel [15:13] */ 9744 #define TX1_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 9745 #define TX1_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 9746 #define TX1_ANATXMDATA0_TXTESTMUXSEL_BITS 3 9747 #define TX1_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 9748 9749 /* Tx1 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 9750 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 9751 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 9752 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 9753 #define TX1_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 9754 9755 /* Tx1 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 9756 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 9757 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 9758 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 9759 #define TX1_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 9760 9761 9762 /**************************************************************************** 9763 * Tx1 :: anaTxmdata1 9764 */ 9765 /* Tx1 :: anaTxmdata1 :: reserved0 [15:10] */ 9766 #define TX1_ANATXMDATA1_RESERVED0_MASK 0xfc00 9767 #define TX1_ANATXMDATA1_RESERVED0_ALIGN 0 9768 #define TX1_ANATXMDATA1_RESERVED0_BITS 6 9769 #define TX1_ANATXMDATA1_RESERVED0_SHIFT 10 9770 9771 /* Tx1 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 9772 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 9773 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 9774 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 9775 #define TX1_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 9776 9777 9778 /**************************************************************************** 9779 * Tx1 :: anaTxAStatus1 9780 */ 9781 /* Tx1 :: anaTxAStatus1 :: tx_id [15:14] */ 9782 #define TX1_ANATXASTATUS1_TX_ID_MASK 0xc000 9783 #define TX1_ANATXASTATUS1_TX_ID_ALIGN 0 9784 #define TX1_ANATXASTATUS1_TX_ID_BITS 2 9785 #define TX1_ANATXASTATUS1_TX_ID_SHIFT 14 9786 9787 /* Tx1 :: anaTxAStatus1 :: reserved0 [13:00] */ 9788 #define TX1_ANATXASTATUS1_RESERVED0_MASK 0x3fff 9789 #define TX1_ANATXASTATUS1_RESERVED0_ALIGN 0 9790 #define TX1_ANATXASTATUS1_RESERVED0_BITS 14 9791 #define TX1_ANATXASTATUS1_RESERVED0_SHIFT 0 9792 9793 9794 /**************************************************************************** 9795 * Tx1 :: anaTxAControl1 9796 */ 9797 /* Tx1 :: anaTxAControl1 :: id2c [15:13] */ 9798 #define TX1_ANATXACONTROL1_ID2C_MASK 0xe000 9799 #define TX1_ANATXACONTROL1_ID2C_ALIGN 0 9800 #define TX1_ANATXACONTROL1_ID2C_BITS 3 9801 #define TX1_ANATXACONTROL1_ID2C_SHIFT 13 9802 9803 /* Tx1 :: anaTxAControl1 :: refl_tx [12:12] */ 9804 #define TX1_ANATXACONTROL1_REFL_TX_MASK 0x1000 9805 #define TX1_ANATXACONTROL1_REFL_TX_ALIGN 0 9806 #define TX1_ANATXACONTROL1_REFL_TX_BITS 1 9807 #define TX1_ANATXACONTROL1_REFL_TX_SHIFT 12 9808 9809 /* Tx1 :: anaTxAControl1 :: refh_tx [11:11] */ 9810 #define TX1_ANATXACONTROL1_REFH_TX_MASK 0x0800 9811 #define TX1_ANATXACONTROL1_REFH_TX_ALIGN 0 9812 #define TX1_ANATXACONTROL1_REFH_TX_BITS 1 9813 #define TX1_ANATXACONTROL1_REFH_TX_SHIFT 11 9814 9815 /* Tx1 :: anaTxAControl1 :: newbias_en [10:10] */ 9816 #define TX1_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 9817 #define TX1_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 9818 #define TX1_ANATXACONTROL1_NEWBIAS_EN_BITS 1 9819 #define TX1_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 9820 9821 /* Tx1 :: anaTxAControl1 :: drivermode [09:09] */ 9822 #define TX1_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 9823 #define TX1_ANATXACONTROL1_DRIVERMODE_ALIGN 0 9824 #define TX1_ANATXACONTROL1_DRIVERMODE_BITS 1 9825 #define TX1_ANATXACONTROL1_DRIVERMODE_SHIFT 9 9826 9827 /* Tx1 :: anaTxAControl1 :: vddr_bgb [08:08] */ 9828 #define TX1_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 9829 #define TX1_ANATXACONTROL1_VDDR_BGB_ALIGN 0 9830 #define TX1_ANATXACONTROL1_VDDR_BGB_BITS 1 9831 #define TX1_ANATXACONTROL1_VDDR_BGB_SHIFT 8 9832 9833 /* Tx1 :: anaTxAControl1 :: ticksel [07:06] */ 9834 #define TX1_ANATXACONTROL1_TICKSEL_MASK 0x00c0 9835 #define TX1_ANATXACONTROL1_TICKSEL_ALIGN 0 9836 #define TX1_ANATXACONTROL1_TICKSEL_BITS 2 9837 #define TX1_ANATXACONTROL1_TICKSEL_SHIFT 6 9838 9839 /* Tx1 :: anaTxAControl1 :: driver_vcm [05:04] */ 9840 #define TX1_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 9841 #define TX1_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 9842 #define TX1_ANATXACONTROL1_DRIVER_VCM_BITS 2 9843 #define TX1_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 9844 9845 /* Tx1 :: anaTxAControl1 :: tx_sel_halfrate [03:03] */ 9846 #define TX1_ANATXACONTROL1_TX_SEL_HALFRATE_MASK 0x0008 9847 #define TX1_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN 0 9848 #define TX1_ANATXACONTROL1_TX_SEL_HALFRATE_BITS 1 9849 #define TX1_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT 3 9850 9851 /* Tx1 :: anaTxAControl1 :: ifullspd [02:00] */ 9852 #define TX1_ANATXACONTROL1_IFULLSPD_MASK 0x0007 9853 #define TX1_ANATXACONTROL1_IFULLSPD_ALIGN 0 9854 #define TX1_ANATXACONTROL1_IFULLSPD_BITS 3 9855 #define TX1_ANATXACONTROL1_IFULLSPD_SHIFT 0 9856 9857 9858 /**************************************************************************** 9859 * Tx1 :: anaTxAControl2 9860 */ 9861 /* Tx1 :: anaTxAControl2 :: icbuf1t [15:14] */ 9862 #define TX1_ANATXACONTROL2_ICBUF1T_MASK 0xc000 9863 #define TX1_ANATXACONTROL2_ICBUF1T_ALIGN 0 9864 #define TX1_ANATXACONTROL2_ICBUF1T_BITS 2 9865 #define TX1_ANATXACONTROL2_ICBUF1T_SHIFT 14 9866 9867 /* Tx1 :: anaTxAControl2 :: icbuf2t [13:11] */ 9868 #define TX1_ANATXACONTROL2_ICBUF2T_MASK 0x3800 9869 #define TX1_ANATXACONTROL2_ICBUF2T_ALIGN 0 9870 #define TX1_ANATXACONTROL2_ICBUF2T_BITS 3 9871 #define TX1_ANATXACONTROL2_ICBUF2T_SHIFT 11 9872 9873 /* Tx1 :: anaTxAControl2 :: imin_predrv [10:10] */ 9874 #define TX1_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 9875 #define TX1_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 9876 #define TX1_ANATXACONTROL2_IMIN_PREDRV_BITS 1 9877 #define TX1_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 9878 9879 /* Tx1 :: anaTxAControl2 :: imax_predrv [09:09] */ 9880 #define TX1_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 9881 #define TX1_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 9882 #define TX1_ANATXACONTROL2_IMAX_PREDRV_BITS 1 9883 #define TX1_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 9884 9885 /* Tx1 :: anaTxAControl2 :: imode_predrv [08:08] */ 9886 #define TX1_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 9887 #define TX1_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 9888 #define TX1_ANATXACONTROL2_IMODE_PREDRV_BITS 1 9889 #define TX1_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 9890 9891 /* Tx1 :: anaTxAControl2 :: i21mux [07:05] */ 9892 #define TX1_ANATXACONTROL2_I21MUX_MASK 0x00e0 9893 #define TX1_ANATXACONTROL2_I21MUX_ALIGN 0 9894 #define TX1_ANATXACONTROL2_I21MUX_BITS 3 9895 #define TX1_ANATXACONTROL2_I21MUX_SHIFT 5 9896 9897 /* Tx1 :: anaTxAControl2 :: imin_drvr [04:04] */ 9898 #define TX1_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 9899 #define TX1_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 9900 #define TX1_ANATXACONTROL2_IMIN_DRVR_BITS 1 9901 #define TX1_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 9902 9903 /* Tx1 :: anaTxAControl2 :: imax_drvr [03:03] */ 9904 #define TX1_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 9905 #define TX1_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 9906 #define TX1_ANATXACONTROL2_IMAX_DRVR_BITS 1 9907 #define TX1_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 9908 9909 /* Tx1 :: anaTxAControl2 :: imode_drvr [02:02] */ 9910 #define TX1_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 9911 #define TX1_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 9912 #define TX1_ANATXACONTROL2_IMODE_DRVR_BITS 1 9913 #define TX1_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 9914 9915 /* Tx1 :: anaTxAControl2 :: reserved0 [01:00] */ 9916 #define TX1_ANATXACONTROL2_RESERVED0_MASK 0x0003 9917 #define TX1_ANATXACONTROL2_RESERVED0_ALIGN 0 9918 #define TX1_ANATXACONTROL2_RESERVED0_BITS 2 9919 #define TX1_ANATXACONTROL2_RESERVED0_SHIFT 0 9920 9921 9922 /**************************************************************************** 9923 * Tx1 :: Tx_OS_Driver 9924 */ 9925 /* Tx1 :: Tx_OS_Driver :: preemphasis_post [15:12] */ 9926 #define TX1_TX_OS_DRIVER_PREEMPHASIS_POST_MASK 0xf000 9927 #define TX1_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN 0 9928 #define TX1_TX_OS_DRIVER_PREEMPHASIS_POST_BITS 4 9929 #define TX1_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT 12 9930 9931 /* Tx1 :: Tx_OS_Driver :: Idriver [11:08] */ 9932 #define TX1_TX_OS_DRIVER_IDRIVER_MASK 0x0f00 9933 #define TX1_TX_OS_DRIVER_IDRIVER_ALIGN 0 9934 #define TX1_TX_OS_DRIVER_IDRIVER_BITS 4 9935 #define TX1_TX_OS_DRIVER_IDRIVER_SHIFT 8 9936 9937 /* Tx1 :: Tx_OS_Driver :: Ipredriver [07:04] */ 9938 #define TX1_TX_OS_DRIVER_IPREDRIVER_MASK 0x00f0 9939 #define TX1_TX_OS_DRIVER_IPREDRIVER_ALIGN 0 9940 #define TX1_TX_OS_DRIVER_IPREDRIVER_BITS 4 9941 #define TX1_TX_OS_DRIVER_IPREDRIVER_SHIFT 4 9942 9943 /* Tx1 :: Tx_OS_Driver :: preemphasis_pre [03:01] */ 9944 #define TX1_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 9945 #define TX1_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN 0 9946 #define TX1_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS 3 9947 #define TX1_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT 1 9948 9949 /* Tx1 :: Tx_OS_Driver :: icbuf1t0 [00:00] */ 9950 #define TX1_TX_OS_DRIVER_ICBUF1T0_MASK 0x0001 9951 #define TX1_TX_OS_DRIVER_ICBUF1T0_ALIGN 0 9952 #define TX1_TX_OS_DRIVER_ICBUF1T0_BITS 1 9953 #define TX1_TX_OS_DRIVER_ICBUF1T0_SHIFT 0 9954 9955 9956 /**************************************************************************** 9957 * Tx1 :: Tx_BR_Driver 9958 */ 9959 /* Tx1 :: Tx_BR_Driver :: preemphasis_post [15:12] */ 9960 #define TX1_TX_BR_DRIVER_PREEMPHASIS_POST_MASK 0xf000 9961 #define TX1_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN 0 9962 #define TX1_TX_BR_DRIVER_PREEMPHASIS_POST_BITS 4 9963 #define TX1_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT 12 9964 9965 /* Tx1 :: Tx_BR_Driver :: Idriver [11:08] */ 9966 #define TX1_TX_BR_DRIVER_IDRIVER_MASK 0x0f00 9967 #define TX1_TX_BR_DRIVER_IDRIVER_ALIGN 0 9968 #define TX1_TX_BR_DRIVER_IDRIVER_BITS 4 9969 #define TX1_TX_BR_DRIVER_IDRIVER_SHIFT 8 9970 9971 /* Tx1 :: Tx_BR_Driver :: Ipredriver [07:04] */ 9972 #define TX1_TX_BR_DRIVER_IPREDRIVER_MASK 0x00f0 9973 #define TX1_TX_BR_DRIVER_IPREDRIVER_ALIGN 0 9974 #define TX1_TX_BR_DRIVER_IPREDRIVER_BITS 4 9975 #define TX1_TX_BR_DRIVER_IPREDRIVER_SHIFT 4 9976 9977 /* Tx1 :: Tx_BR_Driver :: preemphasis_pre [03:01] */ 9978 #define TX1_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 9979 #define TX1_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN 0 9980 #define TX1_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS 3 9981 #define TX1_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT 1 9982 9983 /* Tx1 :: Tx_BR_Driver :: icbuf1t0 [00:00] */ 9984 #define TX1_TX_BR_DRIVER_ICBUF1T0_MASK 0x0001 9985 #define TX1_TX_BR_DRIVER_ICBUF1T0_ALIGN 0 9986 #define TX1_TX_BR_DRIVER_ICBUF1T0_BITS 1 9987 #define TX1_TX_BR_DRIVER_ICBUF1T0_SHIFT 0 9988 9989 9990 /**************************************************************************** 9991 * Hypercore_USER_Tx2 9992 */ 9993 /**************************************************************************** 9994 * Tx2 :: anaTxAStatus0 9995 */ 9996 /* Tx2 :: anaTxAStatus0 :: reserved0 [15:07] */ 9997 #define TX2_ANATXASTATUS0_RESERVED0_MASK 0xff80 9998 #define TX2_ANATXASTATUS0_RESERVED0_ALIGN 0 9999 #define TX2_ANATXASTATUS0_RESERVED0_BITS 9 10000 #define TX2_ANATXASTATUS0_RESERVED0_SHIFT 7 10001 10002 /* Tx2 :: anaTxAStatus0 :: txdisable_ln [06:06] */ 10003 #define TX2_ANATXASTATUS0_TXDISABLE_LN_MASK 0x0040 10004 #define TX2_ANATXASTATUS0_TXDISABLE_LN_ALIGN 0 10005 #define TX2_ANATXASTATUS0_TXDISABLE_LN_BITS 1 10006 #define TX2_ANATXASTATUS0_TXDISABLE_LN_SHIFT 6 10007 10008 /* Tx2 :: anaTxAStatus0 :: txferr_stky [05:05] */ 10009 #define TX2_ANATXASTATUS0_TXFERR_STKY_MASK 0x0020 10010 #define TX2_ANATXASTATUS0_TXFERR_STKY_ALIGN 0 10011 #define TX2_ANATXASTATUS0_TXFERR_STKY_BITS 1 10012 #define TX2_ANATXASTATUS0_TXFERR_STKY_SHIFT 5 10013 10014 /* Tx2 :: anaTxAStatus0 :: tbi_mode [04:04] */ 10015 #define TX2_ANATXASTATUS0_TBI_MODE_MASK 0x0010 10016 #define TX2_ANATXASTATUS0_TBI_MODE_ALIGN 0 10017 #define TX2_ANATXASTATUS0_TBI_MODE_BITS 1 10018 #define TX2_ANATXASTATUS0_TBI_MODE_SHIFT 4 10019 10020 /* Tx2 :: anaTxAStatus0 :: tx_reset [03:03] */ 10021 #define TX2_ANATXASTATUS0_TX_RESET_MASK 0x0008 10022 #define TX2_ANATXASTATUS0_TX_RESET_ALIGN 0 10023 #define TX2_ANATXASTATUS0_TX_RESET_BITS 1 10024 #define TX2_ANATXASTATUS0_TX_RESET_SHIFT 3 10025 10026 /* Tx2 :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 10027 #define TX2_ANATXASTATUS0_TX_PWRDN_MASK 0x0004 10028 #define TX2_ANATXASTATUS0_TX_PWRDN_ALIGN 0 10029 #define TX2_ANATXASTATUS0_TX_PWRDN_BITS 1 10030 #define TX2_ANATXASTATUS0_TX_PWRDN_SHIFT 2 10031 10032 /* Tx2 :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 10033 #define TX2_ANATXASTATUS0_RLTXFERR_STKY_MASK 0x0002 10034 #define TX2_ANATXASTATUS0_RLTXFERR_STKY_ALIGN 0 10035 #define TX2_ANATXASTATUS0_RLTXFERR_STKY_BITS 1 10036 #define TX2_ANATXASTATUS0_RLTXFERR_STKY_SHIFT 1 10037 10038 /* Tx2 :: anaTxAStatus0 :: txpll_lock [00:00] */ 10039 #define TX2_ANATXASTATUS0_TXPLL_LOCK_MASK 0x0001 10040 #define TX2_ANATXASTATUS0_TXPLL_LOCK_ALIGN 0 10041 #define TX2_ANATXASTATUS0_TXPLL_LOCK_BITS 1 10042 #define TX2_ANATXASTATUS0_TXPLL_LOCK_SHIFT 0 10043 10044 10045 /**************************************************************************** 10046 * Tx2 :: anaTxAControl0 10047 */ 10048 /* Tx2 :: anaTxAControl0 :: reserved0 [15:15] */ 10049 #define TX2_ANATXACONTROL0_RESERVED0_MASK 0x8000 10050 #define TX2_ANATXACONTROL0_RESERVED0_ALIGN 0 10051 #define TX2_ANATXACONTROL0_RESERVED0_BITS 1 10052 #define TX2_ANATXACONTROL0_RESERVED0_SHIFT 15 10053 10054 /* Tx2 :: anaTxAControl0 :: force_txclk [14:14] */ 10055 #define TX2_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 10056 #define TX2_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 10057 #define TX2_ANATXACONTROL0_FORCE_TXCLK_BITS 1 10058 #define TX2_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 10059 10060 /* Tx2 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 10061 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 10062 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 10063 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 10064 #define TX2_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 10065 10066 /* Tx2 :: anaTxAControl0 :: gloopOutEn [12:12] */ 10067 #define TX2_ANATXACONTROL0_GLOOPOUTEN_MASK 0x1000 10068 #define TX2_ANATXACONTROL0_GLOOPOUTEN_ALIGN 0 10069 #define TX2_ANATXACONTROL0_GLOOPOUTEN_BITS 1 10070 #define TX2_ANATXACONTROL0_GLOOPOUTEN_SHIFT 12 10071 10072 /* Tx2 :: anaTxAControl0 :: reserved1 [11:09] */ 10073 #define TX2_ANATXACONTROL0_RESERVED1_MASK 0x0e00 10074 #define TX2_ANATXACONTROL0_RESERVED1_ALIGN 0 10075 #define TX2_ANATXACONTROL0_RESERVED1_BITS 3 10076 #define TX2_ANATXACONTROL0_RESERVED1_SHIFT 9 10077 10078 /* Tx2 :: anaTxAControl0 :: prbs_en [08:08] */ 10079 #define TX2_ANATXACONTROL0_PRBS_EN_MASK 0x0100 10080 #define TX2_ANATXACONTROL0_PRBS_EN_ALIGN 0 10081 #define TX2_ANATXACONTROL0_PRBS_EN_BITS 1 10082 #define TX2_ANATXACONTROL0_PRBS_EN_SHIFT 8 10083 10084 /* Tx2 :: anaTxAControl0 :: pckt_en [07:07] */ 10085 #define TX2_ANATXACONTROL0_PCKT_EN_MASK 0x0080 10086 #define TX2_ANATXACONTROL0_PCKT_EN_ALIGN 0 10087 #define TX2_ANATXACONTROL0_PCKT_EN_BITS 1 10088 #define TX2_ANATXACONTROL0_PCKT_EN_SHIFT 7 10089 10090 /* Tx2 :: anaTxAControl0 :: pckt_strt [06:06] */ 10091 #define TX2_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 10092 #define TX2_ANATXACONTROL0_PCKT_STRT_ALIGN 0 10093 #define TX2_ANATXACONTROL0_PCKT_STRT_BITS 1 10094 #define TX2_ANATXACONTROL0_PCKT_STRT_SHIFT 6 10095 10096 /* Tx2 :: anaTxAControl0 :: txpol_flip [05:05] */ 10097 #define TX2_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 10098 #define TX2_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 10099 #define TX2_ANATXACONTROL0_TXPOL_FLIP_BITS 1 10100 #define TX2_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 10101 10102 /* Tx2 :: anaTxAControl0 :: rtbi_flip [04:04] */ 10103 #define TX2_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 10104 #define TX2_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 10105 #define TX2_ANATXACONTROL0_RTBI_FLIP_BITS 1 10106 #define TX2_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 10107 10108 /* Tx2 :: anaTxAControl0 :: eden_r [03:03] */ 10109 #define TX2_ANATXACONTROL0_EDEN_R_MASK 0x0008 10110 #define TX2_ANATXACONTROL0_EDEN_R_ALIGN 0 10111 #define TX2_ANATXACONTROL0_EDEN_R_BITS 1 10112 #define TX2_ANATXACONTROL0_EDEN_R_SHIFT 3 10113 10114 /* Tx2 :: anaTxAControl0 :: eden_force_r [02:02] */ 10115 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 10116 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 10117 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 10118 #define TX2_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 10119 10120 /* Tx2 :: anaTxAControl0 :: txpat_en [01:01] */ 10121 #define TX2_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 10122 #define TX2_ANATXACONTROL0_TXPAT_EN_ALIGN 0 10123 #define TX2_ANATXACONTROL0_TXPAT_EN_BITS 1 10124 #define TX2_ANATXACONTROL0_TXPAT_EN_SHIFT 1 10125 10126 /* Tx2 :: anaTxAControl0 :: tx_mdata_en [00:00] */ 10127 #define TX2_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 10128 #define TX2_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 10129 #define TX2_ANATXACONTROL0_TX_MDATA_EN_BITS 1 10130 #define TX2_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 10131 10132 10133 /**************************************************************************** 10134 * Tx2 :: anaTxmdata0 10135 */ 10136 /* Tx2 :: anaTxmdata0 :: txTestMuxSel [15:13] */ 10137 #define TX2_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 10138 #define TX2_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 10139 #define TX2_ANATXMDATA0_TXTESTMUXSEL_BITS 3 10140 #define TX2_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 10141 10142 /* Tx2 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 10143 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 10144 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 10145 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 10146 #define TX2_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 10147 10148 /* Tx2 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 10149 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 10150 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 10151 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 10152 #define TX2_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 10153 10154 10155 /**************************************************************************** 10156 * Tx2 :: anaTxmdata1 10157 */ 10158 /* Tx2 :: anaTxmdata1 :: reserved0 [15:10] */ 10159 #define TX2_ANATXMDATA1_RESERVED0_MASK 0xfc00 10160 #define TX2_ANATXMDATA1_RESERVED0_ALIGN 0 10161 #define TX2_ANATXMDATA1_RESERVED0_BITS 6 10162 #define TX2_ANATXMDATA1_RESERVED0_SHIFT 10 10163 10164 /* Tx2 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 10165 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 10166 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 10167 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 10168 #define TX2_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 10169 10170 10171 /**************************************************************************** 10172 * Tx2 :: anaTxAStatus1 10173 */ 10174 /* Tx2 :: anaTxAStatus1 :: tx_id [15:14] */ 10175 #define TX2_ANATXASTATUS1_TX_ID_MASK 0xc000 10176 #define TX2_ANATXASTATUS1_TX_ID_ALIGN 0 10177 #define TX2_ANATXASTATUS1_TX_ID_BITS 2 10178 #define TX2_ANATXASTATUS1_TX_ID_SHIFT 14 10179 10180 /* Tx2 :: anaTxAStatus1 :: reserved0 [13:00] */ 10181 #define TX2_ANATXASTATUS1_RESERVED0_MASK 0x3fff 10182 #define TX2_ANATXASTATUS1_RESERVED0_ALIGN 0 10183 #define TX2_ANATXASTATUS1_RESERVED0_BITS 14 10184 #define TX2_ANATXASTATUS1_RESERVED0_SHIFT 0 10185 10186 10187 /**************************************************************************** 10188 * Tx2 :: anaTxAControl1 10189 */ 10190 /* Tx2 :: anaTxAControl1 :: id2c [15:13] */ 10191 #define TX2_ANATXACONTROL1_ID2C_MASK 0xe000 10192 #define TX2_ANATXACONTROL1_ID2C_ALIGN 0 10193 #define TX2_ANATXACONTROL1_ID2C_BITS 3 10194 #define TX2_ANATXACONTROL1_ID2C_SHIFT 13 10195 10196 /* Tx2 :: anaTxAControl1 :: refl_tx [12:12] */ 10197 #define TX2_ANATXACONTROL1_REFL_TX_MASK 0x1000 10198 #define TX2_ANATXACONTROL1_REFL_TX_ALIGN 0 10199 #define TX2_ANATXACONTROL1_REFL_TX_BITS 1 10200 #define TX2_ANATXACONTROL1_REFL_TX_SHIFT 12 10201 10202 /* Tx2 :: anaTxAControl1 :: refh_tx [11:11] */ 10203 #define TX2_ANATXACONTROL1_REFH_TX_MASK 0x0800 10204 #define TX2_ANATXACONTROL1_REFH_TX_ALIGN 0 10205 #define TX2_ANATXACONTROL1_REFH_TX_BITS 1 10206 #define TX2_ANATXACONTROL1_REFH_TX_SHIFT 11 10207 10208 /* Tx2 :: anaTxAControl1 :: newbias_en [10:10] */ 10209 #define TX2_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 10210 #define TX2_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 10211 #define TX2_ANATXACONTROL1_NEWBIAS_EN_BITS 1 10212 #define TX2_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 10213 10214 /* Tx2 :: anaTxAControl1 :: drivermode [09:09] */ 10215 #define TX2_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 10216 #define TX2_ANATXACONTROL1_DRIVERMODE_ALIGN 0 10217 #define TX2_ANATXACONTROL1_DRIVERMODE_BITS 1 10218 #define TX2_ANATXACONTROL1_DRIVERMODE_SHIFT 9 10219 10220 /* Tx2 :: anaTxAControl1 :: vddr_bgb [08:08] */ 10221 #define TX2_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 10222 #define TX2_ANATXACONTROL1_VDDR_BGB_ALIGN 0 10223 #define TX2_ANATXACONTROL1_VDDR_BGB_BITS 1 10224 #define TX2_ANATXACONTROL1_VDDR_BGB_SHIFT 8 10225 10226 /* Tx2 :: anaTxAControl1 :: ticksel [07:06] */ 10227 #define TX2_ANATXACONTROL1_TICKSEL_MASK 0x00c0 10228 #define TX2_ANATXACONTROL1_TICKSEL_ALIGN 0 10229 #define TX2_ANATXACONTROL1_TICKSEL_BITS 2 10230 #define TX2_ANATXACONTROL1_TICKSEL_SHIFT 6 10231 10232 /* Tx2 :: anaTxAControl1 :: driver_vcm [05:04] */ 10233 #define TX2_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 10234 #define TX2_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 10235 #define TX2_ANATXACONTROL1_DRIVER_VCM_BITS 2 10236 #define TX2_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 10237 10238 /* Tx2 :: anaTxAControl1 :: tx_sel_halfrate [03:03] */ 10239 #define TX2_ANATXACONTROL1_TX_SEL_HALFRATE_MASK 0x0008 10240 #define TX2_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN 0 10241 #define TX2_ANATXACONTROL1_TX_SEL_HALFRATE_BITS 1 10242 #define TX2_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT 3 10243 10244 /* Tx2 :: anaTxAControl1 :: ifullspd [02:00] */ 10245 #define TX2_ANATXACONTROL1_IFULLSPD_MASK 0x0007 10246 #define TX2_ANATXACONTROL1_IFULLSPD_ALIGN 0 10247 #define TX2_ANATXACONTROL1_IFULLSPD_BITS 3 10248 #define TX2_ANATXACONTROL1_IFULLSPD_SHIFT 0 10249 10250 10251 /**************************************************************************** 10252 * Tx2 :: anaTxAControl2 10253 */ 10254 /* Tx2 :: anaTxAControl2 :: icbuf1t [15:14] */ 10255 #define TX2_ANATXACONTROL2_ICBUF1T_MASK 0xc000 10256 #define TX2_ANATXACONTROL2_ICBUF1T_ALIGN 0 10257 #define TX2_ANATXACONTROL2_ICBUF1T_BITS 2 10258 #define TX2_ANATXACONTROL2_ICBUF1T_SHIFT 14 10259 10260 /* Tx2 :: anaTxAControl2 :: icbuf2t [13:11] */ 10261 #define TX2_ANATXACONTROL2_ICBUF2T_MASK 0x3800 10262 #define TX2_ANATXACONTROL2_ICBUF2T_ALIGN 0 10263 #define TX2_ANATXACONTROL2_ICBUF2T_BITS 3 10264 #define TX2_ANATXACONTROL2_ICBUF2T_SHIFT 11 10265 10266 /* Tx2 :: anaTxAControl2 :: imin_predrv [10:10] */ 10267 #define TX2_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 10268 #define TX2_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 10269 #define TX2_ANATXACONTROL2_IMIN_PREDRV_BITS 1 10270 #define TX2_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 10271 10272 /* Tx2 :: anaTxAControl2 :: imax_predrv [09:09] */ 10273 #define TX2_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 10274 #define TX2_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 10275 #define TX2_ANATXACONTROL2_IMAX_PREDRV_BITS 1 10276 #define TX2_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 10277 10278 /* Tx2 :: anaTxAControl2 :: imode_predrv [08:08] */ 10279 #define TX2_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 10280 #define TX2_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 10281 #define TX2_ANATXACONTROL2_IMODE_PREDRV_BITS 1 10282 #define TX2_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 10283 10284 /* Tx2 :: anaTxAControl2 :: i21mux [07:05] */ 10285 #define TX2_ANATXACONTROL2_I21MUX_MASK 0x00e0 10286 #define TX2_ANATXACONTROL2_I21MUX_ALIGN 0 10287 #define TX2_ANATXACONTROL2_I21MUX_BITS 3 10288 #define TX2_ANATXACONTROL2_I21MUX_SHIFT 5 10289 10290 /* Tx2 :: anaTxAControl2 :: imin_drvr [04:04] */ 10291 #define TX2_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 10292 #define TX2_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 10293 #define TX2_ANATXACONTROL2_IMIN_DRVR_BITS 1 10294 #define TX2_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 10295 10296 /* Tx2 :: anaTxAControl2 :: imax_drvr [03:03] */ 10297 #define TX2_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 10298 #define TX2_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 10299 #define TX2_ANATXACONTROL2_IMAX_DRVR_BITS 1 10300 #define TX2_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 10301 10302 /* Tx2 :: anaTxAControl2 :: imode_drvr [02:02] */ 10303 #define TX2_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 10304 #define TX2_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 10305 #define TX2_ANATXACONTROL2_IMODE_DRVR_BITS 1 10306 #define TX2_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 10307 10308 /* Tx2 :: anaTxAControl2 :: reserved0 [01:00] */ 10309 #define TX2_ANATXACONTROL2_RESERVED0_MASK 0x0003 10310 #define TX2_ANATXACONTROL2_RESERVED0_ALIGN 0 10311 #define TX2_ANATXACONTROL2_RESERVED0_BITS 2 10312 #define TX2_ANATXACONTROL2_RESERVED0_SHIFT 0 10313 10314 10315 /**************************************************************************** 10316 * Tx2 :: Tx_OS_Driver 10317 */ 10318 /* Tx2 :: Tx_OS_Driver :: preemphasis_post [15:12] */ 10319 #define TX2_TX_OS_DRIVER_PREEMPHASIS_POST_MASK 0xf000 10320 #define TX2_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN 0 10321 #define TX2_TX_OS_DRIVER_PREEMPHASIS_POST_BITS 4 10322 #define TX2_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT 12 10323 10324 /* Tx2 :: Tx_OS_Driver :: Idriver [11:08] */ 10325 #define TX2_TX_OS_DRIVER_IDRIVER_MASK 0x0f00 10326 #define TX2_TX_OS_DRIVER_IDRIVER_ALIGN 0 10327 #define TX2_TX_OS_DRIVER_IDRIVER_BITS 4 10328 #define TX2_TX_OS_DRIVER_IDRIVER_SHIFT 8 10329 10330 /* Tx2 :: Tx_OS_Driver :: Ipredriver [07:04] */ 10331 #define TX2_TX_OS_DRIVER_IPREDRIVER_MASK 0x00f0 10332 #define TX2_TX_OS_DRIVER_IPREDRIVER_ALIGN 0 10333 #define TX2_TX_OS_DRIVER_IPREDRIVER_BITS 4 10334 #define TX2_TX_OS_DRIVER_IPREDRIVER_SHIFT 4 10335 10336 /* Tx2 :: Tx_OS_Driver :: preemphasis_pre [03:01] */ 10337 #define TX2_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 10338 #define TX2_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN 0 10339 #define TX2_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS 3 10340 #define TX2_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT 1 10341 10342 /* Tx2 :: Tx_OS_Driver :: icbuf1t0 [00:00] */ 10343 #define TX2_TX_OS_DRIVER_ICBUF1T0_MASK 0x0001 10344 #define TX2_TX_OS_DRIVER_ICBUF1T0_ALIGN 0 10345 #define TX2_TX_OS_DRIVER_ICBUF1T0_BITS 1 10346 #define TX2_TX_OS_DRIVER_ICBUF1T0_SHIFT 0 10347 10348 10349 /**************************************************************************** 10350 * Tx2 :: Tx_BR_Driver 10351 */ 10352 /* Tx2 :: Tx_BR_Driver :: preemphasis_post [15:12] */ 10353 #define TX2_TX_BR_DRIVER_PREEMPHASIS_POST_MASK 0xf000 10354 #define TX2_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN 0 10355 #define TX2_TX_BR_DRIVER_PREEMPHASIS_POST_BITS 4 10356 #define TX2_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT 12 10357 10358 /* Tx2 :: Tx_BR_Driver :: Idriver [11:08] */ 10359 #define TX2_TX_BR_DRIVER_IDRIVER_MASK 0x0f00 10360 #define TX2_TX_BR_DRIVER_IDRIVER_ALIGN 0 10361 #define TX2_TX_BR_DRIVER_IDRIVER_BITS 4 10362 #define TX2_TX_BR_DRIVER_IDRIVER_SHIFT 8 10363 10364 /* Tx2 :: Tx_BR_Driver :: Ipredriver [07:04] */ 10365 #define TX2_TX_BR_DRIVER_IPREDRIVER_MASK 0x00f0 10366 #define TX2_TX_BR_DRIVER_IPREDRIVER_ALIGN 0 10367 #define TX2_TX_BR_DRIVER_IPREDRIVER_BITS 4 10368 #define TX2_TX_BR_DRIVER_IPREDRIVER_SHIFT 4 10369 10370 /* Tx2 :: Tx_BR_Driver :: preemphasis_pre [03:01] */ 10371 #define TX2_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 10372 #define TX2_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN 0 10373 #define TX2_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS 3 10374 #define TX2_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT 1 10375 10376 /* Tx2 :: Tx_BR_Driver :: icbuf1t0 [00:00] */ 10377 #define TX2_TX_BR_DRIVER_ICBUF1T0_MASK 0x0001 10378 #define TX2_TX_BR_DRIVER_ICBUF1T0_ALIGN 0 10379 #define TX2_TX_BR_DRIVER_ICBUF1T0_BITS 1 10380 #define TX2_TX_BR_DRIVER_ICBUF1T0_SHIFT 0 10381 10382 10383 /**************************************************************************** 10384 * Hypercore_USER_Tx3 10385 */ 10386 /**************************************************************************** 10387 * Tx3 :: anaTxAStatus0 10388 */ 10389 /* Tx3 :: anaTxAStatus0 :: reserved0 [15:07] */ 10390 #define TX3_ANATXASTATUS0_RESERVED0_MASK 0xff80 10391 #define TX3_ANATXASTATUS0_RESERVED0_ALIGN 0 10392 #define TX3_ANATXASTATUS0_RESERVED0_BITS 9 10393 #define TX3_ANATXASTATUS0_RESERVED0_SHIFT 7 10394 10395 /* Tx3 :: anaTxAStatus0 :: txdisable_ln [06:06] */ 10396 #define TX3_ANATXASTATUS0_TXDISABLE_LN_MASK 0x0040 10397 #define TX3_ANATXASTATUS0_TXDISABLE_LN_ALIGN 0 10398 #define TX3_ANATXASTATUS0_TXDISABLE_LN_BITS 1 10399 #define TX3_ANATXASTATUS0_TXDISABLE_LN_SHIFT 6 10400 10401 /* Tx3 :: anaTxAStatus0 :: txferr_stky [05:05] */ 10402 #define TX3_ANATXASTATUS0_TXFERR_STKY_MASK 0x0020 10403 #define TX3_ANATXASTATUS0_TXFERR_STKY_ALIGN 0 10404 #define TX3_ANATXASTATUS0_TXFERR_STKY_BITS 1 10405 #define TX3_ANATXASTATUS0_TXFERR_STKY_SHIFT 5 10406 10407 /* Tx3 :: anaTxAStatus0 :: tbi_mode [04:04] */ 10408 #define TX3_ANATXASTATUS0_TBI_MODE_MASK 0x0010 10409 #define TX3_ANATXASTATUS0_TBI_MODE_ALIGN 0 10410 #define TX3_ANATXASTATUS0_TBI_MODE_BITS 1 10411 #define TX3_ANATXASTATUS0_TBI_MODE_SHIFT 4 10412 10413 /* Tx3 :: anaTxAStatus0 :: tx_reset [03:03] */ 10414 #define TX3_ANATXASTATUS0_TX_RESET_MASK 0x0008 10415 #define TX3_ANATXASTATUS0_TX_RESET_ALIGN 0 10416 #define TX3_ANATXASTATUS0_TX_RESET_BITS 1 10417 #define TX3_ANATXASTATUS0_TX_RESET_SHIFT 3 10418 10419 /* Tx3 :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 10420 #define TX3_ANATXASTATUS0_TX_PWRDN_MASK 0x0004 10421 #define TX3_ANATXASTATUS0_TX_PWRDN_ALIGN 0 10422 #define TX3_ANATXASTATUS0_TX_PWRDN_BITS 1 10423 #define TX3_ANATXASTATUS0_TX_PWRDN_SHIFT 2 10424 10425 /* Tx3 :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 10426 #define TX3_ANATXASTATUS0_RLTXFERR_STKY_MASK 0x0002 10427 #define TX3_ANATXASTATUS0_RLTXFERR_STKY_ALIGN 0 10428 #define TX3_ANATXASTATUS0_RLTXFERR_STKY_BITS 1 10429 #define TX3_ANATXASTATUS0_RLTXFERR_STKY_SHIFT 1 10430 10431 /* Tx3 :: anaTxAStatus0 :: txpll_lock [00:00] */ 10432 #define TX3_ANATXASTATUS0_TXPLL_LOCK_MASK 0x0001 10433 #define TX3_ANATXASTATUS0_TXPLL_LOCK_ALIGN 0 10434 #define TX3_ANATXASTATUS0_TXPLL_LOCK_BITS 1 10435 #define TX3_ANATXASTATUS0_TXPLL_LOCK_SHIFT 0 10436 10437 10438 /**************************************************************************** 10439 * Tx3 :: anaTxAControl0 10440 */ 10441 /* Tx3 :: anaTxAControl0 :: reserved0 [15:15] */ 10442 #define TX3_ANATXACONTROL0_RESERVED0_MASK 0x8000 10443 #define TX3_ANATXACONTROL0_RESERVED0_ALIGN 0 10444 #define TX3_ANATXACONTROL0_RESERVED0_BITS 1 10445 #define TX3_ANATXACONTROL0_RESERVED0_SHIFT 15 10446 10447 /* Tx3 :: anaTxAControl0 :: force_txclk [14:14] */ 10448 #define TX3_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 10449 #define TX3_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 10450 #define TX3_ANATXACONTROL0_FORCE_TXCLK_BITS 1 10451 #define TX3_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 10452 10453 /* Tx3 :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 10454 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 10455 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 10456 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 10457 #define TX3_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 10458 10459 /* Tx3 :: anaTxAControl0 :: gloopOutEn [12:12] */ 10460 #define TX3_ANATXACONTROL0_GLOOPOUTEN_MASK 0x1000 10461 #define TX3_ANATXACONTROL0_GLOOPOUTEN_ALIGN 0 10462 #define TX3_ANATXACONTROL0_GLOOPOUTEN_BITS 1 10463 #define TX3_ANATXACONTROL0_GLOOPOUTEN_SHIFT 12 10464 10465 /* Tx3 :: anaTxAControl0 :: reserved1 [11:09] */ 10466 #define TX3_ANATXACONTROL0_RESERVED1_MASK 0x0e00 10467 #define TX3_ANATXACONTROL0_RESERVED1_ALIGN 0 10468 #define TX3_ANATXACONTROL0_RESERVED1_BITS 3 10469 #define TX3_ANATXACONTROL0_RESERVED1_SHIFT 9 10470 10471 /* Tx3 :: anaTxAControl0 :: prbs_en [08:08] */ 10472 #define TX3_ANATXACONTROL0_PRBS_EN_MASK 0x0100 10473 #define TX3_ANATXACONTROL0_PRBS_EN_ALIGN 0 10474 #define TX3_ANATXACONTROL0_PRBS_EN_BITS 1 10475 #define TX3_ANATXACONTROL0_PRBS_EN_SHIFT 8 10476 10477 /* Tx3 :: anaTxAControl0 :: pckt_en [07:07] */ 10478 #define TX3_ANATXACONTROL0_PCKT_EN_MASK 0x0080 10479 #define TX3_ANATXACONTROL0_PCKT_EN_ALIGN 0 10480 #define TX3_ANATXACONTROL0_PCKT_EN_BITS 1 10481 #define TX3_ANATXACONTROL0_PCKT_EN_SHIFT 7 10482 10483 /* Tx3 :: anaTxAControl0 :: pckt_strt [06:06] */ 10484 #define TX3_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 10485 #define TX3_ANATXACONTROL0_PCKT_STRT_ALIGN 0 10486 #define TX3_ANATXACONTROL0_PCKT_STRT_BITS 1 10487 #define TX3_ANATXACONTROL0_PCKT_STRT_SHIFT 6 10488 10489 /* Tx3 :: anaTxAControl0 :: txpol_flip [05:05] */ 10490 #define TX3_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 10491 #define TX3_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 10492 #define TX3_ANATXACONTROL0_TXPOL_FLIP_BITS 1 10493 #define TX3_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 10494 10495 /* Tx3 :: anaTxAControl0 :: rtbi_flip [04:04] */ 10496 #define TX3_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 10497 #define TX3_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 10498 #define TX3_ANATXACONTROL0_RTBI_FLIP_BITS 1 10499 #define TX3_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 10500 10501 /* Tx3 :: anaTxAControl0 :: eden_r [03:03] */ 10502 #define TX3_ANATXACONTROL0_EDEN_R_MASK 0x0008 10503 #define TX3_ANATXACONTROL0_EDEN_R_ALIGN 0 10504 #define TX3_ANATXACONTROL0_EDEN_R_BITS 1 10505 #define TX3_ANATXACONTROL0_EDEN_R_SHIFT 3 10506 10507 /* Tx3 :: anaTxAControl0 :: eden_force_r [02:02] */ 10508 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 10509 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 10510 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 10511 #define TX3_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 10512 10513 /* Tx3 :: anaTxAControl0 :: txpat_en [01:01] */ 10514 #define TX3_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 10515 #define TX3_ANATXACONTROL0_TXPAT_EN_ALIGN 0 10516 #define TX3_ANATXACONTROL0_TXPAT_EN_BITS 1 10517 #define TX3_ANATXACONTROL0_TXPAT_EN_SHIFT 1 10518 10519 /* Tx3 :: anaTxAControl0 :: tx_mdata_en [00:00] */ 10520 #define TX3_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 10521 #define TX3_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 10522 #define TX3_ANATXACONTROL0_TX_MDATA_EN_BITS 1 10523 #define TX3_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 10524 10525 10526 /**************************************************************************** 10527 * Tx3 :: anaTxmdata0 10528 */ 10529 /* Tx3 :: anaTxmdata0 :: txTestMuxSel [15:13] */ 10530 #define TX3_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 10531 #define TX3_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 10532 #define TX3_ANATXMDATA0_TXTESTMUXSEL_BITS 3 10533 #define TX3_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 10534 10535 /* Tx3 :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 10536 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 10537 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 10538 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 10539 #define TX3_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 10540 10541 /* Tx3 :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 10542 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 10543 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 10544 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 10545 #define TX3_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 10546 10547 10548 /**************************************************************************** 10549 * Tx3 :: anaTxmdata1 10550 */ 10551 /* Tx3 :: anaTxmdata1 :: reserved0 [15:10] */ 10552 #define TX3_ANATXMDATA1_RESERVED0_MASK 0xfc00 10553 #define TX3_ANATXMDATA1_RESERVED0_ALIGN 0 10554 #define TX3_ANATXMDATA1_RESERVED0_BITS 6 10555 #define TX3_ANATXMDATA1_RESERVED0_SHIFT 10 10556 10557 /* Tx3 :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 10558 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 10559 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 10560 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 10561 #define TX3_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 10562 10563 10564 /**************************************************************************** 10565 * Tx3 :: anaTxAStatus1 10566 */ 10567 /* Tx3 :: anaTxAStatus1 :: tx_id [15:14] */ 10568 #define TX3_ANATXASTATUS1_TX_ID_MASK 0xc000 10569 #define TX3_ANATXASTATUS1_TX_ID_ALIGN 0 10570 #define TX3_ANATXASTATUS1_TX_ID_BITS 2 10571 #define TX3_ANATXASTATUS1_TX_ID_SHIFT 14 10572 10573 /* Tx3 :: anaTxAStatus1 :: reserved0 [13:00] */ 10574 #define TX3_ANATXASTATUS1_RESERVED0_MASK 0x3fff 10575 #define TX3_ANATXASTATUS1_RESERVED0_ALIGN 0 10576 #define TX3_ANATXASTATUS1_RESERVED0_BITS 14 10577 #define TX3_ANATXASTATUS1_RESERVED0_SHIFT 0 10578 10579 10580 /**************************************************************************** 10581 * Tx3 :: anaTxAControl1 10582 */ 10583 /* Tx3 :: anaTxAControl1 :: id2c [15:13] */ 10584 #define TX3_ANATXACONTROL1_ID2C_MASK 0xe000 10585 #define TX3_ANATXACONTROL1_ID2C_ALIGN 0 10586 #define TX3_ANATXACONTROL1_ID2C_BITS 3 10587 #define TX3_ANATXACONTROL1_ID2C_SHIFT 13 10588 10589 /* Tx3 :: anaTxAControl1 :: refl_tx [12:12] */ 10590 #define TX3_ANATXACONTROL1_REFL_TX_MASK 0x1000 10591 #define TX3_ANATXACONTROL1_REFL_TX_ALIGN 0 10592 #define TX3_ANATXACONTROL1_REFL_TX_BITS 1 10593 #define TX3_ANATXACONTROL1_REFL_TX_SHIFT 12 10594 10595 /* Tx3 :: anaTxAControl1 :: refh_tx [11:11] */ 10596 #define TX3_ANATXACONTROL1_REFH_TX_MASK 0x0800 10597 #define TX3_ANATXACONTROL1_REFH_TX_ALIGN 0 10598 #define TX3_ANATXACONTROL1_REFH_TX_BITS 1 10599 #define TX3_ANATXACONTROL1_REFH_TX_SHIFT 11 10600 10601 /* Tx3 :: anaTxAControl1 :: newbias_en [10:10] */ 10602 #define TX3_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 10603 #define TX3_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 10604 #define TX3_ANATXACONTROL1_NEWBIAS_EN_BITS 1 10605 #define TX3_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 10606 10607 /* Tx3 :: anaTxAControl1 :: drivermode [09:09] */ 10608 #define TX3_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 10609 #define TX3_ANATXACONTROL1_DRIVERMODE_ALIGN 0 10610 #define TX3_ANATXACONTROL1_DRIVERMODE_BITS 1 10611 #define TX3_ANATXACONTROL1_DRIVERMODE_SHIFT 9 10612 10613 /* Tx3 :: anaTxAControl1 :: vddr_bgb [08:08] */ 10614 #define TX3_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 10615 #define TX3_ANATXACONTROL1_VDDR_BGB_ALIGN 0 10616 #define TX3_ANATXACONTROL1_VDDR_BGB_BITS 1 10617 #define TX3_ANATXACONTROL1_VDDR_BGB_SHIFT 8 10618 10619 /* Tx3 :: anaTxAControl1 :: ticksel [07:06] */ 10620 #define TX3_ANATXACONTROL1_TICKSEL_MASK 0x00c0 10621 #define TX3_ANATXACONTROL1_TICKSEL_ALIGN 0 10622 #define TX3_ANATXACONTROL1_TICKSEL_BITS 2 10623 #define TX3_ANATXACONTROL1_TICKSEL_SHIFT 6 10624 10625 /* Tx3 :: anaTxAControl1 :: driver_vcm [05:04] */ 10626 #define TX3_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 10627 #define TX3_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 10628 #define TX3_ANATXACONTROL1_DRIVER_VCM_BITS 2 10629 #define TX3_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 10630 10631 /* Tx3 :: anaTxAControl1 :: tx_sel_halfrate [03:03] */ 10632 #define TX3_ANATXACONTROL1_TX_SEL_HALFRATE_MASK 0x0008 10633 #define TX3_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN 0 10634 #define TX3_ANATXACONTROL1_TX_SEL_HALFRATE_BITS 1 10635 #define TX3_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT 3 10636 10637 /* Tx3 :: anaTxAControl1 :: ifullspd [02:00] */ 10638 #define TX3_ANATXACONTROL1_IFULLSPD_MASK 0x0007 10639 #define TX3_ANATXACONTROL1_IFULLSPD_ALIGN 0 10640 #define TX3_ANATXACONTROL1_IFULLSPD_BITS 3 10641 #define TX3_ANATXACONTROL1_IFULLSPD_SHIFT 0 10642 10643 10644 /**************************************************************************** 10645 * Tx3 :: anaTxAControl2 10646 */ 10647 /* Tx3 :: anaTxAControl2 :: icbuf1t [15:14] */ 10648 #define TX3_ANATXACONTROL2_ICBUF1T_MASK 0xc000 10649 #define TX3_ANATXACONTROL2_ICBUF1T_ALIGN 0 10650 #define TX3_ANATXACONTROL2_ICBUF1T_BITS 2 10651 #define TX3_ANATXACONTROL2_ICBUF1T_SHIFT 14 10652 10653 /* Tx3 :: anaTxAControl2 :: icbuf2t [13:11] */ 10654 #define TX3_ANATXACONTROL2_ICBUF2T_MASK 0x3800 10655 #define TX3_ANATXACONTROL2_ICBUF2T_ALIGN 0 10656 #define TX3_ANATXACONTROL2_ICBUF2T_BITS 3 10657 #define TX3_ANATXACONTROL2_ICBUF2T_SHIFT 11 10658 10659 /* Tx3 :: anaTxAControl2 :: imin_predrv [10:10] */ 10660 #define TX3_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 10661 #define TX3_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 10662 #define TX3_ANATXACONTROL2_IMIN_PREDRV_BITS 1 10663 #define TX3_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 10664 10665 /* Tx3 :: anaTxAControl2 :: imax_predrv [09:09] */ 10666 #define TX3_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 10667 #define TX3_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 10668 #define TX3_ANATXACONTROL2_IMAX_PREDRV_BITS 1 10669 #define TX3_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 10670 10671 /* Tx3 :: anaTxAControl2 :: imode_predrv [08:08] */ 10672 #define TX3_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 10673 #define TX3_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 10674 #define TX3_ANATXACONTROL2_IMODE_PREDRV_BITS 1 10675 #define TX3_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 10676 10677 /* Tx3 :: anaTxAControl2 :: i21mux [07:05] */ 10678 #define TX3_ANATXACONTROL2_I21MUX_MASK 0x00e0 10679 #define TX3_ANATXACONTROL2_I21MUX_ALIGN 0 10680 #define TX3_ANATXACONTROL2_I21MUX_BITS 3 10681 #define TX3_ANATXACONTROL2_I21MUX_SHIFT 5 10682 10683 /* Tx3 :: anaTxAControl2 :: imin_drvr [04:04] */ 10684 #define TX3_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 10685 #define TX3_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 10686 #define TX3_ANATXACONTROL2_IMIN_DRVR_BITS 1 10687 #define TX3_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 10688 10689 /* Tx3 :: anaTxAControl2 :: imax_drvr [03:03] */ 10690 #define TX3_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 10691 #define TX3_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 10692 #define TX3_ANATXACONTROL2_IMAX_DRVR_BITS 1 10693 #define TX3_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 10694 10695 /* Tx3 :: anaTxAControl2 :: imode_drvr [02:02] */ 10696 #define TX3_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 10697 #define TX3_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 10698 #define TX3_ANATXACONTROL2_IMODE_DRVR_BITS 1 10699 #define TX3_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 10700 10701 /* Tx3 :: anaTxAControl2 :: reserved0 [01:00] */ 10702 #define TX3_ANATXACONTROL2_RESERVED0_MASK 0x0003 10703 #define TX3_ANATXACONTROL2_RESERVED0_ALIGN 0 10704 #define TX3_ANATXACONTROL2_RESERVED0_BITS 2 10705 #define TX3_ANATXACONTROL2_RESERVED0_SHIFT 0 10706 10707 10708 /**************************************************************************** 10709 * Tx3 :: Tx_OS_Driver 10710 */ 10711 /* Tx3 :: Tx_OS_Driver :: preemphasis_post [15:12] */ 10712 #define TX3_TX_OS_DRIVER_PREEMPHASIS_POST_MASK 0xf000 10713 #define TX3_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN 0 10714 #define TX3_TX_OS_DRIVER_PREEMPHASIS_POST_BITS 4 10715 #define TX3_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT 12 10716 10717 /* Tx3 :: Tx_OS_Driver :: Idriver [11:08] */ 10718 #define TX3_TX_OS_DRIVER_IDRIVER_MASK 0x0f00 10719 #define TX3_TX_OS_DRIVER_IDRIVER_ALIGN 0 10720 #define TX3_TX_OS_DRIVER_IDRIVER_BITS 4 10721 #define TX3_TX_OS_DRIVER_IDRIVER_SHIFT 8 10722 10723 /* Tx3 :: Tx_OS_Driver :: Ipredriver [07:04] */ 10724 #define TX3_TX_OS_DRIVER_IPREDRIVER_MASK 0x00f0 10725 #define TX3_TX_OS_DRIVER_IPREDRIVER_ALIGN 0 10726 #define TX3_TX_OS_DRIVER_IPREDRIVER_BITS 4 10727 #define TX3_TX_OS_DRIVER_IPREDRIVER_SHIFT 4 10728 10729 /* Tx3 :: Tx_OS_Driver :: preemphasis_pre [03:01] */ 10730 #define TX3_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 10731 #define TX3_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN 0 10732 #define TX3_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS 3 10733 #define TX3_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT 1 10734 10735 /* Tx3 :: Tx_OS_Driver :: icbuf1t0 [00:00] */ 10736 #define TX3_TX_OS_DRIVER_ICBUF1T0_MASK 0x0001 10737 #define TX3_TX_OS_DRIVER_ICBUF1T0_ALIGN 0 10738 #define TX3_TX_OS_DRIVER_ICBUF1T0_BITS 1 10739 #define TX3_TX_OS_DRIVER_ICBUF1T0_SHIFT 0 10740 10741 10742 /**************************************************************************** 10743 * Tx3 :: Tx_BR_Driver 10744 */ 10745 /* Tx3 :: Tx_BR_Driver :: preemphasis_post [15:12] */ 10746 #define TX3_TX_BR_DRIVER_PREEMPHASIS_POST_MASK 0xf000 10747 #define TX3_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN 0 10748 #define TX3_TX_BR_DRIVER_PREEMPHASIS_POST_BITS 4 10749 #define TX3_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT 12 10750 10751 /* Tx3 :: Tx_BR_Driver :: Idriver [11:08] */ 10752 #define TX3_TX_BR_DRIVER_IDRIVER_MASK 0x0f00 10753 #define TX3_TX_BR_DRIVER_IDRIVER_ALIGN 0 10754 #define TX3_TX_BR_DRIVER_IDRIVER_BITS 4 10755 #define TX3_TX_BR_DRIVER_IDRIVER_SHIFT 8 10756 10757 /* Tx3 :: Tx_BR_Driver :: Ipredriver [07:04] */ 10758 #define TX3_TX_BR_DRIVER_IPREDRIVER_MASK 0x00f0 10759 #define TX3_TX_BR_DRIVER_IPREDRIVER_ALIGN 0 10760 #define TX3_TX_BR_DRIVER_IPREDRIVER_BITS 4 10761 #define TX3_TX_BR_DRIVER_IPREDRIVER_SHIFT 4 10762 10763 /* Tx3 :: Tx_BR_Driver :: preemphasis_pre [03:01] */ 10764 #define TX3_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 10765 #define TX3_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN 0 10766 #define TX3_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS 3 10767 #define TX3_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT 1 10768 10769 /* Tx3 :: Tx_BR_Driver :: icbuf1t0 [00:00] */ 10770 #define TX3_TX_BR_DRIVER_ICBUF1T0_MASK 0x0001 10771 #define TX3_TX_BR_DRIVER_ICBUF1T0_ALIGN 0 10772 #define TX3_TX_BR_DRIVER_ICBUF1T0_BITS 1 10773 #define TX3_TX_BR_DRIVER_ICBUF1T0_SHIFT 0 10774 10775 10776 /**************************************************************************** 10777 * Hypercore_USER_TxB 10778 */ 10779 /**************************************************************************** 10780 * TxB :: anaTxAStatus0 10781 */ 10782 /* TxB :: anaTxAStatus0 :: reserved0 [15:07] */ 10783 #define TXB_ANATXASTATUS0_RESERVED0_MASK 0xff80 10784 #define TXB_ANATXASTATUS0_RESERVED0_ALIGN 0 10785 #define TXB_ANATXASTATUS0_RESERVED0_BITS 9 10786 #define TXB_ANATXASTATUS0_RESERVED0_SHIFT 7 10787 10788 /* TxB :: anaTxAStatus0 :: txdisable_ln [06:06] */ 10789 #define TXB_ANATXASTATUS0_TXDISABLE_LN_MASK 0x0040 10790 #define TXB_ANATXASTATUS0_TXDISABLE_LN_ALIGN 0 10791 #define TXB_ANATXASTATUS0_TXDISABLE_LN_BITS 1 10792 #define TXB_ANATXASTATUS0_TXDISABLE_LN_SHIFT 6 10793 10794 /* TxB :: anaTxAStatus0 :: txferr_stky [05:05] */ 10795 #define TXB_ANATXASTATUS0_TXFERR_STKY_MASK 0x0020 10796 #define TXB_ANATXASTATUS0_TXFERR_STKY_ALIGN 0 10797 #define TXB_ANATXASTATUS0_TXFERR_STKY_BITS 1 10798 #define TXB_ANATXASTATUS0_TXFERR_STKY_SHIFT 5 10799 10800 /* TxB :: anaTxAStatus0 :: tbi_mode [04:04] */ 10801 #define TXB_ANATXASTATUS0_TBI_MODE_MASK 0x0010 10802 #define TXB_ANATXASTATUS0_TBI_MODE_ALIGN 0 10803 #define TXB_ANATXASTATUS0_TBI_MODE_BITS 1 10804 #define TXB_ANATXASTATUS0_TBI_MODE_SHIFT 4 10805 10806 /* TxB :: anaTxAStatus0 :: tx_reset [03:03] */ 10807 #define TXB_ANATXASTATUS0_TX_RESET_MASK 0x0008 10808 #define TXB_ANATXASTATUS0_TX_RESET_ALIGN 0 10809 #define TXB_ANATXASTATUS0_TX_RESET_BITS 1 10810 #define TXB_ANATXASTATUS0_TX_RESET_SHIFT 3 10811 10812 /* TxB :: anaTxAStatus0 :: tx_pwrdn [02:02] */ 10813 #define TXB_ANATXASTATUS0_TX_PWRDN_MASK 0x0004 10814 #define TXB_ANATXASTATUS0_TX_PWRDN_ALIGN 0 10815 #define TXB_ANATXASTATUS0_TX_PWRDN_BITS 1 10816 #define TXB_ANATXASTATUS0_TX_PWRDN_SHIFT 2 10817 10818 /* TxB :: anaTxAStatus0 :: rltxferr_stky [01:01] */ 10819 #define TXB_ANATXASTATUS0_RLTXFERR_STKY_MASK 0x0002 10820 #define TXB_ANATXASTATUS0_RLTXFERR_STKY_ALIGN 0 10821 #define TXB_ANATXASTATUS0_RLTXFERR_STKY_BITS 1 10822 #define TXB_ANATXASTATUS0_RLTXFERR_STKY_SHIFT 1 10823 10824 /* TxB :: anaTxAStatus0 :: txpll_lock [00:00] */ 10825 #define TXB_ANATXASTATUS0_TXPLL_LOCK_MASK 0x0001 10826 #define TXB_ANATXASTATUS0_TXPLL_LOCK_ALIGN 0 10827 #define TXB_ANATXASTATUS0_TXPLL_LOCK_BITS 1 10828 #define TXB_ANATXASTATUS0_TXPLL_LOCK_SHIFT 0 10829 10830 10831 /**************************************************************************** 10832 * TxB :: anaTxAControl0 10833 */ 10834 /* TxB :: anaTxAControl0 :: reserved0 [15:15] */ 10835 #define TXB_ANATXACONTROL0_RESERVED0_MASK 0x8000 10836 #define TXB_ANATXACONTROL0_RESERVED0_ALIGN 0 10837 #define TXB_ANATXACONTROL0_RESERVED0_BITS 1 10838 #define TXB_ANATXACONTROL0_RESERVED0_SHIFT 15 10839 10840 /* TxB :: anaTxAControl0 :: force_txclk [14:14] */ 10841 #define TXB_ANATXACONTROL0_FORCE_TXCLK_MASK 0x4000 10842 #define TXB_ANATXACONTROL0_FORCE_TXCLK_ALIGN 0 10843 #define TXB_ANATXACONTROL0_FORCE_TXCLK_BITS 1 10844 #define TXB_ANATXACONTROL0_FORCE_TXCLK_SHIFT 14 10845 10846 /* TxB :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */ 10847 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_MASK 0x2000 10848 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN 0 10849 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_BITS 1 10850 #define TXB_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT 13 10851 10852 /* TxB :: anaTxAControl0 :: gloopOutEn [12:12] */ 10853 #define TXB_ANATXACONTROL0_GLOOPOUTEN_MASK 0x1000 10854 #define TXB_ANATXACONTROL0_GLOOPOUTEN_ALIGN 0 10855 #define TXB_ANATXACONTROL0_GLOOPOUTEN_BITS 1 10856 #define TXB_ANATXACONTROL0_GLOOPOUTEN_SHIFT 12 10857 10858 /* TxB :: anaTxAControl0 :: reserved1 [11:09] */ 10859 #define TXB_ANATXACONTROL0_RESERVED1_MASK 0x0e00 10860 #define TXB_ANATXACONTROL0_RESERVED1_ALIGN 0 10861 #define TXB_ANATXACONTROL0_RESERVED1_BITS 3 10862 #define TXB_ANATXACONTROL0_RESERVED1_SHIFT 9 10863 10864 /* TxB :: anaTxAControl0 :: prbs_en [08:08] */ 10865 #define TXB_ANATXACONTROL0_PRBS_EN_MASK 0x0100 10866 #define TXB_ANATXACONTROL0_PRBS_EN_ALIGN 0 10867 #define TXB_ANATXACONTROL0_PRBS_EN_BITS 1 10868 #define TXB_ANATXACONTROL0_PRBS_EN_SHIFT 8 10869 10870 /* TxB :: anaTxAControl0 :: pckt_en [07:07] */ 10871 #define TXB_ANATXACONTROL0_PCKT_EN_MASK 0x0080 10872 #define TXB_ANATXACONTROL0_PCKT_EN_ALIGN 0 10873 #define TXB_ANATXACONTROL0_PCKT_EN_BITS 1 10874 #define TXB_ANATXACONTROL0_PCKT_EN_SHIFT 7 10875 10876 /* TxB :: anaTxAControl0 :: pckt_strt [06:06] */ 10877 #define TXB_ANATXACONTROL0_PCKT_STRT_MASK 0x0040 10878 #define TXB_ANATXACONTROL0_PCKT_STRT_ALIGN 0 10879 #define TXB_ANATXACONTROL0_PCKT_STRT_BITS 1 10880 #define TXB_ANATXACONTROL0_PCKT_STRT_SHIFT 6 10881 10882 /* TxB :: anaTxAControl0 :: txpol_flip [05:05] */ 10883 #define TXB_ANATXACONTROL0_TXPOL_FLIP_MASK 0x0020 10884 #define TXB_ANATXACONTROL0_TXPOL_FLIP_ALIGN 0 10885 #define TXB_ANATXACONTROL0_TXPOL_FLIP_BITS 1 10886 #define TXB_ANATXACONTROL0_TXPOL_FLIP_SHIFT 5 10887 10888 /* TxB :: anaTxAControl0 :: rtbi_flip [04:04] */ 10889 #define TXB_ANATXACONTROL0_RTBI_FLIP_MASK 0x0010 10890 #define TXB_ANATXACONTROL0_RTBI_FLIP_ALIGN 0 10891 #define TXB_ANATXACONTROL0_RTBI_FLIP_BITS 1 10892 #define TXB_ANATXACONTROL0_RTBI_FLIP_SHIFT 4 10893 10894 /* TxB :: anaTxAControl0 :: eden_r [03:03] */ 10895 #define TXB_ANATXACONTROL0_EDEN_R_MASK 0x0008 10896 #define TXB_ANATXACONTROL0_EDEN_R_ALIGN 0 10897 #define TXB_ANATXACONTROL0_EDEN_R_BITS 1 10898 #define TXB_ANATXACONTROL0_EDEN_R_SHIFT 3 10899 10900 /* TxB :: anaTxAControl0 :: eden_force_r [02:02] */ 10901 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_MASK 0x0004 10902 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_ALIGN 0 10903 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_BITS 1 10904 #define TXB_ANATXACONTROL0_EDEN_FORCE_R_SHIFT 2 10905 10906 /* TxB :: anaTxAControl0 :: txpat_en [01:01] */ 10907 #define TXB_ANATXACONTROL0_TXPAT_EN_MASK 0x0002 10908 #define TXB_ANATXACONTROL0_TXPAT_EN_ALIGN 0 10909 #define TXB_ANATXACONTROL0_TXPAT_EN_BITS 1 10910 #define TXB_ANATXACONTROL0_TXPAT_EN_SHIFT 1 10911 10912 /* TxB :: anaTxAControl0 :: tx_mdata_en [00:00] */ 10913 #define TXB_ANATXACONTROL0_TX_MDATA_EN_MASK 0x0001 10914 #define TXB_ANATXACONTROL0_TX_MDATA_EN_ALIGN 0 10915 #define TXB_ANATXACONTROL0_TX_MDATA_EN_BITS 1 10916 #define TXB_ANATXACONTROL0_TX_MDATA_EN_SHIFT 0 10917 10918 10919 /**************************************************************************** 10920 * TxB :: anaTxmdata0 10921 */ 10922 /* TxB :: anaTxmdata0 :: txTestMuxSel [15:13] */ 10923 #define TXB_ANATXMDATA0_TXTESTMUXSEL_MASK 0xe000 10924 #define TXB_ANATXMDATA0_TXTESTMUXSEL_ALIGN 0 10925 #define TXB_ANATXMDATA0_TXTESTMUXSEL_BITS 3 10926 #define TXB_ANATXMDATA0_TXTESTMUXSEL_SHIFT 13 10927 10928 /* TxB :: anaTxmdata0 :: rlfifo_tstsel [12:10] */ 10929 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_MASK 0x1c00 10930 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN 0 10931 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_BITS 3 10932 #define TXB_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT 10 10933 10934 /* TxB :: anaTxmdata0 :: TxMdioTstDataL [09:00] */ 10935 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_MASK 0x03ff 10936 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN 0 10937 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_BITS 10 10938 #define TXB_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT 0 10939 10940 10941 /**************************************************************************** 10942 * TxB :: anaTxmdata1 10943 */ 10944 /* TxB :: anaTxmdata1 :: reserved0 [15:10] */ 10945 #define TXB_ANATXMDATA1_RESERVED0_MASK 0xfc00 10946 #define TXB_ANATXMDATA1_RESERVED0_ALIGN 0 10947 #define TXB_ANATXMDATA1_RESERVED0_BITS 6 10948 #define TXB_ANATXMDATA1_RESERVED0_SHIFT 10 10949 10950 /* TxB :: anaTxmdata1 :: TxMdioTstDataH [09:00] */ 10951 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_MASK 0x03ff 10952 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN 0 10953 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_BITS 10 10954 #define TXB_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT 0 10955 10956 10957 /**************************************************************************** 10958 * TxB :: anaTxAStatus1 10959 */ 10960 /* TxB :: anaTxAStatus1 :: tx_id [15:14] */ 10961 #define TXB_ANATXASTATUS1_TX_ID_MASK 0xc000 10962 #define TXB_ANATXASTATUS1_TX_ID_ALIGN 0 10963 #define TXB_ANATXASTATUS1_TX_ID_BITS 2 10964 #define TXB_ANATXASTATUS1_TX_ID_SHIFT 14 10965 10966 /* TxB :: anaTxAStatus1 :: reserved0 [13:00] */ 10967 #define TXB_ANATXASTATUS1_RESERVED0_MASK 0x3fff 10968 #define TXB_ANATXASTATUS1_RESERVED0_ALIGN 0 10969 #define TXB_ANATXASTATUS1_RESERVED0_BITS 14 10970 #define TXB_ANATXASTATUS1_RESERVED0_SHIFT 0 10971 10972 10973 /**************************************************************************** 10974 * TxB :: anaTxAControl1 10975 */ 10976 /* TxB :: anaTxAControl1 :: id2c [15:13] */ 10977 #define TXB_ANATXACONTROL1_ID2C_MASK 0xe000 10978 #define TXB_ANATXACONTROL1_ID2C_ALIGN 0 10979 #define TXB_ANATXACONTROL1_ID2C_BITS 3 10980 #define TXB_ANATXACONTROL1_ID2C_SHIFT 13 10981 10982 /* TxB :: anaTxAControl1 :: refl_tx [12:12] */ 10983 #define TXB_ANATXACONTROL1_REFL_TX_MASK 0x1000 10984 #define TXB_ANATXACONTROL1_REFL_TX_ALIGN 0 10985 #define TXB_ANATXACONTROL1_REFL_TX_BITS 1 10986 #define TXB_ANATXACONTROL1_REFL_TX_SHIFT 12 10987 10988 /* TxB :: anaTxAControl1 :: refh_tx [11:11] */ 10989 #define TXB_ANATXACONTROL1_REFH_TX_MASK 0x0800 10990 #define TXB_ANATXACONTROL1_REFH_TX_ALIGN 0 10991 #define TXB_ANATXACONTROL1_REFH_TX_BITS 1 10992 #define TXB_ANATXACONTROL1_REFH_TX_SHIFT 11 10993 10994 /* TxB :: anaTxAControl1 :: newbias_en [10:10] */ 10995 #define TXB_ANATXACONTROL1_NEWBIAS_EN_MASK 0x0400 10996 #define TXB_ANATXACONTROL1_NEWBIAS_EN_ALIGN 0 10997 #define TXB_ANATXACONTROL1_NEWBIAS_EN_BITS 1 10998 #define TXB_ANATXACONTROL1_NEWBIAS_EN_SHIFT 10 10999 11000 /* TxB :: anaTxAControl1 :: drivermode [09:09] */ 11001 #define TXB_ANATXACONTROL1_DRIVERMODE_MASK 0x0200 11002 #define TXB_ANATXACONTROL1_DRIVERMODE_ALIGN 0 11003 #define TXB_ANATXACONTROL1_DRIVERMODE_BITS 1 11004 #define TXB_ANATXACONTROL1_DRIVERMODE_SHIFT 9 11005 11006 /* TxB :: anaTxAControl1 :: vddr_bgb [08:08] */ 11007 #define TXB_ANATXACONTROL1_VDDR_BGB_MASK 0x0100 11008 #define TXB_ANATXACONTROL1_VDDR_BGB_ALIGN 0 11009 #define TXB_ANATXACONTROL1_VDDR_BGB_BITS 1 11010 #define TXB_ANATXACONTROL1_VDDR_BGB_SHIFT 8 11011 11012 /* TxB :: anaTxAControl1 :: ticksel [07:06] */ 11013 #define TXB_ANATXACONTROL1_TICKSEL_MASK 0x00c0 11014 #define TXB_ANATXACONTROL1_TICKSEL_ALIGN 0 11015 #define TXB_ANATXACONTROL1_TICKSEL_BITS 2 11016 #define TXB_ANATXACONTROL1_TICKSEL_SHIFT 6 11017 11018 /* TxB :: anaTxAControl1 :: driver_vcm [05:04] */ 11019 #define TXB_ANATXACONTROL1_DRIVER_VCM_MASK 0x0030 11020 #define TXB_ANATXACONTROL1_DRIVER_VCM_ALIGN 0 11021 #define TXB_ANATXACONTROL1_DRIVER_VCM_BITS 2 11022 #define TXB_ANATXACONTROL1_DRIVER_VCM_SHIFT 4 11023 11024 /* TxB :: anaTxAControl1 :: tx_sel_halfrate [03:03] */ 11025 #define TXB_ANATXACONTROL1_TX_SEL_HALFRATE_MASK 0x0008 11026 #define TXB_ANATXACONTROL1_TX_SEL_HALFRATE_ALIGN 0 11027 #define TXB_ANATXACONTROL1_TX_SEL_HALFRATE_BITS 1 11028 #define TXB_ANATXACONTROL1_TX_SEL_HALFRATE_SHIFT 3 11029 11030 /* TxB :: anaTxAControl1 :: ifullspd [02:00] */ 11031 #define TXB_ANATXACONTROL1_IFULLSPD_MASK 0x0007 11032 #define TXB_ANATXACONTROL1_IFULLSPD_ALIGN 0 11033 #define TXB_ANATXACONTROL1_IFULLSPD_BITS 3 11034 #define TXB_ANATXACONTROL1_IFULLSPD_SHIFT 0 11035 11036 11037 /**************************************************************************** 11038 * TxB :: anaTxAControl2 11039 */ 11040 /* TxB :: anaTxAControl2 :: icbuf1t [15:14] */ 11041 #define TXB_ANATXACONTROL2_ICBUF1T_MASK 0xc000 11042 #define TXB_ANATXACONTROL2_ICBUF1T_ALIGN 0 11043 #define TXB_ANATXACONTROL2_ICBUF1T_BITS 2 11044 #define TXB_ANATXACONTROL2_ICBUF1T_SHIFT 14 11045 11046 /* TxB :: anaTxAControl2 :: icbuf2t [13:11] */ 11047 #define TXB_ANATXACONTROL2_ICBUF2T_MASK 0x3800 11048 #define TXB_ANATXACONTROL2_ICBUF2T_ALIGN 0 11049 #define TXB_ANATXACONTROL2_ICBUF2T_BITS 3 11050 #define TXB_ANATXACONTROL2_ICBUF2T_SHIFT 11 11051 11052 /* TxB :: anaTxAControl2 :: imin_predrv [10:10] */ 11053 #define TXB_ANATXACONTROL2_IMIN_PREDRV_MASK 0x0400 11054 #define TXB_ANATXACONTROL2_IMIN_PREDRV_ALIGN 0 11055 #define TXB_ANATXACONTROL2_IMIN_PREDRV_BITS 1 11056 #define TXB_ANATXACONTROL2_IMIN_PREDRV_SHIFT 10 11057 11058 /* TxB :: anaTxAControl2 :: imax_predrv [09:09] */ 11059 #define TXB_ANATXACONTROL2_IMAX_PREDRV_MASK 0x0200 11060 #define TXB_ANATXACONTROL2_IMAX_PREDRV_ALIGN 0 11061 #define TXB_ANATXACONTROL2_IMAX_PREDRV_BITS 1 11062 #define TXB_ANATXACONTROL2_IMAX_PREDRV_SHIFT 9 11063 11064 /* TxB :: anaTxAControl2 :: imode_predrv [08:08] */ 11065 #define TXB_ANATXACONTROL2_IMODE_PREDRV_MASK 0x0100 11066 #define TXB_ANATXACONTROL2_IMODE_PREDRV_ALIGN 0 11067 #define TXB_ANATXACONTROL2_IMODE_PREDRV_BITS 1 11068 #define TXB_ANATXACONTROL2_IMODE_PREDRV_SHIFT 8 11069 11070 /* TxB :: anaTxAControl2 :: i21mux [07:05] */ 11071 #define TXB_ANATXACONTROL2_I21MUX_MASK 0x00e0 11072 #define TXB_ANATXACONTROL2_I21MUX_ALIGN 0 11073 #define TXB_ANATXACONTROL2_I21MUX_BITS 3 11074 #define TXB_ANATXACONTROL2_I21MUX_SHIFT 5 11075 11076 /* TxB :: anaTxAControl2 :: imin_drvr [04:04] */ 11077 #define TXB_ANATXACONTROL2_IMIN_DRVR_MASK 0x0010 11078 #define TXB_ANATXACONTROL2_IMIN_DRVR_ALIGN 0 11079 #define TXB_ANATXACONTROL2_IMIN_DRVR_BITS 1 11080 #define TXB_ANATXACONTROL2_IMIN_DRVR_SHIFT 4 11081 11082 /* TxB :: anaTxAControl2 :: imax_drvr [03:03] */ 11083 #define TXB_ANATXACONTROL2_IMAX_DRVR_MASK 0x0008 11084 #define TXB_ANATXACONTROL2_IMAX_DRVR_ALIGN 0 11085 #define TXB_ANATXACONTROL2_IMAX_DRVR_BITS 1 11086 #define TXB_ANATXACONTROL2_IMAX_DRVR_SHIFT 3 11087 11088 /* TxB :: anaTxAControl2 :: imode_drvr [02:02] */ 11089 #define TXB_ANATXACONTROL2_IMODE_DRVR_MASK 0x0004 11090 #define TXB_ANATXACONTROL2_IMODE_DRVR_ALIGN 0 11091 #define TXB_ANATXACONTROL2_IMODE_DRVR_BITS 1 11092 #define TXB_ANATXACONTROL2_IMODE_DRVR_SHIFT 2 11093 11094 /* TxB :: anaTxAControl2 :: reserved0 [01:00] */ 11095 #define TXB_ANATXACONTROL2_RESERVED0_MASK 0x0003 11096 #define TXB_ANATXACONTROL2_RESERVED0_ALIGN 0 11097 #define TXB_ANATXACONTROL2_RESERVED0_BITS 2 11098 #define TXB_ANATXACONTROL2_RESERVED0_SHIFT 0 11099 11100 11101 /**************************************************************************** 11102 * TxB :: Tx_OS_Driver 11103 */ 11104 /* TxB :: Tx_OS_Driver :: preemphasis_post [15:12] */ 11105 #define TXB_TX_OS_DRIVER_PREEMPHASIS_POST_MASK 0xf000 11106 #define TXB_TX_OS_DRIVER_PREEMPHASIS_POST_ALIGN 0 11107 #define TXB_TX_OS_DRIVER_PREEMPHASIS_POST_BITS 4 11108 #define TXB_TX_OS_DRIVER_PREEMPHASIS_POST_SHIFT 12 11109 11110 /* TxB :: Tx_OS_Driver :: Idriver [11:08] */ 11111 #define TXB_TX_OS_DRIVER_IDRIVER_MASK 0x0f00 11112 #define TXB_TX_OS_DRIVER_IDRIVER_ALIGN 0 11113 #define TXB_TX_OS_DRIVER_IDRIVER_BITS 4 11114 #define TXB_TX_OS_DRIVER_IDRIVER_SHIFT 8 11115 11116 /* TxB :: Tx_OS_Driver :: Ipredriver [07:04] */ 11117 #define TXB_TX_OS_DRIVER_IPREDRIVER_MASK 0x00f0 11118 #define TXB_TX_OS_DRIVER_IPREDRIVER_ALIGN 0 11119 #define TXB_TX_OS_DRIVER_IPREDRIVER_BITS 4 11120 #define TXB_TX_OS_DRIVER_IPREDRIVER_SHIFT 4 11121 11122 /* TxB :: Tx_OS_Driver :: preemphasis_pre [03:01] */ 11123 #define TXB_TX_OS_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 11124 #define TXB_TX_OS_DRIVER_PREEMPHASIS_PRE_ALIGN 0 11125 #define TXB_TX_OS_DRIVER_PREEMPHASIS_PRE_BITS 3 11126 #define TXB_TX_OS_DRIVER_PREEMPHASIS_PRE_SHIFT 1 11127 11128 /* TxB :: Tx_OS_Driver :: icbuf1t0 [00:00] */ 11129 #define TXB_TX_OS_DRIVER_ICBUF1T0_MASK 0x0001 11130 #define TXB_TX_OS_DRIVER_ICBUF1T0_ALIGN 0 11131 #define TXB_TX_OS_DRIVER_ICBUF1T0_BITS 1 11132 #define TXB_TX_OS_DRIVER_ICBUF1T0_SHIFT 0 11133 11134 11135 /**************************************************************************** 11136 * TxB :: Tx_BR_Driver 11137 */ 11138 /* TxB :: Tx_BR_Driver :: preemphasis_post [15:12] */ 11139 #define TXB_TX_BR_DRIVER_PREEMPHASIS_POST_MASK 0xf000 11140 #define TXB_TX_BR_DRIVER_PREEMPHASIS_POST_ALIGN 0 11141 #define TXB_TX_BR_DRIVER_PREEMPHASIS_POST_BITS 4 11142 #define TXB_TX_BR_DRIVER_PREEMPHASIS_POST_SHIFT 12 11143 11144 /* TxB :: Tx_BR_Driver :: Idriver [11:08] */ 11145 #define TXB_TX_BR_DRIVER_IDRIVER_MASK 0x0f00 11146 #define TXB_TX_BR_DRIVER_IDRIVER_ALIGN 0 11147 #define TXB_TX_BR_DRIVER_IDRIVER_BITS 4 11148 #define TXB_TX_BR_DRIVER_IDRIVER_SHIFT 8 11149 11150 /* TxB :: Tx_BR_Driver :: Ipredriver [07:04] */ 11151 #define TXB_TX_BR_DRIVER_IPREDRIVER_MASK 0x00f0 11152 #define TXB_TX_BR_DRIVER_IPREDRIVER_ALIGN 0 11153 #define TXB_TX_BR_DRIVER_IPREDRIVER_BITS 4 11154 #define TXB_TX_BR_DRIVER_IPREDRIVER_SHIFT 4 11155 11156 /* TxB :: Tx_BR_Driver :: preemphasis_pre [03:01] */ 11157 #define TXB_TX_BR_DRIVER_PREEMPHASIS_PRE_MASK 0x000e 11158 #define TXB_TX_BR_DRIVER_PREEMPHASIS_PRE_ALIGN 0 11159 #define TXB_TX_BR_DRIVER_PREEMPHASIS_PRE_BITS 3 11160 #define TXB_TX_BR_DRIVER_PREEMPHASIS_PRE_SHIFT 1 11161 11162 /* TxB :: Tx_BR_Driver :: icbuf1t0 [00:00] */ 11163 #define TXB_TX_BR_DRIVER_ICBUF1T0_MASK 0x0001 11164 #define TXB_TX_BR_DRIVER_ICBUF1T0_ALIGN 0 11165 #define TXB_TX_BR_DRIVER_ICBUF1T0_BITS 1 11166 #define TXB_TX_BR_DRIVER_ICBUF1T0_SHIFT 0 11167 11168 11169 /**************************************************************************** 11170 * Hypercore_USER_Rx0 11171 */ 11172 /**************************************************************************** 11173 * Rx0 :: anaRxStatus 11174 */ 11175 /* union - case sigdet_Status [15:00] */ 11176 /* Rx0 :: anaRxStatus :: cx4_sigdet [15:15] */ 11177 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 11178 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 11179 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 11180 #define RX0_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 11181 11182 /* Rx0 :: anaRxStatus :: reserved0 [14:13] */ 11183 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 11184 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 11185 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 11186 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 11187 11188 /* Rx0 :: anaRxStatus :: rxSeqDone [12:12] */ 11189 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 11190 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 11191 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 11192 #define RX0_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 11193 11194 /* Rx0 :: anaRxStatus :: rx_sigdet_ll [11:11] */ 11195 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 11196 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 11197 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 11198 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 11199 11200 /* Rx0 :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 11201 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 11202 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 11203 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 11204 #define RX0_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 11205 11206 /* Rx0 :: anaRxStatus :: rx_reset [09:09] */ 11207 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 11208 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 11209 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 11210 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 11211 11212 /* Rx0 :: anaRxStatus :: rx_pwrdn [08:08] */ 11213 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 11214 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 11215 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 11216 #define RX0_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 11217 11218 /* Rx0 :: anaRxStatus :: reserved1 [07:00] */ 11219 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 11220 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 11221 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 11222 #define RX0_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 11223 11224 11225 /* union - case sync_Status [15:00] */ 11226 /* Rx0 :: anaRxStatus :: reserved0 [15:11] */ 11227 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 11228 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 11229 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 11230 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 11231 11232 /* Rx0 :: anaRxStatus :: test_acq_en [10:10] */ 11233 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 11234 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 11235 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 11236 #define RX0_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 11237 11238 /* Rx0 :: anaRxStatus :: reserved1 [09:09] */ 11239 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 11240 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 11241 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 11242 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 11243 11244 /* Rx0 :: anaRxStatus :: rxSeqStart [08:08] */ 11245 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 11246 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 11247 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 11248 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 11249 11250 /* Rx0 :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 11251 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 11252 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 11253 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 11254 #define RX0_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 11255 11256 /* Rx0 :: anaRxStatus :: sync_status [06:06] */ 11257 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 11258 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 11259 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 11260 #define RX0_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 11261 11262 /* Rx0 :: anaRxStatus :: rx_sigdet [05:05] */ 11263 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 11264 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 11265 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 11266 #define RX0_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 11267 11268 /* Rx0 :: anaRxStatus :: reserved2 [04:03] */ 11269 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 11270 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 11271 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 11272 #define RX0_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 11273 11274 /* Rx0 :: anaRxStatus :: saturate_status [02:02] */ 11275 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 11276 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 11277 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 11278 #define RX0_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 11279 11280 /* Rx0 :: anaRxStatus :: cx4_sigdet [01:01] */ 11281 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 11282 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 11283 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 11284 #define RX0_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 11285 11286 /* Rx0 :: anaRxStatus :: rxSeqDone [00:00] */ 11287 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 11288 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 11289 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 11290 #define RX0_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 11291 11292 11293 /* union - case rxTestSel_0 [15:00] */ 11294 /* Rx0 :: anaRxStatus :: reserved0 [15:10] */ 11295 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 11296 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 11297 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 11298 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 11299 11300 /* Rx0 :: anaRxStatus :: indck_mode_en [09:09] */ 11301 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 11302 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 11303 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 11304 #define RX0_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 11305 11306 /* Rx0 :: anaRxStatus :: pci_mode_en [08:08] */ 11307 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 11308 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 11309 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 11310 #define RX0_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 11311 11312 /* Rx0 :: anaRxStatus :: rx_polarity [07:07] */ 11313 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 11314 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 11315 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 11316 #define RX0_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 11317 11318 /* Rx0 :: anaRxStatus :: rxpol_flip [06:06] */ 11319 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 11320 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 11321 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 11322 #define RX0_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 11323 11324 /* Rx0 :: anaRxStatus :: comma_mask [05:05] */ 11325 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 11326 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 11327 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 11328 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 11329 11330 /* Rx0 :: anaRxStatus :: link_en_r [04:04] */ 11331 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 11332 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 11333 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 11334 #define RX0_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 11335 11336 /* Rx0 :: anaRxStatus :: comma_adj_en [03:03] */ 11337 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 11338 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 11339 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 11340 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 11341 11342 /* Rx0 :: anaRxStatus :: comma_adj_en_ext [02:02] */ 11343 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 11344 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 11345 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 11346 #define RX0_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 11347 11348 /* Rx0 :: anaRxStatus :: reserved1 [01:00] */ 11349 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 11350 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 11351 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 11352 #define RX0_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 11353 11354 11355 /* union - case rxTestSel_1 [15:00] */ 11356 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 11357 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 11358 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 11359 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 11360 #define RX0_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 11361 11362 /* Rx0 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 11363 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 11364 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 11365 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 11366 #define RX0_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 11367 11368 /* Rx0 :: anaRxStatus :: freq_sel_PC [03:03] */ 11369 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 11370 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 11371 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 11372 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 11373 11374 /* Rx0 :: anaRxStatus :: freq_sel_SM [02:02] */ 11375 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 11376 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 11377 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 11378 #define RX0_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 11379 11380 /* Rx0 :: anaRxStatus :: integ_mode_SM [01:00] */ 11381 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 11382 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 11383 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 11384 #define RX0_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 11385 11386 11387 /* union - case scale_Status [15:00] */ 11388 /* Rx0 :: anaRxStatus :: prop_scale [15:12] */ 11389 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 11390 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 11391 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 11392 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 11393 11394 /* Rx0 :: anaRxStatus :: integ_scale [11:08] */ 11395 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 11396 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 11397 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 11398 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 11399 11400 /* Rx0 :: anaRxStatus :: prop_scale_acq [07:04] */ 11401 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 11402 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 11403 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 11404 #define RX0_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 11405 11406 /* Rx0 :: anaRxStatus :: integ_scale_acq [03:00] */ 11407 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 11408 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 11409 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 11410 #define RX0_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 11411 11412 11413 /* union - case adc_CdrStatus1 [15:00] */ 11414 /* Rx0 :: anaRxStatus :: reserved0 [15:07] */ 11415 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 11416 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 11417 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 11418 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 11419 11420 /* Rx0 :: anaRxStatus :: rxMuxCkSel [06:06] */ 11421 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 11422 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 11423 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 11424 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 11425 11426 /* Rx0 :: anaRxStatus :: glpbk_combo [05:05] */ 11427 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 11428 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 11429 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 11430 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 11431 11432 /* Rx0 :: anaRxStatus :: clockSwitchSel [04:04] */ 11433 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 11434 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 11435 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 11436 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 11437 11438 /* Rx0 :: anaRxStatus :: rxck_tst [03:03] */ 11439 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 11440 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 11441 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 11442 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 11443 11444 /* Rx0 :: anaRxStatus :: rxck_i [02:02] */ 11445 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 11446 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 11447 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 11448 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 11449 11450 /* Rx0 :: anaRxStatus :: refclk [01:01] */ 11451 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 11452 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 11453 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 11454 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 11455 11456 /* Rx0 :: anaRxStatus :: pll_bypass [00:00] */ 11457 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 11458 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 11459 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 11460 #define RX0_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 11461 11462 11463 /* union - case adc_CdrStatus2 [15:00] */ 11464 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */ 11465 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 11466 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 11467 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 11468 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 11469 11470 /* Rx0 :: anaRxStatus :: rxMuxCkSel [05:05] */ 11471 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 11472 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 11473 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 11474 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 11475 11476 /* Rx0 :: anaRxStatus :: rxSeqStart [04:04] */ 11477 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 11478 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 11479 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 11480 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 11481 11482 /* Rx0 :: anaRxStatus :: reserved1 [03:01] */ 11483 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 11484 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 11485 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 11486 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 11487 11488 /* Rx0 :: anaRxStatus :: rxSeqDone [00:00] */ 11489 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 11490 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 11491 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 11492 #define RX0_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 11493 11494 11495 /* union - case adc_CdrStatus3 [15:00] */ 11496 /* Rx0 :: anaRxStatus :: reserved0 [15:04] */ 11497 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 11498 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 11499 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 11500 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 11501 11502 /* Rx0 :: anaRxStatus :: rxSeqStart [03:03] */ 11503 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 11504 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 11505 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 11506 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 11507 11508 /* Rx0 :: anaRxStatus :: reserved1 [02:01] */ 11509 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 11510 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 11511 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 11512 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 11513 11514 /* Rx0 :: anaRxStatus :: allow_increment_PC [00:00] */ 11515 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 11516 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 11517 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 11518 #define RX0_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 11519 11520 11521 /* union - case adc_CdrStatus4 [15:00] */ 11522 /* Rx0 :: anaRxStatus :: reserved0 [15:08] */ 11523 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 11524 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 11525 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 11526 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 11527 11528 /* Rx0 :: anaRxStatus :: rx_pwrdn [07:07] */ 11529 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 11530 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 11531 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 11532 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 11533 11534 /* Rx0 :: anaRxStatus :: freq_sel [06:06] */ 11535 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 11536 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 11537 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 11538 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 11539 11540 /* Rx0 :: anaRxStatus :: pll_lock_rstb [05:05] */ 11541 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 11542 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 11543 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 11544 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 11545 11546 /* Rx0 :: anaRxStatus :: pwrdn [04:04] */ 11547 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 11548 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 11549 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 11550 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 11551 11552 /* Rx0 :: anaRxStatus :: reserved1 [03:00] */ 11553 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 11554 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 11555 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 11556 #define RX0_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 11557 11558 11559 /* union - case adc_CdrStatus5 [15:00] */ 11560 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */ 11561 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 11562 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 11563 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 11564 #define RX0_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 11565 11566 11567 /* union - case adc_CdrStatus6 [15:00] */ 11568 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 11569 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 11570 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 11571 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 11572 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 11573 11574 /* Rx0 :: anaRxStatus :: rx_reset [04:04] */ 11575 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 11576 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 11577 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 11578 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 11579 11580 /* Rx0 :: anaRxStatus :: rx_pwrdn [03:03] */ 11581 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 11582 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 11583 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 11584 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 11585 11586 /* Rx0 :: anaRxStatus :: reset_anlg [02:02] */ 11587 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 11588 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 11589 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 11590 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 11591 11592 /* Rx0 :: anaRxStatus :: pwrdn_rx [01:01] */ 11593 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 11594 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 11595 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 11596 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 11597 11598 /* Rx0 :: anaRxStatus :: pwrdn_pll [00:00] */ 11599 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 11600 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 11601 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 11602 #define RX0_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 11603 11604 11605 /* union - case adc_CdrStatus7e [15:00] */ 11606 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 11607 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 11608 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 11609 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 11610 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 11611 11612 /* Rx0 :: anaRxStatus :: rxck0_even [04:04] */ 11613 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 11614 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 11615 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 11616 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 11617 11618 /* Rx0 :: anaRxStatus :: rxck1_even [03:03] */ 11619 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 11620 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 11621 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 11622 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 11623 11624 /* Rx0 :: anaRxStatus :: comdet_even [02:02] */ 11625 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 11626 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 11627 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 11628 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 11629 11630 /* Rx0 :: anaRxStatus :: en_cdet_even [01:01] */ 11631 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 11632 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 11633 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 11634 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 11635 11636 /* Rx0 :: anaRxStatus :: comma_adj_en_even [00:00] */ 11637 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 11638 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 11639 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 11640 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 11641 11642 11643 /* union - case adc_CdrStatus7o [15:00] */ 11644 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 11645 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 11646 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 11647 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 11648 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 11649 11650 /* Rx0 :: anaRxStatus :: rxck0_odd [04:04] */ 11651 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 11652 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 11653 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 11654 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 11655 11656 /* Rx0 :: anaRxStatus :: rxck1_odd [03:03] */ 11657 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 11658 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 11659 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 11660 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 11661 11662 /* Rx0 :: anaRxStatus :: comdet_odd [02:02] */ 11663 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 11664 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 11665 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 11666 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 11667 11668 /* Rx0 :: anaRxStatus :: en_cdet_odd [01:01] */ 11669 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 11670 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 11671 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 11672 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 11673 11674 /* Rx0 :: anaRxStatus :: comma_adj_en_odd [00:00] */ 11675 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 11676 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 11677 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 11678 #define RX0_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 11679 11680 11681 /* union - case adc_CdrStatus8 [15:00] */ 11682 /* Rx0 :: anaRxStatus :: reserved0 [15:01] */ 11683 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 11684 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 11685 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 11686 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 11687 11688 /* Rx0 :: anaRxStatus :: sigdet [00:00] */ 11689 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 11690 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 11691 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 11692 #define RX0_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 11693 11694 11695 /* union - case adc_CdrStatus9 [15:00] */ 11696 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */ 11697 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 11698 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 11699 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 11700 #define RX0_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 11701 11702 11703 /* union - case adc_CdrStatus10 [15:00] */ 11704 /* Rx0 :: anaRxStatus :: reserved0 [15:07] */ 11705 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 11706 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 11707 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 11708 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 11709 11710 /* Rx0 :: anaRxStatus :: prbs_en [06:06] */ 11711 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 11712 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 11713 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 11714 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 11715 11716 /* Rx0 :: anaRxStatus :: rstb_tst [05:05] */ 11717 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 11718 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 11719 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 11720 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 11721 11722 /* Rx0 :: anaRxStatus :: reserved1 [04:04] */ 11723 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 11724 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 11725 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 11726 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 11727 11728 /* Rx0 :: anaRxStatus :: prbs_state [03:00] */ 11729 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 11730 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 11731 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 11732 #define RX0_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 11733 11734 11735 /* union - case adc_CdrStatus11 [15:00] */ 11736 /* Rx0 :: anaRxStatus :: reserved0 [15:00] */ 11737 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 11738 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 11739 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 11740 #define RX0_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 11741 11742 11743 /* union - case adc_CdrStatus12_1 [15:00] */ 11744 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */ 11745 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 11746 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 11747 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 11748 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 11749 11750 /* Rx0 :: anaRxStatus :: enable4 [05:05] */ 11751 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 11752 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 11753 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 11754 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 11755 11756 /* Rx0 :: anaRxStatus :: radr_test [04:00] */ 11757 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 11758 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 11759 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 11760 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 11761 11762 11763 /* union - case adc_CdrStatus12_2 [15:00] */ 11764 /* Rx0 :: anaRxStatus :: reserved0 [15:05] */ 11765 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 11766 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 11767 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 11768 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 11769 11770 /* Rx0 :: anaRxStatus :: wadr_test [04:00] */ 11771 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 11772 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 11773 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 11774 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 11775 11776 11777 /* union - case adc_CdrStatus12_3 [15:00] */ 11778 /* Rx0 :: anaRxStatus :: reserved0 [15:06] */ 11779 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 11780 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 11781 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 11782 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 11783 11784 /* Rx0 :: anaRxStatus :: rxck_66B_tmux [05:05] */ 11785 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 11786 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 11787 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 11788 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 11789 11790 /* Rx0 :: anaRxStatus :: rstb_66B [04:04] */ 11791 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 11792 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 11793 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 11794 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 11795 11796 /* Rx0 :: anaRxStatus :: prstb_66B_mux [03:03] */ 11797 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 11798 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 11799 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 11800 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 11801 11802 /* Rx0 :: anaRxStatus :: rxck_i66_tmux [02:02] */ 11803 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 11804 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 11805 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 11806 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 11807 11808 /* Rx0 :: anaRxStatus :: rstb_i66 [01:01] */ 11809 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 11810 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 11811 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 11812 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 11813 11814 /* Rx0 :: anaRxStatus :: prstb_i66_mux [00:00] */ 11815 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 11816 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 11817 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 11818 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 11819 11820 11821 /* union - case adc_CdrStatus12_4 [15:00] */ 11822 /* Rx0 :: anaRxStatus :: reserved0 [15:04] */ 11823 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 11824 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 11825 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 11826 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 11827 11828 /* Rx0 :: anaRxStatus :: rfifo_error_r [03:02] */ 11829 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 11830 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 11831 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 11832 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 11833 11834 /* Rx0 :: anaRxStatus :: rfifo_unflow [01:01] */ 11835 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 11836 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 11837 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 11838 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 11839 11840 /* Rx0 :: anaRxStatus :: rfifo_ovflow [00:00] */ 11841 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 11842 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 11843 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 11844 #define RX0_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 11845 11846 11847 /* union - case integ_Status [15:00] */ 11848 /* Rx0 :: anaRxStatus :: integ_status [15:00] */ 11849 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 11850 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 11851 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 11852 #define RX0_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 11853 11854 11855 /* union - case vco_Status [15:00] */ 11856 /* Rx0 :: anaRxStatus :: vco_status [15:00] */ 11857 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 11858 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 11859 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 11860 #define RX0_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 11861 11862 11863 /* union - case prbs_Status [15:00] */ 11864 /* Rx0 :: anaRxStatus :: prbs_lock [15:15] */ 11865 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 11866 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 11867 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 11868 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 11869 11870 /* Rx0 :: anaRxStatus :: prbs_stky [14:14] */ 11871 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 11872 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 11873 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 11874 #define RX0_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 11875 11876 /* Rx0 :: anaRxStatus :: ptbs_errors [13:00] */ 11877 #define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 11878 #define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 11879 #define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 11880 #define RX0_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 11881 11882 11883 11884 /**************************************************************************** 11885 * Rx0 :: anaRxControl 11886 */ 11887 /* Rx0 :: anaRxControl :: reserved0 [15:10] */ 11888 #define RX0_ANARXCONTROL_RESERVED0_MASK 0xfc00 11889 #define RX0_ANARXCONTROL_RESERVED0_ALIGN 0 11890 #define RX0_ANARXCONTROL_RESERVED0_BITS 6 11891 #define RX0_ANARXCONTROL_RESERVED0_SHIFT 10 11892 11893 /* Rx0 :: anaRxControl :: override_sigdet_en [09:09] */ 11894 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 11895 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 11896 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 11897 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 11898 11899 /* Rx0 :: anaRxControl :: override_sigdet_val [08:08] */ 11900 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 11901 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 11902 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 11903 #define RX0_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 11904 11905 /* Rx0 :: anaRxControl :: reserved1 [07:03] */ 11906 #define RX0_ANARXCONTROL_RESERVED1_MASK 0x00f8 11907 #define RX0_ANARXCONTROL_RESERVED1_ALIGN 0 11908 #define RX0_ANARXCONTROL_RESERVED1_BITS 5 11909 #define RX0_ANARXCONTROL_RESERVED1_SHIFT 3 11910 11911 /* Rx0 :: anaRxControl :: status_sel [02:00] */ 11912 #define RX0_ANARXCONTROL_STATUS_SEL_MASK 0x0007 11913 #define RX0_ANARXCONTROL_STATUS_SEL_ALIGN 0 11914 #define RX0_ANARXCONTROL_STATUS_SEL_BITS 3 11915 #define RX0_ANARXCONTROL_STATUS_SEL_SHIFT 0 11916 #define RX0_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 11917 #define RX0_ANARXCONTROL_STATUS_SEL_syncStatus 1 11918 #define RX0_ANARXCONTROL_STATUS_SEL_rxTestSel 2 11919 #define RX0_ANARXCONTROL_STATUS_SEL_scaleStatus 3 11920 #define RX0_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 11921 #define RX0_ANARXCONTROL_STATUS_SEL_integStatus 5 11922 #define RX0_ANARXCONTROL_STATUS_SEL_vcoStatus 6 11923 #define RX0_ANARXCONTROL_STATUS_SEL_prbsStatus 7 11924 11925 11926 /**************************************************************************** 11927 * Rx0 :: anaRxTest 11928 */ 11929 /* Rx0 :: anaRxTest :: sigdet_mux_SM [15:12] */ 11930 #define RX0_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 11931 #define RX0_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 11932 #define RX0_ANARXTEST_SIGDET_MUX_SM_BITS 4 11933 #define RX0_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 11934 11935 /* Rx0 :: anaRxTest :: reserved0 [11:09] */ 11936 #define RX0_ANARXTEST_RESERVED0_MASK 0x0e00 11937 #define RX0_ANARXTEST_RESERVED0_ALIGN 0 11938 #define RX0_ANARXTEST_RESERVED0_BITS 3 11939 #define RX0_ANARXTEST_RESERVED0_SHIFT 9 11940 11941 /* Rx0 :: anaRxTest :: tpctrl_SM [08:04] */ 11942 #define RX0_ANARXTEST_TPCTRL_SM_MASK 0x01f0 11943 #define RX0_ANARXTEST_TPCTRL_SM_ALIGN 0 11944 #define RX0_ANARXTEST_TPCTRL_SM_BITS 5 11945 #define RX0_ANARXTEST_TPCTRL_SM_SHIFT 4 11946 11947 /* Rx0 :: anaRxTest :: testMuxSelect_SM [03:00] */ 11948 #define RX0_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 11949 #define RX0_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 11950 #define RX0_ANARXTEST_TESTMUXSELECT_SM_BITS 4 11951 #define RX0_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 11952 11953 11954 /**************************************************************************** 11955 * Rx0 :: anaRxControl1G 11956 */ 11957 /* Rx0 :: anaRxControl1G :: fpat_md [15:15] */ 11958 #define RX0_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 11959 #define RX0_ANARXCONTROL1G_FPAT_MD_ALIGN 0 11960 #define RX0_ANARXCONTROL1G_FPAT_MD_BITS 1 11961 #define RX0_ANARXCONTROL1G_FPAT_MD_SHIFT 15 11962 11963 /* Rx0 :: anaRxControl1G :: pkt_count_en [14:14] */ 11964 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 11965 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 11966 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 11967 #define RX0_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 11968 11969 /* Rx0 :: anaRxControl1G :: staMuxRegDis [13:13] */ 11970 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 11971 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 11972 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 11973 #define RX0_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 11974 11975 /* Rx0 :: anaRxControl1G :: prbs_clr_dis [12:12] */ 11976 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 11977 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 11978 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 11979 #define RX0_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 11980 11981 /* Rx0 :: anaRxControl1G :: rxd_dec_sel [11:11] */ 11982 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 11983 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 11984 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 11985 #define RX0_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 11986 11987 /* Rx0 :: anaRxControl1G :: cgbad_tst [10:10] */ 11988 #define RX0_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 11989 #define RX0_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 11990 #define RX0_ANARXCONTROL1G_CGBAD_TST_BITS 1 11991 #define RX0_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 11992 11993 /* Rx0 :: anaRxControl1G :: Emon_en [09:09] */ 11994 #define RX0_ANARXCONTROL1G_EMON_EN_MASK 0x0200 11995 #define RX0_ANARXCONTROL1G_EMON_EN_ALIGN 0 11996 #define RX0_ANARXCONTROL1G_EMON_EN_BITS 1 11997 #define RX0_ANARXCONTROL1G_EMON_EN_SHIFT 9 11998 11999 /* Rx0 :: anaRxControl1G :: prbs_en [08:08] */ 12000 #define RX0_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 12001 #define RX0_ANARXCONTROL1G_PRBS_EN_ALIGN 0 12002 #define RX0_ANARXCONTROL1G_PRBS_EN_BITS 1 12003 #define RX0_ANARXCONTROL1G_PRBS_EN_SHIFT 8 12004 12005 /* Rx0 :: anaRxControl1G :: cgbad_en [07:07] */ 12006 #define RX0_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 12007 #define RX0_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 12008 #define RX0_ANARXCONTROL1G_CGBAD_EN_BITS 1 12009 #define RX0_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 12010 12011 /* Rx0 :: anaRxControl1G :: cstretch [06:06] */ 12012 #define RX0_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 12013 #define RX0_ANARXCONTROL1G_CSTRETCH_ALIGN 0 12014 #define RX0_ANARXCONTROL1G_CSTRETCH_BITS 1 12015 #define RX0_ANARXCONTROL1G_CSTRETCH_SHIFT 6 12016 12017 /* Rx0 :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 12018 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 12019 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 12020 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 12021 #define RX0_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 12022 12023 /* Rx0 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 12024 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 12025 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 12026 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 12027 #define RX0_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 12028 12029 /* Rx0 :: anaRxControl1G :: reserved0 [03:02] */ 12030 #define RX0_ANARXCONTROL1G_RESERVED0_MASK 0x000c 12031 #define RX0_ANARXCONTROL1G_RESERVED0_ALIGN 0 12032 #define RX0_ANARXCONTROL1G_RESERVED0_BITS 2 12033 #define RX0_ANARXCONTROL1G_RESERVED0_SHIFT 2 12034 12035 /* Rx0 :: anaRxControl1G :: freq_sel_force [01:01] */ 12036 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 12037 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 12038 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 12039 #define RX0_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 12040 12041 /* Rx0 :: anaRxControl1G :: freq_sel [00:00] */ 12042 #define RX0_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 12043 #define RX0_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 12044 #define RX0_ANARXCONTROL1G_FREQ_SEL_BITS 1 12045 #define RX0_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 12046 12047 12048 /**************************************************************************** 12049 * Rx0 :: anaRxControlPci 12050 */ 12051 /* Rx0 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 12052 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 12053 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 12054 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 12055 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 12056 12057 /* Rx0 :: anaRxControlPci :: comma_mask_force_r [14:14] */ 12058 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 12059 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 12060 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 12061 #define RX0_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 12062 12063 /* Rx0 :: anaRxControlPci :: comma_mask_r [13:13] */ 12064 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 12065 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 12066 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 12067 #define RX0_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 12068 12069 /* Rx0 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 12070 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 12071 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 12072 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 12073 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 12074 12075 /* Rx0 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 12076 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 12077 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 12078 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 12079 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 12080 12081 /* Rx0 :: anaRxControlPci :: sync_status_force_r [10:10] */ 12082 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 12083 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 12084 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 12085 #define RX0_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 12086 12087 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 12088 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 12089 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 12090 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 12091 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 12092 12093 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 12094 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 12095 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 12096 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 12097 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 12098 12099 /* Rx0 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 12100 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 12101 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 12102 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 12103 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 12104 12105 /* Rx0 :: anaRxControlPci :: comma_adj_en_r [06:06] */ 12106 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 12107 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 12108 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 12109 #define RX0_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 12110 12111 /* Rx0 :: anaRxControlPci :: link_en_force_SM [05:05] */ 12112 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 12113 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 12114 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 12115 #define RX0_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 12116 12117 /* Rx0 :: anaRxControlPci :: link_en_r [04:04] */ 12118 #define RX0_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 12119 #define RX0_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 12120 #define RX0_ANARXCONTROLPCI_LINK_EN_R_BITS 1 12121 #define RX0_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 12122 12123 /* Rx0 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 12124 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 12125 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 12126 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 12127 #define RX0_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 12128 12129 /* Rx0 :: anaRxControlPci :: rx_polarity_r [02:02] */ 12130 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 12131 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 12132 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 12133 #define RX0_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 12134 12135 /* Rx0 :: anaRxControlPci :: integ_mode_SM [01:00] */ 12136 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 12137 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 12138 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 12139 #define RX0_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 12140 12141 12142 /**************************************************************************** 12143 * Rx0 :: anaRxAstatus 12144 */ 12145 /* Rx0 :: anaRxAstatus :: sigdet [15:15] */ 12146 #define RX0_ANARXASTATUS_SIGDET_MASK 0x8000 12147 #define RX0_ANARXASTATUS_SIGDET_ALIGN 0 12148 #define RX0_ANARXASTATUS_SIGDET_BITS 1 12149 #define RX0_ANARXASTATUS_SIGDET_SHIFT 15 12150 12151 /* Rx0 :: anaRxAstatus :: rx_pf [14:12] */ 12152 #define RX0_ANARXASTATUS_RX_PF_MASK 0x7000 12153 #define RX0_ANARXASTATUS_RX_PF_ALIGN 0 12154 #define RX0_ANARXASTATUS_RX_PF_BITS 3 12155 #define RX0_ANARXASTATUS_RX_PF_SHIFT 12 12156 12157 /* Rx0 :: anaRxAstatus :: dfe [11:06] */ 12158 #define RX0_ANARXASTATUS_DFE_MASK 0x0fc0 12159 #define RX0_ANARXASTATUS_DFE_ALIGN 0 12160 #define RX0_ANARXASTATUS_DFE_BITS 6 12161 #define RX0_ANARXASTATUS_DFE_SHIFT 6 12162 12163 /* Rx0 :: anaRxAstatus :: reserved0 [05:05] */ 12164 #define RX0_ANARXASTATUS_RESERVED0_MASK 0x0020 12165 #define RX0_ANARXASTATUS_RESERVED0_ALIGN 0 12166 #define RX0_ANARXASTATUS_RESERVED0_BITS 1 12167 #define RX0_ANARXASTATUS_RESERVED0_SHIFT 5 12168 12169 /* Rx0 :: anaRxAstatus :: vga [04:00] */ 12170 #define RX0_ANARXASTATUS_VGA_MASK 0x001f 12171 #define RX0_ANARXASTATUS_VGA_ALIGN 0 12172 #define RX0_ANARXASTATUS_VGA_BITS 5 12173 #define RX0_ANARXASTATUS_VGA_SHIFT 0 12174 12175 12176 /**************************************************************************** 12177 * Rx0 :: anaRxAControl1 12178 */ 12179 /* Rx0 :: anaRxAControl1 :: imode_vcm [15:15] */ 12180 #define RX0_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 12181 #define RX0_ANARXACONTROL1_IMODE_VCM_ALIGN 0 12182 #define RX0_ANARXACONTROL1_IMODE_VCM_BITS 1 12183 #define RX0_ANARXACONTROL1_IMODE_VCM_SHIFT 15 12184 12185 /* Rx0 :: anaRxAControl1 :: imin_vcm [14:14] */ 12186 #define RX0_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 12187 #define RX0_ANARXACONTROL1_IMIN_VCM_ALIGN 0 12188 #define RX0_ANARXACONTROL1_IMIN_VCM_BITS 1 12189 #define RX0_ANARXACONTROL1_IMIN_VCM_SHIFT 14 12190 12191 /* Rx0 :: anaRxAControl1 :: imax_sigdet [13:13] */ 12192 #define RX0_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 12193 #define RX0_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 12194 #define RX0_ANARXACONTROL1_IMAX_SIGDET_BITS 1 12195 #define RX0_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 12196 12197 /* Rx0 :: anaRxAControl1 :: imode_sigdet [12:12] */ 12198 #define RX0_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 12199 #define RX0_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 12200 #define RX0_ANARXACONTROL1_IMODE_SIGDET_BITS 1 12201 #define RX0_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 12202 12203 /* Rx0 :: anaRxAControl1 :: imin_sigdet [11:11] */ 12204 #define RX0_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 12205 #define RX0_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 12206 #define RX0_ANARXACONTROL1_IMIN_SIGDET_BITS 1 12207 #define RX0_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 12208 12209 /* Rx0 :: anaRxAControl1 :: refh_rx [10:10] */ 12210 #define RX0_ANARXACONTROL1_REFH_RX_MASK 0x0400 12211 #define RX0_ANARXACONTROL1_REFH_RX_ALIGN 0 12212 #define RX0_ANARXACONTROL1_REFH_RX_BITS 1 12213 #define RX0_ANARXACONTROL1_REFH_RX_SHIFT 10 12214 12215 /* Rx0 :: anaRxAControl1 :: refl_rx [09:09] */ 12216 #define RX0_ANARXACONTROL1_REFL_RX_MASK 0x0200 12217 #define RX0_ANARXACONTROL1_REFL_RX_ALIGN 0 12218 #define RX0_ANARXACONTROL1_REFL_RX_BITS 1 12219 #define RX0_ANARXACONTROL1_REFL_RX_SHIFT 9 12220 12221 /* Rx0 :: anaRxAControl1 :: tport_en [08:08] */ 12222 #define RX0_ANARXACONTROL1_TPORT_EN_MASK 0x0100 12223 #define RX0_ANARXACONTROL1_TPORT_EN_ALIGN 0 12224 #define RX0_ANARXACONTROL1_TPORT_EN_BITS 1 12225 #define RX0_ANARXACONTROL1_TPORT_EN_SHIFT 8 12226 12227 /* Rx0 :: anaRxAControl1 :: vddrb_bg [07:07] */ 12228 #define RX0_ANARXACONTROL1_VDDRB_BG_MASK 0x0080 12229 #define RX0_ANARXACONTROL1_VDDRB_BG_ALIGN 0 12230 #define RX0_ANARXACONTROL1_VDDRB_BG_BITS 1 12231 #define RX0_ANARXACONTROL1_VDDRB_BG_SHIFT 7 12232 12233 /* Rx0 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 12234 #define RX0_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 12235 #define RX0_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 12236 #define RX0_ANARXACONTROL1_SIG_PWRDN_BITS 1 12237 #define RX0_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 12238 12239 /* Rx0 :: anaRxAControl1 :: offset_ctrl [05:03] */ 12240 #define RX0_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 12241 #define RX0_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 12242 #define RX0_ANARXACONTROL1_OFFSET_CTRL_BITS 3 12243 #define RX0_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 12244 12245 /* Rx0 :: anaRxAControl1 :: offset_sel [02:02] */ 12246 #define RX0_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 12247 #define RX0_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 12248 #define RX0_ANARXACONTROL1_OFFSET_SEL_BITS 1 12249 #define RX0_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 12250 12251 /* Rx0 :: anaRxAControl1 :: reserved0 [01:00] */ 12252 #define RX0_ANARXACONTROL1_RESERVED0_MASK 0x0003 12253 #define RX0_ANARXACONTROL1_RESERVED0_ALIGN 0 12254 #define RX0_ANARXACONTROL1_RESERVED0_BITS 2 12255 #define RX0_ANARXACONTROL1_RESERVED0_SHIFT 0 12256 12257 12258 /**************************************************************************** 12259 * Rx0 :: anaRxAControl2 12260 */ 12261 /* Rx0 :: anaRxAControl2 :: imax_clkbuf [15:15] */ 12262 #define RX0_ANARXACONTROL2_IMAX_CLKBUF_MASK 0x8000 12263 #define RX0_ANARXACONTROL2_IMAX_CLKBUF_ALIGN 0 12264 #define RX0_ANARXACONTROL2_IMAX_CLKBUF_BITS 1 12265 #define RX0_ANARXACONTROL2_IMAX_CLKBUF_SHIFT 15 12266 12267 /* Rx0 :: anaRxAControl2 :: imode_clkbuf [14:14] */ 12268 #define RX0_ANARXACONTROL2_IMODE_CLKBUF_MASK 0x4000 12269 #define RX0_ANARXACONTROL2_IMODE_CLKBUF_ALIGN 0 12270 #define RX0_ANARXACONTROL2_IMODE_CLKBUF_BITS 1 12271 #define RX0_ANARXACONTROL2_IMODE_CLKBUF_SHIFT 14 12272 12273 /* Rx0 :: anaRxAControl2 :: imin_clkbuf [13:13] */ 12274 #define RX0_ANARXACONTROL2_IMIN_CLKBUF_MASK 0x2000 12275 #define RX0_ANARXACONTROL2_IMIN_CLKBUF_ALIGN 0 12276 #define RX0_ANARXACONTROL2_IMIN_CLKBUF_BITS 1 12277 #define RX0_ANARXACONTROL2_IMIN_CLKBUF_SHIFT 13 12278 12279 /* Rx0 :: anaRxAControl2 :: imax_eqfl [12:12] */ 12280 #define RX0_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 12281 #define RX0_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 12282 #define RX0_ANARXACONTROL2_IMAX_EQFL_BITS 1 12283 #define RX0_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 12284 12285 /* Rx0 :: anaRxAControl2 :: imode_eqfl [11:11] */ 12286 #define RX0_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 12287 #define RX0_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 12288 #define RX0_ANARXACONTROL2_IMODE_EQFL_BITS 1 12289 #define RX0_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 12290 12291 /* Rx0 :: anaRxAControl2 :: imin_eqfl [10:10] */ 12292 #define RX0_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 12293 #define RX0_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 12294 #define RX0_ANARXACONTROL2_IMIN_EQFL_BITS 1 12295 #define RX0_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 12296 12297 /* Rx0 :: anaRxAControl2 :: imax_dfesum [09:09] */ 12298 #define RX0_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 12299 #define RX0_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 12300 #define RX0_ANARXACONTROL2_IMAX_DFESUM_BITS 1 12301 #define RX0_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 12302 12303 /* Rx0 :: anaRxAControl2 :: imode_dfesum [08:08] */ 12304 #define RX0_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 12305 #define RX0_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 12306 #define RX0_ANARXACONTROL2_IMODE_DFESUM_BITS 1 12307 #define RX0_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 12308 12309 /* Rx0 :: anaRxAControl2 :: imin_dfesum [07:07] */ 12310 #define RX0_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 12311 #define RX0_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 12312 #define RX0_ANARXACONTROL2_IMIN_DFESUM_BITS 1 12313 #define RX0_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 12314 12315 /* Rx0 :: anaRxAControl2 :: imax_vga [06:06] */ 12316 #define RX0_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 12317 #define RX0_ANARXACONTROL2_IMAX_VGA_ALIGN 0 12318 #define RX0_ANARXACONTROL2_IMAX_VGA_BITS 1 12319 #define RX0_ANARXACONTROL2_IMAX_VGA_SHIFT 6 12320 12321 /* Rx0 :: anaRxAControl2 :: imode_vga [05:05] */ 12322 #define RX0_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 12323 #define RX0_ANARXACONTROL2_IMODE_VGA_ALIGN 0 12324 #define RX0_ANARXACONTROL2_IMODE_VGA_BITS 1 12325 #define RX0_ANARXACONTROL2_IMODE_VGA_SHIFT 5 12326 12327 /* Rx0 :: anaRxAControl2 :: imin_vga [04:04] */ 12328 #define RX0_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 12329 #define RX0_ANARXACONTROL2_IMIN_VGA_ALIGN 0 12330 #define RX0_ANARXACONTROL2_IMIN_VGA_BITS 1 12331 #define RX0_ANARXACONTROL2_IMIN_VGA_SHIFT 4 12332 12333 /* Rx0 :: anaRxAControl2 :: imax_interp [03:03] */ 12334 #define RX0_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 12335 #define RX0_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 12336 #define RX0_ANARXACONTROL2_IMAX_INTERP_BITS 1 12337 #define RX0_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 12338 12339 /* Rx0 :: anaRxAControl2 :: imode_interp [02:02] */ 12340 #define RX0_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 12341 #define RX0_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 12342 #define RX0_ANARXACONTROL2_IMODE_INTERP_BITS 1 12343 #define RX0_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 12344 12345 /* Rx0 :: anaRxAControl2 :: imin_interp [01:01] */ 12346 #define RX0_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 12347 #define RX0_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 12348 #define RX0_ANARXACONTROL2_IMIN_INTERP_BITS 1 12349 #define RX0_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 12350 12351 /* Rx0 :: anaRxAControl2 :: imax_vcm [00:00] */ 12352 #define RX0_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 12353 #define RX0_ANARXACONTROL2_IMAX_VCM_ALIGN 0 12354 #define RX0_ANARXACONTROL2_IMAX_VCM_BITS 1 12355 #define RX0_ANARXACONTROL2_IMAX_VCM_SHIFT 0 12356 12357 12358 /**************************************************************************** 12359 * Rx0 :: anaRxAControl3 12360 */ 12361 /* Rx0 :: anaRxAControl3 :: en_clk16 [15:15] */ 12362 #define RX0_ANARXACONTROL3_EN_CLK16_MASK 0x8000 12363 #define RX0_ANARXACONTROL3_EN_CLK16_ALIGN 0 12364 #define RX0_ANARXACONTROL3_EN_CLK16_BITS 1 12365 #define RX0_ANARXACONTROL3_EN_CLK16_SHIFT 15 12366 12367 /* Rx0 :: anaRxAControl3 :: pd_ch_p1 [14:14] */ 12368 #define RX0_ANARXACONTROL3_PD_CH_P1_MASK 0x4000 12369 #define RX0_ANARXACONTROL3_PD_CH_P1_ALIGN 0 12370 #define RX0_ANARXACONTROL3_PD_CH_P1_BITS 1 12371 #define RX0_ANARXACONTROL3_PD_CH_P1_SHIFT 14 12372 12373 /* Rx0 :: anaRxAControl3 :: en_vcctrl [13:13] */ 12374 #define RX0_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 12375 #define RX0_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 12376 #define RX0_ANARXACONTROL3_EN_VCCTRL_BITS 1 12377 #define RX0_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 12378 12379 /* Rx0 :: anaRxAControl3 :: en_dfeclk [12:12] */ 12380 #define RX0_ANARXACONTROL3_EN_DFECLK_MASK 0x1000 12381 #define RX0_ANARXACONTROL3_EN_DFECLK_ALIGN 0 12382 #define RX0_ANARXACONTROL3_EN_DFECLK_BITS 1 12383 #define RX0_ANARXACONTROL3_EN_DFECLK_SHIFT 12 12384 12385 /* Rx0 :: anaRxAControl3 :: en_hgain [11:11] */ 12386 #define RX0_ANARXACONTROL3_EN_HGAIN_MASK 0x0800 12387 #define RX0_ANARXACONTROL3_EN_HGAIN_ALIGN 0 12388 #define RX0_ANARXACONTROL3_EN_HGAIN_BITS 1 12389 #define RX0_ANARXACONTROL3_EN_HGAIN_SHIFT 11 12390 12391 /* Rx0 :: anaRxAControl3 :: en_dfeckpwr [10:10] */ 12392 #define RX0_ANARXACONTROL3_EN_DFECKPWR_MASK 0x0400 12393 #define RX0_ANARXACONTROL3_EN_DFECKPWR_ALIGN 0 12394 #define RX0_ANARXACONTROL3_EN_DFECKPWR_BITS 1 12395 #define RX0_ANARXACONTROL3_EN_DFECKPWR_SHIFT 10 12396 12397 /* Rx0 :: anaRxAControl3 :: offset_pd [09:09] */ 12398 #define RX0_ANARXACONTROL3_OFFSET_PD_MASK 0x0200 12399 #define RX0_ANARXACONTROL3_OFFSET_PD_ALIGN 0 12400 #define RX0_ANARXACONTROL3_OFFSET_PD_BITS 1 12401 #define RX0_ANARXACONTROL3_OFFSET_PD_SHIFT 9 12402 12403 /* Rx0 :: anaRxAControl3 :: imax_dfetap [08:08] */ 12404 #define RX0_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 12405 #define RX0_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 12406 #define RX0_ANARXACONTROL3_IMAX_DFETAP_BITS 1 12407 #define RX0_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 12408 12409 /* Rx0 :: anaRxAControl3 :: imode_dfetap [07:07] */ 12410 #define RX0_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 12411 #define RX0_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 12412 #define RX0_ANARXACONTROL3_IMODE_DFETAP_BITS 1 12413 #define RX0_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 12414 12415 /* Rx0 :: anaRxAControl3 :: imin_dfetap [06:06] */ 12416 #define RX0_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 12417 #define RX0_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 12418 #define RX0_ANARXACONTROL3_IMIN_DFETAP_BITS 1 12419 #define RX0_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 12420 12421 /* Rx0 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 12422 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 12423 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 12424 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 12425 #define RX0_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 12426 12427 /* Rx0 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 12428 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 12429 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 12430 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 12431 #define RX0_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 12432 12433 /* Rx0 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 12434 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 12435 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 12436 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 12437 #define RX0_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 12438 12439 /* Rx0 :: anaRxAControl3 :: imax_dfevref [02:02] */ 12440 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 12441 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 12442 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 12443 #define RX0_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 12444 12445 /* Rx0 :: anaRxAControl3 :: imode_dfevref [01:01] */ 12446 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 12447 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 12448 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 12449 #define RX0_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 12450 12451 /* Rx0 :: anaRxAControl3 :: imin_dfevref [00:00] */ 12452 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 12453 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 12454 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 12455 #define RX0_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 12456 12457 12458 /**************************************************************************** 12459 * Hypercore_USER_Rx1 12460 */ 12461 /**************************************************************************** 12462 * Rx1 :: anaRxStatus 12463 */ 12464 /* union - case sigdet_Status [15:00] */ 12465 /* Rx1 :: anaRxStatus :: cx4_sigdet [15:15] */ 12466 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 12467 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 12468 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 12469 #define RX1_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 12470 12471 /* Rx1 :: anaRxStatus :: reserved0 [14:13] */ 12472 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 12473 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 12474 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 12475 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 12476 12477 /* Rx1 :: anaRxStatus :: rxSeqDone [12:12] */ 12478 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 12479 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 12480 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 12481 #define RX1_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 12482 12483 /* Rx1 :: anaRxStatus :: rx_sigdet_ll [11:11] */ 12484 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 12485 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 12486 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 12487 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 12488 12489 /* Rx1 :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 12490 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 12491 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 12492 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 12493 #define RX1_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 12494 12495 /* Rx1 :: anaRxStatus :: rx_reset [09:09] */ 12496 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 12497 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 12498 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 12499 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 12500 12501 /* Rx1 :: anaRxStatus :: rx_pwrdn [08:08] */ 12502 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 12503 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 12504 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 12505 #define RX1_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 12506 12507 /* Rx1 :: anaRxStatus :: reserved1 [07:00] */ 12508 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 12509 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 12510 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 12511 #define RX1_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 12512 12513 12514 /* union - case sync_Status [15:00] */ 12515 /* Rx1 :: anaRxStatus :: reserved0 [15:11] */ 12516 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 12517 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 12518 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 12519 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 12520 12521 /* Rx1 :: anaRxStatus :: test_acq_en [10:10] */ 12522 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 12523 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 12524 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 12525 #define RX1_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 12526 12527 /* Rx1 :: anaRxStatus :: reserved1 [09:09] */ 12528 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 12529 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 12530 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 12531 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 12532 12533 /* Rx1 :: anaRxStatus :: rxSeqStart [08:08] */ 12534 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 12535 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 12536 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 12537 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 12538 12539 /* Rx1 :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 12540 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 12541 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 12542 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 12543 #define RX1_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 12544 12545 /* Rx1 :: anaRxStatus :: sync_status [06:06] */ 12546 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 12547 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 12548 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 12549 #define RX1_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 12550 12551 /* Rx1 :: anaRxStatus :: rx_sigdet [05:05] */ 12552 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 12553 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 12554 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 12555 #define RX1_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 12556 12557 /* Rx1 :: anaRxStatus :: reserved2 [04:03] */ 12558 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 12559 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 12560 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 12561 #define RX1_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 12562 12563 /* Rx1 :: anaRxStatus :: saturate_status [02:02] */ 12564 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 12565 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 12566 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 12567 #define RX1_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 12568 12569 /* Rx1 :: anaRxStatus :: cx4_sigdet [01:01] */ 12570 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 12571 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 12572 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 12573 #define RX1_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 12574 12575 /* Rx1 :: anaRxStatus :: rxSeqDone [00:00] */ 12576 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 12577 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 12578 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 12579 #define RX1_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 12580 12581 12582 /* union - case rxTestSel_0 [15:00] */ 12583 /* Rx1 :: anaRxStatus :: reserved0 [15:10] */ 12584 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 12585 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 12586 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 12587 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 12588 12589 /* Rx1 :: anaRxStatus :: indck_mode_en [09:09] */ 12590 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 12591 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 12592 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 12593 #define RX1_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 12594 12595 /* Rx1 :: anaRxStatus :: pci_mode_en [08:08] */ 12596 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 12597 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 12598 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 12599 #define RX1_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 12600 12601 /* Rx1 :: anaRxStatus :: rx_polarity [07:07] */ 12602 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 12603 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 12604 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 12605 #define RX1_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 12606 12607 /* Rx1 :: anaRxStatus :: rxpol_flip [06:06] */ 12608 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 12609 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 12610 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 12611 #define RX1_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 12612 12613 /* Rx1 :: anaRxStatus :: comma_mask [05:05] */ 12614 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 12615 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 12616 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 12617 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 12618 12619 /* Rx1 :: anaRxStatus :: link_en_r [04:04] */ 12620 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 12621 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 12622 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 12623 #define RX1_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 12624 12625 /* Rx1 :: anaRxStatus :: comma_adj_en [03:03] */ 12626 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 12627 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 12628 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 12629 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 12630 12631 /* Rx1 :: anaRxStatus :: comma_adj_en_ext [02:02] */ 12632 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 12633 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 12634 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 12635 #define RX1_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 12636 12637 /* Rx1 :: anaRxStatus :: reserved1 [01:00] */ 12638 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 12639 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 12640 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 12641 #define RX1_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 12642 12643 12644 /* union - case rxTestSel_1 [15:00] */ 12645 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 12646 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 12647 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 12648 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 12649 #define RX1_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 12650 12651 /* Rx1 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 12652 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 12653 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 12654 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 12655 #define RX1_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 12656 12657 /* Rx1 :: anaRxStatus :: freq_sel_PC [03:03] */ 12658 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 12659 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 12660 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 12661 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 12662 12663 /* Rx1 :: anaRxStatus :: freq_sel_SM [02:02] */ 12664 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 12665 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 12666 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 12667 #define RX1_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 12668 12669 /* Rx1 :: anaRxStatus :: integ_mode_SM [01:00] */ 12670 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 12671 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 12672 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 12673 #define RX1_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 12674 12675 12676 /* union - case scale_Status [15:00] */ 12677 /* Rx1 :: anaRxStatus :: prop_scale [15:12] */ 12678 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 12679 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 12680 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 12681 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 12682 12683 /* Rx1 :: anaRxStatus :: integ_scale [11:08] */ 12684 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 12685 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 12686 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 12687 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 12688 12689 /* Rx1 :: anaRxStatus :: prop_scale_acq [07:04] */ 12690 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 12691 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 12692 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 12693 #define RX1_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 12694 12695 /* Rx1 :: anaRxStatus :: integ_scale_acq [03:00] */ 12696 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 12697 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 12698 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 12699 #define RX1_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 12700 12701 12702 /* union - case adc_CdrStatus1 [15:00] */ 12703 /* Rx1 :: anaRxStatus :: reserved0 [15:07] */ 12704 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 12705 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 12706 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 12707 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 12708 12709 /* Rx1 :: anaRxStatus :: rxMuxCkSel [06:06] */ 12710 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 12711 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 12712 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 12713 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 12714 12715 /* Rx1 :: anaRxStatus :: glpbk_combo [05:05] */ 12716 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 12717 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 12718 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 12719 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 12720 12721 /* Rx1 :: anaRxStatus :: clockSwitchSel [04:04] */ 12722 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 12723 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 12724 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 12725 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 12726 12727 /* Rx1 :: anaRxStatus :: rxck_tst [03:03] */ 12728 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 12729 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 12730 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 12731 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 12732 12733 /* Rx1 :: anaRxStatus :: rxck_i [02:02] */ 12734 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 12735 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 12736 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 12737 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 12738 12739 /* Rx1 :: anaRxStatus :: refclk [01:01] */ 12740 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 12741 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 12742 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 12743 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 12744 12745 /* Rx1 :: anaRxStatus :: pll_bypass [00:00] */ 12746 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 12747 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 12748 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 12749 #define RX1_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 12750 12751 12752 /* union - case adc_CdrStatus2 [15:00] */ 12753 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */ 12754 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 12755 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 12756 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 12757 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 12758 12759 /* Rx1 :: anaRxStatus :: rxMuxCkSel [05:05] */ 12760 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 12761 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 12762 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 12763 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 12764 12765 /* Rx1 :: anaRxStatus :: rxSeqStart [04:04] */ 12766 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 12767 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 12768 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 12769 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 12770 12771 /* Rx1 :: anaRxStatus :: reserved1 [03:01] */ 12772 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 12773 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 12774 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 12775 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 12776 12777 /* Rx1 :: anaRxStatus :: rxSeqDone [00:00] */ 12778 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 12779 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 12780 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 12781 #define RX1_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 12782 12783 12784 /* union - case adc_CdrStatus3 [15:00] */ 12785 /* Rx1 :: anaRxStatus :: reserved0 [15:04] */ 12786 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 12787 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 12788 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 12789 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 12790 12791 /* Rx1 :: anaRxStatus :: rxSeqStart [03:03] */ 12792 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 12793 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 12794 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 12795 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 12796 12797 /* Rx1 :: anaRxStatus :: reserved1 [02:01] */ 12798 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 12799 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 12800 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 12801 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 12802 12803 /* Rx1 :: anaRxStatus :: allow_increment_PC [00:00] */ 12804 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 12805 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 12806 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 12807 #define RX1_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 12808 12809 12810 /* union - case adc_CdrStatus4 [15:00] */ 12811 /* Rx1 :: anaRxStatus :: reserved0 [15:08] */ 12812 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 12813 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 12814 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 12815 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 12816 12817 /* Rx1 :: anaRxStatus :: rx_pwrdn [07:07] */ 12818 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 12819 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 12820 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 12821 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 12822 12823 /* Rx1 :: anaRxStatus :: freq_sel [06:06] */ 12824 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 12825 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 12826 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 12827 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 12828 12829 /* Rx1 :: anaRxStatus :: pll_lock_rstb [05:05] */ 12830 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 12831 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 12832 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 12833 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 12834 12835 /* Rx1 :: anaRxStatus :: pwrdn [04:04] */ 12836 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 12837 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 12838 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 12839 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 12840 12841 /* Rx1 :: anaRxStatus :: reserved1 [03:00] */ 12842 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 12843 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 12844 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 12845 #define RX1_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 12846 12847 12848 /* union - case adc_CdrStatus5 [15:00] */ 12849 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */ 12850 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 12851 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 12852 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 12853 #define RX1_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 12854 12855 12856 /* union - case adc_CdrStatus6 [15:00] */ 12857 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 12858 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 12859 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 12860 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 12861 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 12862 12863 /* Rx1 :: anaRxStatus :: rx_reset [04:04] */ 12864 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 12865 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 12866 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 12867 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 12868 12869 /* Rx1 :: anaRxStatus :: rx_pwrdn [03:03] */ 12870 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 12871 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 12872 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 12873 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 12874 12875 /* Rx1 :: anaRxStatus :: reset_anlg [02:02] */ 12876 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 12877 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 12878 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 12879 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 12880 12881 /* Rx1 :: anaRxStatus :: pwrdn_rx [01:01] */ 12882 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 12883 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 12884 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 12885 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 12886 12887 /* Rx1 :: anaRxStatus :: pwrdn_pll [00:00] */ 12888 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 12889 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 12890 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 12891 #define RX1_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 12892 12893 12894 /* union - case adc_CdrStatus7e [15:00] */ 12895 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 12896 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 12897 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 12898 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 12899 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 12900 12901 /* Rx1 :: anaRxStatus :: rxck0_even [04:04] */ 12902 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 12903 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 12904 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 12905 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 12906 12907 /* Rx1 :: anaRxStatus :: rxck1_even [03:03] */ 12908 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 12909 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 12910 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 12911 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 12912 12913 /* Rx1 :: anaRxStatus :: comdet_even [02:02] */ 12914 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 12915 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 12916 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 12917 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 12918 12919 /* Rx1 :: anaRxStatus :: en_cdet_even [01:01] */ 12920 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 12921 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 12922 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 12923 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 12924 12925 /* Rx1 :: anaRxStatus :: comma_adj_en_even [00:00] */ 12926 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 12927 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 12928 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 12929 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 12930 12931 12932 /* union - case adc_CdrStatus7o [15:00] */ 12933 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 12934 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 12935 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 12936 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 12937 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 12938 12939 /* Rx1 :: anaRxStatus :: rxck0_odd [04:04] */ 12940 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 12941 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 12942 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 12943 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 12944 12945 /* Rx1 :: anaRxStatus :: rxck1_odd [03:03] */ 12946 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 12947 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 12948 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 12949 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 12950 12951 /* Rx1 :: anaRxStatus :: comdet_odd [02:02] */ 12952 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 12953 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 12954 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 12955 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 12956 12957 /* Rx1 :: anaRxStatus :: en_cdet_odd [01:01] */ 12958 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 12959 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 12960 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 12961 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 12962 12963 /* Rx1 :: anaRxStatus :: comma_adj_en_odd [00:00] */ 12964 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 12965 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 12966 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 12967 #define RX1_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 12968 12969 12970 /* union - case adc_CdrStatus8 [15:00] */ 12971 /* Rx1 :: anaRxStatus :: reserved0 [15:01] */ 12972 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 12973 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 12974 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 12975 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 12976 12977 /* Rx1 :: anaRxStatus :: sigdet [00:00] */ 12978 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 12979 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 12980 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 12981 #define RX1_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 12982 12983 12984 /* union - case adc_CdrStatus9 [15:00] */ 12985 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */ 12986 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 12987 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 12988 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 12989 #define RX1_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 12990 12991 12992 /* union - case adc_CdrStatus10 [15:00] */ 12993 /* Rx1 :: anaRxStatus :: reserved0 [15:07] */ 12994 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 12995 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 12996 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 12997 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 12998 12999 /* Rx1 :: anaRxStatus :: prbs_en [06:06] */ 13000 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 13001 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 13002 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 13003 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 13004 13005 /* Rx1 :: anaRxStatus :: rstb_tst [05:05] */ 13006 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 13007 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 13008 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 13009 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 13010 13011 /* Rx1 :: anaRxStatus :: reserved1 [04:04] */ 13012 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 13013 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 13014 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 13015 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 13016 13017 /* Rx1 :: anaRxStatus :: prbs_state [03:00] */ 13018 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 13019 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 13020 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 13021 #define RX1_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 13022 13023 13024 /* union - case adc_CdrStatus11 [15:00] */ 13025 /* Rx1 :: anaRxStatus :: reserved0 [15:00] */ 13026 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 13027 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 13028 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 13029 #define RX1_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 13030 13031 13032 /* union - case adc_CdrStatus12_1 [15:00] */ 13033 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */ 13034 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 13035 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 13036 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 13037 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 13038 13039 /* Rx1 :: anaRxStatus :: enable4 [05:05] */ 13040 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 13041 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 13042 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 13043 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 13044 13045 /* Rx1 :: anaRxStatus :: radr_test [04:00] */ 13046 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 13047 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 13048 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 13049 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 13050 13051 13052 /* union - case adc_CdrStatus12_2 [15:00] */ 13053 /* Rx1 :: anaRxStatus :: reserved0 [15:05] */ 13054 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 13055 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 13056 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 13057 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 13058 13059 /* Rx1 :: anaRxStatus :: wadr_test [04:00] */ 13060 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 13061 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 13062 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 13063 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 13064 13065 13066 /* union - case adc_CdrStatus12_3 [15:00] */ 13067 /* Rx1 :: anaRxStatus :: reserved0 [15:06] */ 13068 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 13069 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 13070 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 13071 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 13072 13073 /* Rx1 :: anaRxStatus :: rxck_66B_tmux [05:05] */ 13074 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 13075 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 13076 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 13077 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 13078 13079 /* Rx1 :: anaRxStatus :: rstb_66B [04:04] */ 13080 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 13081 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 13082 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 13083 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 13084 13085 /* Rx1 :: anaRxStatus :: prstb_66B_mux [03:03] */ 13086 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 13087 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 13088 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 13089 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 13090 13091 /* Rx1 :: anaRxStatus :: rxck_i66_tmux [02:02] */ 13092 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 13093 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 13094 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 13095 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 13096 13097 /* Rx1 :: anaRxStatus :: rstb_i66 [01:01] */ 13098 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 13099 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 13100 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 13101 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 13102 13103 /* Rx1 :: anaRxStatus :: prstb_i66_mux [00:00] */ 13104 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 13105 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 13106 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 13107 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 13108 13109 13110 /* union - case adc_CdrStatus12_4 [15:00] */ 13111 /* Rx1 :: anaRxStatus :: reserved0 [15:04] */ 13112 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 13113 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 13114 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 13115 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 13116 13117 /* Rx1 :: anaRxStatus :: rfifo_error_r [03:02] */ 13118 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 13119 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 13120 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 13121 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 13122 13123 /* Rx1 :: anaRxStatus :: rfifo_unflow [01:01] */ 13124 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 13125 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 13126 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 13127 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 13128 13129 /* Rx1 :: anaRxStatus :: rfifo_ovflow [00:00] */ 13130 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 13131 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 13132 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 13133 #define RX1_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 13134 13135 13136 /* union - case integ_Status [15:00] */ 13137 /* Rx1 :: anaRxStatus :: integ_status [15:00] */ 13138 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 13139 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 13140 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 13141 #define RX1_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 13142 13143 13144 /* union - case vco_Status [15:00] */ 13145 /* Rx1 :: anaRxStatus :: vco_status [15:00] */ 13146 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 13147 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 13148 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 13149 #define RX1_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 13150 13151 13152 /* union - case prbs_Status [15:00] */ 13153 /* Rx1 :: anaRxStatus :: prbs_lock [15:15] */ 13154 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 13155 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 13156 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 13157 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 13158 13159 /* Rx1 :: anaRxStatus :: prbs_stky [14:14] */ 13160 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 13161 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 13162 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 13163 #define RX1_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 13164 13165 /* Rx1 :: anaRxStatus :: ptbs_errors [13:00] */ 13166 #define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 13167 #define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 13168 #define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 13169 #define RX1_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 13170 13171 13172 13173 /**************************************************************************** 13174 * Rx1 :: anaRxControl 13175 */ 13176 /* Rx1 :: anaRxControl :: reserved0 [15:10] */ 13177 #define RX1_ANARXCONTROL_RESERVED0_MASK 0xfc00 13178 #define RX1_ANARXCONTROL_RESERVED0_ALIGN 0 13179 #define RX1_ANARXCONTROL_RESERVED0_BITS 6 13180 #define RX1_ANARXCONTROL_RESERVED0_SHIFT 10 13181 13182 /* Rx1 :: anaRxControl :: override_sigdet_en [09:09] */ 13183 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 13184 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 13185 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 13186 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 13187 13188 /* Rx1 :: anaRxControl :: override_sigdet_val [08:08] */ 13189 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 13190 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 13191 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 13192 #define RX1_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 13193 13194 /* Rx1 :: anaRxControl :: reserved1 [07:03] */ 13195 #define RX1_ANARXCONTROL_RESERVED1_MASK 0x00f8 13196 #define RX1_ANARXCONTROL_RESERVED1_ALIGN 0 13197 #define RX1_ANARXCONTROL_RESERVED1_BITS 5 13198 #define RX1_ANARXCONTROL_RESERVED1_SHIFT 3 13199 13200 /* Rx1 :: anaRxControl :: status_sel [02:00] */ 13201 #define RX1_ANARXCONTROL_STATUS_SEL_MASK 0x0007 13202 #define RX1_ANARXCONTROL_STATUS_SEL_ALIGN 0 13203 #define RX1_ANARXCONTROL_STATUS_SEL_BITS 3 13204 #define RX1_ANARXCONTROL_STATUS_SEL_SHIFT 0 13205 #define RX1_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 13206 #define RX1_ANARXCONTROL_STATUS_SEL_syncStatus 1 13207 #define RX1_ANARXCONTROL_STATUS_SEL_rxTestSel 2 13208 #define RX1_ANARXCONTROL_STATUS_SEL_scaleStatus 3 13209 #define RX1_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 13210 #define RX1_ANARXCONTROL_STATUS_SEL_integStatus 5 13211 #define RX1_ANARXCONTROL_STATUS_SEL_vcoStatus 6 13212 #define RX1_ANARXCONTROL_STATUS_SEL_prbsStatus 7 13213 13214 13215 /**************************************************************************** 13216 * Rx1 :: anaRxTest 13217 */ 13218 /* Rx1 :: anaRxTest :: sigdet_mux_SM [15:12] */ 13219 #define RX1_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 13220 #define RX1_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 13221 #define RX1_ANARXTEST_SIGDET_MUX_SM_BITS 4 13222 #define RX1_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 13223 13224 /* Rx1 :: anaRxTest :: reserved0 [11:09] */ 13225 #define RX1_ANARXTEST_RESERVED0_MASK 0x0e00 13226 #define RX1_ANARXTEST_RESERVED0_ALIGN 0 13227 #define RX1_ANARXTEST_RESERVED0_BITS 3 13228 #define RX1_ANARXTEST_RESERVED0_SHIFT 9 13229 13230 /* Rx1 :: anaRxTest :: tpctrl_SM [08:04] */ 13231 #define RX1_ANARXTEST_TPCTRL_SM_MASK 0x01f0 13232 #define RX1_ANARXTEST_TPCTRL_SM_ALIGN 0 13233 #define RX1_ANARXTEST_TPCTRL_SM_BITS 5 13234 #define RX1_ANARXTEST_TPCTRL_SM_SHIFT 4 13235 13236 /* Rx1 :: anaRxTest :: testMuxSelect_SM [03:00] */ 13237 #define RX1_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 13238 #define RX1_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 13239 #define RX1_ANARXTEST_TESTMUXSELECT_SM_BITS 4 13240 #define RX1_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 13241 13242 13243 /**************************************************************************** 13244 * Rx1 :: anaRxControl1G 13245 */ 13246 /* Rx1 :: anaRxControl1G :: fpat_md [15:15] */ 13247 #define RX1_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 13248 #define RX1_ANARXCONTROL1G_FPAT_MD_ALIGN 0 13249 #define RX1_ANARXCONTROL1G_FPAT_MD_BITS 1 13250 #define RX1_ANARXCONTROL1G_FPAT_MD_SHIFT 15 13251 13252 /* Rx1 :: anaRxControl1G :: pkt_count_en [14:14] */ 13253 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 13254 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 13255 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 13256 #define RX1_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 13257 13258 /* Rx1 :: anaRxControl1G :: staMuxRegDis [13:13] */ 13259 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 13260 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 13261 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 13262 #define RX1_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 13263 13264 /* Rx1 :: anaRxControl1G :: prbs_clr_dis [12:12] */ 13265 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 13266 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 13267 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 13268 #define RX1_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 13269 13270 /* Rx1 :: anaRxControl1G :: rxd_dec_sel [11:11] */ 13271 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 13272 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 13273 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 13274 #define RX1_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 13275 13276 /* Rx1 :: anaRxControl1G :: cgbad_tst [10:10] */ 13277 #define RX1_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 13278 #define RX1_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 13279 #define RX1_ANARXCONTROL1G_CGBAD_TST_BITS 1 13280 #define RX1_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 13281 13282 /* Rx1 :: anaRxControl1G :: Emon_en [09:09] */ 13283 #define RX1_ANARXCONTROL1G_EMON_EN_MASK 0x0200 13284 #define RX1_ANARXCONTROL1G_EMON_EN_ALIGN 0 13285 #define RX1_ANARXCONTROL1G_EMON_EN_BITS 1 13286 #define RX1_ANARXCONTROL1G_EMON_EN_SHIFT 9 13287 13288 /* Rx1 :: anaRxControl1G :: prbs_en [08:08] */ 13289 #define RX1_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 13290 #define RX1_ANARXCONTROL1G_PRBS_EN_ALIGN 0 13291 #define RX1_ANARXCONTROL1G_PRBS_EN_BITS 1 13292 #define RX1_ANARXCONTROL1G_PRBS_EN_SHIFT 8 13293 13294 /* Rx1 :: anaRxControl1G :: cgbad_en [07:07] */ 13295 #define RX1_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 13296 #define RX1_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 13297 #define RX1_ANARXCONTROL1G_CGBAD_EN_BITS 1 13298 #define RX1_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 13299 13300 /* Rx1 :: anaRxControl1G :: cstretch [06:06] */ 13301 #define RX1_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 13302 #define RX1_ANARXCONTROL1G_CSTRETCH_ALIGN 0 13303 #define RX1_ANARXCONTROL1G_CSTRETCH_BITS 1 13304 #define RX1_ANARXCONTROL1G_CSTRETCH_SHIFT 6 13305 13306 /* Rx1 :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 13307 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 13308 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 13309 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 13310 #define RX1_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 13311 13312 /* Rx1 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 13313 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 13314 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 13315 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 13316 #define RX1_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 13317 13318 /* Rx1 :: anaRxControl1G :: reserved0 [03:02] */ 13319 #define RX1_ANARXCONTROL1G_RESERVED0_MASK 0x000c 13320 #define RX1_ANARXCONTROL1G_RESERVED0_ALIGN 0 13321 #define RX1_ANARXCONTROL1G_RESERVED0_BITS 2 13322 #define RX1_ANARXCONTROL1G_RESERVED0_SHIFT 2 13323 13324 /* Rx1 :: anaRxControl1G :: freq_sel_force [01:01] */ 13325 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 13326 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 13327 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 13328 #define RX1_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 13329 13330 /* Rx1 :: anaRxControl1G :: freq_sel [00:00] */ 13331 #define RX1_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 13332 #define RX1_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 13333 #define RX1_ANARXCONTROL1G_FREQ_SEL_BITS 1 13334 #define RX1_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 13335 13336 13337 /**************************************************************************** 13338 * Rx1 :: anaRxControlPci 13339 */ 13340 /* Rx1 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 13341 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 13342 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 13343 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 13344 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 13345 13346 /* Rx1 :: anaRxControlPci :: comma_mask_force_r [14:14] */ 13347 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 13348 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 13349 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 13350 #define RX1_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 13351 13352 /* Rx1 :: anaRxControlPci :: comma_mask_r [13:13] */ 13353 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 13354 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 13355 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 13356 #define RX1_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 13357 13358 /* Rx1 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 13359 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 13360 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 13361 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 13362 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 13363 13364 /* Rx1 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 13365 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 13366 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 13367 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 13368 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 13369 13370 /* Rx1 :: anaRxControlPci :: sync_status_force_r [10:10] */ 13371 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 13372 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 13373 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 13374 #define RX1_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 13375 13376 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 13377 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 13378 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 13379 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 13380 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 13381 13382 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 13383 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 13384 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 13385 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 13386 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 13387 13388 /* Rx1 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 13389 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 13390 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 13391 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 13392 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 13393 13394 /* Rx1 :: anaRxControlPci :: comma_adj_en_r [06:06] */ 13395 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 13396 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 13397 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 13398 #define RX1_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 13399 13400 /* Rx1 :: anaRxControlPci :: link_en_force_SM [05:05] */ 13401 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 13402 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 13403 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 13404 #define RX1_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 13405 13406 /* Rx1 :: anaRxControlPci :: link_en_r [04:04] */ 13407 #define RX1_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 13408 #define RX1_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 13409 #define RX1_ANARXCONTROLPCI_LINK_EN_R_BITS 1 13410 #define RX1_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 13411 13412 /* Rx1 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 13413 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 13414 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 13415 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 13416 #define RX1_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 13417 13418 /* Rx1 :: anaRxControlPci :: rx_polarity_r [02:02] */ 13419 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 13420 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 13421 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 13422 #define RX1_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 13423 13424 /* Rx1 :: anaRxControlPci :: integ_mode_SM [01:00] */ 13425 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 13426 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 13427 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 13428 #define RX1_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 13429 13430 13431 /**************************************************************************** 13432 * Rx1 :: anaRxAstatus 13433 */ 13434 /* Rx1 :: anaRxAstatus :: sigdet [15:15] */ 13435 #define RX1_ANARXASTATUS_SIGDET_MASK 0x8000 13436 #define RX1_ANARXASTATUS_SIGDET_ALIGN 0 13437 #define RX1_ANARXASTATUS_SIGDET_BITS 1 13438 #define RX1_ANARXASTATUS_SIGDET_SHIFT 15 13439 13440 /* Rx1 :: anaRxAstatus :: rx_pf [14:12] */ 13441 #define RX1_ANARXASTATUS_RX_PF_MASK 0x7000 13442 #define RX1_ANARXASTATUS_RX_PF_ALIGN 0 13443 #define RX1_ANARXASTATUS_RX_PF_BITS 3 13444 #define RX1_ANARXASTATUS_RX_PF_SHIFT 12 13445 13446 /* Rx1 :: anaRxAstatus :: dfe [11:06] */ 13447 #define RX1_ANARXASTATUS_DFE_MASK 0x0fc0 13448 #define RX1_ANARXASTATUS_DFE_ALIGN 0 13449 #define RX1_ANARXASTATUS_DFE_BITS 6 13450 #define RX1_ANARXASTATUS_DFE_SHIFT 6 13451 13452 /* Rx1 :: anaRxAstatus :: reserved0 [05:05] */ 13453 #define RX1_ANARXASTATUS_RESERVED0_MASK 0x0020 13454 #define RX1_ANARXASTATUS_RESERVED0_ALIGN 0 13455 #define RX1_ANARXASTATUS_RESERVED0_BITS 1 13456 #define RX1_ANARXASTATUS_RESERVED0_SHIFT 5 13457 13458 /* Rx1 :: anaRxAstatus :: vga [04:00] */ 13459 #define RX1_ANARXASTATUS_VGA_MASK 0x001f 13460 #define RX1_ANARXASTATUS_VGA_ALIGN 0 13461 #define RX1_ANARXASTATUS_VGA_BITS 5 13462 #define RX1_ANARXASTATUS_VGA_SHIFT 0 13463 13464 13465 /**************************************************************************** 13466 * Rx1 :: anaRxAControl1 13467 */ 13468 /* Rx1 :: anaRxAControl1 :: imode_vcm [15:15] */ 13469 #define RX1_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 13470 #define RX1_ANARXACONTROL1_IMODE_VCM_ALIGN 0 13471 #define RX1_ANARXACONTROL1_IMODE_VCM_BITS 1 13472 #define RX1_ANARXACONTROL1_IMODE_VCM_SHIFT 15 13473 13474 /* Rx1 :: anaRxAControl1 :: imin_vcm [14:14] */ 13475 #define RX1_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 13476 #define RX1_ANARXACONTROL1_IMIN_VCM_ALIGN 0 13477 #define RX1_ANARXACONTROL1_IMIN_VCM_BITS 1 13478 #define RX1_ANARXACONTROL1_IMIN_VCM_SHIFT 14 13479 13480 /* Rx1 :: anaRxAControl1 :: imax_sigdet [13:13] */ 13481 #define RX1_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 13482 #define RX1_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 13483 #define RX1_ANARXACONTROL1_IMAX_SIGDET_BITS 1 13484 #define RX1_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 13485 13486 /* Rx1 :: anaRxAControl1 :: imode_sigdet [12:12] */ 13487 #define RX1_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 13488 #define RX1_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 13489 #define RX1_ANARXACONTROL1_IMODE_SIGDET_BITS 1 13490 #define RX1_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 13491 13492 /* Rx1 :: anaRxAControl1 :: imin_sigdet [11:11] */ 13493 #define RX1_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 13494 #define RX1_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 13495 #define RX1_ANARXACONTROL1_IMIN_SIGDET_BITS 1 13496 #define RX1_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 13497 13498 /* Rx1 :: anaRxAControl1 :: refh_rx [10:10] */ 13499 #define RX1_ANARXACONTROL1_REFH_RX_MASK 0x0400 13500 #define RX1_ANARXACONTROL1_REFH_RX_ALIGN 0 13501 #define RX1_ANARXACONTROL1_REFH_RX_BITS 1 13502 #define RX1_ANARXACONTROL1_REFH_RX_SHIFT 10 13503 13504 /* Rx1 :: anaRxAControl1 :: refl_rx [09:09] */ 13505 #define RX1_ANARXACONTROL1_REFL_RX_MASK 0x0200 13506 #define RX1_ANARXACONTROL1_REFL_RX_ALIGN 0 13507 #define RX1_ANARXACONTROL1_REFL_RX_BITS 1 13508 #define RX1_ANARXACONTROL1_REFL_RX_SHIFT 9 13509 13510 /* Rx1 :: anaRxAControl1 :: tport_en [08:08] */ 13511 #define RX1_ANARXACONTROL1_TPORT_EN_MASK 0x0100 13512 #define RX1_ANARXACONTROL1_TPORT_EN_ALIGN 0 13513 #define RX1_ANARXACONTROL1_TPORT_EN_BITS 1 13514 #define RX1_ANARXACONTROL1_TPORT_EN_SHIFT 8 13515 13516 /* Rx1 :: anaRxAControl1 :: vddrb_bg [07:07] */ 13517 #define RX1_ANARXACONTROL1_VDDRB_BG_MASK 0x0080 13518 #define RX1_ANARXACONTROL1_VDDRB_BG_ALIGN 0 13519 #define RX1_ANARXACONTROL1_VDDRB_BG_BITS 1 13520 #define RX1_ANARXACONTROL1_VDDRB_BG_SHIFT 7 13521 13522 /* Rx1 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 13523 #define RX1_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 13524 #define RX1_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 13525 #define RX1_ANARXACONTROL1_SIG_PWRDN_BITS 1 13526 #define RX1_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 13527 13528 /* Rx1 :: anaRxAControl1 :: offset_ctrl [05:03] */ 13529 #define RX1_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 13530 #define RX1_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 13531 #define RX1_ANARXACONTROL1_OFFSET_CTRL_BITS 3 13532 #define RX1_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 13533 13534 /* Rx1 :: anaRxAControl1 :: offset_sel [02:02] */ 13535 #define RX1_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 13536 #define RX1_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 13537 #define RX1_ANARXACONTROL1_OFFSET_SEL_BITS 1 13538 #define RX1_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 13539 13540 /* Rx1 :: anaRxAControl1 :: reserved0 [01:00] */ 13541 #define RX1_ANARXACONTROL1_RESERVED0_MASK 0x0003 13542 #define RX1_ANARXACONTROL1_RESERVED0_ALIGN 0 13543 #define RX1_ANARXACONTROL1_RESERVED0_BITS 2 13544 #define RX1_ANARXACONTROL1_RESERVED0_SHIFT 0 13545 13546 13547 /**************************************************************************** 13548 * Rx1 :: anaRxAControl2 13549 */ 13550 /* Rx1 :: anaRxAControl2 :: imax_clkbuf [15:15] */ 13551 #define RX1_ANARXACONTROL2_IMAX_CLKBUF_MASK 0x8000 13552 #define RX1_ANARXACONTROL2_IMAX_CLKBUF_ALIGN 0 13553 #define RX1_ANARXACONTROL2_IMAX_CLKBUF_BITS 1 13554 #define RX1_ANARXACONTROL2_IMAX_CLKBUF_SHIFT 15 13555 13556 /* Rx1 :: anaRxAControl2 :: imode_clkbuf [14:14] */ 13557 #define RX1_ANARXACONTROL2_IMODE_CLKBUF_MASK 0x4000 13558 #define RX1_ANARXACONTROL2_IMODE_CLKBUF_ALIGN 0 13559 #define RX1_ANARXACONTROL2_IMODE_CLKBUF_BITS 1 13560 #define RX1_ANARXACONTROL2_IMODE_CLKBUF_SHIFT 14 13561 13562 /* Rx1 :: anaRxAControl2 :: imin_clkbuf [13:13] */ 13563 #define RX1_ANARXACONTROL2_IMIN_CLKBUF_MASK 0x2000 13564 #define RX1_ANARXACONTROL2_IMIN_CLKBUF_ALIGN 0 13565 #define RX1_ANARXACONTROL2_IMIN_CLKBUF_BITS 1 13566 #define RX1_ANARXACONTROL2_IMIN_CLKBUF_SHIFT 13 13567 13568 /* Rx1 :: anaRxAControl2 :: imax_eqfl [12:12] */ 13569 #define RX1_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 13570 #define RX1_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 13571 #define RX1_ANARXACONTROL2_IMAX_EQFL_BITS 1 13572 #define RX1_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 13573 13574 /* Rx1 :: anaRxAControl2 :: imode_eqfl [11:11] */ 13575 #define RX1_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 13576 #define RX1_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 13577 #define RX1_ANARXACONTROL2_IMODE_EQFL_BITS 1 13578 #define RX1_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 13579 13580 /* Rx1 :: anaRxAControl2 :: imin_eqfl [10:10] */ 13581 #define RX1_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 13582 #define RX1_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 13583 #define RX1_ANARXACONTROL2_IMIN_EQFL_BITS 1 13584 #define RX1_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 13585 13586 /* Rx1 :: anaRxAControl2 :: imax_dfesum [09:09] */ 13587 #define RX1_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 13588 #define RX1_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 13589 #define RX1_ANARXACONTROL2_IMAX_DFESUM_BITS 1 13590 #define RX1_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 13591 13592 /* Rx1 :: anaRxAControl2 :: imode_dfesum [08:08] */ 13593 #define RX1_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 13594 #define RX1_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 13595 #define RX1_ANARXACONTROL2_IMODE_DFESUM_BITS 1 13596 #define RX1_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 13597 13598 /* Rx1 :: anaRxAControl2 :: imin_dfesum [07:07] */ 13599 #define RX1_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 13600 #define RX1_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 13601 #define RX1_ANARXACONTROL2_IMIN_DFESUM_BITS 1 13602 #define RX1_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 13603 13604 /* Rx1 :: anaRxAControl2 :: imax_vga [06:06] */ 13605 #define RX1_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 13606 #define RX1_ANARXACONTROL2_IMAX_VGA_ALIGN 0 13607 #define RX1_ANARXACONTROL2_IMAX_VGA_BITS 1 13608 #define RX1_ANARXACONTROL2_IMAX_VGA_SHIFT 6 13609 13610 /* Rx1 :: anaRxAControl2 :: imode_vga [05:05] */ 13611 #define RX1_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 13612 #define RX1_ANARXACONTROL2_IMODE_VGA_ALIGN 0 13613 #define RX1_ANARXACONTROL2_IMODE_VGA_BITS 1 13614 #define RX1_ANARXACONTROL2_IMODE_VGA_SHIFT 5 13615 13616 /* Rx1 :: anaRxAControl2 :: imin_vga [04:04] */ 13617 #define RX1_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 13618 #define RX1_ANARXACONTROL2_IMIN_VGA_ALIGN 0 13619 #define RX1_ANARXACONTROL2_IMIN_VGA_BITS 1 13620 #define RX1_ANARXACONTROL2_IMIN_VGA_SHIFT 4 13621 13622 /* Rx1 :: anaRxAControl2 :: imax_interp [03:03] */ 13623 #define RX1_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 13624 #define RX1_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 13625 #define RX1_ANARXACONTROL2_IMAX_INTERP_BITS 1 13626 #define RX1_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 13627 13628 /* Rx1 :: anaRxAControl2 :: imode_interp [02:02] */ 13629 #define RX1_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 13630 #define RX1_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 13631 #define RX1_ANARXACONTROL2_IMODE_INTERP_BITS 1 13632 #define RX1_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 13633 13634 /* Rx1 :: anaRxAControl2 :: imin_interp [01:01] */ 13635 #define RX1_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 13636 #define RX1_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 13637 #define RX1_ANARXACONTROL2_IMIN_INTERP_BITS 1 13638 #define RX1_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 13639 13640 /* Rx1 :: anaRxAControl2 :: imax_vcm [00:00] */ 13641 #define RX1_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 13642 #define RX1_ANARXACONTROL2_IMAX_VCM_ALIGN 0 13643 #define RX1_ANARXACONTROL2_IMAX_VCM_BITS 1 13644 #define RX1_ANARXACONTROL2_IMAX_VCM_SHIFT 0 13645 13646 13647 /**************************************************************************** 13648 * Rx1 :: anaRxAControl3 13649 */ 13650 /* Rx1 :: anaRxAControl3 :: en_clk16 [15:15] */ 13651 #define RX1_ANARXACONTROL3_EN_CLK16_MASK 0x8000 13652 #define RX1_ANARXACONTROL3_EN_CLK16_ALIGN 0 13653 #define RX1_ANARXACONTROL3_EN_CLK16_BITS 1 13654 #define RX1_ANARXACONTROL3_EN_CLK16_SHIFT 15 13655 13656 /* Rx1 :: anaRxAControl3 :: pd_ch_p1 [14:14] */ 13657 #define RX1_ANARXACONTROL3_PD_CH_P1_MASK 0x4000 13658 #define RX1_ANARXACONTROL3_PD_CH_P1_ALIGN 0 13659 #define RX1_ANARXACONTROL3_PD_CH_P1_BITS 1 13660 #define RX1_ANARXACONTROL3_PD_CH_P1_SHIFT 14 13661 13662 /* Rx1 :: anaRxAControl3 :: en_vcctrl [13:13] */ 13663 #define RX1_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 13664 #define RX1_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 13665 #define RX1_ANARXACONTROL3_EN_VCCTRL_BITS 1 13666 #define RX1_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 13667 13668 /* Rx1 :: anaRxAControl3 :: en_dfeclk [12:12] */ 13669 #define RX1_ANARXACONTROL3_EN_DFECLK_MASK 0x1000 13670 #define RX1_ANARXACONTROL3_EN_DFECLK_ALIGN 0 13671 #define RX1_ANARXACONTROL3_EN_DFECLK_BITS 1 13672 #define RX1_ANARXACONTROL3_EN_DFECLK_SHIFT 12 13673 13674 /* Rx1 :: anaRxAControl3 :: en_hgain [11:11] */ 13675 #define RX1_ANARXACONTROL3_EN_HGAIN_MASK 0x0800 13676 #define RX1_ANARXACONTROL3_EN_HGAIN_ALIGN 0 13677 #define RX1_ANARXACONTROL3_EN_HGAIN_BITS 1 13678 #define RX1_ANARXACONTROL3_EN_HGAIN_SHIFT 11 13679 13680 /* Rx1 :: anaRxAControl3 :: en_dfeckpwr [10:10] */ 13681 #define RX1_ANARXACONTROL3_EN_DFECKPWR_MASK 0x0400 13682 #define RX1_ANARXACONTROL3_EN_DFECKPWR_ALIGN 0 13683 #define RX1_ANARXACONTROL3_EN_DFECKPWR_BITS 1 13684 #define RX1_ANARXACONTROL3_EN_DFECKPWR_SHIFT 10 13685 13686 /* Rx1 :: anaRxAControl3 :: offset_pd [09:09] */ 13687 #define RX1_ANARXACONTROL3_OFFSET_PD_MASK 0x0200 13688 #define RX1_ANARXACONTROL3_OFFSET_PD_ALIGN 0 13689 #define RX1_ANARXACONTROL3_OFFSET_PD_BITS 1 13690 #define RX1_ANARXACONTROL3_OFFSET_PD_SHIFT 9 13691 13692 /* Rx1 :: anaRxAControl3 :: imax_dfetap [08:08] */ 13693 #define RX1_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 13694 #define RX1_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 13695 #define RX1_ANARXACONTROL3_IMAX_DFETAP_BITS 1 13696 #define RX1_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 13697 13698 /* Rx1 :: anaRxAControl3 :: imode_dfetap [07:07] */ 13699 #define RX1_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 13700 #define RX1_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 13701 #define RX1_ANARXACONTROL3_IMODE_DFETAP_BITS 1 13702 #define RX1_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 13703 13704 /* Rx1 :: anaRxAControl3 :: imin_dfetap [06:06] */ 13705 #define RX1_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 13706 #define RX1_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 13707 #define RX1_ANARXACONTROL3_IMIN_DFETAP_BITS 1 13708 #define RX1_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 13709 13710 /* Rx1 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 13711 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 13712 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 13713 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 13714 #define RX1_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 13715 13716 /* Rx1 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 13717 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 13718 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 13719 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 13720 #define RX1_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 13721 13722 /* Rx1 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 13723 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 13724 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 13725 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 13726 #define RX1_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 13727 13728 /* Rx1 :: anaRxAControl3 :: imax_dfevref [02:02] */ 13729 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 13730 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 13731 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 13732 #define RX1_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 13733 13734 /* Rx1 :: anaRxAControl3 :: imode_dfevref [01:01] */ 13735 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 13736 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 13737 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 13738 #define RX1_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 13739 13740 /* Rx1 :: anaRxAControl3 :: imin_dfevref [00:00] */ 13741 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 13742 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 13743 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 13744 #define RX1_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 13745 13746 13747 /**************************************************************************** 13748 * Hypercore_USER_Rx2 13749 */ 13750 /**************************************************************************** 13751 * Rx2 :: anaRxStatus 13752 */ 13753 /* union - case sigdet_Status [15:00] */ 13754 /* Rx2 :: anaRxStatus :: cx4_sigdet [15:15] */ 13755 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 13756 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 13757 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 13758 #define RX2_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 13759 13760 /* Rx2 :: anaRxStatus :: reserved0 [14:13] */ 13761 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 13762 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 13763 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 13764 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 13765 13766 /* Rx2 :: anaRxStatus :: rxSeqDone [12:12] */ 13767 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 13768 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 13769 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 13770 #define RX2_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 13771 13772 /* Rx2 :: anaRxStatus :: rx_sigdet_ll [11:11] */ 13773 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 13774 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 13775 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 13776 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 13777 13778 /* Rx2 :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 13779 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 13780 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 13781 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 13782 #define RX2_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 13783 13784 /* Rx2 :: anaRxStatus :: rx_reset [09:09] */ 13785 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 13786 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 13787 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 13788 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 13789 13790 /* Rx2 :: anaRxStatus :: rx_pwrdn [08:08] */ 13791 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 13792 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 13793 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 13794 #define RX2_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 13795 13796 /* Rx2 :: anaRxStatus :: reserved1 [07:00] */ 13797 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 13798 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 13799 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 13800 #define RX2_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 13801 13802 13803 /* union - case sync_Status [15:00] */ 13804 /* Rx2 :: anaRxStatus :: reserved0 [15:11] */ 13805 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 13806 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 13807 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 13808 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 13809 13810 /* Rx2 :: anaRxStatus :: test_acq_en [10:10] */ 13811 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 13812 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 13813 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 13814 #define RX2_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 13815 13816 /* Rx2 :: anaRxStatus :: reserved1 [09:09] */ 13817 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 13818 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 13819 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 13820 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 13821 13822 /* Rx2 :: anaRxStatus :: rxSeqStart [08:08] */ 13823 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 13824 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 13825 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 13826 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 13827 13828 /* Rx2 :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 13829 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 13830 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 13831 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 13832 #define RX2_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 13833 13834 /* Rx2 :: anaRxStatus :: sync_status [06:06] */ 13835 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 13836 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 13837 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 13838 #define RX2_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 13839 13840 /* Rx2 :: anaRxStatus :: rx_sigdet [05:05] */ 13841 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 13842 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 13843 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 13844 #define RX2_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 13845 13846 /* Rx2 :: anaRxStatus :: reserved2 [04:03] */ 13847 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 13848 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 13849 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 13850 #define RX2_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 13851 13852 /* Rx2 :: anaRxStatus :: saturate_status [02:02] */ 13853 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 13854 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 13855 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 13856 #define RX2_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 13857 13858 /* Rx2 :: anaRxStatus :: cx4_sigdet [01:01] */ 13859 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 13860 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 13861 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 13862 #define RX2_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 13863 13864 /* Rx2 :: anaRxStatus :: rxSeqDone [00:00] */ 13865 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 13866 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 13867 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 13868 #define RX2_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 13869 13870 13871 /* union - case rxTestSel_0 [15:00] */ 13872 /* Rx2 :: anaRxStatus :: reserved0 [15:10] */ 13873 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 13874 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 13875 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 13876 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 13877 13878 /* Rx2 :: anaRxStatus :: indck_mode_en [09:09] */ 13879 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 13880 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 13881 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 13882 #define RX2_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 13883 13884 /* Rx2 :: anaRxStatus :: pci_mode_en [08:08] */ 13885 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 13886 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 13887 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 13888 #define RX2_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 13889 13890 /* Rx2 :: anaRxStatus :: rx_polarity [07:07] */ 13891 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 13892 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 13893 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 13894 #define RX2_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 13895 13896 /* Rx2 :: anaRxStatus :: rxpol_flip [06:06] */ 13897 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 13898 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 13899 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 13900 #define RX2_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 13901 13902 /* Rx2 :: anaRxStatus :: comma_mask [05:05] */ 13903 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 13904 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 13905 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 13906 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 13907 13908 /* Rx2 :: anaRxStatus :: link_en_r [04:04] */ 13909 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 13910 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 13911 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 13912 #define RX2_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 13913 13914 /* Rx2 :: anaRxStatus :: comma_adj_en [03:03] */ 13915 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 13916 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 13917 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 13918 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 13919 13920 /* Rx2 :: anaRxStatus :: comma_adj_en_ext [02:02] */ 13921 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 13922 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 13923 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 13924 #define RX2_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 13925 13926 /* Rx2 :: anaRxStatus :: reserved1 [01:00] */ 13927 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 13928 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 13929 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 13930 #define RX2_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 13931 13932 13933 /* union - case rxTestSel_1 [15:00] */ 13934 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 13935 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 13936 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 13937 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 13938 #define RX2_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 13939 13940 /* Rx2 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 13941 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 13942 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 13943 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 13944 #define RX2_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 13945 13946 /* Rx2 :: anaRxStatus :: freq_sel_PC [03:03] */ 13947 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 13948 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 13949 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 13950 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 13951 13952 /* Rx2 :: anaRxStatus :: freq_sel_SM [02:02] */ 13953 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 13954 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 13955 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 13956 #define RX2_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 13957 13958 /* Rx2 :: anaRxStatus :: integ_mode_SM [01:00] */ 13959 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 13960 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 13961 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 13962 #define RX2_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 13963 13964 13965 /* union - case scale_Status [15:00] */ 13966 /* Rx2 :: anaRxStatus :: prop_scale [15:12] */ 13967 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 13968 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 13969 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 13970 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 13971 13972 /* Rx2 :: anaRxStatus :: integ_scale [11:08] */ 13973 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 13974 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 13975 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 13976 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 13977 13978 /* Rx2 :: anaRxStatus :: prop_scale_acq [07:04] */ 13979 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 13980 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 13981 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 13982 #define RX2_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 13983 13984 /* Rx2 :: anaRxStatus :: integ_scale_acq [03:00] */ 13985 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 13986 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 13987 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 13988 #define RX2_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 13989 13990 13991 /* union - case adc_CdrStatus1 [15:00] */ 13992 /* Rx2 :: anaRxStatus :: reserved0 [15:07] */ 13993 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 13994 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 13995 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 13996 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 13997 13998 /* Rx2 :: anaRxStatus :: rxMuxCkSel [06:06] */ 13999 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 14000 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 14001 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 14002 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 14003 14004 /* Rx2 :: anaRxStatus :: glpbk_combo [05:05] */ 14005 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 14006 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 14007 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 14008 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 14009 14010 /* Rx2 :: anaRxStatus :: clockSwitchSel [04:04] */ 14011 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 14012 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 14013 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 14014 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 14015 14016 /* Rx2 :: anaRxStatus :: rxck_tst [03:03] */ 14017 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 14018 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 14019 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 14020 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 14021 14022 /* Rx2 :: anaRxStatus :: rxck_i [02:02] */ 14023 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 14024 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 14025 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 14026 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 14027 14028 /* Rx2 :: anaRxStatus :: refclk [01:01] */ 14029 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 14030 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 14031 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 14032 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 14033 14034 /* Rx2 :: anaRxStatus :: pll_bypass [00:00] */ 14035 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 14036 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 14037 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 14038 #define RX2_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 14039 14040 14041 /* union - case adc_CdrStatus2 [15:00] */ 14042 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */ 14043 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 14044 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 14045 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 14046 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 14047 14048 /* Rx2 :: anaRxStatus :: rxMuxCkSel [05:05] */ 14049 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 14050 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 14051 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 14052 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 14053 14054 /* Rx2 :: anaRxStatus :: rxSeqStart [04:04] */ 14055 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 14056 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 14057 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 14058 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 14059 14060 /* Rx2 :: anaRxStatus :: reserved1 [03:01] */ 14061 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 14062 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 14063 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 14064 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 14065 14066 /* Rx2 :: anaRxStatus :: rxSeqDone [00:00] */ 14067 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 14068 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 14069 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 14070 #define RX2_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 14071 14072 14073 /* union - case adc_CdrStatus3 [15:00] */ 14074 /* Rx2 :: anaRxStatus :: reserved0 [15:04] */ 14075 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 14076 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 14077 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 14078 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 14079 14080 /* Rx2 :: anaRxStatus :: rxSeqStart [03:03] */ 14081 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 14082 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 14083 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 14084 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 14085 14086 /* Rx2 :: anaRxStatus :: reserved1 [02:01] */ 14087 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 14088 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 14089 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 14090 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 14091 14092 /* Rx2 :: anaRxStatus :: allow_increment_PC [00:00] */ 14093 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 14094 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 14095 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 14096 #define RX2_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 14097 14098 14099 /* union - case adc_CdrStatus4 [15:00] */ 14100 /* Rx2 :: anaRxStatus :: reserved0 [15:08] */ 14101 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 14102 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 14103 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 14104 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 14105 14106 /* Rx2 :: anaRxStatus :: rx_pwrdn [07:07] */ 14107 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 14108 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 14109 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 14110 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 14111 14112 /* Rx2 :: anaRxStatus :: freq_sel [06:06] */ 14113 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 14114 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 14115 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 14116 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 14117 14118 /* Rx2 :: anaRxStatus :: pll_lock_rstb [05:05] */ 14119 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 14120 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 14121 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 14122 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 14123 14124 /* Rx2 :: anaRxStatus :: pwrdn [04:04] */ 14125 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 14126 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 14127 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 14128 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 14129 14130 /* Rx2 :: anaRxStatus :: reserved1 [03:00] */ 14131 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 14132 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 14133 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 14134 #define RX2_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 14135 14136 14137 /* union - case adc_CdrStatus5 [15:00] */ 14138 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */ 14139 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 14140 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 14141 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 14142 #define RX2_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 14143 14144 14145 /* union - case adc_CdrStatus6 [15:00] */ 14146 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 14147 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 14148 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 14149 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 14150 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 14151 14152 /* Rx2 :: anaRxStatus :: rx_reset [04:04] */ 14153 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 14154 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 14155 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 14156 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 14157 14158 /* Rx2 :: anaRxStatus :: rx_pwrdn [03:03] */ 14159 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 14160 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 14161 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 14162 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 14163 14164 /* Rx2 :: anaRxStatus :: reset_anlg [02:02] */ 14165 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 14166 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 14167 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 14168 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 14169 14170 /* Rx2 :: anaRxStatus :: pwrdn_rx [01:01] */ 14171 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 14172 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 14173 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 14174 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 14175 14176 /* Rx2 :: anaRxStatus :: pwrdn_pll [00:00] */ 14177 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 14178 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 14179 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 14180 #define RX2_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 14181 14182 14183 /* union - case adc_CdrStatus7e [15:00] */ 14184 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 14185 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 14186 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 14187 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 14188 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 14189 14190 /* Rx2 :: anaRxStatus :: rxck0_even [04:04] */ 14191 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 14192 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 14193 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 14194 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 14195 14196 /* Rx2 :: anaRxStatus :: rxck1_even [03:03] */ 14197 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 14198 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 14199 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 14200 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 14201 14202 /* Rx2 :: anaRxStatus :: comdet_even [02:02] */ 14203 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 14204 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 14205 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 14206 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 14207 14208 /* Rx2 :: anaRxStatus :: en_cdet_even [01:01] */ 14209 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 14210 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 14211 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 14212 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 14213 14214 /* Rx2 :: anaRxStatus :: comma_adj_en_even [00:00] */ 14215 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 14216 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 14217 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 14218 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 14219 14220 14221 /* union - case adc_CdrStatus7o [15:00] */ 14222 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 14223 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 14224 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 14225 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 14226 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 14227 14228 /* Rx2 :: anaRxStatus :: rxck0_odd [04:04] */ 14229 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 14230 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 14231 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 14232 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 14233 14234 /* Rx2 :: anaRxStatus :: rxck1_odd [03:03] */ 14235 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 14236 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 14237 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 14238 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 14239 14240 /* Rx2 :: anaRxStatus :: comdet_odd [02:02] */ 14241 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 14242 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 14243 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 14244 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 14245 14246 /* Rx2 :: anaRxStatus :: en_cdet_odd [01:01] */ 14247 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 14248 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 14249 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 14250 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 14251 14252 /* Rx2 :: anaRxStatus :: comma_adj_en_odd [00:00] */ 14253 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 14254 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 14255 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 14256 #define RX2_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 14257 14258 14259 /* union - case adc_CdrStatus8 [15:00] */ 14260 /* Rx2 :: anaRxStatus :: reserved0 [15:01] */ 14261 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 14262 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 14263 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 14264 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 14265 14266 /* Rx2 :: anaRxStatus :: sigdet [00:00] */ 14267 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 14268 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 14269 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 14270 #define RX2_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 14271 14272 14273 /* union - case adc_CdrStatus9 [15:00] */ 14274 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */ 14275 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 14276 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 14277 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 14278 #define RX2_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 14279 14280 14281 /* union - case adc_CdrStatus10 [15:00] */ 14282 /* Rx2 :: anaRxStatus :: reserved0 [15:07] */ 14283 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 14284 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 14285 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 14286 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 14287 14288 /* Rx2 :: anaRxStatus :: prbs_en [06:06] */ 14289 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 14290 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 14291 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 14292 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 14293 14294 /* Rx2 :: anaRxStatus :: rstb_tst [05:05] */ 14295 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 14296 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 14297 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 14298 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 14299 14300 /* Rx2 :: anaRxStatus :: reserved1 [04:04] */ 14301 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 14302 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 14303 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 14304 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 14305 14306 /* Rx2 :: anaRxStatus :: prbs_state [03:00] */ 14307 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 14308 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 14309 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 14310 #define RX2_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 14311 14312 14313 /* union - case adc_CdrStatus11 [15:00] */ 14314 /* Rx2 :: anaRxStatus :: reserved0 [15:00] */ 14315 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 14316 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 14317 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 14318 #define RX2_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 14319 14320 14321 /* union - case adc_CdrStatus12_1 [15:00] */ 14322 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */ 14323 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 14324 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 14325 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 14326 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 14327 14328 /* Rx2 :: anaRxStatus :: enable4 [05:05] */ 14329 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 14330 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 14331 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 14332 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 14333 14334 /* Rx2 :: anaRxStatus :: radr_test [04:00] */ 14335 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 14336 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 14337 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 14338 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 14339 14340 14341 /* union - case adc_CdrStatus12_2 [15:00] */ 14342 /* Rx2 :: anaRxStatus :: reserved0 [15:05] */ 14343 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 14344 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 14345 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 14346 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 14347 14348 /* Rx2 :: anaRxStatus :: wadr_test [04:00] */ 14349 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 14350 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 14351 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 14352 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 14353 14354 14355 /* union - case adc_CdrStatus12_3 [15:00] */ 14356 /* Rx2 :: anaRxStatus :: reserved0 [15:06] */ 14357 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 14358 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 14359 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 14360 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 14361 14362 /* Rx2 :: anaRxStatus :: rxck_66B_tmux [05:05] */ 14363 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 14364 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 14365 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 14366 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 14367 14368 /* Rx2 :: anaRxStatus :: rstb_66B [04:04] */ 14369 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 14370 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 14371 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 14372 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 14373 14374 /* Rx2 :: anaRxStatus :: prstb_66B_mux [03:03] */ 14375 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 14376 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 14377 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 14378 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 14379 14380 /* Rx2 :: anaRxStatus :: rxck_i66_tmux [02:02] */ 14381 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 14382 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 14383 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 14384 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 14385 14386 /* Rx2 :: anaRxStatus :: rstb_i66 [01:01] */ 14387 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 14388 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 14389 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 14390 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 14391 14392 /* Rx2 :: anaRxStatus :: prstb_i66_mux [00:00] */ 14393 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 14394 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 14395 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 14396 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 14397 14398 14399 /* union - case adc_CdrStatus12_4 [15:00] */ 14400 /* Rx2 :: anaRxStatus :: reserved0 [15:04] */ 14401 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 14402 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 14403 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 14404 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 14405 14406 /* Rx2 :: anaRxStatus :: rfifo_error_r [03:02] */ 14407 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 14408 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 14409 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 14410 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 14411 14412 /* Rx2 :: anaRxStatus :: rfifo_unflow [01:01] */ 14413 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 14414 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 14415 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 14416 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 14417 14418 /* Rx2 :: anaRxStatus :: rfifo_ovflow [00:00] */ 14419 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 14420 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 14421 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 14422 #define RX2_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 14423 14424 14425 /* union - case integ_Status [15:00] */ 14426 /* Rx2 :: anaRxStatus :: integ_status [15:00] */ 14427 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 14428 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 14429 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 14430 #define RX2_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 14431 14432 14433 /* union - case vco_Status [15:00] */ 14434 /* Rx2 :: anaRxStatus :: vco_status [15:00] */ 14435 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 14436 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 14437 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 14438 #define RX2_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 14439 14440 14441 /* union - case prbs_Status [15:00] */ 14442 /* Rx2 :: anaRxStatus :: prbs_lock [15:15] */ 14443 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 14444 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 14445 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 14446 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 14447 14448 /* Rx2 :: anaRxStatus :: prbs_stky [14:14] */ 14449 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 14450 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 14451 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 14452 #define RX2_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 14453 14454 /* Rx2 :: anaRxStatus :: ptbs_errors [13:00] */ 14455 #define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 14456 #define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 14457 #define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 14458 #define RX2_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 14459 14460 14461 14462 /**************************************************************************** 14463 * Rx2 :: anaRxControl 14464 */ 14465 /* Rx2 :: anaRxControl :: reserved0 [15:10] */ 14466 #define RX2_ANARXCONTROL_RESERVED0_MASK 0xfc00 14467 #define RX2_ANARXCONTROL_RESERVED0_ALIGN 0 14468 #define RX2_ANARXCONTROL_RESERVED0_BITS 6 14469 #define RX2_ANARXCONTROL_RESERVED0_SHIFT 10 14470 14471 /* Rx2 :: anaRxControl :: override_sigdet_en [09:09] */ 14472 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 14473 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 14474 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 14475 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 14476 14477 /* Rx2 :: anaRxControl :: override_sigdet_val [08:08] */ 14478 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 14479 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 14480 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 14481 #define RX2_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 14482 14483 /* Rx2 :: anaRxControl :: reserved1 [07:03] */ 14484 #define RX2_ANARXCONTROL_RESERVED1_MASK 0x00f8 14485 #define RX2_ANARXCONTROL_RESERVED1_ALIGN 0 14486 #define RX2_ANARXCONTROL_RESERVED1_BITS 5 14487 #define RX2_ANARXCONTROL_RESERVED1_SHIFT 3 14488 14489 /* Rx2 :: anaRxControl :: status_sel [02:00] */ 14490 #define RX2_ANARXCONTROL_STATUS_SEL_MASK 0x0007 14491 #define RX2_ANARXCONTROL_STATUS_SEL_ALIGN 0 14492 #define RX2_ANARXCONTROL_STATUS_SEL_BITS 3 14493 #define RX2_ANARXCONTROL_STATUS_SEL_SHIFT 0 14494 #define RX2_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 14495 #define RX2_ANARXCONTROL_STATUS_SEL_syncStatus 1 14496 #define RX2_ANARXCONTROL_STATUS_SEL_rxTestSel 2 14497 #define RX2_ANARXCONTROL_STATUS_SEL_scaleStatus 3 14498 #define RX2_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 14499 #define RX2_ANARXCONTROL_STATUS_SEL_integStatus 5 14500 #define RX2_ANARXCONTROL_STATUS_SEL_vcoStatus 6 14501 #define RX2_ANARXCONTROL_STATUS_SEL_prbsStatus 7 14502 14503 14504 /**************************************************************************** 14505 * Rx2 :: anaRxTest 14506 */ 14507 /* Rx2 :: anaRxTest :: sigdet_mux_SM [15:12] */ 14508 #define RX2_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 14509 #define RX2_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 14510 #define RX2_ANARXTEST_SIGDET_MUX_SM_BITS 4 14511 #define RX2_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 14512 14513 /* Rx2 :: anaRxTest :: reserved0 [11:09] */ 14514 #define RX2_ANARXTEST_RESERVED0_MASK 0x0e00 14515 #define RX2_ANARXTEST_RESERVED0_ALIGN 0 14516 #define RX2_ANARXTEST_RESERVED0_BITS 3 14517 #define RX2_ANARXTEST_RESERVED0_SHIFT 9 14518 14519 /* Rx2 :: anaRxTest :: tpctrl_SM [08:04] */ 14520 #define RX2_ANARXTEST_TPCTRL_SM_MASK 0x01f0 14521 #define RX2_ANARXTEST_TPCTRL_SM_ALIGN 0 14522 #define RX2_ANARXTEST_TPCTRL_SM_BITS 5 14523 #define RX2_ANARXTEST_TPCTRL_SM_SHIFT 4 14524 14525 /* Rx2 :: anaRxTest :: testMuxSelect_SM [03:00] */ 14526 #define RX2_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 14527 #define RX2_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 14528 #define RX2_ANARXTEST_TESTMUXSELECT_SM_BITS 4 14529 #define RX2_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 14530 14531 14532 /**************************************************************************** 14533 * Rx2 :: anaRxControl1G 14534 */ 14535 /* Rx2 :: anaRxControl1G :: fpat_md [15:15] */ 14536 #define RX2_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 14537 #define RX2_ANARXCONTROL1G_FPAT_MD_ALIGN 0 14538 #define RX2_ANARXCONTROL1G_FPAT_MD_BITS 1 14539 #define RX2_ANARXCONTROL1G_FPAT_MD_SHIFT 15 14540 14541 /* Rx2 :: anaRxControl1G :: pkt_count_en [14:14] */ 14542 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 14543 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 14544 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 14545 #define RX2_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 14546 14547 /* Rx2 :: anaRxControl1G :: staMuxRegDis [13:13] */ 14548 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 14549 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 14550 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 14551 #define RX2_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 14552 14553 /* Rx2 :: anaRxControl1G :: prbs_clr_dis [12:12] */ 14554 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 14555 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 14556 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 14557 #define RX2_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 14558 14559 /* Rx2 :: anaRxControl1G :: rxd_dec_sel [11:11] */ 14560 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 14561 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 14562 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 14563 #define RX2_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 14564 14565 /* Rx2 :: anaRxControl1G :: cgbad_tst [10:10] */ 14566 #define RX2_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 14567 #define RX2_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 14568 #define RX2_ANARXCONTROL1G_CGBAD_TST_BITS 1 14569 #define RX2_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 14570 14571 /* Rx2 :: anaRxControl1G :: Emon_en [09:09] */ 14572 #define RX2_ANARXCONTROL1G_EMON_EN_MASK 0x0200 14573 #define RX2_ANARXCONTROL1G_EMON_EN_ALIGN 0 14574 #define RX2_ANARXCONTROL1G_EMON_EN_BITS 1 14575 #define RX2_ANARXCONTROL1G_EMON_EN_SHIFT 9 14576 14577 /* Rx2 :: anaRxControl1G :: prbs_en [08:08] */ 14578 #define RX2_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 14579 #define RX2_ANARXCONTROL1G_PRBS_EN_ALIGN 0 14580 #define RX2_ANARXCONTROL1G_PRBS_EN_BITS 1 14581 #define RX2_ANARXCONTROL1G_PRBS_EN_SHIFT 8 14582 14583 /* Rx2 :: anaRxControl1G :: cgbad_en [07:07] */ 14584 #define RX2_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 14585 #define RX2_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 14586 #define RX2_ANARXCONTROL1G_CGBAD_EN_BITS 1 14587 #define RX2_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 14588 14589 /* Rx2 :: anaRxControl1G :: cstretch [06:06] */ 14590 #define RX2_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 14591 #define RX2_ANARXCONTROL1G_CSTRETCH_ALIGN 0 14592 #define RX2_ANARXCONTROL1G_CSTRETCH_BITS 1 14593 #define RX2_ANARXCONTROL1G_CSTRETCH_SHIFT 6 14594 14595 /* Rx2 :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 14596 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 14597 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 14598 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 14599 #define RX2_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 14600 14601 /* Rx2 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 14602 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 14603 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 14604 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 14605 #define RX2_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 14606 14607 /* Rx2 :: anaRxControl1G :: reserved0 [03:02] */ 14608 #define RX2_ANARXCONTROL1G_RESERVED0_MASK 0x000c 14609 #define RX2_ANARXCONTROL1G_RESERVED0_ALIGN 0 14610 #define RX2_ANARXCONTROL1G_RESERVED0_BITS 2 14611 #define RX2_ANARXCONTROL1G_RESERVED0_SHIFT 2 14612 14613 /* Rx2 :: anaRxControl1G :: freq_sel_force [01:01] */ 14614 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 14615 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 14616 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 14617 #define RX2_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 14618 14619 /* Rx2 :: anaRxControl1G :: freq_sel [00:00] */ 14620 #define RX2_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 14621 #define RX2_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 14622 #define RX2_ANARXCONTROL1G_FREQ_SEL_BITS 1 14623 #define RX2_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 14624 14625 14626 /**************************************************************************** 14627 * Rx2 :: anaRxControlPci 14628 */ 14629 /* Rx2 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 14630 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 14631 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 14632 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 14633 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 14634 14635 /* Rx2 :: anaRxControlPci :: comma_mask_force_r [14:14] */ 14636 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 14637 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 14638 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 14639 #define RX2_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 14640 14641 /* Rx2 :: anaRxControlPci :: comma_mask_r [13:13] */ 14642 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 14643 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 14644 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 14645 #define RX2_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 14646 14647 /* Rx2 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 14648 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 14649 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 14650 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 14651 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 14652 14653 /* Rx2 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 14654 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 14655 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 14656 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 14657 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 14658 14659 /* Rx2 :: anaRxControlPci :: sync_status_force_r [10:10] */ 14660 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 14661 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 14662 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 14663 #define RX2_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 14664 14665 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 14666 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 14667 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 14668 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 14669 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 14670 14671 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 14672 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 14673 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 14674 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 14675 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 14676 14677 /* Rx2 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 14678 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 14679 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 14680 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 14681 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 14682 14683 /* Rx2 :: anaRxControlPci :: comma_adj_en_r [06:06] */ 14684 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 14685 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 14686 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 14687 #define RX2_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 14688 14689 /* Rx2 :: anaRxControlPci :: link_en_force_SM [05:05] */ 14690 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 14691 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 14692 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 14693 #define RX2_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 14694 14695 /* Rx2 :: anaRxControlPci :: link_en_r [04:04] */ 14696 #define RX2_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 14697 #define RX2_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 14698 #define RX2_ANARXCONTROLPCI_LINK_EN_R_BITS 1 14699 #define RX2_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 14700 14701 /* Rx2 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 14702 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 14703 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 14704 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 14705 #define RX2_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 14706 14707 /* Rx2 :: anaRxControlPci :: rx_polarity_r [02:02] */ 14708 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 14709 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 14710 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 14711 #define RX2_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 14712 14713 /* Rx2 :: anaRxControlPci :: integ_mode_SM [01:00] */ 14714 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 14715 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 14716 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 14717 #define RX2_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 14718 14719 14720 /**************************************************************************** 14721 * Rx2 :: anaRxAstatus 14722 */ 14723 /* Rx2 :: anaRxAstatus :: sigdet [15:15] */ 14724 #define RX2_ANARXASTATUS_SIGDET_MASK 0x8000 14725 #define RX2_ANARXASTATUS_SIGDET_ALIGN 0 14726 #define RX2_ANARXASTATUS_SIGDET_BITS 1 14727 #define RX2_ANARXASTATUS_SIGDET_SHIFT 15 14728 14729 /* Rx2 :: anaRxAstatus :: rx_pf [14:12] */ 14730 #define RX2_ANARXASTATUS_RX_PF_MASK 0x7000 14731 #define RX2_ANARXASTATUS_RX_PF_ALIGN 0 14732 #define RX2_ANARXASTATUS_RX_PF_BITS 3 14733 #define RX2_ANARXASTATUS_RX_PF_SHIFT 12 14734 14735 /* Rx2 :: anaRxAstatus :: dfe [11:06] */ 14736 #define RX2_ANARXASTATUS_DFE_MASK 0x0fc0 14737 #define RX2_ANARXASTATUS_DFE_ALIGN 0 14738 #define RX2_ANARXASTATUS_DFE_BITS 6 14739 #define RX2_ANARXASTATUS_DFE_SHIFT 6 14740 14741 /* Rx2 :: anaRxAstatus :: reserved0 [05:05] */ 14742 #define RX2_ANARXASTATUS_RESERVED0_MASK 0x0020 14743 #define RX2_ANARXASTATUS_RESERVED0_ALIGN 0 14744 #define RX2_ANARXASTATUS_RESERVED0_BITS 1 14745 #define RX2_ANARXASTATUS_RESERVED0_SHIFT 5 14746 14747 /* Rx2 :: anaRxAstatus :: vga [04:00] */ 14748 #define RX2_ANARXASTATUS_VGA_MASK 0x001f 14749 #define RX2_ANARXASTATUS_VGA_ALIGN 0 14750 #define RX2_ANARXASTATUS_VGA_BITS 5 14751 #define RX2_ANARXASTATUS_VGA_SHIFT 0 14752 14753 14754 /**************************************************************************** 14755 * Rx2 :: anaRxAControl1 14756 */ 14757 /* Rx2 :: anaRxAControl1 :: imode_vcm [15:15] */ 14758 #define RX2_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 14759 #define RX2_ANARXACONTROL1_IMODE_VCM_ALIGN 0 14760 #define RX2_ANARXACONTROL1_IMODE_VCM_BITS 1 14761 #define RX2_ANARXACONTROL1_IMODE_VCM_SHIFT 15 14762 14763 /* Rx2 :: anaRxAControl1 :: imin_vcm [14:14] */ 14764 #define RX2_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 14765 #define RX2_ANARXACONTROL1_IMIN_VCM_ALIGN 0 14766 #define RX2_ANARXACONTROL1_IMIN_VCM_BITS 1 14767 #define RX2_ANARXACONTROL1_IMIN_VCM_SHIFT 14 14768 14769 /* Rx2 :: anaRxAControl1 :: imax_sigdet [13:13] */ 14770 #define RX2_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 14771 #define RX2_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 14772 #define RX2_ANARXACONTROL1_IMAX_SIGDET_BITS 1 14773 #define RX2_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 14774 14775 /* Rx2 :: anaRxAControl1 :: imode_sigdet [12:12] */ 14776 #define RX2_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 14777 #define RX2_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 14778 #define RX2_ANARXACONTROL1_IMODE_SIGDET_BITS 1 14779 #define RX2_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 14780 14781 /* Rx2 :: anaRxAControl1 :: imin_sigdet [11:11] */ 14782 #define RX2_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 14783 #define RX2_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 14784 #define RX2_ANARXACONTROL1_IMIN_SIGDET_BITS 1 14785 #define RX2_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 14786 14787 /* Rx2 :: anaRxAControl1 :: refh_rx [10:10] */ 14788 #define RX2_ANARXACONTROL1_REFH_RX_MASK 0x0400 14789 #define RX2_ANARXACONTROL1_REFH_RX_ALIGN 0 14790 #define RX2_ANARXACONTROL1_REFH_RX_BITS 1 14791 #define RX2_ANARXACONTROL1_REFH_RX_SHIFT 10 14792 14793 /* Rx2 :: anaRxAControl1 :: refl_rx [09:09] */ 14794 #define RX2_ANARXACONTROL1_REFL_RX_MASK 0x0200 14795 #define RX2_ANARXACONTROL1_REFL_RX_ALIGN 0 14796 #define RX2_ANARXACONTROL1_REFL_RX_BITS 1 14797 #define RX2_ANARXACONTROL1_REFL_RX_SHIFT 9 14798 14799 /* Rx2 :: anaRxAControl1 :: tport_en [08:08] */ 14800 #define RX2_ANARXACONTROL1_TPORT_EN_MASK 0x0100 14801 #define RX2_ANARXACONTROL1_TPORT_EN_ALIGN 0 14802 #define RX2_ANARXACONTROL1_TPORT_EN_BITS 1 14803 #define RX2_ANARXACONTROL1_TPORT_EN_SHIFT 8 14804 14805 /* Rx2 :: anaRxAControl1 :: vddrb_bg [07:07] */ 14806 #define RX2_ANARXACONTROL1_VDDRB_BG_MASK 0x0080 14807 #define RX2_ANARXACONTROL1_VDDRB_BG_ALIGN 0 14808 #define RX2_ANARXACONTROL1_VDDRB_BG_BITS 1 14809 #define RX2_ANARXACONTROL1_VDDRB_BG_SHIFT 7 14810 14811 /* Rx2 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 14812 #define RX2_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 14813 #define RX2_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 14814 #define RX2_ANARXACONTROL1_SIG_PWRDN_BITS 1 14815 #define RX2_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 14816 14817 /* Rx2 :: anaRxAControl1 :: offset_ctrl [05:03] */ 14818 #define RX2_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 14819 #define RX2_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 14820 #define RX2_ANARXACONTROL1_OFFSET_CTRL_BITS 3 14821 #define RX2_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 14822 14823 /* Rx2 :: anaRxAControl1 :: offset_sel [02:02] */ 14824 #define RX2_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 14825 #define RX2_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 14826 #define RX2_ANARXACONTROL1_OFFSET_SEL_BITS 1 14827 #define RX2_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 14828 14829 /* Rx2 :: anaRxAControl1 :: reserved0 [01:00] */ 14830 #define RX2_ANARXACONTROL1_RESERVED0_MASK 0x0003 14831 #define RX2_ANARXACONTROL1_RESERVED0_ALIGN 0 14832 #define RX2_ANARXACONTROL1_RESERVED0_BITS 2 14833 #define RX2_ANARXACONTROL1_RESERVED0_SHIFT 0 14834 14835 14836 /**************************************************************************** 14837 * Rx2 :: anaRxAControl2 14838 */ 14839 /* Rx2 :: anaRxAControl2 :: imax_clkbuf [15:15] */ 14840 #define RX2_ANARXACONTROL2_IMAX_CLKBUF_MASK 0x8000 14841 #define RX2_ANARXACONTROL2_IMAX_CLKBUF_ALIGN 0 14842 #define RX2_ANARXACONTROL2_IMAX_CLKBUF_BITS 1 14843 #define RX2_ANARXACONTROL2_IMAX_CLKBUF_SHIFT 15 14844 14845 /* Rx2 :: anaRxAControl2 :: imode_clkbuf [14:14] */ 14846 #define RX2_ANARXACONTROL2_IMODE_CLKBUF_MASK 0x4000 14847 #define RX2_ANARXACONTROL2_IMODE_CLKBUF_ALIGN 0 14848 #define RX2_ANARXACONTROL2_IMODE_CLKBUF_BITS 1 14849 #define RX2_ANARXACONTROL2_IMODE_CLKBUF_SHIFT 14 14850 14851 /* Rx2 :: anaRxAControl2 :: imin_clkbuf [13:13] */ 14852 #define RX2_ANARXACONTROL2_IMIN_CLKBUF_MASK 0x2000 14853 #define RX2_ANARXACONTROL2_IMIN_CLKBUF_ALIGN 0 14854 #define RX2_ANARXACONTROL2_IMIN_CLKBUF_BITS 1 14855 #define RX2_ANARXACONTROL2_IMIN_CLKBUF_SHIFT 13 14856 14857 /* Rx2 :: anaRxAControl2 :: imax_eqfl [12:12] */ 14858 #define RX2_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 14859 #define RX2_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 14860 #define RX2_ANARXACONTROL2_IMAX_EQFL_BITS 1 14861 #define RX2_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 14862 14863 /* Rx2 :: anaRxAControl2 :: imode_eqfl [11:11] */ 14864 #define RX2_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 14865 #define RX2_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 14866 #define RX2_ANARXACONTROL2_IMODE_EQFL_BITS 1 14867 #define RX2_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 14868 14869 /* Rx2 :: anaRxAControl2 :: imin_eqfl [10:10] */ 14870 #define RX2_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 14871 #define RX2_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 14872 #define RX2_ANARXACONTROL2_IMIN_EQFL_BITS 1 14873 #define RX2_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 14874 14875 /* Rx2 :: anaRxAControl2 :: imax_dfesum [09:09] */ 14876 #define RX2_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 14877 #define RX2_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 14878 #define RX2_ANARXACONTROL2_IMAX_DFESUM_BITS 1 14879 #define RX2_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 14880 14881 /* Rx2 :: anaRxAControl2 :: imode_dfesum [08:08] */ 14882 #define RX2_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 14883 #define RX2_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 14884 #define RX2_ANARXACONTROL2_IMODE_DFESUM_BITS 1 14885 #define RX2_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 14886 14887 /* Rx2 :: anaRxAControl2 :: imin_dfesum [07:07] */ 14888 #define RX2_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 14889 #define RX2_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 14890 #define RX2_ANARXACONTROL2_IMIN_DFESUM_BITS 1 14891 #define RX2_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 14892 14893 /* Rx2 :: anaRxAControl2 :: imax_vga [06:06] */ 14894 #define RX2_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 14895 #define RX2_ANARXACONTROL2_IMAX_VGA_ALIGN 0 14896 #define RX2_ANARXACONTROL2_IMAX_VGA_BITS 1 14897 #define RX2_ANARXACONTROL2_IMAX_VGA_SHIFT 6 14898 14899 /* Rx2 :: anaRxAControl2 :: imode_vga [05:05] */ 14900 #define RX2_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 14901 #define RX2_ANARXACONTROL2_IMODE_VGA_ALIGN 0 14902 #define RX2_ANARXACONTROL2_IMODE_VGA_BITS 1 14903 #define RX2_ANARXACONTROL2_IMODE_VGA_SHIFT 5 14904 14905 /* Rx2 :: anaRxAControl2 :: imin_vga [04:04] */ 14906 #define RX2_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 14907 #define RX2_ANARXACONTROL2_IMIN_VGA_ALIGN 0 14908 #define RX2_ANARXACONTROL2_IMIN_VGA_BITS 1 14909 #define RX2_ANARXACONTROL2_IMIN_VGA_SHIFT 4 14910 14911 /* Rx2 :: anaRxAControl2 :: imax_interp [03:03] */ 14912 #define RX2_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 14913 #define RX2_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 14914 #define RX2_ANARXACONTROL2_IMAX_INTERP_BITS 1 14915 #define RX2_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 14916 14917 /* Rx2 :: anaRxAControl2 :: imode_interp [02:02] */ 14918 #define RX2_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 14919 #define RX2_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 14920 #define RX2_ANARXACONTROL2_IMODE_INTERP_BITS 1 14921 #define RX2_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 14922 14923 /* Rx2 :: anaRxAControl2 :: imin_interp [01:01] */ 14924 #define RX2_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 14925 #define RX2_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 14926 #define RX2_ANARXACONTROL2_IMIN_INTERP_BITS 1 14927 #define RX2_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 14928 14929 /* Rx2 :: anaRxAControl2 :: imax_vcm [00:00] */ 14930 #define RX2_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 14931 #define RX2_ANARXACONTROL2_IMAX_VCM_ALIGN 0 14932 #define RX2_ANARXACONTROL2_IMAX_VCM_BITS 1 14933 #define RX2_ANARXACONTROL2_IMAX_VCM_SHIFT 0 14934 14935 14936 /**************************************************************************** 14937 * Rx2 :: anaRxAControl3 14938 */ 14939 /* Rx2 :: anaRxAControl3 :: en_clk16 [15:15] */ 14940 #define RX2_ANARXACONTROL3_EN_CLK16_MASK 0x8000 14941 #define RX2_ANARXACONTROL3_EN_CLK16_ALIGN 0 14942 #define RX2_ANARXACONTROL3_EN_CLK16_BITS 1 14943 #define RX2_ANARXACONTROL3_EN_CLK16_SHIFT 15 14944 14945 /* Rx2 :: anaRxAControl3 :: pd_ch_p1 [14:14] */ 14946 #define RX2_ANARXACONTROL3_PD_CH_P1_MASK 0x4000 14947 #define RX2_ANARXACONTROL3_PD_CH_P1_ALIGN 0 14948 #define RX2_ANARXACONTROL3_PD_CH_P1_BITS 1 14949 #define RX2_ANARXACONTROL3_PD_CH_P1_SHIFT 14 14950 14951 /* Rx2 :: anaRxAControl3 :: en_vcctrl [13:13] */ 14952 #define RX2_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 14953 #define RX2_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 14954 #define RX2_ANARXACONTROL3_EN_VCCTRL_BITS 1 14955 #define RX2_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 14956 14957 /* Rx2 :: anaRxAControl3 :: en_dfeclk [12:12] */ 14958 #define RX2_ANARXACONTROL3_EN_DFECLK_MASK 0x1000 14959 #define RX2_ANARXACONTROL3_EN_DFECLK_ALIGN 0 14960 #define RX2_ANARXACONTROL3_EN_DFECLK_BITS 1 14961 #define RX2_ANARXACONTROL3_EN_DFECLK_SHIFT 12 14962 14963 /* Rx2 :: anaRxAControl3 :: en_hgain [11:11] */ 14964 #define RX2_ANARXACONTROL3_EN_HGAIN_MASK 0x0800 14965 #define RX2_ANARXACONTROL3_EN_HGAIN_ALIGN 0 14966 #define RX2_ANARXACONTROL3_EN_HGAIN_BITS 1 14967 #define RX2_ANARXACONTROL3_EN_HGAIN_SHIFT 11 14968 14969 /* Rx2 :: anaRxAControl3 :: en_dfeckpwr [10:10] */ 14970 #define RX2_ANARXACONTROL3_EN_DFECKPWR_MASK 0x0400 14971 #define RX2_ANARXACONTROL3_EN_DFECKPWR_ALIGN 0 14972 #define RX2_ANARXACONTROL3_EN_DFECKPWR_BITS 1 14973 #define RX2_ANARXACONTROL3_EN_DFECKPWR_SHIFT 10 14974 14975 /* Rx2 :: anaRxAControl3 :: offset_pd [09:09] */ 14976 #define RX2_ANARXACONTROL3_OFFSET_PD_MASK 0x0200 14977 #define RX2_ANARXACONTROL3_OFFSET_PD_ALIGN 0 14978 #define RX2_ANARXACONTROL3_OFFSET_PD_BITS 1 14979 #define RX2_ANARXACONTROL3_OFFSET_PD_SHIFT 9 14980 14981 /* Rx2 :: anaRxAControl3 :: imax_dfetap [08:08] */ 14982 #define RX2_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 14983 #define RX2_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 14984 #define RX2_ANARXACONTROL3_IMAX_DFETAP_BITS 1 14985 #define RX2_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 14986 14987 /* Rx2 :: anaRxAControl3 :: imode_dfetap [07:07] */ 14988 #define RX2_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 14989 #define RX2_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 14990 #define RX2_ANARXACONTROL3_IMODE_DFETAP_BITS 1 14991 #define RX2_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 14992 14993 /* Rx2 :: anaRxAControl3 :: imin_dfetap [06:06] */ 14994 #define RX2_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 14995 #define RX2_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 14996 #define RX2_ANARXACONTROL3_IMIN_DFETAP_BITS 1 14997 #define RX2_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 14998 14999 /* Rx2 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 15000 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 15001 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 15002 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 15003 #define RX2_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 15004 15005 /* Rx2 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 15006 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 15007 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 15008 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 15009 #define RX2_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 15010 15011 /* Rx2 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 15012 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 15013 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 15014 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 15015 #define RX2_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 15016 15017 /* Rx2 :: anaRxAControl3 :: imax_dfevref [02:02] */ 15018 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 15019 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 15020 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 15021 #define RX2_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 15022 15023 /* Rx2 :: anaRxAControl3 :: imode_dfevref [01:01] */ 15024 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 15025 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 15026 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 15027 #define RX2_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 15028 15029 /* Rx2 :: anaRxAControl3 :: imin_dfevref [00:00] */ 15030 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 15031 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 15032 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 15033 #define RX2_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 15034 15035 15036 /**************************************************************************** 15037 * Hypercore_USER_Rx3 15038 */ 15039 /**************************************************************************** 15040 * Rx3 :: anaRxStatus 15041 */ 15042 /* union - case sigdet_Status [15:00] */ 15043 /* Rx3 :: anaRxStatus :: cx4_sigdet [15:15] */ 15044 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 15045 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 15046 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 15047 #define RX3_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 15048 15049 /* Rx3 :: anaRxStatus :: reserved0 [14:13] */ 15050 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 15051 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 15052 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 15053 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 15054 15055 /* Rx3 :: anaRxStatus :: rxSeqDone [12:12] */ 15056 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 15057 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 15058 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 15059 #define RX3_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 15060 15061 /* Rx3 :: anaRxStatus :: rx_sigdet_ll [11:11] */ 15062 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 15063 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 15064 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 15065 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 15066 15067 /* Rx3 :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 15068 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 15069 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 15070 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 15071 #define RX3_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 15072 15073 /* Rx3 :: anaRxStatus :: rx_reset [09:09] */ 15074 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 15075 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 15076 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 15077 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 15078 15079 /* Rx3 :: anaRxStatus :: rx_pwrdn [08:08] */ 15080 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 15081 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 15082 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 15083 #define RX3_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 15084 15085 /* Rx3 :: anaRxStatus :: reserved1 [07:00] */ 15086 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 15087 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 15088 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 15089 #define RX3_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 15090 15091 15092 /* union - case sync_Status [15:00] */ 15093 /* Rx3 :: anaRxStatus :: reserved0 [15:11] */ 15094 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 15095 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 15096 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 15097 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 15098 15099 /* Rx3 :: anaRxStatus :: test_acq_en [10:10] */ 15100 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 15101 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 15102 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 15103 #define RX3_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 15104 15105 /* Rx3 :: anaRxStatus :: reserved1 [09:09] */ 15106 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 15107 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 15108 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 15109 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 15110 15111 /* Rx3 :: anaRxStatus :: rxSeqStart [08:08] */ 15112 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 15113 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 15114 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 15115 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 15116 15117 /* Rx3 :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 15118 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 15119 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 15120 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 15121 #define RX3_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 15122 15123 /* Rx3 :: anaRxStatus :: sync_status [06:06] */ 15124 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 15125 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 15126 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 15127 #define RX3_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 15128 15129 /* Rx3 :: anaRxStatus :: rx_sigdet [05:05] */ 15130 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 15131 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 15132 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 15133 #define RX3_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 15134 15135 /* Rx3 :: anaRxStatus :: reserved2 [04:03] */ 15136 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 15137 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 15138 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 15139 #define RX3_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 15140 15141 /* Rx3 :: anaRxStatus :: saturate_status [02:02] */ 15142 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 15143 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 15144 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 15145 #define RX3_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 15146 15147 /* Rx3 :: anaRxStatus :: cx4_sigdet [01:01] */ 15148 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 15149 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 15150 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 15151 #define RX3_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 15152 15153 /* Rx3 :: anaRxStatus :: rxSeqDone [00:00] */ 15154 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 15155 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 15156 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 15157 #define RX3_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 15158 15159 15160 /* union - case rxTestSel_0 [15:00] */ 15161 /* Rx3 :: anaRxStatus :: reserved0 [15:10] */ 15162 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 15163 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 15164 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 15165 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 15166 15167 /* Rx3 :: anaRxStatus :: indck_mode_en [09:09] */ 15168 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 15169 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 15170 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 15171 #define RX3_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 15172 15173 /* Rx3 :: anaRxStatus :: pci_mode_en [08:08] */ 15174 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 15175 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 15176 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 15177 #define RX3_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 15178 15179 /* Rx3 :: anaRxStatus :: rx_polarity [07:07] */ 15180 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 15181 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 15182 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 15183 #define RX3_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 15184 15185 /* Rx3 :: anaRxStatus :: rxpol_flip [06:06] */ 15186 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 15187 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 15188 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 15189 #define RX3_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 15190 15191 /* Rx3 :: anaRxStatus :: comma_mask [05:05] */ 15192 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 15193 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 15194 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 15195 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 15196 15197 /* Rx3 :: anaRxStatus :: link_en_r [04:04] */ 15198 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 15199 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 15200 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 15201 #define RX3_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 15202 15203 /* Rx3 :: anaRxStatus :: comma_adj_en [03:03] */ 15204 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 15205 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 15206 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 15207 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 15208 15209 /* Rx3 :: anaRxStatus :: comma_adj_en_ext [02:02] */ 15210 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 15211 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 15212 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 15213 #define RX3_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 15214 15215 /* Rx3 :: anaRxStatus :: reserved1 [01:00] */ 15216 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 15217 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 15218 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 15219 #define RX3_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 15220 15221 15222 /* union - case rxTestSel_1 [15:00] */ 15223 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 15224 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 15225 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 15226 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 15227 #define RX3_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 15228 15229 /* Rx3 :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 15230 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 15231 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 15232 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 15233 #define RX3_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 15234 15235 /* Rx3 :: anaRxStatus :: freq_sel_PC [03:03] */ 15236 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 15237 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 15238 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 15239 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 15240 15241 /* Rx3 :: anaRxStatus :: freq_sel_SM [02:02] */ 15242 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 15243 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 15244 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 15245 #define RX3_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 15246 15247 /* Rx3 :: anaRxStatus :: integ_mode_SM [01:00] */ 15248 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 15249 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 15250 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 15251 #define RX3_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 15252 15253 15254 /* union - case scale_Status [15:00] */ 15255 /* Rx3 :: anaRxStatus :: prop_scale [15:12] */ 15256 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 15257 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 15258 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 15259 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 15260 15261 /* Rx3 :: anaRxStatus :: integ_scale [11:08] */ 15262 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 15263 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 15264 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 15265 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 15266 15267 /* Rx3 :: anaRxStatus :: prop_scale_acq [07:04] */ 15268 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 15269 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 15270 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 15271 #define RX3_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 15272 15273 /* Rx3 :: anaRxStatus :: integ_scale_acq [03:00] */ 15274 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 15275 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 15276 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 15277 #define RX3_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 15278 15279 15280 /* union - case adc_CdrStatus1 [15:00] */ 15281 /* Rx3 :: anaRxStatus :: reserved0 [15:07] */ 15282 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 15283 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 15284 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 15285 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 15286 15287 /* Rx3 :: anaRxStatus :: rxMuxCkSel [06:06] */ 15288 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 15289 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 15290 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 15291 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 15292 15293 /* Rx3 :: anaRxStatus :: glpbk_combo [05:05] */ 15294 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 15295 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 15296 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 15297 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 15298 15299 /* Rx3 :: anaRxStatus :: clockSwitchSel [04:04] */ 15300 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 15301 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 15302 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 15303 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 15304 15305 /* Rx3 :: anaRxStatus :: rxck_tst [03:03] */ 15306 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 15307 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 15308 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 15309 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 15310 15311 /* Rx3 :: anaRxStatus :: rxck_i [02:02] */ 15312 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 15313 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 15314 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 15315 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 15316 15317 /* Rx3 :: anaRxStatus :: refclk [01:01] */ 15318 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 15319 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 15320 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 15321 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 15322 15323 /* Rx3 :: anaRxStatus :: pll_bypass [00:00] */ 15324 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 15325 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 15326 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 15327 #define RX3_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 15328 15329 15330 /* union - case adc_CdrStatus2 [15:00] */ 15331 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */ 15332 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 15333 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 15334 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 15335 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 15336 15337 /* Rx3 :: anaRxStatus :: rxMuxCkSel [05:05] */ 15338 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 15339 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 15340 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 15341 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 15342 15343 /* Rx3 :: anaRxStatus :: rxSeqStart [04:04] */ 15344 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 15345 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 15346 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 15347 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 15348 15349 /* Rx3 :: anaRxStatus :: reserved1 [03:01] */ 15350 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 15351 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 15352 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 15353 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 15354 15355 /* Rx3 :: anaRxStatus :: rxSeqDone [00:00] */ 15356 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 15357 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 15358 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 15359 #define RX3_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 15360 15361 15362 /* union - case adc_CdrStatus3 [15:00] */ 15363 /* Rx3 :: anaRxStatus :: reserved0 [15:04] */ 15364 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 15365 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 15366 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 15367 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 15368 15369 /* Rx3 :: anaRxStatus :: rxSeqStart [03:03] */ 15370 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 15371 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 15372 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 15373 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 15374 15375 /* Rx3 :: anaRxStatus :: reserved1 [02:01] */ 15376 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 15377 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 15378 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 15379 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 15380 15381 /* Rx3 :: anaRxStatus :: allow_increment_PC [00:00] */ 15382 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 15383 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 15384 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 15385 #define RX3_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 15386 15387 15388 /* union - case adc_CdrStatus4 [15:00] */ 15389 /* Rx3 :: anaRxStatus :: reserved0 [15:08] */ 15390 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 15391 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 15392 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 15393 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 15394 15395 /* Rx3 :: anaRxStatus :: rx_pwrdn [07:07] */ 15396 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 15397 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 15398 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 15399 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 15400 15401 /* Rx3 :: anaRxStatus :: freq_sel [06:06] */ 15402 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 15403 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 15404 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 15405 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 15406 15407 /* Rx3 :: anaRxStatus :: pll_lock_rstb [05:05] */ 15408 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 15409 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 15410 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 15411 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 15412 15413 /* Rx3 :: anaRxStatus :: pwrdn [04:04] */ 15414 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 15415 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 15416 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 15417 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 15418 15419 /* Rx3 :: anaRxStatus :: reserved1 [03:00] */ 15420 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 15421 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 15422 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 15423 #define RX3_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 15424 15425 15426 /* union - case adc_CdrStatus5 [15:00] */ 15427 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */ 15428 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 15429 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 15430 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 15431 #define RX3_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 15432 15433 15434 /* union - case adc_CdrStatus6 [15:00] */ 15435 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 15436 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 15437 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 15438 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 15439 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 15440 15441 /* Rx3 :: anaRxStatus :: rx_reset [04:04] */ 15442 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 15443 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 15444 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 15445 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 15446 15447 /* Rx3 :: anaRxStatus :: rx_pwrdn [03:03] */ 15448 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 15449 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 15450 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 15451 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 15452 15453 /* Rx3 :: anaRxStatus :: reset_anlg [02:02] */ 15454 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 15455 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 15456 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 15457 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 15458 15459 /* Rx3 :: anaRxStatus :: pwrdn_rx [01:01] */ 15460 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 15461 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 15462 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 15463 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 15464 15465 /* Rx3 :: anaRxStatus :: pwrdn_pll [00:00] */ 15466 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 15467 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 15468 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 15469 #define RX3_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 15470 15471 15472 /* union - case adc_CdrStatus7e [15:00] */ 15473 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 15474 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 15475 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 15476 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 15477 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 15478 15479 /* Rx3 :: anaRxStatus :: rxck0_even [04:04] */ 15480 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 15481 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 15482 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 15483 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 15484 15485 /* Rx3 :: anaRxStatus :: rxck1_even [03:03] */ 15486 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 15487 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 15488 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 15489 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 15490 15491 /* Rx3 :: anaRxStatus :: comdet_even [02:02] */ 15492 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 15493 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 15494 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 15495 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 15496 15497 /* Rx3 :: anaRxStatus :: en_cdet_even [01:01] */ 15498 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 15499 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 15500 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 15501 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 15502 15503 /* Rx3 :: anaRxStatus :: comma_adj_en_even [00:00] */ 15504 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 15505 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 15506 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 15507 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 15508 15509 15510 /* union - case adc_CdrStatus7o [15:00] */ 15511 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 15512 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 15513 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 15514 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 15515 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 15516 15517 /* Rx3 :: anaRxStatus :: rxck0_odd [04:04] */ 15518 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 15519 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 15520 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 15521 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 15522 15523 /* Rx3 :: anaRxStatus :: rxck1_odd [03:03] */ 15524 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 15525 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 15526 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 15527 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 15528 15529 /* Rx3 :: anaRxStatus :: comdet_odd [02:02] */ 15530 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 15531 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 15532 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 15533 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 15534 15535 /* Rx3 :: anaRxStatus :: en_cdet_odd [01:01] */ 15536 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 15537 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 15538 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 15539 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 15540 15541 /* Rx3 :: anaRxStatus :: comma_adj_en_odd [00:00] */ 15542 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 15543 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 15544 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 15545 #define RX3_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 15546 15547 15548 /* union - case adc_CdrStatus8 [15:00] */ 15549 /* Rx3 :: anaRxStatus :: reserved0 [15:01] */ 15550 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 15551 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 15552 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 15553 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 15554 15555 /* Rx3 :: anaRxStatus :: sigdet [00:00] */ 15556 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 15557 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 15558 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 15559 #define RX3_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 15560 15561 15562 /* union - case adc_CdrStatus9 [15:00] */ 15563 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */ 15564 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 15565 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 15566 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 15567 #define RX3_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 15568 15569 15570 /* union - case adc_CdrStatus10 [15:00] */ 15571 /* Rx3 :: anaRxStatus :: reserved0 [15:07] */ 15572 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 15573 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 15574 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 15575 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 15576 15577 /* Rx3 :: anaRxStatus :: prbs_en [06:06] */ 15578 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 15579 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 15580 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 15581 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 15582 15583 /* Rx3 :: anaRxStatus :: rstb_tst [05:05] */ 15584 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 15585 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 15586 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 15587 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 15588 15589 /* Rx3 :: anaRxStatus :: reserved1 [04:04] */ 15590 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 15591 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 15592 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 15593 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 15594 15595 /* Rx3 :: anaRxStatus :: prbs_state [03:00] */ 15596 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 15597 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 15598 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 15599 #define RX3_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 15600 15601 15602 /* union - case adc_CdrStatus11 [15:00] */ 15603 /* Rx3 :: anaRxStatus :: reserved0 [15:00] */ 15604 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 15605 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 15606 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 15607 #define RX3_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 15608 15609 15610 /* union - case adc_CdrStatus12_1 [15:00] */ 15611 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */ 15612 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 15613 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 15614 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 15615 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 15616 15617 /* Rx3 :: anaRxStatus :: enable4 [05:05] */ 15618 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 15619 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 15620 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 15621 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 15622 15623 /* Rx3 :: anaRxStatus :: radr_test [04:00] */ 15624 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 15625 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 15626 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 15627 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 15628 15629 15630 /* union - case adc_CdrStatus12_2 [15:00] */ 15631 /* Rx3 :: anaRxStatus :: reserved0 [15:05] */ 15632 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 15633 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 15634 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 15635 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 15636 15637 /* Rx3 :: anaRxStatus :: wadr_test [04:00] */ 15638 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 15639 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 15640 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 15641 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 15642 15643 15644 /* union - case adc_CdrStatus12_3 [15:00] */ 15645 /* Rx3 :: anaRxStatus :: reserved0 [15:06] */ 15646 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 15647 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 15648 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 15649 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 15650 15651 /* Rx3 :: anaRxStatus :: rxck_66B_tmux [05:05] */ 15652 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 15653 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 15654 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 15655 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 15656 15657 /* Rx3 :: anaRxStatus :: rstb_66B [04:04] */ 15658 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 15659 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 15660 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 15661 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 15662 15663 /* Rx3 :: anaRxStatus :: prstb_66B_mux [03:03] */ 15664 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 15665 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 15666 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 15667 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 15668 15669 /* Rx3 :: anaRxStatus :: rxck_i66_tmux [02:02] */ 15670 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 15671 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 15672 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 15673 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 15674 15675 /* Rx3 :: anaRxStatus :: rstb_i66 [01:01] */ 15676 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 15677 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 15678 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 15679 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 15680 15681 /* Rx3 :: anaRxStatus :: prstb_i66_mux [00:00] */ 15682 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 15683 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 15684 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 15685 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 15686 15687 15688 /* union - case adc_CdrStatus12_4 [15:00] */ 15689 /* Rx3 :: anaRxStatus :: reserved0 [15:04] */ 15690 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 15691 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 15692 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 15693 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 15694 15695 /* Rx3 :: anaRxStatus :: rfifo_error_r [03:02] */ 15696 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 15697 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 15698 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 15699 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 15700 15701 /* Rx3 :: anaRxStatus :: rfifo_unflow [01:01] */ 15702 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 15703 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 15704 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 15705 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 15706 15707 /* Rx3 :: anaRxStatus :: rfifo_ovflow [00:00] */ 15708 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 15709 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 15710 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 15711 #define RX3_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 15712 15713 15714 /* union - case integ_Status [15:00] */ 15715 /* Rx3 :: anaRxStatus :: integ_status [15:00] */ 15716 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 15717 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 15718 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 15719 #define RX3_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 15720 15721 15722 /* union - case vco_Status [15:00] */ 15723 /* Rx3 :: anaRxStatus :: vco_status [15:00] */ 15724 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 15725 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 15726 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 15727 #define RX3_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 15728 15729 15730 /* union - case prbs_Status [15:00] */ 15731 /* Rx3 :: anaRxStatus :: prbs_lock [15:15] */ 15732 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 15733 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 15734 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 15735 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 15736 15737 /* Rx3 :: anaRxStatus :: prbs_stky [14:14] */ 15738 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 15739 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 15740 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 15741 #define RX3_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 15742 15743 /* Rx3 :: anaRxStatus :: ptbs_errors [13:00] */ 15744 #define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 15745 #define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 15746 #define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 15747 #define RX3_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 15748 15749 15750 15751 /**************************************************************************** 15752 * Rx3 :: anaRxControl 15753 */ 15754 /* Rx3 :: anaRxControl :: reserved0 [15:10] */ 15755 #define RX3_ANARXCONTROL_RESERVED0_MASK 0xfc00 15756 #define RX3_ANARXCONTROL_RESERVED0_ALIGN 0 15757 #define RX3_ANARXCONTROL_RESERVED0_BITS 6 15758 #define RX3_ANARXCONTROL_RESERVED0_SHIFT 10 15759 15760 /* Rx3 :: anaRxControl :: override_sigdet_en [09:09] */ 15761 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 15762 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 15763 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 15764 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 15765 15766 /* Rx3 :: anaRxControl :: override_sigdet_val [08:08] */ 15767 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 15768 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 15769 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 15770 #define RX3_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 15771 15772 /* Rx3 :: anaRxControl :: reserved1 [07:03] */ 15773 #define RX3_ANARXCONTROL_RESERVED1_MASK 0x00f8 15774 #define RX3_ANARXCONTROL_RESERVED1_ALIGN 0 15775 #define RX3_ANARXCONTROL_RESERVED1_BITS 5 15776 #define RX3_ANARXCONTROL_RESERVED1_SHIFT 3 15777 15778 /* Rx3 :: anaRxControl :: status_sel [02:00] */ 15779 #define RX3_ANARXCONTROL_STATUS_SEL_MASK 0x0007 15780 #define RX3_ANARXCONTROL_STATUS_SEL_ALIGN 0 15781 #define RX3_ANARXCONTROL_STATUS_SEL_BITS 3 15782 #define RX3_ANARXCONTROL_STATUS_SEL_SHIFT 0 15783 #define RX3_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 15784 #define RX3_ANARXCONTROL_STATUS_SEL_syncStatus 1 15785 #define RX3_ANARXCONTROL_STATUS_SEL_rxTestSel 2 15786 #define RX3_ANARXCONTROL_STATUS_SEL_scaleStatus 3 15787 #define RX3_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 15788 #define RX3_ANARXCONTROL_STATUS_SEL_integStatus 5 15789 #define RX3_ANARXCONTROL_STATUS_SEL_vcoStatus 6 15790 #define RX3_ANARXCONTROL_STATUS_SEL_prbsStatus 7 15791 15792 15793 /**************************************************************************** 15794 * Rx3 :: anaRxTest 15795 */ 15796 /* Rx3 :: anaRxTest :: sigdet_mux_SM [15:12] */ 15797 #define RX3_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 15798 #define RX3_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 15799 #define RX3_ANARXTEST_SIGDET_MUX_SM_BITS 4 15800 #define RX3_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 15801 15802 /* Rx3 :: anaRxTest :: reserved0 [11:09] */ 15803 #define RX3_ANARXTEST_RESERVED0_MASK 0x0e00 15804 #define RX3_ANARXTEST_RESERVED0_ALIGN 0 15805 #define RX3_ANARXTEST_RESERVED0_BITS 3 15806 #define RX3_ANARXTEST_RESERVED0_SHIFT 9 15807 15808 /* Rx3 :: anaRxTest :: tpctrl_SM [08:04] */ 15809 #define RX3_ANARXTEST_TPCTRL_SM_MASK 0x01f0 15810 #define RX3_ANARXTEST_TPCTRL_SM_ALIGN 0 15811 #define RX3_ANARXTEST_TPCTRL_SM_BITS 5 15812 #define RX3_ANARXTEST_TPCTRL_SM_SHIFT 4 15813 15814 /* Rx3 :: anaRxTest :: testMuxSelect_SM [03:00] */ 15815 #define RX3_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 15816 #define RX3_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 15817 #define RX3_ANARXTEST_TESTMUXSELECT_SM_BITS 4 15818 #define RX3_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 15819 15820 15821 /**************************************************************************** 15822 * Rx3 :: anaRxControl1G 15823 */ 15824 /* Rx3 :: anaRxControl1G :: fpat_md [15:15] */ 15825 #define RX3_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 15826 #define RX3_ANARXCONTROL1G_FPAT_MD_ALIGN 0 15827 #define RX3_ANARXCONTROL1G_FPAT_MD_BITS 1 15828 #define RX3_ANARXCONTROL1G_FPAT_MD_SHIFT 15 15829 15830 /* Rx3 :: anaRxControl1G :: pkt_count_en [14:14] */ 15831 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 15832 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 15833 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 15834 #define RX3_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 15835 15836 /* Rx3 :: anaRxControl1G :: staMuxRegDis [13:13] */ 15837 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 15838 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 15839 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 15840 #define RX3_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 15841 15842 /* Rx3 :: anaRxControl1G :: prbs_clr_dis [12:12] */ 15843 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 15844 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 15845 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 15846 #define RX3_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 15847 15848 /* Rx3 :: anaRxControl1G :: rxd_dec_sel [11:11] */ 15849 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 15850 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 15851 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 15852 #define RX3_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 15853 15854 /* Rx3 :: anaRxControl1G :: cgbad_tst [10:10] */ 15855 #define RX3_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 15856 #define RX3_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 15857 #define RX3_ANARXCONTROL1G_CGBAD_TST_BITS 1 15858 #define RX3_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 15859 15860 /* Rx3 :: anaRxControl1G :: Emon_en [09:09] */ 15861 #define RX3_ANARXCONTROL1G_EMON_EN_MASK 0x0200 15862 #define RX3_ANARXCONTROL1G_EMON_EN_ALIGN 0 15863 #define RX3_ANARXCONTROL1G_EMON_EN_BITS 1 15864 #define RX3_ANARXCONTROL1G_EMON_EN_SHIFT 9 15865 15866 /* Rx3 :: anaRxControl1G :: prbs_en [08:08] */ 15867 #define RX3_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 15868 #define RX3_ANARXCONTROL1G_PRBS_EN_ALIGN 0 15869 #define RX3_ANARXCONTROL1G_PRBS_EN_BITS 1 15870 #define RX3_ANARXCONTROL1G_PRBS_EN_SHIFT 8 15871 15872 /* Rx3 :: anaRxControl1G :: cgbad_en [07:07] */ 15873 #define RX3_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 15874 #define RX3_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 15875 #define RX3_ANARXCONTROL1G_CGBAD_EN_BITS 1 15876 #define RX3_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 15877 15878 /* Rx3 :: anaRxControl1G :: cstretch [06:06] */ 15879 #define RX3_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 15880 #define RX3_ANARXCONTROL1G_CSTRETCH_ALIGN 0 15881 #define RX3_ANARXCONTROL1G_CSTRETCH_BITS 1 15882 #define RX3_ANARXCONTROL1G_CSTRETCH_SHIFT 6 15883 15884 /* Rx3 :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 15885 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 15886 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 15887 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 15888 #define RX3_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 15889 15890 /* Rx3 :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 15891 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 15892 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 15893 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 15894 #define RX3_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 15895 15896 /* Rx3 :: anaRxControl1G :: reserved0 [03:02] */ 15897 #define RX3_ANARXCONTROL1G_RESERVED0_MASK 0x000c 15898 #define RX3_ANARXCONTROL1G_RESERVED0_ALIGN 0 15899 #define RX3_ANARXCONTROL1G_RESERVED0_BITS 2 15900 #define RX3_ANARXCONTROL1G_RESERVED0_SHIFT 2 15901 15902 /* Rx3 :: anaRxControl1G :: freq_sel_force [01:01] */ 15903 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 15904 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 15905 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 15906 #define RX3_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 15907 15908 /* Rx3 :: anaRxControl1G :: freq_sel [00:00] */ 15909 #define RX3_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 15910 #define RX3_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 15911 #define RX3_ANARXCONTROL1G_FREQ_SEL_BITS 1 15912 #define RX3_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 15913 15914 15915 /**************************************************************************** 15916 * Rx3 :: anaRxControlPci 15917 */ 15918 /* Rx3 :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 15919 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 15920 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 15921 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 15922 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 15923 15924 /* Rx3 :: anaRxControlPci :: comma_mask_force_r [14:14] */ 15925 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 15926 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 15927 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 15928 #define RX3_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 15929 15930 /* Rx3 :: anaRxControlPci :: comma_mask_r [13:13] */ 15931 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 15932 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 15933 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 15934 #define RX3_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 15935 15936 /* Rx3 :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 15937 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 15938 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 15939 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 15940 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 15941 15942 /* Rx3 :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 15943 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 15944 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 15945 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 15946 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 15947 15948 /* Rx3 :: anaRxControlPci :: sync_status_force_r [10:10] */ 15949 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 15950 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 15951 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 15952 #define RX3_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 15953 15954 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 15955 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 15956 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 15957 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 15958 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 15959 15960 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 15961 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 15962 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 15963 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 15964 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 15965 15966 /* Rx3 :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 15967 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 15968 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 15969 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 15970 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 15971 15972 /* Rx3 :: anaRxControlPci :: comma_adj_en_r [06:06] */ 15973 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 15974 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 15975 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 15976 #define RX3_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 15977 15978 /* Rx3 :: anaRxControlPci :: link_en_force_SM [05:05] */ 15979 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 15980 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 15981 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 15982 #define RX3_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 15983 15984 /* Rx3 :: anaRxControlPci :: link_en_r [04:04] */ 15985 #define RX3_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 15986 #define RX3_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 15987 #define RX3_ANARXCONTROLPCI_LINK_EN_R_BITS 1 15988 #define RX3_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 15989 15990 /* Rx3 :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 15991 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 15992 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 15993 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 15994 #define RX3_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 15995 15996 /* Rx3 :: anaRxControlPci :: rx_polarity_r [02:02] */ 15997 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 15998 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 15999 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 16000 #define RX3_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 16001 16002 /* Rx3 :: anaRxControlPci :: integ_mode_SM [01:00] */ 16003 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 16004 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 16005 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 16006 #define RX3_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 16007 16008 16009 /**************************************************************************** 16010 * Rx3 :: anaRxAstatus 16011 */ 16012 /* Rx3 :: anaRxAstatus :: sigdet [15:15] */ 16013 #define RX3_ANARXASTATUS_SIGDET_MASK 0x8000 16014 #define RX3_ANARXASTATUS_SIGDET_ALIGN 0 16015 #define RX3_ANARXASTATUS_SIGDET_BITS 1 16016 #define RX3_ANARXASTATUS_SIGDET_SHIFT 15 16017 16018 /* Rx3 :: anaRxAstatus :: rx_pf [14:12] */ 16019 #define RX3_ANARXASTATUS_RX_PF_MASK 0x7000 16020 #define RX3_ANARXASTATUS_RX_PF_ALIGN 0 16021 #define RX3_ANARXASTATUS_RX_PF_BITS 3 16022 #define RX3_ANARXASTATUS_RX_PF_SHIFT 12 16023 16024 /* Rx3 :: anaRxAstatus :: dfe [11:06] */ 16025 #define RX3_ANARXASTATUS_DFE_MASK 0x0fc0 16026 #define RX3_ANARXASTATUS_DFE_ALIGN 0 16027 #define RX3_ANARXASTATUS_DFE_BITS 6 16028 #define RX3_ANARXASTATUS_DFE_SHIFT 6 16029 16030 /* Rx3 :: anaRxAstatus :: reserved0 [05:05] */ 16031 #define RX3_ANARXASTATUS_RESERVED0_MASK 0x0020 16032 #define RX3_ANARXASTATUS_RESERVED0_ALIGN 0 16033 #define RX3_ANARXASTATUS_RESERVED0_BITS 1 16034 #define RX3_ANARXASTATUS_RESERVED0_SHIFT 5 16035 16036 /* Rx3 :: anaRxAstatus :: vga [04:00] */ 16037 #define RX3_ANARXASTATUS_VGA_MASK 0x001f 16038 #define RX3_ANARXASTATUS_VGA_ALIGN 0 16039 #define RX3_ANARXASTATUS_VGA_BITS 5 16040 #define RX3_ANARXASTATUS_VGA_SHIFT 0 16041 16042 16043 /**************************************************************************** 16044 * Rx3 :: anaRxAControl1 16045 */ 16046 /* Rx3 :: anaRxAControl1 :: imode_vcm [15:15] */ 16047 #define RX3_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 16048 #define RX3_ANARXACONTROL1_IMODE_VCM_ALIGN 0 16049 #define RX3_ANARXACONTROL1_IMODE_VCM_BITS 1 16050 #define RX3_ANARXACONTROL1_IMODE_VCM_SHIFT 15 16051 16052 /* Rx3 :: anaRxAControl1 :: imin_vcm [14:14] */ 16053 #define RX3_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 16054 #define RX3_ANARXACONTROL1_IMIN_VCM_ALIGN 0 16055 #define RX3_ANARXACONTROL1_IMIN_VCM_BITS 1 16056 #define RX3_ANARXACONTROL1_IMIN_VCM_SHIFT 14 16057 16058 /* Rx3 :: anaRxAControl1 :: imax_sigdet [13:13] */ 16059 #define RX3_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 16060 #define RX3_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 16061 #define RX3_ANARXACONTROL1_IMAX_SIGDET_BITS 1 16062 #define RX3_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 16063 16064 /* Rx3 :: anaRxAControl1 :: imode_sigdet [12:12] */ 16065 #define RX3_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 16066 #define RX3_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 16067 #define RX3_ANARXACONTROL1_IMODE_SIGDET_BITS 1 16068 #define RX3_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 16069 16070 /* Rx3 :: anaRxAControl1 :: imin_sigdet [11:11] */ 16071 #define RX3_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 16072 #define RX3_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 16073 #define RX3_ANARXACONTROL1_IMIN_SIGDET_BITS 1 16074 #define RX3_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 16075 16076 /* Rx3 :: anaRxAControl1 :: refh_rx [10:10] */ 16077 #define RX3_ANARXACONTROL1_REFH_RX_MASK 0x0400 16078 #define RX3_ANARXACONTROL1_REFH_RX_ALIGN 0 16079 #define RX3_ANARXACONTROL1_REFH_RX_BITS 1 16080 #define RX3_ANARXACONTROL1_REFH_RX_SHIFT 10 16081 16082 /* Rx3 :: anaRxAControl1 :: refl_rx [09:09] */ 16083 #define RX3_ANARXACONTROL1_REFL_RX_MASK 0x0200 16084 #define RX3_ANARXACONTROL1_REFL_RX_ALIGN 0 16085 #define RX3_ANARXACONTROL1_REFL_RX_BITS 1 16086 #define RX3_ANARXACONTROL1_REFL_RX_SHIFT 9 16087 16088 /* Rx3 :: anaRxAControl1 :: tport_en [08:08] */ 16089 #define RX3_ANARXACONTROL1_TPORT_EN_MASK 0x0100 16090 #define RX3_ANARXACONTROL1_TPORT_EN_ALIGN 0 16091 #define RX3_ANARXACONTROL1_TPORT_EN_BITS 1 16092 #define RX3_ANARXACONTROL1_TPORT_EN_SHIFT 8 16093 16094 /* Rx3 :: anaRxAControl1 :: vddrb_bg [07:07] */ 16095 #define RX3_ANARXACONTROL1_VDDRB_BG_MASK 0x0080 16096 #define RX3_ANARXACONTROL1_VDDRB_BG_ALIGN 0 16097 #define RX3_ANARXACONTROL1_VDDRB_BG_BITS 1 16098 #define RX3_ANARXACONTROL1_VDDRB_BG_SHIFT 7 16099 16100 /* Rx3 :: anaRxAControl1 :: sig_pwrdn [06:06] */ 16101 #define RX3_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 16102 #define RX3_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 16103 #define RX3_ANARXACONTROL1_SIG_PWRDN_BITS 1 16104 #define RX3_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 16105 16106 /* Rx3 :: anaRxAControl1 :: offset_ctrl [05:03] */ 16107 #define RX3_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 16108 #define RX3_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 16109 #define RX3_ANARXACONTROL1_OFFSET_CTRL_BITS 3 16110 #define RX3_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 16111 16112 /* Rx3 :: anaRxAControl1 :: offset_sel [02:02] */ 16113 #define RX3_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 16114 #define RX3_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 16115 #define RX3_ANARXACONTROL1_OFFSET_SEL_BITS 1 16116 #define RX3_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 16117 16118 /* Rx3 :: anaRxAControl1 :: reserved0 [01:00] */ 16119 #define RX3_ANARXACONTROL1_RESERVED0_MASK 0x0003 16120 #define RX3_ANARXACONTROL1_RESERVED0_ALIGN 0 16121 #define RX3_ANARXACONTROL1_RESERVED0_BITS 2 16122 #define RX3_ANARXACONTROL1_RESERVED0_SHIFT 0 16123 16124 16125 /**************************************************************************** 16126 * Rx3 :: anaRxAControl2 16127 */ 16128 /* Rx3 :: anaRxAControl2 :: imax_clkbuf [15:15] */ 16129 #define RX3_ANARXACONTROL2_IMAX_CLKBUF_MASK 0x8000 16130 #define RX3_ANARXACONTROL2_IMAX_CLKBUF_ALIGN 0 16131 #define RX3_ANARXACONTROL2_IMAX_CLKBUF_BITS 1 16132 #define RX3_ANARXACONTROL2_IMAX_CLKBUF_SHIFT 15 16133 16134 /* Rx3 :: anaRxAControl2 :: imode_clkbuf [14:14] */ 16135 #define RX3_ANARXACONTROL2_IMODE_CLKBUF_MASK 0x4000 16136 #define RX3_ANARXACONTROL2_IMODE_CLKBUF_ALIGN 0 16137 #define RX3_ANARXACONTROL2_IMODE_CLKBUF_BITS 1 16138 #define RX3_ANARXACONTROL2_IMODE_CLKBUF_SHIFT 14 16139 16140 /* Rx3 :: anaRxAControl2 :: imin_clkbuf [13:13] */ 16141 #define RX3_ANARXACONTROL2_IMIN_CLKBUF_MASK 0x2000 16142 #define RX3_ANARXACONTROL2_IMIN_CLKBUF_ALIGN 0 16143 #define RX3_ANARXACONTROL2_IMIN_CLKBUF_BITS 1 16144 #define RX3_ANARXACONTROL2_IMIN_CLKBUF_SHIFT 13 16145 16146 /* Rx3 :: anaRxAControl2 :: imax_eqfl [12:12] */ 16147 #define RX3_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 16148 #define RX3_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 16149 #define RX3_ANARXACONTROL2_IMAX_EQFL_BITS 1 16150 #define RX3_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 16151 16152 /* Rx3 :: anaRxAControl2 :: imode_eqfl [11:11] */ 16153 #define RX3_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 16154 #define RX3_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 16155 #define RX3_ANARXACONTROL2_IMODE_EQFL_BITS 1 16156 #define RX3_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 16157 16158 /* Rx3 :: anaRxAControl2 :: imin_eqfl [10:10] */ 16159 #define RX3_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 16160 #define RX3_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 16161 #define RX3_ANARXACONTROL2_IMIN_EQFL_BITS 1 16162 #define RX3_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 16163 16164 /* Rx3 :: anaRxAControl2 :: imax_dfesum [09:09] */ 16165 #define RX3_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 16166 #define RX3_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 16167 #define RX3_ANARXACONTROL2_IMAX_DFESUM_BITS 1 16168 #define RX3_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 16169 16170 /* Rx3 :: anaRxAControl2 :: imode_dfesum [08:08] */ 16171 #define RX3_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 16172 #define RX3_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 16173 #define RX3_ANARXACONTROL2_IMODE_DFESUM_BITS 1 16174 #define RX3_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 16175 16176 /* Rx3 :: anaRxAControl2 :: imin_dfesum [07:07] */ 16177 #define RX3_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 16178 #define RX3_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 16179 #define RX3_ANARXACONTROL2_IMIN_DFESUM_BITS 1 16180 #define RX3_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 16181 16182 /* Rx3 :: anaRxAControl2 :: imax_vga [06:06] */ 16183 #define RX3_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 16184 #define RX3_ANARXACONTROL2_IMAX_VGA_ALIGN 0 16185 #define RX3_ANARXACONTROL2_IMAX_VGA_BITS 1 16186 #define RX3_ANARXACONTROL2_IMAX_VGA_SHIFT 6 16187 16188 /* Rx3 :: anaRxAControl2 :: imode_vga [05:05] */ 16189 #define RX3_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 16190 #define RX3_ANARXACONTROL2_IMODE_VGA_ALIGN 0 16191 #define RX3_ANARXACONTROL2_IMODE_VGA_BITS 1 16192 #define RX3_ANARXACONTROL2_IMODE_VGA_SHIFT 5 16193 16194 /* Rx3 :: anaRxAControl2 :: imin_vga [04:04] */ 16195 #define RX3_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 16196 #define RX3_ANARXACONTROL2_IMIN_VGA_ALIGN 0 16197 #define RX3_ANARXACONTROL2_IMIN_VGA_BITS 1 16198 #define RX3_ANARXACONTROL2_IMIN_VGA_SHIFT 4 16199 16200 /* Rx3 :: anaRxAControl2 :: imax_interp [03:03] */ 16201 #define RX3_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 16202 #define RX3_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 16203 #define RX3_ANARXACONTROL2_IMAX_INTERP_BITS 1 16204 #define RX3_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 16205 16206 /* Rx3 :: anaRxAControl2 :: imode_interp [02:02] */ 16207 #define RX3_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 16208 #define RX3_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 16209 #define RX3_ANARXACONTROL2_IMODE_INTERP_BITS 1 16210 #define RX3_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 16211 16212 /* Rx3 :: anaRxAControl2 :: imin_interp [01:01] */ 16213 #define RX3_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 16214 #define RX3_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 16215 #define RX3_ANARXACONTROL2_IMIN_INTERP_BITS 1 16216 #define RX3_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 16217 16218 /* Rx3 :: anaRxAControl2 :: imax_vcm [00:00] */ 16219 #define RX3_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 16220 #define RX3_ANARXACONTROL2_IMAX_VCM_ALIGN 0 16221 #define RX3_ANARXACONTROL2_IMAX_VCM_BITS 1 16222 #define RX3_ANARXACONTROL2_IMAX_VCM_SHIFT 0 16223 16224 16225 /**************************************************************************** 16226 * Rx3 :: anaRxAControl3 16227 */ 16228 /* Rx3 :: anaRxAControl3 :: en_clk16 [15:15] */ 16229 #define RX3_ANARXACONTROL3_EN_CLK16_MASK 0x8000 16230 #define RX3_ANARXACONTROL3_EN_CLK16_ALIGN 0 16231 #define RX3_ANARXACONTROL3_EN_CLK16_BITS 1 16232 #define RX3_ANARXACONTROL3_EN_CLK16_SHIFT 15 16233 16234 /* Rx3 :: anaRxAControl3 :: pd_ch_p1 [14:14] */ 16235 #define RX3_ANARXACONTROL3_PD_CH_P1_MASK 0x4000 16236 #define RX3_ANARXACONTROL3_PD_CH_P1_ALIGN 0 16237 #define RX3_ANARXACONTROL3_PD_CH_P1_BITS 1 16238 #define RX3_ANARXACONTROL3_PD_CH_P1_SHIFT 14 16239 16240 /* Rx3 :: anaRxAControl3 :: en_vcctrl [13:13] */ 16241 #define RX3_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 16242 #define RX3_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 16243 #define RX3_ANARXACONTROL3_EN_VCCTRL_BITS 1 16244 #define RX3_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 16245 16246 /* Rx3 :: anaRxAControl3 :: en_dfeclk [12:12] */ 16247 #define RX3_ANARXACONTROL3_EN_DFECLK_MASK 0x1000 16248 #define RX3_ANARXACONTROL3_EN_DFECLK_ALIGN 0 16249 #define RX3_ANARXACONTROL3_EN_DFECLK_BITS 1 16250 #define RX3_ANARXACONTROL3_EN_DFECLK_SHIFT 12 16251 16252 /* Rx3 :: anaRxAControl3 :: en_hgain [11:11] */ 16253 #define RX3_ANARXACONTROL3_EN_HGAIN_MASK 0x0800 16254 #define RX3_ANARXACONTROL3_EN_HGAIN_ALIGN 0 16255 #define RX3_ANARXACONTROL3_EN_HGAIN_BITS 1 16256 #define RX3_ANARXACONTROL3_EN_HGAIN_SHIFT 11 16257 16258 /* Rx3 :: anaRxAControl3 :: en_dfeckpwr [10:10] */ 16259 #define RX3_ANARXACONTROL3_EN_DFECKPWR_MASK 0x0400 16260 #define RX3_ANARXACONTROL3_EN_DFECKPWR_ALIGN 0 16261 #define RX3_ANARXACONTROL3_EN_DFECKPWR_BITS 1 16262 #define RX3_ANARXACONTROL3_EN_DFECKPWR_SHIFT 10 16263 16264 /* Rx3 :: anaRxAControl3 :: offset_pd [09:09] */ 16265 #define RX3_ANARXACONTROL3_OFFSET_PD_MASK 0x0200 16266 #define RX3_ANARXACONTROL3_OFFSET_PD_ALIGN 0 16267 #define RX3_ANARXACONTROL3_OFFSET_PD_BITS 1 16268 #define RX3_ANARXACONTROL3_OFFSET_PD_SHIFT 9 16269 16270 /* Rx3 :: anaRxAControl3 :: imax_dfetap [08:08] */ 16271 #define RX3_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 16272 #define RX3_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 16273 #define RX3_ANARXACONTROL3_IMAX_DFETAP_BITS 1 16274 #define RX3_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 16275 16276 /* Rx3 :: anaRxAControl3 :: imode_dfetap [07:07] */ 16277 #define RX3_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 16278 #define RX3_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 16279 #define RX3_ANARXACONTROL3_IMODE_DFETAP_BITS 1 16280 #define RX3_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 16281 16282 /* Rx3 :: anaRxAControl3 :: imin_dfetap [06:06] */ 16283 #define RX3_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 16284 #define RX3_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 16285 #define RX3_ANARXACONTROL3_IMIN_DFETAP_BITS 1 16286 #define RX3_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 16287 16288 /* Rx3 :: anaRxAControl3 :: imax_slcd2c [05:05] */ 16289 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 16290 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 16291 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 16292 #define RX3_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 16293 16294 /* Rx3 :: anaRxAControl3 :: imode_slcd2c [04:04] */ 16295 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 16296 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 16297 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 16298 #define RX3_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 16299 16300 /* Rx3 :: anaRxAControl3 :: imin_slcd2c [03:03] */ 16301 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 16302 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 16303 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 16304 #define RX3_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 16305 16306 /* Rx3 :: anaRxAControl3 :: imax_dfevref [02:02] */ 16307 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 16308 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 16309 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 16310 #define RX3_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 16311 16312 /* Rx3 :: anaRxAControl3 :: imode_dfevref [01:01] */ 16313 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 16314 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 16315 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 16316 #define RX3_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 16317 16318 /* Rx3 :: anaRxAControl3 :: imin_dfevref [00:00] */ 16319 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 16320 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 16321 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 16322 #define RX3_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 16323 16324 16325 /**************************************************************************** 16326 * Hypercore_USER_RxB 16327 */ 16328 /**************************************************************************** 16329 * RxB :: anaRxStatus 16330 */ 16331 /* union - case sigdet_Status [15:00] */ 16332 /* RxB :: anaRxStatus :: cx4_sigdet [15:15] */ 16333 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK 0x8000 16334 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN 0 16335 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS 1 16336 #define RXB_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT 15 16337 16338 /* RxB :: anaRxStatus :: reserved0 [14:13] */ 16339 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK 0x6000 16340 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN 0 16341 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS 2 16342 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT 13 16343 16344 /* RxB :: anaRxStatus :: rxSeqDone [12:12] */ 16345 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK 0x1000 16346 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN 0 16347 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS 1 16348 #define RXB_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT 12 16349 16350 /* RxB :: anaRxStatus :: rx_sigdet_ll [11:11] */ 16351 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK 0x0800 16352 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0 16353 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS 1 16354 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11 16355 16356 /* RxB :: anaRxStatus :: cs4_sigdet_ll [10:10] */ 16357 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400 16358 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0 16359 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1 16360 #define RXB_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10 16361 16362 /* RxB :: anaRxStatus :: rx_reset [09:09] */ 16363 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK 0x0200 16364 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN 0 16365 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS 1 16366 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT 9 16367 16368 /* RxB :: anaRxStatus :: rx_pwrdn [08:08] */ 16369 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK 0x0100 16370 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN 0 16371 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS 1 16372 #define RXB_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT 8 16373 16374 /* RxB :: anaRxStatus :: reserved1 [07:00] */ 16375 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK 0x00ff 16376 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN 0 16377 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS 8 16378 #define RXB_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT 0 16379 16380 16381 /* union - case sync_Status [15:00] */ 16382 /* RxB :: anaRxStatus :: reserved0 [15:11] */ 16383 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK 0xf800 16384 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN 0 16385 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS 5 16386 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT 11 16387 16388 /* RxB :: anaRxStatus :: test_acq_en [10:10] */ 16389 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK 0x0400 16390 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN 0 16391 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS 1 16392 #define RXB_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT 10 16393 16394 /* RxB :: anaRxStatus :: reserved1 [09:09] */ 16395 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK 0x0200 16396 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN 0 16397 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS 1 16398 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT 9 16399 16400 /* RxB :: anaRxStatus :: rxSeqStart [08:08] */ 16401 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK 0x0100 16402 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN 0 16403 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS 1 16404 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT 8 16405 16406 /* RxB :: anaRxStatus :: mux_comadj_sync_status [07:07] */ 16407 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080 16408 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0 16409 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1 16410 #define RXB_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7 16411 16412 /* RxB :: anaRxStatus :: sync_status [06:06] */ 16413 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK 0x0040 16414 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN 0 16415 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS 1 16416 #define RXB_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT 6 16417 16418 /* RxB :: anaRxStatus :: rx_sigdet [05:05] */ 16419 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK 0x0020 16420 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN 0 16421 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS 1 16422 #define RXB_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT 5 16423 16424 /* RxB :: anaRxStatus :: reserved2 [04:03] */ 16425 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK 0x0018 16426 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN 0 16427 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS 2 16428 #define RXB_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT 3 16429 16430 /* RxB :: anaRxStatus :: saturate_status [02:02] */ 16431 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004 16432 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0 16433 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1 16434 #define RXB_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2 16435 16436 /* RxB :: anaRxStatus :: cx4_sigdet [01:01] */ 16437 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK 0x0002 16438 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN 0 16439 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS 1 16440 #define RXB_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT 1 16441 16442 /* RxB :: anaRxStatus :: rxSeqDone [00:00] */ 16443 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK 0x0001 16444 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN 0 16445 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS 1 16446 #define RXB_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT 0 16447 16448 16449 /* union - case rxTestSel_0 [15:00] */ 16450 /* RxB :: anaRxStatus :: reserved0 [15:10] */ 16451 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK 0xfc00 16452 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN 0 16453 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS 6 16454 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT 10 16455 16456 /* RxB :: anaRxStatus :: indck_mode_en [09:09] */ 16457 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK 0x0200 16458 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN 0 16459 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS 1 16460 #define RXB_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT 9 16461 16462 /* RxB :: anaRxStatus :: pci_mode_en [08:08] */ 16463 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK 0x0100 16464 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN 0 16465 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS 1 16466 #define RXB_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT 8 16467 16468 /* RxB :: anaRxStatus :: rx_polarity [07:07] */ 16469 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK 0x0080 16470 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN 0 16471 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS 1 16472 #define RXB_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT 7 16473 16474 /* RxB :: anaRxStatus :: rxpol_flip [06:06] */ 16475 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK 0x0040 16476 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN 0 16477 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS 1 16478 #define RXB_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT 6 16479 16480 /* RxB :: anaRxStatus :: comma_mask [05:05] */ 16481 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK 0x0020 16482 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN 0 16483 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS 1 16484 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT 5 16485 16486 /* RxB :: anaRxStatus :: link_en_r [04:04] */ 16487 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK 0x0010 16488 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN 0 16489 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS 1 16490 #define RXB_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT 4 16491 16492 /* RxB :: anaRxStatus :: comma_adj_en [03:03] */ 16493 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK 0x0008 16494 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN 0 16495 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS 1 16496 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT 3 16497 16498 /* RxB :: anaRxStatus :: comma_adj_en_ext [02:02] */ 16499 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004 16500 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0 16501 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1 16502 #define RXB_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2 16503 16504 /* RxB :: anaRxStatus :: reserved1 [01:00] */ 16505 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK 0x0003 16506 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN 0 16507 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS 2 16508 #define RXB_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT 0 16509 16510 16511 /* union - case rxTestSel_1 [15:00] */ 16512 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 16513 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK 0xffe0 16514 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN 0 16515 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS 11 16516 #define RXB_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT 5 16517 16518 /* RxB :: anaRxStatus :: cdrAcqDone_r2 [04:04] */ 16519 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK 0x0010 16520 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN 0 16521 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS 1 16522 #define RXB_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT 4 16523 16524 /* RxB :: anaRxStatus :: freq_sel_PC [03:03] */ 16525 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK 0x0008 16526 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN 0 16527 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS 1 16528 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT 3 16529 16530 /* RxB :: anaRxStatus :: freq_sel_SM [02:02] */ 16531 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK 0x0004 16532 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN 0 16533 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS 1 16534 #define RXB_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT 2 16535 16536 /* RxB :: anaRxStatus :: integ_mode_SM [01:00] */ 16537 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK 0x0003 16538 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN 0 16539 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS 2 16540 #define RXB_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT 0 16541 16542 16543 /* union - case scale_Status [15:00] */ 16544 /* RxB :: anaRxStatus :: prop_scale [15:12] */ 16545 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK 0xf000 16546 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN 0 16547 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS 4 16548 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT 12 16549 16550 /* RxB :: anaRxStatus :: integ_scale [11:08] */ 16551 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK 0x0f00 16552 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN 0 16553 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS 4 16554 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT 8 16555 16556 /* RxB :: anaRxStatus :: prop_scale_acq [07:04] */ 16557 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0 16558 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0 16559 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4 16560 #define RXB_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4 16561 16562 /* RxB :: anaRxStatus :: integ_scale_acq [03:00] */ 16563 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f 16564 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0 16565 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4 16566 #define RXB_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0 16567 16568 16569 /* union - case adc_CdrStatus1 [15:00] */ 16570 /* RxB :: anaRxStatus :: reserved0 [15:07] */ 16571 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK 0xff80 16572 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN 0 16573 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS 9 16574 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT 7 16575 16576 /* RxB :: anaRxStatus :: rxMuxCkSel [06:06] */ 16577 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK 0x0040 16578 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN 0 16579 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS 1 16580 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT 6 16581 16582 /* RxB :: anaRxStatus :: glpbk_combo [05:05] */ 16583 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK 0x0020 16584 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0 16585 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS 1 16586 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5 16587 16588 /* RxB :: anaRxStatus :: clockSwitchSel [04:04] */ 16589 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010 16590 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0 16591 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1 16592 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4 16593 16594 /* RxB :: anaRxStatus :: rxck_tst [03:03] */ 16595 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK 0x0008 16596 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN 0 16597 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS 1 16598 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT 3 16599 16600 /* RxB :: anaRxStatus :: rxck_i [02:02] */ 16601 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK 0x0004 16602 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN 0 16603 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS 1 16604 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT 2 16605 16606 /* RxB :: anaRxStatus :: refclk [01:01] */ 16607 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK 0x0002 16608 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN 0 16609 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS 1 16610 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT 1 16611 16612 /* RxB :: anaRxStatus :: pll_bypass [00:00] */ 16613 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK 0x0001 16614 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN 0 16615 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS 1 16616 #define RXB_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT 0 16617 16618 16619 /* union - case adc_CdrStatus2 [15:00] */ 16620 /* RxB :: anaRxStatus :: reserved0 [15:06] */ 16621 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK 0xffc0 16622 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN 0 16623 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS 10 16624 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT 6 16625 16626 /* RxB :: anaRxStatus :: rxMuxCkSel [05:05] */ 16627 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK 0x0020 16628 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN 0 16629 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS 1 16630 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT 5 16631 16632 /* RxB :: anaRxStatus :: rxSeqStart [04:04] */ 16633 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK 0x0010 16634 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN 0 16635 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS 1 16636 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT 4 16637 16638 /* RxB :: anaRxStatus :: reserved1 [03:01] */ 16639 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK 0x000e 16640 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN 0 16641 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS 3 16642 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT 1 16643 16644 /* RxB :: anaRxStatus :: rxSeqDone [00:00] */ 16645 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK 0x0001 16646 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN 0 16647 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS 1 16648 #define RXB_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT 0 16649 16650 16651 /* union - case adc_CdrStatus3 [15:00] */ 16652 /* RxB :: anaRxStatus :: reserved0 [15:04] */ 16653 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK 0xfff0 16654 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN 0 16655 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS 12 16656 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT 4 16657 16658 /* RxB :: anaRxStatus :: rxSeqStart [03:03] */ 16659 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK 0x0008 16660 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN 0 16661 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS 1 16662 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT 3 16663 16664 /* RxB :: anaRxStatus :: reserved1 [02:01] */ 16665 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK 0x0006 16666 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN 0 16667 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS 2 16668 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT 1 16669 16670 /* RxB :: anaRxStatus :: allow_increment_PC [00:00] */ 16671 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001 16672 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0 16673 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1 16674 #define RXB_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0 16675 16676 16677 /* union - case adc_CdrStatus4 [15:00] */ 16678 /* RxB :: anaRxStatus :: reserved0 [15:08] */ 16679 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK 0xff00 16680 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN 0 16681 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS 8 16682 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT 8 16683 16684 /* RxB :: anaRxStatus :: rx_pwrdn [07:07] */ 16685 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK 0x0080 16686 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN 0 16687 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS 1 16688 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT 7 16689 16690 /* RxB :: anaRxStatus :: freq_sel [06:06] */ 16691 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK 0x0040 16692 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN 0 16693 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS 1 16694 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT 6 16695 16696 /* RxB :: anaRxStatus :: pll_lock_rstb [05:05] */ 16697 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020 16698 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0 16699 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1 16700 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5 16701 16702 /* RxB :: anaRxStatus :: pwrdn [04:04] */ 16703 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK 0x0010 16704 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN 0 16705 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS 1 16706 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT 4 16707 16708 /* RxB :: anaRxStatus :: reserved1 [03:00] */ 16709 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK 0x000f 16710 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN 0 16711 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS 4 16712 #define RXB_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT 0 16713 16714 16715 /* union - case adc_CdrStatus5 [15:00] */ 16716 /* RxB :: anaRxStatus :: reserved0 [15:00] */ 16717 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK 0xffff 16718 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN 0 16719 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS 16 16720 #define RXB_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT 0 16721 16722 16723 /* union - case adc_CdrStatus6 [15:00] */ 16724 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 16725 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK 0xffe0 16726 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN 0 16727 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS 11 16728 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT 5 16729 16730 /* RxB :: anaRxStatus :: rx_reset [04:04] */ 16731 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK 0x0010 16732 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN 0 16733 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS 1 16734 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT 4 16735 16736 /* RxB :: anaRxStatus :: rx_pwrdn [03:03] */ 16737 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK 0x0008 16738 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN 0 16739 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS 1 16740 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT 3 16741 16742 /* RxB :: anaRxStatus :: reset_anlg [02:02] */ 16743 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK 0x0004 16744 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN 0 16745 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS 1 16746 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT 2 16747 16748 /* RxB :: anaRxStatus :: pwrdn_rx [01:01] */ 16749 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK 0x0002 16750 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN 0 16751 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS 1 16752 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT 1 16753 16754 /* RxB :: anaRxStatus :: pwrdn_pll [00:00] */ 16755 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK 0x0001 16756 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN 0 16757 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS 1 16758 #define RXB_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT 0 16759 16760 16761 /* union - case adc_CdrStatus7e [15:00] */ 16762 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 16763 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK 0xffe0 16764 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN 0 16765 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS 11 16766 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT 5 16767 16768 /* RxB :: anaRxStatus :: rxck0_even [04:04] */ 16769 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK 0x0010 16770 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0 16771 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS 1 16772 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4 16773 16774 /* RxB :: anaRxStatus :: rxck1_even [03:03] */ 16775 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK 0x0008 16776 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0 16777 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS 1 16778 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3 16779 16780 /* RxB :: anaRxStatus :: comdet_even [02:02] */ 16781 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004 16782 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0 16783 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1 16784 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2 16785 16786 /* RxB :: anaRxStatus :: en_cdet_even [01:01] */ 16787 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002 16788 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0 16789 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1 16790 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1 16791 16792 /* RxB :: anaRxStatus :: comma_adj_en_even [00:00] */ 16793 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001 16794 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0 16795 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1 16796 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0 16797 16798 16799 /* union - case adc_CdrStatus7o [15:00] */ 16800 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 16801 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK 0xffe0 16802 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN 0 16803 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS 11 16804 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT 5 16805 16806 /* RxB :: anaRxStatus :: rxck0_odd [04:04] */ 16807 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK 0x0010 16808 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN 0 16809 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS 1 16810 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT 4 16811 16812 /* RxB :: anaRxStatus :: rxck1_odd [03:03] */ 16813 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK 0x0008 16814 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN 0 16815 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS 1 16816 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT 3 16817 16818 /* RxB :: anaRxStatus :: comdet_odd [02:02] */ 16819 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK 0x0004 16820 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0 16821 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS 1 16822 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2 16823 16824 /* RxB :: anaRxStatus :: en_cdet_odd [01:01] */ 16825 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002 16826 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0 16827 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1 16828 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1 16829 16830 /* RxB :: anaRxStatus :: comma_adj_en_odd [00:00] */ 16831 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001 16832 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0 16833 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1 16834 #define RXB_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0 16835 16836 16837 /* union - case adc_CdrStatus8 [15:00] */ 16838 /* RxB :: anaRxStatus :: reserved0 [15:01] */ 16839 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK 0xfffe 16840 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN 0 16841 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS 15 16842 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT 1 16843 16844 /* RxB :: anaRxStatus :: sigdet [00:00] */ 16845 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK 0x0001 16846 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN 0 16847 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS 1 16848 #define RXB_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT 0 16849 16850 16851 /* union - case adc_CdrStatus9 [15:00] */ 16852 /* RxB :: anaRxStatus :: reserved0 [15:00] */ 16853 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK 0xffff 16854 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN 0 16855 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS 16 16856 #define RXB_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT 0 16857 16858 16859 /* union - case adc_CdrStatus10 [15:00] */ 16860 /* RxB :: anaRxStatus :: reserved0 [15:07] */ 16861 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK 0xff80 16862 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN 0 16863 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS 9 16864 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT 7 16865 16866 /* RxB :: anaRxStatus :: prbs_en [06:06] */ 16867 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK 0x0040 16868 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN 0 16869 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS 1 16870 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT 6 16871 16872 /* RxB :: anaRxStatus :: rstb_tst [05:05] */ 16873 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK 0x0020 16874 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN 0 16875 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS 1 16876 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT 5 16877 16878 /* RxB :: anaRxStatus :: reserved1 [04:04] */ 16879 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK 0x0010 16880 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN 0 16881 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS 1 16882 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT 4 16883 16884 /* RxB :: anaRxStatus :: prbs_state [03:00] */ 16885 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK 0x000f 16886 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0 16887 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS 4 16888 #define RXB_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0 16889 16890 16891 /* union - case adc_CdrStatus11 [15:00] */ 16892 /* RxB :: anaRxStatus :: reserved0 [15:00] */ 16893 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK 0xffff 16894 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN 0 16895 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS 16 16896 #define RXB_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT 0 16897 16898 16899 /* union - case adc_CdrStatus12_1 [15:00] */ 16900 /* RxB :: anaRxStatus :: reserved0 [15:06] */ 16901 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0 16902 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0 16903 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10 16904 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6 16905 16906 /* RxB :: anaRxStatus :: enable4 [05:05] */ 16907 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK 0x0020 16908 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN 0 16909 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS 1 16910 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT 5 16911 16912 /* RxB :: anaRxStatus :: radr_test [04:00] */ 16913 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f 16914 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0 16915 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5 16916 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0 16917 16918 16919 /* union - case adc_CdrStatus12_2 [15:00] */ 16920 /* RxB :: anaRxStatus :: reserved0 [15:05] */ 16921 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0 16922 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0 16923 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11 16924 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5 16925 16926 /* RxB :: anaRxStatus :: wadr_test [04:00] */ 16927 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f 16928 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0 16929 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5 16930 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0 16931 16932 16933 /* union - case adc_CdrStatus12_3 [15:00] */ 16934 /* RxB :: anaRxStatus :: reserved0 [15:06] */ 16935 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0 16936 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0 16937 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10 16938 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6 16939 16940 /* RxB :: anaRxStatus :: rxck_66B_tmux [05:05] */ 16941 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020 16942 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0 16943 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1 16944 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5 16945 16946 /* RxB :: anaRxStatus :: rstb_66B [04:04] */ 16947 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK 0x0010 16948 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0 16949 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS 1 16950 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4 16951 16952 /* RxB :: anaRxStatus :: prstb_66B_mux [03:03] */ 16953 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008 16954 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0 16955 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1 16956 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3 16957 16958 /* RxB :: anaRxStatus :: rxck_i66_tmux [02:02] */ 16959 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004 16960 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0 16961 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1 16962 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2 16963 16964 /* RxB :: anaRxStatus :: rstb_i66 [01:01] */ 16965 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK 0x0002 16966 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0 16967 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS 1 16968 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1 16969 16970 /* RxB :: anaRxStatus :: prstb_i66_mux [00:00] */ 16971 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001 16972 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0 16973 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1 16974 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0 16975 16976 16977 /* union - case adc_CdrStatus12_4 [15:00] */ 16978 /* RxB :: anaRxStatus :: reserved0 [15:04] */ 16979 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0 16980 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0 16981 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12 16982 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4 16983 16984 /* RxB :: anaRxStatus :: rfifo_error_r [03:02] */ 16985 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c 16986 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0 16987 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2 16988 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2 16989 16990 /* RxB :: anaRxStatus :: rfifo_unflow [01:01] */ 16991 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002 16992 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0 16993 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1 16994 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1 16995 16996 /* RxB :: anaRxStatus :: rfifo_ovflow [00:00] */ 16997 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001 16998 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0 16999 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1 17000 #define RXB_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0 17001 17002 17003 /* union - case integ_Status [15:00] */ 17004 /* RxB :: anaRxStatus :: integ_status [15:00] */ 17005 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK 0xffff 17006 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN 0 17007 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS 16 17008 #define RXB_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT 0 17009 17010 17011 /* union - case vco_Status [15:00] */ 17012 /* RxB :: anaRxStatus :: vco_status [15:00] */ 17013 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK 0xffff 17014 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN 0 17015 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS 16 17016 #define RXB_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT 0 17017 17018 17019 /* union - case prbs_Status [15:00] */ 17020 /* RxB :: anaRxStatus :: prbs_lock [15:15] */ 17021 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK 0x8000 17022 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN 0 17023 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS 1 17024 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT 15 17025 17026 /* RxB :: anaRxStatus :: prbs_stky [14:14] */ 17027 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK 0x4000 17028 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN 0 17029 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS 1 17030 #define RXB_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT 14 17031 17032 /* RxB :: anaRxStatus :: ptbs_errors [13:00] */ 17033 #define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_MASK 0x3fff 17034 #define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_ALIGN 0 17035 #define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_BITS 14 17036 #define RXB_ANARXSTATUS_PRBS_STATUS_PTBS_ERRORS_SHIFT 0 17037 17038 17039 17040 /**************************************************************************** 17041 * RxB :: anaRxControl 17042 */ 17043 /* RxB :: anaRxControl :: reserved0 [15:10] */ 17044 #define RXB_ANARXCONTROL_RESERVED0_MASK 0xfc00 17045 #define RXB_ANARXCONTROL_RESERVED0_ALIGN 0 17046 #define RXB_ANARXCONTROL_RESERVED0_BITS 6 17047 #define RXB_ANARXCONTROL_RESERVED0_SHIFT 10 17048 17049 /* RxB :: anaRxControl :: override_sigdet_en [09:09] */ 17050 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK 0x0200 17051 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN 0 17052 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS 1 17053 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT 9 17054 17055 /* RxB :: anaRxControl :: override_sigdet_val [08:08] */ 17056 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK 0x0100 17057 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN 0 17058 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS 1 17059 #define RXB_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT 8 17060 17061 /* RxB :: anaRxControl :: reserved1 [07:03] */ 17062 #define RXB_ANARXCONTROL_RESERVED1_MASK 0x00f8 17063 #define RXB_ANARXCONTROL_RESERVED1_ALIGN 0 17064 #define RXB_ANARXCONTROL_RESERVED1_BITS 5 17065 #define RXB_ANARXCONTROL_RESERVED1_SHIFT 3 17066 17067 /* RxB :: anaRxControl :: status_sel [02:00] */ 17068 #define RXB_ANARXCONTROL_STATUS_SEL_MASK 0x0007 17069 #define RXB_ANARXCONTROL_STATUS_SEL_ALIGN 0 17070 #define RXB_ANARXCONTROL_STATUS_SEL_BITS 3 17071 #define RXB_ANARXCONTROL_STATUS_SEL_SHIFT 0 17072 #define RXB_ANARXCONTROL_STATUS_SEL_sigdetStatus 0 17073 #define RXB_ANARXCONTROL_STATUS_SEL_syncStatus 1 17074 #define RXB_ANARXCONTROL_STATUS_SEL_rxTestSel 2 17075 #define RXB_ANARXCONTROL_STATUS_SEL_scaleStatus 3 17076 #define RXB_ANARXCONTROL_STATUS_SEL_adcCdrStatus 4 17077 #define RXB_ANARXCONTROL_STATUS_SEL_integStatus 5 17078 #define RXB_ANARXCONTROL_STATUS_SEL_vcoStatus 6 17079 #define RXB_ANARXCONTROL_STATUS_SEL_prbsStatus 7 17080 17081 17082 /**************************************************************************** 17083 * RxB :: anaRxTest 17084 */ 17085 /* RxB :: anaRxTest :: sigdet_mux_SM [15:12] */ 17086 #define RXB_ANARXTEST_SIGDET_MUX_SM_MASK 0xf000 17087 #define RXB_ANARXTEST_SIGDET_MUX_SM_ALIGN 0 17088 #define RXB_ANARXTEST_SIGDET_MUX_SM_BITS 4 17089 #define RXB_ANARXTEST_SIGDET_MUX_SM_SHIFT 12 17090 17091 /* RxB :: anaRxTest :: reserved0 [11:09] */ 17092 #define RXB_ANARXTEST_RESERVED0_MASK 0x0e00 17093 #define RXB_ANARXTEST_RESERVED0_ALIGN 0 17094 #define RXB_ANARXTEST_RESERVED0_BITS 3 17095 #define RXB_ANARXTEST_RESERVED0_SHIFT 9 17096 17097 /* RxB :: anaRxTest :: tpctrl_SM [08:04] */ 17098 #define RXB_ANARXTEST_TPCTRL_SM_MASK 0x01f0 17099 #define RXB_ANARXTEST_TPCTRL_SM_ALIGN 0 17100 #define RXB_ANARXTEST_TPCTRL_SM_BITS 5 17101 #define RXB_ANARXTEST_TPCTRL_SM_SHIFT 4 17102 17103 /* RxB :: anaRxTest :: testMuxSelect_SM [03:00] */ 17104 #define RXB_ANARXTEST_TESTMUXSELECT_SM_MASK 0x000f 17105 #define RXB_ANARXTEST_TESTMUXSELECT_SM_ALIGN 0 17106 #define RXB_ANARXTEST_TESTMUXSELECT_SM_BITS 4 17107 #define RXB_ANARXTEST_TESTMUXSELECT_SM_SHIFT 0 17108 17109 17110 /**************************************************************************** 17111 * RxB :: anaRxControl1G 17112 */ 17113 /* RxB :: anaRxControl1G :: fpat_md [15:15] */ 17114 #define RXB_ANARXCONTROL1G_FPAT_MD_MASK 0x8000 17115 #define RXB_ANARXCONTROL1G_FPAT_MD_ALIGN 0 17116 #define RXB_ANARXCONTROL1G_FPAT_MD_BITS 1 17117 #define RXB_ANARXCONTROL1G_FPAT_MD_SHIFT 15 17118 17119 /* RxB :: anaRxControl1G :: pkt_count_en [14:14] */ 17120 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_MASK 0x4000 17121 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN 0 17122 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_BITS 1 17123 #define RXB_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT 14 17124 17125 /* RxB :: anaRxControl1G :: staMuxRegDis [13:13] */ 17126 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_MASK 0x2000 17127 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_ALIGN 0 17128 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_BITS 1 17129 #define RXB_ANARXCONTROL1G_STAMUXREGDIS_SHIFT 13 17130 17131 /* RxB :: anaRxControl1G :: prbs_clr_dis [12:12] */ 17132 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_MASK 0x1000 17133 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN 0 17134 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_BITS 1 17135 #define RXB_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT 12 17136 17137 /* RxB :: anaRxControl1G :: rxd_dec_sel [11:11] */ 17138 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_MASK 0x0800 17139 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN 0 17140 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_BITS 1 17141 #define RXB_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT 11 17142 17143 /* RxB :: anaRxControl1G :: cgbad_tst [10:10] */ 17144 #define RXB_ANARXCONTROL1G_CGBAD_TST_MASK 0x0400 17145 #define RXB_ANARXCONTROL1G_CGBAD_TST_ALIGN 0 17146 #define RXB_ANARXCONTROL1G_CGBAD_TST_BITS 1 17147 #define RXB_ANARXCONTROL1G_CGBAD_TST_SHIFT 10 17148 17149 /* RxB :: anaRxControl1G :: Emon_en [09:09] */ 17150 #define RXB_ANARXCONTROL1G_EMON_EN_MASK 0x0200 17151 #define RXB_ANARXCONTROL1G_EMON_EN_ALIGN 0 17152 #define RXB_ANARXCONTROL1G_EMON_EN_BITS 1 17153 #define RXB_ANARXCONTROL1G_EMON_EN_SHIFT 9 17154 17155 /* RxB :: anaRxControl1G :: prbs_en [08:08] */ 17156 #define RXB_ANARXCONTROL1G_PRBS_EN_MASK 0x0100 17157 #define RXB_ANARXCONTROL1G_PRBS_EN_ALIGN 0 17158 #define RXB_ANARXCONTROL1G_PRBS_EN_BITS 1 17159 #define RXB_ANARXCONTROL1G_PRBS_EN_SHIFT 8 17160 17161 /* RxB :: anaRxControl1G :: cgbad_en [07:07] */ 17162 #define RXB_ANARXCONTROL1G_CGBAD_EN_MASK 0x0080 17163 #define RXB_ANARXCONTROL1G_CGBAD_EN_ALIGN 0 17164 #define RXB_ANARXCONTROL1G_CGBAD_EN_BITS 1 17165 #define RXB_ANARXCONTROL1G_CGBAD_EN_SHIFT 7 17166 17167 /* RxB :: anaRxControl1G :: cstretch [06:06] */ 17168 #define RXB_ANARXCONTROL1G_CSTRETCH_MASK 0x0040 17169 #define RXB_ANARXCONTROL1G_CSTRETCH_ALIGN 0 17170 #define RXB_ANARXCONTROL1G_CSTRETCH_BITS 1 17171 #define RXB_ANARXCONTROL1G_CSTRETCH_SHIFT 6 17172 17173 /* RxB :: anaRxControl1G :: comma_low_byte_SM [05:05] */ 17174 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_MASK 0x0020 17175 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_ALIGN 0 17176 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_BITS 1 17177 #define RXB_ANARXCONTROL1G_COMMA_LOW_BYTE_SM_SHIFT 5 17178 17179 /* RxB :: anaRxControl1G :: comma_byte_adj_en_SM [04:04] */ 17180 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_MASK 0x0010 17181 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_ALIGN 0 17182 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_BITS 1 17183 #define RXB_ANARXCONTROL1G_COMMA_BYTE_ADJ_EN_SM_SHIFT 4 17184 17185 /* RxB :: anaRxControl1G :: reserved0 [03:02] */ 17186 #define RXB_ANARXCONTROL1G_RESERVED0_MASK 0x000c 17187 #define RXB_ANARXCONTROL1G_RESERVED0_ALIGN 0 17188 #define RXB_ANARXCONTROL1G_RESERVED0_BITS 2 17189 #define RXB_ANARXCONTROL1G_RESERVED0_SHIFT 2 17190 17191 /* RxB :: anaRxControl1G :: freq_sel_force [01:01] */ 17192 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK 0x0002 17193 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN 0 17194 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS 1 17195 #define RXB_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT 1 17196 17197 /* RxB :: anaRxControl1G :: freq_sel [00:00] */ 17198 #define RXB_ANARXCONTROL1G_FREQ_SEL_MASK 0x0001 17199 #define RXB_ANARXCONTROL1G_FREQ_SEL_ALIGN 0 17200 #define RXB_ANARXCONTROL1G_FREQ_SEL_BITS 1 17201 #define RXB_ANARXCONTROL1G_FREQ_SEL_SHIFT 0 17202 17203 17204 /**************************************************************************** 17205 * RxB :: anaRxControlPci 17206 */ 17207 /* RxB :: anaRxControlPci :: comma_adj_sync_sel [15:15] */ 17208 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK 0x8000 17209 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN 0 17210 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS 1 17211 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT 15 17212 17213 /* RxB :: anaRxControlPci :: comma_mask_force_r [14:14] */ 17214 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK 0x4000 17215 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN 0 17216 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS 1 17217 #define RXB_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT 14 17218 17219 /* RxB :: anaRxControlPci :: comma_mask_r [13:13] */ 17220 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_MASK 0x2000 17221 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN 0 17222 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_BITS 1 17223 #define RXB_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT 13 17224 17225 /* RxB :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */ 17226 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000 17227 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0 17228 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1 17229 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12 17230 17231 /* RxB :: anaRxControlPci :: sync_status_force_r_SM [11:11] */ 17232 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK 0x0800 17233 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0 17234 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS 1 17235 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11 17236 17237 /* RxB :: anaRxControlPci :: sync_status_force_r [10:10] */ 17238 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK 0x0400 17239 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN 0 17240 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS 1 17241 #define RXB_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT 10 17242 17243 /* RxB :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */ 17244 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200 17245 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0 17246 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1 17247 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9 17248 17249 /* RxB :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */ 17250 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100 17251 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0 17252 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1 17253 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8 17254 17255 /* RxB :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */ 17256 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080 17257 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0 17258 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1 17259 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7 17260 17261 /* RxB :: anaRxControlPci :: comma_adj_en_r [06:06] */ 17262 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK 0x0040 17263 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN 0 17264 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS 1 17265 #define RXB_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT 6 17266 17267 /* RxB :: anaRxControlPci :: link_en_force_SM [05:05] */ 17268 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK 0x0020 17269 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN 0 17270 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS 1 17271 #define RXB_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT 5 17272 17273 /* RxB :: anaRxControlPci :: link_en_r [04:04] */ 17274 #define RXB_ANARXCONTROLPCI_LINK_EN_R_MASK 0x0010 17275 #define RXB_ANARXCONTROLPCI_LINK_EN_R_ALIGN 0 17276 #define RXB_ANARXCONTROLPCI_LINK_EN_R_BITS 1 17277 #define RXB_ANARXCONTROLPCI_LINK_EN_R_SHIFT 4 17278 17279 /* RxB :: anaRxControlPci :: rx_polarity_force_SM [03:03] */ 17280 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK 0x0008 17281 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN 0 17282 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS 1 17283 #define RXB_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT 3 17284 17285 /* RxB :: anaRxControlPci :: rx_polarity_r [02:02] */ 17286 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_MASK 0x0004 17287 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN 0 17288 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_BITS 1 17289 #define RXB_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT 2 17290 17291 /* RxB :: anaRxControlPci :: integ_mode_SM [01:00] */ 17292 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_MASK 0x0003 17293 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN 0 17294 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_BITS 2 17295 #define RXB_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT 0 17296 17297 17298 /**************************************************************************** 17299 * RxB :: anaRxAstatus 17300 */ 17301 /* RxB :: anaRxAstatus :: sigdet [15:15] */ 17302 #define RXB_ANARXASTATUS_SIGDET_MASK 0x8000 17303 #define RXB_ANARXASTATUS_SIGDET_ALIGN 0 17304 #define RXB_ANARXASTATUS_SIGDET_BITS 1 17305 #define RXB_ANARXASTATUS_SIGDET_SHIFT 15 17306 17307 /* RxB :: anaRxAstatus :: rx_pf [14:12] */ 17308 #define RXB_ANARXASTATUS_RX_PF_MASK 0x7000 17309 #define RXB_ANARXASTATUS_RX_PF_ALIGN 0 17310 #define RXB_ANARXASTATUS_RX_PF_BITS 3 17311 #define RXB_ANARXASTATUS_RX_PF_SHIFT 12 17312 17313 /* RxB :: anaRxAstatus :: dfe [11:06] */ 17314 #define RXB_ANARXASTATUS_DFE_MASK 0x0fc0 17315 #define RXB_ANARXASTATUS_DFE_ALIGN 0 17316 #define RXB_ANARXASTATUS_DFE_BITS 6 17317 #define RXB_ANARXASTATUS_DFE_SHIFT 6 17318 17319 /* RxB :: anaRxAstatus :: reserved0 [05:05] */ 17320 #define RXB_ANARXASTATUS_RESERVED0_MASK 0x0020 17321 #define RXB_ANARXASTATUS_RESERVED0_ALIGN 0 17322 #define RXB_ANARXASTATUS_RESERVED0_BITS 1 17323 #define RXB_ANARXASTATUS_RESERVED0_SHIFT 5 17324 17325 /* RxB :: anaRxAstatus :: vga [04:00] */ 17326 #define RXB_ANARXASTATUS_VGA_MASK 0x001f 17327 #define RXB_ANARXASTATUS_VGA_ALIGN 0 17328 #define RXB_ANARXASTATUS_VGA_BITS 5 17329 #define RXB_ANARXASTATUS_VGA_SHIFT 0 17330 17331 17332 /**************************************************************************** 17333 * RxB :: anaRxAControl1 17334 */ 17335 /* RxB :: anaRxAControl1 :: imode_vcm [15:15] */ 17336 #define RXB_ANARXACONTROL1_IMODE_VCM_MASK 0x8000 17337 #define RXB_ANARXACONTROL1_IMODE_VCM_ALIGN 0 17338 #define RXB_ANARXACONTROL1_IMODE_VCM_BITS 1 17339 #define RXB_ANARXACONTROL1_IMODE_VCM_SHIFT 15 17340 17341 /* RxB :: anaRxAControl1 :: imin_vcm [14:14] */ 17342 #define RXB_ANARXACONTROL1_IMIN_VCM_MASK 0x4000 17343 #define RXB_ANARXACONTROL1_IMIN_VCM_ALIGN 0 17344 #define RXB_ANARXACONTROL1_IMIN_VCM_BITS 1 17345 #define RXB_ANARXACONTROL1_IMIN_VCM_SHIFT 14 17346 17347 /* RxB :: anaRxAControl1 :: imax_sigdet [13:13] */ 17348 #define RXB_ANARXACONTROL1_IMAX_SIGDET_MASK 0x2000 17349 #define RXB_ANARXACONTROL1_IMAX_SIGDET_ALIGN 0 17350 #define RXB_ANARXACONTROL1_IMAX_SIGDET_BITS 1 17351 #define RXB_ANARXACONTROL1_IMAX_SIGDET_SHIFT 13 17352 17353 /* RxB :: anaRxAControl1 :: imode_sigdet [12:12] */ 17354 #define RXB_ANARXACONTROL1_IMODE_SIGDET_MASK 0x1000 17355 #define RXB_ANARXACONTROL1_IMODE_SIGDET_ALIGN 0 17356 #define RXB_ANARXACONTROL1_IMODE_SIGDET_BITS 1 17357 #define RXB_ANARXACONTROL1_IMODE_SIGDET_SHIFT 12 17358 17359 /* RxB :: anaRxAControl1 :: imin_sigdet [11:11] */ 17360 #define RXB_ANARXACONTROL1_IMIN_SIGDET_MASK 0x0800 17361 #define RXB_ANARXACONTROL1_IMIN_SIGDET_ALIGN 0 17362 #define RXB_ANARXACONTROL1_IMIN_SIGDET_BITS 1 17363 #define RXB_ANARXACONTROL1_IMIN_SIGDET_SHIFT 11 17364 17365 /* RxB :: anaRxAControl1 :: refh_rx [10:10] */ 17366 #define RXB_ANARXACONTROL1_REFH_RX_MASK 0x0400 17367 #define RXB_ANARXACONTROL1_REFH_RX_ALIGN 0 17368 #define RXB_ANARXACONTROL1_REFH_RX_BITS 1 17369 #define RXB_ANARXACONTROL1_REFH_RX_SHIFT 10 17370 17371 /* RxB :: anaRxAControl1 :: refl_rx [09:09] */ 17372 #define RXB_ANARXACONTROL1_REFL_RX_MASK 0x0200 17373 #define RXB_ANARXACONTROL1_REFL_RX_ALIGN 0 17374 #define RXB_ANARXACONTROL1_REFL_RX_BITS 1 17375 #define RXB_ANARXACONTROL1_REFL_RX_SHIFT 9 17376 17377 /* RxB :: anaRxAControl1 :: tport_en [08:08] */ 17378 #define RXB_ANARXACONTROL1_TPORT_EN_MASK 0x0100 17379 #define RXB_ANARXACONTROL1_TPORT_EN_ALIGN 0 17380 #define RXB_ANARXACONTROL1_TPORT_EN_BITS 1 17381 #define RXB_ANARXACONTROL1_TPORT_EN_SHIFT 8 17382 17383 /* RxB :: anaRxAControl1 :: vddrb_bg [07:07] */ 17384 #define RXB_ANARXACONTROL1_VDDRB_BG_MASK 0x0080 17385 #define RXB_ANARXACONTROL1_VDDRB_BG_ALIGN 0 17386 #define RXB_ANARXACONTROL1_VDDRB_BG_BITS 1 17387 #define RXB_ANARXACONTROL1_VDDRB_BG_SHIFT 7 17388 17389 /* RxB :: anaRxAControl1 :: sig_pwrdn [06:06] */ 17390 #define RXB_ANARXACONTROL1_SIG_PWRDN_MASK 0x0040 17391 #define RXB_ANARXACONTROL1_SIG_PWRDN_ALIGN 0 17392 #define RXB_ANARXACONTROL1_SIG_PWRDN_BITS 1 17393 #define RXB_ANARXACONTROL1_SIG_PWRDN_SHIFT 6 17394 17395 /* RxB :: anaRxAControl1 :: offset_ctrl [05:03] */ 17396 #define RXB_ANARXACONTROL1_OFFSET_CTRL_MASK 0x0038 17397 #define RXB_ANARXACONTROL1_OFFSET_CTRL_ALIGN 0 17398 #define RXB_ANARXACONTROL1_OFFSET_CTRL_BITS 3 17399 #define RXB_ANARXACONTROL1_OFFSET_CTRL_SHIFT 3 17400 17401 /* RxB :: anaRxAControl1 :: offset_sel [02:02] */ 17402 #define RXB_ANARXACONTROL1_OFFSET_SEL_MASK 0x0004 17403 #define RXB_ANARXACONTROL1_OFFSET_SEL_ALIGN 0 17404 #define RXB_ANARXACONTROL1_OFFSET_SEL_BITS 1 17405 #define RXB_ANARXACONTROL1_OFFSET_SEL_SHIFT 2 17406 17407 /* RxB :: anaRxAControl1 :: reserved0 [01:00] */ 17408 #define RXB_ANARXACONTROL1_RESERVED0_MASK 0x0003 17409 #define RXB_ANARXACONTROL1_RESERVED0_ALIGN 0 17410 #define RXB_ANARXACONTROL1_RESERVED0_BITS 2 17411 #define RXB_ANARXACONTROL1_RESERVED0_SHIFT 0 17412 17413 17414 /**************************************************************************** 17415 * RxB :: anaRxAControl2 17416 */ 17417 /* RxB :: anaRxAControl2 :: imax_clkbuf [15:15] */ 17418 #define RXB_ANARXACONTROL2_IMAX_CLKBUF_MASK 0x8000 17419 #define RXB_ANARXACONTROL2_IMAX_CLKBUF_ALIGN 0 17420 #define RXB_ANARXACONTROL2_IMAX_CLKBUF_BITS 1 17421 #define RXB_ANARXACONTROL2_IMAX_CLKBUF_SHIFT 15 17422 17423 /* RxB :: anaRxAControl2 :: imode_clkbuf [14:14] */ 17424 #define RXB_ANARXACONTROL2_IMODE_CLKBUF_MASK 0x4000 17425 #define RXB_ANARXACONTROL2_IMODE_CLKBUF_ALIGN 0 17426 #define RXB_ANARXACONTROL2_IMODE_CLKBUF_BITS 1 17427 #define RXB_ANARXACONTROL2_IMODE_CLKBUF_SHIFT 14 17428 17429 /* RxB :: anaRxAControl2 :: imin_clkbuf [13:13] */ 17430 #define RXB_ANARXACONTROL2_IMIN_CLKBUF_MASK 0x2000 17431 #define RXB_ANARXACONTROL2_IMIN_CLKBUF_ALIGN 0 17432 #define RXB_ANARXACONTROL2_IMIN_CLKBUF_BITS 1 17433 #define RXB_ANARXACONTROL2_IMIN_CLKBUF_SHIFT 13 17434 17435 /* RxB :: anaRxAControl2 :: imax_eqfl [12:12] */ 17436 #define RXB_ANARXACONTROL2_IMAX_EQFL_MASK 0x1000 17437 #define RXB_ANARXACONTROL2_IMAX_EQFL_ALIGN 0 17438 #define RXB_ANARXACONTROL2_IMAX_EQFL_BITS 1 17439 #define RXB_ANARXACONTROL2_IMAX_EQFL_SHIFT 12 17440 17441 /* RxB :: anaRxAControl2 :: imode_eqfl [11:11] */ 17442 #define RXB_ANARXACONTROL2_IMODE_EQFL_MASK 0x0800 17443 #define RXB_ANARXACONTROL2_IMODE_EQFL_ALIGN 0 17444 #define RXB_ANARXACONTROL2_IMODE_EQFL_BITS 1 17445 #define RXB_ANARXACONTROL2_IMODE_EQFL_SHIFT 11 17446 17447 /* RxB :: anaRxAControl2 :: imin_eqfl [10:10] */ 17448 #define RXB_ANARXACONTROL2_IMIN_EQFL_MASK 0x0400 17449 #define RXB_ANARXACONTROL2_IMIN_EQFL_ALIGN 0 17450 #define RXB_ANARXACONTROL2_IMIN_EQFL_BITS 1 17451 #define RXB_ANARXACONTROL2_IMIN_EQFL_SHIFT 10 17452 17453 /* RxB :: anaRxAControl2 :: imax_dfesum [09:09] */ 17454 #define RXB_ANARXACONTROL2_IMAX_DFESUM_MASK 0x0200 17455 #define RXB_ANARXACONTROL2_IMAX_DFESUM_ALIGN 0 17456 #define RXB_ANARXACONTROL2_IMAX_DFESUM_BITS 1 17457 #define RXB_ANARXACONTROL2_IMAX_DFESUM_SHIFT 9 17458 17459 /* RxB :: anaRxAControl2 :: imode_dfesum [08:08] */ 17460 #define RXB_ANARXACONTROL2_IMODE_DFESUM_MASK 0x0100 17461 #define RXB_ANARXACONTROL2_IMODE_DFESUM_ALIGN 0 17462 #define RXB_ANARXACONTROL2_IMODE_DFESUM_BITS 1 17463 #define RXB_ANARXACONTROL2_IMODE_DFESUM_SHIFT 8 17464 17465 /* RxB :: anaRxAControl2 :: imin_dfesum [07:07] */ 17466 #define RXB_ANARXACONTROL2_IMIN_DFESUM_MASK 0x0080 17467 #define RXB_ANARXACONTROL2_IMIN_DFESUM_ALIGN 0 17468 #define RXB_ANARXACONTROL2_IMIN_DFESUM_BITS 1 17469 #define RXB_ANARXACONTROL2_IMIN_DFESUM_SHIFT 7 17470 17471 /* RxB :: anaRxAControl2 :: imax_vga [06:06] */ 17472 #define RXB_ANARXACONTROL2_IMAX_VGA_MASK 0x0040 17473 #define RXB_ANARXACONTROL2_IMAX_VGA_ALIGN 0 17474 #define RXB_ANARXACONTROL2_IMAX_VGA_BITS 1 17475 #define RXB_ANARXACONTROL2_IMAX_VGA_SHIFT 6 17476 17477 /* RxB :: anaRxAControl2 :: imode_vga [05:05] */ 17478 #define RXB_ANARXACONTROL2_IMODE_VGA_MASK 0x0020 17479 #define RXB_ANARXACONTROL2_IMODE_VGA_ALIGN 0 17480 #define RXB_ANARXACONTROL2_IMODE_VGA_BITS 1 17481 #define RXB_ANARXACONTROL2_IMODE_VGA_SHIFT 5 17482 17483 /* RxB :: anaRxAControl2 :: imin_vga [04:04] */ 17484 #define RXB_ANARXACONTROL2_IMIN_VGA_MASK 0x0010 17485 #define RXB_ANARXACONTROL2_IMIN_VGA_ALIGN 0 17486 #define RXB_ANARXACONTROL2_IMIN_VGA_BITS 1 17487 #define RXB_ANARXACONTROL2_IMIN_VGA_SHIFT 4 17488 17489 /* RxB :: anaRxAControl2 :: imax_interp [03:03] */ 17490 #define RXB_ANARXACONTROL2_IMAX_INTERP_MASK 0x0008 17491 #define RXB_ANARXACONTROL2_IMAX_INTERP_ALIGN 0 17492 #define RXB_ANARXACONTROL2_IMAX_INTERP_BITS 1 17493 #define RXB_ANARXACONTROL2_IMAX_INTERP_SHIFT 3 17494 17495 /* RxB :: anaRxAControl2 :: imode_interp [02:02] */ 17496 #define RXB_ANARXACONTROL2_IMODE_INTERP_MASK 0x0004 17497 #define RXB_ANARXACONTROL2_IMODE_INTERP_ALIGN 0 17498 #define RXB_ANARXACONTROL2_IMODE_INTERP_BITS 1 17499 #define RXB_ANARXACONTROL2_IMODE_INTERP_SHIFT 2 17500 17501 /* RxB :: anaRxAControl2 :: imin_interp [01:01] */ 17502 #define RXB_ANARXACONTROL2_IMIN_INTERP_MASK 0x0002 17503 #define RXB_ANARXACONTROL2_IMIN_INTERP_ALIGN 0 17504 #define RXB_ANARXACONTROL2_IMIN_INTERP_BITS 1 17505 #define RXB_ANARXACONTROL2_IMIN_INTERP_SHIFT 1 17506 17507 /* RxB :: anaRxAControl2 :: imax_vcm [00:00] */ 17508 #define RXB_ANARXACONTROL2_IMAX_VCM_MASK 0x0001 17509 #define RXB_ANARXACONTROL2_IMAX_VCM_ALIGN 0 17510 #define RXB_ANARXACONTROL2_IMAX_VCM_BITS 1 17511 #define RXB_ANARXACONTROL2_IMAX_VCM_SHIFT 0 17512 17513 17514 /**************************************************************************** 17515 * RxB :: anaRxAControl3 17516 */ 17517 /* RxB :: anaRxAControl3 :: en_clk16 [15:15] */ 17518 #define RXB_ANARXACONTROL3_EN_CLK16_MASK 0x8000 17519 #define RXB_ANARXACONTROL3_EN_CLK16_ALIGN 0 17520 #define RXB_ANARXACONTROL3_EN_CLK16_BITS 1 17521 #define RXB_ANARXACONTROL3_EN_CLK16_SHIFT 15 17522 17523 /* RxB :: anaRxAControl3 :: pd_ch_p1 [14:14] */ 17524 #define RXB_ANARXACONTROL3_PD_CH_P1_MASK 0x4000 17525 #define RXB_ANARXACONTROL3_PD_CH_P1_ALIGN 0 17526 #define RXB_ANARXACONTROL3_PD_CH_P1_BITS 1 17527 #define RXB_ANARXACONTROL3_PD_CH_P1_SHIFT 14 17528 17529 /* RxB :: anaRxAControl3 :: en_vcctrl [13:13] */ 17530 #define RXB_ANARXACONTROL3_EN_VCCTRL_MASK 0x2000 17531 #define RXB_ANARXACONTROL3_EN_VCCTRL_ALIGN 0 17532 #define RXB_ANARXACONTROL3_EN_VCCTRL_BITS 1 17533 #define RXB_ANARXACONTROL3_EN_VCCTRL_SHIFT 13 17534 17535 /* RxB :: anaRxAControl3 :: en_dfeclk [12:12] */ 17536 #define RXB_ANARXACONTROL3_EN_DFECLK_MASK 0x1000 17537 #define RXB_ANARXACONTROL3_EN_DFECLK_ALIGN 0 17538 #define RXB_ANARXACONTROL3_EN_DFECLK_BITS 1 17539 #define RXB_ANARXACONTROL3_EN_DFECLK_SHIFT 12 17540 17541 /* RxB :: anaRxAControl3 :: en_hgain [11:11] */ 17542 #define RXB_ANARXACONTROL3_EN_HGAIN_MASK 0x0800 17543 #define RXB_ANARXACONTROL3_EN_HGAIN_ALIGN 0 17544 #define RXB_ANARXACONTROL3_EN_HGAIN_BITS 1 17545 #define RXB_ANARXACONTROL3_EN_HGAIN_SHIFT 11 17546 17547 /* RxB :: anaRxAControl3 :: en_dfeckpwr [10:10] */ 17548 #define RXB_ANARXACONTROL3_EN_DFECKPWR_MASK 0x0400 17549 #define RXB_ANARXACONTROL3_EN_DFECKPWR_ALIGN 0 17550 #define RXB_ANARXACONTROL3_EN_DFECKPWR_BITS 1 17551 #define RXB_ANARXACONTROL3_EN_DFECKPWR_SHIFT 10 17552 17553 /* RxB :: anaRxAControl3 :: offset_pd [09:09] */ 17554 #define RXB_ANARXACONTROL3_OFFSET_PD_MASK 0x0200 17555 #define RXB_ANARXACONTROL3_OFFSET_PD_ALIGN 0 17556 #define RXB_ANARXACONTROL3_OFFSET_PD_BITS 1 17557 #define RXB_ANARXACONTROL3_OFFSET_PD_SHIFT 9 17558 17559 /* RxB :: anaRxAControl3 :: imax_dfetap [08:08] */ 17560 #define RXB_ANARXACONTROL3_IMAX_DFETAP_MASK 0x0100 17561 #define RXB_ANARXACONTROL3_IMAX_DFETAP_ALIGN 0 17562 #define RXB_ANARXACONTROL3_IMAX_DFETAP_BITS 1 17563 #define RXB_ANARXACONTROL3_IMAX_DFETAP_SHIFT 8 17564 17565 /* RxB :: anaRxAControl3 :: imode_dfetap [07:07] */ 17566 #define RXB_ANARXACONTROL3_IMODE_DFETAP_MASK 0x0080 17567 #define RXB_ANARXACONTROL3_IMODE_DFETAP_ALIGN 0 17568 #define RXB_ANARXACONTROL3_IMODE_DFETAP_BITS 1 17569 #define RXB_ANARXACONTROL3_IMODE_DFETAP_SHIFT 7 17570 17571 /* RxB :: anaRxAControl3 :: imin_dfetap [06:06] */ 17572 #define RXB_ANARXACONTROL3_IMIN_DFETAP_MASK 0x0040 17573 #define RXB_ANARXACONTROL3_IMIN_DFETAP_ALIGN 0 17574 #define RXB_ANARXACONTROL3_IMIN_DFETAP_BITS 1 17575 #define RXB_ANARXACONTROL3_IMIN_DFETAP_SHIFT 6 17576 17577 /* RxB :: anaRxAControl3 :: imax_slcd2c [05:05] */ 17578 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_MASK 0x0020 17579 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_ALIGN 0 17580 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_BITS 1 17581 #define RXB_ANARXACONTROL3_IMAX_SLCD2C_SHIFT 5 17582 17583 /* RxB :: anaRxAControl3 :: imode_slcd2c [04:04] */ 17584 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_MASK 0x0010 17585 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_ALIGN 0 17586 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_BITS 1 17587 #define RXB_ANARXACONTROL3_IMODE_SLCD2C_SHIFT 4 17588 17589 /* RxB :: anaRxAControl3 :: imin_slcd2c [03:03] */ 17590 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_MASK 0x0008 17591 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_ALIGN 0 17592 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_BITS 1 17593 #define RXB_ANARXACONTROL3_IMIN_SLCD2C_SHIFT 3 17594 17595 /* RxB :: anaRxAControl3 :: imax_dfevref [02:02] */ 17596 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_MASK 0x0004 17597 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_ALIGN 0 17598 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_BITS 1 17599 #define RXB_ANARXACONTROL3_IMAX_DFEVREF_SHIFT 2 17600 17601 /* RxB :: anaRxAControl3 :: imode_dfevref [01:01] */ 17602 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_MASK 0x0002 17603 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_ALIGN 0 17604 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_BITS 1 17605 #define RXB_ANARXACONTROL3_IMODE_DFEVREF_SHIFT 1 17606 17607 /* RxB :: anaRxAControl3 :: imin_dfevref [00:00] */ 17608 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_MASK 0x0001 17609 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_ALIGN 0 17610 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_BITS 1 17611 #define RXB_ANARXACONTROL3_IMIN_DFEVREF_SHIFT 0 17612 17613 17614 /**************************************************************************** 17615 * Hypercore_USER_XgxsBlk2 17616 */ 17617 /**************************************************************************** 17618 * XgxsBlk2 :: rxLnSwap 17619 */ 17620 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_en [15:15] */ 17621 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_MASK 0x8000 17622 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_ALIGN 0 17623 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_BITS 1 17624 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_EN_SHIFT 15 17625 17626 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_force_en [14:14] */ 17627 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_MASK 0x4000 17628 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_ALIGN 0 17629 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_BITS 1 17630 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE_EN_SHIFT 14 17631 17632 /* XgxsBlk2 :: rxLnSwap :: Qset_prog_en [13:13] */ 17633 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_MASK 0x2000 17634 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_ALIGN 0 17635 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_BITS 1 17636 #define XGXSBLK2_RXLNSWAP_QSET_PROG_EN_SHIFT 13 17637 17638 /* XgxsBlk2 :: rxLnSwap :: rx_lnswap_link_en [12:12] */ 17639 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_MASK 0x1000 17640 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_ALIGN 0 17641 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_BITS 1 17642 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_LINK_EN_SHIFT 12 17643 17644 /* XgxsBlk2 :: rxLnSwap :: Q0_msb [11:11] */ 17645 #define XGXSBLK2_RXLNSWAP_Q0_MSB_MASK 0x0800 17646 #define XGXSBLK2_RXLNSWAP_Q0_MSB_ALIGN 0 17647 #define XGXSBLK2_RXLNSWAP_Q0_MSB_BITS 1 17648 #define XGXSBLK2_RXLNSWAP_Q0_MSB_SHIFT 11 17649 17650 /* XgxsBlk2 :: rxLnSwap :: Q1_msb [10:10] */ 17651 #define XGXSBLK2_RXLNSWAP_Q1_MSB_MASK 0x0400 17652 #define XGXSBLK2_RXLNSWAP_Q1_MSB_ALIGN 0 17653 #define XGXSBLK2_RXLNSWAP_Q1_MSB_BITS 1 17654 #define XGXSBLK2_RXLNSWAP_Q1_MSB_SHIFT 10 17655 17656 /* XgxsBlk2 :: rxLnSwap :: Q2_msb [09:09] */ 17657 #define XGXSBLK2_RXLNSWAP_Q2_MSB_MASK 0x0200 17658 #define XGXSBLK2_RXLNSWAP_Q2_MSB_ALIGN 0 17659 #define XGXSBLK2_RXLNSWAP_Q2_MSB_BITS 1 17660 #define XGXSBLK2_RXLNSWAP_Q2_MSB_SHIFT 9 17661 17662 /* XgxsBlk2 :: rxLnSwap :: Q3_msb [08:08] */ 17663 #define XGXSBLK2_RXLNSWAP_Q3_MSB_MASK 0x0100 17664 #define XGXSBLK2_RXLNSWAP_Q3_MSB_ALIGN 0 17665 #define XGXSBLK2_RXLNSWAP_Q3_MSB_BITS 1 17666 #define XGXSBLK2_RXLNSWAP_Q3_MSB_SHIFT 8 17667 17668 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force0 [07:06] */ 17669 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_MASK 0x00c0 17670 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_ALIGN 0 17671 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_BITS 2 17672 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE0_SHIFT 6 17673 17674 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force1 [05:04] */ 17675 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_MASK 0x0030 17676 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_ALIGN 0 17677 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_BITS 2 17678 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE1_SHIFT 4 17679 17680 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force2 [03:02] */ 17681 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_MASK 0x000c 17682 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_ALIGN 0 17683 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_BITS 2 17684 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE2_SHIFT 2 17685 17686 /* XgxsBlk2 :: rxLnSwap :: rx_lnSwap_force3 [01:00] */ 17687 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_MASK 0x0003 17688 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_ALIGN 0 17689 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_BITS 2 17690 #define XGXSBLK2_RXLNSWAP_RX_LNSWAP_FORCE3_SHIFT 0 17691 17692 17693 /**************************************************************************** 17694 * XgxsBlk2 :: txLnSwap 17695 */ 17696 /* XgxsBlk2 :: txLnSwap :: tx_lnswap_en [15:15] */ 17697 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_MASK 0x8000 17698 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_ALIGN 0 17699 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_BITS 1 17700 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_EN_SHIFT 15 17701 17702 /* XgxsBlk2 :: txLnSwap :: reserved0 [14:08] */ 17703 #define XGXSBLK2_TXLNSWAP_RESERVED0_MASK 0x7f00 17704 #define XGXSBLK2_TXLNSWAP_RESERVED0_ALIGN 0 17705 #define XGXSBLK2_TXLNSWAP_RESERVED0_BITS 7 17706 #define XGXSBLK2_TXLNSWAP_RESERVED0_SHIFT 8 17707 17708 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force0 [07:06] */ 17709 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_MASK 0x00c0 17710 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_ALIGN 0 17711 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_BITS 2 17712 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE0_SHIFT 6 17713 17714 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force1 [05:04] */ 17715 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_MASK 0x0030 17716 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_ALIGN 0 17717 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_BITS 2 17718 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE1_SHIFT 4 17719 17720 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force2 [03:02] */ 17721 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_MASK 0x000c 17722 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_ALIGN 0 17723 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_BITS 2 17724 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE2_SHIFT 2 17725 17726 /* XgxsBlk2 :: txLnSwap :: tx_lnSwap_force3 [01:00] */ 17727 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_MASK 0x0003 17728 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_ALIGN 0 17729 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_BITS 2 17730 #define XGXSBLK2_TXLNSWAP_TX_LNSWAP_FORCE3_SHIFT 0 17731 17732 17733 /**************************************************************************** 17734 * XgxsBlk2 :: QsetLns01 17735 */ 17736 /* XgxsBlk2 :: QsetLns01 :: Q1 [15:08] */ 17737 #define XGXSBLK2_QSETLNS01_Q1_MASK 0xff00 17738 #define XGXSBLK2_QSETLNS01_Q1_ALIGN 0 17739 #define XGXSBLK2_QSETLNS01_Q1_BITS 8 17740 #define XGXSBLK2_QSETLNS01_Q1_SHIFT 8 17741 17742 /* XgxsBlk2 :: QsetLns01 :: Q0 [07:00] */ 17743 #define XGXSBLK2_QSETLNS01_Q0_MASK 0x00ff 17744 #define XGXSBLK2_QSETLNS01_Q0_ALIGN 0 17745 #define XGXSBLK2_QSETLNS01_Q0_BITS 8 17746 #define XGXSBLK2_QSETLNS01_Q0_SHIFT 0 17747 17748 17749 /**************************************************************************** 17750 * XgxsBlk2 :: QsetLns23 17751 */ 17752 /* XgxsBlk2 :: QsetLns23 :: Q3 [15:08] */ 17753 #define XGXSBLK2_QSETLNS23_Q3_MASK 0xff00 17754 #define XGXSBLK2_QSETLNS23_Q3_ALIGN 0 17755 #define XGXSBLK2_QSETLNS23_Q3_BITS 8 17756 #define XGXSBLK2_QSETLNS23_Q3_SHIFT 8 17757 17758 /* XgxsBlk2 :: QsetLns23 :: Q2 [07:00] */ 17759 #define XGXSBLK2_QSETLNS23_Q2_MASK 0x00ff 17760 #define XGXSBLK2_QSETLNS23_Q2_ALIGN 0 17761 #define XGXSBLK2_QSETLNS23_Q2_BITS 8 17762 #define XGXSBLK2_QSETLNS23_Q2_SHIFT 0 17763 17764 17765 /**************************************************************************** 17766 * XgxsBlk2 :: unicoreMode10g 17767 */ 17768 /* XgxsBlk2 :: unicoreMode10g :: reserved0 [15:08] */ 17769 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_MASK 0xff00 17770 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_ALIGN 0 17771 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_BITS 8 17772 #define XGXSBLK2_UNICOREMODE10G_RESERVED0_SHIFT 8 17773 17774 /* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gHiG [07:04] */ 17775 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_MASK 0x00f0 17776 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ALIGN 0 17777 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_BITS 4 17778 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_SHIFT 4 17779 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS 0 17780 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXG_nCC 1 17781 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_IndLane_OS5 5 17782 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_Indlanes 6 17783 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PCI 7 17784 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQ 8 17785 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_XGXS_nLQnCC 9 17786 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PBypass 10 17787 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_PBypass_nDSK 11 17788 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_ComboCoreMode 12 17789 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GHIG_Clocks_off 15 17790 17791 /* XgxsBlk2 :: unicoreMode10g :: unicoreMode10gCx4 [03:00] */ 17792 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_MASK 0x000f 17793 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ALIGN 0 17794 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_BITS 4 17795 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_SHIFT 0 17796 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS 0 17797 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXG_nCC 1 17798 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_IndLane_OS5 5 17799 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_Indlanes 6 17800 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PCI 7 17801 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS_nLQ 8 17802 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_XGXS_nLQnCC 9 17803 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PBypass 10 17804 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_PBypass_nDSK 11 17805 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_ComboCoreMode 12 17806 #define XGXSBLK2_UNICOREMODE10G_UNICOREMODE10GCX4_Clocks_off 15 17807 17808 17809 /**************************************************************************** 17810 * XgxsBlk2 :: indCombCtrl 17811 */ 17812 /* XgxsBlk2 :: indCombCtrl :: reserved0 [15:02] */ 17813 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_MASK 0xfffc 17814 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_ALIGN 0 17815 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_BITS 14 17816 #define XGXSBLK2_INDCOMBCTRL_RESERVED0_SHIFT 2 17817 17818 /* XgxsBlk2 :: indCombCtrl :: masterLn_indx [01:00] */ 17819 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_MASK 0x0003 17820 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_ALIGN 0 17821 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_BITS 2 17822 #define XGXSBLK2_INDCOMBCTRL_MASTERLN_INDX_SHIFT 0 17823 17824 17825 /**************************************************************************** 17826 * XgxsBlk2 :: TestModeLane 17827 */ 17828 /* XgxsBlk2 :: TestModeLane :: reserved0 [15:02] */ 17829 #define XGXSBLK2_TESTMODELANE_RESERVED0_MASK 0xfffc 17830 #define XGXSBLK2_TESTMODELANE_RESERVED0_ALIGN 0 17831 #define XGXSBLK2_TESTMODELANE_RESERVED0_BITS 14 17832 #define XGXSBLK2_TESTMODELANE_RESERVED0_SHIFT 2 17833 17834 /* XgxsBlk2 :: TestModeLane :: slice_selector [01:00] */ 17835 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_MASK 0x0003 17836 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_ALIGN 0 17837 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_BITS 2 17838 #define XGXSBLK2_TESTMODELANE_SLICE_SELECTOR_SHIFT 0 17839 17840 17841 /**************************************************************************** 17842 * XgxsBlk2 :: TestModeCombo 17843 */ 17844 /* XgxsBlk2 :: TestModeCombo :: reserved0 [15:12] */ 17845 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_MASK 0xf000 17846 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_ALIGN 0 17847 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_BITS 4 17848 #define XGXSBLK2_TESTMODECOMBO_RESERVED0_SHIFT 12 17849 17850 /* XgxsBlk2 :: TestModeCombo :: test_monitor_mode2 [11:06] */ 17851 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_MASK 0x0fc0 17852 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_ALIGN 0 17853 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_BITS 6 17854 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_SHIFT 6 17855 17856 /* XgxsBlk2 :: TestModeCombo :: test_monitor_mode1 [05:00] */ 17857 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_MASK 0x003f 17858 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_ALIGN 0 17859 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_BITS 6 17860 #define XGXSBLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_SHIFT 0 17861 17862 17863 /**************************************************************************** 17864 * XgxsBlk2 :: TestModeMux 17865 */ 17866 /* XgxsBlk2 :: TestModeMux :: reserved0 [15:04] */ 17867 #define XGXSBLK2_TESTMODEMUX_RESERVED0_MASK 0xfff0 17868 #define XGXSBLK2_TESTMODEMUX_RESERVED0_ALIGN 0 17869 #define XGXSBLK2_TESTMODEMUX_RESERVED0_BITS 12 17870 #define XGXSBLK2_TESTMODEMUX_RESERVED0_SHIFT 4 17871 17872 /* XgxsBlk2 :: TestModeMux :: tmux_sel [03:01] */ 17873 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_MASK 0x000e 17874 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_ALIGN 0 17875 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_BITS 3 17876 #define XGXSBLK2_TESTMODEMUX_TMUX_SEL_SHIFT 1 17877 17878 /* XgxsBlk2 :: TestModeMux :: tmux_en [00:00] */ 17879 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_MASK 0x0001 17880 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_ALIGN 0 17881 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_BITS 1 17882 #define XGXSBLK2_TESTMODEMUX_TMUX_EN_SHIFT 0 17883 17884 17885 /**************************************************************************** 17886 * XgxsBlk2 :: cx4SigdetCnt 17887 */ 17888 /* XgxsBlk2 :: cx4SigdetCnt :: cx4SigdetCnt [15:00] */ 17889 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_MASK 0xffff 17890 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_ALIGN 0 17891 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_BITS 16 17892 #define XGXSBLK2_CX4SIGDETCNT_CX4SIGDETCNT_SHIFT 0 17893 17894 17895 /**************************************************************************** 17896 * XgxsBlk2 :: laneReset 17897 */ 17898 /* XgxsBlk2 :: laneReset :: reset_mdio [15:15] */ 17899 #define XGXSBLK2_LANERESET_RESET_MDIO_MASK 0x8000 17900 #define XGXSBLK2_LANERESET_RESET_MDIO_ALIGN 0 17901 #define XGXSBLK2_LANERESET_RESET_MDIO_BITS 1 17902 #define XGXSBLK2_LANERESET_RESET_MDIO_SHIFT 15 17903 17904 /* XgxsBlk2 :: laneReset :: reserved0 [14:09] */ 17905 #define XGXSBLK2_LANERESET_RESERVED0_MASK 0x7e00 17906 #define XGXSBLK2_LANERESET_RESERVED0_ALIGN 0 17907 #define XGXSBLK2_LANERESET_RESERVED0_BITS 6 17908 #define XGXSBLK2_LANERESET_RESERVED0_SHIFT 9 17909 17910 /* XgxsBlk2 :: laneReset :: reset_pll [08:08] */ 17911 #define XGXSBLK2_LANERESET_RESET_PLL_MASK 0x0100 17912 #define XGXSBLK2_LANERESET_RESET_PLL_ALIGN 0 17913 #define XGXSBLK2_LANERESET_RESET_PLL_BITS 1 17914 #define XGXSBLK2_LANERESET_RESET_PLL_SHIFT 8 17915 17916 /* XgxsBlk2 :: laneReset :: reset_tx [07:04] */ 17917 #define XGXSBLK2_LANERESET_RESET_TX_MASK 0x00f0 17918 #define XGXSBLK2_LANERESET_RESET_TX_ALIGN 0 17919 #define XGXSBLK2_LANERESET_RESET_TX_BITS 4 17920 #define XGXSBLK2_LANERESET_RESET_TX_SHIFT 4 17921 17922 /* XgxsBlk2 :: laneReset :: reset_rx [03:00] */ 17923 #define XGXSBLK2_LANERESET_RESET_RX_MASK 0x000f 17924 #define XGXSBLK2_LANERESET_RESET_RX_ALIGN 0 17925 #define XGXSBLK2_LANERESET_RESET_RX_BITS 4 17926 #define XGXSBLK2_LANERESET_RESET_RX_SHIFT 0 17927 17928 17929 /**************************************************************************** 17930 * XgxsBlk2 :: xgxsStatus6 17931 */ 17932 /* XgxsBlk2 :: xgxsStatus6 :: reserved0 [15:11] */ 17933 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_MASK 0xf800 17934 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_ALIGN 0 17935 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_BITS 5 17936 #define XGXSBLK2_XGXSSTATUS6_RESERVED0_SHIFT 11 17937 17938 /* XgxsBlk2 :: xgxsStatus6 :: hcd_over_1g [10:00] */ 17939 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_MASK 0x07ff 17940 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_ALIGN 0 17941 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_BITS 11 17942 #define XGXSBLK2_XGXSSTATUS6_HCD_OVER_1G_SHIFT 0 17943 17944 17945 /**************************************************************************** 17946 * XgxsBlk2 :: cl73Control7 17947 */ 17948 /* XgxsBlk2 :: cl73Control7 :: cl73_an_switch_cntL [15:00] */ 17949 #define XGXSBLK2_CL73CONTROL7_CL73_AN_SWITCH_CNTL_MASK 0xffff 17950 #define XGXSBLK2_CL73CONTROL7_CL73_AN_SWITCH_CNTL_ALIGN 0 17951 #define XGXSBLK2_CL73CONTROL7_CL73_AN_SWITCH_CNTL_BITS 16 17952 #define XGXSBLK2_CL73CONTROL7_CL73_AN_SWITCH_CNTL_SHIFT 0 17953 17954 17955 /**************************************************************************** 17956 * XgxsBlk2 :: cl73Control8 17957 */ 17958 /* XgxsBlk2 :: cl73Control8 :: reserved0 [15:08] */ 17959 #define XGXSBLK2_CL73CONTROL8_RESERVED0_MASK 0xff00 17960 #define XGXSBLK2_CL73CONTROL8_RESERVED0_ALIGN 0 17961 #define XGXSBLK2_CL73CONTROL8_RESERVED0_BITS 8 17962 #define XGXSBLK2_CL73CONTROL8_RESERVED0_SHIFT 8 17963 17964 /* XgxsBlk2 :: cl73Control8 :: cl73_an_switch_cntH [07:00] */ 17965 #define XGXSBLK2_CL73CONTROL8_CL73_AN_SWITCH_CNTH_MASK 0x00ff 17966 #define XGXSBLK2_CL73CONTROL8_CL73_AN_SWITCH_CNTH_ALIGN 0 17967 #define XGXSBLK2_CL73CONTROL8_CL73_AN_SWITCH_CNTH_BITS 8 17968 #define XGXSBLK2_CL73CONTROL8_CL73_AN_SWITCH_CNTH_SHIFT 0 17969 17970 17971 /**************************************************************************** 17972 * Hypercore_USER_XgxsBlk3 17973 */ 17974 /**************************************************************************** 17975 * XgxsBlk3 :: localStatus 17976 */ 17977 /* XgxsBlk3 :: localStatus :: reserved0 [15:03] */ 17978 #define XGXSBLK3_LOCALSTATUS_RESERVED0_MASK 0xfff8 17979 #define XGXSBLK3_LOCALSTATUS_RESERVED0_ALIGN 0 17980 #define XGXSBLK3_LOCALSTATUS_RESERVED0_BITS 13 17981 #define XGXSBLK3_LOCALSTATUS_RESERVED0_SHIFT 3 17982 17983 /* XgxsBlk3 :: localStatus :: localIACRdy [02:02] */ 17984 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_MASK 0x0004 17985 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_ALIGN 0 17986 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_BITS 1 17987 #define XGXSBLK3_LOCALSTATUS_LOCALIACRDY_SHIFT 2 17988 17989 /* XgxsBlk3 :: localStatus :: localRdDataRdy [01:01] */ 17990 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_MASK 0x0002 17991 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_ALIGN 0 17992 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_BITS 1 17993 #define XGXSBLK3_LOCALSTATUS_LOCALRDDATARDY_SHIFT 1 17994 17995 /* XgxsBlk3 :: localStatus :: localMdioEn [00:00] */ 17996 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_MASK 0x0001 17997 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_ALIGN 0 17998 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_BITS 1 17999 #define XGXSBLK3_LOCALSTATUS_LOCALMDIOEN_SHIFT 0 18000 18001 18002 /**************************************************************************** 18003 * XgxsBlk3 :: localControl0 18004 */ 18005 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln3_msb [15:15] */ 18006 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_MASK 0x8000 18007 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_ALIGN 0 18008 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_BITS 1 18009 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN3_MSB_SHIFT 15 18010 18011 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln2_msb [14:14] */ 18012 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_MASK 0x4000 18013 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_ALIGN 0 18014 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_BITS 1 18015 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN2_MSB_SHIFT 14 18016 18017 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln1_msb [13:13] */ 18018 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_MASK 0x2000 18019 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_ALIGN 0 18020 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_BITS 1 18021 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN1_MSB_SHIFT 13 18022 18023 /* XgxsBlk3 :: localControl0 :: remoteWrite_ln0_msb [12:12] */ 18024 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_MASK 0x1000 18025 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_ALIGN 0 18026 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_BITS 1 18027 #define XGXSBLK3_LOCALCONTROL0_REMOTEWRITE_LN0_MSB_SHIFT 12 18028 18029 /* XgxsBlk3 :: localControl0 :: reserved0 [11:08] */ 18030 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_MASK 0x0f00 18031 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_ALIGN 0 18032 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_BITS 4 18033 #define XGXSBLK3_LOCALCONTROL0_RESERVED0_SHIFT 8 18034 18035 /* XgxsBlk3 :: localControl0 :: Q0_DetDis [07:07] */ 18036 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_MASK 0x0080 18037 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_ALIGN 0 18038 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_BITS 1 18039 #define XGXSBLK3_LOCALCONTROL0_Q0_DETDIS_SHIFT 7 18040 18041 /* XgxsBlk3 :: localControl0 :: remoteMdioPassThru [06:06] */ 18042 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_MASK 0x0040 18043 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_ALIGN 0 18044 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_BITS 1 18045 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOPASSTHRU_SHIFT 6 18046 18047 /* XgxsBlk3 :: localControl0 :: remoteMdioEndPnt [05:05] */ 18048 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_MASK 0x0020 18049 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_ALIGN 0 18050 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_BITS 1 18051 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOENDPNT_SHIFT 5 18052 18053 /* XgxsBlk3 :: localControl0 :: extRemoteMdioEn [04:04] */ 18054 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_MASK 0x0010 18055 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_ALIGN 0 18056 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_BITS 1 18057 #define XGXSBLK3_LOCALCONTROL0_EXTREMOTEMDIOEN_SHIFT 4 18058 18059 /* XgxsBlk3 :: localControl0 :: rx_inBandMdio_rst [03:03] */ 18060 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_MASK 0x0008 18061 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_ALIGN 0 18062 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_BITS 1 18063 #define XGXSBLK3_LOCALCONTROL0_RX_INBANDMDIO_RST_SHIFT 3 18064 18065 /* XgxsBlk3 :: localControl0 :: tx_inBandMdio_rst [02:02] */ 18066 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_MASK 0x0004 18067 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_ALIGN 0 18068 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_BITS 1 18069 #define XGXSBLK3_LOCALCONTROL0_TX_INBANDMDIO_RST_SHIFT 2 18070 18071 /* XgxsBlk3 :: localControl0 :: localWriteReq [01:01] */ 18072 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_MASK 0x0002 18073 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_ALIGN 0 18074 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_BITS 1 18075 #define XGXSBLK3_LOCALCONTROL0_LOCALWRITEREQ_SHIFT 1 18076 18077 /* XgxsBlk3 :: localControl0 :: remoteMdioEn_reg [00:00] */ 18078 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_MASK 0x0001 18079 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_ALIGN 0 18080 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_BITS 1 18081 #define XGXSBLK3_LOCALCONTROL0_REMOTEMDIOEN_REG_SHIFT 0 18082 18083 18084 /**************************************************************************** 18085 * XgxsBlk3 :: localControl1 18086 */ 18087 /* XgxsBlk3 :: localControl1 :: rx_inBandMdio_Q0 [15:08] */ 18088 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_MASK 0xff00 18089 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_ALIGN 0 18090 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_BITS 8 18091 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIO_Q0_SHIFT 8 18092 18093 /* XgxsBlk3 :: localControl1 :: reserved0 [07:04] */ 18094 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_MASK 0x00f0 18095 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_ALIGN 0 18096 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_BITS 4 18097 #define XGXSBLK3_LOCALCONTROL1_RESERVED0_SHIFT 4 18098 18099 /* XgxsBlk3 :: localControl1 :: localRemoteErrorClr [03:03] */ 18100 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_MASK 0x0008 18101 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_ALIGN 0 18102 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_BITS 1 18103 #define XGXSBLK3_LOCALCONTROL1_LOCALREMOTEERRORCLR_SHIFT 3 18104 18105 /* XgxsBlk3 :: localControl1 :: rx_inBandMdioStatSel [02:00] */ 18106 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_MASK 0x0007 18107 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_ALIGN 0 18108 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_BITS 3 18109 #define XGXSBLK3_LOCALCONTROL1_RX_INBANDMDIOSTATSEL_SHIFT 0 18110 18111 18112 /**************************************************************************** 18113 * XgxsBlk3 :: remoteWrite03 18114 */ 18115 /* XgxsBlk3 :: remoteWrite03 :: localWrite_ln0_lsb [15:08] */ 18116 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_MASK 0xff00 18117 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_ALIGN 0 18118 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_BITS 8 18119 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN0_LSB_SHIFT 8 18120 18121 /* XgxsBlk3 :: remoteWrite03 :: localWrite_ln3_lsb [07:00] */ 18122 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_MASK 0x00ff 18123 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_ALIGN 0 18124 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_BITS 8 18125 #define XGXSBLK3_REMOTEWRITE03_LOCALWRITE_LN3_LSB_SHIFT 0 18126 18127 18128 /**************************************************************************** 18129 * XgxsBlk3 :: remoteWrite12 18130 */ 18131 /* XgxsBlk3 :: remoteWrite12 :: localWrite_ln1_lsb [15:08] */ 18132 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_MASK 0xff00 18133 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_ALIGN 0 18134 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_BITS 8 18135 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN1_LSB_SHIFT 8 18136 18137 /* XgxsBlk3 :: remoteWrite12 :: localWrite_ln2_lsb [07:00] */ 18138 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_MASK 0x00ff 18139 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_ALIGN 0 18140 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_BITS 8 18141 #define XGXSBLK3_REMOTEWRITE12_LOCALWRITE_LN2_LSB_SHIFT 0 18142 18143 18144 /**************************************************************************** 18145 * XgxsBlk3 :: remoteRead12 18146 */ 18147 /* XgxsBlk3 :: remoteRead12 :: localRdData [15:00] */ 18148 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_MASK 0xffff 18149 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_ALIGN 0 18150 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_BITS 16 18151 #define XGXSBLK3_REMOTEREAD12_LOCALRDDATA_SHIFT 0 18152 18153 18154 /**************************************************************************** 18155 * XgxsBlk3 :: remoteReadx3 18156 */ 18157 /* XgxsBlk3 :: remoteReadx3 :: reserved0 [15:08] */ 18158 #define XGXSBLK3_REMOTEREADX3_RESERVED0_MASK 0xff00 18159 #define XGXSBLK3_REMOTEREADX3_RESERVED0_ALIGN 0 18160 #define XGXSBLK3_REMOTEREADX3_RESERVED0_BITS 8 18161 #define XGXSBLK3_REMOTEREADX3_RESERVED0_SHIFT 8 18162 18163 /* XgxsBlk3 :: remoteReadx3 :: localRdDataId [07:00] */ 18164 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_MASK 0x00ff 18165 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_ALIGN 0 18166 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_BITS 8 18167 #define XGXSBLK3_REMOTEREADX3_LOCALRDDATAID_SHIFT 0 18168 18169 18170 /**************************************************************************** 18171 * XgxsBlk3 :: rx_inBandMdioStat 18172 */ 18173 /* union - case remoteStatus [15:00] */ 18174 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteStatus [15:00] */ 18175 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_MASK 0xffff 18176 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_ALIGN 0 18177 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_BITS 16 18178 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTESTATUS_REMOTESTATUS_SHIFT 0 18179 18180 18181 /* union - case remoteControl [15:00] */ 18182 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteControl [15:00] */ 18183 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_MASK 0xffff 18184 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_ALIGN 0 18185 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_BITS 16 18186 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTECONTROL_REMOTECONTROL_SHIFT 0 18187 18188 18189 /* union - case remoteAddr [15:00] */ 18190 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteAddr [15:00] */ 18191 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_MASK 0xffff 18192 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_ALIGN 0 18193 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_BITS 16 18194 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEADDR_REMOTEADDR_SHIFT 0 18195 18196 18197 /* union - case remoteWrtData [15:00] */ 18198 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteWrtData [15:00] */ 18199 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_MASK 0xffff 18200 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_ALIGN 0 18201 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_BITS 16 18202 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEWRTDATA_REMOTEWRTDATA_SHIFT 0 18203 18204 18205 /* union - case remoteIACn_sel [15:00] */ 18206 /* XgxsBlk3 :: rx_inBandMdioStat :: reserved0 [15:08] */ 18207 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_MASK 0xff00 18208 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_ALIGN 0 18209 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_BITS 8 18210 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_RESERVED0_SHIFT 8 18211 18212 /* XgxsBlk3 :: rx_inBandMdioStat :: remoteIACn [07:00] */ 18213 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_MASK 0x00ff 18214 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_ALIGN 0 18215 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_BITS 8 18216 #define XGXSBLK3_RX_INBANDMDIOSTAT_REMOTEIACN_SEL_REMOTEIACN_SHIFT 0 18217 18218 18219 /* union - case rx_inBandTestBus [15:00] */ 18220 /* XgxsBlk3 :: rx_inBandMdioStat :: rx_inBandTestBus [15:00] */ 18221 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_MASK 0xffff 18222 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_ALIGN 0 18223 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_BITS 16 18224 #define XGXSBLK3_RX_INBANDMDIOSTAT_RX_INBANDTESTBUS_RX_INBANDTESTBUS_SHIFT 0 18225 18226 18227 /* union - case StatusOff [15:00] */ 18228 /* XgxsBlk3 :: rx_inBandMdioStat :: reserved0 [15:00] */ 18229 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_MASK 0xffff 18230 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_ALIGN 0 18231 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_BITS 16 18232 #define XGXSBLK3_RX_INBANDMDIOSTAT_STATUSOFF_RESERVED0_SHIFT 0 18233 18234 18235 18236 /**************************************************************************** 18237 * XgxsBlk3 :: localIAC 18238 */ 18239 /* XgxsBlk3 :: localIAC :: IAC_ln1_ln2 [15:08] */ 18240 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_MASK 0xff00 18241 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_ALIGN 0 18242 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_BITS 8 18243 #define XGXSBLK3_LOCALIAC_IAC_LN1_LN2_SHIFT 8 18244 18245 /* XgxsBlk3 :: localIAC :: reserved0 [07:01] */ 18246 #define XGXSBLK3_LOCALIAC_RESERVED0_MASK 0x00fe 18247 #define XGXSBLK3_LOCALIAC_RESERVED0_ALIGN 0 18248 #define XGXSBLK3_LOCALIAC_RESERVED0_BITS 7 18249 #define XGXSBLK3_LOCALIAC_RESERVED0_SHIFT 1 18250 18251 /* XgxsBlk3 :: localIAC :: localIACReq [00:00] */ 18252 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_MASK 0x0001 18253 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_ALIGN 0 18254 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_BITS 1 18255 #define XGXSBLK3_LOCALIAC_LOCALIACREQ_SHIFT 0 18256 18257 18258 /**************************************************************************** 18259 * XgxsBlk3 :: remoteIACn 18260 */ 18261 /* XgxsBlk3 :: remoteIACn :: reserved0 [15:08] */ 18262 #define XGXSBLK3_REMOTEIACN_RESERVED0_MASK 0xff00 18263 #define XGXSBLK3_REMOTEIACN_RESERVED0_ALIGN 0 18264 #define XGXSBLK3_REMOTEIACN_RESERVED0_BITS 8 18265 #define XGXSBLK3_REMOTEIACN_RESERVED0_SHIFT 8 18266 18267 /* XgxsBlk3 :: remoteIACn :: localIACn [07:00] */ 18268 #define XGXSBLK3_REMOTEIACN_LOCALIACN_MASK 0x00ff 18269 #define XGXSBLK3_REMOTEIACN_LOCALIACN_ALIGN 0 18270 #define XGXSBLK3_REMOTEIACN_LOCALIACN_BITS 8 18271 #define XGXSBLK3_REMOTEIACN_LOCALIACN_SHIFT 0 18272 18273 18274 /**************************************************************************** 18275 * Hypercore_USER_GP_Status 18276 */ 18277 /**************************************************************************** 18278 * GP_Status :: MiscRxStatus 18279 */ 18280 /* union - case statusSelect0 [15:00] */ 18281 /* GP_Status :: MiscRxStatus :: capture_NP_lh [15:15] */ 18282 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK 0x8000 18283 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN 0 18284 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS 1 18285 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT 15 18286 18287 /* GP_Status :: MiscRxStatus :: teton_brk_link_lh [14:14] */ 18288 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000 18289 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0 18290 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1 18291 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14 18292 18293 /* GP_Status :: MiscRxStatus :: UP3_lh [13:13] */ 18294 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK 0x2000 18295 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN 0 18296 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS 1 18297 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT 13 18298 18299 /* GP_Status :: MiscRxStatus :: MP5_lh [12:12] */ 18300 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK 0x1000 18301 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN 0 18302 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS 1 18303 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT 12 18304 18305 /* GP_Status :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */ 18306 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800 18307 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0 18308 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1 18309 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11 18310 18311 /* GP_Status :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */ 18312 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400 18313 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0 18314 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1 18315 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10 18316 18317 /* GP_Status :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */ 18318 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200 18319 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0 18320 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1 18321 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9 18322 18323 /* GP_Status :: MiscRxStatus :: invalidSeq_lh [08:08] */ 18324 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK 0x0100 18325 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN 0 18326 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS 1 18327 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT 8 18328 18329 /* GP_Status :: MiscRxStatus :: nullMP_lh [07:07] */ 18330 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK 0x0080 18331 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN 0 18332 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS 1 18333 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT 7 18334 18335 /* GP_Status :: MiscRxStatus :: remotePhyMP_lh [06:06] */ 18336 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK 0x0040 18337 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN 0 18338 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS 1 18339 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT 6 18340 18341 /* GP_Status :: MiscRxStatus :: nonMatchingMP_lh [05:05] */ 18342 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020 18343 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0 18344 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1 18345 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5 18346 18347 /* GP_Status :: MiscRxStatus :: over1gMP_lh [04:04] */ 18348 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK 0x0010 18349 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN 0 18350 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS 1 18351 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT 4 18352 18353 /* GP_Status :: MiscRxStatus :: rx_config_is_0_lh [03:03] */ 18354 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008 18355 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0 18356 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1 18357 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3 18358 18359 /* GP_Status :: MiscRxStatus :: np_toggle_err_lh [02:02] */ 18360 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004 18361 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0 18362 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1 18363 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2 18364 18365 /* GP_Status :: MiscRxStatus :: mr_np_lh [01:01] */ 18366 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK 0x0002 18367 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN 0 18368 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS 1 18369 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT 1 18370 18371 /* GP_Status :: MiscRxStatus :: mr_bp_lh [00:00] */ 18372 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK 0x0001 18373 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN 0 18374 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS 1 18375 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT 0 18376 18377 18378 /* union - case statusSelect1 [15:00] */ 18379 /* GP_Status :: MiscRxStatus :: reserved0 [15:04] */ 18380 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK 0xfff0 18381 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN 0 18382 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS 12 18383 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT 4 18384 18385 /* GP_Status :: MiscRxStatus :: np_count [03:00] */ 18386 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK 0x000f 18387 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN 0 18388 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS 4 18389 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT 0 18390 18391 18392 /* union - case statusSelect2 [15:00] */ 18393 /* GP_Status :: MiscRxStatus :: reserved0 [15:06] */ 18394 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK 0xffc0 18395 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN 0 18396 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS 10 18397 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT 6 18398 18399 /* GP_Status :: MiscRxStatus :: remote_phy_enable [05:05] */ 18400 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020 18401 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0 18402 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1 18403 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5 18404 18405 /* GP_Status :: MiscRxStatus :: det_teton_mode [04:04] */ 18406 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK 0x0010 18407 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN 0 18408 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS 1 18409 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT 4 18410 18411 /* GP_Status :: MiscRxStatus :: cu_linkdown [03:03] */ 18412 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK 0x0008 18413 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN 0 18414 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS 1 18415 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT 3 18416 18417 /* GP_Status :: MiscRxStatus :: cu_resolution_error [02:02] */ 18418 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004 18419 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0 18420 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1 18421 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2 18422 18423 /* GP_Status :: MiscRxStatus :: remotePhy_autosel [01:01] */ 18424 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002 18425 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0 18426 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1 18427 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1 18428 18429 /* GP_Status :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */ 18430 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001 18431 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0 18432 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1 18433 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0 18434 18435 18436 /* union - case statusSelect3 [15:00] */ 18437 /* GP_Status :: MiscRxStatus :: reserved0 [15:06] */ 18438 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_RESERVED0_MASK 0xffc0 18439 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_RESERVED0_ALIGN 0 18440 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_RESERVED0_BITS 10 18441 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_RESERVED0_SHIFT 6 18442 18443 /* GP_Status :: MiscRxStatus :: sgmii_selector_mismatch [05:05] */ 18444 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_MASK 0x0020 18445 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_ALIGN 0 18446 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_BITS 1 18447 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_SHIFT 5 18448 18449 /* GP_Status :: MiscRxStatus :: autoneg_enable_ov [04:04] */ 18450 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_MASK 0x0010 18451 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_ALIGN 0 18452 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_BITS 1 18453 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_SHIFT 4 18454 18455 /* GP_Status :: MiscRxStatus :: s_mr_an_enable [03:03] */ 18456 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_MASK 0x0008 18457 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_ALIGN 0 18458 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_BITS 1 18459 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_SHIFT 3 18460 18461 /* GP_Status :: MiscRxStatus :: s_cl73_rslv_KX4 [02:02] */ 18462 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_MASK 0x0004 18463 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_ALIGN 0 18464 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_BITS 1 18465 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_SHIFT 2 18466 18467 /* GP_Status :: MiscRxStatus :: s_cl73_rslv_KX [01:01] */ 18468 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_MASK 0x0002 18469 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_ALIGN 0 18470 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_BITS 1 18471 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_SHIFT 1 18472 18473 /* GP_Status :: MiscRxStatus :: KX_detect [00:00] */ 18474 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_MASK 0x0001 18475 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_ALIGN 0 18476 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_BITS 1 18477 #define GP_STATUS_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_SHIFT 0 18478 18479 18480 18481 /**************************************************************************** 18482 * GP_Status :: xgxsStatus0 18483 */ 18484 /* GP_Status :: xgxsStatus0 :: status_en [15:15] */ 18485 #define GP_STATUS_XGXSSTATUS0_STATUS_EN_MASK 0x8000 18486 #define GP_STATUS_XGXSSTATUS0_STATUS_EN_ALIGN 0 18487 #define GP_STATUS_XGXSSTATUS0_STATUS_EN_BITS 1 18488 #define GP_STATUS_XGXSSTATUS0_STATUS_EN_SHIFT 15 18489 18490 /* GP_Status :: xgxsStatus0 :: reserved0 [14:14] */ 18491 #define GP_STATUS_XGXSSTATUS0_RESERVED0_MASK 0x4000 18492 #define GP_STATUS_XGXSSTATUS0_RESERVED0_ALIGN 0 18493 #define GP_STATUS_XGXSSTATUS0_RESERVED0_BITS 1 18494 #define GP_STATUS_XGXSSTATUS0_RESERVED0_SHIFT 14 18495 18496 /* GP_Status :: xgxsStatus0 :: tx_remote_fault [13:13] */ 18497 #define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_MASK 0x2000 18498 #define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_ALIGN 0 18499 #define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_BITS 1 18500 #define GP_STATUS_XGXSSTATUS0_TX_REMOTE_FAULT_SHIFT 13 18501 18502 /* GP_Status :: xgxsStatus0 :: rx_remote_fault [12:12] */ 18503 #define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_MASK 0x1000 18504 #define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_ALIGN 0 18505 #define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_BITS 1 18506 #define GP_STATUS_XGXSSTATUS0_RX_REMOTE_FAULT_SHIFT 12 18507 18508 /* GP_Status :: xgxsStatus0 :: txpll_lock [11:11] */ 18509 #define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_MASK 0x0800 18510 #define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_ALIGN 0 18511 #define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_BITS 1 18512 #define GP_STATUS_XGXSSTATUS0_TXPLL_LOCK_SHIFT 11 18513 18514 /* GP_Status :: xgxsStatus0 :: txd_fifo_err [10:10] */ 18515 #define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_MASK 0x0400 18516 #define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_ALIGN 0 18517 #define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_BITS 1 18518 #define GP_STATUS_XGXSSTATUS0_TXD_FIFO_ERR_SHIFT 10 18519 18520 /* GP_Status :: xgxsStatus0 :: sequencer_done [09:09] */ 18521 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_MASK 0x0200 18522 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_ALIGN 0 18523 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_BITS 1 18524 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_DONE_SHIFT 9 18525 18526 /* GP_Status :: xgxsStatus0 :: sequencer_pass [08:08] */ 18527 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_MASK 0x0100 18528 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_ALIGN 0 18529 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_BITS 1 18530 #define GP_STATUS_XGXSSTATUS0_SEQUENCER_PASS_SHIFT 8 18531 18532 /* GP_Status :: xgxsStatus0 :: rxferr [07:04] */ 18533 #define GP_STATUS_XGXSSTATUS0_RXFERR_MASK 0x00f0 18534 #define GP_STATUS_XGXSSTATUS0_RXFERR_ALIGN 0 18535 #define GP_STATUS_XGXSSTATUS0_RXFERR_BITS 4 18536 #define GP_STATUS_XGXSSTATUS0_RXFERR_SHIFT 4 18537 18538 /* GP_Status :: xgxsStatus0 :: pll_mode_afe [03:03] */ 18539 #define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_MASK 0x0008 18540 #define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_ALIGN 0 18541 #define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_BITS 1 18542 #define GP_STATUS_XGXSSTATUS0_PLL_MODE_AFE_SHIFT 3 18543 18544 /* GP_Status :: xgxsStatus0 :: ckcmp_unflow [02:02] */ 18545 #define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_MASK 0x0004 18546 #define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_ALIGN 0 18547 #define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_BITS 1 18548 #define GP_STATUS_XGXSSTATUS0_CKCMP_UNFLOW_SHIFT 2 18549 18550 /* GP_Status :: xgxsStatus0 :: ckcmp_ovflow [01:01] */ 18551 #define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_MASK 0x0002 18552 #define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_ALIGN 0 18553 #define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_BITS 1 18554 #define GP_STATUS_XGXSSTATUS0_CKCMP_OVFLOW_SHIFT 1 18555 18556 /* GP_Status :: xgxsStatus0 :: skew_status [00:00] */ 18557 #define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_MASK 0x0001 18558 #define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_ALIGN 0 18559 #define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_BITS 1 18560 #define GP_STATUS_XGXSSTATUS0_SKEW_STATUS_SHIFT 0 18561 18562 18563 /**************************************************************************** 18564 * GP_Status :: xgxsStatus1 18565 */ 18566 /* GP_Status :: xgxsStatus1 :: mode_10g_tx [15:12] */ 18567 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_MASK 0xf000 18568 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_ALIGN 0 18569 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_BITS 4 18570 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_SHIFT 12 18571 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS 0 18572 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXG_nCC 1 18573 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_IndLane_OS5 5 18574 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_Indlanes 6 18575 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PCI 7 18576 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQ 8 18577 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_XGXS_nLQnCC 9 18578 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PBypass 10 18579 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_PBypass_nDSK 11 18580 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_ComboCoreMode 12 18581 #define GP_STATUS_XGXSSTATUS1_MODE_10G_TX_Clocks_off 15 18582 18583 /* GP_Status :: xgxsStatus1 :: serdesMode_en_tx [11:11] */ 18584 #define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_MASK 0x0800 18585 #define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_ALIGN 0 18586 #define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_BITS 1 18587 #define GP_STATUS_XGXSSTATUS1_SERDESMODE_EN_TX_SHIFT 11 18588 18589 /* GP_Status :: xgxsStatus1 :: sgmii_mode [10:10] */ 18590 #define GP_STATUS_XGXSSTATUS1_SGMII_MODE_MASK 0x0400 18591 #define GP_STATUS_XGXSSTATUS1_SGMII_MODE_ALIGN 0 18592 #define GP_STATUS_XGXSSTATUS1_SGMII_MODE_BITS 1 18593 #define GP_STATUS_XGXSSTATUS1_SGMII_MODE_SHIFT 10 18594 18595 /* GP_Status :: xgxsStatus1 :: link10g [09:09] */ 18596 #define GP_STATUS_XGXSSTATUS1_LINK10G_MASK 0x0200 18597 #define GP_STATUS_XGXSSTATUS1_LINK10G_ALIGN 0 18598 #define GP_STATUS_XGXSSTATUS1_LINK10G_BITS 1 18599 #define GP_STATUS_XGXSSTATUS1_LINK10G_SHIFT 9 18600 18601 /* GP_Status :: xgxsStatus1 :: linkstat [08:08] */ 18602 #define GP_STATUS_XGXSSTATUS1_LINKSTAT_MASK 0x0100 18603 #define GP_STATUS_XGXSSTATUS1_LINKSTAT_ALIGN 0 18604 #define GP_STATUS_XGXSSTATUS1_LINKSTAT_BITS 1 18605 #define GP_STATUS_XGXSSTATUS1_LINKSTAT_SHIFT 8 18606 18607 /* GP_Status :: xgxsStatus1 :: autoneg_complete [07:07] */ 18608 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_MASK 0x0080 18609 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_ALIGN 0 18610 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_BITS 1 18611 #define GP_STATUS_XGXSSTATUS1_AUTONEG_COMPLETE_SHIFT 7 18612 18613 /* GP_Status :: xgxsStatus1 :: reserved0 [06:06] */ 18614 #define GP_STATUS_XGXSSTATUS1_RESERVED0_MASK 0x0040 18615 #define GP_STATUS_XGXSSTATUS1_RESERVED0_ALIGN 0 18616 #define GP_STATUS_XGXSSTATUS1_RESERVED0_BITS 1 18617 #define GP_STATUS_XGXSSTATUS1_RESERVED0_SHIFT 6 18618 18619 /* GP_Status :: xgxsStatus1 :: pll_mode_afe [05:04] */ 18620 #define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_MASK 0x0030 18621 #define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_ALIGN 0 18622 #define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_BITS 2 18623 #define GP_STATUS_XGXSSTATUS1_PLL_MODE_AFE_SHIFT 4 18624 18625 /* GP_Status :: xgxsStatus1 :: actual_speed_ln0 [03:00] */ 18626 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_MASK 0x000f 18627 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_ALIGN 0 18628 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_BITS 4 18629 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_SHIFT 0 18630 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10M 0 18631 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_100M 1 18632 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G 2 18633 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_2p5G 3 18634 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_5G_X4 4 18635 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_6G_X4 5 18636 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_HiG 6 18637 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_CX4 7 18638 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12G_HiG 8 18639 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12p5G_X4 9 18640 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_13G_X4 10 18641 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_15G_X4 11 18642 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_16G_X4 12 18643 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G_KX 13 18644 #define GP_STATUS_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_KX4 14 18645 18646 18647 /**************************************************************************** 18648 * GP_Status :: xgxsStatus2 18649 */ 18650 /* GP_Status :: xgxsStatus2 :: gpwrdwn_rx [15:12] */ 18651 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_MASK 0xf000 18652 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_ALIGN 0 18653 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_BITS 4 18654 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_RX_SHIFT 12 18655 18656 /* GP_Status :: xgxsStatus2 :: gpwrdwn_tx [11:08] */ 18657 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_MASK 0x0f00 18658 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_ALIGN 0 18659 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_BITS 4 18660 #define GP_STATUS_XGXSSTATUS2_GPWRDWN_TX_SHIFT 8 18661 18662 /* GP_Status :: xgxsStatus2 :: freq_sel_rx [07:04] */ 18663 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_MASK 0x00f0 18664 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_ALIGN 0 18665 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_BITS 4 18666 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_RX_SHIFT 4 18667 18668 /* GP_Status :: xgxsStatus2 :: freq_sel_tx [03:00] */ 18669 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_MASK 0x000f 18670 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_ALIGN 0 18671 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_BITS 4 18672 #define GP_STATUS_XGXSSTATUS2_FREQ_SEL_TX_SHIFT 0 18673 18674 18675 /**************************************************************************** 18676 * GP_Status :: Status1000X1 18677 */ 18678 /* GP_Status :: Status1000X1 :: txfifo_err_detected [15:15] */ 18679 #define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK 0x8000 18680 #define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN 0 18681 #define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS 1 18682 #define GP_STATUS_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT 15 18683 18684 /* GP_Status :: Status1000X1 :: rxfifo_err_detected [14:14] */ 18685 #define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK 0x4000 18686 #define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN 0 18687 #define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS 1 18688 #define GP_STATUS_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT 14 18689 18690 /* GP_Status :: Status1000X1 :: false_carrier_detected [13:13] */ 18691 #define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK 0x2000 18692 #define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN 0 18693 #define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS 1 18694 #define GP_STATUS_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT 13 18695 18696 /* GP_Status :: Status1000X1 :: crc_err_detected [12:12] */ 18697 #define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_MASK 0x1000 18698 #define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_ALIGN 0 18699 #define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_BITS 1 18700 #define GP_STATUS_STATUS1000X1_CRC_ERR_DETECTED_SHIFT 12 18701 18702 /* GP_Status :: Status1000X1 :: tx_err_detected [11:11] */ 18703 #define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 18704 #define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 18705 #define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_BITS 1 18706 #define GP_STATUS_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 18707 18708 /* GP_Status :: Status1000X1 :: rx_err_detected [10:10] */ 18709 #define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 18710 #define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 18711 #define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_BITS 1 18712 #define GP_STATUS_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 18713 18714 /* GP_Status :: Status1000X1 :: carrier_extend_err_detected [09:09] */ 18715 #define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200 18716 #define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0 18717 #define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1 18718 #define GP_STATUS_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9 18719 18720 /* GP_Status :: Status1000X1 :: early_end_extension_detected [08:08] */ 18721 #define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100 18722 #define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0 18723 #define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1 18724 #define GP_STATUS_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8 18725 18726 /* GP_Status :: Status1000X1 :: link_status_change [07:07] */ 18727 #define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 18728 #define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 18729 #define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 18730 #define GP_STATUS_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 18731 18732 /* GP_Status :: Status1000X1 :: pause_resolution_rxside [06:06] */ 18733 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0040 18734 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 18735 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS 1 18736 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT 6 18737 18738 /* GP_Status :: Status1000X1 :: pause_resolution_txside [05:05] */ 18739 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0020 18740 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 18741 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS 1 18742 #define GP_STATUS_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT 5 18743 18744 /* GP_Status :: Status1000X1 :: speed_status [04:03] */ 18745 #define GP_STATUS_STATUS1000X1_SPEED_STATUS_MASK 0x0018 18746 #define GP_STATUS_STATUS1000X1_SPEED_STATUS_ALIGN 0 18747 #define GP_STATUS_STATUS1000X1_SPEED_STATUS_BITS 2 18748 #define GP_STATUS_STATUS1000X1_SPEED_STATUS_SHIFT 3 18749 18750 /* GP_Status :: Status1000X1 :: duplex_status [02:02] */ 18751 #define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_MASK 0x0004 18752 #define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_ALIGN 0 18753 #define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_BITS 1 18754 #define GP_STATUS_STATUS1000X1_DUPLEX_STATUS_SHIFT 2 18755 18756 /* GP_Status :: Status1000X1 :: link_status [01:01] */ 18757 #define GP_STATUS_STATUS1000X1_LINK_STATUS_MASK 0x0002 18758 #define GP_STATUS_STATUS1000X1_LINK_STATUS_ALIGN 0 18759 #define GP_STATUS_STATUS1000X1_LINK_STATUS_BITS 1 18760 #define GP_STATUS_STATUS1000X1_LINK_STATUS_SHIFT 1 18761 18762 /* GP_Status :: Status1000X1 :: sgmii_mode [00:00] */ 18763 #define GP_STATUS_STATUS1000X1_SGMII_MODE_MASK 0x0001 18764 #define GP_STATUS_STATUS1000X1_SGMII_MODE_ALIGN 0 18765 #define GP_STATUS_STATUS1000X1_SGMII_MODE_BITS 1 18766 #define GP_STATUS_STATUS1000X1_SGMII_MODE_SHIFT 0 18767 18768 18769 /**************************************************************************** 18770 * GP_Status :: Status1000X2 18771 */ 18772 /* GP_Status :: Status1000X2 :: sgmii_mode_change [15:15] */ 18773 #define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_MASK 0x8000 18774 #define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN 0 18775 #define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_BITS 1 18776 #define GP_STATUS_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT 15 18777 18778 /* GP_Status :: Status1000X2 :: consistency_mismatch [14:14] */ 18779 #define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_MASK 0x4000 18780 #define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN 0 18781 #define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_BITS 1 18782 #define GP_STATUS_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT 14 18783 18784 /* GP_Status :: Status1000X2 :: autoneg_resolution_err [13:13] */ 18785 #define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK 0x2000 18786 #define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN 0 18787 #define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS 1 18788 #define GP_STATUS_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT 13 18789 18790 /* GP_Status :: Status1000X2 :: sgmii_selector_mismatch [12:12] */ 18791 #define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK 0x1000 18792 #define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN 0 18793 #define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS 1 18794 #define GP_STATUS_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT 12 18795 18796 /* GP_Status :: Status1000X2 :: sync_status_fail [11:11] */ 18797 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_MASK 0x0800 18798 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN 0 18799 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_BITS 1 18800 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT 11 18801 18802 /* GP_Status :: Status1000X2 :: sync_status_ok [10:10] */ 18803 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_MASK 0x0400 18804 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_ALIGN 0 18805 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_BITS 1 18806 #define GP_STATUS_STATUS1000X2_SYNC_STATUS_OK_SHIFT 10 18807 18808 /* GP_Status :: Status1000X2 :: rudi_c [09:09] */ 18809 #define GP_STATUS_STATUS1000X2_RUDI_C_MASK 0x0200 18810 #define GP_STATUS_STATUS1000X2_RUDI_C_ALIGN 0 18811 #define GP_STATUS_STATUS1000X2_RUDI_C_BITS 1 18812 #define GP_STATUS_STATUS1000X2_RUDI_C_SHIFT 9 18813 18814 /* GP_Status :: Status1000X2 :: rudi_I [08:08] */ 18815 #define GP_STATUS_STATUS1000X2_RUDI_I_MASK 0x0100 18816 #define GP_STATUS_STATUS1000X2_RUDI_I_ALIGN 0 18817 #define GP_STATUS_STATUS1000X2_RUDI_I_BITS 1 18818 #define GP_STATUS_STATUS1000X2_RUDI_I_SHIFT 8 18819 18820 /* GP_Status :: Status1000X2 :: rudi_invalid [07:07] */ 18821 #define GP_STATUS_STATUS1000X2_RUDI_INVALID_MASK 0x0080 18822 #define GP_STATUS_STATUS1000X2_RUDI_INVALID_ALIGN 0 18823 #define GP_STATUS_STATUS1000X2_RUDI_INVALID_BITS 1 18824 #define GP_STATUS_STATUS1000X2_RUDI_INVALID_SHIFT 7 18825 18826 /* GP_Status :: Status1000X2 :: linkDown_syncLoss [06:06] */ 18827 #define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK 0x0040 18828 #define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN 0 18829 #define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS 1 18830 #define GP_STATUS_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT 6 18831 18832 /* GP_Status :: Status1000X2 :: idle_detect_state [05:05] */ 18833 #define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_MASK 0x0020 18834 #define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_ALIGN 0 18835 #define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_BITS 1 18836 #define GP_STATUS_STATUS1000X2_IDLE_DETECT_STATE_SHIFT 5 18837 18838 /* GP_Status :: Status1000X2 :: complete_acknowledge_state [04:04] */ 18839 #define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010 18840 #define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0 18841 #define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1 18842 #define GP_STATUS_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4 18843 18844 /* GP_Status :: Status1000X2 :: acknowledge_detect_state [03:03] */ 18845 #define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK 0x0008 18846 #define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0 18847 #define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS 1 18848 #define GP_STATUS_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3 18849 18850 /* GP_Status :: Status1000X2 :: ability_detect_state [02:02] */ 18851 #define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_MASK 0x0004 18852 #define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN 0 18853 #define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_BITS 1 18854 #define GP_STATUS_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT 2 18855 18856 /* union - case anError [01:01] */ 18857 /* GP_Status :: Status1000X2 :: an_error_state [01:01] */ 18858 #define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK 0x0002 18859 #define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN 0 18860 #define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS 1 18861 #define GP_STATUS_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT 1 18862 18863 18864 /* union - case anDisableLink [01:01] */ 18865 /* GP_Status :: Status1000X2 :: an_disable_link_ok_state [01:01] */ 18866 #define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002 18867 #define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0 18868 #define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1 18869 #define GP_STATUS_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1 18870 18871 18872 /* GP_Status :: Status1000X2 :: an_enable_state [00:00] */ 18873 #define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_MASK 0x0001 18874 #define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_ALIGN 0 18875 #define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_BITS 1 18876 #define GP_STATUS_STATUS1000X2_AN_ENABLE_STATE_SHIFT 0 18877 18878 18879 /**************************************************************************** 18880 * GP_Status :: Status1000X3 18881 */ 18882 /* GP_Status :: Status1000X3 :: reserved0 [15:13] */ 18883 #define GP_STATUS_STATUS1000X3_RESERVED0_MASK 0xe000 18884 #define GP_STATUS_STATUS1000X3_RESERVED0_ALIGN 0 18885 #define GP_STATUS_STATUS1000X3_RESERVED0_BITS 3 18886 #define GP_STATUS_STATUS1000X3_RESERVED0_SHIFT 13 18887 18888 /* GP_Status :: Status1000X3 :: pd_park_an [12:12] */ 18889 #define GP_STATUS_STATUS1000X3_PD_PARK_AN_MASK 0x1000 18890 #define GP_STATUS_STATUS1000X3_PD_PARK_AN_ALIGN 0 18891 #define GP_STATUS_STATUS1000X3_PD_PARK_AN_BITS 1 18892 #define GP_STATUS_STATUS1000X3_PD_PARK_AN_SHIFT 12 18893 18894 /* GP_Status :: Status1000X3 :: remotePhy_autosel [11:11] */ 18895 #define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK 0x0800 18896 #define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN 0 18897 #define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS 1 18898 #define GP_STATUS_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT 11 18899 18900 /* GP_Status :: Status1000X3 :: latch_linkdown [10:10] */ 18901 #define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_MASK 0x0400 18902 #define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_ALIGN 0 18903 #define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_BITS 1 18904 #define GP_STATUS_STATUS1000X3_LATCH_LINKDOWN_SHIFT 10 18905 18906 /* GP_Status :: Status1000X3 :: sd_filter [09:09] */ 18907 #define GP_STATUS_STATUS1000X3_SD_FILTER_MASK 0x0200 18908 #define GP_STATUS_STATUS1000X3_SD_FILTER_ALIGN 0 18909 #define GP_STATUS_STATUS1000X3_SD_FILTER_BITS 1 18910 #define GP_STATUS_STATUS1000X3_SD_FILTER_SHIFT 9 18911 18912 /* GP_Status :: Status1000X3 :: sd_mux [08:08] */ 18913 #define GP_STATUS_STATUS1000X3_SD_MUX_MASK 0x0100 18914 #define GP_STATUS_STATUS1000X3_SD_MUX_ALIGN 0 18915 #define GP_STATUS_STATUS1000X3_SD_MUX_BITS 1 18916 #define GP_STATUS_STATUS1000X3_SD_MUX_SHIFT 8 18917 18918 /* GP_Status :: Status1000X3 :: sd_filter_chg [07:07] */ 18919 #define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_MASK 0x0080 18920 #define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_ALIGN 0 18921 #define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_BITS 1 18922 #define GP_STATUS_STATUS1000X3_SD_FILTER_CHG_SHIFT 7 18923 18924 /* GP_Status :: Status1000X3 :: reserved1 [06:00] */ 18925 #define GP_STATUS_STATUS1000X3_RESERVED1_MASK 0x007f 18926 #define GP_STATUS_STATUS1000X3_RESERVED1_ALIGN 0 18927 #define GP_STATUS_STATUS1000X3_RESERVED1_BITS 7 18928 #define GP_STATUS_STATUS1000X3_RESERVED1_SHIFT 0 18929 18930 18931 /**************************************************************************** 18932 * GP_Status :: TPOUT_1 18933 */ 18934 /* GP_Status :: TPOUT_1 :: tpout1 [15:00] */ 18935 #define GP_STATUS_TPOUT_1_TPOUT1_MASK 0xffff 18936 #define GP_STATUS_TPOUT_1_TPOUT1_ALIGN 0 18937 #define GP_STATUS_TPOUT_1_TPOUT1_BITS 16 18938 #define GP_STATUS_TPOUT_1_TPOUT1_SHIFT 0 18939 18940 18941 /**************************************************************************** 18942 * GP_Status :: TPOUT_2 18943 */ 18944 /* GP_Status :: TPOUT_2 :: tpout2 [15:00] */ 18945 #define GP_STATUS_TPOUT_2_TPOUT2_MASK 0xffff 18946 #define GP_STATUS_TPOUT_2_TPOUT2_ALIGN 0 18947 #define GP_STATUS_TPOUT_2_TPOUT2_BITS 16 18948 #define GP_STATUS_TPOUT_2_TPOUT2_SHIFT 0 18949 18950 18951 /**************************************************************************** 18952 * GP_Status :: xgxsStatus3 18953 */ 18954 /* GP_Status :: xgxsStatus3 :: link [15:15] */ 18955 #define GP_STATUS_XGXSSTATUS3_LINK_MASK 0x8000 18956 #define GP_STATUS_XGXSSTATUS3_LINK_ALIGN 0 18957 #define GP_STATUS_XGXSSTATUS3_LINK_BITS 1 18958 #define GP_STATUS_XGXSSTATUS3_LINK_SHIFT 15 18959 18960 /* GP_Status :: xgxsStatus3 :: link_latchdown [14:14] */ 18961 #define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_MASK 0x4000 18962 #define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_ALIGN 0 18963 #define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_BITS 1 18964 #define GP_STATUS_XGXSSTATUS3_LINK_LATCHDOWN_SHIFT 14 18965 18966 /* GP_Status :: xgxsStatus3 :: latch_linkdown_10g_o [13:13] */ 18967 #define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_MASK 0x2000 18968 #define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_ALIGN 0 18969 #define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_BITS 1 18970 #define GP_STATUS_XGXSSTATUS3_LATCH_LINKDOWN_10G_O_SHIFT 13 18971 18972 /* GP_Status :: xgxsStatus3 :: pd_park_an [12:12] */ 18973 #define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_MASK 0x1000 18974 #define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_ALIGN 0 18975 #define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_BITS 1 18976 #define GP_STATUS_XGXSSTATUS3_PD_PARK_AN_SHIFT 12 18977 18978 /* GP_Status :: xgxsStatus3 :: gpwrdwn_pll [11:11] */ 18979 #define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_MASK 0x0800 18980 #define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_ALIGN 0 18981 #define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_BITS 1 18982 #define GP_STATUS_XGXSSTATUS3_GPWRDWN_PLL_SHIFT 11 18983 18984 /* GP_Status :: xgxsStatus3 :: hcd_over_1g [10:00] */ 18985 #define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_MASK 0x07ff 18986 #define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_ALIGN 0 18987 #define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_BITS 11 18988 #define GP_STATUS_XGXSSTATUS3_HCD_OVER_1G_SHIFT 0 18989 18990 18991 /**************************************************************************** 18992 * GP_Status :: x2500Status1 18993 */ 18994 /* GP_Status :: x2500Status1 :: hcd_over_1g_or [15:15] */ 18995 #define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_MASK 0x8000 18996 #define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_ALIGN 0 18997 #define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_BITS 1 18998 #define GP_STATUS_X2500STATUS1_HCD_OVER_1G_OR_SHIFT 15 18999 19000 /* GP_Status :: x2500Status1 :: latch_hcd_over_1g [14:14] */ 19001 #define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_MASK 0x4000 19002 #define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_ALIGN 0 19003 #define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_BITS 1 19004 #define GP_STATUS_X2500STATUS1_LATCH_HCD_OVER_1G_SHIFT 14 19005 19006 /* GP_Status :: x2500Status1 :: latchmdio [13:13] */ 19007 #define GP_STATUS_X2500STATUS1_LATCHMDIO_MASK 0x2000 19008 #define GP_STATUS_X2500STATUS1_LATCHMDIO_ALIGN 0 19009 #define GP_STATUS_X2500STATUS1_LATCHMDIO_BITS 1 19010 #define GP_STATUS_X2500STATUS1_LATCHMDIO_SHIFT 13 19011 19012 /* GP_Status :: x2500Status1 :: s_bc_reg_rst [12:12] */ 19013 #define GP_STATUS_X2500STATUS1_S_BC_REG_RST_MASK 0x1000 19014 #define GP_STATUS_X2500STATUS1_S_BC_REG_RST_ALIGN 0 19015 #define GP_STATUS_X2500STATUS1_S_BC_REG_RST_BITS 1 19016 #define GP_STATUS_X2500STATUS1_S_BC_REG_RST_SHIFT 12 19017 19018 /* GP_Status :: x2500Status1 :: s_wait2res [11:11] */ 19019 #define GP_STATUS_X2500STATUS1_S_WAIT2RES_MASK 0x0800 19020 #define GP_STATUS_X2500STATUS1_S_WAIT2RES_ALIGN 0 19021 #define GP_STATUS_X2500STATUS1_S_WAIT2RES_BITS 1 19022 #define GP_STATUS_X2500STATUS1_S_WAIT2RES_SHIFT 11 19023 19024 /* GP_Status :: x2500Status1 :: s_wait30ms [10:10] */ 19025 #define GP_STATUS_X2500STATUS1_S_WAIT30MS_MASK 0x0400 19026 #define GP_STATUS_X2500STATUS1_S_WAIT30MS_ALIGN 0 19027 #define GP_STATUS_X2500STATUS1_S_WAIT30MS_BITS 1 19028 #define GP_STATUS_X2500STATUS1_S_WAIT30MS_SHIFT 10 19029 19030 /* GP_Status :: x2500Status1 :: s_clockswit [09:09] */ 19031 #define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_MASK 0x0200 19032 #define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_ALIGN 0 19033 #define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_BITS 1 19034 #define GP_STATUS_X2500STATUS1_S_CLOCKSWIT_SHIFT 9 19035 19036 /* GP_Status :: x2500Status1 :: s_pllswit [08:08] */ 19037 #define GP_STATUS_X2500STATUS1_S_PLLSWIT_MASK 0x0100 19038 #define GP_STATUS_X2500STATUS1_S_PLLSWIT_ALIGN 0 19039 #define GP_STATUS_X2500STATUS1_S_PLLSWIT_BITS 1 19040 #define GP_STATUS_X2500STATUS1_S_PLLSWIT_SHIFT 8 19041 19042 /* GP_Status :: x2500Status1 :: s_wait4link [07:07] */ 19043 #define GP_STATUS_X2500STATUS1_S_WAIT4LINK_MASK 0x0080 19044 #define GP_STATUS_X2500STATUS1_S_WAIT4LINK_ALIGN 0 19045 #define GP_STATUS_X2500STATUS1_S_WAIT4LINK_BITS 1 19046 #define GP_STATUS_X2500STATUS1_S_WAIT4LINK_SHIFT 7 19047 19048 /* GP_Status :: x2500Status1 :: s_complete [06:06] */ 19049 #define GP_STATUS_X2500STATUS1_S_COMPLETE_MASK 0x0040 19050 #define GP_STATUS_X2500STATUS1_S_COMPLETE_ALIGN 0 19051 #define GP_STATUS_X2500STATUS1_S_COMPLETE_BITS 1 19052 #define GP_STATUS_X2500STATUS1_S_COMPLETE_SHIFT 6 19053 19054 /* GP_Status :: x2500Status1 :: s_lostlink [05:05] */ 19055 #define GP_STATUS_X2500STATUS1_S_LOSTLINK_MASK 0x0020 19056 #define GP_STATUS_X2500STATUS1_S_LOSTLINK_ALIGN 0 19057 #define GP_STATUS_X2500STATUS1_S_LOSTLINK_BITS 1 19058 #define GP_STATUS_X2500STATUS1_S_LOSTLINK_SHIFT 5 19059 19060 /* GP_Status :: x2500Status1 :: s_dead [04:04] */ 19061 #define GP_STATUS_X2500STATUS1_S_DEAD_MASK 0x0010 19062 #define GP_STATUS_X2500STATUS1_S_DEAD_ALIGN 0 19063 #define GP_STATUS_X2500STATUS1_S_DEAD_BITS 1 19064 #define GP_STATUS_X2500STATUS1_S_DEAD_SHIFT 4 19065 19066 /* GP_Status :: x2500Status1 :: fail_cnt [03:00] */ 19067 #define GP_STATUS_X2500STATUS1_FAIL_CNT_MASK 0x000f 19068 #define GP_STATUS_X2500STATUS1_FAIL_CNT_ALIGN 0 19069 #define GP_STATUS_X2500STATUS1_FAIL_CNT_BITS 4 19070 #define GP_STATUS_X2500STATUS1_FAIL_CNT_SHIFT 0 19071 19072 19073 /**************************************************************************** 19074 * GP_Status :: topANStatus1 19075 */ 19076 /* GP_Status :: topANStatus1 :: reserved0 [15:14] */ 19077 #define GP_STATUS_TOPANSTATUS1_RESERVED0_MASK 0xc000 19078 #define GP_STATUS_TOPANSTATUS1_RESERVED0_ALIGN 0 19079 #define GP_STATUS_TOPANSTATUS1_RESERVED0_BITS 2 19080 #define GP_STATUS_TOPANSTATUS1_RESERVED0_SHIFT 14 19081 19082 /* GP_Status :: topANStatus1 :: actual_speed [13:08] */ 19083 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_MASK 0x3f00 19084 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_ALIGN 0 19085 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_BITS 6 19086 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_SHIFT 8 19087 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_10M 0 19088 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_100M 1 19089 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_1G 2 19090 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_2p5G 3 19091 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_5G_X4 4 19092 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_6G_X4 5 19093 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_HiG 6 19094 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_10G_CX4 7 19095 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_12G_HiG 8 19096 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_12p5G_X4 9 19097 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_13G_X4 10 19098 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_15G_X4 11 19099 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_16G_X4 12 19100 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_5G 16 19101 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_6p4G 17 19102 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_20G_X4 18 19103 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_21G_X4 19 19104 #define GP_STATUS_TOPANSTATUS1_ACTUAL_SPEED_dr_25G_X4 20 19105 19106 /* GP_Status :: topANStatus1 :: pause_resolution_rxside [07:07] */ 19107 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0080 19108 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 19109 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_BITS 1 19110 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_RXSIDE_SHIFT 7 19111 19112 /* GP_Status :: topANStatus1 :: pause_resolution_txside [06:06] */ 19113 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0040 19114 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 19115 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_BITS 1 19116 #define GP_STATUS_TOPANSTATUS1_PAUSE_RESOLUTION_TXSIDE_SHIFT 6 19117 19118 /* GP_Status :: topANStatus1 :: cl73_lp_np_BAM_able [05:05] */ 19119 #define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_MASK 0x0020 19120 #define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_ALIGN 0 19121 #define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_BITS 1 19122 #define GP_STATUS_TOPANSTATUS1_CL73_LP_NP_BAM_ABLE_SHIFT 5 19123 19124 /* GP_Status :: topANStatus1 :: cl73_mr_lp_autoneg_able [04:04] */ 19125 #define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_MASK 0x0010 19126 #define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_ALIGN 0 19127 #define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_BITS 1 19128 #define GP_STATUS_TOPANSTATUS1_CL73_MR_LP_AUTONEG_ABLE_SHIFT 4 19129 19130 /* GP_Status :: topANStatus1 :: duplex_status [03:03] */ 19131 #define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_MASK 0x0008 19132 #define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_ALIGN 0 19133 #define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_BITS 1 19134 #define GP_STATUS_TOPANSTATUS1_DUPLEX_STATUS_SHIFT 3 19135 19136 /* GP_Status :: topANStatus1 :: link_status [02:02] */ 19137 #define GP_STATUS_TOPANSTATUS1_LINK_STATUS_MASK 0x0004 19138 #define GP_STATUS_TOPANSTATUS1_LINK_STATUS_ALIGN 0 19139 #define GP_STATUS_TOPANSTATUS1_LINK_STATUS_BITS 1 19140 #define GP_STATUS_TOPANSTATUS1_LINK_STATUS_SHIFT 2 19141 19142 /* GP_Status :: topANStatus1 :: cl37_autoneg_complete [01:01] */ 19143 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_MASK 0x0002 19144 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_ALIGN 0 19145 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_BITS 1 19146 #define GP_STATUS_TOPANSTATUS1_CL37_AUTONEG_COMPLETE_SHIFT 1 19147 19148 /* GP_Status :: topANStatus1 :: cl73_autoneg_complete [00:00] */ 19149 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_MASK 0x0001 19150 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_ALIGN 0 19151 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_BITS 1 19152 #define GP_STATUS_TOPANSTATUS1_CL73_AUTONEG_COMPLETE_SHIFT 0 19153 19154 19155 /**************************************************************************** 19156 * GP_Status :: LP_UP1 19157 */ 19158 /* GP_Status :: LP_UP1 :: reserved0 [15:11] */ 19159 #define GP_STATUS_LP_UP1_RESERVED0_MASK 0xf800 19160 #define GP_STATUS_LP_UP1_RESERVED0_ALIGN 0 19161 #define GP_STATUS_LP_UP1_RESERVED0_BITS 5 19162 #define GP_STATUS_LP_UP1_RESERVED0_SHIFT 11 19163 19164 /* GP_Status :: LP_UP1 :: dataRate_20GX4 [10:10] */ 19165 #define GP_STATUS_LP_UP1_DATARATE_20GX4_MASK 0x0400 19166 #define GP_STATUS_LP_UP1_DATARATE_20GX4_ALIGN 0 19167 #define GP_STATUS_LP_UP1_DATARATE_20GX4_BITS 1 19168 #define GP_STATUS_LP_UP1_DATARATE_20GX4_SHIFT 10 19169 19170 /* GP_Status :: LP_UP1 :: dataRate_16GX4 [09:09] */ 19171 #define GP_STATUS_LP_UP1_DATARATE_16GX4_MASK 0x0200 19172 #define GP_STATUS_LP_UP1_DATARATE_16GX4_ALIGN 0 19173 #define GP_STATUS_LP_UP1_DATARATE_16GX4_BITS 1 19174 #define GP_STATUS_LP_UP1_DATARATE_16GX4_SHIFT 9 19175 19176 /* GP_Status :: LP_UP1 :: dataRate_15GX4 [08:08] */ 19177 #define GP_STATUS_LP_UP1_DATARATE_15GX4_MASK 0x0100 19178 #define GP_STATUS_LP_UP1_DATARATE_15GX4_ALIGN 0 19179 #define GP_STATUS_LP_UP1_DATARATE_15GX4_BITS 1 19180 #define GP_STATUS_LP_UP1_DATARATE_15GX4_SHIFT 8 19181 19182 /* GP_Status :: LP_UP1 :: dataRate_13GX4 [07:07] */ 19183 #define GP_STATUS_LP_UP1_DATARATE_13GX4_MASK 0x0080 19184 #define GP_STATUS_LP_UP1_DATARATE_13GX4_ALIGN 0 19185 #define GP_STATUS_LP_UP1_DATARATE_13GX4_BITS 1 19186 #define GP_STATUS_LP_UP1_DATARATE_13GX4_SHIFT 7 19187 19188 /* GP_Status :: LP_UP1 :: dataRate_12p5GX4 [06:06] */ 19189 #define GP_STATUS_LP_UP1_DATARATE_12P5GX4_MASK 0x0040 19190 #define GP_STATUS_LP_UP1_DATARATE_12P5GX4_ALIGN 0 19191 #define GP_STATUS_LP_UP1_DATARATE_12P5GX4_BITS 1 19192 #define GP_STATUS_LP_UP1_DATARATE_12P5GX4_SHIFT 6 19193 19194 /* GP_Status :: LP_UP1 :: dataRate_12GX4 [05:05] */ 19195 #define GP_STATUS_LP_UP1_DATARATE_12GX4_MASK 0x0020 19196 #define GP_STATUS_LP_UP1_DATARATE_12GX4_ALIGN 0 19197 #define GP_STATUS_LP_UP1_DATARATE_12GX4_BITS 1 19198 #define GP_STATUS_LP_UP1_DATARATE_12GX4_SHIFT 5 19199 19200 /* GP_Status :: LP_UP1 :: dataRate_10GCX4 [04:04] */ 19201 #define GP_STATUS_LP_UP1_DATARATE_10GCX4_MASK 0x0010 19202 #define GP_STATUS_LP_UP1_DATARATE_10GCX4_ALIGN 0 19203 #define GP_STATUS_LP_UP1_DATARATE_10GCX4_BITS 1 19204 #define GP_STATUS_LP_UP1_DATARATE_10GCX4_SHIFT 4 19205 19206 /* GP_Status :: LP_UP1 :: dataRate_10GX4 [03:03] */ 19207 #define GP_STATUS_LP_UP1_DATARATE_10GX4_MASK 0x0008 19208 #define GP_STATUS_LP_UP1_DATARATE_10GX4_ALIGN 0 19209 #define GP_STATUS_LP_UP1_DATARATE_10GX4_BITS 1 19210 #define GP_STATUS_LP_UP1_DATARATE_10GX4_SHIFT 3 19211 19212 /* GP_Status :: LP_UP1 :: dataRate_6GX4 [02:02] */ 19213 #define GP_STATUS_LP_UP1_DATARATE_6GX4_MASK 0x0004 19214 #define GP_STATUS_LP_UP1_DATARATE_6GX4_ALIGN 0 19215 #define GP_STATUS_LP_UP1_DATARATE_6GX4_BITS 1 19216 #define GP_STATUS_LP_UP1_DATARATE_6GX4_SHIFT 2 19217 19218 /* GP_Status :: LP_UP1 :: dataRate_5GX4 [01:01] */ 19219 #define GP_STATUS_LP_UP1_DATARATE_5GX4_MASK 0x0002 19220 #define GP_STATUS_LP_UP1_DATARATE_5GX4_ALIGN 0 19221 #define GP_STATUS_LP_UP1_DATARATE_5GX4_BITS 1 19222 #define GP_STATUS_LP_UP1_DATARATE_5GX4_SHIFT 1 19223 19224 /* GP_Status :: LP_UP1 :: dataRate_2p5GX1 [00:00] */ 19225 #define GP_STATUS_LP_UP1_DATARATE_2P5GX1_MASK 0x0001 19226 #define GP_STATUS_LP_UP1_DATARATE_2P5GX1_ALIGN 0 19227 #define GP_STATUS_LP_UP1_DATARATE_2P5GX1_BITS 1 19228 #define GP_STATUS_LP_UP1_DATARATE_2P5GX1_SHIFT 0 19229 19230 19231 /**************************************************************************** 19232 * GP_Status :: LP_UP2 19233 */ 19234 /* GP_Status :: LP_UP2 :: reserved0 [15:11] */ 19235 #define GP_STATUS_LP_UP2_RESERVED0_MASK 0xf800 19236 #define GP_STATUS_LP_UP2_RESERVED0_ALIGN 0 19237 #define GP_STATUS_LP_UP2_RESERVED0_BITS 5 19238 #define GP_STATUS_LP_UP2_RESERVED0_SHIFT 11 19239 19240 /* GP_Status :: LP_UP2 :: valid [10:10] */ 19241 #define GP_STATUS_LP_UP2_VALID_MASK 0x0400 19242 #define GP_STATUS_LP_UP2_VALID_ALIGN 0 19243 #define GP_STATUS_LP_UP2_VALID_BITS 1 19244 #define GP_STATUS_LP_UP2_VALID_SHIFT 10 19245 19246 /* GP_Status :: LP_UP2 :: preemphasis [09:06] */ 19247 #define GP_STATUS_LP_UP2_PREEMPHASIS_MASK 0x03c0 19248 #define GP_STATUS_LP_UP2_PREEMPHASIS_ALIGN 0 19249 #define GP_STATUS_LP_UP2_PREEMPHASIS_BITS 4 19250 #define GP_STATUS_LP_UP2_PREEMPHASIS_SHIFT 6 19251 19252 /* GP_Status :: LP_UP2 :: idriver [05:03] */ 19253 #define GP_STATUS_LP_UP2_IDRIVER_MASK 0x0038 19254 #define GP_STATUS_LP_UP2_IDRIVER_ALIGN 0 19255 #define GP_STATUS_LP_UP2_IDRIVER_BITS 3 19256 #define GP_STATUS_LP_UP2_IDRIVER_SHIFT 3 19257 19258 /* GP_Status :: LP_UP2 :: ipredriver [02:00] */ 19259 #define GP_STATUS_LP_UP2_IPREDRIVER_MASK 0x0007 19260 #define GP_STATUS_LP_UP2_IPREDRIVER_ALIGN 0 19261 #define GP_STATUS_LP_UP2_IPREDRIVER_BITS 3 19262 #define GP_STATUS_LP_UP2_IPREDRIVER_SHIFT 0 19263 19264 19265 /**************************************************************************** 19266 * GP_Status :: LP_UP3 19267 */ 19268 /* GP_Status :: LP_UP3 :: reserved0 [15:11] */ 19269 #define GP_STATUS_LP_UP3_RESERVED0_MASK 0xf800 19270 #define GP_STATUS_LP_UP3_RESERVED0_ALIGN 0 19271 #define GP_STATUS_LP_UP3_RESERVED0_BITS 5 19272 #define GP_STATUS_LP_UP3_RESERVED0_SHIFT 11 19273 19274 /* GP_Status :: LP_UP3 :: last [10:10] */ 19275 #define GP_STATUS_LP_UP3_LAST_MASK 0x0400 19276 #define GP_STATUS_LP_UP3_LAST_ALIGN 0 19277 #define GP_STATUS_LP_UP3_LAST_BITS 1 19278 #define GP_STATUS_LP_UP3_LAST_SHIFT 10 19279 19280 /* GP_Status :: LP_UP3 :: dataRate_21GX4 [09:09] */ 19281 #define GP_STATUS_LP_UP3_DATARATE_21GX4_MASK 0x0200 19282 #define GP_STATUS_LP_UP3_DATARATE_21GX4_ALIGN 0 19283 #define GP_STATUS_LP_UP3_DATARATE_21GX4_BITS 1 19284 #define GP_STATUS_LP_UP3_DATARATE_21GX4_SHIFT 9 19285 19286 /* GP_Status :: LP_UP3 :: dataRate_25p45GX4 [08:08] */ 19287 #define GP_STATUS_LP_UP3_DATARATE_25P45GX4_MASK 0x0100 19288 #define GP_STATUS_LP_UP3_DATARATE_25P45GX4_ALIGN 0 19289 #define GP_STATUS_LP_UP3_DATARATE_25P45GX4_BITS 1 19290 #define GP_STATUS_LP_UP3_DATARATE_25P45GX4_SHIFT 8 19291 19292 /* GP_Status :: LP_UP3 :: reserved1 [07:02] */ 19293 #define GP_STATUS_LP_UP3_RESERVED1_MASK 0x00fc 19294 #define GP_STATUS_LP_UP3_RESERVED1_ALIGN 0 19295 #define GP_STATUS_LP_UP3_RESERVED1_BITS 6 19296 #define GP_STATUS_LP_UP3_RESERVED1_SHIFT 2 19297 19298 /* GP_Status :: LP_UP3 :: scramble_8B10B [01:01] */ 19299 #define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_MASK 0x0002 19300 #define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_ALIGN 0 19301 #define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_BITS 1 19302 #define GP_STATUS_LP_UP3_SCRAMBLE_8B10B_SHIFT 1 19303 19304 /* GP_Status :: LP_UP3 :: HiGig2 [00:00] */ 19305 #define GP_STATUS_LP_UP3_HIGIG2_MASK 0x0001 19306 #define GP_STATUS_LP_UP3_HIGIG2_ALIGN 0 19307 #define GP_STATUS_LP_UP3_HIGIG2_BITS 1 19308 #define GP_STATUS_LP_UP3_HIGIG2_SHIFT 0 19309 19310 19311 /**************************************************************************** 19312 * Hypercore_USER_AN73_pdet 19313 */ 19314 /**************************************************************************** 19315 * AN73_pdet :: parDet10GStatus 19316 */ 19317 /* union - case pdStatus0 [15:00] */ 19318 /* AN73_pdet :: parDet10GStatus :: pd_link [15:15] */ 19319 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_MASK 0x8000 19320 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_ALIGN 0 19321 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_BITS 1 19322 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LINK_SHIFT 15 19323 19324 /* AN73_pdet :: parDet10GStatus :: pd_CX4_en [14:14] */ 19325 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_MASK 0x4000 19326 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_ALIGN 0 19327 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_BITS 1 19328 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_CX4_EN_SHIFT 14 19329 19330 /* AN73_pdet :: parDet10GStatus :: pd_lssFaultCount_en [13:13] */ 19331 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_MASK 0x2000 19332 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_ALIGN 0 19333 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_BITS 1 19334 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_EN_SHIFT 13 19335 19336 /* AN73_pdet :: parDet10GStatus :: pd_tunePll12g [12:12] */ 19337 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_MASK 0x1000 19338 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_ALIGN 0 19339 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_BITS 1 19340 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL12G_SHIFT 12 19341 19342 /* AN73_pdet :: parDet10GStatus :: pd_tunePll10g [11:11] */ 19343 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_MASK 0x0800 19344 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_ALIGN 0 19345 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_BITS 1 19346 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TUNEPLL10G_SHIFT 11 19347 19348 /* AN73_pdet :: parDet10GStatus :: pd_txdLaneOff [10:10] */ 19349 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_MASK 0x0400 19350 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_ALIGN 0 19351 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_BITS 1 19352 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_TXDLANEOFF_SHIFT 10 19353 19354 /* AN73_pdet :: parDet10GStatus :: pd_busy [09:09] */ 19355 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_MASK 0x0200 19356 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_ALIGN 0 19357 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_BITS 1 19358 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_BUSY_SHIFT 9 19359 19360 /* AN73_pdet :: parDet10GStatus :: pd_park_an [08:08] */ 19361 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_MASK 0x0100 19362 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_ALIGN 0 19363 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_BITS 1 19364 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_PARK_AN_SHIFT 8 19365 19366 /* AN73_pdet :: parDet10GStatus :: pd_lssFaultCount [07:04] */ 19367 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_MASK 0x00f0 19368 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_ALIGN 0 19369 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_BITS 4 19370 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_PD_LSSFAULTCOUNT_SHIFT 4 19371 19372 /* AN73_pdet :: parDet10GStatus :: rxSeqDone [03:00] */ 19373 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_MASK 0x000f 19374 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_ALIGN 0 19375 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_BITS 4 19376 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS0_RXSEQDONE_SHIFT 0 19377 19378 19379 /* union - case pdStatus1 [15:00] */ 19380 /* AN73_pdet :: parDet10GStatus :: reserved0 [15:09] */ 19381 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_MASK 0xfe00 19382 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_ALIGN 0 19383 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_BITS 7 19384 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_RESERVED0_SHIFT 9 19385 19386 /* AN73_pdet :: parDet10GStatus :: fail_lh [08:08] */ 19387 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_MASK 0x0100 19388 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_ALIGN 0 19389 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_BITS 1 19390 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_FAIL_LH_SHIFT 8 19391 19392 /* AN73_pdet :: parDet10GStatus :: complete_lh [07:07] */ 19393 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_MASK 0x0080 19394 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_ALIGN 0 19395 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_BITS 1 19396 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_COMPLETE_LH_SHIFT 7 19397 19398 /* AN73_pdet :: parDet10GStatus :: link12gretry_lh [06:06] */ 19399 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_MASK 0x0040 19400 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_ALIGN 0 19401 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_BITS 1 19402 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK12GRETRY_LH_SHIFT 6 19403 19404 /* AN73_pdet :: parDet10GStatus :: wait4link12g_lh [05:05] */ 19405 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_MASK 0x0020 19406 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_ALIGN 0 19407 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_BITS 1 19408 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK12G_LH_SHIFT 5 19409 19410 /* AN73_pdet :: parDet10GStatus :: samplefault_lh [04:04] */ 19411 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_MASK 0x0010 19412 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_ALIGN 0 19413 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_BITS 1 19414 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_SAMPLEFAULT_LH_SHIFT 4 19415 19416 /* AN73_pdet :: parDet10GStatus :: link10gretry_lh [03:03] */ 19417 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_MASK 0x0008 19418 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_ALIGN 0 19419 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_BITS 1 19420 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_LINK10GRETRY_LH_SHIFT 3 19421 19422 /* AN73_pdet :: parDet10GStatus :: wait4link10g_lh [02:02] */ 19423 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_MASK 0x0004 19424 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_ALIGN 0 19425 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_BITS 1 19426 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LINK10G_LH_SHIFT 2 19427 19428 /* AN73_pdet :: parDet10GStatus :: wait4sigdet_lh [01:01] */ 19429 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_MASK 0x0002 19430 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_ALIGN 0 19431 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_BITS 1 19432 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4SIGDET_LH_SHIFT 1 19433 19434 /* AN73_pdet :: parDet10GStatus :: wait4lock_lh [00:00] */ 19435 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_MASK 0x0001 19436 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_ALIGN 0 19437 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_BITS 1 19438 #define AN73_PDET_PARDET10GSTATUS_PDSTATUS1_WAIT4LOCK_LH_SHIFT 0 19439 19440 19441 19442 /**************************************************************************** 19443 * AN73_pdet :: parDet10GControl 19444 */ 19445 /* AN73_pdet :: parDet10GControl :: force_parDet10g_en [15:15] */ 19446 #define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_MASK 0x8000 19447 #define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_ALIGN 0 19448 #define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_BITS 1 19449 #define AN73_PDET_PARDET10GCONTROL_FORCE_PARDET10G_EN_SHIFT 15 19450 19451 /* AN73_pdet :: parDet10GControl :: pd_cx4_init [14:14] */ 19452 #define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_MASK 0x4000 19453 #define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_ALIGN 0 19454 #define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_BITS 1 19455 #define AN73_PDET_PARDET10GCONTROL_PD_CX4_INIT_SHIFT 14 19456 19457 /* AN73_pdet :: parDet10GControl :: pd_sw_overide [13:13] */ 19458 #define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_MASK 0x2000 19459 #define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_ALIGN 0 19460 #define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_BITS 1 19461 #define AN73_PDET_PARDET10GCONTROL_PD_SW_OVERIDE_SHIFT 13 19462 19463 /* AN73_pdet :: parDet10GControl :: pd_sw_busy_an [12:12] */ 19464 #define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_MASK 0x1000 19465 #define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_ALIGN 0 19466 #define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_BITS 1 19467 #define AN73_PDET_PARDET10GCONTROL_PD_SW_BUSY_AN_SHIFT 12 19468 19469 /* AN73_pdet :: parDet10GControl :: pd_sw_CX4_en [11:11] */ 19470 #define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_MASK 0x0800 19471 #define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_ALIGN 0 19472 #define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_BITS 1 19473 #define AN73_PDET_PARDET10GCONTROL_PD_SW_CX4_EN_SHIFT 11 19474 19475 /* AN73_pdet :: parDet10GControl :: pd_sw_tunePll12g [10:10] */ 19476 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_MASK 0x0400 19477 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_ALIGN 0 19478 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_BITS 1 19479 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL12G_SHIFT 10 19480 19481 /* AN73_pdet :: parDet10GControl :: pd_sw_tunePll10g [09:09] */ 19482 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_MASK 0x0200 19483 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_ALIGN 0 19484 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_BITS 1 19485 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TUNEPLL10G_SHIFT 9 19486 19487 /* AN73_pdet :: parDet10GControl :: pd_sw_lssFaultCount_en [08:08] */ 19488 #define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_MASK 0x0100 19489 #define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_ALIGN 0 19490 #define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_BITS 1 19491 #define AN73_PDET_PARDET10GCONTROL_PD_SW_LSSFAULTCOUNT_EN_SHIFT 8 19492 19493 /* AN73_pdet :: parDet10GControl :: pd_sw_txdOff [07:07] */ 19494 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_MASK 0x0080 19495 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_ALIGN 0 19496 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_BITS 1 19497 #define AN73_PDET_PARDET10GCONTROL_PD_SW_TXDOFF_SHIFT 7 19498 19499 /* AN73_pdet :: parDet10GControl :: pd_12g_txdOn_disable [06:06] */ 19500 #define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_MASK 0x0040 19501 #define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_ALIGN 0 19502 #define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_BITS 1 19503 #define AN73_PDET_PARDET10GCONTROL_PD_12G_TXDON_DISABLE_SHIFT 6 19504 19505 /* AN73_pdet :: parDet10GControl :: pd_12g_disable [05:05] */ 19506 #define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_MASK 0x0020 19507 #define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_ALIGN 0 19508 #define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_BITS 1 19509 #define AN73_PDET_PARDET10GCONTROL_PD_12G_DISABLE_SHIFT 5 19510 19511 /* AN73_pdet :: parDet10GControl :: pd_10g_txdOn_disable [04:04] */ 19512 #define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_MASK 0x0010 19513 #define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_ALIGN 0 19514 #define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_BITS 1 19515 #define AN73_PDET_PARDET10GCONTROL_PD_10G_TXDON_DISABLE_SHIFT 4 19516 19517 /* AN73_pdet :: parDet10GControl :: pd_10g_disable [03:03] */ 19518 #define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_MASK 0x0008 19519 #define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_ALIGN 0 19520 #define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_BITS 1 19521 #define AN73_PDET_PARDET10GCONTROL_PD_10G_DISABLE_SHIFT 3 19522 19523 /* AN73_pdet :: parDet10GControl :: pd_stat_sel [02:02] */ 19524 #define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_MASK 0x0004 19525 #define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_ALIGN 0 19526 #define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_BITS 1 19527 #define AN73_PDET_PARDET10GCONTROL_PD_STAT_SEL_SHIFT 2 19528 19529 /* AN73_pdet :: parDet10GControl :: pd_fast_timer_en [01:01] */ 19530 #define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_MASK 0x0002 19531 #define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_ALIGN 0 19532 #define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_BITS 1 19533 #define AN73_PDET_PARDET10GCONTROL_PD_FAST_TIMER_EN_SHIFT 1 19534 19535 /* AN73_pdet :: parDet10GControl :: parDet10g_en [00:00] */ 19536 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_MASK 0x0001 19537 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_ALIGN 0 19538 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_BITS 1 19539 #define AN73_PDET_PARDET10GCONTROL_PARDET10G_EN_SHIFT 0 19540 19541 19542 /**************************************************************************** 19543 * AN73_pdet :: parDet10GSigDet 19544 */ 19545 /* AN73_pdet :: parDet10GSigDet :: pd_sd_count [15:00] */ 19546 #define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_MASK 0xffff 19547 #define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_ALIGN 0 19548 #define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_BITS 16 19549 #define AN73_PDET_PARDET10GSIGDET_PD_SD_COUNT_SHIFT 0 19550 19551 19552 /**************************************************************************** 19553 * AN73_pdet :: parDet10GLink 19554 */ 19555 /* AN73_pdet :: parDet10GLink :: pd_link_count [15:00] */ 19556 #define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_MASK 0xffff 19557 #define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_ALIGN 0 19558 #define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_BITS 16 19559 #define AN73_PDET_PARDET10GLINK_PD_LINK_COUNT_SHIFT 0 19560 19561 19562 /**************************************************************************** 19563 * AN73_pdet :: parDet10GLostLink 19564 */ 19565 /* AN73_pdet :: parDet10GLostLink :: pd_lostlink_count [15:00] */ 19566 #define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_MASK 0xffff 19567 #define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_ALIGN 0 19568 #define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_BITS 16 19569 #define AN73_PDET_PARDET10GLOSTLINK_PD_LOSTLINK_COUNT_SHIFT 0 19570 19571 19572 /**************************************************************************** 19573 * AN73_pdet :: cl73Control1 19574 */ 19575 /* AN73_pdet :: cl73Control1 :: reserved0 [15:08] */ 19576 #define AN73_PDET_CL73CONTROL1_RESERVED0_MASK 0xff00 19577 #define AN73_PDET_CL73CONTROL1_RESERVED0_ALIGN 0 19578 #define AN73_PDET_CL73CONTROL1_RESERVED0_BITS 8 19579 #define AN73_PDET_CL73CONTROL1_RESERVED0_SHIFT 8 19580 19581 /* AN73_pdet :: cl73Control1 :: cl73_internal_10us_timer_val [07:00] */ 19582 #define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_MASK 0x00ff 19583 #define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_ALIGN 0 19584 #define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_BITS 8 19585 #define AN73_PDET_CL73CONTROL1_CL73_INTERNAL_10US_TIMER_VAL_SHIFT 0 19586 19587 19588 /**************************************************************************** 19589 * AN73_pdet :: cl73Control2 19590 */ 19591 /* AN73_pdet :: cl73Control2 :: reserved0 [15:13] */ 19592 #define AN73_PDET_CL73CONTROL2_RESERVED0_MASK 0xe000 19593 #define AN73_PDET_CL73CONTROL2_RESERVED0_ALIGN 0 19594 #define AN73_PDET_CL73CONTROL2_RESERVED0_BITS 3 19595 #define AN73_PDET_CL73CONTROL2_RESERVED0_SHIFT 13 19596 19597 /* AN73_pdet :: cl73Control2 :: cl73_link_fail_inhibit_timer_val [12:00] */ 19598 #define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_MASK 0x1fff 19599 #define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_ALIGN 0 19600 #define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_BITS 13 19601 #define AN73_PDET_CL73CONTROL2_CL73_LINK_FAIL_INHIBIT_TIMER_VAL_SHIFT 0 19602 19603 19604 /**************************************************************************** 19605 * AN73_pdet :: cl73Control3 19606 */ 19607 /* AN73_pdet :: cl73Control3 :: reserved0 [15:13] */ 19608 #define AN73_PDET_CL73CONTROL3_RESERVED0_MASK 0xe000 19609 #define AN73_PDET_CL73CONTROL3_RESERVED0_ALIGN 0 19610 #define AN73_PDET_CL73CONTROL3_RESERVED0_BITS 3 19611 #define AN73_PDET_CL73CONTROL3_RESERVED0_SHIFT 13 19612 19613 /* AN73_pdet :: cl73Control3 :: cl73_an_wait_timer_val [12:00] */ 19614 #define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_MASK 0x1fff 19615 #define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_ALIGN 0 19616 #define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_BITS 13 19617 #define AN73_PDET_CL73CONTROL3_CL73_AN_WAIT_TIMER_VAL_SHIFT 0 19618 19619 19620 /**************************************************************************** 19621 * AN73_pdet :: cl73Control4 19622 */ 19623 /* AN73_pdet :: cl73Control4 :: reserved0 [15:13] */ 19624 #define AN73_PDET_CL73CONTROL4_RESERVED0_MASK 0xe000 19625 #define AN73_PDET_CL73CONTROL4_RESERVED0_ALIGN 0 19626 #define AN73_PDET_CL73CONTROL4_RESERVED0_BITS 3 19627 #define AN73_PDET_CL73CONTROL4_RESERVED0_SHIFT 13 19628 19629 /* AN73_pdet :: cl73Control4 :: cl73_break_link_timer_val [12:00] */ 19630 #define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_MASK 0x1fff 19631 #define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_ALIGN 0 19632 #define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_BITS 13 19633 #define AN73_PDET_CL73CONTROL4_CL73_BREAK_LINK_TIMER_VAL_SHIFT 0 19634 19635 19636 /**************************************************************************** 19637 * AN73_pdet :: cl73Control5 19638 */ 19639 /* AN73_pdet :: cl73Control5 :: reserved0 [15:13] */ 19640 #define AN73_PDET_CL73CONTROL5_RESERVED0_MASK 0xe000 19641 #define AN73_PDET_CL73CONTROL5_RESERVED0_ALIGN 0 19642 #define AN73_PDET_CL73CONTROL5_RESERVED0_BITS 3 19643 #define AN73_PDET_CL73CONTROL5_RESERVED0_SHIFT 13 19644 19645 /* AN73_pdet :: cl73Control5 :: cl73_link_fail_inhibit_timer_bam_val [12:00] */ 19646 #define AN73_PDET_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_MASK 0x1fff 19647 #define AN73_PDET_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_ALIGN 0 19648 #define AN73_PDET_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_BITS 13 19649 #define AN73_PDET_CL73CONTROL5_CL73_LINK_FAIL_INHIBIT_TIMER_BAM_VAL_SHIFT 0 19650 19651 19652 /**************************************************************************** 19653 * AN73_pdet :: cl73Control6 19654 */ 19655 /* AN73_pdet :: cl73Control6 :: reserved0 [15:13] */ 19656 #define AN73_PDET_CL73CONTROL6_RESERVED0_MASK 0xe000 19657 #define AN73_PDET_CL73CONTROL6_RESERVED0_ALIGN 0 19658 #define AN73_PDET_CL73CONTROL6_RESERVED0_BITS 3 19659 #define AN73_PDET_CL73CONTROL6_RESERVED0_SHIFT 13 19660 19661 /* AN73_pdet :: cl73Control6 :: cl73_ignore_link_timer_val [12:00] */ 19662 #define AN73_PDET_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_MASK 0x1fff 19663 #define AN73_PDET_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_ALIGN 0 19664 #define AN73_PDET_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_BITS 13 19665 #define AN73_PDET_CL73CONTROL6_CL73_IGNORE_LINK_TIMER_VAL_SHIFT 0 19666 19667 19668 /**************************************************************************** 19669 * AN73_pdet :: cl73DmeTmrs 19670 */ 19671 /* AN73_pdet :: cl73DmeTmrs :: cl73_dme_page_test_max_cnt_val [15:08] */ 19672 #define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_MASK 0xff00 19673 #define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_ALIGN 0 19674 #define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_BITS 8 19675 #define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MAX_CNT_VAL_SHIFT 8 19676 19677 /* AN73_pdet :: cl73DmeTmrs :: cl73_dme_page_test_min_cnt_val [07:00] */ 19678 #define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_MASK 0x00ff 19679 #define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_ALIGN 0 19680 #define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_BITS 8 19681 #define AN73_PDET_CL73DMETMRS_CL73_DME_PAGE_TEST_MIN_CNT_VAL_SHIFT 0 19682 19683 19684 /**************************************************************************** 19685 * AN73_pdet :: xgxsStatus4 19686 */ 19687 /* AN73_pdet :: xgxsStatus4 :: reserved0 [15:15] */ 19688 #define AN73_PDET_XGXSSTATUS4_RESERVED0_MASK 0x8000 19689 #define AN73_PDET_XGXSSTATUS4_RESERVED0_ALIGN 0 19690 #define AN73_PDET_XGXSSTATUS4_RESERVED0_BITS 1 19691 #define AN73_PDET_XGXSSTATUS4_RESERVED0_SHIFT 15 19692 19693 /* AN73_pdet :: xgxsStatus4 :: sgmii_mode [14:14] */ 19694 #define AN73_PDET_XGXSSTATUS4_SGMII_MODE_MASK 0x4000 19695 #define AN73_PDET_XGXSSTATUS4_SGMII_MODE_ALIGN 0 19696 #define AN73_PDET_XGXSSTATUS4_SGMII_MODE_BITS 1 19697 #define AN73_PDET_XGXSSTATUS4_SGMII_MODE_SHIFT 14 19698 19699 /* AN73_pdet :: xgxsStatus4 :: link10g [13:13] */ 19700 #define AN73_PDET_XGXSSTATUS4_LINK10G_MASK 0x2000 19701 #define AN73_PDET_XGXSSTATUS4_LINK10G_ALIGN 0 19702 #define AN73_PDET_XGXSSTATUS4_LINK10G_BITS 1 19703 #define AN73_PDET_XGXSSTATUS4_LINK10G_SHIFT 13 19704 19705 /* AN73_pdet :: xgxsStatus4 :: link_status [12:12] */ 19706 #define AN73_PDET_XGXSSTATUS4_LINK_STATUS_MASK 0x1000 19707 #define AN73_PDET_XGXSSTATUS4_LINK_STATUS_ALIGN 0 19708 #define AN73_PDET_XGXSSTATUS4_LINK_STATUS_BITS 1 19709 #define AN73_PDET_XGXSSTATUS4_LINK_STATUS_SHIFT 12 19710 19711 /* AN73_pdet :: xgxsStatus4 :: pll_mode_afe [11:08] */ 19712 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_MASK 0x0f00 19713 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_ALIGN 0 19714 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_BITS 4 19715 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_SHIFT 8 19716 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div16 0 19717 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div20 1 19718 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div24 2 19719 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div26 3 19720 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div30 4 19721 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div32 5 19722 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div36 6 19723 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div40 7 19724 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div42 8 19725 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div48 9 19726 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div50 10 19727 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div52 11 19728 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div60 12 19729 #define AN73_PDET_XGXSSTATUS4_PLL_MODE_AFE_div64 13 19730 19731 /* AN73_pdet :: xgxsStatus4 :: reserved1 [07:06] */ 19732 #define AN73_PDET_XGXSSTATUS4_RESERVED1_MASK 0x00c0 19733 #define AN73_PDET_XGXSSTATUS4_RESERVED1_ALIGN 0 19734 #define AN73_PDET_XGXSSTATUS4_RESERVED1_BITS 2 19735 #define AN73_PDET_XGXSSTATUS4_RESERVED1_SHIFT 6 19736 19737 /* AN73_pdet :: xgxsStatus4 :: actual_speed_ln0 [05:00] */ 19738 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_MASK 0x003f 19739 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_ALIGN 0 19740 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_BITS 6 19741 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_SHIFT 0 19742 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10M 0 19743 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_100M 1 19744 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_1G 2 19745 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_2p5G 3 19746 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G_X4 4 19747 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6G_X4 5 19748 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG 6 19749 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_CX4 7 19750 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12G_HiG 8 19751 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p5G_X4 9 19752 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_13G_X4 10 19753 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_15G_X4 11 19754 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_16G_X4 12 19755 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G 16 19756 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_6p4G 17 19757 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_20G_X4 18 19758 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_21G_X4 19 19759 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_25G_X4 20 19760 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_HiG_DXGXS 21 19761 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10G_DXGXS 22 19762 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p5G_HiG_DXGXS 23 19763 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_10p5G_DXGXS 24 19764 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p773G_HiG_DXGXS 25 19765 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_12p773G_DXGXS 26 19766 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G_HiG_DXGXS 42 19767 #define AN73_PDET_XGXSSTATUS4_ACTUAL_SPEED_LN0_dr_5G_DXGXS 43 19768 19769 /**************************************************************************** 19770 * AN73_pdet :: xgxsStatus5 19771 */ 19772 /* AN73_pdet :: xgxsStatus5 :: tx1g_mode_ln3 [15:14] */ 19773 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_MASK 0xc000 19774 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_ALIGN 0 19775 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_BITS 2 19776 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_SHIFT 14 19777 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_SWSDR_div2 0 19778 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_SWSDR_div1 1 19779 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_DWSDR_div2 2 19780 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN3_DWSDR_div1 3 19781 19782 /* AN73_pdet :: xgxsStatus5 :: tx1g_mode_ln2 [13:12] */ 19783 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_MASK 0x3000 19784 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_ALIGN 0 19785 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_BITS 2 19786 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_SHIFT 12 19787 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_SWSDR_div2 0 19788 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_SWSDR_div1 1 19789 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_DWSDR_div2 2 19790 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN2_DWSDR_div1 3 19791 19792 /* AN73_pdet :: xgxsStatus5 :: tx1g_mode_ln1 [11:10] */ 19793 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_MASK 0x0c00 19794 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_ALIGN 0 19795 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_BITS 2 19796 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_SHIFT 10 19797 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_SWSDR_div2 0 19798 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_SWSDR_div1 1 19799 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_DWSDR_div2 2 19800 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN1_DWSDR_div1 3 19801 19802 /* AN73_pdet :: xgxsStatus5 :: tx1g_mode_ln0 [09:08] */ 19803 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_MASK 0x0300 19804 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_ALIGN 0 19805 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_BITS 2 19806 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_SHIFT 8 19807 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_SWSDR_div2 0 19808 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_SWSDR_div1 1 19809 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_DWSDR_div2 2 19810 #define AN73_PDET_XGXSSTATUS5_TX1G_MODE_LN0_DWSDR_div1 3 19811 19812 /* AN73_pdet :: xgxsStatus5 :: rx1g_mode_ln3 [07:06] */ 19813 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_MASK 0x00c0 19814 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_ALIGN 0 19815 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_BITS 2 19816 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_SHIFT 6 19817 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_SWSDR_div2 0 19818 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_SWSDR_div1 1 19819 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_DWSDR_div2 2 19820 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN3_DWSDR_div1 3 19821 19822 /* AN73_pdet :: xgxsStatus5 :: rx1g_mode_ln2 [05:04] */ 19823 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_MASK 0x0030 19824 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_ALIGN 0 19825 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_BITS 2 19826 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_SHIFT 4 19827 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_SWSDR_div2 0 19828 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_SWSDR_div1 1 19829 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_DWSDR_div2 2 19830 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN2_DWSDR_div1 3 19831 19832 /* AN73_pdet :: xgxsStatus5 :: rx1g_mode_ln1 [03:02] */ 19833 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_MASK 0x000c 19834 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_ALIGN 0 19835 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_BITS 2 19836 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_SHIFT 2 19837 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_SWSDR_div2 0 19838 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_SWSDR_div1 1 19839 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_DWSDR_div2 2 19840 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN1_DWSDR_div1 3 19841 19842 /* AN73_pdet :: xgxsStatus5 :: rx1g_mode_ln0 [01:00] */ 19843 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_MASK 0x0003 19844 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_ALIGN 0 19845 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_BITS 2 19846 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_SHIFT 0 19847 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_SWSDR_div2 0 19848 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_SWSDR_div1 1 19849 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_DWSDR_div2 2 19850 #define AN73_PDET_XGXSSTATUS5_RX1G_MODE_LN0_DWSDR_div1 3 19851 19852 19853 /**************************************************************************** 19854 * AN73_pdet :: parDet10GControl2 19855 */ 19856 /* AN73_pdet :: parDet10GControl2 :: reserved0 [15:04] */ 19857 #define AN73_PDET_PARDET10GCONTROL2_RESERVED0_MASK 0xfff0 19858 #define AN73_PDET_PARDET10GCONTROL2_RESERVED0_ALIGN 0 19859 #define AN73_PDET_PARDET10GCONTROL2_RESERVED0_BITS 12 19860 #define AN73_PDET_PARDET10GCONTROL2_RESERVED0_SHIFT 4 19861 19862 /* AN73_pdet :: parDet10GControl2 :: pd_parkFail [03:03] */ 19863 #define AN73_PDET_PARDET10GCONTROL2_PD_PARKFAIL_MASK 0x0008 19864 #define AN73_PDET_PARDET10GCONTROL2_PD_PARKFAIL_ALIGN 0 19865 #define AN73_PDET_PARDET10GCONTROL2_PD_PARKFAIL_BITS 1 19866 #define AN73_PDET_PARDET10GCONTROL2_PD_PARKFAIL_SHIFT 3 19867 19868 /* AN73_pdet :: parDet10GControl2 :: pd_useLinkStatus [02:02] */ 19869 #define AN73_PDET_PARDET10GCONTROL2_PD_USELINKSTATUS_MASK 0x0004 19870 #define AN73_PDET_PARDET10GCONTROL2_PD_USELINKSTATUS_ALIGN 0 19871 #define AN73_PDET_PARDET10GCONTROL2_PD_USELINKSTATUS_BITS 1 19872 #define AN73_PDET_PARDET10GCONTROL2_PD_USELINKSTATUS_SHIFT 2 19873 19874 /* AN73_pdet :: parDet10GControl2 :: pd_cl73_couple_dis [01:01] */ 19875 #define AN73_PDET_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_MASK 0x0002 19876 #define AN73_PDET_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_ALIGN 0 19877 #define AN73_PDET_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_BITS 1 19878 #define AN73_PDET_PARDET10GCONTROL2_PD_CL73_COUPLE_DIS_SHIFT 1 19879 19880 /* AN73_pdet :: parDet10GControl2 :: pd_IgnoreLink_dis [00:00] */ 19881 #define AN73_PDET_PARDET10GCONTROL2_PD_IGNORELINK_DIS_MASK 0x0001 19882 #define AN73_PDET_PARDET10GCONTROL2_PD_IGNORELINK_DIS_ALIGN 0 19883 #define AN73_PDET_PARDET10GCONTROL2_PD_IGNORELINK_DIS_BITS 1 19884 #define AN73_PDET_PARDET10GCONTROL2_PD_IGNORELINK_DIS_SHIFT 0 19885 19886 19887 /**************************************************************************** 19888 * Hypercore_USER_tx66_0 19889 */ 19890 /**************************************************************************** 19891 * tx66_0 :: Control 19892 */ 19893 /* tx66_0 :: Control :: reserved_for_eco0 [15:04] */ 19894 #define TX66_0_CONTROL_RESERVED_FOR_ECO0_MASK 0xfff0 19895 #define TX66_0_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 19896 #define TX66_0_CONTROL_RESERVED_FOR_ECO0_BITS 12 19897 #define TX66_0_CONTROL_RESERVED_FOR_ECO0_SHIFT 4 19898 19899 /* tx66_0 :: Control :: scramblerControl [03:02] */ 19900 #define TX66_0_CONTROL_SCRAMBLERCONTROL_MASK 0x000c 19901 #define TX66_0_CONTROL_SCRAMBLERCONTROL_ALIGN 0 19902 #define TX66_0_CONTROL_SCRAMBLERCONTROL_BITS 2 19903 #define TX66_0_CONTROL_SCRAMBLERCONTROL_SHIFT 2 19904 19905 /* tx66_0 :: Control :: tfifo_sbitclr [01:01] */ 19906 #define TX66_0_CONTROL_TFIFO_SBITCLR_MASK 0x0002 19907 #define TX66_0_CONTROL_TFIFO_SBITCLR_ALIGN 0 19908 #define TX66_0_CONTROL_TFIFO_SBITCLR_BITS 1 19909 #define TX66_0_CONTROL_TFIFO_SBITCLR_SHIFT 1 19910 19911 /* tx66_0 :: Control :: tfifo_afrst_en [00:00] */ 19912 #define TX66_0_CONTROL_TFIFO_AFRST_EN_MASK 0x0001 19913 #define TX66_0_CONTROL_TFIFO_AFRST_EN_ALIGN 0 19914 #define TX66_0_CONTROL_TFIFO_AFRST_EN_BITS 1 19915 #define TX66_0_CONTROL_TFIFO_AFRST_EN_SHIFT 0 19916 19917 19918 /**************************************************************************** 19919 * tx66_0 :: Status 19920 */ 19921 /* tx66_0 :: Status :: reserved_for_eco0 [15:03] */ 19922 #define TX66_0_STATUS_RESERVED_FOR_ECO0_MASK 0xfff8 19923 #define TX66_0_STATUS_RESERVED_FOR_ECO0_ALIGN 0 19924 #define TX66_0_STATUS_RESERVED_FOR_ECO0_BITS 13 19925 #define TX66_0_STATUS_RESERVED_FOR_ECO0_SHIFT 3 19926 19927 /* tx66_0 :: Status :: ovflow [02:02] */ 19928 #define TX66_0_STATUS_OVFLOW_MASK 0x0004 19929 #define TX66_0_STATUS_OVFLOW_ALIGN 0 19930 #define TX66_0_STATUS_OVFLOW_BITS 1 19931 #define TX66_0_STATUS_OVFLOW_SHIFT 2 19932 19933 /* tx66_0 :: Status :: unflow [01:01] */ 19934 #define TX66_0_STATUS_UNFLOW_MASK 0x0002 19935 #define TX66_0_STATUS_UNFLOW_ALIGN 0 19936 #define TX66_0_STATUS_UNFLOW_BITS 1 19937 #define TX66_0_STATUS_UNFLOW_SHIFT 1 19938 19939 /* tx66_0 :: Status :: ferr [00:00] */ 19940 #define TX66_0_STATUS_FERR_MASK 0x0001 19941 #define TX66_0_STATUS_FERR_ALIGN 0 19942 #define TX66_0_STATUS_FERR_BITS 1 19943 #define TX66_0_STATUS_FERR_SHIFT 0 19944 19945 19946 /**************************************************************************** 19947 * Hypercore_USER_tx66_1 19948 */ 19949 /**************************************************************************** 19950 * tx66_1 :: Control 19951 */ 19952 /* tx66_1 :: Control :: reserved_for_eco0 [15:04] */ 19953 #define TX66_1_CONTROL_RESERVED_FOR_ECO0_MASK 0xfff0 19954 #define TX66_1_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 19955 #define TX66_1_CONTROL_RESERVED_FOR_ECO0_BITS 12 19956 #define TX66_1_CONTROL_RESERVED_FOR_ECO0_SHIFT 4 19957 19958 /* tx66_1 :: Control :: scramblerControl [03:02] */ 19959 #define TX66_1_CONTROL_SCRAMBLERCONTROL_MASK 0x000c 19960 #define TX66_1_CONTROL_SCRAMBLERCONTROL_ALIGN 0 19961 #define TX66_1_CONTROL_SCRAMBLERCONTROL_BITS 2 19962 #define TX66_1_CONTROL_SCRAMBLERCONTROL_SHIFT 2 19963 19964 /* tx66_1 :: Control :: tfifo_sbitclr [01:01] */ 19965 #define TX66_1_CONTROL_TFIFO_SBITCLR_MASK 0x0002 19966 #define TX66_1_CONTROL_TFIFO_SBITCLR_ALIGN 0 19967 #define TX66_1_CONTROL_TFIFO_SBITCLR_BITS 1 19968 #define TX66_1_CONTROL_TFIFO_SBITCLR_SHIFT 1 19969 19970 /* tx66_1 :: Control :: tfifo_afrst_en [00:00] */ 19971 #define TX66_1_CONTROL_TFIFO_AFRST_EN_MASK 0x0001 19972 #define TX66_1_CONTROL_TFIFO_AFRST_EN_ALIGN 0 19973 #define TX66_1_CONTROL_TFIFO_AFRST_EN_BITS 1 19974 #define TX66_1_CONTROL_TFIFO_AFRST_EN_SHIFT 0 19975 19976 19977 /**************************************************************************** 19978 * tx66_1 :: Status 19979 */ 19980 /* tx66_1 :: Status :: reserved_for_eco0 [15:03] */ 19981 #define TX66_1_STATUS_RESERVED_FOR_ECO0_MASK 0xfff8 19982 #define TX66_1_STATUS_RESERVED_FOR_ECO0_ALIGN 0 19983 #define TX66_1_STATUS_RESERVED_FOR_ECO0_BITS 13 19984 #define TX66_1_STATUS_RESERVED_FOR_ECO0_SHIFT 3 19985 19986 /* tx66_1 :: Status :: ovflow [02:02] */ 19987 #define TX66_1_STATUS_OVFLOW_MASK 0x0004 19988 #define TX66_1_STATUS_OVFLOW_ALIGN 0 19989 #define TX66_1_STATUS_OVFLOW_BITS 1 19990 #define TX66_1_STATUS_OVFLOW_SHIFT 2 19991 19992 /* tx66_1 :: Status :: unflow [01:01] */ 19993 #define TX66_1_STATUS_UNFLOW_MASK 0x0002 19994 #define TX66_1_STATUS_UNFLOW_ALIGN 0 19995 #define TX66_1_STATUS_UNFLOW_BITS 1 19996 #define TX66_1_STATUS_UNFLOW_SHIFT 1 19997 19998 /* tx66_1 :: Status :: ferr [00:00] */ 19999 #define TX66_1_STATUS_FERR_MASK 0x0001 20000 #define TX66_1_STATUS_FERR_ALIGN 0 20001 #define TX66_1_STATUS_FERR_BITS 1 20002 #define TX66_1_STATUS_FERR_SHIFT 0 20003 20004 20005 /**************************************************************************** 20006 * Hypercore_USER_tx66_2 20007 */ 20008 /**************************************************************************** 20009 * tx66_2 :: Control 20010 */ 20011 /* tx66_2 :: Control :: reserved_for_eco0 [15:04] */ 20012 #define TX66_2_CONTROL_RESERVED_FOR_ECO0_MASK 0xfff0 20013 #define TX66_2_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 20014 #define TX66_2_CONTROL_RESERVED_FOR_ECO0_BITS 12 20015 #define TX66_2_CONTROL_RESERVED_FOR_ECO0_SHIFT 4 20016 20017 /* tx66_2 :: Control :: scramblerControl [03:02] */ 20018 #define TX66_2_CONTROL_SCRAMBLERCONTROL_MASK 0x000c 20019 #define TX66_2_CONTROL_SCRAMBLERCONTROL_ALIGN 0 20020 #define TX66_2_CONTROL_SCRAMBLERCONTROL_BITS 2 20021 #define TX66_2_CONTROL_SCRAMBLERCONTROL_SHIFT 2 20022 20023 /* tx66_2 :: Control :: tfifo_sbitclr [01:01] */ 20024 #define TX66_2_CONTROL_TFIFO_SBITCLR_MASK 0x0002 20025 #define TX66_2_CONTROL_TFIFO_SBITCLR_ALIGN 0 20026 #define TX66_2_CONTROL_TFIFO_SBITCLR_BITS 1 20027 #define TX66_2_CONTROL_TFIFO_SBITCLR_SHIFT 1 20028 20029 /* tx66_2 :: Control :: tfifo_afrst_en [00:00] */ 20030 #define TX66_2_CONTROL_TFIFO_AFRST_EN_MASK 0x0001 20031 #define TX66_2_CONTROL_TFIFO_AFRST_EN_ALIGN 0 20032 #define TX66_2_CONTROL_TFIFO_AFRST_EN_BITS 1 20033 #define TX66_2_CONTROL_TFIFO_AFRST_EN_SHIFT 0 20034 20035 20036 /**************************************************************************** 20037 * tx66_2 :: Status 20038 */ 20039 /* tx66_2 :: Status :: reserved_for_eco0 [15:03] */ 20040 #define TX66_2_STATUS_RESERVED_FOR_ECO0_MASK 0xfff8 20041 #define TX66_2_STATUS_RESERVED_FOR_ECO0_ALIGN 0 20042 #define TX66_2_STATUS_RESERVED_FOR_ECO0_BITS 13 20043 #define TX66_2_STATUS_RESERVED_FOR_ECO0_SHIFT 3 20044 20045 /* tx66_2 :: Status :: ovflow [02:02] */ 20046 #define TX66_2_STATUS_OVFLOW_MASK 0x0004 20047 #define TX66_2_STATUS_OVFLOW_ALIGN 0 20048 #define TX66_2_STATUS_OVFLOW_BITS 1 20049 #define TX66_2_STATUS_OVFLOW_SHIFT 2 20050 20051 /* tx66_2 :: Status :: unflow [01:01] */ 20052 #define TX66_2_STATUS_UNFLOW_MASK 0x0002 20053 #define TX66_2_STATUS_UNFLOW_ALIGN 0 20054 #define TX66_2_STATUS_UNFLOW_BITS 1 20055 #define TX66_2_STATUS_UNFLOW_SHIFT 1 20056 20057 /* tx66_2 :: Status :: ferr [00:00] */ 20058 #define TX66_2_STATUS_FERR_MASK 0x0001 20059 #define TX66_2_STATUS_FERR_ALIGN 0 20060 #define TX66_2_STATUS_FERR_BITS 1 20061 #define TX66_2_STATUS_FERR_SHIFT 0 20062 20063 20064 /**************************************************************************** 20065 * Hypercore_USER_tx66_3 20066 */ 20067 /**************************************************************************** 20068 * tx66_3 :: Control 20069 */ 20070 /* tx66_3 :: Control :: reserved_for_eco0 [15:04] */ 20071 #define TX66_3_CONTROL_RESERVED_FOR_ECO0_MASK 0xfff0 20072 #define TX66_3_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 20073 #define TX66_3_CONTROL_RESERVED_FOR_ECO0_BITS 12 20074 #define TX66_3_CONTROL_RESERVED_FOR_ECO0_SHIFT 4 20075 20076 /* tx66_3 :: Control :: scramblerControl [03:02] */ 20077 #define TX66_3_CONTROL_SCRAMBLERCONTROL_MASK 0x000c 20078 #define TX66_3_CONTROL_SCRAMBLERCONTROL_ALIGN 0 20079 #define TX66_3_CONTROL_SCRAMBLERCONTROL_BITS 2 20080 #define TX66_3_CONTROL_SCRAMBLERCONTROL_SHIFT 2 20081 20082 /* tx66_3 :: Control :: tfifo_sbitclr [01:01] */ 20083 #define TX66_3_CONTROL_TFIFO_SBITCLR_MASK 0x0002 20084 #define TX66_3_CONTROL_TFIFO_SBITCLR_ALIGN 0 20085 #define TX66_3_CONTROL_TFIFO_SBITCLR_BITS 1 20086 #define TX66_3_CONTROL_TFIFO_SBITCLR_SHIFT 1 20087 20088 /* tx66_3 :: Control :: tfifo_afrst_en [00:00] */ 20089 #define TX66_3_CONTROL_TFIFO_AFRST_EN_MASK 0x0001 20090 #define TX66_3_CONTROL_TFIFO_AFRST_EN_ALIGN 0 20091 #define TX66_3_CONTROL_TFIFO_AFRST_EN_BITS 1 20092 #define TX66_3_CONTROL_TFIFO_AFRST_EN_SHIFT 0 20093 20094 20095 /**************************************************************************** 20096 * tx66_3 :: Status 20097 */ 20098 /* tx66_3 :: Status :: reserved_for_eco0 [15:03] */ 20099 #define TX66_3_STATUS_RESERVED_FOR_ECO0_MASK 0xfff8 20100 #define TX66_3_STATUS_RESERVED_FOR_ECO0_ALIGN 0 20101 #define TX66_3_STATUS_RESERVED_FOR_ECO0_BITS 13 20102 #define TX66_3_STATUS_RESERVED_FOR_ECO0_SHIFT 3 20103 20104 /* tx66_3 :: Status :: ovflow [02:02] */ 20105 #define TX66_3_STATUS_OVFLOW_MASK 0x0004 20106 #define TX66_3_STATUS_OVFLOW_ALIGN 0 20107 #define TX66_3_STATUS_OVFLOW_BITS 1 20108 #define TX66_3_STATUS_OVFLOW_SHIFT 2 20109 20110 /* tx66_3 :: Status :: unflow [01:01] */ 20111 #define TX66_3_STATUS_UNFLOW_MASK 0x0002 20112 #define TX66_3_STATUS_UNFLOW_ALIGN 0 20113 #define TX66_3_STATUS_UNFLOW_BITS 1 20114 #define TX66_3_STATUS_UNFLOW_SHIFT 1 20115 20116 /* tx66_3 :: Status :: ferr [00:00] */ 20117 #define TX66_3_STATUS_FERR_MASK 0x0001 20118 #define TX66_3_STATUS_FERR_ALIGN 0 20119 #define TX66_3_STATUS_FERR_BITS 1 20120 #define TX66_3_STATUS_FERR_SHIFT 0 20121 20122 20123 /**************************************************************************** 20124 * Hypercore_USER_tx66_A 20125 */ 20126 /**************************************************************************** 20127 * tx66_A :: Control 20128 */ 20129 /* tx66_A :: Control :: reserved_for_eco0 [15:04] */ 20130 #define TX66_A_CONTROL_RESERVED_FOR_ECO0_MASK 0xfff0 20131 #define TX66_A_CONTROL_RESERVED_FOR_ECO0_ALIGN 0 20132 #define TX66_A_CONTROL_RESERVED_FOR_ECO0_BITS 12 20133 #define TX66_A_CONTROL_RESERVED_FOR_ECO0_SHIFT 4 20134 20135 /* tx66_A :: Control :: scramblerControl [03:02] */ 20136 #define TX66_A_CONTROL_SCRAMBLERCONTROL_MASK 0x000c 20137 #define TX66_A_CONTROL_SCRAMBLERCONTROL_ALIGN 0 20138 #define TX66_A_CONTROL_SCRAMBLERCONTROL_BITS 2 20139 #define TX66_A_CONTROL_SCRAMBLERCONTROL_SHIFT 2 20140 20141 /* tx66_A :: Control :: tfifo_sbitclr [01:01] */ 20142 #define TX66_A_CONTROL_TFIFO_SBITCLR_MASK 0x0002 20143 #define TX66_A_CONTROL_TFIFO_SBITCLR_ALIGN 0 20144 #define TX66_A_CONTROL_TFIFO_SBITCLR_BITS 1 20145 #define TX66_A_CONTROL_TFIFO_SBITCLR_SHIFT 1 20146 20147 /* tx66_A :: Control :: tfifo_afrst_en [00:00] */ 20148 #define TX66_A_CONTROL_TFIFO_AFRST_EN_MASK 0x0001 20149 #define TX66_A_CONTROL_TFIFO_AFRST_EN_ALIGN 0 20150 #define TX66_A_CONTROL_TFIFO_AFRST_EN_BITS 1 20151 #define TX66_A_CONTROL_TFIFO_AFRST_EN_SHIFT 0 20152 20153 20154 /**************************************************************************** 20155 * tx66_A :: Status 20156 */ 20157 /* tx66_A :: Status :: reserved_for_eco0 [15:03] */ 20158 #define TX66_A_STATUS_RESERVED_FOR_ECO0_MASK 0xfff8 20159 #define TX66_A_STATUS_RESERVED_FOR_ECO0_ALIGN 0 20160 #define TX66_A_STATUS_RESERVED_FOR_ECO0_BITS 13 20161 #define TX66_A_STATUS_RESERVED_FOR_ECO0_SHIFT 3 20162 20163 /* tx66_A :: Status :: ovflow [02:02] */ 20164 #define TX66_A_STATUS_OVFLOW_MASK 0x0004 20165 #define TX66_A_STATUS_OVFLOW_ALIGN 0 20166 #define TX66_A_STATUS_OVFLOW_BITS 1 20167 #define TX66_A_STATUS_OVFLOW_SHIFT 2 20168 20169 /* tx66_A :: Status :: unflow [01:01] */ 20170 #define TX66_A_STATUS_UNFLOW_MASK 0x0002 20171 #define TX66_A_STATUS_UNFLOW_ALIGN 0 20172 #define TX66_A_STATUS_UNFLOW_BITS 1 20173 #define TX66_A_STATUS_UNFLOW_SHIFT 1 20174 20175 /* tx66_A :: Status :: ferr [00:00] */ 20176 #define TX66_A_STATUS_FERR_MASK 0x0001 20177 #define TX66_A_STATUS_FERR_ALIGN 0 20178 #define TX66_A_STATUS_FERR_BITS 1 20179 #define TX66_A_STATUS_FERR_SHIFT 0 20180 20181 20182 /**************************************************************************** 20183 * Hypercore_USER_rx66_0 20184 */ 20185 /**************************************************************************** 20186 * rx66_0 :: Control 20187 */ 20188 /* rx66_0 :: Control :: reserved0 [15:10] */ 20189 #define RX66_0_CONTROL_RESERVED0_MASK 0xfc00 20190 #define RX66_0_CONTROL_RESERVED0_ALIGN 0 20191 #define RX66_0_CONTROL_RESERVED0_BITS 6 20192 #define RX66_0_CONTROL_RESERVED0_SHIFT 10 20193 20194 /* rx66_0 :: Control :: rxSeqDoneMask [09:09] */ 20195 #define RX66_0_CONTROL_RXSEQDONEMASK_MASK 0x0200 20196 #define RX66_0_CONTROL_RXSEQDONEMASK_ALIGN 0 20197 #define RX66_0_CONTROL_RXSEQDONEMASK_BITS 1 20198 #define RX66_0_CONTROL_RXSEQDONEMASK_SHIFT 9 20199 20200 /* rx66_0 :: Control :: cwCount_sel [08:08] */ 20201 #define RX66_0_CONTROL_CWCOUNT_SEL_MASK 0x0100 20202 #define RX66_0_CONTROL_CWCOUNT_SEL_ALIGN 0 20203 #define RX66_0_CONTROL_CWCOUNT_SEL_BITS 1 20204 #define RX66_0_CONTROL_CWCOUNT_SEL_SHIFT 8 20205 20206 /* rx66_0 :: Control :: cwCount_en [07:07] */ 20207 #define RX66_0_CONTROL_CWCOUNT_EN_MASK 0x0080 20208 #define RX66_0_CONTROL_CWCOUNT_EN_ALIGN 0 20209 #define RX66_0_CONTROL_CWCOUNT_EN_BITS 1 20210 #define RX66_0_CONTROL_CWCOUNT_EN_SHIFT 7 20211 20212 /* rx66_0 :: Control :: sync66ErrCount_en [06:06] */ 20213 #define RX66_0_CONTROL_SYNC66ERRCOUNT_EN_MASK 0x0040 20214 #define RX66_0_CONTROL_SYNC66ERRCOUNT_EN_ALIGN 0 20215 #define RX66_0_CONTROL_SYNC66ERRCOUNT_EN_BITS 1 20216 #define RX66_0_CONTROL_SYNC66ERRCOUNT_EN_SHIFT 6 20217 20218 /* rx66_0 :: Control :: kcode66ErrCount_en [05:05] */ 20219 #define RX66_0_CONTROL_KCODE66ERRCOUNT_EN_MASK 0x0020 20220 #define RX66_0_CONTROL_KCODE66ERRCOUNT_EN_ALIGN 0 20221 #define RX66_0_CONTROL_KCODE66ERRCOUNT_EN_BITS 1 20222 #define RX66_0_CONTROL_KCODE66ERRCOUNT_EN_SHIFT 5 20223 20224 /* rx66_0 :: Control :: cgbad_kcode66Err_en [04:04] */ 20225 #define RX66_0_CONTROL_CGBAD_KCODE66ERR_EN_MASK 0x0010 20226 #define RX66_0_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN 0 20227 #define RX66_0_CONTROL_CGBAD_KCODE66ERR_EN_BITS 1 20228 #define RX66_0_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT 4 20229 20230 /* rx66_0 :: Control :: descramblerControl [03:02] */ 20231 #define RX66_0_CONTROL_DESCRAMBLERCONTROL_MASK 0x000c 20232 #define RX66_0_CONTROL_DESCRAMBLERCONTROL_ALIGN 0 20233 #define RX66_0_CONTROL_DESCRAMBLERCONTROL_BITS 2 20234 #define RX66_0_CONTROL_DESCRAMBLERCONTROL_SHIFT 2 20235 20236 /* rx66_0 :: Control :: rfifo_sbitclr [01:01] */ 20237 #define RX66_0_CONTROL_RFIFO_SBITCLR_MASK 0x0002 20238 #define RX66_0_CONTROL_RFIFO_SBITCLR_ALIGN 0 20239 #define RX66_0_CONTROL_RFIFO_SBITCLR_BITS 1 20240 #define RX66_0_CONTROL_RFIFO_SBITCLR_SHIFT 1 20241 20242 /* rx66_0 :: Control :: rfifo_afrst_en [00:00] */ 20243 #define RX66_0_CONTROL_RFIFO_AFRST_EN_MASK 0x0001 20244 #define RX66_0_CONTROL_RFIFO_AFRST_EN_ALIGN 0 20245 #define RX66_0_CONTROL_RFIFO_AFRST_EN_BITS 1 20246 #define RX66_0_CONTROL_RFIFO_AFRST_EN_SHIFT 0 20247 20248 20249 /**************************************************************************** 20250 * rx66_0 :: Status 20251 */ 20252 /* rx66_0 :: Status :: LOSS_OF_SYNC [15:15] */ 20253 #define RX66_0_STATUS_LOSS_OF_SYNC_MASK 0x8000 20254 #define RX66_0_STATUS_LOSS_OF_SYNC_ALIGN 0 20255 #define RX66_0_STATUS_LOSS_OF_SYNC_BITS 1 20256 #define RX66_0_STATUS_LOSS_OF_SYNC_SHIFT 15 20257 20258 /* rx66_0 :: Status :: COMMA_DETECT [14:14] */ 20259 #define RX66_0_STATUS_COMMA_DETECT_MASK 0x4000 20260 #define RX66_0_STATUS_COMMA_DETECT_ALIGN 0 20261 #define RX66_0_STATUS_COMMA_DETECT_BITS 1 20262 #define RX66_0_STATUS_COMMA_DETECT_SHIFT 14 20263 20264 /* rx66_0 :: Status :: SYNC_ACQD1 [13:13] */ 20265 #define RX66_0_STATUS_SYNC_ACQD1_MASK 0x2000 20266 #define RX66_0_STATUS_SYNC_ACQD1_ALIGN 0 20267 #define RX66_0_STATUS_SYNC_ACQD1_BITS 1 20268 #define RX66_0_STATUS_SYNC_ACQD1_SHIFT 13 20269 20270 /* rx66_0 :: Status :: SYNC_ACQD2 [12:12] */ 20271 #define RX66_0_STATUS_SYNC_ACQD2_MASK 0x1000 20272 #define RX66_0_STATUS_SYNC_ACQD2_ALIGN 0 20273 #define RX66_0_STATUS_SYNC_ACQD2_BITS 1 20274 #define RX66_0_STATUS_SYNC_ACQD2_SHIFT 12 20275 20276 /* rx66_0 :: Status :: reserved0 [11:04] */ 20277 #define RX66_0_STATUS_RESERVED0_MASK 0x0ff0 20278 #define RX66_0_STATUS_RESERVED0_ALIGN 0 20279 #define RX66_0_STATUS_RESERVED0_BITS 8 20280 #define RX66_0_STATUS_RESERVED0_SHIFT 4 20281 20282 /* rx66_0 :: Status :: syncDone [03:03] */ 20283 #define RX66_0_STATUS_SYNCDONE_MASK 0x0008 20284 #define RX66_0_STATUS_SYNCDONE_ALIGN 0 20285 #define RX66_0_STATUS_SYNCDONE_BITS 1 20286 #define RX66_0_STATUS_SYNCDONE_SHIFT 3 20287 20288 /* rx66_0 :: Status :: unflow [02:02] */ 20289 #define RX66_0_STATUS_UNFLOW_MASK 0x0004 20290 #define RX66_0_STATUS_UNFLOW_ALIGN 0 20291 #define RX66_0_STATUS_UNFLOW_BITS 1 20292 #define RX66_0_STATUS_UNFLOW_SHIFT 2 20293 20294 /* rx66_0 :: Status :: ovflow [01:01] */ 20295 #define RX66_0_STATUS_OVFLOW_MASK 0x0002 20296 #define RX66_0_STATUS_OVFLOW_ALIGN 0 20297 #define RX66_0_STATUS_OVFLOW_BITS 1 20298 #define RX66_0_STATUS_OVFLOW_SHIFT 1 20299 20300 /* rx66_0 :: Status :: ferr [00:00] */ 20301 #define RX66_0_STATUS_FERR_MASK 0x0001 20302 #define RX66_0_STATUS_FERR_ALIGN 0 20303 #define RX66_0_STATUS_FERR_BITS 1 20304 #define RX66_0_STATUS_FERR_SHIFT 0 20305 20306 20307 /**************************************************************************** 20308 * rx66_0 :: scw0 20309 */ 20310 /* rx66_0 :: scw0 :: scw0 [15:00] */ 20311 #define RX66_0_SCW0_SCW0_MASK 0xffff 20312 #define RX66_0_SCW0_SCW0_ALIGN 0 20313 #define RX66_0_SCW0_SCW0_BITS 16 20314 #define RX66_0_SCW0_SCW0_SHIFT 0 20315 20316 20317 /**************************************************************************** 20318 * rx66_0 :: scw1 20319 */ 20320 /* rx66_0 :: scw1 :: scw1 [15:00] */ 20321 #define RX66_0_SCW1_SCW1_MASK 0xffff 20322 #define RX66_0_SCW1_SCW1_ALIGN 0 20323 #define RX66_0_SCW1_SCW1_BITS 16 20324 #define RX66_0_SCW1_SCW1_SHIFT 0 20325 20326 20327 /**************************************************************************** 20328 * rx66_0 :: scw2 20329 */ 20330 /* rx66_0 :: scw2 :: scw2 [15:00] */ 20331 #define RX66_0_SCW2_SCW2_MASK 0xffff 20332 #define RX66_0_SCW2_SCW2_ALIGN 0 20333 #define RX66_0_SCW2_SCW2_BITS 16 20334 #define RX66_0_SCW2_SCW2_SHIFT 0 20335 20336 20337 /**************************************************************************** 20338 * rx66_0 :: scw3 20339 */ 20340 /* rx66_0 :: scw3 :: scw3 [15:00] */ 20341 #define RX66_0_SCW3_SCW3_MASK 0xffff 20342 #define RX66_0_SCW3_SCW3_ALIGN 0 20343 #define RX66_0_SCW3_SCW3_BITS 16 20344 #define RX66_0_SCW3_SCW3_SHIFT 0 20345 20346 20347 /**************************************************************************** 20348 * rx66_0 :: scw0_mask 20349 */ 20350 /* rx66_0 :: scw0_mask :: scw0_mask [15:00] */ 20351 #define RX66_0_SCW0_MASK_SCW0_MASK_MASK 0xffff 20352 #define RX66_0_SCW0_MASK_SCW0_MASK_ALIGN 0 20353 #define RX66_0_SCW0_MASK_SCW0_MASK_BITS 16 20354 #define RX66_0_SCW0_MASK_SCW0_MASK_SHIFT 0 20355 20356 20357 /**************************************************************************** 20358 * rx66_0 :: scw1_mask 20359 */ 20360 /* rx66_0 :: scw1_mask :: scw1_mask [15:00] */ 20361 #define RX66_0_SCW1_MASK_SCW1_MASK_MASK 0xffff 20362 #define RX66_0_SCW1_MASK_SCW1_MASK_ALIGN 0 20363 #define RX66_0_SCW1_MASK_SCW1_MASK_BITS 16 20364 #define RX66_0_SCW1_MASK_SCW1_MASK_SHIFT 0 20365 20366 20367 /**************************************************************************** 20368 * rx66_0 :: scw2_mask 20369 */ 20370 /* rx66_0 :: scw2_mask :: scw2_mask [15:00] */ 20371 #define RX66_0_SCW2_MASK_SCW2_MASK_MASK 0xffff 20372 #define RX66_0_SCW2_MASK_SCW2_MASK_ALIGN 0 20373 #define RX66_0_SCW2_MASK_SCW2_MASK_BITS 16 20374 #define RX66_0_SCW2_MASK_SCW2_MASK_SHIFT 0 20375 20376 20377 /**************************************************************************** 20378 * rx66_0 :: scw3_mask 20379 */ 20380 /* rx66_0 :: scw3_mask :: scw3_mask [15:00] */ 20381 #define RX66_0_SCW3_MASK_SCW3_MASK_MASK 0xffff 20382 #define RX66_0_SCW3_MASK_SCW3_MASK_ALIGN 0 20383 #define RX66_0_SCW3_MASK_SCW3_MASK_BITS 16 20384 #define RX66_0_SCW3_MASK_SCW3_MASK_SHIFT 0 20385 20386 20387 /**************************************************************************** 20388 * rx66_0 :: syncbits 20389 */ 20390 /* rx66_0 :: syncbits :: reserved0 [15:04] */ 20391 #define RX66_0_SYNCBITS_RESERVED0_MASK 0xfff0 20392 #define RX66_0_SYNCBITS_RESERVED0_ALIGN 0 20393 #define RX66_0_SYNCBITS_RESERVED0_BITS 12 20394 #define RX66_0_SYNCBITS_RESERVED0_SHIFT 4 20395 20396 /* rx66_0 :: syncbits :: syncbits [03:02] */ 20397 #define RX66_0_SYNCBITS_SYNCBITS_MASK 0x000c 20398 #define RX66_0_SYNCBITS_SYNCBITS_ALIGN 0 20399 #define RX66_0_SYNCBITS_SYNCBITS_BITS 2 20400 #define RX66_0_SYNCBITS_SYNCBITS_SHIFT 2 20401 20402 /* rx66_0 :: syncbits :: syncbits_mask [01:00] */ 20403 #define RX66_0_SYNCBITS_SYNCBITS_MASK_MASK 0x0003 20404 #define RX66_0_SYNCBITS_SYNCBITS_MASK_ALIGN 0 20405 #define RX66_0_SYNCBITS_SYNCBITS_MASK_BITS 2 20406 #define RX66_0_SYNCBITS_SYNCBITS_MASK_SHIFT 0 20407 20408 20409 /**************************************************************************** 20410 * rx66_0 :: scwControl 20411 */ 20412 /* rx66_0 :: scwControl :: reserved0 [15:15] */ 20413 #define RX66_0_SCWCONTROL_RESERVED0_MASK 0x8000 20414 #define RX66_0_SCWCONTROL_RESERVED0_ALIGN 0 20415 #define RX66_0_SCWCONTROL_RESERVED0_BITS 1 20416 #define RX66_0_SCWCONTROL_RESERVED0_SHIFT 15 20417 20418 /* rx66_0 :: scwControl :: scwCount [14:10] */ 20419 #define RX66_0_SCWCONTROL_SCWCOUNT_MASK 0x7c00 20420 #define RX66_0_SCWCONTROL_SCWCOUNT_ALIGN 0 20421 #define RX66_0_SCWCONTROL_SCWCOUNT_BITS 5 20422 #define RX66_0_SCWCONTROL_SCWCOUNT_SHIFT 10 20423 20424 /* rx66_0 :: scwControl :: gcwCount [09:05] */ 20425 #define RX66_0_SCWCONTROL_GCWCOUNT_MASK 0x03e0 20426 #define RX66_0_SCWCONTROL_GCWCOUNT_ALIGN 0 20427 #define RX66_0_SCWCONTROL_GCWCOUNT_BITS 5 20428 #define RX66_0_SCWCONTROL_GCWCOUNT_SHIFT 5 20429 20430 /* rx66_0 :: scwControl :: hystCount [04:00] */ 20431 #define RX66_0_SCWCONTROL_HYSTCOUNT_MASK 0x001f 20432 #define RX66_0_SCWCONTROL_HYSTCOUNT_ALIGN 0 20433 #define RX66_0_SCWCONTROL_HYSTCOUNT_BITS 5 20434 #define RX66_0_SCWCONTROL_HYSTCOUNT_SHIFT 0 20435 20436 20437 /**************************************************************************** 20438 * rx66_0 :: scwCount 20439 */ 20440 /* rx66_0 :: scwCount :: reserved0 [15:15] */ 20441 #define RX66_0_SCWCOUNT_RESERVED0_MASK 0x8000 20442 #define RX66_0_SCWCOUNT_RESERVED0_ALIGN 0 20443 #define RX66_0_SCWCOUNT_RESERVED0_BITS 1 20444 #define RX66_0_SCWCOUNT_RESERVED0_SHIFT 15 20445 20446 /* rx66_0 :: scwCount :: scwShift [14:08] */ 20447 #define RX66_0_SCWCOUNT_SCWSHIFT_MASK 0x7f00 20448 #define RX66_0_SCWCOUNT_SCWSHIFT_ALIGN 0 20449 #define RX66_0_SCWCOUNT_SCWSHIFT_BITS 7 20450 #define RX66_0_SCWCOUNT_SCWSHIFT_SHIFT 8 20451 20452 /* union - case COMMA_DETECT [07:00] */ 20453 /* rx66_0 :: scwCount :: cwCount [07:00] */ 20454 #define RX66_0_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK 0x00ff 20455 #define RX66_0_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN 0 20456 #define RX66_0_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS 8 20457 #define RX66_0_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT 0 20458 20459 20460 /* union - case SYNC_ACQD2 [07:00] */ 20461 /* rx66_0 :: scwCount :: cwCount [07:00] */ 20462 #define RX66_0_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK 0x00ff 20463 #define RX66_0_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN 0 20464 #define RX66_0_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS 8 20465 #define RX66_0_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT 0 20466 20467 20468 20469 /**************************************************************************** 20470 * rx66_0 :: errCount 20471 */ 20472 /* rx66_0 :: errCount :: sync66ErrCount [15:08] */ 20473 #define RX66_0_ERRCOUNT_SYNC66ERRCOUNT_MASK 0xff00 20474 #define RX66_0_ERRCOUNT_SYNC66ERRCOUNT_ALIGN 0 20475 #define RX66_0_ERRCOUNT_SYNC66ERRCOUNT_BITS 8 20476 #define RX66_0_ERRCOUNT_SYNC66ERRCOUNT_SHIFT 8 20477 20478 /* rx66_0 :: errCount :: kcode66ErrCount [07:00] */ 20479 #define RX66_0_ERRCOUNT_KCODE66ERRCOUNT_MASK 0x00ff 20480 #define RX66_0_ERRCOUNT_KCODE66ERRCOUNT_ALIGN 0 20481 #define RX66_0_ERRCOUNT_KCODE66ERRCOUNT_BITS 8 20482 #define RX66_0_ERRCOUNT_KCODE66ERRCOUNT_SHIFT 0 20483 20484 20485 /**************************************************************************** 20486 * Hypercore_USER_rx66_1 20487 */ 20488 /**************************************************************************** 20489 * rx66_1 :: Control 20490 */ 20491 /* rx66_1 :: Control :: reserved0 [15:10] */ 20492 #define RX66_1_CONTROL_RESERVED0_MASK 0xfc00 20493 #define RX66_1_CONTROL_RESERVED0_ALIGN 0 20494 #define RX66_1_CONTROL_RESERVED0_BITS 6 20495 #define RX66_1_CONTROL_RESERVED0_SHIFT 10 20496 20497 /* rx66_1 :: Control :: rxSeqDoneMask [09:09] */ 20498 #define RX66_1_CONTROL_RXSEQDONEMASK_MASK 0x0200 20499 #define RX66_1_CONTROL_RXSEQDONEMASK_ALIGN 0 20500 #define RX66_1_CONTROL_RXSEQDONEMASK_BITS 1 20501 #define RX66_1_CONTROL_RXSEQDONEMASK_SHIFT 9 20502 20503 /* rx66_1 :: Control :: cwCount_sel [08:08] */ 20504 #define RX66_1_CONTROL_CWCOUNT_SEL_MASK 0x0100 20505 #define RX66_1_CONTROL_CWCOUNT_SEL_ALIGN 0 20506 #define RX66_1_CONTROL_CWCOUNT_SEL_BITS 1 20507 #define RX66_1_CONTROL_CWCOUNT_SEL_SHIFT 8 20508 20509 /* rx66_1 :: Control :: cwCount_en [07:07] */ 20510 #define RX66_1_CONTROL_CWCOUNT_EN_MASK 0x0080 20511 #define RX66_1_CONTROL_CWCOUNT_EN_ALIGN 0 20512 #define RX66_1_CONTROL_CWCOUNT_EN_BITS 1 20513 #define RX66_1_CONTROL_CWCOUNT_EN_SHIFT 7 20514 20515 /* rx66_1 :: Control :: sync66ErrCount_en [06:06] */ 20516 #define RX66_1_CONTROL_SYNC66ERRCOUNT_EN_MASK 0x0040 20517 #define RX66_1_CONTROL_SYNC66ERRCOUNT_EN_ALIGN 0 20518 #define RX66_1_CONTROL_SYNC66ERRCOUNT_EN_BITS 1 20519 #define RX66_1_CONTROL_SYNC66ERRCOUNT_EN_SHIFT 6 20520 20521 /* rx66_1 :: Control :: kcode66ErrCount_en [05:05] */ 20522 #define RX66_1_CONTROL_KCODE66ERRCOUNT_EN_MASK 0x0020 20523 #define RX66_1_CONTROL_KCODE66ERRCOUNT_EN_ALIGN 0 20524 #define RX66_1_CONTROL_KCODE66ERRCOUNT_EN_BITS 1 20525 #define RX66_1_CONTROL_KCODE66ERRCOUNT_EN_SHIFT 5 20526 20527 /* rx66_1 :: Control :: cgbad_kcode66Err_en [04:04] */ 20528 #define RX66_1_CONTROL_CGBAD_KCODE66ERR_EN_MASK 0x0010 20529 #define RX66_1_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN 0 20530 #define RX66_1_CONTROL_CGBAD_KCODE66ERR_EN_BITS 1 20531 #define RX66_1_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT 4 20532 20533 /* rx66_1 :: Control :: descramblerControl [03:02] */ 20534 #define RX66_1_CONTROL_DESCRAMBLERCONTROL_MASK 0x000c 20535 #define RX66_1_CONTROL_DESCRAMBLERCONTROL_ALIGN 0 20536 #define RX66_1_CONTROL_DESCRAMBLERCONTROL_BITS 2 20537 #define RX66_1_CONTROL_DESCRAMBLERCONTROL_SHIFT 2 20538 20539 /* rx66_1 :: Control :: rfifo_sbitclr [01:01] */ 20540 #define RX66_1_CONTROL_RFIFO_SBITCLR_MASK 0x0002 20541 #define RX66_1_CONTROL_RFIFO_SBITCLR_ALIGN 0 20542 #define RX66_1_CONTROL_RFIFO_SBITCLR_BITS 1 20543 #define RX66_1_CONTROL_RFIFO_SBITCLR_SHIFT 1 20544 20545 /* rx66_1 :: Control :: rfifo_afrst_en [00:00] */ 20546 #define RX66_1_CONTROL_RFIFO_AFRST_EN_MASK 0x0001 20547 #define RX66_1_CONTROL_RFIFO_AFRST_EN_ALIGN 0 20548 #define RX66_1_CONTROL_RFIFO_AFRST_EN_BITS 1 20549 #define RX66_1_CONTROL_RFIFO_AFRST_EN_SHIFT 0 20550 20551 20552 /**************************************************************************** 20553 * rx66_1 :: Status 20554 */ 20555 /* rx66_1 :: Status :: LOSS_OF_SYNC [15:15] */ 20556 #define RX66_1_STATUS_LOSS_OF_SYNC_MASK 0x8000 20557 #define RX66_1_STATUS_LOSS_OF_SYNC_ALIGN 0 20558 #define RX66_1_STATUS_LOSS_OF_SYNC_BITS 1 20559 #define RX66_1_STATUS_LOSS_OF_SYNC_SHIFT 15 20560 20561 /* rx66_1 :: Status :: COMMA_DETECT [14:14] */ 20562 #define RX66_1_STATUS_COMMA_DETECT_MASK 0x4000 20563 #define RX66_1_STATUS_COMMA_DETECT_ALIGN 0 20564 #define RX66_1_STATUS_COMMA_DETECT_BITS 1 20565 #define RX66_1_STATUS_COMMA_DETECT_SHIFT 14 20566 20567 /* rx66_1 :: Status :: SYNC_ACQD1 [13:13] */ 20568 #define RX66_1_STATUS_SYNC_ACQD1_MASK 0x2000 20569 #define RX66_1_STATUS_SYNC_ACQD1_ALIGN 0 20570 #define RX66_1_STATUS_SYNC_ACQD1_BITS 1 20571 #define RX66_1_STATUS_SYNC_ACQD1_SHIFT 13 20572 20573 /* rx66_1 :: Status :: SYNC_ACQD2 [12:12] */ 20574 #define RX66_1_STATUS_SYNC_ACQD2_MASK 0x1000 20575 #define RX66_1_STATUS_SYNC_ACQD2_ALIGN 0 20576 #define RX66_1_STATUS_SYNC_ACQD2_BITS 1 20577 #define RX66_1_STATUS_SYNC_ACQD2_SHIFT 12 20578 20579 /* rx66_1 :: Status :: reserved0 [11:04] */ 20580 #define RX66_1_STATUS_RESERVED0_MASK 0x0ff0 20581 #define RX66_1_STATUS_RESERVED0_ALIGN 0 20582 #define RX66_1_STATUS_RESERVED0_BITS 8 20583 #define RX66_1_STATUS_RESERVED0_SHIFT 4 20584 20585 /* rx66_1 :: Status :: syncDone [03:03] */ 20586 #define RX66_1_STATUS_SYNCDONE_MASK 0x0008 20587 #define RX66_1_STATUS_SYNCDONE_ALIGN 0 20588 #define RX66_1_STATUS_SYNCDONE_BITS 1 20589 #define RX66_1_STATUS_SYNCDONE_SHIFT 3 20590 20591 /* rx66_1 :: Status :: unflow [02:02] */ 20592 #define RX66_1_STATUS_UNFLOW_MASK 0x0004 20593 #define RX66_1_STATUS_UNFLOW_ALIGN 0 20594 #define RX66_1_STATUS_UNFLOW_BITS 1 20595 #define RX66_1_STATUS_UNFLOW_SHIFT 2 20596 20597 /* rx66_1 :: Status :: ovflow [01:01] */ 20598 #define RX66_1_STATUS_OVFLOW_MASK 0x0002 20599 #define RX66_1_STATUS_OVFLOW_ALIGN 0 20600 #define RX66_1_STATUS_OVFLOW_BITS 1 20601 #define RX66_1_STATUS_OVFLOW_SHIFT 1 20602 20603 /* rx66_1 :: Status :: ferr [00:00] */ 20604 #define RX66_1_STATUS_FERR_MASK 0x0001 20605 #define RX66_1_STATUS_FERR_ALIGN 0 20606 #define RX66_1_STATUS_FERR_BITS 1 20607 #define RX66_1_STATUS_FERR_SHIFT 0 20608 20609 20610 /**************************************************************************** 20611 * rx66_1 :: scw0 20612 */ 20613 /* rx66_1 :: scw0 :: scw0 [15:00] */ 20614 #define RX66_1_SCW0_SCW0_MASK 0xffff 20615 #define RX66_1_SCW0_SCW0_ALIGN 0 20616 #define RX66_1_SCW0_SCW0_BITS 16 20617 #define RX66_1_SCW0_SCW0_SHIFT 0 20618 20619 20620 /**************************************************************************** 20621 * rx66_1 :: scw1 20622 */ 20623 /* rx66_1 :: scw1 :: scw1 [15:00] */ 20624 #define RX66_1_SCW1_SCW1_MASK 0xffff 20625 #define RX66_1_SCW1_SCW1_ALIGN 0 20626 #define RX66_1_SCW1_SCW1_BITS 16 20627 #define RX66_1_SCW1_SCW1_SHIFT 0 20628 20629 20630 /**************************************************************************** 20631 * rx66_1 :: scw2 20632 */ 20633 /* rx66_1 :: scw2 :: scw2 [15:00] */ 20634 #define RX66_1_SCW2_SCW2_MASK 0xffff 20635 #define RX66_1_SCW2_SCW2_ALIGN 0 20636 #define RX66_1_SCW2_SCW2_BITS 16 20637 #define RX66_1_SCW2_SCW2_SHIFT 0 20638 20639 20640 /**************************************************************************** 20641 * rx66_1 :: scw3 20642 */ 20643 /* rx66_1 :: scw3 :: scw3 [15:00] */ 20644 #define RX66_1_SCW3_SCW3_MASK 0xffff 20645 #define RX66_1_SCW3_SCW3_ALIGN 0 20646 #define RX66_1_SCW3_SCW3_BITS 16 20647 #define RX66_1_SCW3_SCW3_SHIFT 0 20648 20649 20650 /**************************************************************************** 20651 * rx66_1 :: scw0_mask 20652 */ 20653 /* rx66_1 :: scw0_mask :: scw0_mask [15:00] */ 20654 #define RX66_1_SCW0_MASK_SCW0_MASK_MASK 0xffff 20655 #define RX66_1_SCW0_MASK_SCW0_MASK_ALIGN 0 20656 #define RX66_1_SCW0_MASK_SCW0_MASK_BITS 16 20657 #define RX66_1_SCW0_MASK_SCW0_MASK_SHIFT 0 20658 20659 20660 /**************************************************************************** 20661 * rx66_1 :: scw1_mask 20662 */ 20663 /* rx66_1 :: scw1_mask :: scw1_mask [15:00] */ 20664 #define RX66_1_SCW1_MASK_SCW1_MASK_MASK 0xffff 20665 #define RX66_1_SCW1_MASK_SCW1_MASK_ALIGN 0 20666 #define RX66_1_SCW1_MASK_SCW1_MASK_BITS 16 20667 #define RX66_1_SCW1_MASK_SCW1_MASK_SHIFT 0 20668 20669 20670 /**************************************************************************** 20671 * rx66_1 :: scw2_mask 20672 */ 20673 /* rx66_1 :: scw2_mask :: scw2_mask [15:00] */ 20674 #define RX66_1_SCW2_MASK_SCW2_MASK_MASK 0xffff 20675 #define RX66_1_SCW2_MASK_SCW2_MASK_ALIGN 0 20676 #define RX66_1_SCW2_MASK_SCW2_MASK_BITS 16 20677 #define RX66_1_SCW2_MASK_SCW2_MASK_SHIFT 0 20678 20679 20680 /**************************************************************************** 20681 * rx66_1 :: scw3_mask 20682 */ 20683 /* rx66_1 :: scw3_mask :: scw3_mask [15:00] */ 20684 #define RX66_1_SCW3_MASK_SCW3_MASK_MASK 0xffff 20685 #define RX66_1_SCW3_MASK_SCW3_MASK_ALIGN 0 20686 #define RX66_1_SCW3_MASK_SCW3_MASK_BITS 16 20687 #define RX66_1_SCW3_MASK_SCW3_MASK_SHIFT 0 20688 20689 20690 /**************************************************************************** 20691 * rx66_1 :: syncbits 20692 */ 20693 /* rx66_1 :: syncbits :: reserved0 [15:04] */ 20694 #define RX66_1_SYNCBITS_RESERVED0_MASK 0xfff0 20695 #define RX66_1_SYNCBITS_RESERVED0_ALIGN 0 20696 #define RX66_1_SYNCBITS_RESERVED0_BITS 12 20697 #define RX66_1_SYNCBITS_RESERVED0_SHIFT 4 20698 20699 /* rx66_1 :: syncbits :: syncbits [03:02] */ 20700 #define RX66_1_SYNCBITS_SYNCBITS_MASK 0x000c 20701 #define RX66_1_SYNCBITS_SYNCBITS_ALIGN 0 20702 #define RX66_1_SYNCBITS_SYNCBITS_BITS 2 20703 #define RX66_1_SYNCBITS_SYNCBITS_SHIFT 2 20704 20705 /* rx66_1 :: syncbits :: syncbits_mask [01:00] */ 20706 #define RX66_1_SYNCBITS_SYNCBITS_MASK_MASK 0x0003 20707 #define RX66_1_SYNCBITS_SYNCBITS_MASK_ALIGN 0 20708 #define RX66_1_SYNCBITS_SYNCBITS_MASK_BITS 2 20709 #define RX66_1_SYNCBITS_SYNCBITS_MASK_SHIFT 0 20710 20711 20712 /**************************************************************************** 20713 * rx66_1 :: scwControl 20714 */ 20715 /* rx66_1 :: scwControl :: reserved0 [15:15] */ 20716 #define RX66_1_SCWCONTROL_RESERVED0_MASK 0x8000 20717 #define RX66_1_SCWCONTROL_RESERVED0_ALIGN 0 20718 #define RX66_1_SCWCONTROL_RESERVED0_BITS 1 20719 #define RX66_1_SCWCONTROL_RESERVED0_SHIFT 15 20720 20721 /* rx66_1 :: scwControl :: scwCount [14:10] */ 20722 #define RX66_1_SCWCONTROL_SCWCOUNT_MASK 0x7c00 20723 #define RX66_1_SCWCONTROL_SCWCOUNT_ALIGN 0 20724 #define RX66_1_SCWCONTROL_SCWCOUNT_BITS 5 20725 #define RX66_1_SCWCONTROL_SCWCOUNT_SHIFT 10 20726 20727 /* rx66_1 :: scwControl :: gcwCount [09:05] */ 20728 #define RX66_1_SCWCONTROL_GCWCOUNT_MASK 0x03e0 20729 #define RX66_1_SCWCONTROL_GCWCOUNT_ALIGN 0 20730 #define RX66_1_SCWCONTROL_GCWCOUNT_BITS 5 20731 #define RX66_1_SCWCONTROL_GCWCOUNT_SHIFT 5 20732 20733 /* rx66_1 :: scwControl :: hystCount [04:00] */ 20734 #define RX66_1_SCWCONTROL_HYSTCOUNT_MASK 0x001f 20735 #define RX66_1_SCWCONTROL_HYSTCOUNT_ALIGN 0 20736 #define RX66_1_SCWCONTROL_HYSTCOUNT_BITS 5 20737 #define RX66_1_SCWCONTROL_HYSTCOUNT_SHIFT 0 20738 20739 20740 /**************************************************************************** 20741 * rx66_1 :: scwCount 20742 */ 20743 /* rx66_1 :: scwCount :: reserved0 [15:15] */ 20744 #define RX66_1_SCWCOUNT_RESERVED0_MASK 0x8000 20745 #define RX66_1_SCWCOUNT_RESERVED0_ALIGN 0 20746 #define RX66_1_SCWCOUNT_RESERVED0_BITS 1 20747 #define RX66_1_SCWCOUNT_RESERVED0_SHIFT 15 20748 20749 /* rx66_1 :: scwCount :: scwShift [14:08] */ 20750 #define RX66_1_SCWCOUNT_SCWSHIFT_MASK 0x7f00 20751 #define RX66_1_SCWCOUNT_SCWSHIFT_ALIGN 0 20752 #define RX66_1_SCWCOUNT_SCWSHIFT_BITS 7 20753 #define RX66_1_SCWCOUNT_SCWSHIFT_SHIFT 8 20754 20755 /* union - case COMMA_DETECT [07:00] */ 20756 /* rx66_1 :: scwCount :: cwCount [07:00] */ 20757 #define RX66_1_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK 0x00ff 20758 #define RX66_1_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN 0 20759 #define RX66_1_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS 8 20760 #define RX66_1_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT 0 20761 20762 20763 /* union - case SYNC_ACQD2 [07:00] */ 20764 /* rx66_1 :: scwCount :: cwCount [07:00] */ 20765 #define RX66_1_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK 0x00ff 20766 #define RX66_1_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN 0 20767 #define RX66_1_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS 8 20768 #define RX66_1_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT 0 20769 20770 20771 20772 /**************************************************************************** 20773 * rx66_1 :: errCount 20774 */ 20775 /* rx66_1 :: errCount :: sync66ErrCount [15:08] */ 20776 #define RX66_1_ERRCOUNT_SYNC66ERRCOUNT_MASK 0xff00 20777 #define RX66_1_ERRCOUNT_SYNC66ERRCOUNT_ALIGN 0 20778 #define RX66_1_ERRCOUNT_SYNC66ERRCOUNT_BITS 8 20779 #define RX66_1_ERRCOUNT_SYNC66ERRCOUNT_SHIFT 8 20780 20781 /* rx66_1 :: errCount :: kcode66ErrCount [07:00] */ 20782 #define RX66_1_ERRCOUNT_KCODE66ERRCOUNT_MASK 0x00ff 20783 #define RX66_1_ERRCOUNT_KCODE66ERRCOUNT_ALIGN 0 20784 #define RX66_1_ERRCOUNT_KCODE66ERRCOUNT_BITS 8 20785 #define RX66_1_ERRCOUNT_KCODE66ERRCOUNT_SHIFT 0 20786 20787 20788 /**************************************************************************** 20789 * Hypercore_USER_rx66_2 20790 */ 20791 /**************************************************************************** 20792 * rx66_2 :: Control 20793 */ 20794 /* rx66_2 :: Control :: reserved0 [15:10] */ 20795 #define RX66_2_CONTROL_RESERVED0_MASK 0xfc00 20796 #define RX66_2_CONTROL_RESERVED0_ALIGN 0 20797 #define RX66_2_CONTROL_RESERVED0_BITS 6 20798 #define RX66_2_CONTROL_RESERVED0_SHIFT 10 20799 20800 /* rx66_2 :: Control :: rxSeqDoneMask [09:09] */ 20801 #define RX66_2_CONTROL_RXSEQDONEMASK_MASK 0x0200 20802 #define RX66_2_CONTROL_RXSEQDONEMASK_ALIGN 0 20803 #define RX66_2_CONTROL_RXSEQDONEMASK_BITS 1 20804 #define RX66_2_CONTROL_RXSEQDONEMASK_SHIFT 9 20805 20806 /* rx66_2 :: Control :: cwCount_sel [08:08] */ 20807 #define RX66_2_CONTROL_CWCOUNT_SEL_MASK 0x0100 20808 #define RX66_2_CONTROL_CWCOUNT_SEL_ALIGN 0 20809 #define RX66_2_CONTROL_CWCOUNT_SEL_BITS 1 20810 #define RX66_2_CONTROL_CWCOUNT_SEL_SHIFT 8 20811 20812 /* rx66_2 :: Control :: cwCount_en [07:07] */ 20813 #define RX66_2_CONTROL_CWCOUNT_EN_MASK 0x0080 20814 #define RX66_2_CONTROL_CWCOUNT_EN_ALIGN 0 20815 #define RX66_2_CONTROL_CWCOUNT_EN_BITS 1 20816 #define RX66_2_CONTROL_CWCOUNT_EN_SHIFT 7 20817 20818 /* rx66_2 :: Control :: sync66ErrCount_en [06:06] */ 20819 #define RX66_2_CONTROL_SYNC66ERRCOUNT_EN_MASK 0x0040 20820 #define RX66_2_CONTROL_SYNC66ERRCOUNT_EN_ALIGN 0 20821 #define RX66_2_CONTROL_SYNC66ERRCOUNT_EN_BITS 1 20822 #define RX66_2_CONTROL_SYNC66ERRCOUNT_EN_SHIFT 6 20823 20824 /* rx66_2 :: Control :: kcode66ErrCount_en [05:05] */ 20825 #define RX66_2_CONTROL_KCODE66ERRCOUNT_EN_MASK 0x0020 20826 #define RX66_2_CONTROL_KCODE66ERRCOUNT_EN_ALIGN 0 20827 #define RX66_2_CONTROL_KCODE66ERRCOUNT_EN_BITS 1 20828 #define RX66_2_CONTROL_KCODE66ERRCOUNT_EN_SHIFT 5 20829 20830 /* rx66_2 :: Control :: cgbad_kcode66Err_en [04:04] */ 20831 #define RX66_2_CONTROL_CGBAD_KCODE66ERR_EN_MASK 0x0010 20832 #define RX66_2_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN 0 20833 #define RX66_2_CONTROL_CGBAD_KCODE66ERR_EN_BITS 1 20834 #define RX66_2_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT 4 20835 20836 /* rx66_2 :: Control :: descramblerControl [03:02] */ 20837 #define RX66_2_CONTROL_DESCRAMBLERCONTROL_MASK 0x000c 20838 #define RX66_2_CONTROL_DESCRAMBLERCONTROL_ALIGN 0 20839 #define RX66_2_CONTROL_DESCRAMBLERCONTROL_BITS 2 20840 #define RX66_2_CONTROL_DESCRAMBLERCONTROL_SHIFT 2 20841 20842 /* rx66_2 :: Control :: rfifo_sbitclr [01:01] */ 20843 #define RX66_2_CONTROL_RFIFO_SBITCLR_MASK 0x0002 20844 #define RX66_2_CONTROL_RFIFO_SBITCLR_ALIGN 0 20845 #define RX66_2_CONTROL_RFIFO_SBITCLR_BITS 1 20846 #define RX66_2_CONTROL_RFIFO_SBITCLR_SHIFT 1 20847 20848 /* rx66_2 :: Control :: rfifo_afrst_en [00:00] */ 20849 #define RX66_2_CONTROL_RFIFO_AFRST_EN_MASK 0x0001 20850 #define RX66_2_CONTROL_RFIFO_AFRST_EN_ALIGN 0 20851 #define RX66_2_CONTROL_RFIFO_AFRST_EN_BITS 1 20852 #define RX66_2_CONTROL_RFIFO_AFRST_EN_SHIFT 0 20853 20854 20855 /**************************************************************************** 20856 * rx66_2 :: Status 20857 */ 20858 /* rx66_2 :: Status :: LOSS_OF_SYNC [15:15] */ 20859 #define RX66_2_STATUS_LOSS_OF_SYNC_MASK 0x8000 20860 #define RX66_2_STATUS_LOSS_OF_SYNC_ALIGN 0 20861 #define RX66_2_STATUS_LOSS_OF_SYNC_BITS 1 20862 #define RX66_2_STATUS_LOSS_OF_SYNC_SHIFT 15 20863 20864 /* rx66_2 :: Status :: COMMA_DETECT [14:14] */ 20865 #define RX66_2_STATUS_COMMA_DETECT_MASK 0x4000 20866 #define RX66_2_STATUS_COMMA_DETECT_ALIGN 0 20867 #define RX66_2_STATUS_COMMA_DETECT_BITS 1 20868 #define RX66_2_STATUS_COMMA_DETECT_SHIFT 14 20869 20870 /* rx66_2 :: Status :: SYNC_ACQD1 [13:13] */ 20871 #define RX66_2_STATUS_SYNC_ACQD1_MASK 0x2000 20872 #define RX66_2_STATUS_SYNC_ACQD1_ALIGN 0 20873 #define RX66_2_STATUS_SYNC_ACQD1_BITS 1 20874 #define RX66_2_STATUS_SYNC_ACQD1_SHIFT 13 20875 20876 /* rx66_2 :: Status :: SYNC_ACQD2 [12:12] */ 20877 #define RX66_2_STATUS_SYNC_ACQD2_MASK 0x1000 20878 #define RX66_2_STATUS_SYNC_ACQD2_ALIGN 0 20879 #define RX66_2_STATUS_SYNC_ACQD2_BITS 1 20880 #define RX66_2_STATUS_SYNC_ACQD2_SHIFT 12 20881 20882 /* rx66_2 :: Status :: reserved0 [11:04] */ 20883 #define RX66_2_STATUS_RESERVED0_MASK 0x0ff0 20884 #define RX66_2_STATUS_RESERVED0_ALIGN 0 20885 #define RX66_2_STATUS_RESERVED0_BITS 8 20886 #define RX66_2_STATUS_RESERVED0_SHIFT 4 20887 20888 /* rx66_2 :: Status :: syncDone [03:03] */ 20889 #define RX66_2_STATUS_SYNCDONE_MASK 0x0008 20890 #define RX66_2_STATUS_SYNCDONE_ALIGN 0 20891 #define RX66_2_STATUS_SYNCDONE_BITS 1 20892 #define RX66_2_STATUS_SYNCDONE_SHIFT 3 20893 20894 /* rx66_2 :: Status :: unflow [02:02] */ 20895 #define RX66_2_STATUS_UNFLOW_MASK 0x0004 20896 #define RX66_2_STATUS_UNFLOW_ALIGN 0 20897 #define RX66_2_STATUS_UNFLOW_BITS 1 20898 #define RX66_2_STATUS_UNFLOW_SHIFT 2 20899 20900 /* rx66_2 :: Status :: ovflow [01:01] */ 20901 #define RX66_2_STATUS_OVFLOW_MASK 0x0002 20902 #define RX66_2_STATUS_OVFLOW_ALIGN 0 20903 #define RX66_2_STATUS_OVFLOW_BITS 1 20904 #define RX66_2_STATUS_OVFLOW_SHIFT 1 20905 20906 /* rx66_2 :: Status :: ferr [00:00] */ 20907 #define RX66_2_STATUS_FERR_MASK 0x0001 20908 #define RX66_2_STATUS_FERR_ALIGN 0 20909 #define RX66_2_STATUS_FERR_BITS 1 20910 #define RX66_2_STATUS_FERR_SHIFT 0 20911 20912 20913 /**************************************************************************** 20914 * rx66_2 :: scw0 20915 */ 20916 /* rx66_2 :: scw0 :: scw0 [15:00] */ 20917 #define RX66_2_SCW0_SCW0_MASK 0xffff 20918 #define RX66_2_SCW0_SCW0_ALIGN 0 20919 #define RX66_2_SCW0_SCW0_BITS 16 20920 #define RX66_2_SCW0_SCW0_SHIFT 0 20921 20922 20923 /**************************************************************************** 20924 * rx66_2 :: scw1 20925 */ 20926 /* rx66_2 :: scw1 :: scw1 [15:00] */ 20927 #define RX66_2_SCW1_SCW1_MASK 0xffff 20928 #define RX66_2_SCW1_SCW1_ALIGN 0 20929 #define RX66_2_SCW1_SCW1_BITS 16 20930 #define RX66_2_SCW1_SCW1_SHIFT 0 20931 20932 20933 /**************************************************************************** 20934 * rx66_2 :: scw2 20935 */ 20936 /* rx66_2 :: scw2 :: scw2 [15:00] */ 20937 #define RX66_2_SCW2_SCW2_MASK 0xffff 20938 #define RX66_2_SCW2_SCW2_ALIGN 0 20939 #define RX66_2_SCW2_SCW2_BITS 16 20940 #define RX66_2_SCW2_SCW2_SHIFT 0 20941 20942 20943 /**************************************************************************** 20944 * rx66_2 :: scw3 20945 */ 20946 /* rx66_2 :: scw3 :: scw3 [15:00] */ 20947 #define RX66_2_SCW3_SCW3_MASK 0xffff 20948 #define RX66_2_SCW3_SCW3_ALIGN 0 20949 #define RX66_2_SCW3_SCW3_BITS 16 20950 #define RX66_2_SCW3_SCW3_SHIFT 0 20951 20952 20953 /**************************************************************************** 20954 * rx66_2 :: scw0_mask 20955 */ 20956 /* rx66_2 :: scw0_mask :: scw0_mask [15:00] */ 20957 #define RX66_2_SCW0_MASK_SCW0_MASK_MASK 0xffff 20958 #define RX66_2_SCW0_MASK_SCW0_MASK_ALIGN 0 20959 #define RX66_2_SCW0_MASK_SCW0_MASK_BITS 16 20960 #define RX66_2_SCW0_MASK_SCW0_MASK_SHIFT 0 20961 20962 20963 /**************************************************************************** 20964 * rx66_2 :: scw1_mask 20965 */ 20966 /* rx66_2 :: scw1_mask :: scw1_mask [15:00] */ 20967 #define RX66_2_SCW1_MASK_SCW1_MASK_MASK 0xffff 20968 #define RX66_2_SCW1_MASK_SCW1_MASK_ALIGN 0 20969 #define RX66_2_SCW1_MASK_SCW1_MASK_BITS 16 20970 #define RX66_2_SCW1_MASK_SCW1_MASK_SHIFT 0 20971 20972 20973 /**************************************************************************** 20974 * rx66_2 :: scw2_mask 20975 */ 20976 /* rx66_2 :: scw2_mask :: scw2_mask [15:00] */ 20977 #define RX66_2_SCW2_MASK_SCW2_MASK_MASK 0xffff 20978 #define RX66_2_SCW2_MASK_SCW2_MASK_ALIGN 0 20979 #define RX66_2_SCW2_MASK_SCW2_MASK_BITS 16 20980 #define RX66_2_SCW2_MASK_SCW2_MASK_SHIFT 0 20981 20982 20983 /**************************************************************************** 20984 * rx66_2 :: scw3_mask 20985 */ 20986 /* rx66_2 :: scw3_mask :: scw3_mask [15:00] */ 20987 #define RX66_2_SCW3_MASK_SCW3_MASK_MASK 0xffff 20988 #define RX66_2_SCW3_MASK_SCW3_MASK_ALIGN 0 20989 #define RX66_2_SCW3_MASK_SCW3_MASK_BITS 16 20990 #define RX66_2_SCW3_MASK_SCW3_MASK_SHIFT 0 20991 20992 20993 /**************************************************************************** 20994 * rx66_2 :: syncbits 20995 */ 20996 /* rx66_2 :: syncbits :: reserved0 [15:04] */ 20997 #define RX66_2_SYNCBITS_RESERVED0_MASK 0xfff0 20998 #define RX66_2_SYNCBITS_RESERVED0_ALIGN 0 20999 #define RX66_2_SYNCBITS_RESERVED0_BITS 12 21000 #define RX66_2_SYNCBITS_RESERVED0_SHIFT 4 21001 21002 /* rx66_2 :: syncbits :: syncbits [03:02] */ 21003 #define RX66_2_SYNCBITS_SYNCBITS_MASK 0x000c 21004 #define RX66_2_SYNCBITS_SYNCBITS_ALIGN 0 21005 #define RX66_2_SYNCBITS_SYNCBITS_BITS 2 21006 #define RX66_2_SYNCBITS_SYNCBITS_SHIFT 2 21007 21008 /* rx66_2 :: syncbits :: syncbits_mask [01:00] */ 21009 #define RX66_2_SYNCBITS_SYNCBITS_MASK_MASK 0x0003 21010 #define RX66_2_SYNCBITS_SYNCBITS_MASK_ALIGN 0 21011 #define RX66_2_SYNCBITS_SYNCBITS_MASK_BITS 2 21012 #define RX66_2_SYNCBITS_SYNCBITS_MASK_SHIFT 0 21013 21014 21015 /**************************************************************************** 21016 * rx66_2 :: scwControl 21017 */ 21018 /* rx66_2 :: scwControl :: reserved0 [15:15] */ 21019 #define RX66_2_SCWCONTROL_RESERVED0_MASK 0x8000 21020 #define RX66_2_SCWCONTROL_RESERVED0_ALIGN 0 21021 #define RX66_2_SCWCONTROL_RESERVED0_BITS 1 21022 #define RX66_2_SCWCONTROL_RESERVED0_SHIFT 15 21023 21024 /* rx66_2 :: scwControl :: scwCount [14:10] */ 21025 #define RX66_2_SCWCONTROL_SCWCOUNT_MASK 0x7c00 21026 #define RX66_2_SCWCONTROL_SCWCOUNT_ALIGN 0 21027 #define RX66_2_SCWCONTROL_SCWCOUNT_BITS 5 21028 #define RX66_2_SCWCONTROL_SCWCOUNT_SHIFT 10 21029 21030 /* rx66_2 :: scwControl :: gcwCount [09:05] */ 21031 #define RX66_2_SCWCONTROL_GCWCOUNT_MASK 0x03e0 21032 #define RX66_2_SCWCONTROL_GCWCOUNT_ALIGN 0 21033 #define RX66_2_SCWCONTROL_GCWCOUNT_BITS 5 21034 #define RX66_2_SCWCONTROL_GCWCOUNT_SHIFT 5 21035 21036 /* rx66_2 :: scwControl :: hystCount [04:00] */ 21037 #define RX66_2_SCWCONTROL_HYSTCOUNT_MASK 0x001f 21038 #define RX66_2_SCWCONTROL_HYSTCOUNT_ALIGN 0 21039 #define RX66_2_SCWCONTROL_HYSTCOUNT_BITS 5 21040 #define RX66_2_SCWCONTROL_HYSTCOUNT_SHIFT 0 21041 21042 21043 /**************************************************************************** 21044 * rx66_2 :: scwCount 21045 */ 21046 /* rx66_2 :: scwCount :: reserved0 [15:15] */ 21047 #define RX66_2_SCWCOUNT_RESERVED0_MASK 0x8000 21048 #define RX66_2_SCWCOUNT_RESERVED0_ALIGN 0 21049 #define RX66_2_SCWCOUNT_RESERVED0_BITS 1 21050 #define RX66_2_SCWCOUNT_RESERVED0_SHIFT 15 21051 21052 /* rx66_2 :: scwCount :: scwShift [14:08] */ 21053 #define RX66_2_SCWCOUNT_SCWSHIFT_MASK 0x7f00 21054 #define RX66_2_SCWCOUNT_SCWSHIFT_ALIGN 0 21055 #define RX66_2_SCWCOUNT_SCWSHIFT_BITS 7 21056 #define RX66_2_SCWCOUNT_SCWSHIFT_SHIFT 8 21057 21058 /* union - case COMMA_DETECT [07:00] */ 21059 /* rx66_2 :: scwCount :: cwCount [07:00] */ 21060 #define RX66_2_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK 0x00ff 21061 #define RX66_2_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN 0 21062 #define RX66_2_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS 8 21063 #define RX66_2_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT 0 21064 21065 21066 /* union - case SYNC_ACQD2 [07:00] */ 21067 /* rx66_2 :: scwCount :: cwCount [07:00] */ 21068 #define RX66_2_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK 0x00ff 21069 #define RX66_2_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN 0 21070 #define RX66_2_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS 8 21071 #define RX66_2_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT 0 21072 21073 21074 21075 /**************************************************************************** 21076 * rx66_2 :: errCount 21077 */ 21078 /* rx66_2 :: errCount :: sync66ErrCount [15:08] */ 21079 #define RX66_2_ERRCOUNT_SYNC66ERRCOUNT_MASK 0xff00 21080 #define RX66_2_ERRCOUNT_SYNC66ERRCOUNT_ALIGN 0 21081 #define RX66_2_ERRCOUNT_SYNC66ERRCOUNT_BITS 8 21082 #define RX66_2_ERRCOUNT_SYNC66ERRCOUNT_SHIFT 8 21083 21084 /* rx66_2 :: errCount :: kcode66ErrCount [07:00] */ 21085 #define RX66_2_ERRCOUNT_KCODE66ERRCOUNT_MASK 0x00ff 21086 #define RX66_2_ERRCOUNT_KCODE66ERRCOUNT_ALIGN 0 21087 #define RX66_2_ERRCOUNT_KCODE66ERRCOUNT_BITS 8 21088 #define RX66_2_ERRCOUNT_KCODE66ERRCOUNT_SHIFT 0 21089 21090 21091 /**************************************************************************** 21092 * Hypercore_USER_rx66_3 21093 */ 21094 /**************************************************************************** 21095 * rx66_3 :: Control 21096 */ 21097 /* rx66_3 :: Control :: reserved0 [15:10] */ 21098 #define RX66_3_CONTROL_RESERVED0_MASK 0xfc00 21099 #define RX66_3_CONTROL_RESERVED0_ALIGN 0 21100 #define RX66_3_CONTROL_RESERVED0_BITS 6 21101 #define RX66_3_CONTROL_RESERVED0_SHIFT 10 21102 21103 /* rx66_3 :: Control :: rxSeqDoneMask [09:09] */ 21104 #define RX66_3_CONTROL_RXSEQDONEMASK_MASK 0x0200 21105 #define RX66_3_CONTROL_RXSEQDONEMASK_ALIGN 0 21106 #define RX66_3_CONTROL_RXSEQDONEMASK_BITS 1 21107 #define RX66_3_CONTROL_RXSEQDONEMASK_SHIFT 9 21108 21109 /* rx66_3 :: Control :: cwCount_sel [08:08] */ 21110 #define RX66_3_CONTROL_CWCOUNT_SEL_MASK 0x0100 21111 #define RX66_3_CONTROL_CWCOUNT_SEL_ALIGN 0 21112 #define RX66_3_CONTROL_CWCOUNT_SEL_BITS 1 21113 #define RX66_3_CONTROL_CWCOUNT_SEL_SHIFT 8 21114 21115 /* rx66_3 :: Control :: cwCount_en [07:07] */ 21116 #define RX66_3_CONTROL_CWCOUNT_EN_MASK 0x0080 21117 #define RX66_3_CONTROL_CWCOUNT_EN_ALIGN 0 21118 #define RX66_3_CONTROL_CWCOUNT_EN_BITS 1 21119 #define RX66_3_CONTROL_CWCOUNT_EN_SHIFT 7 21120 21121 /* rx66_3 :: Control :: sync66ErrCount_en [06:06] */ 21122 #define RX66_3_CONTROL_SYNC66ERRCOUNT_EN_MASK 0x0040 21123 #define RX66_3_CONTROL_SYNC66ERRCOUNT_EN_ALIGN 0 21124 #define RX66_3_CONTROL_SYNC66ERRCOUNT_EN_BITS 1 21125 #define RX66_3_CONTROL_SYNC66ERRCOUNT_EN_SHIFT 6 21126 21127 /* rx66_3 :: Control :: kcode66ErrCount_en [05:05] */ 21128 #define RX66_3_CONTROL_KCODE66ERRCOUNT_EN_MASK 0x0020 21129 #define RX66_3_CONTROL_KCODE66ERRCOUNT_EN_ALIGN 0 21130 #define RX66_3_CONTROL_KCODE66ERRCOUNT_EN_BITS 1 21131 #define RX66_3_CONTROL_KCODE66ERRCOUNT_EN_SHIFT 5 21132 21133 /* rx66_3 :: Control :: cgbad_kcode66Err_en [04:04] */ 21134 #define RX66_3_CONTROL_CGBAD_KCODE66ERR_EN_MASK 0x0010 21135 #define RX66_3_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN 0 21136 #define RX66_3_CONTROL_CGBAD_KCODE66ERR_EN_BITS 1 21137 #define RX66_3_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT 4 21138 21139 /* rx66_3 :: Control :: descramblerControl [03:02] */ 21140 #define RX66_3_CONTROL_DESCRAMBLERCONTROL_MASK 0x000c 21141 #define RX66_3_CONTROL_DESCRAMBLERCONTROL_ALIGN 0 21142 #define RX66_3_CONTROL_DESCRAMBLERCONTROL_BITS 2 21143 #define RX66_3_CONTROL_DESCRAMBLERCONTROL_SHIFT 2 21144 21145 /* rx66_3 :: Control :: rfifo_sbitclr [01:01] */ 21146 #define RX66_3_CONTROL_RFIFO_SBITCLR_MASK 0x0002 21147 #define RX66_3_CONTROL_RFIFO_SBITCLR_ALIGN 0 21148 #define RX66_3_CONTROL_RFIFO_SBITCLR_BITS 1 21149 #define RX66_3_CONTROL_RFIFO_SBITCLR_SHIFT 1 21150 21151 /* rx66_3 :: Control :: rfifo_afrst_en [00:00] */ 21152 #define RX66_3_CONTROL_RFIFO_AFRST_EN_MASK 0x0001 21153 #define RX66_3_CONTROL_RFIFO_AFRST_EN_ALIGN 0 21154 #define RX66_3_CONTROL_RFIFO_AFRST_EN_BITS 1 21155 #define RX66_3_CONTROL_RFIFO_AFRST_EN_SHIFT 0 21156 21157 21158 /**************************************************************************** 21159 * rx66_3 :: Status 21160 */ 21161 /* rx66_3 :: Status :: LOSS_OF_SYNC [15:15] */ 21162 #define RX66_3_STATUS_LOSS_OF_SYNC_MASK 0x8000 21163 #define RX66_3_STATUS_LOSS_OF_SYNC_ALIGN 0 21164 #define RX66_3_STATUS_LOSS_OF_SYNC_BITS 1 21165 #define RX66_3_STATUS_LOSS_OF_SYNC_SHIFT 15 21166 21167 /* rx66_3 :: Status :: COMMA_DETECT [14:14] */ 21168 #define RX66_3_STATUS_COMMA_DETECT_MASK 0x4000 21169 #define RX66_3_STATUS_COMMA_DETECT_ALIGN 0 21170 #define RX66_3_STATUS_COMMA_DETECT_BITS 1 21171 #define RX66_3_STATUS_COMMA_DETECT_SHIFT 14 21172 21173 /* rx66_3 :: Status :: SYNC_ACQD1 [13:13] */ 21174 #define RX66_3_STATUS_SYNC_ACQD1_MASK 0x2000 21175 #define RX66_3_STATUS_SYNC_ACQD1_ALIGN 0 21176 #define RX66_3_STATUS_SYNC_ACQD1_BITS 1 21177 #define RX66_3_STATUS_SYNC_ACQD1_SHIFT 13 21178 21179 /* rx66_3 :: Status :: SYNC_ACQD2 [12:12] */ 21180 #define RX66_3_STATUS_SYNC_ACQD2_MASK 0x1000 21181 #define RX66_3_STATUS_SYNC_ACQD2_ALIGN 0 21182 #define RX66_3_STATUS_SYNC_ACQD2_BITS 1 21183 #define RX66_3_STATUS_SYNC_ACQD2_SHIFT 12 21184 21185 /* rx66_3 :: Status :: reserved0 [11:04] */ 21186 #define RX66_3_STATUS_RESERVED0_MASK 0x0ff0 21187 #define RX66_3_STATUS_RESERVED0_ALIGN 0 21188 #define RX66_3_STATUS_RESERVED0_BITS 8 21189 #define RX66_3_STATUS_RESERVED0_SHIFT 4 21190 21191 /* rx66_3 :: Status :: syncDone [03:03] */ 21192 #define RX66_3_STATUS_SYNCDONE_MASK 0x0008 21193 #define RX66_3_STATUS_SYNCDONE_ALIGN 0 21194 #define RX66_3_STATUS_SYNCDONE_BITS 1 21195 #define RX66_3_STATUS_SYNCDONE_SHIFT 3 21196 21197 /* rx66_3 :: Status :: unflow [02:02] */ 21198 #define RX66_3_STATUS_UNFLOW_MASK 0x0004 21199 #define RX66_3_STATUS_UNFLOW_ALIGN 0 21200 #define RX66_3_STATUS_UNFLOW_BITS 1 21201 #define RX66_3_STATUS_UNFLOW_SHIFT 2 21202 21203 /* rx66_3 :: Status :: ovflow [01:01] */ 21204 #define RX66_3_STATUS_OVFLOW_MASK 0x0002 21205 #define RX66_3_STATUS_OVFLOW_ALIGN 0 21206 #define RX66_3_STATUS_OVFLOW_BITS 1 21207 #define RX66_3_STATUS_OVFLOW_SHIFT 1 21208 21209 /* rx66_3 :: Status :: ferr [00:00] */ 21210 #define RX66_3_STATUS_FERR_MASK 0x0001 21211 #define RX66_3_STATUS_FERR_ALIGN 0 21212 #define RX66_3_STATUS_FERR_BITS 1 21213 #define RX66_3_STATUS_FERR_SHIFT 0 21214 21215 21216 /**************************************************************************** 21217 * rx66_3 :: scw0 21218 */ 21219 /* rx66_3 :: scw0 :: scw0 [15:00] */ 21220 #define RX66_3_SCW0_SCW0_MASK 0xffff 21221 #define RX66_3_SCW0_SCW0_ALIGN 0 21222 #define RX66_3_SCW0_SCW0_BITS 16 21223 #define RX66_3_SCW0_SCW0_SHIFT 0 21224 21225 21226 /**************************************************************************** 21227 * rx66_3 :: scw1 21228 */ 21229 /* rx66_3 :: scw1 :: scw1 [15:00] */ 21230 #define RX66_3_SCW1_SCW1_MASK 0xffff 21231 #define RX66_3_SCW1_SCW1_ALIGN 0 21232 #define RX66_3_SCW1_SCW1_BITS 16 21233 #define RX66_3_SCW1_SCW1_SHIFT 0 21234 21235 21236 /**************************************************************************** 21237 * rx66_3 :: scw2 21238 */ 21239 /* rx66_3 :: scw2 :: scw2 [15:00] */ 21240 #define RX66_3_SCW2_SCW2_MASK 0xffff 21241 #define RX66_3_SCW2_SCW2_ALIGN 0 21242 #define RX66_3_SCW2_SCW2_BITS 16 21243 #define RX66_3_SCW2_SCW2_SHIFT 0 21244 21245 21246 /**************************************************************************** 21247 * rx66_3 :: scw3 21248 */ 21249 /* rx66_3 :: scw3 :: scw3 [15:00] */ 21250 #define RX66_3_SCW3_SCW3_MASK 0xffff 21251 #define RX66_3_SCW3_SCW3_ALIGN 0 21252 #define RX66_3_SCW3_SCW3_BITS 16 21253 #define RX66_3_SCW3_SCW3_SHIFT 0 21254 21255 21256 /**************************************************************************** 21257 * rx66_3 :: scw0_mask 21258 */ 21259 /* rx66_3 :: scw0_mask :: scw0_mask [15:00] */ 21260 #define RX66_3_SCW0_MASK_SCW0_MASK_MASK 0xffff 21261 #define RX66_3_SCW0_MASK_SCW0_MASK_ALIGN 0 21262 #define RX66_3_SCW0_MASK_SCW0_MASK_BITS 16 21263 #define RX66_3_SCW0_MASK_SCW0_MASK_SHIFT 0 21264 21265 21266 /**************************************************************************** 21267 * rx66_3 :: scw1_mask 21268 */ 21269 /* rx66_3 :: scw1_mask :: scw1_mask [15:00] */ 21270 #define RX66_3_SCW1_MASK_SCW1_MASK_MASK 0xffff 21271 #define RX66_3_SCW1_MASK_SCW1_MASK_ALIGN 0 21272 #define RX66_3_SCW1_MASK_SCW1_MASK_BITS 16 21273 #define RX66_3_SCW1_MASK_SCW1_MASK_SHIFT 0 21274 21275 21276 /**************************************************************************** 21277 * rx66_3 :: scw2_mask 21278 */ 21279 /* rx66_3 :: scw2_mask :: scw2_mask [15:00] */ 21280 #define RX66_3_SCW2_MASK_SCW2_MASK_MASK 0xffff 21281 #define RX66_3_SCW2_MASK_SCW2_MASK_ALIGN 0 21282 #define RX66_3_SCW2_MASK_SCW2_MASK_BITS 16 21283 #define RX66_3_SCW2_MASK_SCW2_MASK_SHIFT 0 21284 21285 21286 /**************************************************************************** 21287 * rx66_3 :: scw3_mask 21288 */ 21289 /* rx66_3 :: scw3_mask :: scw3_mask [15:00] */ 21290 #define RX66_3_SCW3_MASK_SCW3_MASK_MASK 0xffff 21291 #define RX66_3_SCW3_MASK_SCW3_MASK_ALIGN 0 21292 #define RX66_3_SCW3_MASK_SCW3_MASK_BITS 16 21293 #define RX66_3_SCW3_MASK_SCW3_MASK_SHIFT 0 21294 21295 21296 /**************************************************************************** 21297 * rx66_3 :: syncbits 21298 */ 21299 /* rx66_3 :: syncbits :: reserved0 [15:04] */ 21300 #define RX66_3_SYNCBITS_RESERVED0_MASK 0xfff0 21301 #define RX66_3_SYNCBITS_RESERVED0_ALIGN 0 21302 #define RX66_3_SYNCBITS_RESERVED0_BITS 12 21303 #define RX66_3_SYNCBITS_RESERVED0_SHIFT 4 21304 21305 /* rx66_3 :: syncbits :: syncbits [03:02] */ 21306 #define RX66_3_SYNCBITS_SYNCBITS_MASK 0x000c 21307 #define RX66_3_SYNCBITS_SYNCBITS_ALIGN 0 21308 #define RX66_3_SYNCBITS_SYNCBITS_BITS 2 21309 #define RX66_3_SYNCBITS_SYNCBITS_SHIFT 2 21310 21311 /* rx66_3 :: syncbits :: syncbits_mask [01:00] */ 21312 #define RX66_3_SYNCBITS_SYNCBITS_MASK_MASK 0x0003 21313 #define RX66_3_SYNCBITS_SYNCBITS_MASK_ALIGN 0 21314 #define RX66_3_SYNCBITS_SYNCBITS_MASK_BITS 2 21315 #define RX66_3_SYNCBITS_SYNCBITS_MASK_SHIFT 0 21316 21317 21318 /**************************************************************************** 21319 * rx66_3 :: scwControl 21320 */ 21321 /* rx66_3 :: scwControl :: reserved0 [15:15] */ 21322 #define RX66_3_SCWCONTROL_RESERVED0_MASK 0x8000 21323 #define RX66_3_SCWCONTROL_RESERVED0_ALIGN 0 21324 #define RX66_3_SCWCONTROL_RESERVED0_BITS 1 21325 #define RX66_3_SCWCONTROL_RESERVED0_SHIFT 15 21326 21327 /* rx66_3 :: scwControl :: scwCount [14:10] */ 21328 #define RX66_3_SCWCONTROL_SCWCOUNT_MASK 0x7c00 21329 #define RX66_3_SCWCONTROL_SCWCOUNT_ALIGN 0 21330 #define RX66_3_SCWCONTROL_SCWCOUNT_BITS 5 21331 #define RX66_3_SCWCONTROL_SCWCOUNT_SHIFT 10 21332 21333 /* rx66_3 :: scwControl :: gcwCount [09:05] */ 21334 #define RX66_3_SCWCONTROL_GCWCOUNT_MASK 0x03e0 21335 #define RX66_3_SCWCONTROL_GCWCOUNT_ALIGN 0 21336 #define RX66_3_SCWCONTROL_GCWCOUNT_BITS 5 21337 #define RX66_3_SCWCONTROL_GCWCOUNT_SHIFT 5 21338 21339 /* rx66_3 :: scwControl :: hystCount [04:00] */ 21340 #define RX66_3_SCWCONTROL_HYSTCOUNT_MASK 0x001f 21341 #define RX66_3_SCWCONTROL_HYSTCOUNT_ALIGN 0 21342 #define RX66_3_SCWCONTROL_HYSTCOUNT_BITS 5 21343 #define RX66_3_SCWCONTROL_HYSTCOUNT_SHIFT 0 21344 21345 21346 /**************************************************************************** 21347 * rx66_3 :: scwCount 21348 */ 21349 /* rx66_3 :: scwCount :: reserved0 [15:15] */ 21350 #define RX66_3_SCWCOUNT_RESERVED0_MASK 0x8000 21351 #define RX66_3_SCWCOUNT_RESERVED0_ALIGN 0 21352 #define RX66_3_SCWCOUNT_RESERVED0_BITS 1 21353 #define RX66_3_SCWCOUNT_RESERVED0_SHIFT 15 21354 21355 /* rx66_3 :: scwCount :: scwShift [14:08] */ 21356 #define RX66_3_SCWCOUNT_SCWSHIFT_MASK 0x7f00 21357 #define RX66_3_SCWCOUNT_SCWSHIFT_ALIGN 0 21358 #define RX66_3_SCWCOUNT_SCWSHIFT_BITS 7 21359 #define RX66_3_SCWCOUNT_SCWSHIFT_SHIFT 8 21360 21361 /* union - case COMMA_DETECT [07:00] */ 21362 /* rx66_3 :: scwCount :: cwCount [07:00] */ 21363 #define RX66_3_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK 0x00ff 21364 #define RX66_3_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN 0 21365 #define RX66_3_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS 8 21366 #define RX66_3_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT 0 21367 21368 21369 /* union - case SYNC_ACQD2 [07:00] */ 21370 /* rx66_3 :: scwCount :: cwCount [07:00] */ 21371 #define RX66_3_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK 0x00ff 21372 #define RX66_3_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN 0 21373 #define RX66_3_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS 8 21374 #define RX66_3_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT 0 21375 21376 21377 21378 /**************************************************************************** 21379 * rx66_3 :: errCount 21380 */ 21381 /* rx66_3 :: errCount :: sync66ErrCount [15:08] */ 21382 #define RX66_3_ERRCOUNT_SYNC66ERRCOUNT_MASK 0xff00 21383 #define RX66_3_ERRCOUNT_SYNC66ERRCOUNT_ALIGN 0 21384 #define RX66_3_ERRCOUNT_SYNC66ERRCOUNT_BITS 8 21385 #define RX66_3_ERRCOUNT_SYNC66ERRCOUNT_SHIFT 8 21386 21387 /* rx66_3 :: errCount :: kcode66ErrCount [07:00] */ 21388 #define RX66_3_ERRCOUNT_KCODE66ERRCOUNT_MASK 0x00ff 21389 #define RX66_3_ERRCOUNT_KCODE66ERRCOUNT_ALIGN 0 21390 #define RX66_3_ERRCOUNT_KCODE66ERRCOUNT_BITS 8 21391 #define RX66_3_ERRCOUNT_KCODE66ERRCOUNT_SHIFT 0 21392 21393 21394 /**************************************************************************** 21395 * Hypercore_USER_rx66_A 21396 */ 21397 /**************************************************************************** 21398 * rx66_A :: Control 21399 */ 21400 /* rx66_A :: Control :: reserved0 [15:10] */ 21401 #define RX66_A_CONTROL_RESERVED0_MASK 0xfc00 21402 #define RX66_A_CONTROL_RESERVED0_ALIGN 0 21403 #define RX66_A_CONTROL_RESERVED0_BITS 6 21404 #define RX66_A_CONTROL_RESERVED0_SHIFT 10 21405 21406 /* rx66_A :: Control :: rxSeqDoneMask [09:09] */ 21407 #define RX66_A_CONTROL_RXSEQDONEMASK_MASK 0x0200 21408 #define RX66_A_CONTROL_RXSEQDONEMASK_ALIGN 0 21409 #define RX66_A_CONTROL_RXSEQDONEMASK_BITS 1 21410 #define RX66_A_CONTROL_RXSEQDONEMASK_SHIFT 9 21411 21412 /* rx66_A :: Control :: cwCount_sel [08:08] */ 21413 #define RX66_A_CONTROL_CWCOUNT_SEL_MASK 0x0100 21414 #define RX66_A_CONTROL_CWCOUNT_SEL_ALIGN 0 21415 #define RX66_A_CONTROL_CWCOUNT_SEL_BITS 1 21416 #define RX66_A_CONTROL_CWCOUNT_SEL_SHIFT 8 21417 21418 /* rx66_A :: Control :: cwCount_en [07:07] */ 21419 #define RX66_A_CONTROL_CWCOUNT_EN_MASK 0x0080 21420 #define RX66_A_CONTROL_CWCOUNT_EN_ALIGN 0 21421 #define RX66_A_CONTROL_CWCOUNT_EN_BITS 1 21422 #define RX66_A_CONTROL_CWCOUNT_EN_SHIFT 7 21423 21424 /* rx66_A :: Control :: sync66ErrCount_en [06:06] */ 21425 #define RX66_A_CONTROL_SYNC66ERRCOUNT_EN_MASK 0x0040 21426 #define RX66_A_CONTROL_SYNC66ERRCOUNT_EN_ALIGN 0 21427 #define RX66_A_CONTROL_SYNC66ERRCOUNT_EN_BITS 1 21428 #define RX66_A_CONTROL_SYNC66ERRCOUNT_EN_SHIFT 6 21429 21430 /* rx66_A :: Control :: kcode66ErrCount_en [05:05] */ 21431 #define RX66_A_CONTROL_KCODE66ERRCOUNT_EN_MASK 0x0020 21432 #define RX66_A_CONTROL_KCODE66ERRCOUNT_EN_ALIGN 0 21433 #define RX66_A_CONTROL_KCODE66ERRCOUNT_EN_BITS 1 21434 #define RX66_A_CONTROL_KCODE66ERRCOUNT_EN_SHIFT 5 21435 21436 /* rx66_A :: Control :: cgbad_kcode66Err_en [04:04] */ 21437 #define RX66_A_CONTROL_CGBAD_KCODE66ERR_EN_MASK 0x0010 21438 #define RX66_A_CONTROL_CGBAD_KCODE66ERR_EN_ALIGN 0 21439 #define RX66_A_CONTROL_CGBAD_KCODE66ERR_EN_BITS 1 21440 #define RX66_A_CONTROL_CGBAD_KCODE66ERR_EN_SHIFT 4 21441 21442 /* rx66_A :: Control :: descramblerControl [03:02] */ 21443 #define RX66_A_CONTROL_DESCRAMBLERCONTROL_MASK 0x000c 21444 #define RX66_A_CONTROL_DESCRAMBLERCONTROL_ALIGN 0 21445 #define RX66_A_CONTROL_DESCRAMBLERCONTROL_BITS 2 21446 #define RX66_A_CONTROL_DESCRAMBLERCONTROL_SHIFT 2 21447 21448 /* rx66_A :: Control :: rfifo_sbitclr [01:01] */ 21449 #define RX66_A_CONTROL_RFIFO_SBITCLR_MASK 0x0002 21450 #define RX66_A_CONTROL_RFIFO_SBITCLR_ALIGN 0 21451 #define RX66_A_CONTROL_RFIFO_SBITCLR_BITS 1 21452 #define RX66_A_CONTROL_RFIFO_SBITCLR_SHIFT 1 21453 21454 /* rx66_A :: Control :: rfifo_afrst_en [00:00] */ 21455 #define RX66_A_CONTROL_RFIFO_AFRST_EN_MASK 0x0001 21456 #define RX66_A_CONTROL_RFIFO_AFRST_EN_ALIGN 0 21457 #define RX66_A_CONTROL_RFIFO_AFRST_EN_BITS 1 21458 #define RX66_A_CONTROL_RFIFO_AFRST_EN_SHIFT 0 21459 21460 21461 /**************************************************************************** 21462 * rx66_A :: Status 21463 */ 21464 /* rx66_A :: Status :: LOSS_OF_SYNC [15:15] */ 21465 #define RX66_A_STATUS_LOSS_OF_SYNC_MASK 0x8000 21466 #define RX66_A_STATUS_LOSS_OF_SYNC_ALIGN 0 21467 #define RX66_A_STATUS_LOSS_OF_SYNC_BITS 1 21468 #define RX66_A_STATUS_LOSS_OF_SYNC_SHIFT 15 21469 21470 /* rx66_A :: Status :: COMMA_DETECT [14:14] */ 21471 #define RX66_A_STATUS_COMMA_DETECT_MASK 0x4000 21472 #define RX66_A_STATUS_COMMA_DETECT_ALIGN 0 21473 #define RX66_A_STATUS_COMMA_DETECT_BITS 1 21474 #define RX66_A_STATUS_COMMA_DETECT_SHIFT 14 21475 21476 /* rx66_A :: Status :: SYNC_ACQD1 [13:13] */ 21477 #define RX66_A_STATUS_SYNC_ACQD1_MASK 0x2000 21478 #define RX66_A_STATUS_SYNC_ACQD1_ALIGN 0 21479 #define RX66_A_STATUS_SYNC_ACQD1_BITS 1 21480 #define RX66_A_STATUS_SYNC_ACQD1_SHIFT 13 21481 21482 /* rx66_A :: Status :: SYNC_ACQD2 [12:12] */ 21483 #define RX66_A_STATUS_SYNC_ACQD2_MASK 0x1000 21484 #define RX66_A_STATUS_SYNC_ACQD2_ALIGN 0 21485 #define RX66_A_STATUS_SYNC_ACQD2_BITS 1 21486 #define RX66_A_STATUS_SYNC_ACQD2_SHIFT 12 21487 21488 /* rx66_A :: Status :: reserved0 [11:04] */ 21489 #define RX66_A_STATUS_RESERVED0_MASK 0x0ff0 21490 #define RX66_A_STATUS_RESERVED0_ALIGN 0 21491 #define RX66_A_STATUS_RESERVED0_BITS 8 21492 #define RX66_A_STATUS_RESERVED0_SHIFT 4 21493 21494 /* rx66_A :: Status :: syncDone [03:03] */ 21495 #define RX66_A_STATUS_SYNCDONE_MASK 0x0008 21496 #define RX66_A_STATUS_SYNCDONE_ALIGN 0 21497 #define RX66_A_STATUS_SYNCDONE_BITS 1 21498 #define RX66_A_STATUS_SYNCDONE_SHIFT 3 21499 21500 /* rx66_A :: Status :: unflow [02:02] */ 21501 #define RX66_A_STATUS_UNFLOW_MASK 0x0004 21502 #define RX66_A_STATUS_UNFLOW_ALIGN 0 21503 #define RX66_A_STATUS_UNFLOW_BITS 1 21504 #define RX66_A_STATUS_UNFLOW_SHIFT 2 21505 21506 /* rx66_A :: Status :: ovflow [01:01] */ 21507 #define RX66_A_STATUS_OVFLOW_MASK 0x0002 21508 #define RX66_A_STATUS_OVFLOW_ALIGN 0 21509 #define RX66_A_STATUS_OVFLOW_BITS 1 21510 #define RX66_A_STATUS_OVFLOW_SHIFT 1 21511 21512 /* rx66_A :: Status :: ferr [00:00] */ 21513 #define RX66_A_STATUS_FERR_MASK 0x0001 21514 #define RX66_A_STATUS_FERR_ALIGN 0 21515 #define RX66_A_STATUS_FERR_BITS 1 21516 #define RX66_A_STATUS_FERR_SHIFT 0 21517 21518 21519 /**************************************************************************** 21520 * rx66_A :: scw0 21521 */ 21522 /* rx66_A :: scw0 :: scw0 [15:00] */ 21523 #define RX66_A_SCW0_SCW0_MASK 0xffff 21524 #define RX66_A_SCW0_SCW0_ALIGN 0 21525 #define RX66_A_SCW0_SCW0_BITS 16 21526 #define RX66_A_SCW0_SCW0_SHIFT 0 21527 21528 21529 /**************************************************************************** 21530 * rx66_A :: scw1 21531 */ 21532 /* rx66_A :: scw1 :: scw1 [15:00] */ 21533 #define RX66_A_SCW1_SCW1_MASK 0xffff 21534 #define RX66_A_SCW1_SCW1_ALIGN 0 21535 #define RX66_A_SCW1_SCW1_BITS 16 21536 #define RX66_A_SCW1_SCW1_SHIFT 0 21537 21538 21539 /**************************************************************************** 21540 * rx66_A :: scw2 21541 */ 21542 /* rx66_A :: scw2 :: scw2 [15:00] */ 21543 #define RX66_A_SCW2_SCW2_MASK 0xffff 21544 #define RX66_A_SCW2_SCW2_ALIGN 0 21545 #define RX66_A_SCW2_SCW2_BITS 16 21546 #define RX66_A_SCW2_SCW2_SHIFT 0 21547 21548 21549 /**************************************************************************** 21550 * rx66_A :: scw3 21551 */ 21552 /* rx66_A :: scw3 :: scw3 [15:00] */ 21553 #define RX66_A_SCW3_SCW3_MASK 0xffff 21554 #define RX66_A_SCW3_SCW3_ALIGN 0 21555 #define RX66_A_SCW3_SCW3_BITS 16 21556 #define RX66_A_SCW3_SCW3_SHIFT 0 21557 21558 21559 /**************************************************************************** 21560 * rx66_A :: scw0_mask 21561 */ 21562 /* rx66_A :: scw0_mask :: scw0_mask [15:00] */ 21563 #define RX66_A_SCW0_MASK_SCW0_MASK_MASK 0xffff 21564 #define RX66_A_SCW0_MASK_SCW0_MASK_ALIGN 0 21565 #define RX66_A_SCW0_MASK_SCW0_MASK_BITS 16 21566 #define RX66_A_SCW0_MASK_SCW0_MASK_SHIFT 0 21567 21568 21569 /**************************************************************************** 21570 * rx66_A :: scw1_mask 21571 */ 21572 /* rx66_A :: scw1_mask :: scw1_mask [15:00] */ 21573 #define RX66_A_SCW1_MASK_SCW1_MASK_MASK 0xffff 21574 #define RX66_A_SCW1_MASK_SCW1_MASK_ALIGN 0 21575 #define RX66_A_SCW1_MASK_SCW1_MASK_BITS 16 21576 #define RX66_A_SCW1_MASK_SCW1_MASK_SHIFT 0 21577 21578 21579 /**************************************************************************** 21580 * rx66_A :: scw2_mask 21581 */ 21582 /* rx66_A :: scw2_mask :: scw2_mask [15:00] */ 21583 #define RX66_A_SCW2_MASK_SCW2_MASK_MASK 0xffff 21584 #define RX66_A_SCW2_MASK_SCW2_MASK_ALIGN 0 21585 #define RX66_A_SCW2_MASK_SCW2_MASK_BITS 16 21586 #define RX66_A_SCW2_MASK_SCW2_MASK_SHIFT 0 21587 21588 21589 /**************************************************************************** 21590 * rx66_A :: scw3_mask 21591 */ 21592 /* rx66_A :: scw3_mask :: scw3_mask [15:00] */ 21593 #define RX66_A_SCW3_MASK_SCW3_MASK_MASK 0xffff 21594 #define RX66_A_SCW3_MASK_SCW3_MASK_ALIGN 0 21595 #define RX66_A_SCW3_MASK_SCW3_MASK_BITS 16 21596 #define RX66_A_SCW3_MASK_SCW3_MASK_SHIFT 0 21597 21598 21599 /**************************************************************************** 21600 * rx66_A :: syncbits 21601 */ 21602 /* rx66_A :: syncbits :: reserved0 [15:04] */ 21603 #define RX66_A_SYNCBITS_RESERVED0_MASK 0xfff0 21604 #define RX66_A_SYNCBITS_RESERVED0_ALIGN 0 21605 #define RX66_A_SYNCBITS_RESERVED0_BITS 12 21606 #define RX66_A_SYNCBITS_RESERVED0_SHIFT 4 21607 21608 /* rx66_A :: syncbits :: syncbits [03:02] */ 21609 #define RX66_A_SYNCBITS_SYNCBITS_MASK 0x000c 21610 #define RX66_A_SYNCBITS_SYNCBITS_ALIGN 0 21611 #define RX66_A_SYNCBITS_SYNCBITS_BITS 2 21612 #define RX66_A_SYNCBITS_SYNCBITS_SHIFT 2 21613 21614 /* rx66_A :: syncbits :: syncbits_mask [01:00] */ 21615 #define RX66_A_SYNCBITS_SYNCBITS_MASK_MASK 0x0003 21616 #define RX66_A_SYNCBITS_SYNCBITS_MASK_ALIGN 0 21617 #define RX66_A_SYNCBITS_SYNCBITS_MASK_BITS 2 21618 #define RX66_A_SYNCBITS_SYNCBITS_MASK_SHIFT 0 21619 21620 21621 /**************************************************************************** 21622 * rx66_A :: scwControl 21623 */ 21624 /* rx66_A :: scwControl :: reserved0 [15:15] */ 21625 #define RX66_A_SCWCONTROL_RESERVED0_MASK 0x8000 21626 #define RX66_A_SCWCONTROL_RESERVED0_ALIGN 0 21627 #define RX66_A_SCWCONTROL_RESERVED0_BITS 1 21628 #define RX66_A_SCWCONTROL_RESERVED0_SHIFT 15 21629 21630 /* rx66_A :: scwControl :: scwCount [14:10] */ 21631 #define RX66_A_SCWCONTROL_SCWCOUNT_MASK 0x7c00 21632 #define RX66_A_SCWCONTROL_SCWCOUNT_ALIGN 0 21633 #define RX66_A_SCWCONTROL_SCWCOUNT_BITS 5 21634 #define RX66_A_SCWCONTROL_SCWCOUNT_SHIFT 10 21635 21636 /* rx66_A :: scwControl :: gcwCount [09:05] */ 21637 #define RX66_A_SCWCONTROL_GCWCOUNT_MASK 0x03e0 21638 #define RX66_A_SCWCONTROL_GCWCOUNT_ALIGN 0 21639 #define RX66_A_SCWCONTROL_GCWCOUNT_BITS 5 21640 #define RX66_A_SCWCONTROL_GCWCOUNT_SHIFT 5 21641 21642 /* rx66_A :: scwControl :: hystCount [04:00] */ 21643 #define RX66_A_SCWCONTROL_HYSTCOUNT_MASK 0x001f 21644 #define RX66_A_SCWCONTROL_HYSTCOUNT_ALIGN 0 21645 #define RX66_A_SCWCONTROL_HYSTCOUNT_BITS 5 21646 #define RX66_A_SCWCONTROL_HYSTCOUNT_SHIFT 0 21647 21648 21649 /**************************************************************************** 21650 * rx66_A :: scwCount 21651 */ 21652 /* rx66_A :: scwCount :: reserved0 [15:15] */ 21653 #define RX66_A_SCWCOUNT_RESERVED0_MASK 0x8000 21654 #define RX66_A_SCWCOUNT_RESERVED0_ALIGN 0 21655 #define RX66_A_SCWCOUNT_RESERVED0_BITS 1 21656 #define RX66_A_SCWCOUNT_RESERVED0_SHIFT 15 21657 21658 /* rx66_A :: scwCount :: scwShift [14:08] */ 21659 #define RX66_A_SCWCOUNT_SCWSHIFT_MASK 0x7f00 21660 #define RX66_A_SCWCOUNT_SCWSHIFT_ALIGN 0 21661 #define RX66_A_SCWCOUNT_SCWSHIFT_BITS 7 21662 #define RX66_A_SCWCOUNT_SCWSHIFT_SHIFT 8 21663 21664 /* union - case COMMA_DETECT [07:00] */ 21665 /* rx66_A :: scwCount :: cwCount [07:00] */ 21666 #define RX66_A_SCWCOUNT_COMMA_DETECT_CWCOUNT_MASK 0x00ff 21667 #define RX66_A_SCWCOUNT_COMMA_DETECT_CWCOUNT_ALIGN 0 21668 #define RX66_A_SCWCOUNT_COMMA_DETECT_CWCOUNT_BITS 8 21669 #define RX66_A_SCWCOUNT_COMMA_DETECT_CWCOUNT_SHIFT 0 21670 21671 21672 /* union - case SYNC_ACQD2 [07:00] */ 21673 /* rx66_A :: scwCount :: cwCount [07:00] */ 21674 #define RX66_A_SCWCOUNT_SYNC_ACQD2_CWCOUNT_MASK 0x00ff 21675 #define RX66_A_SCWCOUNT_SYNC_ACQD2_CWCOUNT_ALIGN 0 21676 #define RX66_A_SCWCOUNT_SYNC_ACQD2_CWCOUNT_BITS 8 21677 #define RX66_A_SCWCOUNT_SYNC_ACQD2_CWCOUNT_SHIFT 0 21678 21679 21680 21681 /**************************************************************************** 21682 * rx66_A :: errCount 21683 */ 21684 /* rx66_A :: errCount :: sync66ErrCount [15:08] */ 21685 #define RX66_A_ERRCOUNT_SYNC66ERRCOUNT_MASK 0xff00 21686 #define RX66_A_ERRCOUNT_SYNC66ERRCOUNT_ALIGN 0 21687 #define RX66_A_ERRCOUNT_SYNC66ERRCOUNT_BITS 8 21688 #define RX66_A_ERRCOUNT_SYNC66ERRCOUNT_SHIFT 8 21689 21690 /* rx66_A :: errCount :: kcode66ErrCount [07:00] */ 21691 #define RX66_A_ERRCOUNT_KCODE66ERRCOUNT_MASK 0x00ff 21692 #define RX66_A_ERRCOUNT_KCODE66ERRCOUNT_ALIGN 0 21693 #define RX66_A_ERRCOUNT_KCODE66ERRCOUNT_BITS 8 21694 #define RX66_A_ERRCOUNT_KCODE66ERRCOUNT_SHIFT 0 21695 21696 21697 /**************************************************************************** 21698 * Hypercore_USER_Dsc1b0 21699 */ 21700 /**************************************************************************** 21701 * Dsc1b0 :: cdr_ctrl0 21702 */ 21703 /* Dsc1b0 :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */ 21704 #define DSC1B0_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xe000 21705 #define DSC1B0_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 21706 #define DSC1B0_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 3 21707 #define DSC1B0_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 13 21708 21709 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 21710 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 21711 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 21712 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_BITS 1 21713 #define DSC1B0_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 21714 21715 /* Dsc1b0 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 21716 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 21717 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 21718 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 21719 #define DSC1B0_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 21720 21721 /* Dsc1b0 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 21722 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 21723 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 21724 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 21725 #define DSC1B0_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 21726 21727 /* Dsc1b0 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 21728 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 21729 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 21730 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 21731 #define DSC1B0_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 21732 21733 /* Dsc1b0 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 21734 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 21735 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 21736 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 21737 #define DSC1B0_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 21738 21739 /* Dsc1b0 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 21740 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 21741 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 21742 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 21743 #define DSC1B0_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 21744 21745 /* Dsc1b0 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 21746 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 21747 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 21748 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 21749 #define DSC1B0_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 21750 21751 /* Dsc1b0 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 21752 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 21753 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 21754 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 21755 #define DSC1B0_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 21756 21757 /* Dsc1b0 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 21758 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 21759 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 21760 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 21761 #define DSC1B0_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 21762 21763 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 21764 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 21765 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 21766 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 21767 #define DSC1B0_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 21768 21769 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 21770 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 21771 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 21772 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_BITS 1 21773 #define DSC1B0_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 21774 21775 /* Dsc1b0 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 21776 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 21777 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 21778 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 21779 #define DSC1B0_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 21780 21781 21782 /**************************************************************************** 21783 * Dsc1b0 :: cdr_ctrl1 21784 */ 21785 /* Dsc1b0 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 21786 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 21787 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 21788 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 21789 #define DSC1B0_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 21790 21791 21792 /**************************************************************************** 21793 * Dsc1b0 :: cdr_ctrl2 21794 */ 21795 /* Dsc1b0 :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */ 21796 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xffc0 21797 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 21798 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 10 21799 #define DSC1B0_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 6 21800 21801 /* Dsc1b0 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 21802 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 21803 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 21804 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 21805 #define DSC1B0_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 21806 21807 21808 /**************************************************************************** 21809 * Dsc1b0 :: pi_ctrl0 21810 */ 21811 /* Dsc1b0 :: pi_ctrl0 :: pi_cw_rst [15:15] */ 21812 #define DSC1B0_PI_CTRL0_PI_CW_RST_MASK 0x8000 21813 #define DSC1B0_PI_CTRL0_PI_CW_RST_ALIGN 0 21814 #define DSC1B0_PI_CTRL0_PI_CW_RST_BITS 1 21815 #define DSC1B0_PI_CTRL0_PI_CW_RST_SHIFT 15 21816 21817 /* Dsc1b0 :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */ 21818 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_MASK 0x7000 21819 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_ALIGN 0 21820 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_BITS 3 21821 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_SHIFT 12 21822 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb 0 21823 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb 1 21824 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb 2 21825 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb 3 21826 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb 4 21827 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb 5 21828 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb 6 21829 #define DSC1B0_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb 7 21830 21831 /* Dsc1b0 :: pi_ctrl0 :: reserved_for_eco0 [11:11] */ 21832 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0x0800 21833 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 21834 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_BITS 1 21835 #define DSC1B0_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 21836 21837 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_invert [10:10] */ 21838 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 21839 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 21840 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_BITS 1 21841 #define DSC1B0_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 21842 21843 /* Dsc1b0 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 21844 #define DSC1B0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 21845 #define DSC1B0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 21846 #define DSC1B0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 21847 #define DSC1B0_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 21848 21849 /* Dsc1b0 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 21850 #define DSC1B0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 21851 #define DSC1B0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 21852 #define DSC1B0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 21853 #define DSC1B0_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 21854 21855 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_dec [07:07] */ 21856 #define DSC1B0_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 21857 #define DSC1B0_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 21858 #define DSC1B0_PI_CTRL0_PI_PHASE_DEC_BITS 1 21859 #define DSC1B0_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 21860 21861 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_inc [06:06] */ 21862 #define DSC1B0_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 21863 #define DSC1B0_PI_CTRL0_PI_PHASE_INC_ALIGN 0 21864 #define DSC1B0_PI_CTRL0_PI_PHASE_INC_BITS 1 21865 #define DSC1B0_PI_CTRL0_PI_PHASE_INC_SHIFT 6 21866 21867 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 21868 #define DSC1B0_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 21869 #define DSC1B0_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 21870 #define DSC1B0_PI_CTRL0_PI_PHASE_STROBE_BITS 1 21871 #define DSC1B0_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 21872 21873 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_delta [04:01] */ 21874 #define DSC1B0_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 21875 #define DSC1B0_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 21876 #define DSC1B0_PI_CTRL0_PI_PHASE_DELTA_BITS 4 21877 #define DSC1B0_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 21878 21879 /* Dsc1b0 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 21880 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 21881 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 21882 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 21883 #define DSC1B0_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 21884 21885 21886 /**************************************************************************** 21887 * Dsc1b0 :: dfe_vga_ctrl0 21888 */ 21889 /* Dsc1b0 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */ 21890 #define DSC1B0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xff00 21891 #define DSC1B0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 21892 #define DSC1B0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 8 21893 #define DSC1B0_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 8 21894 21895 /* Dsc1b0 :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */ 21896 #define DSC1B0_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK 0x00c0 21897 #define DSC1B0_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN 0 21898 #define DSC1B0_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS 2 21899 #define DSC1B0_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT 6 21900 21901 /* Dsc1b0 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 21902 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 21903 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 21904 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 21905 #define DSC1B0_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 21906 21907 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 21908 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 21909 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 21910 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 21911 #define DSC1B0_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 21912 21913 /* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 21914 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 21915 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 21916 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 21917 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 21918 21919 /* Dsc1b0 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 21920 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 21921 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 21922 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 21923 #define DSC1B0_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 21924 21925 /* Dsc1b0 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 21926 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 21927 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 21928 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 21929 #define DSC1B0_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 21930 21931 /* Dsc1b0 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 21932 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 21933 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 21934 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 21935 #define DSC1B0_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 21936 21937 21938 /**************************************************************************** 21939 * Dsc1b0 :: dfe_vga_ctrl1 21940 */ 21941 /* Dsc1b0 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */ 21942 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0xe000 21943 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 21944 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 3 21945 #define DSC1B0_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 13 21946 21947 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */ 21948 #define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK 0x1f80 21949 #define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN 0 21950 #define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS 6 21951 #define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT 7 21952 21953 /* Dsc1b0 :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */ 21954 #define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK 0x0040 21955 #define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN 0 21956 #define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS 1 21957 #define DSC1B0_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT 6 21958 21959 /* Dsc1b0 :: dfe_vga_ctrl1 :: vga_write_val [05:01] */ 21960 #define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK 0x003e 21961 #define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN 0 21962 #define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS 5 21963 #define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT 1 21964 21965 /* Dsc1b0 :: dfe_vga_ctrl1 :: vga_write_en [00:00] */ 21966 #define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK 0x0001 21967 #define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN 0 21968 #define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS 1 21969 #define DSC1B0_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT 0 21970 21971 21972 /**************************************************************************** 21973 * Dsc1b0 :: dfe_vga_ctrl2 21974 */ 21975 /* Dsc1b0 :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */ 21976 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 21977 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 21978 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS 2 21979 #define DSC1B0_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 21980 21981 /* Dsc1b0 :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */ 21982 #define DSC1B0_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK 0x3f80 21983 #define DSC1B0_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN 0 21984 #define DSC1B0_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS 7 21985 #define DSC1B0_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT 7 21986 21987 /* Dsc1b0 :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */ 21988 #define DSC1B0_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK 0x007f 21989 #define DSC1B0_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN 0 21990 #define DSC1B0_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS 7 21991 #define DSC1B0_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT 0 21992 21993 21994 /**************************************************************************** 21995 * Dsc1b0 :: dfe_vga_ctrl3 21996 */ 21997 /* Dsc1b0 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */ 21998 #define DSC1B0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xc000 21999 #define DSC1B0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 22000 #define DSC1B0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 2 22001 #define DSC1B0_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 14 22002 22003 /* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */ 22004 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK 0x3f80 22005 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN 0 22006 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS 7 22007 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT 7 22008 22009 /* Dsc1b0 :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */ 22010 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK 0x007f 22011 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN 0 22012 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS 7 22013 #define DSC1B0_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT 0 22014 22015 22016 /**************************************************************************** 22017 * Dsc1b0 :: dfe_vga_ctrl4 22018 */ 22019 /* Dsc1b0 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 22020 #define DSC1B0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 22021 #define DSC1B0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 22022 #define DSC1B0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 22023 #define DSC1B0_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 22024 22025 /* Dsc1b0 :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */ 22026 #define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK 0x03e0 22027 #define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN 0 22028 #define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS 5 22029 #define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT 5 22030 22031 /* Dsc1b0 :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */ 22032 #define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK 0x001f 22033 #define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN 0 22034 #define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS 5 22035 #define DSC1B0_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT 0 22036 22037 22038 /**************************************************************************** 22039 * Dsc1b0 :: dfe_vga_ctrl5 22040 */ 22041 /* Dsc1b0 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */ 22042 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK 0xfc00 22043 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 22044 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS 6 22045 #define DSC1B0_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT 10 22046 22047 /* Dsc1b0 :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */ 22048 #define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK 0x03e0 22049 #define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN 0 22050 #define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS 5 22051 #define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT 5 22052 22053 /* Dsc1b0 :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */ 22054 #define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK 0x001f 22055 #define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN 0 22056 #define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS 5 22057 #define DSC1B0_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT 0 22058 22059 22060 /**************************************************************************** 22061 * Dsc1b0 :: dsc_ana_ctrl0 22062 */ 22063 /* Dsc1b0 :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */ 22064 #define DSC1B0_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK 0x8000 22065 #define DSC1B0_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN 0 22066 #define DSC1B0_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS 1 22067 #define DSC1B0_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT 15 22068 22069 /* Dsc1b0 :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */ 22070 #define DSC1B0_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x7c00 22071 #define DSC1B0_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 22072 #define DSC1B0_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 5 22073 #define DSC1B0_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 10 22074 22075 /* Dsc1b0 :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */ 22076 #define DSC1B0_DSC_ANA_CTRL0_D_ODD_CTRL_MASK 0x03e0 22077 #define DSC1B0_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN 0 22078 #define DSC1B0_DSC_ANA_CTRL0_D_ODD_CTRL_BITS 5 22079 #define DSC1B0_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT 5 22080 22081 /* Dsc1b0 :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */ 22082 #define DSC1B0_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK 0x001f 22083 #define DSC1B0_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN 0 22084 #define DSC1B0_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS 5 22085 #define DSC1B0_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT 0 22086 22087 22088 /**************************************************************************** 22089 * Dsc1b0 :: dsc_ana_ctrl1 22090 */ 22091 /* Dsc1b0 :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */ 22092 #define DSC1B0_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK 0x8000 22093 #define DSC1B0_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN 0 22094 #define DSC1B0_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS 1 22095 #define DSC1B0_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT 15 22096 22097 /* Dsc1b0 :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */ 22098 #define DSC1B0_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK 0x7c00 22099 #define DSC1B0_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN 0 22100 #define DSC1B0_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS 5 22101 #define DSC1B0_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT 10 22102 22103 /* Dsc1b0 :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */ 22104 #define DSC1B0_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x03e0 22105 #define DSC1B0_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 22106 #define DSC1B0_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 5 22107 #define DSC1B0_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 5 22108 22109 /* Dsc1b0 :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */ 22110 #define DSC1B0_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK 0x001f 22111 #define DSC1B0_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN 0 22112 #define DSC1B0_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS 5 22113 #define DSC1B0_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT 0 22114 22115 22116 /**************************************************************************** 22117 * Dsc1b0 :: dsc_ana_ctrl2 22118 */ 22119 /* Dsc1b0 :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */ 22120 #define DSC1B0_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK 0x8000 22121 #define DSC1B0_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN 0 22122 #define DSC1B0_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS 1 22123 #define DSC1B0_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT 15 22124 22125 /* Dsc1b0 :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */ 22126 #define DSC1B0_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK 0x4000 22127 #define DSC1B0_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN 0 22128 #define DSC1B0_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS 1 22129 #define DSC1B0_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT 14 22130 22131 /* Dsc1b0 :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */ 22132 #define DSC1B0_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK 0x2000 22133 #define DSC1B0_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN 0 22134 #define DSC1B0_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS 1 22135 #define DSC1B0_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT 13 22136 22137 /* Dsc1b0 :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */ 22138 #define DSC1B0_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK 0x1000 22139 #define DSC1B0_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN 0 22140 #define DSC1B0_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS 1 22141 #define DSC1B0_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT 12 22142 22143 /* Dsc1b0 :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */ 22144 #define DSC1B0_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK 0x0800 22145 #define DSC1B0_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN 0 22146 #define DSC1B0_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS 1 22147 #define DSC1B0_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT 11 22148 22149 /* Dsc1b0 :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */ 22150 #define DSC1B0_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK 0x0400 22151 #define DSC1B0_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN 0 22152 #define DSC1B0_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS 1 22153 #define DSC1B0_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT 10 22154 22155 /* Dsc1b0 :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */ 22156 #define DSC1B0_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK 0x0200 22157 #define DSC1B0_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN 0 22158 #define DSC1B0_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS 1 22159 #define DSC1B0_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT 9 22160 22161 /* Dsc1b0 :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */ 22162 #define DSC1B0_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK 0x0100 22163 #define DSC1B0_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN 0 22164 #define DSC1B0_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS 1 22165 #define DSC1B0_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT 8 22166 22167 /* Dsc1b0 :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */ 22168 #define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK 0x0080 22169 #define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 22170 #define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS 1 22171 #define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT 7 22172 22173 /* Dsc1b0 :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */ 22174 #define DSC1B0_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK 0x0040 22175 #define DSC1B0_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN 0 22176 #define DSC1B0_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS 1 22177 #define DSC1B0_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT 6 22178 22179 /* Dsc1b0 :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */ 22180 #define DSC1B0_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK 0x0030 22181 #define DSC1B0_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN 0 22182 #define DSC1B0_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS 2 22183 #define DSC1B0_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT 4 22184 22185 /* Dsc1b0 :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */ 22186 #define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK 0x0008 22187 #define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN 0 22188 #define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS 1 22189 #define DSC1B0_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT 3 22190 22191 /* Dsc1b0 :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */ 22192 #define DSC1B0_DSC_ANA_CTRL2_RX_PF_CTRL_MASK 0x0007 22193 #define DSC1B0_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN 0 22194 #define DSC1B0_DSC_ANA_CTRL2_RX_PF_CTRL_BITS 3 22195 #define DSC1B0_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT 0 22196 22197 22198 /**************************************************************************** 22199 * Dsc1b0 :: dsc_100fx_ctrl 22200 */ 22201 /* Dsc1b0 :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */ 22202 #define DSC1B0_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK 0xf800 22203 #define DSC1B0_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN 0 22204 #define DSC1B0_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS 5 22205 #define DSC1B0_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT 11 22206 22207 /* Dsc1b0 :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */ 22208 #define DSC1B0_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK 0x0600 22209 #define DSC1B0_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN 0 22210 #define DSC1B0_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS 2 22211 #define DSC1B0_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT 9 22212 22213 /* Dsc1b0 :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */ 22214 #define DSC1B0_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 22215 #define DSC1B0_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN 0 22216 #define DSC1B0_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS 1 22217 #define DSC1B0_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT 8 22218 22219 /* Dsc1b0 :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */ 22220 #define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 22221 #define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN 0 22222 #define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS 4 22223 #define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT 4 22224 22225 /* Dsc1b0 :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */ 22226 #define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK 0x000f 22227 #define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN 0 22228 #define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS 4 22229 #define DSC1B0_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT 0 22230 22231 22232 /**************************************************************************** 22233 * Dsc1b0 :: dsc_ana_ctrl3 22234 */ 22235 /* Dsc1b0 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */ 22236 #define DSC1B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK 0xffc0 22237 #define DSC1B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 22238 #define DSC1B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS 10 22239 #define DSC1B0_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT 6 22240 22241 /* Dsc1b0 :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */ 22242 #define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK 0x0020 22243 #define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN 0 22244 #define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS 1 22245 #define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT 5 22246 22247 /* Dsc1b0 :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */ 22248 #define DSC1B0_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK 0x0010 22249 #define DSC1B0_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN 0 22250 #define DSC1B0_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS 1 22251 #define DSC1B0_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT 4 22252 22253 /* Dsc1b0 :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */ 22254 #define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK 0x0008 22255 #define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN 0 22256 #define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS 1 22257 #define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT 3 22258 22259 /* Dsc1b0 :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */ 22260 #define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK 0x0004 22261 #define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN 0 22262 #define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS 1 22263 #define DSC1B0_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT 2 22264 22265 /* Dsc1b0 :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */ 22266 #define DSC1B0_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK 0x0002 22267 #define DSC1B0_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN 0 22268 #define DSC1B0_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS 1 22269 #define DSC1B0_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT 1 22270 22271 /* Dsc1b0 :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */ 22272 #define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK 0x0001 22273 #define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN 0 22274 #define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS 1 22275 #define DSC1B0_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT 0 22276 22277 22278 /**************************************************************************** 22279 * Hypercore_USER_Dsc1b1 22280 */ 22281 /**************************************************************************** 22282 * Dsc1b1 :: cdr_ctrl0 22283 */ 22284 /* Dsc1b1 :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */ 22285 #define DSC1B1_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xe000 22286 #define DSC1B1_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 22287 #define DSC1B1_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 3 22288 #define DSC1B1_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 13 22289 22290 /* Dsc1b1 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 22291 #define DSC1B1_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 22292 #define DSC1B1_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 22293 #define DSC1B1_CDR_CTRL0_CDRBR_POLARITY_BITS 1 22294 #define DSC1B1_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 22295 22296 /* Dsc1b1 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 22297 #define DSC1B1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 22298 #define DSC1B1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 22299 #define DSC1B1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 22300 #define DSC1B1_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 22301 22302 /* Dsc1b1 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 22303 #define DSC1B1_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 22304 #define DSC1B1_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 22305 #define DSC1B1_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 22306 #define DSC1B1_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 22307 22308 /* Dsc1b1 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 22309 #define DSC1B1_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 22310 #define DSC1B1_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 22311 #define DSC1B1_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 22312 #define DSC1B1_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 22313 22314 /* Dsc1b1 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 22315 #define DSC1B1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 22316 #define DSC1B1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 22317 #define DSC1B1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 22318 #define DSC1B1_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 22319 22320 /* Dsc1b1 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 22321 #define DSC1B1_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 22322 #define DSC1B1_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 22323 #define DSC1B1_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 22324 #define DSC1B1_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 22325 22326 /* Dsc1b1 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 22327 #define DSC1B1_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 22328 #define DSC1B1_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 22329 #define DSC1B1_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 22330 #define DSC1B1_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 22331 22332 /* Dsc1b1 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 22333 #define DSC1B1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 22334 #define DSC1B1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 22335 #define DSC1B1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 22336 #define DSC1B1_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 22337 22338 /* Dsc1b1 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 22339 #define DSC1B1_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 22340 #define DSC1B1_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 22341 #define DSC1B1_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 22342 #define DSC1B1_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 22343 22344 /* Dsc1b1 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 22345 #define DSC1B1_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 22346 #define DSC1B1_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 22347 #define DSC1B1_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 22348 #define DSC1B1_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 22349 22350 /* Dsc1b1 :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 22351 #define DSC1B1_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 22352 #define DSC1B1_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 22353 #define DSC1B1_CDR_CTRL0_CDR_FREQ_EN_BITS 1 22354 #define DSC1B1_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 22355 22356 /* Dsc1b1 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 22357 #define DSC1B1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 22358 #define DSC1B1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 22359 #define DSC1B1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 22360 #define DSC1B1_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 22361 22362 22363 /**************************************************************************** 22364 * Dsc1b1 :: cdr_ctrl1 22365 */ 22366 /* Dsc1b1 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 22367 #define DSC1B1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 22368 #define DSC1B1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 22369 #define DSC1B1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 22370 #define DSC1B1_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 22371 22372 22373 /**************************************************************************** 22374 * Dsc1b1 :: cdr_ctrl2 22375 */ 22376 /* Dsc1b1 :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */ 22377 #define DSC1B1_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xffc0 22378 #define DSC1B1_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 22379 #define DSC1B1_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 10 22380 #define DSC1B1_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 6 22381 22382 /* Dsc1b1 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 22383 #define DSC1B1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 22384 #define DSC1B1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 22385 #define DSC1B1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 22386 #define DSC1B1_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 22387 22388 22389 /**************************************************************************** 22390 * Dsc1b1 :: pi_ctrl0 22391 */ 22392 /* Dsc1b1 :: pi_ctrl0 :: pi_cw_rst [15:15] */ 22393 #define DSC1B1_PI_CTRL0_PI_CW_RST_MASK 0x8000 22394 #define DSC1B1_PI_CTRL0_PI_CW_RST_ALIGN 0 22395 #define DSC1B1_PI_CTRL0_PI_CW_RST_BITS 1 22396 #define DSC1B1_PI_CTRL0_PI_CW_RST_SHIFT 15 22397 22398 /* Dsc1b1 :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */ 22399 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_MASK 0x7000 22400 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_ALIGN 0 22401 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_BITS 3 22402 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_SHIFT 12 22403 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb 0 22404 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb 1 22405 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb 2 22406 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb 3 22407 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb 4 22408 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb 5 22409 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb 6 22410 #define DSC1B1_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb 7 22411 22412 /* Dsc1b1 :: pi_ctrl0 :: reserved_for_eco0 [11:11] */ 22413 #define DSC1B1_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0x0800 22414 #define DSC1B1_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 22415 #define DSC1B1_PI_CTRL0_RESERVED_FOR_ECO0_BITS 1 22416 #define DSC1B1_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 22417 22418 /* Dsc1b1 :: pi_ctrl0 :: pi_phase_invert [10:10] */ 22419 #define DSC1B1_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 22420 #define DSC1B1_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 22421 #define DSC1B1_PI_CTRL0_PI_PHASE_INVERT_BITS 1 22422 #define DSC1B1_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 22423 22424 /* Dsc1b1 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 22425 #define DSC1B1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 22426 #define DSC1B1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 22427 #define DSC1B1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 22428 #define DSC1B1_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 22429 22430 /* Dsc1b1 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 22431 #define DSC1B1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 22432 #define DSC1B1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 22433 #define DSC1B1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 22434 #define DSC1B1_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 22435 22436 /* Dsc1b1 :: pi_ctrl0 :: pi_phase_dec [07:07] */ 22437 #define DSC1B1_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 22438 #define DSC1B1_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 22439 #define DSC1B1_PI_CTRL0_PI_PHASE_DEC_BITS 1 22440 #define DSC1B1_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 22441 22442 /* Dsc1b1 :: pi_ctrl0 :: pi_phase_inc [06:06] */ 22443 #define DSC1B1_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 22444 #define DSC1B1_PI_CTRL0_PI_PHASE_INC_ALIGN 0 22445 #define DSC1B1_PI_CTRL0_PI_PHASE_INC_BITS 1 22446 #define DSC1B1_PI_CTRL0_PI_PHASE_INC_SHIFT 6 22447 22448 /* Dsc1b1 :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 22449 #define DSC1B1_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 22450 #define DSC1B1_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 22451 #define DSC1B1_PI_CTRL0_PI_PHASE_STROBE_BITS 1 22452 #define DSC1B1_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 22453 22454 /* Dsc1b1 :: pi_ctrl0 :: pi_phase_delta [04:01] */ 22455 #define DSC1B1_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 22456 #define DSC1B1_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 22457 #define DSC1B1_PI_CTRL0_PI_PHASE_DELTA_BITS 4 22458 #define DSC1B1_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 22459 22460 /* Dsc1b1 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 22461 #define DSC1B1_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 22462 #define DSC1B1_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 22463 #define DSC1B1_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 22464 #define DSC1B1_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 22465 22466 22467 /**************************************************************************** 22468 * Dsc1b1 :: dfe_vga_ctrl0 22469 */ 22470 /* Dsc1b1 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */ 22471 #define DSC1B1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xff00 22472 #define DSC1B1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 22473 #define DSC1B1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 8 22474 #define DSC1B1_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 8 22475 22476 /* Dsc1b1 :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */ 22477 #define DSC1B1_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK 0x00c0 22478 #define DSC1B1_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN 0 22479 #define DSC1B1_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS 2 22480 #define DSC1B1_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT 6 22481 22482 /* Dsc1b1 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 22483 #define DSC1B1_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 22484 #define DSC1B1_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 22485 #define DSC1B1_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 22486 #define DSC1B1_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 22487 22488 /* Dsc1b1 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 22489 #define DSC1B1_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 22490 #define DSC1B1_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 22491 #define DSC1B1_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 22492 #define DSC1B1_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 22493 22494 /* Dsc1b1 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 22495 #define DSC1B1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 22496 #define DSC1B1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 22497 #define DSC1B1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 22498 #define DSC1B1_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 22499 22500 /* Dsc1b1 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 22501 #define DSC1B1_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 22502 #define DSC1B1_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 22503 #define DSC1B1_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 22504 #define DSC1B1_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 22505 22506 /* Dsc1b1 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 22507 #define DSC1B1_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 22508 #define DSC1B1_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 22509 #define DSC1B1_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 22510 #define DSC1B1_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 22511 22512 /* Dsc1b1 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 22513 #define DSC1B1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 22514 #define DSC1B1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 22515 #define DSC1B1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 22516 #define DSC1B1_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 22517 22518 22519 /**************************************************************************** 22520 * Dsc1b1 :: dfe_vga_ctrl1 22521 */ 22522 /* Dsc1b1 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */ 22523 #define DSC1B1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0xe000 22524 #define DSC1B1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 22525 #define DSC1B1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 3 22526 #define DSC1B1_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 13 22527 22528 /* Dsc1b1 :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */ 22529 #define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK 0x1f80 22530 #define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN 0 22531 #define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS 6 22532 #define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT 7 22533 22534 /* Dsc1b1 :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */ 22535 #define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK 0x0040 22536 #define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN 0 22537 #define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS 1 22538 #define DSC1B1_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT 6 22539 22540 /* Dsc1b1 :: dfe_vga_ctrl1 :: vga_write_val [05:01] */ 22541 #define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK 0x003e 22542 #define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN 0 22543 #define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS 5 22544 #define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT 1 22545 22546 /* Dsc1b1 :: dfe_vga_ctrl1 :: vga_write_en [00:00] */ 22547 #define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK 0x0001 22548 #define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN 0 22549 #define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS 1 22550 #define DSC1B1_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT 0 22551 22552 22553 /**************************************************************************** 22554 * Dsc1b1 :: dfe_vga_ctrl2 22555 */ 22556 /* Dsc1b1 :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */ 22557 #define DSC1B1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 22558 #define DSC1B1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 22559 #define DSC1B1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS 2 22560 #define DSC1B1_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 22561 22562 /* Dsc1b1 :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */ 22563 #define DSC1B1_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK 0x3f80 22564 #define DSC1B1_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN 0 22565 #define DSC1B1_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS 7 22566 #define DSC1B1_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT 7 22567 22568 /* Dsc1b1 :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */ 22569 #define DSC1B1_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK 0x007f 22570 #define DSC1B1_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN 0 22571 #define DSC1B1_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS 7 22572 #define DSC1B1_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT 0 22573 22574 22575 /**************************************************************************** 22576 * Dsc1b1 :: dfe_vga_ctrl3 22577 */ 22578 /* Dsc1b1 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */ 22579 #define DSC1B1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xc000 22580 #define DSC1B1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 22581 #define DSC1B1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 2 22582 #define DSC1B1_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 14 22583 22584 /* Dsc1b1 :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */ 22585 #define DSC1B1_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK 0x3f80 22586 #define DSC1B1_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN 0 22587 #define DSC1B1_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS 7 22588 #define DSC1B1_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT 7 22589 22590 /* Dsc1b1 :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */ 22591 #define DSC1B1_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK 0x007f 22592 #define DSC1B1_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN 0 22593 #define DSC1B1_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS 7 22594 #define DSC1B1_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT 0 22595 22596 22597 /**************************************************************************** 22598 * Dsc1b1 :: dfe_vga_ctrl4 22599 */ 22600 /* Dsc1b1 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 22601 #define DSC1B1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 22602 #define DSC1B1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 22603 #define DSC1B1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 22604 #define DSC1B1_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 22605 22606 /* Dsc1b1 :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */ 22607 #define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK 0x03e0 22608 #define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN 0 22609 #define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS 5 22610 #define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT 5 22611 22612 /* Dsc1b1 :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */ 22613 #define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK 0x001f 22614 #define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN 0 22615 #define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS 5 22616 #define DSC1B1_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT 0 22617 22618 22619 /**************************************************************************** 22620 * Dsc1b1 :: dfe_vga_ctrl5 22621 */ 22622 /* Dsc1b1 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */ 22623 #define DSC1B1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK 0xfc00 22624 #define DSC1B1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 22625 #define DSC1B1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS 6 22626 #define DSC1B1_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT 10 22627 22628 /* Dsc1b1 :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */ 22629 #define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK 0x03e0 22630 #define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN 0 22631 #define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS 5 22632 #define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT 5 22633 22634 /* Dsc1b1 :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */ 22635 #define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK 0x001f 22636 #define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN 0 22637 #define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS 5 22638 #define DSC1B1_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT 0 22639 22640 22641 /**************************************************************************** 22642 * Dsc1b1 :: dsc_ana_ctrl0 22643 */ 22644 /* Dsc1b1 :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */ 22645 #define DSC1B1_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK 0x8000 22646 #define DSC1B1_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN 0 22647 #define DSC1B1_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS 1 22648 #define DSC1B1_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT 15 22649 22650 /* Dsc1b1 :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */ 22651 #define DSC1B1_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x7c00 22652 #define DSC1B1_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 22653 #define DSC1B1_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 5 22654 #define DSC1B1_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 10 22655 22656 /* Dsc1b1 :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */ 22657 #define DSC1B1_DSC_ANA_CTRL0_D_ODD_CTRL_MASK 0x03e0 22658 #define DSC1B1_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN 0 22659 #define DSC1B1_DSC_ANA_CTRL0_D_ODD_CTRL_BITS 5 22660 #define DSC1B1_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT 5 22661 22662 /* Dsc1b1 :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */ 22663 #define DSC1B1_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK 0x001f 22664 #define DSC1B1_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN 0 22665 #define DSC1B1_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS 5 22666 #define DSC1B1_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT 0 22667 22668 22669 /**************************************************************************** 22670 * Dsc1b1 :: dsc_ana_ctrl1 22671 */ 22672 /* Dsc1b1 :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */ 22673 #define DSC1B1_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK 0x8000 22674 #define DSC1B1_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN 0 22675 #define DSC1B1_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS 1 22676 #define DSC1B1_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT 15 22677 22678 /* Dsc1b1 :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */ 22679 #define DSC1B1_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK 0x7c00 22680 #define DSC1B1_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN 0 22681 #define DSC1B1_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS 5 22682 #define DSC1B1_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT 10 22683 22684 /* Dsc1b1 :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */ 22685 #define DSC1B1_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x03e0 22686 #define DSC1B1_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 22687 #define DSC1B1_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 5 22688 #define DSC1B1_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 5 22689 22690 /* Dsc1b1 :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */ 22691 #define DSC1B1_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK 0x001f 22692 #define DSC1B1_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN 0 22693 #define DSC1B1_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS 5 22694 #define DSC1B1_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT 0 22695 22696 22697 /**************************************************************************** 22698 * Dsc1b1 :: dsc_ana_ctrl2 22699 */ 22700 /* Dsc1b1 :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */ 22701 #define DSC1B1_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK 0x8000 22702 #define DSC1B1_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN 0 22703 #define DSC1B1_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS 1 22704 #define DSC1B1_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT 15 22705 22706 /* Dsc1b1 :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */ 22707 #define DSC1B1_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK 0x4000 22708 #define DSC1B1_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN 0 22709 #define DSC1B1_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS 1 22710 #define DSC1B1_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT 14 22711 22712 /* Dsc1b1 :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */ 22713 #define DSC1B1_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK 0x2000 22714 #define DSC1B1_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN 0 22715 #define DSC1B1_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS 1 22716 #define DSC1B1_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT 13 22717 22718 /* Dsc1b1 :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */ 22719 #define DSC1B1_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK 0x1000 22720 #define DSC1B1_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN 0 22721 #define DSC1B1_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS 1 22722 #define DSC1B1_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT 12 22723 22724 /* Dsc1b1 :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */ 22725 #define DSC1B1_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK 0x0800 22726 #define DSC1B1_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN 0 22727 #define DSC1B1_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS 1 22728 #define DSC1B1_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT 11 22729 22730 /* Dsc1b1 :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */ 22731 #define DSC1B1_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK 0x0400 22732 #define DSC1B1_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN 0 22733 #define DSC1B1_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS 1 22734 #define DSC1B1_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT 10 22735 22736 /* Dsc1b1 :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */ 22737 #define DSC1B1_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK 0x0200 22738 #define DSC1B1_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN 0 22739 #define DSC1B1_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS 1 22740 #define DSC1B1_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT 9 22741 22742 /* Dsc1b1 :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */ 22743 #define DSC1B1_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK 0x0100 22744 #define DSC1B1_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN 0 22745 #define DSC1B1_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS 1 22746 #define DSC1B1_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT 8 22747 22748 /* Dsc1b1 :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */ 22749 #define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK 0x0080 22750 #define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 22751 #define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS 1 22752 #define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT 7 22753 22754 /* Dsc1b1 :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */ 22755 #define DSC1B1_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK 0x0040 22756 #define DSC1B1_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN 0 22757 #define DSC1B1_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS 1 22758 #define DSC1B1_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT 6 22759 22760 /* Dsc1b1 :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */ 22761 #define DSC1B1_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK 0x0030 22762 #define DSC1B1_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN 0 22763 #define DSC1B1_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS 2 22764 #define DSC1B1_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT 4 22765 22766 /* Dsc1b1 :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */ 22767 #define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK 0x0008 22768 #define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN 0 22769 #define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS 1 22770 #define DSC1B1_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT 3 22771 22772 /* Dsc1b1 :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */ 22773 #define DSC1B1_DSC_ANA_CTRL2_RX_PF_CTRL_MASK 0x0007 22774 #define DSC1B1_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN 0 22775 #define DSC1B1_DSC_ANA_CTRL2_RX_PF_CTRL_BITS 3 22776 #define DSC1B1_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT 0 22777 22778 22779 /**************************************************************************** 22780 * Dsc1b1 :: dsc_100fx_ctrl 22781 */ 22782 /* Dsc1b1 :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */ 22783 #define DSC1B1_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK 0xf800 22784 #define DSC1B1_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN 0 22785 #define DSC1B1_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS 5 22786 #define DSC1B1_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT 11 22787 22788 /* Dsc1b1 :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */ 22789 #define DSC1B1_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK 0x0600 22790 #define DSC1B1_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN 0 22791 #define DSC1B1_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS 2 22792 #define DSC1B1_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT 9 22793 22794 /* Dsc1b1 :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */ 22795 #define DSC1B1_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 22796 #define DSC1B1_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN 0 22797 #define DSC1B1_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS 1 22798 #define DSC1B1_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT 8 22799 22800 /* Dsc1b1 :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */ 22801 #define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 22802 #define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN 0 22803 #define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS 4 22804 #define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT 4 22805 22806 /* Dsc1b1 :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */ 22807 #define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK 0x000f 22808 #define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN 0 22809 #define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS 4 22810 #define DSC1B1_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT 0 22811 22812 22813 /**************************************************************************** 22814 * Dsc1b1 :: dsc_ana_ctrl3 22815 */ 22816 /* Dsc1b1 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */ 22817 #define DSC1B1_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK 0xffc0 22818 #define DSC1B1_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 22819 #define DSC1B1_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS 10 22820 #define DSC1B1_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT 6 22821 22822 /* Dsc1b1 :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */ 22823 #define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK 0x0020 22824 #define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN 0 22825 #define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS 1 22826 #define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT 5 22827 22828 /* Dsc1b1 :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */ 22829 #define DSC1B1_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK 0x0010 22830 #define DSC1B1_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN 0 22831 #define DSC1B1_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS 1 22832 #define DSC1B1_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT 4 22833 22834 /* Dsc1b1 :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */ 22835 #define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK 0x0008 22836 #define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN 0 22837 #define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS 1 22838 #define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT 3 22839 22840 /* Dsc1b1 :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */ 22841 #define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK 0x0004 22842 #define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN 0 22843 #define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS 1 22844 #define DSC1B1_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT 2 22845 22846 /* Dsc1b1 :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */ 22847 #define DSC1B1_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK 0x0002 22848 #define DSC1B1_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN 0 22849 #define DSC1B1_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS 1 22850 #define DSC1B1_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT 1 22851 22852 /* Dsc1b1 :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */ 22853 #define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK 0x0001 22854 #define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN 0 22855 #define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS 1 22856 #define DSC1B1_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT 0 22857 22858 22859 /**************************************************************************** 22860 * Hypercore_USER_Dsc1b2 22861 */ 22862 /**************************************************************************** 22863 * Dsc1b2 :: cdr_ctrl0 22864 */ 22865 /* Dsc1b2 :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */ 22866 #define DSC1B2_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xe000 22867 #define DSC1B2_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 22868 #define DSC1B2_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 3 22869 #define DSC1B2_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 13 22870 22871 /* Dsc1b2 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 22872 #define DSC1B2_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 22873 #define DSC1B2_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 22874 #define DSC1B2_CDR_CTRL0_CDRBR_POLARITY_BITS 1 22875 #define DSC1B2_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 22876 22877 /* Dsc1b2 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 22878 #define DSC1B2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 22879 #define DSC1B2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 22880 #define DSC1B2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 22881 #define DSC1B2_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 22882 22883 /* Dsc1b2 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 22884 #define DSC1B2_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 22885 #define DSC1B2_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 22886 #define DSC1B2_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 22887 #define DSC1B2_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 22888 22889 /* Dsc1b2 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 22890 #define DSC1B2_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 22891 #define DSC1B2_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 22892 #define DSC1B2_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 22893 #define DSC1B2_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 22894 22895 /* Dsc1b2 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 22896 #define DSC1B2_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 22897 #define DSC1B2_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 22898 #define DSC1B2_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 22899 #define DSC1B2_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 22900 22901 /* Dsc1b2 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 22902 #define DSC1B2_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 22903 #define DSC1B2_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 22904 #define DSC1B2_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 22905 #define DSC1B2_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 22906 22907 /* Dsc1b2 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 22908 #define DSC1B2_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 22909 #define DSC1B2_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 22910 #define DSC1B2_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 22911 #define DSC1B2_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 22912 22913 /* Dsc1b2 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 22914 #define DSC1B2_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 22915 #define DSC1B2_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 22916 #define DSC1B2_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 22917 #define DSC1B2_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 22918 22919 /* Dsc1b2 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 22920 #define DSC1B2_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 22921 #define DSC1B2_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 22922 #define DSC1B2_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 22923 #define DSC1B2_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 22924 22925 /* Dsc1b2 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 22926 #define DSC1B2_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 22927 #define DSC1B2_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 22928 #define DSC1B2_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 22929 #define DSC1B2_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 22930 22931 /* Dsc1b2 :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 22932 #define DSC1B2_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 22933 #define DSC1B2_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 22934 #define DSC1B2_CDR_CTRL0_CDR_FREQ_EN_BITS 1 22935 #define DSC1B2_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 22936 22937 /* Dsc1b2 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 22938 #define DSC1B2_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 22939 #define DSC1B2_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 22940 #define DSC1B2_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 22941 #define DSC1B2_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 22942 22943 22944 /**************************************************************************** 22945 * Dsc1b2 :: cdr_ctrl1 22946 */ 22947 /* Dsc1b2 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 22948 #define DSC1B2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 22949 #define DSC1B2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 22950 #define DSC1B2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 22951 #define DSC1B2_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 22952 22953 22954 /**************************************************************************** 22955 * Dsc1b2 :: cdr_ctrl2 22956 */ 22957 /* Dsc1b2 :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */ 22958 #define DSC1B2_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xffc0 22959 #define DSC1B2_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 22960 #define DSC1B2_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 10 22961 #define DSC1B2_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 6 22962 22963 /* Dsc1b2 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 22964 #define DSC1B2_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 22965 #define DSC1B2_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 22966 #define DSC1B2_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 22967 #define DSC1B2_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 22968 22969 22970 /**************************************************************************** 22971 * Dsc1b2 :: pi_ctrl0 22972 */ 22973 /* Dsc1b2 :: pi_ctrl0 :: pi_cw_rst [15:15] */ 22974 #define DSC1B2_PI_CTRL0_PI_CW_RST_MASK 0x8000 22975 #define DSC1B2_PI_CTRL0_PI_CW_RST_ALIGN 0 22976 #define DSC1B2_PI_CTRL0_PI_CW_RST_BITS 1 22977 #define DSC1B2_PI_CTRL0_PI_CW_RST_SHIFT 15 22978 22979 /* Dsc1b2 :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */ 22980 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_MASK 0x7000 22981 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_ALIGN 0 22982 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_BITS 3 22983 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_SHIFT 12 22984 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb 0 22985 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb 1 22986 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb 2 22987 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb 3 22988 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb 4 22989 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb 5 22990 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb 6 22991 #define DSC1B2_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb 7 22992 22993 /* Dsc1b2 :: pi_ctrl0 :: reserved_for_eco0 [11:11] */ 22994 #define DSC1B2_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0x0800 22995 #define DSC1B2_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 22996 #define DSC1B2_PI_CTRL0_RESERVED_FOR_ECO0_BITS 1 22997 #define DSC1B2_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 22998 22999 /* Dsc1b2 :: pi_ctrl0 :: pi_phase_invert [10:10] */ 23000 #define DSC1B2_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 23001 #define DSC1B2_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 23002 #define DSC1B2_PI_CTRL0_PI_PHASE_INVERT_BITS 1 23003 #define DSC1B2_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 23004 23005 /* Dsc1b2 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 23006 #define DSC1B2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 23007 #define DSC1B2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 23008 #define DSC1B2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 23009 #define DSC1B2_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 23010 23011 /* Dsc1b2 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 23012 #define DSC1B2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 23013 #define DSC1B2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 23014 #define DSC1B2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 23015 #define DSC1B2_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 23016 23017 /* Dsc1b2 :: pi_ctrl0 :: pi_phase_dec [07:07] */ 23018 #define DSC1B2_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 23019 #define DSC1B2_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 23020 #define DSC1B2_PI_CTRL0_PI_PHASE_DEC_BITS 1 23021 #define DSC1B2_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 23022 23023 /* Dsc1b2 :: pi_ctrl0 :: pi_phase_inc [06:06] */ 23024 #define DSC1B2_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 23025 #define DSC1B2_PI_CTRL0_PI_PHASE_INC_ALIGN 0 23026 #define DSC1B2_PI_CTRL0_PI_PHASE_INC_BITS 1 23027 #define DSC1B2_PI_CTRL0_PI_PHASE_INC_SHIFT 6 23028 23029 /* Dsc1b2 :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 23030 #define DSC1B2_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 23031 #define DSC1B2_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 23032 #define DSC1B2_PI_CTRL0_PI_PHASE_STROBE_BITS 1 23033 #define DSC1B2_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 23034 23035 /* Dsc1b2 :: pi_ctrl0 :: pi_phase_delta [04:01] */ 23036 #define DSC1B2_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 23037 #define DSC1B2_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 23038 #define DSC1B2_PI_CTRL0_PI_PHASE_DELTA_BITS 4 23039 #define DSC1B2_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 23040 23041 /* Dsc1b2 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 23042 #define DSC1B2_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 23043 #define DSC1B2_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 23044 #define DSC1B2_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 23045 #define DSC1B2_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 23046 23047 23048 /**************************************************************************** 23049 * Dsc1b2 :: dfe_vga_ctrl0 23050 */ 23051 /* Dsc1b2 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */ 23052 #define DSC1B2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xff00 23053 #define DSC1B2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 23054 #define DSC1B2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 8 23055 #define DSC1B2_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 8 23056 23057 /* Dsc1b2 :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */ 23058 #define DSC1B2_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK 0x00c0 23059 #define DSC1B2_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN 0 23060 #define DSC1B2_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS 2 23061 #define DSC1B2_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT 6 23062 23063 /* Dsc1b2 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 23064 #define DSC1B2_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 23065 #define DSC1B2_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 23066 #define DSC1B2_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 23067 #define DSC1B2_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 23068 23069 /* Dsc1b2 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 23070 #define DSC1B2_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 23071 #define DSC1B2_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 23072 #define DSC1B2_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 23073 #define DSC1B2_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 23074 23075 /* Dsc1b2 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 23076 #define DSC1B2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 23077 #define DSC1B2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 23078 #define DSC1B2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 23079 #define DSC1B2_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 23080 23081 /* Dsc1b2 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 23082 #define DSC1B2_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 23083 #define DSC1B2_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 23084 #define DSC1B2_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 23085 #define DSC1B2_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 23086 23087 /* Dsc1b2 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 23088 #define DSC1B2_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 23089 #define DSC1B2_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 23090 #define DSC1B2_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 23091 #define DSC1B2_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 23092 23093 /* Dsc1b2 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 23094 #define DSC1B2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 23095 #define DSC1B2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 23096 #define DSC1B2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 23097 #define DSC1B2_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 23098 23099 23100 /**************************************************************************** 23101 * Dsc1b2 :: dfe_vga_ctrl1 23102 */ 23103 /* Dsc1b2 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */ 23104 #define DSC1B2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0xe000 23105 #define DSC1B2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 23106 #define DSC1B2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 3 23107 #define DSC1B2_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 13 23108 23109 /* Dsc1b2 :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */ 23110 #define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK 0x1f80 23111 #define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN 0 23112 #define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS 6 23113 #define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT 7 23114 23115 /* Dsc1b2 :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */ 23116 #define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK 0x0040 23117 #define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN 0 23118 #define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS 1 23119 #define DSC1B2_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT 6 23120 23121 /* Dsc1b2 :: dfe_vga_ctrl1 :: vga_write_val [05:01] */ 23122 #define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK 0x003e 23123 #define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN 0 23124 #define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS 5 23125 #define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT 1 23126 23127 /* Dsc1b2 :: dfe_vga_ctrl1 :: vga_write_en [00:00] */ 23128 #define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK 0x0001 23129 #define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN 0 23130 #define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS 1 23131 #define DSC1B2_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT 0 23132 23133 23134 /**************************************************************************** 23135 * Dsc1b2 :: dfe_vga_ctrl2 23136 */ 23137 /* Dsc1b2 :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */ 23138 #define DSC1B2_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 23139 #define DSC1B2_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 23140 #define DSC1B2_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS 2 23141 #define DSC1B2_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 23142 23143 /* Dsc1b2 :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */ 23144 #define DSC1B2_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK 0x3f80 23145 #define DSC1B2_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN 0 23146 #define DSC1B2_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS 7 23147 #define DSC1B2_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT 7 23148 23149 /* Dsc1b2 :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */ 23150 #define DSC1B2_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK 0x007f 23151 #define DSC1B2_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN 0 23152 #define DSC1B2_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS 7 23153 #define DSC1B2_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT 0 23154 23155 23156 /**************************************************************************** 23157 * Dsc1b2 :: dfe_vga_ctrl3 23158 */ 23159 /* Dsc1b2 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */ 23160 #define DSC1B2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xc000 23161 #define DSC1B2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 23162 #define DSC1B2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 2 23163 #define DSC1B2_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 14 23164 23165 /* Dsc1b2 :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */ 23166 #define DSC1B2_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK 0x3f80 23167 #define DSC1B2_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN 0 23168 #define DSC1B2_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS 7 23169 #define DSC1B2_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT 7 23170 23171 /* Dsc1b2 :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */ 23172 #define DSC1B2_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK 0x007f 23173 #define DSC1B2_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN 0 23174 #define DSC1B2_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS 7 23175 #define DSC1B2_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT 0 23176 23177 23178 /**************************************************************************** 23179 * Dsc1b2 :: dfe_vga_ctrl4 23180 */ 23181 /* Dsc1b2 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 23182 #define DSC1B2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 23183 #define DSC1B2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 23184 #define DSC1B2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 23185 #define DSC1B2_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 23186 23187 /* Dsc1b2 :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */ 23188 #define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK 0x03e0 23189 #define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN 0 23190 #define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS 5 23191 #define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT 5 23192 23193 /* Dsc1b2 :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */ 23194 #define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK 0x001f 23195 #define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN 0 23196 #define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS 5 23197 #define DSC1B2_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT 0 23198 23199 23200 /**************************************************************************** 23201 * Dsc1b2 :: dfe_vga_ctrl5 23202 */ 23203 /* Dsc1b2 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */ 23204 #define DSC1B2_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK 0xfc00 23205 #define DSC1B2_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 23206 #define DSC1B2_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS 6 23207 #define DSC1B2_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT 10 23208 23209 /* Dsc1b2 :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */ 23210 #define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK 0x03e0 23211 #define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN 0 23212 #define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS 5 23213 #define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT 5 23214 23215 /* Dsc1b2 :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */ 23216 #define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK 0x001f 23217 #define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN 0 23218 #define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS 5 23219 #define DSC1B2_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT 0 23220 23221 23222 /**************************************************************************** 23223 * Dsc1b2 :: dsc_ana_ctrl0 23224 */ 23225 /* Dsc1b2 :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */ 23226 #define DSC1B2_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK 0x8000 23227 #define DSC1B2_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN 0 23228 #define DSC1B2_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS 1 23229 #define DSC1B2_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT 15 23230 23231 /* Dsc1b2 :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */ 23232 #define DSC1B2_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x7c00 23233 #define DSC1B2_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 23234 #define DSC1B2_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 5 23235 #define DSC1B2_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 10 23236 23237 /* Dsc1b2 :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */ 23238 #define DSC1B2_DSC_ANA_CTRL0_D_ODD_CTRL_MASK 0x03e0 23239 #define DSC1B2_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN 0 23240 #define DSC1B2_DSC_ANA_CTRL0_D_ODD_CTRL_BITS 5 23241 #define DSC1B2_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT 5 23242 23243 /* Dsc1b2 :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */ 23244 #define DSC1B2_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK 0x001f 23245 #define DSC1B2_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN 0 23246 #define DSC1B2_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS 5 23247 #define DSC1B2_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT 0 23248 23249 23250 /**************************************************************************** 23251 * Dsc1b2 :: dsc_ana_ctrl1 23252 */ 23253 /* Dsc1b2 :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */ 23254 #define DSC1B2_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK 0x8000 23255 #define DSC1B2_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN 0 23256 #define DSC1B2_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS 1 23257 #define DSC1B2_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT 15 23258 23259 /* Dsc1b2 :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */ 23260 #define DSC1B2_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK 0x7c00 23261 #define DSC1B2_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN 0 23262 #define DSC1B2_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS 5 23263 #define DSC1B2_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT 10 23264 23265 /* Dsc1b2 :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */ 23266 #define DSC1B2_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x03e0 23267 #define DSC1B2_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 23268 #define DSC1B2_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 5 23269 #define DSC1B2_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 5 23270 23271 /* Dsc1b2 :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */ 23272 #define DSC1B2_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK 0x001f 23273 #define DSC1B2_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN 0 23274 #define DSC1B2_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS 5 23275 #define DSC1B2_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT 0 23276 23277 23278 /**************************************************************************** 23279 * Dsc1b2 :: dsc_ana_ctrl2 23280 */ 23281 /* Dsc1b2 :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */ 23282 #define DSC1B2_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK 0x8000 23283 #define DSC1B2_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN 0 23284 #define DSC1B2_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS 1 23285 #define DSC1B2_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT 15 23286 23287 /* Dsc1b2 :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */ 23288 #define DSC1B2_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK 0x4000 23289 #define DSC1B2_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN 0 23290 #define DSC1B2_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS 1 23291 #define DSC1B2_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT 14 23292 23293 /* Dsc1b2 :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */ 23294 #define DSC1B2_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK 0x2000 23295 #define DSC1B2_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN 0 23296 #define DSC1B2_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS 1 23297 #define DSC1B2_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT 13 23298 23299 /* Dsc1b2 :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */ 23300 #define DSC1B2_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK 0x1000 23301 #define DSC1B2_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN 0 23302 #define DSC1B2_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS 1 23303 #define DSC1B2_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT 12 23304 23305 /* Dsc1b2 :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */ 23306 #define DSC1B2_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK 0x0800 23307 #define DSC1B2_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN 0 23308 #define DSC1B2_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS 1 23309 #define DSC1B2_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT 11 23310 23311 /* Dsc1b2 :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */ 23312 #define DSC1B2_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK 0x0400 23313 #define DSC1B2_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN 0 23314 #define DSC1B2_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS 1 23315 #define DSC1B2_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT 10 23316 23317 /* Dsc1b2 :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */ 23318 #define DSC1B2_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK 0x0200 23319 #define DSC1B2_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN 0 23320 #define DSC1B2_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS 1 23321 #define DSC1B2_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT 9 23322 23323 /* Dsc1b2 :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */ 23324 #define DSC1B2_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK 0x0100 23325 #define DSC1B2_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN 0 23326 #define DSC1B2_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS 1 23327 #define DSC1B2_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT 8 23328 23329 /* Dsc1b2 :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */ 23330 #define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK 0x0080 23331 #define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 23332 #define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS 1 23333 #define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT 7 23334 23335 /* Dsc1b2 :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */ 23336 #define DSC1B2_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK 0x0040 23337 #define DSC1B2_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN 0 23338 #define DSC1B2_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS 1 23339 #define DSC1B2_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT 6 23340 23341 /* Dsc1b2 :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */ 23342 #define DSC1B2_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK 0x0030 23343 #define DSC1B2_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN 0 23344 #define DSC1B2_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS 2 23345 #define DSC1B2_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT 4 23346 23347 /* Dsc1b2 :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */ 23348 #define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK 0x0008 23349 #define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN 0 23350 #define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS 1 23351 #define DSC1B2_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT 3 23352 23353 /* Dsc1b2 :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */ 23354 #define DSC1B2_DSC_ANA_CTRL2_RX_PF_CTRL_MASK 0x0007 23355 #define DSC1B2_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN 0 23356 #define DSC1B2_DSC_ANA_CTRL2_RX_PF_CTRL_BITS 3 23357 #define DSC1B2_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT 0 23358 23359 23360 /**************************************************************************** 23361 * Dsc1b2 :: dsc_100fx_ctrl 23362 */ 23363 /* Dsc1b2 :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */ 23364 #define DSC1B2_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK 0xf800 23365 #define DSC1B2_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN 0 23366 #define DSC1B2_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS 5 23367 #define DSC1B2_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT 11 23368 23369 /* Dsc1b2 :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */ 23370 #define DSC1B2_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK 0x0600 23371 #define DSC1B2_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN 0 23372 #define DSC1B2_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS 2 23373 #define DSC1B2_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT 9 23374 23375 /* Dsc1b2 :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */ 23376 #define DSC1B2_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 23377 #define DSC1B2_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN 0 23378 #define DSC1B2_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS 1 23379 #define DSC1B2_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT 8 23380 23381 /* Dsc1b2 :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */ 23382 #define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 23383 #define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN 0 23384 #define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS 4 23385 #define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT 4 23386 23387 /* Dsc1b2 :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */ 23388 #define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK 0x000f 23389 #define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN 0 23390 #define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS 4 23391 #define DSC1B2_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT 0 23392 23393 23394 /**************************************************************************** 23395 * Dsc1b2 :: dsc_ana_ctrl3 23396 */ 23397 /* Dsc1b2 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */ 23398 #define DSC1B2_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK 0xffc0 23399 #define DSC1B2_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 23400 #define DSC1B2_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS 10 23401 #define DSC1B2_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT 6 23402 23403 /* Dsc1b2 :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */ 23404 #define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK 0x0020 23405 #define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN 0 23406 #define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS 1 23407 #define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT 5 23408 23409 /* Dsc1b2 :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */ 23410 #define DSC1B2_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK 0x0010 23411 #define DSC1B2_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN 0 23412 #define DSC1B2_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS 1 23413 #define DSC1B2_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT 4 23414 23415 /* Dsc1b2 :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */ 23416 #define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK 0x0008 23417 #define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN 0 23418 #define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS 1 23419 #define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT 3 23420 23421 /* Dsc1b2 :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */ 23422 #define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK 0x0004 23423 #define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN 0 23424 #define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS 1 23425 #define DSC1B2_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT 2 23426 23427 /* Dsc1b2 :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */ 23428 #define DSC1B2_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK 0x0002 23429 #define DSC1B2_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN 0 23430 #define DSC1B2_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS 1 23431 #define DSC1B2_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT 1 23432 23433 /* Dsc1b2 :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */ 23434 #define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK 0x0001 23435 #define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN 0 23436 #define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS 1 23437 #define DSC1B2_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT 0 23438 23439 23440 /**************************************************************************** 23441 * Hypercore_USER_Dsc1b3 23442 */ 23443 /**************************************************************************** 23444 * Dsc1b3 :: cdr_ctrl0 23445 */ 23446 /* Dsc1b3 :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */ 23447 #define DSC1B3_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xe000 23448 #define DSC1B3_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 23449 #define DSC1B3_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 3 23450 #define DSC1B3_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 13 23451 23452 /* Dsc1b3 :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 23453 #define DSC1B3_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 23454 #define DSC1B3_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 23455 #define DSC1B3_CDR_CTRL0_CDRBR_POLARITY_BITS 1 23456 #define DSC1B3_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 23457 23458 /* Dsc1b3 :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 23459 #define DSC1B3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 23460 #define DSC1B3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 23461 #define DSC1B3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 23462 #define DSC1B3_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 23463 23464 /* Dsc1b3 :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 23465 #define DSC1B3_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 23466 #define DSC1B3_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 23467 #define DSC1B3_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 23468 #define DSC1B3_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 23469 23470 /* Dsc1b3 :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 23471 #define DSC1B3_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 23472 #define DSC1B3_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 23473 #define DSC1B3_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 23474 #define DSC1B3_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 23475 23476 /* Dsc1b3 :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 23477 #define DSC1B3_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 23478 #define DSC1B3_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 23479 #define DSC1B3_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 23480 #define DSC1B3_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 23481 23482 /* Dsc1b3 :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 23483 #define DSC1B3_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 23484 #define DSC1B3_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 23485 #define DSC1B3_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 23486 #define DSC1B3_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 23487 23488 /* Dsc1b3 :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 23489 #define DSC1B3_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 23490 #define DSC1B3_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 23491 #define DSC1B3_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 23492 #define DSC1B3_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 23493 23494 /* Dsc1b3 :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 23495 #define DSC1B3_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 23496 #define DSC1B3_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 23497 #define DSC1B3_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 23498 #define DSC1B3_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 23499 23500 /* Dsc1b3 :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 23501 #define DSC1B3_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 23502 #define DSC1B3_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 23503 #define DSC1B3_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 23504 #define DSC1B3_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 23505 23506 /* Dsc1b3 :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 23507 #define DSC1B3_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 23508 #define DSC1B3_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 23509 #define DSC1B3_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 23510 #define DSC1B3_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 23511 23512 /* Dsc1b3 :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 23513 #define DSC1B3_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 23514 #define DSC1B3_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 23515 #define DSC1B3_CDR_CTRL0_CDR_FREQ_EN_BITS 1 23516 #define DSC1B3_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 23517 23518 /* Dsc1b3 :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 23519 #define DSC1B3_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 23520 #define DSC1B3_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 23521 #define DSC1B3_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 23522 #define DSC1B3_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 23523 23524 23525 /**************************************************************************** 23526 * Dsc1b3 :: cdr_ctrl1 23527 */ 23528 /* Dsc1b3 :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 23529 #define DSC1B3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 23530 #define DSC1B3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 23531 #define DSC1B3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 23532 #define DSC1B3_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 23533 23534 23535 /**************************************************************************** 23536 * Dsc1b3 :: cdr_ctrl2 23537 */ 23538 /* Dsc1b3 :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */ 23539 #define DSC1B3_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xffc0 23540 #define DSC1B3_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 23541 #define DSC1B3_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 10 23542 #define DSC1B3_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 6 23543 23544 /* Dsc1b3 :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 23545 #define DSC1B3_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 23546 #define DSC1B3_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 23547 #define DSC1B3_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 23548 #define DSC1B3_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 23549 23550 23551 /**************************************************************************** 23552 * Dsc1b3 :: pi_ctrl0 23553 */ 23554 /* Dsc1b3 :: pi_ctrl0 :: pi_cw_rst [15:15] */ 23555 #define DSC1B3_PI_CTRL0_PI_CW_RST_MASK 0x8000 23556 #define DSC1B3_PI_CTRL0_PI_CW_RST_ALIGN 0 23557 #define DSC1B3_PI_CTRL0_PI_CW_RST_BITS 1 23558 #define DSC1B3_PI_CTRL0_PI_CW_RST_SHIFT 15 23559 23560 /* Dsc1b3 :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */ 23561 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_MASK 0x7000 23562 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_ALIGN 0 23563 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_BITS 3 23564 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_SHIFT 12 23565 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb 0 23566 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb 1 23567 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb 2 23568 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb 3 23569 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb 4 23570 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb 5 23571 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb 6 23572 #define DSC1B3_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb 7 23573 23574 /* Dsc1b3 :: pi_ctrl0 :: reserved_for_eco0 [11:11] */ 23575 #define DSC1B3_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0x0800 23576 #define DSC1B3_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 23577 #define DSC1B3_PI_CTRL0_RESERVED_FOR_ECO0_BITS 1 23578 #define DSC1B3_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 23579 23580 /* Dsc1b3 :: pi_ctrl0 :: pi_phase_invert [10:10] */ 23581 #define DSC1B3_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 23582 #define DSC1B3_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 23583 #define DSC1B3_PI_CTRL0_PI_PHASE_INVERT_BITS 1 23584 #define DSC1B3_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 23585 23586 /* Dsc1b3 :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 23587 #define DSC1B3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 23588 #define DSC1B3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 23589 #define DSC1B3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 23590 #define DSC1B3_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 23591 23592 /* Dsc1b3 :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 23593 #define DSC1B3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 23594 #define DSC1B3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 23595 #define DSC1B3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 23596 #define DSC1B3_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 23597 23598 /* Dsc1b3 :: pi_ctrl0 :: pi_phase_dec [07:07] */ 23599 #define DSC1B3_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 23600 #define DSC1B3_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 23601 #define DSC1B3_PI_CTRL0_PI_PHASE_DEC_BITS 1 23602 #define DSC1B3_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 23603 23604 /* Dsc1b3 :: pi_ctrl0 :: pi_phase_inc [06:06] */ 23605 #define DSC1B3_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 23606 #define DSC1B3_PI_CTRL0_PI_PHASE_INC_ALIGN 0 23607 #define DSC1B3_PI_CTRL0_PI_PHASE_INC_BITS 1 23608 #define DSC1B3_PI_CTRL0_PI_PHASE_INC_SHIFT 6 23609 23610 /* Dsc1b3 :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 23611 #define DSC1B3_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 23612 #define DSC1B3_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 23613 #define DSC1B3_PI_CTRL0_PI_PHASE_STROBE_BITS 1 23614 #define DSC1B3_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 23615 23616 /* Dsc1b3 :: pi_ctrl0 :: pi_phase_delta [04:01] */ 23617 #define DSC1B3_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 23618 #define DSC1B3_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 23619 #define DSC1B3_PI_CTRL0_PI_PHASE_DELTA_BITS 4 23620 #define DSC1B3_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 23621 23622 /* Dsc1b3 :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 23623 #define DSC1B3_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 23624 #define DSC1B3_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 23625 #define DSC1B3_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 23626 #define DSC1B3_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 23627 23628 23629 /**************************************************************************** 23630 * Dsc1b3 :: dfe_vga_ctrl0 23631 */ 23632 /* Dsc1b3 :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */ 23633 #define DSC1B3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xff00 23634 #define DSC1B3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 23635 #define DSC1B3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 8 23636 #define DSC1B3_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 8 23637 23638 /* Dsc1b3 :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */ 23639 #define DSC1B3_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK 0x00c0 23640 #define DSC1B3_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN 0 23641 #define DSC1B3_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS 2 23642 #define DSC1B3_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT 6 23643 23644 /* Dsc1b3 :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 23645 #define DSC1B3_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 23646 #define DSC1B3_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 23647 #define DSC1B3_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 23648 #define DSC1B3_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 23649 23650 /* Dsc1b3 :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 23651 #define DSC1B3_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 23652 #define DSC1B3_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 23653 #define DSC1B3_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 23654 #define DSC1B3_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 23655 23656 /* Dsc1b3 :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 23657 #define DSC1B3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 23658 #define DSC1B3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 23659 #define DSC1B3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 23660 #define DSC1B3_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 23661 23662 /* Dsc1b3 :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 23663 #define DSC1B3_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 23664 #define DSC1B3_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 23665 #define DSC1B3_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 23666 #define DSC1B3_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 23667 23668 /* Dsc1b3 :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 23669 #define DSC1B3_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 23670 #define DSC1B3_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 23671 #define DSC1B3_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 23672 #define DSC1B3_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 23673 23674 /* Dsc1b3 :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 23675 #define DSC1B3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 23676 #define DSC1B3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 23677 #define DSC1B3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 23678 #define DSC1B3_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 23679 23680 23681 /**************************************************************************** 23682 * Dsc1b3 :: dfe_vga_ctrl1 23683 */ 23684 /* Dsc1b3 :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */ 23685 #define DSC1B3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0xe000 23686 #define DSC1B3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 23687 #define DSC1B3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 3 23688 #define DSC1B3_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 13 23689 23690 /* Dsc1b3 :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */ 23691 #define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK 0x1f80 23692 #define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN 0 23693 #define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS 6 23694 #define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT 7 23695 23696 /* Dsc1b3 :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */ 23697 #define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK 0x0040 23698 #define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN 0 23699 #define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS 1 23700 #define DSC1B3_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT 6 23701 23702 /* Dsc1b3 :: dfe_vga_ctrl1 :: vga_write_val [05:01] */ 23703 #define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK 0x003e 23704 #define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN 0 23705 #define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS 5 23706 #define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT 1 23707 23708 /* Dsc1b3 :: dfe_vga_ctrl1 :: vga_write_en [00:00] */ 23709 #define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK 0x0001 23710 #define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN 0 23711 #define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS 1 23712 #define DSC1B3_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT 0 23713 23714 23715 /**************************************************************************** 23716 * Dsc1b3 :: dfe_vga_ctrl2 23717 */ 23718 /* Dsc1b3 :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */ 23719 #define DSC1B3_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 23720 #define DSC1B3_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 23721 #define DSC1B3_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS 2 23722 #define DSC1B3_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 23723 23724 /* Dsc1b3 :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */ 23725 #define DSC1B3_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK 0x3f80 23726 #define DSC1B3_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN 0 23727 #define DSC1B3_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS 7 23728 #define DSC1B3_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT 7 23729 23730 /* Dsc1b3 :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */ 23731 #define DSC1B3_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK 0x007f 23732 #define DSC1B3_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN 0 23733 #define DSC1B3_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS 7 23734 #define DSC1B3_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT 0 23735 23736 23737 /**************************************************************************** 23738 * Dsc1b3 :: dfe_vga_ctrl3 23739 */ 23740 /* Dsc1b3 :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */ 23741 #define DSC1B3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xc000 23742 #define DSC1B3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 23743 #define DSC1B3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 2 23744 #define DSC1B3_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 14 23745 23746 /* Dsc1b3 :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */ 23747 #define DSC1B3_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK 0x3f80 23748 #define DSC1B3_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN 0 23749 #define DSC1B3_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS 7 23750 #define DSC1B3_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT 7 23751 23752 /* Dsc1b3 :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */ 23753 #define DSC1B3_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK 0x007f 23754 #define DSC1B3_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN 0 23755 #define DSC1B3_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS 7 23756 #define DSC1B3_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT 0 23757 23758 23759 /**************************************************************************** 23760 * Dsc1b3 :: dfe_vga_ctrl4 23761 */ 23762 /* Dsc1b3 :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 23763 #define DSC1B3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 23764 #define DSC1B3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 23765 #define DSC1B3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 23766 #define DSC1B3_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 23767 23768 /* Dsc1b3 :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */ 23769 #define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK 0x03e0 23770 #define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN 0 23771 #define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS 5 23772 #define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT 5 23773 23774 /* Dsc1b3 :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */ 23775 #define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK 0x001f 23776 #define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN 0 23777 #define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS 5 23778 #define DSC1B3_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT 0 23779 23780 23781 /**************************************************************************** 23782 * Dsc1b3 :: dfe_vga_ctrl5 23783 */ 23784 /* Dsc1b3 :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */ 23785 #define DSC1B3_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK 0xfc00 23786 #define DSC1B3_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 23787 #define DSC1B3_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS 6 23788 #define DSC1B3_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT 10 23789 23790 /* Dsc1b3 :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */ 23791 #define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK 0x03e0 23792 #define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN 0 23793 #define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS 5 23794 #define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT 5 23795 23796 /* Dsc1b3 :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */ 23797 #define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK 0x001f 23798 #define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN 0 23799 #define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS 5 23800 #define DSC1B3_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT 0 23801 23802 23803 /**************************************************************************** 23804 * Dsc1b3 :: dsc_ana_ctrl0 23805 */ 23806 /* Dsc1b3 :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */ 23807 #define DSC1B3_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK 0x8000 23808 #define DSC1B3_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN 0 23809 #define DSC1B3_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS 1 23810 #define DSC1B3_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT 15 23811 23812 /* Dsc1b3 :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */ 23813 #define DSC1B3_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x7c00 23814 #define DSC1B3_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 23815 #define DSC1B3_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 5 23816 #define DSC1B3_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 10 23817 23818 /* Dsc1b3 :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */ 23819 #define DSC1B3_DSC_ANA_CTRL0_D_ODD_CTRL_MASK 0x03e0 23820 #define DSC1B3_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN 0 23821 #define DSC1B3_DSC_ANA_CTRL0_D_ODD_CTRL_BITS 5 23822 #define DSC1B3_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT 5 23823 23824 /* Dsc1b3 :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */ 23825 #define DSC1B3_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK 0x001f 23826 #define DSC1B3_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN 0 23827 #define DSC1B3_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS 5 23828 #define DSC1B3_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT 0 23829 23830 23831 /**************************************************************************** 23832 * Dsc1b3 :: dsc_ana_ctrl1 23833 */ 23834 /* Dsc1b3 :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */ 23835 #define DSC1B3_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK 0x8000 23836 #define DSC1B3_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN 0 23837 #define DSC1B3_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS 1 23838 #define DSC1B3_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT 15 23839 23840 /* Dsc1b3 :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */ 23841 #define DSC1B3_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK 0x7c00 23842 #define DSC1B3_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN 0 23843 #define DSC1B3_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS 5 23844 #define DSC1B3_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT 10 23845 23846 /* Dsc1b3 :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */ 23847 #define DSC1B3_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x03e0 23848 #define DSC1B3_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 23849 #define DSC1B3_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 5 23850 #define DSC1B3_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 5 23851 23852 /* Dsc1b3 :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */ 23853 #define DSC1B3_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK 0x001f 23854 #define DSC1B3_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN 0 23855 #define DSC1B3_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS 5 23856 #define DSC1B3_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT 0 23857 23858 23859 /**************************************************************************** 23860 * Dsc1b3 :: dsc_ana_ctrl2 23861 */ 23862 /* Dsc1b3 :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */ 23863 #define DSC1B3_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK 0x8000 23864 #define DSC1B3_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN 0 23865 #define DSC1B3_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS 1 23866 #define DSC1B3_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT 15 23867 23868 /* Dsc1b3 :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */ 23869 #define DSC1B3_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK 0x4000 23870 #define DSC1B3_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN 0 23871 #define DSC1B3_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS 1 23872 #define DSC1B3_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT 14 23873 23874 /* Dsc1b3 :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */ 23875 #define DSC1B3_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK 0x2000 23876 #define DSC1B3_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN 0 23877 #define DSC1B3_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS 1 23878 #define DSC1B3_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT 13 23879 23880 /* Dsc1b3 :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */ 23881 #define DSC1B3_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK 0x1000 23882 #define DSC1B3_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN 0 23883 #define DSC1B3_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS 1 23884 #define DSC1B3_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT 12 23885 23886 /* Dsc1b3 :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */ 23887 #define DSC1B3_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK 0x0800 23888 #define DSC1B3_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN 0 23889 #define DSC1B3_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS 1 23890 #define DSC1B3_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT 11 23891 23892 /* Dsc1b3 :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */ 23893 #define DSC1B3_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK 0x0400 23894 #define DSC1B3_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN 0 23895 #define DSC1B3_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS 1 23896 #define DSC1B3_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT 10 23897 23898 /* Dsc1b3 :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */ 23899 #define DSC1B3_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK 0x0200 23900 #define DSC1B3_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN 0 23901 #define DSC1B3_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS 1 23902 #define DSC1B3_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT 9 23903 23904 /* Dsc1b3 :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */ 23905 #define DSC1B3_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK 0x0100 23906 #define DSC1B3_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN 0 23907 #define DSC1B3_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS 1 23908 #define DSC1B3_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT 8 23909 23910 /* Dsc1b3 :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */ 23911 #define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK 0x0080 23912 #define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 23913 #define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS 1 23914 #define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT 7 23915 23916 /* Dsc1b3 :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */ 23917 #define DSC1B3_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK 0x0040 23918 #define DSC1B3_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN 0 23919 #define DSC1B3_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS 1 23920 #define DSC1B3_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT 6 23921 23922 /* Dsc1b3 :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */ 23923 #define DSC1B3_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK 0x0030 23924 #define DSC1B3_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN 0 23925 #define DSC1B3_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS 2 23926 #define DSC1B3_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT 4 23927 23928 /* Dsc1b3 :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */ 23929 #define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK 0x0008 23930 #define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN 0 23931 #define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS 1 23932 #define DSC1B3_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT 3 23933 23934 /* Dsc1b3 :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */ 23935 #define DSC1B3_DSC_ANA_CTRL2_RX_PF_CTRL_MASK 0x0007 23936 #define DSC1B3_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN 0 23937 #define DSC1B3_DSC_ANA_CTRL2_RX_PF_CTRL_BITS 3 23938 #define DSC1B3_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT 0 23939 23940 23941 /**************************************************************************** 23942 * Dsc1b3 :: dsc_100fx_ctrl 23943 */ 23944 /* Dsc1b3 :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */ 23945 #define DSC1B3_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK 0xf800 23946 #define DSC1B3_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN 0 23947 #define DSC1B3_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS 5 23948 #define DSC1B3_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT 11 23949 23950 /* Dsc1b3 :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */ 23951 #define DSC1B3_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK 0x0600 23952 #define DSC1B3_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN 0 23953 #define DSC1B3_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS 2 23954 #define DSC1B3_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT 9 23955 23956 /* Dsc1b3 :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */ 23957 #define DSC1B3_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 23958 #define DSC1B3_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN 0 23959 #define DSC1B3_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS 1 23960 #define DSC1B3_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT 8 23961 23962 /* Dsc1b3 :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */ 23963 #define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 23964 #define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN 0 23965 #define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS 4 23966 #define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT 4 23967 23968 /* Dsc1b3 :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */ 23969 #define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK 0x000f 23970 #define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN 0 23971 #define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS 4 23972 #define DSC1B3_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT 0 23973 23974 23975 /**************************************************************************** 23976 * Dsc1b3 :: dsc_ana_ctrl3 23977 */ 23978 /* Dsc1b3 :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */ 23979 #define DSC1B3_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK 0xffc0 23980 #define DSC1B3_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 23981 #define DSC1B3_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS 10 23982 #define DSC1B3_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT 6 23983 23984 /* Dsc1b3 :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */ 23985 #define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK 0x0020 23986 #define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN 0 23987 #define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS 1 23988 #define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT 5 23989 23990 /* Dsc1b3 :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */ 23991 #define DSC1B3_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK 0x0010 23992 #define DSC1B3_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN 0 23993 #define DSC1B3_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS 1 23994 #define DSC1B3_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT 4 23995 23996 /* Dsc1b3 :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */ 23997 #define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK 0x0008 23998 #define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN 0 23999 #define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS 1 24000 #define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT 3 24001 24002 /* Dsc1b3 :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */ 24003 #define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK 0x0004 24004 #define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN 0 24005 #define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS 1 24006 #define DSC1B3_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT 2 24007 24008 /* Dsc1b3 :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */ 24009 #define DSC1B3_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK 0x0002 24010 #define DSC1B3_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN 0 24011 #define DSC1B3_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS 1 24012 #define DSC1B3_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT 1 24013 24014 /* Dsc1b3 :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */ 24015 #define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK 0x0001 24016 #define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN 0 24017 #define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS 1 24018 #define DSC1B3_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT 0 24019 24020 24021 /**************************************************************************** 24022 * Hypercore_USER_Dsc1bB 24023 */ 24024 /**************************************************************************** 24025 * Dsc1bB :: cdr_ctrl0 24026 */ 24027 /* Dsc1bB :: cdr_ctrl0 :: reserved_for_eco0 [15:13] */ 24028 #define DSC1BB_CDR_CTRL0_RESERVED_FOR_ECO0_MASK 0xe000 24029 #define DSC1BB_CDR_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 24030 #define DSC1BB_CDR_CTRL0_RESERVED_FOR_ECO0_BITS 3 24031 #define DSC1BB_CDR_CTRL0_RESERVED_FOR_ECO0_SHIFT 13 24032 24033 /* Dsc1bB :: cdr_ctrl0 :: cdrbr_polarity [12:12] */ 24034 #define DSC1BB_CDR_CTRL0_CDRBR_POLARITY_MASK 0x1000 24035 #define DSC1BB_CDR_CTRL0_CDRBR_POLARITY_ALIGN 0 24036 #define DSC1BB_CDR_CTRL0_CDRBR_POLARITY_BITS 1 24037 #define DSC1BB_CDR_CTRL0_CDRBR_POLARITY_SHIFT 12 24038 24039 /* Dsc1bB :: cdr_ctrl0 :: cdrbr_third_vec_en [11:11] */ 24040 #define DSC1BB_CDR_CTRL0_CDRBR_THIRD_VEC_EN_MASK 0x0800 24041 #define DSC1BB_CDR_CTRL0_CDRBR_THIRD_VEC_EN_ALIGN 0 24042 #define DSC1BB_CDR_CTRL0_CDRBR_THIRD_VEC_EN_BITS 1 24043 #define DSC1BB_CDR_CTRL0_CDRBR_THIRD_VEC_EN_SHIFT 11 24044 24045 /* Dsc1bB :: cdr_ctrl0 :: cdros_rising_edge [10:10] */ 24046 #define DSC1BB_CDR_CTRL0_CDROS_RISING_EDGE_MASK 0x0400 24047 #define DSC1BB_CDR_CTRL0_CDROS_RISING_EDGE_ALIGN 0 24048 #define DSC1BB_CDR_CTRL0_CDROS_RISING_EDGE_BITS 1 24049 #define DSC1BB_CDR_CTRL0_CDROS_RISING_EDGE_SHIFT 10 24050 24051 /* Dsc1bB :: cdr_ctrl0 :: cdros_falling_edge [09:09] */ 24052 #define DSC1BB_CDR_CTRL0_CDROS_FALLING_EDGE_MASK 0x0200 24053 #define DSC1BB_CDR_CTRL0_CDROS_FALLING_EDGE_ALIGN 0 24054 #define DSC1BB_CDR_CTRL0_CDROS_FALLING_EDGE_BITS 1 24055 #define DSC1BB_CDR_CTRL0_CDROS_FALLING_EDGE_SHIFT 9 24056 24057 /* Dsc1bB :: cdr_ctrl0 :: cdros_phase_sat_ctrl [08:07] */ 24058 #define DSC1BB_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_MASK 0x0180 24059 #define DSC1BB_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_ALIGN 0 24060 #define DSC1BB_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_BITS 2 24061 #define DSC1BB_CDR_CTRL0_CDROS_PHASE_SAT_CTRL_SHIFT 7 24062 24063 /* Dsc1bB :: cdr_ctrl0 :: cdros_peak_polarity [06:06] */ 24064 #define DSC1BB_CDR_CTRL0_CDROS_PEAK_POLARITY_MASK 0x0040 24065 #define DSC1BB_CDR_CTRL0_CDROS_PEAK_POLARITY_ALIGN 0 24066 #define DSC1BB_CDR_CTRL0_CDROS_PEAK_POLARITY_BITS 1 24067 #define DSC1BB_CDR_CTRL0_CDROS_PEAK_POLARITY_SHIFT 6 24068 24069 /* Dsc1bB :: cdr_ctrl0 :: cdros_zero_polarity [05:05] */ 24070 #define DSC1BB_CDR_CTRL0_CDROS_ZERO_POLARITY_MASK 0x0020 24071 #define DSC1BB_CDR_CTRL0_CDROS_ZERO_POLARITY_ALIGN 0 24072 #define DSC1BB_CDR_CTRL0_CDROS_ZERO_POLARITY_BITS 1 24073 #define DSC1BB_CDR_CTRL0_CDROS_ZERO_POLARITY_SHIFT 5 24074 24075 /* Dsc1bB :: cdr_ctrl0 :: cdr_phase_err_frz [04:04] */ 24076 #define DSC1BB_CDR_CTRL0_CDR_PHASE_ERR_FRZ_MASK 0x0010 24077 #define DSC1BB_CDR_CTRL0_CDR_PHASE_ERR_FRZ_ALIGN 0 24078 #define DSC1BB_CDR_CTRL0_CDR_PHASE_ERR_FRZ_BITS 1 24079 #define DSC1BB_CDR_CTRL0_CDR_PHASE_ERR_FRZ_SHIFT 4 24080 24081 /* Dsc1bB :: cdr_ctrl0 :: cdr_integ_reg_clr [03:03] */ 24082 #define DSC1BB_CDR_CTRL0_CDR_INTEG_REG_CLR_MASK 0x0008 24083 #define DSC1BB_CDR_CTRL0_CDR_INTEG_REG_CLR_ALIGN 0 24084 #define DSC1BB_CDR_CTRL0_CDR_INTEG_REG_CLR_BITS 1 24085 #define DSC1BB_CDR_CTRL0_CDR_INTEG_REG_CLR_SHIFT 3 24086 24087 /* Dsc1bB :: cdr_ctrl0 :: cdr_freq_upd_en [02:02] */ 24088 #define DSC1BB_CDR_CTRL0_CDR_FREQ_UPD_EN_MASK 0x0004 24089 #define DSC1BB_CDR_CTRL0_CDR_FREQ_UPD_EN_ALIGN 0 24090 #define DSC1BB_CDR_CTRL0_CDR_FREQ_UPD_EN_BITS 1 24091 #define DSC1BB_CDR_CTRL0_CDR_FREQ_UPD_EN_SHIFT 2 24092 24093 /* Dsc1bB :: cdr_ctrl0 :: cdr_freq_en [01:01] */ 24094 #define DSC1BB_CDR_CTRL0_CDR_FREQ_EN_MASK 0x0002 24095 #define DSC1BB_CDR_CTRL0_CDR_FREQ_EN_ALIGN 0 24096 #define DSC1BB_CDR_CTRL0_CDR_FREQ_EN_BITS 1 24097 #define DSC1BB_CDR_CTRL0_CDR_FREQ_EN_SHIFT 1 24098 24099 /* Dsc1bB :: cdr_ctrl0 :: cdr_freq_override_en [00:00] */ 24100 #define DSC1BB_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_MASK 0x0001 24101 #define DSC1BB_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_ALIGN 0 24102 #define DSC1BB_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_BITS 1 24103 #define DSC1BB_CDR_CTRL0_CDR_FREQ_OVERRIDE_EN_SHIFT 0 24104 24105 24106 /**************************************************************************** 24107 * Dsc1bB :: cdr_ctrl1 24108 */ 24109 /* Dsc1bB :: cdr_ctrl1 :: cdr_freq_override_val [15:00] */ 24110 #define DSC1BB_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_MASK 0xffff 24111 #define DSC1BB_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_ALIGN 0 24112 #define DSC1BB_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_BITS 16 24113 #define DSC1BB_CDR_CTRL1_CDR_FREQ_OVERRIDE_VAL_SHIFT 0 24114 24115 24116 /**************************************************************************** 24117 * Dsc1bB :: cdr_ctrl2 24118 */ 24119 /* Dsc1bB :: cdr_ctrl2 :: reserved_for_eco0 [15:06] */ 24120 #define DSC1BB_CDR_CTRL2_RESERVED_FOR_ECO0_MASK 0xffc0 24121 #define DSC1BB_CDR_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 24122 #define DSC1BB_CDR_CTRL2_RESERVED_FOR_ECO0_BITS 10 24123 #define DSC1BB_CDR_CTRL2_RESERVED_FOR_ECO0_SHIFT 6 24124 24125 /* Dsc1bB :: cdr_ctrl2 :: cdrbr_phase_err_offset [05:00] */ 24126 #define DSC1BB_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_MASK 0x003f 24127 #define DSC1BB_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_ALIGN 0 24128 #define DSC1BB_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_BITS 6 24129 #define DSC1BB_CDR_CTRL2_CDRBR_PHASE_ERR_OFFSET_SHIFT 0 24130 24131 24132 /**************************************************************************** 24133 * Dsc1bB :: pi_ctrl0 24134 */ 24135 /* Dsc1bB :: pi_ctrl0 :: pi_cw_rst [15:15] */ 24136 #define DSC1BB_PI_CTRL0_PI_CW_RST_MASK 0x8000 24137 #define DSC1BB_PI_CTRL0_PI_CW_RST_ALIGN 0 24138 #define DSC1BB_PI_CTRL0_PI_CW_RST_BITS 1 24139 #define DSC1BB_PI_CTRL0_PI_CW_RST_SHIFT 15 24140 24141 /* Dsc1bB :: pi_ctrl0 :: intrp_tmuxSelect [14:12] */ 24142 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_MASK 0x7000 24143 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_ALIGN 0 24144 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_BITS 3 24145 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_SHIFT 12 24146 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_lsb 0 24147 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSingle0_msb 1 24148 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_lsb 2 24149 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSequence0_msb 3 24150 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_lsb 4 24151 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSingle90_msb 5 24152 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_lsb 6 24153 #define DSC1BB_PI_CTRL0_INTRP_TMUXSELECT_piSequence90_msb 7 24154 24155 /* Dsc1bB :: pi_ctrl0 :: reserved_for_eco0 [11:11] */ 24156 #define DSC1BB_PI_CTRL0_RESERVED_FOR_ECO0_MASK 0x0800 24157 #define DSC1BB_PI_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 24158 #define DSC1BB_PI_CTRL0_RESERVED_FOR_ECO0_BITS 1 24159 #define DSC1BB_PI_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 24160 24161 /* Dsc1bB :: pi_ctrl0 :: pi_phase_invert [10:10] */ 24162 #define DSC1BB_PI_CTRL0_PI_PHASE_INVERT_MASK 0x0400 24163 #define DSC1BB_PI_CTRL0_PI_PHASE_INVERT_ALIGN 0 24164 #define DSC1BB_PI_CTRL0_PI_PHASE_INVERT_BITS 1 24165 #define DSC1BB_PI_CTRL0_PI_PHASE_INVERT_SHIFT 10 24166 24167 /* Dsc1bB :: pi_ctrl0 :: pi_dual_phase_override [09:09] */ 24168 #define DSC1BB_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_MASK 0x0200 24169 #define DSC1BB_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_ALIGN 0 24170 #define DSC1BB_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_BITS 1 24171 #define DSC1BB_PI_CTRL0_PI_DUAL_PHASE_OVERRIDE_SHIFT 9 24172 24173 /* Dsc1bB :: pi_ctrl0 :: pi_clk90_offset_override [08:08] */ 24174 #define DSC1BB_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_MASK 0x0100 24175 #define DSC1BB_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_ALIGN 0 24176 #define DSC1BB_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_BITS 1 24177 #define DSC1BB_PI_CTRL0_PI_CLK90_OFFSET_OVERRIDE_SHIFT 8 24178 24179 /* Dsc1bB :: pi_ctrl0 :: pi_phase_dec [07:07] */ 24180 #define DSC1BB_PI_CTRL0_PI_PHASE_DEC_MASK 0x0080 24181 #define DSC1BB_PI_CTRL0_PI_PHASE_DEC_ALIGN 0 24182 #define DSC1BB_PI_CTRL0_PI_PHASE_DEC_BITS 1 24183 #define DSC1BB_PI_CTRL0_PI_PHASE_DEC_SHIFT 7 24184 24185 /* Dsc1bB :: pi_ctrl0 :: pi_phase_inc [06:06] */ 24186 #define DSC1BB_PI_CTRL0_PI_PHASE_INC_MASK 0x0040 24187 #define DSC1BB_PI_CTRL0_PI_PHASE_INC_ALIGN 0 24188 #define DSC1BB_PI_CTRL0_PI_PHASE_INC_BITS 1 24189 #define DSC1BB_PI_CTRL0_PI_PHASE_INC_SHIFT 6 24190 24191 /* Dsc1bB :: pi_ctrl0 :: pi_phase_strobe [05:05] */ 24192 #define DSC1BB_PI_CTRL0_PI_PHASE_STROBE_MASK 0x0020 24193 #define DSC1BB_PI_CTRL0_PI_PHASE_STROBE_ALIGN 0 24194 #define DSC1BB_PI_CTRL0_PI_PHASE_STROBE_BITS 1 24195 #define DSC1BB_PI_CTRL0_PI_PHASE_STROBE_SHIFT 5 24196 24197 /* Dsc1bB :: pi_ctrl0 :: pi_phase_delta [04:01] */ 24198 #define DSC1BB_PI_CTRL0_PI_PHASE_DELTA_MASK 0x001e 24199 #define DSC1BB_PI_CTRL0_PI_PHASE_DELTA_ALIGN 0 24200 #define DSC1BB_PI_CTRL0_PI_PHASE_DELTA_BITS 4 24201 #define DSC1BB_PI_CTRL0_PI_PHASE_DELTA_SHIFT 1 24202 24203 /* Dsc1bB :: pi_ctrl0 :: pi_phase_step_mult [00:00] */ 24204 #define DSC1BB_PI_CTRL0_PI_PHASE_STEP_MULT_MASK 0x0001 24205 #define DSC1BB_PI_CTRL0_PI_PHASE_STEP_MULT_ALIGN 0 24206 #define DSC1BB_PI_CTRL0_PI_PHASE_STEP_MULT_BITS 1 24207 #define DSC1BB_PI_CTRL0_PI_PHASE_STEP_MULT_SHIFT 0 24208 24209 24210 /**************************************************************************** 24211 * Dsc1bB :: dfe_vga_ctrl0 24212 */ 24213 /* Dsc1bB :: dfe_vga_ctrl0 :: reserved_for_eco0 [15:08] */ 24214 #define DSC1BB_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_MASK 0xff00 24215 #define DSC1BB_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 24216 #define DSC1BB_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_BITS 8 24217 #define DSC1BB_DFE_VGA_CTRL0_RESERVED_FOR_ECO0_SHIFT 8 24218 24219 /* Dsc1bB :: dfe_vga_ctrl0 :: vga_timer_ctrl [07:06] */ 24220 #define DSC1BB_DFE_VGA_CTRL0_VGA_TIMER_CTRL_MASK 0x00c0 24221 #define DSC1BB_DFE_VGA_CTRL0_VGA_TIMER_CTRL_ALIGN 0 24222 #define DSC1BB_DFE_VGA_CTRL0_VGA_TIMER_CTRL_BITS 2 24223 #define DSC1BB_DFE_VGA_CTRL0_VGA_TIMER_CTRL_SHIFT 6 24224 24225 /* Dsc1bB :: dfe_vga_ctrl0 :: vga_polarity [05:05] */ 24226 #define DSC1BB_DFE_VGA_CTRL0_VGA_POLARITY_MASK 0x0020 24227 #define DSC1BB_DFE_VGA_CTRL0_VGA_POLARITY_ALIGN 0 24228 #define DSC1BB_DFE_VGA_CTRL0_VGA_POLARITY_BITS 1 24229 #define DSC1BB_DFE_VGA_CTRL0_VGA_POLARITY_SHIFT 5 24230 24231 /* Dsc1bB :: dfe_vga_ctrl0 :: dfe_polarity [04:04] */ 24232 #define DSC1BB_DFE_VGA_CTRL0_DFE_POLARITY_MASK 0x0010 24233 #define DSC1BB_DFE_VGA_CTRL0_DFE_POLARITY_ALIGN 0 24234 #define DSC1BB_DFE_VGA_CTRL0_DFE_POLARITY_BITS 1 24235 #define DSC1BB_DFE_VGA_CTRL0_DFE_POLARITY_SHIFT 4 24236 24237 /* Dsc1bB :: dfe_vga_ctrl0 :: trnsum_tap0_only [03:03] */ 24238 #define DSC1BB_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_MASK 0x0008 24239 #define DSC1BB_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_ALIGN 0 24240 #define DSC1BB_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_BITS 1 24241 #define DSC1BB_DFE_VGA_CTRL0_TRNSUM_TAP0_ONLY_SHIFT 3 24242 24243 /* Dsc1bB :: dfe_vga_ctrl0 :: sum_m1err [02:02] */ 24244 #define DSC1BB_DFE_VGA_CTRL0_SUM_M1ERR_MASK 0x0004 24245 #define DSC1BB_DFE_VGA_CTRL0_SUM_M1ERR_ALIGN 0 24246 #define DSC1BB_DFE_VGA_CTRL0_SUM_M1ERR_BITS 1 24247 #define DSC1BB_DFE_VGA_CTRL0_SUM_M1ERR_SHIFT 2 24248 24249 /* Dsc1bB :: dfe_vga_ctrl0 :: trnsum_en [01:01] */ 24250 #define DSC1BB_DFE_VGA_CTRL0_TRNSUM_EN_MASK 0x0002 24251 #define DSC1BB_DFE_VGA_CTRL0_TRNSUM_EN_ALIGN 0 24252 #define DSC1BB_DFE_VGA_CTRL0_TRNSUM_EN_BITS 1 24253 #define DSC1BB_DFE_VGA_CTRL0_TRNSUM_EN_SHIFT 1 24254 24255 /* Dsc1bB :: dfe_vga_ctrl0 :: dfe_vga_clken [00:00] */ 24256 #define DSC1BB_DFE_VGA_CTRL0_DFE_VGA_CLKEN_MASK 0x0001 24257 #define DSC1BB_DFE_VGA_CTRL0_DFE_VGA_CLKEN_ALIGN 0 24258 #define DSC1BB_DFE_VGA_CTRL0_DFE_VGA_CLKEN_BITS 1 24259 #define DSC1BB_DFE_VGA_CTRL0_DFE_VGA_CLKEN_SHIFT 0 24260 24261 24262 /**************************************************************************** 24263 * Dsc1bB :: dfe_vga_ctrl1 24264 */ 24265 /* Dsc1bB :: dfe_vga_ctrl1 :: reserved_for_eco0 [15:13] */ 24266 #define DSC1BB_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_MASK 0xe000 24267 #define DSC1BB_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_ALIGN 0 24268 #define DSC1BB_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_BITS 3 24269 #define DSC1BB_DFE_VGA_CTRL1_RESERVED_FOR_ECO0_SHIFT 13 24270 24271 /* Dsc1bB :: dfe_vga_ctrl1 :: dfe_write_val [12:07] */ 24272 #define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_VAL_MASK 0x1f80 24273 #define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_VAL_ALIGN 0 24274 #define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_VAL_BITS 6 24275 #define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_VAL_SHIFT 7 24276 24277 /* Dsc1bB :: dfe_vga_ctrl1 :: dfe_write_en [06:06] */ 24278 #define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_EN_MASK 0x0040 24279 #define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_EN_ALIGN 0 24280 #define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_EN_BITS 1 24281 #define DSC1BB_DFE_VGA_CTRL1_DFE_WRITE_EN_SHIFT 6 24282 24283 /* Dsc1bB :: dfe_vga_ctrl1 :: vga_write_val [05:01] */ 24284 #define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_VAL_MASK 0x003e 24285 #define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_VAL_ALIGN 0 24286 #define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_VAL_BITS 5 24287 #define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_VAL_SHIFT 1 24288 24289 /* Dsc1bB :: dfe_vga_ctrl1 :: vga_write_en [00:00] */ 24290 #define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_EN_MASK 0x0001 24291 #define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_EN_ALIGN 0 24292 #define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_EN_BITS 1 24293 #define DSC1BB_DFE_VGA_CTRL1_VGA_WRITE_EN_SHIFT 0 24294 24295 24296 /**************************************************************************** 24297 * Dsc1bB :: dfe_vga_ctrl2 24298 */ 24299 /* Dsc1bB :: dfe_vga_ctrl2 :: reserved_for_eco0 [15:14] */ 24300 #define DSC1BB_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_MASK 0xc000 24301 #define DSC1BB_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_ALIGN 0 24302 #define DSC1BB_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_BITS 2 24303 #define DSC1BB_DFE_VGA_CTRL2_RESERVED_FOR_ECO0_SHIFT 14 24304 24305 /* Dsc1bB :: dfe_vga_ctrl2 :: trnsum_otap_en [13:07] */ 24306 #define DSC1BB_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_MASK 0x3f80 24307 #define DSC1BB_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_ALIGN 0 24308 #define DSC1BB_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_BITS 7 24309 #define DSC1BB_DFE_VGA_CTRL2_TRNSUM_OTAP_EN_SHIFT 7 24310 24311 /* Dsc1bB :: dfe_vga_ctrl2 :: trnsum_etap_en [06:00] */ 24312 #define DSC1BB_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_MASK 0x007f 24313 #define DSC1BB_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_ALIGN 0 24314 #define DSC1BB_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_BITS 7 24315 #define DSC1BB_DFE_VGA_CTRL2_TRNSUM_ETAP_EN_SHIFT 0 24316 24317 24318 /**************************************************************************** 24319 * Dsc1bB :: dfe_vga_ctrl3 24320 */ 24321 /* Dsc1bB :: dfe_vga_ctrl3 :: reserved_for_eco0 [15:14] */ 24322 #define DSC1BB_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_MASK 0xc000 24323 #define DSC1BB_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 24324 #define DSC1BB_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_BITS 2 24325 #define DSC1BB_DFE_VGA_CTRL3_RESERVED_FOR_ECO0_SHIFT 14 24326 24327 /* Dsc1bB :: dfe_vga_ctrl3 :: trnsum_otap_sign [13:07] */ 24328 #define DSC1BB_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_MASK 0x3f80 24329 #define DSC1BB_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_ALIGN 0 24330 #define DSC1BB_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_BITS 7 24331 #define DSC1BB_DFE_VGA_CTRL3_TRNSUM_OTAP_SIGN_SHIFT 7 24332 24333 /* Dsc1bB :: dfe_vga_ctrl3 :: trnsum_etap_sign [06:00] */ 24334 #define DSC1BB_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_MASK 0x007f 24335 #define DSC1BB_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_ALIGN 0 24336 #define DSC1BB_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_BITS 7 24337 #define DSC1BB_DFE_VGA_CTRL3_TRNSUM_ETAP_SIGN_SHIFT 0 24338 24339 24340 /**************************************************************************** 24341 * Dsc1bB :: dfe_vga_ctrl4 24342 */ 24343 /* Dsc1bB :: dfe_vga_ctrl4 :: reserved_for_eco0 [15:10] */ 24344 #define DSC1BB_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_MASK 0xfc00 24345 #define DSC1BB_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_ALIGN 0 24346 #define DSC1BB_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_BITS 6 24347 #define DSC1BB_DFE_VGA_CTRL4_RESERVED_FOR_ECO0_SHIFT 10 24348 24349 /* Dsc1bB :: dfe_vga_ctrl4 :: vga_cor_sel_e [09:05] */ 24350 #define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_E_MASK 0x03e0 24351 #define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_E_ALIGN 0 24352 #define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_E_BITS 5 24353 #define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_E_SHIFT 5 24354 24355 /* Dsc1bB :: dfe_vga_ctrl4 :: vga_cor_sel_o [04:00] */ 24356 #define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_O_MASK 0x001f 24357 #define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_O_ALIGN 0 24358 #define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_O_BITS 5 24359 #define DSC1BB_DFE_VGA_CTRL4_VGA_COR_SEL_O_SHIFT 0 24360 24361 24362 /**************************************************************************** 24363 * Dsc1bB :: dfe_vga_ctrl5 24364 */ 24365 /* Dsc1bB :: dfe_vga_ctrl5 :: reserved_for_eco0 [15:10] */ 24366 #define DSC1BB_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_MASK 0xfc00 24367 #define DSC1BB_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_ALIGN 0 24368 #define DSC1BB_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_BITS 6 24369 #define DSC1BB_DFE_VGA_CTRL5_RESERVED_FOR_ECO0_SHIFT 10 24370 24371 /* Dsc1bB :: dfe_vga_ctrl5 :: dfe_cor_sel_e [09:05] */ 24372 #define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_E_MASK 0x03e0 24373 #define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_E_ALIGN 0 24374 #define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_E_BITS 5 24375 #define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_E_SHIFT 5 24376 24377 /* Dsc1bB :: dfe_vga_ctrl5 :: dfe_cor_sel_o [04:00] */ 24378 #define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_O_MASK 0x001f 24379 #define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_O_ALIGN 0 24380 #define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_O_BITS 5 24381 #define DSC1BB_DFE_VGA_CTRL5_DFE_COR_SEL_O_SHIFT 0 24382 24383 24384 /**************************************************************************** 24385 * Dsc1bB :: dsc_ana_ctrl0 24386 */ 24387 /* Dsc1bB :: dsc_ana_ctrl0 :: force_odd_ctrl [15:15] */ 24388 #define DSC1BB_DSC_ANA_CTRL0_FORCE_ODD_CTRL_MASK 0x8000 24389 #define DSC1BB_DSC_ANA_CTRL0_FORCE_ODD_CTRL_ALIGN 0 24390 #define DSC1BB_DSC_ANA_CTRL0_FORCE_ODD_CTRL_BITS 1 24391 #define DSC1BB_DSC_ANA_CTRL0_FORCE_ODD_CTRL_SHIFT 15 24392 24393 /* Dsc1bB :: dsc_ana_ctrl0 :: p1_odd_ctrl [14:10] */ 24394 #define DSC1BB_DSC_ANA_CTRL0_P1_ODD_CTRL_MASK 0x7c00 24395 #define DSC1BB_DSC_ANA_CTRL0_P1_ODD_CTRL_ALIGN 0 24396 #define DSC1BB_DSC_ANA_CTRL0_P1_ODD_CTRL_BITS 5 24397 #define DSC1BB_DSC_ANA_CTRL0_P1_ODD_CTRL_SHIFT 10 24398 24399 /* Dsc1bB :: dsc_ana_ctrl0 :: d_odd_ctrl [09:05] */ 24400 #define DSC1BB_DSC_ANA_CTRL0_D_ODD_CTRL_MASK 0x03e0 24401 #define DSC1BB_DSC_ANA_CTRL0_D_ODD_CTRL_ALIGN 0 24402 #define DSC1BB_DSC_ANA_CTRL0_D_ODD_CTRL_BITS 5 24403 #define DSC1BB_DSC_ANA_CTRL0_D_ODD_CTRL_SHIFT 5 24404 24405 /* Dsc1bB :: dsc_ana_ctrl0 :: m1_odd_ctrl [04:00] */ 24406 #define DSC1BB_DSC_ANA_CTRL0_M1_ODD_CTRL_MASK 0x001f 24407 #define DSC1BB_DSC_ANA_CTRL0_M1_ODD_CTRL_ALIGN 0 24408 #define DSC1BB_DSC_ANA_CTRL0_M1_ODD_CTRL_BITS 5 24409 #define DSC1BB_DSC_ANA_CTRL0_M1_ODD_CTRL_SHIFT 0 24410 24411 24412 /**************************************************************************** 24413 * Dsc1bB :: dsc_ana_ctrl1 24414 */ 24415 /* Dsc1bB :: dsc_ana_ctrl1 :: force_evn_ctrl [15:15] */ 24416 #define DSC1BB_DSC_ANA_CTRL1_FORCE_EVN_CTRL_MASK 0x8000 24417 #define DSC1BB_DSC_ANA_CTRL1_FORCE_EVN_CTRL_ALIGN 0 24418 #define DSC1BB_DSC_ANA_CTRL1_FORCE_EVN_CTRL_BITS 1 24419 #define DSC1BB_DSC_ANA_CTRL1_FORCE_EVN_CTRL_SHIFT 15 24420 24421 /* Dsc1bB :: dsc_ana_ctrl1 :: p1_evn_ctrl [14:10] */ 24422 #define DSC1BB_DSC_ANA_CTRL1_P1_EVN_CTRL_MASK 0x7c00 24423 #define DSC1BB_DSC_ANA_CTRL1_P1_EVN_CTRL_ALIGN 0 24424 #define DSC1BB_DSC_ANA_CTRL1_P1_EVN_CTRL_BITS 5 24425 #define DSC1BB_DSC_ANA_CTRL1_P1_EVN_CTRL_SHIFT 10 24426 24427 /* Dsc1bB :: dsc_ana_ctrl1 :: d_evn_ctrl [09:05] */ 24428 #define DSC1BB_DSC_ANA_CTRL1_D_EVN_CTRL_MASK 0x03e0 24429 #define DSC1BB_DSC_ANA_CTRL1_D_EVN_CTRL_ALIGN 0 24430 #define DSC1BB_DSC_ANA_CTRL1_D_EVN_CTRL_BITS 5 24431 #define DSC1BB_DSC_ANA_CTRL1_D_EVN_CTRL_SHIFT 5 24432 24433 /* Dsc1bB :: dsc_ana_ctrl1 :: m1_evn_ctrl [04:00] */ 24434 #define DSC1BB_DSC_ANA_CTRL1_M1_EVN_CTRL_MASK 0x001f 24435 #define DSC1BB_DSC_ANA_CTRL1_M1_EVN_CTRL_ALIGN 0 24436 #define DSC1BB_DSC_ANA_CTRL1_M1_EVN_CTRL_BITS 5 24437 #define DSC1BB_DSC_ANA_CTRL1_M1_EVN_CTRL_SHIFT 0 24438 24439 24440 /**************************************************************************** 24441 * Dsc1bB :: dsc_ana_ctrl2 24442 */ 24443 /* Dsc1bB :: dsc_ana_ctrl2 :: br_offset_pd [15:15] */ 24444 #define DSC1BB_DSC_ANA_CTRL2_BR_OFFSET_PD_MASK 0x8000 24445 #define DSC1BB_DSC_ANA_CTRL2_BR_OFFSET_PD_ALIGN 0 24446 #define DSC1BB_DSC_ANA_CTRL2_BR_OFFSET_PD_BITS 1 24447 #define DSC1BB_DSC_ANA_CTRL2_BR_OFFSET_PD_SHIFT 15 24448 24449 /* Dsc1bB :: dsc_ana_ctrl2 :: br_en_hgain [14:14] */ 24450 #define DSC1BB_DSC_ANA_CTRL2_BR_EN_HGAIN_MASK 0x4000 24451 #define DSC1BB_DSC_ANA_CTRL2_BR_EN_HGAIN_ALIGN 0 24452 #define DSC1BB_DSC_ANA_CTRL2_BR_EN_HGAIN_BITS 1 24453 #define DSC1BB_DSC_ANA_CTRL2_BR_EN_HGAIN_SHIFT 14 24454 24455 /* Dsc1bB :: dsc_ana_ctrl2 :: br_en_dfe_clk [13:13] */ 24456 #define DSC1BB_DSC_ANA_CTRL2_BR_EN_DFE_CLK_MASK 0x2000 24457 #define DSC1BB_DSC_ANA_CTRL2_BR_EN_DFE_CLK_ALIGN 0 24458 #define DSC1BB_DSC_ANA_CTRL2_BR_EN_DFE_CLK_BITS 1 24459 #define DSC1BB_DSC_ANA_CTRL2_BR_EN_DFE_CLK_SHIFT 13 24460 24461 /* Dsc1bB :: dsc_ana_ctrl2 :: br_pd_ch_p1 [12:12] */ 24462 #define DSC1BB_DSC_ANA_CTRL2_BR_PD_CH_P1_MASK 0x1000 24463 #define DSC1BB_DSC_ANA_CTRL2_BR_PD_CH_P1_ALIGN 0 24464 #define DSC1BB_DSC_ANA_CTRL2_BR_PD_CH_P1_BITS 1 24465 #define DSC1BB_DSC_ANA_CTRL2_BR_PD_CH_P1_SHIFT 12 24466 24467 /* Dsc1bB :: dsc_ana_ctrl2 :: osr_offset_pd [11:11] */ 24468 #define DSC1BB_DSC_ANA_CTRL2_OSR_OFFSET_PD_MASK 0x0800 24469 #define DSC1BB_DSC_ANA_CTRL2_OSR_OFFSET_PD_ALIGN 0 24470 #define DSC1BB_DSC_ANA_CTRL2_OSR_OFFSET_PD_BITS 1 24471 #define DSC1BB_DSC_ANA_CTRL2_OSR_OFFSET_PD_SHIFT 11 24472 24473 /* Dsc1bB :: dsc_ana_ctrl2 :: osr_en_hgain [10:10] */ 24474 #define DSC1BB_DSC_ANA_CTRL2_OSR_EN_HGAIN_MASK 0x0400 24475 #define DSC1BB_DSC_ANA_CTRL2_OSR_EN_HGAIN_ALIGN 0 24476 #define DSC1BB_DSC_ANA_CTRL2_OSR_EN_HGAIN_BITS 1 24477 #define DSC1BB_DSC_ANA_CTRL2_OSR_EN_HGAIN_SHIFT 10 24478 24479 /* Dsc1bB :: dsc_ana_ctrl2 :: osr_en_dfe_clk [09:09] */ 24480 #define DSC1BB_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_MASK 0x0200 24481 #define DSC1BB_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_ALIGN 0 24482 #define DSC1BB_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_BITS 1 24483 #define DSC1BB_DSC_ANA_CTRL2_OSR_EN_DFE_CLK_SHIFT 9 24484 24485 /* Dsc1bB :: dsc_ana_ctrl2 :: osr_pd_ch_p1 [08:08] */ 24486 #define DSC1BB_DSC_ANA_CTRL2_OSR_PD_CH_P1_MASK 0x0100 24487 #define DSC1BB_DSC_ANA_CTRL2_OSR_PD_CH_P1_ALIGN 0 24488 #define DSC1BB_DSC_ANA_CTRL2_OSR_PD_CH_P1_BITS 1 24489 #define DSC1BB_DSC_ANA_CTRL2_OSR_PD_CH_P1_SHIFT 8 24490 24491 /* Dsc1bB :: dsc_ana_ctrl2 :: force_rx_m1_thresh_zero [07:07] */ 24492 #define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_MASK 0x0080 24493 #define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_ALIGN 0 24494 #define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_BITS 1 24495 #define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_M1_THRESH_ZERO_SHIFT 7 24496 24497 /* Dsc1bB :: dsc_ana_ctrl2 :: rx_m1_thresh_zero [06:06] */ 24498 #define DSC1BB_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_MASK 0x0040 24499 #define DSC1BB_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_ALIGN 0 24500 #define DSC1BB_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_BITS 1 24501 #define DSC1BB_DSC_ANA_CTRL2_RX_M1_THRESH_ZERO_SHIFT 6 24502 24503 /* Dsc1bB :: dsc_ana_ctrl2 :: rx_thresh_sel [05:04] */ 24504 #define DSC1BB_DSC_ANA_CTRL2_RX_THRESH_SEL_MASK 0x0030 24505 #define DSC1BB_DSC_ANA_CTRL2_RX_THRESH_SEL_ALIGN 0 24506 #define DSC1BB_DSC_ANA_CTRL2_RX_THRESH_SEL_BITS 2 24507 #define DSC1BB_DSC_ANA_CTRL2_RX_THRESH_SEL_SHIFT 4 24508 24509 /* Dsc1bB :: dsc_ana_ctrl2 :: force_rx_pf_ctrl [03:03] */ 24510 #define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_MASK 0x0008 24511 #define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_ALIGN 0 24512 #define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_BITS 1 24513 #define DSC1BB_DSC_ANA_CTRL2_FORCE_RX_PF_CTRL_SHIFT 3 24514 24515 /* Dsc1bB :: dsc_ana_ctrl2 :: rx_pf_ctrl [02:00] */ 24516 #define DSC1BB_DSC_ANA_CTRL2_RX_PF_CTRL_MASK 0x0007 24517 #define DSC1BB_DSC_ANA_CTRL2_RX_PF_CTRL_ALIGN 0 24518 #define DSC1BB_DSC_ANA_CTRL2_RX_PF_CTRL_BITS 3 24519 #define DSC1BB_DSC_ANA_CTRL2_RX_PF_CTRL_SHIFT 0 24520 24521 24522 /**************************************************************************** 24523 * Dsc1bB :: dsc_100fx_ctrl 24524 */ 24525 /* Dsc1bB :: dsc_100fx_ctrl :: reserved_for_eco0 [15:11] */ 24526 #define DSC1BB_DSC_100FX_CTRL_RESERVED_FOR_ECO0_MASK 0xf800 24527 #define DSC1BB_DSC_100FX_CTRL_RESERVED_FOR_ECO0_ALIGN 0 24528 #define DSC1BB_DSC_100FX_CTRL_RESERVED_FOR_ECO0_BITS 5 24529 #define DSC1BB_DSC_100FX_CTRL_RESERVED_FOR_ECO0_SHIFT 11 24530 24531 /* Dsc1bB :: dsc_100fx_ctrl :: phase_sat_ctrl_100fx [10:09] */ 24532 #define DSC1BB_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_MASK 0x0600 24533 #define DSC1BB_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_ALIGN 0 24534 #define DSC1BB_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_BITS 2 24535 #define DSC1BB_DSC_100FX_CTRL_PHASE_SAT_CTRL_100FX_SHIFT 9 24536 24537 /* Dsc1bB :: dsc_100fx_ctrl :: pi_phase_step_mult_100fx [08:08] */ 24538 #define DSC1BB_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_MASK 0x0100 24539 #define DSC1BB_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_ALIGN 0 24540 #define DSC1BB_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_BITS 1 24541 #define DSC1BB_DSC_100FX_CTRL_PI_PHASE_STEP_MULT_100FX_SHIFT 8 24542 24543 /* Dsc1bB :: dsc_100fx_ctrl :: cdros_bwsel_integ_100fx [07:04] */ 24544 #define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_MASK 0x00f0 24545 #define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_ALIGN 0 24546 #define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_BITS 4 24547 #define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_INTEG_100FX_SHIFT 4 24548 24549 /* Dsc1bB :: dsc_100fx_ctrl :: cdros_bwsel_prop_100fx [03:00] */ 24550 #define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_MASK 0x000f 24551 #define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_ALIGN 0 24552 #define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_BITS 4 24553 #define DSC1BB_DSC_100FX_CTRL_CDROS_BWSEL_PROP_100FX_SHIFT 0 24554 24555 24556 /**************************************************************************** 24557 * Dsc1bB :: dsc_ana_ctrl3 24558 */ 24559 /* Dsc1bB :: dsc_ana_ctrl3 :: reserved_for_eco0 [15:06] */ 24560 #define DSC1BB_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_MASK 0xffc0 24561 #define DSC1BB_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 24562 #define DSC1BB_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_BITS 10 24563 #define DSC1BB_DSC_ANA_CTRL3_RESERVED_FOR_ECO0_SHIFT 6 24564 24565 /* Dsc1bB :: dsc_ana_ctrl3 :: force_p1_evn_ctrl [05:05] */ 24566 #define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_MASK 0x0020 24567 #define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_ALIGN 0 24568 #define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_BITS 1 24569 #define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_EVN_CTRL_SHIFT 5 24570 24571 /* Dsc1bB :: dsc_ana_ctrl3 :: force_d_evn_ctrl [04:04] */ 24572 #define DSC1BB_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_MASK 0x0010 24573 #define DSC1BB_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_ALIGN 0 24574 #define DSC1BB_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_BITS 1 24575 #define DSC1BB_DSC_ANA_CTRL3_FORCE_D_EVN_CTRL_SHIFT 4 24576 24577 /* Dsc1bB :: dsc_ana_ctrl3 :: force_m1_evn_ctrl [03:03] */ 24578 #define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_MASK 0x0008 24579 #define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_ALIGN 0 24580 #define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_BITS 1 24581 #define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_EVN_CTRL_SHIFT 3 24582 24583 /* Dsc1bB :: dsc_ana_ctrl3 :: force_p1_odd_ctrl [02:02] */ 24584 #define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_MASK 0x0004 24585 #define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_ALIGN 0 24586 #define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_BITS 1 24587 #define DSC1BB_DSC_ANA_CTRL3_FORCE_P1_ODD_CTRL_SHIFT 2 24588 24589 /* Dsc1bB :: dsc_ana_ctrl3 :: force_d_odd_ctrl [01:01] */ 24590 #define DSC1BB_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_MASK 0x0002 24591 #define DSC1BB_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_ALIGN 0 24592 #define DSC1BB_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_BITS 1 24593 #define DSC1BB_DSC_ANA_CTRL3_FORCE_D_ODD_CTRL_SHIFT 1 24594 24595 /* Dsc1bB :: dsc_ana_ctrl3 :: force_m1_odd_ctrl [00:00] */ 24596 #define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_MASK 0x0001 24597 #define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_ALIGN 0 24598 #define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_BITS 1 24599 #define DSC1BB_DSC_ANA_CTRL3_FORCE_M1_ODD_CTRL_SHIFT 0 24600 24601 24602 /**************************************************************************** 24603 * Hypercore_USER_Dsc2b0 24604 */ 24605 /**************************************************************************** 24606 * Dsc2b0 :: sm_ctrl0 24607 */ 24608 /* Dsc2b0 :: sm_ctrl0 :: reserved_for_eco0 [15:15] */ 24609 #define DSC2B0_SM_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 24610 #define DSC2B0_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 24611 #define DSC2B0_SM_CTRL0_RESERVED_FOR_ECO0_BITS 1 24612 #define DSC2B0_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 24613 24614 /* Dsc2b0 :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */ 24615 #define DSC2B0_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK 0x4000 24616 #define DSC2B0_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN 0 24617 #define DSC2B0_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS 1 24618 #define DSC2B0_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT 14 24619 24620 /* Dsc2b0 :: sm_ctrl0 :: bypass_br_vga [13:13] */ 24621 #define DSC2B0_SM_CTRL0_BYPASS_BR_VGA_MASK 0x2000 24622 #define DSC2B0_SM_CTRL0_BYPASS_BR_VGA_ALIGN 0 24623 #define DSC2B0_SM_CTRL0_BYPASS_BR_VGA_BITS 1 24624 #define DSC2B0_SM_CTRL0_BYPASS_BR_VGA_SHIFT 13 24625 24626 /* Dsc2b0 :: sm_ctrl0 :: postc_metric_ctrl [12:12] */ 24627 #define DSC2B0_SM_CTRL0_POSTC_METRIC_CTRL_MASK 0x1000 24628 #define DSC2B0_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN 0 24629 #define DSC2B0_SM_CTRL0_POSTC_METRIC_CTRL_BITS 1 24630 #define DSC2B0_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT 12 24631 24632 /* Dsc2b0 :: sm_ctrl0 :: hysteresis_en [11:11] */ 24633 #define DSC2B0_SM_CTRL0_HYSTERESIS_EN_MASK 0x0800 24634 #define DSC2B0_SM_CTRL0_HYSTERESIS_EN_ALIGN 0 24635 #define DSC2B0_SM_CTRL0_HYSTERESIS_EN_BITS 1 24636 #define DSC2B0_SM_CTRL0_HYSTERESIS_EN_SHIFT 11 24637 24638 /* Dsc2b0 :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */ 24639 #define DSC2B0_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK 0x0400 24640 #define DSC2B0_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN 0 24641 #define DSC2B0_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS 1 24642 #define DSC2B0_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT 10 24643 24644 /* Dsc2b0 :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */ 24645 #define DSC2B0_SM_CTRL0_BYPASS_BR_PF_CAL_MASK 0x0200 24646 #define DSC2B0_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN 0 24647 #define DSC2B0_SM_CTRL0_BYPASS_BR_PF_CAL_BITS 1 24648 #define DSC2B0_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT 9 24649 24650 /* Dsc2b0 :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */ 24651 #define DSC2B0_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK 0x0100 24652 #define DSC2B0_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN 0 24653 #define DSC2B0_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS 1 24654 #define DSC2B0_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT 8 24655 24656 /* Dsc2b0 :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */ 24657 #define DSC2B0_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK 0x0080 24658 #define DSC2B0_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN 0 24659 #define DSC2B0_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS 1 24660 #define DSC2B0_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT 7 24661 24662 /* Dsc2b0 :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */ 24663 #define DSC2B0_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK 0x0040 24664 #define DSC2B0_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN 0 24665 #define DSC2B0_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS 1 24666 #define DSC2B0_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT 6 24667 24668 /* Dsc2b0 :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */ 24669 #define DSC2B0_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK 0x0020 24670 #define DSC2B0_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN 0 24671 #define DSC2B0_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS 1 24672 #define DSC2B0_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT 5 24673 24674 /* Dsc2b0 :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */ 24675 #define DSC2B0_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK 0x0010 24676 #define DSC2B0_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN 0 24677 #define DSC2B0_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS 1 24678 #define DSC2B0_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT 4 24679 24680 /* Dsc2b0 :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */ 24681 #define DSC2B0_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK 0x0008 24682 #define DSC2B0_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN 0 24683 #define DSC2B0_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS 1 24684 #define DSC2B0_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT 3 24685 24686 /* Dsc2b0 :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */ 24687 #define DSC2B0_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK 0x0004 24688 #define DSC2B0_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN 0 24689 #define DSC2B0_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS 1 24690 #define DSC2B0_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT 2 24691 24692 /* Dsc2b0 :: sm_ctrl0 :: restart_tuning [01:01] */ 24693 #define DSC2B0_SM_CTRL0_RESTART_TUNING_MASK 0x0002 24694 #define DSC2B0_SM_CTRL0_RESTART_TUNING_ALIGN 0 24695 #define DSC2B0_SM_CTRL0_RESTART_TUNING_BITS 1 24696 #define DSC2B0_SM_CTRL0_RESTART_TUNING_SHIFT 1 24697 24698 /* Dsc2b0 :: sm_ctrl0 :: tuning_sm_en [00:00] */ 24699 #define DSC2B0_SM_CTRL0_TUNING_SM_EN_MASK 0x0001 24700 #define DSC2B0_SM_CTRL0_TUNING_SM_EN_ALIGN 0 24701 #define DSC2B0_SM_CTRL0_TUNING_SM_EN_BITS 1 24702 #define DSC2B0_SM_CTRL0_TUNING_SM_EN_SHIFT 0 24703 24704 24705 /**************************************************************************** 24706 * Dsc2b0 :: sm_ctrl1 24707 */ 24708 /* Dsc2b0 :: sm_ctrl1 :: fast_timer [15:15] */ 24709 #define DSC2B0_SM_CTRL1_FAST_TIMER_MASK 0x8000 24710 #define DSC2B0_SM_CTRL1_FAST_TIMER_ALIGN 0 24711 #define DSC2B0_SM_CTRL1_FAST_TIMER_BITS 1 24712 #define DSC2B0_SM_CTRL1_FAST_TIMER_SHIFT 15 24713 24714 /* Dsc2b0 :: sm_ctrl1 :: acq2_timeout [14:10] */ 24715 #define DSC2B0_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 24716 #define DSC2B0_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 24717 #define DSC2B0_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 24718 #define DSC2B0_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 24719 24720 /* Dsc2b0 :: sm_ctrl1 :: acq1_timeout [09:05] */ 24721 #define DSC2B0_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 24722 #define DSC2B0_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 24723 #define DSC2B0_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 24724 #define DSC2B0_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 24725 24726 /* Dsc2b0 :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 24727 #define DSC2B0_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 24728 #define DSC2B0_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 24729 #define DSC2B0_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 24730 #define DSC2B0_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 24731 24732 24733 /**************************************************************************** 24734 * Dsc2b0 :: sm_ctrl2 24735 */ 24736 /* Dsc2b0 :: sm_ctrl2 :: acqvga_timeout [15:11] */ 24737 #define DSC2B0_SM_CTRL2_ACQVGA_TIMEOUT_MASK 0xf800 24738 #define DSC2B0_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN 0 24739 #define DSC2B0_SM_CTRL2_ACQVGA_TIMEOUT_BITS 5 24740 #define DSC2B0_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT 11 24741 24742 /* Dsc2b0 :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */ 24743 #define DSC2B0_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK 0x0400 24744 #define DSC2B0_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN 0 24745 #define DSC2B0_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS 1 24746 #define DSC2B0_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT 10 24747 24748 /* Dsc2b0 :: sm_ctrl2 :: vga_frzval [09:09] */ 24749 #define DSC2B0_SM_CTRL2_VGA_FRZVAL_MASK 0x0200 24750 #define DSC2B0_SM_CTRL2_VGA_FRZVAL_ALIGN 0 24751 #define DSC2B0_SM_CTRL2_VGA_FRZVAL_BITS 1 24752 #define DSC2B0_SM_CTRL2_VGA_FRZVAL_SHIFT 9 24753 24754 /* Dsc2b0 :: sm_ctrl2 :: vga_frcfrz [08:08] */ 24755 #define DSC2B0_SM_CTRL2_VGA_FRCFRZ_MASK 0x0100 24756 #define DSC2B0_SM_CTRL2_VGA_FRCFRZ_ALIGN 0 24757 #define DSC2B0_SM_CTRL2_VGA_FRCFRZ_BITS 1 24758 #define DSC2B0_SM_CTRL2_VGA_FRCFRZ_SHIFT 8 24759 24760 /* Dsc2b0 :: sm_ctrl2 :: dfe_frzval [07:07] */ 24761 #define DSC2B0_SM_CTRL2_DFE_FRZVAL_MASK 0x0080 24762 #define DSC2B0_SM_CTRL2_DFE_FRZVAL_ALIGN 0 24763 #define DSC2B0_SM_CTRL2_DFE_FRZVAL_BITS 1 24764 #define DSC2B0_SM_CTRL2_DFE_FRZVAL_SHIFT 7 24765 24766 /* Dsc2b0 :: sm_ctrl2 :: dfe_frcfrz [06:06] */ 24767 #define DSC2B0_SM_CTRL2_DFE_FRCFRZ_MASK 0x0040 24768 #define DSC2B0_SM_CTRL2_DFE_FRCFRZ_ALIGN 0 24769 #define DSC2B0_SM_CTRL2_DFE_FRCFRZ_BITS 1 24770 #define DSC2B0_SM_CTRL2_DFE_FRCFRZ_SHIFT 6 24771 24772 /* Dsc2b0 :: sm_ctrl2 :: dsc_clr_val [05:05] */ 24773 #define DSC2B0_SM_CTRL2_DSC_CLR_VAL_MASK 0x0020 24774 #define DSC2B0_SM_CTRL2_DSC_CLR_VAL_ALIGN 0 24775 #define DSC2B0_SM_CTRL2_DSC_CLR_VAL_BITS 1 24776 #define DSC2B0_SM_CTRL2_DSC_CLR_VAL_SHIFT 5 24777 24778 /* Dsc2b0 :: sm_ctrl2 :: dsc_clr_frc [04:04] */ 24779 #define DSC2B0_SM_CTRL2_DSC_CLR_FRC_MASK 0x0010 24780 #define DSC2B0_SM_CTRL2_DSC_CLR_FRC_ALIGN 0 24781 #define DSC2B0_SM_CTRL2_DSC_CLR_FRC_BITS 1 24782 #define DSC2B0_SM_CTRL2_DSC_CLR_FRC_SHIFT 4 24783 24784 /* Dsc2b0 :: sm_ctrl2 :: train2_req [03:03] */ 24785 #define DSC2B0_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 24786 #define DSC2B0_SM_CTRL2_TRAIN2_REQ_ALIGN 0 24787 #define DSC2B0_SM_CTRL2_TRAIN2_REQ_BITS 1 24788 #define DSC2B0_SM_CTRL2_TRAIN2_REQ_SHIFT 3 24789 24790 /* Dsc2b0 :: sm_ctrl2 :: train1_req [02:02] */ 24791 #define DSC2B0_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 24792 #define DSC2B0_SM_CTRL2_TRAIN1_REQ_ALIGN 0 24793 #define DSC2B0_SM_CTRL2_TRAIN1_REQ_BITS 1 24794 #define DSC2B0_SM_CTRL2_TRAIN1_REQ_SHIFT 2 24795 24796 /* Dsc2b0 :: sm_ctrl2 :: soft_ack [01:01] */ 24797 #define DSC2B0_SM_CTRL2_SOFT_ACK_MASK 0x0002 24798 #define DSC2B0_SM_CTRL2_SOFT_ACK_ALIGN 0 24799 #define DSC2B0_SM_CTRL2_SOFT_ACK_BITS 1 24800 #define DSC2B0_SM_CTRL2_SOFT_ACK_SHIFT 1 24801 24802 /* Dsc2b0 :: sm_ctrl2 :: train_mode_en [00:00] */ 24803 #define DSC2B0_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 24804 #define DSC2B0_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 24805 #define DSC2B0_SM_CTRL2_TRAIN_MODE_EN_BITS 1 24806 #define DSC2B0_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 24807 24808 24809 /**************************************************************************** 24810 * Dsc2b0 :: sm_ctrl3 24811 */ 24812 /* Dsc2b0 :: sm_ctrl3 :: reserved_for_eco0 [15:15] */ 24813 #define DSC2B0_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0x8000 24814 #define DSC2B0_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 24815 #define DSC2B0_SM_CTRL3_RESERVED_FOR_ECO0_BITS 1 24816 #define DSC2B0_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 15 24817 24818 /* Dsc2b0 :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 24819 #define DSC2B0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 24820 #define DSC2B0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 24821 #define DSC2B0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 24822 #define DSC2B0_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 24823 24824 /* Dsc2b0 :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 24825 #define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 24826 #define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 24827 #define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 24828 #define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 24829 24830 /* Dsc2b0 :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 24831 #define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 24832 #define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 24833 #define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 24834 #define DSC2B0_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 24835 24836 /* Dsc2b0 :: sm_ctrl3 :: vga_gain_acq2 [07:06] */ 24837 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 24838 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 24839 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 24840 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 24841 24842 /* Dsc2b0 :: sm_ctrl3 :: vga_gain_acq1 [05:04] */ 24843 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 24844 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 24845 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 24846 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 24847 24848 /* Dsc2b0 :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 24849 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 24850 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 24851 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 24852 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 24853 24854 /* Dsc2b0 :: sm_ctrl3 :: vga_gain_acqvga [01:00] */ 24855 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 24856 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 24857 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 24858 #define DSC2B0_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 24859 24860 24861 /**************************************************************************** 24862 * Dsc2b0 :: sm_ctrl4 24863 */ 24864 /* Dsc2b0 :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 24865 #define DSC2B0_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 24866 #define DSC2B0_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 24867 #define DSC2B0_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 24868 #define DSC2B0_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 24869 24870 /* Dsc2b0 :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */ 24871 #define DSC2B0_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK 0x3000 24872 #define DSC2B0_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN 0 24873 #define DSC2B0_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS 2 24874 #define DSC2B0_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT 12 24875 24876 /* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */ 24877 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 24878 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 24879 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 24880 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 24881 24882 /* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */ 24883 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 24884 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 24885 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 24886 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 24887 24888 /* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 24889 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 24890 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 24891 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 24892 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 24893 24894 /* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */ 24895 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 24896 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 24897 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS 3 24898 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 24899 24900 /* Dsc2b0 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */ 24901 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 24902 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 24903 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS 3 24904 #define DSC2B0_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 24905 24906 24907 /**************************************************************************** 24908 * Dsc2b0 :: sm_ctrl5 24909 */ 24910 /* Dsc2b0 :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */ 24911 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 24912 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 24913 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 24914 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 24915 24916 /* Dsc2b0 :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */ 24917 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 24918 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 24919 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 24920 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 24921 24922 /* Dsc2b0 :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */ 24923 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 24924 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 24925 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 24926 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 24927 24928 /* Dsc2b0 :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */ 24929 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 24930 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 24931 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS 4 24932 #define DSC2B0_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 24933 24934 24935 /**************************************************************************** 24936 * Dsc2b0 :: sm_ctrl6 24937 */ 24938 /* Dsc2b0 :: sm_ctrl6 :: reserved_for_eco0 [15:13] */ 24939 #define DSC2B0_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xe000 24940 #define DSC2B0_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 24941 #define DSC2B0_SM_CTRL6_RESERVED_FOR_ECO0_BITS 3 24942 #define DSC2B0_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 13 24943 24944 /* Dsc2b0 :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */ 24945 #define DSC2B0_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x1800 24946 #define DSC2B0_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 24947 #define DSC2B0_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 2 24948 #define DSC2B0_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 11 24949 24950 /* Dsc2b0 :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */ 24951 #define DSC2B0_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0700 24952 #define DSC2B0_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 24953 #define DSC2B0_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 24954 #define DSC2B0_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 8 24955 24956 /* Dsc2b0 :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */ 24957 #define DSC2B0_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x00f0 24958 #define DSC2B0_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 24959 #define DSC2B0_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 24960 #define DSC2B0_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 4 24961 24962 /* Dsc2b0 :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */ 24963 #define DSC2B0_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 24964 #define DSC2B0_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 24965 #define DSC2B0_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS 4 24966 #define DSC2B0_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 24967 24968 24969 /**************************************************************************** 24970 * Dsc2b0 :: sm_ctrl7 24971 */ 24972 /* Dsc2b0 :: sm_ctrl7 :: reserved_for_eco0 [15:15] */ 24973 #define DSC2B0_SM_CTRL7_RESERVED_FOR_ECO0_MASK 0x8000 24974 #define DSC2B0_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN 0 24975 #define DSC2B0_SM_CTRL7_RESERVED_FOR_ECO0_BITS 1 24976 #define DSC2B0_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT 15 24977 24978 /* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */ 24979 #define DSC2B0_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK 0x7000 24980 #define DSC2B0_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN 0 24981 #define DSC2B0_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS 3 24982 #define DSC2B0_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT 12 24983 24984 /* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */ 24985 #define DSC2B0_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK 0x0e00 24986 #define DSC2B0_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN 0 24987 #define DSC2B0_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS 3 24988 #define DSC2B0_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT 9 24989 24990 /* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */ 24991 #define DSC2B0_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK 0x01c0 24992 #define DSC2B0_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN 0 24993 #define DSC2B0_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS 3 24994 #define DSC2B0_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT 6 24995 24996 /* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */ 24997 #define DSC2B0_SM_CTRL7_PF_CTRL_BR_INIT_MASK 0x0038 24998 #define DSC2B0_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN 0 24999 #define DSC2B0_SM_CTRL7_PF_CTRL_BR_INIT_BITS 3 25000 #define DSC2B0_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT 3 25001 25002 /* Dsc2b0 :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */ 25003 #define DSC2B0_SM_CTRL7_PF_CTRL_OS_INIT_MASK 0x0007 25004 #define DSC2B0_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN 0 25005 #define DSC2B0_SM_CTRL7_PF_CTRL_OS_INIT_BITS 3 25006 #define DSC2B0_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT 0 25007 25008 25009 /**************************************************************************** 25010 * Dsc2b0 :: sm_ctrl8 25011 */ 25012 /* Dsc2b0 :: sm_ctrl8 :: reserved_for_eco0 [15:10] */ 25013 #define DSC2B0_SM_CTRL8_RESERVED_FOR_ECO0_MASK 0xfc00 25014 #define DSC2B0_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN 0 25015 #define DSC2B0_SM_CTRL8_RESERVED_FOR_ECO0_BITS 6 25016 #define DSC2B0_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT 10 25017 25018 /* Dsc2b0 :: sm_ctrl8 :: vga_max_val [09:05] */ 25019 #define DSC2B0_SM_CTRL8_VGA_MAX_VAL_MASK 0x03e0 25020 #define DSC2B0_SM_CTRL8_VGA_MAX_VAL_ALIGN 0 25021 #define DSC2B0_SM_CTRL8_VGA_MAX_VAL_BITS 5 25022 #define DSC2B0_SM_CTRL8_VGA_MAX_VAL_SHIFT 5 25023 25024 /* Dsc2b0 :: sm_ctrl8 :: vga_min_val [04:00] */ 25025 #define DSC2B0_SM_CTRL8_VGA_MIN_VAL_MASK 0x001f 25026 #define DSC2B0_SM_CTRL8_VGA_MIN_VAL_ALIGN 0 25027 #define DSC2B0_SM_CTRL8_VGA_MIN_VAL_BITS 5 25028 #define DSC2B0_SM_CTRL8_VGA_MIN_VAL_SHIFT 0 25029 25030 25031 /**************************************************************************** 25032 * Dsc2b0 :: sm_ctrl9 25033 */ 25034 /* Dsc2b0 :: sm_ctrl9 :: reserved_for_eco0 [15:12] */ 25035 #define DSC2B0_SM_CTRL9_RESERVED_FOR_ECO0_MASK 0xf000 25036 #define DSC2B0_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN 0 25037 #define DSC2B0_SM_CTRL9_RESERVED_FOR_ECO0_BITS 4 25038 #define DSC2B0_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT 12 25039 25040 /* Dsc2b0 :: sm_ctrl9 :: dfe_max_val [11:06] */ 25041 #define DSC2B0_SM_CTRL9_DFE_MAX_VAL_MASK 0x0fc0 25042 #define DSC2B0_SM_CTRL9_DFE_MAX_VAL_ALIGN 0 25043 #define DSC2B0_SM_CTRL9_DFE_MAX_VAL_BITS 6 25044 #define DSC2B0_SM_CTRL9_DFE_MAX_VAL_SHIFT 6 25045 25046 /* Dsc2b0 :: sm_ctrl9 :: dfe_min_val [05:00] */ 25047 #define DSC2B0_SM_CTRL9_DFE_MIN_VAL_MASK 0x003f 25048 #define DSC2B0_SM_CTRL9_DFE_MIN_VAL_ALIGN 0 25049 #define DSC2B0_SM_CTRL9_DFE_MIN_VAL_BITS 6 25050 #define DSC2B0_SM_CTRL9_DFE_MIN_VAL_SHIFT 0 25051 25052 25053 /**************************************************************************** 25054 * Dsc2b0 :: sm_ctrl10 25055 */ 25056 /* Dsc2b0 :: sm_ctrl10 :: reserved_for_eco0 [15:14] */ 25057 #define DSC2B0_SM_CTRL10_RESERVED_FOR_ECO0_MASK 0xc000 25058 #define DSC2B0_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN 0 25059 #define DSC2B0_SM_CTRL10_RESERVED_FOR_ECO0_BITS 2 25060 #define DSC2B0_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT 14 25061 25062 /* Dsc2b0 :: sm_ctrl10 :: br_pf_tap_en [13:07] */ 25063 #define DSC2B0_SM_CTRL10_BR_PF_TAP_EN_MASK 0x3f80 25064 #define DSC2B0_SM_CTRL10_BR_PF_TAP_EN_ALIGN 0 25065 #define DSC2B0_SM_CTRL10_BR_PF_TAP_EN_BITS 7 25066 #define DSC2B0_SM_CTRL10_BR_PF_TAP_EN_SHIFT 7 25067 25068 /* Dsc2b0 :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */ 25069 #define DSC2B0_SM_CTRL10_OSX1_PF_TAP_EN_MASK 0x007f 25070 #define DSC2B0_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN 0 25071 #define DSC2B0_SM_CTRL10_OSX1_PF_TAP_EN_BITS 7 25072 #define DSC2B0_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT 0 25073 25074 25075 /**************************************************************************** 25076 * Dsc2b0 :: sm_ctrl11 25077 */ 25078 /* Dsc2b0 :: sm_ctrl11 :: reserved_for_eco0 [15:15] */ 25079 #define DSC2B0_SM_CTRL11_RESERVED_FOR_ECO0_MASK 0x8000 25080 #define DSC2B0_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN 0 25081 #define DSC2B0_SM_CTRL11_RESERVED_FOR_ECO0_BITS 1 25082 #define DSC2B0_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT 15 25083 25084 /* Dsc2b0 :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */ 25085 #define DSC2B0_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK 0x7c00 25086 #define DSC2B0_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN 0 25087 #define DSC2B0_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS 5 25088 #define DSC2B0_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT 10 25089 25090 /* Dsc2b0 :: sm_ctrl11 :: hysteresis_timeout [09:05] */ 25091 #define DSC2B0_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK 0x03e0 25092 #define DSC2B0_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN 0 25093 #define DSC2B0_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS 5 25094 #define DSC2B0_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT 5 25095 25096 /* Dsc2b0 :: sm_ctrl11 :: msr_postc_timeout [04:00] */ 25097 #define DSC2B0_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK 0x001f 25098 #define DSC2B0_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN 0 25099 #define DSC2B0_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS 5 25100 #define DSC2B0_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT 0 25101 25102 25103 /**************************************************************************** 25104 * Dsc2b0 :: sm_ctrl12 25105 */ 25106 /* Dsc2b0 :: sm_ctrl12 :: reserved_for_eco0 [15:14] */ 25107 #define DSC2B0_SM_CTRL12_RESERVED_FOR_ECO0_MASK 0xc000 25108 #define DSC2B0_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN 0 25109 #define DSC2B0_SM_CTRL12_RESERVED_FOR_ECO0_BITS 2 25110 #define DSC2B0_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT 14 25111 25112 /* Dsc2b0 :: sm_ctrl12 :: br_vga_lms_gain [13:12] */ 25113 #define DSC2B0_SM_CTRL12_BR_VGA_LMS_GAIN_MASK 0x3000 25114 #define DSC2B0_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN 0 25115 #define DSC2B0_SM_CTRL12_BR_VGA_LMS_GAIN_BITS 2 25116 #define DSC2B0_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT 12 25117 25118 /* Dsc2b0 :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */ 25119 #define DSC2B0_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK 0x0c00 25120 #define DSC2B0_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN 0 25121 #define DSC2B0_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS 2 25122 #define DSC2B0_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT 10 25123 25124 /* Dsc2b0 :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */ 25125 #define DSC2B0_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK 0x03e0 25126 #define DSC2B0_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN 0 25127 #define DSC2B0_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS 5 25128 #define DSC2B0_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT 5 25129 25130 /* Dsc2b0 :: sm_ctrl12 :: msr_pf_timeout [04:00] */ 25131 #define DSC2B0_SM_CTRL12_MSR_PF_TIMEOUT_MASK 0x001f 25132 #define DSC2B0_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN 0 25133 #define DSC2B0_SM_CTRL12_MSR_PF_TIMEOUT_BITS 5 25134 #define DSC2B0_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT 0 25135 25136 25137 /**************************************************************************** 25138 * Dsc2b0 :: dsc_diag_ctrl0 25139 */ 25140 /* Dsc2b0 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */ 25141 #define DSC2B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 25142 #define DSC2B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 25143 #define DSC2B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS 5 25144 #define DSC2B0_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 25145 25146 /* Dsc2b0 :: dsc_diag_ctrl0 :: voffset [10:07] */ 25147 #define DSC2B0_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 25148 #define DSC2B0_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 25149 #define DSC2B0_DSC_DIAG_CTRL0_VOFFSET_BITS 4 25150 #define DSC2B0_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 25151 25152 /* Dsc2b0 :: dsc_diag_ctrl0 :: hoffset [06:01] */ 25153 #define DSC2B0_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 25154 #define DSC2B0_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 25155 #define DSC2B0_DSC_DIAG_CTRL0_HOFFSET_BITS 6 25156 #define DSC2B0_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 25157 25158 /* Dsc2b0 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 25159 #define DSC2B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 25160 #define DSC2B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 25161 #define DSC2B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 25162 #define DSC2B0_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 25163 25164 25165 /**************************************************************************** 25166 * Dsc2b0 :: dsc_misc_ctrl0 25167 */ 25168 /* Dsc2b0 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 25169 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 25170 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 25171 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 25172 #define DSC2B0_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 25173 25174 /* Dsc2b0 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 25175 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 25176 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 25177 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 25178 #define DSC2B0_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 25179 25180 /* Dsc2b0 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */ 25181 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK 0x2000 25182 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN 0 25183 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS 1 25184 #define DSC2B0_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT 13 25185 25186 /* Dsc2b0 :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */ 25187 #define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK 0x1c00 25188 #define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 25189 #define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS 3 25190 #define DSC2B0_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT 10 25191 25192 /* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 25193 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 25194 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 25195 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 25196 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 25197 25198 /* Dsc2b0 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 25199 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 25200 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 25201 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 25202 #define DSC2B0_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 25203 25204 /* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 25205 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 25206 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 25207 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 25208 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 25209 25210 /* Dsc2b0 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 25211 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 25212 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 25213 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 25214 #define DSC2B0_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 25215 25216 /* Dsc2b0 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 25217 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 25218 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 25219 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 25220 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 25221 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 25222 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 25223 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 25224 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 25225 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 25226 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 25227 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 25228 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 25229 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 25230 #define DSC2B0_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 25231 25232 25233 /**************************************************************************** 25234 * Hypercore_USER_Dsc2b1 25235 */ 25236 /**************************************************************************** 25237 * Dsc2b1 :: sm_ctrl0 25238 */ 25239 /* Dsc2b1 :: sm_ctrl0 :: reserved_for_eco0 [15:15] */ 25240 #define DSC2B1_SM_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 25241 #define DSC2B1_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 25242 #define DSC2B1_SM_CTRL0_RESERVED_FOR_ECO0_BITS 1 25243 #define DSC2B1_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 25244 25245 /* Dsc2b1 :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */ 25246 #define DSC2B1_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK 0x4000 25247 #define DSC2B1_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN 0 25248 #define DSC2B1_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS 1 25249 #define DSC2B1_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT 14 25250 25251 /* Dsc2b1 :: sm_ctrl0 :: bypass_br_vga [13:13] */ 25252 #define DSC2B1_SM_CTRL0_BYPASS_BR_VGA_MASK 0x2000 25253 #define DSC2B1_SM_CTRL0_BYPASS_BR_VGA_ALIGN 0 25254 #define DSC2B1_SM_CTRL0_BYPASS_BR_VGA_BITS 1 25255 #define DSC2B1_SM_CTRL0_BYPASS_BR_VGA_SHIFT 13 25256 25257 /* Dsc2b1 :: sm_ctrl0 :: postc_metric_ctrl [12:12] */ 25258 #define DSC2B1_SM_CTRL0_POSTC_METRIC_CTRL_MASK 0x1000 25259 #define DSC2B1_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN 0 25260 #define DSC2B1_SM_CTRL0_POSTC_METRIC_CTRL_BITS 1 25261 #define DSC2B1_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT 12 25262 25263 /* Dsc2b1 :: sm_ctrl0 :: hysteresis_en [11:11] */ 25264 #define DSC2B1_SM_CTRL0_HYSTERESIS_EN_MASK 0x0800 25265 #define DSC2B1_SM_CTRL0_HYSTERESIS_EN_ALIGN 0 25266 #define DSC2B1_SM_CTRL0_HYSTERESIS_EN_BITS 1 25267 #define DSC2B1_SM_CTRL0_HYSTERESIS_EN_SHIFT 11 25268 25269 /* Dsc2b1 :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */ 25270 #define DSC2B1_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK 0x0400 25271 #define DSC2B1_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN 0 25272 #define DSC2B1_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS 1 25273 #define DSC2B1_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT 10 25274 25275 /* Dsc2b1 :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */ 25276 #define DSC2B1_SM_CTRL0_BYPASS_BR_PF_CAL_MASK 0x0200 25277 #define DSC2B1_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN 0 25278 #define DSC2B1_SM_CTRL0_BYPASS_BR_PF_CAL_BITS 1 25279 #define DSC2B1_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT 9 25280 25281 /* Dsc2b1 :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */ 25282 #define DSC2B1_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK 0x0100 25283 #define DSC2B1_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN 0 25284 #define DSC2B1_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS 1 25285 #define DSC2B1_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT 8 25286 25287 /* Dsc2b1 :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */ 25288 #define DSC2B1_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK 0x0080 25289 #define DSC2B1_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN 0 25290 #define DSC2B1_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS 1 25291 #define DSC2B1_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT 7 25292 25293 /* Dsc2b1 :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */ 25294 #define DSC2B1_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK 0x0040 25295 #define DSC2B1_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN 0 25296 #define DSC2B1_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS 1 25297 #define DSC2B1_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT 6 25298 25299 /* Dsc2b1 :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */ 25300 #define DSC2B1_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK 0x0020 25301 #define DSC2B1_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN 0 25302 #define DSC2B1_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS 1 25303 #define DSC2B1_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT 5 25304 25305 /* Dsc2b1 :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */ 25306 #define DSC2B1_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK 0x0010 25307 #define DSC2B1_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN 0 25308 #define DSC2B1_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS 1 25309 #define DSC2B1_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT 4 25310 25311 /* Dsc2b1 :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */ 25312 #define DSC2B1_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK 0x0008 25313 #define DSC2B1_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN 0 25314 #define DSC2B1_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS 1 25315 #define DSC2B1_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT 3 25316 25317 /* Dsc2b1 :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */ 25318 #define DSC2B1_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK 0x0004 25319 #define DSC2B1_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN 0 25320 #define DSC2B1_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS 1 25321 #define DSC2B1_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT 2 25322 25323 /* Dsc2b1 :: sm_ctrl0 :: restart_tuning [01:01] */ 25324 #define DSC2B1_SM_CTRL0_RESTART_TUNING_MASK 0x0002 25325 #define DSC2B1_SM_CTRL0_RESTART_TUNING_ALIGN 0 25326 #define DSC2B1_SM_CTRL0_RESTART_TUNING_BITS 1 25327 #define DSC2B1_SM_CTRL0_RESTART_TUNING_SHIFT 1 25328 25329 /* Dsc2b1 :: sm_ctrl0 :: tuning_sm_en [00:00] */ 25330 #define DSC2B1_SM_CTRL0_TUNING_SM_EN_MASK 0x0001 25331 #define DSC2B1_SM_CTRL0_TUNING_SM_EN_ALIGN 0 25332 #define DSC2B1_SM_CTRL0_TUNING_SM_EN_BITS 1 25333 #define DSC2B1_SM_CTRL0_TUNING_SM_EN_SHIFT 0 25334 25335 25336 /**************************************************************************** 25337 * Dsc2b1 :: sm_ctrl1 25338 */ 25339 /* Dsc2b1 :: sm_ctrl1 :: fast_timer [15:15] */ 25340 #define DSC2B1_SM_CTRL1_FAST_TIMER_MASK 0x8000 25341 #define DSC2B1_SM_CTRL1_FAST_TIMER_ALIGN 0 25342 #define DSC2B1_SM_CTRL1_FAST_TIMER_BITS 1 25343 #define DSC2B1_SM_CTRL1_FAST_TIMER_SHIFT 15 25344 25345 /* Dsc2b1 :: sm_ctrl1 :: acq2_timeout [14:10] */ 25346 #define DSC2B1_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 25347 #define DSC2B1_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 25348 #define DSC2B1_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 25349 #define DSC2B1_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 25350 25351 /* Dsc2b1 :: sm_ctrl1 :: acq1_timeout [09:05] */ 25352 #define DSC2B1_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 25353 #define DSC2B1_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 25354 #define DSC2B1_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 25355 #define DSC2B1_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 25356 25357 /* Dsc2b1 :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 25358 #define DSC2B1_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 25359 #define DSC2B1_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 25360 #define DSC2B1_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 25361 #define DSC2B1_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 25362 25363 25364 /**************************************************************************** 25365 * Dsc2b1 :: sm_ctrl2 25366 */ 25367 /* Dsc2b1 :: sm_ctrl2 :: acqvga_timeout [15:11] */ 25368 #define DSC2B1_SM_CTRL2_ACQVGA_TIMEOUT_MASK 0xf800 25369 #define DSC2B1_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN 0 25370 #define DSC2B1_SM_CTRL2_ACQVGA_TIMEOUT_BITS 5 25371 #define DSC2B1_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT 11 25372 25373 /* Dsc2b1 :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */ 25374 #define DSC2B1_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK 0x0400 25375 #define DSC2B1_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN 0 25376 #define DSC2B1_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS 1 25377 #define DSC2B1_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT 10 25378 25379 /* Dsc2b1 :: sm_ctrl2 :: vga_frzval [09:09] */ 25380 #define DSC2B1_SM_CTRL2_VGA_FRZVAL_MASK 0x0200 25381 #define DSC2B1_SM_CTRL2_VGA_FRZVAL_ALIGN 0 25382 #define DSC2B1_SM_CTRL2_VGA_FRZVAL_BITS 1 25383 #define DSC2B1_SM_CTRL2_VGA_FRZVAL_SHIFT 9 25384 25385 /* Dsc2b1 :: sm_ctrl2 :: vga_frcfrz [08:08] */ 25386 #define DSC2B1_SM_CTRL2_VGA_FRCFRZ_MASK 0x0100 25387 #define DSC2B1_SM_CTRL2_VGA_FRCFRZ_ALIGN 0 25388 #define DSC2B1_SM_CTRL2_VGA_FRCFRZ_BITS 1 25389 #define DSC2B1_SM_CTRL2_VGA_FRCFRZ_SHIFT 8 25390 25391 /* Dsc2b1 :: sm_ctrl2 :: dfe_frzval [07:07] */ 25392 #define DSC2B1_SM_CTRL2_DFE_FRZVAL_MASK 0x0080 25393 #define DSC2B1_SM_CTRL2_DFE_FRZVAL_ALIGN 0 25394 #define DSC2B1_SM_CTRL2_DFE_FRZVAL_BITS 1 25395 #define DSC2B1_SM_CTRL2_DFE_FRZVAL_SHIFT 7 25396 25397 /* Dsc2b1 :: sm_ctrl2 :: dfe_frcfrz [06:06] */ 25398 #define DSC2B1_SM_CTRL2_DFE_FRCFRZ_MASK 0x0040 25399 #define DSC2B1_SM_CTRL2_DFE_FRCFRZ_ALIGN 0 25400 #define DSC2B1_SM_CTRL2_DFE_FRCFRZ_BITS 1 25401 #define DSC2B1_SM_CTRL2_DFE_FRCFRZ_SHIFT 6 25402 25403 /* Dsc2b1 :: sm_ctrl2 :: dsc_clr_val [05:05] */ 25404 #define DSC2B1_SM_CTRL2_DSC_CLR_VAL_MASK 0x0020 25405 #define DSC2B1_SM_CTRL2_DSC_CLR_VAL_ALIGN 0 25406 #define DSC2B1_SM_CTRL2_DSC_CLR_VAL_BITS 1 25407 #define DSC2B1_SM_CTRL2_DSC_CLR_VAL_SHIFT 5 25408 25409 /* Dsc2b1 :: sm_ctrl2 :: dsc_clr_frc [04:04] */ 25410 #define DSC2B1_SM_CTRL2_DSC_CLR_FRC_MASK 0x0010 25411 #define DSC2B1_SM_CTRL2_DSC_CLR_FRC_ALIGN 0 25412 #define DSC2B1_SM_CTRL2_DSC_CLR_FRC_BITS 1 25413 #define DSC2B1_SM_CTRL2_DSC_CLR_FRC_SHIFT 4 25414 25415 /* Dsc2b1 :: sm_ctrl2 :: train2_req [03:03] */ 25416 #define DSC2B1_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 25417 #define DSC2B1_SM_CTRL2_TRAIN2_REQ_ALIGN 0 25418 #define DSC2B1_SM_CTRL2_TRAIN2_REQ_BITS 1 25419 #define DSC2B1_SM_CTRL2_TRAIN2_REQ_SHIFT 3 25420 25421 /* Dsc2b1 :: sm_ctrl2 :: train1_req [02:02] */ 25422 #define DSC2B1_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 25423 #define DSC2B1_SM_CTRL2_TRAIN1_REQ_ALIGN 0 25424 #define DSC2B1_SM_CTRL2_TRAIN1_REQ_BITS 1 25425 #define DSC2B1_SM_CTRL2_TRAIN1_REQ_SHIFT 2 25426 25427 /* Dsc2b1 :: sm_ctrl2 :: soft_ack [01:01] */ 25428 #define DSC2B1_SM_CTRL2_SOFT_ACK_MASK 0x0002 25429 #define DSC2B1_SM_CTRL2_SOFT_ACK_ALIGN 0 25430 #define DSC2B1_SM_CTRL2_SOFT_ACK_BITS 1 25431 #define DSC2B1_SM_CTRL2_SOFT_ACK_SHIFT 1 25432 25433 /* Dsc2b1 :: sm_ctrl2 :: train_mode_en [00:00] */ 25434 #define DSC2B1_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 25435 #define DSC2B1_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 25436 #define DSC2B1_SM_CTRL2_TRAIN_MODE_EN_BITS 1 25437 #define DSC2B1_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 25438 25439 25440 /**************************************************************************** 25441 * Dsc2b1 :: sm_ctrl3 25442 */ 25443 /* Dsc2b1 :: sm_ctrl3 :: reserved_for_eco0 [15:15] */ 25444 #define DSC2B1_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0x8000 25445 #define DSC2B1_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 25446 #define DSC2B1_SM_CTRL3_RESERVED_FOR_ECO0_BITS 1 25447 #define DSC2B1_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 15 25448 25449 /* Dsc2b1 :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 25450 #define DSC2B1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 25451 #define DSC2B1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 25452 #define DSC2B1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 25453 #define DSC2B1_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 25454 25455 /* Dsc2b1 :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 25456 #define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 25457 #define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 25458 #define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 25459 #define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 25460 25461 /* Dsc2b1 :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 25462 #define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 25463 #define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 25464 #define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 25465 #define DSC2B1_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 25466 25467 /* Dsc2b1 :: sm_ctrl3 :: vga_gain_acq2 [07:06] */ 25468 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 25469 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 25470 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 25471 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 25472 25473 /* Dsc2b1 :: sm_ctrl3 :: vga_gain_acq1 [05:04] */ 25474 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 25475 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 25476 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 25477 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 25478 25479 /* Dsc2b1 :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 25480 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 25481 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 25482 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 25483 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 25484 25485 /* Dsc2b1 :: sm_ctrl3 :: vga_gain_acqvga [01:00] */ 25486 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 25487 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 25488 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 25489 #define DSC2B1_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 25490 25491 25492 /**************************************************************************** 25493 * Dsc2b1 :: sm_ctrl4 25494 */ 25495 /* Dsc2b1 :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 25496 #define DSC2B1_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 25497 #define DSC2B1_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 25498 #define DSC2B1_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 25499 #define DSC2B1_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 25500 25501 /* Dsc2b1 :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */ 25502 #define DSC2B1_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK 0x3000 25503 #define DSC2B1_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN 0 25504 #define DSC2B1_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS 2 25505 #define DSC2B1_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT 12 25506 25507 /* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */ 25508 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 25509 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 25510 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 25511 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 25512 25513 /* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */ 25514 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 25515 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 25516 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 25517 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 25518 25519 /* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 25520 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 25521 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 25522 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 25523 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 25524 25525 /* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */ 25526 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 25527 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 25528 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS 3 25529 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 25530 25531 /* Dsc2b1 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */ 25532 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 25533 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 25534 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS 3 25535 #define DSC2B1_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 25536 25537 25538 /**************************************************************************** 25539 * Dsc2b1 :: sm_ctrl5 25540 */ 25541 /* Dsc2b1 :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */ 25542 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 25543 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 25544 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 25545 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 25546 25547 /* Dsc2b1 :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */ 25548 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 25549 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 25550 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 25551 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 25552 25553 /* Dsc2b1 :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */ 25554 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 25555 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 25556 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 25557 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 25558 25559 /* Dsc2b1 :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */ 25560 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 25561 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 25562 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS 4 25563 #define DSC2B1_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 25564 25565 25566 /**************************************************************************** 25567 * Dsc2b1 :: sm_ctrl6 25568 */ 25569 /* Dsc2b1 :: sm_ctrl6 :: reserved_for_eco0 [15:13] */ 25570 #define DSC2B1_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xe000 25571 #define DSC2B1_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 25572 #define DSC2B1_SM_CTRL6_RESERVED_FOR_ECO0_BITS 3 25573 #define DSC2B1_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 13 25574 25575 /* Dsc2b1 :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */ 25576 #define DSC2B1_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x1800 25577 #define DSC2B1_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 25578 #define DSC2B1_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 2 25579 #define DSC2B1_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 11 25580 25581 /* Dsc2b1 :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */ 25582 #define DSC2B1_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0700 25583 #define DSC2B1_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 25584 #define DSC2B1_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 25585 #define DSC2B1_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 8 25586 25587 /* Dsc2b1 :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */ 25588 #define DSC2B1_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x00f0 25589 #define DSC2B1_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 25590 #define DSC2B1_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 25591 #define DSC2B1_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 4 25592 25593 /* Dsc2b1 :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */ 25594 #define DSC2B1_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 25595 #define DSC2B1_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 25596 #define DSC2B1_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS 4 25597 #define DSC2B1_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 25598 25599 25600 /**************************************************************************** 25601 * Dsc2b1 :: sm_ctrl7 25602 */ 25603 /* Dsc2b1 :: sm_ctrl7 :: reserved_for_eco0 [15:15] */ 25604 #define DSC2B1_SM_CTRL7_RESERVED_FOR_ECO0_MASK 0x8000 25605 #define DSC2B1_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN 0 25606 #define DSC2B1_SM_CTRL7_RESERVED_FOR_ECO0_BITS 1 25607 #define DSC2B1_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT 15 25608 25609 /* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */ 25610 #define DSC2B1_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK 0x7000 25611 #define DSC2B1_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN 0 25612 #define DSC2B1_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS 3 25613 #define DSC2B1_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT 12 25614 25615 /* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */ 25616 #define DSC2B1_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK 0x0e00 25617 #define DSC2B1_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN 0 25618 #define DSC2B1_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS 3 25619 #define DSC2B1_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT 9 25620 25621 /* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */ 25622 #define DSC2B1_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK 0x01c0 25623 #define DSC2B1_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN 0 25624 #define DSC2B1_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS 3 25625 #define DSC2B1_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT 6 25626 25627 /* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */ 25628 #define DSC2B1_SM_CTRL7_PF_CTRL_BR_INIT_MASK 0x0038 25629 #define DSC2B1_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN 0 25630 #define DSC2B1_SM_CTRL7_PF_CTRL_BR_INIT_BITS 3 25631 #define DSC2B1_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT 3 25632 25633 /* Dsc2b1 :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */ 25634 #define DSC2B1_SM_CTRL7_PF_CTRL_OS_INIT_MASK 0x0007 25635 #define DSC2B1_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN 0 25636 #define DSC2B1_SM_CTRL7_PF_CTRL_OS_INIT_BITS 3 25637 #define DSC2B1_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT 0 25638 25639 25640 /**************************************************************************** 25641 * Dsc2b1 :: sm_ctrl8 25642 */ 25643 /* Dsc2b1 :: sm_ctrl8 :: reserved_for_eco0 [15:10] */ 25644 #define DSC2B1_SM_CTRL8_RESERVED_FOR_ECO0_MASK 0xfc00 25645 #define DSC2B1_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN 0 25646 #define DSC2B1_SM_CTRL8_RESERVED_FOR_ECO0_BITS 6 25647 #define DSC2B1_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT 10 25648 25649 /* Dsc2b1 :: sm_ctrl8 :: vga_max_val [09:05] */ 25650 #define DSC2B1_SM_CTRL8_VGA_MAX_VAL_MASK 0x03e0 25651 #define DSC2B1_SM_CTRL8_VGA_MAX_VAL_ALIGN 0 25652 #define DSC2B1_SM_CTRL8_VGA_MAX_VAL_BITS 5 25653 #define DSC2B1_SM_CTRL8_VGA_MAX_VAL_SHIFT 5 25654 25655 /* Dsc2b1 :: sm_ctrl8 :: vga_min_val [04:00] */ 25656 #define DSC2B1_SM_CTRL8_VGA_MIN_VAL_MASK 0x001f 25657 #define DSC2B1_SM_CTRL8_VGA_MIN_VAL_ALIGN 0 25658 #define DSC2B1_SM_CTRL8_VGA_MIN_VAL_BITS 5 25659 #define DSC2B1_SM_CTRL8_VGA_MIN_VAL_SHIFT 0 25660 25661 25662 /**************************************************************************** 25663 * Dsc2b1 :: sm_ctrl9 25664 */ 25665 /* Dsc2b1 :: sm_ctrl9 :: reserved_for_eco0 [15:12] */ 25666 #define DSC2B1_SM_CTRL9_RESERVED_FOR_ECO0_MASK 0xf000 25667 #define DSC2B1_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN 0 25668 #define DSC2B1_SM_CTRL9_RESERVED_FOR_ECO0_BITS 4 25669 #define DSC2B1_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT 12 25670 25671 /* Dsc2b1 :: sm_ctrl9 :: dfe_max_val [11:06] */ 25672 #define DSC2B1_SM_CTRL9_DFE_MAX_VAL_MASK 0x0fc0 25673 #define DSC2B1_SM_CTRL9_DFE_MAX_VAL_ALIGN 0 25674 #define DSC2B1_SM_CTRL9_DFE_MAX_VAL_BITS 6 25675 #define DSC2B1_SM_CTRL9_DFE_MAX_VAL_SHIFT 6 25676 25677 /* Dsc2b1 :: sm_ctrl9 :: dfe_min_val [05:00] */ 25678 #define DSC2B1_SM_CTRL9_DFE_MIN_VAL_MASK 0x003f 25679 #define DSC2B1_SM_CTRL9_DFE_MIN_VAL_ALIGN 0 25680 #define DSC2B1_SM_CTRL9_DFE_MIN_VAL_BITS 6 25681 #define DSC2B1_SM_CTRL9_DFE_MIN_VAL_SHIFT 0 25682 25683 25684 /**************************************************************************** 25685 * Dsc2b1 :: sm_ctrl10 25686 */ 25687 /* Dsc2b1 :: sm_ctrl10 :: reserved_for_eco0 [15:14] */ 25688 #define DSC2B1_SM_CTRL10_RESERVED_FOR_ECO0_MASK 0xc000 25689 #define DSC2B1_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN 0 25690 #define DSC2B1_SM_CTRL10_RESERVED_FOR_ECO0_BITS 2 25691 #define DSC2B1_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT 14 25692 25693 /* Dsc2b1 :: sm_ctrl10 :: br_pf_tap_en [13:07] */ 25694 #define DSC2B1_SM_CTRL10_BR_PF_TAP_EN_MASK 0x3f80 25695 #define DSC2B1_SM_CTRL10_BR_PF_TAP_EN_ALIGN 0 25696 #define DSC2B1_SM_CTRL10_BR_PF_TAP_EN_BITS 7 25697 #define DSC2B1_SM_CTRL10_BR_PF_TAP_EN_SHIFT 7 25698 25699 /* Dsc2b1 :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */ 25700 #define DSC2B1_SM_CTRL10_OSX1_PF_TAP_EN_MASK 0x007f 25701 #define DSC2B1_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN 0 25702 #define DSC2B1_SM_CTRL10_OSX1_PF_TAP_EN_BITS 7 25703 #define DSC2B1_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT 0 25704 25705 25706 /**************************************************************************** 25707 * Dsc2b1 :: sm_ctrl11 25708 */ 25709 /* Dsc2b1 :: sm_ctrl11 :: reserved_for_eco0 [15:15] */ 25710 #define DSC2B1_SM_CTRL11_RESERVED_FOR_ECO0_MASK 0x8000 25711 #define DSC2B1_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN 0 25712 #define DSC2B1_SM_CTRL11_RESERVED_FOR_ECO0_BITS 1 25713 #define DSC2B1_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT 15 25714 25715 /* Dsc2b1 :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */ 25716 #define DSC2B1_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK 0x7c00 25717 #define DSC2B1_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN 0 25718 #define DSC2B1_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS 5 25719 #define DSC2B1_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT 10 25720 25721 /* Dsc2b1 :: sm_ctrl11 :: hysteresis_timeout [09:05] */ 25722 #define DSC2B1_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK 0x03e0 25723 #define DSC2B1_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN 0 25724 #define DSC2B1_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS 5 25725 #define DSC2B1_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT 5 25726 25727 /* Dsc2b1 :: sm_ctrl11 :: msr_postc_timeout [04:00] */ 25728 #define DSC2B1_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK 0x001f 25729 #define DSC2B1_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN 0 25730 #define DSC2B1_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS 5 25731 #define DSC2B1_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT 0 25732 25733 25734 /**************************************************************************** 25735 * Dsc2b1 :: sm_ctrl12 25736 */ 25737 /* Dsc2b1 :: sm_ctrl12 :: reserved_for_eco0 [15:14] */ 25738 #define DSC2B1_SM_CTRL12_RESERVED_FOR_ECO0_MASK 0xc000 25739 #define DSC2B1_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN 0 25740 #define DSC2B1_SM_CTRL12_RESERVED_FOR_ECO0_BITS 2 25741 #define DSC2B1_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT 14 25742 25743 /* Dsc2b1 :: sm_ctrl12 :: br_vga_lms_gain [13:12] */ 25744 #define DSC2B1_SM_CTRL12_BR_VGA_LMS_GAIN_MASK 0x3000 25745 #define DSC2B1_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN 0 25746 #define DSC2B1_SM_CTRL12_BR_VGA_LMS_GAIN_BITS 2 25747 #define DSC2B1_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT 12 25748 25749 /* Dsc2b1 :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */ 25750 #define DSC2B1_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK 0x0c00 25751 #define DSC2B1_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN 0 25752 #define DSC2B1_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS 2 25753 #define DSC2B1_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT 10 25754 25755 /* Dsc2b1 :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */ 25756 #define DSC2B1_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK 0x03e0 25757 #define DSC2B1_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN 0 25758 #define DSC2B1_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS 5 25759 #define DSC2B1_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT 5 25760 25761 /* Dsc2b1 :: sm_ctrl12 :: msr_pf_timeout [04:00] */ 25762 #define DSC2B1_SM_CTRL12_MSR_PF_TIMEOUT_MASK 0x001f 25763 #define DSC2B1_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN 0 25764 #define DSC2B1_SM_CTRL12_MSR_PF_TIMEOUT_BITS 5 25765 #define DSC2B1_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT 0 25766 25767 25768 /**************************************************************************** 25769 * Dsc2b1 :: dsc_diag_ctrl0 25770 */ 25771 /* Dsc2b1 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */ 25772 #define DSC2B1_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 25773 #define DSC2B1_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 25774 #define DSC2B1_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS 5 25775 #define DSC2B1_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 25776 25777 /* Dsc2b1 :: dsc_diag_ctrl0 :: voffset [10:07] */ 25778 #define DSC2B1_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 25779 #define DSC2B1_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 25780 #define DSC2B1_DSC_DIAG_CTRL0_VOFFSET_BITS 4 25781 #define DSC2B1_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 25782 25783 /* Dsc2b1 :: dsc_diag_ctrl0 :: hoffset [06:01] */ 25784 #define DSC2B1_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 25785 #define DSC2B1_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 25786 #define DSC2B1_DSC_DIAG_CTRL0_HOFFSET_BITS 6 25787 #define DSC2B1_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 25788 25789 /* Dsc2b1 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 25790 #define DSC2B1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 25791 #define DSC2B1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 25792 #define DSC2B1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 25793 #define DSC2B1_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 25794 25795 25796 /**************************************************************************** 25797 * Dsc2b1 :: dsc_misc_ctrl0 25798 */ 25799 /* Dsc2b1 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 25800 #define DSC2B1_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 25801 #define DSC2B1_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 25802 #define DSC2B1_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 25803 #define DSC2B1_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 25804 25805 /* Dsc2b1 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 25806 #define DSC2B1_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 25807 #define DSC2B1_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 25808 #define DSC2B1_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 25809 #define DSC2B1_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 25810 25811 /* Dsc2b1 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */ 25812 #define DSC2B1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK 0x2000 25813 #define DSC2B1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN 0 25814 #define DSC2B1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS 1 25815 #define DSC2B1_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT 13 25816 25817 /* Dsc2b1 :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */ 25818 #define DSC2B1_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK 0x1c00 25819 #define DSC2B1_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 25820 #define DSC2B1_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS 3 25821 #define DSC2B1_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT 10 25822 25823 /* Dsc2b1 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 25824 #define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 25825 #define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 25826 #define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 25827 #define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 25828 25829 /* Dsc2b1 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 25830 #define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 25831 #define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 25832 #define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 25833 #define DSC2B1_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 25834 25835 /* Dsc2b1 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 25836 #define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 25837 #define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 25838 #define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 25839 #define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 25840 25841 /* Dsc2b1 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 25842 #define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 25843 #define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 25844 #define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 25845 #define DSC2B1_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 25846 25847 /* Dsc2b1 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 25848 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 25849 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 25850 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 25851 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 25852 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 25853 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 25854 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 25855 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 25856 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 25857 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 25858 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 25859 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 25860 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 25861 #define DSC2B1_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 25862 25863 25864 /**************************************************************************** 25865 * Hypercore_USER_Dsc2b2 25866 */ 25867 /**************************************************************************** 25868 * Dsc2b2 :: sm_ctrl0 25869 */ 25870 /* Dsc2b2 :: sm_ctrl0 :: reserved_for_eco0 [15:15] */ 25871 #define DSC2B2_SM_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 25872 #define DSC2B2_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 25873 #define DSC2B2_SM_CTRL0_RESERVED_FOR_ECO0_BITS 1 25874 #define DSC2B2_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 25875 25876 /* Dsc2b2 :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */ 25877 #define DSC2B2_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK 0x4000 25878 #define DSC2B2_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN 0 25879 #define DSC2B2_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS 1 25880 #define DSC2B2_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT 14 25881 25882 /* Dsc2b2 :: sm_ctrl0 :: bypass_br_vga [13:13] */ 25883 #define DSC2B2_SM_CTRL0_BYPASS_BR_VGA_MASK 0x2000 25884 #define DSC2B2_SM_CTRL0_BYPASS_BR_VGA_ALIGN 0 25885 #define DSC2B2_SM_CTRL0_BYPASS_BR_VGA_BITS 1 25886 #define DSC2B2_SM_CTRL0_BYPASS_BR_VGA_SHIFT 13 25887 25888 /* Dsc2b2 :: sm_ctrl0 :: postc_metric_ctrl [12:12] */ 25889 #define DSC2B2_SM_CTRL0_POSTC_METRIC_CTRL_MASK 0x1000 25890 #define DSC2B2_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN 0 25891 #define DSC2B2_SM_CTRL0_POSTC_METRIC_CTRL_BITS 1 25892 #define DSC2B2_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT 12 25893 25894 /* Dsc2b2 :: sm_ctrl0 :: hysteresis_en [11:11] */ 25895 #define DSC2B2_SM_CTRL0_HYSTERESIS_EN_MASK 0x0800 25896 #define DSC2B2_SM_CTRL0_HYSTERESIS_EN_ALIGN 0 25897 #define DSC2B2_SM_CTRL0_HYSTERESIS_EN_BITS 1 25898 #define DSC2B2_SM_CTRL0_HYSTERESIS_EN_SHIFT 11 25899 25900 /* Dsc2b2 :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */ 25901 #define DSC2B2_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK 0x0400 25902 #define DSC2B2_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN 0 25903 #define DSC2B2_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS 1 25904 #define DSC2B2_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT 10 25905 25906 /* Dsc2b2 :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */ 25907 #define DSC2B2_SM_CTRL0_BYPASS_BR_PF_CAL_MASK 0x0200 25908 #define DSC2B2_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN 0 25909 #define DSC2B2_SM_CTRL0_BYPASS_BR_PF_CAL_BITS 1 25910 #define DSC2B2_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT 9 25911 25912 /* Dsc2b2 :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */ 25913 #define DSC2B2_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK 0x0100 25914 #define DSC2B2_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN 0 25915 #define DSC2B2_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS 1 25916 #define DSC2B2_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT 8 25917 25918 /* Dsc2b2 :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */ 25919 #define DSC2B2_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK 0x0080 25920 #define DSC2B2_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN 0 25921 #define DSC2B2_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS 1 25922 #define DSC2B2_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT 7 25923 25924 /* Dsc2b2 :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */ 25925 #define DSC2B2_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK 0x0040 25926 #define DSC2B2_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN 0 25927 #define DSC2B2_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS 1 25928 #define DSC2B2_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT 6 25929 25930 /* Dsc2b2 :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */ 25931 #define DSC2B2_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK 0x0020 25932 #define DSC2B2_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN 0 25933 #define DSC2B2_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS 1 25934 #define DSC2B2_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT 5 25935 25936 /* Dsc2b2 :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */ 25937 #define DSC2B2_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK 0x0010 25938 #define DSC2B2_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN 0 25939 #define DSC2B2_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS 1 25940 #define DSC2B2_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT 4 25941 25942 /* Dsc2b2 :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */ 25943 #define DSC2B2_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK 0x0008 25944 #define DSC2B2_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN 0 25945 #define DSC2B2_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS 1 25946 #define DSC2B2_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT 3 25947 25948 /* Dsc2b2 :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */ 25949 #define DSC2B2_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK 0x0004 25950 #define DSC2B2_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN 0 25951 #define DSC2B2_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS 1 25952 #define DSC2B2_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT 2 25953 25954 /* Dsc2b2 :: sm_ctrl0 :: restart_tuning [01:01] */ 25955 #define DSC2B2_SM_CTRL0_RESTART_TUNING_MASK 0x0002 25956 #define DSC2B2_SM_CTRL0_RESTART_TUNING_ALIGN 0 25957 #define DSC2B2_SM_CTRL0_RESTART_TUNING_BITS 1 25958 #define DSC2B2_SM_CTRL0_RESTART_TUNING_SHIFT 1 25959 25960 /* Dsc2b2 :: sm_ctrl0 :: tuning_sm_en [00:00] */ 25961 #define DSC2B2_SM_CTRL0_TUNING_SM_EN_MASK 0x0001 25962 #define DSC2B2_SM_CTRL0_TUNING_SM_EN_ALIGN 0 25963 #define DSC2B2_SM_CTRL0_TUNING_SM_EN_BITS 1 25964 #define DSC2B2_SM_CTRL0_TUNING_SM_EN_SHIFT 0 25965 25966 25967 /**************************************************************************** 25968 * Dsc2b2 :: sm_ctrl1 25969 */ 25970 /* Dsc2b2 :: sm_ctrl1 :: fast_timer [15:15] */ 25971 #define DSC2B2_SM_CTRL1_FAST_TIMER_MASK 0x8000 25972 #define DSC2B2_SM_CTRL1_FAST_TIMER_ALIGN 0 25973 #define DSC2B2_SM_CTRL1_FAST_TIMER_BITS 1 25974 #define DSC2B2_SM_CTRL1_FAST_TIMER_SHIFT 15 25975 25976 /* Dsc2b2 :: sm_ctrl1 :: acq2_timeout [14:10] */ 25977 #define DSC2B2_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 25978 #define DSC2B2_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 25979 #define DSC2B2_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 25980 #define DSC2B2_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 25981 25982 /* Dsc2b2 :: sm_ctrl1 :: acq1_timeout [09:05] */ 25983 #define DSC2B2_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 25984 #define DSC2B2_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 25985 #define DSC2B2_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 25986 #define DSC2B2_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 25987 25988 /* Dsc2b2 :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 25989 #define DSC2B2_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 25990 #define DSC2B2_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 25991 #define DSC2B2_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 25992 #define DSC2B2_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 25993 25994 25995 /**************************************************************************** 25996 * Dsc2b2 :: sm_ctrl2 25997 */ 25998 /* Dsc2b2 :: sm_ctrl2 :: acqvga_timeout [15:11] */ 25999 #define DSC2B2_SM_CTRL2_ACQVGA_TIMEOUT_MASK 0xf800 26000 #define DSC2B2_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN 0 26001 #define DSC2B2_SM_CTRL2_ACQVGA_TIMEOUT_BITS 5 26002 #define DSC2B2_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT 11 26003 26004 /* Dsc2b2 :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */ 26005 #define DSC2B2_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK 0x0400 26006 #define DSC2B2_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN 0 26007 #define DSC2B2_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS 1 26008 #define DSC2B2_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT 10 26009 26010 /* Dsc2b2 :: sm_ctrl2 :: vga_frzval [09:09] */ 26011 #define DSC2B2_SM_CTRL2_VGA_FRZVAL_MASK 0x0200 26012 #define DSC2B2_SM_CTRL2_VGA_FRZVAL_ALIGN 0 26013 #define DSC2B2_SM_CTRL2_VGA_FRZVAL_BITS 1 26014 #define DSC2B2_SM_CTRL2_VGA_FRZVAL_SHIFT 9 26015 26016 /* Dsc2b2 :: sm_ctrl2 :: vga_frcfrz [08:08] */ 26017 #define DSC2B2_SM_CTRL2_VGA_FRCFRZ_MASK 0x0100 26018 #define DSC2B2_SM_CTRL2_VGA_FRCFRZ_ALIGN 0 26019 #define DSC2B2_SM_CTRL2_VGA_FRCFRZ_BITS 1 26020 #define DSC2B2_SM_CTRL2_VGA_FRCFRZ_SHIFT 8 26021 26022 /* Dsc2b2 :: sm_ctrl2 :: dfe_frzval [07:07] */ 26023 #define DSC2B2_SM_CTRL2_DFE_FRZVAL_MASK 0x0080 26024 #define DSC2B2_SM_CTRL2_DFE_FRZVAL_ALIGN 0 26025 #define DSC2B2_SM_CTRL2_DFE_FRZVAL_BITS 1 26026 #define DSC2B2_SM_CTRL2_DFE_FRZVAL_SHIFT 7 26027 26028 /* Dsc2b2 :: sm_ctrl2 :: dfe_frcfrz [06:06] */ 26029 #define DSC2B2_SM_CTRL2_DFE_FRCFRZ_MASK 0x0040 26030 #define DSC2B2_SM_CTRL2_DFE_FRCFRZ_ALIGN 0 26031 #define DSC2B2_SM_CTRL2_DFE_FRCFRZ_BITS 1 26032 #define DSC2B2_SM_CTRL2_DFE_FRCFRZ_SHIFT 6 26033 26034 /* Dsc2b2 :: sm_ctrl2 :: dsc_clr_val [05:05] */ 26035 #define DSC2B2_SM_CTRL2_DSC_CLR_VAL_MASK 0x0020 26036 #define DSC2B2_SM_CTRL2_DSC_CLR_VAL_ALIGN 0 26037 #define DSC2B2_SM_CTRL2_DSC_CLR_VAL_BITS 1 26038 #define DSC2B2_SM_CTRL2_DSC_CLR_VAL_SHIFT 5 26039 26040 /* Dsc2b2 :: sm_ctrl2 :: dsc_clr_frc [04:04] */ 26041 #define DSC2B2_SM_CTRL2_DSC_CLR_FRC_MASK 0x0010 26042 #define DSC2B2_SM_CTRL2_DSC_CLR_FRC_ALIGN 0 26043 #define DSC2B2_SM_CTRL2_DSC_CLR_FRC_BITS 1 26044 #define DSC2B2_SM_CTRL2_DSC_CLR_FRC_SHIFT 4 26045 26046 /* Dsc2b2 :: sm_ctrl2 :: train2_req [03:03] */ 26047 #define DSC2B2_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 26048 #define DSC2B2_SM_CTRL2_TRAIN2_REQ_ALIGN 0 26049 #define DSC2B2_SM_CTRL2_TRAIN2_REQ_BITS 1 26050 #define DSC2B2_SM_CTRL2_TRAIN2_REQ_SHIFT 3 26051 26052 /* Dsc2b2 :: sm_ctrl2 :: train1_req [02:02] */ 26053 #define DSC2B2_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 26054 #define DSC2B2_SM_CTRL2_TRAIN1_REQ_ALIGN 0 26055 #define DSC2B2_SM_CTRL2_TRAIN1_REQ_BITS 1 26056 #define DSC2B2_SM_CTRL2_TRAIN1_REQ_SHIFT 2 26057 26058 /* Dsc2b2 :: sm_ctrl2 :: soft_ack [01:01] */ 26059 #define DSC2B2_SM_CTRL2_SOFT_ACK_MASK 0x0002 26060 #define DSC2B2_SM_CTRL2_SOFT_ACK_ALIGN 0 26061 #define DSC2B2_SM_CTRL2_SOFT_ACK_BITS 1 26062 #define DSC2B2_SM_CTRL2_SOFT_ACK_SHIFT 1 26063 26064 /* Dsc2b2 :: sm_ctrl2 :: train_mode_en [00:00] */ 26065 #define DSC2B2_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 26066 #define DSC2B2_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 26067 #define DSC2B2_SM_CTRL2_TRAIN_MODE_EN_BITS 1 26068 #define DSC2B2_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 26069 26070 26071 /**************************************************************************** 26072 * Dsc2b2 :: sm_ctrl3 26073 */ 26074 /* Dsc2b2 :: sm_ctrl3 :: reserved_for_eco0 [15:15] */ 26075 #define DSC2B2_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0x8000 26076 #define DSC2B2_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 26077 #define DSC2B2_SM_CTRL3_RESERVED_FOR_ECO0_BITS 1 26078 #define DSC2B2_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 15 26079 26080 /* Dsc2b2 :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 26081 #define DSC2B2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 26082 #define DSC2B2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 26083 #define DSC2B2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 26084 #define DSC2B2_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 26085 26086 /* Dsc2b2 :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 26087 #define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 26088 #define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 26089 #define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 26090 #define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 26091 26092 /* Dsc2b2 :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 26093 #define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 26094 #define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 26095 #define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 26096 #define DSC2B2_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 26097 26098 /* Dsc2b2 :: sm_ctrl3 :: vga_gain_acq2 [07:06] */ 26099 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 26100 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 26101 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 26102 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 26103 26104 /* Dsc2b2 :: sm_ctrl3 :: vga_gain_acq1 [05:04] */ 26105 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 26106 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 26107 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 26108 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 26109 26110 /* Dsc2b2 :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 26111 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 26112 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 26113 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 26114 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 26115 26116 /* Dsc2b2 :: sm_ctrl3 :: vga_gain_acqvga [01:00] */ 26117 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 26118 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 26119 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 26120 #define DSC2B2_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 26121 26122 26123 /**************************************************************************** 26124 * Dsc2b2 :: sm_ctrl4 26125 */ 26126 /* Dsc2b2 :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 26127 #define DSC2B2_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 26128 #define DSC2B2_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 26129 #define DSC2B2_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 26130 #define DSC2B2_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 26131 26132 /* Dsc2b2 :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */ 26133 #define DSC2B2_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK 0x3000 26134 #define DSC2B2_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN 0 26135 #define DSC2B2_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS 2 26136 #define DSC2B2_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT 12 26137 26138 /* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */ 26139 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 26140 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 26141 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 26142 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 26143 26144 /* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */ 26145 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 26146 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 26147 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 26148 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 26149 26150 /* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 26151 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 26152 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 26153 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 26154 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 26155 26156 /* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */ 26157 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 26158 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 26159 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS 3 26160 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 26161 26162 /* Dsc2b2 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */ 26163 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 26164 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 26165 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS 3 26166 #define DSC2B2_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 26167 26168 26169 /**************************************************************************** 26170 * Dsc2b2 :: sm_ctrl5 26171 */ 26172 /* Dsc2b2 :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */ 26173 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 26174 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 26175 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 26176 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 26177 26178 /* Dsc2b2 :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */ 26179 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 26180 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 26181 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 26182 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 26183 26184 /* Dsc2b2 :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */ 26185 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 26186 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 26187 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 26188 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 26189 26190 /* Dsc2b2 :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */ 26191 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 26192 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 26193 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS 4 26194 #define DSC2B2_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 26195 26196 26197 /**************************************************************************** 26198 * Dsc2b2 :: sm_ctrl6 26199 */ 26200 /* Dsc2b2 :: sm_ctrl6 :: reserved_for_eco0 [15:13] */ 26201 #define DSC2B2_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xe000 26202 #define DSC2B2_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 26203 #define DSC2B2_SM_CTRL6_RESERVED_FOR_ECO0_BITS 3 26204 #define DSC2B2_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 13 26205 26206 /* Dsc2b2 :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */ 26207 #define DSC2B2_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x1800 26208 #define DSC2B2_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 26209 #define DSC2B2_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 2 26210 #define DSC2B2_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 11 26211 26212 /* Dsc2b2 :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */ 26213 #define DSC2B2_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0700 26214 #define DSC2B2_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 26215 #define DSC2B2_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 26216 #define DSC2B2_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 8 26217 26218 /* Dsc2b2 :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */ 26219 #define DSC2B2_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x00f0 26220 #define DSC2B2_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 26221 #define DSC2B2_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 26222 #define DSC2B2_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 4 26223 26224 /* Dsc2b2 :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */ 26225 #define DSC2B2_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 26226 #define DSC2B2_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 26227 #define DSC2B2_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS 4 26228 #define DSC2B2_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 26229 26230 26231 /**************************************************************************** 26232 * Dsc2b2 :: sm_ctrl7 26233 */ 26234 /* Dsc2b2 :: sm_ctrl7 :: reserved_for_eco0 [15:15] */ 26235 #define DSC2B2_SM_CTRL7_RESERVED_FOR_ECO0_MASK 0x8000 26236 #define DSC2B2_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN 0 26237 #define DSC2B2_SM_CTRL7_RESERVED_FOR_ECO0_BITS 1 26238 #define DSC2B2_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT 15 26239 26240 /* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */ 26241 #define DSC2B2_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK 0x7000 26242 #define DSC2B2_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN 0 26243 #define DSC2B2_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS 3 26244 #define DSC2B2_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT 12 26245 26246 /* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */ 26247 #define DSC2B2_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK 0x0e00 26248 #define DSC2B2_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN 0 26249 #define DSC2B2_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS 3 26250 #define DSC2B2_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT 9 26251 26252 /* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */ 26253 #define DSC2B2_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK 0x01c0 26254 #define DSC2B2_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN 0 26255 #define DSC2B2_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS 3 26256 #define DSC2B2_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT 6 26257 26258 /* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */ 26259 #define DSC2B2_SM_CTRL7_PF_CTRL_BR_INIT_MASK 0x0038 26260 #define DSC2B2_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN 0 26261 #define DSC2B2_SM_CTRL7_PF_CTRL_BR_INIT_BITS 3 26262 #define DSC2B2_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT 3 26263 26264 /* Dsc2b2 :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */ 26265 #define DSC2B2_SM_CTRL7_PF_CTRL_OS_INIT_MASK 0x0007 26266 #define DSC2B2_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN 0 26267 #define DSC2B2_SM_CTRL7_PF_CTRL_OS_INIT_BITS 3 26268 #define DSC2B2_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT 0 26269 26270 26271 /**************************************************************************** 26272 * Dsc2b2 :: sm_ctrl8 26273 */ 26274 /* Dsc2b2 :: sm_ctrl8 :: reserved_for_eco0 [15:10] */ 26275 #define DSC2B2_SM_CTRL8_RESERVED_FOR_ECO0_MASK 0xfc00 26276 #define DSC2B2_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN 0 26277 #define DSC2B2_SM_CTRL8_RESERVED_FOR_ECO0_BITS 6 26278 #define DSC2B2_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT 10 26279 26280 /* Dsc2b2 :: sm_ctrl8 :: vga_max_val [09:05] */ 26281 #define DSC2B2_SM_CTRL8_VGA_MAX_VAL_MASK 0x03e0 26282 #define DSC2B2_SM_CTRL8_VGA_MAX_VAL_ALIGN 0 26283 #define DSC2B2_SM_CTRL8_VGA_MAX_VAL_BITS 5 26284 #define DSC2B2_SM_CTRL8_VGA_MAX_VAL_SHIFT 5 26285 26286 /* Dsc2b2 :: sm_ctrl8 :: vga_min_val [04:00] */ 26287 #define DSC2B2_SM_CTRL8_VGA_MIN_VAL_MASK 0x001f 26288 #define DSC2B2_SM_CTRL8_VGA_MIN_VAL_ALIGN 0 26289 #define DSC2B2_SM_CTRL8_VGA_MIN_VAL_BITS 5 26290 #define DSC2B2_SM_CTRL8_VGA_MIN_VAL_SHIFT 0 26291 26292 26293 /**************************************************************************** 26294 * Dsc2b2 :: sm_ctrl9 26295 */ 26296 /* Dsc2b2 :: sm_ctrl9 :: reserved_for_eco0 [15:12] */ 26297 #define DSC2B2_SM_CTRL9_RESERVED_FOR_ECO0_MASK 0xf000 26298 #define DSC2B2_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN 0 26299 #define DSC2B2_SM_CTRL9_RESERVED_FOR_ECO0_BITS 4 26300 #define DSC2B2_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT 12 26301 26302 /* Dsc2b2 :: sm_ctrl9 :: dfe_max_val [11:06] */ 26303 #define DSC2B2_SM_CTRL9_DFE_MAX_VAL_MASK 0x0fc0 26304 #define DSC2B2_SM_CTRL9_DFE_MAX_VAL_ALIGN 0 26305 #define DSC2B2_SM_CTRL9_DFE_MAX_VAL_BITS 6 26306 #define DSC2B2_SM_CTRL9_DFE_MAX_VAL_SHIFT 6 26307 26308 /* Dsc2b2 :: sm_ctrl9 :: dfe_min_val [05:00] */ 26309 #define DSC2B2_SM_CTRL9_DFE_MIN_VAL_MASK 0x003f 26310 #define DSC2B2_SM_CTRL9_DFE_MIN_VAL_ALIGN 0 26311 #define DSC2B2_SM_CTRL9_DFE_MIN_VAL_BITS 6 26312 #define DSC2B2_SM_CTRL9_DFE_MIN_VAL_SHIFT 0 26313 26314 26315 /**************************************************************************** 26316 * Dsc2b2 :: sm_ctrl10 26317 */ 26318 /* Dsc2b2 :: sm_ctrl10 :: reserved_for_eco0 [15:14] */ 26319 #define DSC2B2_SM_CTRL10_RESERVED_FOR_ECO0_MASK 0xc000 26320 #define DSC2B2_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN 0 26321 #define DSC2B2_SM_CTRL10_RESERVED_FOR_ECO0_BITS 2 26322 #define DSC2B2_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT 14 26323 26324 /* Dsc2b2 :: sm_ctrl10 :: br_pf_tap_en [13:07] */ 26325 #define DSC2B2_SM_CTRL10_BR_PF_TAP_EN_MASK 0x3f80 26326 #define DSC2B2_SM_CTRL10_BR_PF_TAP_EN_ALIGN 0 26327 #define DSC2B2_SM_CTRL10_BR_PF_TAP_EN_BITS 7 26328 #define DSC2B2_SM_CTRL10_BR_PF_TAP_EN_SHIFT 7 26329 26330 /* Dsc2b2 :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */ 26331 #define DSC2B2_SM_CTRL10_OSX1_PF_TAP_EN_MASK 0x007f 26332 #define DSC2B2_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN 0 26333 #define DSC2B2_SM_CTRL10_OSX1_PF_TAP_EN_BITS 7 26334 #define DSC2B2_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT 0 26335 26336 26337 /**************************************************************************** 26338 * Dsc2b2 :: sm_ctrl11 26339 */ 26340 /* Dsc2b2 :: sm_ctrl11 :: reserved_for_eco0 [15:15] */ 26341 #define DSC2B2_SM_CTRL11_RESERVED_FOR_ECO0_MASK 0x8000 26342 #define DSC2B2_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN 0 26343 #define DSC2B2_SM_CTRL11_RESERVED_FOR_ECO0_BITS 1 26344 #define DSC2B2_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT 15 26345 26346 /* Dsc2b2 :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */ 26347 #define DSC2B2_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK 0x7c00 26348 #define DSC2B2_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN 0 26349 #define DSC2B2_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS 5 26350 #define DSC2B2_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT 10 26351 26352 /* Dsc2b2 :: sm_ctrl11 :: hysteresis_timeout [09:05] */ 26353 #define DSC2B2_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK 0x03e0 26354 #define DSC2B2_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN 0 26355 #define DSC2B2_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS 5 26356 #define DSC2B2_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT 5 26357 26358 /* Dsc2b2 :: sm_ctrl11 :: msr_postc_timeout [04:00] */ 26359 #define DSC2B2_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK 0x001f 26360 #define DSC2B2_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN 0 26361 #define DSC2B2_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS 5 26362 #define DSC2B2_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT 0 26363 26364 26365 /**************************************************************************** 26366 * Dsc2b2 :: sm_ctrl12 26367 */ 26368 /* Dsc2b2 :: sm_ctrl12 :: reserved_for_eco0 [15:14] */ 26369 #define DSC2B2_SM_CTRL12_RESERVED_FOR_ECO0_MASK 0xc000 26370 #define DSC2B2_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN 0 26371 #define DSC2B2_SM_CTRL12_RESERVED_FOR_ECO0_BITS 2 26372 #define DSC2B2_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT 14 26373 26374 /* Dsc2b2 :: sm_ctrl12 :: br_vga_lms_gain [13:12] */ 26375 #define DSC2B2_SM_CTRL12_BR_VGA_LMS_GAIN_MASK 0x3000 26376 #define DSC2B2_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN 0 26377 #define DSC2B2_SM_CTRL12_BR_VGA_LMS_GAIN_BITS 2 26378 #define DSC2B2_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT 12 26379 26380 /* Dsc2b2 :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */ 26381 #define DSC2B2_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK 0x0c00 26382 #define DSC2B2_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN 0 26383 #define DSC2B2_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS 2 26384 #define DSC2B2_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT 10 26385 26386 /* Dsc2b2 :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */ 26387 #define DSC2B2_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK 0x03e0 26388 #define DSC2B2_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN 0 26389 #define DSC2B2_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS 5 26390 #define DSC2B2_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT 5 26391 26392 /* Dsc2b2 :: sm_ctrl12 :: msr_pf_timeout [04:00] */ 26393 #define DSC2B2_SM_CTRL12_MSR_PF_TIMEOUT_MASK 0x001f 26394 #define DSC2B2_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN 0 26395 #define DSC2B2_SM_CTRL12_MSR_PF_TIMEOUT_BITS 5 26396 #define DSC2B2_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT 0 26397 26398 26399 /**************************************************************************** 26400 * Dsc2b2 :: dsc_diag_ctrl0 26401 */ 26402 /* Dsc2b2 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */ 26403 #define DSC2B2_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 26404 #define DSC2B2_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 26405 #define DSC2B2_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS 5 26406 #define DSC2B2_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 26407 26408 /* Dsc2b2 :: dsc_diag_ctrl0 :: voffset [10:07] */ 26409 #define DSC2B2_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 26410 #define DSC2B2_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 26411 #define DSC2B2_DSC_DIAG_CTRL0_VOFFSET_BITS 4 26412 #define DSC2B2_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 26413 26414 /* Dsc2b2 :: dsc_diag_ctrl0 :: hoffset [06:01] */ 26415 #define DSC2B2_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 26416 #define DSC2B2_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 26417 #define DSC2B2_DSC_DIAG_CTRL0_HOFFSET_BITS 6 26418 #define DSC2B2_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 26419 26420 /* Dsc2b2 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 26421 #define DSC2B2_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 26422 #define DSC2B2_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 26423 #define DSC2B2_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 26424 #define DSC2B2_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 26425 26426 26427 /**************************************************************************** 26428 * Dsc2b2 :: dsc_misc_ctrl0 26429 */ 26430 /* Dsc2b2 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 26431 #define DSC2B2_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 26432 #define DSC2B2_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 26433 #define DSC2B2_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 26434 #define DSC2B2_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 26435 26436 /* Dsc2b2 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 26437 #define DSC2B2_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 26438 #define DSC2B2_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 26439 #define DSC2B2_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 26440 #define DSC2B2_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 26441 26442 /* Dsc2b2 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */ 26443 #define DSC2B2_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK 0x2000 26444 #define DSC2B2_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN 0 26445 #define DSC2B2_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS 1 26446 #define DSC2B2_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT 13 26447 26448 /* Dsc2b2 :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */ 26449 #define DSC2B2_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK 0x1c00 26450 #define DSC2B2_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 26451 #define DSC2B2_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS 3 26452 #define DSC2B2_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT 10 26453 26454 /* Dsc2b2 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 26455 #define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 26456 #define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 26457 #define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 26458 #define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 26459 26460 /* Dsc2b2 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 26461 #define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 26462 #define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 26463 #define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 26464 #define DSC2B2_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 26465 26466 /* Dsc2b2 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 26467 #define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 26468 #define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 26469 #define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 26470 #define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 26471 26472 /* Dsc2b2 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 26473 #define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 26474 #define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 26475 #define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 26476 #define DSC2B2_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 26477 26478 /* Dsc2b2 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 26479 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 26480 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 26481 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 26482 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 26483 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 26484 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 26485 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 26486 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 26487 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 26488 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 26489 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 26490 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 26491 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 26492 #define DSC2B2_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 26493 26494 26495 /**************************************************************************** 26496 * Hypercore_USER_Dsc2b3 26497 */ 26498 /**************************************************************************** 26499 * Dsc2b3 :: sm_ctrl0 26500 */ 26501 /* Dsc2b3 :: sm_ctrl0 :: reserved_for_eco0 [15:15] */ 26502 #define DSC2B3_SM_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 26503 #define DSC2B3_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 26504 #define DSC2B3_SM_CTRL0_RESERVED_FOR_ECO0_BITS 1 26505 #define DSC2B3_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 26506 26507 /* Dsc2b3 :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */ 26508 #define DSC2B3_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK 0x4000 26509 #define DSC2B3_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN 0 26510 #define DSC2B3_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS 1 26511 #define DSC2B3_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT 14 26512 26513 /* Dsc2b3 :: sm_ctrl0 :: bypass_br_vga [13:13] */ 26514 #define DSC2B3_SM_CTRL0_BYPASS_BR_VGA_MASK 0x2000 26515 #define DSC2B3_SM_CTRL0_BYPASS_BR_VGA_ALIGN 0 26516 #define DSC2B3_SM_CTRL0_BYPASS_BR_VGA_BITS 1 26517 #define DSC2B3_SM_CTRL0_BYPASS_BR_VGA_SHIFT 13 26518 26519 /* Dsc2b3 :: sm_ctrl0 :: postc_metric_ctrl [12:12] */ 26520 #define DSC2B3_SM_CTRL0_POSTC_METRIC_CTRL_MASK 0x1000 26521 #define DSC2B3_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN 0 26522 #define DSC2B3_SM_CTRL0_POSTC_METRIC_CTRL_BITS 1 26523 #define DSC2B3_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT 12 26524 26525 /* Dsc2b3 :: sm_ctrl0 :: hysteresis_en [11:11] */ 26526 #define DSC2B3_SM_CTRL0_HYSTERESIS_EN_MASK 0x0800 26527 #define DSC2B3_SM_CTRL0_HYSTERESIS_EN_ALIGN 0 26528 #define DSC2B3_SM_CTRL0_HYSTERESIS_EN_BITS 1 26529 #define DSC2B3_SM_CTRL0_HYSTERESIS_EN_SHIFT 11 26530 26531 /* Dsc2b3 :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */ 26532 #define DSC2B3_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK 0x0400 26533 #define DSC2B3_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN 0 26534 #define DSC2B3_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS 1 26535 #define DSC2B3_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT 10 26536 26537 /* Dsc2b3 :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */ 26538 #define DSC2B3_SM_CTRL0_BYPASS_BR_PF_CAL_MASK 0x0200 26539 #define DSC2B3_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN 0 26540 #define DSC2B3_SM_CTRL0_BYPASS_BR_PF_CAL_BITS 1 26541 #define DSC2B3_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT 9 26542 26543 /* Dsc2b3 :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */ 26544 #define DSC2B3_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK 0x0100 26545 #define DSC2B3_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN 0 26546 #define DSC2B3_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS 1 26547 #define DSC2B3_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT 8 26548 26549 /* Dsc2b3 :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */ 26550 #define DSC2B3_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK 0x0080 26551 #define DSC2B3_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN 0 26552 #define DSC2B3_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS 1 26553 #define DSC2B3_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT 7 26554 26555 /* Dsc2b3 :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */ 26556 #define DSC2B3_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK 0x0040 26557 #define DSC2B3_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN 0 26558 #define DSC2B3_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS 1 26559 #define DSC2B3_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT 6 26560 26561 /* Dsc2b3 :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */ 26562 #define DSC2B3_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK 0x0020 26563 #define DSC2B3_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN 0 26564 #define DSC2B3_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS 1 26565 #define DSC2B3_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT 5 26566 26567 /* Dsc2b3 :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */ 26568 #define DSC2B3_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK 0x0010 26569 #define DSC2B3_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN 0 26570 #define DSC2B3_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS 1 26571 #define DSC2B3_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT 4 26572 26573 /* Dsc2b3 :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */ 26574 #define DSC2B3_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK 0x0008 26575 #define DSC2B3_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN 0 26576 #define DSC2B3_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS 1 26577 #define DSC2B3_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT 3 26578 26579 /* Dsc2b3 :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */ 26580 #define DSC2B3_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK 0x0004 26581 #define DSC2B3_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN 0 26582 #define DSC2B3_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS 1 26583 #define DSC2B3_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT 2 26584 26585 /* Dsc2b3 :: sm_ctrl0 :: restart_tuning [01:01] */ 26586 #define DSC2B3_SM_CTRL0_RESTART_TUNING_MASK 0x0002 26587 #define DSC2B3_SM_CTRL0_RESTART_TUNING_ALIGN 0 26588 #define DSC2B3_SM_CTRL0_RESTART_TUNING_BITS 1 26589 #define DSC2B3_SM_CTRL0_RESTART_TUNING_SHIFT 1 26590 26591 /* Dsc2b3 :: sm_ctrl0 :: tuning_sm_en [00:00] */ 26592 #define DSC2B3_SM_CTRL0_TUNING_SM_EN_MASK 0x0001 26593 #define DSC2B3_SM_CTRL0_TUNING_SM_EN_ALIGN 0 26594 #define DSC2B3_SM_CTRL0_TUNING_SM_EN_BITS 1 26595 #define DSC2B3_SM_CTRL0_TUNING_SM_EN_SHIFT 0 26596 26597 26598 /**************************************************************************** 26599 * Dsc2b3 :: sm_ctrl1 26600 */ 26601 /* Dsc2b3 :: sm_ctrl1 :: fast_timer [15:15] */ 26602 #define DSC2B3_SM_CTRL1_FAST_TIMER_MASK 0x8000 26603 #define DSC2B3_SM_CTRL1_FAST_TIMER_ALIGN 0 26604 #define DSC2B3_SM_CTRL1_FAST_TIMER_BITS 1 26605 #define DSC2B3_SM_CTRL1_FAST_TIMER_SHIFT 15 26606 26607 /* Dsc2b3 :: sm_ctrl1 :: acq2_timeout [14:10] */ 26608 #define DSC2B3_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 26609 #define DSC2B3_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 26610 #define DSC2B3_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 26611 #define DSC2B3_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 26612 26613 /* Dsc2b3 :: sm_ctrl1 :: acq1_timeout [09:05] */ 26614 #define DSC2B3_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 26615 #define DSC2B3_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 26616 #define DSC2B3_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 26617 #define DSC2B3_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 26618 26619 /* Dsc2b3 :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 26620 #define DSC2B3_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 26621 #define DSC2B3_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 26622 #define DSC2B3_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 26623 #define DSC2B3_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 26624 26625 26626 /**************************************************************************** 26627 * Dsc2b3 :: sm_ctrl2 26628 */ 26629 /* Dsc2b3 :: sm_ctrl2 :: acqvga_timeout [15:11] */ 26630 #define DSC2B3_SM_CTRL2_ACQVGA_TIMEOUT_MASK 0xf800 26631 #define DSC2B3_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN 0 26632 #define DSC2B3_SM_CTRL2_ACQVGA_TIMEOUT_BITS 5 26633 #define DSC2B3_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT 11 26634 26635 /* Dsc2b3 :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */ 26636 #define DSC2B3_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK 0x0400 26637 #define DSC2B3_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN 0 26638 #define DSC2B3_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS 1 26639 #define DSC2B3_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT 10 26640 26641 /* Dsc2b3 :: sm_ctrl2 :: vga_frzval [09:09] */ 26642 #define DSC2B3_SM_CTRL2_VGA_FRZVAL_MASK 0x0200 26643 #define DSC2B3_SM_CTRL2_VGA_FRZVAL_ALIGN 0 26644 #define DSC2B3_SM_CTRL2_VGA_FRZVAL_BITS 1 26645 #define DSC2B3_SM_CTRL2_VGA_FRZVAL_SHIFT 9 26646 26647 /* Dsc2b3 :: sm_ctrl2 :: vga_frcfrz [08:08] */ 26648 #define DSC2B3_SM_CTRL2_VGA_FRCFRZ_MASK 0x0100 26649 #define DSC2B3_SM_CTRL2_VGA_FRCFRZ_ALIGN 0 26650 #define DSC2B3_SM_CTRL2_VGA_FRCFRZ_BITS 1 26651 #define DSC2B3_SM_CTRL2_VGA_FRCFRZ_SHIFT 8 26652 26653 /* Dsc2b3 :: sm_ctrl2 :: dfe_frzval [07:07] */ 26654 #define DSC2B3_SM_CTRL2_DFE_FRZVAL_MASK 0x0080 26655 #define DSC2B3_SM_CTRL2_DFE_FRZVAL_ALIGN 0 26656 #define DSC2B3_SM_CTRL2_DFE_FRZVAL_BITS 1 26657 #define DSC2B3_SM_CTRL2_DFE_FRZVAL_SHIFT 7 26658 26659 /* Dsc2b3 :: sm_ctrl2 :: dfe_frcfrz [06:06] */ 26660 #define DSC2B3_SM_CTRL2_DFE_FRCFRZ_MASK 0x0040 26661 #define DSC2B3_SM_CTRL2_DFE_FRCFRZ_ALIGN 0 26662 #define DSC2B3_SM_CTRL2_DFE_FRCFRZ_BITS 1 26663 #define DSC2B3_SM_CTRL2_DFE_FRCFRZ_SHIFT 6 26664 26665 /* Dsc2b3 :: sm_ctrl2 :: dsc_clr_val [05:05] */ 26666 #define DSC2B3_SM_CTRL2_DSC_CLR_VAL_MASK 0x0020 26667 #define DSC2B3_SM_CTRL2_DSC_CLR_VAL_ALIGN 0 26668 #define DSC2B3_SM_CTRL2_DSC_CLR_VAL_BITS 1 26669 #define DSC2B3_SM_CTRL2_DSC_CLR_VAL_SHIFT 5 26670 26671 /* Dsc2b3 :: sm_ctrl2 :: dsc_clr_frc [04:04] */ 26672 #define DSC2B3_SM_CTRL2_DSC_CLR_FRC_MASK 0x0010 26673 #define DSC2B3_SM_CTRL2_DSC_CLR_FRC_ALIGN 0 26674 #define DSC2B3_SM_CTRL2_DSC_CLR_FRC_BITS 1 26675 #define DSC2B3_SM_CTRL2_DSC_CLR_FRC_SHIFT 4 26676 26677 /* Dsc2b3 :: sm_ctrl2 :: train2_req [03:03] */ 26678 #define DSC2B3_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 26679 #define DSC2B3_SM_CTRL2_TRAIN2_REQ_ALIGN 0 26680 #define DSC2B3_SM_CTRL2_TRAIN2_REQ_BITS 1 26681 #define DSC2B3_SM_CTRL2_TRAIN2_REQ_SHIFT 3 26682 26683 /* Dsc2b3 :: sm_ctrl2 :: train1_req [02:02] */ 26684 #define DSC2B3_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 26685 #define DSC2B3_SM_CTRL2_TRAIN1_REQ_ALIGN 0 26686 #define DSC2B3_SM_CTRL2_TRAIN1_REQ_BITS 1 26687 #define DSC2B3_SM_CTRL2_TRAIN1_REQ_SHIFT 2 26688 26689 /* Dsc2b3 :: sm_ctrl2 :: soft_ack [01:01] */ 26690 #define DSC2B3_SM_CTRL2_SOFT_ACK_MASK 0x0002 26691 #define DSC2B3_SM_CTRL2_SOFT_ACK_ALIGN 0 26692 #define DSC2B3_SM_CTRL2_SOFT_ACK_BITS 1 26693 #define DSC2B3_SM_CTRL2_SOFT_ACK_SHIFT 1 26694 26695 /* Dsc2b3 :: sm_ctrl2 :: train_mode_en [00:00] */ 26696 #define DSC2B3_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 26697 #define DSC2B3_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 26698 #define DSC2B3_SM_CTRL2_TRAIN_MODE_EN_BITS 1 26699 #define DSC2B3_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 26700 26701 26702 /**************************************************************************** 26703 * Dsc2b3 :: sm_ctrl3 26704 */ 26705 /* Dsc2b3 :: sm_ctrl3 :: reserved_for_eco0 [15:15] */ 26706 #define DSC2B3_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0x8000 26707 #define DSC2B3_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 26708 #define DSC2B3_SM_CTRL3_RESERVED_FOR_ECO0_BITS 1 26709 #define DSC2B3_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 15 26710 26711 /* Dsc2b3 :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 26712 #define DSC2B3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 26713 #define DSC2B3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 26714 #define DSC2B3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 26715 #define DSC2B3_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 26716 26717 /* Dsc2b3 :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 26718 #define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 26719 #define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 26720 #define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 26721 #define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 26722 26723 /* Dsc2b3 :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 26724 #define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 26725 #define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 26726 #define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 26727 #define DSC2B3_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 26728 26729 /* Dsc2b3 :: sm_ctrl3 :: vga_gain_acq2 [07:06] */ 26730 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 26731 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 26732 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 26733 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 26734 26735 /* Dsc2b3 :: sm_ctrl3 :: vga_gain_acq1 [05:04] */ 26736 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 26737 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 26738 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 26739 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 26740 26741 /* Dsc2b3 :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 26742 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 26743 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 26744 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 26745 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 26746 26747 /* Dsc2b3 :: sm_ctrl3 :: vga_gain_acqvga [01:00] */ 26748 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 26749 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 26750 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 26751 #define DSC2B3_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 26752 26753 26754 /**************************************************************************** 26755 * Dsc2b3 :: sm_ctrl4 26756 */ 26757 /* Dsc2b3 :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 26758 #define DSC2B3_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 26759 #define DSC2B3_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 26760 #define DSC2B3_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 26761 #define DSC2B3_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 26762 26763 /* Dsc2b3 :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */ 26764 #define DSC2B3_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK 0x3000 26765 #define DSC2B3_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN 0 26766 #define DSC2B3_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS 2 26767 #define DSC2B3_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT 12 26768 26769 /* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */ 26770 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 26771 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 26772 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 26773 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 26774 26775 /* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */ 26776 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 26777 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 26778 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 26779 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 26780 26781 /* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 26782 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 26783 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 26784 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 26785 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 26786 26787 /* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */ 26788 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 26789 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 26790 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS 3 26791 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 26792 26793 /* Dsc2b3 :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */ 26794 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 26795 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 26796 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS 3 26797 #define DSC2B3_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 26798 26799 26800 /**************************************************************************** 26801 * Dsc2b3 :: sm_ctrl5 26802 */ 26803 /* Dsc2b3 :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */ 26804 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 26805 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 26806 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 26807 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 26808 26809 /* Dsc2b3 :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */ 26810 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 26811 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 26812 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 26813 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 26814 26815 /* Dsc2b3 :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */ 26816 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 26817 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 26818 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 26819 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 26820 26821 /* Dsc2b3 :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */ 26822 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 26823 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 26824 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS 4 26825 #define DSC2B3_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 26826 26827 26828 /**************************************************************************** 26829 * Dsc2b3 :: sm_ctrl6 26830 */ 26831 /* Dsc2b3 :: sm_ctrl6 :: reserved_for_eco0 [15:13] */ 26832 #define DSC2B3_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xe000 26833 #define DSC2B3_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 26834 #define DSC2B3_SM_CTRL6_RESERVED_FOR_ECO0_BITS 3 26835 #define DSC2B3_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 13 26836 26837 /* Dsc2b3 :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */ 26838 #define DSC2B3_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x1800 26839 #define DSC2B3_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 26840 #define DSC2B3_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 2 26841 #define DSC2B3_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 11 26842 26843 /* Dsc2b3 :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */ 26844 #define DSC2B3_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0700 26845 #define DSC2B3_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 26846 #define DSC2B3_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 26847 #define DSC2B3_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 8 26848 26849 /* Dsc2b3 :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */ 26850 #define DSC2B3_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x00f0 26851 #define DSC2B3_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 26852 #define DSC2B3_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 26853 #define DSC2B3_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 4 26854 26855 /* Dsc2b3 :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */ 26856 #define DSC2B3_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 26857 #define DSC2B3_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 26858 #define DSC2B3_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS 4 26859 #define DSC2B3_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 26860 26861 26862 /**************************************************************************** 26863 * Dsc2b3 :: sm_ctrl7 26864 */ 26865 /* Dsc2b3 :: sm_ctrl7 :: reserved_for_eco0 [15:15] */ 26866 #define DSC2B3_SM_CTRL7_RESERVED_FOR_ECO0_MASK 0x8000 26867 #define DSC2B3_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN 0 26868 #define DSC2B3_SM_CTRL7_RESERVED_FOR_ECO0_BITS 1 26869 #define DSC2B3_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT 15 26870 26871 /* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */ 26872 #define DSC2B3_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK 0x7000 26873 #define DSC2B3_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN 0 26874 #define DSC2B3_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS 3 26875 #define DSC2B3_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT 12 26876 26877 /* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */ 26878 #define DSC2B3_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK 0x0e00 26879 #define DSC2B3_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN 0 26880 #define DSC2B3_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS 3 26881 #define DSC2B3_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT 9 26882 26883 /* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */ 26884 #define DSC2B3_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK 0x01c0 26885 #define DSC2B3_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN 0 26886 #define DSC2B3_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS 3 26887 #define DSC2B3_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT 6 26888 26889 /* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */ 26890 #define DSC2B3_SM_CTRL7_PF_CTRL_BR_INIT_MASK 0x0038 26891 #define DSC2B3_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN 0 26892 #define DSC2B3_SM_CTRL7_PF_CTRL_BR_INIT_BITS 3 26893 #define DSC2B3_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT 3 26894 26895 /* Dsc2b3 :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */ 26896 #define DSC2B3_SM_CTRL7_PF_CTRL_OS_INIT_MASK 0x0007 26897 #define DSC2B3_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN 0 26898 #define DSC2B3_SM_CTRL7_PF_CTRL_OS_INIT_BITS 3 26899 #define DSC2B3_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT 0 26900 26901 26902 /**************************************************************************** 26903 * Dsc2b3 :: sm_ctrl8 26904 */ 26905 /* Dsc2b3 :: sm_ctrl8 :: reserved_for_eco0 [15:10] */ 26906 #define DSC2B3_SM_CTRL8_RESERVED_FOR_ECO0_MASK 0xfc00 26907 #define DSC2B3_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN 0 26908 #define DSC2B3_SM_CTRL8_RESERVED_FOR_ECO0_BITS 6 26909 #define DSC2B3_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT 10 26910 26911 /* Dsc2b3 :: sm_ctrl8 :: vga_max_val [09:05] */ 26912 #define DSC2B3_SM_CTRL8_VGA_MAX_VAL_MASK 0x03e0 26913 #define DSC2B3_SM_CTRL8_VGA_MAX_VAL_ALIGN 0 26914 #define DSC2B3_SM_CTRL8_VGA_MAX_VAL_BITS 5 26915 #define DSC2B3_SM_CTRL8_VGA_MAX_VAL_SHIFT 5 26916 26917 /* Dsc2b3 :: sm_ctrl8 :: vga_min_val [04:00] */ 26918 #define DSC2B3_SM_CTRL8_VGA_MIN_VAL_MASK 0x001f 26919 #define DSC2B3_SM_CTRL8_VGA_MIN_VAL_ALIGN 0 26920 #define DSC2B3_SM_CTRL8_VGA_MIN_VAL_BITS 5 26921 #define DSC2B3_SM_CTRL8_VGA_MIN_VAL_SHIFT 0 26922 26923 26924 /**************************************************************************** 26925 * Dsc2b3 :: sm_ctrl9 26926 */ 26927 /* Dsc2b3 :: sm_ctrl9 :: reserved_for_eco0 [15:12] */ 26928 #define DSC2B3_SM_CTRL9_RESERVED_FOR_ECO0_MASK 0xf000 26929 #define DSC2B3_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN 0 26930 #define DSC2B3_SM_CTRL9_RESERVED_FOR_ECO0_BITS 4 26931 #define DSC2B3_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT 12 26932 26933 /* Dsc2b3 :: sm_ctrl9 :: dfe_max_val [11:06] */ 26934 #define DSC2B3_SM_CTRL9_DFE_MAX_VAL_MASK 0x0fc0 26935 #define DSC2B3_SM_CTRL9_DFE_MAX_VAL_ALIGN 0 26936 #define DSC2B3_SM_CTRL9_DFE_MAX_VAL_BITS 6 26937 #define DSC2B3_SM_CTRL9_DFE_MAX_VAL_SHIFT 6 26938 26939 /* Dsc2b3 :: sm_ctrl9 :: dfe_min_val [05:00] */ 26940 #define DSC2B3_SM_CTRL9_DFE_MIN_VAL_MASK 0x003f 26941 #define DSC2B3_SM_CTRL9_DFE_MIN_VAL_ALIGN 0 26942 #define DSC2B3_SM_CTRL9_DFE_MIN_VAL_BITS 6 26943 #define DSC2B3_SM_CTRL9_DFE_MIN_VAL_SHIFT 0 26944 26945 26946 /**************************************************************************** 26947 * Dsc2b3 :: sm_ctrl10 26948 */ 26949 /* Dsc2b3 :: sm_ctrl10 :: reserved_for_eco0 [15:14] */ 26950 #define DSC2B3_SM_CTRL10_RESERVED_FOR_ECO0_MASK 0xc000 26951 #define DSC2B3_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN 0 26952 #define DSC2B3_SM_CTRL10_RESERVED_FOR_ECO0_BITS 2 26953 #define DSC2B3_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT 14 26954 26955 /* Dsc2b3 :: sm_ctrl10 :: br_pf_tap_en [13:07] */ 26956 #define DSC2B3_SM_CTRL10_BR_PF_TAP_EN_MASK 0x3f80 26957 #define DSC2B3_SM_CTRL10_BR_PF_TAP_EN_ALIGN 0 26958 #define DSC2B3_SM_CTRL10_BR_PF_TAP_EN_BITS 7 26959 #define DSC2B3_SM_CTRL10_BR_PF_TAP_EN_SHIFT 7 26960 26961 /* Dsc2b3 :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */ 26962 #define DSC2B3_SM_CTRL10_OSX1_PF_TAP_EN_MASK 0x007f 26963 #define DSC2B3_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN 0 26964 #define DSC2B3_SM_CTRL10_OSX1_PF_TAP_EN_BITS 7 26965 #define DSC2B3_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT 0 26966 26967 26968 /**************************************************************************** 26969 * Dsc2b3 :: sm_ctrl11 26970 */ 26971 /* Dsc2b3 :: sm_ctrl11 :: reserved_for_eco0 [15:15] */ 26972 #define DSC2B3_SM_CTRL11_RESERVED_FOR_ECO0_MASK 0x8000 26973 #define DSC2B3_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN 0 26974 #define DSC2B3_SM_CTRL11_RESERVED_FOR_ECO0_BITS 1 26975 #define DSC2B3_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT 15 26976 26977 /* Dsc2b3 :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */ 26978 #define DSC2B3_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK 0x7c00 26979 #define DSC2B3_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN 0 26980 #define DSC2B3_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS 5 26981 #define DSC2B3_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT 10 26982 26983 /* Dsc2b3 :: sm_ctrl11 :: hysteresis_timeout [09:05] */ 26984 #define DSC2B3_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK 0x03e0 26985 #define DSC2B3_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN 0 26986 #define DSC2B3_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS 5 26987 #define DSC2B3_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT 5 26988 26989 /* Dsc2b3 :: sm_ctrl11 :: msr_postc_timeout [04:00] */ 26990 #define DSC2B3_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK 0x001f 26991 #define DSC2B3_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN 0 26992 #define DSC2B3_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS 5 26993 #define DSC2B3_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT 0 26994 26995 26996 /**************************************************************************** 26997 * Dsc2b3 :: sm_ctrl12 26998 */ 26999 /* Dsc2b3 :: sm_ctrl12 :: reserved_for_eco0 [15:14] */ 27000 #define DSC2B3_SM_CTRL12_RESERVED_FOR_ECO0_MASK 0xc000 27001 #define DSC2B3_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN 0 27002 #define DSC2B3_SM_CTRL12_RESERVED_FOR_ECO0_BITS 2 27003 #define DSC2B3_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT 14 27004 27005 /* Dsc2b3 :: sm_ctrl12 :: br_vga_lms_gain [13:12] */ 27006 #define DSC2B3_SM_CTRL12_BR_VGA_LMS_GAIN_MASK 0x3000 27007 #define DSC2B3_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN 0 27008 #define DSC2B3_SM_CTRL12_BR_VGA_LMS_GAIN_BITS 2 27009 #define DSC2B3_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT 12 27010 27011 /* Dsc2b3 :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */ 27012 #define DSC2B3_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK 0x0c00 27013 #define DSC2B3_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN 0 27014 #define DSC2B3_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS 2 27015 #define DSC2B3_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT 10 27016 27017 /* Dsc2b3 :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */ 27018 #define DSC2B3_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK 0x03e0 27019 #define DSC2B3_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN 0 27020 #define DSC2B3_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS 5 27021 #define DSC2B3_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT 5 27022 27023 /* Dsc2b3 :: sm_ctrl12 :: msr_pf_timeout [04:00] */ 27024 #define DSC2B3_SM_CTRL12_MSR_PF_TIMEOUT_MASK 0x001f 27025 #define DSC2B3_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN 0 27026 #define DSC2B3_SM_CTRL12_MSR_PF_TIMEOUT_BITS 5 27027 #define DSC2B3_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT 0 27028 27029 27030 /**************************************************************************** 27031 * Dsc2b3 :: dsc_diag_ctrl0 27032 */ 27033 /* Dsc2b3 :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */ 27034 #define DSC2B3_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 27035 #define DSC2B3_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 27036 #define DSC2B3_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS 5 27037 #define DSC2B3_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 27038 27039 /* Dsc2b3 :: dsc_diag_ctrl0 :: voffset [10:07] */ 27040 #define DSC2B3_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 27041 #define DSC2B3_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 27042 #define DSC2B3_DSC_DIAG_CTRL0_VOFFSET_BITS 4 27043 #define DSC2B3_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 27044 27045 /* Dsc2b3 :: dsc_diag_ctrl0 :: hoffset [06:01] */ 27046 #define DSC2B3_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 27047 #define DSC2B3_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 27048 #define DSC2B3_DSC_DIAG_CTRL0_HOFFSET_BITS 6 27049 #define DSC2B3_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 27050 27051 /* Dsc2b3 :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 27052 #define DSC2B3_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 27053 #define DSC2B3_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 27054 #define DSC2B3_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 27055 #define DSC2B3_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 27056 27057 27058 /**************************************************************************** 27059 * Dsc2b3 :: dsc_misc_ctrl0 27060 */ 27061 /* Dsc2b3 :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 27062 #define DSC2B3_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 27063 #define DSC2B3_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 27064 #define DSC2B3_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 27065 #define DSC2B3_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 27066 27067 /* Dsc2b3 :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 27068 #define DSC2B3_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 27069 #define DSC2B3_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 27070 #define DSC2B3_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 27071 #define DSC2B3_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 27072 27073 /* Dsc2b3 :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */ 27074 #define DSC2B3_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK 0x2000 27075 #define DSC2B3_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN 0 27076 #define DSC2B3_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS 1 27077 #define DSC2B3_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT 13 27078 27079 /* Dsc2b3 :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */ 27080 #define DSC2B3_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK 0x1c00 27081 #define DSC2B3_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 27082 #define DSC2B3_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS 3 27083 #define DSC2B3_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT 10 27084 27085 /* Dsc2b3 :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 27086 #define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 27087 #define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 27088 #define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 27089 #define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 27090 27091 /* Dsc2b3 :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 27092 #define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 27093 #define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 27094 #define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 27095 #define DSC2B3_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 27096 27097 /* Dsc2b3 :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 27098 #define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 27099 #define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 27100 #define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 27101 #define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 27102 27103 /* Dsc2b3 :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 27104 #define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 27105 #define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 27106 #define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 27107 #define DSC2B3_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 27108 27109 /* Dsc2b3 :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 27110 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 27111 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 27112 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 27113 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 27114 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 27115 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 27116 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 27117 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 27118 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 27119 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 27120 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 27121 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 27122 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 27123 #define DSC2B3_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 27124 27125 27126 /**************************************************************************** 27127 * Hypercore_USER_Dsc2bB 27128 */ 27129 /**************************************************************************** 27130 * Dsc2bB :: sm_ctrl0 27131 */ 27132 /* Dsc2bB :: sm_ctrl0 :: reserved_for_eco0 [15:15] */ 27133 #define DSC2BB_SM_CTRL0_RESERVED_FOR_ECO0_MASK 0x8000 27134 #define DSC2BB_SM_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 27135 #define DSC2BB_SM_CTRL0_RESERVED_FOR_ECO0_BITS 1 27136 #define DSC2BB_SM_CTRL0_RESERVED_FOR_ECO0_SHIFT 15 27137 27138 /* Dsc2bB :: sm_ctrl0 :: bypass_tx_postc_cal [14:14] */ 27139 #define DSC2BB_SM_CTRL0_BYPASS_TX_POSTC_CAL_MASK 0x4000 27140 #define DSC2BB_SM_CTRL0_BYPASS_TX_POSTC_CAL_ALIGN 0 27141 #define DSC2BB_SM_CTRL0_BYPASS_TX_POSTC_CAL_BITS 1 27142 #define DSC2BB_SM_CTRL0_BYPASS_TX_POSTC_CAL_SHIFT 14 27143 27144 /* Dsc2bB :: sm_ctrl0 :: bypass_br_vga [13:13] */ 27145 #define DSC2BB_SM_CTRL0_BYPASS_BR_VGA_MASK 0x2000 27146 #define DSC2BB_SM_CTRL0_BYPASS_BR_VGA_ALIGN 0 27147 #define DSC2BB_SM_CTRL0_BYPASS_BR_VGA_BITS 1 27148 #define DSC2BB_SM_CTRL0_BYPASS_BR_VGA_SHIFT 13 27149 27150 /* Dsc2bB :: sm_ctrl0 :: postc_metric_ctrl [12:12] */ 27151 #define DSC2BB_SM_CTRL0_POSTC_METRIC_CTRL_MASK 0x1000 27152 #define DSC2BB_SM_CTRL0_POSTC_METRIC_CTRL_ALIGN 0 27153 #define DSC2BB_SM_CTRL0_POSTC_METRIC_CTRL_BITS 1 27154 #define DSC2BB_SM_CTRL0_POSTC_METRIC_CTRL_SHIFT 12 27155 27156 /* Dsc2bB :: sm_ctrl0 :: hysteresis_en [11:11] */ 27157 #define DSC2BB_SM_CTRL0_HYSTERESIS_EN_MASK 0x0800 27158 #define DSC2BB_SM_CTRL0_HYSTERESIS_EN_ALIGN 0 27159 #define DSC2BB_SM_CTRL0_HYSTERESIS_EN_BITS 1 27160 #define DSC2BB_SM_CTRL0_HYSTERESIS_EN_SHIFT 11 27161 27162 /* Dsc2bB :: sm_ctrl0 :: slicer_cal_linear_srch [10:10] */ 27163 #define DSC2BB_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_MASK 0x0400 27164 #define DSC2BB_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_ALIGN 0 27165 #define DSC2BB_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_BITS 1 27166 #define DSC2BB_SM_CTRL0_SLICER_CAL_LINEAR_SRCH_SHIFT 10 27167 27168 /* Dsc2bB :: sm_ctrl0 :: bypass_br_pf_cal [09:09] */ 27169 #define DSC2BB_SM_CTRL0_BYPASS_BR_PF_CAL_MASK 0x0200 27170 #define DSC2BB_SM_CTRL0_BYPASS_BR_PF_CAL_ALIGN 0 27171 #define DSC2BB_SM_CTRL0_BYPASS_BR_PF_CAL_BITS 1 27172 #define DSC2BB_SM_CTRL0_BYPASS_BR_PF_CAL_SHIFT 9 27173 27174 /* Dsc2bB :: sm_ctrl0 :: bypass_osx2_pf_cal [08:08] */ 27175 #define DSC2BB_SM_CTRL0_BYPASS_OSX2_PF_CAL_MASK 0x0100 27176 #define DSC2BB_SM_CTRL0_BYPASS_OSX2_PF_CAL_ALIGN 0 27177 #define DSC2BB_SM_CTRL0_BYPASS_OSX2_PF_CAL_BITS 1 27178 #define DSC2BB_SM_CTRL0_BYPASS_OSX2_PF_CAL_SHIFT 8 27179 27180 /* Dsc2bB :: sm_ctrl0 :: bypass_osx1_pf_cal [07:07] */ 27181 #define DSC2BB_SM_CTRL0_BYPASS_OSX1_PF_CAL_MASK 0x0080 27182 #define DSC2BB_SM_CTRL0_BYPASS_OSX1_PF_CAL_ALIGN 0 27183 #define DSC2BB_SM_CTRL0_BYPASS_OSX1_PF_CAL_BITS 1 27184 #define DSC2BB_SM_CTRL0_BYPASS_OSX1_PF_CAL_SHIFT 7 27185 27186 /* Dsc2bB :: sm_ctrl0 :: bypass_data_slicer_recal [06:06] */ 27187 #define DSC2BB_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_MASK 0x0040 27188 #define DSC2BB_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_ALIGN 0 27189 #define DSC2BB_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_BITS 1 27190 #define DSC2BB_SM_CTRL0_BYPASS_DATA_SLICER_RECAL_SHIFT 6 27191 27192 /* Dsc2bB :: sm_ctrl0 :: bypass_osx45_slicer_cal [05:05] */ 27193 #define DSC2BB_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_MASK 0x0020 27194 #define DSC2BB_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_ALIGN 0 27195 #define DSC2BB_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_BITS 1 27196 #define DSC2BB_SM_CTRL0_BYPASS_OSX45_SLICER_CAL_SHIFT 5 27197 27198 /* Dsc2bB :: sm_ctrl0 :: bypass_phase_slicer_cal [04:04] */ 27199 #define DSC2BB_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_MASK 0x0010 27200 #define DSC2BB_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_ALIGN 0 27201 #define DSC2BB_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_BITS 1 27202 #define DSC2BB_SM_CTRL0_BYPASS_PHASE_SLICER_CAL_SHIFT 4 27203 27204 /* Dsc2bB :: sm_ctrl0 :: bypass_br_data_slicer_cal [03:03] */ 27205 #define DSC2BB_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_MASK 0x0008 27206 #define DSC2BB_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_ALIGN 0 27207 #define DSC2BB_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_BITS 1 27208 #define DSC2BB_SM_CTRL0_BYPASS_BR_DATA_SLICER_CAL_SHIFT 3 27209 27210 /* Dsc2bB :: sm_ctrl0 :: bypass_os_data_slicer_cal [02:02] */ 27211 #define DSC2BB_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_MASK 0x0004 27212 #define DSC2BB_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_ALIGN 0 27213 #define DSC2BB_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_BITS 1 27214 #define DSC2BB_SM_CTRL0_BYPASS_OS_DATA_SLICER_CAL_SHIFT 2 27215 27216 /* Dsc2bB :: sm_ctrl0 :: restart_tuning [01:01] */ 27217 #define DSC2BB_SM_CTRL0_RESTART_TUNING_MASK 0x0002 27218 #define DSC2BB_SM_CTRL0_RESTART_TUNING_ALIGN 0 27219 #define DSC2BB_SM_CTRL0_RESTART_TUNING_BITS 1 27220 #define DSC2BB_SM_CTRL0_RESTART_TUNING_SHIFT 1 27221 27222 /* Dsc2bB :: sm_ctrl0 :: tuning_sm_en [00:00] */ 27223 #define DSC2BB_SM_CTRL0_TUNING_SM_EN_MASK 0x0001 27224 #define DSC2BB_SM_CTRL0_TUNING_SM_EN_ALIGN 0 27225 #define DSC2BB_SM_CTRL0_TUNING_SM_EN_BITS 1 27226 #define DSC2BB_SM_CTRL0_TUNING_SM_EN_SHIFT 0 27227 27228 27229 /**************************************************************************** 27230 * Dsc2bB :: sm_ctrl1 27231 */ 27232 /* Dsc2bB :: sm_ctrl1 :: fast_timer [15:15] */ 27233 #define DSC2BB_SM_CTRL1_FAST_TIMER_MASK 0x8000 27234 #define DSC2BB_SM_CTRL1_FAST_TIMER_ALIGN 0 27235 #define DSC2BB_SM_CTRL1_FAST_TIMER_BITS 1 27236 #define DSC2BB_SM_CTRL1_FAST_TIMER_SHIFT 15 27237 27238 /* Dsc2bB :: sm_ctrl1 :: acq2_timeout [14:10] */ 27239 #define DSC2BB_SM_CTRL1_ACQ2_TIMEOUT_MASK 0x7c00 27240 #define DSC2BB_SM_CTRL1_ACQ2_TIMEOUT_ALIGN 0 27241 #define DSC2BB_SM_CTRL1_ACQ2_TIMEOUT_BITS 5 27242 #define DSC2BB_SM_CTRL1_ACQ2_TIMEOUT_SHIFT 10 27243 27244 /* Dsc2bB :: sm_ctrl1 :: acq1_timeout [09:05] */ 27245 #define DSC2BB_SM_CTRL1_ACQ1_TIMEOUT_MASK 0x03e0 27246 #define DSC2BB_SM_CTRL1_ACQ1_TIMEOUT_ALIGN 0 27247 #define DSC2BB_SM_CTRL1_ACQ1_TIMEOUT_BITS 5 27248 #define DSC2BB_SM_CTRL1_ACQ1_TIMEOUT_SHIFT 5 27249 27250 /* Dsc2bB :: sm_ctrl1 :: acqcdr_timeout [04:00] */ 27251 #define DSC2BB_SM_CTRL1_ACQCDR_TIMEOUT_MASK 0x001f 27252 #define DSC2BB_SM_CTRL1_ACQCDR_TIMEOUT_ALIGN 0 27253 #define DSC2BB_SM_CTRL1_ACQCDR_TIMEOUT_BITS 5 27254 #define DSC2BB_SM_CTRL1_ACQCDR_TIMEOUT_SHIFT 0 27255 27256 27257 /**************************************************************************** 27258 * Dsc2bB :: sm_ctrl2 27259 */ 27260 /* Dsc2bB :: sm_ctrl2 :: acqvga_timeout [15:11] */ 27261 #define DSC2BB_SM_CTRL2_ACQVGA_TIMEOUT_MASK 0xf800 27262 #define DSC2BB_SM_CTRL2_ACQVGA_TIMEOUT_ALIGN 0 27263 #define DSC2BB_SM_CTRL2_ACQVGA_TIMEOUT_BITS 5 27264 #define DSC2BB_SM_CTRL2_ACQVGA_TIMEOUT_SHIFT 11 27265 27266 /* Dsc2bB :: sm_ctrl2 :: bypass_os_integ_xfer [10:10] */ 27267 #define DSC2BB_SM_CTRL2_BYPASS_OS_INTEG_XFER_MASK 0x0400 27268 #define DSC2BB_SM_CTRL2_BYPASS_OS_INTEG_XFER_ALIGN 0 27269 #define DSC2BB_SM_CTRL2_BYPASS_OS_INTEG_XFER_BITS 1 27270 #define DSC2BB_SM_CTRL2_BYPASS_OS_INTEG_XFER_SHIFT 10 27271 27272 /* Dsc2bB :: sm_ctrl2 :: vga_frzval [09:09] */ 27273 #define DSC2BB_SM_CTRL2_VGA_FRZVAL_MASK 0x0200 27274 #define DSC2BB_SM_CTRL2_VGA_FRZVAL_ALIGN 0 27275 #define DSC2BB_SM_CTRL2_VGA_FRZVAL_BITS 1 27276 #define DSC2BB_SM_CTRL2_VGA_FRZVAL_SHIFT 9 27277 27278 /* Dsc2bB :: sm_ctrl2 :: vga_frcfrz [08:08] */ 27279 #define DSC2BB_SM_CTRL2_VGA_FRCFRZ_MASK 0x0100 27280 #define DSC2BB_SM_CTRL2_VGA_FRCFRZ_ALIGN 0 27281 #define DSC2BB_SM_CTRL2_VGA_FRCFRZ_BITS 1 27282 #define DSC2BB_SM_CTRL2_VGA_FRCFRZ_SHIFT 8 27283 27284 /* Dsc2bB :: sm_ctrl2 :: dfe_frzval [07:07] */ 27285 #define DSC2BB_SM_CTRL2_DFE_FRZVAL_MASK 0x0080 27286 #define DSC2BB_SM_CTRL2_DFE_FRZVAL_ALIGN 0 27287 #define DSC2BB_SM_CTRL2_DFE_FRZVAL_BITS 1 27288 #define DSC2BB_SM_CTRL2_DFE_FRZVAL_SHIFT 7 27289 27290 /* Dsc2bB :: sm_ctrl2 :: dfe_frcfrz [06:06] */ 27291 #define DSC2BB_SM_CTRL2_DFE_FRCFRZ_MASK 0x0040 27292 #define DSC2BB_SM_CTRL2_DFE_FRCFRZ_ALIGN 0 27293 #define DSC2BB_SM_CTRL2_DFE_FRCFRZ_BITS 1 27294 #define DSC2BB_SM_CTRL2_DFE_FRCFRZ_SHIFT 6 27295 27296 /* Dsc2bB :: sm_ctrl2 :: dsc_clr_val [05:05] */ 27297 #define DSC2BB_SM_CTRL2_DSC_CLR_VAL_MASK 0x0020 27298 #define DSC2BB_SM_CTRL2_DSC_CLR_VAL_ALIGN 0 27299 #define DSC2BB_SM_CTRL2_DSC_CLR_VAL_BITS 1 27300 #define DSC2BB_SM_CTRL2_DSC_CLR_VAL_SHIFT 5 27301 27302 /* Dsc2bB :: sm_ctrl2 :: dsc_clr_frc [04:04] */ 27303 #define DSC2BB_SM_CTRL2_DSC_CLR_FRC_MASK 0x0010 27304 #define DSC2BB_SM_CTRL2_DSC_CLR_FRC_ALIGN 0 27305 #define DSC2BB_SM_CTRL2_DSC_CLR_FRC_BITS 1 27306 #define DSC2BB_SM_CTRL2_DSC_CLR_FRC_SHIFT 4 27307 27308 /* Dsc2bB :: sm_ctrl2 :: train2_req [03:03] */ 27309 #define DSC2BB_SM_CTRL2_TRAIN2_REQ_MASK 0x0008 27310 #define DSC2BB_SM_CTRL2_TRAIN2_REQ_ALIGN 0 27311 #define DSC2BB_SM_CTRL2_TRAIN2_REQ_BITS 1 27312 #define DSC2BB_SM_CTRL2_TRAIN2_REQ_SHIFT 3 27313 27314 /* Dsc2bB :: sm_ctrl2 :: train1_req [02:02] */ 27315 #define DSC2BB_SM_CTRL2_TRAIN1_REQ_MASK 0x0004 27316 #define DSC2BB_SM_CTRL2_TRAIN1_REQ_ALIGN 0 27317 #define DSC2BB_SM_CTRL2_TRAIN1_REQ_BITS 1 27318 #define DSC2BB_SM_CTRL2_TRAIN1_REQ_SHIFT 2 27319 27320 /* Dsc2bB :: sm_ctrl2 :: soft_ack [01:01] */ 27321 #define DSC2BB_SM_CTRL2_SOFT_ACK_MASK 0x0002 27322 #define DSC2BB_SM_CTRL2_SOFT_ACK_ALIGN 0 27323 #define DSC2BB_SM_CTRL2_SOFT_ACK_BITS 1 27324 #define DSC2BB_SM_CTRL2_SOFT_ACK_SHIFT 1 27325 27326 /* Dsc2bB :: sm_ctrl2 :: train_mode_en [00:00] */ 27327 #define DSC2BB_SM_CTRL2_TRAIN_MODE_EN_MASK 0x0001 27328 #define DSC2BB_SM_CTRL2_TRAIN_MODE_EN_ALIGN 0 27329 #define DSC2BB_SM_CTRL2_TRAIN_MODE_EN_BITS 1 27330 #define DSC2BB_SM_CTRL2_TRAIN_MODE_EN_SHIFT 0 27331 27332 27333 /**************************************************************************** 27334 * Dsc2bB :: sm_ctrl3 27335 */ 27336 /* Dsc2bB :: sm_ctrl3 :: reserved_for_eco0 [15:15] */ 27337 #define DSC2BB_SM_CTRL3_RESERVED_FOR_ECO0_MASK 0x8000 27338 #define DSC2BB_SM_CTRL3_RESERVED_FOR_ECO0_ALIGN 0 27339 #define DSC2BB_SM_CTRL3_RESERVED_FOR_ECO0_BITS 1 27340 #define DSC2BB_SM_CTRL3_RESERVED_FOR_ECO0_SHIFT 15 27341 27342 /* Dsc2bB :: sm_ctrl3 :: cdrbr_bwsel_prop_acqcdr [14:12] */ 27343 #define DSC2BB_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_MASK 0x7000 27344 #define DSC2BB_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_ALIGN 0 27345 #define DSC2BB_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_BITS 3 27346 #define DSC2BB_SM_CTRL3_CDRBR_BWSEL_PROP_ACQCDR_SHIFT 12 27347 27348 /* Dsc2bB :: sm_ctrl3 :: dfe_gain_acq2 [11:10] */ 27349 #define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ2_MASK 0x0c00 27350 #define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ2_ALIGN 0 27351 #define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ2_BITS 2 27352 #define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ2_SHIFT 10 27353 27354 /* Dsc2bB :: sm_ctrl3 :: dfe_gain_acq1 [09:08] */ 27355 #define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ1_MASK 0x0300 27356 #define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ1_ALIGN 0 27357 #define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ1_BITS 2 27358 #define DSC2BB_SM_CTRL3_DFE_GAIN_ACQ1_SHIFT 8 27359 27360 /* Dsc2bB :: sm_ctrl3 :: vga_gain_acq2 [07:06] */ 27361 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ2_MASK 0x00c0 27362 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ2_ALIGN 0 27363 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ2_BITS 2 27364 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ2_SHIFT 6 27365 27366 /* Dsc2bB :: sm_ctrl3 :: vga_gain_acq1 [05:04] */ 27367 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ1_MASK 0x0030 27368 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ1_ALIGN 0 27369 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ1_BITS 2 27370 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQ1_SHIFT 4 27371 27372 /* Dsc2bB :: sm_ctrl3 :: vga_gain_acqcdr [03:02] */ 27373 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQCDR_MASK 0x000c 27374 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQCDR_ALIGN 0 27375 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQCDR_BITS 2 27376 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQCDR_SHIFT 2 27377 27378 /* Dsc2bB :: sm_ctrl3 :: vga_gain_acqvga [01:00] */ 27379 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQVGA_MASK 0x0003 27380 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQVGA_ALIGN 0 27381 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQVGA_BITS 2 27382 #define DSC2BB_SM_CTRL3_VGA_GAIN_ACQVGA_SHIFT 0 27383 27384 27385 /**************************************************************************** 27386 * Dsc2bB :: sm_ctrl4 27387 */ 27388 /* Dsc2bB :: sm_ctrl4 :: cdros45_bwsel_prop_offset [15:14] */ 27389 #define DSC2BB_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_MASK 0xc000 27390 #define DSC2BB_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_ALIGN 0 27391 #define DSC2BB_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_BITS 2 27392 #define DSC2BB_SM_CTRL4_CDROS45_BWSEL_PROP_OFFSET_SHIFT 14 27393 27394 /* Dsc2bB :: sm_ctrl4 :: cdros45_bwsel_integ_offset [13:12] */ 27395 #define DSC2BB_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_MASK 0x3000 27396 #define DSC2BB_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_ALIGN 0 27397 #define DSC2BB_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_BITS 2 27398 #define DSC2BB_SM_CTRL4_CDROS45_BWSEL_INTEG_OFFSET_SHIFT 12 27399 27400 /* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_integ_acq2 [11:10] */ 27401 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_MASK 0x0c00 27402 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_ALIGN 0 27403 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_BITS 2 27404 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ2_SHIFT 10 27405 27406 /* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_integ_acq1 [09:08] */ 27407 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_MASK 0x0300 27408 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_ALIGN 0 27409 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_BITS 2 27410 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQ1_SHIFT 8 27411 27412 /* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_integ_acqcdr [07:06] */ 27413 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_MASK 0x00c0 27414 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_ALIGN 0 27415 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_BITS 2 27416 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_INTEG_ACQCDR_SHIFT 6 27417 27418 /* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_prop_acq2 [05:03] */ 27419 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_MASK 0x0038 27420 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_ALIGN 0 27421 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_BITS 3 27422 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ2_SHIFT 3 27423 27424 /* Dsc2bB :: sm_ctrl4 :: cdrbr_bwsel_prop_acq1 [02:00] */ 27425 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_MASK 0x0007 27426 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_ALIGN 0 27427 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_BITS 3 27428 #define DSC2BB_SM_CTRL4_CDRBR_BWSEL_PROP_ACQ1_SHIFT 0 27429 27430 27431 /**************************************************************************** 27432 * Dsc2bB :: sm_ctrl5 27433 */ 27434 /* Dsc2bB :: sm_ctrl5 :: cdros_bwsel_integ_acq1_2 [15:12] */ 27435 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_MASK 0xf000 27436 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_ALIGN 0 27437 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_BITS 4 27438 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQ1_2_SHIFT 12 27439 27440 /* Dsc2bB :: sm_ctrl5 :: cdros_bwsel_integ_acqcdr [11:08] */ 27441 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_MASK 0x0f00 27442 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_ALIGN 0 27443 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_BITS 4 27444 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_INTEG_ACQCDR_SHIFT 8 27445 27446 /* Dsc2bB :: sm_ctrl5 :: cdros_bwsel_prop_acq1_2 [07:04] */ 27447 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_MASK 0x00f0 27448 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_ALIGN 0 27449 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_BITS 4 27450 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQ1_2_SHIFT 4 27451 27452 /* Dsc2bB :: sm_ctrl5 :: cdros_bwsel_prop_acqcdr [03:00] */ 27453 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_MASK 0x000f 27454 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_ALIGN 0 27455 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_BITS 4 27456 #define DSC2BB_SM_CTRL5_CDROS_BWSEL_PROP_ACQCDR_SHIFT 0 27457 27458 27459 /**************************************************************************** 27460 * Dsc2bB :: sm_ctrl6 27461 */ 27462 /* Dsc2bB :: sm_ctrl6 :: reserved_for_eco0 [15:13] */ 27463 #define DSC2BB_SM_CTRL6_RESERVED_FOR_ECO0_MASK 0xe000 27464 #define DSC2BB_SM_CTRL6_RESERVED_FOR_ECO0_ALIGN 0 27465 #define DSC2BB_SM_CTRL6_RESERVED_FOR_ECO0_BITS 3 27466 #define DSC2BB_SM_CTRL6_RESERVED_FOR_ECO0_SHIFT 13 27467 27468 /* Dsc2bB :: sm_ctrl6 :: cdrbr_bwsel_integ_acqphase [12:11] */ 27469 #define DSC2BB_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_MASK 0x1800 27470 #define DSC2BB_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_ALIGN 0 27471 #define DSC2BB_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_BITS 2 27472 #define DSC2BB_SM_CTRL6_CDRBR_BWSEL_INTEG_ACQPHASE_SHIFT 11 27473 27474 /* Dsc2bB :: sm_ctrl6 :: cdrbr_bwsel_prop_acqphase [10:08] */ 27475 #define DSC2BB_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_MASK 0x0700 27476 #define DSC2BB_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_ALIGN 0 27477 #define DSC2BB_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_BITS 3 27478 #define DSC2BB_SM_CTRL6_CDRBR_BWSEL_PROP_ACQPHASE_SHIFT 8 27479 27480 /* Dsc2bB :: sm_ctrl6 :: cdros_bwsel_integ_acqvga [07:04] */ 27481 #define DSC2BB_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_MASK 0x00f0 27482 #define DSC2BB_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_ALIGN 0 27483 #define DSC2BB_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_BITS 4 27484 #define DSC2BB_SM_CTRL6_CDROS_BWSEL_INTEG_ACQVGA_SHIFT 4 27485 27486 /* Dsc2bB :: sm_ctrl6 :: cdros_bwsel_prop_acqvga [03:00] */ 27487 #define DSC2BB_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_MASK 0x000f 27488 #define DSC2BB_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_ALIGN 0 27489 #define DSC2BB_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_BITS 4 27490 #define DSC2BB_SM_CTRL6_CDROS_BWSEL_PROP_ACQVGA_SHIFT 0 27491 27492 27493 /**************************************************************************** 27494 * Dsc2bB :: sm_ctrl7 27495 */ 27496 /* Dsc2bB :: sm_ctrl7 :: reserved_for_eco0 [15:15] */ 27497 #define DSC2BB_SM_CTRL7_RESERVED_FOR_ECO0_MASK 0x8000 27498 #define DSC2BB_SM_CTRL7_RESERVED_FOR_ECO0_ALIGN 0 27499 #define DSC2BB_SM_CTRL7_RESERVED_FOR_ECO0_BITS 1 27500 #define DSC2BB_SM_CTRL7_RESERVED_FOR_ECO0_SHIFT 15 27501 27502 /* Dsc2bB :: sm_ctrl7 :: pf_ctrl_br_offset [14:12] */ 27503 #define DSC2BB_SM_CTRL7_PF_CTRL_BR_OFFSET_MASK 0x7000 27504 #define DSC2BB_SM_CTRL7_PF_CTRL_BR_OFFSET_ALIGN 0 27505 #define DSC2BB_SM_CTRL7_PF_CTRL_BR_OFFSET_BITS 3 27506 #define DSC2BB_SM_CTRL7_PF_CTRL_BR_OFFSET_SHIFT 12 27507 27508 /* Dsc2bB :: sm_ctrl7 :: pf_ctrl_osx1_offset [11:09] */ 27509 #define DSC2BB_SM_CTRL7_PF_CTRL_OSX1_OFFSET_MASK 0x0e00 27510 #define DSC2BB_SM_CTRL7_PF_CTRL_OSX1_OFFSET_ALIGN 0 27511 #define DSC2BB_SM_CTRL7_PF_CTRL_OSX1_OFFSET_BITS 3 27512 #define DSC2BB_SM_CTRL7_PF_CTRL_OSX1_OFFSET_SHIFT 9 27513 27514 /* Dsc2bB :: sm_ctrl7 :: pf_ctrl_osx2_offset [08:06] */ 27515 #define DSC2BB_SM_CTRL7_PF_CTRL_OSX2_OFFSET_MASK 0x01c0 27516 #define DSC2BB_SM_CTRL7_PF_CTRL_OSX2_OFFSET_ALIGN 0 27517 #define DSC2BB_SM_CTRL7_PF_CTRL_OSX2_OFFSET_BITS 3 27518 #define DSC2BB_SM_CTRL7_PF_CTRL_OSX2_OFFSET_SHIFT 6 27519 27520 /* Dsc2bB :: sm_ctrl7 :: pf_ctrl_br_init [05:03] */ 27521 #define DSC2BB_SM_CTRL7_PF_CTRL_BR_INIT_MASK 0x0038 27522 #define DSC2BB_SM_CTRL7_PF_CTRL_BR_INIT_ALIGN 0 27523 #define DSC2BB_SM_CTRL7_PF_CTRL_BR_INIT_BITS 3 27524 #define DSC2BB_SM_CTRL7_PF_CTRL_BR_INIT_SHIFT 3 27525 27526 /* Dsc2bB :: sm_ctrl7 :: pf_ctrl_os_init [02:00] */ 27527 #define DSC2BB_SM_CTRL7_PF_CTRL_OS_INIT_MASK 0x0007 27528 #define DSC2BB_SM_CTRL7_PF_CTRL_OS_INIT_ALIGN 0 27529 #define DSC2BB_SM_CTRL7_PF_CTRL_OS_INIT_BITS 3 27530 #define DSC2BB_SM_CTRL7_PF_CTRL_OS_INIT_SHIFT 0 27531 27532 27533 /**************************************************************************** 27534 * Dsc2bB :: sm_ctrl8 27535 */ 27536 /* Dsc2bB :: sm_ctrl8 :: reserved_for_eco0 [15:10] */ 27537 #define DSC2BB_SM_CTRL8_RESERVED_FOR_ECO0_MASK 0xfc00 27538 #define DSC2BB_SM_CTRL8_RESERVED_FOR_ECO0_ALIGN 0 27539 #define DSC2BB_SM_CTRL8_RESERVED_FOR_ECO0_BITS 6 27540 #define DSC2BB_SM_CTRL8_RESERVED_FOR_ECO0_SHIFT 10 27541 27542 /* Dsc2bB :: sm_ctrl8 :: vga_max_val [09:05] */ 27543 #define DSC2BB_SM_CTRL8_VGA_MAX_VAL_MASK 0x03e0 27544 #define DSC2BB_SM_CTRL8_VGA_MAX_VAL_ALIGN 0 27545 #define DSC2BB_SM_CTRL8_VGA_MAX_VAL_BITS 5 27546 #define DSC2BB_SM_CTRL8_VGA_MAX_VAL_SHIFT 5 27547 27548 /* Dsc2bB :: sm_ctrl8 :: vga_min_val [04:00] */ 27549 #define DSC2BB_SM_CTRL8_VGA_MIN_VAL_MASK 0x001f 27550 #define DSC2BB_SM_CTRL8_VGA_MIN_VAL_ALIGN 0 27551 #define DSC2BB_SM_CTRL8_VGA_MIN_VAL_BITS 5 27552 #define DSC2BB_SM_CTRL8_VGA_MIN_VAL_SHIFT 0 27553 27554 27555 /**************************************************************************** 27556 * Dsc2bB :: sm_ctrl9 27557 */ 27558 /* Dsc2bB :: sm_ctrl9 :: reserved_for_eco0 [15:12] */ 27559 #define DSC2BB_SM_CTRL9_RESERVED_FOR_ECO0_MASK 0xf000 27560 #define DSC2BB_SM_CTRL9_RESERVED_FOR_ECO0_ALIGN 0 27561 #define DSC2BB_SM_CTRL9_RESERVED_FOR_ECO0_BITS 4 27562 #define DSC2BB_SM_CTRL9_RESERVED_FOR_ECO0_SHIFT 12 27563 27564 /* Dsc2bB :: sm_ctrl9 :: dfe_max_val [11:06] */ 27565 #define DSC2BB_SM_CTRL9_DFE_MAX_VAL_MASK 0x0fc0 27566 #define DSC2BB_SM_CTRL9_DFE_MAX_VAL_ALIGN 0 27567 #define DSC2BB_SM_CTRL9_DFE_MAX_VAL_BITS 6 27568 #define DSC2BB_SM_CTRL9_DFE_MAX_VAL_SHIFT 6 27569 27570 /* Dsc2bB :: sm_ctrl9 :: dfe_min_val [05:00] */ 27571 #define DSC2BB_SM_CTRL9_DFE_MIN_VAL_MASK 0x003f 27572 #define DSC2BB_SM_CTRL9_DFE_MIN_VAL_ALIGN 0 27573 #define DSC2BB_SM_CTRL9_DFE_MIN_VAL_BITS 6 27574 #define DSC2BB_SM_CTRL9_DFE_MIN_VAL_SHIFT 0 27575 27576 27577 /**************************************************************************** 27578 * Dsc2bB :: sm_ctrl10 27579 */ 27580 /* Dsc2bB :: sm_ctrl10 :: reserved_for_eco0 [15:14] */ 27581 #define DSC2BB_SM_CTRL10_RESERVED_FOR_ECO0_MASK 0xc000 27582 #define DSC2BB_SM_CTRL10_RESERVED_FOR_ECO0_ALIGN 0 27583 #define DSC2BB_SM_CTRL10_RESERVED_FOR_ECO0_BITS 2 27584 #define DSC2BB_SM_CTRL10_RESERVED_FOR_ECO0_SHIFT 14 27585 27586 /* Dsc2bB :: sm_ctrl10 :: br_pf_tap_en [13:07] */ 27587 #define DSC2BB_SM_CTRL10_BR_PF_TAP_EN_MASK 0x3f80 27588 #define DSC2BB_SM_CTRL10_BR_PF_TAP_EN_ALIGN 0 27589 #define DSC2BB_SM_CTRL10_BR_PF_TAP_EN_BITS 7 27590 #define DSC2BB_SM_CTRL10_BR_PF_TAP_EN_SHIFT 7 27591 27592 /* Dsc2bB :: sm_ctrl10 :: osx1_pf_tap_en [06:00] */ 27593 #define DSC2BB_SM_CTRL10_OSX1_PF_TAP_EN_MASK 0x007f 27594 #define DSC2BB_SM_CTRL10_OSX1_PF_TAP_EN_ALIGN 0 27595 #define DSC2BB_SM_CTRL10_OSX1_PF_TAP_EN_BITS 7 27596 #define DSC2BB_SM_CTRL10_OSX1_PF_TAP_EN_SHIFT 0 27597 27598 27599 /**************************************************************************** 27600 * Dsc2bB :: sm_ctrl11 27601 */ 27602 /* Dsc2bB :: sm_ctrl11 :: reserved_for_eco0 [15:15] */ 27603 #define DSC2BB_SM_CTRL11_RESERVED_FOR_ECO0_MASK 0x8000 27604 #define DSC2BB_SM_CTRL11_RESERVED_FOR_ECO0_ALIGN 0 27605 #define DSC2BB_SM_CTRL11_RESERVED_FOR_ECO0_BITS 1 27606 #define DSC2BB_SM_CTRL11_RESERVED_FOR_ECO0_SHIFT 15 27607 27608 /* Dsc2bB :: sm_ctrl11 :: msr_br_vga_timeout [14:10] */ 27609 #define DSC2BB_SM_CTRL11_MSR_BR_VGA_TIMEOUT_MASK 0x7c00 27610 #define DSC2BB_SM_CTRL11_MSR_BR_VGA_TIMEOUT_ALIGN 0 27611 #define DSC2BB_SM_CTRL11_MSR_BR_VGA_TIMEOUT_BITS 5 27612 #define DSC2BB_SM_CTRL11_MSR_BR_VGA_TIMEOUT_SHIFT 10 27613 27614 /* Dsc2bB :: sm_ctrl11 :: hysteresis_timeout [09:05] */ 27615 #define DSC2BB_SM_CTRL11_HYSTERESIS_TIMEOUT_MASK 0x03e0 27616 #define DSC2BB_SM_CTRL11_HYSTERESIS_TIMEOUT_ALIGN 0 27617 #define DSC2BB_SM_CTRL11_HYSTERESIS_TIMEOUT_BITS 5 27618 #define DSC2BB_SM_CTRL11_HYSTERESIS_TIMEOUT_SHIFT 5 27619 27620 /* Dsc2bB :: sm_ctrl11 :: msr_postc_timeout [04:00] */ 27621 #define DSC2BB_SM_CTRL11_MSR_POSTC_TIMEOUT_MASK 0x001f 27622 #define DSC2BB_SM_CTRL11_MSR_POSTC_TIMEOUT_ALIGN 0 27623 #define DSC2BB_SM_CTRL11_MSR_POSTC_TIMEOUT_BITS 5 27624 #define DSC2BB_SM_CTRL11_MSR_POSTC_TIMEOUT_SHIFT 0 27625 27626 27627 /**************************************************************************** 27628 * Dsc2bB :: sm_ctrl12 27629 */ 27630 /* Dsc2bB :: sm_ctrl12 :: reserved_for_eco0 [15:14] */ 27631 #define DSC2BB_SM_CTRL12_RESERVED_FOR_ECO0_MASK 0xc000 27632 #define DSC2BB_SM_CTRL12_RESERVED_FOR_ECO0_ALIGN 0 27633 #define DSC2BB_SM_CTRL12_RESERVED_FOR_ECO0_BITS 2 27634 #define DSC2BB_SM_CTRL12_RESERVED_FOR_ECO0_SHIFT 14 27635 27636 /* Dsc2bB :: sm_ctrl12 :: br_vga_lms_gain [13:12] */ 27637 #define DSC2BB_SM_CTRL12_BR_VGA_LMS_GAIN_MASK 0x3000 27638 #define DSC2BB_SM_CTRL12_BR_VGA_LMS_GAIN_ALIGN 0 27639 #define DSC2BB_SM_CTRL12_BR_VGA_LMS_GAIN_BITS 2 27640 #define DSC2BB_SM_CTRL12_BR_VGA_LMS_GAIN_SHIFT 12 27641 27642 /* Dsc2bB :: sm_ctrl12 :: postc_dfe_lms_gain [11:10] */ 27643 #define DSC2BB_SM_CTRL12_POSTC_DFE_LMS_GAIN_MASK 0x0c00 27644 #define DSC2BB_SM_CTRL12_POSTC_DFE_LMS_GAIN_ALIGN 0 27645 #define DSC2BB_SM_CTRL12_POSTC_DFE_LMS_GAIN_BITS 2 27646 #define DSC2BB_SM_CTRL12_POSTC_DFE_LMS_GAIN_SHIFT 10 27647 27648 /* Dsc2bB :: sm_ctrl12 :: cdr_phase_inversion_timeout [09:05] */ 27649 #define DSC2BB_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_MASK 0x03e0 27650 #define DSC2BB_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_ALIGN 0 27651 #define DSC2BB_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_BITS 5 27652 #define DSC2BB_SM_CTRL12_CDR_PHASE_INVERSION_TIMEOUT_SHIFT 5 27653 27654 /* Dsc2bB :: sm_ctrl12 :: msr_pf_timeout [04:00] */ 27655 #define DSC2BB_SM_CTRL12_MSR_PF_TIMEOUT_MASK 0x001f 27656 #define DSC2BB_SM_CTRL12_MSR_PF_TIMEOUT_ALIGN 0 27657 #define DSC2BB_SM_CTRL12_MSR_PF_TIMEOUT_BITS 5 27658 #define DSC2BB_SM_CTRL12_MSR_PF_TIMEOUT_SHIFT 0 27659 27660 27661 /**************************************************************************** 27662 * Dsc2bB :: dsc_diag_ctrl0 27663 */ 27664 /* Dsc2bB :: dsc_diag_ctrl0 :: reserved_for_eco0 [15:11] */ 27665 #define DSC2BB_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_MASK 0xf800 27666 #define DSC2BB_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 27667 #define DSC2BB_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_BITS 5 27668 #define DSC2BB_DSC_DIAG_CTRL0_RESERVED_FOR_ECO0_SHIFT 11 27669 27670 /* Dsc2bB :: dsc_diag_ctrl0 :: voffset [10:07] */ 27671 #define DSC2BB_DSC_DIAG_CTRL0_VOFFSET_MASK 0x0780 27672 #define DSC2BB_DSC_DIAG_CTRL0_VOFFSET_ALIGN 0 27673 #define DSC2BB_DSC_DIAG_CTRL0_VOFFSET_BITS 4 27674 #define DSC2BB_DSC_DIAG_CTRL0_VOFFSET_SHIFT 7 27675 27676 /* Dsc2bB :: dsc_diag_ctrl0 :: hoffset [06:01] */ 27677 #define DSC2BB_DSC_DIAG_CTRL0_HOFFSET_MASK 0x007e 27678 #define DSC2BB_DSC_DIAG_CTRL0_HOFFSET_ALIGN 0 27679 #define DSC2BB_DSC_DIAG_CTRL0_HOFFSET_BITS 6 27680 #define DSC2BB_DSC_DIAG_CTRL0_HOFFSET_SHIFT 1 27681 27682 /* Dsc2bB :: dsc_diag_ctrl0 :: diagnostics_en [00:00] */ 27683 #define DSC2BB_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_MASK 0x0001 27684 #define DSC2BB_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_ALIGN 0 27685 #define DSC2BB_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_BITS 1 27686 #define DSC2BB_DSC_DIAG_CTRL0_DIAGNOSTICS_EN_SHIFT 0 27687 27688 27689 /**************************************************************************** 27690 * Dsc2bB :: dsc_misc_ctrl0 27691 */ 27692 /* Dsc2bB :: dsc_misc_ctrl0 :: rxSeqStart [15:15] */ 27693 #define DSC2BB_DSC_MISC_CTRL0_RXSEQSTART_MASK 0x8000 27694 #define DSC2BB_DSC_MISC_CTRL0_RXSEQSTART_ALIGN 0 27695 #define DSC2BB_DSC_MISC_CTRL0_RXSEQSTART_BITS 1 27696 #define DSC2BB_DSC_MISC_CTRL0_RXSEQSTART_SHIFT 15 27697 27698 /* Dsc2bB :: dsc_misc_ctrl0 :: forceRxSeqDone [14:14] */ 27699 #define DSC2BB_DSC_MISC_CTRL0_FORCERXSEQDONE_MASK 0x4000 27700 #define DSC2BB_DSC_MISC_CTRL0_FORCERXSEQDONE_ALIGN 0 27701 #define DSC2BB_DSC_MISC_CTRL0_FORCERXSEQDONE_BITS 1 27702 #define DSC2BB_DSC_MISC_CTRL0_FORCERXSEQDONE_SHIFT 14 27703 27704 /* Dsc2bB :: dsc_misc_ctrl0 :: enable_acor_picw [13:13] */ 27705 #define DSC2BB_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_MASK 0x2000 27706 #define DSC2BB_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_ALIGN 0 27707 #define DSC2BB_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_BITS 1 27708 #define DSC2BB_DSC_MISC_CTRL0_ENABLE_ACOR_PICW_SHIFT 13 27709 27710 /* Dsc2bB :: dsc_misc_ctrl0 :: reserved_for_eco0 [12:10] */ 27711 #define DSC2BB_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_MASK 0x1c00 27712 #define DSC2BB_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_ALIGN 0 27713 #define DSC2BB_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_BITS 3 27714 #define DSC2BB_DSC_MISC_CTRL0_RESERVED_FOR_ECO0_SHIFT 10 27715 27716 /* Dsc2bB :: dsc_misc_ctrl0 :: cdrbr_sel_force [09:09] */ 27717 #define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_MASK 0x0200 27718 #define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_ALIGN 0 27719 #define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_BITS 1 27720 #define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_SHIFT 9 27721 27722 /* Dsc2bB :: dsc_misc_ctrl0 :: cdrbr_sel_force_val [08:08] */ 27723 #define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_MASK 0x0100 27724 #define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_ALIGN 0 27725 #define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_BITS 1 27726 #define DSC2BB_DSC_MISC_CTRL0_CDRBR_SEL_FORCE_VAL_SHIFT 8 27727 27728 /* Dsc2bB :: dsc_misc_ctrl0 :: osr_mode_force [07:07] */ 27729 #define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_MASK 0x0080 27730 #define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_ALIGN 0 27731 #define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_BITS 1 27732 #define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_SHIFT 7 27733 27734 /* Dsc2bB :: dsc_misc_ctrl0 :: osr_mode_force_val [06:04] */ 27735 #define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_MASK 0x0070 27736 #define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_ALIGN 0 27737 #define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_BITS 3 27738 #define DSC2BB_DSC_MISC_CTRL0_OSR_MODE_FORCE_VAL_SHIFT 4 27739 27740 /* Dsc2bB :: dsc_misc_ctrl0 :: test_bus_sel [03:00] */ 27741 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_MASK 0x000f 27742 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_ALIGN 0 27743 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_BITS 4 27744 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_SHIFT 0 27745 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_Off 0 27746 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx2data 1 27747 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_OSx1data_m1 2 27748 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_BR_data_m1_p1 3 27749 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseVco 4 27750 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrIntg 6 27751 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_cdrPhaseErr 7 27752 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeAccEvenOdd 8 27753 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeVgasumDfe 9 27754 #define DSC2BB_DSC_MISC_CTRL0_TEST_BUS_SEL_dfeTrnsum 10 27755 27756 27757 /**************************************************************************** 27758 * Hypercore_USER_Dsc3b0 27759 */ 27760 /**************************************************************************** 27761 * Dsc3b0 :: cdr_status0 27762 */ 27763 /* Dsc3b0 :: cdr_status0 :: integ_reg [15:00] */ 27764 #define DSC3B0_CDR_STATUS0_INTEG_REG_MASK 0xffff 27765 #define DSC3B0_CDR_STATUS0_INTEG_REG_ALIGN 0 27766 #define DSC3B0_CDR_STATUS0_INTEG_REG_BITS 16 27767 #define DSC3B0_CDR_STATUS0_INTEG_REG_SHIFT 0 27768 27769 27770 /**************************************************************************** 27771 * Dsc3b0 :: cdr_status1 27772 */ 27773 /* Dsc3b0 :: cdr_status1 :: integ_reg_xfer [15:00] */ 27774 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_MASK 0xffff 27775 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_ALIGN 0 27776 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_BITS 16 27777 #define DSC3B0_CDR_STATUS1_INTEG_REG_XFER_SHIFT 0 27778 27779 27780 /**************************************************************************** 27781 * Dsc3b0 :: cdr_status2 27782 */ 27783 /* Dsc3b0 :: cdr_status2 :: reserved_for_eco0 [15:11] */ 27784 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_MASK 0xf800 27785 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 27786 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_BITS 5 27787 #define DSC3B0_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT 11 27788 27789 /* Dsc3b0 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */ 27790 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK 0x0400 27791 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN 0 27792 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS 1 27793 #define DSC3B0_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT 10 27794 27795 /* Dsc3b0 :: cdr_status2 :: br_cdr_enabled [09:09] */ 27796 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_MASK 0x0200 27797 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_ALIGN 0 27798 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_BITS 1 27799 #define DSC3B0_CDR_STATUS2_BR_CDR_ENABLED_SHIFT 9 27800 27801 /* Dsc3b0 :: cdr_status2 :: oscdr_mode [08:06] */ 27802 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_MASK 0x01c0 27803 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_ALIGN 0 27804 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_BITS 3 27805 #define DSC3B0_CDR_STATUS2_OSCDR_MODE_SHIFT 6 27806 27807 /* Dsc3b0 :: cdr_status2 :: phase_err [05:00] */ 27808 #define DSC3B0_CDR_STATUS2_PHASE_ERR_MASK 0x003f 27809 #define DSC3B0_CDR_STATUS2_PHASE_ERR_ALIGN 0 27810 #define DSC3B0_CDR_STATUS2_PHASE_ERR_BITS 6 27811 #define DSC3B0_CDR_STATUS2_PHASE_ERR_SHIFT 0 27812 27813 27814 /**************************************************************************** 27815 * Dsc3b0 :: pi_status0 27816 */ 27817 /* Dsc3b0 :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */ 27818 #define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL0_MASK 0x8000 27819 #define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN 0 27820 #define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL0_BITS 1 27821 #define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT 15 27822 27823 /* Dsc3b0 :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */ 27824 #define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL90_MASK 0x4000 27825 #define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN 0 27826 #define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL90_BITS 1 27827 #define DSC3B0_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT 14 27828 27829 /* Dsc3b0 :: pi_status0 :: clk90_phase_offset [13:07] */ 27830 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 27831 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 27832 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 27833 #define DSC3B0_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 27834 27835 /* Dsc3b0 :: pi_status0 :: phase_cntr [06:00] */ 27836 #define DSC3B0_PI_STATUS0_PHASE_CNTR_MASK 0x007f 27837 #define DSC3B0_PI_STATUS0_PHASE_CNTR_ALIGN 0 27838 #define DSC3B0_PI_STATUS0_PHASE_CNTR_BITS 7 27839 #define DSC3B0_PI_STATUS0_PHASE_CNTR_SHIFT 0 27840 27841 27842 /**************************************************************************** 27843 * Dsc3b0 :: pi_status1 27844 */ 27845 /* union - case pi_Single0_lsb [15:00] */ 27846 /* Dsc3b0 :: pi_status1 :: Single0_lsb [15:00] */ 27847 #define DSC3B0_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK 0xffff 27848 #define DSC3B0_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN 0 27849 #define DSC3B0_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS 16 27850 #define DSC3B0_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT 0 27851 27852 27853 /* union - case pi_Single0_msb [15:00] */ 27854 /* Dsc3b0 :: pi_status1 :: Single0_msb [15:00] */ 27855 #define DSC3B0_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK 0xffff 27856 #define DSC3B0_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN 0 27857 #define DSC3B0_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS 16 27858 #define DSC3B0_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT 0 27859 27860 27861 /* union - case pi_Sequence0_lsb [15:00] */ 27862 /* Dsc3b0 :: pi_status1 :: Sequence0_lsb [15:00] */ 27863 #define DSC3B0_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK 0xffff 27864 #define DSC3B0_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN 0 27865 #define DSC3B0_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS 16 27866 #define DSC3B0_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT 0 27867 27868 27869 /* union - case pi_Sequence0_msb [15:00] */ 27870 /* Dsc3b0 :: pi_status1 :: Sequence0_msb [15:00] */ 27871 #define DSC3B0_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK 0xffff 27872 #define DSC3B0_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN 0 27873 #define DSC3B0_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS 16 27874 #define DSC3B0_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT 0 27875 27876 27877 /* union - case pi_Single90_lsb [15:00] */ 27878 /* Dsc3b0 :: pi_status1 :: Single90_lsb [15:00] */ 27879 #define DSC3B0_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK 0xffff 27880 #define DSC3B0_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN 0 27881 #define DSC3B0_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS 16 27882 #define DSC3B0_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT 0 27883 27884 27885 /* union - case pi_Single90_msb [15:00] */ 27886 /* Dsc3b0 :: pi_status1 :: Single90_msb [15:00] */ 27887 #define DSC3B0_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK 0xffff 27888 #define DSC3B0_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN 0 27889 #define DSC3B0_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS 16 27890 #define DSC3B0_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT 0 27891 27892 27893 /* union - case pi_Sequence90_lsb [15:00] */ 27894 /* Dsc3b0 :: pi_status1 :: Sequence90_lsb [15:00] */ 27895 #define DSC3B0_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK 0xffff 27896 #define DSC3B0_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN 0 27897 #define DSC3B0_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS 16 27898 #define DSC3B0_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT 0 27899 27900 27901 /* union - case pi_Sequence90_msb [15:00] */ 27902 /* Dsc3b0 :: pi_status1 :: Sequence90_msb [15:00] */ 27903 #define DSC3B0_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK 0xffff 27904 #define DSC3B0_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN 0 27905 #define DSC3B0_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS 16 27906 #define DSC3B0_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT 0 27907 27908 27909 27910 /**************************************************************************** 27911 * Dsc3b0 :: dfe_vga_status0 27912 */ 27913 /* Dsc3b0 :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */ 27914 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK 0xf800 27915 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 27916 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS 5 27917 #define DSC3B0_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT 11 27918 27919 /* Dsc3b0 :: dfe_vga_status0 :: vga_sum [10:06] */ 27920 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_MASK 0x07c0 27921 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 27922 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_BITS 5 27923 #define DSC3B0_DFE_VGA_STATUS0_VGA_SUM_SHIFT 6 27924 27925 /* Dsc3b0 :: dfe_vga_status0 :: dfe_tap_bin [05:00] */ 27926 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK 0x003f 27927 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN 0 27928 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS 6 27929 #define DSC3B0_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT 0 27930 27931 27932 /**************************************************************************** 27933 * Dsc3b0 :: dfe_vga_status1 27934 */ 27935 /* Dsc3b0 :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */ 27936 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 27937 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 27938 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS 5 27939 #define DSC3B0_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 27940 27941 /* Dsc3b0 :: dfe_vga_status1 :: trnsum [10:00] */ 27942 #define DSC3B0_DFE_VGA_STATUS1_TRNSUM_MASK 0x07ff 27943 #define DSC3B0_DFE_VGA_STATUS1_TRNSUM_ALIGN 0 27944 #define DSC3B0_DFE_VGA_STATUS1_TRNSUM_BITS 11 27945 #define DSC3B0_DFE_VGA_STATUS1_TRNSUM_SHIFT 0 27946 27947 27948 /**************************************************************************** 27949 * Dsc3b0 :: sm_status0 27950 */ 27951 /* Dsc3b0 :: sm_status0 :: reserved_for_eco0 [15:14] */ 27952 #define DSC3B0_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 27953 #define DSC3B0_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 27954 #define DSC3B0_SM_STATUS0_RESERVED_FOR_ECO0_BITS 2 27955 #define DSC3B0_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 27956 27957 /* Dsc3b0 :: sm_status0 :: tuning_done [13:13] */ 27958 #define DSC3B0_SM_STATUS0_TUNING_DONE_MASK 0x2000 27959 #define DSC3B0_SM_STATUS0_TUNING_DONE_ALIGN 0 27960 #define DSC3B0_SM_STATUS0_TUNING_DONE_BITS 1 27961 #define DSC3B0_SM_STATUS0_TUNING_DONE_SHIFT 13 27962 27963 /* Dsc3b0 :: sm_status0 :: srch_state [12:09] */ 27964 #define DSC3B0_SM_STATUS0_SRCH_STATE_MASK 0x1e00 27965 #define DSC3B0_SM_STATUS0_SRCH_STATE_ALIGN 0 27966 #define DSC3B0_SM_STATUS0_SRCH_STATE_BITS 4 27967 #define DSC3B0_SM_STATUS0_SRCH_STATE_SHIFT 9 27968 27969 /* Dsc3b0 :: sm_status0 :: tuning_state [08:04] */ 27970 #define DSC3B0_SM_STATUS0_TUNING_STATE_MASK 0x01f0 27971 #define DSC3B0_SM_STATUS0_TUNING_STATE_ALIGN 0 27972 #define DSC3B0_SM_STATUS0_TUNING_STATE_BITS 5 27973 #define DSC3B0_SM_STATUS0_TUNING_STATE_SHIFT 4 27974 27975 /* Dsc3b0 :: sm_status0 :: dsc_state [03:00] */ 27976 #define DSC3B0_SM_STATUS0_DSC_STATE_MASK 0x000f 27977 #define DSC3B0_SM_STATUS0_DSC_STATE_ALIGN 0 27978 #define DSC3B0_SM_STATUS0_DSC_STATE_BITS 4 27979 #define DSC3B0_SM_STATUS0_DSC_STATE_SHIFT 0 27980 27981 27982 /**************************************************************************** 27983 * Dsc3b0 :: sm_status1 27984 */ 27985 /* Dsc3b0 :: sm_status1 :: reserved_for_eco0 [15:11] */ 27986 #define DSC3B0_SM_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 27987 #define DSC3B0_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 27988 #define DSC3B0_SM_STATUS1_RESERVED_FOR_ECO0_BITS 5 27989 #define DSC3B0_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 27990 27991 /* Dsc3b0 :: sm_status1 :: postc_metric [10:00] */ 27992 #define DSC3B0_SM_STATUS1_POSTC_METRIC_MASK 0x07ff 27993 #define DSC3B0_SM_STATUS1_POSTC_METRIC_ALIGN 0 27994 #define DSC3B0_SM_STATUS1_POSTC_METRIC_BITS 11 27995 #define DSC3B0_SM_STATUS1_POSTC_METRIC_SHIFT 0 27996 27997 27998 /**************************************************************************** 27999 * Dsc3b0 :: sm_status2 28000 */ 28001 /* Dsc3b0 :: sm_status2 :: reserved_for_eco0 [15:15] */ 28002 #define DSC3B0_SM_STATUS2_RESERVED_FOR_ECO0_MASK 0x8000 28003 #define DSC3B0_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 28004 #define DSC3B0_SM_STATUS2_RESERVED_FOR_ECO0_BITS 1 28005 #define DSC3B0_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT 15 28006 28007 /* Dsc3b0 :: sm_status2 :: slicer_offset_po [14:10] */ 28008 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_PO_MASK 0x7c00 28009 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_PO_ALIGN 0 28010 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_PO_BITS 5 28011 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_PO_SHIFT 10 28012 28013 /* Dsc3b0 :: sm_status2 :: slicer_offset_zo [09:05] */ 28014 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_ZO_MASK 0x03e0 28015 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN 0 28016 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_ZO_BITS 5 28017 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT 5 28018 28019 /* Dsc3b0 :: sm_status2 :: slicer_offset_mo [04:00] */ 28020 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_MO_MASK 0x001f 28021 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_MO_ALIGN 0 28022 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_MO_BITS 5 28023 #define DSC3B0_SM_STATUS2_SLICER_OFFSET_MO_SHIFT 0 28024 28025 28026 /**************************************************************************** 28027 * Dsc3b0 :: sm_status3 28028 */ 28029 /* Dsc3b0 :: sm_status3 :: reserved_for_eco0 [15:15] */ 28030 #define DSC3B0_SM_STATUS3_RESERVED_FOR_ECO0_MASK 0x8000 28031 #define DSC3B0_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 28032 #define DSC3B0_SM_STATUS3_RESERVED_FOR_ECO0_BITS 1 28033 #define DSC3B0_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT 15 28034 28035 /* Dsc3b0 :: sm_status3 :: slicer_offset_pe [14:10] */ 28036 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_PE_MASK 0x7c00 28037 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_PE_ALIGN 0 28038 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_PE_BITS 5 28039 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_PE_SHIFT 10 28040 28041 /* Dsc3b0 :: sm_status3 :: slicer_offset_ze [09:05] */ 28042 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_ZE_MASK 0x03e0 28043 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN 0 28044 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_ZE_BITS 5 28045 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT 5 28046 28047 /* Dsc3b0 :: sm_status3 :: slicer_offset_me [04:00] */ 28048 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_ME_MASK 0x001f 28049 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_ME_ALIGN 0 28050 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_ME_BITS 5 28051 #define DSC3B0_SM_STATUS3_SLICER_OFFSET_ME_SHIFT 0 28052 28053 28054 /**************************************************************************** 28055 * Dsc3b0 :: sm_status4 28056 */ 28057 /* Dsc3b0 :: sm_status4 :: reserved_for_eco0 [15:09] */ 28058 #define DSC3B0_SM_STATUS4_RESERVED_FOR_ECO0_MASK 0xfe00 28059 #define DSC3B0_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN 0 28060 #define DSC3B0_SM_STATUS4_RESERVED_FOR_ECO0_BITS 7 28061 #define DSC3B0_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT 9 28062 28063 /* Dsc3b0 :: sm_status4 :: dfe_max [08:08] */ 28064 #define DSC3B0_SM_STATUS4_DFE_MAX_MASK 0x0100 28065 #define DSC3B0_SM_STATUS4_DFE_MAX_ALIGN 0 28066 #define DSC3B0_SM_STATUS4_DFE_MAX_BITS 1 28067 #define DSC3B0_SM_STATUS4_DFE_MAX_SHIFT 8 28068 28069 /* Dsc3b0 :: sm_status4 :: dfe_min [07:07] */ 28070 #define DSC3B0_SM_STATUS4_DFE_MIN_MASK 0x0080 28071 #define DSC3B0_SM_STATUS4_DFE_MIN_ALIGN 0 28072 #define DSC3B0_SM_STATUS4_DFE_MIN_BITS 1 28073 #define DSC3B0_SM_STATUS4_DFE_MIN_SHIFT 7 28074 28075 /* Dsc3b0 :: sm_status4 :: vga_max [06:06] */ 28076 #define DSC3B0_SM_STATUS4_VGA_MAX_MASK 0x0040 28077 #define DSC3B0_SM_STATUS4_VGA_MAX_ALIGN 0 28078 #define DSC3B0_SM_STATUS4_VGA_MAX_BITS 1 28079 #define DSC3B0_SM_STATUS4_VGA_MAX_SHIFT 6 28080 28081 /* Dsc3b0 :: sm_status4 :: vga_min [05:05] */ 28082 #define DSC3B0_SM_STATUS4_VGA_MIN_MASK 0x0020 28083 #define DSC3B0_SM_STATUS4_VGA_MIN_ALIGN 0 28084 #define DSC3B0_SM_STATUS4_VGA_MIN_BITS 1 28085 #define DSC3B0_SM_STATUS4_VGA_MIN_SHIFT 5 28086 28087 /* Dsc3b0 :: sm_status4 :: pf_max [04:04] */ 28088 #define DSC3B0_SM_STATUS4_PF_MAX_MASK 0x0010 28089 #define DSC3B0_SM_STATUS4_PF_MAX_ALIGN 0 28090 #define DSC3B0_SM_STATUS4_PF_MAX_BITS 1 28091 #define DSC3B0_SM_STATUS4_PF_MAX_SHIFT 4 28092 28093 /* Dsc3b0 :: sm_status4 :: pf_min [03:03] */ 28094 #define DSC3B0_SM_STATUS4_PF_MIN_MASK 0x0008 28095 #define DSC3B0_SM_STATUS4_PF_MIN_ALIGN 0 28096 #define DSC3B0_SM_STATUS4_PF_MIN_BITS 1 28097 #define DSC3B0_SM_STATUS4_PF_MIN_SHIFT 3 28098 28099 /* Dsc3b0 :: sm_status4 :: pf_ctrl [02:00] */ 28100 #define DSC3B0_SM_STATUS4_PF_CTRL_MASK 0x0007 28101 #define DSC3B0_SM_STATUS4_PF_CTRL_ALIGN 0 28102 #define DSC3B0_SM_STATUS4_PF_CTRL_BITS 3 28103 #define DSC3B0_SM_STATUS4_PF_CTRL_SHIFT 0 28104 28105 28106 /**************************************************************************** 28107 * Dsc3b0 :: ana_status0 28108 */ 28109 /* Dsc3b0 :: ana_status0 :: reserved_for_eco0 [15:04] */ 28110 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 28111 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 28112 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_BITS 12 28113 #define DSC3B0_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 28114 28115 /* Dsc3b0 :: ana_status0 :: pd_ch_p1 [03:03] */ 28116 #define DSC3B0_ANA_STATUS0_PD_CH_P1_MASK 0x0008 28117 #define DSC3B0_ANA_STATUS0_PD_CH_P1_ALIGN 0 28118 #define DSC3B0_ANA_STATUS0_PD_CH_P1_BITS 1 28119 #define DSC3B0_ANA_STATUS0_PD_CH_P1_SHIFT 3 28120 28121 /* Dsc3b0 :: ana_status0 :: en_dfe_clk [02:02] */ 28122 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_MASK 0x0004 28123 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_ALIGN 0 28124 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_BITS 1 28125 #define DSC3B0_ANA_STATUS0_EN_DFE_CLK_SHIFT 2 28126 28127 /* Dsc3b0 :: ana_status0 :: en_hgain [01:01] */ 28128 #define DSC3B0_ANA_STATUS0_EN_HGAIN_MASK 0x0002 28129 #define DSC3B0_ANA_STATUS0_EN_HGAIN_ALIGN 0 28130 #define DSC3B0_ANA_STATUS0_EN_HGAIN_BITS 1 28131 #define DSC3B0_ANA_STATUS0_EN_HGAIN_SHIFT 1 28132 28133 /* Dsc3b0 :: ana_status0 :: offset_pd [00:00] */ 28134 #define DSC3B0_ANA_STATUS0_OFFSET_PD_MASK 0x0001 28135 #define DSC3B0_ANA_STATUS0_OFFSET_PD_ALIGN 0 28136 #define DSC3B0_ANA_STATUS0_OFFSET_PD_BITS 1 28137 #define DSC3B0_ANA_STATUS0_OFFSET_PD_SHIFT 0 28138 28139 28140 /**************************************************************************** 28141 * Dsc3b0 :: sm_status5 28142 */ 28143 /* Dsc3b0 :: sm_status5 :: reserved_for_eco0 [15:11] */ 28144 #define DSC3B0_SM_STATUS5_RESERVED_FOR_ECO0_MASK 0xf800 28145 #define DSC3B0_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN 0 28146 #define DSC3B0_SM_STATUS5_RESERVED_FOR_ECO0_BITS 5 28147 #define DSC3B0_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT 11 28148 28149 /* Dsc3b0 :: sm_status5 :: trnsum_br_vga [10:00] */ 28150 #define DSC3B0_SM_STATUS5_TRNSUM_BR_VGA_MASK 0x07ff 28151 #define DSC3B0_SM_STATUS5_TRNSUM_BR_VGA_ALIGN 0 28152 #define DSC3B0_SM_STATUS5_TRNSUM_BR_VGA_BITS 11 28153 #define DSC3B0_SM_STATUS5_TRNSUM_BR_VGA_SHIFT 0 28154 28155 28156 /**************************************************************************** 28157 * Dsc3b0 :: sm_status6 28158 */ 28159 /* Dsc3b0 :: sm_status6 :: reserved_for_eco0 [15:11] */ 28160 #define DSC3B0_SM_STATUS6_RESERVED_FOR_ECO0_MASK 0xf800 28161 #define DSC3B0_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN 0 28162 #define DSC3B0_SM_STATUS6_RESERVED_FOR_ECO0_BITS 5 28163 #define DSC3B0_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT 11 28164 28165 /* Dsc3b0 :: sm_status6 :: trnsum_pf [10:00] */ 28166 #define DSC3B0_SM_STATUS6_TRNSUM_PF_MASK 0x07ff 28167 #define DSC3B0_SM_STATUS6_TRNSUM_PF_ALIGN 0 28168 #define DSC3B0_SM_STATUS6_TRNSUM_PF_BITS 11 28169 #define DSC3B0_SM_STATUS6_TRNSUM_PF_SHIFT 0 28170 28171 28172 /**************************************************************************** 28173 * Hypercore_USER_Dsc3b1 28174 */ 28175 /**************************************************************************** 28176 * Dsc3b1 :: cdr_status0 28177 */ 28178 /* Dsc3b1 :: cdr_status0 :: integ_reg [15:00] */ 28179 #define DSC3B1_CDR_STATUS0_INTEG_REG_MASK 0xffff 28180 #define DSC3B1_CDR_STATUS0_INTEG_REG_ALIGN 0 28181 #define DSC3B1_CDR_STATUS0_INTEG_REG_BITS 16 28182 #define DSC3B1_CDR_STATUS0_INTEG_REG_SHIFT 0 28183 28184 28185 /**************************************************************************** 28186 * Dsc3b1 :: cdr_status1 28187 */ 28188 /* Dsc3b1 :: cdr_status1 :: integ_reg_xfer [15:00] */ 28189 #define DSC3B1_CDR_STATUS1_INTEG_REG_XFER_MASK 0xffff 28190 #define DSC3B1_CDR_STATUS1_INTEG_REG_XFER_ALIGN 0 28191 #define DSC3B1_CDR_STATUS1_INTEG_REG_XFER_BITS 16 28192 #define DSC3B1_CDR_STATUS1_INTEG_REG_XFER_SHIFT 0 28193 28194 28195 /**************************************************************************** 28196 * Dsc3b1 :: cdr_status2 28197 */ 28198 /* Dsc3b1 :: cdr_status2 :: reserved_for_eco0 [15:11] */ 28199 #define DSC3B1_CDR_STATUS2_RESERVED_FOR_ECO0_MASK 0xf800 28200 #define DSC3B1_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 28201 #define DSC3B1_CDR_STATUS2_RESERVED_FOR_ECO0_BITS 5 28202 #define DSC3B1_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT 11 28203 28204 /* Dsc3b1 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */ 28205 #define DSC3B1_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK 0x0400 28206 #define DSC3B1_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN 0 28207 #define DSC3B1_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS 1 28208 #define DSC3B1_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT 10 28209 28210 /* Dsc3b1 :: cdr_status2 :: br_cdr_enabled [09:09] */ 28211 #define DSC3B1_CDR_STATUS2_BR_CDR_ENABLED_MASK 0x0200 28212 #define DSC3B1_CDR_STATUS2_BR_CDR_ENABLED_ALIGN 0 28213 #define DSC3B1_CDR_STATUS2_BR_CDR_ENABLED_BITS 1 28214 #define DSC3B1_CDR_STATUS2_BR_CDR_ENABLED_SHIFT 9 28215 28216 /* Dsc3b1 :: cdr_status2 :: oscdr_mode [08:06] */ 28217 #define DSC3B1_CDR_STATUS2_OSCDR_MODE_MASK 0x01c0 28218 #define DSC3B1_CDR_STATUS2_OSCDR_MODE_ALIGN 0 28219 #define DSC3B1_CDR_STATUS2_OSCDR_MODE_BITS 3 28220 #define DSC3B1_CDR_STATUS2_OSCDR_MODE_SHIFT 6 28221 28222 /* Dsc3b1 :: cdr_status2 :: phase_err [05:00] */ 28223 #define DSC3B1_CDR_STATUS2_PHASE_ERR_MASK 0x003f 28224 #define DSC3B1_CDR_STATUS2_PHASE_ERR_ALIGN 0 28225 #define DSC3B1_CDR_STATUS2_PHASE_ERR_BITS 6 28226 #define DSC3B1_CDR_STATUS2_PHASE_ERR_SHIFT 0 28227 28228 28229 /**************************************************************************** 28230 * Dsc3b1 :: pi_status0 28231 */ 28232 /* Dsc3b1 :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */ 28233 #define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL0_MASK 0x8000 28234 #define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN 0 28235 #define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL0_BITS 1 28236 #define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT 15 28237 28238 /* Dsc3b1 :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */ 28239 #define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL90_MASK 0x4000 28240 #define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN 0 28241 #define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL90_BITS 1 28242 #define DSC3B1_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT 14 28243 28244 /* Dsc3b1 :: pi_status0 :: clk90_phase_offset [13:07] */ 28245 #define DSC3B1_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 28246 #define DSC3B1_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 28247 #define DSC3B1_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 28248 #define DSC3B1_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 28249 28250 /* Dsc3b1 :: pi_status0 :: phase_cntr [06:00] */ 28251 #define DSC3B1_PI_STATUS0_PHASE_CNTR_MASK 0x007f 28252 #define DSC3B1_PI_STATUS0_PHASE_CNTR_ALIGN 0 28253 #define DSC3B1_PI_STATUS0_PHASE_CNTR_BITS 7 28254 #define DSC3B1_PI_STATUS0_PHASE_CNTR_SHIFT 0 28255 28256 28257 /**************************************************************************** 28258 * Dsc3b1 :: pi_status1 28259 */ 28260 /* union - case pi_Single0_lsb [15:00] */ 28261 /* Dsc3b1 :: pi_status1 :: Single0_lsb [15:00] */ 28262 #define DSC3B1_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK 0xffff 28263 #define DSC3B1_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN 0 28264 #define DSC3B1_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS 16 28265 #define DSC3B1_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT 0 28266 28267 28268 /* union - case pi_Single0_msb [15:00] */ 28269 /* Dsc3b1 :: pi_status1 :: Single0_msb [15:00] */ 28270 #define DSC3B1_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK 0xffff 28271 #define DSC3B1_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN 0 28272 #define DSC3B1_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS 16 28273 #define DSC3B1_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT 0 28274 28275 28276 /* union - case pi_Sequence0_lsb [15:00] */ 28277 /* Dsc3b1 :: pi_status1 :: Sequence0_lsb [15:00] */ 28278 #define DSC3B1_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK 0xffff 28279 #define DSC3B1_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN 0 28280 #define DSC3B1_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS 16 28281 #define DSC3B1_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT 0 28282 28283 28284 /* union - case pi_Sequence0_msb [15:00] */ 28285 /* Dsc3b1 :: pi_status1 :: Sequence0_msb [15:00] */ 28286 #define DSC3B1_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK 0xffff 28287 #define DSC3B1_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN 0 28288 #define DSC3B1_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS 16 28289 #define DSC3B1_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT 0 28290 28291 28292 /* union - case pi_Single90_lsb [15:00] */ 28293 /* Dsc3b1 :: pi_status1 :: Single90_lsb [15:00] */ 28294 #define DSC3B1_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK 0xffff 28295 #define DSC3B1_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN 0 28296 #define DSC3B1_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS 16 28297 #define DSC3B1_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT 0 28298 28299 28300 /* union - case pi_Single90_msb [15:00] */ 28301 /* Dsc3b1 :: pi_status1 :: Single90_msb [15:00] */ 28302 #define DSC3B1_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK 0xffff 28303 #define DSC3B1_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN 0 28304 #define DSC3B1_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS 16 28305 #define DSC3B1_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT 0 28306 28307 28308 /* union - case pi_Sequence90_lsb [15:00] */ 28309 /* Dsc3b1 :: pi_status1 :: Sequence90_lsb [15:00] */ 28310 #define DSC3B1_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK 0xffff 28311 #define DSC3B1_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN 0 28312 #define DSC3B1_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS 16 28313 #define DSC3B1_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT 0 28314 28315 28316 /* union - case pi_Sequence90_msb [15:00] */ 28317 /* Dsc3b1 :: pi_status1 :: Sequence90_msb [15:00] */ 28318 #define DSC3B1_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK 0xffff 28319 #define DSC3B1_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN 0 28320 #define DSC3B1_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS 16 28321 #define DSC3B1_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT 0 28322 28323 28324 28325 /**************************************************************************** 28326 * Dsc3b1 :: dfe_vga_status0 28327 */ 28328 /* Dsc3b1 :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */ 28329 #define DSC3B1_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK 0xf800 28330 #define DSC3B1_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 28331 #define DSC3B1_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS 5 28332 #define DSC3B1_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT 11 28333 28334 /* Dsc3b1 :: dfe_vga_status0 :: vga_sum [10:06] */ 28335 #define DSC3B1_DFE_VGA_STATUS0_VGA_SUM_MASK 0x07c0 28336 #define DSC3B1_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 28337 #define DSC3B1_DFE_VGA_STATUS0_VGA_SUM_BITS 5 28338 #define DSC3B1_DFE_VGA_STATUS0_VGA_SUM_SHIFT 6 28339 28340 /* Dsc3b1 :: dfe_vga_status0 :: dfe_tap_bin [05:00] */ 28341 #define DSC3B1_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK 0x003f 28342 #define DSC3B1_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN 0 28343 #define DSC3B1_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS 6 28344 #define DSC3B1_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT 0 28345 28346 28347 /**************************************************************************** 28348 * Dsc3b1 :: dfe_vga_status1 28349 */ 28350 /* Dsc3b1 :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */ 28351 #define DSC3B1_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 28352 #define DSC3B1_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 28353 #define DSC3B1_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS 5 28354 #define DSC3B1_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 28355 28356 /* Dsc3b1 :: dfe_vga_status1 :: trnsum [10:00] */ 28357 #define DSC3B1_DFE_VGA_STATUS1_TRNSUM_MASK 0x07ff 28358 #define DSC3B1_DFE_VGA_STATUS1_TRNSUM_ALIGN 0 28359 #define DSC3B1_DFE_VGA_STATUS1_TRNSUM_BITS 11 28360 #define DSC3B1_DFE_VGA_STATUS1_TRNSUM_SHIFT 0 28361 28362 28363 /**************************************************************************** 28364 * Dsc3b1 :: sm_status0 28365 */ 28366 /* Dsc3b1 :: sm_status0 :: reserved_for_eco0 [15:14] */ 28367 #define DSC3B1_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 28368 #define DSC3B1_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 28369 #define DSC3B1_SM_STATUS0_RESERVED_FOR_ECO0_BITS 2 28370 #define DSC3B1_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 28371 28372 /* Dsc3b1 :: sm_status0 :: tuning_done [13:13] */ 28373 #define DSC3B1_SM_STATUS0_TUNING_DONE_MASK 0x2000 28374 #define DSC3B1_SM_STATUS0_TUNING_DONE_ALIGN 0 28375 #define DSC3B1_SM_STATUS0_TUNING_DONE_BITS 1 28376 #define DSC3B1_SM_STATUS0_TUNING_DONE_SHIFT 13 28377 28378 /* Dsc3b1 :: sm_status0 :: srch_state [12:09] */ 28379 #define DSC3B1_SM_STATUS0_SRCH_STATE_MASK 0x1e00 28380 #define DSC3B1_SM_STATUS0_SRCH_STATE_ALIGN 0 28381 #define DSC3B1_SM_STATUS0_SRCH_STATE_BITS 4 28382 #define DSC3B1_SM_STATUS0_SRCH_STATE_SHIFT 9 28383 28384 /* Dsc3b1 :: sm_status0 :: tuning_state [08:04] */ 28385 #define DSC3B1_SM_STATUS0_TUNING_STATE_MASK 0x01f0 28386 #define DSC3B1_SM_STATUS0_TUNING_STATE_ALIGN 0 28387 #define DSC3B1_SM_STATUS0_TUNING_STATE_BITS 5 28388 #define DSC3B1_SM_STATUS0_TUNING_STATE_SHIFT 4 28389 28390 /* Dsc3b1 :: sm_status0 :: dsc_state [03:00] */ 28391 #define DSC3B1_SM_STATUS0_DSC_STATE_MASK 0x000f 28392 #define DSC3B1_SM_STATUS0_DSC_STATE_ALIGN 0 28393 #define DSC3B1_SM_STATUS0_DSC_STATE_BITS 4 28394 #define DSC3B1_SM_STATUS0_DSC_STATE_SHIFT 0 28395 28396 28397 /**************************************************************************** 28398 * Dsc3b1 :: sm_status1 28399 */ 28400 /* Dsc3b1 :: sm_status1 :: reserved_for_eco0 [15:11] */ 28401 #define DSC3B1_SM_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 28402 #define DSC3B1_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 28403 #define DSC3B1_SM_STATUS1_RESERVED_FOR_ECO0_BITS 5 28404 #define DSC3B1_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 28405 28406 /* Dsc3b1 :: sm_status1 :: postc_metric [10:00] */ 28407 #define DSC3B1_SM_STATUS1_POSTC_METRIC_MASK 0x07ff 28408 #define DSC3B1_SM_STATUS1_POSTC_METRIC_ALIGN 0 28409 #define DSC3B1_SM_STATUS1_POSTC_METRIC_BITS 11 28410 #define DSC3B1_SM_STATUS1_POSTC_METRIC_SHIFT 0 28411 28412 28413 /**************************************************************************** 28414 * Dsc3b1 :: sm_status2 28415 */ 28416 /* Dsc3b1 :: sm_status2 :: reserved_for_eco0 [15:15] */ 28417 #define DSC3B1_SM_STATUS2_RESERVED_FOR_ECO0_MASK 0x8000 28418 #define DSC3B1_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 28419 #define DSC3B1_SM_STATUS2_RESERVED_FOR_ECO0_BITS 1 28420 #define DSC3B1_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT 15 28421 28422 /* Dsc3b1 :: sm_status2 :: slicer_offset_po [14:10] */ 28423 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_PO_MASK 0x7c00 28424 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_PO_ALIGN 0 28425 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_PO_BITS 5 28426 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_PO_SHIFT 10 28427 28428 /* Dsc3b1 :: sm_status2 :: slicer_offset_zo [09:05] */ 28429 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_ZO_MASK 0x03e0 28430 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN 0 28431 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_ZO_BITS 5 28432 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT 5 28433 28434 /* Dsc3b1 :: sm_status2 :: slicer_offset_mo [04:00] */ 28435 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_MO_MASK 0x001f 28436 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_MO_ALIGN 0 28437 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_MO_BITS 5 28438 #define DSC3B1_SM_STATUS2_SLICER_OFFSET_MO_SHIFT 0 28439 28440 28441 /**************************************************************************** 28442 * Dsc3b1 :: sm_status3 28443 */ 28444 /* Dsc3b1 :: sm_status3 :: reserved_for_eco0 [15:15] */ 28445 #define DSC3B1_SM_STATUS3_RESERVED_FOR_ECO0_MASK 0x8000 28446 #define DSC3B1_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 28447 #define DSC3B1_SM_STATUS3_RESERVED_FOR_ECO0_BITS 1 28448 #define DSC3B1_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT 15 28449 28450 /* Dsc3b1 :: sm_status3 :: slicer_offset_pe [14:10] */ 28451 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_PE_MASK 0x7c00 28452 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_PE_ALIGN 0 28453 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_PE_BITS 5 28454 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_PE_SHIFT 10 28455 28456 /* Dsc3b1 :: sm_status3 :: slicer_offset_ze [09:05] */ 28457 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_ZE_MASK 0x03e0 28458 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN 0 28459 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_ZE_BITS 5 28460 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT 5 28461 28462 /* Dsc3b1 :: sm_status3 :: slicer_offset_me [04:00] */ 28463 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_ME_MASK 0x001f 28464 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_ME_ALIGN 0 28465 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_ME_BITS 5 28466 #define DSC3B1_SM_STATUS3_SLICER_OFFSET_ME_SHIFT 0 28467 28468 28469 /**************************************************************************** 28470 * Dsc3b1 :: sm_status4 28471 */ 28472 /* Dsc3b1 :: sm_status4 :: reserved_for_eco0 [15:09] */ 28473 #define DSC3B1_SM_STATUS4_RESERVED_FOR_ECO0_MASK 0xfe00 28474 #define DSC3B1_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN 0 28475 #define DSC3B1_SM_STATUS4_RESERVED_FOR_ECO0_BITS 7 28476 #define DSC3B1_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT 9 28477 28478 /* Dsc3b1 :: sm_status4 :: dfe_max [08:08] */ 28479 #define DSC3B1_SM_STATUS4_DFE_MAX_MASK 0x0100 28480 #define DSC3B1_SM_STATUS4_DFE_MAX_ALIGN 0 28481 #define DSC3B1_SM_STATUS4_DFE_MAX_BITS 1 28482 #define DSC3B1_SM_STATUS4_DFE_MAX_SHIFT 8 28483 28484 /* Dsc3b1 :: sm_status4 :: dfe_min [07:07] */ 28485 #define DSC3B1_SM_STATUS4_DFE_MIN_MASK 0x0080 28486 #define DSC3B1_SM_STATUS4_DFE_MIN_ALIGN 0 28487 #define DSC3B1_SM_STATUS4_DFE_MIN_BITS 1 28488 #define DSC3B1_SM_STATUS4_DFE_MIN_SHIFT 7 28489 28490 /* Dsc3b1 :: sm_status4 :: vga_max [06:06] */ 28491 #define DSC3B1_SM_STATUS4_VGA_MAX_MASK 0x0040 28492 #define DSC3B1_SM_STATUS4_VGA_MAX_ALIGN 0 28493 #define DSC3B1_SM_STATUS4_VGA_MAX_BITS 1 28494 #define DSC3B1_SM_STATUS4_VGA_MAX_SHIFT 6 28495 28496 /* Dsc3b1 :: sm_status4 :: vga_min [05:05] */ 28497 #define DSC3B1_SM_STATUS4_VGA_MIN_MASK 0x0020 28498 #define DSC3B1_SM_STATUS4_VGA_MIN_ALIGN 0 28499 #define DSC3B1_SM_STATUS4_VGA_MIN_BITS 1 28500 #define DSC3B1_SM_STATUS4_VGA_MIN_SHIFT 5 28501 28502 /* Dsc3b1 :: sm_status4 :: pf_max [04:04] */ 28503 #define DSC3B1_SM_STATUS4_PF_MAX_MASK 0x0010 28504 #define DSC3B1_SM_STATUS4_PF_MAX_ALIGN 0 28505 #define DSC3B1_SM_STATUS4_PF_MAX_BITS 1 28506 #define DSC3B1_SM_STATUS4_PF_MAX_SHIFT 4 28507 28508 /* Dsc3b1 :: sm_status4 :: pf_min [03:03] */ 28509 #define DSC3B1_SM_STATUS4_PF_MIN_MASK 0x0008 28510 #define DSC3B1_SM_STATUS4_PF_MIN_ALIGN 0 28511 #define DSC3B1_SM_STATUS4_PF_MIN_BITS 1 28512 #define DSC3B1_SM_STATUS4_PF_MIN_SHIFT 3 28513 28514 /* Dsc3b1 :: sm_status4 :: pf_ctrl [02:00] */ 28515 #define DSC3B1_SM_STATUS4_PF_CTRL_MASK 0x0007 28516 #define DSC3B1_SM_STATUS4_PF_CTRL_ALIGN 0 28517 #define DSC3B1_SM_STATUS4_PF_CTRL_BITS 3 28518 #define DSC3B1_SM_STATUS4_PF_CTRL_SHIFT 0 28519 28520 28521 /**************************************************************************** 28522 * Dsc3b1 :: ana_status0 28523 */ 28524 /* Dsc3b1 :: ana_status0 :: reserved_for_eco0 [15:04] */ 28525 #define DSC3B1_ANA_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 28526 #define DSC3B1_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 28527 #define DSC3B1_ANA_STATUS0_RESERVED_FOR_ECO0_BITS 12 28528 #define DSC3B1_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 28529 28530 /* Dsc3b1 :: ana_status0 :: pd_ch_p1 [03:03] */ 28531 #define DSC3B1_ANA_STATUS0_PD_CH_P1_MASK 0x0008 28532 #define DSC3B1_ANA_STATUS0_PD_CH_P1_ALIGN 0 28533 #define DSC3B1_ANA_STATUS0_PD_CH_P1_BITS 1 28534 #define DSC3B1_ANA_STATUS0_PD_CH_P1_SHIFT 3 28535 28536 /* Dsc3b1 :: ana_status0 :: en_dfe_clk [02:02] */ 28537 #define DSC3B1_ANA_STATUS0_EN_DFE_CLK_MASK 0x0004 28538 #define DSC3B1_ANA_STATUS0_EN_DFE_CLK_ALIGN 0 28539 #define DSC3B1_ANA_STATUS0_EN_DFE_CLK_BITS 1 28540 #define DSC3B1_ANA_STATUS0_EN_DFE_CLK_SHIFT 2 28541 28542 /* Dsc3b1 :: ana_status0 :: en_hgain [01:01] */ 28543 #define DSC3B1_ANA_STATUS0_EN_HGAIN_MASK 0x0002 28544 #define DSC3B1_ANA_STATUS0_EN_HGAIN_ALIGN 0 28545 #define DSC3B1_ANA_STATUS0_EN_HGAIN_BITS 1 28546 #define DSC3B1_ANA_STATUS0_EN_HGAIN_SHIFT 1 28547 28548 /* Dsc3b1 :: ana_status0 :: offset_pd [00:00] */ 28549 #define DSC3B1_ANA_STATUS0_OFFSET_PD_MASK 0x0001 28550 #define DSC3B1_ANA_STATUS0_OFFSET_PD_ALIGN 0 28551 #define DSC3B1_ANA_STATUS0_OFFSET_PD_BITS 1 28552 #define DSC3B1_ANA_STATUS0_OFFSET_PD_SHIFT 0 28553 28554 28555 /**************************************************************************** 28556 * Dsc3b1 :: sm_status5 28557 */ 28558 /* Dsc3b1 :: sm_status5 :: reserved_for_eco0 [15:11] */ 28559 #define DSC3B1_SM_STATUS5_RESERVED_FOR_ECO0_MASK 0xf800 28560 #define DSC3B1_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN 0 28561 #define DSC3B1_SM_STATUS5_RESERVED_FOR_ECO0_BITS 5 28562 #define DSC3B1_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT 11 28563 28564 /* Dsc3b1 :: sm_status5 :: trnsum_br_vga [10:00] */ 28565 #define DSC3B1_SM_STATUS5_TRNSUM_BR_VGA_MASK 0x07ff 28566 #define DSC3B1_SM_STATUS5_TRNSUM_BR_VGA_ALIGN 0 28567 #define DSC3B1_SM_STATUS5_TRNSUM_BR_VGA_BITS 11 28568 #define DSC3B1_SM_STATUS5_TRNSUM_BR_VGA_SHIFT 0 28569 28570 28571 /**************************************************************************** 28572 * Dsc3b1 :: sm_status6 28573 */ 28574 /* Dsc3b1 :: sm_status6 :: reserved_for_eco0 [15:11] */ 28575 #define DSC3B1_SM_STATUS6_RESERVED_FOR_ECO0_MASK 0xf800 28576 #define DSC3B1_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN 0 28577 #define DSC3B1_SM_STATUS6_RESERVED_FOR_ECO0_BITS 5 28578 #define DSC3B1_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT 11 28579 28580 /* Dsc3b1 :: sm_status6 :: trnsum_pf [10:00] */ 28581 #define DSC3B1_SM_STATUS6_TRNSUM_PF_MASK 0x07ff 28582 #define DSC3B1_SM_STATUS6_TRNSUM_PF_ALIGN 0 28583 #define DSC3B1_SM_STATUS6_TRNSUM_PF_BITS 11 28584 #define DSC3B1_SM_STATUS6_TRNSUM_PF_SHIFT 0 28585 28586 28587 /**************************************************************************** 28588 * Hypercore_USER_Dsc3b2 28589 */ 28590 /**************************************************************************** 28591 * Dsc3b2 :: cdr_status0 28592 */ 28593 /* Dsc3b2 :: cdr_status0 :: integ_reg [15:00] */ 28594 #define DSC3B2_CDR_STATUS0_INTEG_REG_MASK 0xffff 28595 #define DSC3B2_CDR_STATUS0_INTEG_REG_ALIGN 0 28596 #define DSC3B2_CDR_STATUS0_INTEG_REG_BITS 16 28597 #define DSC3B2_CDR_STATUS0_INTEG_REG_SHIFT 0 28598 28599 28600 /**************************************************************************** 28601 * Dsc3b2 :: cdr_status1 28602 */ 28603 /* Dsc3b2 :: cdr_status1 :: integ_reg_xfer [15:00] */ 28604 #define DSC3B2_CDR_STATUS1_INTEG_REG_XFER_MASK 0xffff 28605 #define DSC3B2_CDR_STATUS1_INTEG_REG_XFER_ALIGN 0 28606 #define DSC3B2_CDR_STATUS1_INTEG_REG_XFER_BITS 16 28607 #define DSC3B2_CDR_STATUS1_INTEG_REG_XFER_SHIFT 0 28608 28609 28610 /**************************************************************************** 28611 * Dsc3b2 :: cdr_status2 28612 */ 28613 /* Dsc3b2 :: cdr_status2 :: reserved_for_eco0 [15:11] */ 28614 #define DSC3B2_CDR_STATUS2_RESERVED_FOR_ECO0_MASK 0xf800 28615 #define DSC3B2_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 28616 #define DSC3B2_CDR_STATUS2_RESERVED_FOR_ECO0_BITS 5 28617 #define DSC3B2_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT 11 28618 28619 /* Dsc3b2 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */ 28620 #define DSC3B2_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK 0x0400 28621 #define DSC3B2_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN 0 28622 #define DSC3B2_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS 1 28623 #define DSC3B2_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT 10 28624 28625 /* Dsc3b2 :: cdr_status2 :: br_cdr_enabled [09:09] */ 28626 #define DSC3B2_CDR_STATUS2_BR_CDR_ENABLED_MASK 0x0200 28627 #define DSC3B2_CDR_STATUS2_BR_CDR_ENABLED_ALIGN 0 28628 #define DSC3B2_CDR_STATUS2_BR_CDR_ENABLED_BITS 1 28629 #define DSC3B2_CDR_STATUS2_BR_CDR_ENABLED_SHIFT 9 28630 28631 /* Dsc3b2 :: cdr_status2 :: oscdr_mode [08:06] */ 28632 #define DSC3B2_CDR_STATUS2_OSCDR_MODE_MASK 0x01c0 28633 #define DSC3B2_CDR_STATUS2_OSCDR_MODE_ALIGN 0 28634 #define DSC3B2_CDR_STATUS2_OSCDR_MODE_BITS 3 28635 #define DSC3B2_CDR_STATUS2_OSCDR_MODE_SHIFT 6 28636 28637 /* Dsc3b2 :: cdr_status2 :: phase_err [05:00] */ 28638 #define DSC3B2_CDR_STATUS2_PHASE_ERR_MASK 0x003f 28639 #define DSC3B2_CDR_STATUS2_PHASE_ERR_ALIGN 0 28640 #define DSC3B2_CDR_STATUS2_PHASE_ERR_BITS 6 28641 #define DSC3B2_CDR_STATUS2_PHASE_ERR_SHIFT 0 28642 28643 28644 /**************************************************************************** 28645 * Dsc3b2 :: pi_status0 28646 */ 28647 /* Dsc3b2 :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */ 28648 #define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL0_MASK 0x8000 28649 #define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN 0 28650 #define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL0_BITS 1 28651 #define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT 15 28652 28653 /* Dsc3b2 :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */ 28654 #define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL90_MASK 0x4000 28655 #define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN 0 28656 #define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL90_BITS 1 28657 #define DSC3B2_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT 14 28658 28659 /* Dsc3b2 :: pi_status0 :: clk90_phase_offset [13:07] */ 28660 #define DSC3B2_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 28661 #define DSC3B2_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 28662 #define DSC3B2_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 28663 #define DSC3B2_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 28664 28665 /* Dsc3b2 :: pi_status0 :: phase_cntr [06:00] */ 28666 #define DSC3B2_PI_STATUS0_PHASE_CNTR_MASK 0x007f 28667 #define DSC3B2_PI_STATUS0_PHASE_CNTR_ALIGN 0 28668 #define DSC3B2_PI_STATUS0_PHASE_CNTR_BITS 7 28669 #define DSC3B2_PI_STATUS0_PHASE_CNTR_SHIFT 0 28670 28671 28672 /**************************************************************************** 28673 * Dsc3b2 :: pi_status1 28674 */ 28675 /* union - case pi_Single0_lsb [15:00] */ 28676 /* Dsc3b2 :: pi_status1 :: Single0_lsb [15:00] */ 28677 #define DSC3B2_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK 0xffff 28678 #define DSC3B2_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN 0 28679 #define DSC3B2_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS 16 28680 #define DSC3B2_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT 0 28681 28682 28683 /* union - case pi_Single0_msb [15:00] */ 28684 /* Dsc3b2 :: pi_status1 :: Single0_msb [15:00] */ 28685 #define DSC3B2_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK 0xffff 28686 #define DSC3B2_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN 0 28687 #define DSC3B2_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS 16 28688 #define DSC3B2_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT 0 28689 28690 28691 /* union - case pi_Sequence0_lsb [15:00] */ 28692 /* Dsc3b2 :: pi_status1 :: Sequence0_lsb [15:00] */ 28693 #define DSC3B2_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK 0xffff 28694 #define DSC3B2_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN 0 28695 #define DSC3B2_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS 16 28696 #define DSC3B2_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT 0 28697 28698 28699 /* union - case pi_Sequence0_msb [15:00] */ 28700 /* Dsc3b2 :: pi_status1 :: Sequence0_msb [15:00] */ 28701 #define DSC3B2_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK 0xffff 28702 #define DSC3B2_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN 0 28703 #define DSC3B2_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS 16 28704 #define DSC3B2_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT 0 28705 28706 28707 /* union - case pi_Single90_lsb [15:00] */ 28708 /* Dsc3b2 :: pi_status1 :: Single90_lsb [15:00] */ 28709 #define DSC3B2_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK 0xffff 28710 #define DSC3B2_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN 0 28711 #define DSC3B2_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS 16 28712 #define DSC3B2_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT 0 28713 28714 28715 /* union - case pi_Single90_msb [15:00] */ 28716 /* Dsc3b2 :: pi_status1 :: Single90_msb [15:00] */ 28717 #define DSC3B2_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK 0xffff 28718 #define DSC3B2_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN 0 28719 #define DSC3B2_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS 16 28720 #define DSC3B2_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT 0 28721 28722 28723 /* union - case pi_Sequence90_lsb [15:00] */ 28724 /* Dsc3b2 :: pi_status1 :: Sequence90_lsb [15:00] */ 28725 #define DSC3B2_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK 0xffff 28726 #define DSC3B2_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN 0 28727 #define DSC3B2_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS 16 28728 #define DSC3B2_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT 0 28729 28730 28731 /* union - case pi_Sequence90_msb [15:00] */ 28732 /* Dsc3b2 :: pi_status1 :: Sequence90_msb [15:00] */ 28733 #define DSC3B2_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK 0xffff 28734 #define DSC3B2_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN 0 28735 #define DSC3B2_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS 16 28736 #define DSC3B2_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT 0 28737 28738 28739 28740 /**************************************************************************** 28741 * Dsc3b2 :: dfe_vga_status0 28742 */ 28743 /* Dsc3b2 :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */ 28744 #define DSC3B2_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK 0xf800 28745 #define DSC3B2_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 28746 #define DSC3B2_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS 5 28747 #define DSC3B2_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT 11 28748 28749 /* Dsc3b2 :: dfe_vga_status0 :: vga_sum [10:06] */ 28750 #define DSC3B2_DFE_VGA_STATUS0_VGA_SUM_MASK 0x07c0 28751 #define DSC3B2_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 28752 #define DSC3B2_DFE_VGA_STATUS0_VGA_SUM_BITS 5 28753 #define DSC3B2_DFE_VGA_STATUS0_VGA_SUM_SHIFT 6 28754 28755 /* Dsc3b2 :: dfe_vga_status0 :: dfe_tap_bin [05:00] */ 28756 #define DSC3B2_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK 0x003f 28757 #define DSC3B2_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN 0 28758 #define DSC3B2_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS 6 28759 #define DSC3B2_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT 0 28760 28761 28762 /**************************************************************************** 28763 * Dsc3b2 :: dfe_vga_status1 28764 */ 28765 /* Dsc3b2 :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */ 28766 #define DSC3B2_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 28767 #define DSC3B2_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 28768 #define DSC3B2_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS 5 28769 #define DSC3B2_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 28770 28771 /* Dsc3b2 :: dfe_vga_status1 :: trnsum [10:00] */ 28772 #define DSC3B2_DFE_VGA_STATUS1_TRNSUM_MASK 0x07ff 28773 #define DSC3B2_DFE_VGA_STATUS1_TRNSUM_ALIGN 0 28774 #define DSC3B2_DFE_VGA_STATUS1_TRNSUM_BITS 11 28775 #define DSC3B2_DFE_VGA_STATUS1_TRNSUM_SHIFT 0 28776 28777 28778 /**************************************************************************** 28779 * Dsc3b2 :: sm_status0 28780 */ 28781 /* Dsc3b2 :: sm_status0 :: reserved_for_eco0 [15:14] */ 28782 #define DSC3B2_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 28783 #define DSC3B2_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 28784 #define DSC3B2_SM_STATUS0_RESERVED_FOR_ECO0_BITS 2 28785 #define DSC3B2_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 28786 28787 /* Dsc3b2 :: sm_status0 :: tuning_done [13:13] */ 28788 #define DSC3B2_SM_STATUS0_TUNING_DONE_MASK 0x2000 28789 #define DSC3B2_SM_STATUS0_TUNING_DONE_ALIGN 0 28790 #define DSC3B2_SM_STATUS0_TUNING_DONE_BITS 1 28791 #define DSC3B2_SM_STATUS0_TUNING_DONE_SHIFT 13 28792 28793 /* Dsc3b2 :: sm_status0 :: srch_state [12:09] */ 28794 #define DSC3B2_SM_STATUS0_SRCH_STATE_MASK 0x1e00 28795 #define DSC3B2_SM_STATUS0_SRCH_STATE_ALIGN 0 28796 #define DSC3B2_SM_STATUS0_SRCH_STATE_BITS 4 28797 #define DSC3B2_SM_STATUS0_SRCH_STATE_SHIFT 9 28798 28799 /* Dsc3b2 :: sm_status0 :: tuning_state [08:04] */ 28800 #define DSC3B2_SM_STATUS0_TUNING_STATE_MASK 0x01f0 28801 #define DSC3B2_SM_STATUS0_TUNING_STATE_ALIGN 0 28802 #define DSC3B2_SM_STATUS0_TUNING_STATE_BITS 5 28803 #define DSC3B2_SM_STATUS0_TUNING_STATE_SHIFT 4 28804 28805 /* Dsc3b2 :: sm_status0 :: dsc_state [03:00] */ 28806 #define DSC3B2_SM_STATUS0_DSC_STATE_MASK 0x000f 28807 #define DSC3B2_SM_STATUS0_DSC_STATE_ALIGN 0 28808 #define DSC3B2_SM_STATUS0_DSC_STATE_BITS 4 28809 #define DSC3B2_SM_STATUS0_DSC_STATE_SHIFT 0 28810 28811 28812 /**************************************************************************** 28813 * Dsc3b2 :: sm_status1 28814 */ 28815 /* Dsc3b2 :: sm_status1 :: reserved_for_eco0 [15:11] */ 28816 #define DSC3B2_SM_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 28817 #define DSC3B2_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 28818 #define DSC3B2_SM_STATUS1_RESERVED_FOR_ECO0_BITS 5 28819 #define DSC3B2_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 28820 28821 /* Dsc3b2 :: sm_status1 :: postc_metric [10:00] */ 28822 #define DSC3B2_SM_STATUS1_POSTC_METRIC_MASK 0x07ff 28823 #define DSC3B2_SM_STATUS1_POSTC_METRIC_ALIGN 0 28824 #define DSC3B2_SM_STATUS1_POSTC_METRIC_BITS 11 28825 #define DSC3B2_SM_STATUS1_POSTC_METRIC_SHIFT 0 28826 28827 28828 /**************************************************************************** 28829 * Dsc3b2 :: sm_status2 28830 */ 28831 /* Dsc3b2 :: sm_status2 :: reserved_for_eco0 [15:15] */ 28832 #define DSC3B2_SM_STATUS2_RESERVED_FOR_ECO0_MASK 0x8000 28833 #define DSC3B2_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 28834 #define DSC3B2_SM_STATUS2_RESERVED_FOR_ECO0_BITS 1 28835 #define DSC3B2_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT 15 28836 28837 /* Dsc3b2 :: sm_status2 :: slicer_offset_po [14:10] */ 28838 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_PO_MASK 0x7c00 28839 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_PO_ALIGN 0 28840 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_PO_BITS 5 28841 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_PO_SHIFT 10 28842 28843 /* Dsc3b2 :: sm_status2 :: slicer_offset_zo [09:05] */ 28844 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_ZO_MASK 0x03e0 28845 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN 0 28846 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_ZO_BITS 5 28847 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT 5 28848 28849 /* Dsc3b2 :: sm_status2 :: slicer_offset_mo [04:00] */ 28850 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_MO_MASK 0x001f 28851 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_MO_ALIGN 0 28852 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_MO_BITS 5 28853 #define DSC3B2_SM_STATUS2_SLICER_OFFSET_MO_SHIFT 0 28854 28855 28856 /**************************************************************************** 28857 * Dsc3b2 :: sm_status3 28858 */ 28859 /* Dsc3b2 :: sm_status3 :: reserved_for_eco0 [15:15] */ 28860 #define DSC3B2_SM_STATUS3_RESERVED_FOR_ECO0_MASK 0x8000 28861 #define DSC3B2_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 28862 #define DSC3B2_SM_STATUS3_RESERVED_FOR_ECO0_BITS 1 28863 #define DSC3B2_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT 15 28864 28865 /* Dsc3b2 :: sm_status3 :: slicer_offset_pe [14:10] */ 28866 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_PE_MASK 0x7c00 28867 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_PE_ALIGN 0 28868 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_PE_BITS 5 28869 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_PE_SHIFT 10 28870 28871 /* Dsc3b2 :: sm_status3 :: slicer_offset_ze [09:05] */ 28872 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_ZE_MASK 0x03e0 28873 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN 0 28874 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_ZE_BITS 5 28875 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT 5 28876 28877 /* Dsc3b2 :: sm_status3 :: slicer_offset_me [04:00] */ 28878 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_ME_MASK 0x001f 28879 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_ME_ALIGN 0 28880 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_ME_BITS 5 28881 #define DSC3B2_SM_STATUS3_SLICER_OFFSET_ME_SHIFT 0 28882 28883 28884 /**************************************************************************** 28885 * Dsc3b2 :: sm_status4 28886 */ 28887 /* Dsc3b2 :: sm_status4 :: reserved_for_eco0 [15:09] */ 28888 #define DSC3B2_SM_STATUS4_RESERVED_FOR_ECO0_MASK 0xfe00 28889 #define DSC3B2_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN 0 28890 #define DSC3B2_SM_STATUS4_RESERVED_FOR_ECO0_BITS 7 28891 #define DSC3B2_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT 9 28892 28893 /* Dsc3b2 :: sm_status4 :: dfe_max [08:08] */ 28894 #define DSC3B2_SM_STATUS4_DFE_MAX_MASK 0x0100 28895 #define DSC3B2_SM_STATUS4_DFE_MAX_ALIGN 0 28896 #define DSC3B2_SM_STATUS4_DFE_MAX_BITS 1 28897 #define DSC3B2_SM_STATUS4_DFE_MAX_SHIFT 8 28898 28899 /* Dsc3b2 :: sm_status4 :: dfe_min [07:07] */ 28900 #define DSC3B2_SM_STATUS4_DFE_MIN_MASK 0x0080 28901 #define DSC3B2_SM_STATUS4_DFE_MIN_ALIGN 0 28902 #define DSC3B2_SM_STATUS4_DFE_MIN_BITS 1 28903 #define DSC3B2_SM_STATUS4_DFE_MIN_SHIFT 7 28904 28905 /* Dsc3b2 :: sm_status4 :: vga_max [06:06] */ 28906 #define DSC3B2_SM_STATUS4_VGA_MAX_MASK 0x0040 28907 #define DSC3B2_SM_STATUS4_VGA_MAX_ALIGN 0 28908 #define DSC3B2_SM_STATUS4_VGA_MAX_BITS 1 28909 #define DSC3B2_SM_STATUS4_VGA_MAX_SHIFT 6 28910 28911 /* Dsc3b2 :: sm_status4 :: vga_min [05:05] */ 28912 #define DSC3B2_SM_STATUS4_VGA_MIN_MASK 0x0020 28913 #define DSC3B2_SM_STATUS4_VGA_MIN_ALIGN 0 28914 #define DSC3B2_SM_STATUS4_VGA_MIN_BITS 1 28915 #define DSC3B2_SM_STATUS4_VGA_MIN_SHIFT 5 28916 28917 /* Dsc3b2 :: sm_status4 :: pf_max [04:04] */ 28918 #define DSC3B2_SM_STATUS4_PF_MAX_MASK 0x0010 28919 #define DSC3B2_SM_STATUS4_PF_MAX_ALIGN 0 28920 #define DSC3B2_SM_STATUS4_PF_MAX_BITS 1 28921 #define DSC3B2_SM_STATUS4_PF_MAX_SHIFT 4 28922 28923 /* Dsc3b2 :: sm_status4 :: pf_min [03:03] */ 28924 #define DSC3B2_SM_STATUS4_PF_MIN_MASK 0x0008 28925 #define DSC3B2_SM_STATUS4_PF_MIN_ALIGN 0 28926 #define DSC3B2_SM_STATUS4_PF_MIN_BITS 1 28927 #define DSC3B2_SM_STATUS4_PF_MIN_SHIFT 3 28928 28929 /* Dsc3b2 :: sm_status4 :: pf_ctrl [02:00] */ 28930 #define DSC3B2_SM_STATUS4_PF_CTRL_MASK 0x0007 28931 #define DSC3B2_SM_STATUS4_PF_CTRL_ALIGN 0 28932 #define DSC3B2_SM_STATUS4_PF_CTRL_BITS 3 28933 #define DSC3B2_SM_STATUS4_PF_CTRL_SHIFT 0 28934 28935 28936 /**************************************************************************** 28937 * Dsc3b2 :: ana_status0 28938 */ 28939 /* Dsc3b2 :: ana_status0 :: reserved_for_eco0 [15:04] */ 28940 #define DSC3B2_ANA_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 28941 #define DSC3B2_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 28942 #define DSC3B2_ANA_STATUS0_RESERVED_FOR_ECO0_BITS 12 28943 #define DSC3B2_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 28944 28945 /* Dsc3b2 :: ana_status0 :: pd_ch_p1 [03:03] */ 28946 #define DSC3B2_ANA_STATUS0_PD_CH_P1_MASK 0x0008 28947 #define DSC3B2_ANA_STATUS0_PD_CH_P1_ALIGN 0 28948 #define DSC3B2_ANA_STATUS0_PD_CH_P1_BITS 1 28949 #define DSC3B2_ANA_STATUS0_PD_CH_P1_SHIFT 3 28950 28951 /* Dsc3b2 :: ana_status0 :: en_dfe_clk [02:02] */ 28952 #define DSC3B2_ANA_STATUS0_EN_DFE_CLK_MASK 0x0004 28953 #define DSC3B2_ANA_STATUS0_EN_DFE_CLK_ALIGN 0 28954 #define DSC3B2_ANA_STATUS0_EN_DFE_CLK_BITS 1 28955 #define DSC3B2_ANA_STATUS0_EN_DFE_CLK_SHIFT 2 28956 28957 /* Dsc3b2 :: ana_status0 :: en_hgain [01:01] */ 28958 #define DSC3B2_ANA_STATUS0_EN_HGAIN_MASK 0x0002 28959 #define DSC3B2_ANA_STATUS0_EN_HGAIN_ALIGN 0 28960 #define DSC3B2_ANA_STATUS0_EN_HGAIN_BITS 1 28961 #define DSC3B2_ANA_STATUS0_EN_HGAIN_SHIFT 1 28962 28963 /* Dsc3b2 :: ana_status0 :: offset_pd [00:00] */ 28964 #define DSC3B2_ANA_STATUS0_OFFSET_PD_MASK 0x0001 28965 #define DSC3B2_ANA_STATUS0_OFFSET_PD_ALIGN 0 28966 #define DSC3B2_ANA_STATUS0_OFFSET_PD_BITS 1 28967 #define DSC3B2_ANA_STATUS0_OFFSET_PD_SHIFT 0 28968 28969 28970 /**************************************************************************** 28971 * Dsc3b2 :: sm_status5 28972 */ 28973 /* Dsc3b2 :: sm_status5 :: reserved_for_eco0 [15:11] */ 28974 #define DSC3B2_SM_STATUS5_RESERVED_FOR_ECO0_MASK 0xf800 28975 #define DSC3B2_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN 0 28976 #define DSC3B2_SM_STATUS5_RESERVED_FOR_ECO0_BITS 5 28977 #define DSC3B2_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT 11 28978 28979 /* Dsc3b2 :: sm_status5 :: trnsum_br_vga [10:00] */ 28980 #define DSC3B2_SM_STATUS5_TRNSUM_BR_VGA_MASK 0x07ff 28981 #define DSC3B2_SM_STATUS5_TRNSUM_BR_VGA_ALIGN 0 28982 #define DSC3B2_SM_STATUS5_TRNSUM_BR_VGA_BITS 11 28983 #define DSC3B2_SM_STATUS5_TRNSUM_BR_VGA_SHIFT 0 28984 28985 28986 /**************************************************************************** 28987 * Dsc3b2 :: sm_status6 28988 */ 28989 /* Dsc3b2 :: sm_status6 :: reserved_for_eco0 [15:11] */ 28990 #define DSC3B2_SM_STATUS6_RESERVED_FOR_ECO0_MASK 0xf800 28991 #define DSC3B2_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN 0 28992 #define DSC3B2_SM_STATUS6_RESERVED_FOR_ECO0_BITS 5 28993 #define DSC3B2_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT 11 28994 28995 /* Dsc3b2 :: sm_status6 :: trnsum_pf [10:00] */ 28996 #define DSC3B2_SM_STATUS6_TRNSUM_PF_MASK 0x07ff 28997 #define DSC3B2_SM_STATUS6_TRNSUM_PF_ALIGN 0 28998 #define DSC3B2_SM_STATUS6_TRNSUM_PF_BITS 11 28999 #define DSC3B2_SM_STATUS6_TRNSUM_PF_SHIFT 0 29000 29001 29002 /**************************************************************************** 29003 * Hypercore_USER_Dsc3b3 29004 */ 29005 /**************************************************************************** 29006 * Dsc3b3 :: cdr_status0 29007 */ 29008 /* Dsc3b3 :: cdr_status0 :: integ_reg [15:00] */ 29009 #define DSC3B3_CDR_STATUS0_INTEG_REG_MASK 0xffff 29010 #define DSC3B3_CDR_STATUS0_INTEG_REG_ALIGN 0 29011 #define DSC3B3_CDR_STATUS0_INTEG_REG_BITS 16 29012 #define DSC3B3_CDR_STATUS0_INTEG_REG_SHIFT 0 29013 29014 29015 /**************************************************************************** 29016 * Dsc3b3 :: cdr_status1 29017 */ 29018 /* Dsc3b3 :: cdr_status1 :: integ_reg_xfer [15:00] */ 29019 #define DSC3B3_CDR_STATUS1_INTEG_REG_XFER_MASK 0xffff 29020 #define DSC3B3_CDR_STATUS1_INTEG_REG_XFER_ALIGN 0 29021 #define DSC3B3_CDR_STATUS1_INTEG_REG_XFER_BITS 16 29022 #define DSC3B3_CDR_STATUS1_INTEG_REG_XFER_SHIFT 0 29023 29024 29025 /**************************************************************************** 29026 * Dsc3b3 :: cdr_status2 29027 */ 29028 /* Dsc3b3 :: cdr_status2 :: reserved_for_eco0 [15:11] */ 29029 #define DSC3B3_CDR_STATUS2_RESERVED_FOR_ECO0_MASK 0xf800 29030 #define DSC3B3_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 29031 #define DSC3B3_CDR_STATUS2_RESERVED_FOR_ECO0_BITS 5 29032 #define DSC3B3_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT 11 29033 29034 /* Dsc3b3 :: cdr_status2 :: sm_br_cdr_enabled [10:10] */ 29035 #define DSC3B3_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK 0x0400 29036 #define DSC3B3_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN 0 29037 #define DSC3B3_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS 1 29038 #define DSC3B3_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT 10 29039 29040 /* Dsc3b3 :: cdr_status2 :: br_cdr_enabled [09:09] */ 29041 #define DSC3B3_CDR_STATUS2_BR_CDR_ENABLED_MASK 0x0200 29042 #define DSC3B3_CDR_STATUS2_BR_CDR_ENABLED_ALIGN 0 29043 #define DSC3B3_CDR_STATUS2_BR_CDR_ENABLED_BITS 1 29044 #define DSC3B3_CDR_STATUS2_BR_CDR_ENABLED_SHIFT 9 29045 29046 /* Dsc3b3 :: cdr_status2 :: oscdr_mode [08:06] */ 29047 #define DSC3B3_CDR_STATUS2_OSCDR_MODE_MASK 0x01c0 29048 #define DSC3B3_CDR_STATUS2_OSCDR_MODE_ALIGN 0 29049 #define DSC3B3_CDR_STATUS2_OSCDR_MODE_BITS 3 29050 #define DSC3B3_CDR_STATUS2_OSCDR_MODE_SHIFT 6 29051 29052 /* Dsc3b3 :: cdr_status2 :: phase_err [05:00] */ 29053 #define DSC3B3_CDR_STATUS2_PHASE_ERR_MASK 0x003f 29054 #define DSC3B3_CDR_STATUS2_PHASE_ERR_ALIGN 0 29055 #define DSC3B3_CDR_STATUS2_PHASE_ERR_BITS 6 29056 #define DSC3B3_CDR_STATUS2_PHASE_ERR_SHIFT 0 29057 29058 29059 /**************************************************************************** 29060 * Dsc3b3 :: pi_status0 29061 */ 29062 /* Dsc3b3 :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */ 29063 #define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL0_MASK 0x8000 29064 #define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN 0 29065 #define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL0_BITS 1 29066 #define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT 15 29067 29068 /* Dsc3b3 :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */ 29069 #define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL90_MASK 0x4000 29070 #define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN 0 29071 #define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL90_BITS 1 29072 #define DSC3B3_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT 14 29073 29074 /* Dsc3b3 :: pi_status0 :: clk90_phase_offset [13:07] */ 29075 #define DSC3B3_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 29076 #define DSC3B3_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 29077 #define DSC3B3_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 29078 #define DSC3B3_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 29079 29080 /* Dsc3b3 :: pi_status0 :: phase_cntr [06:00] */ 29081 #define DSC3B3_PI_STATUS0_PHASE_CNTR_MASK 0x007f 29082 #define DSC3B3_PI_STATUS0_PHASE_CNTR_ALIGN 0 29083 #define DSC3B3_PI_STATUS0_PHASE_CNTR_BITS 7 29084 #define DSC3B3_PI_STATUS0_PHASE_CNTR_SHIFT 0 29085 29086 29087 /**************************************************************************** 29088 * Dsc3b3 :: pi_status1 29089 */ 29090 /* union - case pi_Single0_lsb [15:00] */ 29091 /* Dsc3b3 :: pi_status1 :: Single0_lsb [15:00] */ 29092 #define DSC3B3_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK 0xffff 29093 #define DSC3B3_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN 0 29094 #define DSC3B3_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS 16 29095 #define DSC3B3_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT 0 29096 29097 29098 /* union - case pi_Single0_msb [15:00] */ 29099 /* Dsc3b3 :: pi_status1 :: Single0_msb [15:00] */ 29100 #define DSC3B3_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK 0xffff 29101 #define DSC3B3_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN 0 29102 #define DSC3B3_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS 16 29103 #define DSC3B3_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT 0 29104 29105 29106 /* union - case pi_Sequence0_lsb [15:00] */ 29107 /* Dsc3b3 :: pi_status1 :: Sequence0_lsb [15:00] */ 29108 #define DSC3B3_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK 0xffff 29109 #define DSC3B3_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN 0 29110 #define DSC3B3_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS 16 29111 #define DSC3B3_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT 0 29112 29113 29114 /* union - case pi_Sequence0_msb [15:00] */ 29115 /* Dsc3b3 :: pi_status1 :: Sequence0_msb [15:00] */ 29116 #define DSC3B3_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK 0xffff 29117 #define DSC3B3_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN 0 29118 #define DSC3B3_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS 16 29119 #define DSC3B3_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT 0 29120 29121 29122 /* union - case pi_Single90_lsb [15:00] */ 29123 /* Dsc3b3 :: pi_status1 :: Single90_lsb [15:00] */ 29124 #define DSC3B3_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK 0xffff 29125 #define DSC3B3_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN 0 29126 #define DSC3B3_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS 16 29127 #define DSC3B3_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT 0 29128 29129 29130 /* union - case pi_Single90_msb [15:00] */ 29131 /* Dsc3b3 :: pi_status1 :: Single90_msb [15:00] */ 29132 #define DSC3B3_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK 0xffff 29133 #define DSC3B3_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN 0 29134 #define DSC3B3_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS 16 29135 #define DSC3B3_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT 0 29136 29137 29138 /* union - case pi_Sequence90_lsb [15:00] */ 29139 /* Dsc3b3 :: pi_status1 :: Sequence90_lsb [15:00] */ 29140 #define DSC3B3_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK 0xffff 29141 #define DSC3B3_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN 0 29142 #define DSC3B3_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS 16 29143 #define DSC3B3_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT 0 29144 29145 29146 /* union - case pi_Sequence90_msb [15:00] */ 29147 /* Dsc3b3 :: pi_status1 :: Sequence90_msb [15:00] */ 29148 #define DSC3B3_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK 0xffff 29149 #define DSC3B3_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN 0 29150 #define DSC3B3_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS 16 29151 #define DSC3B3_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT 0 29152 29153 29154 29155 /**************************************************************************** 29156 * Dsc3b3 :: dfe_vga_status0 29157 */ 29158 /* Dsc3b3 :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */ 29159 #define DSC3B3_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK 0xf800 29160 #define DSC3B3_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29161 #define DSC3B3_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS 5 29162 #define DSC3B3_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT 11 29163 29164 /* Dsc3b3 :: dfe_vga_status0 :: vga_sum [10:06] */ 29165 #define DSC3B3_DFE_VGA_STATUS0_VGA_SUM_MASK 0x07c0 29166 #define DSC3B3_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 29167 #define DSC3B3_DFE_VGA_STATUS0_VGA_SUM_BITS 5 29168 #define DSC3B3_DFE_VGA_STATUS0_VGA_SUM_SHIFT 6 29169 29170 /* Dsc3b3 :: dfe_vga_status0 :: dfe_tap_bin [05:00] */ 29171 #define DSC3B3_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK 0x003f 29172 #define DSC3B3_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN 0 29173 #define DSC3B3_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS 6 29174 #define DSC3B3_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT 0 29175 29176 29177 /**************************************************************************** 29178 * Dsc3b3 :: dfe_vga_status1 29179 */ 29180 /* Dsc3b3 :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */ 29181 #define DSC3B3_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 29182 #define DSC3B3_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 29183 #define DSC3B3_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS 5 29184 #define DSC3B3_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 29185 29186 /* Dsc3b3 :: dfe_vga_status1 :: trnsum [10:00] */ 29187 #define DSC3B3_DFE_VGA_STATUS1_TRNSUM_MASK 0x07ff 29188 #define DSC3B3_DFE_VGA_STATUS1_TRNSUM_ALIGN 0 29189 #define DSC3B3_DFE_VGA_STATUS1_TRNSUM_BITS 11 29190 #define DSC3B3_DFE_VGA_STATUS1_TRNSUM_SHIFT 0 29191 29192 29193 /**************************************************************************** 29194 * Dsc3b3 :: sm_status0 29195 */ 29196 /* Dsc3b3 :: sm_status0 :: reserved_for_eco0 [15:14] */ 29197 #define DSC3B3_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 29198 #define DSC3B3_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29199 #define DSC3B3_SM_STATUS0_RESERVED_FOR_ECO0_BITS 2 29200 #define DSC3B3_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 29201 29202 /* Dsc3b3 :: sm_status0 :: tuning_done [13:13] */ 29203 #define DSC3B3_SM_STATUS0_TUNING_DONE_MASK 0x2000 29204 #define DSC3B3_SM_STATUS0_TUNING_DONE_ALIGN 0 29205 #define DSC3B3_SM_STATUS0_TUNING_DONE_BITS 1 29206 #define DSC3B3_SM_STATUS0_TUNING_DONE_SHIFT 13 29207 29208 /* Dsc3b3 :: sm_status0 :: srch_state [12:09] */ 29209 #define DSC3B3_SM_STATUS0_SRCH_STATE_MASK 0x1e00 29210 #define DSC3B3_SM_STATUS0_SRCH_STATE_ALIGN 0 29211 #define DSC3B3_SM_STATUS0_SRCH_STATE_BITS 4 29212 #define DSC3B3_SM_STATUS0_SRCH_STATE_SHIFT 9 29213 29214 /* Dsc3b3 :: sm_status0 :: tuning_state [08:04] */ 29215 #define DSC3B3_SM_STATUS0_TUNING_STATE_MASK 0x01f0 29216 #define DSC3B3_SM_STATUS0_TUNING_STATE_ALIGN 0 29217 #define DSC3B3_SM_STATUS0_TUNING_STATE_BITS 5 29218 #define DSC3B3_SM_STATUS0_TUNING_STATE_SHIFT 4 29219 29220 /* Dsc3b3 :: sm_status0 :: dsc_state [03:00] */ 29221 #define DSC3B3_SM_STATUS0_DSC_STATE_MASK 0x000f 29222 #define DSC3B3_SM_STATUS0_DSC_STATE_ALIGN 0 29223 #define DSC3B3_SM_STATUS0_DSC_STATE_BITS 4 29224 #define DSC3B3_SM_STATUS0_DSC_STATE_SHIFT 0 29225 29226 29227 /**************************************************************************** 29228 * Dsc3b3 :: sm_status1 29229 */ 29230 /* Dsc3b3 :: sm_status1 :: reserved_for_eco0 [15:11] */ 29231 #define DSC3B3_SM_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 29232 #define DSC3B3_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 29233 #define DSC3B3_SM_STATUS1_RESERVED_FOR_ECO0_BITS 5 29234 #define DSC3B3_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 29235 29236 /* Dsc3b3 :: sm_status1 :: postc_metric [10:00] */ 29237 #define DSC3B3_SM_STATUS1_POSTC_METRIC_MASK 0x07ff 29238 #define DSC3B3_SM_STATUS1_POSTC_METRIC_ALIGN 0 29239 #define DSC3B3_SM_STATUS1_POSTC_METRIC_BITS 11 29240 #define DSC3B3_SM_STATUS1_POSTC_METRIC_SHIFT 0 29241 29242 29243 /**************************************************************************** 29244 * Dsc3b3 :: sm_status2 29245 */ 29246 /* Dsc3b3 :: sm_status2 :: reserved_for_eco0 [15:15] */ 29247 #define DSC3B3_SM_STATUS2_RESERVED_FOR_ECO0_MASK 0x8000 29248 #define DSC3B3_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 29249 #define DSC3B3_SM_STATUS2_RESERVED_FOR_ECO0_BITS 1 29250 #define DSC3B3_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT 15 29251 29252 /* Dsc3b3 :: sm_status2 :: slicer_offset_po [14:10] */ 29253 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_PO_MASK 0x7c00 29254 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_PO_ALIGN 0 29255 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_PO_BITS 5 29256 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_PO_SHIFT 10 29257 29258 /* Dsc3b3 :: sm_status2 :: slicer_offset_zo [09:05] */ 29259 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_ZO_MASK 0x03e0 29260 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN 0 29261 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_ZO_BITS 5 29262 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT 5 29263 29264 /* Dsc3b3 :: sm_status2 :: slicer_offset_mo [04:00] */ 29265 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_MO_MASK 0x001f 29266 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_MO_ALIGN 0 29267 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_MO_BITS 5 29268 #define DSC3B3_SM_STATUS2_SLICER_OFFSET_MO_SHIFT 0 29269 29270 29271 /**************************************************************************** 29272 * Dsc3b3 :: sm_status3 29273 */ 29274 /* Dsc3b3 :: sm_status3 :: reserved_for_eco0 [15:15] */ 29275 #define DSC3B3_SM_STATUS3_RESERVED_FOR_ECO0_MASK 0x8000 29276 #define DSC3B3_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 29277 #define DSC3B3_SM_STATUS3_RESERVED_FOR_ECO0_BITS 1 29278 #define DSC3B3_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT 15 29279 29280 /* Dsc3b3 :: sm_status3 :: slicer_offset_pe [14:10] */ 29281 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_PE_MASK 0x7c00 29282 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_PE_ALIGN 0 29283 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_PE_BITS 5 29284 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_PE_SHIFT 10 29285 29286 /* Dsc3b3 :: sm_status3 :: slicer_offset_ze [09:05] */ 29287 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_ZE_MASK 0x03e0 29288 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN 0 29289 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_ZE_BITS 5 29290 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT 5 29291 29292 /* Dsc3b3 :: sm_status3 :: slicer_offset_me [04:00] */ 29293 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_ME_MASK 0x001f 29294 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_ME_ALIGN 0 29295 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_ME_BITS 5 29296 #define DSC3B3_SM_STATUS3_SLICER_OFFSET_ME_SHIFT 0 29297 29298 29299 /**************************************************************************** 29300 * Dsc3b3 :: sm_status4 29301 */ 29302 /* Dsc3b3 :: sm_status4 :: reserved_for_eco0 [15:09] */ 29303 #define DSC3B3_SM_STATUS4_RESERVED_FOR_ECO0_MASK 0xfe00 29304 #define DSC3B3_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN 0 29305 #define DSC3B3_SM_STATUS4_RESERVED_FOR_ECO0_BITS 7 29306 #define DSC3B3_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT 9 29307 29308 /* Dsc3b3 :: sm_status4 :: dfe_max [08:08] */ 29309 #define DSC3B3_SM_STATUS4_DFE_MAX_MASK 0x0100 29310 #define DSC3B3_SM_STATUS4_DFE_MAX_ALIGN 0 29311 #define DSC3B3_SM_STATUS4_DFE_MAX_BITS 1 29312 #define DSC3B3_SM_STATUS4_DFE_MAX_SHIFT 8 29313 29314 /* Dsc3b3 :: sm_status4 :: dfe_min [07:07] */ 29315 #define DSC3B3_SM_STATUS4_DFE_MIN_MASK 0x0080 29316 #define DSC3B3_SM_STATUS4_DFE_MIN_ALIGN 0 29317 #define DSC3B3_SM_STATUS4_DFE_MIN_BITS 1 29318 #define DSC3B3_SM_STATUS4_DFE_MIN_SHIFT 7 29319 29320 /* Dsc3b3 :: sm_status4 :: vga_max [06:06] */ 29321 #define DSC3B3_SM_STATUS4_VGA_MAX_MASK 0x0040 29322 #define DSC3B3_SM_STATUS4_VGA_MAX_ALIGN 0 29323 #define DSC3B3_SM_STATUS4_VGA_MAX_BITS 1 29324 #define DSC3B3_SM_STATUS4_VGA_MAX_SHIFT 6 29325 29326 /* Dsc3b3 :: sm_status4 :: vga_min [05:05] */ 29327 #define DSC3B3_SM_STATUS4_VGA_MIN_MASK 0x0020 29328 #define DSC3B3_SM_STATUS4_VGA_MIN_ALIGN 0 29329 #define DSC3B3_SM_STATUS4_VGA_MIN_BITS 1 29330 #define DSC3B3_SM_STATUS4_VGA_MIN_SHIFT 5 29331 29332 /* Dsc3b3 :: sm_status4 :: pf_max [04:04] */ 29333 #define DSC3B3_SM_STATUS4_PF_MAX_MASK 0x0010 29334 #define DSC3B3_SM_STATUS4_PF_MAX_ALIGN 0 29335 #define DSC3B3_SM_STATUS4_PF_MAX_BITS 1 29336 #define DSC3B3_SM_STATUS4_PF_MAX_SHIFT 4 29337 29338 /* Dsc3b3 :: sm_status4 :: pf_min [03:03] */ 29339 #define DSC3B3_SM_STATUS4_PF_MIN_MASK 0x0008 29340 #define DSC3B3_SM_STATUS4_PF_MIN_ALIGN 0 29341 #define DSC3B3_SM_STATUS4_PF_MIN_BITS 1 29342 #define DSC3B3_SM_STATUS4_PF_MIN_SHIFT 3 29343 29344 /* Dsc3b3 :: sm_status4 :: pf_ctrl [02:00] */ 29345 #define DSC3B3_SM_STATUS4_PF_CTRL_MASK 0x0007 29346 #define DSC3B3_SM_STATUS4_PF_CTRL_ALIGN 0 29347 #define DSC3B3_SM_STATUS4_PF_CTRL_BITS 3 29348 #define DSC3B3_SM_STATUS4_PF_CTRL_SHIFT 0 29349 29350 29351 /**************************************************************************** 29352 * Dsc3b3 :: ana_status0 29353 */ 29354 /* Dsc3b3 :: ana_status0 :: reserved_for_eco0 [15:04] */ 29355 #define DSC3B3_ANA_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 29356 #define DSC3B3_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29357 #define DSC3B3_ANA_STATUS0_RESERVED_FOR_ECO0_BITS 12 29358 #define DSC3B3_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 29359 29360 /* Dsc3b3 :: ana_status0 :: pd_ch_p1 [03:03] */ 29361 #define DSC3B3_ANA_STATUS0_PD_CH_P1_MASK 0x0008 29362 #define DSC3B3_ANA_STATUS0_PD_CH_P1_ALIGN 0 29363 #define DSC3B3_ANA_STATUS0_PD_CH_P1_BITS 1 29364 #define DSC3B3_ANA_STATUS0_PD_CH_P1_SHIFT 3 29365 29366 /* Dsc3b3 :: ana_status0 :: en_dfe_clk [02:02] */ 29367 #define DSC3B3_ANA_STATUS0_EN_DFE_CLK_MASK 0x0004 29368 #define DSC3B3_ANA_STATUS0_EN_DFE_CLK_ALIGN 0 29369 #define DSC3B3_ANA_STATUS0_EN_DFE_CLK_BITS 1 29370 #define DSC3B3_ANA_STATUS0_EN_DFE_CLK_SHIFT 2 29371 29372 /* Dsc3b3 :: ana_status0 :: en_hgain [01:01] */ 29373 #define DSC3B3_ANA_STATUS0_EN_HGAIN_MASK 0x0002 29374 #define DSC3B3_ANA_STATUS0_EN_HGAIN_ALIGN 0 29375 #define DSC3B3_ANA_STATUS0_EN_HGAIN_BITS 1 29376 #define DSC3B3_ANA_STATUS0_EN_HGAIN_SHIFT 1 29377 29378 /* Dsc3b3 :: ana_status0 :: offset_pd [00:00] */ 29379 #define DSC3B3_ANA_STATUS0_OFFSET_PD_MASK 0x0001 29380 #define DSC3B3_ANA_STATUS0_OFFSET_PD_ALIGN 0 29381 #define DSC3B3_ANA_STATUS0_OFFSET_PD_BITS 1 29382 #define DSC3B3_ANA_STATUS0_OFFSET_PD_SHIFT 0 29383 29384 29385 /**************************************************************************** 29386 * Dsc3b3 :: sm_status5 29387 */ 29388 /* Dsc3b3 :: sm_status5 :: reserved_for_eco0 [15:11] */ 29389 #define DSC3B3_SM_STATUS5_RESERVED_FOR_ECO0_MASK 0xf800 29390 #define DSC3B3_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN 0 29391 #define DSC3B3_SM_STATUS5_RESERVED_FOR_ECO0_BITS 5 29392 #define DSC3B3_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT 11 29393 29394 /* Dsc3b3 :: sm_status5 :: trnsum_br_vga [10:00] */ 29395 #define DSC3B3_SM_STATUS5_TRNSUM_BR_VGA_MASK 0x07ff 29396 #define DSC3B3_SM_STATUS5_TRNSUM_BR_VGA_ALIGN 0 29397 #define DSC3B3_SM_STATUS5_TRNSUM_BR_VGA_BITS 11 29398 #define DSC3B3_SM_STATUS5_TRNSUM_BR_VGA_SHIFT 0 29399 29400 29401 /**************************************************************************** 29402 * Dsc3b3 :: sm_status6 29403 */ 29404 /* Dsc3b3 :: sm_status6 :: reserved_for_eco0 [15:11] */ 29405 #define DSC3B3_SM_STATUS6_RESERVED_FOR_ECO0_MASK 0xf800 29406 #define DSC3B3_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN 0 29407 #define DSC3B3_SM_STATUS6_RESERVED_FOR_ECO0_BITS 5 29408 #define DSC3B3_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT 11 29409 29410 /* Dsc3b3 :: sm_status6 :: trnsum_pf [10:00] */ 29411 #define DSC3B3_SM_STATUS6_TRNSUM_PF_MASK 0x07ff 29412 #define DSC3B3_SM_STATUS6_TRNSUM_PF_ALIGN 0 29413 #define DSC3B3_SM_STATUS6_TRNSUM_PF_BITS 11 29414 #define DSC3B3_SM_STATUS6_TRNSUM_PF_SHIFT 0 29415 29416 29417 /**************************************************************************** 29418 * Hypercore_USER_Dsc3bB 29419 */ 29420 /**************************************************************************** 29421 * Dsc3bB :: cdr_status0 29422 */ 29423 /* Dsc3bB :: cdr_status0 :: integ_reg [15:00] */ 29424 #define DSC3BB_CDR_STATUS0_INTEG_REG_MASK 0xffff 29425 #define DSC3BB_CDR_STATUS0_INTEG_REG_ALIGN 0 29426 #define DSC3BB_CDR_STATUS0_INTEG_REG_BITS 16 29427 #define DSC3BB_CDR_STATUS0_INTEG_REG_SHIFT 0 29428 29429 29430 /**************************************************************************** 29431 * Dsc3bB :: cdr_status1 29432 */ 29433 /* Dsc3bB :: cdr_status1 :: integ_reg_xfer [15:00] */ 29434 #define DSC3BB_CDR_STATUS1_INTEG_REG_XFER_MASK 0xffff 29435 #define DSC3BB_CDR_STATUS1_INTEG_REG_XFER_ALIGN 0 29436 #define DSC3BB_CDR_STATUS1_INTEG_REG_XFER_BITS 16 29437 #define DSC3BB_CDR_STATUS1_INTEG_REG_XFER_SHIFT 0 29438 29439 29440 /**************************************************************************** 29441 * Dsc3bB :: cdr_status2 29442 */ 29443 /* Dsc3bB :: cdr_status2 :: reserved_for_eco0 [15:11] */ 29444 #define DSC3BB_CDR_STATUS2_RESERVED_FOR_ECO0_MASK 0xf800 29445 #define DSC3BB_CDR_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 29446 #define DSC3BB_CDR_STATUS2_RESERVED_FOR_ECO0_BITS 5 29447 #define DSC3BB_CDR_STATUS2_RESERVED_FOR_ECO0_SHIFT 11 29448 29449 /* Dsc3bB :: cdr_status2 :: sm_br_cdr_enabled [10:10] */ 29450 #define DSC3BB_CDR_STATUS2_SM_BR_CDR_ENABLED_MASK 0x0400 29451 #define DSC3BB_CDR_STATUS2_SM_BR_CDR_ENABLED_ALIGN 0 29452 #define DSC3BB_CDR_STATUS2_SM_BR_CDR_ENABLED_BITS 1 29453 #define DSC3BB_CDR_STATUS2_SM_BR_CDR_ENABLED_SHIFT 10 29454 29455 /* Dsc3bB :: cdr_status2 :: br_cdr_enabled [09:09] */ 29456 #define DSC3BB_CDR_STATUS2_BR_CDR_ENABLED_MASK 0x0200 29457 #define DSC3BB_CDR_STATUS2_BR_CDR_ENABLED_ALIGN 0 29458 #define DSC3BB_CDR_STATUS2_BR_CDR_ENABLED_BITS 1 29459 #define DSC3BB_CDR_STATUS2_BR_CDR_ENABLED_SHIFT 9 29460 29461 /* Dsc3bB :: cdr_status2 :: oscdr_mode [08:06] */ 29462 #define DSC3BB_CDR_STATUS2_OSCDR_MODE_MASK 0x01c0 29463 #define DSC3BB_CDR_STATUS2_OSCDR_MODE_ALIGN 0 29464 #define DSC3BB_CDR_STATUS2_OSCDR_MODE_BITS 3 29465 #define DSC3BB_CDR_STATUS2_OSCDR_MODE_SHIFT 6 29466 29467 /* Dsc3bB :: cdr_status2 :: phase_err [05:00] */ 29468 #define DSC3BB_CDR_STATUS2_PHASE_ERR_MASK 0x003f 29469 #define DSC3BB_CDR_STATUS2_PHASE_ERR_ALIGN 0 29470 #define DSC3BB_CDR_STATUS2_PHASE_ERR_BITS 6 29471 #define DSC3BB_CDR_STATUS2_PHASE_ERR_SHIFT 0 29472 29473 29474 /**************************************************************************** 29475 * Dsc3bB :: pi_status0 29476 */ 29477 /* Dsc3bB :: pi_status0 :: invalid_intrp_ctrl0 [15:15] */ 29478 #define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL0_MASK 0x8000 29479 #define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL0_ALIGN 0 29480 #define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL0_BITS 1 29481 #define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL0_SHIFT 15 29482 29483 /* Dsc3bB :: pi_status0 :: invalid_intrp_ctrl90 [14:14] */ 29484 #define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL90_MASK 0x4000 29485 #define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL90_ALIGN 0 29486 #define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL90_BITS 1 29487 #define DSC3BB_PI_STATUS0_INVALID_INTRP_CTRL90_SHIFT 14 29488 29489 /* Dsc3bB :: pi_status0 :: clk90_phase_offset [13:07] */ 29490 #define DSC3BB_PI_STATUS0_CLK90_PHASE_OFFSET_MASK 0x3f80 29491 #define DSC3BB_PI_STATUS0_CLK90_PHASE_OFFSET_ALIGN 0 29492 #define DSC3BB_PI_STATUS0_CLK90_PHASE_OFFSET_BITS 7 29493 #define DSC3BB_PI_STATUS0_CLK90_PHASE_OFFSET_SHIFT 7 29494 29495 /* Dsc3bB :: pi_status0 :: phase_cntr [06:00] */ 29496 #define DSC3BB_PI_STATUS0_PHASE_CNTR_MASK 0x007f 29497 #define DSC3BB_PI_STATUS0_PHASE_CNTR_ALIGN 0 29498 #define DSC3BB_PI_STATUS0_PHASE_CNTR_BITS 7 29499 #define DSC3BB_PI_STATUS0_PHASE_CNTR_SHIFT 0 29500 29501 29502 /**************************************************************************** 29503 * Dsc3bB :: pi_status1 29504 */ 29505 /* union - case pi_Single0_lsb [15:00] */ 29506 /* Dsc3bB :: pi_status1 :: Single0_lsb [15:00] */ 29507 #define DSC3BB_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_MASK 0xffff 29508 #define DSC3BB_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_ALIGN 0 29509 #define DSC3BB_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_BITS 16 29510 #define DSC3BB_PI_STATUS1_PI_SINGLE0_LSB_SINGLE0_LSB_SHIFT 0 29511 29512 29513 /* union - case pi_Single0_msb [15:00] */ 29514 /* Dsc3bB :: pi_status1 :: Single0_msb [15:00] */ 29515 #define DSC3BB_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_MASK 0xffff 29516 #define DSC3BB_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_ALIGN 0 29517 #define DSC3BB_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_BITS 16 29518 #define DSC3BB_PI_STATUS1_PI_SINGLE0_MSB_SINGLE0_MSB_SHIFT 0 29519 29520 29521 /* union - case pi_Sequence0_lsb [15:00] */ 29522 /* Dsc3bB :: pi_status1 :: Sequence0_lsb [15:00] */ 29523 #define DSC3BB_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_MASK 0xffff 29524 #define DSC3BB_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_ALIGN 0 29525 #define DSC3BB_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_BITS 16 29526 #define DSC3BB_PI_STATUS1_PI_SEQUENCE0_LSB_SEQUENCE0_LSB_SHIFT 0 29527 29528 29529 /* union - case pi_Sequence0_msb [15:00] */ 29530 /* Dsc3bB :: pi_status1 :: Sequence0_msb [15:00] */ 29531 #define DSC3BB_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_MASK 0xffff 29532 #define DSC3BB_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_ALIGN 0 29533 #define DSC3BB_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_BITS 16 29534 #define DSC3BB_PI_STATUS1_PI_SEQUENCE0_MSB_SEQUENCE0_MSB_SHIFT 0 29535 29536 29537 /* union - case pi_Single90_lsb [15:00] */ 29538 /* Dsc3bB :: pi_status1 :: Single90_lsb [15:00] */ 29539 #define DSC3BB_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_MASK 0xffff 29540 #define DSC3BB_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_ALIGN 0 29541 #define DSC3BB_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_BITS 16 29542 #define DSC3BB_PI_STATUS1_PI_SINGLE90_LSB_SINGLE90_LSB_SHIFT 0 29543 29544 29545 /* union - case pi_Single90_msb [15:00] */ 29546 /* Dsc3bB :: pi_status1 :: Single90_msb [15:00] */ 29547 #define DSC3BB_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_MASK 0xffff 29548 #define DSC3BB_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_ALIGN 0 29549 #define DSC3BB_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_BITS 16 29550 #define DSC3BB_PI_STATUS1_PI_SINGLE90_MSB_SINGLE90_MSB_SHIFT 0 29551 29552 29553 /* union - case pi_Sequence90_lsb [15:00] */ 29554 /* Dsc3bB :: pi_status1 :: Sequence90_lsb [15:00] */ 29555 #define DSC3BB_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_MASK 0xffff 29556 #define DSC3BB_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_ALIGN 0 29557 #define DSC3BB_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_BITS 16 29558 #define DSC3BB_PI_STATUS1_PI_SEQUENCE90_LSB_SEQUENCE90_LSB_SHIFT 0 29559 29560 29561 /* union - case pi_Sequence90_msb [15:00] */ 29562 /* Dsc3bB :: pi_status1 :: Sequence90_msb [15:00] */ 29563 #define DSC3BB_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_MASK 0xffff 29564 #define DSC3BB_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_ALIGN 0 29565 #define DSC3BB_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_BITS 16 29566 #define DSC3BB_PI_STATUS1_PI_SEQUENCE90_MSB_SEQUENCE90_MSB_SHIFT 0 29567 29568 29569 29570 /**************************************************************************** 29571 * Dsc3bB :: dfe_vga_status0 29572 */ 29573 /* Dsc3bB :: dfe_vga_status0 :: reserved_for_eco0 [15:11] */ 29574 #define DSC3BB_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_MASK 0xf800 29575 #define DSC3BB_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29576 #define DSC3BB_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_BITS 5 29577 #define DSC3BB_DFE_VGA_STATUS0_RESERVED_FOR_ECO0_SHIFT 11 29578 29579 /* Dsc3bB :: dfe_vga_status0 :: vga_sum [10:06] */ 29580 #define DSC3BB_DFE_VGA_STATUS0_VGA_SUM_MASK 0x07c0 29581 #define DSC3BB_DFE_VGA_STATUS0_VGA_SUM_ALIGN 0 29582 #define DSC3BB_DFE_VGA_STATUS0_VGA_SUM_BITS 5 29583 #define DSC3BB_DFE_VGA_STATUS0_VGA_SUM_SHIFT 6 29584 29585 /* Dsc3bB :: dfe_vga_status0 :: dfe_tap_bin [05:00] */ 29586 #define DSC3BB_DFE_VGA_STATUS0_DFE_TAP_BIN_MASK 0x003f 29587 #define DSC3BB_DFE_VGA_STATUS0_DFE_TAP_BIN_ALIGN 0 29588 #define DSC3BB_DFE_VGA_STATUS0_DFE_TAP_BIN_BITS 6 29589 #define DSC3BB_DFE_VGA_STATUS0_DFE_TAP_BIN_SHIFT 0 29590 29591 29592 /**************************************************************************** 29593 * Dsc3bB :: dfe_vga_status1 29594 */ 29595 /* Dsc3bB :: dfe_vga_status1 :: reserved_for_eco0 [15:11] */ 29596 #define DSC3BB_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 29597 #define DSC3BB_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 29598 #define DSC3BB_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_BITS 5 29599 #define DSC3BB_DFE_VGA_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 29600 29601 /* Dsc3bB :: dfe_vga_status1 :: trnsum [10:00] */ 29602 #define DSC3BB_DFE_VGA_STATUS1_TRNSUM_MASK 0x07ff 29603 #define DSC3BB_DFE_VGA_STATUS1_TRNSUM_ALIGN 0 29604 #define DSC3BB_DFE_VGA_STATUS1_TRNSUM_BITS 11 29605 #define DSC3BB_DFE_VGA_STATUS1_TRNSUM_SHIFT 0 29606 29607 29608 /**************************************************************************** 29609 * Dsc3bB :: sm_status0 29610 */ 29611 /* Dsc3bB :: sm_status0 :: reserved_for_eco0 [15:14] */ 29612 #define DSC3BB_SM_STATUS0_RESERVED_FOR_ECO0_MASK 0xc000 29613 #define DSC3BB_SM_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29614 #define DSC3BB_SM_STATUS0_RESERVED_FOR_ECO0_BITS 2 29615 #define DSC3BB_SM_STATUS0_RESERVED_FOR_ECO0_SHIFT 14 29616 29617 /* Dsc3bB :: sm_status0 :: tuning_done [13:13] */ 29618 #define DSC3BB_SM_STATUS0_TUNING_DONE_MASK 0x2000 29619 #define DSC3BB_SM_STATUS0_TUNING_DONE_ALIGN 0 29620 #define DSC3BB_SM_STATUS0_TUNING_DONE_BITS 1 29621 #define DSC3BB_SM_STATUS0_TUNING_DONE_SHIFT 13 29622 29623 /* Dsc3bB :: sm_status0 :: srch_state [12:09] */ 29624 #define DSC3BB_SM_STATUS0_SRCH_STATE_MASK 0x1e00 29625 #define DSC3BB_SM_STATUS0_SRCH_STATE_ALIGN 0 29626 #define DSC3BB_SM_STATUS0_SRCH_STATE_BITS 4 29627 #define DSC3BB_SM_STATUS0_SRCH_STATE_SHIFT 9 29628 29629 /* Dsc3bB :: sm_status0 :: tuning_state [08:04] */ 29630 #define DSC3BB_SM_STATUS0_TUNING_STATE_MASK 0x01f0 29631 #define DSC3BB_SM_STATUS0_TUNING_STATE_ALIGN 0 29632 #define DSC3BB_SM_STATUS0_TUNING_STATE_BITS 5 29633 #define DSC3BB_SM_STATUS0_TUNING_STATE_SHIFT 4 29634 29635 /* Dsc3bB :: sm_status0 :: dsc_state [03:00] */ 29636 #define DSC3BB_SM_STATUS0_DSC_STATE_MASK 0x000f 29637 #define DSC3BB_SM_STATUS0_DSC_STATE_ALIGN 0 29638 #define DSC3BB_SM_STATUS0_DSC_STATE_BITS 4 29639 #define DSC3BB_SM_STATUS0_DSC_STATE_SHIFT 0 29640 29641 29642 /**************************************************************************** 29643 * Dsc3bB :: sm_status1 29644 */ 29645 /* Dsc3bB :: sm_status1 :: reserved_for_eco0 [15:11] */ 29646 #define DSC3BB_SM_STATUS1_RESERVED_FOR_ECO0_MASK 0xf800 29647 #define DSC3BB_SM_STATUS1_RESERVED_FOR_ECO0_ALIGN 0 29648 #define DSC3BB_SM_STATUS1_RESERVED_FOR_ECO0_BITS 5 29649 #define DSC3BB_SM_STATUS1_RESERVED_FOR_ECO0_SHIFT 11 29650 29651 /* Dsc3bB :: sm_status1 :: postc_metric [10:00] */ 29652 #define DSC3BB_SM_STATUS1_POSTC_METRIC_MASK 0x07ff 29653 #define DSC3BB_SM_STATUS1_POSTC_METRIC_ALIGN 0 29654 #define DSC3BB_SM_STATUS1_POSTC_METRIC_BITS 11 29655 #define DSC3BB_SM_STATUS1_POSTC_METRIC_SHIFT 0 29656 29657 29658 /**************************************************************************** 29659 * Dsc3bB :: sm_status2 29660 */ 29661 /* Dsc3bB :: sm_status2 :: reserved_for_eco0 [15:15] */ 29662 #define DSC3BB_SM_STATUS2_RESERVED_FOR_ECO0_MASK 0x8000 29663 #define DSC3BB_SM_STATUS2_RESERVED_FOR_ECO0_ALIGN 0 29664 #define DSC3BB_SM_STATUS2_RESERVED_FOR_ECO0_BITS 1 29665 #define DSC3BB_SM_STATUS2_RESERVED_FOR_ECO0_SHIFT 15 29666 29667 /* Dsc3bB :: sm_status2 :: slicer_offset_po [14:10] */ 29668 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_PO_MASK 0x7c00 29669 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_PO_ALIGN 0 29670 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_PO_BITS 5 29671 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_PO_SHIFT 10 29672 29673 /* Dsc3bB :: sm_status2 :: slicer_offset_zo [09:05] */ 29674 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_ZO_MASK 0x03e0 29675 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_ZO_ALIGN 0 29676 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_ZO_BITS 5 29677 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_ZO_SHIFT 5 29678 29679 /* Dsc3bB :: sm_status2 :: slicer_offset_mo [04:00] */ 29680 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_MO_MASK 0x001f 29681 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_MO_ALIGN 0 29682 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_MO_BITS 5 29683 #define DSC3BB_SM_STATUS2_SLICER_OFFSET_MO_SHIFT 0 29684 29685 29686 /**************************************************************************** 29687 * Dsc3bB :: sm_status3 29688 */ 29689 /* Dsc3bB :: sm_status3 :: reserved_for_eco0 [15:15] */ 29690 #define DSC3BB_SM_STATUS3_RESERVED_FOR_ECO0_MASK 0x8000 29691 #define DSC3BB_SM_STATUS3_RESERVED_FOR_ECO0_ALIGN 0 29692 #define DSC3BB_SM_STATUS3_RESERVED_FOR_ECO0_BITS 1 29693 #define DSC3BB_SM_STATUS3_RESERVED_FOR_ECO0_SHIFT 15 29694 29695 /* Dsc3bB :: sm_status3 :: slicer_offset_pe [14:10] */ 29696 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_PE_MASK 0x7c00 29697 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_PE_ALIGN 0 29698 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_PE_BITS 5 29699 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_PE_SHIFT 10 29700 29701 /* Dsc3bB :: sm_status3 :: slicer_offset_ze [09:05] */ 29702 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_ZE_MASK 0x03e0 29703 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_ZE_ALIGN 0 29704 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_ZE_BITS 5 29705 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_ZE_SHIFT 5 29706 29707 /* Dsc3bB :: sm_status3 :: slicer_offset_me [04:00] */ 29708 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_ME_MASK 0x001f 29709 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_ME_ALIGN 0 29710 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_ME_BITS 5 29711 #define DSC3BB_SM_STATUS3_SLICER_OFFSET_ME_SHIFT 0 29712 29713 29714 /**************************************************************************** 29715 * Dsc3bB :: sm_status4 29716 */ 29717 /* Dsc3bB :: sm_status4 :: reserved_for_eco0 [15:09] */ 29718 #define DSC3BB_SM_STATUS4_RESERVED_FOR_ECO0_MASK 0xfe00 29719 #define DSC3BB_SM_STATUS4_RESERVED_FOR_ECO0_ALIGN 0 29720 #define DSC3BB_SM_STATUS4_RESERVED_FOR_ECO0_BITS 7 29721 #define DSC3BB_SM_STATUS4_RESERVED_FOR_ECO0_SHIFT 9 29722 29723 /* Dsc3bB :: sm_status4 :: dfe_max [08:08] */ 29724 #define DSC3BB_SM_STATUS4_DFE_MAX_MASK 0x0100 29725 #define DSC3BB_SM_STATUS4_DFE_MAX_ALIGN 0 29726 #define DSC3BB_SM_STATUS4_DFE_MAX_BITS 1 29727 #define DSC3BB_SM_STATUS4_DFE_MAX_SHIFT 8 29728 29729 /* Dsc3bB :: sm_status4 :: dfe_min [07:07] */ 29730 #define DSC3BB_SM_STATUS4_DFE_MIN_MASK 0x0080 29731 #define DSC3BB_SM_STATUS4_DFE_MIN_ALIGN 0 29732 #define DSC3BB_SM_STATUS4_DFE_MIN_BITS 1 29733 #define DSC3BB_SM_STATUS4_DFE_MIN_SHIFT 7 29734 29735 /* Dsc3bB :: sm_status4 :: vga_max [06:06] */ 29736 #define DSC3BB_SM_STATUS4_VGA_MAX_MASK 0x0040 29737 #define DSC3BB_SM_STATUS4_VGA_MAX_ALIGN 0 29738 #define DSC3BB_SM_STATUS4_VGA_MAX_BITS 1 29739 #define DSC3BB_SM_STATUS4_VGA_MAX_SHIFT 6 29740 29741 /* Dsc3bB :: sm_status4 :: vga_min [05:05] */ 29742 #define DSC3BB_SM_STATUS4_VGA_MIN_MASK 0x0020 29743 #define DSC3BB_SM_STATUS4_VGA_MIN_ALIGN 0 29744 #define DSC3BB_SM_STATUS4_VGA_MIN_BITS 1 29745 #define DSC3BB_SM_STATUS4_VGA_MIN_SHIFT 5 29746 29747 /* Dsc3bB :: sm_status4 :: pf_max [04:04] */ 29748 #define DSC3BB_SM_STATUS4_PF_MAX_MASK 0x0010 29749 #define DSC3BB_SM_STATUS4_PF_MAX_ALIGN 0 29750 #define DSC3BB_SM_STATUS4_PF_MAX_BITS 1 29751 #define DSC3BB_SM_STATUS4_PF_MAX_SHIFT 4 29752 29753 /* Dsc3bB :: sm_status4 :: pf_min [03:03] */ 29754 #define DSC3BB_SM_STATUS4_PF_MIN_MASK 0x0008 29755 #define DSC3BB_SM_STATUS4_PF_MIN_ALIGN 0 29756 #define DSC3BB_SM_STATUS4_PF_MIN_BITS 1 29757 #define DSC3BB_SM_STATUS4_PF_MIN_SHIFT 3 29758 29759 /* Dsc3bB :: sm_status4 :: pf_ctrl [02:00] */ 29760 #define DSC3BB_SM_STATUS4_PF_CTRL_MASK 0x0007 29761 #define DSC3BB_SM_STATUS4_PF_CTRL_ALIGN 0 29762 #define DSC3BB_SM_STATUS4_PF_CTRL_BITS 3 29763 #define DSC3BB_SM_STATUS4_PF_CTRL_SHIFT 0 29764 29765 29766 /**************************************************************************** 29767 * Dsc3bB :: ana_status0 29768 */ 29769 /* Dsc3bB :: ana_status0 :: reserved_for_eco0 [15:04] */ 29770 #define DSC3BB_ANA_STATUS0_RESERVED_FOR_ECO0_MASK 0xfff0 29771 #define DSC3BB_ANA_STATUS0_RESERVED_FOR_ECO0_ALIGN 0 29772 #define DSC3BB_ANA_STATUS0_RESERVED_FOR_ECO0_BITS 12 29773 #define DSC3BB_ANA_STATUS0_RESERVED_FOR_ECO0_SHIFT 4 29774 29775 /* Dsc3bB :: ana_status0 :: pd_ch_p1 [03:03] */ 29776 #define DSC3BB_ANA_STATUS0_PD_CH_P1_MASK 0x0008 29777 #define DSC3BB_ANA_STATUS0_PD_CH_P1_ALIGN 0 29778 #define DSC3BB_ANA_STATUS0_PD_CH_P1_BITS 1 29779 #define DSC3BB_ANA_STATUS0_PD_CH_P1_SHIFT 3 29780 29781 /* Dsc3bB :: ana_status0 :: en_dfe_clk [02:02] */ 29782 #define DSC3BB_ANA_STATUS0_EN_DFE_CLK_MASK 0x0004 29783 #define DSC3BB_ANA_STATUS0_EN_DFE_CLK_ALIGN 0 29784 #define DSC3BB_ANA_STATUS0_EN_DFE_CLK_BITS 1 29785 #define DSC3BB_ANA_STATUS0_EN_DFE_CLK_SHIFT 2 29786 29787 /* Dsc3bB :: ana_status0 :: en_hgain [01:01] */ 29788 #define DSC3BB_ANA_STATUS0_EN_HGAIN_MASK 0x0002 29789 #define DSC3BB_ANA_STATUS0_EN_HGAIN_ALIGN 0 29790 #define DSC3BB_ANA_STATUS0_EN_HGAIN_BITS 1 29791 #define DSC3BB_ANA_STATUS0_EN_HGAIN_SHIFT 1 29792 29793 /* Dsc3bB :: ana_status0 :: offset_pd [00:00] */ 29794 #define DSC3BB_ANA_STATUS0_OFFSET_PD_MASK 0x0001 29795 #define DSC3BB_ANA_STATUS0_OFFSET_PD_ALIGN 0 29796 #define DSC3BB_ANA_STATUS0_OFFSET_PD_BITS 1 29797 #define DSC3BB_ANA_STATUS0_OFFSET_PD_SHIFT 0 29798 29799 29800 /**************************************************************************** 29801 * Dsc3bB :: sm_status5 29802 */ 29803 /* Dsc3bB :: sm_status5 :: reserved_for_eco0 [15:11] */ 29804 #define DSC3BB_SM_STATUS5_RESERVED_FOR_ECO0_MASK 0xf800 29805 #define DSC3BB_SM_STATUS5_RESERVED_FOR_ECO0_ALIGN 0 29806 #define DSC3BB_SM_STATUS5_RESERVED_FOR_ECO0_BITS 5 29807 #define DSC3BB_SM_STATUS5_RESERVED_FOR_ECO0_SHIFT 11 29808 29809 /* Dsc3bB :: sm_status5 :: trnsum_br_vga [10:00] */ 29810 #define DSC3BB_SM_STATUS5_TRNSUM_BR_VGA_MASK 0x07ff 29811 #define DSC3BB_SM_STATUS5_TRNSUM_BR_VGA_ALIGN 0 29812 #define DSC3BB_SM_STATUS5_TRNSUM_BR_VGA_BITS 11 29813 #define DSC3BB_SM_STATUS5_TRNSUM_BR_VGA_SHIFT 0 29814 29815 29816 /**************************************************************************** 29817 * Dsc3bB :: sm_status6 29818 */ 29819 /* Dsc3bB :: sm_status6 :: reserved_for_eco0 [15:11] */ 29820 #define DSC3BB_SM_STATUS6_RESERVED_FOR_ECO0_MASK 0xf800 29821 #define DSC3BB_SM_STATUS6_RESERVED_FOR_ECO0_ALIGN 0 29822 #define DSC3BB_SM_STATUS6_RESERVED_FOR_ECO0_BITS 5 29823 #define DSC3BB_SM_STATUS6_RESERVED_FOR_ECO0_SHIFT 11 29824 29825 /* Dsc3bB :: sm_status6 :: trnsum_pf [10:00] */ 29826 #define DSC3BB_SM_STATUS6_TRNSUM_PF_MASK 0x07ff 29827 #define DSC3BB_SM_STATUS6_TRNSUM_PF_ALIGN 0 29828 #define DSC3BB_SM_STATUS6_TRNSUM_PF_BITS 11 29829 #define DSC3BB_SM_STATUS6_TRNSUM_PF_SHIFT 0 29830 29831 29832 /**************************************************************************** 29833 * Hypercore_USER_Digital 29834 */ 29835 /**************************************************************************** 29836 * Digital :: Control1000X1 29837 */ 29838 /* Digital :: Control1000X1 :: reserved0 [15:15] */ 29839 #define DIGITAL_CONTROL1000X1_RESERVED0_MASK 0x8000 29840 #define DIGITAL_CONTROL1000X1_RESERVED0_ALIGN 0 29841 #define DIGITAL_CONTROL1000X1_RESERVED0_BITS 1 29842 #define DIGITAL_CONTROL1000X1_RESERVED0_SHIFT 15 29843 29844 /* Digital :: Control1000X1 :: disable_signal_detect_filter [14:14] */ 29845 #define DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000 29846 #define DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0 29847 #define DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1 29848 #define DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14 29849 29850 /* Digital :: Control1000X1 :: reserved1 [13:12] */ 29851 #define DIGITAL_CONTROL1000X1_RESERVED1_MASK 0x3000 29852 #define DIGITAL_CONTROL1000X1_RESERVED1_ALIGN 0 29853 #define DIGITAL_CONTROL1000X1_RESERVED1_BITS 2 29854 #define DIGITAL_CONTROL1000X1_RESERVED1_SHIFT 12 29855 29856 /* Digital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */ 29857 #define DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK 0x0800 29858 #define DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN 0 29859 #define DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS 1 29860 #define DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT 11 29861 29862 /* Digital :: Control1000X1 :: remote_loopback [10:10] */ 29863 #define DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK 0x0400 29864 #define DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN 0 29865 #define DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS 1 29866 #define DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT 10 29867 29868 /* Digital :: Control1000X1 :: zero_comma_detector_phase [09:09] */ 29869 #define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200 29870 #define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0 29871 #define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1 29872 #define DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9 29873 29874 /* Digital :: Control1000X1 :: comma_det_en [08:08] */ 29875 #define DIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK 0x0100 29876 #define DIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN 0 29877 #define DIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS 1 29878 #define DIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT 8 29879 29880 /* Digital :: Control1000X1 :: crc_checker_disable [07:07] */ 29881 #define DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK 0x0080 29882 #define DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN 0 29883 #define DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS 1 29884 #define DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT 7 29885 29886 /* Digital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */ 29887 #define DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK 0x0040 29888 #define DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN 0 29889 #define DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS 1 29890 #define DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT 6 29891 29892 /* Digital :: Control1000X1 :: sgmii_master_mode [05:05] */ 29893 #define DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK 0x0020 29894 #define DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN 0 29895 #define DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS 1 29896 #define DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT 5 29897 29898 /* Digital :: Control1000X1 :: autodet_en [04:04] */ 29899 #define DIGITAL_CONTROL1000X1_AUTODET_EN_MASK 0x0010 29900 #define DIGITAL_CONTROL1000X1_AUTODET_EN_ALIGN 0 29901 #define DIGITAL_CONTROL1000X1_AUTODET_EN_BITS 1 29902 #define DIGITAL_CONTROL1000X1_AUTODET_EN_SHIFT 4 29903 29904 /* Digital :: Control1000X1 :: invert_signal_detect [03:03] */ 29905 #define DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK 0x0008 29906 #define DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN 0 29907 #define DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS 1 29908 #define DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT 3 29909 29910 /* Digital :: Control1000X1 :: signal_detect_en [02:02] */ 29911 #define DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK 0x0004 29912 #define DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN 0 29913 #define DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS 1 29914 #define DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT 2 29915 29916 /* Digital :: Control1000X1 :: tbi_interface [01:01] */ 29917 #define DIGITAL_CONTROL1000X1_TBI_INTERFACE_MASK 0x0002 29918 #define DIGITAL_CONTROL1000X1_TBI_INTERFACE_ALIGN 0 29919 #define DIGITAL_CONTROL1000X1_TBI_INTERFACE_BITS 1 29920 #define DIGITAL_CONTROL1000X1_TBI_INTERFACE_SHIFT 1 29921 29922 /* Digital :: Control1000X1 :: fiber_mode_1000X [00:00] */ 29923 #define DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK 0x0001 29924 #define DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN 0 29925 #define DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS 1 29926 #define DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT 0 29927 29928 29929 /**************************************************************************** 29930 * Digital :: Control1000X2 29931 */ 29932 /* Digital :: Control1000X2 :: disable_extend_fdx_only [15:15] */ 29933 #define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK 0x8000 29934 #define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0 29935 #define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS 1 29936 #define DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15 29937 29938 /* Digital :: Control1000X2 :: clear_ber_counter [14:14] */ 29939 #define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK 0x4000 29940 #define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN 0 29941 #define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS 1 29942 #define DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT 14 29943 29944 /* Digital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */ 29945 #define DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000 29946 #define DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0 29947 #define DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1 29948 #define DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13 29949 29950 /* Digital :: Control1000X2 :: transmit_packet_seq_test [12:12] */ 29951 #define DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK 0x1000 29952 #define DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0 29953 #define DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS 1 29954 #define DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12 29955 29956 /* Digital :: Control1000X2 :: test_cntr [11:11] */ 29957 #define DIGITAL_CONTROL1000X2_TEST_CNTR_MASK 0x0800 29958 #define DIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN 0 29959 #define DIGITAL_CONTROL1000X2_TEST_CNTR_BITS 1 29960 #define DIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT 11 29961 29962 /* Digital :: Control1000X2 :: bypass_pcs_tx [10:10] */ 29963 #define DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK 0x0400 29964 #define DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN 0 29965 #define DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS 1 29966 #define DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT 10 29967 29968 /* Digital :: Control1000X2 :: bypass_pcs_rx [09:09] */ 29969 #define DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK 0x0200 29970 #define DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN 0 29971 #define DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS 1 29972 #define DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT 9 29973 29974 /* Digital :: Control1000X2 :: disable_TRRR_generation [08:08] */ 29975 #define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK 0x0100 29976 #define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0 29977 #define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS 1 29978 #define DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8 29979 29980 /* Digital :: Control1000X2 :: disable_carrier_extend [07:07] */ 29981 #define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK 0x0080 29982 #define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN 0 29983 #define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS 1 29984 #define DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT 7 29985 29986 /* Digital :: Control1000X2 :: autoneg_fast_timers [06:06] */ 29987 #define DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK 0x0040 29988 #define DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN 0 29989 #define DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS 1 29990 #define DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT 6 29991 29992 /* Digital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */ 29993 #define DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020 29994 #define DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0 29995 #define DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1 29996 #define DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5 29997 29998 /* Digital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */ 29999 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010 30000 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0 30001 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1 30002 #define DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4 30003 30004 /* Digital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */ 30005 #define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008 30006 #define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0 30007 #define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1 30008 #define DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3 30009 30010 /* Digital :: Control1000X2 :: filter_force_link [02:02] */ 30011 #define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK 0x0004 30012 #define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN 0 30013 #define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS 1 30014 #define DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT 2 30015 30016 /* Digital :: Control1000X2 :: disable_false_link [01:01] */ 30017 #define DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK 0x0002 30018 #define DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN 0 30019 #define DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS 1 30020 #define DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT 1 30021 30022 /* Digital :: Control1000X2 :: enable_parallel_detection [00:00] */ 30023 #define DIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_MASK 0x0001 30024 #define DIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_ALIGN 0 30025 #define DIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_BITS 1 30026 #define DIGITAL_CONTROL1000X2_ENABLE_PARALLEL_DETECTION_SHIFT 0 30027 30028 30029 /**************************************************************************** 30030 * Digital :: Control1000X3 30031 */ 30032 /* Digital :: Control1000X3 :: disable_packet_misalign [15:15] */ 30033 #define DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK 0x8000 30034 #define DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN 0 30035 #define DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS 1 30036 #define DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT 15 30037 30038 /* Digital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */ 30039 #define DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK 0x4000 30040 #define DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN 0 30041 #define DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS 1 30042 #define DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT 14 30043 30044 /* Digital :: Control1000X3 :: disable_tx_crs [13:13] */ 30045 #define DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK 0x2000 30046 #define DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN 0 30047 #define DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS 1 30048 #define DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT 13 30049 30050 /* Digital :: Control1000X3 :: invert_ext_phy_crs [12:12] */ 30051 #define DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK 0x1000 30052 #define DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN 0 30053 #define DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS 1 30054 #define DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT 12 30055 30056 /* Digital :: Control1000X3 :: ext_phy_crs_mode [11:11] */ 30057 #define DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK 0x0800 30058 #define DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN 0 30059 #define DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS 1 30060 #define DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT 11 30061 30062 /* Digital :: Control1000X3 :: jam_false_carrier_mode [10:10] */ 30063 #define DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK 0x0400 30064 #define DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN 0 30065 #define DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS 1 30066 #define DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT 10 30067 30068 /* Digital :: Control1000X3 :: block_txen_mode [09:09] */ 30069 #define DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK 0x0200 30070 #define DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN 0 30071 #define DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS 1 30072 #define DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT 9 30073 30074 /* Digital :: Control1000X3 :: force_txfifo_on [08:08] */ 30075 #define DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK 0x0100 30076 #define DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN 0 30077 #define DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS 1 30078 #define DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT 8 30079 30080 /* Digital :: Control1000X3 :: bypass_txfifo1000 [07:07] */ 30081 #define DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK 0x0080 30082 #define DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN 0 30083 #define DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS 1 30084 #define DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT 7 30085 30086 /* Digital :: Control1000X3 :: freq_lock_elasticity_tx [06:06] */ 30087 #define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_MASK 0x0040 30088 #define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_ALIGN 0 30089 #define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_BITS 1 30090 #define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_TX_SHIFT 6 30091 30092 /* Digital :: Control1000X3 :: freq_lock_elasticity_rx [05:05] */ 30093 #define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_MASK 0x0020 30094 #define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_ALIGN 0 30095 #define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_BITS 1 30096 #define DIGITAL_CONTROL1000X3_FREQ_LOCK_ELASTICITY_RX_SHIFT 5 30097 30098 /* Digital :: Control1000X3 :: early_preamble_rx [04:04] */ 30099 #define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK 0x0010 30100 #define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN 0 30101 #define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS 1 30102 #define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT 4 30103 30104 /* Digital :: Control1000X3 :: early_preamble_tx [03:03] */ 30105 #define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK 0x0008 30106 #define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN 0 30107 #define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS 1 30108 #define DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT 3 30109 30110 /* Digital :: Control1000X3 :: fifo_elasicity_tx_rx [02:01] */ 30111 #define DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_MASK 0x0006 30112 #define DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_ALIGN 0 30113 #define DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_BITS 2 30114 #define DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_RX_SHIFT 1 30115 30116 /* Digital :: Control1000X3 :: tx_fifo_rst [00:00] */ 30117 #define DIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK 0x0001 30118 #define DIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN 0 30119 #define DIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS 1 30120 #define DIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT 0 30121 30122 30123 /**************************************************************************** 30124 * Digital :: Control1000X4 30125 */ 30126 /* Digital :: Control1000X4 :: reserved0 [15:14] */ 30127 #define DIGITAL_CONTROL1000X4_RESERVED0_MASK 0xc000 30128 #define DIGITAL_CONTROL1000X4_RESERVED0_ALIGN 0 30129 #define DIGITAL_CONTROL1000X4_RESERVED0_BITS 2 30130 #define DIGITAL_CONTROL1000X4_RESERVED0_SHIFT 14 30131 30132 /* Digital :: Control1000X4 :: disable_resolution_err_restart [13:13] */ 30133 #define DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000 30134 #define DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0 30135 #define DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1 30136 #define DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13 30137 30138 /* Digital :: Control1000X4 :: enable_last_resolution_err [12:12] */ 30139 #define DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000 30140 #define DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0 30141 #define DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1 30142 #define DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12 30143 30144 /* Digital :: Control1000X4 :: tx_config_reg_sel [11:11] */ 30145 #define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK 0x0800 30146 #define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN 0 30147 #define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS 1 30148 #define DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT 11 30149 30150 /* Digital :: Control1000X4 :: zero_rxdgmii [10:10] */ 30151 #define DIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK 0x0400 30152 #define DIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN 0 30153 #define DIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS 1 30154 #define DIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT 10 30155 30156 /* Digital :: Control1000X4 :: clear_linkdown [09:09] */ 30157 #define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK 0x0200 30158 #define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN 0 30159 #define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS 1 30160 #define DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT 9 30161 30162 /* Digital :: Control1000X4 :: latch_linkdown_enable [08:08] */ 30163 #define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK 0x0100 30164 #define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN 0 30165 #define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS 1 30166 #define DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT 8 30167 30168 /* Digital :: Control1000X4 :: link_force [07:07] */ 30169 #define DIGITAL_CONTROL1000X4_LINK_FORCE_MASK 0x0080 30170 #define DIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN 0 30171 #define DIGITAL_CONTROL1000X4_LINK_FORCE_BITS 1 30172 #define DIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT 7 30173 30174 /* Digital :: Control1000X4 :: reserved1 [06:06] */ 30175 #define DIGITAL_CONTROL1000X4_RESERVED1_MASK 0x0040 30176 #define DIGITAL_CONTROL1000X4_RESERVED1_ALIGN 0 30177 #define DIGITAL_CONTROL1000X4_RESERVED1_BITS 1 30178 #define DIGITAL_CONTROL1000X4_RESERVED1_SHIFT 6 30179 30180 /* Digital :: Control1000X4 :: lp_next_page_sel [05:05] */ 30181 #define DIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_MASK 0x0020 30182 #define DIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_ALIGN 0 30183 #define DIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_BITS 1 30184 #define DIGITAL_CONTROL1000X4_LP_NEXT_PAGE_SEL_SHIFT 5 30185 30186 /* Digital :: Control1000X4 :: np_count_ClrnBp [04:04] */ 30187 #define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_MASK 0x0010 30188 #define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_ALIGN 0 30189 #define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_BITS 1 30190 #define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNBP_SHIFT 4 30191 30192 /* Digital :: Control1000X4 :: np_count_ClrnRd [03:03] */ 30193 #define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_MASK 0x0008 30194 #define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_ALIGN 0 30195 #define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_BITS 1 30196 #define DIGITAL_CONTROL1000X4_NP_COUNT_CLRNRD_SHIFT 3 30197 30198 /* Digital :: Control1000X4 :: MiscRxStatus_sel [02:00] */ 30199 #define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK 0x0007 30200 #define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN 0 30201 #define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS 3 30202 #define DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT 0 30203 30204 30205 /**************************************************************************** 30206 * Digital :: Status1000X1 30207 */ 30208 /* Digital :: Status1000X1 :: txfifo_err_detected [15:15] */ 30209 #define DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK 0x8000 30210 #define DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN 0 30211 #define DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS 1 30212 #define DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT 15 30213 30214 /* Digital :: Status1000X1 :: rxfifo_err_detected [14:14] */ 30215 #define DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK 0x4000 30216 #define DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN 0 30217 #define DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS 1 30218 #define DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT 14 30219 30220 /* Digital :: Status1000X1 :: false_carrier_detected [13:13] */ 30221 #define DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK 0x2000 30222 #define DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN 0 30223 #define DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS 1 30224 #define DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT 13 30225 30226 /* Digital :: Status1000X1 :: crc_err_detected [12:12] */ 30227 #define DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK 0x1000 30228 #define DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN 0 30229 #define DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS 1 30230 #define DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT 12 30231 30232 /* Digital :: Status1000X1 :: tx_err_detected [11:11] */ 30233 #define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK 0x0800 30234 #define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN 0 30235 #define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS 1 30236 #define DIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT 11 30237 30238 /* Digital :: Status1000X1 :: rx_err_detected [10:10] */ 30239 #define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK 0x0400 30240 #define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN 0 30241 #define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS 1 30242 #define DIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT 10 30243 30244 /* Digital :: Status1000X1 :: carrier_extend_err_detected [09:09] */ 30245 #define DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200 30246 #define DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0 30247 #define DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1 30248 #define DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9 30249 30250 /* Digital :: Status1000X1 :: early_end_extension_detected [08:08] */ 30251 #define DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100 30252 #define DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0 30253 #define DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1 30254 #define DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8 30255 30256 /* Digital :: Status1000X1 :: link_status_change [07:07] */ 30257 #define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK 0x0080 30258 #define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN 0 30259 #define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS 1 30260 #define DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT 7 30261 30262 /* Digital :: Status1000X1 :: pause_resolution_rxside [06:06] */ 30263 #define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK 0x0040 30264 #define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN 0 30265 #define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS 1 30266 #define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT 6 30267 30268 /* Digital :: Status1000X1 :: pause_resolution_txside [05:05] */ 30269 #define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK 0x0020 30270 #define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN 0 30271 #define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS 1 30272 #define DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT 5 30273 30274 /* Digital :: Status1000X1 :: speed_status [04:03] */ 30275 #define DIGITAL_STATUS1000X1_SPEED_STATUS_MASK 0x0018 30276 #define DIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN 0 30277 #define DIGITAL_STATUS1000X1_SPEED_STATUS_BITS 2 30278 #define DIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT 3 30279 30280 /* Digital :: Status1000X1 :: duplex_status [02:02] */ 30281 #define DIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK 0x0004 30282 #define DIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN 0 30283 #define DIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS 1 30284 #define DIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT 2 30285 30286 /* Digital :: Status1000X1 :: link_status [01:01] */ 30287 #define DIGITAL_STATUS1000X1_LINK_STATUS_MASK 0x0002 30288 #define DIGITAL_STATUS1000X1_LINK_STATUS_ALIGN 0 30289 #define DIGITAL_STATUS1000X1_LINK_STATUS_BITS 1 30290 #define DIGITAL_STATUS1000X1_LINK_STATUS_SHIFT 1 30291 30292 /* Digital :: Status1000X1 :: sgmii_mode [00:00] */ 30293 #define DIGITAL_STATUS1000X1_SGMII_MODE_MASK 0x0001 30294 #define DIGITAL_STATUS1000X1_SGMII_MODE_ALIGN 0 30295 #define DIGITAL_STATUS1000X1_SGMII_MODE_BITS 1 30296 #define DIGITAL_STATUS1000X1_SGMII_MODE_SHIFT 0 30297 30298 30299 /**************************************************************************** 30300 * Digital :: Status1000X2 30301 */ 30302 /* Digital :: Status1000X2 :: sgmii_mode_change [15:15] */ 30303 #define DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK 0x8000 30304 #define DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN 0 30305 #define DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS 1 30306 #define DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT 15 30307 30308 /* Digital :: Status1000X2 :: consistency_mismatch [14:14] */ 30309 #define DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK 0x4000 30310 #define DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN 0 30311 #define DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS 1 30312 #define DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT 14 30313 30314 /* Digital :: Status1000X2 :: autoneg_resolution_err [13:13] */ 30315 #define DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK 0x2000 30316 #define DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN 0 30317 #define DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS 1 30318 #define DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT 13 30319 30320 /* Digital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */ 30321 #define DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK 0x1000 30322 #define DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN 0 30323 #define DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS 1 30324 #define DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT 12 30325 30326 /* Digital :: Status1000X2 :: sync_status_fail [11:11] */ 30327 #define DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK 0x0800 30328 #define DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN 0 30329 #define DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS 1 30330 #define DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT 11 30331 30332 /* Digital :: Status1000X2 :: sync_status_ok [10:10] */ 30333 #define DIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK 0x0400 30334 #define DIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN 0 30335 #define DIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS 1 30336 #define DIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT 10 30337 30338 /* Digital :: Status1000X2 :: rudi_c [09:09] */ 30339 #define DIGITAL_STATUS1000X2_RUDI_C_MASK 0x0200 30340 #define DIGITAL_STATUS1000X2_RUDI_C_ALIGN 0 30341 #define DIGITAL_STATUS1000X2_RUDI_C_BITS 1 30342 #define DIGITAL_STATUS1000X2_RUDI_C_SHIFT 9 30343 30344 /* Digital :: Status1000X2 :: rudi_I [08:08] */ 30345 #define DIGITAL_STATUS1000X2_RUDI_I_MASK 0x0100 30346 #define DIGITAL_STATUS1000X2_RUDI_I_ALIGN 0 30347 #define DIGITAL_STATUS1000X2_RUDI_I_BITS 1 30348 #define DIGITAL_STATUS1000X2_RUDI_I_SHIFT 8 30349 30350 /* Digital :: Status1000X2 :: rudi_invalid [07:07] */ 30351 #define DIGITAL_STATUS1000X2_RUDI_INVALID_MASK 0x0080 30352 #define DIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN 0 30353 #define DIGITAL_STATUS1000X2_RUDI_INVALID_BITS 1 30354 #define DIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT 7 30355 30356 /* Digital :: Status1000X2 :: linkDown_syncLoss [06:06] */ 30357 #define DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK 0x0040 30358 #define DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN 0 30359 #define DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS 1 30360 #define DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT 6 30361 30362 /* Digital :: Status1000X2 :: idle_detect_state [05:05] */ 30363 #define DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK 0x0020 30364 #define DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN 0 30365 #define DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS 1 30366 #define DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT 5 30367 30368 /* Digital :: Status1000X2 :: complete_acknowledge_state [04:04] */ 30369 #define DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010 30370 #define DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0 30371 #define DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1 30372 #define DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4 30373 30374 /* Digital :: Status1000X2 :: acknowledge_detect_state [03:03] */ 30375 #define DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK 0x0008 30376 #define DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0 30377 #define DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS 1 30378 #define DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3 30379 30380 /* Digital :: Status1000X2 :: ability_detect_state [02:02] */ 30381 #define DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK 0x0004 30382 #define DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN 0 30383 #define DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS 1 30384 #define DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT 2 30385 30386 /* union - case anError [01:01] */ 30387 /* Digital :: Status1000X2 :: an_error_state [01:01] */ 30388 #define DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK 0x0002 30389 #define DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN 0 30390 #define DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS 1 30391 #define DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT 1 30392 30393 30394 /* union - case anDisableLink [01:01] */ 30395 /* Digital :: Status1000X2 :: an_disable_link_ok_state [01:01] */ 30396 #define DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002 30397 #define DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0 30398 #define DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1 30399 #define DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1 30400 30401 30402 /* Digital :: Status1000X2 :: an_enable_state [00:00] */ 30403 #define DIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK 0x0001 30404 #define DIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN 0 30405 #define DIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS 1 30406 #define DIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT 0 30407 30408 30409 /**************************************************************************** 30410 * Digital :: Status1000X3 30411 */ 30412 /* Digital :: Status1000X3 :: reserved0 [15:13] */ 30413 #define DIGITAL_STATUS1000X3_RESERVED0_MASK 0xe000 30414 #define DIGITAL_STATUS1000X3_RESERVED0_ALIGN 0 30415 #define DIGITAL_STATUS1000X3_RESERVED0_BITS 3 30416 #define DIGITAL_STATUS1000X3_RESERVED0_SHIFT 13 30417 30418 /* Digital :: Status1000X3 :: pd_park_an [12:12] */ 30419 #define DIGITAL_STATUS1000X3_PD_PARK_AN_MASK 0x1000 30420 #define DIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN 0 30421 #define DIGITAL_STATUS1000X3_PD_PARK_AN_BITS 1 30422 #define DIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT 12 30423 30424 /* Digital :: Status1000X3 :: remotePhy_autosel [11:11] */ 30425 #define DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK 0x0800 30426 #define DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN 0 30427 #define DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS 1 30428 #define DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT 11 30429 30430 /* Digital :: Status1000X3 :: latch_linkdown [10:10] */ 30431 #define DIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK 0x0400 30432 #define DIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN 0 30433 #define DIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS 1 30434 #define DIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT 10 30435 30436 /* Digital :: Status1000X3 :: sd_filter [09:09] */ 30437 #define DIGITAL_STATUS1000X3_SD_FILTER_MASK 0x0200 30438 #define DIGITAL_STATUS1000X3_SD_FILTER_ALIGN 0 30439 #define DIGITAL_STATUS1000X3_SD_FILTER_BITS 1 30440 #define DIGITAL_STATUS1000X3_SD_FILTER_SHIFT 9 30441 30442 /* Digital :: Status1000X3 :: sd_mux [08:08] */ 30443 #define DIGITAL_STATUS1000X3_SD_MUX_MASK 0x0100 30444 #define DIGITAL_STATUS1000X3_SD_MUX_ALIGN 0 30445 #define DIGITAL_STATUS1000X3_SD_MUX_BITS 1 30446 #define DIGITAL_STATUS1000X3_SD_MUX_SHIFT 8 30447 30448 /* Digital :: Status1000X3 :: sd_filter_chg [07:07] */ 30449 #define DIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK 0x0080 30450 #define DIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN 0 30451 #define DIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS 1 30452 #define DIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT 7 30453 30454 /* Digital :: Status1000X3 :: reserved1 [06:00] */ 30455 #define DIGITAL_STATUS1000X3_RESERVED1_MASK 0x007f 30456 #define DIGITAL_STATUS1000X3_RESERVED1_ALIGN 0 30457 #define DIGITAL_STATUS1000X3_RESERVED1_BITS 7 30458 #define DIGITAL_STATUS1000X3_RESERVED1_SHIFT 0 30459 30460 30461 /**************************************************************************** 30462 * Digital :: BadCodeGroup 30463 */ 30464 /* Digital :: BadCodeGroup :: badCodeGroups [15:08] */ 30465 #define DIGITAL_BADCODEGROUP_BADCODEGROUPS_MASK 0xff00 30466 #define DIGITAL_BADCODEGROUP_BADCODEGROUPS_ALIGN 0 30467 #define DIGITAL_BADCODEGROUP_BADCODEGROUPS_BITS 8 30468 #define DIGITAL_BADCODEGROUP_BADCODEGROUPS_SHIFT 8 30469 30470 /* Digital :: BadCodeGroup :: reserved0 [07:00] */ 30471 #define DIGITAL_BADCODEGROUP_RESERVED0_MASK 0x00ff 30472 #define DIGITAL_BADCODEGROUP_RESERVED0_ALIGN 0 30473 #define DIGITAL_BADCODEGROUP_RESERVED0_BITS 8 30474 #define DIGITAL_BADCODEGROUP_RESERVED0_SHIFT 0 30475 30476 30477 /**************************************************************************** 30478 * Digital :: Misc1 30479 */ 30480 /* Digital :: Misc1 :: refclk_sel [15:13] */ 30481 #define DIGITAL_MISC1_REFCLK_SEL_MASK 0xe000 30482 #define DIGITAL_MISC1_REFCLK_SEL_ALIGN 0 30483 #define DIGITAL_MISC1_REFCLK_SEL_BITS 3 30484 #define DIGITAL_MISC1_REFCLK_SEL_SHIFT 13 30485 #define DIGITAL_MISC1_REFCLK_SEL_clk_25MHz 0 30486 #define DIGITAL_MISC1_REFCLK_SEL_clk_100MHz 1 30487 #define DIGITAL_MISC1_REFCLK_SEL_clk_125MHz 2 30488 #define DIGITAL_MISC1_REFCLK_SEL_clk_156p25MHz 3 30489 #define DIGITAL_MISC1_REFCLK_SEL_clk_187p5MHz 4 30490 30491 /* Digital :: Misc1 :: force_pll_mode_afe_sel [12:12] */ 30492 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_MASK 0x1000 30493 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_ALIGN 0 30494 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_BITS 1 30495 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SEL_SHIFT 12 30496 30497 /* Digital :: Misc1 :: force_pll_mode_afe [11:08] */ 30498 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_MASK 0x0f00 30499 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_ALIGN 0 30500 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_BITS 4 30501 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_SHIFT 8 30502 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div16 0 30503 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div20 1 30504 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div24 2 30505 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div26 3 30506 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div30 4 30507 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div32 5 30508 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div36 6 30509 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div40 7 30510 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div42 8 30511 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div48 9 30512 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div50 10 30513 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div52 11 30514 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div60 12 30515 #define DIGITAL_MISC1_FORCE_PLL_MODE_AFE_div64 13 30516 30517 /* Digital :: Misc1 :: force_tick0_sw2 [07:07] */ 30518 #define DIGITAL_MISC1_FORCE_TICK0_SW2_MASK 0x0080 30519 #define DIGITAL_MISC1_FORCE_TICK0_SW2_ALIGN 0 30520 #define DIGITAL_MISC1_FORCE_TICK0_SW2_BITS 1 30521 #define DIGITAL_MISC1_FORCE_TICK0_SW2_SHIFT 7 30522 30523 /* Digital :: Misc1 :: tx_underrun_1000_dis [06:06] */ 30524 #define DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK 0x0040 30525 #define DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN 0 30526 #define DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS 1 30527 #define DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT 6 30528 30529 /* Digital :: Misc1 :: force_ln_mode [05:05] */ 30530 #define DIGITAL_MISC1_FORCE_LN_MODE_MASK 0x0020 30531 #define DIGITAL_MISC1_FORCE_LN_MODE_ALIGN 0 30532 #define DIGITAL_MISC1_FORCE_LN_MODE_BITS 1 30533 #define DIGITAL_MISC1_FORCE_LN_MODE_SHIFT 5 30534 30535 /* Digital :: Misc1 :: force_speed [04:00] */ 30536 #define DIGITAL_MISC1_FORCE_SPEED_MASK 0x001f 30537 #define DIGITAL_MISC1_FORCE_SPEED_ALIGN 0 30538 #define DIGITAL_MISC1_FORCE_SPEED_BITS 5 30539 #define DIGITAL_MISC1_FORCE_SPEED_SHIFT 0 30540 #define DIGITAL_MISC1_FORCE_SPEED_dr_2500BRCM_X1 16 30541 #define DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X4 17 30542 #define DIGITAL_MISC1_FORCE_SPEED_dr_6000BRCM_X4 18 30543 #define DIGITAL_MISC1_FORCE_SPEED_dr_10GHiGig_X4 19 30544 #define DIGITAL_MISC1_FORCE_SPEED_dr_10GBASE_CX4 20 30545 #define DIGITAL_MISC1_FORCE_SPEED_dr_12GHiGig_X4 21 30546 #define DIGITAL_MISC1_FORCE_SPEED_dr_12p5GHiGig_X4 22 30547 #define DIGITAL_MISC1_FORCE_SPEED_dr_13GHiGig_X4 23 30548 #define DIGITAL_MISC1_FORCE_SPEED_dr_15GHiGig_X4 24 30549 #define DIGITAL_MISC1_FORCE_SPEED_dr_16GHiGig_X4 25 30550 #define DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X1 26 30551 #define DIGITAL_MISC1_FORCE_SPEED_dr_6363BRCM_X1 27 30552 #define DIGITAL_MISC1_FORCE_SPEED_dr_20GHiGig_X4 28 30553 #define DIGITAL_MISC1_FORCE_SPEED_dr_21GHiGig_X4 29 30554 #define DIGITAL_MISC1_FORCE_SPEED_dr_25p45GHiGig_X4 30 30555 30556 30557 /**************************************************************************** 30558 * Digital :: Misc2 30559 */ 30560 /* Digital :: Misc2 :: rxckpl_sel_combo [15:15] */ 30561 #define DIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK 0x8000 30562 #define DIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN 0 30563 #define DIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS 1 30564 #define DIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT 15 30565 30566 /* Digital :: Misc2 :: rxck_mii_gen_sel_force [14:14] */ 30567 #define DIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_MASK 0x4000 30568 #define DIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_ALIGN 0 30569 #define DIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_BITS 1 30570 #define DIGITAL_MISC2_RXCK_MII_GEN_SEL_FORCE_SHIFT 14 30571 30572 /* Digital :: Misc2 :: rxck_mii_gen_sel_val [13:13] */ 30573 #define DIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_MASK 0x2000 30574 #define DIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_ALIGN 0 30575 #define DIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_BITS 1 30576 #define DIGITAL_MISC2_RXCK_MII_GEN_SEL_VAL_SHIFT 13 30577 30578 /* Digital :: Misc2 :: rlpbk_sw_force [12:12] */ 30579 #define DIGITAL_MISC2_RLPBK_SW_FORCE_MASK 0x1000 30580 #define DIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN 0 30581 #define DIGITAL_MISC2_RLPBK_SW_FORCE_BITS 1 30582 #define DIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT 12 30583 30584 /* Digital :: Misc2 :: rlpbk_RxRst_en [11:11] */ 30585 #define DIGITAL_MISC2_RLPBK_RXRST_EN_MASK 0x0800 30586 #define DIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN 0 30587 #define DIGITAL_MISC2_RLPBK_RXRST_EN_BITS 1 30588 #define DIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT 11 30589 30590 /* Digital :: Misc2 :: clkSigdet_bypass [10:10] */ 30591 #define DIGITAL_MISC2_CLKSIGDET_BYPASS_MASK 0x0400 30592 #define DIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN 0 30593 #define DIGITAL_MISC2_CLKSIGDET_BYPASS_BITS 1 30594 #define DIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT 10 30595 30596 /* Digital :: Misc2 :: clk41_bypass [09:09] */ 30597 #define DIGITAL_MISC2_CLK41_BYPASS_MASK 0x0200 30598 #define DIGITAL_MISC2_CLK41_BYPASS_ALIGN 0 30599 #define DIGITAL_MISC2_CLK41_BYPASS_BITS 1 30600 #define DIGITAL_MISC2_CLK41_BYPASS_SHIFT 9 30601 30602 /* Digital :: Misc2 :: miiGmiiDly_en [08:08] */ 30603 #define DIGITAL_MISC2_MIIGMIIDLY_EN_MASK 0x0100 30604 #define DIGITAL_MISC2_MIIGMIIDLY_EN_ALIGN 0 30605 #define DIGITAL_MISC2_MIIGMIIDLY_EN_BITS 1 30606 #define DIGITAL_MISC2_MIIGMIIDLY_EN_SHIFT 8 30607 30608 /* Digital :: Misc2 :: miiGmiiMux_en [07:07] */ 30609 #define DIGITAL_MISC2_MIIGMIIMUX_EN_MASK 0x0080 30610 #define DIGITAL_MISC2_MIIGMIIMUX_EN_ALIGN 0 30611 #define DIGITAL_MISC2_MIIGMIIMUX_EN_BITS 1 30612 #define DIGITAL_MISC2_MIIGMIIMUX_EN_SHIFT 7 30613 30614 /* Digital :: Misc2 :: KX_cl73_an_en [06:06] */ 30615 #define DIGITAL_MISC2_KX_CL73_AN_EN_MASK 0x0040 30616 #define DIGITAL_MISC2_KX_CL73_AN_EN_ALIGN 0 30617 #define DIGITAL_MISC2_KX_CL73_AN_EN_BITS 1 30618 #define DIGITAL_MISC2_KX_CL73_AN_EN_SHIFT 6 30619 30620 /* Digital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */ 30621 #define DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK 0x0020 30622 #define DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN 0 30623 #define DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS 1 30624 #define DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT 5 30625 30626 /* Digital :: Misc2 :: fifo_err_cya [04:04] */ 30627 #define DIGITAL_MISC2_FIFO_ERR_CYA_MASK 0x0010 30628 #define DIGITAL_MISC2_FIFO_ERR_CYA_ALIGN 0 30629 #define DIGITAL_MISC2_FIFO_ERR_CYA_BITS 1 30630 #define DIGITAL_MISC2_FIFO_ERR_CYA_SHIFT 4 30631 30632 /* Digital :: Misc2 :: an_txdisablePhase [03:03] */ 30633 #define DIGITAL_MISC2_AN_TXDISABLEPHASE_MASK 0x0008 30634 #define DIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN 0 30635 #define DIGITAL_MISC2_AN_TXDISABLEPHASE_BITS 1 30636 #define DIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT 3 30637 30638 /* Digital :: Misc2 :: an_rxSeqStartDis [02:02] */ 30639 #define DIGITAL_MISC2_AN_RXSEQSTARTDIS_MASK 0x0004 30640 #define DIGITAL_MISC2_AN_RXSEQSTARTDIS_ALIGN 0 30641 #define DIGITAL_MISC2_AN_RXSEQSTARTDIS_BITS 1 30642 #define DIGITAL_MISC2_AN_RXSEQSTARTDIS_SHIFT 2 30643 30644 /* Digital :: Misc2 :: an_txdisable_ln [01:01] */ 30645 #define DIGITAL_MISC2_AN_TXDISABLE_LN_MASK 0x0002 30646 #define DIGITAL_MISC2_AN_TXDISABLE_LN_ALIGN 0 30647 #define DIGITAL_MISC2_AN_TXDISABLE_LN_BITS 1 30648 #define DIGITAL_MISC2_AN_TXDISABLE_LN_SHIFT 1 30649 30650 /* Digital :: Misc2 :: an_deadTrap [00:00] */ 30651 #define DIGITAL_MISC2_AN_DEADTRAP_MASK 0x0001 30652 #define DIGITAL_MISC2_AN_DEADTRAP_ALIGN 0 30653 #define DIGITAL_MISC2_AN_DEADTRAP_BITS 1 30654 #define DIGITAL_MISC2_AN_DEADTRAP_SHIFT 0 30655 30656 30657 /**************************************************************************** 30658 * Digital :: PatGenCtrl 30659 */ 30660 /* Digital :: PatGenCtrl :: reserved0 [15:15] */ 30661 #define DIGITAL_PATGENCTRL_RESERVED0_MASK 0x8000 30662 #define DIGITAL_PATGENCTRL_RESERVED0_ALIGN 0 30663 #define DIGITAL_PATGENCTRL_RESERVED0_BITS 1 30664 #define DIGITAL_PATGENCTRL_RESERVED0_SHIFT 15 30665 30666 /* Digital :: PatGenCtrl :: tx_err [14:14] */ 30667 #define DIGITAL_PATGENCTRL_TX_ERR_MASK 0x4000 30668 #define DIGITAL_PATGENCTRL_TX_ERR_ALIGN 0 30669 #define DIGITAL_PATGENCTRL_TX_ERR_BITS 1 30670 #define DIGITAL_PATGENCTRL_TX_ERR_SHIFT 14 30671 30672 /* Digital :: PatGenCtrl :: skip_crc [13:13] */ 30673 #define DIGITAL_PATGENCTRL_SKIP_CRC_MASK 0x2000 30674 #define DIGITAL_PATGENCTRL_SKIP_CRC_ALIGN 0 30675 #define DIGITAL_PATGENCTRL_SKIP_CRC_BITS 1 30676 #define DIGITAL_PATGENCTRL_SKIP_CRC_SHIFT 13 30677 30678 /* Digital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */ 30679 #define DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000 30680 #define DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0 30681 #define DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1 30682 #define DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12 30683 30684 /* Digital :: PatGenCtrl :: ipg_select [11:09] */ 30685 #define DIGITAL_PATGENCTRL_IPG_SELECT_MASK 0x0e00 30686 #define DIGITAL_PATGENCTRL_IPG_SELECT_ALIGN 0 30687 #define DIGITAL_PATGENCTRL_IPG_SELECT_BITS 3 30688 #define DIGITAL_PATGENCTRL_IPG_SELECT_SHIFT 9 30689 30690 /* Digital :: PatGenCtrl :: pkt_size [08:03] */ 30691 #define DIGITAL_PATGENCTRL_PKT_SIZE_MASK 0x01f8 30692 #define DIGITAL_PATGENCTRL_PKT_SIZE_ALIGN 0 30693 #define DIGITAL_PATGENCTRL_PKT_SIZE_BITS 6 30694 #define DIGITAL_PATGENCTRL_PKT_SIZE_SHIFT 3 30695 30696 /* Digital :: PatGenCtrl :: single_pass_mode [02:02] */ 30697 #define DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK 0x0004 30698 #define DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN 0 30699 #define DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS 1 30700 #define DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT 2 30701 30702 /* Digital :: PatGenCtrl :: run_pattern_gen [01:01] */ 30703 #define DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK 0x0002 30704 #define DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN 0 30705 #define DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS 1 30706 #define DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT 1 30707 30708 /* Digital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */ 30709 #define DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK 0x0001 30710 #define DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN 0 30711 #define DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS 1 30712 #define DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT 0 30713 30714 30715 /**************************************************************************** 30716 * Digital :: PatGenStat 30717 */ 30718 /* Digital :: PatGenStat :: reserved0 [15:04] */ 30719 #define DIGITAL_PATGENSTAT_RESERVED0_MASK 0xfff0 30720 #define DIGITAL_PATGENSTAT_RESERVED0_ALIGN 0 30721 #define DIGITAL_PATGENSTAT_RESERVED0_BITS 12 30722 #define DIGITAL_PATGENSTAT_RESERVED0_SHIFT 4 30723 30724 /* Digital :: PatGenStat :: pattern_gen_active [03:03] */ 30725 #define DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK 0x0008 30726 #define DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN 0 30727 #define DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS 1 30728 #define DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT 3 30729 30730 /* Digital :: PatGenStat :: pattern_gen_fsm [02:00] */ 30731 #define DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK 0x0007 30732 #define DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN 0 30733 #define DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS 3 30734 #define DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT 0 30735 30736 30737 /**************************************************************************** 30738 * Digital :: TestMode 30739 */ 30740 /* Digital :: TestMode :: disable_reset_cnt [15:15] */ 30741 #define DIGITAL_TESTMODE_DISABLE_RESET_CNT_MASK 0x8000 30742 #define DIGITAL_TESTMODE_DISABLE_RESET_CNT_ALIGN 0 30743 #define DIGITAL_TESTMODE_DISABLE_RESET_CNT_BITS 1 30744 #define DIGITAL_TESTMODE_DISABLE_RESET_CNT_SHIFT 15 30745 30746 /* Digital :: TestMode :: clear_packet_counters [14:14] */ 30747 #define DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_MASK 0x4000 30748 #define DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN 0 30749 #define DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_BITS 1 30750 #define DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT 14 30751 30752 /* Digital :: TestMode :: reserved0 [13:12] */ 30753 #define DIGITAL_TESTMODE_RESERVED0_MASK 0x3000 30754 #define DIGITAL_TESTMODE_RESERVED0_ALIGN 0 30755 #define DIGITAL_TESTMODE_RESERVED0_BITS 2 30756 #define DIGITAL_TESTMODE_RESERVED0_SHIFT 12 30757 30758 /* Digital :: TestMode :: test_monitor_mode2 [11:06] */ 30759 #define DIGITAL_TESTMODE_TEST_MONITOR_MODE2_MASK 0x0fc0 30760 #define DIGITAL_TESTMODE_TEST_MONITOR_MODE2_ALIGN 0 30761 #define DIGITAL_TESTMODE_TEST_MONITOR_MODE2_BITS 6 30762 #define DIGITAL_TESTMODE_TEST_MONITOR_MODE2_SHIFT 6 30763 30764 /* Digital :: TestMode :: test_monitor_mode1 [05:00] */ 30765 #define DIGITAL_TESTMODE_TEST_MONITOR_MODE1_MASK 0x003f 30766 #define DIGITAL_TESTMODE_TEST_MONITOR_MODE1_ALIGN 0 30767 #define DIGITAL_TESTMODE_TEST_MONITOR_MODE1_BITS 6 30768 #define DIGITAL_TESTMODE_TEST_MONITOR_MODE1_SHIFT 0 30769 30770 30771 /**************************************************************************** 30772 * Digital :: TxPktCnt 30773 */ 30774 /* Digital :: TxPktCnt :: TxPktCnt [15:00] */ 30775 #define DIGITAL_TXPKTCNT_TXPKTCNT_MASK 0xffff 30776 #define DIGITAL_TXPKTCNT_TXPKTCNT_ALIGN 0 30777 #define DIGITAL_TXPKTCNT_TXPKTCNT_BITS 16 30778 #define DIGITAL_TXPKTCNT_TXPKTCNT_SHIFT 0 30779 30780 30781 /**************************************************************************** 30782 * Digital :: RxPktCnt 30783 */ 30784 /* Digital :: RxPktCnt :: RxPktCnt [15:00] */ 30785 #define DIGITAL_RXPKTCNT_RXPKTCNT_MASK 0xffff 30786 #define DIGITAL_RXPKTCNT_RXPKTCNT_ALIGN 0 30787 #define DIGITAL_RXPKTCNT_RXPKTCNT_BITS 16 30788 #define DIGITAL_RXPKTCNT_RXPKTCNT_SHIFT 0 30789 30790 30791 /**************************************************************************** 30792 * Hypercore_USER_Test 30793 */ 30794 /**************************************************************************** 30795 * Test :: serdesID0 30796 */ 30797 /* Test :: serdesID0 :: rev_letter [15:14] */ 30798 #define TEST_SERDESID0_REV_LETTER_MASK 0xc000 30799 #define TEST_SERDESID0_REV_LETTER_ALIGN 0 30800 #define TEST_SERDESID0_REV_LETTER_BITS 2 30801 #define TEST_SERDESID0_REV_LETTER_SHIFT 14 30802 30803 /* Test :: serdesID0 :: rev_number [13:11] */ 30804 #define TEST_SERDESID0_REV_NUMBER_MASK 0x3800 30805 #define TEST_SERDESID0_REV_NUMBER_ALIGN 0 30806 #define TEST_SERDESID0_REV_NUMBER_BITS 3 30807 #define TEST_SERDESID0_REV_NUMBER_SHIFT 11 30808 30809 /* Test :: serdesID0 :: bonding [10:09] */ 30810 #define TEST_SERDESID0_BONDING_MASK 0x0600 30811 #define TEST_SERDESID0_BONDING_ALIGN 0 30812 #define TEST_SERDESID0_BONDING_BITS 2 30813 #define TEST_SERDESID0_BONDING_SHIFT 9 30814 30815 /* Test :: serdesID0 :: tech_proc [08:06] */ 30816 #define TEST_SERDESID0_TECH_PROC_MASK 0x01c0 30817 #define TEST_SERDESID0_TECH_PROC_ALIGN 0 30818 #define TEST_SERDESID0_TECH_PROC_BITS 3 30819 #define TEST_SERDESID0_TECH_PROC_SHIFT 6 30820 30821 /* Test :: serdesID0 :: model_number [05:00] */ 30822 #define TEST_SERDESID0_MODEL_NUMBER_MASK 0x003f 30823 #define TEST_SERDESID0_MODEL_NUMBER_ALIGN 0 30824 #define TEST_SERDESID0_MODEL_NUMBER_BITS 6 30825 #define TEST_SERDESID0_MODEL_NUMBER_SHIFT 0 30826 30827 30828 /**************************************************************************** 30829 * Test :: serdesID1 30830 */ 30831 /* Test :: serdesID1 :: multiplicity [15:12] */ 30832 #define TEST_SERDESID1_MULTIPLICITY_MASK 0xf000 30833 #define TEST_SERDESID1_MULTIPLICITY_ALIGN 0 30834 #define TEST_SERDESID1_MULTIPLICITY_BITS 4 30835 #define TEST_SERDESID1_MULTIPLICITY_SHIFT 12 30836 30837 /* Test :: serdesID1 :: CL37 [11:11] */ 30838 #define TEST_SERDESID1_CL37_MASK 0x0800 30839 #define TEST_SERDESID1_CL37_ALIGN 0 30840 #define TEST_SERDESID1_CL37_BITS 1 30841 #define TEST_SERDESID1_CL37_SHIFT 11 30842 30843 /* Test :: serdesID1 :: CL73 [10:10] */ 30844 #define TEST_SERDESID1_CL73_MASK 0x0400 30845 #define TEST_SERDESID1_CL73_ALIGN 0 30846 #define TEST_SERDESID1_CL73_BITS 1 30847 #define TEST_SERDESID1_CL73_SHIFT 10 30848 30849 /* Test :: serdesID1 :: CL36 [09:09] */ 30850 #define TEST_SERDESID1_CL36_MASK 0x0200 30851 #define TEST_SERDESID1_CL36_ALIGN 0 30852 #define TEST_SERDESID1_CL36_BITS 1 30853 #define TEST_SERDESID1_CL36_SHIFT 9 30854 30855 /* Test :: serdesID1 :: CL48 [08:08] */ 30856 #define TEST_SERDESID1_CL48_MASK 0x0100 30857 #define TEST_SERDESID1_CL48_ALIGN 0 30858 #define TEST_SERDESID1_CL48_BITS 1 30859 #define TEST_SERDESID1_CL48_SHIFT 8 30860 30861 /* Test :: serdesID1 :: HiGig [07:07] */ 30862 #define TEST_SERDESID1_HIGIG_MASK 0x0080 30863 #define TEST_SERDESID1_HIGIG_ALIGN 0 30864 #define TEST_SERDESID1_HIGIG_BITS 1 30865 #define TEST_SERDESID1_HIGIG_SHIFT 7 30866 30867 /* Test :: serdesID1 :: HiGigII [06:06] */ 30868 #define TEST_SERDESID1_HIGIGII_MASK 0x0040 30869 #define TEST_SERDESID1_HIGIGII_ALIGN 0 30870 #define TEST_SERDESID1_HIGIGII_BITS 1 30871 #define TEST_SERDESID1_HIGIGII_SHIFT 6 30872 30873 /* Test :: serdesID1 :: PCIE [05:05] */ 30874 #define TEST_SERDESID1_PCIE_MASK 0x0020 30875 #define TEST_SERDESID1_PCIE_ALIGN 0 30876 #define TEST_SERDESID1_PCIE_BITS 1 30877 #define TEST_SERDESID1_PCIE_SHIFT 5 30878 30879 /* Test :: serdesID1 :: PCIE_II [04:04] */ 30880 #define TEST_SERDESID1_PCIE_II_MASK 0x0010 30881 #define TEST_SERDESID1_PCIE_II_ALIGN 0 30882 #define TEST_SERDESID1_PCIE_II_BITS 1 30883 #define TEST_SERDESID1_PCIE_II_SHIFT 4 30884 30885 /* Test :: serdesID1 :: brcm_64B66B [03:03] */ 30886 #define TEST_SERDESID1_BRCM_64B66B_MASK 0x0008 30887 #define TEST_SERDESID1_BRCM_64B66B_ALIGN 0 30888 #define TEST_SERDESID1_BRCM_64B66B_BITS 1 30889 #define TEST_SERDESID1_BRCM_64B66B_SHIFT 3 30890 30891 /* Test :: serdesID1 :: Scrambler [02:02] */ 30892 #define TEST_SERDESID1_SCRAMBLER_MASK 0x0004 30893 #define TEST_SERDESID1_SCRAMBLER_ALIGN 0 30894 #define TEST_SERDESID1_SCRAMBLER_BITS 1 30895 #define TEST_SERDESID1_SCRAMBLER_SHIFT 2 30896 30897 /* Test :: serdesID1 :: reserved0 [01:00] */ 30898 #define TEST_SERDESID1_RESERVED0_MASK 0x0003 30899 #define TEST_SERDESID1_RESERVED0_ALIGN 0 30900 #define TEST_SERDESID1_RESERVED0_BITS 2 30901 #define TEST_SERDESID1_RESERVED0_SHIFT 0 30902 30903 30904 /**************************************************************************** 30905 * Test :: serdesID2 30906 */ 30907 /* Test :: serdesID2 :: ID3present [15:15] */ 30908 #define TEST_SERDESID2_ID3PRESENT_MASK 0x8000 30909 #define TEST_SERDESID2_ID3PRESENT_ALIGN 0 30910 #define TEST_SERDESID2_ID3PRESENT_BITS 1 30911 #define TEST_SERDESID2_ID3PRESENT_SHIFT 15 30912 30913 /* Test :: serdesID2 :: dr_25G_4L [14:14] */ 30914 #define TEST_SERDESID2_DR_25G_4L_MASK 0x4000 30915 #define TEST_SERDESID2_DR_25G_4L_ALIGN 0 30916 #define TEST_SERDESID2_DR_25G_4L_BITS 1 30917 #define TEST_SERDESID2_DR_25G_4L_SHIFT 14 30918 30919 /* Test :: serdesID2 :: dr_21G_4L [13:13] */ 30920 #define TEST_SERDESID2_DR_21G_4L_MASK 0x2000 30921 #define TEST_SERDESID2_DR_21G_4L_ALIGN 0 30922 #define TEST_SERDESID2_DR_21G_4L_BITS 1 30923 #define TEST_SERDESID2_DR_21G_4L_SHIFT 13 30924 30925 /* Test :: serdesID2 :: dr_20G_4L [12:12] */ 30926 #define TEST_SERDESID2_DR_20G_4L_MASK 0x1000 30927 #define TEST_SERDESID2_DR_20G_4L_ALIGN 0 30928 #define TEST_SERDESID2_DR_20G_4L_BITS 1 30929 #define TEST_SERDESID2_DR_20G_4L_SHIFT 12 30930 30931 /* Test :: serdesID2 :: dr_16G_4L [11:11] */ 30932 #define TEST_SERDESID2_DR_16G_4L_MASK 0x0800 30933 #define TEST_SERDESID2_DR_16G_4L_ALIGN 0 30934 #define TEST_SERDESID2_DR_16G_4L_BITS 1 30935 #define TEST_SERDESID2_DR_16G_4L_SHIFT 11 30936 30937 /* Test :: serdesID2 :: dr_15G_4L [10:10] */ 30938 #define TEST_SERDESID2_DR_15G_4L_MASK 0x0400 30939 #define TEST_SERDESID2_DR_15G_4L_ALIGN 0 30940 #define TEST_SERDESID2_DR_15G_4L_BITS 1 30941 #define TEST_SERDESID2_DR_15G_4L_SHIFT 10 30942 30943 /* Test :: serdesID2 :: dr_13G_4L [09:09] */ 30944 #define TEST_SERDESID2_DR_13G_4L_MASK 0x0200 30945 #define TEST_SERDESID2_DR_13G_4L_ALIGN 0 30946 #define TEST_SERDESID2_DR_13G_4L_BITS 1 30947 #define TEST_SERDESID2_DR_13G_4L_SHIFT 9 30948 30949 /* Test :: serdesID2 :: dr_12_5G_4L [08:08] */ 30950 #define TEST_SERDESID2_DR_12_5G_4L_MASK 0x0100 30951 #define TEST_SERDESID2_DR_12_5G_4L_ALIGN 0 30952 #define TEST_SERDESID2_DR_12_5G_4L_BITS 1 30953 #define TEST_SERDESID2_DR_12_5G_4L_SHIFT 8 30954 30955 /* Test :: serdesID2 :: dr_12G_4L [07:07] */ 30956 #define TEST_SERDESID2_DR_12G_4L_MASK 0x0080 30957 #define TEST_SERDESID2_DR_12G_4L_ALIGN 0 30958 #define TEST_SERDESID2_DR_12G_4L_BITS 1 30959 #define TEST_SERDESID2_DR_12G_4L_SHIFT 7 30960 30961 /* Test :: serdesID2 :: dr_10G_4L [06:06] */ 30962 #define TEST_SERDESID2_DR_10G_4L_MASK 0x0040 30963 #define TEST_SERDESID2_DR_10G_4L_ALIGN 0 30964 #define TEST_SERDESID2_DR_10G_4L_BITS 1 30965 #define TEST_SERDESID2_DR_10G_4L_SHIFT 6 30966 30967 /* Test :: serdesID2 :: dr_6G_4L [05:05] */ 30968 #define TEST_SERDESID2_DR_6G_4L_MASK 0x0020 30969 #define TEST_SERDESID2_DR_6G_4L_ALIGN 0 30970 #define TEST_SERDESID2_DR_6G_4L_BITS 1 30971 #define TEST_SERDESID2_DR_6G_4L_SHIFT 5 30972 30973 /* Test :: serdesID2 :: dr_5G_4L [04:04] */ 30974 #define TEST_SERDESID2_DR_5G_4L_MASK 0x0010 30975 #define TEST_SERDESID2_DR_5G_4L_ALIGN 0 30976 #define TEST_SERDESID2_DR_5G_4L_BITS 1 30977 #define TEST_SERDESID2_DR_5G_4L_SHIFT 4 30978 30979 /* Test :: serdesID2 :: dr_2p5G_SL [03:03] */ 30980 #define TEST_SERDESID2_DR_2P5G_SL_MASK 0x0008 30981 #define TEST_SERDESID2_DR_2P5G_SL_ALIGN 0 30982 #define TEST_SERDESID2_DR_2P5G_SL_BITS 1 30983 #define TEST_SERDESID2_DR_2P5G_SL_SHIFT 3 30984 30985 /* Test :: serdesID2 :: dr_1G_SL [02:02] */ 30986 #define TEST_SERDESID2_DR_1G_SL_MASK 0x0004 30987 #define TEST_SERDESID2_DR_1G_SL_ALIGN 0 30988 #define TEST_SERDESID2_DR_1G_SL_BITS 1 30989 #define TEST_SERDESID2_DR_1G_SL_SHIFT 2 30990 30991 /* Test :: serdesID2 :: dr_100M_SL [01:01] */ 30992 #define TEST_SERDESID2_DR_100M_SL_MASK 0x0002 30993 #define TEST_SERDESID2_DR_100M_SL_ALIGN 0 30994 #define TEST_SERDESID2_DR_100M_SL_BITS 1 30995 #define TEST_SERDESID2_DR_100M_SL_SHIFT 1 30996 30997 /* Test :: serdesID2 :: dr_10M_SL [00:00] */ 30998 #define TEST_SERDESID2_DR_10M_SL_MASK 0x0001 30999 #define TEST_SERDESID2_DR_10M_SL_ALIGN 0 31000 #define TEST_SERDESID2_DR_10M_SL_BITS 1 31001 #define TEST_SERDESID2_DR_10M_SL_SHIFT 0 31002 31003 31004 /**************************************************************************** 31005 * Test :: serdesID3 31006 */ 31007 /* Test :: serdesID3 :: reserved0 [15:05] */ 31008 #define TEST_SERDESID3_RESERVED0_MASK 0xffe0 31009 #define TEST_SERDESID3_RESERVED0_ALIGN 0 31010 #define TEST_SERDESID3_RESERVED0_BITS 11 31011 #define TEST_SERDESID3_RESERVED0_SHIFT 5 31012 31013 /* Test :: serdesID3 :: dr_6400_SL [04:04] */ 31014 #define TEST_SERDESID3_DR_6400_SL_MASK 0x0010 31015 #define TEST_SERDESID3_DR_6400_SL_ALIGN 0 31016 #define TEST_SERDESID3_DR_6400_SL_BITS 1 31017 #define TEST_SERDESID3_DR_6400_SL_SHIFT 4 31018 31019 /* Test :: serdesID3 :: dr_5000_SL [03:03] */ 31020 #define TEST_SERDESID3_DR_5000_SL_MASK 0x0008 31021 #define TEST_SERDESID3_DR_5000_SL_ALIGN 0 31022 #define TEST_SERDESID3_DR_5000_SL_BITS 1 31023 #define TEST_SERDESID3_DR_5000_SL_SHIFT 3 31024 31025 /* Test :: serdesID3 :: dr_4000_SL [02:02] */ 31026 #define TEST_SERDESID3_DR_4000_SL_MASK 0x0004 31027 #define TEST_SERDESID3_DR_4000_SL_ALIGN 0 31028 #define TEST_SERDESID3_DR_4000_SL_BITS 1 31029 #define TEST_SERDESID3_DR_4000_SL_SHIFT 2 31030 31031 /* Test :: serdesID3 :: dr_2000_SL [01:01] */ 31032 #define TEST_SERDESID3_DR_2000_SL_MASK 0x0002 31033 #define TEST_SERDESID3_DR_2000_SL_ALIGN 0 31034 #define TEST_SERDESID3_DR_2000_SL_BITS 1 31035 #define TEST_SERDESID3_DR_2000_SL_SHIFT 1 31036 31037 /* Test :: serdesID3 :: dr_100FX [00:00] */ 31038 #define TEST_SERDESID3_DR_100FX_MASK 0x0001 31039 #define TEST_SERDESID3_DR_100FX_ALIGN 0 31040 #define TEST_SERDESID3_DR_100FX_BITS 1 31041 #define TEST_SERDESID3_DR_100FX_SHIFT 0 31042 31043 31044 /**************************************************************************** 31045 * Hypercore_USER_Digital3 31046 */ 31047 /**************************************************************************** 31048 * Digital3 :: digctl_3_0 31049 */ 31050 /* Digital3 :: digctl_3_0 :: an_lostLink_cnt [15:00] */ 31051 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_MASK 0xffff 31052 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_ALIGN 0 31053 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_BITS 16 31054 #define DIGITAL3_DIGCTL_3_0_AN_LOSTLINK_CNT_SHIFT 0 31055 31056 31057 /**************************************************************************** 31058 * Digital3 :: digctl_3_1 31059 */ 31060 /* Digital3 :: digctl_3_1 :: an_switch_cnt [15:00] */ 31061 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_MASK 0xffff 31062 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_ALIGN 0 31063 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_BITS 16 31064 #define DIGITAL3_DIGCTL_3_1_AN_SWITCH_CNT_SHIFT 0 31065 31066 31067 /**************************************************************************** 31068 * Digital3 :: digctl_3_2 31069 */ 31070 /* Digital3 :: digctl_3_2 :: an_link_cnt [15:00] */ 31071 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_MASK 0xffff 31072 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_ALIGN 0 31073 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_BITS 16 31074 #define DIGITAL3_DIGCTL_3_2_AN_LINK_CNT_SHIFT 0 31075 31076 31077 /**************************************************************************** 31078 * Digital3 :: digctl_3_3 31079 */ 31080 /* Digital3 :: digctl_3_3 :: an_switch_cnt2 [15:08] */ 31081 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_MASK 0xff00 31082 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_ALIGN 0 31083 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_BITS 8 31084 #define DIGITAL3_DIGCTL_3_3_AN_SWITCH_CNT2_SHIFT 8 31085 31086 /* Digital3 :: digctl_3_3 :: an_link_cnt2 [07:00] */ 31087 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_MASK 0x00ff 31088 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_ALIGN 0 31089 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_BITS 8 31090 #define DIGITAL3_DIGCTL_3_3_AN_LINK_CNT2_SHIFT 0 31091 31092 31093 /**************************************************************************** 31094 * Digital3 :: digctl_3_4 31095 */ 31096 /* Digital3 :: digctl_3_4 :: mp_number [15:05] */ 31097 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_MASK 0xffe0 31098 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_ALIGN 0 31099 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_BITS 11 31100 #define DIGITAL3_DIGCTL_3_4_MP_NUMBER_SHIFT 5 31101 31102 /* Digital3 :: digctl_3_4 :: no_fail_cnt [04:04] */ 31103 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_MASK 0x0010 31104 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_ALIGN 0 31105 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_BITS 1 31106 #define DIGITAL3_DIGCTL_3_4_NO_FAIL_CNT_SHIFT 4 31107 31108 /* Digital3 :: digctl_3_4 :: an_fail_cnt [03:00] */ 31109 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_MASK 0x000f 31110 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_ALIGN 0 31111 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_BITS 4 31112 #define DIGITAL3_DIGCTL_3_4_AN_FAIL_CNT_SHIFT 0 31113 31114 31115 /**************************************************************************** 31116 * Digital3 :: digctl_3_5 31117 */ 31118 /* Digital3 :: digctl_3_5 :: an_ignoreLink_cnt [15:00] */ 31119 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_MASK 0xffff 31120 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_ALIGN 0 31121 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_BITS 16 31122 #define DIGITAL3_DIGCTL_3_5_AN_IGNORELINK_CNT_SHIFT 0 31123 31124 31125 /**************************************************************************** 31126 * Digital3 :: digctl_3_6 31127 */ 31128 /* Digital3 :: digctl_3_6 :: an_lostLink_cnt2 [15:08] */ 31129 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_MASK 0xff00 31130 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_ALIGN 0 31131 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_BITS 8 31132 #define DIGITAL3_DIGCTL_3_6_AN_LOSTLINK_CNT2_SHIFT 8 31133 31134 /* Digital3 :: digctl_3_6 :: an_ingoreLink_cnt2 [07:00] */ 31135 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_MASK 0x00ff 31136 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_ALIGN 0 31137 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_BITS 8 31138 #define DIGITAL3_DIGCTL_3_6_AN_INGORELINK_CNT2_SHIFT 0 31139 31140 31141 /**************************************************************************** 31142 * Digital3 :: TPOUT_1 31143 */ 31144 /* Digital3 :: TPOUT_1 :: tpout1 [15:00] */ 31145 #define DIGITAL3_TPOUT_1_TPOUT1_MASK 0xffff 31146 #define DIGITAL3_TPOUT_1_TPOUT1_ALIGN 0 31147 #define DIGITAL3_TPOUT_1_TPOUT1_BITS 16 31148 #define DIGITAL3_TPOUT_1_TPOUT1_SHIFT 0 31149 31150 31151 /**************************************************************************** 31152 * Digital3 :: TPOUT_2 31153 */ 31154 /* Digital3 :: TPOUT_2 :: tpout2 [15:00] */ 31155 #define DIGITAL3_TPOUT_2_TPOUT2_MASK 0xffff 31156 #define DIGITAL3_TPOUT_2_TPOUT2_ALIGN 0 31157 #define DIGITAL3_TPOUT_2_TPOUT2_BITS 16 31158 #define DIGITAL3_TPOUT_2_TPOUT2_SHIFT 0 31159 31160 31161 /**************************************************************************** 31162 * Digital3 :: UP1 31163 */ 31164 /* Digital3 :: UP1 :: reserved0 [15:11] */ 31165 #define DIGITAL3_UP1_RESERVED0_MASK 0xf800 31166 #define DIGITAL3_UP1_RESERVED0_ALIGN 0 31167 #define DIGITAL3_UP1_RESERVED0_BITS 5 31168 #define DIGITAL3_UP1_RESERVED0_SHIFT 11 31169 31170 /* Digital3 :: UP1 :: dataRate_20GX4 [10:10] */ 31171 #define DIGITAL3_UP1_DATARATE_20GX4_MASK 0x0400 31172 #define DIGITAL3_UP1_DATARATE_20GX4_ALIGN 0 31173 #define DIGITAL3_UP1_DATARATE_20GX4_BITS 1 31174 #define DIGITAL3_UP1_DATARATE_20GX4_SHIFT 10 31175 31176 /* Digital3 :: UP1 :: dataRate_16GX4 [09:09] */ 31177 #define DIGITAL3_UP1_DATARATE_16GX4_MASK 0x0200 31178 #define DIGITAL3_UP1_DATARATE_16GX4_ALIGN 0 31179 #define DIGITAL3_UP1_DATARATE_16GX4_BITS 1 31180 #define DIGITAL3_UP1_DATARATE_16GX4_SHIFT 9 31181 31182 /* Digital3 :: UP1 :: dataRate_15GX4 [08:08] */ 31183 #define DIGITAL3_UP1_DATARATE_15GX4_MASK 0x0100 31184 #define DIGITAL3_UP1_DATARATE_15GX4_ALIGN 0 31185 #define DIGITAL3_UP1_DATARATE_15GX4_BITS 1 31186 #define DIGITAL3_UP1_DATARATE_15GX4_SHIFT 8 31187 31188 /* Digital3 :: UP1 :: dataRate_13GX4 [07:07] */ 31189 #define DIGITAL3_UP1_DATARATE_13GX4_MASK 0x0080 31190 #define DIGITAL3_UP1_DATARATE_13GX4_ALIGN 0 31191 #define DIGITAL3_UP1_DATARATE_13GX4_BITS 1 31192 #define DIGITAL3_UP1_DATARATE_13GX4_SHIFT 7 31193 31194 /* Digital3 :: UP1 :: dataRate_12p5GX4 [06:06] */ 31195 #define DIGITAL3_UP1_DATARATE_12P5GX4_MASK 0x0040 31196 #define DIGITAL3_UP1_DATARATE_12P5GX4_ALIGN 0 31197 #define DIGITAL3_UP1_DATARATE_12P5GX4_BITS 1 31198 #define DIGITAL3_UP1_DATARATE_12P5GX4_SHIFT 6 31199 31200 /* Digital3 :: UP1 :: dataRate_12GX4 [05:05] */ 31201 #define DIGITAL3_UP1_DATARATE_12GX4_MASK 0x0020 31202 #define DIGITAL3_UP1_DATARATE_12GX4_ALIGN 0 31203 #define DIGITAL3_UP1_DATARATE_12GX4_BITS 1 31204 #define DIGITAL3_UP1_DATARATE_12GX4_SHIFT 5 31205 31206 /* Digital3 :: UP1 :: dataRate_10GCX4 [04:04] */ 31207 #define DIGITAL3_UP1_DATARATE_10GCX4_MASK 0x0010 31208 #define DIGITAL3_UP1_DATARATE_10GCX4_ALIGN 0 31209 #define DIGITAL3_UP1_DATARATE_10GCX4_BITS 1 31210 #define DIGITAL3_UP1_DATARATE_10GCX4_SHIFT 4 31211 31212 /* Digital3 :: UP1 :: dataRate_10GX4 [03:03] */ 31213 #define DIGITAL3_UP1_DATARATE_10GX4_MASK 0x0008 31214 #define DIGITAL3_UP1_DATARATE_10GX4_ALIGN 0 31215 #define DIGITAL3_UP1_DATARATE_10GX4_BITS 1 31216 #define DIGITAL3_UP1_DATARATE_10GX4_SHIFT 3 31217 31218 /* Digital3 :: UP1 :: dataRate_6GX4 [02:02] */ 31219 #define DIGITAL3_UP1_DATARATE_6GX4_MASK 0x0004 31220 #define DIGITAL3_UP1_DATARATE_6GX4_ALIGN 0 31221 #define DIGITAL3_UP1_DATARATE_6GX4_BITS 1 31222 #define DIGITAL3_UP1_DATARATE_6GX4_SHIFT 2 31223 31224 /* Digital3 :: UP1 :: dataRate_5GX4 [01:01] */ 31225 #define DIGITAL3_UP1_DATARATE_5GX4_MASK 0x0002 31226 #define DIGITAL3_UP1_DATARATE_5GX4_ALIGN 0 31227 #define DIGITAL3_UP1_DATARATE_5GX4_BITS 1 31228 #define DIGITAL3_UP1_DATARATE_5GX4_SHIFT 1 31229 31230 /* Digital3 :: UP1 :: dataRate_2p5GX1 [00:00] */ 31231 #define DIGITAL3_UP1_DATARATE_2P5GX1_MASK 0x0001 31232 #define DIGITAL3_UP1_DATARATE_2P5GX1_ALIGN 0 31233 #define DIGITAL3_UP1_DATARATE_2P5GX1_BITS 1 31234 #define DIGITAL3_UP1_DATARATE_2P5GX1_SHIFT 0 31235 31236 31237 /**************************************************************************** 31238 * Digital3 :: UP2 31239 */ 31240 /* Digital3 :: UP2 :: reserved0 [15:11] */ 31241 #define DIGITAL3_UP2_RESERVED0_MASK 0xf800 31242 #define DIGITAL3_UP2_RESERVED0_ALIGN 0 31243 #define DIGITAL3_UP2_RESERVED0_BITS 5 31244 #define DIGITAL3_UP2_RESERVED0_SHIFT 11 31245 31246 /* Digital3 :: UP2 :: valid [10:10] */ 31247 #define DIGITAL3_UP2_VALID_MASK 0x0400 31248 #define DIGITAL3_UP2_VALID_ALIGN 0 31249 #define DIGITAL3_UP2_VALID_BITS 1 31250 #define DIGITAL3_UP2_VALID_SHIFT 10 31251 31252 /* Digital3 :: UP2 :: preemphasis [09:06] */ 31253 #define DIGITAL3_UP2_PREEMPHASIS_MASK 0x03c0 31254 #define DIGITAL3_UP2_PREEMPHASIS_ALIGN 0 31255 #define DIGITAL3_UP2_PREEMPHASIS_BITS 4 31256 #define DIGITAL3_UP2_PREEMPHASIS_SHIFT 6 31257 31258 /* Digital3 :: UP2 :: idriver [05:03] */ 31259 #define DIGITAL3_UP2_IDRIVER_MASK 0x0038 31260 #define DIGITAL3_UP2_IDRIVER_ALIGN 0 31261 #define DIGITAL3_UP2_IDRIVER_BITS 3 31262 #define DIGITAL3_UP2_IDRIVER_SHIFT 3 31263 31264 /* Digital3 :: UP2 :: ipredriver [02:00] */ 31265 #define DIGITAL3_UP2_IPREDRIVER_MASK 0x0007 31266 #define DIGITAL3_UP2_IPREDRIVER_ALIGN 0 31267 #define DIGITAL3_UP2_IPREDRIVER_BITS 3 31268 #define DIGITAL3_UP2_IPREDRIVER_SHIFT 0 31269 31270 31271 /**************************************************************************** 31272 * Digital3 :: UP3 31273 */ 31274 /* Digital3 :: UP3 :: reserved0 [15:11] */ 31275 #define DIGITAL3_UP3_RESERVED0_MASK 0xf800 31276 #define DIGITAL3_UP3_RESERVED0_ALIGN 0 31277 #define DIGITAL3_UP3_RESERVED0_BITS 5 31278 #define DIGITAL3_UP3_RESERVED0_SHIFT 11 31279 31280 /* Digital3 :: UP3 :: last [10:10] */ 31281 #define DIGITAL3_UP3_LAST_MASK 0x0400 31282 #define DIGITAL3_UP3_LAST_ALIGN 0 31283 #define DIGITAL3_UP3_LAST_BITS 1 31284 #define DIGITAL3_UP3_LAST_SHIFT 10 31285 31286 /* Digital3 :: UP3 :: dataRate_21GX4 [09:09] */ 31287 #define DIGITAL3_UP3_DATARATE_21GX4_MASK 0x0200 31288 #define DIGITAL3_UP3_DATARATE_21GX4_ALIGN 0 31289 #define DIGITAL3_UP3_DATARATE_21GX4_BITS 1 31290 #define DIGITAL3_UP3_DATARATE_21GX4_SHIFT 9 31291 31292 /* Digital3 :: UP3 :: dataRate_25p45GX4 [08:08] */ 31293 #define DIGITAL3_UP3_DATARATE_25P45GX4_MASK 0x0100 31294 #define DIGITAL3_UP3_DATARATE_25P45GX4_ALIGN 0 31295 #define DIGITAL3_UP3_DATARATE_25P45GX4_BITS 1 31296 #define DIGITAL3_UP3_DATARATE_25P45GX4_SHIFT 8 31297 31298 /* Digital3 :: UP3 :: reserved1 [07:02] */ 31299 #define DIGITAL3_UP3_RESERVED1_MASK 0x00fc 31300 #define DIGITAL3_UP3_RESERVED1_ALIGN 0 31301 #define DIGITAL3_UP3_RESERVED1_BITS 6 31302 #define DIGITAL3_UP3_RESERVED1_SHIFT 2 31303 31304 /* Digital3 :: UP3 :: scramble_8B10B [01:01] */ 31305 #define DIGITAL3_UP3_SCRAMBLE_8B10B_MASK 0x0002 31306 #define DIGITAL3_UP3_SCRAMBLE_8B10B_ALIGN 0 31307 #define DIGITAL3_UP3_SCRAMBLE_8B10B_BITS 1 31308 #define DIGITAL3_UP3_SCRAMBLE_8B10B_SHIFT 1 31309 31310 /* Digital3 :: UP3 :: HiGig2 [00:00] */ 31311 #define DIGITAL3_UP3_HIGIG2_MASK 0x0001 31312 #define DIGITAL3_UP3_HIGIG2_ALIGN 0 31313 #define DIGITAL3_UP3_HIGIG2_BITS 1 31314 #define DIGITAL3_UP3_HIGIG2_SHIFT 0 31315 31316 31317 /**************************************************************************** 31318 * Digital3 :: LP_UP1 31319 */ 31320 /* Digital3 :: LP_UP1 :: reserved0 [15:11] */ 31321 #define DIGITAL3_LP_UP1_RESERVED0_MASK 0xf800 31322 #define DIGITAL3_LP_UP1_RESERVED0_ALIGN 0 31323 #define DIGITAL3_LP_UP1_RESERVED0_BITS 5 31324 #define DIGITAL3_LP_UP1_RESERVED0_SHIFT 11 31325 31326 /* Digital3 :: LP_UP1 :: dataRate_20GX4 [10:10] */ 31327 #define DIGITAL3_LP_UP1_DATARATE_20GX4_MASK 0x0400 31328 #define DIGITAL3_LP_UP1_DATARATE_20GX4_ALIGN 0 31329 #define DIGITAL3_LP_UP1_DATARATE_20GX4_BITS 1 31330 #define DIGITAL3_LP_UP1_DATARATE_20GX4_SHIFT 10 31331 31332 /* Digital3 :: LP_UP1 :: dataRate_16GX4 [09:09] */ 31333 #define DIGITAL3_LP_UP1_DATARATE_16GX4_MASK 0x0200 31334 #define DIGITAL3_LP_UP1_DATARATE_16GX4_ALIGN 0 31335 #define DIGITAL3_LP_UP1_DATARATE_16GX4_BITS 1 31336 #define DIGITAL3_LP_UP1_DATARATE_16GX4_SHIFT 9 31337 31338 /* Digital3 :: LP_UP1 :: dataRate_15GX4 [08:08] */ 31339 #define DIGITAL3_LP_UP1_DATARATE_15GX4_MASK 0x0100 31340 #define DIGITAL3_LP_UP1_DATARATE_15GX4_ALIGN 0 31341 #define DIGITAL3_LP_UP1_DATARATE_15GX4_BITS 1 31342 #define DIGITAL3_LP_UP1_DATARATE_15GX4_SHIFT 8 31343 31344 /* Digital3 :: LP_UP1 :: dataRate_13GX4 [07:07] */ 31345 #define DIGITAL3_LP_UP1_DATARATE_13GX4_MASK 0x0080 31346 #define DIGITAL3_LP_UP1_DATARATE_13GX4_ALIGN 0 31347 #define DIGITAL3_LP_UP1_DATARATE_13GX4_BITS 1 31348 #define DIGITAL3_LP_UP1_DATARATE_13GX4_SHIFT 7 31349 31350 /* Digital3 :: LP_UP1 :: dataRate_12p5GX4 [06:06] */ 31351 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_MASK 0x0040 31352 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_ALIGN 0 31353 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_BITS 1 31354 #define DIGITAL3_LP_UP1_DATARATE_12P5GX4_SHIFT 6 31355 31356 /* Digital3 :: LP_UP1 :: dataRate_12GX4 [05:05] */ 31357 #define DIGITAL3_LP_UP1_DATARATE_12GX4_MASK 0x0020 31358 #define DIGITAL3_LP_UP1_DATARATE_12GX4_ALIGN 0 31359 #define DIGITAL3_LP_UP1_DATARATE_12GX4_BITS 1 31360 #define DIGITAL3_LP_UP1_DATARATE_12GX4_SHIFT 5 31361 31362 /* Digital3 :: LP_UP1 :: dataRate_10GCX4 [04:04] */ 31363 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_MASK 0x0010 31364 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_ALIGN 0 31365 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_BITS 1 31366 #define DIGITAL3_LP_UP1_DATARATE_10GCX4_SHIFT 4 31367 31368 /* Digital3 :: LP_UP1 :: dataRate_10GX4 [03:03] */ 31369 #define DIGITAL3_LP_UP1_DATARATE_10GX4_MASK 0x0008 31370 #define DIGITAL3_LP_UP1_DATARATE_10GX4_ALIGN 0 31371 #define DIGITAL3_LP_UP1_DATARATE_10GX4_BITS 1 31372 #define DIGITAL3_LP_UP1_DATARATE_10GX4_SHIFT 3 31373 31374 /* Digital3 :: LP_UP1 :: dataRate_6GX4 [02:02] */ 31375 #define DIGITAL3_LP_UP1_DATARATE_6GX4_MASK 0x0004 31376 #define DIGITAL3_LP_UP1_DATARATE_6GX4_ALIGN 0 31377 #define DIGITAL3_LP_UP1_DATARATE_6GX4_BITS 1 31378 #define DIGITAL3_LP_UP1_DATARATE_6GX4_SHIFT 2 31379 31380 /* Digital3 :: LP_UP1 :: dataRate_5GX4 [01:01] */ 31381 #define DIGITAL3_LP_UP1_DATARATE_5GX4_MASK 0x0002 31382 #define DIGITAL3_LP_UP1_DATARATE_5GX4_ALIGN 0 31383 #define DIGITAL3_LP_UP1_DATARATE_5GX4_BITS 1 31384 #define DIGITAL3_LP_UP1_DATARATE_5GX4_SHIFT 1 31385 31386 /* Digital3 :: LP_UP1 :: dataRate_2p5GX1 [00:00] */ 31387 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_MASK 0x0001 31388 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_ALIGN 0 31389 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_BITS 1 31390 #define DIGITAL3_LP_UP1_DATARATE_2P5GX1_SHIFT 0 31391 31392 31393 /**************************************************************************** 31394 * Digital3 :: LP_UP2 31395 */ 31396 /* Digital3 :: LP_UP2 :: reserved0 [15:11] */ 31397 #define DIGITAL3_LP_UP2_RESERVED0_MASK 0xf800 31398 #define DIGITAL3_LP_UP2_RESERVED0_ALIGN 0 31399 #define DIGITAL3_LP_UP2_RESERVED0_BITS 5 31400 #define DIGITAL3_LP_UP2_RESERVED0_SHIFT 11 31401 31402 /* Digital3 :: LP_UP2 :: valid [10:10] */ 31403 #define DIGITAL3_LP_UP2_VALID_MASK 0x0400 31404 #define DIGITAL3_LP_UP2_VALID_ALIGN 0 31405 #define DIGITAL3_LP_UP2_VALID_BITS 1 31406 #define DIGITAL3_LP_UP2_VALID_SHIFT 10 31407 31408 /* Digital3 :: LP_UP2 :: preemphasis [09:06] */ 31409 #define DIGITAL3_LP_UP2_PREEMPHASIS_MASK 0x03c0 31410 #define DIGITAL3_LP_UP2_PREEMPHASIS_ALIGN 0 31411 #define DIGITAL3_LP_UP2_PREEMPHASIS_BITS 4 31412 #define DIGITAL3_LP_UP2_PREEMPHASIS_SHIFT 6 31413 31414 /* Digital3 :: LP_UP2 :: idriver [05:03] */ 31415 #define DIGITAL3_LP_UP2_IDRIVER_MASK 0x0038 31416 #define DIGITAL3_LP_UP2_IDRIVER_ALIGN 0 31417 #define DIGITAL3_LP_UP2_IDRIVER_BITS 3 31418 #define DIGITAL3_LP_UP2_IDRIVER_SHIFT 3 31419 31420 /* Digital3 :: LP_UP2 :: ipredriver [02:00] */ 31421 #define DIGITAL3_LP_UP2_IPREDRIVER_MASK 0x0007 31422 #define DIGITAL3_LP_UP2_IPREDRIVER_ALIGN 0 31423 #define DIGITAL3_LP_UP2_IPREDRIVER_BITS 3 31424 #define DIGITAL3_LP_UP2_IPREDRIVER_SHIFT 0 31425 31426 31427 /**************************************************************************** 31428 * Digital3 :: LP_UP3 31429 */ 31430 /* Digital3 :: LP_UP3 :: reserved0 [15:11] */ 31431 #define DIGITAL3_LP_UP3_RESERVED0_MASK 0xf800 31432 #define DIGITAL3_LP_UP3_RESERVED0_ALIGN 0 31433 #define DIGITAL3_LP_UP3_RESERVED0_BITS 5 31434 #define DIGITAL3_LP_UP3_RESERVED0_SHIFT 11 31435 31436 /* Digital3 :: LP_UP3 :: last [10:10] */ 31437 #define DIGITAL3_LP_UP3_LAST_MASK 0x0400 31438 #define DIGITAL3_LP_UP3_LAST_ALIGN 0 31439 #define DIGITAL3_LP_UP3_LAST_BITS 1 31440 #define DIGITAL3_LP_UP3_LAST_SHIFT 10 31441 31442 /* Digital3 :: LP_UP3 :: dataRate_21GX4 [09:09] */ 31443 #define DIGITAL3_LP_UP3_DATARATE_21GX4_MASK 0x0200 31444 #define DIGITAL3_LP_UP3_DATARATE_21GX4_ALIGN 0 31445 #define DIGITAL3_LP_UP3_DATARATE_21GX4_BITS 1 31446 #define DIGITAL3_LP_UP3_DATARATE_21GX4_SHIFT 9 31447 31448 /* Digital3 :: LP_UP3 :: dataRate_25p45GX4 [08:08] */ 31449 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_MASK 0x0100 31450 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_ALIGN 0 31451 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_BITS 1 31452 #define DIGITAL3_LP_UP3_DATARATE_25P45GX4_SHIFT 8 31453 31454 /* Digital3 :: LP_UP3 :: reserved1 [07:02] */ 31455 #define DIGITAL3_LP_UP3_RESERVED1_MASK 0x00fc 31456 #define DIGITAL3_LP_UP3_RESERVED1_ALIGN 0 31457 #define DIGITAL3_LP_UP3_RESERVED1_BITS 6 31458 #define DIGITAL3_LP_UP3_RESERVED1_SHIFT 2 31459 31460 /* Digital3 :: LP_UP3 :: scramble_8B10B [01:01] */ 31461 #define DIGITAL3_LP_UP3_SCRAMBLE_8B10B_MASK 0x0002 31462 #define DIGITAL3_LP_UP3_SCRAMBLE_8B10B_ALIGN 0 31463 #define DIGITAL3_LP_UP3_SCRAMBLE_8B10B_BITS 1 31464 #define DIGITAL3_LP_UP3_SCRAMBLE_8B10B_SHIFT 1 31465 31466 /* Digital3 :: LP_UP3 :: HiGig2 [00:00] */ 31467 #define DIGITAL3_LP_UP3_HIGIG2_MASK 0x0001 31468 #define DIGITAL3_LP_UP3_HIGIG2_ALIGN 0 31469 #define DIGITAL3_LP_UP3_HIGIG2_BITS 1 31470 #define DIGITAL3_LP_UP3_HIGIG2_SHIFT 0 31471 31472 31473 /**************************************************************************** 31474 * Hypercore_USER_Digital4 31475 */ 31476 /**************************************************************************** 31477 * Digital4 :: MiscRxStatus 31478 */ 31479 /* union - case statusSelect0 [15:00] */ 31480 /* Digital4 :: MiscRxStatus :: capture_NP_lh [15:15] */ 31481 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_MASK 0x8000 31482 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_ALIGN 0 31483 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_BITS 1 31484 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_CAPTURE_NP_LH_SHIFT 15 31485 31486 /* Digital4 :: MiscRxStatus :: teton_brk_link_lh [14:14] */ 31487 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_MASK 0x4000 31488 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_ALIGN 0 31489 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_BITS 1 31490 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_TETON_BRK_LINK_LH_SHIFT 14 31491 31492 /* Digital4 :: MiscRxStatus :: UP3_lh [13:13] */ 31493 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_MASK 0x2000 31494 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_ALIGN 0 31495 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_BITS 1 31496 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_UP3_LH_SHIFT 13 31497 31498 /* Digital4 :: MiscRxStatus :: MP5_lh [12:12] */ 31499 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_MASK 0x1000 31500 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_ALIGN 0 31501 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_BITS 1 31502 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MP5_LH_SHIFT 12 31503 31504 /* Digital4 :: MiscRxStatus :: nonMatchingOUI_lh [11:11] */ 31505 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_MASK 0x0800 31506 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_ALIGN 0 31507 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_BITS 1 31508 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGOUI_LH_SHIFT 11 31509 31510 /* Digital4 :: MiscRxStatus :: matchingOUI_msb_lh [10:10] */ 31511 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_MASK 0x0400 31512 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_ALIGN 0 31513 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_BITS 1 31514 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_MSB_LH_SHIFT 10 31515 31516 /* Digital4 :: MiscRxStatus :: matchingOUI_lsb_lh [09:09] */ 31517 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_MASK 0x0200 31518 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_ALIGN 0 31519 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_BITS 1 31520 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MATCHINGOUI_LSB_LH_SHIFT 9 31521 31522 /* Digital4 :: MiscRxStatus :: invalidSeq_lh [08:08] */ 31523 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_MASK 0x0100 31524 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_ALIGN 0 31525 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_BITS 1 31526 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_INVALIDSEQ_LH_SHIFT 8 31527 31528 /* Digital4 :: MiscRxStatus :: nullMP_lh [07:07] */ 31529 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_MASK 0x0080 31530 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_ALIGN 0 31531 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_BITS 1 31532 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NULLMP_LH_SHIFT 7 31533 31534 /* Digital4 :: MiscRxStatus :: remotePhyMP_lh [06:06] */ 31535 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_MASK 0x0040 31536 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_ALIGN 0 31537 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_BITS 1 31538 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_REMOTEPHYMP_LH_SHIFT 6 31539 31540 /* Digital4 :: MiscRxStatus :: nonMatchingMP_lh [05:05] */ 31541 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_MASK 0x0020 31542 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_ALIGN 0 31543 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_BITS 1 31544 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NONMATCHINGMP_LH_SHIFT 5 31545 31546 /* Digital4 :: MiscRxStatus :: over1gMP_lh [04:04] */ 31547 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_MASK 0x0010 31548 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_ALIGN 0 31549 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_BITS 1 31550 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_OVER1GMP_LH_SHIFT 4 31551 31552 /* Digital4 :: MiscRxStatus :: rx_config_is_0_lh [03:03] */ 31553 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_MASK 0x0008 31554 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_ALIGN 0 31555 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_BITS 1 31556 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_RX_CONFIG_IS_0_LH_SHIFT 3 31557 31558 /* Digital4 :: MiscRxStatus :: np_toggle_err_lh [02:02] */ 31559 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_MASK 0x0004 31560 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_ALIGN 0 31561 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_BITS 1 31562 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_NP_TOGGLE_ERR_LH_SHIFT 2 31563 31564 /* Digital4 :: MiscRxStatus :: mr_np_lh [01:01] */ 31565 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_MASK 0x0002 31566 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_ALIGN 0 31567 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_BITS 1 31568 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_NP_LH_SHIFT 1 31569 31570 /* Digital4 :: MiscRxStatus :: mr_bp_lh [00:00] */ 31571 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_MASK 0x0001 31572 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_ALIGN 0 31573 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_BITS 1 31574 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT0_MR_BP_LH_SHIFT 0 31575 31576 31577 /* union - case statusSelect1 [15:00] */ 31578 /* Digital4 :: MiscRxStatus :: reserved0 [15:04] */ 31579 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_MASK 0xfff0 31580 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_ALIGN 0 31581 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_BITS 12 31582 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_RESERVED0_SHIFT 4 31583 31584 /* Digital4 :: MiscRxStatus :: np_count [03:00] */ 31585 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_MASK 0x000f 31586 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_ALIGN 0 31587 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_BITS 4 31588 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT1_NP_COUNT_SHIFT 0 31589 31590 31591 /* union - case statusSelect2 [15:00] */ 31592 /* Digital4 :: MiscRxStatus :: reserved0 [15:06] */ 31593 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_MASK 0xffc0 31594 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_ALIGN 0 31595 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_BITS 10 31596 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RESERVED0_SHIFT 6 31597 31598 /* Digital4 :: MiscRxStatus :: remote_phy_enable [05:05] */ 31599 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_MASK 0x0020 31600 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_ALIGN 0 31601 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_BITS 1 31602 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTE_PHY_ENABLE_SHIFT 5 31603 31604 /* Digital4 :: MiscRxStatus :: det_teton_mode [04:04] */ 31605 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_MASK 0x0010 31606 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_ALIGN 0 31607 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_BITS 1 31608 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_DET_TETON_MODE_SHIFT 4 31609 31610 /* Digital4 :: MiscRxStatus :: cu_linkdown [03:03] */ 31611 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_MASK 0x0008 31612 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_ALIGN 0 31613 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_BITS 1 31614 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_LINKDOWN_SHIFT 3 31615 31616 /* Digital4 :: MiscRxStatus :: cu_resolution_error [02:02] */ 31617 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_MASK 0x0004 31618 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_ALIGN 0 31619 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_BITS 1 31620 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_CU_RESOLUTION_ERROR_SHIFT 2 31621 31622 /* Digital4 :: MiscRxStatus :: remotePhy_autosel [01:01] */ 31623 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_MASK 0x0002 31624 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_ALIGN 0 31625 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_BITS 1 31626 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_REMOTEPHY_AUTOSEL_SHIFT 1 31627 31628 /* Digital4 :: MiscRxStatus :: rx_config_isNot_0_lh [00:00] */ 31629 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_MASK 0x0001 31630 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_ALIGN 0 31631 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_BITS 1 31632 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT2_RX_CONFIG_ISNOT_0_LH_SHIFT 0 31633 31634 31635 /* union - case statusSelect3 [15:00] */ 31636 /* Digital4 :: MiscRxStatus :: reserved0 [15:06] */ 31637 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_MASK 0xffc0 31638 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_ALIGN 0 31639 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_BITS 10 31640 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_RESERVED0_SHIFT 6 31641 31642 /* Digital4 :: MiscRxStatus :: sgmii_selector_mismatch [05:05] */ 31643 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_MASK 0x0020 31644 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_ALIGN 0 31645 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_BITS 1 31646 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_SGMII_SELECTOR_MISMATCH_SHIFT 5 31647 31648 /* Digital4 :: MiscRxStatus :: autoneg_enable_ov [04:04] */ 31649 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_MASK 0x0010 31650 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_ALIGN 0 31651 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_BITS 1 31652 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_AUTONEG_ENABLE_OV_SHIFT 4 31653 31654 /* Digital4 :: MiscRxStatus :: s_mr_an_enable [03:03] */ 31655 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_MASK 0x0008 31656 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_ALIGN 0 31657 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_BITS 1 31658 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_MR_AN_ENABLE_SHIFT 3 31659 31660 /* Digital4 :: MiscRxStatus :: s_cl73_rslv_KX4 [02:02] */ 31661 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_MASK 0x0004 31662 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_ALIGN 0 31663 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_BITS 1 31664 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX4_SHIFT 2 31665 31666 /* Digital4 :: MiscRxStatus :: s_cl73_rslv_KX [01:01] */ 31667 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_MASK 0x0002 31668 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_ALIGN 0 31669 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_BITS 1 31670 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_S_CL73_RSLV_KX_SHIFT 1 31671 31672 /* Digital4 :: MiscRxStatus :: KX_detect [00:00] */ 31673 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_MASK 0x0001 31674 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_ALIGN 0 31675 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_BITS 1 31676 #define DIGITAL4_MISCRXSTATUS_STATUSSELECT3_KX_DETECT_SHIFT 0 31677 31678 31679 31680 /**************************************************************************** 31681 * Digital4 :: lp_basePage 31682 */ 31683 /* Digital4 :: lp_basePage :: lp_basePage [15:00] */ 31684 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_MASK 0xffff 31685 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_ALIGN 0 31686 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_BITS 16 31687 #define DIGITAL4_LP_BASEPAGE_LP_BASEPAGE_SHIFT 0 31688 31689 31690 /**************************************************************************** 31691 * Digital4 :: lp_nextPage_0 31692 */ 31693 /* Digital4 :: lp_nextPage_0 :: lp_nextPage_0 [15:00] */ 31694 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_MASK 0xffff 31695 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_ALIGN 0 31696 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_BITS 16 31697 #define DIGITAL4_LP_NEXTPAGE_0_LP_NEXTPAGE_0_SHIFT 0 31698 31699 31700 /**************************************************************************** 31701 * Digital4 :: lp_nextPage_1 31702 */ 31703 /* Digital4 :: lp_nextPage_1 :: lp_nextPage_1 [15:00] */ 31704 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_MASK 0xffff 31705 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_ALIGN 0 31706 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_BITS 16 31707 #define DIGITAL4_LP_NEXTPAGE_1_LP_NEXTPAGE_1_SHIFT 0 31708 31709 31710 /**************************************************************************** 31711 * Digital4 :: lp_nextPage_2 31712 */ 31713 /* Digital4 :: lp_nextPage_2 :: lp_nextPage_2 [15:00] */ 31714 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_MASK 0xffff 31715 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_ALIGN 0 31716 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_BITS 16 31717 #define DIGITAL4_LP_NEXTPAGE_2_LP_NEXTPAGE_2_SHIFT 0 31718 31719 31720 /**************************************************************************** 31721 * Digital4 :: lp_nextPage_3 31722 */ 31723 /* Digital4 :: lp_nextPage_3 :: lp_nextPage_3 [15:00] */ 31724 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_MASK 0xffff 31725 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_ALIGN 0 31726 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_BITS 16 31727 #define DIGITAL4_LP_NEXTPAGE_3_LP_NEXTPAGE_3_SHIFT 0 31728 31729 31730 /**************************************************************************** 31731 * Digital4 :: lp_nextPage_4 31732 */ 31733 /* Digital4 :: lp_nextPage_4 :: lp_nextPage_4 [15:00] */ 31734 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_MASK 0xffff 31735 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_ALIGN 0 31736 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_BITS 16 31737 #define DIGITAL4_LP_NEXTPAGE_4_LP_NEXTPAGE_4_SHIFT 0 31738 31739 31740 /**************************************************************************** 31741 * Digital4 :: rp_nextPage_0 31742 */ 31743 /* Digital4 :: rp_nextPage_0 :: reserved0 [15:15] */ 31744 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_MASK 0x8000 31745 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_ALIGN 0 31746 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_BITS 1 31747 #define DIGITAL4_RP_NEXTPAGE_0_RESERVED0_SHIFT 15 31748 31749 /* Digital4 :: rp_nextPage_0 :: extra_page_disable [14:14] */ 31750 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_MASK 0x4000 31751 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_ALIGN 0 31752 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_BITS 1 31753 #define DIGITAL4_RP_NEXTPAGE_0_EXTRA_PAGE_DISABLE_SHIFT 14 31754 31755 /* Digital4 :: rp_nextPage_0 :: null_page_enable [13:13] */ 31756 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_MASK 0x2000 31757 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_ALIGN 0 31758 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_BITS 1 31759 #define DIGITAL4_RP_NEXTPAGE_0_NULL_PAGE_ENABLE_SHIFT 13 31760 31761 /* Digital4 :: rp_nextPage_0 :: over_1g_disable [12:12] */ 31762 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_MASK 0x1000 31763 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_ALIGN 0 31764 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_BITS 1 31765 #define DIGITAL4_RP_NEXTPAGE_0_OVER_1G_DISABLE_SHIFT 12 31766 31767 /* Digital4 :: rp_nextPage_0 :: remote_phy_enable [11:11] */ 31768 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_MASK 0x0800 31769 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_ALIGN 0 31770 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_BITS 1 31771 #define DIGITAL4_RP_NEXTPAGE_0_REMOTE_PHY_ENABLE_SHIFT 11 31772 31773 /* Digital4 :: rp_nextPage_0 :: rp_nextPage_0 [10:00] */ 31774 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_MASK 0x07ff 31775 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_ALIGN 0 31776 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_BITS 11 31777 #define DIGITAL4_RP_NEXTPAGE_0_RP_NEXTPAGE_0_SHIFT 0 31778 31779 31780 /**************************************************************************** 31781 * Digital4 :: rp_nextPage_1 31782 */ 31783 /* Digital4 :: rp_nextPage_1 :: reserved0 [15:15] */ 31784 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_MASK 0x8000 31785 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_ALIGN 0 31786 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_BITS 1 31787 #define DIGITAL4_RP_NEXTPAGE_1_RESERVED0_SHIFT 15 31788 31789 /* Digital4 :: rp_nextPage_1 :: remotePhy_linkDown_rstrt_disable [14:14] */ 31790 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_MASK 0x4000 31791 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_ALIGN 0 31792 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_BITS 1 31793 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_LINKDOWN_RSTRT_DISABLE_SHIFT 14 31794 31795 /* Digital4 :: rp_nextPage_1 :: remotePhy_rsltn_err_rstrt_disable [13:13] */ 31796 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_MASK 0x2000 31797 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_ALIGN 0 31798 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_BITS 1 31799 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RSLTN_ERR_RSTRT_DISABLE_SHIFT 13 31800 31801 /* Digital4 :: rp_nextPage_1 :: remotePhy_resolution_disable [12:12] */ 31802 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_MASK 0x1000 31803 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_ALIGN 0 31804 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_BITS 1 31805 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_RESOLUTION_DISABLE_SHIFT 12 31806 31807 /* Digital4 :: rp_nextPage_1 :: remotePhy_decode_enable [11:11] */ 31808 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_MASK 0x0800 31809 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_ALIGN 0 31810 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_BITS 1 31811 #define DIGITAL4_RP_NEXTPAGE_1_REMOTEPHY_DECODE_ENABLE_SHIFT 11 31812 31813 /* Digital4 :: rp_nextPage_1 :: rp_nextPage_1 [10:00] */ 31814 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_MASK 0x07ff 31815 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_ALIGN 0 31816 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_BITS 11 31817 #define DIGITAL4_RP_NEXTPAGE_1_RP_NEXTPAGE_1_SHIFT 0 31818 31819 31820 /**************************************************************************** 31821 * Digital4 :: rp_nextPage_2 31822 */ 31823 /* Digital4 :: rp_nextPage_2 :: reserved0 [15:12] */ 31824 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_MASK 0xf000 31825 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_ALIGN 0 31826 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_BITS 4 31827 #define DIGITAL4_RP_NEXTPAGE_2_RESERVED0_SHIFT 12 31828 31829 /* Digital4 :: rp_nextPage_2 :: remPhy_NP_clr_disable [11:11] */ 31830 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_MASK 0x0800 31831 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_ALIGN 0 31832 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_BITS 1 31833 #define DIGITAL4_RP_NEXTPAGE_2_REMPHY_NP_CLR_DISABLE_SHIFT 11 31834 31835 /* Digital4 :: rp_nextPage_2 :: rp_nextPage_2 [10:00] */ 31836 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_MASK 0x07ff 31837 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_ALIGN 0 31838 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_BITS 11 31839 #define DIGITAL4_RP_NEXTPAGE_2_RP_NEXTPAGE_2_SHIFT 0 31840 31841 31842 /**************************************************************************** 31843 * Digital4 :: rp_nextPage_3 31844 */ 31845 /* Digital4 :: rp_nextPage_3 :: reserved0 [15:11] */ 31846 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_MASK 0xf800 31847 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_ALIGN 0 31848 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_BITS 5 31849 #define DIGITAL4_RP_NEXTPAGE_3_RESERVED0_SHIFT 11 31850 31851 /* Digital4 :: rp_nextPage_3 :: rp_nextPage_3 [10:00] */ 31852 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_MASK 0x07ff 31853 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_ALIGN 0 31854 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_BITS 11 31855 #define DIGITAL4_RP_NEXTPAGE_3_RP_NEXTPAGE_3_SHIFT 0 31856 31857 31858 /**************************************************************************** 31859 * Digital4 :: rp_nextPage_4 31860 */ 31861 /* Digital4 :: rp_nextPage_4 :: reserved0 [15:11] */ 31862 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_MASK 0xf800 31863 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_ALIGN 0 31864 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_BITS 5 31865 #define DIGITAL4_RP_NEXTPAGE_4_RESERVED0_SHIFT 11 31866 31867 /* Digital4 :: rp_nextPage_4 :: rp_nextPage_4 [10:00] */ 31868 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_MASK 0x07ff 31869 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_ALIGN 0 31870 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_BITS 11 31871 #define DIGITAL4_RP_NEXTPAGE_4_RP_NEXTPAGE_4_SHIFT 0 31872 31873 31874 /**************************************************************************** 31875 * Digital4 :: Misc3 31876 */ 31877 /* Digital4 :: Misc3 :: reserved0 [15:12] */ 31878 #define DIGITAL4_MISC3_RESERVED0_MASK 0xf000 31879 #define DIGITAL4_MISC3_RESERVED0_ALIGN 0 31880 #define DIGITAL4_MISC3_RESERVED0_BITS 4 31881 #define DIGITAL4_MISC3_RESERVED0_SHIFT 12 31882 31883 /* Digital4 :: Misc3 :: rxck_mii_override_val [11:11] */ 31884 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_MASK 0x0800 31885 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_ALIGN 0 31886 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_BITS 1 31887 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_VAL_SHIFT 11 31888 31889 /* Digital4 :: Misc3 :: rxck_mii_override [10:10] */ 31890 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_MASK 0x0400 31891 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_ALIGN 0 31892 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_BITS 1 31893 #define DIGITAL4_MISC3_RXCK_MII_OVERRIDE_SHIFT 10 31894 31895 /* Digital4 :: Misc3 :: fifo_ipg_cya [09:09] */ 31896 #define DIGITAL4_MISC3_FIFO_IPG_CYA_MASK 0x0200 31897 #define DIGITAL4_MISC3_FIFO_IPG_CYA_ALIGN 0 31898 #define DIGITAL4_MISC3_FIFO_IPG_CYA_BITS 1 31899 #define DIGITAL4_MISC3_FIFO_IPG_CYA_SHIFT 9 31900 31901 /* Digital4 :: Misc3 :: scr_en_per_lane [08:08] */ 31902 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_MASK 0x0100 31903 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_ALIGN 0 31904 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_BITS 1 31905 #define DIGITAL4_MISC3_SCR_EN_PER_LANE_SHIFT 8 31906 31907 /* Digital4 :: Misc3 :: force_speed_b5 [07:07] */ 31908 #define DIGITAL4_MISC3_FORCE_SPEED_B5_MASK 0x0080 31909 #define DIGITAL4_MISC3_FORCE_SPEED_B5_ALIGN 0 31910 #define DIGITAL4_MISC3_FORCE_SPEED_B5_BITS 1 31911 #define DIGITAL4_MISC3_FORCE_SPEED_B5_SHIFT 7 31912 31913 /* Digital4 :: Misc3 :: laneDisable [06:06] */ 31914 #define DIGITAL4_MISC3_LANEDISABLE_MASK 0x0040 31915 #define DIGITAL4_MISC3_LANEDISABLE_ALIGN 0 31916 #define DIGITAL4_MISC3_LANEDISABLE_BITS 1 31917 #define DIGITAL4_MISC3_LANEDISABLE_SHIFT 6 31918 31919 /* Digital4 :: Misc3 :: fifo_err_cya2 [05:05] */ 31920 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_MASK 0x0020 31921 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_ALIGN 0 31922 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_BITS 1 31923 #define DIGITAL4_MISC3_FIFO_ERR_CYA2_SHIFT 5 31924 31925 /* Digital4 :: Misc3 :: disable_pcs_tx_r [04:04] */ 31926 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_MASK 0x0010 31927 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_ALIGN 0 31928 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_BITS 1 31929 #define DIGITAL4_MISC3_DISABLE_PCS_TX_R_SHIFT 4 31930 31931 /* Digital4 :: Misc3 :: disable_pcs_tx_force_r [03:03] */ 31932 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_MASK 0x0008 31933 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_ALIGN 0 31934 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_BITS 1 31935 #define DIGITAL4_MISC3_DISABLE_PCS_TX_FORCE_R_SHIFT 3 31936 31937 /* Digital4 :: Misc3 :: tbi_mode_force_r [02:02] */ 31938 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_MASK 0x0004 31939 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_ALIGN 0 31940 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_BITS 1 31941 #define DIGITAL4_MISC3_TBI_MODE_FORCE_R_SHIFT 2 31942 31943 /* Digital4 :: Misc3 :: rxSigdetPwrdn_override_val [01:01] */ 31944 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_MASK 0x0002 31945 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_ALIGN 0 31946 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_BITS 1 31947 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_VAL_SHIFT 1 31948 31949 /* Digital4 :: Misc3 :: rxSigdetPwrdn_override [00:00] */ 31950 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_MASK 0x0001 31951 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_ALIGN 0 31952 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_BITS 1 31953 #define DIGITAL4_MISC3_RXSIGDETPWRDN_OVERRIDE_SHIFT 0 31954 31955 31956 /**************************************************************************** 31957 * Hypercore_USER_Digital6 31958 */ 31959 /**************************************************************************** 31960 * Digital6 :: mp5_NextPageCtrl 31961 */ 31962 /* Digital6 :: mp5_NextPageCtrl :: reserved0 [15:04] */ 31963 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_MASK 0xfff0 31964 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_ALIGN 0 31965 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_BITS 12 31966 #define DIGITAL6_MP5_NEXTPAGECTRL_RESERVED0_SHIFT 4 31967 31968 /* Digital6 :: mp5_NextPageCtrl :: np_sw_overRide_en [03:03] */ 31969 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_MASK 0x0008 31970 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_ALIGN 0 31971 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_BITS 1 31972 #define DIGITAL6_MP5_NEXTPAGECTRL_NP_SW_OVERRIDE_EN_SHIFT 3 31973 31974 /* Digital6 :: mp5_NextPageCtrl :: teton_mode_up3_en [02:02] */ 31975 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_MASK 0x0004 31976 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_ALIGN 0 31977 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_BITS 1 31978 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_UP3_EN_SHIFT 2 31979 31980 /* Digital6 :: mp5_NextPageCtrl :: teton_mode [01:01] */ 31981 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_MASK 0x0002 31982 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_ALIGN 0 31983 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_BITS 1 31984 #define DIGITAL6_MP5_NEXTPAGECTRL_TETON_MODE_SHIFT 1 31985 31986 /* Digital6 :: mp5_NextPageCtrl :: bam_mode [00:00] */ 31987 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_MASK 0x0001 31988 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_ALIGN 0 31989 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_BITS 1 31990 #define DIGITAL6_MP5_NEXTPAGECTRL_BAM_MODE_SHIFT 0 31991 31992 31993 /**************************************************************************** 31994 * Digital6 :: link_timer_offset1 31995 */ 31996 /* Digital6 :: link_timer_offset1 :: sgmii_offset [15:08] */ 31997 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_MASK 0xff00 31998 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_ALIGN 0 31999 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_BITS 8 32000 #define DIGITAL6_LINK_TIMER_OFFSET1_SGMII_OFFSET_SHIFT 8 32001 32002 /* Digital6 :: link_timer_offset1 :: max_offset [07:00] */ 32003 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_MASK 0x00ff 32004 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_ALIGN 0 32005 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_BITS 8 32006 #define DIGITAL6_LINK_TIMER_OFFSET1_MAX_OFFSET_SHIFT 0 32007 32008 32009 /**************************************************************************** 32010 * Digital6 :: link_timer_offset2 32011 */ 32012 /* Digital6 :: link_timer_offset2 :: link_up_offset [15:08] */ 32013 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_MASK 0xff00 32014 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_ALIGN 0 32015 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_BITS 8 32016 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_UP_OFFSET_SHIFT 8 32017 32018 /* Digital6 :: link_timer_offset2 :: link_down_offset [07:00] */ 32019 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_MASK 0x00ff 32020 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_ALIGN 0 32021 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_BITS 8 32022 #define DIGITAL6_LINK_TIMER_OFFSET2_LINK_DOWN_OFFSET_SHIFT 0 32023 32024 32025 /**************************************************************************** 32026 * Digital6 :: link_timer_offset3 32027 */ 32028 /* Digital6 :: link_timer_offset3 :: break_link_offset [15:08] */ 32029 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_MASK 0xff00 32030 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_ALIGN 0 32031 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_BITS 8 32032 #define DIGITAL6_LINK_TIMER_OFFSET3_BREAK_LINK_OFFSET_SHIFT 8 32033 32034 /* Digital6 :: link_timer_offset3 :: np_link_offset [07:00] */ 32035 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_MASK 0x00ff 32036 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_ALIGN 0 32037 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_BITS 8 32038 #define DIGITAL6_LINK_TIMER_OFFSET3_NP_LINK_OFFSET_SHIFT 0 32039 32040 32041 /**************************************************************************** 32042 * Digital6 :: oui_msb_field 32043 */ 32044 /* Digital6 :: oui_msb_field :: reserved0 [15:11] */ 32045 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_MASK 0xf800 32046 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_ALIGN 0 32047 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_BITS 5 32048 #define DIGITAL6_OUI_MSB_FIELD_RESERVED0_SHIFT 11 32049 32050 /* Digital6 :: oui_msb_field :: oui_msb_field [10:00] */ 32051 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK 0x07ff 32052 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN 0 32053 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS 11 32054 #define DIGITAL6_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT 0 32055 32056 32057 /**************************************************************************** 32058 * Digital6 :: oui_lsb_field 32059 */ 32060 /* Digital6 :: oui_lsb_field :: reserved0 [15:11] */ 32061 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_MASK 0xf800 32062 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_ALIGN 0 32063 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_BITS 5 32064 #define DIGITAL6_OUI_LSB_FIELD_RESERVED0_SHIFT 11 32065 32066 /* Digital6 :: oui_lsb_field :: oui_lsb_field [10:00] */ 32067 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK 0x07ff 32068 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN 0 32069 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS 11 32070 #define DIGITAL6_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT 0 32071 32072 32073 /**************************************************************************** 32074 * Digital6 :: bam_field 32075 */ 32076 /* Digital6 :: bam_field :: reserved0 [15:11] */ 32077 #define DIGITAL6_BAM_FIELD_RESERVED0_MASK 0xf800 32078 #define DIGITAL6_BAM_FIELD_RESERVED0_ALIGN 0 32079 #define DIGITAL6_BAM_FIELD_RESERVED0_BITS 5 32080 #define DIGITAL6_BAM_FIELD_RESERVED0_SHIFT 11 32081 32082 /* Digital6 :: bam_field :: oui_1_0 [10:09] */ 32083 #define DIGITAL6_BAM_FIELD_OUI_1_0_MASK 0x0600 32084 #define DIGITAL6_BAM_FIELD_OUI_1_0_ALIGN 0 32085 #define DIGITAL6_BAM_FIELD_OUI_1_0_BITS 2 32086 #define DIGITAL6_BAM_FIELD_OUI_1_0_SHIFT 9 32087 32088 /* Digital6 :: bam_field :: bam_field [08:00] */ 32089 #define DIGITAL6_BAM_FIELD_BAM_FIELD_MASK 0x01ff 32090 #define DIGITAL6_BAM_FIELD_BAM_FIELD_ALIGN 0 32091 #define DIGITAL6_BAM_FIELD_BAM_FIELD_BITS 9 32092 #define DIGITAL6_BAM_FIELD_BAM_FIELD_SHIFT 0 32093 32094 32095 /**************************************************************************** 32096 * Digital6 :: ud_field 32097 */ 32098 /* Digital6 :: ud_field :: reserved0 [15:11] */ 32099 #define DIGITAL6_UD_FIELD_RESERVED0_MASK 0xf800 32100 #define DIGITAL6_UD_FIELD_RESERVED0_ALIGN 0 32101 #define DIGITAL6_UD_FIELD_RESERVED0_BITS 5 32102 #define DIGITAL6_UD_FIELD_RESERVED0_SHIFT 11 32103 32104 /* Digital6 :: ud_field :: ud_reserved [10:06] */ 32105 #define DIGITAL6_UD_FIELD_UD_RESERVED_MASK 0x07c0 32106 #define DIGITAL6_UD_FIELD_UD_RESERVED_ALIGN 0 32107 #define DIGITAL6_UD_FIELD_UD_RESERVED_BITS 5 32108 #define DIGITAL6_UD_FIELD_UD_RESERVED_SHIFT 6 32109 32110 /* Digital6 :: ud_field :: remote_BN_page [05:05] */ 32111 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 32112 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 32113 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_BITS 1 32114 #define DIGITAL6_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 32115 32116 /* Digital6 :: ud_field :: inband_MDIO [04:04] */ 32117 #define DIGITAL6_UD_FIELD_INBAND_MDIO_MASK 0x0010 32118 #define DIGITAL6_UD_FIELD_INBAND_MDIO_ALIGN 0 32119 #define DIGITAL6_UD_FIELD_INBAND_MDIO_BITS 1 32120 #define DIGITAL6_UD_FIELD_INBAND_MDIO_SHIFT 4 32121 32122 /* Digital6 :: ud_field :: autoneg_MDIO [03:03] */ 32123 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 32124 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_ALIGN 0 32125 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_BITS 1 32126 #define DIGITAL6_UD_FIELD_AUTONEG_MDIO_SHIFT 3 32127 32128 /* Digital6 :: ud_field :: remote_serdes_phy [02:02] */ 32129 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 32130 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 32131 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 32132 #define DIGITAL6_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 32133 32134 /* Digital6 :: ud_field :: remote_cu_phy [01:01] */ 32135 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 32136 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 32137 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_BITS 1 32138 #define DIGITAL6_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 32139 32140 /* Digital6 :: ud_field :: over1g [00:00] */ 32141 #define DIGITAL6_UD_FIELD_OVER1G_MASK 0x0001 32142 #define DIGITAL6_UD_FIELD_OVER1G_ALIGN 0 32143 #define DIGITAL6_UD_FIELD_OVER1G_BITS 1 32144 #define DIGITAL6_UD_FIELD_OVER1G_SHIFT 0 32145 32146 32147 /**************************************************************************** 32148 * Digital6 :: lp_oui_msb_field 32149 */ 32150 /* Digital6 :: lp_oui_msb_field :: reserved0 [15:11] */ 32151 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_MASK 0xf800 32152 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_ALIGN 0 32153 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_BITS 5 32154 #define DIGITAL6_LP_OUI_MSB_FIELD_RESERVED0_SHIFT 11 32155 32156 /* Digital6 :: lp_oui_msb_field :: oui_msb_field [10:00] */ 32157 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_MASK 0x07ff 32158 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_ALIGN 0 32159 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_BITS 11 32160 #define DIGITAL6_LP_OUI_MSB_FIELD_OUI_MSB_FIELD_SHIFT 0 32161 32162 32163 /**************************************************************************** 32164 * Digital6 :: lp_oui_lsb_field 32165 */ 32166 /* Digital6 :: lp_oui_lsb_field :: reserved0 [15:11] */ 32167 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_MASK 0xf800 32168 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_ALIGN 0 32169 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_BITS 5 32170 #define DIGITAL6_LP_OUI_LSB_FIELD_RESERVED0_SHIFT 11 32171 32172 /* Digital6 :: lp_oui_lsb_field :: oui_lsb_field [10:00] */ 32173 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_MASK 0x07ff 32174 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_ALIGN 0 32175 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_BITS 11 32176 #define DIGITAL6_LP_OUI_LSB_FIELD_OUI_LSB_FIELD_SHIFT 0 32177 32178 32179 /**************************************************************************** 32180 * Digital6 :: lp_bam_field 32181 */ 32182 /* Digital6 :: lp_bam_field :: reserved0 [15:11] */ 32183 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_MASK 0xf800 32184 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_ALIGN 0 32185 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_BITS 5 32186 #define DIGITAL6_LP_BAM_FIELD_RESERVED0_SHIFT 11 32187 32188 /* Digital6 :: lp_bam_field :: oui_1_0 [10:09] */ 32189 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_MASK 0x0600 32190 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_ALIGN 0 32191 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_BITS 2 32192 #define DIGITAL6_LP_BAM_FIELD_OUI_1_0_SHIFT 9 32193 32194 /* Digital6 :: lp_bam_field :: bam_field [08:00] */ 32195 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_MASK 0x01ff 32196 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_ALIGN 0 32197 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_BITS 9 32198 #define DIGITAL6_LP_BAM_FIELD_BAM_FIELD_SHIFT 0 32199 32200 32201 /**************************************************************************** 32202 * Digital6 :: lp_ud_field 32203 */ 32204 /* Digital6 :: lp_ud_field :: reserved0 [15:11] */ 32205 #define DIGITAL6_LP_UD_FIELD_RESERVED0_MASK 0xf800 32206 #define DIGITAL6_LP_UD_FIELD_RESERVED0_ALIGN 0 32207 #define DIGITAL6_LP_UD_FIELD_RESERVED0_BITS 5 32208 #define DIGITAL6_LP_UD_FIELD_RESERVED0_SHIFT 11 32209 32210 /* Digital6 :: lp_ud_field :: ud_reserved [10:06] */ 32211 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_MASK 0x07c0 32212 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_ALIGN 0 32213 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_BITS 5 32214 #define DIGITAL6_LP_UD_FIELD_UD_RESERVED_SHIFT 6 32215 32216 /* Digital6 :: lp_ud_field :: remote_BN_page [05:05] */ 32217 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_MASK 0x0020 32218 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_ALIGN 0 32219 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_BITS 1 32220 #define DIGITAL6_LP_UD_FIELD_REMOTE_BN_PAGE_SHIFT 5 32221 32222 /* Digital6 :: lp_ud_field :: inband_MDIO [04:04] */ 32223 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_MASK 0x0010 32224 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_ALIGN 0 32225 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_BITS 1 32226 #define DIGITAL6_LP_UD_FIELD_INBAND_MDIO_SHIFT 4 32227 32228 /* Digital6 :: lp_ud_field :: autoneg_MDIO [03:03] */ 32229 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_MASK 0x0008 32230 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_ALIGN 0 32231 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_BITS 1 32232 #define DIGITAL6_LP_UD_FIELD_AUTONEG_MDIO_SHIFT 3 32233 32234 /* Digital6 :: lp_ud_field :: remote_serdes_phy [02:02] */ 32235 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_MASK 0x0004 32236 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_ALIGN 0 32237 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_BITS 1 32238 #define DIGITAL6_LP_UD_FIELD_REMOTE_SERDES_PHY_SHIFT 2 32239 32240 /* Digital6 :: lp_ud_field :: remote_cu_phy [01:01] */ 32241 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_MASK 0x0002 32242 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_ALIGN 0 32243 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_BITS 1 32244 #define DIGITAL6_LP_UD_FIELD_REMOTE_CU_PHY_SHIFT 1 32245 32246 /* Digital6 :: lp_ud_field :: over1g [00:00] */ 32247 #define DIGITAL6_LP_UD_FIELD_OVER1G_MASK 0x0001 32248 #define DIGITAL6_LP_UD_FIELD_OVER1G_ALIGN 0 32249 #define DIGITAL6_LP_UD_FIELD_OVER1G_BITS 1 32250 #define DIGITAL6_LP_UD_FIELD_OVER1G_SHIFT 0 32251 32252 32253 /**************************************************************************** 32254 * Hypercore_USER_CL73_UserB0 32255 */ 32256 /**************************************************************************** 32257 * CL73_UserB0 :: CL73_UCtrl1 32258 */ 32259 /* CL73_UserB0 :: CL73_UCtrl1 :: reserved0 [15:13] */ 32260 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_MASK 0xe000 32261 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_ALIGN 0 32262 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_BITS 3 32263 #define CL73_USERB0_CL73_UCTRL1_RESERVED0_SHIFT 13 32264 32265 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_lossOfSyncFail_en [12:12] */ 32266 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_MASK 0x1000 32267 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_ALIGN 0 32268 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_BITS 1 32269 #define CL73_USERB0_CL73_UCTRL1_CL73_LOSSOFSYNCFAIL_EN_SHIFT 12 32270 32271 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_parDet_dis [11:11] */ 32272 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_MASK 0x0800 32273 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_ALIGN 0 32274 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_BITS 1 32275 #define CL73_USERB0_CL73_UCTRL1_CL73_PARDET_DIS_SHIFT 11 32276 32277 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_allowCl37AN [10:10] */ 32278 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_MASK 0x0400 32279 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_ALIGN 0 32280 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_BITS 1 32281 #define CL73_USERB0_CL73_UCTRL1_CL73_ALLOWCL37AN_SHIFT 10 32282 32283 /* CL73_UserB0 :: CL73_UCtrl1 :: longParDetTimer_dis [09:09] */ 32284 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_MASK 0x0200 32285 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_ALIGN 0 32286 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_BITS 1 32287 #define CL73_USERB0_CL73_UCTRL1_LONGPARDETTIMER_DIS_SHIFT 9 32288 32289 /* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimer_dis [08:08] */ 32290 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_MASK 0x0100 32291 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_ALIGN 0 32292 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_BITS 1 32293 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMER_DIS_SHIFT 8 32294 32295 /* CL73_UserB0 :: CL73_UCtrl1 :: linkFailTimerQual_en [07:07] */ 32296 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_MASK 0x0080 32297 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_ALIGN 0 32298 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_BITS 1 32299 #define CL73_USERB0_CL73_UCTRL1_LINKFAILTIMERQUAL_EN_SHIFT 7 32300 32301 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_over [06:06] */ 32302 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_MASK 0x0040 32303 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_ALIGN 0 32304 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_BITS 1 32305 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_OVER_SHIFT 6 32306 32307 /* CL73_UserB0 :: CL73_UCtrl1 :: cl73_nonce_match_val [05:05] */ 32308 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_MASK 0x0020 32309 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_ALIGN 0 32310 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_BITS 1 32311 #define CL73_USERB0_CL73_UCTRL1_CL73_NONCE_MATCH_VAL_SHIFT 5 32312 32313 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart_wo_link_fail [04:04] */ 32314 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_MASK 0x0010 32315 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_ALIGN 0 32316 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_BITS 1 32317 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_WO_LINK_FAIL_SHIFT 4 32318 32319 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl73_restart [03:03] */ 32320 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_MASK 0x0008 32321 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_ALIGN 0 32322 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_BITS 1 32323 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL73_RESTART_SHIFT 3 32324 32325 /* CL73_UserB0 :: CL73_UCtrl1 :: couple_w_cl37_restart [02:02] */ 32326 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_MASK 0x0004 32327 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_ALIGN 0 32328 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_BITS 1 32329 #define CL73_USERB0_CL73_UCTRL1_COUPLE_W_CL37_RESTART_SHIFT 2 32330 32331 /* CL73_UserB0 :: CL73_UCtrl1 :: CL73_Ustat1_muxsel [01:01] */ 32332 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_MASK 0x0002 32333 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_ALIGN 0 32334 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_BITS 1 32335 #define CL73_USERB0_CL73_UCTRL1_CL73_USTAT1_MUXSEL_SHIFT 1 32336 32337 /* CL73_UserB0 :: CL73_UCtrl1 :: force_cl73_tx_omux_en [00:00] */ 32338 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_MASK 0x0001 32339 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_ALIGN 0 32340 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_BITS 1 32341 #define CL73_USERB0_CL73_UCTRL1_FORCE_CL73_TX_OMUX_EN_SHIFT 0 32342 32343 32344 /**************************************************************************** 32345 * CL73_UserB0 :: CL73_Ustat1 32346 */ 32347 /* CL73_UserB0 :: CL73_Ustat1 :: reserved0 [15:10] */ 32348 #define CL73_USERB0_CL73_USTAT1_RESERVED0_MASK 0xfc00 32349 #define CL73_USERB0_CL73_USTAT1_RESERVED0_ALIGN 0 32350 #define CL73_USERB0_CL73_USTAT1_RESERVED0_BITS 6 32351 #define CL73_USERB0_CL73_USTAT1_RESERVED0_SHIFT 10 32352 32353 /* CL73_UserB0 :: CL73_Ustat1 :: arb_fsm [09:00] */ 32354 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_MASK 0x03ff 32355 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_ALIGN 0 32356 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_BITS 10 32357 #define CL73_USERB0_CL73_USTAT1_ARB_FSM_SHIFT 0 32358 32359 32360 /**************************************************************************** 32361 * CL73_UserB0 :: CL73_BAMCtrl1 32362 */ 32363 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamEn [15:15] */ 32364 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_MASK 0x8000 32365 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_ALIGN 0 32366 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_BITS 1 32367 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMEN_SHIFT 15 32368 32369 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_station_mngr_en [14:14] */ 32370 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_MASK 0x4000 32371 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_ALIGN 0 32372 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_BITS 1 32373 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_STATION_MNGR_EN_SHIFT 14 32374 32375 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bamNP_after_bp_en [13:13] */ 32376 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_MASK 0x2000 32377 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_ALIGN 0 32378 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_BITS 1 32379 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAMNP_AFTER_BP_EN_SHIFT 13 32380 32381 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_en [12:12] */ 32382 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_MASK 0x1000 32383 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_ALIGN 0 32384 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_BITS 1 32385 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_EN_SHIFT 12 32386 32387 /* CL73_UserB0 :: CL73_BAMCtrl1 :: CL73_bam_test_MP5_halt_step [11:11] */ 32388 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_MASK 0x0800 32389 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_ALIGN 0 32390 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_BITS 1 32391 #define CL73_USERB0_CL73_BAMCTRL1_CL73_BAM_TEST_MP5_HALT_STEP_SHIFT 11 32392 32393 /* CL73_UserB0 :: CL73_BAMCtrl1 :: reserved0 [10:10] */ 32394 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_MASK 0x0400 32395 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_ALIGN 0 32396 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_BITS 1 32397 #define CL73_USERB0_CL73_BAMCTRL1_RESERVED0_SHIFT 10 32398 32399 /* CL73_UserB0 :: CL73_BAMCtrl1 :: UD_code_field [09:00] */ 32400 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_MASK 0x03ff 32401 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_ALIGN 0 32402 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_BITS 10 32403 #define CL73_USERB0_CL73_BAMCTRL1_UD_CODE_FIELD_SHIFT 0 32404 32405 32406 /**************************************************************************** 32407 * CL73_UserB0 :: CL73_BAMCtrl2 32408 */ 32409 /* CL73_UserB0 :: CL73_BAMCtrl2 :: UD_code_field [15:00] */ 32410 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_MASK 0xffff 32411 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_ALIGN 0 32412 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_BITS 16 32413 #define CL73_USERB0_CL73_BAMCTRL2_UD_CODE_FIELD_SHIFT 0 32414 32415 32416 /**************************************************************************** 32417 * CL73_UserB0 :: CL73_BAMCtrl3 32418 */ 32419 /* CL73_UserB0 :: CL73_BAMCtrl3 :: UD_code_field [15:00] */ 32420 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_MASK 0xffff 32421 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_ALIGN 0 32422 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_BITS 16 32423 #define CL73_USERB0_CL73_BAMCTRL3_UD_CODE_FIELD_SHIFT 0 32424 32425 32426 /**************************************************************************** 32427 * CL73_UserB0 :: CL73_BAMStat1 32428 */ 32429 /* CL73_UserB0 :: CL73_BAMStat1 :: reserved0 [15:10] */ 32430 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_MASK 0xfc00 32431 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_ALIGN 0 32432 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_BITS 6 32433 #define CL73_USERB0_CL73_BAMSTAT1_RESERVED0_SHIFT 10 32434 32435 /* CL73_UserB0 :: CL73_BAMStat1 :: LP_UD_code_field [09:00] */ 32436 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_MASK 0x03ff 32437 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_ALIGN 0 32438 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_BITS 10 32439 #define CL73_USERB0_CL73_BAMSTAT1_LP_UD_CODE_FIELD_SHIFT 0 32440 32441 32442 /**************************************************************************** 32443 * CL73_UserB0 :: CL73_BAMStat2 32444 */ 32445 /* CL73_UserB0 :: CL73_BAMStat2 :: LP_UD_code_field [15:00] */ 32446 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_MASK 0xffff 32447 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_ALIGN 0 32448 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_BITS 16 32449 #define CL73_USERB0_CL73_BAMSTAT2_LP_UD_CODE_FIELD_SHIFT 0 32450 32451 32452 /**************************************************************************** 32453 * CL73_UserB0 :: CL73_BAMStat3 32454 */ 32455 /* CL73_UserB0 :: CL73_BAMStat3 :: LP_UD_code_field [15:00] */ 32456 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_MASK 0xffff 32457 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_ALIGN 0 32458 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_BITS 16 32459 #define CL73_USERB0_CL73_BAMSTAT3_LP_UD_CODE_FIELD_SHIFT 0 32460 32461 32462 /**************************************************************************** 32463 * Hypercore_USER_Dsc4b0 32464 */ 32465 /**************************************************************************** 32466 * Dsc4b0 :: sm_ctrl13 32467 */ 32468 /* Dsc4b0 :: sm_ctrl13 :: reserved0 [15:15] */ 32469 #define DSC4B0_SM_CTRL13_RESERVED0_MASK 0x8000 32470 #define DSC4B0_SM_CTRL13_RESERVED0_ALIGN 0 32471 #define DSC4B0_SM_CTRL13_RESERVED0_BITS 1 32472 #define DSC4B0_SM_CTRL13_RESERVED0_SHIFT 15 32473 32474 /* Dsc4b0 :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */ 32475 #define DSC4B0_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK 0x7c00 32476 #define DSC4B0_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN 0 32477 #define DSC4B0_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS 5 32478 #define DSC4B0_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT 10 32479 32480 /* Dsc4b0 :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */ 32481 #define DSC4B0_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK 0x03e0 32482 #define DSC4B0_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN 0 32483 #define DSC4B0_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS 5 32484 #define DSC4B0_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT 5 32485 32486 /* Dsc4b0 :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */ 32487 #define DSC4B0_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK 0x001f 32488 #define DSC4B0_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN 0 32489 #define DSC4B0_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS 5 32490 #define DSC4B0_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT 0 32491 32492 32493 /**************************************************************************** 32494 * Dsc4b0 :: sm_ctrl14 32495 */ 32496 /* Dsc4b0 :: sm_ctrl14 :: reserved0 [15:14] */ 32497 #define DSC4B0_SM_CTRL14_RESERVED0_MASK 0xc000 32498 #define DSC4B0_SM_CTRL14_RESERVED0_ALIGN 0 32499 #define DSC4B0_SM_CTRL14_RESERVED0_BITS 2 32500 #define DSC4B0_SM_CTRL14_RESERVED0_SHIFT 14 32501 32502 /* Dsc4b0 :: sm_ctrl14 :: br_postc_tap_en [13:07] */ 32503 #define DSC4B0_SM_CTRL14_BR_POSTC_TAP_EN_MASK 0x3f80 32504 #define DSC4B0_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN 0 32505 #define DSC4B0_SM_CTRL14_BR_POSTC_TAP_EN_BITS 7 32506 #define DSC4B0_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT 7 32507 32508 /* Dsc4b0 :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */ 32509 #define DSC4B0_SM_CTRL14_OSX2_PF_TAP_EN_MASK 0x007f 32510 #define DSC4B0_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN 0 32511 #define DSC4B0_SM_CTRL14_OSX2_PF_TAP_EN_BITS 7 32512 #define DSC4B0_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT 0 32513 32514 32515 /**************************************************************************** 32516 * Dsc4b0 :: sm_ctrl15 32517 */ 32518 /* Dsc4b0 :: sm_ctrl15 :: reserved0 [15:14] */ 32519 #define DSC4B0_SM_CTRL15_RESERVED0_MASK 0xc000 32520 #define DSC4B0_SM_CTRL15_RESERVED0_ALIGN 0 32521 #define DSC4B0_SM_CTRL15_RESERVED0_BITS 2 32522 #define DSC4B0_SM_CTRL15_RESERVED0_SHIFT 14 32523 32524 /* Dsc4b0 :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */ 32525 #define DSC4B0_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK 0x3f80 32526 #define DSC4B0_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN 0 32527 #define DSC4B0_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS 7 32528 #define DSC4B0_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT 7 32529 32530 /* Dsc4b0 :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */ 32531 #define DSC4B0_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK 0x007f 32532 #define DSC4B0_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN 0 32533 #define DSC4B0_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS 7 32534 #define DSC4B0_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT 0 32535 32536 32537 /**************************************************************************** 32538 * Dsc4b0 :: sm_ctrl16 32539 */ 32540 /* Dsc4b0 :: sm_ctrl16 :: reserved0 [15:15] */ 32541 #define DSC4B0_SM_CTRL16_RESERVED0_MASK 0x8000 32542 #define DSC4B0_SM_CTRL16_RESERVED0_ALIGN 0 32543 #define DSC4B0_SM_CTRL16_RESERVED0_BITS 1 32544 #define DSC4B0_SM_CTRL16_RESERVED0_SHIFT 15 32545 32546 /* Dsc4b0 :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */ 32547 #define DSC4B0_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK 0x7c00 32548 #define DSC4B0_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN 0 32549 #define DSC4B0_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS 5 32550 #define DSC4B0_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT 10 32551 32552 /* Dsc4b0 :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */ 32553 #define DSC4B0_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK 0x03e0 32554 #define DSC4B0_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN 0 32555 #define DSC4B0_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS 5 32556 #define DSC4B0_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT 5 32557 32558 /* Dsc4b0 :: sm_ctrl16 :: default_trn2_timeout [04:00] */ 32559 #define DSC4B0_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK 0x001f 32560 #define DSC4B0_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN 0 32561 #define DSC4B0_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS 5 32562 #define DSC4B0_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT 0 32563 32564 32565 /**************************************************************************** 32566 * Dsc4b0 :: sm_ctrl17 32567 */ 32568 /* Dsc4b0 :: sm_ctrl17 :: reserved0 [15:02] */ 32569 #define DSC4B0_SM_CTRL17_RESERVED0_MASK 0xfffc 32570 #define DSC4B0_SM_CTRL17_RESERVED0_ALIGN 0 32571 #define DSC4B0_SM_CTRL17_RESERVED0_BITS 14 32572 #define DSC4B0_SM_CTRL17_RESERVED0_SHIFT 2 32573 32574 /* Dsc4b0 :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */ 32575 #define DSC4B0_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK 0x0002 32576 #define DSC4B0_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN 0 32577 #define DSC4B0_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS 1 32578 #define DSC4B0_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT 1 32579 32580 /* Dsc4b0 :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */ 32581 #define DSC4B0_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK 0x0001 32582 #define DSC4B0_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN 0 32583 #define DSC4B0_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS 1 32584 #define DSC4B0_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT 0 32585 32586 32587 /**************************************************************************** 32588 * Dsc4b0 :: sm_status7 32589 */ 32590 /* Dsc4b0 :: sm_status7 :: reserved_for_eco0 [15:12] */ 32591 #define DSC4B0_SM_STATUS7_RESERVED_FOR_ECO0_MASK 0xf000 32592 #define DSC4B0_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN 0 32593 #define DSC4B0_SM_STATUS7_RESERVED_FOR_ECO0_BITS 4 32594 #define DSC4B0_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT 12 32595 32596 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_11 [11:11] */ 32597 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK 0x0800 32598 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN 0 32599 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS 1 32600 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT 11 32601 32602 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_10 [10:10] */ 32603 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK 0x0400 32604 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN 0 32605 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS 1 32606 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT 10 32607 32608 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_9 [09:09] */ 32609 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK 0x0200 32610 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN 0 32611 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS 1 32612 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT 9 32613 32614 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_8 [08:08] */ 32615 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK 0x0100 32616 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN 0 32617 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS 1 32618 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT 8 32619 32620 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_7 [07:07] */ 32621 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK 0x0080 32622 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN 0 32623 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS 1 32624 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT 7 32625 32626 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_6 [06:06] */ 32627 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK 0x0040 32628 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN 0 32629 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS 1 32630 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT 6 32631 32632 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_5 [05:05] */ 32633 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK 0x0020 32634 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN 0 32635 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS 1 32636 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT 5 32637 32638 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_4 [04:04] */ 32639 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK 0x0010 32640 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN 0 32641 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS 1 32642 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT 4 32643 32644 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_3 [03:03] */ 32645 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK 0x0008 32646 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN 0 32647 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS 1 32648 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT 3 32649 32650 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_2 [02:02] */ 32651 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK 0x0004 32652 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN 0 32653 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS 1 32654 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT 2 32655 32656 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_1 [01:01] */ 32657 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK 0x0002 32658 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN 0 32659 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS 1 32660 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT 1 32661 32662 /* Dsc4b0 :: sm_status7 :: dsc_state_one_hot_0 [00:00] */ 32663 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK 0x0001 32664 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN 0 32665 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS 1 32666 #define DSC4B0_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT 0 32667 32668 32669 /**************************************************************************** 32670 * Dsc4b0 :: sm_status8 32671 */ 32672 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_15 [15:15] */ 32673 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK 0x8000 32674 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN 0 32675 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS 1 32676 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT 15 32677 32678 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_14 [14:14] */ 32679 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK 0x4000 32680 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN 0 32681 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS 1 32682 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT 14 32683 32684 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_13 [13:13] */ 32685 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK 0x2000 32686 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN 0 32687 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS 1 32688 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT 13 32689 32690 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_12 [12:12] */ 32691 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK 0x1000 32692 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN 0 32693 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS 1 32694 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT 12 32695 32696 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_11 [11:11] */ 32697 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK 0x0800 32698 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN 0 32699 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS 1 32700 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT 11 32701 32702 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_10 [10:10] */ 32703 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK 0x0400 32704 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN 0 32705 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS 1 32706 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT 10 32707 32708 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_9 [09:09] */ 32709 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK 0x0200 32710 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN 0 32711 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS 1 32712 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT 9 32713 32714 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_8 [08:08] */ 32715 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK 0x0100 32716 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN 0 32717 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS 1 32718 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT 8 32719 32720 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_7 [07:07] */ 32721 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK 0x0080 32722 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN 0 32723 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS 1 32724 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT 7 32725 32726 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_6 [06:06] */ 32727 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK 0x0040 32728 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN 0 32729 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS 1 32730 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT 6 32731 32732 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_5 [05:05] */ 32733 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK 0x0020 32734 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN 0 32735 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS 1 32736 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT 5 32737 32738 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_4 [04:04] */ 32739 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK 0x0010 32740 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN 0 32741 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS 1 32742 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT 4 32743 32744 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_3 [03:03] */ 32745 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK 0x0008 32746 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN 0 32747 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS 1 32748 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT 3 32749 32750 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_2 [02:02] */ 32751 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK 0x0004 32752 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN 0 32753 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS 1 32754 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT 2 32755 32756 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_1 [01:01] */ 32757 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK 0x0002 32758 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN 0 32759 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS 1 32760 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT 1 32761 32762 /* Dsc4b0 :: sm_status8 :: tuning_state_one_hot_0 [00:00] */ 32763 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK 0x0001 32764 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN 0 32765 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS 1 32766 #define DSC4B0_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT 0 32767 32768 32769 /**************************************************************************** 32770 * Dsc4b0 :: sm_status9 32771 */ 32772 /* Dsc4b0 :: sm_status9 :: reserved_for_eco0 [15:12] */ 32773 #define DSC4B0_SM_STATUS9_RESERVED_FOR_ECO0_MASK 0xf000 32774 #define DSC4B0_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN 0 32775 #define DSC4B0_SM_STATUS9_RESERVED_FOR_ECO0_BITS 4 32776 #define DSC4B0_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT 12 32777 32778 /* Dsc4b0 :: sm_status9 :: tuning_state_one_hot_17 [11:11] */ 32779 #define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK 0x0800 32780 #define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN 0 32781 #define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS 1 32782 #define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT 11 32783 32784 /* Dsc4b0 :: sm_status9 :: tuning_state_one_hot_16 [10:10] */ 32785 #define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK 0x0400 32786 #define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN 0 32787 #define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS 1 32788 #define DSC4B0_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT 10 32789 32790 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_9 [09:09] */ 32791 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK 0x0200 32792 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN 0 32793 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS 1 32794 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT 9 32795 32796 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_8 [08:08] */ 32797 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK 0x0100 32798 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN 0 32799 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS 1 32800 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT 8 32801 32802 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_7 [07:07] */ 32803 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK 0x0080 32804 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN 0 32805 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS 1 32806 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT 7 32807 32808 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_6 [06:06] */ 32809 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK 0x0040 32810 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN 0 32811 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS 1 32812 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT 6 32813 32814 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_5 [05:05] */ 32815 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK 0x0020 32816 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN 0 32817 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS 1 32818 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT 5 32819 32820 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_4 [04:04] */ 32821 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK 0x0010 32822 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN 0 32823 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS 1 32824 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT 4 32825 32826 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_3 [03:03] */ 32827 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK 0x0008 32828 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN 0 32829 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS 1 32830 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT 3 32831 32832 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_2 [02:02] */ 32833 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK 0x0004 32834 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN 0 32835 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS 1 32836 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT 2 32837 32838 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_1 [01:01] */ 32839 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK 0x0002 32840 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN 0 32841 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS 1 32842 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT 1 32843 32844 /* Dsc4b0 :: sm_status9 :: srch_state_one_hot_0 [00:00] */ 32845 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK 0x0001 32846 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN 0 32847 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS 1 32848 #define DSC4B0_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT 0 32849 32850 32851 /**************************************************************************** 32852 * Hypercore_USER_Dsc4b1 32853 */ 32854 /**************************************************************************** 32855 * Dsc4b1 :: sm_ctrl13 32856 */ 32857 /* Dsc4b1 :: sm_ctrl13 :: reserved0 [15:15] */ 32858 #define DSC4B1_SM_CTRL13_RESERVED0_MASK 0x8000 32859 #define DSC4B1_SM_CTRL13_RESERVED0_ALIGN 0 32860 #define DSC4B1_SM_CTRL13_RESERVED0_BITS 1 32861 #define DSC4B1_SM_CTRL13_RESERVED0_SHIFT 15 32862 32863 /* Dsc4b1 :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */ 32864 #define DSC4B1_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK 0x7c00 32865 #define DSC4B1_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN 0 32866 #define DSC4B1_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS 5 32867 #define DSC4B1_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT 10 32868 32869 /* Dsc4b1 :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */ 32870 #define DSC4B1_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK 0x03e0 32871 #define DSC4B1_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN 0 32872 #define DSC4B1_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS 5 32873 #define DSC4B1_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT 5 32874 32875 /* Dsc4b1 :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */ 32876 #define DSC4B1_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK 0x001f 32877 #define DSC4B1_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN 0 32878 #define DSC4B1_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS 5 32879 #define DSC4B1_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT 0 32880 32881 32882 /**************************************************************************** 32883 * Dsc4b1 :: sm_ctrl14 32884 */ 32885 /* Dsc4b1 :: sm_ctrl14 :: reserved0 [15:14] */ 32886 #define DSC4B1_SM_CTRL14_RESERVED0_MASK 0xc000 32887 #define DSC4B1_SM_CTRL14_RESERVED0_ALIGN 0 32888 #define DSC4B1_SM_CTRL14_RESERVED0_BITS 2 32889 #define DSC4B1_SM_CTRL14_RESERVED0_SHIFT 14 32890 32891 /* Dsc4b1 :: sm_ctrl14 :: br_postc_tap_en [13:07] */ 32892 #define DSC4B1_SM_CTRL14_BR_POSTC_TAP_EN_MASK 0x3f80 32893 #define DSC4B1_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN 0 32894 #define DSC4B1_SM_CTRL14_BR_POSTC_TAP_EN_BITS 7 32895 #define DSC4B1_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT 7 32896 32897 /* Dsc4b1 :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */ 32898 #define DSC4B1_SM_CTRL14_OSX2_PF_TAP_EN_MASK 0x007f 32899 #define DSC4B1_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN 0 32900 #define DSC4B1_SM_CTRL14_OSX2_PF_TAP_EN_BITS 7 32901 #define DSC4B1_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT 0 32902 32903 32904 /**************************************************************************** 32905 * Dsc4b1 :: sm_ctrl15 32906 */ 32907 /* Dsc4b1 :: sm_ctrl15 :: reserved0 [15:14] */ 32908 #define DSC4B1_SM_CTRL15_RESERVED0_MASK 0xc000 32909 #define DSC4B1_SM_CTRL15_RESERVED0_ALIGN 0 32910 #define DSC4B1_SM_CTRL15_RESERVED0_BITS 2 32911 #define DSC4B1_SM_CTRL15_RESERVED0_SHIFT 14 32912 32913 /* Dsc4b1 :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */ 32914 #define DSC4B1_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK 0x3f80 32915 #define DSC4B1_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN 0 32916 #define DSC4B1_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS 7 32917 #define DSC4B1_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT 7 32918 32919 /* Dsc4b1 :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */ 32920 #define DSC4B1_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK 0x007f 32921 #define DSC4B1_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN 0 32922 #define DSC4B1_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS 7 32923 #define DSC4B1_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT 0 32924 32925 32926 /**************************************************************************** 32927 * Dsc4b1 :: sm_ctrl16 32928 */ 32929 /* Dsc4b1 :: sm_ctrl16 :: reserved0 [15:15] */ 32930 #define DSC4B1_SM_CTRL16_RESERVED0_MASK 0x8000 32931 #define DSC4B1_SM_CTRL16_RESERVED0_ALIGN 0 32932 #define DSC4B1_SM_CTRL16_RESERVED0_BITS 1 32933 #define DSC4B1_SM_CTRL16_RESERVED0_SHIFT 15 32934 32935 /* Dsc4b1 :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */ 32936 #define DSC4B1_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK 0x7c00 32937 #define DSC4B1_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN 0 32938 #define DSC4B1_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS 5 32939 #define DSC4B1_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT 10 32940 32941 /* Dsc4b1 :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */ 32942 #define DSC4B1_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK 0x03e0 32943 #define DSC4B1_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN 0 32944 #define DSC4B1_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS 5 32945 #define DSC4B1_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT 5 32946 32947 /* Dsc4b1 :: sm_ctrl16 :: default_trn2_timeout [04:00] */ 32948 #define DSC4B1_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK 0x001f 32949 #define DSC4B1_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN 0 32950 #define DSC4B1_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS 5 32951 #define DSC4B1_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT 0 32952 32953 32954 /**************************************************************************** 32955 * Dsc4b1 :: sm_ctrl17 32956 */ 32957 /* Dsc4b1 :: sm_ctrl17 :: reserved0 [15:02] */ 32958 #define DSC4B1_SM_CTRL17_RESERVED0_MASK 0xfffc 32959 #define DSC4B1_SM_CTRL17_RESERVED0_ALIGN 0 32960 #define DSC4B1_SM_CTRL17_RESERVED0_BITS 14 32961 #define DSC4B1_SM_CTRL17_RESERVED0_SHIFT 2 32962 32963 /* Dsc4b1 :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */ 32964 #define DSC4B1_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK 0x0002 32965 #define DSC4B1_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN 0 32966 #define DSC4B1_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS 1 32967 #define DSC4B1_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT 1 32968 32969 /* Dsc4b1 :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */ 32970 #define DSC4B1_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK 0x0001 32971 #define DSC4B1_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN 0 32972 #define DSC4B1_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS 1 32973 #define DSC4B1_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT 0 32974 32975 32976 /**************************************************************************** 32977 * Dsc4b1 :: sm_status7 32978 */ 32979 /* Dsc4b1 :: sm_status7 :: reserved_for_eco0 [15:12] */ 32980 #define DSC4B1_SM_STATUS7_RESERVED_FOR_ECO0_MASK 0xf000 32981 #define DSC4B1_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN 0 32982 #define DSC4B1_SM_STATUS7_RESERVED_FOR_ECO0_BITS 4 32983 #define DSC4B1_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT 12 32984 32985 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_11 [11:11] */ 32986 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK 0x0800 32987 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN 0 32988 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS 1 32989 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT 11 32990 32991 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_10 [10:10] */ 32992 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK 0x0400 32993 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN 0 32994 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS 1 32995 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT 10 32996 32997 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_9 [09:09] */ 32998 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK 0x0200 32999 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN 0 33000 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS 1 33001 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT 9 33002 33003 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_8 [08:08] */ 33004 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK 0x0100 33005 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN 0 33006 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS 1 33007 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT 8 33008 33009 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_7 [07:07] */ 33010 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK 0x0080 33011 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN 0 33012 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS 1 33013 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT 7 33014 33015 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_6 [06:06] */ 33016 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK 0x0040 33017 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN 0 33018 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS 1 33019 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT 6 33020 33021 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_5 [05:05] */ 33022 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK 0x0020 33023 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN 0 33024 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS 1 33025 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT 5 33026 33027 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_4 [04:04] */ 33028 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK 0x0010 33029 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN 0 33030 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS 1 33031 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT 4 33032 33033 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_3 [03:03] */ 33034 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK 0x0008 33035 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN 0 33036 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS 1 33037 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT 3 33038 33039 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_2 [02:02] */ 33040 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK 0x0004 33041 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN 0 33042 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS 1 33043 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT 2 33044 33045 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_1 [01:01] */ 33046 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK 0x0002 33047 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN 0 33048 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS 1 33049 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT 1 33050 33051 /* Dsc4b1 :: sm_status7 :: dsc_state_one_hot_0 [00:00] */ 33052 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK 0x0001 33053 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN 0 33054 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS 1 33055 #define DSC4B1_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT 0 33056 33057 33058 /**************************************************************************** 33059 * Dsc4b1 :: sm_status8 33060 */ 33061 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_15 [15:15] */ 33062 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK 0x8000 33063 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN 0 33064 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS 1 33065 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT 15 33066 33067 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_14 [14:14] */ 33068 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK 0x4000 33069 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN 0 33070 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS 1 33071 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT 14 33072 33073 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_13 [13:13] */ 33074 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK 0x2000 33075 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN 0 33076 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS 1 33077 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT 13 33078 33079 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_12 [12:12] */ 33080 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK 0x1000 33081 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN 0 33082 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS 1 33083 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT 12 33084 33085 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_11 [11:11] */ 33086 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK 0x0800 33087 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN 0 33088 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS 1 33089 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT 11 33090 33091 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_10 [10:10] */ 33092 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK 0x0400 33093 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN 0 33094 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS 1 33095 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT 10 33096 33097 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_9 [09:09] */ 33098 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK 0x0200 33099 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN 0 33100 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS 1 33101 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT 9 33102 33103 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_8 [08:08] */ 33104 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK 0x0100 33105 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN 0 33106 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS 1 33107 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT 8 33108 33109 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_7 [07:07] */ 33110 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK 0x0080 33111 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN 0 33112 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS 1 33113 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT 7 33114 33115 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_6 [06:06] */ 33116 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK 0x0040 33117 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN 0 33118 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS 1 33119 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT 6 33120 33121 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_5 [05:05] */ 33122 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK 0x0020 33123 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN 0 33124 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS 1 33125 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT 5 33126 33127 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_4 [04:04] */ 33128 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK 0x0010 33129 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN 0 33130 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS 1 33131 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT 4 33132 33133 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_3 [03:03] */ 33134 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK 0x0008 33135 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN 0 33136 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS 1 33137 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT 3 33138 33139 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_2 [02:02] */ 33140 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK 0x0004 33141 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN 0 33142 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS 1 33143 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT 2 33144 33145 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_1 [01:01] */ 33146 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK 0x0002 33147 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN 0 33148 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS 1 33149 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT 1 33150 33151 /* Dsc4b1 :: sm_status8 :: tuning_state_one_hot_0 [00:00] */ 33152 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK 0x0001 33153 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN 0 33154 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS 1 33155 #define DSC4B1_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT 0 33156 33157 33158 /**************************************************************************** 33159 * Dsc4b1 :: sm_status9 33160 */ 33161 /* Dsc4b1 :: sm_status9 :: reserved_for_eco0 [15:12] */ 33162 #define DSC4B1_SM_STATUS9_RESERVED_FOR_ECO0_MASK 0xf000 33163 #define DSC4B1_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN 0 33164 #define DSC4B1_SM_STATUS9_RESERVED_FOR_ECO0_BITS 4 33165 #define DSC4B1_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT 12 33166 33167 /* Dsc4b1 :: sm_status9 :: tuning_state_one_hot_17 [11:11] */ 33168 #define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK 0x0800 33169 #define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN 0 33170 #define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS 1 33171 #define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT 11 33172 33173 /* Dsc4b1 :: sm_status9 :: tuning_state_one_hot_16 [10:10] */ 33174 #define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK 0x0400 33175 #define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN 0 33176 #define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS 1 33177 #define DSC4B1_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT 10 33178 33179 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_9 [09:09] */ 33180 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK 0x0200 33181 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN 0 33182 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS 1 33183 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT 9 33184 33185 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_8 [08:08] */ 33186 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK 0x0100 33187 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN 0 33188 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS 1 33189 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT 8 33190 33191 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_7 [07:07] */ 33192 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK 0x0080 33193 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN 0 33194 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS 1 33195 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT 7 33196 33197 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_6 [06:06] */ 33198 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK 0x0040 33199 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN 0 33200 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS 1 33201 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT 6 33202 33203 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_5 [05:05] */ 33204 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK 0x0020 33205 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN 0 33206 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS 1 33207 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT 5 33208 33209 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_4 [04:04] */ 33210 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK 0x0010 33211 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN 0 33212 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS 1 33213 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT 4 33214 33215 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_3 [03:03] */ 33216 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK 0x0008 33217 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN 0 33218 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS 1 33219 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT 3 33220 33221 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_2 [02:02] */ 33222 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK 0x0004 33223 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN 0 33224 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS 1 33225 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT 2 33226 33227 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_1 [01:01] */ 33228 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK 0x0002 33229 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN 0 33230 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS 1 33231 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT 1 33232 33233 /* Dsc4b1 :: sm_status9 :: srch_state_one_hot_0 [00:00] */ 33234 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK 0x0001 33235 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN 0 33236 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS 1 33237 #define DSC4B1_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT 0 33238 33239 33240 /**************************************************************************** 33241 * Hypercore_USER_Dsc4b2 33242 */ 33243 /**************************************************************************** 33244 * Dsc4b2 :: sm_ctrl13 33245 */ 33246 /* Dsc4b2 :: sm_ctrl13 :: reserved0 [15:15] */ 33247 #define DSC4B2_SM_CTRL13_RESERVED0_MASK 0x8000 33248 #define DSC4B2_SM_CTRL13_RESERVED0_ALIGN 0 33249 #define DSC4B2_SM_CTRL13_RESERVED0_BITS 1 33250 #define DSC4B2_SM_CTRL13_RESERVED0_SHIFT 15 33251 33252 /* Dsc4b2 :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */ 33253 #define DSC4B2_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK 0x7c00 33254 #define DSC4B2_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN 0 33255 #define DSC4B2_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS 5 33256 #define DSC4B2_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT 10 33257 33258 /* Dsc4b2 :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */ 33259 #define DSC4B2_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK 0x03e0 33260 #define DSC4B2_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN 0 33261 #define DSC4B2_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS 5 33262 #define DSC4B2_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT 5 33263 33264 /* Dsc4b2 :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */ 33265 #define DSC4B2_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK 0x001f 33266 #define DSC4B2_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN 0 33267 #define DSC4B2_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS 5 33268 #define DSC4B2_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT 0 33269 33270 33271 /**************************************************************************** 33272 * Dsc4b2 :: sm_ctrl14 33273 */ 33274 /* Dsc4b2 :: sm_ctrl14 :: reserved0 [15:14] */ 33275 #define DSC4B2_SM_CTRL14_RESERVED0_MASK 0xc000 33276 #define DSC4B2_SM_CTRL14_RESERVED0_ALIGN 0 33277 #define DSC4B2_SM_CTRL14_RESERVED0_BITS 2 33278 #define DSC4B2_SM_CTRL14_RESERVED0_SHIFT 14 33279 33280 /* Dsc4b2 :: sm_ctrl14 :: br_postc_tap_en [13:07] */ 33281 #define DSC4B2_SM_CTRL14_BR_POSTC_TAP_EN_MASK 0x3f80 33282 #define DSC4B2_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN 0 33283 #define DSC4B2_SM_CTRL14_BR_POSTC_TAP_EN_BITS 7 33284 #define DSC4B2_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT 7 33285 33286 /* Dsc4b2 :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */ 33287 #define DSC4B2_SM_CTRL14_OSX2_PF_TAP_EN_MASK 0x007f 33288 #define DSC4B2_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN 0 33289 #define DSC4B2_SM_CTRL14_OSX2_PF_TAP_EN_BITS 7 33290 #define DSC4B2_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT 0 33291 33292 33293 /**************************************************************************** 33294 * Dsc4b2 :: sm_ctrl15 33295 */ 33296 /* Dsc4b2 :: sm_ctrl15 :: reserved0 [15:14] */ 33297 #define DSC4B2_SM_CTRL15_RESERVED0_MASK 0xc000 33298 #define DSC4B2_SM_CTRL15_RESERVED0_ALIGN 0 33299 #define DSC4B2_SM_CTRL15_RESERVED0_BITS 2 33300 #define DSC4B2_SM_CTRL15_RESERVED0_SHIFT 14 33301 33302 /* Dsc4b2 :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */ 33303 #define DSC4B2_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK 0x3f80 33304 #define DSC4B2_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN 0 33305 #define DSC4B2_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS 7 33306 #define DSC4B2_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT 7 33307 33308 /* Dsc4b2 :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */ 33309 #define DSC4B2_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK 0x007f 33310 #define DSC4B2_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN 0 33311 #define DSC4B2_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS 7 33312 #define DSC4B2_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT 0 33313 33314 33315 /**************************************************************************** 33316 * Dsc4b2 :: sm_ctrl16 33317 */ 33318 /* Dsc4b2 :: sm_ctrl16 :: reserved0 [15:15] */ 33319 #define DSC4B2_SM_CTRL16_RESERVED0_MASK 0x8000 33320 #define DSC4B2_SM_CTRL16_RESERVED0_ALIGN 0 33321 #define DSC4B2_SM_CTRL16_RESERVED0_BITS 1 33322 #define DSC4B2_SM_CTRL16_RESERVED0_SHIFT 15 33323 33324 /* Dsc4b2 :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */ 33325 #define DSC4B2_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK 0x7c00 33326 #define DSC4B2_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN 0 33327 #define DSC4B2_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS 5 33328 #define DSC4B2_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT 10 33329 33330 /* Dsc4b2 :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */ 33331 #define DSC4B2_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK 0x03e0 33332 #define DSC4B2_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN 0 33333 #define DSC4B2_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS 5 33334 #define DSC4B2_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT 5 33335 33336 /* Dsc4b2 :: sm_ctrl16 :: default_trn2_timeout [04:00] */ 33337 #define DSC4B2_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK 0x001f 33338 #define DSC4B2_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN 0 33339 #define DSC4B2_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS 5 33340 #define DSC4B2_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT 0 33341 33342 33343 /**************************************************************************** 33344 * Dsc4b2 :: sm_ctrl17 33345 */ 33346 /* Dsc4b2 :: sm_ctrl17 :: reserved0 [15:02] */ 33347 #define DSC4B2_SM_CTRL17_RESERVED0_MASK 0xfffc 33348 #define DSC4B2_SM_CTRL17_RESERVED0_ALIGN 0 33349 #define DSC4B2_SM_CTRL17_RESERVED0_BITS 14 33350 #define DSC4B2_SM_CTRL17_RESERVED0_SHIFT 2 33351 33352 /* Dsc4b2 :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */ 33353 #define DSC4B2_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK 0x0002 33354 #define DSC4B2_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN 0 33355 #define DSC4B2_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS 1 33356 #define DSC4B2_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT 1 33357 33358 /* Dsc4b2 :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */ 33359 #define DSC4B2_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK 0x0001 33360 #define DSC4B2_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN 0 33361 #define DSC4B2_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS 1 33362 #define DSC4B2_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT 0 33363 33364 33365 /**************************************************************************** 33366 * Dsc4b2 :: sm_status7 33367 */ 33368 /* Dsc4b2 :: sm_status7 :: reserved_for_eco0 [15:12] */ 33369 #define DSC4B2_SM_STATUS7_RESERVED_FOR_ECO0_MASK 0xf000 33370 #define DSC4B2_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN 0 33371 #define DSC4B2_SM_STATUS7_RESERVED_FOR_ECO0_BITS 4 33372 #define DSC4B2_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT 12 33373 33374 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_11 [11:11] */ 33375 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK 0x0800 33376 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN 0 33377 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS 1 33378 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT 11 33379 33380 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_10 [10:10] */ 33381 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK 0x0400 33382 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN 0 33383 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS 1 33384 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT 10 33385 33386 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_9 [09:09] */ 33387 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK 0x0200 33388 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN 0 33389 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS 1 33390 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT 9 33391 33392 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_8 [08:08] */ 33393 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK 0x0100 33394 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN 0 33395 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS 1 33396 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT 8 33397 33398 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_7 [07:07] */ 33399 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK 0x0080 33400 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN 0 33401 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS 1 33402 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT 7 33403 33404 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_6 [06:06] */ 33405 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK 0x0040 33406 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN 0 33407 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS 1 33408 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT 6 33409 33410 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_5 [05:05] */ 33411 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK 0x0020 33412 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN 0 33413 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS 1 33414 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT 5 33415 33416 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_4 [04:04] */ 33417 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK 0x0010 33418 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN 0 33419 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS 1 33420 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT 4 33421 33422 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_3 [03:03] */ 33423 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK 0x0008 33424 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN 0 33425 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS 1 33426 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT 3 33427 33428 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_2 [02:02] */ 33429 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK 0x0004 33430 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN 0 33431 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS 1 33432 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT 2 33433 33434 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_1 [01:01] */ 33435 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK 0x0002 33436 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN 0 33437 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS 1 33438 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT 1 33439 33440 /* Dsc4b2 :: sm_status7 :: dsc_state_one_hot_0 [00:00] */ 33441 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK 0x0001 33442 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN 0 33443 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS 1 33444 #define DSC4B2_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT 0 33445 33446 33447 /**************************************************************************** 33448 * Dsc4b2 :: sm_status8 33449 */ 33450 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_15 [15:15] */ 33451 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK 0x8000 33452 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN 0 33453 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS 1 33454 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT 15 33455 33456 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_14 [14:14] */ 33457 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK 0x4000 33458 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN 0 33459 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS 1 33460 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT 14 33461 33462 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_13 [13:13] */ 33463 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK 0x2000 33464 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN 0 33465 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS 1 33466 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT 13 33467 33468 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_12 [12:12] */ 33469 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK 0x1000 33470 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN 0 33471 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS 1 33472 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT 12 33473 33474 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_11 [11:11] */ 33475 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK 0x0800 33476 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN 0 33477 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS 1 33478 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT 11 33479 33480 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_10 [10:10] */ 33481 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK 0x0400 33482 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN 0 33483 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS 1 33484 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT 10 33485 33486 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_9 [09:09] */ 33487 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK 0x0200 33488 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN 0 33489 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS 1 33490 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT 9 33491 33492 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_8 [08:08] */ 33493 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK 0x0100 33494 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN 0 33495 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS 1 33496 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT 8 33497 33498 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_7 [07:07] */ 33499 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK 0x0080 33500 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN 0 33501 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS 1 33502 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT 7 33503 33504 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_6 [06:06] */ 33505 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK 0x0040 33506 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN 0 33507 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS 1 33508 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT 6 33509 33510 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_5 [05:05] */ 33511 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK 0x0020 33512 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN 0 33513 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS 1 33514 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT 5 33515 33516 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_4 [04:04] */ 33517 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK 0x0010 33518 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN 0 33519 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS 1 33520 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT 4 33521 33522 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_3 [03:03] */ 33523 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK 0x0008 33524 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN 0 33525 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS 1 33526 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT 3 33527 33528 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_2 [02:02] */ 33529 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK 0x0004 33530 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN 0 33531 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS 1 33532 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT 2 33533 33534 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_1 [01:01] */ 33535 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK 0x0002 33536 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN 0 33537 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS 1 33538 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT 1 33539 33540 /* Dsc4b2 :: sm_status8 :: tuning_state_one_hot_0 [00:00] */ 33541 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK 0x0001 33542 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN 0 33543 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS 1 33544 #define DSC4B2_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT 0 33545 33546 33547 /**************************************************************************** 33548 * Dsc4b2 :: sm_status9 33549 */ 33550 /* Dsc4b2 :: sm_status9 :: reserved_for_eco0 [15:12] */ 33551 #define DSC4B2_SM_STATUS9_RESERVED_FOR_ECO0_MASK 0xf000 33552 #define DSC4B2_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN 0 33553 #define DSC4B2_SM_STATUS9_RESERVED_FOR_ECO0_BITS 4 33554 #define DSC4B2_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT 12 33555 33556 /* Dsc4b2 :: sm_status9 :: tuning_state_one_hot_17 [11:11] */ 33557 #define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK 0x0800 33558 #define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN 0 33559 #define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS 1 33560 #define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT 11 33561 33562 /* Dsc4b2 :: sm_status9 :: tuning_state_one_hot_16 [10:10] */ 33563 #define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK 0x0400 33564 #define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN 0 33565 #define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS 1 33566 #define DSC4B2_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT 10 33567 33568 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_9 [09:09] */ 33569 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK 0x0200 33570 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN 0 33571 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS 1 33572 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT 9 33573 33574 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_8 [08:08] */ 33575 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK 0x0100 33576 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN 0 33577 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS 1 33578 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT 8 33579 33580 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_7 [07:07] */ 33581 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK 0x0080 33582 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN 0 33583 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS 1 33584 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT 7 33585 33586 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_6 [06:06] */ 33587 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK 0x0040 33588 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN 0 33589 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS 1 33590 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT 6 33591 33592 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_5 [05:05] */ 33593 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK 0x0020 33594 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN 0 33595 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS 1 33596 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT 5 33597 33598 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_4 [04:04] */ 33599 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK 0x0010 33600 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN 0 33601 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS 1 33602 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT 4 33603 33604 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_3 [03:03] */ 33605 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK 0x0008 33606 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN 0 33607 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS 1 33608 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT 3 33609 33610 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_2 [02:02] */ 33611 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK 0x0004 33612 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN 0 33613 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS 1 33614 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT 2 33615 33616 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_1 [01:01] */ 33617 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK 0x0002 33618 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN 0 33619 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS 1 33620 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT 1 33621 33622 /* Dsc4b2 :: sm_status9 :: srch_state_one_hot_0 [00:00] */ 33623 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK 0x0001 33624 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN 0 33625 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS 1 33626 #define DSC4B2_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT 0 33627 33628 33629 /**************************************************************************** 33630 * Hypercore_USER_Dsc4b3 33631 */ 33632 /**************************************************************************** 33633 * Dsc4b3 :: sm_ctrl13 33634 */ 33635 /* Dsc4b3 :: sm_ctrl13 :: reserved0 [15:15] */ 33636 #define DSC4B3_SM_CTRL13_RESERVED0_MASK 0x8000 33637 #define DSC4B3_SM_CTRL13_RESERVED0_ALIGN 0 33638 #define DSC4B3_SM_CTRL13_RESERVED0_BITS 1 33639 #define DSC4B3_SM_CTRL13_RESERVED0_SHIFT 15 33640 33641 /* Dsc4b3 :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */ 33642 #define DSC4B3_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK 0x7c00 33643 #define DSC4B3_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN 0 33644 #define DSC4B3_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS 5 33645 #define DSC4B3_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT 10 33646 33647 /* Dsc4b3 :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */ 33648 #define DSC4B3_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK 0x03e0 33649 #define DSC4B3_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN 0 33650 #define DSC4B3_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS 5 33651 #define DSC4B3_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT 5 33652 33653 /* Dsc4b3 :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */ 33654 #define DSC4B3_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK 0x001f 33655 #define DSC4B3_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN 0 33656 #define DSC4B3_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS 5 33657 #define DSC4B3_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT 0 33658 33659 33660 /**************************************************************************** 33661 * Dsc4b3 :: sm_ctrl14 33662 */ 33663 /* Dsc4b3 :: sm_ctrl14 :: reserved0 [15:14] */ 33664 #define DSC4B3_SM_CTRL14_RESERVED0_MASK 0xc000 33665 #define DSC4B3_SM_CTRL14_RESERVED0_ALIGN 0 33666 #define DSC4B3_SM_CTRL14_RESERVED0_BITS 2 33667 #define DSC4B3_SM_CTRL14_RESERVED0_SHIFT 14 33668 33669 /* Dsc4b3 :: sm_ctrl14 :: br_postc_tap_en [13:07] */ 33670 #define DSC4B3_SM_CTRL14_BR_POSTC_TAP_EN_MASK 0x3f80 33671 #define DSC4B3_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN 0 33672 #define DSC4B3_SM_CTRL14_BR_POSTC_TAP_EN_BITS 7 33673 #define DSC4B3_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT 7 33674 33675 /* Dsc4b3 :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */ 33676 #define DSC4B3_SM_CTRL14_OSX2_PF_TAP_EN_MASK 0x007f 33677 #define DSC4B3_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN 0 33678 #define DSC4B3_SM_CTRL14_OSX2_PF_TAP_EN_BITS 7 33679 #define DSC4B3_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT 0 33680 33681 33682 /**************************************************************************** 33683 * Dsc4b3 :: sm_ctrl15 33684 */ 33685 /* Dsc4b3 :: sm_ctrl15 :: reserved0 [15:14] */ 33686 #define DSC4B3_SM_CTRL15_RESERVED0_MASK 0xc000 33687 #define DSC4B3_SM_CTRL15_RESERVED0_ALIGN 0 33688 #define DSC4B3_SM_CTRL15_RESERVED0_BITS 2 33689 #define DSC4B3_SM_CTRL15_RESERVED0_SHIFT 14 33690 33691 /* Dsc4b3 :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */ 33692 #define DSC4B3_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK 0x3f80 33693 #define DSC4B3_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN 0 33694 #define DSC4B3_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS 7 33695 #define DSC4B3_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT 7 33696 33697 /* Dsc4b3 :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */ 33698 #define DSC4B3_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK 0x007f 33699 #define DSC4B3_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN 0 33700 #define DSC4B3_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS 7 33701 #define DSC4B3_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT 0 33702 33703 33704 /**************************************************************************** 33705 * Dsc4b3 :: sm_ctrl16 33706 */ 33707 /* Dsc4b3 :: sm_ctrl16 :: reserved0 [15:15] */ 33708 #define DSC4B3_SM_CTRL16_RESERVED0_MASK 0x8000 33709 #define DSC4B3_SM_CTRL16_RESERVED0_ALIGN 0 33710 #define DSC4B3_SM_CTRL16_RESERVED0_BITS 1 33711 #define DSC4B3_SM_CTRL16_RESERVED0_SHIFT 15 33712 33713 /* Dsc4b3 :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */ 33714 #define DSC4B3_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK 0x7c00 33715 #define DSC4B3_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN 0 33716 #define DSC4B3_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS 5 33717 #define DSC4B3_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT 10 33718 33719 /* Dsc4b3 :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */ 33720 #define DSC4B3_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK 0x03e0 33721 #define DSC4B3_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN 0 33722 #define DSC4B3_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS 5 33723 #define DSC4B3_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT 5 33724 33725 /* Dsc4b3 :: sm_ctrl16 :: default_trn2_timeout [04:00] */ 33726 #define DSC4B3_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK 0x001f 33727 #define DSC4B3_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN 0 33728 #define DSC4B3_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS 5 33729 #define DSC4B3_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT 0 33730 33731 33732 /**************************************************************************** 33733 * Dsc4b3 :: sm_ctrl17 33734 */ 33735 /* Dsc4b3 :: sm_ctrl17 :: reserved0 [15:02] */ 33736 #define DSC4B3_SM_CTRL17_RESERVED0_MASK 0xfffc 33737 #define DSC4B3_SM_CTRL17_RESERVED0_ALIGN 0 33738 #define DSC4B3_SM_CTRL17_RESERVED0_BITS 14 33739 #define DSC4B3_SM_CTRL17_RESERVED0_SHIFT 2 33740 33741 /* Dsc4b3 :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */ 33742 #define DSC4B3_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK 0x0002 33743 #define DSC4B3_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN 0 33744 #define DSC4B3_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS 1 33745 #define DSC4B3_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT 1 33746 33747 /* Dsc4b3 :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */ 33748 #define DSC4B3_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK 0x0001 33749 #define DSC4B3_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN 0 33750 #define DSC4B3_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS 1 33751 #define DSC4B3_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT 0 33752 33753 33754 /**************************************************************************** 33755 * Dsc4b3 :: sm_status7 33756 */ 33757 /* Dsc4b3 :: sm_status7 :: reserved_for_eco0 [15:12] */ 33758 #define DSC4B3_SM_STATUS7_RESERVED_FOR_ECO0_MASK 0xf000 33759 #define DSC4B3_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN 0 33760 #define DSC4B3_SM_STATUS7_RESERVED_FOR_ECO0_BITS 4 33761 #define DSC4B3_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT 12 33762 33763 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_11 [11:11] */ 33764 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK 0x0800 33765 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN 0 33766 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS 1 33767 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT 11 33768 33769 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_10 [10:10] */ 33770 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK 0x0400 33771 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN 0 33772 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS 1 33773 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT 10 33774 33775 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_9 [09:09] */ 33776 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK 0x0200 33777 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN 0 33778 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS 1 33779 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT 9 33780 33781 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_8 [08:08] */ 33782 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK 0x0100 33783 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN 0 33784 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS 1 33785 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT 8 33786 33787 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_7 [07:07] */ 33788 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK 0x0080 33789 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN 0 33790 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS 1 33791 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT 7 33792 33793 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_6 [06:06] */ 33794 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK 0x0040 33795 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN 0 33796 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS 1 33797 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT 6 33798 33799 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_5 [05:05] */ 33800 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK 0x0020 33801 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN 0 33802 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS 1 33803 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT 5 33804 33805 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_4 [04:04] */ 33806 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK 0x0010 33807 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN 0 33808 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS 1 33809 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT 4 33810 33811 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_3 [03:03] */ 33812 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK 0x0008 33813 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN 0 33814 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS 1 33815 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT 3 33816 33817 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_2 [02:02] */ 33818 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK 0x0004 33819 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN 0 33820 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS 1 33821 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT 2 33822 33823 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_1 [01:01] */ 33824 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK 0x0002 33825 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN 0 33826 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS 1 33827 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT 1 33828 33829 /* Dsc4b3 :: sm_status7 :: dsc_state_one_hot_0 [00:00] */ 33830 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK 0x0001 33831 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN 0 33832 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS 1 33833 #define DSC4B3_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT 0 33834 33835 33836 /**************************************************************************** 33837 * Dsc4b3 :: sm_status8 33838 */ 33839 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_15 [15:15] */ 33840 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK 0x8000 33841 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN 0 33842 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS 1 33843 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT 15 33844 33845 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_14 [14:14] */ 33846 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK 0x4000 33847 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN 0 33848 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS 1 33849 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT 14 33850 33851 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_13 [13:13] */ 33852 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK 0x2000 33853 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN 0 33854 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS 1 33855 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT 13 33856 33857 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_12 [12:12] */ 33858 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK 0x1000 33859 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN 0 33860 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS 1 33861 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT 12 33862 33863 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_11 [11:11] */ 33864 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK 0x0800 33865 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN 0 33866 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS 1 33867 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT 11 33868 33869 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_10 [10:10] */ 33870 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK 0x0400 33871 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN 0 33872 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS 1 33873 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT 10 33874 33875 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_9 [09:09] */ 33876 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK 0x0200 33877 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN 0 33878 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS 1 33879 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT 9 33880 33881 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_8 [08:08] */ 33882 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK 0x0100 33883 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN 0 33884 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS 1 33885 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT 8 33886 33887 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_7 [07:07] */ 33888 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK 0x0080 33889 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN 0 33890 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS 1 33891 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT 7 33892 33893 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_6 [06:06] */ 33894 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK 0x0040 33895 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN 0 33896 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS 1 33897 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT 6 33898 33899 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_5 [05:05] */ 33900 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK 0x0020 33901 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN 0 33902 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS 1 33903 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT 5 33904 33905 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_4 [04:04] */ 33906 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK 0x0010 33907 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN 0 33908 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS 1 33909 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT 4 33910 33911 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_3 [03:03] */ 33912 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK 0x0008 33913 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN 0 33914 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS 1 33915 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT 3 33916 33917 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_2 [02:02] */ 33918 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK 0x0004 33919 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN 0 33920 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS 1 33921 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT 2 33922 33923 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_1 [01:01] */ 33924 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK 0x0002 33925 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN 0 33926 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS 1 33927 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT 1 33928 33929 /* Dsc4b3 :: sm_status8 :: tuning_state_one_hot_0 [00:00] */ 33930 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK 0x0001 33931 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN 0 33932 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS 1 33933 #define DSC4B3_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT 0 33934 33935 33936 /**************************************************************************** 33937 * Dsc4b3 :: sm_status9 33938 */ 33939 /* Dsc4b3 :: sm_status9 :: reserved_for_eco0 [15:12] */ 33940 #define DSC4B3_SM_STATUS9_RESERVED_FOR_ECO0_MASK 0xf000 33941 #define DSC4B3_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN 0 33942 #define DSC4B3_SM_STATUS9_RESERVED_FOR_ECO0_BITS 4 33943 #define DSC4B3_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT 12 33944 33945 /* Dsc4b3 :: sm_status9 :: tuning_state_one_hot_17 [11:11] */ 33946 #define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK 0x0800 33947 #define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN 0 33948 #define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS 1 33949 #define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT 11 33950 33951 /* Dsc4b3 :: sm_status9 :: tuning_state_one_hot_16 [10:10] */ 33952 #define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK 0x0400 33953 #define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN 0 33954 #define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS 1 33955 #define DSC4B3_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT 10 33956 33957 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_9 [09:09] */ 33958 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK 0x0200 33959 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN 0 33960 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS 1 33961 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT 9 33962 33963 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_8 [08:08] */ 33964 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK 0x0100 33965 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN 0 33966 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS 1 33967 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT 8 33968 33969 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_7 [07:07] */ 33970 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK 0x0080 33971 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN 0 33972 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS 1 33973 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT 7 33974 33975 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_6 [06:06] */ 33976 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK 0x0040 33977 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN 0 33978 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS 1 33979 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT 6 33980 33981 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_5 [05:05] */ 33982 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK 0x0020 33983 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN 0 33984 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS 1 33985 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT 5 33986 33987 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_4 [04:04] */ 33988 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK 0x0010 33989 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN 0 33990 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS 1 33991 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT 4 33992 33993 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_3 [03:03] */ 33994 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK 0x0008 33995 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN 0 33996 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS 1 33997 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT 3 33998 33999 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_2 [02:02] */ 34000 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK 0x0004 34001 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN 0 34002 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS 1 34003 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT 2 34004 34005 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_1 [01:01] */ 34006 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK 0x0002 34007 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN 0 34008 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS 1 34009 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT 1 34010 34011 /* Dsc4b3 :: sm_status9 :: srch_state_one_hot_0 [00:00] */ 34012 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK 0x0001 34013 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN 0 34014 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS 1 34015 #define DSC4B3_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT 0 34016 34017 34018 /**************************************************************************** 34019 * Hypercore_USER_Dsc4bB 34020 */ 34021 /**************************************************************************** 34022 * Dsc4bB :: sm_ctrl13 34023 */ 34024 /* Dsc4bB :: sm_ctrl13 :: reserved0 [15:15] */ 34025 #define DSC4BB_SM_CTRL13_RESERVED0_MASK 0x8000 34026 #define DSC4BB_SM_CTRL13_RESERVED0_ALIGN 0 34027 #define DSC4BB_SM_CTRL13_RESERVED0_BITS 1 34028 #define DSC4BB_SM_CTRL13_RESERVED0_SHIFT 15 34029 34030 /* Dsc4bB :: sm_ctrl13 :: br_vga_trn2_timeout [14:10] */ 34031 #define DSC4BB_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_MASK 0x7c00 34032 #define DSC4BB_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_ALIGN 0 34033 #define DSC4BB_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_BITS 5 34034 #define DSC4BB_SM_CTRL13_BR_VGA_TRN2_TIMEOUT_SHIFT 10 34035 34036 /* Dsc4bB :: sm_ctrl13 :: br_pf_trn2_timeout [09:05] */ 34037 #define DSC4BB_SM_CTRL13_BR_PF_TRN2_TIMEOUT_MASK 0x03e0 34038 #define DSC4BB_SM_CTRL13_BR_PF_TRN2_TIMEOUT_ALIGN 0 34039 #define DSC4BB_SM_CTRL13_BR_PF_TRN2_TIMEOUT_BITS 5 34040 #define DSC4BB_SM_CTRL13_BR_PF_TRN2_TIMEOUT_SHIFT 5 34041 34042 /* Dsc4bB :: sm_ctrl13 :: br_pf_trn1_timeout [04:00] */ 34043 #define DSC4BB_SM_CTRL13_BR_PF_TRN1_TIMEOUT_MASK 0x001f 34044 #define DSC4BB_SM_CTRL13_BR_PF_TRN1_TIMEOUT_ALIGN 0 34045 #define DSC4BB_SM_CTRL13_BR_PF_TRN1_TIMEOUT_BITS 5 34046 #define DSC4BB_SM_CTRL13_BR_PF_TRN1_TIMEOUT_SHIFT 0 34047 34048 34049 /**************************************************************************** 34050 * Dsc4bB :: sm_ctrl14 34051 */ 34052 /* Dsc4bB :: sm_ctrl14 :: reserved0 [15:14] */ 34053 #define DSC4BB_SM_CTRL14_RESERVED0_MASK 0xc000 34054 #define DSC4BB_SM_CTRL14_RESERVED0_ALIGN 0 34055 #define DSC4BB_SM_CTRL14_RESERVED0_BITS 2 34056 #define DSC4BB_SM_CTRL14_RESERVED0_SHIFT 14 34057 34058 /* Dsc4bB :: sm_ctrl14 :: br_postc_tap_en [13:07] */ 34059 #define DSC4BB_SM_CTRL14_BR_POSTC_TAP_EN_MASK 0x3f80 34060 #define DSC4BB_SM_CTRL14_BR_POSTC_TAP_EN_ALIGN 0 34061 #define DSC4BB_SM_CTRL14_BR_POSTC_TAP_EN_BITS 7 34062 #define DSC4BB_SM_CTRL14_BR_POSTC_TAP_EN_SHIFT 7 34063 34064 /* Dsc4bB :: sm_ctrl14 :: osx2_pf_tap_en [06:00] */ 34065 #define DSC4BB_SM_CTRL14_OSX2_PF_TAP_EN_MASK 0x007f 34066 #define DSC4BB_SM_CTRL14_OSX2_PF_TAP_EN_ALIGN 0 34067 #define DSC4BB_SM_CTRL14_OSX2_PF_TAP_EN_BITS 7 34068 #define DSC4BB_SM_CTRL14_OSX2_PF_TAP_EN_SHIFT 0 34069 34070 34071 /**************************************************************************** 34072 * Dsc4bB :: sm_ctrl15 34073 */ 34074 /* Dsc4bB :: sm_ctrl15 :: reserved0 [15:14] */ 34075 #define DSC4BB_SM_CTRL15_RESERVED0_MASK 0xc000 34076 #define DSC4BB_SM_CTRL15_RESERVED0_ALIGN 0 34077 #define DSC4BB_SM_CTRL15_RESERVED0_BITS 2 34078 #define DSC4BB_SM_CTRL15_RESERVED0_SHIFT 14 34079 34080 /* Dsc4bB :: sm_ctrl15 :: osx2_postc_tap_en [13:07] */ 34081 #define DSC4BB_SM_CTRL15_OSX2_POSTC_TAP_EN_MASK 0x3f80 34082 #define DSC4BB_SM_CTRL15_OSX2_POSTC_TAP_EN_ALIGN 0 34083 #define DSC4BB_SM_CTRL15_OSX2_POSTC_TAP_EN_BITS 7 34084 #define DSC4BB_SM_CTRL15_OSX2_POSTC_TAP_EN_SHIFT 7 34085 34086 /* Dsc4bB :: sm_ctrl15 :: osx1_postc_tap_en [06:00] */ 34087 #define DSC4BB_SM_CTRL15_OSX1_POSTC_TAP_EN_MASK 0x007f 34088 #define DSC4BB_SM_CTRL15_OSX1_POSTC_TAP_EN_ALIGN 0 34089 #define DSC4BB_SM_CTRL15_OSX1_POSTC_TAP_EN_BITS 7 34090 #define DSC4BB_SM_CTRL15_OSX1_POSTC_TAP_EN_SHIFT 0 34091 34092 34093 /**************************************************************************** 34094 * Dsc4bB :: sm_ctrl16 34095 */ 34096 /* Dsc4bB :: sm_ctrl16 :: reserved0 [15:15] */ 34097 #define DSC4BB_SM_CTRL16_RESERVED0_MASK 0x8000 34098 #define DSC4BB_SM_CTRL16_RESERVED0_ALIGN 0 34099 #define DSC4BB_SM_CTRL16_RESERVED0_BITS 1 34100 #define DSC4BB_SM_CTRL16_RESERVED0_SHIFT 15 34101 34102 /* Dsc4bB :: sm_ctrl16 :: msr_slicer_slow_timeout [14:10] */ 34103 #define DSC4BB_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_MASK 0x7c00 34104 #define DSC4BB_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_ALIGN 0 34105 #define DSC4BB_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_BITS 5 34106 #define DSC4BB_SM_CTRL16_MSR_SLICER_SLOW_TIMEOUT_SHIFT 10 34107 34108 /* Dsc4bB :: sm_ctrl16 :: msr_slicer_fast_timeout [09:05] */ 34109 #define DSC4BB_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_MASK 0x03e0 34110 #define DSC4BB_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_ALIGN 0 34111 #define DSC4BB_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_BITS 5 34112 #define DSC4BB_SM_CTRL16_MSR_SLICER_FAST_TIMEOUT_SHIFT 5 34113 34114 /* Dsc4bB :: sm_ctrl16 :: default_trn2_timeout [04:00] */ 34115 #define DSC4BB_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_MASK 0x001f 34116 #define DSC4BB_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_ALIGN 0 34117 #define DSC4BB_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_BITS 5 34118 #define DSC4BB_SM_CTRL16_DEFAULT_TRN2_TIMEOUT_SHIFT 0 34119 34120 34121 /**************************************************************************** 34122 * Dsc4bB :: sm_ctrl17 34123 */ 34124 /* Dsc4bB :: sm_ctrl17 :: reserved0 [15:02] */ 34125 #define DSC4BB_SM_CTRL17_RESERVED0_MASK 0xfffc 34126 #define DSC4BB_SM_CTRL17_RESERVED0_ALIGN 0 34127 #define DSC4BB_SM_CTRL17_RESERVED0_BITS 14 34128 #define DSC4BB_SM_CTRL17_RESERVED0_SHIFT 2 34129 34130 /* Dsc4bB :: sm_ctrl17 :: bypass_osx1_slicer_cal [01:01] */ 34131 #define DSC4BB_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_MASK 0x0002 34132 #define DSC4BB_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_ALIGN 0 34133 #define DSC4BB_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_BITS 1 34134 #define DSC4BB_SM_CTRL17_BYPASS_OSX1_SLICER_CAL_SHIFT 1 34135 34136 /* Dsc4bB :: sm_ctrl17 :: bypass_osx2_slicer_cal [00:00] */ 34137 #define DSC4BB_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_MASK 0x0001 34138 #define DSC4BB_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_ALIGN 0 34139 #define DSC4BB_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_BITS 1 34140 #define DSC4BB_SM_CTRL17_BYPASS_OSX2_SLICER_CAL_SHIFT 0 34141 34142 34143 /**************************************************************************** 34144 * Dsc4bB :: sm_status7 34145 */ 34146 /* Dsc4bB :: sm_status7 :: reserved_for_eco0 [15:12] */ 34147 #define DSC4BB_SM_STATUS7_RESERVED_FOR_ECO0_MASK 0xf000 34148 #define DSC4BB_SM_STATUS7_RESERVED_FOR_ECO0_ALIGN 0 34149 #define DSC4BB_SM_STATUS7_RESERVED_FOR_ECO0_BITS 4 34150 #define DSC4BB_SM_STATUS7_RESERVED_FOR_ECO0_SHIFT 12 34151 34152 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_11 [11:11] */ 34153 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_11_MASK 0x0800 34154 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_11_ALIGN 0 34155 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_11_BITS 1 34156 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_11_SHIFT 11 34157 34158 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_10 [10:10] */ 34159 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_10_MASK 0x0400 34160 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_10_ALIGN 0 34161 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_10_BITS 1 34162 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_10_SHIFT 10 34163 34164 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_9 [09:09] */ 34165 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_9_MASK 0x0200 34166 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_9_ALIGN 0 34167 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_9_BITS 1 34168 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_9_SHIFT 9 34169 34170 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_8 [08:08] */ 34171 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_8_MASK 0x0100 34172 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_8_ALIGN 0 34173 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_8_BITS 1 34174 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_8_SHIFT 8 34175 34176 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_7 [07:07] */ 34177 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_7_MASK 0x0080 34178 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_7_ALIGN 0 34179 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_7_BITS 1 34180 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_7_SHIFT 7 34181 34182 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_6 [06:06] */ 34183 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_6_MASK 0x0040 34184 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_6_ALIGN 0 34185 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_6_BITS 1 34186 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_6_SHIFT 6 34187 34188 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_5 [05:05] */ 34189 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_5_MASK 0x0020 34190 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_5_ALIGN 0 34191 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_5_BITS 1 34192 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_5_SHIFT 5 34193 34194 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_4 [04:04] */ 34195 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_4_MASK 0x0010 34196 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_4_ALIGN 0 34197 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_4_BITS 1 34198 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_4_SHIFT 4 34199 34200 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_3 [03:03] */ 34201 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_3_MASK 0x0008 34202 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_3_ALIGN 0 34203 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_3_BITS 1 34204 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_3_SHIFT 3 34205 34206 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_2 [02:02] */ 34207 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_2_MASK 0x0004 34208 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_2_ALIGN 0 34209 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_2_BITS 1 34210 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_2_SHIFT 2 34211 34212 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_1 [01:01] */ 34213 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_1_MASK 0x0002 34214 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_1_ALIGN 0 34215 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_1_BITS 1 34216 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_1_SHIFT 1 34217 34218 /* Dsc4bB :: sm_status7 :: dsc_state_one_hot_0 [00:00] */ 34219 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_0_MASK 0x0001 34220 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_0_ALIGN 0 34221 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_0_BITS 1 34222 #define DSC4BB_SM_STATUS7_DSC_STATE_ONE_HOT_0_SHIFT 0 34223 34224 34225 /**************************************************************************** 34226 * Dsc4bB :: sm_status8 34227 */ 34228 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_15 [15:15] */ 34229 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_15_MASK 0x8000 34230 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_15_ALIGN 0 34231 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_15_BITS 1 34232 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_15_SHIFT 15 34233 34234 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_14 [14:14] */ 34235 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_14_MASK 0x4000 34236 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_14_ALIGN 0 34237 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_14_BITS 1 34238 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_14_SHIFT 14 34239 34240 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_13 [13:13] */ 34241 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_13_MASK 0x2000 34242 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_13_ALIGN 0 34243 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_13_BITS 1 34244 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_13_SHIFT 13 34245 34246 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_12 [12:12] */ 34247 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_12_MASK 0x1000 34248 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_12_ALIGN 0 34249 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_12_BITS 1 34250 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_12_SHIFT 12 34251 34252 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_11 [11:11] */ 34253 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_11_MASK 0x0800 34254 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_11_ALIGN 0 34255 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_11_BITS 1 34256 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_11_SHIFT 11 34257 34258 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_10 [10:10] */ 34259 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_10_MASK 0x0400 34260 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_10_ALIGN 0 34261 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_10_BITS 1 34262 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_10_SHIFT 10 34263 34264 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_9 [09:09] */ 34265 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_9_MASK 0x0200 34266 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_9_ALIGN 0 34267 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_9_BITS 1 34268 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_9_SHIFT 9 34269 34270 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_8 [08:08] */ 34271 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_8_MASK 0x0100 34272 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_8_ALIGN 0 34273 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_8_BITS 1 34274 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_8_SHIFT 8 34275 34276 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_7 [07:07] */ 34277 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_7_MASK 0x0080 34278 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_7_ALIGN 0 34279 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_7_BITS 1 34280 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_7_SHIFT 7 34281 34282 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_6 [06:06] */ 34283 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_6_MASK 0x0040 34284 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_6_ALIGN 0 34285 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_6_BITS 1 34286 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_6_SHIFT 6 34287 34288 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_5 [05:05] */ 34289 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_5_MASK 0x0020 34290 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_5_ALIGN 0 34291 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_5_BITS 1 34292 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_5_SHIFT 5 34293 34294 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_4 [04:04] */ 34295 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_4_MASK 0x0010 34296 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_4_ALIGN 0 34297 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_4_BITS 1 34298 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_4_SHIFT 4 34299 34300 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_3 [03:03] */ 34301 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_3_MASK 0x0008 34302 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_3_ALIGN 0 34303 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_3_BITS 1 34304 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_3_SHIFT 3 34305 34306 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_2 [02:02] */ 34307 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_2_MASK 0x0004 34308 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_2_ALIGN 0 34309 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_2_BITS 1 34310 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_2_SHIFT 2 34311 34312 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_1 [01:01] */ 34313 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_1_MASK 0x0002 34314 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_1_ALIGN 0 34315 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_1_BITS 1 34316 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_1_SHIFT 1 34317 34318 /* Dsc4bB :: sm_status8 :: tuning_state_one_hot_0 [00:00] */ 34319 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_0_MASK 0x0001 34320 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_0_ALIGN 0 34321 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_0_BITS 1 34322 #define DSC4BB_SM_STATUS8_TUNING_STATE_ONE_HOT_0_SHIFT 0 34323 34324 34325 /**************************************************************************** 34326 * Dsc4bB :: sm_status9 34327 */ 34328 /* Dsc4bB :: sm_status9 :: reserved_for_eco0 [15:12] */ 34329 #define DSC4BB_SM_STATUS9_RESERVED_FOR_ECO0_MASK 0xf000 34330 #define DSC4BB_SM_STATUS9_RESERVED_FOR_ECO0_ALIGN 0 34331 #define DSC4BB_SM_STATUS9_RESERVED_FOR_ECO0_BITS 4 34332 #define DSC4BB_SM_STATUS9_RESERVED_FOR_ECO0_SHIFT 12 34333 34334 /* Dsc4bB :: sm_status9 :: tuning_state_one_hot_17 [11:11] */ 34335 #define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_17_MASK 0x0800 34336 #define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_17_ALIGN 0 34337 #define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_17_BITS 1 34338 #define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_17_SHIFT 11 34339 34340 /* Dsc4bB :: sm_status9 :: tuning_state_one_hot_16 [10:10] */ 34341 #define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_16_MASK 0x0400 34342 #define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_16_ALIGN 0 34343 #define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_16_BITS 1 34344 #define DSC4BB_SM_STATUS9_TUNING_STATE_ONE_HOT_16_SHIFT 10 34345 34346 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_9 [09:09] */ 34347 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_9_MASK 0x0200 34348 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_9_ALIGN 0 34349 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_9_BITS 1 34350 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_9_SHIFT 9 34351 34352 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_8 [08:08] */ 34353 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_8_MASK 0x0100 34354 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_8_ALIGN 0 34355 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_8_BITS 1 34356 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_8_SHIFT 8 34357 34358 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_7 [07:07] */ 34359 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_7_MASK 0x0080 34360 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_7_ALIGN 0 34361 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_7_BITS 1 34362 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_7_SHIFT 7 34363 34364 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_6 [06:06] */ 34365 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_6_MASK 0x0040 34366 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_6_ALIGN 0 34367 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_6_BITS 1 34368 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_6_SHIFT 6 34369 34370 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_5 [05:05] */ 34371 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_5_MASK 0x0020 34372 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_5_ALIGN 0 34373 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_5_BITS 1 34374 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_5_SHIFT 5 34375 34376 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_4 [04:04] */ 34377 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_4_MASK 0x0010 34378 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_4_ALIGN 0 34379 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_4_BITS 1 34380 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_4_SHIFT 4 34381 34382 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_3 [03:03] */ 34383 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_3_MASK 0x0008 34384 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_3_ALIGN 0 34385 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_3_BITS 1 34386 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_3_SHIFT 3 34387 34388 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_2 [02:02] */ 34389 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_2_MASK 0x0004 34390 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_2_ALIGN 0 34391 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_2_BITS 1 34392 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_2_SHIFT 2 34393 34394 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_1 [01:01] */ 34395 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_1_MASK 0x0002 34396 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_1_ALIGN 0 34397 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_1_BITS 1 34398 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_1_SHIFT 1 34399 34400 /* Dsc4bB :: sm_status9 :: srch_state_one_hot_0 [00:00] */ 34401 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_0_MASK 0x0001 34402 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_0_ALIGN 0 34403 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_0_BITS 1 34404 #define DSC4BB_SM_STATUS9_SRCH_STATE_ONE_HOT_0_SHIFT 0 34405 34406 34407 /**************************************************************************** 34408 * Hypercore_USER_FX100 34409 */ 34410 /**************************************************************************** 34411 * FX100 :: Control1 34412 */ 34413 /* FX100 :: Control1 :: data_sampler_en [15:15] */ 34414 #define FX100_CONTROL1_DATA_SAMPLER_EN_MASK 0x8000 34415 #define FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN 0 34416 #define FX100_CONTROL1_DATA_SAMPLER_EN_BITS 1 34417 #define FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT 15 34418 34419 /* FX100 :: Control1 :: fiber_autopwrdwn_wakeup [14:14] */ 34420 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_MASK 0x4000 34421 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_ALIGN 0 34422 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_BITS 1 34423 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_WAKEUP_SHIFT 14 34424 34425 /* FX100 :: Control1 :: fiber_autopwrdwn_sleep [13:13] */ 34426 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_MASK 0x2000 34427 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_ALIGN 0 34428 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_BITS 1 34429 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_SLEEP_SHIFT 13 34430 34431 /* FX100 :: Control1 :: fiberautopwrdwn_en [12:12] */ 34432 #define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_MASK 0x1000 34433 #define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_ALIGN 0 34434 #define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_BITS 1 34435 #define FX100_CONTROL1_FIBERAUTOPWRDWN_EN_SHIFT 12 34436 34437 /* FX100 :: Control1 :: fiber_autopwrdwn_dis [11:11] */ 34438 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_MASK 0x0800 34439 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_ALIGN 0 34440 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_BITS 1 34441 #define FX100_CONTROL1_FIBER_AUTOPWRDWN_DIS_SHIFT 11 34442 34443 /* FX100 :: Control1 :: autodet_timer_sel [10:10] */ 34444 #define FX100_CONTROL1_AUTODET_TIMER_SEL_MASK 0x0400 34445 #define FX100_CONTROL1_AUTODET_TIMER_SEL_ALIGN 0 34446 #define FX100_CONTROL1_AUTODET_TIMER_SEL_BITS 1 34447 #define FX100_CONTROL1_AUTODET_TIMER_SEL_SHIFT 10 34448 34449 /* FX100 :: Control1 :: rxdata_sel [09:06] */ 34450 #define FX100_CONTROL1_RXDATA_SEL_MASK 0x03c0 34451 #define FX100_CONTROL1_RXDATA_SEL_ALIGN 0 34452 #define FX100_CONTROL1_RXDATA_SEL_BITS 4 34453 #define FX100_CONTROL1_RXDATA_SEL_SHIFT 6 34454 34455 /* FX100 :: Control1 :: disable_rx_qual [05:05] */ 34456 #define FX100_CONTROL1_DISABLE_RX_QUAL_MASK 0x0020 34457 #define FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN 0 34458 #define FX100_CONTROL1_DISABLE_RX_QUAL_BITS 1 34459 #define FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT 5 34460 34461 /* FX100 :: Control1 :: force_rx_qual [04:04] */ 34462 #define FX100_CONTROL1_FORCE_RX_QUAL_MASK 0x0010 34463 #define FX100_CONTROL1_FORCE_RX_QUAL_ALIGN 0 34464 #define FX100_CONTROL1_FORCE_RX_QUAL_BITS 1 34465 #define FX100_CONTROL1_FORCE_RX_QUAL_SHIFT 4 34466 34467 /* FX100 :: Control1 :: far_end_fault_en [03:03] */ 34468 #define FX100_CONTROL1_FAR_END_FAULT_EN_MASK 0x0008 34469 #define FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN 0 34470 #define FX100_CONTROL1_FAR_END_FAULT_EN_BITS 1 34471 #define FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT 3 34472 34473 /* FX100 :: Control1 :: autodet_en [02:02] */ 34474 #define FX100_CONTROL1_AUTODET_EN_MASK 0x0004 34475 #define FX100_CONTROL1_AUTODET_EN_ALIGN 0 34476 #define FX100_CONTROL1_AUTODET_EN_BITS 1 34477 #define FX100_CONTROL1_AUTODET_EN_SHIFT 2 34478 34479 /* FX100 :: Control1 :: full_duplex [01:01] */ 34480 #define FX100_CONTROL1_FULL_DUPLEX_MASK 0x0002 34481 #define FX100_CONTROL1_FULL_DUPLEX_ALIGN 0 34482 #define FX100_CONTROL1_FULL_DUPLEX_BITS 1 34483 #define FX100_CONTROL1_FULL_DUPLEX_SHIFT 1 34484 34485 /* FX100 :: Control1 :: enable [00:00] */ 34486 #define FX100_CONTROL1_ENABLE_MASK 0x0001 34487 #define FX100_CONTROL1_ENABLE_ALIGN 0 34488 #define FX100_CONTROL1_ENABLE_BITS 1 34489 #define FX100_CONTROL1_ENABLE_SHIFT 0 34490 34491 34492 /**************************************************************************** 34493 * FX100 :: Control2 34494 */ 34495 /* FX100 :: Control2 :: reserved0 [15:12] */ 34496 #define FX100_CONTROL2_RESERVED0_MASK 0xf000 34497 #define FX100_CONTROL2_RESERVED0_ALIGN 0 34498 #define FX100_CONTROL2_RESERVED0_BITS 4 34499 #define FX100_CONTROL2_RESERVED0_SHIFT 12 34500 34501 /* FX100 :: Control2 :: ping_pong_disable [11:11] */ 34502 #define FX100_CONTROL2_PING_PONG_DISABLE_MASK 0x0800 34503 #define FX100_CONTROL2_PING_PONG_DISABLE_ALIGN 0 34504 #define FX100_CONTROL2_PING_PONG_DISABLE_BITS 1 34505 #define FX100_CONTROL2_PING_PONG_DISABLE_SHIFT 11 34506 34507 /* FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */ 34508 #define FX100_CONTROL2_PLL_CLK125_SW_REF_MASK 0x0400 34509 #define FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN 0 34510 #define FX100_CONTROL2_PLL_CLK125_SW_REF_BITS 1 34511 #define FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT 10 34512 34513 /* FX100 :: Control2 :: pll_clk125_sw_en [09:09] */ 34514 #define FX100_CONTROL2_PLL_CLK125_SW_EN_MASK 0x0200 34515 #define FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN 0 34516 #define FX100_CONTROL2_PLL_CLK125_SW_EN_BITS 1 34517 #define FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT 9 34518 34519 /* FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */ 34520 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK 0x0100 34521 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN 0 34522 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS 1 34523 #define FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT 8 34524 34525 /* FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */ 34526 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK 0x0080 34527 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN 0 34528 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS 1 34529 #define FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT 7 34530 34531 /* FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */ 34532 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK 0x0040 34533 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN 0 34534 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS 1 34535 #define FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT 6 34536 34537 /* FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */ 34538 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK 0x0020 34539 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN 0 34540 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS 1 34541 #define FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT 5 34542 34543 /* FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */ 34544 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK 0x0010 34545 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN 0 34546 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS 1 34547 #define FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT 4 34548 34549 /* FX100 :: Control2 :: mode_chg_nrst [03:03] */ 34550 #define FX100_CONTROL2_MODE_CHG_NRST_MASK 0x0008 34551 #define FX100_CONTROL2_MODE_CHG_NRST_ALIGN 0 34552 #define FX100_CONTROL2_MODE_CHG_NRST_BITS 1 34553 #define FX100_CONTROL2_MODE_CHG_NRST_SHIFT 3 34554 34555 /* FX100 :: Control2 :: reset_rxfifo [02:02] */ 34556 #define FX100_CONTROL2_RESET_RXFIFO_MASK 0x0004 34557 #define FX100_CONTROL2_RESET_RXFIFO_ALIGN 0 34558 #define FX100_CONTROL2_RESET_RXFIFO_BITS 1 34559 #define FX100_CONTROL2_RESET_RXFIFO_SHIFT 2 34560 34561 /* FX100 :: Control2 :: bypass_rxfifo [01:01] */ 34562 #define FX100_CONTROL2_BYPASS_RXFIFO_MASK 0x0002 34563 #define FX100_CONTROL2_BYPASS_RXFIFO_ALIGN 0 34564 #define FX100_CONTROL2_BYPASS_RXFIFO_BITS 1 34565 #define FX100_CONTROL2_BYPASS_RXFIFO_SHIFT 1 34566 34567 /* FX100 :: Control2 :: extend_pkt_size [00:00] */ 34568 #define FX100_CONTROL2_EXTEND_PKT_SIZE_MASK 0x0001 34569 #define FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN 0 34570 #define FX100_CONTROL2_EXTEND_PKT_SIZE_BITS 1 34571 #define FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT 0 34572 34573 34574 /**************************************************************************** 34575 * FX100 :: Control3 34576 */ 34577 /* FX100 :: Control3 :: number_of_idle [15:08] */ 34578 #define FX100_CONTROL3_NUMBER_OF_IDLE_MASK 0xff00 34579 #define FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN 0 34580 #define FX100_CONTROL3_NUMBER_OF_IDLE_BITS 8 34581 #define FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT 8 34582 34583 /* FX100 :: Control3 :: correlator_disable [07:07] */ 34584 #define FX100_CONTROL3_CORRELATOR_DISABLE_MASK 0x0080 34585 #define FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN 0 34586 #define FX100_CONTROL3_CORRELATOR_DISABLE_BITS 1 34587 #define FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT 7 34588 34589 /* FX100 :: Control3 :: bypass_nrz [06:06] */ 34590 #define FX100_CONTROL3_BYPASS_NRZ_MASK 0x0040 34591 #define FX100_CONTROL3_BYPASS_NRZ_ALIGN 0 34592 #define FX100_CONTROL3_BYPASS_NRZ_BITS 1 34593 #define FX100_CONTROL3_BYPASS_NRZ_SHIFT 6 34594 34595 /* FX100 :: Control3 :: bypass_encoder [05:05] */ 34596 #define FX100_CONTROL3_BYPASS_ENCODER_MASK 0x0020 34597 #define FX100_CONTROL3_BYPASS_ENCODER_ALIGN 0 34598 #define FX100_CONTROL3_BYPASS_ENCODER_BITS 1 34599 #define FX100_CONTROL3_BYPASS_ENCODER_SHIFT 5 34600 34601 /* FX100 :: Control3 :: bypass_alignment [04:04] */ 34602 #define FX100_CONTROL3_BYPASS_ALIGNMENT_MASK 0x0010 34603 #define FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN 0 34604 #define FX100_CONTROL3_BYPASS_ALIGNMENT_BITS 1 34605 #define FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT 4 34606 34607 /* FX100 :: Control3 :: force_link [03:03] */ 34608 #define FX100_CONTROL3_FORCE_LINK_MASK 0x0008 34609 #define FX100_CONTROL3_FORCE_LINK_ALIGN 0 34610 #define FX100_CONTROL3_FORCE_LINK_BITS 1 34611 #define FX100_CONTROL3_FORCE_LINK_SHIFT 3 34612 34613 /* FX100 :: Control3 :: force_lock [02:02] */ 34614 #define FX100_CONTROL3_FORCE_LOCK_MASK 0x0004 34615 #define FX100_CONTROL3_FORCE_LOCK_ALIGN 0 34616 #define FX100_CONTROL3_FORCE_LOCK_BITS 1 34617 #define FX100_CONTROL3_FORCE_LOCK_SHIFT 2 34618 34619 /* FX100 :: Control3 :: fast_unlock_timer [01:01] */ 34620 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK 0x0002 34621 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN 0 34622 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS 1 34623 #define FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT 1 34624 34625 /* FX100 :: Control3 :: fast_timers [00:00] */ 34626 #define FX100_CONTROL3_FAST_TIMERS_MASK 0x0001 34627 #define FX100_CONTROL3_FAST_TIMERS_ALIGN 0 34628 #define FX100_CONTROL3_FAST_TIMERS_BITS 1 34629 #define FX100_CONTROL3_FAST_TIMERS_SHIFT 0 34630 34631 34632 /**************************************************************************** 34633 * FX100 :: Status1 34634 */ 34635 /* FX100 :: Status1 :: mode_change [15:15] */ 34636 #define FX100_STATUS1_MODE_CHANGE_MASK 0x8000 34637 #define FX100_STATUS1_MODE_CHANGE_ALIGN 0 34638 #define FX100_STATUS1_MODE_CHANGE_BITS 1 34639 #define FX100_STATUS1_MODE_CHANGE_SHIFT 15 34640 34641 /* FX100 :: Status1 :: reserved0 [14:12] */ 34642 #define FX100_STATUS1_RESERVED0_MASK 0x7000 34643 #define FX100_STATUS1_RESERVED0_ALIGN 0 34644 #define FX100_STATUS1_RESERVED0_BITS 3 34645 #define FX100_STATUS1_RESERVED0_SHIFT 12 34646 34647 /* FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */ 34648 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK 0x0800 34649 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN 0 34650 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS 1 34651 #define FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT 11 34652 34653 /* FX100 :: Status1 :: fiber_pwrdwn [10:10] */ 34654 #define FX100_STATUS1_FIBER_PWRDWN_MASK 0x0400 34655 #define FX100_STATUS1_FIBER_PWRDWN_ALIGN 0 34656 #define FX100_STATUS1_FIBER_PWRDWN_BITS 1 34657 #define FX100_STATUS1_FIBER_PWRDWN_SHIFT 10 34658 34659 /* FX100 :: Status1 :: link_status_chg [09:09] */ 34660 #define FX100_STATUS1_LINK_STATUS_CHG_MASK 0x0200 34661 #define FX100_STATUS1_LINK_STATUS_CHG_ALIGN 0 34662 #define FX100_STATUS1_LINK_STATUS_CHG_BITS 1 34663 #define FX100_STATUS1_LINK_STATUS_CHG_SHIFT 9 34664 34665 /* FX100 :: Status1 :: bad_esd_detected [08:08] */ 34666 #define FX100_STATUS1_BAD_ESD_DETECTED_MASK 0x0100 34667 #define FX100_STATUS1_BAD_ESD_DETECTED_ALIGN 0 34668 #define FX100_STATUS1_BAD_ESD_DETECTED_BITS 1 34669 #define FX100_STATUS1_BAD_ESD_DETECTED_SHIFT 8 34670 34671 /* FX100 :: Status1 :: false_carrier_detected [07:07] */ 34672 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK 0x0080 34673 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN 0 34674 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS 1 34675 #define FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT 7 34676 34677 /* FX100 :: Status1 :: tx_err_detected [06:06] */ 34678 #define FX100_STATUS1_TX_ERR_DETECTED_MASK 0x0040 34679 #define FX100_STATUS1_TX_ERR_DETECTED_ALIGN 0 34680 #define FX100_STATUS1_TX_ERR_DETECTED_BITS 1 34681 #define FX100_STATUS1_TX_ERR_DETECTED_SHIFT 6 34682 34683 /* FX100 :: Status1 :: rx_err_detected [05:05] */ 34684 #define FX100_STATUS1_RX_ERR_DETECTED_MASK 0x0020 34685 #define FX100_STATUS1_RX_ERR_DETECTED_ALIGN 0 34686 #define FX100_STATUS1_RX_ERR_DETECTED_BITS 1 34687 #define FX100_STATUS1_RX_ERR_DETECTED_SHIFT 5 34688 34689 /* FX100 :: Status1 :: lock_timer_expired [04:04] */ 34690 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK 0x0010 34691 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN 0 34692 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS 1 34693 #define FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT 4 34694 34695 /* FX100 :: Status1 :: lost_lock [03:03] */ 34696 #define FX100_STATUS1_LOST_LOCK_MASK 0x0008 34697 #define FX100_STATUS1_LOST_LOCK_ALIGN 0 34698 #define FX100_STATUS1_LOST_LOCK_BITS 1 34699 #define FX100_STATUS1_LOST_LOCK_SHIFT 3 34700 34701 /* FX100 :: Status1 :: faulting [02:02] */ 34702 #define FX100_STATUS1_FAULTING_MASK 0x0004 34703 #define FX100_STATUS1_FAULTING_ALIGN 0 34704 #define FX100_STATUS1_FAULTING_BITS 1 34705 #define FX100_STATUS1_FAULTING_SHIFT 2 34706 34707 /* FX100 :: Status1 :: locked [01:01] */ 34708 #define FX100_STATUS1_LOCKED_MASK 0x0002 34709 #define FX100_STATUS1_LOCKED_ALIGN 0 34710 #define FX100_STATUS1_LOCKED_BITS 1 34711 #define FX100_STATUS1_LOCKED_SHIFT 1 34712 34713 /* FX100 :: Status1 :: link [00:00] */ 34714 #define FX100_STATUS1_LINK_MASK 0x0001 34715 #define FX100_STATUS1_LINK_ALIGN 0 34716 #define FX100_STATUS1_LINK_BITS 1 34717 #define FX100_STATUS1_LINK_SHIFT 0 34718 34719 34720 /**************************************************************************** 34721 * FX100 :: Status3 34722 */ 34723 /* FX100 :: Status3 :: linkmon_cntr [15:08] */ 34724 #define FX100_STATUS3_LINKMON_CNTR_MASK 0xff00 34725 #define FX100_STATUS3_LINKMON_CNTR_ALIGN 0 34726 #define FX100_STATUS3_LINKMON_CNTR_BITS 8 34727 #define FX100_STATUS3_LINKMON_CNTR_SHIFT 8 34728 34729 /* FX100 :: Status3 :: reserved0 [07:07] */ 34730 #define FX100_STATUS3_RESERVED0_MASK 0x0080 34731 #define FX100_STATUS3_RESERVED0_ALIGN 0 34732 #define FX100_STATUS3_RESERVED0_BITS 1 34733 #define FX100_STATUS3_RESERVED0_SHIFT 7 34734 34735 /* FX100 :: Status3 :: idles_detected_5b [06:06] */ 34736 #define FX100_STATUS3_IDLES_DETECTED_5B_MASK 0x0040 34737 #define FX100_STATUS3_IDLES_DETECTED_5B_ALIGN 0 34738 #define FX100_STATUS3_IDLES_DETECTED_5B_BITS 1 34739 #define FX100_STATUS3_IDLES_DETECTED_5B_SHIFT 6 34740 34741 /* FX100 :: Status3 :: crs_ind_detected [05:05] */ 34742 #define FX100_STATUS3_CRS_IND_DETECTED_MASK 0x0020 34743 #define FX100_STATUS3_CRS_IND_DETECTED_ALIGN 0 34744 #define FX100_STATUS3_CRS_IND_DETECTED_BITS 1 34745 #define FX100_STATUS3_CRS_IND_DETECTED_SHIFT 5 34746 34747 /* FX100 :: Status3 :: err_detected [04:04] */ 34748 #define FX100_STATUS3_ERR_DETECTED_MASK 0x0010 34749 #define FX100_STATUS3_ERR_DETECTED_ALIGN 0 34750 #define FX100_STATUS3_ERR_DETECTED_BITS 1 34751 #define FX100_STATUS3_ERR_DETECTED_SHIFT 4 34752 34753 /* FX100 :: Status3 :: esd_detected [03:03] */ 34754 #define FX100_STATUS3_ESD_DETECTED_MASK 0x0008 34755 #define FX100_STATUS3_ESD_DETECTED_ALIGN 0 34756 #define FX100_STATUS3_ESD_DETECTED_BITS 1 34757 #define FX100_STATUS3_ESD_DETECTED_SHIFT 3 34758 34759 /* FX100 :: Status3 :: ssd_detected [02:02] */ 34760 #define FX100_STATUS3_SSD_DETECTED_MASK 0x0004 34761 #define FX100_STATUS3_SSD_DETECTED_ALIGN 0 34762 #define FX100_STATUS3_SSD_DETECTED_BITS 1 34763 #define FX100_STATUS3_SSD_DETECTED_SHIFT 2 34764 34765 /* FX100 :: Status3 :: ij_detected [01:01] */ 34766 #define FX100_STATUS3_IJ_DETECTED_MASK 0x0002 34767 #define FX100_STATUS3_IJ_DETECTED_ALIGN 0 34768 #define FX100_STATUS3_IJ_DETECTED_BITS 1 34769 #define FX100_STATUS3_IJ_DETECTED_SHIFT 1 34770 34771 /* FX100 :: Status3 :: idles_detected [00:00] */ 34772 #define FX100_STATUS3_IDLES_DETECTED_MASK 0x0001 34773 #define FX100_STATUS3_IDLES_DETECTED_ALIGN 0 34774 #define FX100_STATUS3_IDLES_DETECTED_BITS 1 34775 #define FX100_STATUS3_IDLES_DETECTED_SHIFT 0 34776 34777 34778 /**************************************************************************** 34779 * FX100 :: Status4 34780 */ 34781 /* FX100 :: Status4 :: reserved0 [15:15] */ 34782 #define FX100_STATUS4_RESERVED0_MASK 0x8000 34783 #define FX100_STATUS4_RESERVED0_ALIGN 0 34784 #define FX100_STATUS4_RESERVED0_BITS 1 34785 #define FX100_STATUS4_RESERVED0_SHIFT 15 34786 34787 /* FX100 :: Status4 :: rx_badend [14:14] */ 34788 #define FX100_STATUS4_RX_BADEND_MASK 0x4000 34789 #define FX100_STATUS4_RX_BADEND_ALIGN 0 34790 #define FX100_STATUS4_RX_BADEND_BITS 1 34791 #define FX100_STATUS4_RX_BADEND_SHIFT 14 34792 34793 /* FX100 :: Status4 :: rx_data [13:13] */ 34794 #define FX100_STATUS4_RX_DATA_MASK 0x2000 34795 #define FX100_STATUS4_RX_DATA_ALIGN 0 34796 #define FX100_STATUS4_RX_DATA_BITS 1 34797 #define FX100_STATUS4_RX_DATA_SHIFT 13 34798 34799 /* FX100 :: Status4 :: rx_ssk [12:12] */ 34800 #define FX100_STATUS4_RX_SSK_MASK 0x1000 34801 #define FX100_STATUS4_RX_SSK_ALIGN 0 34802 #define FX100_STATUS4_RX_SSK_BITS 1 34803 #define FX100_STATUS4_RX_SSK_SHIFT 12 34804 34805 /* FX100 :: Status4 :: rx_ssj [11:11] */ 34806 #define FX100_STATUS4_RX_SSJ_MASK 0x0800 34807 #define FX100_STATUS4_RX_SSJ_ALIGN 0 34808 #define FX100_STATUS4_RX_SSJ_BITS 1 34809 #define FX100_STATUS4_RX_SSJ_SHIFT 11 34810 34811 /* FX100 :: Status4 :: rx_confirmk [10:10] */ 34812 #define FX100_STATUS4_RX_CONFIRMK_MASK 0x0400 34813 #define FX100_STATUS4_RX_CONFIRMK_ALIGN 0 34814 #define FX100_STATUS4_RX_CONFIRMK_BITS 1 34815 #define FX100_STATUS4_RX_CONFIRMK_SHIFT 10 34816 34817 /* FX100 :: Status4 :: rx_badssd [09:09] */ 34818 #define FX100_STATUS4_RX_BADSSD_MASK 0x0200 34819 #define FX100_STATUS4_RX_BADSSD_ALIGN 0 34820 #define FX100_STATUS4_RX_BADSSD_BITS 1 34821 #define FX100_STATUS4_RX_BADSSD_SHIFT 9 34822 34823 /* FX100 :: Status4 :: fx_linkfail [08:08] */ 34824 #define FX100_STATUS4_FX_LINKFAIL_MASK 0x0100 34825 #define FX100_STATUS4_FX_LINKFAIL_ALIGN 0 34826 #define FX100_STATUS4_FX_LINKFAIL_BITS 1 34827 #define FX100_STATUS4_FX_LINKFAIL_SHIFT 8 34828 34829 /* FX100 :: Status4 :: tx_esr [07:07] */ 34830 #define FX100_STATUS4_TX_ESR_MASK 0x0080 34831 #define FX100_STATUS4_TX_ESR_ALIGN 0 34832 #define FX100_STATUS4_TX_ESR_BITS 1 34833 #define FX100_STATUS4_TX_ESR_SHIFT 7 34834 34835 /* FX100 :: Status4 :: tx_est [06:06] */ 34836 #define FX100_STATUS4_TX_EST_MASK 0x0040 34837 #define FX100_STATUS4_TX_EST_ALIGN 0 34838 #define FX100_STATUS4_TX_EST_BITS 1 34839 #define FX100_STATUS4_TX_EST_SHIFT 6 34840 34841 /* FX100 :: Status4 :: tx_terror [05:05] */ 34842 #define FX100_STATUS4_TX_TERROR_MASK 0x0020 34843 #define FX100_STATUS4_TX_TERROR_ALIGN 0 34844 #define FX100_STATUS4_TX_TERROR_BITS 1 34845 #define FX100_STATUS4_TX_TERROR_SHIFT 5 34846 34847 /* FX100 :: Status4 :: tx_tdata [04:04] */ 34848 #define FX100_STATUS4_TX_TDATA_MASK 0x0010 34849 #define FX100_STATUS4_TX_TDATA_ALIGN 0 34850 #define FX100_STATUS4_TX_TDATA_BITS 1 34851 #define FX100_STATUS4_TX_TDATA_SHIFT 4 34852 34853 /* FX100 :: Status4 :: tx_ssk [03:03] */ 34854 #define FX100_STATUS4_TX_SSK_MASK 0x0008 34855 #define FX100_STATUS4_TX_SSK_ALIGN 0 34856 #define FX100_STATUS4_TX_SSK_BITS 1 34857 #define FX100_STATUS4_TX_SSK_SHIFT 3 34858 34859 /* FX100 :: Status4 :: tx_sek [02:02] */ 34860 #define FX100_STATUS4_TX_SEK_MASK 0x0004 34861 #define FX100_STATUS4_TX_SEK_ALIGN 0 34862 #define FX100_STATUS4_TX_SEK_BITS 1 34863 #define FX100_STATUS4_TX_SEK_SHIFT 2 34864 34865 /* FX100 :: Status4 :: tx_ssj [01:01] */ 34866 #define FX100_STATUS4_TX_SSJ_MASK 0x0002 34867 #define FX100_STATUS4_TX_SSJ_ALIGN 0 34868 #define FX100_STATUS4_TX_SSJ_BITS 1 34869 #define FX100_STATUS4_TX_SSJ_SHIFT 1 34870 34871 /* FX100 :: Status4 :: tx_sej [00:00] */ 34872 #define FX100_STATUS4_TX_SEJ_MASK 0x0001 34873 #define FX100_STATUS4_TX_SEJ_ALIGN 0 34874 #define FX100_STATUS4_TX_SEJ_BITS 1 34875 #define FX100_STATUS4_TX_SEJ_SHIFT 0 34876 34877 34878 /**************************************************************************** 34879 * Hypercore_USER_aerBlk 34880 */ 34881 /**************************************************************************** 34882 * aerBlk :: aer 34883 */ 34884 /* aerBlk :: aer :: MMD_deviceType [15:10] */ 34885 #define AERBLK_AER_MMD_DEVICETYPE_MASK 0xfc00 34886 #define AERBLK_AER_MMD_DEVICETYPE_ALIGN 0 34887 #define AERBLK_AER_MMD_DEVICETYPE_BITS 6 34888 #define AERBLK_AER_MMD_DEVICETYPE_SHIFT 10 34889 34890 /* aerBlk :: aer :: MMD_port [09:00] */ 34891 #define AERBLK_AER_MMD_PORT_MASK 0x03ff 34892 #define AERBLK_AER_MMD_PORT_ALIGN 0 34893 #define AERBLK_AER_MMD_PORT_BITS 10 34894 #define AERBLK_AER_MMD_PORT_SHIFT 0 34895 34896 34897 /**************************************************************************** 34898 * Hypercore_USER_Combo_IEEE0 34899 */ 34900 /**************************************************************************** 34901 * Combo_IEEE0 :: MIICntl 34902 */ 34903 /* Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */ 34904 #define COMBO_IEEE0_MIICNTL_RST_HW_MASK 0x8000 34905 #define COMBO_IEEE0_MIICNTL_RST_HW_ALIGN 0 34906 #define COMBO_IEEE0_MIICNTL_RST_HW_BITS 1 34907 #define COMBO_IEEE0_MIICNTL_RST_HW_SHIFT 15 34908 34909 /* Combo_IEEE0 :: MIICntl :: gloopback [14:14] */ 34910 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK 0x4000 34911 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN 0 34912 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS 1 34913 #define COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT 14 34914 34915 /* Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */ 34916 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK 0x2000 34917 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN 0 34918 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS 1 34919 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT 13 34920 34921 /* Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */ 34922 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK 0x1000 34923 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN 0 34924 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS 1 34925 #define COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT 12 34926 34927 /* Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */ 34928 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK 0x0800 34929 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN 0 34930 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS 1 34931 #define COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT 11 34932 34933 /* Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */ 34934 #define COMBO_IEEE0_MIICNTL_RESERVED0_MASK 0x0400 34935 #define COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN 0 34936 #define COMBO_IEEE0_MIICNTL_RESERVED0_BITS 1 34937 #define COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT 10 34938 34939 /* Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */ 34940 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK 0x0200 34941 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN 0 34942 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS 1 34943 #define COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT 9 34944 34945 /* Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */ 34946 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK 0x0100 34947 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN 0 34948 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS 1 34949 #define COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT 8 34950 34951 /* Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */ 34952 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK 0x0080 34953 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN 0 34954 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS 1 34955 #define COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT 7 34956 34957 /* Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */ 34958 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK 0x0040 34959 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN 0 34960 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS 1 34961 #define COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT 6 34962 34963 /* Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */ 34964 #define COMBO_IEEE0_MIICNTL_RESERVED1_MASK 0x003f 34965 #define COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN 0 34966 #define COMBO_IEEE0_MIICNTL_RESERVED1_BITS 6 34967 #define COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT 0 34968 34969 34970 /**************************************************************************** 34971 * Combo_IEEE0 :: MIIStat 34972 */ 34973 /* Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */ 34974 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK 0x8000 34975 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN 0 34976 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS 1 34977 #define COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT 15 34978 34979 /* Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */ 34980 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000 34981 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 34982 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 34983 #define COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14 34984 34985 /* Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */ 34986 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000 34987 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 34988 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 34989 #define COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13 34990 34991 /* Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */ 34992 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x1000 34993 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 34994 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 34995 #define COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12 34996 34997 /* Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */ 34998 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x0800 34999 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 35000 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 35001 #define COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11 35002 35003 /* Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */ 35004 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400 35005 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0 35006 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1 35007 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10 35008 35009 /* Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */ 35010 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200 35011 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0 35012 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1 35013 #define COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9 35014 35015 /* Combo_IEEE0 :: MIIStat :: extended_status [08:08] */ 35016 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK 0x0100 35017 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN 0 35018 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS 1 35019 #define COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT 8 35020 35021 /* Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */ 35022 #define COMBO_IEEE0_MIISTAT_RESERVED0_MASK 0x0080 35023 #define COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN 0 35024 #define COMBO_IEEE0_MIISTAT_RESERVED0_BITS 1 35025 #define COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT 7 35026 35027 /* Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */ 35028 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK 0x0040 35029 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN 0 35030 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS 1 35031 #define COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT 6 35032 35033 /* Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */ 35034 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK 0x0020 35035 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN 0 35036 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS 1 35037 #define COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT 5 35038 35039 /* Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */ 35040 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK 0x0010 35041 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN 0 35042 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS 1 35043 #define COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT 4 35044 35045 /* Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */ 35046 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK 0x0008 35047 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN 0 35048 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS 1 35049 #define COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT 3 35050 35051 /* Combo_IEEE0 :: MIIStat :: link_status [02:02] */ 35052 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK 0x0004 35053 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN 0 35054 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS 1 35055 #define COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT 2 35056 35057 /* Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */ 35058 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK 0x0002 35059 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN 0 35060 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS 1 35061 #define COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT 1 35062 35063 /* Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */ 35064 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK 0x0001 35065 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN 0 35066 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS 1 35067 #define COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT 0 35068 35069 35070 /**************************************************************************** 35071 * Combo_IEEE0 :: Id1 35072 */ 35073 /* Combo_IEEE0 :: Id1 :: regid [15:00] */ 35074 #define COMBO_IEEE0_ID1_REGID_MASK 0xffff 35075 #define COMBO_IEEE0_ID1_REGID_ALIGN 0 35076 #define COMBO_IEEE0_ID1_REGID_BITS 16 35077 #define COMBO_IEEE0_ID1_REGID_SHIFT 0 35078 35079 35080 /**************************************************************************** 35081 * Combo_IEEE0 :: Id2 35082 */ 35083 /* Combo_IEEE0 :: Id2 :: regid [15:00] */ 35084 #define COMBO_IEEE0_ID2_REGID_MASK 0xffff 35085 #define COMBO_IEEE0_ID2_REGID_ALIGN 0 35086 #define COMBO_IEEE0_ID2_REGID_BITS 16 35087 #define COMBO_IEEE0_ID2_REGID_SHIFT 0 35088 35089 35090 /**************************************************************************** 35091 * Combo_IEEE0 :: AutoNegAdv 35092 */ 35093 /* Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */ 35094 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK 0x8000 35095 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN 0 35096 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS 1 35097 #define COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT 15 35098 35099 /* Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */ 35100 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK 0x4000 35101 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN 0 35102 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS 1 35103 #define COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT 14 35104 35105 /* Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */ 35106 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK 0x3000 35107 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN 0 35108 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS 2 35109 #define COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT 12 35110 35111 /* Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */ 35112 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK 0x0e00 35113 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN 0 35114 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS 3 35115 #define COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT 9 35116 35117 /* Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */ 35118 #define COMBO_IEEE0_AUTONEGADV_PAUSE_MASK 0x0180 35119 #define COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN 0 35120 #define COMBO_IEEE0_AUTONEGADV_PAUSE_BITS 2 35121 #define COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT 7 35122 35123 /* Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */ 35124 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK 0x0040 35125 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN 0 35126 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS 1 35127 #define COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT 6 35128 35129 /* Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */ 35130 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK 0x0020 35131 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN 0 35132 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS 1 35133 #define COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT 5 35134 35135 /* Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */ 35136 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK 0x001f 35137 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN 0 35138 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS 5 35139 #define COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT 0 35140 35141 35142 /**************************************************************************** 35143 * Combo_IEEE0 :: AutoNegLPAbil 35144 */ 35145 /* Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */ 35146 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK 0x8000 35147 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN 0 35148 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS 1 35149 #define COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT 15 35150 35151 /* Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */ 35152 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK 0x4000 35153 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN 0 35154 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS 1 35155 #define COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT 14 35156 35157 /* Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */ 35158 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK 0x3000 35159 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN 0 35160 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS 2 35161 #define COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT 12 35162 35163 /* Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */ 35164 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK 0x0e00 35165 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN 0 35166 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS 3 35167 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT 9 35168 35169 /* Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */ 35170 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK 0x0180 35171 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN 0 35172 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS 2 35173 #define COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT 7 35174 35175 /* Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */ 35176 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK 0x0040 35177 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN 0 35178 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS 1 35179 #define COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT 6 35180 35181 /* Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */ 35182 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK 0x0020 35183 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN 0 35184 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS 1 35185 #define COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT 5 35186 35187 /* Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */ 35188 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK 0x001e 35189 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN 0 35190 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS 4 35191 #define COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT 1 35192 35193 /* Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */ 35194 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK 0x0001 35195 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN 0 35196 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS 1 35197 #define COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT 0 35198 35199 35200 /**************************************************************************** 35201 * Combo_IEEE0 :: AutoNegExp 35202 */ 35203 /* Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */ 35204 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK 0xfff8 35205 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN 0 35206 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS 13 35207 #define COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT 3 35208 35209 /* Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */ 35210 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK 0x0004 35211 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN 0 35212 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS 1 35213 #define COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT 2 35214 35215 /* Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */ 35216 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK 0x0002 35217 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN 0 35218 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS 1 35219 #define COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT 1 35220 35221 /* Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */ 35222 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK 0x0001 35223 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN 0 35224 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS 1 35225 #define COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT 0 35226 35227 35228 /**************************************************************************** 35229 * Combo_IEEE0 :: AutoNegNP 35230 */ 35231 /* Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */ 35232 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK 0x8000 35233 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN 0 35234 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS 1 35235 #define COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT 15 35236 35237 /* Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */ 35238 #define COMBO_IEEE0_AUTONEGNP_ACK_MASK 0x4000 35239 #define COMBO_IEEE0_AUTONEGNP_ACK_ALIGN 0 35240 #define COMBO_IEEE0_AUTONEGNP_ACK_BITS 1 35241 #define COMBO_IEEE0_AUTONEGNP_ACK_SHIFT 14 35242 35243 /* Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */ 35244 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK 0x2000 35245 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN 0 35246 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS 1 35247 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT 13 35248 35249 /* Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */ 35250 #define COMBO_IEEE0_AUTONEGNP_ACK2_MASK 0x1000 35251 #define COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN 0 35252 #define COMBO_IEEE0_AUTONEGNP_ACK2_BITS 1 35253 #define COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT 12 35254 35255 /* Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */ 35256 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK 0x0800 35257 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN 0 35258 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS 1 35259 #define COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT 11 35260 35261 /* Combo_IEEE0 :: AutoNegNP :: Message [10:00] */ 35262 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK 0x07ff 35263 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN 0 35264 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS 11 35265 #define COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT 0 35266 35267 35268 /**************************************************************************** 35269 * Combo_IEEE0 :: AutoNegLPAbil2 35270 */ 35271 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */ 35272 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK 0x8000 35273 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN 0 35274 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS 1 35275 #define COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT 15 35276 35277 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */ 35278 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK 0x4000 35279 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN 0 35280 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS 1 35281 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT 14 35282 35283 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */ 35284 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK 0x2000 35285 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN 0 35286 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS 1 35287 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT 13 35288 35289 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */ 35290 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK 0x1000 35291 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN 0 35292 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS 1 35293 #define COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT 12 35294 35295 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */ 35296 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK 0x0800 35297 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN 0 35298 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS 1 35299 #define COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT 11 35300 35301 /* Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */ 35302 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK 0x07ff 35303 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN 0 35304 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS 11 35305 #define COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT 0 35306 35307 35308 /**************************************************************************** 35309 * Combo_IEEE0 :: MIIextStat 35310 */ 35311 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */ 35312 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000 35313 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0 35314 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1 35315 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15 35316 35317 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */ 35318 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000 35319 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0 35320 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1 35321 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14 35322 35323 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */ 35324 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000 35325 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0 35326 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1 35327 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13 35328 35329 /* Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */ 35330 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000 35331 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0 35332 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1 35333 #define COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12 35334 35335 /* Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */ 35336 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK 0x0fff 35337 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN 0 35338 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS 12 35339 #define COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT 0 35340 35341 35342 /**************************************************************************** 35343 * Hypercore_IEEE_PMD_PMD_ieee0Blk 35344 */ 35345 /**************************************************************************** 35346 * PMD_ieee0Blk :: PMD_ieeeControl1 35347 */ 35348 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: rst_sw [15:15] */ 35349 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_MASK 0x8000 35350 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_ALIGN 0 35351 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_BITS 1 35352 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RST_SW_SHIFT 15 35353 35354 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved0 [14:14] */ 35355 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_MASK 0x4000 35356 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_ALIGN 0 35357 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_BITS 1 35358 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED0_SHIFT 14 35359 35360 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection0 [13:13] */ 35361 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_MASK 0x2000 35362 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_ALIGN 0 35363 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_BITS 1 35364 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION0_SHIFT 13 35365 35366 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved1 [12:12] */ 35367 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_MASK 0x1000 35368 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_ALIGN 0 35369 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_BITS 1 35370 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED1_SHIFT 12 35371 35372 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: pwrdwn_sw_10g [11:11] */ 35373 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_MASK 0x0800 35374 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_ALIGN 0 35375 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_BITS 1 35376 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_PWRDWN_SW_10G_SHIFT 11 35377 35378 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved2 [10:07] */ 35379 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_MASK 0x0780 35380 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_ALIGN 0 35381 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_BITS 4 35382 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED2_SHIFT 7 35383 35384 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection1 [06:06] */ 35385 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_MASK 0x0040 35386 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_ALIGN 0 35387 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_BITS 1 35388 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION1_SHIFT 6 35389 35390 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: SpeedSelection2 [05:02] */ 35391 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_MASK 0x003c 35392 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_ALIGN 0 35393 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_BITS 4 35394 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_SPEEDSELECTION2_SHIFT 2 35395 35396 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: reserved3 [01:01] */ 35397 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_MASK 0x0002 35398 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_ALIGN 0 35399 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_BITS 1 35400 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_RESERVED3_SHIFT 1 35401 35402 /* PMD_ieee0Blk :: PMD_ieeeControl1 :: gloop10g [00:00] */ 35403 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_MASK 0x0001 35404 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_ALIGN 0 35405 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_BITS 1 35406 #define PMD_IEEE0BLK_PMD_IEEECONTROL1_GLOOP10G_SHIFT 0 35407 35408 35409 /**************************************************************************** 35410 * PMD_ieee0Blk :: PMD_ieeeStatus1 35411 */ 35412 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved0 [15:08] */ 35413 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_MASK 0xff00 35414 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_ALIGN 0 35415 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_BITS 8 35416 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED0_SHIFT 8 35417 35418 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: Fault [07:07] */ 35419 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_MASK 0x0080 35420 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_ALIGN 0 35421 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_BITS 1 35422 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_FAULT_SHIFT 7 35423 35424 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved1 [06:03] */ 35425 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_MASK 0x0078 35426 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_ALIGN 0 35427 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_BITS 4 35428 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED1_SHIFT 3 35429 35430 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: Rx_linkStatus [02:02] */ 35431 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_MASK 0x0004 35432 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_ALIGN 0 35433 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_BITS 1 35434 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RX_LINKSTATUS_SHIFT 2 35435 35436 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: lowPoerwAbility [01:01] */ 35437 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_MASK 0x0002 35438 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_ALIGN 0 35439 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_BITS 1 35440 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_LOWPOERWABILITY_SHIFT 1 35441 35442 /* PMD_ieee0Blk :: PMD_ieeeStatus1 :: reserved2 [00:00] */ 35443 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_MASK 0x0001 35444 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_ALIGN 0 35445 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_BITS 1 35446 #define PMD_IEEE0BLK_PMD_IEEESTATUS1_RESERVED2_SHIFT 0 35447 35448 35449 /**************************************************************************** 35450 * PMD_ieee0Blk :: PMD_ieeeId1 35451 */ 35452 /* PMD_ieee0Blk :: PMD_ieeeId1 :: IEEEID1 [15:00] */ 35453 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_MASK 0xffff 35454 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_ALIGN 0 35455 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_BITS 16 35456 #define PMD_IEEE0BLK_PMD_IEEEID1_IEEEID1_SHIFT 0 35457 35458 35459 /**************************************************************************** 35460 * PMD_ieee0Blk :: PMD_ieeeId2 35461 */ 35462 /* PMD_ieee0Blk :: PMD_ieeeId2 :: IEEEID2 [15:00] */ 35463 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_MASK 0xffff 35464 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_ALIGN 0 35465 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_BITS 16 35466 #define PMD_IEEE0BLK_PMD_IEEEID2_IEEEID2_SHIFT 0 35467 35468 35469 /**************************************************************************** 35470 * PMD_ieee0Blk :: PMD_ieeeSpeedAbility 35471 */ 35472 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: reserved0 [15:07] */ 35473 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_MASK 0xff80 35474 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_ALIGN 0 35475 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_BITS 9 35476 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED0_SHIFT 7 35477 35478 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10M [06:06] */ 35479 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_MASK 0x0040 35480 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_ALIGN 0 35481 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_BITS 1 35482 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10M_SHIFT 6 35483 35484 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed100M [05:05] */ 35485 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_MASK 0x0020 35486 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_ALIGN 0 35487 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_BITS 1 35488 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED100M_SHIFT 5 35489 35490 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed1000B [04:04] */ 35491 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_MASK 0x0010 35492 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_ALIGN 0 35493 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_BITS 1 35494 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED1000B_SHIFT 4 35495 35496 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: reserved1 [03:03] */ 35497 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_MASK 0x0008 35498 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_ALIGN 0 35499 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_BITS 1 35500 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_RESERVED1_SHIFT 3 35501 35502 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10PASS_TS [02:02] */ 35503 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_MASK 0x0004 35504 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_ALIGN 0 35505 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_BITS 1 35506 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10PASS_TS_SHIFT 2 35507 35508 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed2BASE_TL [01:01] */ 35509 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_MASK 0x0002 35510 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_ALIGN 0 35511 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_BITS 1 35512 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED2BASE_TL_SHIFT 1 35513 35514 /* PMD_ieee0Blk :: PMD_ieeeSpeedAbility :: speed10G [00:00] */ 35515 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_MASK 0x0001 35516 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_ALIGN 0 35517 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_BITS 1 35518 #define PMD_IEEE0BLK_PMD_IEEESPEEDABILITY_SPEED10G_SHIFT 0 35519 35520 35521 /**************************************************************************** 35522 * PMD_ieee0Blk :: PMD_ieeeDevInPkg2 35523 */ 35524 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: Vendor2 [15:15] */ 35525 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR2_MASK 0x8000 35526 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR2_ALIGN 0 35527 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR2_BITS 1 35528 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR2_SHIFT 15 35529 35530 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: Vendor1 [14:14] */ 35531 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR1_MASK 0x4000 35532 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR1_ALIGN 0 35533 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR1_BITS 1 35534 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_VENDOR1_SHIFT 14 35535 35536 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: CL22ext [13:13] */ 35537 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CL22EXT_MASK 0x2000 35538 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CL22EXT_ALIGN 0 35539 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CL22EXT_BITS 1 35540 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_CL22EXT_SHIFT 13 35541 35542 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg2 :: reserved0 [12:00] */ 35543 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_MASK 0x1fff 35544 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_ALIGN 0 35545 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_BITS 13 35546 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG2_RESERVED0_SHIFT 0 35547 35548 35549 /**************************************************************************** 35550 * PMD_ieee0Blk :: PMD_ieeeDevInPkg1 35551 */ 35552 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: reserved0 [15:08] */ 35553 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_MASK 0xff00 35554 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_ALIGN 0 35555 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_BITS 8 35556 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_RESERVED0_SHIFT 8 35557 35558 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: AN [07:07] */ 35559 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_AN_MASK 0x0080 35560 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_AN_ALIGN 0 35561 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_AN_BITS 1 35562 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_AN_SHIFT 7 35563 35564 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: TC [06:06] */ 35565 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_TC_MASK 0x0040 35566 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_TC_ALIGN 0 35567 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_TC_BITS 1 35568 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_TC_SHIFT 6 35569 35570 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: DTE_XS [05:05] */ 35571 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_DTE_XS_MASK 0x0020 35572 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_DTE_XS_ALIGN 0 35573 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_DTE_XS_BITS 1 35574 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_DTE_XS_SHIFT 5 35575 35576 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: PHY_XS [04:04] */ 35577 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PHY_XS_MASK 0x0010 35578 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PHY_XS_ALIGN 0 35579 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PHY_XS_BITS 1 35580 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PHY_XS_SHIFT 4 35581 35582 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: PCS_XS [03:03] */ 35583 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PCS_XS_MASK 0x0008 35584 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PCS_XS_ALIGN 0 35585 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PCS_XS_BITS 1 35586 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PCS_XS_SHIFT 3 35587 35588 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: WIS [02:02] */ 35589 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_WIS_MASK 0x0004 35590 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_WIS_ALIGN 0 35591 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_WIS_BITS 1 35592 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_WIS_SHIFT 2 35593 35594 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: PMA_PMD [01:01] */ 35595 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PMA_PMD_MASK 0x0002 35596 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PMA_PMD_ALIGN 0 35597 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PMA_PMD_BITS 1 35598 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_PMA_PMD_SHIFT 1 35599 35600 /* PMD_ieee0Blk :: PMD_ieeeDevInPkg1 :: Clause22 [00:00] */ 35601 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CLAUSE22_MASK 0x0001 35602 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CLAUSE22_ALIGN 0 35603 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CLAUSE22_BITS 1 35604 #define PMD_IEEE0BLK_PMD_IEEEDEVINPKG1_CLAUSE22_SHIFT 0 35605 35606 35607 /**************************************************************************** 35608 * PMD_ieee0Blk :: PMD_ieeeControl2 35609 */ 35610 /* PMD_ieee0Blk :: PMD_ieeeControl2 :: reserved0 [15:03] */ 35611 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_MASK 0xfff8 35612 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_ALIGN 0 35613 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_BITS 13 35614 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_RESERVED0_SHIFT 3 35615 35616 /* PMD_ieee0Blk :: PMD_ieeeControl2 :: PMA_PMD_typeSel [02:00] */ 35617 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_MASK 0x0007 35618 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_ALIGN 0 35619 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_BITS 3 35620 #define PMD_IEEE0BLK_PMD_IEEECONTROL2_PMA_PMD_TYPESEL_SHIFT 0 35621 35622 35623 /**************************************************************************** 35624 * PMD_ieee0Blk :: PMD_ieeeStatus2 35625 */ 35626 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: devPresent [15:14] */ 35627 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_MASK 0xc000 35628 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_ALIGN 0 35629 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_BITS 2 35630 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_DEVPRESENT_SHIFT 14 35631 35632 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: txFaultAbility [13:13] */ 35633 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_MASK 0x2000 35634 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_ALIGN 0 35635 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_BITS 1 35636 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULTABILITY_SHIFT 13 35637 35638 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: rxFaultAbility [12:12] */ 35639 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_MASK 0x1000 35640 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_ALIGN 0 35641 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_BITS 1 35642 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULTABILITY_SHIFT 12 35643 35644 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: txFault [11:11] */ 35645 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_MASK 0x0800 35646 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_ALIGN 0 35647 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_BITS 1 35648 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_TXFAULT_SHIFT 11 35649 35650 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: rxFault [10:10] */ 35651 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_MASK 0x0400 35652 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_ALIGN 0 35653 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_BITS 1 35654 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_RXFAULT_SHIFT 10 35655 35656 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: extAbilities [09:09] */ 35657 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_MASK 0x0200 35658 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_ALIGN 0 35659 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_BITS 1 35660 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_EXTABILITIES_SHIFT 9 35661 35662 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_txDisableAble [08:08] */ 35663 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_MASK 0x0100 35664 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_ALIGN 0 35665 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_BITS 1 35666 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_TXDISABLEABLE_SHIFT 8 35667 35668 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_SR_able [07:07] */ 35669 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_MASK 0x0080 35670 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_ALIGN 0 35671 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_BITS 1 35672 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SR_ABLE_SHIFT 7 35673 35674 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LR_able [06:06] */ 35675 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_MASK 0x0040 35676 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_ALIGN 0 35677 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_BITS 1 35678 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LR_ABLE_SHIFT 6 35679 35680 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_ER_able [05:05] */ 35681 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_MASK 0x0020 35682 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_ALIGN 0 35683 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_BITS 1 35684 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_ER_ABLE_SHIFT 5 35685 35686 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LX4_able [04:04] */ 35687 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_MASK 0x0010 35688 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_ALIGN 0 35689 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_BITS 1 35690 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LX4_ABLE_SHIFT 4 35691 35692 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_SW_able [03:03] */ 35693 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_MASK 0x0008 35694 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_ALIGN 0 35695 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_BITS 1 35696 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_SW_ABLE_SHIFT 3 35697 35698 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_LW_able [02:02] */ 35699 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_MASK 0x0004 35700 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_ALIGN 0 35701 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_BITS 1 35702 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_LW_ABLE_SHIFT 2 35703 35704 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMD_10GBASE_EW_able [01:01] */ 35705 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_MASK 0x0002 35706 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_ALIGN 0 35707 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_BITS 1 35708 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMD_10GBASE_EW_ABLE_SHIFT 1 35709 35710 /* PMD_ieee0Blk :: PMD_ieeeStatus2 :: PMA_loopback_able [00:00] */ 35711 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_MASK 0x0001 35712 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_ALIGN 0 35713 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_BITS 1 35714 #define PMD_IEEE0BLK_PMD_IEEESTATUS2_PMA_LOOPBACK_ABLE_SHIFT 0 35715 35716 35717 /**************************************************************************** 35718 * PMD_ieee0Blk :: PMD_txDisable_type 35719 */ 35720 /* PMD_ieee0Blk :: PMD_txDisable_type :: reserved0 [15:05] */ 35721 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_RESERVED0_MASK 0xffe0 35722 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_RESERVED0_ALIGN 0 35723 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_RESERVED0_BITS 11 35724 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_RESERVED0_SHIFT 5 35725 35726 /* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_ln3 [04:04] */ 35727 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN3_MASK 0x0010 35728 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN3_ALIGN 0 35729 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN3_BITS 1 35730 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN3_SHIFT 4 35731 35732 /* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_ln2 [03:03] */ 35733 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN2_MASK 0x0008 35734 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN2_ALIGN 0 35735 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN2_BITS 1 35736 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN2_SHIFT 3 35737 35738 /* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_ln1 [02:02] */ 35739 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN1_MASK 0x0004 35740 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN1_ALIGN 0 35741 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN1_BITS 1 35742 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN1_SHIFT 2 35743 35744 /* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_ln0 [01:01] */ 35745 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN0_MASK 0x0002 35746 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN0_ALIGN 0 35747 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN0_BITS 1 35748 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_LN0_SHIFT 1 35749 35750 /* PMD_ieee0Blk :: PMD_txDisable_type :: tx_disable_global [00:00] */ 35751 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_GLOBAL_MASK 0x0001 35752 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_GLOBAL_ALIGN 0 35753 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_GLOBAL_BITS 1 35754 #define PMD_IEEE0BLK_PMD_TXDISABLE_TYPE_TX_DISABLE_GLOBAL_SHIFT 0 35755 35756 35757 /**************************************************************************** 35758 * PMD_ieee0Blk :: PMD_rxSignalDetect 35759 */ 35760 /* PMD_ieee0Blk :: PMD_rxSignalDetect :: reserved0 [15:05] */ 35761 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RESERVED0_MASK 0xffe0 35762 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RESERVED0_ALIGN 0 35763 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RESERVED0_BITS 11 35764 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RESERVED0_SHIFT 5 35765 35766 /* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_ln3 [04:04] */ 35767 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN3_MASK 0x0010 35768 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN3_ALIGN 0 35769 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN3_BITS 1 35770 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN3_SHIFT 4 35771 35772 /* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_ln2 [03:03] */ 35773 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN2_MASK 0x0008 35774 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN2_ALIGN 0 35775 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN2_BITS 1 35776 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN2_SHIFT 3 35777 35778 /* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_ln1 [02:02] */ 35779 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN1_MASK 0x0004 35780 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN1_ALIGN 0 35781 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN1_BITS 1 35782 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN1_SHIFT 2 35783 35784 /* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_ln0 [01:01] */ 35785 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN0_MASK 0x0002 35786 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN0_ALIGN 0 35787 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN0_BITS 1 35788 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_LN0_SHIFT 1 35789 35790 /* PMD_ieee0Blk :: PMD_rxSignalDetect :: rxSigdet_global [00:00] */ 35791 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_GLOBAL_MASK 0x0001 35792 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_GLOBAL_ALIGN 0 35793 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_GLOBAL_BITS 1 35794 #define PMD_IEEE0BLK_PMD_RXSIGNALDETECT_RXSIGDET_GLOBAL_SHIFT 0 35795 35796 35797 /**************************************************************************** 35798 * PMD_ieee0Blk :: PMD_extendedAbility 35799 */ 35800 /* PMD_ieee0Blk :: PMD_extendedAbility :: reserved0 [15:09] */ 35801 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_MASK 0xfe00 35802 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_ALIGN 0 35803 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_BITS 7 35804 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_RESERVED0_SHIFT 9 35805 35806 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10BASE_T_Ability [08:08] */ 35807 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_MASK 0x0100 35808 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_ALIGN 0 35809 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_BITS 1 35810 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10BASE_T_ABILITY_SHIFT 8 35811 35812 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_100BASE_TX_Ability [07:07] */ 35813 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_MASK 0x0080 35814 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_ALIGN 0 35815 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_BITS 1 35816 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_100BASE_TX_ABILITY_SHIFT 7 35817 35818 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_1000BASE_KX_Ability [06:06] */ 35819 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_MASK 0x0040 35820 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_ALIGN 0 35821 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_BITS 1 35822 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_KX_ABILITY_SHIFT 6 35823 35824 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_1000BASE_T_Ability [05:05] */ 35825 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_MASK 0x0020 35826 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_ALIGN 0 35827 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_BITS 1 35828 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_1000BASE_T_ABILITY_SHIFT 5 35829 35830 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_KR_Ability [04:04] */ 35831 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_MASK 0x0010 35832 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_ALIGN 0 35833 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_BITS 1 35834 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KR_ABILITY_SHIFT 4 35835 35836 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_KX4_Ability [03:03] */ 35837 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_MASK 0x0008 35838 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_ALIGN 0 35839 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_BITS 1 35840 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_KX4_ABILITY_SHIFT 3 35841 35842 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_T_Ability [02:02] */ 35843 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_MASK 0x0004 35844 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_ALIGN 0 35845 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_BITS 1 35846 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_T_ABILITY_SHIFT 2 35847 35848 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_LRM_Ability [01:01] */ 35849 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_MASK 0x0002 35850 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_ALIGN 0 35851 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_BITS 1 35852 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_LRM_ABILITY_SHIFT 1 35853 35854 /* PMD_ieee0Blk :: PMD_extendedAbility :: PMD_10GBASE_CX4_Ability [00:00] */ 35855 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_MASK 0x0001 35856 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_ALIGN 0 35857 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_BITS 1 35858 #define PMD_IEEE0BLK_PMD_EXTENDEDABILITY_PMD_10GBASE_CX4_ABILITY_SHIFT 0 35859 35860 35861 /**************************************************************************** 35862 * Hypercore_IEEE_PMD_PMD_ieee10Blk 35863 */ 35864 /**************************************************************************** 35865 * PMD_ieee10Blk :: PMD_KX_control 35866 */ 35867 /* PMD_ieee10Blk :: PMD_KX_control :: reserved0 [15:01] */ 35868 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_MASK 0xfffe 35869 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_ALIGN 0 35870 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_BITS 15 35871 #define PMD_IEEE10BLK_PMD_KX_CONTROL_RESERVED0_SHIFT 1 35872 35873 /* PMD_ieee10Blk :: PMD_KX_control :: tx_disable [00:00] */ 35874 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_MASK 0x0001 35875 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_ALIGN 0 35876 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_BITS 1 35877 #define PMD_IEEE10BLK_PMD_KX_CONTROL_TX_DISABLE_SHIFT 0 35878 35879 35880 /**************************************************************************** 35881 * PMD_ieee10Blk :: PMD_KX_status 35882 */ 35883 /* PMD_ieee10Blk :: PMD_KX_status :: reserved0 [15:14] */ 35884 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_MASK 0xc000 35885 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_ALIGN 0 35886 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_BITS 2 35887 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED0_SHIFT 14 35888 35889 /* PMD_ieee10Blk :: PMD_KX_status :: KX_txFaultAbility [13:13] */ 35890 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_MASK 0x2000 35891 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_ALIGN 0 35892 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_BITS 1 35893 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULTABILITY_SHIFT 13 35894 35895 /* PMD_ieee10Blk :: PMD_KX_status :: KX_rxFaultAbility [12:12] */ 35896 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_MASK 0x1000 35897 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_ALIGN 0 35898 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_BITS 1 35899 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RXFAULTABILITY_SHIFT 12 35900 35901 /* PMD_ieee10Blk :: PMD_KX_status :: KX_txFault [11:11] */ 35902 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_MASK 0x0800 35903 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_ALIGN 0 35904 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_BITS 1 35905 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_TXFAULT_SHIFT 11 35906 35907 /* PMD_ieee10Blk :: PMD_KX_status :: KX_rsFault [10:10] */ 35908 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_MASK 0x0400 35909 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_ALIGN 0 35910 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_BITS 1 35911 #define PMD_IEEE10BLK_PMD_KX_STATUS_KX_RSFAULT_SHIFT 10 35912 35913 /* PMD_ieee10Blk :: PMD_KX_status :: reserved1 [09:09] */ 35914 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_MASK 0x0200 35915 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_ALIGN 0 35916 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_BITS 1 35917 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED1_SHIFT 9 35918 35919 /* PMD_ieee10Blk :: PMD_KX_status :: txDisableAbility [08:08] */ 35920 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_MASK 0x0100 35921 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_ALIGN 0 35922 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_BITS 1 35923 #define PMD_IEEE10BLK_PMD_KX_STATUS_TXDISABLEABILITY_SHIFT 8 35924 35925 /* PMD_ieee10Blk :: PMD_KX_status :: reserved2 [07:01] */ 35926 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_MASK 0x00fe 35927 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_ALIGN 0 35928 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_BITS 7 35929 #define PMD_IEEE10BLK_PMD_KX_STATUS_RESERVED2_SHIFT 1 35930 35931 /* PMD_ieee10Blk :: PMD_KX_status :: PMD_sigdet [00:00] */ 35932 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_MASK 0x0001 35933 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_ALIGN 0 35934 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_BITS 1 35935 #define PMD_IEEE10BLK_PMD_KX_STATUS_PMD_SIGDET_SHIFT 0 35936 35937 35938 /**************************************************************************** 35939 * Hypercore_IEEE_DTE_DTE_ieee0Blk 35940 */ 35941 /**************************************************************************** 35942 * DTE_ieee0Blk :: DTE_ieeeControl1 35943 */ 35944 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: rst_sw [15:15] */ 35945 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RST_SW_MASK 0x8000 35946 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RST_SW_ALIGN 0 35947 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RST_SW_BITS 1 35948 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RST_SW_SHIFT 15 35949 35950 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: gloop10g [14:14] */ 35951 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_GLOOP10G_MASK 0x4000 35952 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_GLOOP10G_ALIGN 0 35953 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_GLOOP10G_BITS 1 35954 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_GLOOP10G_SHIFT 14 35955 35956 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: SpeedSelection0 [13:13] */ 35957 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION0_MASK 0x2000 35958 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION0_ALIGN 0 35959 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION0_BITS 1 35960 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION0_SHIFT 13 35961 35962 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: reserved0 [12:12] */ 35963 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED0_MASK 0x1000 35964 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED0_ALIGN 0 35965 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED0_BITS 1 35966 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED0_SHIFT 12 35967 35968 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: pwrdwn_sw_10g [11:11] */ 35969 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_PWRDWN_SW_10G_MASK 0x0800 35970 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_PWRDWN_SW_10G_ALIGN 0 35971 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_PWRDWN_SW_10G_BITS 1 35972 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_PWRDWN_SW_10G_SHIFT 11 35973 35974 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: reserved1 [10:07] */ 35975 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED1_MASK 0x0780 35976 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED1_ALIGN 0 35977 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED1_BITS 4 35978 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED1_SHIFT 7 35979 35980 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: SpeedSelection1 [06:06] */ 35981 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION1_MASK 0x0040 35982 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION1_ALIGN 0 35983 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION1_BITS 1 35984 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION1_SHIFT 6 35985 35986 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: SpeedSelection2 [05:02] */ 35987 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION2_MASK 0x003c 35988 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION2_ALIGN 0 35989 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION2_BITS 4 35990 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_SPEEDSELECTION2_SHIFT 2 35991 35992 /* DTE_ieee0Blk :: DTE_ieeeControl1 :: reserved2 [01:00] */ 35993 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED2_MASK 0x0003 35994 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED2_ALIGN 0 35995 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED2_BITS 2 35996 #define DTE_IEEE0BLK_DTE_IEEECONTROL1_RESERVED2_SHIFT 0 35997 35998 35999 /**************************************************************************** 36000 * DTE_ieee0Blk :: DTE_ieeeStatus1 36001 */ 36002 /* DTE_ieee0Blk :: DTE_ieeeStatus1 :: reserved0 [15:08] */ 36003 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED0_MASK 0xff00 36004 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED0_ALIGN 0 36005 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED0_BITS 8 36006 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED0_SHIFT 8 36007 36008 /* DTE_ieee0Blk :: DTE_ieeeStatus1 :: Fault [07:07] */ 36009 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_FAULT_MASK 0x0080 36010 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_FAULT_ALIGN 0 36011 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_FAULT_BITS 1 36012 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_FAULT_SHIFT 7 36013 36014 /* DTE_ieee0Blk :: DTE_ieeeStatus1 :: reserved1 [06:03] */ 36015 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED1_MASK 0x0078 36016 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED1_ALIGN 0 36017 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED1_BITS 4 36018 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED1_SHIFT 3 36019 36020 /* DTE_ieee0Blk :: DTE_ieeeStatus1 :: Rx_linkStatus [02:02] */ 36021 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RX_LINKSTATUS_MASK 0x0004 36022 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RX_LINKSTATUS_ALIGN 0 36023 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RX_LINKSTATUS_BITS 1 36024 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RX_LINKSTATUS_SHIFT 2 36025 36026 /* DTE_ieee0Blk :: DTE_ieeeStatus1 :: lowPowerAbility [01:01] */ 36027 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_LOWPOWERABILITY_MASK 0x0002 36028 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_LOWPOWERABILITY_ALIGN 0 36029 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_LOWPOWERABILITY_BITS 1 36030 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_LOWPOWERABILITY_SHIFT 1 36031 36032 /* DTE_ieee0Blk :: DTE_ieeeStatus1 :: reserved2 [00:00] */ 36033 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED2_MASK 0x0001 36034 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED2_ALIGN 0 36035 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED2_BITS 1 36036 #define DTE_IEEE0BLK_DTE_IEEESTATUS1_RESERVED2_SHIFT 0 36037 36038 36039 /**************************************************************************** 36040 * DTE_ieee0Blk :: DTE_ieeeId1 36041 */ 36042 /* DTE_ieee0Blk :: DTE_ieeeId1 :: IEEEID1 [15:00] */ 36043 #define DTE_IEEE0BLK_DTE_IEEEID1_IEEEID1_MASK 0xffff 36044 #define DTE_IEEE0BLK_DTE_IEEEID1_IEEEID1_ALIGN 0 36045 #define DTE_IEEE0BLK_DTE_IEEEID1_IEEEID1_BITS 16 36046 #define DTE_IEEE0BLK_DTE_IEEEID1_IEEEID1_SHIFT 0 36047 36048 36049 /**************************************************************************** 36050 * DTE_ieee0Blk :: DTE_ieeeId2 36051 */ 36052 /* DTE_ieee0Blk :: DTE_ieeeId2 :: IEEEID2 [15:00] */ 36053 #define DTE_IEEE0BLK_DTE_IEEEID2_IEEEID2_MASK 0xffff 36054 #define DTE_IEEE0BLK_DTE_IEEEID2_IEEEID2_ALIGN 0 36055 #define DTE_IEEE0BLK_DTE_IEEEID2_IEEEID2_BITS 16 36056 #define DTE_IEEE0BLK_DTE_IEEEID2_IEEEID2_SHIFT 0 36057 36058 36059 /**************************************************************************** 36060 * DTE_ieee0Blk :: DTE_ieeeSpeedAbility 36061 */ 36062 /* DTE_ieee0Blk :: DTE_ieeeSpeedAbility :: reserved0 [15:01] */ 36063 #define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_RESERVED0_MASK 0xfffe 36064 #define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_RESERVED0_ALIGN 0 36065 #define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_RESERVED0_BITS 15 36066 #define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_RESERVED0_SHIFT 1 36067 36068 /* DTE_ieee0Blk :: DTE_ieeeSpeedAbility :: speed10G [00:00] */ 36069 #define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_SPEED10G_MASK 0x0001 36070 #define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_SPEED10G_ALIGN 0 36071 #define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_SPEED10G_BITS 1 36072 #define DTE_IEEE0BLK_DTE_IEEESPEEDABILITY_SPEED10G_SHIFT 0 36073 36074 36075 /**************************************************************************** 36076 * DTE_ieee0Blk :: DTE_ieeeDevInPkg2 36077 */ 36078 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg2 :: Vendor2 [15:15] */ 36079 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR2_MASK 0x8000 36080 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR2_ALIGN 0 36081 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR2_BITS 1 36082 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR2_SHIFT 15 36083 36084 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg2 :: Vendor1 [14:14] */ 36085 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR1_MASK 0x4000 36086 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR1_ALIGN 0 36087 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR1_BITS 1 36088 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_VENDOR1_SHIFT 14 36089 36090 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg2 :: CL22ext [13:13] */ 36091 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_CL22EXT_MASK 0x2000 36092 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_CL22EXT_ALIGN 0 36093 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_CL22EXT_BITS 1 36094 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_CL22EXT_SHIFT 13 36095 36096 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg2 :: reserved0 [12:00] */ 36097 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_RESERVED0_MASK 0x1fff 36098 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_RESERVED0_ALIGN 0 36099 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_RESERVED0_BITS 13 36100 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG2_RESERVED0_SHIFT 0 36101 36102 36103 /**************************************************************************** 36104 * DTE_ieee0Blk :: DTE_ieeeDevInPkg1 36105 */ 36106 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: reserved0 [15:08] */ 36107 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_RESERVED0_MASK 0xff00 36108 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_RESERVED0_ALIGN 0 36109 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_RESERVED0_BITS 8 36110 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_RESERVED0_SHIFT 8 36111 36112 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: AN [07:07] */ 36113 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_AN_MASK 0x0080 36114 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_AN_ALIGN 0 36115 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_AN_BITS 1 36116 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_AN_SHIFT 7 36117 36118 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: TC [06:06] */ 36119 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_TC_MASK 0x0040 36120 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_TC_ALIGN 0 36121 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_TC_BITS 1 36122 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_TC_SHIFT 6 36123 36124 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: DTE_XS [05:05] */ 36125 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_DTE_XS_MASK 0x0020 36126 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_DTE_XS_ALIGN 0 36127 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_DTE_XS_BITS 1 36128 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_DTE_XS_SHIFT 5 36129 36130 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: PHY_XS [04:04] */ 36131 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PHY_XS_MASK 0x0010 36132 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PHY_XS_ALIGN 0 36133 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PHY_XS_BITS 1 36134 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PHY_XS_SHIFT 4 36135 36136 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: PCS_XS [03:03] */ 36137 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PCS_XS_MASK 0x0008 36138 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PCS_XS_ALIGN 0 36139 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PCS_XS_BITS 1 36140 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PCS_XS_SHIFT 3 36141 36142 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: WIS [02:02] */ 36143 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_WIS_MASK 0x0004 36144 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_WIS_ALIGN 0 36145 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_WIS_BITS 1 36146 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_WIS_SHIFT 2 36147 36148 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: PMA_PMD [01:01] */ 36149 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PMA_PMD_MASK 0x0002 36150 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PMA_PMD_ALIGN 0 36151 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PMA_PMD_BITS 1 36152 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_PMA_PMD_SHIFT 1 36153 36154 /* DTE_ieee0Blk :: DTE_ieeeDevInPkg1 :: Clause22 [00:00] */ 36155 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_CLAUSE22_MASK 0x0001 36156 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_CLAUSE22_ALIGN 0 36157 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_CLAUSE22_BITS 1 36158 #define DTE_IEEE0BLK_DTE_IEEEDEVINPKG1_CLAUSE22_SHIFT 0 36159 36160 36161 /**************************************************************************** 36162 * DTE_ieee0Blk :: DTE_ieeeStatus2 36163 */ 36164 /* DTE_ieee0Blk :: DTE_ieeeStatus2 :: devPresent [15:14] */ 36165 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_DEVPRESENT_MASK 0xc000 36166 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_DEVPRESENT_ALIGN 0 36167 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_DEVPRESENT_BITS 2 36168 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_DEVPRESENT_SHIFT 14 36169 36170 /* DTE_ieee0Blk :: DTE_ieeeStatus2 :: reserved0 [13:12] */ 36171 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED0_MASK 0x3000 36172 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED0_ALIGN 0 36173 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED0_BITS 2 36174 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED0_SHIFT 12 36175 36176 /* DTE_ieee0Blk :: DTE_ieeeStatus2 :: txFault [11:11] */ 36177 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_TXFAULT_MASK 0x0800 36178 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_TXFAULT_ALIGN 0 36179 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_TXFAULT_BITS 1 36180 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_TXFAULT_SHIFT 11 36181 36182 /* DTE_ieee0Blk :: DTE_ieeeStatus2 :: rxFault [10:10] */ 36183 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RXFAULT_MASK 0x0400 36184 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RXFAULT_ALIGN 0 36185 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RXFAULT_BITS 1 36186 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RXFAULT_SHIFT 10 36187 36188 /* DTE_ieee0Blk :: DTE_ieeeStatus2 :: reserved1 [09:00] */ 36189 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED1_MASK 0x03ff 36190 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED1_ALIGN 0 36191 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED1_BITS 10 36192 #define DTE_IEEE0BLK_DTE_IEEESTATUS2_RESERVED1_SHIFT 0 36193 36194 36195 /**************************************************************************** 36196 * Hypercore_IEEE_DTE_DTE_ieee1Blk 36197 */ 36198 /**************************************************************************** 36199 * DTE_ieee1Blk :: DTE_laneStatus 36200 */ 36201 /* DTE_ieee1Blk :: DTE_laneStatus :: reserved0 [15:13] */ 36202 #define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED0_MASK 0xe000 36203 #define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED0_ALIGN 0 36204 #define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED0_BITS 3 36205 #define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED0_SHIFT 13 36206 36207 /* DTE_ieee1Blk :: DTE_laneStatus :: DTE_alignStatus [12:12] */ 36208 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_ALIGNSTATUS_MASK 0x1000 36209 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_ALIGNSTATUS_ALIGN 0 36210 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_ALIGNSTATUS_BITS 1 36211 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_ALIGNSTATUS_SHIFT 12 36212 36213 /* DTE_ieee1Blk :: DTE_laneStatus :: DTE_PatTestAbility [11:11] */ 36214 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_PATTESTABILITY_MASK 0x0800 36215 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_PATTESTABILITY_ALIGN 0 36216 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_PATTESTABILITY_BITS 1 36217 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_PATTESTABILITY_SHIFT 11 36218 36219 /* DTE_ieee1Blk :: DTE_laneStatus :: reserved1 [10:04] */ 36220 #define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED1_MASK 0x07f0 36221 #define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED1_ALIGN 0 36222 #define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED1_BITS 7 36223 #define DTE_IEEE1BLK_DTE_LANESTATUS_RESERVED1_SHIFT 4 36224 36225 /* DTE_ieee1Blk :: DTE_laneStatus :: DTE_lane3Sync [03:03] */ 36226 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE3SYNC_MASK 0x0008 36227 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE3SYNC_ALIGN 0 36228 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE3SYNC_BITS 1 36229 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE3SYNC_SHIFT 3 36230 36231 /* DTE_ieee1Blk :: DTE_laneStatus :: DTE_lane2Sync [02:02] */ 36232 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE2SYNC_MASK 0x0004 36233 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE2SYNC_ALIGN 0 36234 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE2SYNC_BITS 1 36235 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE2SYNC_SHIFT 2 36236 36237 /* DTE_ieee1Blk :: DTE_laneStatus :: DTE_lane1Sync [01:01] */ 36238 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE1SYNC_MASK 0x0002 36239 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE1SYNC_ALIGN 0 36240 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE1SYNC_BITS 1 36241 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE1SYNC_SHIFT 1 36242 36243 /* DTE_ieee1Blk :: DTE_laneStatus :: DTE_lane0Sync [00:00] */ 36244 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE0SYNC_MASK 0x0001 36245 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE0SYNC_ALIGN 0 36246 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE0SYNC_BITS 1 36247 #define DTE_IEEE1BLK_DTE_LANESTATUS_DTE_LANE0SYNC_SHIFT 0 36248 36249 36250 /**************************************************************************** 36251 * DTE_ieee1Blk :: DTE_ieeeTestControl 36252 */ 36253 /* DTE_ieee1Blk :: DTE_ieeeTestControl :: reserved0 [15:03] */ 36254 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_RESERVED0_MASK 0xfff8 36255 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_RESERVED0_ALIGN 0 36256 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_RESERVED0_BITS 13 36257 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_RESERVED0_SHIFT 3 36258 36259 /* DTE_ieee1Blk :: DTE_ieeeTestControl :: DTE_txTestPatEn [02:02] */ 36260 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TXTESTPATEN_MASK 0x0004 36261 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TXTESTPATEN_ALIGN 0 36262 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TXTESTPATEN_BITS 1 36263 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TXTESTPATEN_SHIFT 2 36264 36265 /* DTE_ieee1Blk :: DTE_ieeeTestControl :: DTE_testPatSel [01:00] */ 36266 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TESTPATSEL_MASK 0x0003 36267 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TESTPATSEL_ALIGN 0 36268 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TESTPATSEL_BITS 2 36269 #define DTE_IEEE1BLK_DTE_IEEETESTCONTROL_DTE_TESTPATSEL_SHIFT 0 36270 36271 36272 /**************************************************************************** 36273 * Hypercore_IEEE_CL73_AN_ieee0Blk 36274 */ 36275 /**************************************************************************** 36276 * AN_ieee0Blk :: AN_ieeeControl1 36277 */ 36278 /* AN_ieee0Blk :: AN_ieeeControl1 :: rst_sw [15:15] */ 36279 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_MASK 0x8000 36280 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_ALIGN 0 36281 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_BITS 1 36282 #define AN_IEEE0BLK_AN_IEEECONTROL1_RST_SW_SHIFT 15 36283 36284 /* AN_ieee0Blk :: AN_ieeeControl1 :: gloop10g [14:14] */ 36285 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_MASK 0x4000 36286 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_ALIGN 0 36287 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_BITS 1 36288 #define AN_IEEE0BLK_AN_IEEECONTROL1_GLOOP10G_SHIFT 14 36289 36290 /* AN_ieee0Blk :: AN_ieeeControl1 :: ExtendNPen [13:13] */ 36291 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_MASK 0x2000 36292 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_ALIGN 0 36293 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_BITS 1 36294 #define AN_IEEE0BLK_AN_IEEECONTROL1_EXTENDNPEN_SHIFT 13 36295 36296 /* AN_ieee0Blk :: AN_ieeeControl1 :: AN_enable [12:12] */ 36297 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_MASK 0x1000 36298 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_ALIGN 0 36299 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_BITS 1 36300 #define AN_IEEE0BLK_AN_IEEECONTROL1_AN_ENABLE_SHIFT 12 36301 36302 /* AN_ieee0Blk :: AN_ieeeControl1 :: reserved0 [11:10] */ 36303 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_MASK 0x0c00 36304 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_ALIGN 0 36305 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_BITS 2 36306 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED0_SHIFT 10 36307 36308 /* AN_ieee0Blk :: AN_ieeeControl1 :: restartAN [09:09] */ 36309 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_MASK 0x0200 36310 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_ALIGN 0 36311 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_BITS 1 36312 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESTARTAN_SHIFT 9 36313 36314 /* AN_ieee0Blk :: AN_ieeeControl1 :: reserved1 [08:00] */ 36315 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_MASK 0x01ff 36316 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_ALIGN 0 36317 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_BITS 9 36318 #define AN_IEEE0BLK_AN_IEEECONTROL1_RESERVED1_SHIFT 0 36319 36320 36321 /**************************************************************************** 36322 * AN_ieee0Blk :: AN_ieeeStatus1 36323 */ 36324 /* AN_ieee0Blk :: AN_ieeeStatus1 :: reserved0 [15:08] */ 36325 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_MASK 0xff00 36326 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_ALIGN 0 36327 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_BITS 8 36328 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED0_SHIFT 8 36329 36330 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ExtendedNP_able [07:07] */ 36331 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_MASK 0x0080 36332 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_ALIGN 0 36333 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_BITS 1 36334 #define AN_IEEE0BLK_AN_IEEESTATUS1_EXTENDEDNP_ABLE_SHIFT 7 36335 36336 /* AN_ieee0Blk :: AN_ieeeStatus1 :: pageReceived [06:06] */ 36337 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_MASK 0x0040 36338 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_ALIGN 0 36339 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_BITS 1 36340 #define AN_IEEE0BLK_AN_IEEESTATUS1_PAGERECEIVED_SHIFT 6 36341 36342 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ANcomplete [05:05] */ 36343 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_MASK 0x0020 36344 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_ALIGN 0 36345 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_BITS 1 36346 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANCOMPLETE_SHIFT 5 36347 36348 /* AN_ieee0Blk :: AN_ieeeStatus1 :: remoteFault [04:04] */ 36349 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_MASK 0x0010 36350 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_ALIGN 0 36351 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_BITS 1 36352 #define AN_IEEE0BLK_AN_IEEESTATUS1_REMOTEFAULT_SHIFT 4 36353 36354 /* AN_ieee0Blk :: AN_ieeeStatus1 :: ANability [03:03] */ 36355 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_MASK 0x0008 36356 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_ALIGN 0 36357 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_BITS 1 36358 #define AN_IEEE0BLK_AN_IEEESTATUS1_ANABILITY_SHIFT 3 36359 36360 /* AN_ieee0Blk :: AN_ieeeStatus1 :: linkStatus [02:02] */ 36361 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_MASK 0x0004 36362 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_ALIGN 0 36363 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_BITS 1 36364 #define AN_IEEE0BLK_AN_IEEESTATUS1_LINKSTATUS_SHIFT 2 36365 36366 /* AN_ieee0Blk :: AN_ieeeStatus1 :: reserved1 [01:01] */ 36367 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_MASK 0x0002 36368 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_ALIGN 0 36369 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_BITS 1 36370 #define AN_IEEE0BLK_AN_IEEESTATUS1_RESERVED1_SHIFT 1 36371 36372 /* AN_ieee0Blk :: AN_ieeeStatus1 :: LP_ANability [00:00] */ 36373 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_MASK 0x0001 36374 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_ALIGN 0 36375 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_BITS 1 36376 #define AN_IEEE0BLK_AN_IEEESTATUS1_LP_ANABILITY_SHIFT 0 36377 36378 36379 /**************************************************************************** 36380 * AN_ieee0Blk :: AN_ieeeId1 36381 */ 36382 /* AN_ieee0Blk :: AN_ieeeId1 :: IEEEID1 [15:00] */ 36383 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_MASK 0xffff 36384 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_ALIGN 0 36385 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_BITS 16 36386 #define AN_IEEE0BLK_AN_IEEEID1_IEEEID1_SHIFT 0 36387 36388 36389 /**************************************************************************** 36390 * AN_ieee0Blk :: AN_ieeeId2 36391 */ 36392 /* AN_ieee0Blk :: AN_ieeeId2 :: IEEEID2 [15:00] */ 36393 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_MASK 0xffff 36394 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_ALIGN 0 36395 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_BITS 16 36396 #define AN_IEEE0BLK_AN_IEEEID2_IEEEID2_SHIFT 0 36397 36398 36399 /**************************************************************************** 36400 * AN_ieee0Blk :: AN_ieeeDevInPkg2 36401 */ 36402 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: Vendor2 [15:15] */ 36403 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_MASK 0x8000 36404 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_ALIGN 0 36405 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_BITS 1 36406 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR2_SHIFT 15 36407 36408 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: Vendor1 [14:14] */ 36409 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_MASK 0x4000 36410 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_ALIGN 0 36411 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_BITS 1 36412 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_VENDOR1_SHIFT 14 36413 36414 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: CL22ext [13:13] */ 36415 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_MASK 0x2000 36416 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_ALIGN 0 36417 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_BITS 1 36418 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_CL22EXT_SHIFT 13 36419 36420 /* AN_ieee0Blk :: AN_ieeeDevInPkg2 :: reserved0 [12:00] */ 36421 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_MASK 0x1fff 36422 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_ALIGN 0 36423 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_BITS 13 36424 #define AN_IEEE0BLK_AN_IEEEDEVINPKG2_RESERVED0_SHIFT 0 36425 36426 36427 /**************************************************************************** 36428 * AN_ieee0Blk :: AN_ieeeDevInPkg1 36429 */ 36430 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: reserved0 [15:08] */ 36431 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_MASK 0xff00 36432 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_ALIGN 0 36433 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_BITS 8 36434 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_RESERVED0_SHIFT 8 36435 36436 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: AN [07:07] */ 36437 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_MASK 0x0080 36438 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_ALIGN 0 36439 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_BITS 1 36440 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_AN_SHIFT 7 36441 36442 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: TC [06:06] */ 36443 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_MASK 0x0040 36444 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_ALIGN 0 36445 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_BITS 1 36446 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_TC_SHIFT 6 36447 36448 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: DTE_XS [05:05] */ 36449 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_MASK 0x0020 36450 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_ALIGN 0 36451 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_BITS 1 36452 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_DTE_XS_SHIFT 5 36453 36454 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PHY_XS [04:04] */ 36455 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_MASK 0x0010 36456 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_ALIGN 0 36457 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_BITS 1 36458 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PHY_XS_SHIFT 4 36459 36460 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PCS_XS [03:03] */ 36461 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_MASK 0x0008 36462 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_ALIGN 0 36463 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_BITS 1 36464 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PCS_XS_SHIFT 3 36465 36466 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: WIS [02:02] */ 36467 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_MASK 0x0004 36468 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_ALIGN 0 36469 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_BITS 1 36470 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_WIS_SHIFT 2 36471 36472 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: PMA_PMD [01:01] */ 36473 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_MASK 0x0002 36474 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_ALIGN 0 36475 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_BITS 1 36476 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_PMA_PMD_SHIFT 1 36477 36478 /* AN_ieee0Blk :: AN_ieeeDevInPkg1 :: Clause22 [00:00] */ 36479 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_MASK 0x0001 36480 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_ALIGN 0 36481 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_BITS 1 36482 #define AN_IEEE0BLK_AN_IEEEDEVINPKG1_CLAUSE22_SHIFT 0 36483 36484 36485 /**************************************************************************** 36486 * Hypercore_IEEE_CL73_AN_ieee1Blk 36487 */ 36488 /**************************************************************************** 36489 * AN_ieee1Blk :: AN_advertisement0 36490 */ 36491 /* AN_ieee1Blk :: AN_advertisement0 :: NP [15:15] */ 36492 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_MASK 0x8000 36493 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_ALIGN 0 36494 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_BITS 1 36495 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_NP_SHIFT 15 36496 36497 /* AN_ieee1Blk :: AN_advertisement0 :: Ack [14:14] */ 36498 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_MASK 0x4000 36499 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_ALIGN 0 36500 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_BITS 1 36501 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_ACK_SHIFT 14 36502 36503 /* AN_ieee1Blk :: AN_advertisement0 :: RF [13:13] */ 36504 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_MASK 0x2000 36505 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_ALIGN 0 36506 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_BITS 1 36507 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_RF_SHIFT 13 36508 36509 /* AN_ieee1Blk :: AN_advertisement0 :: XNP_able [12:12] */ 36510 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_XNP_ABLE_MASK 0x1000 36511 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_XNP_ABLE_ALIGN 0 36512 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_XNP_ABLE_BITS 1 36513 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_XNP_ABLE_SHIFT 12 36514 36515 /* AN_ieee1Blk :: AN_advertisement0 :: techAbility [11:05] */ 36516 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_TECHABILITY_MASK 0x0fe0 36517 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_TECHABILITY_ALIGN 0 36518 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_TECHABILITY_BITS 7 36519 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_TECHABILITY_SHIFT 5 36520 36521 /* AN_ieee1Blk :: AN_advertisement0 :: selector [04:00] */ 36522 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_MASK 0x001f 36523 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_ALIGN 0 36524 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_BITS 5 36525 #define AN_IEEE1BLK_AN_ADVERTISEMENT0_SELECTOR_SHIFT 0 36526 36527 #define CL73_AN_ADV_TECH_10G_KX4 (1 << 6) 36528 #define CL73_AN_ADV_TECH_1G_KX (1 << 5) 36529 #define CL73_AN_ADV_TECH_SPEEDS_MASK (0x7 << 5) 36530 #define CL73_AN_ADV_PAUSE (1 << 10) 36531 #define CL73_AN_ADV_ASYM_PAUSE (1 << 11) 36532 36533 /**************************************************************************** 36534 * AN_ieee1Blk :: AN_LP_basePageAbility0 36535 */ 36536 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: NP [15:15] */ 36537 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_MASK 0x8000 36538 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_ALIGN 0 36539 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_BITS 1 36540 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_NP_SHIFT 15 36541 36542 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: Ack [14:14] */ 36543 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_MASK 0x4000 36544 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_ALIGN 0 36545 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_BITS 1 36546 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_ACK_SHIFT 14 36547 36548 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: RF [13:13] */ 36549 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_MASK 0x2000 36550 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_ALIGN 0 36551 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_BITS 1 36552 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_RF_SHIFT 13 36553 36554 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: XNP_able [12:12] */ 36555 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_XNP_ABLE_MASK 0x1000 36556 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_XNP_ABLE_ALIGN 0 36557 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_XNP_ABLE_BITS 1 36558 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_XNP_ABLE_SHIFT 12 36559 36560 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: techAbility [11:05] */ 36561 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_TECHABILITY_MASK 0x0fe0 36562 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_TECHABILITY_ALIGN 0 36563 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_TECHABILITY_BITS 7 36564 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_TECHABILITY_SHIFT 5 36565 36566 /* AN_ieee1Blk :: AN_LP_basePageAbility0 :: selector [04:00] */ 36567 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_MASK 0x001f 36568 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_ALIGN 0 36569 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_BITS 5 36570 #define AN_IEEE1BLK_AN_LP_BASEPAGEABILITY0_SELECTOR_SHIFT 0 36571 36572 36573 /**************************************************************************** 36574 * AN_ieee1Blk :: AN_XNP_transmit0 36575 */ 36576 /* AN_ieee1Blk :: AN_XNP_transmit0 :: NP [15:15] */ 36577 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_MASK 0x8000 36578 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_ALIGN 0 36579 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_BITS 1 36580 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_NP_SHIFT 15 36581 36582 /* AN_ieee1Blk :: AN_XNP_transmit0 :: reserved0 [14:14] */ 36583 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_MASK 0x4000 36584 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_ALIGN 0 36585 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_BITS 1 36586 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_RESERVED0_SHIFT 14 36587 36588 /* AN_ieee1Blk :: AN_XNP_transmit0 :: MP [13:13] */ 36589 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_MASK 0x2000 36590 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_ALIGN 0 36591 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_BITS 1 36592 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MP_SHIFT 13 36593 36594 /* AN_ieee1Blk :: AN_XNP_transmit0 :: Ack2 [12:12] */ 36595 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_MASK 0x1000 36596 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_ALIGN 0 36597 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_BITS 1 36598 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_ACK2_SHIFT 12 36599 36600 /* AN_ieee1Blk :: AN_XNP_transmit0 :: Toggle [11:11] */ 36601 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_MASK 0x0800 36602 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_ALIGN 0 36603 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_BITS 1 36604 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_TOGGLE_SHIFT 11 36605 36606 /* AN_ieee1Blk :: AN_XNP_transmit0 :: MSG [10:00] */ 36607 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_MASK 0x07ff 36608 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_ALIGN 0 36609 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_BITS 11 36610 #define AN_IEEE1BLK_AN_XNP_TRANSMIT0_MSG_SHIFT 0 36611 36612 36613 /**************************************************************************** 36614 * AN_ieee1Blk :: AN_XNP_transmit1 36615 */ 36616 /* AN_ieee1Blk :: AN_XNP_transmit1 :: UCF1 [15:00] */ 36617 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_MASK 0xffff 36618 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_ALIGN 0 36619 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_BITS 16 36620 #define AN_IEEE1BLK_AN_XNP_TRANSMIT1_UCF1_SHIFT 0 36621 36622 36623 /**************************************************************************** 36624 * AN_ieee1Blk :: AN_XNP_transmit2 36625 */ 36626 /* AN_ieee1Blk :: AN_XNP_transmit2 :: UCF2 [15:00] */ 36627 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_MASK 0xffff 36628 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_ALIGN 0 36629 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_BITS 16 36630 #define AN_IEEE1BLK_AN_XNP_TRANSMIT2_UCF2_SHIFT 0 36631 36632 36633 /**************************************************************************** 36634 * AN_ieee1Blk :: AN_LP_XNP_ability0 36635 */ 36636 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: NP [15:15] */ 36637 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_MASK 0x8000 36638 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_ALIGN 0 36639 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_BITS 1 36640 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_NP_SHIFT 15 36641 36642 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: reserved0 [14:14] */ 36643 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_MASK 0x4000 36644 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_ALIGN 0 36645 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_BITS 1 36646 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_RESERVED0_SHIFT 14 36647 36648 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: MP [13:13] */ 36649 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_MASK 0x2000 36650 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_ALIGN 0 36651 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_BITS 1 36652 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MP_SHIFT 13 36653 36654 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: Ack2 [12:12] */ 36655 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_MASK 0x1000 36656 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_ALIGN 0 36657 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_BITS 1 36658 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_ACK2_SHIFT 12 36659 36660 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: Toggle [11:11] */ 36661 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_MASK 0x0800 36662 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_ALIGN 0 36663 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_BITS 1 36664 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_TOGGLE_SHIFT 11 36665 36666 /* AN_ieee1Blk :: AN_LP_XNP_ability0 :: MSG [10:00] */ 36667 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_MASK 0x07ff 36668 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_ALIGN 0 36669 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_BITS 11 36670 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY0_MSG_SHIFT 0 36671 36672 36673 /**************************************************************************** 36674 * AN_ieee1Blk :: AN_LP_XNP_ability1 36675 */ 36676 /* AN_ieee1Blk :: AN_LP_XNP_ability1 :: UCF1 [15:00] */ 36677 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_MASK 0xffff 36678 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_ALIGN 0 36679 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_BITS 16 36680 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY1_UCF1_SHIFT 0 36681 36682 36683 /**************************************************************************** 36684 * AN_ieee1Blk :: AN_LP_XNP_ability2 36685 */ 36686 /* AN_ieee1Blk :: AN_LP_XNP_ability2 :: UCF2 [15:00] */ 36687 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_MASK 0xffff 36688 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_ALIGN 0 36689 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_BITS 16 36690 #define AN_IEEE1BLK_AN_LP_XNP_ABILITY2_UCF2_SHIFT 0 36691 36692 36693 /**************************************************************************** 36694 * Hypercore_IEEE_CL73_AN_ieee3Blk 36695 */ 36696 /**************************************************************************** 36697 * AN_ieee3Blk :: AN_BPstatus 36698 */ 36699 /* AN_ieee3Blk :: AN_BPstatus :: reserved0 [15:10] */ 36700 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_MASK 0xfc00 36701 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_ALIGN 0 36702 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_BITS 6 36703 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED0_SHIFT 10 36704 36705 /* AN_ieee3Blk :: AN_BPstatus :: pdetFault [09:09] */ 36706 #define AN_IEEE3BLK_AN_BPSTATUS_PDETFAULT_MASK 0x0200 36707 #define AN_IEEE3BLK_AN_BPSTATUS_PDETFAULT_ALIGN 0 36708 #define AN_IEEE3BLK_AN_BPSTATUS_PDETFAULT_BITS 1 36709 #define AN_IEEE3BLK_AN_BPSTATUS_PDETFAULT_SHIFT 9 36710 36711 /* AN_ieee3Blk :: AN_BPstatus :: reserved1 [08:08] */ 36712 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_MASK 0x0100 36713 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_ALIGN 0 36714 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_BITS 1 36715 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED1_SHIFT 8 36716 36717 /* AN_ieee3Blk :: AN_BPstatus :: XNPstatus [07:07] */ 36718 #define AN_IEEE3BLK_AN_BPSTATUS_XNPSTATUS_MASK 0x0080 36719 #define AN_IEEE3BLK_AN_BPSTATUS_XNPSTATUS_ALIGN 0 36720 #define AN_IEEE3BLK_AN_BPSTATUS_XNPSTATUS_BITS 1 36721 #define AN_IEEE3BLK_AN_BPSTATUS_XNPSTATUS_SHIFT 7 36722 36723 /* AN_ieee3Blk :: AN_BPstatus :: pageRcvd [06:06] */ 36724 #define AN_IEEE3BLK_AN_BPSTATUS_PAGERCVD_MASK 0x0040 36725 #define AN_IEEE3BLK_AN_BPSTATUS_PAGERCVD_ALIGN 0 36726 #define AN_IEEE3BLK_AN_BPSTATUS_PAGERCVD_BITS 1 36727 #define AN_IEEE3BLK_AN_BPSTATUS_PAGERCVD_SHIFT 6 36728 36729 /* AN_ieee3Blk :: AN_BPstatus :: ANcomplete [05:05] */ 36730 #define AN_IEEE3BLK_AN_BPSTATUS_ANCOMPLETE_MASK 0x0020 36731 #define AN_IEEE3BLK_AN_BPSTATUS_ANCOMPLETE_ALIGN 0 36732 #define AN_IEEE3BLK_AN_BPSTATUS_ANCOMPLETE_BITS 1 36733 #define AN_IEEE3BLK_AN_BPSTATUS_ANCOMPLETE_SHIFT 5 36734 36735 /* AN_ieee3Blk :: AN_BPstatus :: RF [04:04] */ 36736 #define AN_IEEE3BLK_AN_BPSTATUS_RF_MASK 0x0010 36737 #define AN_IEEE3BLK_AN_BPSTATUS_RF_ALIGN 0 36738 #define AN_IEEE3BLK_AN_BPSTATUS_RF_BITS 1 36739 #define AN_IEEE3BLK_AN_BPSTATUS_RF_SHIFT 4 36740 36741 /* AN_ieee3Blk :: AN_BPstatus :: AN_able [03:03] */ 36742 #define AN_IEEE3BLK_AN_BPSTATUS_AN_ABLE_MASK 0x0008 36743 #define AN_IEEE3BLK_AN_BPSTATUS_AN_ABLE_ALIGN 0 36744 #define AN_IEEE3BLK_AN_BPSTATUS_AN_ABLE_BITS 1 36745 #define AN_IEEE3BLK_AN_BPSTATUS_AN_ABLE_SHIFT 3 36746 36747 /* AN_ieee3Blk :: AN_BPstatus :: Link [02:02] */ 36748 #define AN_IEEE3BLK_AN_BPSTATUS_LINK_MASK 0x0004 36749 #define AN_IEEE3BLK_AN_BPSTATUS_LINK_ALIGN 0 36750 #define AN_IEEE3BLK_AN_BPSTATUS_LINK_BITS 1 36751 #define AN_IEEE3BLK_AN_BPSTATUS_LINK_SHIFT 2 36752 36753 /* AN_ieee3Blk :: AN_BPstatus :: reserved2 [01:01] */ 36754 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED2_MASK 0x0002 36755 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED2_ALIGN 0 36756 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED2_BITS 1 36757 #define AN_IEEE3BLK_AN_BPSTATUS_RESERVED2_SHIFT 1 36758 36759 /* AN_ieee3Blk :: AN_BPstatus :: LP_AN_able [00:00] */ 36760 #define AN_IEEE3BLK_AN_BPSTATUS_LP_AN_ABLE_MASK 0x0001 36761 #define AN_IEEE3BLK_AN_BPSTATUS_LP_AN_ABLE_ALIGN 0 36762 #define AN_IEEE3BLK_AN_BPSTATUS_LP_AN_ABLE_BITS 1 36763 #define AN_IEEE3BLK_AN_BPSTATUS_LP_AN_ABLE_SHIFT 0 36764 36765 36766 /**************************************************************************** 36767 * Datatype Definitions. 36768 */ 36769 #endif /* #ifndef HC65_H__ */ 36770 36771 /* End of File */ 36772