bmacsec_timesync_defs.h (13681B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 8 9 /* Common place to put all the timesync IEEE1588 common utilities */ 10 11 #ifndef BMACSEC_TIMESYNC_DEFS_H 12 #define BMACSEC_TIMESYNC_DEFS_H 13 14 #define BMACSEC_PORT_PHY_TIMESYNC_ETHERNET_CAPABLE (1U<<0) 15 #define BMACSEC_PORT_PHY_TIMESYNC_MPLS_CAPABLE (1U<<1) 16 17 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_FLAGS (1U << 0) 18 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_ITPID (1U << 1) 19 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_OTPID (1U << 2) 20 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_OTPID2 (1U << 3) 21 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_GMODE (1U << 4) 22 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE (1U << 5) 23 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE (1U << 6) 24 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER (1U << 7) 25 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE (1U << 8) 26 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET (1U << 9) 27 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET (1U << 10) 28 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE (1U << 11) 29 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE (1U << 12) 30 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE (1U << 13) 31 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE (1U << 14) 32 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE (1U << 15) 33 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE (1U << 16) 34 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE (1U << 17) 35 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE (1U << 18) 36 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL (1U << 19) 37 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY (1U << 20) 38 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 (1U << 21) 39 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 (1U << 22) 40 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 (1U << 23) 41 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER (1U << 24) 42 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE (1U << 25) 43 #define BMACSEC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA (1U << 26) 44 45 #define BMACSEC_PORT_PHY_TIMESYNC_ENABLE (1U << 0) 46 #define BMACSEC_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE (1U << 1) 47 #define BMACSEC_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE (1U << 2) 48 #define BMACSEC_PORT_PHY_TIMESYNC_RX_CRC_ENABLE (1U << 3) 49 #define BMACSEC_PORT_PHY_TIMESYNC_8021AS_ENABLE (1U << 4) 50 #define BMACSEC_PORT_PHY_TIMESYNC_L2_ENABLE (1U << 5) 51 #define BMACSEC_PORT_PHY_TIMESYNC_IP4_ENABLE (1U << 6) 52 #define BMACSEC_PORT_PHY_TIMESYNC_IP6_ENABLE (1U << 7) 53 #define BMACSEC_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT (1U << 8) /* 0 - NCO FREQ CTRL REG, 1 - DPLL */ 54 #define BMACSEC_PORT_PHY_TIMESYNC_CLOCK_EXT_FREQ_LOCK (1U << 9) /* DPLL 0 - phase, 1 - freq lock */ 55 56 /* Enables the Layer4 IP6 address check when 1588 detection in transmission mode */ 57 #define BMACSEC_PORT_PHY_TIMESYNC_L4_IPV6_ADDR_ENABLE (1U << 10) 58 /* Enables the Layer4 IP address check when 1588 detection in transmission mode */ 59 #define BMACSEC_PORT_PHY_TIMESYNC_L4_IP_ADDR_ENABLE (1U << 11) 60 /* Enables the Layer2 MAC DS check when 1588 detection in transmission mode */ 61 #define BMACSEC_PORT_PHY_TIMESYNC_L2_DS_ENABLE (1U << 12) 62 /* Enables the 802.1as MAC DS check when 1588 detection in transmission mode */ 63 #define BMACSEC_PORT_PHY_TIMESYNC_AS_DS_ENABLE (1U << 13) 64 65 66 67 /* Base time structure. */ 68 typedef struct bmacsec_time_spec_s { 69 buint8_t isnegative; /* Sign identifier. */ 70 buint64_t seconds; /* Seconds absolute value. */ 71 buint32_t nanoseconds; /* Nanoseconds absolute value. */ 72 } bmacsec_time_spec_t; 73 74 /* Actions on Egress event messages */ 75 typedef enum bmacsec_port_phy_timesync_event_message_egress_mode_e { 76 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE, 77 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD, 78 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN, 79 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP, 80 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_RESERVED 81 } bmacsec_port_phy_timesync_event_message_egress_mode_t; 82 83 /* Actions on ingress event messages */ 84 typedef enum bmacsec_port_phy_timesync_event_message_ingress_mode_e { 85 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE, 86 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD, 87 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP, 88 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP_TN, 89 BMACSEC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME 90 } bmacsec_port_phy_timesync_event_message_ingress_mode_t; 91 92 /* Global mode actions */ 93 typedef enum bmacsec_port_phy_timesync_global_mode_e { 94 BMACSEC_PORT_PHY_TIMESYNC_MODE_FREE, 95 BMACSEC_PORT_PHY_TIMESYNC_MODE_SYNCIN, 96 BMACSEC_PORT_PHY_TIMESYNC_MODE_CPU 97 } bmacsec_port_phy_timesync_global_mode_t; 98 99 typedef enum bmacsec_port_phy_timesync_framesync_mode_s 100 { 101 BMACSEC_PORT_PHY_TIMESYNC_FRAMESYNC_NONE, 102 BMACSEC_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN0, 103 BMACSEC_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN1, 104 BMACSEC_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCOUT, 105 BMACSEC_PORT_PHY_TIMESYNC_FRAMESYNC_CPU 106 } bmacsec_port_phy_timesync_framesync_mode_t; 107 108 typedef struct bmacsec_port_phy_framesync_s { 109 bmacsec_port_phy_timesync_framesync_mode_t mode ; 110 buint16_t length_threshold; 111 buint16_t event_offset; 112 } bmacsec_port_phy_timesync_framesync_t; 113 114 typedef enum bmacsec_port_phy_timesync_syncout_mode_s 115 { 116 BMACSEC_PORT_PHY_TIMESYNC_SYNCOUT_DISABLE, 117 BMACSEC_PORT_PHY_TIMESYNC_SYNCOUT_ONE_TIME, 118 BMACSEC_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN, 119 BMACSEC_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN_WITH_SYNC 120 } bmacsec_port_phy_timesync_syncout_mode_t; 121 122 typedef struct bmacsec_port_phy_timesync_syncout_s { 123 124 bmacsec_port_phy_timesync_syncout_mode_t mode; 125 buint16_t pulse_1_length; /* in nanoseconds */ 126 buint16_t pulse_2_length; /* in nanoseconds */ 127 buint16_t interval; /* in nanoseconds */ 128 buint64_t syncout_ts; 129 130 } bmacsec_port_phy_timesync_syncout_t; 131 132 /* mpls_label_flags */ 133 #define BMACSEC_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT (1U<<1) 134 #define BMACSEC_PORT_PHY_TIMESYNC_MPLS_LABEL_IN (1U<<0) 135 136 typedef struct bmacsec_port_phy_timesync_mpls_label_s { 137 138 buint32_t value; /* bits [19:0] */ 139 buint32_t mask; /* bits [19:0] */ 140 buint32_t flags; /* label flags */ 141 142 } bmacsec_port_phy_timesync_mpls_label_t; 143 144 /* mpls_flags */ 145 #define BMACSEC_PORT_PHY_TIMESYNC_MPLS_ENABLE (1U<<0) 146 #define BMACSEC_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE (1U<<1) 147 #define BMACSEC_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE (1U<<3) 148 #define BMACSEC_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE (1U<<2) 149 150 typedef struct bmacsec_port_phy_timesync_mpls_control_s { 151 152 buint32_t flags; 153 buint32_t special_label; /* bits [19:0] */ 154 bmacsec_port_phy_timesync_mpls_label_t labels[10]; /* label */ 155 156 } bmacsec_port_phy_timesync_mpls_control_t; 157 158 159 #define BMACSEC_PORT_PHY_TIMESYNC_TN_LOAD (1U<<23) 160 #define BMACSEC_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD (1U<<22) 161 #define BMACSEC_PORT_PHY_TIMESYNC_TIMECODE_LOAD (1U<<21) 162 #define BMACSEC_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD (1U<<20) 163 #define BMACSEC_PORT_PHY_TIMESYNC_SYNCOUT_LOAD (1U<<19) 164 #define BMACSEC_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD (1U<<18) 165 #define BMACSEC_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD (1U<<17) 166 #define BMACSEC_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD (1U<<16) 167 #define BMACSEC_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD (1U<<15) 168 #define BMACSEC_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD (1U<<14) 169 #define BMACSEC_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD (1U<<13) 170 #define BMACSEC_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD (1U<<12) 171 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD (1U<<11) 172 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD (1U<<10) 173 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD (1U<<9) 174 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD (1U<<8) 175 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD (1U<<7) 176 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD (1U<<6) 177 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_K3_LOAD (1U<<5) 178 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD (1U<<4) 179 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_K2_LOAD (1U<<3) 180 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD (1U<<2) 181 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_K1_LOAD (1U<<1) 182 #define BMACSEC_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD (1U<<0) 183 184 #define BMACSEC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT (1U<<1) 185 #define BMACSEC_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT (1U<<0) 186 187 #define BMACSEC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK (1U<<1) 188 #define BMACSEC_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK (1U<<0) 189 190 191 /* Fast call actions */ 192 typedef enum bmacsec_port_phy_control_timesync_e { 193 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_CAPTURE_TIMESTAMP, 194 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_HEARTBEAT_TIMESTAMP, 195 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_NCOADDEND, 196 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_FRAMESYNC, 197 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_LOCAL_TIME, 198 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_LOAD_CONTROL, 199 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT, 200 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT_MASK, 201 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_TX_TIMESTAMP_OFFSET, 202 BMACSEC_PORT_CONTROL_PHY_TIMESYNC_RX_TIMESTAMP_OFFSET 203 } bmacsec_port_phy_control_timesync_t; 204 205 206 /* Base timesync configuration type. */ 207 typedef struct bmacsec_port_phy_timesync_config_s { 208 buint32_t validity_mask; 209 buint32_t flags; /* Flags BMACSEC_PORT_TIMESYNC_* */ 210 buint16_t itpid; /* 1588 inner tag */ 211 buint16_t otpid; /* 1588 outer tag */ 212 buint16_t otpid2; /* 1588 outer tag 2 */ 213 bmacsec_port_phy_timesync_global_mode_t gmode; /* Global mode */ 214 bmacsec_port_phy_timesync_framesync_t framesync; 215 bmacsec_port_phy_timesync_syncout_t syncout; 216 buint16_t ts_divider; 217 218 bmacsec_time_spec_t original_timecode; /* Original timecode to be inserted */ 219 buint32_t tx_timestamp_offset; /* TX AFE delay in ns - per port */ 220 buint32_t rx_timestamp_offset; /* RX AFE delay in ns - per port */ 221 buint32_t rx_link_delay; 222 223 bmacsec_port_phy_timesync_event_message_egress_mode_t tx_sync_mode; /* sync */ 224 bmacsec_port_phy_timesync_event_message_egress_mode_t tx_delay_request_mode; /* delay request */ 225 bmacsec_port_phy_timesync_event_message_egress_mode_t tx_pdelay_request_mode; /* pdelay request */ 226 bmacsec_port_phy_timesync_event_message_egress_mode_t tx_pdelay_response_mode; /* pdelay response */ 227 bmacsec_port_phy_timesync_event_message_ingress_mode_t rx_sync_mode; /* sync */ 228 bmacsec_port_phy_timesync_event_message_ingress_mode_t rx_delay_request_mode; /* delay request */ 229 bmacsec_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_request_mode; /* pdelay request */ 230 bmacsec_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_response_mode; /* pdelay response */ 231 232 bmacsec_port_phy_timesync_mpls_control_t mpls_control; 233 234 buint16_t phy_1588_dpll_k1; 235 buint16_t phy_1588_dpll_k2; 236 buint16_t phy_1588_dpll_k3; 237 buint64_t phy_1588_dpll_loop_filter; /* loop filter */ 238 buint64_t phy_1588_dpll_ref_phase; /* ref phase */ 239 buint32_t phy_1588_dpll_ref_phase_delta; /* ref phase delta */ 240 } bmacsec_port_phy_timesync_config_t; 241 242 /* bmacsec_port_phy_timesync_config_set */ 243 extern int 244 bmacsec_port_phy_timesync_config_set( 245 bmacsec_dev_addr_t phy_id, 246 bmacsec_port_phy_timesync_config_t *conf); 247 248 /* bmacsec_port_phy_timesync_config_get */ 249 extern int 250 bmacsec_port_phy_timesync_config_get( 251 bmacsec_dev_addr_t phy_id, 252 bmacsec_port_phy_timesync_config_t *conf); 253 254 /* bmacsec_port_phy_control_timesync_set */ 255 extern int 256 bmacsec_port_phy_control_timesync_set( 257 bmacsec_dev_addr_t phy_id, 258 bmacsec_port_phy_control_timesync_t type, 259 buint64_t value); 260 261 /* bmacsec_port_phy_control_timesync_get */ 262 extern int 263 bmacsec_port_phy_control_timesync_get( 264 bmacsec_dev_addr_t phy_id, 265 bmacsec_port_phy_control_timesync_t type, 266 buint64_t *value); 267 268 #endif /* BMACSEC_TIMESYNC_DEFS_H */