fields_x.i (460197B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: fields_x.i 12 * Purpose: Field declarations. 13 */ 14 15 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) 16 soc_field_info_t soc_XCON_CCM_DEFECT_STATUSr_fields[] = { 17 { FIRST_MA_INDEXf, 9, 0, SOCF_LE }, 18 { MULTIf, 1, 10, 0 }, 19 { RESERVED_MA_INDEX_0f, 1, 9, SOCF_RES }, 20 { VALIDf, 1, 11, 0 } 21 }; 22 23 #endif 24 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 25 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 26 defined(BCM_56725_A0) || defined(BCM_56820_A0) 27 soc_field_info_t soc_XGPORT_EXTRA_XGXS_NEWCTL_REGr_fields[] = { 28 { TXD1G_FIFO_RSTBf, 4, 0, SOCF_LE|SOCF_RES } 29 }; 30 31 #endif 32 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 33 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 34 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 35 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 36 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 37 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 38 defined(BCM_56725_A0) || defined(BCM_56820_A0) 39 soc_field_info_t soc_XGPORT_EXTRA_XGXS_NEWSTATUS0_REGr_fields[] = { 40 { XGXS0_AUTONEG_COMPLETEf, 4, 0, SOCF_LE|SOCF_RO }, 41 { XGXS0_DUPLEX_STATUSf, 4, 4, SOCF_LE|SOCF_RO }, 42 { XGXS0_FIBER_RXACTf, 4, 8, SOCF_LE|SOCF_RO }, 43 { XGXS0_FIBER_TXACTf, 4, 12, SOCF_LE|SOCF_RO }, 44 { XGXS0_LINK_STATUSf, 4, 16, SOCF_LE|SOCF_RO }, 45 { XGXS0_SGMIIf, 4, 20, SOCF_LE|SOCF_RO }, 46 { XGXS0_SPEED_10f, 4, 24, SOCF_LE|SOCF_RO }, 47 { XGXS0_SPEED_100f, 4, 28, SOCF_LE|SOCF_RO } 48 }; 49 50 #endif 51 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 52 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 53 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 54 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 55 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 56 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 57 defined(BCM_56725_A0) || defined(BCM_56820_A0) 58 soc_field_info_t soc_XGPORT_EXTRA_XGXS_NEWSTATUS1_REGr_fields[] = { 59 { XGXS0_SPEED1000f, 4, 0, SOCF_LE|SOCF_RO }, 60 { XGXS0_SPEED10000f, 4, 4, SOCF_LE|SOCF_RO }, 61 { XGXS0_SPEED10000_CX4f, 4, 8, SOCF_LE|SOCF_RO }, 62 { XGXS0_SPEED12000f, 4, 12, SOCF_LE|SOCF_RO }, 63 { XGXS0_SPEED12500f, 4, 16, SOCF_LE|SOCF_RO }, 64 { XGXS0_SPEED13000f, 4, 20, SOCF_LE|SOCF_RO }, 65 { XGXS0_SPEED15000f, 4, 24, SOCF_LE|SOCF_RO }, 66 { XGXS0_SPEED16000f, 4, 28, SOCF_LE|SOCF_RO } 67 }; 68 69 #endif 70 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 71 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 72 defined(BCM_56725_A0) || defined(BCM_56820_A0) 73 soc_field_info_t soc_XGPORT_EXTRA_XGXS_NEWSTATUS2_REGr_fields[] = { 74 { XGXS0_SPEED20000f, 4, 0, SOCF_LE|SOCF_RO }, 75 { XGXS0_SPEED21000f, 4, 8, SOCF_LE|SOCF_RO }, 76 { XGXS0_SPEED2500f, 4, 4, SOCF_LE|SOCF_RO }, 77 { XGXS0_SPEED5000f, 4, 12, SOCF_LE|SOCF_RO }, 78 { XGXS0_SPEED5000_SINGLEf, 4, 16, SOCF_LE|SOCF_RO }, 79 { XGXS0_SPEED6000f, 4, 20, SOCF_LE|SOCF_RO }, 80 { XGXS0_SPEED6364_SINGLEf, 4, 24, SOCF_LE|SOCF_RO }, 81 { XGXS0_TICKf, 4, 28, SOCF_LE|SOCF_RO } 82 }; 83 84 #endif 85 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 86 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 87 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 88 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 89 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 90 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 91 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 92 defined(BCM_56725_A0) || defined(BCM_56820_A0) 93 soc_field_info_t soc_XGPORT_EXTRA_XGXS_NEWSTATUS3_REGr_fields[] = { 94 { XGXS0_LINKf, 1, 0, SOCF_RO }, 95 { XGXS0_LINK10Gf, 1, 1, SOCF_RO } 96 }; 97 98 #endif 99 #if defined(BCM_56624_A0) || defined(BCM_56680_A0) 100 soc_field_info_t soc_XGPORT_MODE_REGr_fields[] = { 101 { XGPORT_MODE_BITSf, 2, 0, SOCF_LE|SOCF_RES } 102 }; 103 104 #endif 105 #if defined(BCM_56624_B0) || defined(BCM_56680_B0) 106 soc_field_info_t soc_XGPORT_MODE_REG_BCM56624_B0r_fields[] = { 107 { XGPORT_MODE_BITSf, 3, 0, SOCF_LE|SOCF_RES } 108 }; 109 110 #endif 111 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 112 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 113 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 114 defined(BCM_56680_A0) || defined(BCM_56680_B0) 115 soc_field_info_t soc_XGPORT_SERDES_CTLr_fields[] = { 116 { CLKSRCSELf, 2, 0, SOCF_LE } 117 }; 118 119 #endif 120 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 121 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 122 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 123 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 124 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 125 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 126 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 127 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 128 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 129 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 130 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 131 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 132 defined(BCM_88732_A0) 133 soc_field_info_t soc_XHOL_D0r_fields[] = { 134 { DATA_BYTES_0_3f, 32, 0, SOCF_LE } 135 }; 136 137 #endif 138 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 139 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 140 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 141 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 142 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 143 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 144 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 145 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 146 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 147 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 148 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 149 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 150 defined(BCM_88732_A0) 151 soc_field_info_t soc_XHOL_D1r_fields[] = { 152 { DATA_BYTES_4_7f, 32, 0, SOCF_LE } 153 }; 154 155 #endif 156 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 157 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 158 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 159 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 160 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 161 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 162 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 163 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 164 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 165 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 166 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 167 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 168 defined(BCM_88732_A0) 169 soc_field_info_t soc_XHOL_D2r_fields[] = { 170 { DATA_BYTES_8_11f, 32, 0, SOCF_LE } 171 }; 172 173 #endif 174 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 175 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 176 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 177 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 178 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 179 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 180 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 181 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 182 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 183 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 184 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 185 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 186 defined(BCM_88732_A0) 187 soc_field_info_t soc_XHOL_D3r_fields[] = { 188 { D_BYTES_12_15f, 32, 0, SOCF_LE } 189 }; 190 191 #endif 192 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 193 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 194 defined(BCM_56640_A0) || defined(BCM_56850_A0) 195 soc_field_info_t soc_XHOL_D0_BCM56640_A0r_fields[] = { 196 { DATA_BYTES_0_3f, 32, 0, SOCF_LE } 197 }; 198 199 #endif 200 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 201 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 202 defined(BCM_56640_A0) || defined(BCM_56850_A0) 203 soc_field_info_t soc_XHOL_D1_BCM56640_A0r_fields[] = { 204 { DATA_BYTES_4_7f, 32, 0, SOCF_LE } 205 }; 206 207 #endif 208 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 209 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 210 defined(BCM_56640_A0) || defined(BCM_56850_A0) 211 soc_field_info_t soc_XHOL_D2_BCM56640_A0r_fields[] = { 212 { DATA_BYTES_8_11f, 32, 0, SOCF_LE } 213 }; 214 215 #endif 216 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 217 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 218 defined(BCM_56640_A0) || defined(BCM_56850_A0) 219 soc_field_info_t soc_XHOL_D3_BCM56640_A0r_fields[] = { 220 { D_BYTES_12_15f, 32, 0, SOCF_LE } 221 }; 222 223 #endif 224 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 225 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 226 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 227 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 228 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 229 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 230 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 231 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 232 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 233 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 234 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 235 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 236 defined(BCM_88732_A0) 237 soc_field_info_t soc_XHOL_MH0r_fields[] = { 238 { MH_BYTES_0_3f, 32, 0, SOCF_LE } 239 }; 240 241 #endif 242 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 243 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 244 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 245 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 246 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 247 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 248 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 249 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 250 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 251 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 252 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 253 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 254 defined(BCM_88732_A0) 255 soc_field_info_t soc_XHOL_MH1r_fields[] = { 256 { MH_BYTES_4_7f, 32, 0, SOCF_LE } 257 }; 258 259 #endif 260 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 261 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 262 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 263 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 264 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 265 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 266 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 267 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 268 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 269 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 270 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 271 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 272 defined(BCM_88732_A0) 273 soc_field_info_t soc_XHOL_MH2r_fields[] = { 274 { MH_BYTES_8_11f, 32, 0, SOCF_LE } 275 }; 276 277 #endif 278 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 279 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 280 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 281 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 282 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 283 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 284 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 285 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 286 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 287 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 288 defined(BCM_88732_A0) 289 soc_field_info_t soc_XHOL_MH3r_fields[] = { 290 { MH_BYTES_12_15f, 32, 0, SOCF_LE } 291 }; 292 293 #endif 294 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 295 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 296 defined(BCM_56640_A0) || defined(BCM_56850_A0) 297 soc_field_info_t soc_XHOL_MH0_BCM56640_A0r_fields[] = { 298 { MH_BYTES_0_3f, 32, 0, SOCF_LE } 299 }; 300 301 #endif 302 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 303 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 304 defined(BCM_56640_A0) || defined(BCM_56850_A0) 305 soc_field_info_t soc_XHOL_MH1_BCM56640_A0r_fields[] = { 306 { MH_BYTES_4_7f, 32, 0, SOCF_LE } 307 }; 308 309 #endif 310 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 311 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 312 defined(BCM_56640_A0) || defined(BCM_56850_A0) 313 soc_field_info_t soc_XHOL_MH2_BCM56640_A0r_fields[] = { 314 { MH_BYTES_8_11f, 32, 0, SOCF_LE } 315 }; 316 317 #endif 318 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 319 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 320 defined(BCM_56640_A0) || defined(BCM_56850_A0) 321 soc_field_info_t soc_XHOL_MH3_BCM56640_A0r_fields[] = { 322 { MH_BYTES_12_15f, 32, 0, SOCF_LE } 323 }; 324 325 #endif 326 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 327 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 328 defined(BCM_56685_A0) || defined(BCM_56685_B0) 329 soc_field_info_t soc_XHOL_RX_MH_DATA0r_fields[] = { 330 { RX_MH_D0f, 32, 0, SOCF_LE } 331 }; 332 333 #endif 334 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 335 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 336 defined(BCM_56685_A0) || defined(BCM_56685_B0) 337 soc_field_info_t soc_XHOL_RX_MH_DATA1r_fields[] = { 338 { RX_MH_D1f, 32, 0, SOCF_LE } 339 }; 340 341 #endif 342 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 343 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 344 defined(BCM_56685_A0) || defined(BCM_56685_B0) 345 soc_field_info_t soc_XHOL_RX_MH_DATA2r_fields[] = { 346 { RX_MH_D2f, 32, 0, SOCF_LE } 347 }; 348 349 #endif 350 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 351 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 352 defined(BCM_56685_A0) || defined(BCM_56685_B0) 353 soc_field_info_t soc_XHOL_RX_MH_DATA3r_fields[] = { 354 { RX_MH_D3f, 32, 0, SOCF_LE } 355 }; 356 357 #endif 358 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 359 defined(BCM_56850_A0) 360 soc_field_info_t soc_XHOL_RX_MH_DATA0_BCM56640_A0r_fields[] = { 361 { RX_MH_D0f, 32, 0, SOCF_LE|SOCF_RES } 362 }; 363 364 #endif 365 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 366 defined(BCM_56850_A0) 367 soc_field_info_t soc_XHOL_RX_MH_DATA1_BCM56640_A0r_fields[] = { 368 { RX_MH_D1f, 32, 0, SOCF_LE|SOCF_RES } 369 }; 370 371 #endif 372 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 373 defined(BCM_56850_A0) 374 soc_field_info_t soc_XHOL_RX_MH_DATA2_BCM56640_A0r_fields[] = { 375 { RX_MH_D2f, 32, 0, SOCF_LE|SOCF_RES } 376 }; 377 378 #endif 379 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 380 defined(BCM_56850_A0) 381 soc_field_info_t soc_XHOL_RX_MH_DATA3_BCM56640_A0r_fields[] = { 382 { RX_MH_D3f, 32, 0, SOCF_LE|SOCF_RES } 383 }; 384 385 #endif 386 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 387 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 388 defined(BCM_56685_A0) || defined(BCM_56685_B0) 389 soc_field_info_t soc_XHOL_RX_MH_MASK0r_fields[] = { 390 { RX_MH_M0f, 32, 0, SOCF_LE } 391 }; 392 393 #endif 394 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 395 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 396 defined(BCM_56685_A0) || defined(BCM_56685_B0) 397 soc_field_info_t soc_XHOL_RX_MH_MASK1r_fields[] = { 398 { RX_MH_M1f, 32, 0, SOCF_LE } 399 }; 400 401 #endif 402 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 403 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 404 defined(BCM_56685_A0) || defined(BCM_56685_B0) 405 soc_field_info_t soc_XHOL_RX_MH_MASK2r_fields[] = { 406 { RX_MH_M2f, 32, 0, SOCF_LE } 407 }; 408 409 #endif 410 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 411 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 412 defined(BCM_56685_A0) || defined(BCM_56685_B0) 413 soc_field_info_t soc_XHOL_RX_MH_MASK3r_fields[] = { 414 { RX_MH_M3f, 32, 0, SOCF_LE } 415 }; 416 417 #endif 418 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 419 defined(BCM_56850_A0) 420 soc_field_info_t soc_XHOL_RX_MH_MASK0_BCM56640_A0r_fields[] = { 421 { RX_MH_M0f, 32, 0, SOCF_LE|SOCF_RES } 422 }; 423 424 #endif 425 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 426 defined(BCM_56850_A0) 427 soc_field_info_t soc_XHOL_RX_MH_MASK1_BCM56640_A0r_fields[] = { 428 { RX_MH_M1f, 32, 0, SOCF_LE|SOCF_RES } 429 }; 430 431 #endif 432 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 433 defined(BCM_56850_A0) 434 soc_field_info_t soc_XHOL_RX_MH_MASK2_BCM56640_A0r_fields[] = { 435 { RX_MH_M2f, 32, 0, SOCF_LE|SOCF_RES } 436 }; 437 438 #endif 439 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 440 defined(BCM_56850_A0) 441 soc_field_info_t soc_XHOL_RX_MH_MASK3_BCM56640_A0r_fields[] = { 442 { RX_MH_M3f, 32, 0, SOCF_LE|SOCF_RES } 443 }; 444 445 #endif 446 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 447 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 448 defined(BCM_56685_A0) || defined(BCM_56685_B0) 449 soc_field_info_t soc_XHOL_RX_PKT_DATA0r_fields[] = { 450 { RX_PKT_D0f, 32, 0, SOCF_LE } 451 }; 452 453 #endif 454 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 455 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 456 defined(BCM_56685_A0) || defined(BCM_56685_B0) 457 soc_field_info_t soc_XHOL_RX_PKT_DATA1r_fields[] = { 458 { RX_PKT_D1f, 32, 0, SOCF_LE } 459 }; 460 461 #endif 462 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 463 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 464 defined(BCM_56685_A0) || defined(BCM_56685_B0) 465 soc_field_info_t soc_XHOL_RX_PKT_DATA2r_fields[] = { 466 { RX_PKT_D2f, 32, 0, SOCF_LE } 467 }; 468 469 #endif 470 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 471 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 472 defined(BCM_56685_A0) || defined(BCM_56685_B0) 473 soc_field_info_t soc_XHOL_RX_PKT_DATA3r_fields[] = { 474 { RX_PKT_D3f, 32, 0, SOCF_LE } 475 }; 476 477 #endif 478 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 479 defined(BCM_56850_A0) 480 soc_field_info_t soc_XHOL_RX_PKT_DATA0_BCM56640_A0r_fields[] = { 481 { RX_PKT_D0f, 32, 0, SOCF_LE|SOCF_RES } 482 }; 483 484 #endif 485 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 486 defined(BCM_56850_A0) 487 soc_field_info_t soc_XHOL_RX_PKT_DATA1_BCM56640_A0r_fields[] = { 488 { RX_PKT_D1f, 32, 0, SOCF_LE|SOCF_RES } 489 }; 490 491 #endif 492 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 493 defined(BCM_56850_A0) 494 soc_field_info_t soc_XHOL_RX_PKT_DATA2_BCM56640_A0r_fields[] = { 495 { RX_PKT_D2f, 32, 0, SOCF_LE|SOCF_RES } 496 }; 497 498 #endif 499 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 500 defined(BCM_56850_A0) 501 soc_field_info_t soc_XHOL_RX_PKT_DATA3_BCM56640_A0r_fields[] = { 502 { RX_PKT_D3f, 32, 0, SOCF_LE|SOCF_RES } 503 }; 504 505 #endif 506 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 507 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 508 defined(BCM_56685_A0) || defined(BCM_56685_B0) 509 soc_field_info_t soc_XHOL_RX_PKT_MASK0r_fields[] = { 510 { RX_PKT_M0f, 32, 0, SOCF_LE } 511 }; 512 513 #endif 514 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 515 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 516 defined(BCM_56685_A0) || defined(BCM_56685_B0) 517 soc_field_info_t soc_XHOL_RX_PKT_MASK1r_fields[] = { 518 { RX_PKT_M1f, 32, 0, SOCF_LE } 519 }; 520 521 #endif 522 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 523 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 524 defined(BCM_56685_A0) || defined(BCM_56685_B0) 525 soc_field_info_t soc_XHOL_RX_PKT_MASK2r_fields[] = { 526 { RX_PKT_M2f, 32, 0, SOCF_LE } 527 }; 528 529 #endif 530 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 531 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 532 defined(BCM_56685_A0) || defined(BCM_56685_B0) 533 soc_field_info_t soc_XHOL_RX_PKT_MASK3r_fields[] = { 534 { RX_PKT_M3f, 32, 0, SOCF_LE } 535 }; 536 537 #endif 538 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 539 defined(BCM_56850_A0) 540 soc_field_info_t soc_XHOL_RX_PKT_MASK0_BCM56640_A0r_fields[] = { 541 { RX_PKT_M0f, 32, 0, SOCF_LE|SOCF_RES } 542 }; 543 544 #endif 545 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 546 defined(BCM_56850_A0) 547 soc_field_info_t soc_XHOL_RX_PKT_MASK1_BCM56640_A0r_fields[] = { 548 { RX_PKT_M1f, 32, 0, SOCF_LE|SOCF_RES } 549 }; 550 551 #endif 552 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 553 defined(BCM_56850_A0) 554 soc_field_info_t soc_XHOL_RX_PKT_MASK2_BCM56640_A0r_fields[] = { 555 { RX_PKT_M2f, 32, 0, SOCF_LE|SOCF_RES } 556 }; 557 558 #endif 559 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 560 defined(BCM_56850_A0) 561 soc_field_info_t soc_XHOL_RX_PKT_MASK3_BCM56640_A0r_fields[] = { 562 { RX_PKT_M3f, 32, 0, SOCF_LE|SOCF_RES } 563 }; 564 565 #endif 566 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 567 defined(BCM_88732_A0) 568 soc_field_info_t soc_XIBP_D0r_fields[] = { 569 { DATA_BYTES_0_3f, 32, 0, SOCF_LE|SOCF_RES } 570 }; 571 572 #endif 573 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 574 defined(BCM_88732_A0) 575 soc_field_info_t soc_XIBP_D1r_fields[] = { 576 { DATA_BYTES_4_7f, 32, 0, SOCF_LE|SOCF_RES } 577 }; 578 579 #endif 580 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 581 defined(BCM_88732_A0) 582 soc_field_info_t soc_XIBP_D2r_fields[] = { 583 { DATA_BYTES_8_11f, 32, 0, SOCF_LE|SOCF_RES } 584 }; 585 586 #endif 587 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 588 defined(BCM_88732_A0) 589 soc_field_info_t soc_XIBP_D3r_fields[] = { 590 { D_BYTES_12_15f, 32, 0, SOCF_LE|SOCF_RES } 591 }; 592 593 #endif 594 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 595 defined(BCM_88732_A0) 596 soc_field_info_t soc_XIBP_MH0r_fields[] = { 597 { MH_BYTES_0_3f, 32, 0, SOCF_LE|SOCF_RES } 598 }; 599 600 #endif 601 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 602 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 603 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 604 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 605 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 606 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 607 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 608 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 609 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 610 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 611 defined(BCM_56800_A0) || defined(BCM_56820_A0) 612 soc_field_info_t soc_XIBP_MH1r_fields[] = { 613 { MH_BYTES_4_7f, 32, 0, SOCF_LE } 614 }; 615 616 #endif 617 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 618 defined(BCM_88732_A0) 619 soc_field_info_t soc_XIBP_MH2r_fields[] = { 620 { MH_BYTES_8_11f, 32, 0, SOCF_LE|SOCF_RES } 621 }; 622 623 #endif 624 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 625 defined(BCM_88732_A0) 626 soc_field_info_t soc_XIBP_MH3r_fields[] = { 627 { MH_BYTES_12_15f, 32, 0, SOCF_LE|SOCF_RES } 628 }; 629 630 #endif 631 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 632 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 633 defined(BCM_56640_A0) 634 soc_field_info_t soc_XIBP_MH1_BCM56640_A0r_fields[] = { 635 { MH_BYTES_4_7f, 32, 0, SOCF_LE } 636 }; 637 638 #endif 639 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 640 defined(BCM_88732_A0) 641 soc_field_info_t soc_XIBP_MH1_BCM56840_A0r_fields[] = { 642 { MH_BYTES_4_7f, 32, 0, SOCF_LE|SOCF_RES } 643 }; 644 645 #endif 646 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 647 defined(BCM_56160_A0) || defined(BCM_56260_B0) || \ 648 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 649 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 650 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 651 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 652 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 653 defined(BCM_56980_B0) 654 soc_field_info_t soc_XLMAC_B0_CLEAR_ECC_STATUSr_fields[] = { 655 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, 0 }, 656 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, 0 }, 657 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, 0 }, 658 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, 0 } 659 }; 660 661 #endif 662 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 663 defined(BCM_56160_A0) || defined(BCM_56260_B0) || \ 664 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 665 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 666 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 667 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 668 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 669 defined(BCM_56980_B0) 670 soc_field_info_t soc_XLMAC_B0_CTRLr_fields[] = { 671 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 672 { LAG_FAILOVER_ENf, 1, 5, 0 }, 673 { LINK_STATUS_SELECTf, 1, 13, 0 }, 674 { LOCAL_LPBKf, 1, 2, 0 }, 675 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 676 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 677 { RSVD_1f, 1, 3, SOCF_RES }, 678 { RSVD_4f, 1, 7, SOCF_RES }, 679 { RSVD_5f, 1, 9, SOCF_RES }, 680 { RS_SOFT_RESETf, 1, 10, 0 }, 681 { RX_ENf, 1, 1, 0 }, 682 { SOFT_RESETf, 1, 6, 0 }, 683 { SW_LINK_STATUSf, 1, 12, 0 }, 684 { TX_ENf, 1, 0, 0 }, 685 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 686 }; 687 688 #endif 689 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 690 defined(BCM_56160_A0) || defined(BCM_56260_B0) || \ 691 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 692 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 693 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 694 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 695 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 696 defined(BCM_56980_B0) 697 soc_field_info_t soc_XLMAC_B0_PAUSE_CTRLr_fields[] = { 698 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 699 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 700 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 701 { RSVD_1f, 1, 19, SOCF_RES }, 702 { RSVD_2f, 1, 20, SOCF_RES }, 703 { RX_PAUSE_ENf, 1, 18, 0 }, 704 { TX_PAUSE_ENf, 1, 17, 0 }, 705 { XLMAC_PAUSE_CTRL_HIf, 5, 32, SOCF_LE }, 706 { XLMAC_PAUSE_CTRL_LOf, 32, 0, SOCF_LE } 707 }; 708 709 #endif 710 #if defined(BCM_56160_A0) || defined(BCM_56260_B0) || \ 711 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 712 defined(BCM_56560_B0) 713 soc_field_info_t soc_XLMAC_B0_RX_CTRLr_fields[] = { 714 { RSVD_1f, 1, 0, SOCF_RES }, 715 { RSVD_2f, 1, 11, SOCF_RES }, 716 { RSVD_3f, 1, 12, SOCF_RES }, 717 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 718 { RX_ANY_STARTf, 1, 1, 0 }, 719 { STRICT_PREAMBLEf, 1, 3, 0 }, 720 { STRIP_CRCf, 1, 2, 0 } 721 }; 722 723 #endif 724 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 725 defined(BCM_56160_A0) || defined(BCM_56260_A0) || \ 726 defined(BCM_56260_B0) || defined(BCM_56270_A0) || \ 727 defined(BCM_56370_A0) || defined(BCM_56560_A0) || \ 728 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 729 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 730 defined(BCM_56870_A0) || defined(BCM_56965_A0) || \ 731 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 732 defined(BCM_56980_B0) 733 soc_field_info_t soc_XLMAC_B0_TIMESTAMP_BYTE_ADJUSTr_fields[] = { 734 { RX_TIMER_BYTE_ADJUSTf, 10, 11, SOCF_LE }, 735 { RX_TIMER_BYTE_ADJUST_ENf, 1, 21, 0 }, 736 { TX_TIMER_BYTE_ADJUSTf, 10, 0, SOCF_LE }, 737 { TX_TIMER_BYTE_ADJUST_ENf, 1, 10, 0 } 738 }; 739 740 #endif 741 #if defined(BCM_56160_A0) || defined(BCM_56260_B0) || \ 742 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 743 defined(BCM_56560_B0) 744 soc_field_info_t soc_XLMAC_B0_VERSION_IDr_fields[] = { 745 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 746 }; 747 748 #endif 749 #if defined(BCM_2801PM_A0) || defined(BCM_53400_A0) || \ 750 defined(BCM_56260_A0) || defined(BCM_56560_A0) || \ 751 defined(BCM_56960_A0) || defined(BCM_56965_A0) 752 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUSr_fields[] = { 753 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO }, 754 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO }, 755 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, SOCF_RO }, 756 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, SOCF_RO } 757 }; 758 759 #endif 760 #if defined(BCM_56860_A0) 761 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM56860_A0r_fields[] = { 762 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, 0 }, 763 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, 0 }, 764 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, 0 }, 765 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, 0 } 766 }; 767 768 #endif 769 #if defined(BCM_88270_A0) 770 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM88270_A0r_fields[] = { 771 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO }, 772 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO }, 773 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, SOCF_RO }, 774 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, SOCF_RO } 775 }; 776 777 #endif 778 #if defined(BCM_88375_A0) 779 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM88375_A0r_fields[] = { 780 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO }, 781 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO }, 782 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, SOCF_RO }, 783 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, SOCF_RO } 784 }; 785 786 #endif 787 #if defined(BCM_88375_B0) 788 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM88375_B0r_fields[] = { 789 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, 0 }, 790 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, 0 }, 791 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, 0 }, 792 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, 0 } 793 }; 794 795 #endif 796 #if defined(BCM_88470_A0) 797 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM88470_A0r_fields[] = { 798 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO }, 799 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO }, 800 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, SOCF_RO }, 801 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, SOCF_RO } 802 }; 803 804 #endif 805 #if defined(BCM_88470_B0) 806 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM88470_B0r_fields[] = { 807 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, 0 }, 808 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, 0 }, 809 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, 0 }, 810 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, 0 } 811 }; 812 813 #endif 814 #if defined(BCM_88675_A0) 815 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM88675_A0r_fields[] = { 816 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO }, 817 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO }, 818 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, SOCF_RO }, 819 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, SOCF_RO } 820 }; 821 822 #endif 823 #if defined(BCM_88675_B0) 824 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM88675_B0r_fields[] = { 825 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, 0 }, 826 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, 0 }, 827 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, 0 }, 828 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, 0 } 829 }; 830 831 #endif 832 #if defined(BCM_88680_A0) 833 soc_field_info_t soc_XLMAC_CLEAR_ECC_STATUS_BCM88680_A0r_fields[] = { 834 { CLEAR_RX_CDC_DOUBLE_BIT_ERRf, 1, 1, 0 }, 835 { CLEAR_RX_CDC_SINGLE_BIT_ERRf, 1, 0, 0 }, 836 { CLEAR_TX_CDC_DOUBLE_BIT_ERRf, 1, 3, 0 }, 837 { CLEAR_TX_CDC_SINGLE_BIT_ERRf, 1, 2, 0 } 838 }; 839 840 #endif 841 #if defined(BCM_2801PM_A0) || defined(BCM_53400_A0) || \ 842 defined(BCM_56260_A0) || defined(BCM_56560_A0) || \ 843 defined(BCM_56960_A0) || defined(BCM_56965_A0) 844 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUSr_fields[] = { 845 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 846 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, SOCF_RO }, 847 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 848 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 849 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 850 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO }, 851 { RSVD_1f, 1, 0, SOCF_RO|SOCF_RES }, 852 { RSVD_2f, 1, 4, SOCF_RO|SOCF_RES } 853 }; 854 855 #endif 856 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 857 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM56850_A0r_fields[] = { 858 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 859 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 860 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 861 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 862 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO }, 863 { RSVD_1f, 1, 0, SOCF_RO|SOCF_RES }, 864 { RSVD_2f, 1, 4, SOCF_RO|SOCF_RES } 865 }; 866 867 #endif 868 #if defined(BCM_88270_A0) 869 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM88270_A0r_fields[] = { 870 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, 0 }, 871 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, 0 }, 872 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, 0 }, 873 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, 0 }, 874 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, 0 }, 875 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, 0 }, 876 { RSVD_1f, 1, 0, SOCF_RES }, 877 { RSVD_2f, 1, 4, SOCF_RES } 878 }; 879 880 #endif 881 #if defined(BCM_88375_A0) 882 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM88375_A0r_fields[] = { 883 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 884 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, SOCF_RO }, 885 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 886 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 887 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 888 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO }, 889 { RSVD_1f, 1, 0, SOCF_RO|SOCF_RES }, 890 { RSVD_2f, 1, 4, SOCF_RO|SOCF_RES } 891 }; 892 893 #endif 894 #if defined(BCM_88375_B0) 895 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM88375_B0r_fields[] = { 896 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, 0 }, 897 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, 0 }, 898 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, 0 }, 899 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, 0 }, 900 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, 0 }, 901 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, 0 }, 902 { RSVD_1f, 1, 0, SOCF_RES }, 903 { RSVD_2f, 1, 4, SOCF_RES } 904 }; 905 906 #endif 907 #if defined(BCM_88470_A0) 908 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM88470_A0r_fields[] = { 909 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 910 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, SOCF_RO }, 911 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 912 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 913 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 914 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO }, 915 { RSVD_1f, 1, 0, SOCF_RO|SOCF_RES }, 916 { RSVD_2f, 1, 4, SOCF_RO|SOCF_RES } 917 }; 918 919 #endif 920 #if defined(BCM_88470_B0) 921 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM88470_B0r_fields[] = { 922 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, 0 }, 923 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, 0 }, 924 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, 0 }, 925 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, 0 }, 926 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, 0 }, 927 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, 0 }, 928 { RSVD_1f, 1, 0, SOCF_RES }, 929 { RSVD_2f, 1, 4, SOCF_RES } 930 }; 931 932 #endif 933 #if defined(BCM_88675_A0) 934 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM88675_A0r_fields[] = { 935 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 936 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, SOCF_RO }, 937 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 938 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 939 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 940 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO }, 941 { RSVD_1f, 1, 0, SOCF_RO|SOCF_RES }, 942 { RSVD_2f, 1, 4, SOCF_RO|SOCF_RES } 943 }; 944 945 #endif 946 #if defined(BCM_88675_B0) 947 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM88675_B0r_fields[] = { 948 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, 0 }, 949 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, 0 }, 950 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, 0 }, 951 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, 0 }, 952 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, 0 }, 953 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, 0 }, 954 { RSVD_1f, 1, 0, SOCF_RES }, 955 { RSVD_2f, 1, 4, SOCF_RES } 956 }; 957 958 #endif 959 #if defined(BCM_88680_A0) 960 soc_field_info_t soc_XLMAC_CLEAR_FIFO_STATUS_BCM88680_A0r_fields[] = { 961 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, 0 }, 962 { CLEAR_RX_PKT_OVERFLOWf, 1, 7, 0 }, 963 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, 0 }, 964 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, 0 }, 965 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, 0 }, 966 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, 0 }, 967 { RSVD_1f, 1, 0, SOCF_RES }, 968 { RSVD_2f, 1, 4, SOCF_RES } 969 }; 970 971 #endif 972 #if defined(BCM_88675_A0) 973 soc_field_info_t soc_XLMAC_CLEAR_RX_LSS_STATUSr_fields[] = { 974 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 975 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 976 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 977 }; 978 979 #endif 980 #if defined(BCM_88270_A0) 981 soc_field_info_t soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88270_A0r_fields[] = { 982 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 983 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 984 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 985 }; 986 987 #endif 988 #if defined(BCM_88375_A0) 989 soc_field_info_t soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88375_A0r_fields[] = { 990 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 991 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 992 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 993 }; 994 995 #endif 996 #if defined(BCM_88375_B0) 997 soc_field_info_t soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88375_B0r_fields[] = { 998 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 999 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 1000 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 1001 }; 1002 1003 #endif 1004 #if defined(BCM_88470_A0) 1005 soc_field_info_t soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88470_A0r_fields[] = { 1006 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 1007 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 1008 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 1009 }; 1010 1011 #endif 1012 #if defined(BCM_88470_B0) 1013 soc_field_info_t soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88470_B0r_fields[] = { 1014 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 1015 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 1016 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 1017 }; 1018 1019 #endif 1020 #if defined(BCM_88675_B0) 1021 soc_field_info_t soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88675_B0r_fields[] = { 1022 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 1023 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 1024 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 1025 }; 1026 1027 #endif 1028 #if defined(BCM_88680_A0) 1029 soc_field_info_t soc_XLMAC_CLEAR_RX_LSS_STATUS_BCM88680_A0r_fields[] = { 1030 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 1031 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 1032 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 1033 }; 1034 1035 #endif 1036 #if defined(BCM_2801PM_A0) 1037 soc_field_info_t soc_XLMAC_CTRLr_fields[] = { 1038 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1039 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1040 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1041 { LOCAL_LPBKf, 1, 2, 0 }, 1042 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1043 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1044 { RSVD_1f, 1, 3, SOCF_RO|SOCF_SIG|SOCF_RES }, 1045 { RSVD_4f, 1, 7, SOCF_RES }, 1046 { RSVD_5f, 1, 9, SOCF_RES }, 1047 { RS_SOFT_RESETf, 1, 10, 0 }, 1048 { RX_ENf, 1, 1, 0 }, 1049 { SOFT_RESETf, 1, 6, 0 }, 1050 { SW_LINK_STATUSf, 1, 12, 0 }, 1051 { TX_ENf, 1, 0, 0 }, 1052 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1053 }; 1054 1055 #endif 1056 #if defined(BCM_53400_A0) || defined(BCM_56260_A0) || \ 1057 defined(BCM_56560_A0) || defined(BCM_56960_A0) || \ 1058 defined(BCM_56965_A0) 1059 soc_field_info_t soc_XLMAC_CTRL_BCM53400_A0r_fields[] = { 1060 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1061 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1062 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1063 { LOCAL_LPBKf, 1, 2, 0 }, 1064 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1065 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1066 { RSVD_1f, 1, 3, SOCF_RO|SOCF_RES }, 1067 { RSVD_4f, 1, 7, SOCF_RES }, 1068 { RSVD_5f, 1, 9, SOCF_RES }, 1069 { RS_SOFT_RESETf, 1, 10, 0 }, 1070 { RX_ENf, 1, 1, 0 }, 1071 { SOFT_RESETf, 1, 6, 0 }, 1072 { SW_LINK_STATUSf, 1, 12, 0 }, 1073 { TX_ENf, 1, 0, 0 }, 1074 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1075 }; 1076 1077 #endif 1078 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 1079 soc_field_info_t soc_XLMAC_CTRL_BCM56850_A0r_fields[] = { 1080 { DATA_MEMORY_TM_CTRLf, 2, 14, SOCF_LE }, 1081 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1082 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1083 { LOCAL_LPBKf, 1, 2, 0 }, 1084 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1085 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1086 { RSVD_1f, 1, 3, SOCF_RO|SOCF_RES }, 1087 { RSVD_4f, 1, 7, SOCF_RES }, 1088 { RSVD_5f, 1, 9, SOCF_RES }, 1089 { RS_SOFT_RESETf, 1, 10, 0 }, 1090 { RX_ENf, 1, 1, 0 }, 1091 { SOFT_RESETf, 1, 6, 0 }, 1092 { SW_LINK_STATUSf, 1, 12, 0 }, 1093 { TX_ENf, 1, 0, 0 }, 1094 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1095 }; 1096 1097 #endif 1098 #if defined(BCM_56860_A0) 1099 soc_field_info_t soc_XLMAC_CTRL_BCM56860_A0r_fields[] = { 1100 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1101 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1102 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1103 { LOCAL_LPBKf, 1, 2, 0 }, 1104 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1105 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1106 { RSVD_1f, 1, 3, SOCF_RES }, 1107 { RSVD_4f, 1, 7, SOCF_RES }, 1108 { RSVD_5f, 1, 9, SOCF_RES }, 1109 { RS_SOFT_RESETf, 1, 10, 0 }, 1110 { RX_ENf, 1, 1, 0 }, 1111 { SOFT_RESETf, 1, 6, 0 }, 1112 { SW_LINK_STATUSf, 1, 12, 0 }, 1113 { TX_ENf, 1, 0, 0 }, 1114 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1115 }; 1116 1117 #endif 1118 #if defined(BCM_88270_A0) 1119 soc_field_info_t soc_XLMAC_CTRL_BCM88270_A0r_fields[] = { 1120 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1121 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1122 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1123 { LOCAL_LPBKf, 1, 2, 0 }, 1124 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1125 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1126 { RSVD_1f, 1, 3, SOCF_RES }, 1127 { RSVD_4f, 1, 7, SOCF_RES }, 1128 { RSVD_5f, 1, 9, SOCF_RES }, 1129 { RS_SOFT_RESETf, 1, 10, 0 }, 1130 { RX_ENf, 1, 1, 0 }, 1131 { SOFT_RESETf, 1, 6, 0 }, 1132 { SW_LINK_STATUSf, 1, 12, 0 }, 1133 { TX_ENf, 1, 0, 0 }, 1134 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1135 }; 1136 1137 #endif 1138 #if defined(BCM_88375_A0) 1139 soc_field_info_t soc_XLMAC_CTRL_BCM88375_A0r_fields[] = { 1140 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1141 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1142 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1143 { LOCAL_LPBKf, 1, 2, 0 }, 1144 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1145 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1146 { RSVD_1f, 1, 3, SOCF_RO|SOCF_SIG|SOCF_RES }, 1147 { RSVD_4f, 1, 7, SOCF_RES }, 1148 { RSVD_5f, 1, 9, SOCF_RES }, 1149 { RS_SOFT_RESETf, 1, 10, 0 }, 1150 { RX_ENf, 1, 1, 0 }, 1151 { SOFT_RESETf, 1, 6, 0 }, 1152 { SW_LINK_STATUSf, 1, 12, 0 }, 1153 { TX_ENf, 1, 0, 0 }, 1154 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1155 }; 1156 1157 #endif 1158 #if defined(BCM_88375_B0) 1159 soc_field_info_t soc_XLMAC_CTRL_BCM88375_B0r_fields[] = { 1160 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1161 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1162 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1163 { LOCAL_LPBKf, 1, 2, 0 }, 1164 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1165 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1166 { RSVD_1f, 1, 3, SOCF_RES }, 1167 { RSVD_4f, 1, 7, SOCF_RES }, 1168 { RSVD_5f, 1, 9, SOCF_RES }, 1169 { RS_SOFT_RESETf, 1, 10, 0 }, 1170 { RX_ENf, 1, 1, 0 }, 1171 { SOFT_RESETf, 1, 6, 0 }, 1172 { SW_LINK_STATUSf, 1, 12, 0 }, 1173 { TX_ENf, 1, 0, 0 }, 1174 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1175 }; 1176 1177 #endif 1178 #if defined(BCM_88470_A0) 1179 soc_field_info_t soc_XLMAC_CTRL_BCM88470_A0r_fields[] = { 1180 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1181 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1182 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1183 { LOCAL_LPBKf, 1, 2, 0 }, 1184 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1185 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1186 { RSVD_1f, 1, 3, SOCF_RO|SOCF_SIG|SOCF_RES }, 1187 { RSVD_4f, 1, 7, SOCF_RES }, 1188 { RSVD_5f, 1, 9, SOCF_RES }, 1189 { RS_SOFT_RESETf, 1, 10, 0 }, 1190 { RX_ENf, 1, 1, 0 }, 1191 { SOFT_RESETf, 1, 6, 0 }, 1192 { SW_LINK_STATUSf, 1, 12, 0 }, 1193 { TX_ENf, 1, 0, 0 }, 1194 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1195 }; 1196 1197 #endif 1198 #if defined(BCM_88470_B0) 1199 soc_field_info_t soc_XLMAC_CTRL_BCM88470_B0r_fields[] = { 1200 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1201 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1202 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1203 { LOCAL_LPBKf, 1, 2, 0 }, 1204 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1205 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1206 { RSVD_1f, 1, 3, SOCF_RES }, 1207 { RSVD_4f, 1, 7, SOCF_RES }, 1208 { RSVD_5f, 1, 9, SOCF_RES }, 1209 { RS_SOFT_RESETf, 1, 10, 0 }, 1210 { RX_ENf, 1, 1, 0 }, 1211 { SOFT_RESETf, 1, 6, 0 }, 1212 { SW_LINK_STATUSf, 1, 12, 0 }, 1213 { TX_ENf, 1, 0, 0 }, 1214 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1215 }; 1216 1217 #endif 1218 #if defined(BCM_88675_A0) 1219 soc_field_info_t soc_XLMAC_CTRL_BCM88675_A0r_fields[] = { 1220 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1221 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1222 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1223 { LOCAL_LPBKf, 1, 2, 0 }, 1224 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1225 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1226 { RSVD_1f, 1, 3, SOCF_RO|SOCF_SIG|SOCF_RES }, 1227 { RSVD_4f, 1, 7, SOCF_RES }, 1228 { RSVD_5f, 1, 9, SOCF_RES }, 1229 { RS_SOFT_RESETf, 1, 10, 0 }, 1230 { RX_ENf, 1, 1, 0 }, 1231 { SOFT_RESETf, 1, 6, 0 }, 1232 { SW_LINK_STATUSf, 1, 12, 0 }, 1233 { TX_ENf, 1, 0, 0 }, 1234 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1235 }; 1236 1237 #endif 1238 #if defined(BCM_88675_B0) 1239 soc_field_info_t soc_XLMAC_CTRL_BCM88675_B0r_fields[] = { 1240 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1241 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1242 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1243 { LOCAL_LPBKf, 1, 2, 0 }, 1244 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1245 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1246 { RSVD_1f, 1, 3, SOCF_RES }, 1247 { RSVD_4f, 1, 7, SOCF_RES }, 1248 { RSVD_5f, 1, 9, SOCF_RES }, 1249 { RS_SOFT_RESETf, 1, 10, 0 }, 1250 { RX_ENf, 1, 1, 0 }, 1251 { SOFT_RESETf, 1, 6, 0 }, 1252 { SW_LINK_STATUSf, 1, 12, 0 }, 1253 { TX_ENf, 1, 0, 0 }, 1254 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1255 }; 1256 1257 #endif 1258 #if defined(BCM_88680_A0) 1259 soc_field_info_t soc_XLMAC_CTRL_BCM88680_A0r_fields[] = { 1260 { EXTENDED_HIG2_ENf, 1, 14, 0 }, 1261 { LAG_FAILOVER_ENf, 1, 5, 0 }, 1262 { LINK_STATUS_SELECTf, 1, 13, 0 }, 1263 { LOCAL_LPBKf, 1, 2, 0 }, 1264 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 1265 { REMOVE_FAILOVER_LPBKf, 1, 4, 0 }, 1266 { RSVD_1f, 1, 3, SOCF_RES }, 1267 { RSVD_4f, 1, 7, SOCF_RES }, 1268 { RSVD_5f, 1, 9, SOCF_RES }, 1269 { RS_SOFT_RESETf, 1, 10, 0 }, 1270 { RX_ENf, 1, 1, 0 }, 1271 { SOFT_RESETf, 1, 6, 0 }, 1272 { SW_LINK_STATUSf, 1, 12, 0 }, 1273 { TX_ENf, 1, 0, 0 }, 1274 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 } 1275 }; 1276 1277 #endif 1278 #if defined(BCM_88675_A0) 1279 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0r_fields[] = { 1280 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE } 1281 }; 1282 1283 #endif 1284 #if defined(BCM_88675_A0) 1285 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1r_fields[] = { 1286 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE } 1287 }; 1288 1289 #endif 1290 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 1291 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 1292 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 1293 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 1294 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1295 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1296 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 1297 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1298 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 1299 defined(BCM_56980_B0) 1300 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM53400_A0r_fields[] = { 1301 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE }, 1302 { E2ECC_DATA_HDR_0_HIf, 32, 32, SOCF_LE }, 1303 { E2ECC_DATA_HDR_0_LOf, 32, 0, SOCF_LE } 1304 }; 1305 1306 #endif 1307 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 1308 defined(BCM_56860_A0) 1309 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM56850_A0r_fields[] = { 1310 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE }, 1311 { E2ECC_DATA_HDR_0_HIf, 32, 32, SOCF_LE }, 1312 { E2ECC_DATA_HDR_0_LOf, 32, 0, SOCF_LE } 1313 }; 1314 1315 #endif 1316 #if defined(BCM_88270_A0) 1317 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM88270_A0r_fields[] = { 1318 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE } 1319 }; 1320 1321 #endif 1322 #if defined(BCM_88375_A0) 1323 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM88375_A0r_fields[] = { 1324 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE } 1325 }; 1326 1327 #endif 1328 #if defined(BCM_88375_B0) 1329 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM88375_B0r_fields[] = { 1330 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE } 1331 }; 1332 1333 #endif 1334 #if defined(BCM_88470_A0) 1335 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM88470_A0r_fields[] = { 1336 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE } 1337 }; 1338 1339 #endif 1340 #if defined(BCM_88470_B0) 1341 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM88470_B0r_fields[] = { 1342 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE } 1343 }; 1344 1345 #endif 1346 #if defined(BCM_88675_B0) 1347 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM88675_B0r_fields[] = { 1348 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE } 1349 }; 1350 1351 #endif 1352 #if defined(BCM_88680_A0) 1353 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_0_BCM88680_A0r_fields[] = { 1354 { E2ECC_DATA_HDR_0f, 64, 0, SOCF_LE } 1355 }; 1356 1357 #endif 1358 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 1359 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 1360 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 1361 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 1362 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1363 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1364 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 1365 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1366 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 1367 defined(BCM_56980_B0) 1368 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM53400_A0r_fields[] = { 1369 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE }, 1370 { E2ECC_DATA_HDR_1_HIf, 32, 32, SOCF_LE }, 1371 { E2ECC_DATA_HDR_1_LOf, 32, 0, SOCF_LE } 1372 }; 1373 1374 #endif 1375 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 1376 defined(BCM_56860_A0) 1377 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM56850_A0r_fields[] = { 1378 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE }, 1379 { E2ECC_DATA_HDR_1_HIf, 32, 32, SOCF_LE }, 1380 { E2ECC_DATA_HDR_1_LOf, 32, 0, SOCF_LE } 1381 }; 1382 1383 #endif 1384 #if defined(BCM_88270_A0) 1385 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM88270_A0r_fields[] = { 1386 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE } 1387 }; 1388 1389 #endif 1390 #if defined(BCM_88375_A0) 1391 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM88375_A0r_fields[] = { 1392 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE } 1393 }; 1394 1395 #endif 1396 #if defined(BCM_88375_B0) 1397 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM88375_B0r_fields[] = { 1398 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE } 1399 }; 1400 1401 #endif 1402 #if defined(BCM_88470_A0) 1403 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM88470_A0r_fields[] = { 1404 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE } 1405 }; 1406 1407 #endif 1408 #if defined(BCM_88470_B0) 1409 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM88470_B0r_fields[] = { 1410 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE } 1411 }; 1412 1413 #endif 1414 #if defined(BCM_88675_B0) 1415 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM88675_B0r_fields[] = { 1416 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE } 1417 }; 1418 1419 #endif 1420 #if defined(BCM_88680_A0) 1421 soc_field_info_t soc_XLMAC_E2ECC_DATA_HDR_1_BCM88680_A0r_fields[] = { 1422 { E2ECC_DATA_HDR_1f, 64, 0, SOCF_LE } 1423 }; 1424 1425 #endif 1426 #if defined(BCM_88675_A0) 1427 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0r_fields[] = { 1428 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1429 }; 1430 1431 #endif 1432 #if defined(BCM_88675_A0) 1433 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1r_fields[] = { 1434 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1435 }; 1436 1437 #endif 1438 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 1439 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 1440 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 1441 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 1442 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1443 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1444 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 1445 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1446 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 1447 defined(BCM_56980_B0) 1448 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM53400_A0r_fields[] = { 1449 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE }, 1450 { E2ECC_MODULE_HDR_0_HIf, 32, 32, SOCF_LE }, 1451 { E2ECC_MODULE_HDR_0_LOf, 32, 0, SOCF_LE } 1452 }; 1453 1454 #endif 1455 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 1456 defined(BCM_56860_A0) 1457 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM56850_A0r_fields[] = { 1458 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE }, 1459 { E2ECC_MODULE_HDR_0_HIf, 32, 32, SOCF_LE }, 1460 { E2ECC_MODULE_HDR_0_LOf, 32, 0, SOCF_LE } 1461 }; 1462 1463 #endif 1464 #if defined(BCM_88270_A0) 1465 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88270_A0r_fields[] = { 1466 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1467 }; 1468 1469 #endif 1470 #if defined(BCM_88375_A0) 1471 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88375_A0r_fields[] = { 1472 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1473 }; 1474 1475 #endif 1476 #if defined(BCM_88375_B0) 1477 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88375_B0r_fields[] = { 1478 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1479 }; 1480 1481 #endif 1482 #if defined(BCM_88470_A0) 1483 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88470_A0r_fields[] = { 1484 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1485 }; 1486 1487 #endif 1488 #if defined(BCM_88470_B0) 1489 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88470_B0r_fields[] = { 1490 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1491 }; 1492 1493 #endif 1494 #if defined(BCM_88675_B0) 1495 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88675_B0r_fields[] = { 1496 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1497 }; 1498 1499 #endif 1500 #if defined(BCM_88680_A0) 1501 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_0_BCM88680_A0r_fields[] = { 1502 { E2ECC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1503 }; 1504 1505 #endif 1506 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 1507 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 1508 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 1509 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 1510 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1511 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1512 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 1513 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1514 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 1515 defined(BCM_56980_B0) 1516 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM53400_A0r_fields[] = { 1517 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE }, 1518 { E2ECC_MODULE_HDR_1_HIf, 32, 32, SOCF_LE }, 1519 { E2ECC_MODULE_HDR_1_LOf, 32, 0, SOCF_LE } 1520 }; 1521 1522 #endif 1523 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 1524 defined(BCM_56860_A0) 1525 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM56850_A0r_fields[] = { 1526 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE }, 1527 { E2ECC_MODULE_HDR_1_HIf, 32, 32, SOCF_LE }, 1528 { E2ECC_MODULE_HDR_1_LOf, 32, 0, SOCF_LE } 1529 }; 1530 1531 #endif 1532 #if defined(BCM_88270_A0) 1533 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88270_A0r_fields[] = { 1534 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1535 }; 1536 1537 #endif 1538 #if defined(BCM_88375_A0) 1539 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88375_A0r_fields[] = { 1540 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1541 }; 1542 1543 #endif 1544 #if defined(BCM_88375_B0) 1545 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88375_B0r_fields[] = { 1546 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1547 }; 1548 1549 #endif 1550 #if defined(BCM_88470_A0) 1551 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88470_A0r_fields[] = { 1552 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1553 }; 1554 1555 #endif 1556 #if defined(BCM_88470_B0) 1557 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88470_B0r_fields[] = { 1558 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1559 }; 1560 1561 #endif 1562 #if defined(BCM_88675_B0) 1563 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88675_B0r_fields[] = { 1564 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1565 }; 1566 1567 #endif 1568 #if defined(BCM_88680_A0) 1569 soc_field_info_t soc_XLMAC_E2ECC_MODULE_HDR_1_BCM88680_A0r_fields[] = { 1570 { E2ECC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1571 }; 1572 1573 #endif 1574 #if defined(BCM_88675_A0) 1575 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0r_fields[] = { 1576 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE } 1577 }; 1578 1579 #endif 1580 #if defined(BCM_88675_A0) 1581 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1r_fields[] = { 1582 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE } 1583 }; 1584 1585 #endif 1586 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 1587 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 1588 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 1589 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 1590 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1591 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1592 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 1593 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1594 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 1595 defined(BCM_56980_B0) 1596 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM53400_A0r_fields[] = { 1597 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE }, 1598 { E2EFC_DATA_HDR_0_HIf, 32, 32, SOCF_LE }, 1599 { E2EFC_DATA_HDR_0_LOf, 32, 0, SOCF_LE } 1600 }; 1601 1602 #endif 1603 #if defined(BCM_56150_A0) || defined(BCM_56860_A0) 1604 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM56150_A0r_fields[] = { 1605 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE }, 1606 { E2EFC_DATA_HDR_0_HIf, 32, 32, SOCF_LE }, 1607 { E2EFC_DATA_HDR_0_LOf, 32, 0, SOCF_LE } 1608 }; 1609 1610 #endif 1611 #if defined(BCM_88270_A0) 1612 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM88270_A0r_fields[] = { 1613 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE } 1614 }; 1615 1616 #endif 1617 #if defined(BCM_88375_A0) 1618 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM88375_A0r_fields[] = { 1619 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE } 1620 }; 1621 1622 #endif 1623 #if defined(BCM_88375_B0) 1624 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM88375_B0r_fields[] = { 1625 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE } 1626 }; 1627 1628 #endif 1629 #if defined(BCM_88470_A0) 1630 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM88470_A0r_fields[] = { 1631 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE } 1632 }; 1633 1634 #endif 1635 #if defined(BCM_88470_B0) 1636 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM88470_B0r_fields[] = { 1637 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE } 1638 }; 1639 1640 #endif 1641 #if defined(BCM_88675_B0) 1642 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM88675_B0r_fields[] = { 1643 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE } 1644 }; 1645 1646 #endif 1647 #if defined(BCM_88680_A0) 1648 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_0_BCM88680_A0r_fields[] = { 1649 { E2EFC_DATA_HDR_0f, 64, 0, SOCF_LE } 1650 }; 1651 1652 #endif 1653 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 1654 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 1655 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 1656 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 1657 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1658 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1659 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 1660 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1661 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 1662 defined(BCM_56980_B0) 1663 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM53400_A0r_fields[] = { 1664 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE }, 1665 { E2EFC_DATA_HDR_1_HIf, 32, 32, SOCF_LE }, 1666 { E2EFC_DATA_HDR_1_LOf, 32, 0, SOCF_LE } 1667 }; 1668 1669 #endif 1670 #if defined(BCM_56150_A0) || defined(BCM_56860_A0) 1671 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM56150_A0r_fields[] = { 1672 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE }, 1673 { E2EFC_DATA_HDR_1_HIf, 32, 32, SOCF_LE }, 1674 { E2EFC_DATA_HDR_1_LOf, 32, 0, SOCF_LE } 1675 }; 1676 1677 #endif 1678 #if defined(BCM_88270_A0) 1679 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM88270_A0r_fields[] = { 1680 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE } 1681 }; 1682 1683 #endif 1684 #if defined(BCM_88375_A0) 1685 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM88375_A0r_fields[] = { 1686 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE } 1687 }; 1688 1689 #endif 1690 #if defined(BCM_88375_B0) 1691 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM88375_B0r_fields[] = { 1692 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE } 1693 }; 1694 1695 #endif 1696 #if defined(BCM_88470_A0) 1697 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM88470_A0r_fields[] = { 1698 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE } 1699 }; 1700 1701 #endif 1702 #if defined(BCM_88470_B0) 1703 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM88470_B0r_fields[] = { 1704 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE } 1705 }; 1706 1707 #endif 1708 #if defined(BCM_88675_B0) 1709 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM88675_B0r_fields[] = { 1710 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE } 1711 }; 1712 1713 #endif 1714 #if defined(BCM_88680_A0) 1715 soc_field_info_t soc_XLMAC_E2EFC_DATA_HDR_1_BCM88680_A0r_fields[] = { 1716 { E2EFC_DATA_HDR_1f, 64, 0, SOCF_LE } 1717 }; 1718 1719 #endif 1720 #if defined(BCM_88675_A0) 1721 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0r_fields[] = { 1722 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1723 }; 1724 1725 #endif 1726 #if defined(BCM_88675_A0) 1727 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1r_fields[] = { 1728 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1729 }; 1730 1731 #endif 1732 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 1733 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 1734 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 1735 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 1736 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1737 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1738 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 1739 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1740 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 1741 defined(BCM_56980_B0) 1742 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM53400_A0r_fields[] = { 1743 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE }, 1744 { E2EFC_MODULE_HDR_0_HIf, 32, 32, SOCF_LE }, 1745 { E2EFC_MODULE_HDR_0_LOf, 32, 0, SOCF_LE } 1746 }; 1747 1748 #endif 1749 #if defined(BCM_56150_A0) || defined(BCM_56860_A0) 1750 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM56150_A0r_fields[] = { 1751 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE }, 1752 { E2EFC_MODULE_HDR_0_HIf, 32, 32, SOCF_LE }, 1753 { E2EFC_MODULE_HDR_0_LOf, 32, 0, SOCF_LE } 1754 }; 1755 1756 #endif 1757 #if defined(BCM_88270_A0) 1758 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88270_A0r_fields[] = { 1759 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1760 }; 1761 1762 #endif 1763 #if defined(BCM_88375_A0) 1764 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88375_A0r_fields[] = { 1765 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1766 }; 1767 1768 #endif 1769 #if defined(BCM_88375_B0) 1770 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88375_B0r_fields[] = { 1771 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1772 }; 1773 1774 #endif 1775 #if defined(BCM_88470_A0) 1776 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88470_A0r_fields[] = { 1777 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1778 }; 1779 1780 #endif 1781 #if defined(BCM_88470_B0) 1782 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88470_B0r_fields[] = { 1783 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1784 }; 1785 1786 #endif 1787 #if defined(BCM_88675_B0) 1788 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88675_B0r_fields[] = { 1789 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1790 }; 1791 1792 #endif 1793 #if defined(BCM_88680_A0) 1794 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_0_BCM88680_A0r_fields[] = { 1795 { E2EFC_MODULE_HDR_0f, 64, 0, SOCF_LE } 1796 }; 1797 1798 #endif 1799 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 1800 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 1801 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 1802 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 1803 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1804 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1805 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 1806 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1807 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 1808 defined(BCM_56980_B0) 1809 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM53400_A0r_fields[] = { 1810 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE }, 1811 { E2EFC_MODULE_HDR_1_HIf, 32, 32, SOCF_LE }, 1812 { E2EFC_MODULE_HDR_1_LOf, 32, 0, SOCF_LE } 1813 }; 1814 1815 #endif 1816 #if defined(BCM_56150_A0) || defined(BCM_56860_A0) 1817 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM56150_A0r_fields[] = { 1818 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE }, 1819 { E2EFC_MODULE_HDR_1_HIf, 32, 32, SOCF_LE }, 1820 { E2EFC_MODULE_HDR_1_LOf, 32, 0, SOCF_LE } 1821 }; 1822 1823 #endif 1824 #if defined(BCM_88270_A0) 1825 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88270_A0r_fields[] = { 1826 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1827 }; 1828 1829 #endif 1830 #if defined(BCM_88375_A0) 1831 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88375_A0r_fields[] = { 1832 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1833 }; 1834 1835 #endif 1836 #if defined(BCM_88375_B0) 1837 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88375_B0r_fields[] = { 1838 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1839 }; 1840 1841 #endif 1842 #if defined(BCM_88470_A0) 1843 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88470_A0r_fields[] = { 1844 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1845 }; 1846 1847 #endif 1848 #if defined(BCM_88470_B0) 1849 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88470_B0r_fields[] = { 1850 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1851 }; 1852 1853 #endif 1854 #if defined(BCM_88675_B0) 1855 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88675_B0r_fields[] = { 1856 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1857 }; 1858 1859 #endif 1860 #if defined(BCM_88680_A0) 1861 soc_field_info_t soc_XLMAC_E2EFC_MODULE_HDR_1_BCM88680_A0r_fields[] = { 1862 { E2EFC_MODULE_HDR_1f, 64, 0, SOCF_LE } 1863 }; 1864 1865 #endif 1866 #if defined(BCM_88675_A0) 1867 soc_field_info_t soc_XLMAC_E2E_CTRLr_fields[] = { 1868 { E2ECC_DUAL_MODID_ENf, 1, 2, 0 }, 1869 { E2ECC_LEGACY_IMP_ENf, 1, 3, 0 }, 1870 { E2EFC_DUAL_MODID_ENf, 1, 4, 0 }, 1871 { E2E_ENABLEf, 1, 0, 0 }, 1872 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1873 }; 1874 1875 #endif 1876 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 1877 soc_field_info_t soc_XLMAC_E2E_CTRL_BCM56850_A0r_fields[] = { 1878 { DUAL_MODID_ENf, 1, 2, 0 }, 1879 { E2E_ENABLEf, 1, 0, 0 }, 1880 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1881 }; 1882 1883 #endif 1884 #if defined(BCM_88270_A0) 1885 soc_field_info_t soc_XLMAC_E2E_CTRL_BCM88270_A0r_fields[] = { 1886 { E2ECC_DUAL_MODID_ENf, 1, 2, 0 }, 1887 { E2ECC_LEGACY_IMP_ENf, 1, 3, 0 }, 1888 { E2EFC_DUAL_MODID_ENf, 1, 4, 0 }, 1889 { E2E_ENABLEf, 1, 0, 0 }, 1890 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1891 }; 1892 1893 #endif 1894 #if defined(BCM_88375_A0) 1895 soc_field_info_t soc_XLMAC_E2E_CTRL_BCM88375_A0r_fields[] = { 1896 { E2ECC_DUAL_MODID_ENf, 1, 2, 0 }, 1897 { E2ECC_LEGACY_IMP_ENf, 1, 3, 0 }, 1898 { E2EFC_DUAL_MODID_ENf, 1, 4, 0 }, 1899 { E2E_ENABLEf, 1, 0, 0 }, 1900 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1901 }; 1902 1903 #endif 1904 #if defined(BCM_88375_B0) 1905 soc_field_info_t soc_XLMAC_E2E_CTRL_BCM88375_B0r_fields[] = { 1906 { E2ECC_DUAL_MODID_ENf, 1, 2, 0 }, 1907 { E2ECC_LEGACY_IMP_ENf, 1, 3, 0 }, 1908 { E2EFC_DUAL_MODID_ENf, 1, 4, 0 }, 1909 { E2E_ENABLEf, 1, 0, 0 }, 1910 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1911 }; 1912 1913 #endif 1914 #if defined(BCM_88470_A0) 1915 soc_field_info_t soc_XLMAC_E2E_CTRL_BCM88470_A0r_fields[] = { 1916 { E2ECC_DUAL_MODID_ENf, 1, 2, 0 }, 1917 { E2ECC_LEGACY_IMP_ENf, 1, 3, 0 }, 1918 { E2EFC_DUAL_MODID_ENf, 1, 4, 0 }, 1919 { E2E_ENABLEf, 1, 0, 0 }, 1920 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1921 }; 1922 1923 #endif 1924 #if defined(BCM_88470_B0) 1925 soc_field_info_t soc_XLMAC_E2E_CTRL_BCM88470_B0r_fields[] = { 1926 { E2ECC_DUAL_MODID_ENf, 1, 2, 0 }, 1927 { E2ECC_LEGACY_IMP_ENf, 1, 3, 0 }, 1928 { E2EFC_DUAL_MODID_ENf, 1, 4, 0 }, 1929 { E2E_ENABLEf, 1, 0, 0 }, 1930 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1931 }; 1932 1933 #endif 1934 #if defined(BCM_88675_B0) 1935 soc_field_info_t soc_XLMAC_E2E_CTRL_BCM88675_B0r_fields[] = { 1936 { E2ECC_DUAL_MODID_ENf, 1, 2, 0 }, 1937 { E2ECC_LEGACY_IMP_ENf, 1, 3, 0 }, 1938 { E2EFC_DUAL_MODID_ENf, 1, 4, 0 }, 1939 { E2E_ENABLEf, 1, 0, 0 }, 1940 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1941 }; 1942 1943 #endif 1944 #if defined(BCM_88680_A0) 1945 soc_field_info_t soc_XLMAC_E2E_CTRL_BCM88680_A0r_fields[] = { 1946 { E2ECC_DUAL_MODID_ENf, 1, 2, 0 }, 1947 { E2ECC_LEGACY_IMP_ENf, 1, 3, 0 }, 1948 { E2EFC_DUAL_MODID_ENf, 1, 4, 0 }, 1949 { E2E_ENABLEf, 1, 0, 0 }, 1950 { HONOR_PAUSE_FOR_E2Ef, 1, 1, 0 } 1951 }; 1952 1953 #endif 1954 #if defined(BCM_2801PM_A0) || defined(BCM_53400_A0) || \ 1955 defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 1956 defined(BCM_56160_A0) || defined(BCM_56260_A0) || \ 1957 defined(BCM_56260_B0) || defined(BCM_56270_A0) || \ 1958 defined(BCM_56370_A0) || defined(BCM_56560_A0) || \ 1959 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 1960 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 1961 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 1962 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 1963 defined(BCM_56980_A0) || defined(BCM_56980_B0) 1964 soc_field_info_t soc_XLMAC_ECC_CTRLr_fields[] = { 1965 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 1966 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 1967 }; 1968 1969 #endif 1970 #if defined(BCM_56860_A0) 1971 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM56860_A0r_fields[] = { 1972 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 1973 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 1974 }; 1975 1976 #endif 1977 #if defined(BCM_88270_A0) 1978 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM88270_A0r_fields[] = { 1979 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 1980 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 1981 }; 1982 1983 #endif 1984 #if defined(BCM_88375_A0) 1985 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM88375_A0r_fields[] = { 1986 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 1987 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 1988 }; 1989 1990 #endif 1991 #if defined(BCM_88375_B0) 1992 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM88375_B0r_fields[] = { 1993 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 1994 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 1995 }; 1996 1997 #endif 1998 #if defined(BCM_88470_A0) 1999 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM88470_A0r_fields[] = { 2000 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 2001 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 2002 }; 2003 2004 #endif 2005 #if defined(BCM_88470_B0) 2006 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM88470_B0r_fields[] = { 2007 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 2008 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 2009 }; 2010 2011 #endif 2012 #if defined(BCM_88675_A0) 2013 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM88675_A0r_fields[] = { 2014 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 2015 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 2016 }; 2017 2018 #endif 2019 #if defined(BCM_88675_B0) 2020 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM88675_B0r_fields[] = { 2021 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 2022 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 2023 }; 2024 2025 #endif 2026 #if defined(BCM_88680_A0) 2027 soc_field_info_t soc_XLMAC_ECC_CTRL_BCM88680_A0r_fields[] = { 2028 { RX_CDC_ECC_CTRL_ENf, 1, 0, 0 }, 2029 { TX_CDC_ECC_CTRL_ENf, 1, 1, 0 } 2030 }; 2031 2032 #endif 2033 #if defined(BCM_2801PM_A0) || defined(BCM_53400_A0) || \ 2034 defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 2035 defined(BCM_56160_A0) || defined(BCM_56260_A0) || \ 2036 defined(BCM_56260_B0) || defined(BCM_56270_A0) || \ 2037 defined(BCM_56370_A0) || defined(BCM_56560_A0) || \ 2038 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 2039 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 2040 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 2041 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 2042 defined(BCM_56980_A0) || defined(BCM_56980_B0) 2043 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERRr_fields[] = { 2044 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2045 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2046 }; 2047 2048 #endif 2049 #if defined(BCM_56860_A0) 2050 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM56860_A0r_fields[] = { 2051 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2052 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2053 }; 2054 2055 #endif 2056 #if defined(BCM_88270_A0) 2057 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88270_A0r_fields[] = { 2058 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2059 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2060 }; 2061 2062 #endif 2063 #if defined(BCM_88375_A0) 2064 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88375_A0r_fields[] = { 2065 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2066 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2067 }; 2068 2069 #endif 2070 #if defined(BCM_88375_B0) 2071 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88375_B0r_fields[] = { 2072 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2073 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2074 }; 2075 2076 #endif 2077 #if defined(BCM_88470_A0) 2078 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88470_A0r_fields[] = { 2079 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2080 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2081 }; 2082 2083 #endif 2084 #if defined(BCM_88470_B0) 2085 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88470_B0r_fields[] = { 2086 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2087 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2088 }; 2089 2090 #endif 2091 #if defined(BCM_88675_A0) 2092 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88675_A0r_fields[] = { 2093 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2094 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2095 }; 2096 2097 #endif 2098 #if defined(BCM_88675_B0) 2099 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88675_B0r_fields[] = { 2100 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2101 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2102 }; 2103 2104 #endif 2105 #if defined(BCM_88680_A0) 2106 soc_field_info_t soc_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_BCM88680_A0r_fields[] = { 2107 { RX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 0, 0 }, 2108 { TX_CDC_FORCE_DOUBLE_BIT_ERRf, 1, 1, 0 } 2109 }; 2110 2111 #endif 2112 #if defined(BCM_2801PM_A0) || defined(BCM_53400_A0) || \ 2113 defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 2114 defined(BCM_56160_A0) || defined(BCM_56260_A0) || \ 2115 defined(BCM_56260_B0) || defined(BCM_56270_A0) || \ 2116 defined(BCM_56370_A0) || defined(BCM_56560_A0) || \ 2117 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 2118 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 2119 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 2120 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 2121 defined(BCM_56980_A0) || defined(BCM_56980_B0) 2122 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERRr_fields[] = { 2123 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2124 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2125 }; 2126 2127 #endif 2128 #if defined(BCM_56860_A0) 2129 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM56860_A0r_fields[] = { 2130 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2131 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2132 }; 2133 2134 #endif 2135 #if defined(BCM_88270_A0) 2136 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88270_A0r_fields[] = { 2137 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2138 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2139 }; 2140 2141 #endif 2142 #if defined(BCM_88375_A0) 2143 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88375_A0r_fields[] = { 2144 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2145 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2146 }; 2147 2148 #endif 2149 #if defined(BCM_88375_B0) 2150 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88375_B0r_fields[] = { 2151 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2152 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2153 }; 2154 2155 #endif 2156 #if defined(BCM_88470_A0) 2157 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88470_A0r_fields[] = { 2158 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2159 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2160 }; 2161 2162 #endif 2163 #if defined(BCM_88470_B0) 2164 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88470_B0r_fields[] = { 2165 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2166 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2167 }; 2168 2169 #endif 2170 #if defined(BCM_88675_A0) 2171 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88675_A0r_fields[] = { 2172 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2173 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2174 }; 2175 2176 #endif 2177 #if defined(BCM_88675_B0) 2178 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88675_B0r_fields[] = { 2179 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2180 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2181 }; 2182 2183 #endif 2184 #if defined(BCM_88680_A0) 2185 soc_field_info_t soc_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_BCM88680_A0r_fields[] = { 2186 { RX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 0, 0 }, 2187 { TX_CDC_FORCE_SINGLE_BIT_ERRf, 1, 1, 0 } 2188 }; 2189 2190 #endif 2191 #if defined(BCM_88675_A0) 2192 soc_field_info_t soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields[] = { 2193 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE } 2194 }; 2195 2196 #endif 2197 #if defined(BCM_88270_A0) 2198 soc_field_info_t soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88270_A0r_fields[] = { 2199 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE } 2200 }; 2201 2202 #endif 2203 #if defined(BCM_88375_A0) 2204 soc_field_info_t soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88375_A0r_fields[] = { 2205 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE } 2206 }; 2207 2208 #endif 2209 #if defined(BCM_88375_B0) 2210 soc_field_info_t soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88375_B0r_fields[] = { 2211 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE } 2212 }; 2213 2214 #endif 2215 #if defined(BCM_88470_A0) 2216 soc_field_info_t soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88470_A0r_fields[] = { 2217 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE } 2218 }; 2219 2220 #endif 2221 #if defined(BCM_88470_B0) 2222 soc_field_info_t soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88470_B0r_fields[] = { 2223 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE } 2224 }; 2225 2226 #endif 2227 #if defined(BCM_88675_B0) 2228 soc_field_info_t soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88675_B0r_fields[] = { 2229 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE } 2230 }; 2231 2232 #endif 2233 #if defined(BCM_88680_A0) 2234 soc_field_info_t soc_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88680_A0r_fields[] = { 2235 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE } 2236 }; 2237 2238 #endif 2239 #if defined(BCM_88675_A0) 2240 soc_field_info_t soc_XLMAC_EEE_CTRLr_fields[] = { 2241 { EEE_ENf, 1, 0, 0 }, 2242 { RSVDf, 1, 1, SOCF_RES } 2243 }; 2244 2245 #endif 2246 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 2247 defined(BCM_56860_A0) 2248 soc_field_info_t soc_XLMAC_EEE_CTRL_BCM56850_A0r_fields[] = { 2249 { EEE_ENf, 1, 0, 0 }, 2250 { RSVDf, 1, 1, SOCF_RES } 2251 }; 2252 2253 #endif 2254 #if defined(BCM_88270_A0) 2255 soc_field_info_t soc_XLMAC_EEE_CTRL_BCM88270_A0r_fields[] = { 2256 { EEE_ENf, 1, 0, 0 }, 2257 { RSVDf, 1, 1, SOCF_RES } 2258 }; 2259 2260 #endif 2261 #if defined(BCM_88375_A0) 2262 soc_field_info_t soc_XLMAC_EEE_CTRL_BCM88375_A0r_fields[] = { 2263 { EEE_ENf, 1, 0, 0 }, 2264 { RSVDf, 1, 1, SOCF_RES } 2265 }; 2266 2267 #endif 2268 #if defined(BCM_88375_B0) 2269 soc_field_info_t soc_XLMAC_EEE_CTRL_BCM88375_B0r_fields[] = { 2270 { EEE_ENf, 1, 0, 0 }, 2271 { RSVDf, 1, 1, SOCF_RES } 2272 }; 2273 2274 #endif 2275 #if defined(BCM_88470_A0) 2276 soc_field_info_t soc_XLMAC_EEE_CTRL_BCM88470_A0r_fields[] = { 2277 { EEE_ENf, 1, 0, 0 }, 2278 { RSVDf, 1, 1, SOCF_RES } 2279 }; 2280 2281 #endif 2282 #if defined(BCM_88470_B0) 2283 soc_field_info_t soc_XLMAC_EEE_CTRL_BCM88470_B0r_fields[] = { 2284 { EEE_ENf, 1, 0, 0 }, 2285 { RSVDf, 1, 1, SOCF_RES } 2286 }; 2287 2288 #endif 2289 #if defined(BCM_88675_B0) 2290 soc_field_info_t soc_XLMAC_EEE_CTRL_BCM88675_B0r_fields[] = { 2291 { EEE_ENf, 1, 0, 0 }, 2292 { RSVDf, 1, 1, SOCF_RES } 2293 }; 2294 2295 #endif 2296 #if defined(BCM_88680_A0) 2297 soc_field_info_t soc_XLMAC_EEE_CTRL_BCM88680_A0r_fields[] = { 2298 { EEE_ENf, 1, 0, 0 }, 2299 { RSVDf, 1, 1, SOCF_RES } 2300 }; 2301 2302 #endif 2303 #if defined(BCM_88675_A0) 2304 soc_field_info_t soc_XLMAC_EEE_TIMERSr_fields[] = { 2305 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2306 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2307 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE } 2308 }; 2309 2310 #endif 2311 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 2312 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 2313 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 2314 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 2315 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 2316 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 2317 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 2318 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 2319 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 2320 defined(BCM_56980_B0) 2321 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM53400_A0r_fields[] = { 2322 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2323 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2324 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE }, 2325 { XLMAC_EEE_TIMERS_HIf, 32, 32, SOCF_LE }, 2326 { XLMAC_EEE_TIMERS_LOf, 32, 0, SOCF_LE } 2327 }; 2328 2329 #endif 2330 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 2331 defined(BCM_56860_A0) 2332 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM56850_A0r_fields[] = { 2333 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2334 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2335 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE }, 2336 { XLMAC_EEE_TIMERS_HIf, 32, 32, SOCF_LE }, 2337 { XLMAC_EEE_TIMERS_LOf, 32, 0, SOCF_LE } 2338 }; 2339 2340 #endif 2341 #if defined(BCM_88270_A0) 2342 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM88270_A0r_fields[] = { 2343 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2344 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2345 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE } 2346 }; 2347 2348 #endif 2349 #if defined(BCM_88375_A0) 2350 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM88375_A0r_fields[] = { 2351 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2352 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2353 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE } 2354 }; 2355 2356 #endif 2357 #if defined(BCM_88375_B0) 2358 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM88375_B0r_fields[] = { 2359 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2360 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2361 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE } 2362 }; 2363 2364 #endif 2365 #if defined(BCM_88470_A0) 2366 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM88470_A0r_fields[] = { 2367 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2368 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2369 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE } 2370 }; 2371 2372 #endif 2373 #if defined(BCM_88470_B0) 2374 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM88470_B0r_fields[] = { 2375 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2376 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2377 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE } 2378 }; 2379 2380 #endif 2381 #if defined(BCM_88675_B0) 2382 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM88675_B0r_fields[] = { 2383 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2384 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2385 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE } 2386 }; 2387 2388 #endif 2389 #if defined(BCM_88680_A0) 2390 soc_field_info_t soc_XLMAC_EEE_TIMERS_BCM88680_A0r_fields[] = { 2391 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 2392 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 2393 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE } 2394 }; 2395 2396 #endif 2397 #if defined(BCM_88675_A0) 2398 soc_field_info_t soc_XLMAC_FIFO_STATUSr_fields[] = { 2399 { LINK_STATUSf, 1, 8, SOCF_RO|SOCF_SIG }, 2400 { RSVD_1f, 1, 0, SOCF_RO|SOCF_SIG|SOCF_RES }, 2401 { RSVD_2f, 1, 4, SOCF_RO|SOCF_SIG|SOCF_RES }, 2402 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 2403 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO|SOCF_SIG }, 2404 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 2405 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 2406 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 2407 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 2408 }; 2409 2410 #endif 2411 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 2412 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 2413 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 2414 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 2415 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 2416 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 2417 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 2418 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 2419 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 2420 defined(BCM_56980_B0) 2421 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM53400_A0r_fields[] = { 2422 { LINK_STATUSf, 1, 8, SOCF_RO }, 2423 { RSVD_1f, 1, 0, SOCF_RO|SOCF_RES }, 2424 { RSVD_2f, 1, 4, SOCF_RO|SOCF_RES }, 2425 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 2426 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO }, 2427 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 2428 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 2429 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 2430 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 2431 }; 2432 2433 #endif 2434 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 2435 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM56850_A0r_fields[] = { 2436 { LINK_STATUSf, 1, 7, SOCF_RO }, 2437 { RSVD_1f, 1, 0, SOCF_RO|SOCF_RES }, 2438 { RSVD_2f, 1, 4, SOCF_RO|SOCF_RES }, 2439 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 2440 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 2441 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 2442 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 2443 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 2444 }; 2445 2446 #endif 2447 #if defined(BCM_88270_A0) 2448 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM88270_A0r_fields[] = { 2449 { LINK_STATUSf, 1, 8, SOCF_RO|SOCF_SIG }, 2450 { RSVD_1f, 1, 0, SOCF_RO|SOCF_SIG|SOCF_RES }, 2451 { RSVD_2f, 1, 4, SOCF_RO|SOCF_SIG|SOCF_RES }, 2452 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 2453 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO|SOCF_SIG }, 2454 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 2455 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 2456 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 2457 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 2458 }; 2459 2460 #endif 2461 #if defined(BCM_88375_A0) 2462 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM88375_A0r_fields[] = { 2463 { LINK_STATUSf, 1, 8, SOCF_RO|SOCF_SIG }, 2464 { RSVD_1f, 1, 0, SOCF_RO|SOCF_SIG|SOCF_RES }, 2465 { RSVD_2f, 1, 4, SOCF_RO|SOCF_SIG|SOCF_RES }, 2466 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 2467 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO|SOCF_SIG }, 2468 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 2469 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 2470 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 2471 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 2472 }; 2473 2474 #endif 2475 #if defined(BCM_88375_B0) 2476 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM88375_B0r_fields[] = { 2477 { LINK_STATUSf, 1, 8, SOCF_RO|SOCF_SIG }, 2478 { RSVD_1f, 1, 0, SOCF_RO|SOCF_SIG|SOCF_RES }, 2479 { RSVD_2f, 1, 4, SOCF_RO|SOCF_SIG|SOCF_RES }, 2480 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 2481 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO|SOCF_SIG }, 2482 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 2483 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 2484 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 2485 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 2486 }; 2487 2488 #endif 2489 #if defined(BCM_88470_A0) 2490 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM88470_A0r_fields[] = { 2491 { LINK_STATUSf, 1, 8, SOCF_RO|SOCF_SIG }, 2492 { RSVD_1f, 1, 0, SOCF_RO|SOCF_SIG|SOCF_RES }, 2493 { RSVD_2f, 1, 4, SOCF_RO|SOCF_SIG|SOCF_RES }, 2494 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 2495 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO|SOCF_SIG }, 2496 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 2497 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 2498 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 2499 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 2500 }; 2501 2502 #endif 2503 #if defined(BCM_88470_B0) 2504 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM88470_B0r_fields[] = { 2505 { LINK_STATUSf, 1, 8, SOCF_RO|SOCF_SIG }, 2506 { RSVD_1f, 1, 0, SOCF_RO|SOCF_SIG|SOCF_RES }, 2507 { RSVD_2f, 1, 4, SOCF_RO|SOCF_SIG|SOCF_RES }, 2508 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 2509 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO|SOCF_SIG }, 2510 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 2511 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 2512 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 2513 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 2514 }; 2515 2516 #endif 2517 #if defined(BCM_88675_B0) 2518 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM88675_B0r_fields[] = { 2519 { LINK_STATUSf, 1, 8, SOCF_RO|SOCF_SIG }, 2520 { RSVD_1f, 1, 0, SOCF_RO|SOCF_SIG|SOCF_RES }, 2521 { RSVD_2f, 1, 4, SOCF_RO|SOCF_SIG|SOCF_RES }, 2522 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 2523 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO|SOCF_SIG }, 2524 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 2525 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 2526 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 2527 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 2528 }; 2529 2530 #endif 2531 #if defined(BCM_88680_A0) 2532 soc_field_info_t soc_XLMAC_FIFO_STATUS_BCM88680_A0r_fields[] = { 2533 { LINK_STATUSf, 1, 8, SOCF_RO|SOCF_SIG }, 2534 { RSVD_1f, 1, 0, SOCF_RO|SOCF_SIG|SOCF_RES }, 2535 { RSVD_2f, 1, 4, SOCF_RO|SOCF_SIG|SOCF_RES }, 2536 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 2537 { RX_PKT_OVERFLOWf, 1, 7, SOCF_RO|SOCF_SIG }, 2538 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 2539 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 2540 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 2541 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 2542 }; 2543 2544 #endif 2545 #if defined(BCM_88675_A0) 2546 soc_field_info_t soc_XLMAC_GMII_EEE_CTRLr_fields[] = { 2547 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2548 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2549 }; 2550 2551 #endif 2552 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 2553 defined(BCM_56860_A0) 2554 soc_field_info_t soc_XLMAC_GMII_EEE_CTRL_BCM56850_A0r_fields[] = { 2555 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2556 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2557 }; 2558 2559 #endif 2560 #if defined(BCM_88270_A0) 2561 soc_field_info_t soc_XLMAC_GMII_EEE_CTRL_BCM88270_A0r_fields[] = { 2562 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2563 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2564 }; 2565 2566 #endif 2567 #if defined(BCM_88375_A0) 2568 soc_field_info_t soc_XLMAC_GMII_EEE_CTRL_BCM88375_A0r_fields[] = { 2569 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2570 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2571 }; 2572 2573 #endif 2574 #if defined(BCM_88375_B0) 2575 soc_field_info_t soc_XLMAC_GMII_EEE_CTRL_BCM88375_B0r_fields[] = { 2576 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2577 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2578 }; 2579 2580 #endif 2581 #if defined(BCM_88470_A0) 2582 soc_field_info_t soc_XLMAC_GMII_EEE_CTRL_BCM88470_A0r_fields[] = { 2583 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2584 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2585 }; 2586 2587 #endif 2588 #if defined(BCM_88470_B0) 2589 soc_field_info_t soc_XLMAC_GMII_EEE_CTRL_BCM88470_B0r_fields[] = { 2590 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2591 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2592 }; 2593 2594 #endif 2595 #if defined(BCM_88675_B0) 2596 soc_field_info_t soc_XLMAC_GMII_EEE_CTRL_BCM88675_B0r_fields[] = { 2597 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2598 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2599 }; 2600 2601 #endif 2602 #if defined(BCM_88680_A0) 2603 soc_field_info_t soc_XLMAC_GMII_EEE_CTRL_BCM88680_A0r_fields[] = { 2604 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 2605 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE } 2606 }; 2607 2608 #endif 2609 #if defined(BCM_88675_A0) 2610 soc_field_info_t soc_XLMAC_HIGIG_HDR_0r_fields[] = { 2611 { HIGIG_HDR_0f, 64, 0, SOCF_LE } 2612 }; 2613 2614 #endif 2615 #if defined(BCM_88675_A0) 2616 soc_field_info_t soc_XLMAC_HIGIG_HDR_1r_fields[] = { 2617 { HIGIG_HDR_1f, 64, 0, SOCF_LE } 2618 }; 2619 2620 #endif 2621 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 2622 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 2623 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 2624 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 2625 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 2626 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 2627 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 2628 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 2629 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 2630 defined(BCM_56980_B0) 2631 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM53400_A0r_fields[] = { 2632 { HIGIG_HDR_0f, 64, 0, SOCF_LE }, 2633 { HIGIG_HDR_0_HIf, 32, 32, SOCF_LE }, 2634 { HIGIG_HDR_0_LOf, 32, 0, SOCF_LE } 2635 }; 2636 2637 #endif 2638 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 2639 defined(BCM_56860_A0) 2640 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM56850_A0r_fields[] = { 2641 { HIGIG_HDR_0f, 64, 0, SOCF_LE }, 2642 { HIGIG_HDR_0_HIf, 32, 32, SOCF_LE }, 2643 { HIGIG_HDR_0_LOf, 32, 0, SOCF_LE } 2644 }; 2645 2646 #endif 2647 #if defined(BCM_88270_A0) 2648 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM88270_A0r_fields[] = { 2649 { HIGIG_HDR_0f, 64, 0, SOCF_LE } 2650 }; 2651 2652 #endif 2653 #if defined(BCM_88375_A0) 2654 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM88375_A0r_fields[] = { 2655 { HIGIG_HDR_0f, 64, 0, SOCF_LE } 2656 }; 2657 2658 #endif 2659 #if defined(BCM_88375_B0) 2660 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM88375_B0r_fields[] = { 2661 { HIGIG_HDR_0f, 64, 0, SOCF_LE } 2662 }; 2663 2664 #endif 2665 #if defined(BCM_88470_A0) 2666 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM88470_A0r_fields[] = { 2667 { HIGIG_HDR_0f, 64, 0, SOCF_LE } 2668 }; 2669 2670 #endif 2671 #if defined(BCM_88470_B0) 2672 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM88470_B0r_fields[] = { 2673 { HIGIG_HDR_0f, 64, 0, SOCF_LE } 2674 }; 2675 2676 #endif 2677 #if defined(BCM_88675_B0) 2678 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM88675_B0r_fields[] = { 2679 { HIGIG_HDR_0f, 64, 0, SOCF_LE } 2680 }; 2681 2682 #endif 2683 #if defined(BCM_88680_A0) 2684 soc_field_info_t soc_XLMAC_HIGIG_HDR_0_BCM88680_A0r_fields[] = { 2685 { HIGIG_HDR_0f, 64, 0, SOCF_LE } 2686 }; 2687 2688 #endif 2689 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 2690 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 2691 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 2692 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 2693 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 2694 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 2695 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 2696 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 2697 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 2698 defined(BCM_56980_B0) 2699 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM53400_A0r_fields[] = { 2700 { HIGIG_HDR_1f, 64, 0, SOCF_LE }, 2701 { HIGIG_HDR_1_HIf, 32, 32, SOCF_LE }, 2702 { HIGIG_HDR_1_LOf, 32, 0, SOCF_LE } 2703 }; 2704 2705 #endif 2706 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 2707 defined(BCM_56860_A0) 2708 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM56850_A0r_fields[] = { 2709 { HIGIG_HDR_1f, 64, 0, SOCF_LE }, 2710 { HIGIG_HDR_1_HIf, 32, 32, SOCF_LE }, 2711 { HIGIG_HDR_1_LOf, 32, 0, SOCF_LE } 2712 }; 2713 2714 #endif 2715 #if defined(BCM_88270_A0) 2716 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM88270_A0r_fields[] = { 2717 { HIGIG_HDR_1f, 64, 0, SOCF_LE } 2718 }; 2719 2720 #endif 2721 #if defined(BCM_88375_A0) 2722 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM88375_A0r_fields[] = { 2723 { HIGIG_HDR_1f, 64, 0, SOCF_LE } 2724 }; 2725 2726 #endif 2727 #if defined(BCM_88375_B0) 2728 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM88375_B0r_fields[] = { 2729 { HIGIG_HDR_1f, 64, 0, SOCF_LE } 2730 }; 2731 2732 #endif 2733 #if defined(BCM_88470_A0) 2734 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM88470_A0r_fields[] = { 2735 { HIGIG_HDR_1f, 64, 0, SOCF_LE } 2736 }; 2737 2738 #endif 2739 #if defined(BCM_88470_B0) 2740 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM88470_B0r_fields[] = { 2741 { HIGIG_HDR_1f, 64, 0, SOCF_LE } 2742 }; 2743 2744 #endif 2745 #if defined(BCM_88675_B0) 2746 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM88675_B0r_fields[] = { 2747 { HIGIG_HDR_1f, 64, 0, SOCF_LE } 2748 }; 2749 2750 #endif 2751 #if defined(BCM_88680_A0) 2752 soc_field_info_t soc_XLMAC_HIGIG_HDR_1_BCM88680_A0r_fields[] = { 2753 { HIGIG_HDR_1f, 64, 0, SOCF_LE } 2754 }; 2755 2756 #endif 2757 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2758 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 2759 defined(BCM_56980_A0) || defined(BCM_56980_B0) 2760 soc_field_info_t soc_XLMAC_INTR_ENABLEr_fields[] = { 2761 { EN_LINK_INTERRUPTION_STATUSf, 1, 12, 0 }, 2762 { EN_LOCAL_FAULT_STATUSf, 1, 10, 0 }, 2763 { EN_REMOTE_FAULT_STATUSf, 1, 11, 0 }, 2764 { EN_RX_CDC_DOUBLE_BIT_ERRf, 1, 9, 0 }, 2765 { EN_RX_CDC_SINGLE_BIT_ERRf, 1, 8, 0 }, 2766 { EN_RX_MSG_OVERFLOWf, 1, 5, 0 }, 2767 { EN_RX_PKT_OVERFLOWf, 1, 4, 0 }, 2768 { EN_TS_ENTRY_VALIDf, 1, 13, 0 }, 2769 { EN_TX_CDC_DOUBLE_BIT_ERRf, 1, 7, 0 }, 2770 { EN_TX_CDC_SINGLE_BIT_ERRf, 1, 6, 0 }, 2771 { EN_TX_LLFC_MSG_OVERFLOWf, 1, 2, 0 }, 2772 { EN_TX_PKT_OVERFLOWf, 1, 1, 0 }, 2773 { EN_TX_PKT_UNDERFLOWf, 1, 0, 0 }, 2774 { EN_TX_TS_FIFO_OVERFLOWf, 1, 3, 0 } 2775 }; 2776 2777 #endif 2778 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 2779 defined(BCM_56670_A0) || defined(BCM_56670_B0) 2780 soc_field_info_t soc_XLMAC_INTR_ENABLE_BCM53570_A0r_fields[] = { 2781 { EN_LINK_INTERRUPTION_STATUSf, 1, 12, 0 }, 2782 { EN_LOCAL_FAULT_STATUSf, 1, 10, 0 }, 2783 { EN_REMOTE_FAULT_STATUSf, 1, 11, 0 }, 2784 { EN_RX_CDC_DOUBLE_BIT_ERRf, 1, 9, 0 }, 2785 { EN_RX_CDC_SINGLE_BIT_ERRf, 1, 8, 0 }, 2786 { EN_RX_DBG_CNT_CAPTURE_DONEf, 1, 16, 0 }, 2787 { EN_RX_LOST_EOP_FORCEDf, 1, 15, 0 }, 2788 { EN_RX_MSG_OVERFLOWf, 1, 5, 0 }, 2789 { EN_RX_PKT_OVERFLOWf, 1, 4, 0 }, 2790 { EN_RX_TIMEOUT_EXPIRYf, 1, 14, 0 }, 2791 { EN_TS_ENTRY_VALIDf, 1, 13, 0 }, 2792 { EN_TX_CDC_DOUBLE_BIT_ERRf, 1, 7, 0 }, 2793 { EN_TX_CDC_SINGLE_BIT_ERRf, 1, 6, 0 }, 2794 { EN_TX_DBG_CNT_CAPTURE_DONEf, 1, 17, 0 }, 2795 { EN_TX_LLFC_MSG_OVERFLOWf, 1, 2, 0 }, 2796 { EN_TX_PKT_OVERFLOWf, 1, 1, 0 }, 2797 { EN_TX_PKT_UNDERFLOWf, 1, 0, 0 }, 2798 { EN_TX_TS_FIFO_OVERFLOWf, 1, 3, 0 } 2799 }; 2800 2801 #endif 2802 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2803 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 2804 defined(BCM_56980_A0) || defined(BCM_56980_B0) 2805 soc_field_info_t soc_XLMAC_INTR_STATUSr_fields[] = { 2806 { SUM_LINK_INTERRUPTION_STATUSf, 1, 12, SOCF_RO }, 2807 { SUM_LOCAL_FAULT_STATUSf, 1, 10, SOCF_RO }, 2808 { SUM_REMOTE_FAULT_STATUSf, 1, 11, SOCF_RO }, 2809 { SUM_RX_CDC_DOUBLE_BIT_ERRf, 1, 9, SOCF_RO }, 2810 { SUM_RX_CDC_SINGLE_BIT_ERRf, 1, 8, SOCF_RO }, 2811 { SUM_RX_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 2812 { SUM_RX_PKT_OVERFLOWf, 1, 4, SOCF_RO }, 2813 { SUM_TS_ENTRY_VALIDf, 1, 13, SOCF_RO }, 2814 { SUM_TX_CDC_DOUBLE_BIT_ERRf, 1, 7, SOCF_RO }, 2815 { SUM_TX_CDC_SINGLE_BIT_ERRf, 1, 6, SOCF_RO }, 2816 { SUM_TX_LLFC_MSG_OVERFLOWf, 1, 2, SOCF_RO }, 2817 { SUM_TX_PKT_OVERFLOWf, 1, 1, SOCF_RO }, 2818 { SUM_TX_PKT_UNDERFLOWf, 1, 0, SOCF_RO }, 2819 { SUM_TX_TS_FIFO_OVERFLOWf, 1, 3, SOCF_RO } 2820 }; 2821 2822 #endif 2823 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 2824 defined(BCM_56670_A0) || defined(BCM_56670_B0) 2825 soc_field_info_t soc_XLMAC_INTR_STATUS_BCM53570_A0r_fields[] = { 2826 { SUM_LINK_INTERRUPTION_STATUSf, 1, 12, SOCF_RO }, 2827 { SUM_LOCAL_FAULT_STATUSf, 1, 10, SOCF_RO }, 2828 { SUM_REMOTE_FAULT_STATUSf, 1, 11, SOCF_RO }, 2829 { SUM_RX_CDC_DOUBLE_BIT_ERRf, 1, 9, SOCF_RO }, 2830 { SUM_RX_CDC_SINGLE_BIT_ERRf, 1, 8, SOCF_RO }, 2831 { SUM_RX_DBG_CNT_CAPTURE_DONEf, 1, 16, SOCF_RO }, 2832 { SUM_RX_LOST_EOP_FORCEDf, 1, 15, SOCF_RO }, 2833 { SUM_RX_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 2834 { SUM_RX_PKT_OVERFLOWf, 1, 4, SOCF_RO }, 2835 { SUM_RX_TIMEOUT_EXPIRYf, 1, 14, SOCF_RO }, 2836 { SUM_TS_ENTRY_VALIDf, 1, 13, SOCF_RO }, 2837 { SUM_TX_CDC_DOUBLE_BIT_ERRf, 1, 7, SOCF_RO }, 2838 { SUM_TX_CDC_SINGLE_BIT_ERRf, 1, 6, SOCF_RO }, 2839 { SUM_TX_DBG_CNT_CAPTURE_DONEf, 1, 17, SOCF_RO }, 2840 { SUM_TX_LLFC_MSG_OVERFLOWf, 1, 2, SOCF_RO }, 2841 { SUM_TX_PKT_OVERFLOWf, 1, 1, SOCF_RO }, 2842 { SUM_TX_PKT_UNDERFLOWf, 1, 0, SOCF_RO }, 2843 { SUM_TX_TS_FIFO_OVERFLOWf, 1, 3, SOCF_RO } 2844 }; 2845 2846 #endif 2847 #if defined(BCM_88675_A0) 2848 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUSr_fields[] = { 2849 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO|SOCF_SIG }, 2850 { RSVDf, 1, 1, SOCF_RO|SOCF_SIG|SOCF_RES } 2851 }; 2852 2853 #endif 2854 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 2855 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 2856 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 2857 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 2858 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 2859 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 2860 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 2861 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 2862 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 2863 defined(BCM_56980_B0) 2864 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUS_BCM53400_A0r_fields[] = { 2865 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO }, 2866 { RSVDf, 1, 1, SOCF_RO|SOCF_RES } 2867 }; 2868 2869 #endif 2870 #if defined(BCM_88270_A0) 2871 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUS_BCM88270_A0r_fields[] = { 2872 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO|SOCF_SIG }, 2873 { RSVDf, 1, 1, SOCF_RO|SOCF_SIG|SOCF_RES } 2874 }; 2875 2876 #endif 2877 #if defined(BCM_88375_A0) 2878 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUS_BCM88375_A0r_fields[] = { 2879 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO|SOCF_SIG }, 2880 { RSVDf, 1, 1, SOCF_RO|SOCF_SIG|SOCF_RES } 2881 }; 2882 2883 #endif 2884 #if defined(BCM_88375_B0) 2885 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUS_BCM88375_B0r_fields[] = { 2886 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO|SOCF_SIG }, 2887 { RSVDf, 1, 1, SOCF_RO|SOCF_SIG|SOCF_RES } 2888 }; 2889 2890 #endif 2891 #if defined(BCM_88470_A0) 2892 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUS_BCM88470_A0r_fields[] = { 2893 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO|SOCF_SIG }, 2894 { RSVDf, 1, 1, SOCF_RO|SOCF_SIG|SOCF_RES } 2895 }; 2896 2897 #endif 2898 #if defined(BCM_88470_B0) 2899 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUS_BCM88470_B0r_fields[] = { 2900 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO|SOCF_SIG }, 2901 { RSVDf, 1, 1, SOCF_RO|SOCF_SIG|SOCF_RES } 2902 }; 2903 2904 #endif 2905 #if defined(BCM_88675_B0) 2906 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUS_BCM88675_B0r_fields[] = { 2907 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO|SOCF_SIG }, 2908 { RSVDf, 1, 1, SOCF_RO|SOCF_SIG|SOCF_RES } 2909 }; 2910 2911 #endif 2912 #if defined(BCM_88680_A0) 2913 soc_field_info_t soc_XLMAC_LAG_FAILOVER_STATUS_BCM88680_A0r_fields[] = { 2914 { LAG_FAILOVER_LOOPBACKf, 1, 0, SOCF_RO|SOCF_SIG }, 2915 { RSVDf, 1, 1, SOCF_RO|SOCF_SIG|SOCF_RES } 2916 }; 2917 2918 #endif 2919 #if defined(BCM_88675_A0) 2920 soc_field_info_t soc_XLMAC_LLFC_CTRLr_fields[] = { 2921 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 2922 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 2923 { LLFC_IMGf, 8, 6, SOCF_LE }, 2924 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 2925 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 2926 { RX_LLFC_ENf, 1, 1, 0 }, 2927 { TX_LLFC_ENf, 1, 0, 0 } 2928 }; 2929 2930 #endif 2931 #if defined(BCM_88270_A0) 2932 soc_field_info_t soc_XLMAC_LLFC_CTRL_BCM88270_A0r_fields[] = { 2933 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 2934 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 2935 { LLFC_IMGf, 8, 6, SOCF_LE }, 2936 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 2937 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 2938 { RX_LLFC_ENf, 1, 1, 0 }, 2939 { TX_LLFC_ENf, 1, 0, 0 } 2940 }; 2941 2942 #endif 2943 #if defined(BCM_88375_A0) 2944 soc_field_info_t soc_XLMAC_LLFC_CTRL_BCM88375_A0r_fields[] = { 2945 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 2946 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 2947 { LLFC_IMGf, 8, 6, SOCF_LE }, 2948 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 2949 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 2950 { RX_LLFC_ENf, 1, 1, 0 }, 2951 { TX_LLFC_ENf, 1, 0, 0 } 2952 }; 2953 2954 #endif 2955 #if defined(BCM_88375_B0) 2956 soc_field_info_t soc_XLMAC_LLFC_CTRL_BCM88375_B0r_fields[] = { 2957 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 2958 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 2959 { LLFC_IMGf, 8, 6, SOCF_LE }, 2960 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 2961 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 2962 { RX_LLFC_ENf, 1, 1, 0 }, 2963 { TX_LLFC_ENf, 1, 0, 0 } 2964 }; 2965 2966 #endif 2967 #if defined(BCM_88470_A0) 2968 soc_field_info_t soc_XLMAC_LLFC_CTRL_BCM88470_A0r_fields[] = { 2969 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 2970 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 2971 { LLFC_IMGf, 8, 6, SOCF_LE }, 2972 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 2973 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 2974 { RX_LLFC_ENf, 1, 1, 0 }, 2975 { TX_LLFC_ENf, 1, 0, 0 } 2976 }; 2977 2978 #endif 2979 #if defined(BCM_88470_B0) 2980 soc_field_info_t soc_XLMAC_LLFC_CTRL_BCM88470_B0r_fields[] = { 2981 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 2982 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 2983 { LLFC_IMGf, 8, 6, SOCF_LE }, 2984 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 2985 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 2986 { RX_LLFC_ENf, 1, 1, 0 }, 2987 { TX_LLFC_ENf, 1, 0, 0 } 2988 }; 2989 2990 #endif 2991 #if defined(BCM_88675_B0) 2992 soc_field_info_t soc_XLMAC_LLFC_CTRL_BCM88675_B0r_fields[] = { 2993 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 2994 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 2995 { LLFC_IMGf, 8, 6, SOCF_LE }, 2996 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 2997 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 2998 { RX_LLFC_ENf, 1, 1, 0 }, 2999 { TX_LLFC_ENf, 1, 0, 0 } 3000 }; 3001 3002 #endif 3003 #if defined(BCM_88680_A0) 3004 soc_field_info_t soc_XLMAC_LLFC_CTRL_BCM88680_A0r_fields[] = { 3005 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 3006 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 3007 { LLFC_IMGf, 8, 6, SOCF_LE }, 3008 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 3009 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 3010 { RX_LLFC_ENf, 1, 1, 0 }, 3011 { TX_LLFC_ENf, 1, 0, 0 } 3012 }; 3013 3014 #endif 3015 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 3016 soc_field_info_t soc_XLMAC_MACSEC_CTRLr_fields[] = { 3017 { MACSEC_PROG_TX_CRCf, 32, 3, SOCF_LE }, 3018 { MACSEC_TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 3019 { MACSEC_TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 3020 { RSVDf, 1, 0, SOCF_RES }, 3021 { XLMAC_MACSEC_CTRL_HIf, 3, 32, SOCF_LE }, 3022 { XLMAC_MACSEC_CTRL_LOf, 32, 0, SOCF_LE } 3023 }; 3024 3025 #endif 3026 #if defined(BCM_2801PM_A0) || defined(BCM_53400_A0) || \ 3027 defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3028 defined(BCM_56160_A0) || defined(BCM_56260_A0) || \ 3029 defined(BCM_56260_B0) || defined(BCM_56270_A0) || \ 3030 defined(BCM_56370_A0) || defined(BCM_56560_A0) || \ 3031 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 3032 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 3033 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 3034 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 3035 defined(BCM_56980_A0) || defined(BCM_56980_B0) 3036 soc_field_info_t soc_XLMAC_MEM_CTRLr_fields[] = { 3037 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3038 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3039 }; 3040 3041 #endif 3042 #if defined(BCM_56860_A0) 3043 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM56860_A0r_fields[] = { 3044 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3045 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3046 }; 3047 3048 #endif 3049 #if defined(BCM_88270_A0) 3050 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM88270_A0r_fields[] = { 3051 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3052 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3053 }; 3054 3055 #endif 3056 #if defined(BCM_88375_A0) 3057 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM88375_A0r_fields[] = { 3058 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3059 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3060 }; 3061 3062 #endif 3063 #if defined(BCM_88375_B0) 3064 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM88375_B0r_fields[] = { 3065 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3066 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3067 }; 3068 3069 #endif 3070 #if defined(BCM_88470_A0) 3071 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM88470_A0r_fields[] = { 3072 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3073 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3074 }; 3075 3076 #endif 3077 #if defined(BCM_88470_B0) 3078 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM88470_B0r_fields[] = { 3079 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3080 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3081 }; 3082 3083 #endif 3084 #if defined(BCM_88675_A0) 3085 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM88675_A0r_fields[] = { 3086 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3087 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3088 }; 3089 3090 #endif 3091 #if defined(BCM_88675_B0) 3092 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM88675_B0r_fields[] = { 3093 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3094 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3095 }; 3096 3097 #endif 3098 #if defined(BCM_88680_A0) 3099 soc_field_info_t soc_XLMAC_MEM_CTRL_BCM88680_A0r_fields[] = { 3100 { RX_CDC_MEM_CTRL_TMf, 12, 0, SOCF_LE }, 3101 { TX_CDC_MEM_CTRL_TMf, 12, 12, SOCF_LE } 3102 }; 3103 3104 #endif 3105 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3106 defined(BCM_56670_A0) || defined(BCM_56670_B0) 3107 soc_field_info_t soc_XLMAC_MERGE_CLEAR_STATUSr_fields[] = { 3108 { CLEAR_RX_LOST_EOP_FORCEDf, 1, 1, 0 }, 3109 { CLEAR_RX_TIMEOUT_EXPIRYf, 1, 0, 0 } 3110 }; 3111 3112 #endif 3113 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3114 defined(BCM_56670_A0) || defined(BCM_56670_B0) 3115 soc_field_info_t soc_XLMAC_MERGE_CTRL_SECRET_CONFIGr_fields[] = { 3116 { DISABLE_STRICT_PRMBL_SMD_CHKf, 1, 2, 0 }, 3117 { MCRC_CHK_FFFF_0000f, 1, 1, 0 }, 3118 { USE_MCRC_FOR_TX_MFRAMESf, 1, 0, 0 } 3119 }; 3120 3121 #endif 3122 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3123 defined(BCM_56670_A0) || defined(BCM_56670_B0) 3124 soc_field_info_t soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIGr_fields[] = { 3125 { CAPTURE_ENABLEf, 1, 48, 0 }, 3126 { CAPTURE_START_TIMEf, 48, 0, SOCF_LE } 3127 }; 3128 3129 #endif 3130 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3131 defined(BCM_56670_A0) || defined(BCM_56670_B0) 3132 soc_field_info_t soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0r_fields[] = { 3133 { CAPTURE_DONEf, 1, 32, SOCF_RO }, 3134 { LAST_PREEMPT_EOP_TIME_0f, 32, 0, SOCF_LE|SOCF_RO } 3135 }; 3136 3137 #endif 3138 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3139 defined(BCM_56670_A0) || defined(BCM_56670_B0) 3140 soc_field_info_t soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1r_fields[] = { 3141 { FIRST_EXP_SOP_TIME_1f, 32, 32, SOCF_LE|SOCF_RO }, 3142 { LAST_EXP_EOP_TIME_1f, 32, 0, SOCF_LE|SOCF_RO } 3143 }; 3144 3145 #endif 3146 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3147 defined(BCM_56670_A0) || defined(BCM_56670_B0) 3148 soc_field_info_t soc_XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2r_fields[] = { 3149 { FIRST_PREEMPT_SOP_TIME_1f, 32, 32, SOCF_LE|SOCF_RO }, 3150 { LAST_PREEMPT_EOP_TIME_1f, 32, 0, SOCF_LE|SOCF_RO } 3151 }; 3152 3153 #endif 3154 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3155 defined(BCM_56670_A0) || defined(BCM_56670_B0) 3156 soc_field_info_t soc_XLMAC_MERGE_SMD_CONFIG_0r_fields[] = { 3157 { SMD_C0f, 8, 32, SOCF_LE }, 3158 { SMD_C1f, 8, 40, SOCF_LE }, 3159 { SMD_C2f, 8, 48, SOCF_LE }, 3160 { SMD_C3f, 8, 56, SOCF_LE }, 3161 { SMD_S0f, 8, 0, SOCF_LE }, 3162 { SMD_S1f, 8, 8, SOCF_LE }, 3163 { SMD_S2f, 8, 16, SOCF_LE }, 3164 { SMD_S3f, 8, 24, SOCF_LE } 3165 }; 3166 3167 #endif 3168 #if defined(BCM_88675_A0) 3169 soc_field_info_t soc_XLMAC_MODEr_fields[] = { 3170 { HDR_MODEf, 3, 0, SOCF_LE }, 3171 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 3172 { SPEED_MODEf, 3, 4, SOCF_LE } 3173 }; 3174 3175 #endif 3176 #if defined(BCM_88270_A0) 3177 soc_field_info_t soc_XLMAC_MODE_BCM88270_A0r_fields[] = { 3178 { HDR_MODEf, 3, 0, SOCF_LE }, 3179 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 3180 { SPEED_MODEf, 3, 4, SOCF_LE } 3181 }; 3182 3183 #endif 3184 #if defined(BCM_88375_A0) 3185 soc_field_info_t soc_XLMAC_MODE_BCM88375_A0r_fields[] = { 3186 { HDR_MODEf, 3, 0, SOCF_LE }, 3187 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 3188 { SPEED_MODEf, 3, 4, SOCF_LE } 3189 }; 3190 3191 #endif 3192 #if defined(BCM_88375_B0) 3193 soc_field_info_t soc_XLMAC_MODE_BCM88375_B0r_fields[] = { 3194 { HDR_MODEf, 3, 0, SOCF_LE }, 3195 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 3196 { SPEED_MODEf, 3, 4, SOCF_LE } 3197 }; 3198 3199 #endif 3200 #if defined(BCM_88470_A0) 3201 soc_field_info_t soc_XLMAC_MODE_BCM88470_A0r_fields[] = { 3202 { HDR_MODEf, 3, 0, SOCF_LE }, 3203 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 3204 { SPEED_MODEf, 3, 4, SOCF_LE } 3205 }; 3206 3207 #endif 3208 #if defined(BCM_88470_B0) 3209 soc_field_info_t soc_XLMAC_MODE_BCM88470_B0r_fields[] = { 3210 { HDR_MODEf, 3, 0, SOCF_LE }, 3211 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 3212 { SPEED_MODEf, 3, 4, SOCF_LE } 3213 }; 3214 3215 #endif 3216 #if defined(BCM_88675_B0) 3217 soc_field_info_t soc_XLMAC_MODE_BCM88675_B0r_fields[] = { 3218 { HDR_MODEf, 3, 0, SOCF_LE }, 3219 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 3220 { SPEED_MODEf, 3, 4, SOCF_LE } 3221 }; 3222 3223 #endif 3224 #if defined(BCM_88680_A0) 3225 soc_field_info_t soc_XLMAC_MODE_BCM88680_A0r_fields[] = { 3226 { HDR_MODEf, 3, 0, SOCF_LE }, 3227 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 3228 { SPEED_MODEf, 3, 4, SOCF_LE } 3229 }; 3230 3231 #endif 3232 #if defined(BCM_88675_A0) 3233 soc_field_info_t soc_XLMAC_PAUSE_CTRLr_fields[] = { 3234 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3235 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3236 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3237 { RSVD_1f, 1, 19, SOCF_RES }, 3238 { RSVD_2f, 1, 20, SOCF_RES }, 3239 { RX_PAUSE_ENf, 1, 18, 0 }, 3240 { TX_PAUSE_ENf, 1, 17, 0 } 3241 }; 3242 3243 #endif 3244 #if defined(BCM_53400_A0) || defined(BCM_56260_A0) || \ 3245 defined(BCM_56560_A0) || defined(BCM_56960_A0) || \ 3246 defined(BCM_56965_A0) 3247 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM53400_A0r_fields[] = { 3248 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3249 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3250 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3251 { RSVD_1f, 1, 19, SOCF_RES }, 3252 { RSVD_2f, 1, 20, SOCF_RES }, 3253 { RX_PAUSE_ENf, 1, 18, 0 }, 3254 { TX_PAUSE_ENf, 1, 17, 0 }, 3255 { XLMAC_PAUSE_CTRL_HIf, 5, 32, SOCF_LE }, 3256 { XLMAC_PAUSE_CTRL_LOf, 32, 0, SOCF_LE } 3257 }; 3258 3259 #endif 3260 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 3261 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM56850_A0r_fields[] = { 3262 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3263 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3264 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3265 { RSVD_1f, 1, 19, SOCF_RES }, 3266 { RSVD_2f, 1, 20, SOCF_RES }, 3267 { RX_PAUSE_ENf, 1, 18, 0 }, 3268 { TX_PAUSE_ENf, 1, 17, 0 }, 3269 { XLMAC_PAUSE_CTRL_HIf, 5, 32, SOCF_LE }, 3270 { XLMAC_PAUSE_CTRL_LOf, 32, 0, SOCF_LE } 3271 }; 3272 3273 #endif 3274 #if defined(BCM_56860_A0) 3275 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM56860_A0r_fields[] = { 3276 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3277 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3278 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3279 { RSVD_1f, 1, 19, SOCF_RES }, 3280 { RSVD_2f, 1, 20, SOCF_RES }, 3281 { RX_PAUSE_ENf, 1, 18, 0 }, 3282 { TX_PAUSE_ENf, 1, 17, 0 }, 3283 { XLMAC_PAUSE_CTRL_HIf, 5, 32, SOCF_LE }, 3284 { XLMAC_PAUSE_CTRL_LOf, 32, 0, SOCF_LE } 3285 }; 3286 3287 #endif 3288 #if defined(BCM_88270_A0) 3289 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM88270_A0r_fields[] = { 3290 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3291 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3292 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3293 { RSVD_1f, 1, 19, SOCF_RES }, 3294 { RSVD_2f, 1, 20, SOCF_RES }, 3295 { RX_PAUSE_ENf, 1, 18, 0 }, 3296 { TX_PAUSE_ENf, 1, 17, 0 } 3297 }; 3298 3299 #endif 3300 #if defined(BCM_88375_A0) 3301 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM88375_A0r_fields[] = { 3302 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3303 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3304 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3305 { RSVD_1f, 1, 19, SOCF_RES }, 3306 { RSVD_2f, 1, 20, SOCF_RES }, 3307 { RX_PAUSE_ENf, 1, 18, 0 }, 3308 { TX_PAUSE_ENf, 1, 17, 0 } 3309 }; 3310 3311 #endif 3312 #if defined(BCM_88375_B0) 3313 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM88375_B0r_fields[] = { 3314 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3315 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3316 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3317 { RSVD_1f, 1, 19, SOCF_RES }, 3318 { RSVD_2f, 1, 20, SOCF_RES }, 3319 { RX_PAUSE_ENf, 1, 18, 0 }, 3320 { TX_PAUSE_ENf, 1, 17, 0 } 3321 }; 3322 3323 #endif 3324 #if defined(BCM_88470_A0) 3325 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM88470_A0r_fields[] = { 3326 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3327 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3328 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3329 { RSVD_1f, 1, 19, SOCF_RES }, 3330 { RSVD_2f, 1, 20, SOCF_RES }, 3331 { RX_PAUSE_ENf, 1, 18, 0 }, 3332 { TX_PAUSE_ENf, 1, 17, 0 } 3333 }; 3334 3335 #endif 3336 #if defined(BCM_88470_B0) 3337 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM88470_B0r_fields[] = { 3338 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3339 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3340 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3341 { RSVD_1f, 1, 19, SOCF_RES }, 3342 { RSVD_2f, 1, 20, SOCF_RES }, 3343 { RX_PAUSE_ENf, 1, 18, 0 }, 3344 { TX_PAUSE_ENf, 1, 17, 0 } 3345 }; 3346 3347 #endif 3348 #if defined(BCM_88675_B0) 3349 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM88675_B0r_fields[] = { 3350 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3351 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3352 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3353 { RSVD_1f, 1, 19, SOCF_RES }, 3354 { RSVD_2f, 1, 20, SOCF_RES }, 3355 { RX_PAUSE_ENf, 1, 18, 0 }, 3356 { TX_PAUSE_ENf, 1, 17, 0 } 3357 }; 3358 3359 #endif 3360 #if defined(BCM_88680_A0) 3361 soc_field_info_t soc_XLMAC_PAUSE_CTRL_BCM88680_A0r_fields[] = { 3362 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 3363 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3364 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 3365 { RSVD_1f, 1, 19, SOCF_RES }, 3366 { RSVD_2f, 1, 20, SOCF_RES }, 3367 { RX_PAUSE_ENf, 1, 18, 0 }, 3368 { TX_PAUSE_ENf, 1, 17, 0 } 3369 }; 3370 3371 #endif 3372 #if defined(BCM_88675_A0) 3373 soc_field_info_t soc_XLMAC_PFC_CTRLr_fields[] = { 3374 { FORCE_PFC_XONf, 1, 33, 0 }, 3375 { PFC_REFRESH_ENf, 1, 32, 0 }, 3376 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3377 { PFC_STATS_ENf, 1, 35, 0 }, 3378 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3379 { RSVDf, 1, 34, SOCF_RES }, 3380 { RX_PFC_ENf, 1, 36, 0 }, 3381 { TX_PFC_ENf, 1, 37, 0 } 3382 }; 3383 3384 #endif 3385 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 3386 defined(BCM_56860_A0) 3387 soc_field_info_t soc_XLMAC_PFC_CTRL_BCM56850_A0r_fields[] = { 3388 { FORCE_PFC_XONf, 1, 33, 0 }, 3389 { PFC_REFRESH_ENf, 1, 32, 0 }, 3390 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3391 { PFC_STATS_ENf, 1, 35, 0 }, 3392 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3393 { RSVDf, 1, 34, SOCF_RES }, 3394 { RX_PFC_ENf, 1, 36, 0 }, 3395 { TX_PFC_ENf, 1, 37, 0 } 3396 }; 3397 3398 #endif 3399 #if defined(BCM_88270_A0) 3400 soc_field_info_t soc_XLMAC_PFC_CTRL_BCM88270_A0r_fields[] = { 3401 { FORCE_PFC_XONf, 1, 33, 0 }, 3402 { PFC_REFRESH_ENf, 1, 32, 0 }, 3403 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3404 { PFC_STATS_ENf, 1, 35, 0 }, 3405 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3406 { RSVDf, 1, 34, SOCF_RES }, 3407 { RX_PFC_ENf, 1, 36, 0 }, 3408 { TX_PFC_ENf, 1, 37, 0 } 3409 }; 3410 3411 #endif 3412 #if defined(BCM_88375_A0) 3413 soc_field_info_t soc_XLMAC_PFC_CTRL_BCM88375_A0r_fields[] = { 3414 { FORCE_PFC_XONf, 1, 33, 0 }, 3415 { PFC_REFRESH_ENf, 1, 32, 0 }, 3416 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3417 { PFC_STATS_ENf, 1, 35, 0 }, 3418 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3419 { RSVDf, 1, 34, SOCF_RES }, 3420 { RX_PFC_ENf, 1, 36, 0 }, 3421 { TX_PFC_ENf, 1, 37, 0 } 3422 }; 3423 3424 #endif 3425 #if defined(BCM_88375_B0) 3426 soc_field_info_t soc_XLMAC_PFC_CTRL_BCM88375_B0r_fields[] = { 3427 { FORCE_PFC_XONf, 1, 33, 0 }, 3428 { PFC_REFRESH_ENf, 1, 32, 0 }, 3429 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3430 { PFC_STATS_ENf, 1, 35, 0 }, 3431 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3432 { RSVDf, 1, 34, SOCF_RES }, 3433 { RX_PFC_ENf, 1, 36, 0 }, 3434 { TX_PFC_ENf, 1, 37, 0 } 3435 }; 3436 3437 #endif 3438 #if defined(BCM_88470_A0) 3439 soc_field_info_t soc_XLMAC_PFC_CTRL_BCM88470_A0r_fields[] = { 3440 { FORCE_PFC_XONf, 1, 33, 0 }, 3441 { PFC_REFRESH_ENf, 1, 32, 0 }, 3442 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3443 { PFC_STATS_ENf, 1, 35, 0 }, 3444 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3445 { RSVDf, 1, 34, SOCF_RES }, 3446 { RX_PFC_ENf, 1, 36, 0 }, 3447 { TX_PFC_ENf, 1, 37, 0 } 3448 }; 3449 3450 #endif 3451 #if defined(BCM_88470_B0) 3452 soc_field_info_t soc_XLMAC_PFC_CTRL_BCM88470_B0r_fields[] = { 3453 { FORCE_PFC_XONf, 1, 33, 0 }, 3454 { PFC_REFRESH_ENf, 1, 32, 0 }, 3455 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3456 { PFC_STATS_ENf, 1, 35, 0 }, 3457 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3458 { RSVDf, 1, 34, SOCF_RES }, 3459 { RX_PFC_ENf, 1, 36, 0 }, 3460 { TX_PFC_ENf, 1, 37, 0 } 3461 }; 3462 3463 #endif 3464 #if defined(BCM_88675_B0) 3465 soc_field_info_t soc_XLMAC_PFC_CTRL_BCM88675_B0r_fields[] = { 3466 { FORCE_PFC_XONf, 1, 33, 0 }, 3467 { PFC_REFRESH_ENf, 1, 32, 0 }, 3468 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3469 { PFC_STATS_ENf, 1, 35, 0 }, 3470 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3471 { RSVDf, 1, 34, SOCF_RES }, 3472 { RX_PFC_ENf, 1, 36, 0 }, 3473 { TX_PFC_ENf, 1, 37, 0 } 3474 }; 3475 3476 #endif 3477 #if defined(BCM_88680_A0) 3478 soc_field_info_t soc_XLMAC_PFC_CTRL_BCM88680_A0r_fields[] = { 3479 { FORCE_PFC_XONf, 1, 33, 0 }, 3480 { PFC_REFRESH_ENf, 1, 32, 0 }, 3481 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 3482 { PFC_STATS_ENf, 1, 35, 0 }, 3483 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 3484 { RSVDf, 1, 34, SOCF_RES }, 3485 { RX_PFC_ENf, 1, 36, 0 }, 3486 { TX_PFC_ENf, 1, 37, 0 } 3487 }; 3488 3489 #endif 3490 #if defined(BCM_88675_A0) 3491 soc_field_info_t soc_XLMAC_PFC_DAr_fields[] = { 3492 { PFC_MACDAf, 48, 0, SOCF_LE } 3493 }; 3494 3495 #endif 3496 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 3497 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 3498 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 3499 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 3500 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 3501 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 3502 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 3503 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 3504 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 3505 defined(BCM_56980_B0) 3506 soc_field_info_t soc_XLMAC_PFC_DA_BCM53400_A0r_fields[] = { 3507 { PFC_MACDAf, 48, 0, SOCF_LE }, 3508 { PFC_MACDA_HIf, 16, 32, SOCF_LE }, 3509 { PFC_MACDA_LOf, 32, 0, SOCF_LE } 3510 }; 3511 3512 #endif 3513 #if defined(BCM_88270_A0) 3514 soc_field_info_t soc_XLMAC_PFC_DA_BCM88270_A0r_fields[] = { 3515 { PFC_MACDAf, 48, 0, SOCF_LE } 3516 }; 3517 3518 #endif 3519 #if defined(BCM_88375_A0) 3520 soc_field_info_t soc_XLMAC_PFC_DA_BCM88375_A0r_fields[] = { 3521 { PFC_MACDAf, 48, 0, SOCF_LE } 3522 }; 3523 3524 #endif 3525 #if defined(BCM_88375_B0) 3526 soc_field_info_t soc_XLMAC_PFC_DA_BCM88375_B0r_fields[] = { 3527 { PFC_MACDAf, 48, 0, SOCF_LE } 3528 }; 3529 3530 #endif 3531 #if defined(BCM_88470_A0) 3532 soc_field_info_t soc_XLMAC_PFC_DA_BCM88470_A0r_fields[] = { 3533 { PFC_MACDAf, 48, 0, SOCF_LE } 3534 }; 3535 3536 #endif 3537 #if defined(BCM_88470_B0) 3538 soc_field_info_t soc_XLMAC_PFC_DA_BCM88470_B0r_fields[] = { 3539 { PFC_MACDAf, 48, 0, SOCF_LE } 3540 }; 3541 3542 #endif 3543 #if defined(BCM_88675_B0) 3544 soc_field_info_t soc_XLMAC_PFC_DA_BCM88675_B0r_fields[] = { 3545 { PFC_MACDAf, 48, 0, SOCF_LE } 3546 }; 3547 3548 #endif 3549 #if defined(BCM_88680_A0) 3550 soc_field_info_t soc_XLMAC_PFC_DA_BCM88680_A0r_fields[] = { 3551 { PFC_MACDAf, 48, 0, SOCF_LE } 3552 }; 3553 3554 #endif 3555 #if defined(BCM_88675_A0) 3556 soc_field_info_t soc_XLMAC_PFC_OPCODEr_fields[] = { 3557 { PFC_OPCODEf, 16, 0, SOCF_LE } 3558 }; 3559 3560 #endif 3561 #if defined(BCM_88270_A0) 3562 soc_field_info_t soc_XLMAC_PFC_OPCODE_BCM88270_A0r_fields[] = { 3563 { PFC_OPCODEf, 16, 0, SOCF_LE } 3564 }; 3565 3566 #endif 3567 #if defined(BCM_88375_A0) 3568 soc_field_info_t soc_XLMAC_PFC_OPCODE_BCM88375_A0r_fields[] = { 3569 { PFC_OPCODEf, 16, 0, SOCF_LE } 3570 }; 3571 3572 #endif 3573 #if defined(BCM_88375_B0) 3574 soc_field_info_t soc_XLMAC_PFC_OPCODE_BCM88375_B0r_fields[] = { 3575 { PFC_OPCODEf, 16, 0, SOCF_LE } 3576 }; 3577 3578 #endif 3579 #if defined(BCM_88470_A0) 3580 soc_field_info_t soc_XLMAC_PFC_OPCODE_BCM88470_A0r_fields[] = { 3581 { PFC_OPCODEf, 16, 0, SOCF_LE } 3582 }; 3583 3584 #endif 3585 #if defined(BCM_88470_B0) 3586 soc_field_info_t soc_XLMAC_PFC_OPCODE_BCM88470_B0r_fields[] = { 3587 { PFC_OPCODEf, 16, 0, SOCF_LE } 3588 }; 3589 3590 #endif 3591 #if defined(BCM_88675_B0) 3592 soc_field_info_t soc_XLMAC_PFC_OPCODE_BCM88675_B0r_fields[] = { 3593 { PFC_OPCODEf, 16, 0, SOCF_LE } 3594 }; 3595 3596 #endif 3597 #if defined(BCM_88680_A0) 3598 soc_field_info_t soc_XLMAC_PFC_OPCODE_BCM88680_A0r_fields[] = { 3599 { PFC_OPCODEf, 16, 0, SOCF_LE } 3600 }; 3601 3602 #endif 3603 #if defined(BCM_88675_A0) 3604 soc_field_info_t soc_XLMAC_PFC_TYPEr_fields[] = { 3605 { PFC_ETH_TYPEf, 16, 0, SOCF_LE } 3606 }; 3607 3608 #endif 3609 #if defined(BCM_88270_A0) 3610 soc_field_info_t soc_XLMAC_PFC_TYPE_BCM88270_A0r_fields[] = { 3611 { PFC_ETH_TYPEf, 16, 0, SOCF_LE } 3612 }; 3613 3614 #endif 3615 #if defined(BCM_88375_A0) 3616 soc_field_info_t soc_XLMAC_PFC_TYPE_BCM88375_A0r_fields[] = { 3617 { PFC_ETH_TYPEf, 16, 0, SOCF_LE } 3618 }; 3619 3620 #endif 3621 #if defined(BCM_88375_B0) 3622 soc_field_info_t soc_XLMAC_PFC_TYPE_BCM88375_B0r_fields[] = { 3623 { PFC_ETH_TYPEf, 16, 0, SOCF_LE } 3624 }; 3625 3626 #endif 3627 #if defined(BCM_88470_A0) 3628 soc_field_info_t soc_XLMAC_PFC_TYPE_BCM88470_A0r_fields[] = { 3629 { PFC_ETH_TYPEf, 16, 0, SOCF_LE } 3630 }; 3631 3632 #endif 3633 #if defined(BCM_88470_B0) 3634 soc_field_info_t soc_XLMAC_PFC_TYPE_BCM88470_B0r_fields[] = { 3635 { PFC_ETH_TYPEf, 16, 0, SOCF_LE } 3636 }; 3637 3638 #endif 3639 #if defined(BCM_88675_B0) 3640 soc_field_info_t soc_XLMAC_PFC_TYPE_BCM88675_B0r_fields[] = { 3641 { PFC_ETH_TYPEf, 16, 0, SOCF_LE } 3642 }; 3643 3644 #endif 3645 #if defined(BCM_88680_A0) 3646 soc_field_info_t soc_XLMAC_PFC_TYPE_BCM88680_A0r_fields[] = { 3647 { PFC_ETH_TYPEf, 16, 0, SOCF_LE } 3648 }; 3649 3650 #endif 3651 #if defined(BCM_88675_A0) 3652 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUSr_fields[] = { 3653 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 3654 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 3655 }; 3656 3657 #endif 3658 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 3659 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 3660 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 3661 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 3662 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 3663 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 3664 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 3665 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 3666 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 3667 defined(BCM_56980_B0) 3668 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUS_BCM53400_A0r_fields[] = { 3669 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO }, 3670 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO } 3671 }; 3672 3673 #endif 3674 #if defined(BCM_88270_A0) 3675 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUS_BCM88270_A0r_fields[] = { 3676 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 3677 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 3678 }; 3679 3680 #endif 3681 #if defined(BCM_88375_A0) 3682 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUS_BCM88375_A0r_fields[] = { 3683 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 3684 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 3685 }; 3686 3687 #endif 3688 #if defined(BCM_88375_B0) 3689 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUS_BCM88375_B0r_fields[] = { 3690 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 3691 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 3692 }; 3693 3694 #endif 3695 #if defined(BCM_88470_A0) 3696 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUS_BCM88470_A0r_fields[] = { 3697 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 3698 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 3699 }; 3700 3701 #endif 3702 #if defined(BCM_88470_B0) 3703 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUS_BCM88470_B0r_fields[] = { 3704 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 3705 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 3706 }; 3707 3708 #endif 3709 #if defined(BCM_88675_B0) 3710 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUS_BCM88675_B0r_fields[] = { 3711 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 3712 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 3713 }; 3714 3715 #endif 3716 #if defined(BCM_88680_A0) 3717 soc_field_info_t soc_XLMAC_RX_CDC_ECC_STATUS_BCM88680_A0r_fields[] = { 3718 { RX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 3719 { RX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 3720 }; 3721 3722 #endif 3723 #if defined(BCM_2801PM_A0) || defined(BCM_53400_A0) || \ 3724 defined(BCM_56260_A0) || defined(BCM_56560_A0) || \ 3725 defined(BCM_56960_A0) || defined(BCM_56965_A0) 3726 soc_field_info_t soc_XLMAC_RX_CTRLr_fields[] = { 3727 { RSVD_1f, 1, 0, SOCF_RES }, 3728 { RSVD_2f, 1, 11, SOCF_RES }, 3729 { RSVD_3f, 1, 12, SOCF_RES }, 3730 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3731 { RX_ANY_STARTf, 1, 1, 0 }, 3732 { STRICT_PREAMBLEf, 1, 3, 0 }, 3733 { STRIP_CRCf, 1, 2, 0 } 3734 }; 3735 3736 #endif 3737 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 3738 soc_field_info_t soc_XLMAC_RX_CTRL_BCM56850_A0r_fields[] = { 3739 { RSVD_1f, 1, 0, SOCF_RES }, 3740 { RSVD_2f, 1, 11, SOCF_RES }, 3741 { RSVD_3f, 1, 12, SOCF_RES }, 3742 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3743 { RX_ANY_STARTf, 1, 1, 0 }, 3744 { STRICT_PREAMBLEf, 1, 3, 0 }, 3745 { STRIP_CRCf, 1, 2, 0 } 3746 }; 3747 3748 #endif 3749 #if defined(BCM_56860_A0) 3750 soc_field_info_t soc_XLMAC_RX_CTRL_BCM56860_A0r_fields[] = { 3751 { RSVD_1f, 1, 0, SOCF_RES }, 3752 { RSVD_2f, 1, 11, SOCF_RES }, 3753 { RSVD_3f, 1, 12, SOCF_RES }, 3754 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3755 { RX_ANY_STARTf, 1, 1, 0 }, 3756 { STRICT_PREAMBLEf, 1, 3, 0 }, 3757 { STRIP_CRCf, 1, 2, 0 } 3758 }; 3759 3760 #endif 3761 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 3762 defined(BCM_56370_A0) || defined(BCM_56670_A0) || \ 3763 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 3764 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 3765 defined(BCM_56980_A0) || defined(BCM_56980_B0) 3766 soc_field_info_t soc_XLMAC_RX_CTRL_BCM56970_A0r_fields[] = { 3767 { RSVD_1f, 1, 0, SOCF_RES }, 3768 { RSVD_2f, 1, 11, SOCF_RES }, 3769 { RSVD_3f, 1, 12, SOCF_RES }, 3770 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3771 { RX_ANY_STARTf, 1, 1, 0 }, 3772 { RX_PASS_CTRLf, 1, 13, 0 }, 3773 { RX_PASS_PAUSEf, 1, 14, 0 }, 3774 { RX_PASS_PFCf, 1, 15, 0 }, 3775 { STRICT_PREAMBLEf, 1, 3, 0 }, 3776 { STRIP_CRCf, 1, 2, 0 } 3777 }; 3778 3779 #endif 3780 #if defined(BCM_88270_A0) 3781 soc_field_info_t soc_XLMAC_RX_CTRL_BCM88270_A0r_fields[] = { 3782 { RSVD_1f, 1, 0, SOCF_RES }, 3783 { RSVD_2f, 1, 11, SOCF_RES }, 3784 { RSVD_3f, 1, 12, SOCF_RES }, 3785 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3786 { RX_ANY_STARTf, 1, 1, 0 }, 3787 { STRICT_PREAMBLEf, 1, 3, 0 }, 3788 { STRIP_CRCf, 1, 2, 0 } 3789 }; 3790 3791 #endif 3792 #if defined(BCM_88375_A0) 3793 soc_field_info_t soc_XLMAC_RX_CTRL_BCM88375_A0r_fields[] = { 3794 { RSVD_1f, 1, 0, SOCF_RES }, 3795 { RSVD_2f, 1, 11, SOCF_RES }, 3796 { RSVD_3f, 1, 12, SOCF_RES }, 3797 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3798 { RX_ANY_STARTf, 1, 1, 0 }, 3799 { STRICT_PREAMBLEf, 1, 3, 0 }, 3800 { STRIP_CRCf, 1, 2, 0 } 3801 }; 3802 3803 #endif 3804 #if defined(BCM_88375_B0) 3805 soc_field_info_t soc_XLMAC_RX_CTRL_BCM88375_B0r_fields[] = { 3806 { RSVD_1f, 1, 0, SOCF_RES }, 3807 { RSVD_2f, 1, 11, SOCF_RES }, 3808 { RSVD_3f, 1, 12, SOCF_RES }, 3809 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3810 { RX_ANY_STARTf, 1, 1, 0 }, 3811 { STRICT_PREAMBLEf, 1, 3, 0 }, 3812 { STRIP_CRCf, 1, 2, 0 } 3813 }; 3814 3815 #endif 3816 #if defined(BCM_88470_A0) 3817 soc_field_info_t soc_XLMAC_RX_CTRL_BCM88470_A0r_fields[] = { 3818 { RSVD_1f, 1, 0, SOCF_RES }, 3819 { RSVD_2f, 1, 11, SOCF_RES }, 3820 { RSVD_3f, 1, 12, SOCF_RES }, 3821 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3822 { RX_ANY_STARTf, 1, 1, 0 }, 3823 { STRICT_PREAMBLEf, 1, 3, 0 }, 3824 { STRIP_CRCf, 1, 2, 0 } 3825 }; 3826 3827 #endif 3828 #if defined(BCM_88470_B0) 3829 soc_field_info_t soc_XLMAC_RX_CTRL_BCM88470_B0r_fields[] = { 3830 { RSVD_1f, 1, 0, SOCF_RES }, 3831 { RSVD_2f, 1, 11, SOCF_RES }, 3832 { RSVD_3f, 1, 12, SOCF_RES }, 3833 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3834 { RX_ANY_STARTf, 1, 1, 0 }, 3835 { STRICT_PREAMBLEf, 1, 3, 0 }, 3836 { STRIP_CRCf, 1, 2, 0 } 3837 }; 3838 3839 #endif 3840 #if defined(BCM_88675_A0) 3841 soc_field_info_t soc_XLMAC_RX_CTRL_BCM88675_A0r_fields[] = { 3842 { RSVD_1f, 1, 0, SOCF_RES }, 3843 { RSVD_2f, 1, 11, SOCF_RES }, 3844 { RSVD_3f, 1, 12, SOCF_RES }, 3845 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3846 { RX_ANY_STARTf, 1, 1, 0 }, 3847 { STRICT_PREAMBLEf, 1, 3, 0 }, 3848 { STRIP_CRCf, 1, 2, 0 } 3849 }; 3850 3851 #endif 3852 #if defined(BCM_88675_B0) 3853 soc_field_info_t soc_XLMAC_RX_CTRL_BCM88675_B0r_fields[] = { 3854 { RSVD_1f, 1, 0, SOCF_RES }, 3855 { RSVD_2f, 1, 11, SOCF_RES }, 3856 { RSVD_3f, 1, 12, SOCF_RES }, 3857 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3858 { RX_ANY_STARTf, 1, 1, 0 }, 3859 { STRICT_PREAMBLEf, 1, 3, 0 }, 3860 { STRIP_CRCf, 1, 2, 0 } 3861 }; 3862 3863 #endif 3864 #if defined(BCM_88680_A0) 3865 soc_field_info_t soc_XLMAC_RX_CTRL_BCM88680_A0r_fields[] = { 3866 { RSVD_1f, 1, 0, SOCF_RES }, 3867 { RSVD_2f, 1, 11, SOCF_RES }, 3868 { RSVD_3f, 1, 12, SOCF_RES }, 3869 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 3870 { RX_ANY_STARTf, 1, 1, 0 }, 3871 { STRICT_PREAMBLEf, 1, 3, 0 }, 3872 { STRIP_CRCf, 1, 2, 0 } 3873 }; 3874 3875 #endif 3876 #if defined(BCM_88675_A0) 3877 soc_field_info_t soc_XLMAC_RX_LLFC_MSG_FIELDSr_fields[] = { 3878 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 3879 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 3880 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 3881 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 3882 }; 3883 3884 #endif 3885 #if defined(BCM_88270_A0) 3886 soc_field_info_t soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88270_A0r_fields[] = { 3887 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 3888 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 3889 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 3890 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 3891 }; 3892 3893 #endif 3894 #if defined(BCM_88375_A0) 3895 soc_field_info_t soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88375_A0r_fields[] = { 3896 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 3897 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 3898 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 3899 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 3900 }; 3901 3902 #endif 3903 #if defined(BCM_88375_B0) 3904 soc_field_info_t soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88375_B0r_fields[] = { 3905 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 3906 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 3907 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 3908 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 3909 }; 3910 3911 #endif 3912 #if defined(BCM_88470_A0) 3913 soc_field_info_t soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88470_A0r_fields[] = { 3914 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 3915 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 3916 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 3917 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 3918 }; 3919 3920 #endif 3921 #if defined(BCM_88470_B0) 3922 soc_field_info_t soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88470_B0r_fields[] = { 3923 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 3924 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 3925 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 3926 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 3927 }; 3928 3929 #endif 3930 #if defined(BCM_88675_B0) 3931 soc_field_info_t soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88675_B0r_fields[] = { 3932 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 3933 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 3934 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 3935 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 3936 }; 3937 3938 #endif 3939 #if defined(BCM_88680_A0) 3940 soc_field_info_t soc_XLMAC_RX_LLFC_MSG_FIELDS_BCM88680_A0r_fields[] = { 3941 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 3942 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 3943 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 3944 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 3945 }; 3946 3947 #endif 3948 #if defined(BCM_2801PM_A0) || defined(BCM_53400_A0) || \ 3949 defined(BCM_56260_A0) || defined(BCM_56560_A0) || \ 3950 defined(BCM_56960_A0) || defined(BCM_56965_A0) 3951 soc_field_info_t soc_XLMAC_RX_LSS_CTRLr_fields[] = { 3952 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 3953 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 3954 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 3955 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 3956 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 3957 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 3958 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 3959 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 3960 }; 3961 3962 #endif 3963 #if defined(BCM_88270_A0) 3964 soc_field_info_t soc_XLMAC_RX_LSS_CTRL_BCM88270_A0r_fields[] = { 3965 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 3966 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 3967 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 3968 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 3969 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 3970 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 3971 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 3972 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 3973 }; 3974 3975 #endif 3976 #if defined(BCM_88375_A0) 3977 soc_field_info_t soc_XLMAC_RX_LSS_CTRL_BCM88375_A0r_fields[] = { 3978 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 3979 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 3980 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 3981 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 3982 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 3983 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 3984 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 3985 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 3986 }; 3987 3988 #endif 3989 #if defined(BCM_88375_B0) 3990 soc_field_info_t soc_XLMAC_RX_LSS_CTRL_BCM88375_B0r_fields[] = { 3991 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 3992 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 3993 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 3994 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 3995 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 3996 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 3997 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 3998 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 3999 }; 4000 4001 #endif 4002 #if defined(BCM_88470_A0) 4003 soc_field_info_t soc_XLMAC_RX_LSS_CTRL_BCM88470_A0r_fields[] = { 4004 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 4005 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 4006 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 4007 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 4008 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 4009 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 4010 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 4011 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 4012 }; 4013 4014 #endif 4015 #if defined(BCM_88470_B0) 4016 soc_field_info_t soc_XLMAC_RX_LSS_CTRL_BCM88470_B0r_fields[] = { 4017 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 4018 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 4019 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 4020 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 4021 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 4022 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 4023 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 4024 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 4025 }; 4026 4027 #endif 4028 #if defined(BCM_88675_A0) 4029 soc_field_info_t soc_XLMAC_RX_LSS_CTRL_BCM88675_A0r_fields[] = { 4030 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 4031 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 4032 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 4033 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 4034 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 4035 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 4036 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 4037 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 4038 }; 4039 4040 #endif 4041 #if defined(BCM_88675_B0) 4042 soc_field_info_t soc_XLMAC_RX_LSS_CTRL_BCM88675_B0r_fields[] = { 4043 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 4044 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 4045 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 4046 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 4047 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 4048 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 4049 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 4050 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 4051 }; 4052 4053 #endif 4054 #if defined(BCM_88680_A0) 4055 soc_field_info_t soc_XLMAC_RX_LSS_CTRL_BCM88680_A0r_fields[] = { 4056 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 4057 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 4058 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 4059 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 4060 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 4061 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 4062 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 4063 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 4064 }; 4065 4066 #endif 4067 #if defined(BCM_88675_A0) 4068 soc_field_info_t soc_XLMAC_RX_LSS_STATUSr_fields[] = { 4069 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO|SOCF_SIG|SOCF_INTR }, 4070 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 4071 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_SIG } 4072 }; 4073 4074 #endif 4075 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 4076 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 4077 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4078 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 4079 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 4080 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 4081 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 4082 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4083 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 4084 defined(BCM_56980_B0) 4085 soc_field_info_t soc_XLMAC_RX_LSS_STATUS_BCM53400_A0r_fields[] = { 4086 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO }, 4087 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO }, 4088 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO } 4089 }; 4090 4091 #endif 4092 #if defined(BCM_88270_A0) 4093 soc_field_info_t soc_XLMAC_RX_LSS_STATUS_BCM88270_A0r_fields[] = { 4094 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO|SOCF_SIG|SOCF_INTR }, 4095 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 4096 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_SIG } 4097 }; 4098 4099 #endif 4100 #if defined(BCM_88375_A0) 4101 soc_field_info_t soc_XLMAC_RX_LSS_STATUS_BCM88375_A0r_fields[] = { 4102 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO|SOCF_SIG|SOCF_INTR }, 4103 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 4104 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_SIG } 4105 }; 4106 4107 #endif 4108 #if defined(BCM_88375_B0) 4109 soc_field_info_t soc_XLMAC_RX_LSS_STATUS_BCM88375_B0r_fields[] = { 4110 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO|SOCF_SIG|SOCF_INTR }, 4111 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 4112 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_SIG } 4113 }; 4114 4115 #endif 4116 #if defined(BCM_88470_A0) 4117 soc_field_info_t soc_XLMAC_RX_LSS_STATUS_BCM88470_A0r_fields[] = { 4118 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO|SOCF_SIG|SOCF_INTR }, 4119 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 4120 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_SIG } 4121 }; 4122 4123 #endif 4124 #if defined(BCM_88470_B0) 4125 soc_field_info_t soc_XLMAC_RX_LSS_STATUS_BCM88470_B0r_fields[] = { 4126 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO|SOCF_SIG|SOCF_INTR }, 4127 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 4128 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_SIG } 4129 }; 4130 4131 #endif 4132 #if defined(BCM_88675_B0) 4133 soc_field_info_t soc_XLMAC_RX_LSS_STATUS_BCM88675_B0r_fields[] = { 4134 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO|SOCF_SIG|SOCF_INTR }, 4135 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 4136 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_SIG } 4137 }; 4138 4139 #endif 4140 #if defined(BCM_88680_A0) 4141 soc_field_info_t soc_XLMAC_RX_LSS_STATUS_BCM88680_A0r_fields[] = { 4142 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO|SOCF_SIG|SOCF_INTR }, 4143 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 4144 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_SIG } 4145 }; 4146 4147 #endif 4148 #if defined(BCM_88675_A0) 4149 soc_field_info_t soc_XLMAC_RX_MAC_SAr_fields[] = { 4150 { RX_SAf, 48, 0, SOCF_LE } 4151 }; 4152 4153 #endif 4154 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 4155 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 4156 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4157 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 4158 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 4159 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 4160 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 4161 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4162 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 4163 defined(BCM_56980_B0) 4164 soc_field_info_t soc_XLMAC_RX_MAC_SA_BCM53400_A0r_fields[] = { 4165 { RX_SAf, 48, 0, SOCF_LE }, 4166 { SA_HIf, 16, 32, SOCF_LE }, 4167 { SA_LOf, 32, 0, SOCF_LE } 4168 }; 4169 4170 #endif 4171 #if defined(BCM_88270_A0) 4172 soc_field_info_t soc_XLMAC_RX_MAC_SA_BCM88270_A0r_fields[] = { 4173 { RX_SAf, 48, 0, SOCF_LE } 4174 }; 4175 4176 #endif 4177 #if defined(BCM_88375_A0) 4178 soc_field_info_t soc_XLMAC_RX_MAC_SA_BCM88375_A0r_fields[] = { 4179 { RX_SAf, 48, 0, SOCF_LE } 4180 }; 4181 4182 #endif 4183 #if defined(BCM_88375_B0) 4184 soc_field_info_t soc_XLMAC_RX_MAC_SA_BCM88375_B0r_fields[] = { 4185 { RX_SAf, 48, 0, SOCF_LE } 4186 }; 4187 4188 #endif 4189 #if defined(BCM_88470_A0) 4190 soc_field_info_t soc_XLMAC_RX_MAC_SA_BCM88470_A0r_fields[] = { 4191 { RX_SAf, 48, 0, SOCF_LE } 4192 }; 4193 4194 #endif 4195 #if defined(BCM_88470_B0) 4196 soc_field_info_t soc_XLMAC_RX_MAC_SA_BCM88470_B0r_fields[] = { 4197 { RX_SAf, 48, 0, SOCF_LE } 4198 }; 4199 4200 #endif 4201 #if defined(BCM_88675_B0) 4202 soc_field_info_t soc_XLMAC_RX_MAC_SA_BCM88675_B0r_fields[] = { 4203 { RX_SAf, 48, 0, SOCF_LE } 4204 }; 4205 4206 #endif 4207 #if defined(BCM_88680_A0) 4208 soc_field_info_t soc_XLMAC_RX_MAC_SA_BCM88680_A0r_fields[] = { 4209 { RX_SAf, 48, 0, SOCF_LE } 4210 }; 4211 4212 #endif 4213 #if defined(BCM_88675_A0) 4214 soc_field_info_t soc_XLMAC_RX_MAX_SIZEr_fields[] = { 4215 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 4216 }; 4217 4218 #endif 4219 #if defined(BCM_88270_A0) 4220 soc_field_info_t soc_XLMAC_RX_MAX_SIZE_BCM88270_A0r_fields[] = { 4221 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 4222 }; 4223 4224 #endif 4225 #if defined(BCM_88375_A0) 4226 soc_field_info_t soc_XLMAC_RX_MAX_SIZE_BCM88375_A0r_fields[] = { 4227 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 4228 }; 4229 4230 #endif 4231 #if defined(BCM_88375_B0) 4232 soc_field_info_t soc_XLMAC_RX_MAX_SIZE_BCM88375_B0r_fields[] = { 4233 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 4234 }; 4235 4236 #endif 4237 #if defined(BCM_88470_A0) 4238 soc_field_info_t soc_XLMAC_RX_MAX_SIZE_BCM88470_A0r_fields[] = { 4239 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 4240 }; 4241 4242 #endif 4243 #if defined(BCM_88470_B0) 4244 soc_field_info_t soc_XLMAC_RX_MAX_SIZE_BCM88470_B0r_fields[] = { 4245 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 4246 }; 4247 4248 #endif 4249 #if defined(BCM_88675_B0) 4250 soc_field_info_t soc_XLMAC_RX_MAX_SIZE_BCM88675_B0r_fields[] = { 4251 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 4252 }; 4253 4254 #endif 4255 #if defined(BCM_88680_A0) 4256 soc_field_info_t soc_XLMAC_RX_MAX_SIZE_BCM88680_A0r_fields[] = { 4257 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 4258 }; 4259 4260 #endif 4261 #if defined(BCM_88675_A0) 4262 soc_field_info_t soc_XLMAC_RX_VLAN_TAGr_fields[] = { 4263 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 4264 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 4265 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 4266 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 4267 }; 4268 4269 #endif 4270 #if defined(BCM_88270_A0) 4271 soc_field_info_t soc_XLMAC_RX_VLAN_TAG_BCM88270_A0r_fields[] = { 4272 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 4273 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 4274 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 4275 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 4276 }; 4277 4278 #endif 4279 #if defined(BCM_88375_A0) 4280 soc_field_info_t soc_XLMAC_RX_VLAN_TAG_BCM88375_A0r_fields[] = { 4281 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 4282 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 4283 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 4284 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 4285 }; 4286 4287 #endif 4288 #if defined(BCM_88375_B0) 4289 soc_field_info_t soc_XLMAC_RX_VLAN_TAG_BCM88375_B0r_fields[] = { 4290 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 4291 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 4292 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 4293 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 4294 }; 4295 4296 #endif 4297 #if defined(BCM_88470_A0) 4298 soc_field_info_t soc_XLMAC_RX_VLAN_TAG_BCM88470_A0r_fields[] = { 4299 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 4300 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 4301 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 4302 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 4303 }; 4304 4305 #endif 4306 #if defined(BCM_88470_B0) 4307 soc_field_info_t soc_XLMAC_RX_VLAN_TAG_BCM88470_B0r_fields[] = { 4308 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 4309 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 4310 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 4311 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 4312 }; 4313 4314 #endif 4315 #if defined(BCM_88675_B0) 4316 soc_field_info_t soc_XLMAC_RX_VLAN_TAG_BCM88675_B0r_fields[] = { 4317 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 4318 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 4319 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 4320 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 4321 }; 4322 4323 #endif 4324 #if defined(BCM_88680_A0) 4325 soc_field_info_t soc_XLMAC_RX_VLAN_TAG_BCM88680_A0r_fields[] = { 4326 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 4327 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 4328 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 4329 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 4330 }; 4331 4332 #endif 4333 #if defined(BCM_88675_A0) 4334 soc_field_info_t soc_XLMAC_SPARE0r_fields[] = { 4335 { RSVDf, 32, 0, SOCF_LE } 4336 }; 4337 4338 #endif 4339 #if defined(BCM_88675_A0) 4340 soc_field_info_t soc_XLMAC_SPARE1r_fields[] = { 4341 { RSVDf, 2, 0, SOCF_LE } 4342 }; 4343 4344 #endif 4345 #if defined(BCM_88270_A0) 4346 soc_field_info_t soc_XLMAC_SPARE0_BCM88270_A0r_fields[] = { 4347 { RSVDf, 32, 0, SOCF_LE } 4348 }; 4349 4350 #endif 4351 #if defined(BCM_88375_A0) 4352 soc_field_info_t soc_XLMAC_SPARE0_BCM88375_A0r_fields[] = { 4353 { RSVDf, 32, 0, SOCF_LE } 4354 }; 4355 4356 #endif 4357 #if defined(BCM_88375_B0) 4358 soc_field_info_t soc_XLMAC_SPARE0_BCM88375_B0r_fields[] = { 4359 { RSVDf, 32, 0, SOCF_LE } 4360 }; 4361 4362 #endif 4363 #if defined(BCM_88470_A0) 4364 soc_field_info_t soc_XLMAC_SPARE0_BCM88470_A0r_fields[] = { 4365 { RSVDf, 32, 0, SOCF_LE } 4366 }; 4367 4368 #endif 4369 #if defined(BCM_88470_B0) 4370 soc_field_info_t soc_XLMAC_SPARE0_BCM88470_B0r_fields[] = { 4371 { RSVDf, 32, 0, SOCF_LE } 4372 }; 4373 4374 #endif 4375 #if defined(BCM_88675_B0) 4376 soc_field_info_t soc_XLMAC_SPARE0_BCM88675_B0r_fields[] = { 4377 { RSVDf, 32, 0, SOCF_LE } 4378 }; 4379 4380 #endif 4381 #if defined(BCM_88680_A0) 4382 soc_field_info_t soc_XLMAC_SPARE0_BCM88680_A0r_fields[] = { 4383 { RSVDf, 32, 0, SOCF_LE } 4384 }; 4385 4386 #endif 4387 #if defined(BCM_88270_A0) 4388 soc_field_info_t soc_XLMAC_SPARE1_BCM88270_A0r_fields[] = { 4389 { RSVDf, 2, 0, SOCF_LE } 4390 }; 4391 4392 #endif 4393 #if defined(BCM_88375_A0) 4394 soc_field_info_t soc_XLMAC_SPARE1_BCM88375_A0r_fields[] = { 4395 { RSVDf, 2, 0, SOCF_LE } 4396 }; 4397 4398 #endif 4399 #if defined(BCM_88375_B0) 4400 soc_field_info_t soc_XLMAC_SPARE1_BCM88375_B0r_fields[] = { 4401 { RSVDf, 2, 0, SOCF_LE } 4402 }; 4403 4404 #endif 4405 #if defined(BCM_88470_A0) 4406 soc_field_info_t soc_XLMAC_SPARE1_BCM88470_A0r_fields[] = { 4407 { RSVDf, 2, 0, SOCF_LE } 4408 }; 4409 4410 #endif 4411 #if defined(BCM_88470_B0) 4412 soc_field_info_t soc_XLMAC_SPARE1_BCM88470_B0r_fields[] = { 4413 { RSVDf, 2, 0, SOCF_LE } 4414 }; 4415 4416 #endif 4417 #if defined(BCM_88675_B0) 4418 soc_field_info_t soc_XLMAC_SPARE1_BCM88675_B0r_fields[] = { 4419 { RSVDf, 2, 0, SOCF_LE } 4420 }; 4421 4422 #endif 4423 #if defined(BCM_88680_A0) 4424 soc_field_info_t soc_XLMAC_SPARE1_BCM88680_A0r_fields[] = { 4425 { RSVDf, 2, 0, SOCF_LE } 4426 }; 4427 4428 #endif 4429 #if defined(BCM_88675_A0) 4430 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUSTr_fields[] = { 4431 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4432 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE }, 4433 { TS_USE_CS_OFFSETf, 1, 15, 0 } 4434 }; 4435 4436 #endif 4437 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 4438 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUST_BCM56850_A0r_fields[] = { 4439 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4440 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE } 4441 }; 4442 4443 #endif 4444 #if defined(BCM_88270_A0) 4445 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUST_BCM88270_A0r_fields[] = { 4446 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4447 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE }, 4448 { TS_USE_CS_OFFSETf, 1, 15, 0 } 4449 }; 4450 4451 #endif 4452 #if defined(BCM_88375_A0) 4453 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUST_BCM88375_A0r_fields[] = { 4454 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4455 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE }, 4456 { TS_USE_CS_OFFSETf, 1, 15, 0 } 4457 }; 4458 4459 #endif 4460 #if defined(BCM_88375_B0) 4461 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUST_BCM88375_B0r_fields[] = { 4462 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4463 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE }, 4464 { TS_USE_CS_OFFSETf, 1, 15, 0 } 4465 }; 4466 4467 #endif 4468 #if defined(BCM_88470_A0) 4469 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUST_BCM88470_A0r_fields[] = { 4470 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4471 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE }, 4472 { TS_USE_CS_OFFSETf, 1, 15, 0 } 4473 }; 4474 4475 #endif 4476 #if defined(BCM_88470_B0) 4477 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUST_BCM88470_B0r_fields[] = { 4478 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4479 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE }, 4480 { TS_USE_CS_OFFSETf, 1, 15, 0 } 4481 }; 4482 4483 #endif 4484 #if defined(BCM_88675_B0) 4485 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUST_BCM88675_B0r_fields[] = { 4486 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4487 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE }, 4488 { TS_USE_CS_OFFSETf, 1, 15, 0 } 4489 }; 4490 4491 #endif 4492 #if defined(BCM_88680_A0) 4493 soc_field_info_t soc_XLMAC_TIMESTAMP_ADJUST_BCM88680_A0r_fields[] = { 4494 { TS_OSTS_ADJUSTf, 9, 0, SOCF_LE }, 4495 { TS_TSTS_ADJUSTf, 6, 9, SOCF_LE }, 4496 { TS_USE_CS_OFFSETf, 1, 15, 0 } 4497 }; 4498 4499 #endif 4500 #if defined(BCM_56860_A0) 4501 soc_field_info_t soc_XLMAC_TIMESTAMP_BYTE_ADJUSTr_fields[] = { 4502 { RX_TIMER_BYTE_ADJUSTf, 10, 11, SOCF_LE }, 4503 { RX_TIMER_BYTE_ADJUST_ENf, 1, 21, 0 }, 4504 { TX_TIMER_BYTE_ADJUSTf, 10, 0, SOCF_LE }, 4505 { TX_TIMER_BYTE_ADJUST_ENf, 1, 10, 0 } 4506 }; 4507 4508 #endif 4509 #if defined(BCM_88270_A0) 4510 soc_field_info_t soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88270_A0r_fields[] = { 4511 { RX_TIMER_BYTE_ADJUSTf, 10, 11, SOCF_LE }, 4512 { RX_TIMER_BYTE_ADJUST_ENf, 1, 21, 0 }, 4513 { TX_TIMER_BYTE_ADJUSTf, 10, 0, SOCF_LE }, 4514 { TX_TIMER_BYTE_ADJUST_ENf, 1, 10, 0 } 4515 }; 4516 4517 #endif 4518 #if defined(BCM_88375_B0) 4519 soc_field_info_t soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88375_B0r_fields[] = { 4520 { RX_TIMER_BYTE_ADJUSTf, 10, 11, SOCF_LE }, 4521 { RX_TIMER_BYTE_ADJUST_ENf, 1, 21, 0 }, 4522 { TX_TIMER_BYTE_ADJUSTf, 10, 0, SOCF_LE }, 4523 { TX_TIMER_BYTE_ADJUST_ENf, 1, 10, 0 } 4524 }; 4525 4526 #endif 4527 #if defined(BCM_88470_B0) 4528 soc_field_info_t soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88470_B0r_fields[] = { 4529 { RX_TIMER_BYTE_ADJUSTf, 10, 11, SOCF_LE }, 4530 { RX_TIMER_BYTE_ADJUST_ENf, 1, 21, 0 }, 4531 { TX_TIMER_BYTE_ADJUSTf, 10, 0, SOCF_LE }, 4532 { TX_TIMER_BYTE_ADJUST_ENf, 1, 10, 0 } 4533 }; 4534 4535 #endif 4536 #if defined(BCM_88675_B0) 4537 soc_field_info_t soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88675_B0r_fields[] = { 4538 { RX_TIMER_BYTE_ADJUSTf, 10, 11, SOCF_LE }, 4539 { RX_TIMER_BYTE_ADJUST_ENf, 1, 21, 0 }, 4540 { TX_TIMER_BYTE_ADJUSTf, 10, 0, SOCF_LE }, 4541 { TX_TIMER_BYTE_ADJUST_ENf, 1, 10, 0 } 4542 }; 4543 4544 #endif 4545 #if defined(BCM_88680_A0) 4546 soc_field_info_t soc_XLMAC_TIMESTAMP_BYTE_ADJUST_BCM88680_A0r_fields[] = { 4547 { RX_TIMER_BYTE_ADJUSTf, 10, 11, SOCF_LE }, 4548 { RX_TIMER_BYTE_ADJUST_ENf, 1, 21, 0 }, 4549 { TX_TIMER_BYTE_ADJUSTf, 10, 0, SOCF_LE }, 4550 { TX_TIMER_BYTE_ADJUST_ENf, 1, 10, 0 } 4551 }; 4552 4553 #endif 4554 #if defined(BCM_88675_A0) 4555 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNTr_fields[] = { 4556 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4557 }; 4558 4559 #endif 4560 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 4561 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 4562 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4563 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 4564 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 4565 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 4566 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 4567 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4568 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 4569 defined(BCM_56980_B0) 4570 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNT_BCM53400_A0r_fields[] = { 4571 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO } 4572 }; 4573 4574 #endif 4575 #if defined(BCM_88270_A0) 4576 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNT_BCM88270_A0r_fields[] = { 4577 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4578 }; 4579 4580 #endif 4581 #if defined(BCM_88375_A0) 4582 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNT_BCM88375_A0r_fields[] = { 4583 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4584 }; 4585 4586 #endif 4587 #if defined(BCM_88375_B0) 4588 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNT_BCM88375_B0r_fields[] = { 4589 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4590 }; 4591 4592 #endif 4593 #if defined(BCM_88470_A0) 4594 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNT_BCM88470_A0r_fields[] = { 4595 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4596 }; 4597 4598 #endif 4599 #if defined(BCM_88470_B0) 4600 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNT_BCM88470_B0r_fields[] = { 4601 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4602 }; 4603 4604 #endif 4605 #if defined(BCM_88675_B0) 4606 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNT_BCM88675_B0r_fields[] = { 4607 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4608 }; 4609 4610 #endif 4611 #if defined(BCM_88680_A0) 4612 soc_field_info_t soc_XLMAC_TXFIFO_CELL_CNT_BCM88680_A0r_fields[] = { 4613 { CELL_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4614 }; 4615 4616 #endif 4617 #if defined(BCM_88675_A0) 4618 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNTr_fields[] = { 4619 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4620 }; 4621 4622 #endif 4623 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 4624 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 4625 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4626 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 4627 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 4628 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 4629 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 4630 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4631 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 4632 defined(BCM_56980_B0) 4633 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM53400_A0r_fields[] = { 4634 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO } 4635 }; 4636 4637 #endif 4638 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 4639 defined(BCM_56860_A0) 4640 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM56850_A0r_fields[] = { 4641 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO } 4642 }; 4643 4644 #endif 4645 #if defined(BCM_88270_A0) 4646 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88270_A0r_fields[] = { 4647 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4648 }; 4649 4650 #endif 4651 #if defined(BCM_88375_A0) 4652 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88375_A0r_fields[] = { 4653 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4654 }; 4655 4656 #endif 4657 #if defined(BCM_88375_B0) 4658 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88375_B0r_fields[] = { 4659 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4660 }; 4661 4662 #endif 4663 #if defined(BCM_88470_A0) 4664 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88470_A0r_fields[] = { 4665 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4666 }; 4667 4668 #endif 4669 #if defined(BCM_88470_B0) 4670 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88470_B0r_fields[] = { 4671 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4672 }; 4673 4674 #endif 4675 #if defined(BCM_88675_B0) 4676 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88675_B0r_fields[] = { 4677 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4678 }; 4679 4680 #endif 4681 #if defined(BCM_88680_A0) 4682 soc_field_info_t soc_XLMAC_TXFIFO_CELL_REQ_CNT_BCM88680_A0r_fields[] = { 4683 { REQ_CNTf, 6, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 4684 }; 4685 4686 #endif 4687 #if defined(BCM_88675_A0) 4688 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUSr_fields[] = { 4689 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 4690 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 4691 }; 4692 4693 #endif 4694 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 4695 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 4696 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4697 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 4698 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 4699 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 4700 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 4701 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4702 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 4703 defined(BCM_56980_B0) 4704 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUS_BCM53400_A0r_fields[] = { 4705 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO }, 4706 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO } 4707 }; 4708 4709 #endif 4710 #if defined(BCM_88270_A0) 4711 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUS_BCM88270_A0r_fields[] = { 4712 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 4713 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 4714 }; 4715 4716 #endif 4717 #if defined(BCM_88375_A0) 4718 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUS_BCM88375_A0r_fields[] = { 4719 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 4720 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 4721 }; 4722 4723 #endif 4724 #if defined(BCM_88375_B0) 4725 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUS_BCM88375_B0r_fields[] = { 4726 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 4727 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 4728 }; 4729 4730 #endif 4731 #if defined(BCM_88470_A0) 4732 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUS_BCM88470_A0r_fields[] = { 4733 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 4734 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 4735 }; 4736 4737 #endif 4738 #if defined(BCM_88470_B0) 4739 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUS_BCM88470_B0r_fields[] = { 4740 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 4741 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 4742 }; 4743 4744 #endif 4745 #if defined(BCM_88675_B0) 4746 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUS_BCM88675_B0r_fields[] = { 4747 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 4748 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 4749 }; 4750 4751 #endif 4752 #if defined(BCM_88680_A0) 4753 soc_field_info_t soc_XLMAC_TX_CDC_ECC_STATUS_BCM88680_A0r_fields[] = { 4754 { TX_CDC_DOUBLE_BIT_ERRf, 1, 1, SOCF_RO|SOCF_SIG }, 4755 { TX_CDC_SINGLE_BIT_ERRf, 1, 0, SOCF_RO|SOCF_SIG } 4756 }; 4757 4758 #endif 4759 #if defined(BCM_88675_A0) 4760 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRLr_fields[] = { 4761 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4762 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4763 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4764 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 } 4765 }; 4766 4767 #endif 4768 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 4769 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 4770 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4771 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 4772 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 4773 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 4774 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 4775 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4776 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 4777 defined(BCM_56980_B0) 4778 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM53400_A0r_fields[] = { 4779 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4780 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4781 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4782 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 }, 4783 { XLMAC_TX_CRC_CORRUPT_CTRL_HIf, 3, 32, SOCF_LE }, 4784 { XLMAC_TX_CRC_CORRUPT_CTRL_LOf, 32, 0, SOCF_LE } 4785 }; 4786 4787 #endif 4788 #if defined(BCM_56860_A0) 4789 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM56860_A0r_fields[] = { 4790 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4791 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4792 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4793 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 }, 4794 { XLMAC_TX_CRC_CORRUPT_CTRL_HIf, 3, 32, SOCF_LE }, 4795 { XLMAC_TX_CRC_CORRUPT_CTRL_LOf, 32, 0, SOCF_LE } 4796 }; 4797 4798 #endif 4799 #if defined(BCM_88270_A0) 4800 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88270_A0r_fields[] = { 4801 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4802 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4803 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4804 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 } 4805 }; 4806 4807 #endif 4808 #if defined(BCM_88375_A0) 4809 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88375_A0r_fields[] = { 4810 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4811 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4812 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4813 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 } 4814 }; 4815 4816 #endif 4817 #if defined(BCM_88375_B0) 4818 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88375_B0r_fields[] = { 4819 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4820 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4821 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4822 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 } 4823 }; 4824 4825 #endif 4826 #if defined(BCM_88470_A0) 4827 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88470_A0r_fields[] = { 4828 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4829 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4830 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4831 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 } 4832 }; 4833 4834 #endif 4835 #if defined(BCM_88470_B0) 4836 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88470_B0r_fields[] = { 4837 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4838 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4839 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4840 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 } 4841 }; 4842 4843 #endif 4844 #if defined(BCM_88675_B0) 4845 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88675_B0r_fields[] = { 4846 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4847 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4848 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4849 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 } 4850 }; 4851 4852 #endif 4853 #if defined(BCM_88680_A0) 4854 soc_field_info_t soc_XLMAC_TX_CRC_CORRUPT_CTRL_BCM88680_A0r_fields[] = { 4855 { PROG_TX_CRCf, 32, 3, SOCF_LE }, 4856 { TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 4857 { TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 4858 { TX_ERR_CORRUPTS_CRCf, 1, 0, 0 } 4859 }; 4860 4861 #endif 4862 #if defined(BCM_88675_A0) 4863 soc_field_info_t soc_XLMAC_TX_CTRLr_fields[] = { 4864 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 4865 { CRC_MODEf, 2, 0, SOCF_LE }, 4866 { DISCARDf, 1, 2, 0 }, 4867 { EP_DISCARDf, 1, 37, 0 }, 4868 { PAD_ENf, 1, 4, 0 }, 4869 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 4870 { THROT_DENOMf, 8, 25, SOCF_LE }, 4871 { THROT_NUMf, 6, 19, SOCF_LE }, 4872 { TX_ANY_STARTf, 1, 3, 0 }, 4873 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 4874 { TX_THRESHOLDf, 4, 38, SOCF_LE } 4875 }; 4876 4877 #endif 4878 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 4879 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 4880 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4881 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 4882 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 4883 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 4884 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 4885 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4886 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 4887 defined(BCM_56980_B0) 4888 soc_field_info_t soc_XLMAC_TX_CTRL_BCM53400_A0r_fields[] = { 4889 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 4890 { CRC_MODEf, 2, 0, SOCF_LE }, 4891 { DISCARDf, 1, 2, 0 }, 4892 { EP_DISCARDf, 1, 37, 0 }, 4893 { PAD_ENf, 1, 4, 0 }, 4894 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 4895 { THROT_DENOMf, 8, 25, SOCF_LE }, 4896 { THROT_NUMf, 6, 19, SOCF_LE }, 4897 { TX_ANY_STARTf, 1, 3, 0 }, 4898 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 4899 { TX_THRESHOLDf, 4, 38, SOCF_LE }, 4900 { XLMAC_TX_CTRL_HIf, 10, 32, SOCF_LE }, 4901 { XLMAC_TX_CTRL_LOf, 32, 0, SOCF_LE } 4902 }; 4903 4904 #endif 4905 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 4906 soc_field_info_t soc_XLMAC_TX_CTRL_BCM56850_A0r_fields[] = { 4907 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 4908 { CRC_MODEf, 2, 0, SOCF_LE }, 4909 { DISCARDf, 1, 2, 0 }, 4910 { EP_DISCARDf, 1, 37, 0 }, 4911 { PAD_ENf, 1, 4, 0 }, 4912 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 4913 { THROT_DENOMf, 8, 25, SOCF_LE }, 4914 { THROT_NUMf, 6, 19, SOCF_LE }, 4915 { TX_ANY_STARTf, 1, 3, 0 }, 4916 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 4917 { XLMAC_TX_CTRL_HIf, 6, 32, SOCF_LE }, 4918 { XLMAC_TX_CTRL_LOf, 32, 0, SOCF_LE } 4919 }; 4920 4921 #endif 4922 #if defined(BCM_56860_A0) 4923 soc_field_info_t soc_XLMAC_TX_CTRL_BCM56860_A0r_fields[] = { 4924 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 4925 { CRC_MODEf, 2, 0, SOCF_LE }, 4926 { DISCARDf, 1, 2, 0 }, 4927 { EP_DISCARDf, 1, 37, 0 }, 4928 { PAD_ENf, 1, 4, 0 }, 4929 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 4930 { THROT_DENOMf, 8, 25, SOCF_LE }, 4931 { THROT_NUMf, 6, 19, SOCF_LE }, 4932 { TX_ANY_STARTf, 1, 3, 0 }, 4933 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 4934 { TX_THRESHOLDf, 4, 38, SOCF_LE }, 4935 { XLMAC_TX_CTRL_HIf, 10, 32, SOCF_LE }, 4936 { XLMAC_TX_CTRL_LOf, 32, 0, SOCF_LE } 4937 }; 4938 4939 #endif 4940 #if defined(BCM_88270_A0) 4941 soc_field_info_t soc_XLMAC_TX_CTRL_BCM88270_A0r_fields[] = { 4942 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 4943 { CRC_MODEf, 2, 0, SOCF_LE }, 4944 { DISCARDf, 1, 2, 0 }, 4945 { EP_DISCARDf, 1, 37, 0 }, 4946 { PAD_ENf, 1, 4, 0 }, 4947 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 4948 { THROT_DENOMf, 8, 25, SOCF_LE }, 4949 { THROT_NUMf, 6, 19, SOCF_LE }, 4950 { TX_ANY_STARTf, 1, 3, 0 }, 4951 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 4952 { TX_THRESHOLDf, 4, 38, SOCF_LE } 4953 }; 4954 4955 #endif 4956 #if defined(BCM_88375_A0) 4957 soc_field_info_t soc_XLMAC_TX_CTRL_BCM88375_A0r_fields[] = { 4958 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 4959 { CRC_MODEf, 2, 0, SOCF_LE }, 4960 { DISCARDf, 1, 2, 0 }, 4961 { EP_DISCARDf, 1, 37, 0 }, 4962 { PAD_ENf, 1, 4, 0 }, 4963 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 4964 { THROT_DENOMf, 8, 25, SOCF_LE }, 4965 { THROT_NUMf, 6, 19, SOCF_LE }, 4966 { TX_ANY_STARTf, 1, 3, 0 }, 4967 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 4968 { TX_THRESHOLDf, 4, 38, SOCF_LE } 4969 }; 4970 4971 #endif 4972 #if defined(BCM_88375_B0) 4973 soc_field_info_t soc_XLMAC_TX_CTRL_BCM88375_B0r_fields[] = { 4974 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 4975 { CRC_MODEf, 2, 0, SOCF_LE }, 4976 { DISCARDf, 1, 2, 0 }, 4977 { EP_DISCARDf, 1, 37, 0 }, 4978 { PAD_ENf, 1, 4, 0 }, 4979 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 4980 { THROT_DENOMf, 8, 25, SOCF_LE }, 4981 { THROT_NUMf, 6, 19, SOCF_LE }, 4982 { TX_ANY_STARTf, 1, 3, 0 }, 4983 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 4984 { TX_THRESHOLDf, 4, 38, SOCF_LE } 4985 }; 4986 4987 #endif 4988 #if defined(BCM_88470_A0) 4989 soc_field_info_t soc_XLMAC_TX_CTRL_BCM88470_A0r_fields[] = { 4990 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 4991 { CRC_MODEf, 2, 0, SOCF_LE }, 4992 { DISCARDf, 1, 2, 0 }, 4993 { EP_DISCARDf, 1, 37, 0 }, 4994 { PAD_ENf, 1, 4, 0 }, 4995 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 4996 { THROT_DENOMf, 8, 25, SOCF_LE }, 4997 { THROT_NUMf, 6, 19, SOCF_LE }, 4998 { TX_ANY_STARTf, 1, 3, 0 }, 4999 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 5000 { TX_THRESHOLDf, 4, 38, SOCF_LE } 5001 }; 5002 5003 #endif 5004 #if defined(BCM_88470_B0) 5005 soc_field_info_t soc_XLMAC_TX_CTRL_BCM88470_B0r_fields[] = { 5006 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 5007 { CRC_MODEf, 2, 0, SOCF_LE }, 5008 { DISCARDf, 1, 2, 0 }, 5009 { EP_DISCARDf, 1, 37, 0 }, 5010 { PAD_ENf, 1, 4, 0 }, 5011 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 5012 { THROT_DENOMf, 8, 25, SOCF_LE }, 5013 { THROT_NUMf, 6, 19, SOCF_LE }, 5014 { TX_ANY_STARTf, 1, 3, 0 }, 5015 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 5016 { TX_THRESHOLDf, 4, 38, SOCF_LE } 5017 }; 5018 5019 #endif 5020 #if defined(BCM_88675_B0) 5021 soc_field_info_t soc_XLMAC_TX_CTRL_BCM88675_B0r_fields[] = { 5022 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 5023 { CRC_MODEf, 2, 0, SOCF_LE }, 5024 { DISCARDf, 1, 2, 0 }, 5025 { EP_DISCARDf, 1, 37, 0 }, 5026 { PAD_ENf, 1, 4, 0 }, 5027 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 5028 { THROT_DENOMf, 8, 25, SOCF_LE }, 5029 { THROT_NUMf, 6, 19, SOCF_LE }, 5030 { TX_ANY_STARTf, 1, 3, 0 }, 5031 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 5032 { TX_THRESHOLDf, 4, 38, SOCF_LE } 5033 }; 5034 5035 #endif 5036 #if defined(BCM_88680_A0) 5037 soc_field_info_t soc_XLMAC_TX_CTRL_BCM88680_A0r_fields[] = { 5038 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 5039 { CRC_MODEf, 2, 0, SOCF_LE }, 5040 { DISCARDf, 1, 2, 0 }, 5041 { EP_DISCARDf, 1, 37, 0 }, 5042 { PAD_ENf, 1, 4, 0 }, 5043 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 5044 { THROT_DENOMf, 8, 25, SOCF_LE }, 5045 { THROT_NUMf, 6, 19, SOCF_LE }, 5046 { TX_ANY_STARTf, 1, 3, 0 }, 5047 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 5048 { TX_THRESHOLDf, 4, 38, SOCF_LE } 5049 }; 5050 5051 #endif 5052 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 5053 defined(BCM_56670_A0) || defined(BCM_56670_B0) 5054 soc_field_info_t soc_XLMAC_TX_EP_CREDITS_CONFIGr_fields[] = { 5055 { NO_CREDITSf, 6, 0, SOCF_LE } 5056 }; 5057 5058 #endif 5059 #if defined(BCM_88675_A0) 5060 soc_field_info_t soc_XLMAC_TX_LLFC_MSG_FIELDSr_fields[] = { 5061 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 5062 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 5063 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 5064 }; 5065 5066 #endif 5067 #if defined(BCM_88270_A0) 5068 soc_field_info_t soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88270_A0r_fields[] = { 5069 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 5070 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 5071 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 5072 }; 5073 5074 #endif 5075 #if defined(BCM_88375_A0) 5076 soc_field_info_t soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88375_A0r_fields[] = { 5077 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 5078 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 5079 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 5080 }; 5081 5082 #endif 5083 #if defined(BCM_88375_B0) 5084 soc_field_info_t soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88375_B0r_fields[] = { 5085 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 5086 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 5087 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 5088 }; 5089 5090 #endif 5091 #if defined(BCM_88470_A0) 5092 soc_field_info_t soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88470_A0r_fields[] = { 5093 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 5094 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 5095 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 5096 }; 5097 5098 #endif 5099 #if defined(BCM_88470_B0) 5100 soc_field_info_t soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88470_B0r_fields[] = { 5101 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 5102 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 5103 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 5104 }; 5105 5106 #endif 5107 #if defined(BCM_88675_B0) 5108 soc_field_info_t soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88675_B0r_fields[] = { 5109 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 5110 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 5111 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 5112 }; 5113 5114 #endif 5115 #if defined(BCM_88680_A0) 5116 soc_field_info_t soc_XLMAC_TX_LLFC_MSG_FIELDS_BCM88680_A0r_fields[] = { 5117 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 5118 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 5119 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 5120 }; 5121 5122 #endif 5123 #if defined(BCM_88675_A0) 5124 soc_field_info_t soc_XLMAC_TX_MAC_SAr_fields[] = { 5125 { CTRL_SAf, 48, 0, SOCF_LE } 5126 }; 5127 5128 #endif 5129 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 5130 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 5131 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5132 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 5133 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 5134 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 5135 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5136 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5137 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5138 defined(BCM_56980_B0) 5139 soc_field_info_t soc_XLMAC_TX_MAC_SA_BCM53400_A0r_fields[] = { 5140 { CTRL_SAf, 48, 0, SOCF_LE }, 5141 { SA_HIf, 16, 32, SOCF_LE }, 5142 { SA_LOf, 32, 0, SOCF_LE } 5143 }; 5144 5145 #endif 5146 #if defined(BCM_88270_A0) 5147 soc_field_info_t soc_XLMAC_TX_MAC_SA_BCM88270_A0r_fields[] = { 5148 { CTRL_SAf, 48, 0, SOCF_LE } 5149 }; 5150 5151 #endif 5152 #if defined(BCM_88375_A0) 5153 soc_field_info_t soc_XLMAC_TX_MAC_SA_BCM88375_A0r_fields[] = { 5154 { CTRL_SAf, 48, 0, SOCF_LE } 5155 }; 5156 5157 #endif 5158 #if defined(BCM_88375_B0) 5159 soc_field_info_t soc_XLMAC_TX_MAC_SA_BCM88375_B0r_fields[] = { 5160 { CTRL_SAf, 48, 0, SOCF_LE } 5161 }; 5162 5163 #endif 5164 #if defined(BCM_88470_A0) 5165 soc_field_info_t soc_XLMAC_TX_MAC_SA_BCM88470_A0r_fields[] = { 5166 { CTRL_SAf, 48, 0, SOCF_LE } 5167 }; 5168 5169 #endif 5170 #if defined(BCM_88470_B0) 5171 soc_field_info_t soc_XLMAC_TX_MAC_SA_BCM88470_B0r_fields[] = { 5172 { CTRL_SAf, 48, 0, SOCF_LE } 5173 }; 5174 5175 #endif 5176 #if defined(BCM_88675_B0) 5177 soc_field_info_t soc_XLMAC_TX_MAC_SA_BCM88675_B0r_fields[] = { 5178 { CTRL_SAf, 48, 0, SOCF_LE } 5179 }; 5180 5181 #endif 5182 #if defined(BCM_88680_A0) 5183 soc_field_info_t soc_XLMAC_TX_MAC_SA_BCM88680_A0r_fields[] = { 5184 { CTRL_SAf, 48, 0, SOCF_LE } 5185 }; 5186 5187 #endif 5188 #if defined(BCM_88675_A0) 5189 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATAr_fields[] = { 5190 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO|SOCF_SIG }, 5191 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }, 5192 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO|SOCF_SIG } 5193 }; 5194 5195 #endif 5196 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 5197 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 5198 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5199 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 5200 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 5201 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 5202 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5203 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5204 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5205 defined(BCM_56980_B0) 5206 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM53400_A0r_fields[] = { 5207 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO }, 5208 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO }, 5209 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO } 5210 }; 5211 5212 #endif 5213 #if defined(BCM_88270_A0) 5214 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88270_A0r_fields[] = { 5215 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO|SOCF_SIG }, 5216 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }, 5217 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO|SOCF_SIG } 5218 }; 5219 5220 #endif 5221 #if defined(BCM_88375_A0) 5222 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88375_A0r_fields[] = { 5223 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO|SOCF_SIG }, 5224 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }, 5225 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO|SOCF_SIG } 5226 }; 5227 5228 #endif 5229 #if defined(BCM_88375_B0) 5230 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88375_B0r_fields[] = { 5231 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO|SOCF_SIG }, 5232 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }, 5233 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO|SOCF_SIG } 5234 }; 5235 5236 #endif 5237 #if defined(BCM_88470_A0) 5238 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88470_A0r_fields[] = { 5239 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO|SOCF_SIG }, 5240 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }, 5241 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO|SOCF_SIG } 5242 }; 5243 5244 #endif 5245 #if defined(BCM_88470_B0) 5246 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88470_B0r_fields[] = { 5247 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO|SOCF_SIG }, 5248 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }, 5249 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO|SOCF_SIG } 5250 }; 5251 5252 #endif 5253 #if defined(BCM_88675_B0) 5254 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88675_B0r_fields[] = { 5255 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO|SOCF_SIG }, 5256 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }, 5257 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO|SOCF_SIG } 5258 }; 5259 5260 #endif 5261 #if defined(BCM_88680_A0) 5262 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_DATA_BCM88680_A0r_fields[] = { 5263 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO|SOCF_SIG }, 5264 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO|SOCF_SIG }, 5265 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO|SOCF_SIG } 5266 }; 5267 5268 #endif 5269 #if defined(BCM_88675_A0) 5270 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUSr_fields[] = { 5271 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5272 }; 5273 5274 #endif 5275 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 5276 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 5277 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5278 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 5279 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 5280 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 5281 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5282 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5283 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5284 defined(BCM_56980_B0) 5285 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM53400_A0r_fields[] = { 5286 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO } 5287 }; 5288 5289 #endif 5290 #if defined(BCM_88270_A0) 5291 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88270_A0r_fields[] = { 5292 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5293 }; 5294 5295 #endif 5296 #if defined(BCM_88375_A0) 5297 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88375_A0r_fields[] = { 5298 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5299 }; 5300 5301 #endif 5302 #if defined(BCM_88375_B0) 5303 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88375_B0r_fields[] = { 5304 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5305 }; 5306 5307 #endif 5308 #if defined(BCM_88470_A0) 5309 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88470_A0r_fields[] = { 5310 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5311 }; 5312 5313 #endif 5314 #if defined(BCM_88470_B0) 5315 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88470_B0r_fields[] = { 5316 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5317 }; 5318 5319 #endif 5320 #if defined(BCM_88675_B0) 5321 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88675_B0r_fields[] = { 5322 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5323 }; 5324 5325 #endif 5326 #if defined(BCM_88680_A0) 5327 soc_field_info_t soc_XLMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88680_A0r_fields[] = { 5328 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5329 }; 5330 5331 #endif 5332 #if defined(BCM_2801PM_A0) 5333 soc_field_info_t soc_XLMAC_VERSION_IDr_fields[] = { 5334 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5335 }; 5336 5337 #endif 5338 #if defined(BCM_53400_A0) || defined(BCM_56260_A0) || \ 5339 defined(BCM_56560_A0) || defined(BCM_56960_A0) || \ 5340 defined(BCM_56965_A0) 5341 soc_field_info_t soc_XLMAC_VERSION_ID_BCM53400_A0r_fields[] = { 5342 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 5343 }; 5344 5345 #endif 5346 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 5347 defined(BCM_56670_A0) || defined(BCM_56670_B0) 5348 soc_field_info_t soc_XLMAC_VERSION_ID_BCM53570_A0r_fields[] = { 5349 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 5350 }; 5351 5352 #endif 5353 #if defined(BCM_56150_A0) 5354 soc_field_info_t soc_XLMAC_VERSION_ID_BCM56150_A0r_fields[] = { 5355 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 5356 }; 5357 5358 #endif 5359 #if defined(BCM_56850_A0) 5360 soc_field_info_t soc_XLMAC_VERSION_ID_BCM56850_A0r_fields[] = { 5361 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 5362 }; 5363 5364 #endif 5365 #if defined(BCM_56860_A0) 5366 soc_field_info_t soc_XLMAC_VERSION_ID_BCM56860_A0r_fields[] = { 5367 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 5368 }; 5369 5370 #endif 5371 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5372 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 5373 defined(BCM_56980_A0) || defined(BCM_56980_B0) 5374 soc_field_info_t soc_XLMAC_VERSION_ID_BCM56970_A0r_fields[] = { 5375 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 5376 }; 5377 5378 #endif 5379 #if defined(BCM_88270_A0) 5380 soc_field_info_t soc_XLMAC_VERSION_ID_BCM88270_A0r_fields[] = { 5381 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5382 }; 5383 5384 #endif 5385 #if defined(BCM_88375_A0) 5386 soc_field_info_t soc_XLMAC_VERSION_ID_BCM88375_A0r_fields[] = { 5387 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5388 }; 5389 5390 #endif 5391 #if defined(BCM_88375_B0) 5392 soc_field_info_t soc_XLMAC_VERSION_ID_BCM88375_B0r_fields[] = { 5393 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5394 }; 5395 5396 #endif 5397 #if defined(BCM_88470_A0) 5398 soc_field_info_t soc_XLMAC_VERSION_ID_BCM88470_A0r_fields[] = { 5399 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5400 }; 5401 5402 #endif 5403 #if defined(BCM_88470_B0) 5404 soc_field_info_t soc_XLMAC_VERSION_ID_BCM88470_B0r_fields[] = { 5405 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5406 }; 5407 5408 #endif 5409 #if defined(BCM_88675_A0) 5410 soc_field_info_t soc_XLMAC_VERSION_ID_BCM88675_A0r_fields[] = { 5411 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5412 }; 5413 5414 #endif 5415 #if defined(BCM_88675_B0) 5416 soc_field_info_t soc_XLMAC_VERSION_ID_BCM88675_B0r_fields[] = { 5417 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5418 }; 5419 5420 #endif 5421 #if defined(BCM_88680_A0) 5422 soc_field_info_t soc_XLMAC_VERSION_ID_BCM88680_A0r_fields[] = { 5423 { XLMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO|SOCF_SIG } 5424 }; 5425 5426 #endif 5427 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 5428 defined(BCM_56670_A0) || defined(BCM_56670_B0) 5429 soc_field_info_t soc_XLMIB_RSCHCRCr_fields[] = { 5430 { COUNTf, 40, 0, SOCF_LE|SOCF_RO|SOCF_RES } 5431 }; 5432 5433 #endif 5434 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 5435 defined(BCM_56670_A0) || defined(BCM_56670_B0) 5436 soc_field_info_t soc_XLPMIB_XTHOLr_fields[] = { 5437 { COUNTf, 40, 0, SOCF_LE|SOCF_RO|SOCF_RES } 5438 }; 5439 5440 #endif 5441 #if defined(BCM_56150_A0) 5442 soc_field_info_t soc_XLPORT_BOD_OVERFLOW_ERRORr_fields[] = { 5443 { XLPORT_XLP0_BOD_FULL_ERRORf, 1, 0, SOCF_RO } 5444 }; 5445 5446 #endif 5447 #if defined(BCM_88675_A0) 5448 soc_field_info_t soc_XLPORT_CNTMAXSIZEr_fields[] = { 5449 { CNTMAXSIZEf, 14, 0, SOCF_LE } 5450 }; 5451 5452 #endif 5453 #if defined(BCM_88270_A0) 5454 soc_field_info_t soc_XLPORT_CNTMAXSIZE_BCM88270_A0r_fields[] = { 5455 { CNTMAXSIZEf, 14, 0, SOCF_LE } 5456 }; 5457 5458 #endif 5459 #if defined(BCM_88375_A0) 5460 soc_field_info_t soc_XLPORT_CNTMAXSIZE_BCM88375_A0r_fields[] = { 5461 { CNTMAXSIZEf, 14, 0, SOCF_LE } 5462 }; 5463 5464 #endif 5465 #if defined(BCM_88375_B0) 5466 soc_field_info_t soc_XLPORT_CNTMAXSIZE_BCM88375_B0r_fields[] = { 5467 { CNTMAXSIZEf, 14, 0, SOCF_LE } 5468 }; 5469 5470 #endif 5471 #if defined(BCM_88470_A0) 5472 soc_field_info_t soc_XLPORT_CNTMAXSIZE_BCM88470_A0r_fields[] = { 5473 { CNTMAXSIZEf, 14, 0, SOCF_LE } 5474 }; 5475 5476 #endif 5477 #if defined(BCM_88470_B0) 5478 soc_field_info_t soc_XLPORT_CNTMAXSIZE_BCM88470_B0r_fields[] = { 5479 { CNTMAXSIZEf, 14, 0, SOCF_LE } 5480 }; 5481 5482 #endif 5483 #if defined(BCM_88675_B0) 5484 soc_field_info_t soc_XLPORT_CNTMAXSIZE_BCM88675_B0r_fields[] = { 5485 { CNTMAXSIZEf, 14, 0, SOCF_LE } 5486 }; 5487 5488 #endif 5489 #if defined(BCM_88680_A0) 5490 soc_field_info_t soc_XLPORT_CNTMAXSIZE_BCM88680_A0r_fields[] = { 5491 { CNTMAXSIZEf, 14, 0, SOCF_LE } 5492 }; 5493 5494 #endif 5495 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 5496 defined(BCM_88732_A0) 5497 soc_field_info_t soc_XLPORT_CONFIGr_fields[] = { 5498 { HIGIG2_MODEf, 1, 15, 0 }, 5499 { HIGIG_MODEf, 1, 1, 0 }, 5500 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 5501 { LLFC_ENf, 1, 14, 0 }, 5502 { MH_INBANDf, 1, 13, 0 }, 5503 { MY_MODIDf, 7, 5, SOCF_LE }, 5504 { PFC_ENABLEf, 1, 18, 0 }, 5505 { XLP_RES_0f, 1, 0, SOCF_RES }, 5506 { XLP_RES_4_3f, 2, 3, SOCF_LE|SOCF_RES }, 5507 { XPAUSE_ENf, 1, 2, 0 }, 5508 { XPAUSE_RX_ENf, 1, 16, 0 }, 5509 { XPAUSE_TX_ENf, 1, 17, 0 } 5510 }; 5511 5512 #endif 5513 #if defined(BCM_53400_A0) || defined(BCM_56160_A0) || \ 5514 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5515 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 5516 defined(BCM_56560_B0) || defined(BCM_56960_A0) || \ 5517 defined(BCM_56965_A0) 5518 soc_field_info_t soc_XLPORT_CONFIG_BCM53400_A0r_fields[] = { 5519 { HIGIG2_MODEf, 1, 11, 0 }, 5520 { HIGIG_MODEf, 1, 10, 0 }, 5521 { MY_MODIDf, 8, 1, SOCF_LE }, 5522 { RESERVED_0f, 1, 0, SOCF_RES }, 5523 { RESERVED_15_12f, 4, 12, SOCF_LE|SOCF_RES }, 5524 { RESERVED_9f, 1, 9, SOCF_RES } 5525 }; 5526 5527 #endif 5528 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 5529 defined(BCM_56860_A0) 5530 soc_field_info_t soc_XLPORT_CONFIG_BCM56850_A0r_fields[] = { 5531 { HIGIG2_MODEf, 1, 11, 0 }, 5532 { HIGIG_MODEf, 1, 10, 0 }, 5533 { HONOR_PAUSE_FOR_E2Ef, 1, 9, 0 }, 5534 { MY_MODIDf, 8, 1, SOCF_LE }, 5535 { RESERVED_15_12f, 4, 12, SOCF_LE|SOCF_RES }, 5536 { RX_E2ECC_ENf, 1, 0, 0 } 5537 }; 5538 5539 #endif 5540 #if defined(BCM_88270_A0) 5541 soc_field_info_t soc_XLPORT_CONFIG_BCM88270_A0r_fields[] = { 5542 { FIELD_0_0f, 1, 0, 0 }, 5543 { FIELD_12_15f, 4, 12, SOCF_LE }, 5544 { FIELD_9_9f, 1, 9, 0 }, 5545 { HIGIG2_MODEf, 1, 11, 0 }, 5546 { HIGIG_MODEf, 1, 10, 0 }, 5547 { MY_MODIDf, 8, 1, SOCF_LE } 5548 }; 5549 5550 #endif 5551 #if defined(BCM_88375_A0) 5552 soc_field_info_t soc_XLPORT_CONFIG_BCM88375_A0r_fields[] = { 5553 { FIELD_0_0f, 1, 0, 0 }, 5554 { FIELD_12_15f, 4, 12, SOCF_LE }, 5555 { FIELD_9_9f, 1, 9, 0 }, 5556 { HIGIG2_MODEf, 1, 11, 0 }, 5557 { HIGIG_MODEf, 1, 10, 0 }, 5558 { MY_MODIDf, 8, 1, SOCF_LE } 5559 }; 5560 5561 #endif 5562 #if defined(BCM_88375_B0) 5563 soc_field_info_t soc_XLPORT_CONFIG_BCM88375_B0r_fields[] = { 5564 { FIELD_0_0f, 1, 0, 0 }, 5565 { FIELD_12_15f, 4, 12, SOCF_LE }, 5566 { FIELD_9_9f, 1, 9, 0 }, 5567 { HIGIG2_MODEf, 1, 11, 0 }, 5568 { HIGIG_MODEf, 1, 10, 0 }, 5569 { MY_MODIDf, 8, 1, SOCF_LE } 5570 }; 5571 5572 #endif 5573 #if defined(BCM_88470_A0) 5574 soc_field_info_t soc_XLPORT_CONFIG_BCM88470_A0r_fields[] = { 5575 { FIELD_0_0f, 1, 0, 0 }, 5576 { FIELD_12_15f, 4, 12, SOCF_LE }, 5577 { FIELD_9_9f, 1, 9, 0 }, 5578 { HIGIG2_MODEf, 1, 11, 0 }, 5579 { HIGIG_MODEf, 1, 10, 0 }, 5580 { MY_MODIDf, 8, 1, SOCF_LE } 5581 }; 5582 5583 #endif 5584 #if defined(BCM_88470_B0) 5585 soc_field_info_t soc_XLPORT_CONFIG_BCM88470_B0r_fields[] = { 5586 { FIELD_0_0f, 1, 0, 0 }, 5587 { FIELD_12_15f, 4, 12, SOCF_LE }, 5588 { FIELD_9_9f, 1, 9, 0 }, 5589 { HIGIG2_MODEf, 1, 11, 0 }, 5590 { HIGIG_MODEf, 1, 10, 0 }, 5591 { MY_MODIDf, 8, 1, SOCF_LE } 5592 }; 5593 5594 #endif 5595 #if defined(BCM_88675_A0) 5596 soc_field_info_t soc_XLPORT_CONFIG_BCM88675_A0r_fields[] = { 5597 { FIELD_0_0f, 1, 0, 0 }, 5598 { FIELD_12_15f, 4, 12, SOCF_LE }, 5599 { FIELD_9_9f, 1, 9, 0 }, 5600 { HIGIG2_MODEf, 1, 11, 0 }, 5601 { HIGIG_MODEf, 1, 10, 0 }, 5602 { MY_MODIDf, 8, 1, SOCF_LE } 5603 }; 5604 5605 #endif 5606 #if defined(BCM_88675_B0) 5607 soc_field_info_t soc_XLPORT_CONFIG_BCM88675_B0r_fields[] = { 5608 { FIELD_0_0f, 1, 0, 0 }, 5609 { FIELD_12_15f, 4, 12, SOCF_LE }, 5610 { FIELD_9_9f, 1, 9, 0 }, 5611 { HIGIG2_MODEf, 1, 11, 0 }, 5612 { HIGIG_MODEf, 1, 10, 0 }, 5613 { MY_MODIDf, 8, 1, SOCF_LE } 5614 }; 5615 5616 #endif 5617 #if defined(BCM_88680_A0) 5618 soc_field_info_t soc_XLPORT_CONFIG_BCM88680_A0r_fields[] = { 5619 { FIELD_0_0f, 1, 0, 0 }, 5620 { FIELD_12_15f, 4, 12, SOCF_LE }, 5621 { FIELD_9_9f, 1, 9, 0 }, 5622 { HIGIG2_MODEf, 1, 11, 0 }, 5623 { HIGIG_MODEf, 1, 10, 0 }, 5624 { MY_MODIDf, 8, 1, SOCF_LE } 5625 }; 5626 5627 #endif 5628 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 5629 defined(BCM_88732_A0) 5630 soc_field_info_t soc_XLPORT_ECC_CONTROLr_fields[] = { 5631 { MIB_RSC_MEM_ENf, 1, 2, 0 }, 5632 { MIB_TSC_MEM_ENf, 1, 1, 0 }, 5633 { TXFIFO_MEM_ENf, 1, 0, 0 } 5634 }; 5635 5636 #endif 5637 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 5638 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 5639 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5640 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 5641 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 5642 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5643 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5644 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5645 defined(BCM_56980_B0) 5646 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM53400_A0r_fields[] = { 5647 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5648 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5649 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5650 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5651 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5652 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5653 }; 5654 5655 #endif 5656 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 5657 defined(BCM_56670_A0) || defined(BCM_56670_B0) 5658 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM53570_A0r_fields[] = { 5659 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5660 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5661 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5662 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5663 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5664 { MIB_TSC_MEM_ENf, 1, 0, 0 }, 5665 { P_MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 12, 0 }, 5666 { P_MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 13, 0 }, 5667 { P_MIB_RSC_MEM_ENf, 1, 11, 0 }, 5668 { P_MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 9, 0 }, 5669 { P_MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 10, 0 }, 5670 { P_MIB_TSC_MEM_ENf, 1, 8, 0 }, 5671 { RESERVED_7_6f, 2, 6, SOCF_LE|SOCF_RO|SOCF_RES } 5672 }; 5673 5674 #endif 5675 #if defined(BCM_56150_A0) 5676 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM56150_A0r_fields[] = { 5677 { BOD_ECC_ENABLEf, 1, 6, 0 }, 5678 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5679 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5680 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5681 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5682 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5683 { MIB_TSC_MEM_ENf, 1, 0, 0 }, 5684 { TXFIFO_ECC_ENf, 1, 8, 0 }, 5685 { XLP0_EN_COR_ERR_RPTf, 1, 7, 0 } 5686 }; 5687 5688 #endif 5689 #if defined(BCM_88270_A0) 5690 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM88270_A0r_fields[] = { 5691 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5692 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5693 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5694 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5695 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5696 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5697 }; 5698 5699 #endif 5700 #if defined(BCM_88375_A0) 5701 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM88375_A0r_fields[] = { 5702 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5703 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5704 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5705 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5706 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5707 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5708 }; 5709 5710 #endif 5711 #if defined(BCM_88375_B0) 5712 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM88375_B0r_fields[] = { 5713 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5714 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5715 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5716 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5717 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5718 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5719 }; 5720 5721 #endif 5722 #if defined(BCM_88470_A0) 5723 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM88470_A0r_fields[] = { 5724 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5725 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5726 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5727 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5728 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5729 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5730 }; 5731 5732 #endif 5733 #if defined(BCM_88470_B0) 5734 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM88470_B0r_fields[] = { 5735 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5736 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5737 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5738 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5739 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5740 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5741 }; 5742 5743 #endif 5744 #if defined(BCM_88675_A0) 5745 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM88675_A0r_fields[] = { 5746 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5747 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5748 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5749 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5750 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5751 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5752 }; 5753 5754 #endif 5755 #if defined(BCM_88675_B0) 5756 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM88675_B0r_fields[] = { 5757 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5758 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5759 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5760 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5761 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5762 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5763 }; 5764 5765 #endif 5766 #if defined(BCM_88680_A0) 5767 soc_field_info_t soc_XLPORT_ECC_CONTROL_BCM88680_A0r_fields[] = { 5768 { MIB_RSC0_MEM_EN_COR_ERR_RPTf, 1, 4, 0 }, 5769 { MIB_RSC1_MEM_EN_COR_ERR_RPTf, 1, 5, 0 }, 5770 { MIB_RSC_MEM_ENf, 1, 3, 0 }, 5771 { MIB_TSC0_MEM_EN_COR_ERR_RPTf, 1, 1, 0 }, 5772 { MIB_TSC1_MEM_EN_COR_ERR_RPTf, 1, 2, 0 }, 5773 { MIB_TSC_MEM_ENf, 1, 0, 0 } 5774 }; 5775 5776 #endif 5777 #if defined(BCM_88675_A0) 5778 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATEr_fields[] = { 5779 { CORE0f, 1, 0, 0 } 5780 }; 5781 5782 #endif 5783 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 5784 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 5785 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5786 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 5787 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 5788 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 5789 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5790 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5791 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5792 defined(BCM_56980_B0) 5793 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATE_BCM53400_A0r_fields[] = { 5794 { CORE0f, 1, 0, SOCF_RES } 5795 }; 5796 5797 #endif 5798 #if defined(BCM_88270_A0) 5799 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATE_BCM88270_A0r_fields[] = { 5800 { CORE0f, 1, 0, 0 } 5801 }; 5802 5803 #endif 5804 #if defined(BCM_88375_A0) 5805 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATE_BCM88375_A0r_fields[] = { 5806 { CORE0f, 1, 0, 0 } 5807 }; 5808 5809 #endif 5810 #if defined(BCM_88375_B0) 5811 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATE_BCM88375_B0r_fields[] = { 5812 { CORE0f, 1, 0, 0 } 5813 }; 5814 5815 #endif 5816 #if defined(BCM_88470_A0) 5817 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATE_BCM88470_A0r_fields[] = { 5818 { CORE0f, 1, 0, 0 } 5819 }; 5820 5821 #endif 5822 #if defined(BCM_88470_B0) 5823 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATE_BCM88470_B0r_fields[] = { 5824 { CORE0f, 1, 0, 0 } 5825 }; 5826 5827 #endif 5828 #if defined(BCM_88675_B0) 5829 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATE_BCM88675_B0r_fields[] = { 5830 { CORE0f, 1, 0, 0 } 5831 }; 5832 5833 #endif 5834 #if defined(BCM_88680_A0) 5835 soc_field_info_t soc_XLPORT_EEE_CLOCK_GATE_BCM88680_A0r_fields[] = { 5836 { CORE0f, 1, 0, 0 } 5837 }; 5838 5839 #endif 5840 #if defined(BCM_88675_A0) 5841 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTERr_fields[] = { 5842 { COUNTf, 32, 0, SOCF_LE } 5843 }; 5844 5845 #endif 5846 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 5847 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 5848 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5849 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 5850 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 5851 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 5852 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5853 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5854 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5855 defined(BCM_56980_B0) 5856 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM53400_A0r_fields[] = { 5857 { COUNTf, 32, 0, SOCF_LE|SOCF_RES } 5858 }; 5859 5860 #endif 5861 #if defined(BCM_88270_A0) 5862 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88270_A0r_fields[] = { 5863 { COUNTf, 32, 0, SOCF_LE } 5864 }; 5865 5866 #endif 5867 #if defined(BCM_88375_A0) 5868 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88375_A0r_fields[] = { 5869 { COUNTf, 32, 0, SOCF_LE } 5870 }; 5871 5872 #endif 5873 #if defined(BCM_88375_B0) 5874 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88375_B0r_fields[] = { 5875 { COUNTf, 32, 0, SOCF_LE } 5876 }; 5877 5878 #endif 5879 #if defined(BCM_88470_A0) 5880 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88470_A0r_fields[] = { 5881 { COUNTf, 32, 0, SOCF_LE } 5882 }; 5883 5884 #endif 5885 #if defined(BCM_88470_B0) 5886 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88470_B0r_fields[] = { 5887 { COUNTf, 32, 0, SOCF_LE } 5888 }; 5889 5890 #endif 5891 #if defined(BCM_88675_B0) 5892 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88675_B0r_fields[] = { 5893 { COUNTf, 32, 0, SOCF_LE } 5894 }; 5895 5896 #endif 5897 #if defined(BCM_88680_A0) 5898 soc_field_info_t soc_XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER_BCM88680_A0r_fields[] = { 5899 { COUNTf, 32, 0, SOCF_LE } 5900 }; 5901 5902 #endif 5903 #if defined(BCM_88675_A0) 5904 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODEr_fields[] = { 5905 { MODE_BITf, 1, 0, 0 } 5906 }; 5907 5908 #endif 5909 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 5910 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 5911 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5912 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 5913 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 5914 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 5915 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5916 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5917 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5918 defined(BCM_56980_B0) 5919 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODE_BCM53400_A0r_fields[] = { 5920 { MODE_BITf, 1, 0, 0 } 5921 }; 5922 5923 #endif 5924 #if defined(BCM_88270_A0) 5925 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODE_BCM88270_A0r_fields[] = { 5926 { MODE_BITf, 1, 0, 0 } 5927 }; 5928 5929 #endif 5930 #if defined(BCM_88375_A0) 5931 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODE_BCM88375_A0r_fields[] = { 5932 { MODE_BITf, 1, 0, 0 } 5933 }; 5934 5935 #endif 5936 #if defined(BCM_88375_B0) 5937 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODE_BCM88375_B0r_fields[] = { 5938 { MODE_BITf, 1, 0, 0 } 5939 }; 5940 5941 #endif 5942 #if defined(BCM_88470_A0) 5943 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODE_BCM88470_A0r_fields[] = { 5944 { MODE_BITf, 1, 0, 0 } 5945 }; 5946 5947 #endif 5948 #if defined(BCM_88470_B0) 5949 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODE_BCM88470_B0r_fields[] = { 5950 { MODE_BITf, 1, 0, 0 } 5951 }; 5952 5953 #endif 5954 #if defined(BCM_88675_B0) 5955 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODE_BCM88675_B0r_fields[] = { 5956 { MODE_BITf, 1, 0, 0 } 5957 }; 5958 5959 #endif 5960 #if defined(BCM_88680_A0) 5961 soc_field_info_t soc_XLPORT_EEE_COUNTER_MODE_BCM88680_A0r_fields[] = { 5962 { MODE_BITf, 1, 0, 0 } 5963 }; 5964 5965 #endif 5966 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 5967 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 5968 defined(BCM_88732_A0) 5969 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSEr_fields[] = { 5970 { CNT_VALUEf, 8, 0, SOCF_LE } 5971 }; 5972 5973 #endif 5974 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 5975 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 5976 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5977 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 5978 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 5979 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 5980 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5981 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5982 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5983 defined(BCM_56980_B0) 5984 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM53400_A0r_fields[] = { 5985 { CNT_VALUEf, 8, 0, SOCF_LE } 5986 }; 5987 5988 #endif 5989 #if defined(BCM_88270_A0) 5990 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88270_A0r_fields[] = { 5991 { CNT_VALUEf, 8, 0, SOCF_LE } 5992 }; 5993 5994 #endif 5995 #if defined(BCM_88375_A0) 5996 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88375_A0r_fields[] = { 5997 { CNT_VALUEf, 8, 0, SOCF_LE } 5998 }; 5999 6000 #endif 6001 #if defined(BCM_88375_B0) 6002 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88375_B0r_fields[] = { 6003 { CNT_VALUEf, 8, 0, SOCF_LE } 6004 }; 6005 6006 #endif 6007 #if defined(BCM_88470_A0) 6008 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88470_A0r_fields[] = { 6009 { CNT_VALUEf, 8, 0, SOCF_LE } 6010 }; 6011 6012 #endif 6013 #if defined(BCM_88470_B0) 6014 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88470_B0r_fields[] = { 6015 { CNT_VALUEf, 8, 0, SOCF_LE } 6016 }; 6017 6018 #endif 6019 #if defined(BCM_88675_A0) 6020 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88675_A0r_fields[] = { 6021 { CNT_VALUEf, 8, 0, SOCF_LE } 6022 }; 6023 6024 #endif 6025 #if defined(BCM_88675_B0) 6026 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88675_B0r_fields[] = { 6027 { CNT_VALUEf, 8, 0, SOCF_LE } 6028 }; 6029 6030 #endif 6031 #if defined(BCM_88680_A0) 6032 soc_field_info_t soc_XLPORT_EEE_DURATION_TIMER_PULSE_BCM88680_A0r_fields[] = { 6033 { CNT_VALUEf, 8, 0, SOCF_LE } 6034 }; 6035 6036 #endif 6037 #if defined(BCM_88675_A0) 6038 soc_field_info_t soc_XLPORT_ENABLE_REGr_fields[] = { 6039 { PORT0f, 1, 0, 0 }, 6040 { PORT1f, 1, 1, 0 }, 6041 { PORT2f, 1, 2, 0 }, 6042 { PORT3f, 1, 3, 0 } 6043 }; 6044 6045 #endif 6046 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 6047 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 6048 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 6049 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 6050 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 6051 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 6052 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 6053 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 6054 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 6055 defined(BCM_56980_B0) 6056 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM53400_A0r_fields[] = { 6057 { PORT0f, 1, 0, 0 }, 6058 { PORT1f, 1, 1, 0 }, 6059 { PORT2f, 1, 2, 0 }, 6060 { PORT3f, 1, 3, 0 } 6061 }; 6062 6063 #endif 6064 #if defined(BCM_56150_A0) || defined(BCM_56450_A0) || \ 6065 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 6066 defined(BCM_56850_A0) || defined(BCM_56860_A0) 6067 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM56850_A0r_fields[] = { 6068 { PORT0f, 1, 0, 0 }, 6069 { PORT1f, 1, 1, 0 }, 6070 { PORT2f, 1, 2, 0 }, 6071 { PORT3f, 1, 3, 0 } 6072 }; 6073 6074 #endif 6075 #if defined(BCM_88270_A0) 6076 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM88270_A0r_fields[] = { 6077 { PORT0f, 1, 0, 0 }, 6078 { PORT1f, 1, 1, 0 }, 6079 { PORT2f, 1, 2, 0 }, 6080 { PORT3f, 1, 3, 0 } 6081 }; 6082 6083 #endif 6084 #if defined(BCM_88375_A0) 6085 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM88375_A0r_fields[] = { 6086 { PORT0f, 1, 0, 0 }, 6087 { PORT1f, 1, 1, 0 }, 6088 { PORT2f, 1, 2, 0 }, 6089 { PORT3f, 1, 3, 0 } 6090 }; 6091 6092 #endif 6093 #if defined(BCM_88375_B0) 6094 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM88375_B0r_fields[] = { 6095 { PORT0f, 1, 0, 0 }, 6096 { PORT1f, 1, 1, 0 }, 6097 { PORT2f, 1, 2, 0 }, 6098 { PORT3f, 1, 3, 0 } 6099 }; 6100 6101 #endif 6102 #if defined(BCM_88470_A0) 6103 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM88470_A0r_fields[] = { 6104 { PORT0f, 1, 0, 0 }, 6105 { PORT1f, 1, 1, 0 }, 6106 { PORT2f, 1, 2, 0 }, 6107 { PORT3f, 1, 3, 0 } 6108 }; 6109 6110 #endif 6111 #if defined(BCM_88470_B0) 6112 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM88470_B0r_fields[] = { 6113 { PORT0f, 1, 0, 0 }, 6114 { PORT1f, 1, 1, 0 }, 6115 { PORT2f, 1, 2, 0 }, 6116 { PORT3f, 1, 3, 0 } 6117 }; 6118 6119 #endif 6120 #if defined(BCM_88675_B0) 6121 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM88675_B0r_fields[] = { 6122 { PORT0f, 1, 0, 0 }, 6123 { PORT1f, 1, 1, 0 }, 6124 { PORT2f, 1, 2, 0 }, 6125 { PORT3f, 1, 3, 0 } 6126 }; 6127 6128 #endif 6129 #if defined(BCM_88680_A0) 6130 soc_field_info_t soc_XLPORT_ENABLE_REG_BCM88680_A0r_fields[] = { 6131 { PORT0f, 1, 0, 0 }, 6132 { PORT1f, 1, 1, 0 }, 6133 { PORT2f, 1, 2, 0 }, 6134 { PORT3f, 1, 3, 0 } 6135 }; 6136 6137 #endif 6138 #if defined(BCM_88675_A0) 6139 soc_field_info_t soc_XLPORT_FAULT_LINK_STATUSr_fields[] = { 6140 { LOCAL_FAULTf, 1, 1, 0 }, 6141 { REMOTE_FAULTf, 1, 0, 0 } 6142 }; 6143 6144 #endif 6145 #if defined(BCM_88270_A0) 6146 soc_field_info_t soc_XLPORT_FAULT_LINK_STATUS_BCM88270_A0r_fields[] = { 6147 { LOCAL_FAULTf, 1, 1, 0 }, 6148 { REMOTE_FAULTf, 1, 0, 0 } 6149 }; 6150 6151 #endif 6152 #if defined(BCM_88375_A0) 6153 soc_field_info_t soc_XLPORT_FAULT_LINK_STATUS_BCM88375_A0r_fields[] = { 6154 { LOCAL_FAULTf, 1, 1, 0 }, 6155 { REMOTE_FAULTf, 1, 0, 0 } 6156 }; 6157 6158 #endif 6159 #if defined(BCM_88375_B0) 6160 soc_field_info_t soc_XLPORT_FAULT_LINK_STATUS_BCM88375_B0r_fields[] = { 6161 { LOCAL_FAULTf, 1, 1, 0 }, 6162 { REMOTE_FAULTf, 1, 0, 0 } 6163 }; 6164 6165 #endif 6166 #if defined(BCM_88470_A0) 6167 soc_field_info_t soc_XLPORT_FAULT_LINK_STATUS_BCM88470_A0r_fields[] = { 6168 { LOCAL_FAULTf, 1, 1, 0 }, 6169 { REMOTE_FAULTf, 1, 0, 0 } 6170 }; 6171 6172 #endif 6173 #if defined(BCM_88470_B0) 6174 soc_field_info_t soc_XLPORT_FAULT_LINK_STATUS_BCM88470_B0r_fields[] = { 6175 { LOCAL_FAULTf, 1, 1, 0 }, 6176 { REMOTE_FAULTf, 1, 0, 0 } 6177 }; 6178 6179 #endif 6180 #if defined(BCM_88675_B0) 6181 soc_field_info_t soc_XLPORT_FAULT_LINK_STATUS_BCM88675_B0r_fields[] = { 6182 { LOCAL_FAULTf, 1, 1, 0 }, 6183 { REMOTE_FAULTf, 1, 0, 0 } 6184 }; 6185 6186 #endif 6187 #if defined(BCM_88680_A0) 6188 soc_field_info_t soc_XLPORT_FAULT_LINK_STATUS_BCM88680_A0r_fields[] = { 6189 { LOCAL_FAULTf, 1, 1, 0 }, 6190 { REMOTE_FAULTf, 1, 0, 0 } 6191 }; 6192 6193 #endif 6194 #if defined(BCM_88675_A0) 6195 soc_field_info_t soc_XLPORT_FLOW_CONTROL_CONFIGr_fields[] = { 6196 { MERGE_MODE_ENf, 1, 1, 0 }, 6197 { PARALLEL_FC_ENf, 1, 0, 0 } 6198 }; 6199 6200 #endif 6201 #if defined(BCM_88270_A0) 6202 soc_field_info_t soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88270_A0r_fields[] = { 6203 { MERGE_MODE_ENf, 1, 1, 0 }, 6204 { PARALLEL_FC_ENf, 1, 0, 0 } 6205 }; 6206 6207 #endif 6208 #if defined(BCM_88375_A0) 6209 soc_field_info_t soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88375_A0r_fields[] = { 6210 { MERGE_MODE_ENf, 1, 1, 0 }, 6211 { PARALLEL_FC_ENf, 1, 0, 0 } 6212 }; 6213 6214 #endif 6215 #if defined(BCM_88375_B0) 6216 soc_field_info_t soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88375_B0r_fields[] = { 6217 { MERGE_MODE_ENf, 1, 1, 0 }, 6218 { PARALLEL_FC_ENf, 1, 0, 0 } 6219 }; 6220 6221 #endif 6222 #if defined(BCM_88470_A0) 6223 soc_field_info_t soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88470_A0r_fields[] = { 6224 { MERGE_MODE_ENf, 1, 1, 0 }, 6225 { PARALLEL_FC_ENf, 1, 0, 0 } 6226 }; 6227 6228 #endif 6229 #if defined(BCM_88470_B0) 6230 soc_field_info_t soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88470_B0r_fields[] = { 6231 { MERGE_MODE_ENf, 1, 1, 0 }, 6232 { PARALLEL_FC_ENf, 1, 0, 0 } 6233 }; 6234 6235 #endif 6236 #if defined(BCM_88675_B0) 6237 soc_field_info_t soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88675_B0r_fields[] = { 6238 { MERGE_MODE_ENf, 1, 1, 0 }, 6239 { PARALLEL_FC_ENf, 1, 0, 0 } 6240 }; 6241 6242 #endif 6243 #if defined(BCM_88680_A0) 6244 soc_field_info_t soc_XLPORT_FLOW_CONTROL_CONFIG_BCM88680_A0r_fields[] = { 6245 { MERGE_MODE_ENf, 1, 1, 0 }, 6246 { PARALLEL_FC_ENf, 1, 0, 0 } 6247 }; 6248 6249 #endif 6250 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 6251 defined(BCM_88732_A0) 6252 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERRORr_fields[] = { 6253 { MIB_RSC_MEM0f, 1, 5, SOCF_RES }, 6254 { MIB_RSC_MEM1f, 1, 6, SOCF_RES }, 6255 { MIB_RSC_MEM2f, 1, 7, SOCF_RES }, 6256 { MIB_RSC_MEM3f, 1, 8, SOCF_RES }, 6257 { MIB_RSC_MEM4f, 1, 9, SOCF_RES }, 6258 { MIB_TSC_MEM0f, 1, 1, SOCF_RES }, 6259 { MIB_TSC_MEM1f, 1, 2, SOCF_RES }, 6260 { MIB_TSC_MEM2f, 1, 3, SOCF_RES }, 6261 { MIB_TSC_MEM3f, 1, 4, SOCF_RES }, 6262 { TXFIFO_MEMf, 1, 0, SOCF_RES } 6263 }; 6264 6265 #endif 6266 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 6267 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 6268 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 6269 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 6270 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 6271 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 6272 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 6273 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 6274 defined(BCM_56980_B0) 6275 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53400_A0r_fields[] = { 6276 { MIB_RSC0_MEMf, 1, 2, SOCF_RES }, 6277 { MIB_RSC1_MEMf, 1, 3, SOCF_RES }, 6278 { MIB_TSC0_MEMf, 1, 0, SOCF_RES }, 6279 { MIB_TSC1_MEMf, 1, 1, SOCF_RES } 6280 }; 6281 6282 #endif 6283 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 6284 defined(BCM_56670_A0) || defined(BCM_56670_B0) 6285 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM53570_A0r_fields[] = { 6286 { MIB_RSC0_MEMf, 1, 2, SOCF_RES }, 6287 { MIB_RSC1_MEMf, 1, 3, SOCF_RES }, 6288 { MIB_TSC0_MEMf, 1, 0, SOCF_RES }, 6289 { MIB_TSC1_MEMf, 1, 1, SOCF_RES }, 6290 { P_MIB_RSC0_MEMf, 1, 10, SOCF_RES }, 6291 { P_MIB_RSC1_MEMf, 1, 11, SOCF_RES }, 6292 { P_MIB_TSC0_MEMf, 1, 8, SOCF_RES }, 6293 { P_MIB_TSC1_MEMf, 1, 9, SOCF_RES }, 6294 { RESERVED_7_4f, 4, 4, SOCF_LE|SOCF_RO|SOCF_RES } 6295 }; 6296 6297 #endif 6298 #if defined(BCM_88270_A0) 6299 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88270_A0r_fields[] = { 6300 { MIB_RSC0_MEMf, 1, 2, 0 }, 6301 { MIB_RSC1_MEMf, 1, 3, 0 }, 6302 { MIB_TSC0_MEMf, 1, 0, 0 }, 6303 { MIB_TSC1_MEMf, 1, 1, 0 } 6304 }; 6305 6306 #endif 6307 #if defined(BCM_88375_A0) 6308 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88375_A0r_fields[] = { 6309 { MIB_RSC0_MEMf, 1, 2, 0 }, 6310 { MIB_RSC1_MEMf, 1, 3, 0 }, 6311 { MIB_TSC0_MEMf, 1, 0, 0 }, 6312 { MIB_TSC1_MEMf, 1, 1, 0 } 6313 }; 6314 6315 #endif 6316 #if defined(BCM_88375_B0) 6317 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88375_B0r_fields[] = { 6318 { MIB_RSC0_MEMf, 1, 2, 0 }, 6319 { MIB_RSC1_MEMf, 1, 3, 0 }, 6320 { MIB_TSC0_MEMf, 1, 0, 0 }, 6321 { MIB_TSC1_MEMf, 1, 1, 0 } 6322 }; 6323 6324 #endif 6325 #if defined(BCM_88470_A0) 6326 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88470_A0r_fields[] = { 6327 { MIB_RSC0_MEMf, 1, 2, 0 }, 6328 { MIB_RSC1_MEMf, 1, 3, 0 }, 6329 { MIB_TSC0_MEMf, 1, 0, 0 }, 6330 { MIB_TSC1_MEMf, 1, 1, 0 } 6331 }; 6332 6333 #endif 6334 #if defined(BCM_88470_B0) 6335 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88470_B0r_fields[] = { 6336 { MIB_RSC0_MEMf, 1, 2, 0 }, 6337 { MIB_RSC1_MEMf, 1, 3, 0 }, 6338 { MIB_TSC0_MEMf, 1, 0, 0 }, 6339 { MIB_TSC1_MEMf, 1, 1, 0 } 6340 }; 6341 6342 #endif 6343 #if defined(BCM_88675_A0) 6344 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88675_A0r_fields[] = { 6345 { MIB_RSC0_MEMf, 1, 2, 0 }, 6346 { MIB_RSC1_MEMf, 1, 3, 0 }, 6347 { MIB_TSC0_MEMf, 1, 0, 0 }, 6348 { MIB_TSC1_MEMf, 1, 1, 0 } 6349 }; 6350 6351 #endif 6352 #if defined(BCM_88675_B0) 6353 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88675_B0r_fields[] = { 6354 { MIB_RSC0_MEMf, 1, 2, 0 }, 6355 { MIB_RSC1_MEMf, 1, 3, 0 }, 6356 { MIB_TSC0_MEMf, 1, 0, 0 }, 6357 { MIB_TSC1_MEMf, 1, 1, 0 } 6358 }; 6359 6360 #endif 6361 #if defined(BCM_88680_A0) 6362 soc_field_info_t soc_XLPORT_FORCE_DOUBLE_BIT_ERROR_BCM88680_A0r_fields[] = { 6363 { MIB_RSC0_MEMf, 1, 2, 0 }, 6364 { MIB_RSC1_MEMf, 1, 3, 0 }, 6365 { MIB_TSC0_MEMf, 1, 0, 0 }, 6366 { MIB_TSC1_MEMf, 1, 1, 0 } 6367 }; 6368 6369 #endif 6370 #if defined(BCM_88675_A0) 6371 soc_field_info_t soc_XLPORT_FORCE_SINGLE_BIT_ERRORr_fields[] = { 6372 { MIB_RSC0_MEMf, 1, 2, 0 }, 6373 { MIB_RSC1_MEMf, 1, 3, 0 }, 6374 { MIB_TSC0_MEMf, 1, 0, 0 }, 6375 { MIB_TSC1_MEMf, 1, 1, 0 } 6376 }; 6377 6378 #endif 6379 #if defined(BCM_88270_A0) 6380 soc_field_info_t soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88270_A0r_fields[] = { 6381 { MIB_RSC0_MEMf, 1, 2, 0 }, 6382 { MIB_RSC1_MEMf, 1, 3, 0 }, 6383 { MIB_TSC0_MEMf, 1, 0, 0 }, 6384 { MIB_TSC1_MEMf, 1, 1, 0 } 6385 }; 6386 6387 #endif 6388 #if defined(BCM_88375_A0) 6389 soc_field_info_t soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88375_A0r_fields[] = { 6390 { MIB_RSC0_MEMf, 1, 2, 0 }, 6391 { MIB_RSC1_MEMf, 1, 3, 0 }, 6392 { MIB_TSC0_MEMf, 1, 0, 0 }, 6393 { MIB_TSC1_MEMf, 1, 1, 0 } 6394 }; 6395 6396 #endif 6397 #if defined(BCM_88375_B0) 6398 soc_field_info_t soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88375_B0r_fields[] = { 6399 { MIB_RSC0_MEMf, 1, 2, 0 }, 6400 { MIB_RSC1_MEMf, 1, 3, 0 }, 6401 { MIB_TSC0_MEMf, 1, 0, 0 }, 6402 { MIB_TSC1_MEMf, 1, 1, 0 } 6403 }; 6404 6405 #endif 6406 #if defined(BCM_88470_A0) 6407 soc_field_info_t soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88470_A0r_fields[] = { 6408 { MIB_RSC0_MEMf, 1, 2, 0 }, 6409 { MIB_RSC1_MEMf, 1, 3, 0 }, 6410 { MIB_TSC0_MEMf, 1, 0, 0 }, 6411 { MIB_TSC1_MEMf, 1, 1, 0 } 6412 }; 6413 6414 #endif 6415 #if defined(BCM_88470_B0) 6416 soc_field_info_t soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88470_B0r_fields[] = { 6417 { MIB_RSC0_MEMf, 1, 2, 0 }, 6418 { MIB_RSC1_MEMf, 1, 3, 0 }, 6419 { MIB_TSC0_MEMf, 1, 0, 0 }, 6420 { MIB_TSC1_MEMf, 1, 1, 0 } 6421 }; 6422 6423 #endif 6424 #if defined(BCM_88675_B0) 6425 soc_field_info_t soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88675_B0r_fields[] = { 6426 { MIB_RSC0_MEMf, 1, 2, 0 }, 6427 { MIB_RSC1_MEMf, 1, 3, 0 }, 6428 { MIB_TSC0_MEMf, 1, 0, 0 }, 6429 { MIB_TSC1_MEMf, 1, 1, 0 } 6430 }; 6431 6432 #endif 6433 #if defined(BCM_88680_A0) 6434 soc_field_info_t soc_XLPORT_FORCE_SINGLE_BIT_ERROR_BCM88680_A0r_fields[] = { 6435 { MIB_RSC0_MEMf, 1, 2, 0 }, 6436 { MIB_RSC1_MEMf, 1, 3, 0 }, 6437 { MIB_TSC0_MEMf, 1, 0, 0 }, 6438 { MIB_TSC1_MEMf, 1, 1, 0 } 6439 }; 6440 6441 #endif 6442 #if defined(BCM_56860_A0) 6443 soc_field_info_t soc_XLPORT_GENERAL_SPARE0r_fields[] = { 6444 { RSVDf, 32, 0, SOCF_LE|SOCF_RES } 6445 }; 6446 6447 #endif 6448 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 6449 defined(BCM_88732_A0) 6450 soc_field_info_t soc_XLPORT_INTR_ENABLEr_fields[] = { 6451 { MIB_RSC_MEM0_ERRf, 1, 5, SOCF_RO }, 6452 { MIB_RSC_MEM1_ERRf, 1, 6, SOCF_RO }, 6453 { MIB_RSC_MEM2_ERRf, 1, 7, SOCF_RO }, 6454 { MIB_RSC_MEM3_ERRf, 1, 8, SOCF_RO }, 6455 { MIB_RSC_MEM4_ERRf, 1, 9, SOCF_RO }, 6456 { MIB_TSC_MEM0_ERRf, 1, 1, SOCF_RO }, 6457 { MIB_TSC_MEM1_ERRf, 1, 2, SOCF_RO }, 6458 { MIB_TSC_MEM2_ERRf, 1, 3, SOCF_RO }, 6459 { MIB_TSC_MEM3_ERRf, 1, 4, SOCF_RO }, 6460 { TXFIFO_MEM_ERRf, 1, 0, SOCF_RO } 6461 }; 6462 6463 #endif 6464 #if defined(BCM_2801PM_A0) 6465 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM2801PM_A0r_fields[] = { 6466 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6467 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6468 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6469 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6470 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE }, 6471 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6472 }; 6473 6474 #endif 6475 #if defined(BCM_53400_A0) || defined(BCM_56260_A0) 6476 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM53400_A0r_fields[] = { 6477 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_W1TC }, 6478 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_W1TC }, 6479 { MIB_RX_MEM_ERRf, 1, 1, SOCF_W1TC }, 6480 { MIB_TX_MEM_ERRf, 1, 0, SOCF_W1TC }, 6481 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE|SOCF_W1TC }, 6482 { TSC_ERRf, 1, 4, SOCF_RO } 6483 }; 6484 6485 #endif 6486 #if defined(BCM_56150_A0) 6487 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM56150_A0r_fields[] = { 6488 { BOD_XLP0_ERRf, 1, 4, SOCF_RO }, 6489 { MIB_RSC0_MEM_ERRf, 1, 2, SOCF_RO }, 6490 { MIB_RSC1_MEM_ERRf, 1, 3, SOCF_RO }, 6491 { MIB_TSC0_MEM_ERRf, 1, 0, SOCF_RO }, 6492 { MIB_TSC1_MEM_ERRf, 1, 1, SOCF_RO }, 6493 { TXFIFO0_ERRf, 1, 5, SOCF_RO }, 6494 { TXFIFO1_ERRf, 1, 6, SOCF_RO }, 6495 { TXFIFO2_ERRf, 1, 7, SOCF_RO }, 6496 { TXFIFO3_ERRf, 1, 8, SOCF_RO } 6497 }; 6498 6499 #endif 6500 #if defined(BCM_56160_A0) || defined(BCM_56270_A0) 6501 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM56160_A0r_fields[] = { 6502 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6503 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6504 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6505 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6506 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE|SOCF_SC }, 6507 { TSC_ERRf, 1, 4, 0 } 6508 }; 6509 6510 #endif 6511 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 6512 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM56850_A0r_fields[] = { 6513 { RESERVED7_1f, 7, 1, SOCF_LE|SOCF_RO|SOCF_RES }, 6514 { TXFIFO0_MEM_ERRf, 1, 0, SOCF_RO } 6515 }; 6516 6517 #endif 6518 #if defined(BCM_56260_B0) || defined(BCM_56560_A0) || \ 6519 defined(BCM_56560_B0) || defined(BCM_56960_A0) || \ 6520 defined(BCM_56965_A0) 6521 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM56960_A0r_fields[] = { 6522 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6523 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6524 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6525 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6526 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE }, 6527 { TSC_ERRf, 1, 4, 0 } 6528 }; 6529 6530 #endif 6531 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 6532 defined(BCM_56370_A0) || defined(BCM_56670_A0) || \ 6533 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 6534 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 6535 defined(BCM_56980_A0) || defined(BCM_56980_B0) 6536 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM56970_A0r_fields[] = { 6537 { LINK_DOWNf, 4, 13, SOCF_LE|SOCF_RO }, 6538 { MAC_ERRf, 4, 9, SOCF_LE|SOCF_RO }, 6539 { MIB_RX_MEM_ERRf, 1, 1, SOCF_W1TC }, 6540 { MIB_TX_MEM_ERRf, 1, 0, SOCF_W1TC }, 6541 { RESERVED_2f, 1, 2, SOCF_RO|SOCF_RES }, 6542 { RESERVED_3f, 1, 3, SOCF_RO|SOCF_RES }, 6543 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE|SOCF_W1TC }, 6544 { TSC_ERRf, 1, 4, SOCF_RO } 6545 }; 6546 6547 #endif 6548 #if defined(BCM_88270_A0) 6549 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM88270_A0r_fields[] = { 6550 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6551 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6552 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6553 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6554 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE }, 6555 { TSC_ERRf, 1, 4, 0 } 6556 }; 6557 6558 #endif 6559 #if defined(BCM_88375_A0) 6560 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM88375_A0r_fields[] = { 6561 { FIELD_5_8f, 4, 5, SOCF_LE }, 6562 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6563 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6564 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6565 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6566 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6567 }; 6568 6569 #endif 6570 #if defined(BCM_88375_B0) 6571 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM88375_B0r_fields[] = { 6572 { FIELD_5_8f, 4, 5, SOCF_LE }, 6573 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6574 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6575 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6576 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6577 { TSC_ERRf, 1, 4, 0 } 6578 }; 6579 6580 #endif 6581 #if defined(BCM_88470_A0) 6582 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM88470_A0r_fields[] = { 6583 { FIELD_5_8f, 4, 5, SOCF_LE }, 6584 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6585 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6586 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6587 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6588 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6589 }; 6590 6591 #endif 6592 #if defined(BCM_88470_B0) 6593 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM88470_B0r_fields[] = { 6594 { FIELD_5_8f, 4, 5, SOCF_LE }, 6595 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6596 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6597 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6598 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6599 { TSC_ERRf, 1, 4, 0 } 6600 }; 6601 6602 #endif 6603 #if defined(BCM_88675_A0) 6604 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM88675_A0r_fields[] = { 6605 { FIELD_5_8f, 4, 5, SOCF_LE }, 6606 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6607 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6608 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6609 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6610 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6611 }; 6612 6613 #endif 6614 #if defined(BCM_88675_B0) 6615 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM88675_B0r_fields[] = { 6616 { FIELD_5_8f, 4, 5, SOCF_LE }, 6617 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6618 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6619 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6620 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6621 { TSC_ERRf, 1, 4, 0 } 6622 }; 6623 6624 #endif 6625 #if defined(BCM_88680_A0) 6626 soc_field_info_t soc_XLPORT_INTR_ENABLE_BCM88680_A0r_fields[] = { 6627 { FIELD_5_8f, 4, 5, SOCF_LE }, 6628 { MAC_RX_CDC_MEM_ERRf, 1, 3, 0 }, 6629 { MAC_TX_CDC_MEM_ERRf, 1, 2, 0 }, 6630 { MIB_RX_MEM_ERRf, 1, 1, 0 }, 6631 { MIB_TX_MEM_ERRf, 1, 0, 0 }, 6632 { TSC_ERRf, 1, 4, 0 } 6633 }; 6634 6635 #endif 6636 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 6637 defined(BCM_88732_A0) 6638 soc_field_info_t soc_XLPORT_INTR_STATUSr_fields[] = { 6639 { MIB_RSC_MEM0_ERRf, 1, 5, SOCF_RO }, 6640 { MIB_RSC_MEM1_ERRf, 1, 6, SOCF_RO }, 6641 { MIB_RSC_MEM2_ERRf, 1, 7, SOCF_RO }, 6642 { MIB_RSC_MEM3_ERRf, 1, 8, SOCF_RO }, 6643 { MIB_RSC_MEM4_ERRf, 1, 9, SOCF_RO }, 6644 { MIB_TSC_MEM0_ERRf, 1, 1, SOCF_RO }, 6645 { MIB_TSC_MEM1_ERRf, 1, 2, SOCF_RO }, 6646 { MIB_TSC_MEM2_ERRf, 1, 3, SOCF_RO }, 6647 { MIB_TSC_MEM3_ERRf, 1, 4, SOCF_RO }, 6648 { TXFIFO_MEM_ERRf, 1, 0, SOCF_RO } 6649 }; 6650 6651 #endif 6652 #if defined(BCM_2801PM_A0) 6653 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM2801PM_A0r_fields[] = { 6654 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6655 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6656 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6657 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6658 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE|SOCF_RO }, 6659 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6660 }; 6661 6662 #endif 6663 #if defined(BCM_53400_A0) || defined(BCM_56260_A0) || \ 6664 defined(BCM_56260_B0) || defined(BCM_56560_A0) || \ 6665 defined(BCM_56560_B0) || defined(BCM_56960_A0) || \ 6666 defined(BCM_56965_A0) 6667 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM53400_A0r_fields[] = { 6668 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO|SOCF_W1TC }, 6669 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO|SOCF_W1TC }, 6670 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO|SOCF_W1TC }, 6671 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO|SOCF_W1TC }, 6672 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE|SOCF_RO|SOCF_W1TC }, 6673 { TSC_ERRf, 1, 4, SOCF_RO } 6674 }; 6675 6676 #endif 6677 #if defined(BCM_56150_A0) 6678 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM56150_A0r_fields[] = { 6679 { BOD_XLP0_ERRf, 1, 4, SOCF_RO }, 6680 { MIB_RSC0_MEM_ERRf, 1, 2, SOCF_RO }, 6681 { MIB_RSC1_MEM_ERRf, 1, 3, SOCF_RO }, 6682 { MIB_TSC0_MEM_ERRf, 1, 0, SOCF_RO }, 6683 { MIB_TSC1_MEM_ERRf, 1, 1, SOCF_RO }, 6684 { TXFIFO0_ERRf, 1, 5, SOCF_RO }, 6685 { TXFIFO1_ERRf, 1, 6, SOCF_RO }, 6686 { TXFIFO2_ERRf, 1, 7, SOCF_RO }, 6687 { TXFIFO3_ERRf, 1, 8, SOCF_RO } 6688 }; 6689 6690 #endif 6691 #if defined(BCM_56160_A0) || defined(BCM_56270_A0) 6692 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM56160_A0r_fields[] = { 6693 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO|SOCF_W1TC }, 6694 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO|SOCF_W1TC }, 6695 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO|SOCF_W1TC }, 6696 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO|SOCF_W1TC }, 6697 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE|SOCF_RO|SOCF_SC|SOCF_W1TC }, 6698 { TSC_ERRf, 1, 4, SOCF_RO } 6699 }; 6700 6701 #endif 6702 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 6703 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM56850_A0r_fields[] = { 6704 { RESERVED7_1f, 7, 1, SOCF_LE|SOCF_RO|SOCF_RES }, 6705 { TXFIFO0_MEM_ERRf, 1, 0, SOCF_RO } 6706 }; 6707 6708 #endif 6709 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 6710 defined(BCM_56370_A0) || defined(BCM_56670_A0) || \ 6711 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 6712 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 6713 defined(BCM_56980_A0) || defined(BCM_56980_B0) 6714 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM56970_A0r_fields[] = { 6715 { LINK_DOWNf, 4, 13, SOCF_LE|SOCF_RO }, 6716 { MAC_ERRf, 4, 9, SOCF_LE|SOCF_RO }, 6717 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO|SOCF_W1TC }, 6718 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO|SOCF_W1TC }, 6719 { RESERVED_2f, 1, 2, SOCF_RO|SOCF_RES }, 6720 { RESERVED_3f, 1, 3, SOCF_RO|SOCF_RES }, 6721 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE|SOCF_RO|SOCF_W1TC }, 6722 { TSC_ERRf, 1, 4, SOCF_RO } 6723 }; 6724 6725 #endif 6726 #if defined(BCM_88270_A0) 6727 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM88270_A0r_fields[] = { 6728 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6729 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6730 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6731 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6732 { RX_FLOWCONTROL_REQ_FULLf, 4, 5, SOCF_LE|SOCF_RO }, 6733 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6734 }; 6735 6736 #endif 6737 #if defined(BCM_88375_A0) 6738 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM88375_A0r_fields[] = { 6739 { FIELD_5_8f, 4, 5, SOCF_LE|SOCF_RO }, 6740 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6741 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6742 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6743 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6744 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6745 }; 6746 6747 #endif 6748 #if defined(BCM_88375_B0) 6749 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM88375_B0r_fields[] = { 6750 { FIELD_5_8f, 4, 5, SOCF_LE|SOCF_RO }, 6751 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6752 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6753 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6754 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6755 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6756 }; 6757 6758 #endif 6759 #if defined(BCM_88470_A0) 6760 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM88470_A0r_fields[] = { 6761 { FIELD_5_8f, 4, 5, SOCF_LE|SOCF_RO }, 6762 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6763 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6764 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6765 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6766 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6767 }; 6768 6769 #endif 6770 #if defined(BCM_88470_B0) 6771 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM88470_B0r_fields[] = { 6772 { FIELD_5_8f, 4, 5, SOCF_LE|SOCF_RO }, 6773 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6774 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6775 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6776 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6777 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6778 }; 6779 6780 #endif 6781 #if defined(BCM_88675_A0) 6782 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM88675_A0r_fields[] = { 6783 { FIELD_5_8f, 4, 5, SOCF_LE|SOCF_RO }, 6784 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6785 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6786 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6787 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6788 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6789 }; 6790 6791 #endif 6792 #if defined(BCM_88675_B0) 6793 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM88675_B0r_fields[] = { 6794 { FIELD_5_8f, 4, 5, SOCF_LE|SOCF_RO }, 6795 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6796 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6797 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6798 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6799 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6800 }; 6801 6802 #endif 6803 #if defined(BCM_88680_A0) 6804 soc_field_info_t soc_XLPORT_INTR_STATUS_BCM88680_A0r_fields[] = { 6805 { FIELD_5_8f, 4, 5, SOCF_LE|SOCF_RO }, 6806 { MAC_RX_CDC_MEM_ERRf, 1, 3, SOCF_RO }, 6807 { MAC_TX_CDC_MEM_ERRf, 1, 2, SOCF_RO }, 6808 { MIB_RX_MEM_ERRf, 1, 1, SOCF_RO }, 6809 { MIB_TX_MEM_ERRf, 1, 0, SOCF_RO }, 6810 { TSC_ERRf, 1, 4, SOCF_RO|SOCF_SIG } 6811 }; 6812 6813 #endif 6814 #if defined(BCM_88675_A0) 6815 soc_field_info_t soc_XLPORT_LAG_FAILOVER_CONFIGr_fields[] = { 6816 { LINK_STATUS_UPf, 1, 0, 0 } 6817 }; 6818 6819 #endif 6820 #if defined(BCM_88270_A0) 6821 soc_field_info_t soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88270_A0r_fields[] = { 6822 { LINK_STATUS_UPf, 1, 0, 0 } 6823 }; 6824 6825 #endif 6826 #if defined(BCM_88375_A0) 6827 soc_field_info_t soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88375_A0r_fields[] = { 6828 { LINK_STATUS_UPf, 1, 0, 0 } 6829 }; 6830 6831 #endif 6832 #if defined(BCM_88375_B0) 6833 soc_field_info_t soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88375_B0r_fields[] = { 6834 { LINK_STATUS_UPf, 1, 0, 0 } 6835 }; 6836 6837 #endif 6838 #if defined(BCM_88470_A0) 6839 soc_field_info_t soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88470_A0r_fields[] = { 6840 { LINK_STATUS_UPf, 1, 0, 0 } 6841 }; 6842 6843 #endif 6844 #if defined(BCM_88470_B0) 6845 soc_field_info_t soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88470_B0r_fields[] = { 6846 { LINK_STATUS_UPf, 1, 0, 0 } 6847 }; 6848 6849 #endif 6850 #if defined(BCM_88675_B0) 6851 soc_field_info_t soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88675_B0r_fields[] = { 6852 { LINK_STATUS_UPf, 1, 0, 0 } 6853 }; 6854 6855 #endif 6856 #if defined(BCM_88680_A0) 6857 soc_field_info_t soc_XLPORT_LAG_FAILOVER_CONFIG_BCM88680_A0r_fields[] = { 6858 { LINK_STATUS_UPf, 1, 0, 0 } 6859 }; 6860 6861 #endif 6862 #if defined(BCM_88470_B0) 6863 soc_field_info_t soc_XLPORT_LED_CHAIN_CONFIGr_fields[] = { 6864 { INTRA_DELAYf, 4, 0, SOCF_LE } 6865 }; 6866 6867 #endif 6868 #if defined(BCM_88270_A0) 6869 soc_field_info_t soc_XLPORT_LED_CHAIN_CONFIG_BCM88270_A0r_fields[] = { 6870 { INTRA_DELAYf, 4, 0, SOCF_LE } 6871 }; 6872 6873 #endif 6874 #if defined(BCM_88375_B0) 6875 soc_field_info_t soc_XLPORT_LED_CHAIN_CONFIG_BCM88375_B0r_fields[] = { 6876 { INTRA_DELAYf, 4, 0, SOCF_LE } 6877 }; 6878 6879 #endif 6880 #if defined(BCM_88675_B0) 6881 soc_field_info_t soc_XLPORT_LED_CHAIN_CONFIG_BCM88675_B0r_fields[] = { 6882 { INTRA_DELAYf, 4, 0, SOCF_LE } 6883 }; 6884 6885 #endif 6886 #if defined(BCM_88680_A0) 6887 soc_field_info_t soc_XLPORT_LED_CHAIN_CONFIG_BCM88680_A0r_fields[] = { 6888 { INTRA_DELAYf, 4, 0, SOCF_LE } 6889 }; 6890 6891 #endif 6892 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 6893 defined(BCM_56840_B0) 6894 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWNr_fields[] = { 6895 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO }, 6896 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO }, 6897 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO }, 6898 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO } 6899 }; 6900 6901 #endif 6902 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 6903 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 6904 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 6905 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 6906 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 6907 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 6908 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 6909 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 6910 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 6911 defined(BCM_56980_B0) 6912 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM53400_A0r_fields[] = { 6913 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO }, 6914 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO }, 6915 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO }, 6916 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO } 6917 }; 6918 6919 #endif 6920 #if defined(BCM_56150_A0) || defined(BCM_56450_A0) || \ 6921 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 6922 defined(BCM_56850_A0) || defined(BCM_56860_A0) 6923 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM56850_A0r_fields[] = { 6924 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO }, 6925 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO }, 6926 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO }, 6927 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO } 6928 }; 6929 6930 #endif 6931 #if defined(BCM_88270_A0) 6932 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM88270_A0r_fields[] = { 6933 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 6934 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO|SOCF_SIG }, 6935 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO|SOCF_SIG }, 6936 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO|SOCF_SIG } 6937 }; 6938 6939 #endif 6940 #if defined(BCM_88375_A0) 6941 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM88375_A0r_fields[] = { 6942 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 6943 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO|SOCF_SIG }, 6944 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO|SOCF_SIG }, 6945 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO|SOCF_SIG } 6946 }; 6947 6948 #endif 6949 #if defined(BCM_88375_B0) 6950 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM88375_B0r_fields[] = { 6951 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 6952 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO|SOCF_SIG }, 6953 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO|SOCF_SIG }, 6954 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO|SOCF_SIG } 6955 }; 6956 6957 #endif 6958 #if defined(BCM_88470_A0) 6959 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM88470_A0r_fields[] = { 6960 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 6961 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO|SOCF_SIG }, 6962 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO|SOCF_SIG }, 6963 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO|SOCF_SIG } 6964 }; 6965 6966 #endif 6967 #if defined(BCM_88470_B0) 6968 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM88470_B0r_fields[] = { 6969 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 6970 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO|SOCF_SIG }, 6971 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO|SOCF_SIG }, 6972 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO|SOCF_SIG } 6973 }; 6974 6975 #endif 6976 #if defined(BCM_88675_A0) 6977 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM88675_A0r_fields[] = { 6978 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 6979 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO|SOCF_SIG }, 6980 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO|SOCF_SIG }, 6981 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO|SOCF_SIG } 6982 }; 6983 6984 #endif 6985 #if defined(BCM_88675_B0) 6986 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM88675_B0r_fields[] = { 6987 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 6988 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO|SOCF_SIG }, 6989 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO|SOCF_SIG }, 6990 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO|SOCF_SIG } 6991 }; 6992 6993 #endif 6994 #if defined(BCM_88680_A0) 6995 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_BCM88680_A0r_fields[] = { 6996 { PORT0_LINKSTATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 6997 { PORT1_LINKSTATUSf, 1, 1, SOCF_RO|SOCF_SIG }, 6998 { PORT2_LINKSTATUSf, 1, 2, SOCF_RO|SOCF_SIG }, 6999 { PORT3_LINKSTATUSf, 1, 3, SOCF_RO|SOCF_SIG } 7000 }; 7001 7002 #endif 7003 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7004 defined(BCM_56840_B0) 7005 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEARr_fields[] = { 7006 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7007 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7008 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7009 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7010 }; 7011 7012 #endif 7013 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 7014 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 7015 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 7016 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 7017 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 7018 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 7019 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 7020 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 7021 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 7022 defined(BCM_56980_B0) 7023 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM53400_A0r_fields[] = { 7024 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7025 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7026 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7027 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7028 }; 7029 7030 #endif 7031 #if defined(BCM_56150_A0) || defined(BCM_56450_A0) || \ 7032 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 7033 defined(BCM_56850_A0) || defined(BCM_56860_A0) 7034 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM56850_A0r_fields[] = { 7035 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7036 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7037 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7038 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7039 }; 7040 7041 #endif 7042 #if defined(BCM_88270_A0) 7043 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88270_A0r_fields[] = { 7044 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7045 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7046 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7047 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7048 }; 7049 7050 #endif 7051 #if defined(BCM_88375_A0) 7052 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88375_A0r_fields[] = { 7053 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7054 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7055 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7056 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7057 }; 7058 7059 #endif 7060 #if defined(BCM_88375_B0) 7061 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88375_B0r_fields[] = { 7062 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7063 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7064 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7065 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7066 }; 7067 7068 #endif 7069 #if defined(BCM_88470_A0) 7070 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88470_A0r_fields[] = { 7071 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7072 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7073 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7074 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7075 }; 7076 7077 #endif 7078 #if defined(BCM_88470_B0) 7079 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88470_B0r_fields[] = { 7080 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7081 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7082 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7083 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7084 }; 7085 7086 #endif 7087 #if defined(BCM_88675_A0) 7088 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88675_A0r_fields[] = { 7089 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7090 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7091 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7092 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7093 }; 7094 7095 #endif 7096 #if defined(BCM_88675_B0) 7097 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88675_B0r_fields[] = { 7098 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7099 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7100 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7101 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7102 }; 7103 7104 #endif 7105 #if defined(BCM_88680_A0) 7106 soc_field_info_t soc_XLPORT_LINKSTATUS_DOWN_CLEAR_BCM88680_A0r_fields[] = { 7107 { PORT0_LINKDOWN_CLEARf, 1, 0, 0 }, 7108 { PORT1_LINKDOWN_CLEARf, 1, 1, 0 }, 7109 { PORT2_LINKDOWN_CLEARf, 1, 2, 0 }, 7110 { PORT3_LINKDOWN_CLEARf, 1, 3, 0 } 7111 }; 7112 7113 #endif 7114 #if defined(BCM_2801PM_A0) 7115 soc_field_info_t soc_XLPORT_MAC_CONTROLr_fields[] = { 7116 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7117 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7118 { XMAC0_RESETf, 1, 0, 0 } 7119 }; 7120 7121 #endif 7122 #if defined(BCM_53400_A0) || defined(BCM_56160_A0) || \ 7123 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 7124 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 7125 defined(BCM_56560_B0) || defined(BCM_56960_A0) || \ 7126 defined(BCM_56965_A0) 7127 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM53400_A0r_fields[] = { 7128 { RX_FLEX_TDM_ENABLEf, 1, 2, SOCF_RES }, 7129 { XMAC0_BYPASS_OSTSf, 1, 1, SOCF_RES }, 7130 { XMAC0_RESETf, 1, 0, SOCF_RES } 7131 }; 7132 7133 #endif 7134 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 7135 defined(BCM_56670_A0) || defined(BCM_56670_B0) 7136 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM53570_A0r_fields[] = { 7137 { RESERVED_4f, 1, 4, SOCF_RES }, 7138 { RX_DUAL_CYCLE_TDM_ENf, 1, 5, SOCF_RES }, 7139 { RX_FLEX_TDM_ENABLEf, 1, 2, SOCF_RES }, 7140 { RX_NON_LINEAR_QUAD_TDM_ENf, 1, 3, SOCF_RES }, 7141 { XLMAC_TS_DISABLEf, 1, 6, SOCF_RES }, 7142 { XMAC0_BYPASS_OSTSf, 1, 1, SOCF_RES }, 7143 { XMAC0_RESETf, 1, 0, SOCF_RES } 7144 }; 7145 7146 #endif 7147 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 7148 defined(BCM_56860_A0) 7149 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM56850_A0r_fields[] = { 7150 { XMAC0_BYPASS_OSTSf, 1, 1, SOCF_RES }, 7151 { XMAC0_RESETf, 1, 0, SOCF_RES } 7152 }; 7153 7154 #endif 7155 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7156 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 7157 defined(BCM_56980_A0) || defined(BCM_56980_B0) 7158 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM56970_A0r_fields[] = { 7159 { RESERVED_4f, 1, 4, SOCF_RES }, 7160 { RX_DUAL_CYCLE_TDM_ENf, 1, 5, SOCF_RES }, 7161 { RX_FLEX_TDM_ENABLEf, 1, 2, SOCF_RES }, 7162 { RX_NON_LINEAR_QUAD_TDM_ENf, 1, 3, SOCF_RES }, 7163 { XMAC0_BYPASS_OSTSf, 1, 1, SOCF_RES }, 7164 { XMAC0_RESETf, 1, 0, SOCF_RES } 7165 }; 7166 7167 #endif 7168 #if defined(BCM_88270_A0) 7169 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM88270_A0r_fields[] = { 7170 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7171 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7172 { XMAC0_RESETf, 1, 0, 0 } 7173 }; 7174 7175 #endif 7176 #if defined(BCM_88375_A0) 7177 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM88375_A0r_fields[] = { 7178 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7179 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7180 { XMAC0_RESETf, 1, 0, 0 } 7181 }; 7182 7183 #endif 7184 #if defined(BCM_88375_B0) 7185 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM88375_B0r_fields[] = { 7186 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7187 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7188 { XMAC0_RESETf, 1, 0, 0 } 7189 }; 7190 7191 #endif 7192 #if defined(BCM_88470_A0) 7193 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM88470_A0r_fields[] = { 7194 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7195 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7196 { XMAC0_RESETf, 1, 0, 0 } 7197 }; 7198 7199 #endif 7200 #if defined(BCM_88470_B0) 7201 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM88470_B0r_fields[] = { 7202 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7203 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7204 { XMAC0_RESETf, 1, 0, 0 } 7205 }; 7206 7207 #endif 7208 #if defined(BCM_88675_A0) 7209 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM88675_A0r_fields[] = { 7210 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7211 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7212 { XMAC0_RESETf, 1, 0, 0 } 7213 }; 7214 7215 #endif 7216 #if defined(BCM_88675_B0) 7217 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM88675_B0r_fields[] = { 7218 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7219 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7220 { XMAC0_RESETf, 1, 0, 0 } 7221 }; 7222 7223 #endif 7224 #if defined(BCM_88680_A0) 7225 soc_field_info_t soc_XLPORT_MAC_CONTROL_BCM88680_A0r_fields[] = { 7226 { RX_FLEX_TDM_ENABLEf, 1, 2, 0 }, 7227 { XMAC0_BYPASS_OSTSf, 1, 1, 0 }, 7228 { XMAC0_RESETf, 1, 0, 0 } 7229 }; 7230 7231 #endif 7232 #if defined(BCM_88675_A0) 7233 soc_field_info_t soc_XLPORT_MAC_RSV_MASKr_fields[] = { 7234 { MASKf, 32, 0, SOCF_LE } 7235 }; 7236 7237 #endif 7238 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 7239 defined(BCM_56670_A0) || defined(BCM_56670_B0) 7240 soc_field_info_t soc_XLPORT_MAC_RSV_MASK_BCM53570_A0r_fields[] = { 7241 { MASKf, 32, 0, SOCF_LE } 7242 }; 7243 7244 #endif 7245 #if defined(BCM_88270_A0) 7246 soc_field_info_t soc_XLPORT_MAC_RSV_MASK_BCM88270_A0r_fields[] = { 7247 { MASKf, 32, 0, SOCF_LE } 7248 }; 7249 7250 #endif 7251 #if defined(BCM_88375_A0) 7252 soc_field_info_t soc_XLPORT_MAC_RSV_MASK_BCM88375_A0r_fields[] = { 7253 { MASKf, 32, 0, SOCF_LE } 7254 }; 7255 7256 #endif 7257 #if defined(BCM_88375_B0) 7258 soc_field_info_t soc_XLPORT_MAC_RSV_MASK_BCM88375_B0r_fields[] = { 7259 { MASKf, 32, 0, SOCF_LE } 7260 }; 7261 7262 #endif 7263 #if defined(BCM_88470_A0) 7264 soc_field_info_t soc_XLPORT_MAC_RSV_MASK_BCM88470_A0r_fields[] = { 7265 { MASKf, 32, 0, SOCF_LE } 7266 }; 7267 7268 #endif 7269 #if defined(BCM_88470_B0) 7270 soc_field_info_t soc_XLPORT_MAC_RSV_MASK_BCM88470_B0r_fields[] = { 7271 { MASKf, 32, 0, SOCF_LE } 7272 }; 7273 7274 #endif 7275 #if defined(BCM_88675_B0) 7276 soc_field_info_t soc_XLPORT_MAC_RSV_MASK_BCM88675_B0r_fields[] = { 7277 { MASKf, 32, 0, SOCF_LE } 7278 }; 7279 7280 #endif 7281 #if defined(BCM_88680_A0) 7282 soc_field_info_t soc_XLPORT_MAC_RSV_MASK_BCM88680_A0r_fields[] = { 7283 { MASKf, 32, 0, SOCF_LE } 7284 }; 7285 7286 #endif 7287 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7288 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7289 defined(BCM_88732_A0) 7290 soc_field_info_t soc_XLPORT_MEMORY_CONTROL0r_fields[] = { 7291 { TXFIFO_MEM0_TMf, 8, 0, SOCF_LE|SOCF_RES }, 7292 { TXFIFO_MEM1_TMf, 8, 8, SOCF_LE|SOCF_RES } 7293 }; 7294 7295 #endif 7296 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7297 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7298 defined(BCM_88732_A0) 7299 soc_field_info_t soc_XLPORT_MEMORY_CONTROL1r_fields[] = { 7300 { MIB_RSC_MEM0_TMf, 8, 0, SOCF_LE }, 7301 { MIB_RSC_MEM1_TMf, 8, 8, SOCF_LE }, 7302 { MIB_RSC_MEM2_TMf, 8, 16, SOCF_LE } 7303 }; 7304 7305 #endif 7306 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7307 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7308 defined(BCM_88732_A0) 7309 soc_field_info_t soc_XLPORT_MEMORY_CONTROL2r_fields[] = { 7310 { MIB_TSC_MEM0_TMf, 8, 0, SOCF_LE }, 7311 { MIB_TSC_MEM1_TMf, 8, 8, SOCF_LE }, 7312 { MIB_TSC_MEM2_TMf, 8, 16, SOCF_LE } 7313 }; 7314 7315 #endif 7316 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 7317 defined(BCM_56670_A0) || defined(BCM_56670_B0) 7318 soc_field_info_t soc_XLPORT_MIB_MIN_FRAG_SIZEr_fields[] = { 7319 { MIN_FINAL_FRAG_SIZEf, 7, 0, SOCF_LE }, 7320 { MIN_NON_FINAL_FRAG_SIZEf, 7, 8, SOCF_LE }, 7321 { RESERVED_7f, 1, 7, SOCF_RO|SOCF_SC|SOCF_RES } 7322 }; 7323 7324 #endif 7325 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7326 defined(BCM_88732_A0) 7327 soc_field_info_t soc_XLPORT_MIB_RESETr_fields[] = { 7328 { CLR_CNTf, 4, 0, SOCF_LE } 7329 }; 7330 7331 #endif 7332 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 7333 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 7334 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 7335 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 7336 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 7337 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 7338 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 7339 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 7340 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 7341 defined(BCM_56980_B0) 7342 soc_field_info_t soc_XLPORT_MIB_RESET_BCM53400_A0r_fields[] = { 7343 { CLR_CNTf, 4, 0, SOCF_LE } 7344 }; 7345 7346 #endif 7347 #if defined(BCM_56150_A0) 7348 soc_field_info_t soc_XLPORT_MIB_RESET_BCM56150_A0r_fields[] = { 7349 { CLR_CNTf, 4, 0, SOCF_LE } 7350 }; 7351 7352 #endif 7353 #if defined(BCM_88270_A0) 7354 soc_field_info_t soc_XLPORT_MIB_RESET_BCM88270_A0r_fields[] = { 7355 { CLR_CNTf, 4, 0, SOCF_LE } 7356 }; 7357 7358 #endif 7359 #if defined(BCM_88375_A0) 7360 soc_field_info_t soc_XLPORT_MIB_RESET_BCM88375_A0r_fields[] = { 7361 { CLR_CNTf, 4, 0, SOCF_LE } 7362 }; 7363 7364 #endif 7365 #if defined(BCM_88375_B0) 7366 soc_field_info_t soc_XLPORT_MIB_RESET_BCM88375_B0r_fields[] = { 7367 { CLR_CNTf, 4, 0, SOCF_LE } 7368 }; 7369 7370 #endif 7371 #if defined(BCM_88470_A0) 7372 soc_field_info_t soc_XLPORT_MIB_RESET_BCM88470_A0r_fields[] = { 7373 { CLR_CNTf, 4, 0, SOCF_LE } 7374 }; 7375 7376 #endif 7377 #if defined(BCM_88470_B0) 7378 soc_field_info_t soc_XLPORT_MIB_RESET_BCM88470_B0r_fields[] = { 7379 { CLR_CNTf, 4, 0, SOCF_LE } 7380 }; 7381 7382 #endif 7383 #if defined(BCM_88675_A0) 7384 soc_field_info_t soc_XLPORT_MIB_RESET_BCM88675_A0r_fields[] = { 7385 { CLR_CNTf, 4, 0, SOCF_LE } 7386 }; 7387 7388 #endif 7389 #if defined(BCM_88675_B0) 7390 soc_field_info_t soc_XLPORT_MIB_RESET_BCM88675_B0r_fields[] = { 7391 { CLR_CNTf, 4, 0, SOCF_LE } 7392 }; 7393 7394 #endif 7395 #if defined(BCM_88680_A0) 7396 soc_field_info_t soc_XLPORT_MIB_RESET_BCM88680_A0r_fields[] = { 7397 { CLR_CNTf, 4, 0, SOCF_LE } 7398 }; 7399 7400 #endif 7401 #if defined(BCM_88675_A0) 7402 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUSr_fields[] = { 7403 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7404 { ECC_ERRf, 1, 0, 0 }, 7405 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7406 { MULTIPLE_ERRf, 1, 1, 0 } 7407 }; 7408 7409 #endif 7410 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 7411 defined(BCM_56670_A0) || defined(BCM_56670_B0) 7412 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM53570_A0r_fields[] = { 7413 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7414 { ECC_ERRf, 1, 0, 0 }, 7415 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7416 { MULTIPLE_ERRf, 1, 1, 0 }, 7417 { P_DOUBLE_BIT_ERRf, 1, 18, 0 }, 7418 { P_ECC_ERRf, 1, 16, 0 }, 7419 { P_ENTRY_IDXf, 8, 19, SOCF_LE }, 7420 { P_MULTIPLE_ERRf, 1, 17, 0 }, 7421 { RESERVED_15_11f, 5, 11, SOCF_LE|SOCF_RO|SOCF_RES } 7422 }; 7423 7424 #endif 7425 #if defined(BCM_88270_A0) 7426 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88270_A0r_fields[] = { 7427 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7428 { ECC_ERRf, 1, 0, 0 }, 7429 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7430 { MULTIPLE_ERRf, 1, 1, 0 } 7431 }; 7432 7433 #endif 7434 #if defined(BCM_88375_A0) 7435 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88375_A0r_fields[] = { 7436 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7437 { ECC_ERRf, 1, 0, 0 }, 7438 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7439 { MULTIPLE_ERRf, 1, 1, 0 } 7440 }; 7441 7442 #endif 7443 #if defined(BCM_88375_B0) 7444 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88375_B0r_fields[] = { 7445 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7446 { ECC_ERRf, 1, 0, 0 }, 7447 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7448 { MULTIPLE_ERRf, 1, 1, 0 } 7449 }; 7450 7451 #endif 7452 #if defined(BCM_88470_A0) 7453 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88470_A0r_fields[] = { 7454 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7455 { ECC_ERRf, 1, 0, 0 }, 7456 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7457 { MULTIPLE_ERRf, 1, 1, 0 } 7458 }; 7459 7460 #endif 7461 #if defined(BCM_88470_B0) 7462 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88470_B0r_fields[] = { 7463 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7464 { ECC_ERRf, 1, 0, 0 }, 7465 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7466 { MULTIPLE_ERRf, 1, 1, 0 } 7467 }; 7468 7469 #endif 7470 #if defined(BCM_88675_B0) 7471 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88675_B0r_fields[] = { 7472 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7473 { ECC_ERRf, 1, 0, 0 }, 7474 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7475 { MULTIPLE_ERRf, 1, 1, 0 } 7476 }; 7477 7478 #endif 7479 #if defined(BCM_88680_A0) 7480 soc_field_info_t soc_XLPORT_MIB_RSC0_ECC_STATUS_BCM88680_A0r_fields[] = { 7481 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7482 { ECC_ERRf, 1, 0, 0 }, 7483 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7484 { MULTIPLE_ERRf, 1, 1, 0 } 7485 }; 7486 7487 #endif 7488 #if defined(BCM_88675_A0) 7489 soc_field_info_t soc_XLPORT_MIB_RSC1_ECC_STATUSr_fields[] = { 7490 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7491 { ECC_ERRf, 1, 0, 0 }, 7492 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7493 { MULTIPLE_ERRf, 1, 1, 0 } 7494 }; 7495 7496 #endif 7497 #if defined(BCM_88270_A0) 7498 soc_field_info_t soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88270_A0r_fields[] = { 7499 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7500 { ECC_ERRf, 1, 0, 0 }, 7501 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7502 { MULTIPLE_ERRf, 1, 1, 0 } 7503 }; 7504 7505 #endif 7506 #if defined(BCM_88375_A0) 7507 soc_field_info_t soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88375_A0r_fields[] = { 7508 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7509 { ECC_ERRf, 1, 0, 0 }, 7510 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7511 { MULTIPLE_ERRf, 1, 1, 0 } 7512 }; 7513 7514 #endif 7515 #if defined(BCM_88375_B0) 7516 soc_field_info_t soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88375_B0r_fields[] = { 7517 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7518 { ECC_ERRf, 1, 0, 0 }, 7519 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7520 { MULTIPLE_ERRf, 1, 1, 0 } 7521 }; 7522 7523 #endif 7524 #if defined(BCM_88470_A0) 7525 soc_field_info_t soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88470_A0r_fields[] = { 7526 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7527 { ECC_ERRf, 1, 0, 0 }, 7528 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7529 { MULTIPLE_ERRf, 1, 1, 0 } 7530 }; 7531 7532 #endif 7533 #if defined(BCM_88470_B0) 7534 soc_field_info_t soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88470_B0r_fields[] = { 7535 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7536 { ECC_ERRf, 1, 0, 0 }, 7537 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7538 { MULTIPLE_ERRf, 1, 1, 0 } 7539 }; 7540 7541 #endif 7542 #if defined(BCM_88675_B0) 7543 soc_field_info_t soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88675_B0r_fields[] = { 7544 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7545 { ECC_ERRf, 1, 0, 0 }, 7546 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7547 { MULTIPLE_ERRf, 1, 1, 0 } 7548 }; 7549 7550 #endif 7551 #if defined(BCM_88680_A0) 7552 soc_field_info_t soc_XLPORT_MIB_RSC1_ECC_STATUS_BCM88680_A0r_fields[] = { 7553 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7554 { ECC_ERRf, 1, 0, 0 }, 7555 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7556 { MULTIPLE_ERRf, 1, 1, 0 } 7557 }; 7558 7559 #endif 7560 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7561 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7562 defined(BCM_88732_A0) 7563 soc_field_info_t soc_XLPORT_MIB_RSC_MEM0_ECC_STATUSr_fields[] = { 7564 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7565 { ECC_ERRf, 1, 0, 0 }, 7566 { ENTRY_IDXf, 4, 3, SOCF_LE }, 7567 { MULTIPLE_ERRf, 1, 1, 0 } 7568 }; 7569 7570 #endif 7571 #if defined(BCM_88675_A0) 7572 soc_field_info_t soc_XLPORT_MIB_RSC_RAM_CONTROLr_fields[] = { 7573 { MIB_RSC_DATA_HI_LVMf, 1, 25, 0 }, 7574 { MIB_RSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7575 { MIB_RSC_DATA_LO_LVMf, 1, 24, 0 }, 7576 { MIB_RSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7577 }; 7578 7579 #endif 7580 #if defined(BCM_88270_A0) 7581 soc_field_info_t soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88270_A0r_fields[] = { 7582 { MIB_RSC_DATA_HI_LVMf, 1, 25, 0 }, 7583 { MIB_RSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7584 { MIB_RSC_DATA_LO_LVMf, 1, 24, 0 }, 7585 { MIB_RSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7586 }; 7587 7588 #endif 7589 #if defined(BCM_88375_A0) 7590 soc_field_info_t soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88375_A0r_fields[] = { 7591 { MIB_RSC_DATA_HI_LVMf, 1, 25, 0 }, 7592 { MIB_RSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7593 { MIB_RSC_DATA_LO_LVMf, 1, 24, 0 }, 7594 { MIB_RSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7595 }; 7596 7597 #endif 7598 #if defined(BCM_88375_B0) 7599 soc_field_info_t soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88375_B0r_fields[] = { 7600 { MIB_RSC_DATA_HI_LVMf, 1, 25, 0 }, 7601 { MIB_RSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7602 { MIB_RSC_DATA_LO_LVMf, 1, 24, 0 }, 7603 { MIB_RSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7604 }; 7605 7606 #endif 7607 #if defined(BCM_88470_A0) 7608 soc_field_info_t soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88470_A0r_fields[] = { 7609 { MIB_RSC_DATA_HI_LVMf, 1, 25, 0 }, 7610 { MIB_RSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7611 { MIB_RSC_DATA_LO_LVMf, 1, 24, 0 }, 7612 { MIB_RSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7613 }; 7614 7615 #endif 7616 #if defined(BCM_88470_B0) 7617 soc_field_info_t soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88470_B0r_fields[] = { 7618 { MIB_RSC_DATA_HI_LVMf, 1, 25, 0 }, 7619 { MIB_RSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7620 { MIB_RSC_DATA_LO_LVMf, 1, 24, 0 }, 7621 { MIB_RSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7622 }; 7623 7624 #endif 7625 #if defined(BCM_88675_B0) 7626 soc_field_info_t soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88675_B0r_fields[] = { 7627 { MIB_RSC_DATA_HI_LVMf, 1, 25, 0 }, 7628 { MIB_RSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7629 { MIB_RSC_DATA_LO_LVMf, 1, 24, 0 }, 7630 { MIB_RSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7631 }; 7632 7633 #endif 7634 #if defined(BCM_88680_A0) 7635 soc_field_info_t soc_XLPORT_MIB_RSC_RAM_CONTROL_BCM88680_A0r_fields[] = { 7636 { MIB_RSC_DATA_HI_LVMf, 1, 25, 0 }, 7637 { MIB_RSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7638 { MIB_RSC_DATA_LO_LVMf, 1, 24, 0 }, 7639 { MIB_RSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7640 }; 7641 7642 #endif 7643 #if defined(BCM_88675_A0) 7644 soc_field_info_t soc_XLPORT_MIB_TSC0_ECC_STATUSr_fields[] = { 7645 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7646 { ECC_ERRf, 1, 0, 0 }, 7647 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7648 { MULTIPLE_ERRf, 1, 1, 0 } 7649 }; 7650 7651 #endif 7652 #if defined(BCM_88270_A0) 7653 soc_field_info_t soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88270_A0r_fields[] = { 7654 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7655 { ECC_ERRf, 1, 0, 0 }, 7656 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7657 { MULTIPLE_ERRf, 1, 1, 0 } 7658 }; 7659 7660 #endif 7661 #if defined(BCM_88375_A0) 7662 soc_field_info_t soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88375_A0r_fields[] = { 7663 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7664 { ECC_ERRf, 1, 0, 0 }, 7665 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7666 { MULTIPLE_ERRf, 1, 1, 0 } 7667 }; 7668 7669 #endif 7670 #if defined(BCM_88375_B0) 7671 soc_field_info_t soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88375_B0r_fields[] = { 7672 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7673 { ECC_ERRf, 1, 0, 0 }, 7674 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7675 { MULTIPLE_ERRf, 1, 1, 0 } 7676 }; 7677 7678 #endif 7679 #if defined(BCM_88470_A0) 7680 soc_field_info_t soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88470_A0r_fields[] = { 7681 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7682 { ECC_ERRf, 1, 0, 0 }, 7683 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7684 { MULTIPLE_ERRf, 1, 1, 0 } 7685 }; 7686 7687 #endif 7688 #if defined(BCM_88470_B0) 7689 soc_field_info_t soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88470_B0r_fields[] = { 7690 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7691 { ECC_ERRf, 1, 0, 0 }, 7692 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7693 { MULTIPLE_ERRf, 1, 1, 0 } 7694 }; 7695 7696 #endif 7697 #if defined(BCM_88675_B0) 7698 soc_field_info_t soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88675_B0r_fields[] = { 7699 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7700 { ECC_ERRf, 1, 0, 0 }, 7701 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7702 { MULTIPLE_ERRf, 1, 1, 0 } 7703 }; 7704 7705 #endif 7706 #if defined(BCM_88680_A0) 7707 soc_field_info_t soc_XLPORT_MIB_TSC0_ECC_STATUS_BCM88680_A0r_fields[] = { 7708 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7709 { ECC_ERRf, 1, 0, 0 }, 7710 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7711 { MULTIPLE_ERRf, 1, 1, 0 } 7712 }; 7713 7714 #endif 7715 #if defined(BCM_88675_A0) 7716 soc_field_info_t soc_XLPORT_MIB_TSC1_ECC_STATUSr_fields[] = { 7717 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7718 { ECC_ERRf, 1, 0, 0 }, 7719 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7720 { MULTIPLE_ERRf, 1, 1, 0 } 7721 }; 7722 7723 #endif 7724 #if defined(BCM_88270_A0) 7725 soc_field_info_t soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88270_A0r_fields[] = { 7726 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7727 { ECC_ERRf, 1, 0, 0 }, 7728 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7729 { MULTIPLE_ERRf, 1, 1, 0 } 7730 }; 7731 7732 #endif 7733 #if defined(BCM_88375_A0) 7734 soc_field_info_t soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88375_A0r_fields[] = { 7735 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7736 { ECC_ERRf, 1, 0, 0 }, 7737 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7738 { MULTIPLE_ERRf, 1, 1, 0 } 7739 }; 7740 7741 #endif 7742 #if defined(BCM_88375_B0) 7743 soc_field_info_t soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88375_B0r_fields[] = { 7744 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7745 { ECC_ERRf, 1, 0, 0 }, 7746 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7747 { MULTIPLE_ERRf, 1, 1, 0 } 7748 }; 7749 7750 #endif 7751 #if defined(BCM_88470_A0) 7752 soc_field_info_t soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88470_A0r_fields[] = { 7753 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7754 { ECC_ERRf, 1, 0, 0 }, 7755 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7756 { MULTIPLE_ERRf, 1, 1, 0 } 7757 }; 7758 7759 #endif 7760 #if defined(BCM_88470_B0) 7761 soc_field_info_t soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88470_B0r_fields[] = { 7762 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7763 { ECC_ERRf, 1, 0, 0 }, 7764 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7765 { MULTIPLE_ERRf, 1, 1, 0 } 7766 }; 7767 7768 #endif 7769 #if defined(BCM_88675_B0) 7770 soc_field_info_t soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88675_B0r_fields[] = { 7771 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7772 { ECC_ERRf, 1, 0, 0 }, 7773 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7774 { MULTIPLE_ERRf, 1, 1, 0 } 7775 }; 7776 7777 #endif 7778 #if defined(BCM_88680_A0) 7779 soc_field_info_t soc_XLPORT_MIB_TSC1_ECC_STATUS_BCM88680_A0r_fields[] = { 7780 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 7781 { ECC_ERRf, 1, 0, 0 }, 7782 { ENTRY_IDXf, 8, 3, SOCF_LE }, 7783 { MULTIPLE_ERRf, 1, 1, 0 } 7784 }; 7785 7786 #endif 7787 #if defined(BCM_88675_A0) 7788 soc_field_info_t soc_XLPORT_MIB_TSC_RAM_CONTROLr_fields[] = { 7789 { MIB_TSC_DATA_HI_LVMf, 1, 25, 0 }, 7790 { MIB_TSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7791 { MIB_TSC_DATA_LO_LVMf, 1, 24, 0 }, 7792 { MIB_TSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7793 }; 7794 7795 #endif 7796 #if defined(BCM_88270_A0) 7797 soc_field_info_t soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88270_A0r_fields[] = { 7798 { MIB_TSC_DATA_HI_LVMf, 1, 25, 0 }, 7799 { MIB_TSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7800 { MIB_TSC_DATA_LO_LVMf, 1, 24, 0 }, 7801 { MIB_TSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7802 }; 7803 7804 #endif 7805 #if defined(BCM_88375_A0) 7806 soc_field_info_t soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88375_A0r_fields[] = { 7807 { MIB_TSC_DATA_HI_LVMf, 1, 25, 0 }, 7808 { MIB_TSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7809 { MIB_TSC_DATA_LO_LVMf, 1, 24, 0 }, 7810 { MIB_TSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7811 }; 7812 7813 #endif 7814 #if defined(BCM_88375_B0) 7815 soc_field_info_t soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88375_B0r_fields[] = { 7816 { MIB_TSC_DATA_HI_LVMf, 1, 25, 0 }, 7817 { MIB_TSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7818 { MIB_TSC_DATA_LO_LVMf, 1, 24, 0 }, 7819 { MIB_TSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7820 }; 7821 7822 #endif 7823 #if defined(BCM_88470_A0) 7824 soc_field_info_t soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88470_A0r_fields[] = { 7825 { MIB_TSC_DATA_HI_LVMf, 1, 25, 0 }, 7826 { MIB_TSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7827 { MIB_TSC_DATA_LO_LVMf, 1, 24, 0 }, 7828 { MIB_TSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7829 }; 7830 7831 #endif 7832 #if defined(BCM_88470_B0) 7833 soc_field_info_t soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88470_B0r_fields[] = { 7834 { MIB_TSC_DATA_HI_LVMf, 1, 25, 0 }, 7835 { MIB_TSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7836 { MIB_TSC_DATA_LO_LVMf, 1, 24, 0 }, 7837 { MIB_TSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7838 }; 7839 7840 #endif 7841 #if defined(BCM_88675_B0) 7842 soc_field_info_t soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88675_B0r_fields[] = { 7843 { MIB_TSC_DATA_HI_LVMf, 1, 25, 0 }, 7844 { MIB_TSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7845 { MIB_TSC_DATA_LO_LVMf, 1, 24, 0 }, 7846 { MIB_TSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7847 }; 7848 7849 #endif 7850 #if defined(BCM_88680_A0) 7851 soc_field_info_t soc_XLPORT_MIB_TSC_RAM_CONTROL_BCM88680_A0r_fields[] = { 7852 { MIB_TSC_DATA_HI_LVMf, 1, 25, 0 }, 7853 { MIB_TSC_DATA_HI_TMf, 12, 12, SOCF_LE }, 7854 { MIB_TSC_DATA_LO_LVMf, 1, 24, 0 }, 7855 { MIB_TSC_DATA_LO_TMf, 12, 0, SOCF_LE } 7856 }; 7857 7858 #endif 7859 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7860 defined(BCM_88732_A0) 7861 soc_field_info_t soc_XLPORT_MODE_REGr_fields[] = { 7862 { CORE_PORT_MODEf, 2, 0, SOCF_LE }, 7863 { PHY_PORT_MODEf, 2, 2, SOCF_LE }, 7864 { PORT0_MAC_MODEf, 1, 4, 0 }, 7865 { PORT1_MAC_MODEf, 1, 5, 0 }, 7866 { PORT2_MAC_MODEf, 1, 6, 0 }, 7867 { PORT3_MAC_MODEf, 1, 7, 0 } 7868 }; 7869 7870 #endif 7871 #if defined(BCM_2801PM_A0) 7872 soc_field_info_t soc_XLPORT_MODE_REG_BCM2801PM_A0r_fields[] = { 7873 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7874 { FIELD_8_8f, 1, 8, 0 }, 7875 { FIELD_9_9f, 1, 9, 0 }, 7876 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7877 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7878 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7879 }; 7880 7881 #endif 7882 #if defined(BCM_53400_A0) || defined(BCM_56260_A0) 7883 soc_field_info_t soc_XLPORT_MODE_REG_BCM53400_A0r_fields[] = { 7884 { EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1, 9, SOCF_SC|SOCF_RES }, 7885 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7886 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7887 { TS_TIMER_OVERRIDEf, 1, 8, SOCF_SC|SOCF_RES }, 7888 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7889 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7890 }; 7891 7892 #endif 7893 #if defined(BCM_56150_A0) 7894 soc_field_info_t soc_XLPORT_MODE_REG_BCM56150_A0r_fields[] = { 7895 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7896 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7897 { TS_TIMER_OVERRIDEf, 1, 8, SOCF_SC|SOCF_RES }, 7898 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7899 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7900 }; 7901 7902 #endif 7903 #if defined(BCM_56850_A0) 7904 soc_field_info_t soc_XLPORT_MODE_REG_BCM56850_A0r_fields[] = { 7905 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7906 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7907 }; 7908 7909 #endif 7910 #if defined(BCM_56860_A0) 7911 soc_field_info_t soc_XLPORT_MODE_REG_BCM56860_A0r_fields[] = { 7912 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7913 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7914 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7915 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7916 }; 7917 7918 #endif 7919 #if defined(BCM_56160_A0) || defined(BCM_56260_B0) || \ 7920 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 7921 defined(BCM_56560_B0) || defined(BCM_56960_A0) || \ 7922 defined(BCM_56965_A0) 7923 soc_field_info_t soc_XLPORT_MODE_REG_BCM56960_A0r_fields[] = { 7924 { EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1, 9, SOCF_RES }, 7925 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7926 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7927 { TS_TIMER_OVERRIDEf, 1, 8, SOCF_RES }, 7928 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7929 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7930 }; 7931 7932 #endif 7933 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 7934 defined(BCM_56370_A0) || defined(BCM_56670_A0) || \ 7935 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 7936 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 7937 defined(BCM_56980_A0) || defined(BCM_56980_B0) 7938 soc_field_info_t soc_XLPORT_MODE_REG_BCM56970_A0r_fields[] = { 7939 { EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1, 9, 0 }, 7940 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7941 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7942 { TS_TIMER_OVERRIDEf, 1, 8, SOCF_SC|SOCF_RES }, 7943 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7944 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7945 }; 7946 7947 #endif 7948 #if defined(BCM_88270_A0) 7949 soc_field_info_t soc_XLPORT_MODE_REG_BCM88270_A0r_fields[] = { 7950 { EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1, 9, 0 }, 7951 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7952 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7953 { TS_TIMER_OVERRIDEf, 1, 8, 0 }, 7954 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7955 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7956 }; 7957 7958 #endif 7959 #if defined(BCM_88375_A0) 7960 soc_field_info_t soc_XLPORT_MODE_REG_BCM88375_A0r_fields[] = { 7961 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7962 { FIELD_8_8f, 1, 8, 0 }, 7963 { FIELD_9_9f, 1, 9, 0 }, 7964 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7965 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7966 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7967 }; 7968 7969 #endif 7970 #if defined(BCM_88375_B0) 7971 soc_field_info_t soc_XLPORT_MODE_REG_BCM88375_B0r_fields[] = { 7972 { EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1, 9, 0 }, 7973 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7974 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7975 { TS_TIMER_OVERRIDEf, 1, 8, 0 }, 7976 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7977 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7978 }; 7979 7980 #endif 7981 #if defined(BCM_88470_A0) 7982 soc_field_info_t soc_XLPORT_MODE_REG_BCM88470_A0r_fields[] = { 7983 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7984 { FIELD_8_8f, 1, 8, 0 }, 7985 { FIELD_9_9f, 1, 9, 0 }, 7986 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7987 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7988 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 7989 }; 7990 7991 #endif 7992 #if defined(BCM_88470_B0) 7993 soc_field_info_t soc_XLPORT_MODE_REG_BCM88470_B0r_fields[] = { 7994 { EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1, 9, 0 }, 7995 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 7996 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 7997 { TS_TIMER_OVERRIDEf, 1, 8, 0 }, 7998 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 7999 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 8000 }; 8001 8002 #endif 8003 #if defined(BCM_88675_A0) 8004 soc_field_info_t soc_XLPORT_MODE_REG_BCM88675_A0r_fields[] = { 8005 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 8006 { FIELD_8_8f, 1, 8, 0 }, 8007 { FIELD_9_9f, 1, 9, 0 }, 8008 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 8009 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 8010 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 8011 }; 8012 8013 #endif 8014 #if defined(BCM_88675_B0) 8015 soc_field_info_t soc_XLPORT_MODE_REG_BCM88675_B0r_fields[] = { 8016 { EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1, 9, 0 }, 8017 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 8018 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 8019 { TS_TIMER_OVERRIDEf, 1, 8, 0 }, 8020 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 8021 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 8022 }; 8023 8024 #endif 8025 #if defined(BCM_88680_A0) 8026 soc_field_info_t soc_XLPORT_MODE_REG_BCM88680_A0r_fields[] = { 8027 { EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1, 9, 0 }, 8028 { EGR_1588_TIMESTAMPING_MODEf, 1, 6, 0 }, 8029 { OSTS_TIMER_DISABLEf, 1, 7, 0 }, 8030 { TS_TIMER_OVERRIDEf, 1, 8, 0 }, 8031 { XPORT0_CORE_PORT_MODEf, 3, 3, SOCF_LE }, 8032 { XPORT0_PHY_PORT_MODEf, 3, 0, SOCF_LE } 8033 }; 8034 8035 #endif 8036 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8037 defined(BCM_56370_A0) || defined(BCM_56670_A0) || \ 8038 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 8039 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 8040 defined(BCM_56980_A0) || defined(BCM_56980_B0) 8041 soc_field_info_t soc_XLPORT_PMD_PLL_CTRL_CONFIGr_fields[] = { 8042 { REFCLK_DIV2f, 1, 2, 0 }, 8043 { REFCLK_DIV4f, 1, 3, 0 }, 8044 { REFCLK_TERM_SELf, 2, 0, SOCF_LE } 8045 }; 8046 8047 #endif 8048 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 8049 defined(BCM_56970_A0) 8050 soc_field_info_t soc_XLPORT_PM_VERSION_IDr_fields[] = { 8051 { PM_TYPEf, 4, 0, SOCF_LE|SOCF_RO }, 8052 { REV_LETTERf, 2, 10, SOCF_LE|SOCF_RO }, 8053 { REV_NUMBERf, 3, 7, SOCF_LE|SOCF_RO }, 8054 { RSVDf, 4, 12, SOCF_LE|SOCF_RO|SOCF_RES }, 8055 { TECH_PROCESSf, 3, 4, SOCF_LE|SOCF_RO } 8056 }; 8057 8058 #endif 8059 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8060 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8061 soc_field_info_t soc_XLPORT_PM_VERSION_ID_BCM53570_A0r_fields[] = { 8062 { PM_TYPEf, 4, 0, SOCF_LE|SOCF_RO }, 8063 { REV_LETTERf, 2, 10, SOCF_LE|SOCF_RO }, 8064 { REV_NUMBERf, 3, 7, SOCF_LE|SOCF_RO }, 8065 { RSVDf, 4, 12, SOCF_LE|SOCF_RO|SOCF_RES }, 8066 { TECH_PROCESSf, 3, 4, SOCF_LE|SOCF_RO } 8067 }; 8068 8069 #endif 8070 #if defined(BCM_56370_A0) || defined(BCM_56980_A0) || \ 8071 defined(BCM_56980_B0) 8072 soc_field_info_t soc_XLPORT_PM_VERSION_ID_BCM56980_A0r_fields[] = { 8073 { PM_TYPEf, 4, 0, SOCF_LE|SOCF_RO }, 8074 { REV_LETTERf, 2, 10, SOCF_LE|SOCF_RO }, 8075 { REV_NUMBERf, 3, 7, SOCF_LE|SOCF_RO }, 8076 { RSVDf, 4, 12, SOCF_LE|SOCF_RO|SOCF_RES }, 8077 { TECH_PROCESSf, 3, 4, SOCF_LE|SOCF_RO } 8078 }; 8079 8080 #endif 8081 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 8082 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 8083 defined(BCM_88732_A0) 8084 soc_field_info_t soc_XLPORT_PORT_ENABLEr_fields[] = { 8085 { PORT0f, 1, 0, 0 }, 8086 { PORT1f, 1, 1, 0 }, 8087 { PORT2f, 1, 2, 0 }, 8088 { PORT3f, 1, 3, 0 } 8089 }; 8090 8091 #endif 8092 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8093 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8094 soc_field_info_t soc_XLPORT_PORT_SPARE0r_fields[] = { 8095 { RSVDf, 32, 0, SOCF_LE|SOCF_RES } 8096 }; 8097 8098 #endif 8099 #if defined(BCM_88675_A0) 8100 soc_field_info_t soc_XLPORT_POWER_SAVEr_fields[] = { 8101 { XPORT_CORE0f, 1, 0, 0 } 8102 }; 8103 8104 #endif 8105 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 8106 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 8107 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 8108 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 8109 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 8110 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 8111 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 8112 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 8113 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 8114 defined(BCM_56980_B0) 8115 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM53400_A0r_fields[] = { 8116 { XPORT_CORE0f, 1, 0, SOCF_RES } 8117 }; 8118 8119 #endif 8120 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 8121 defined(BCM_56860_A0) 8122 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM56850_A0r_fields[] = { 8123 { XPORT_CORE0f, 1, 0, SOCF_RES } 8124 }; 8125 8126 #endif 8127 #if defined(BCM_88270_A0) 8128 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM88270_A0r_fields[] = { 8129 { XPORT_CORE0f, 1, 0, 0 } 8130 }; 8131 8132 #endif 8133 #if defined(BCM_88375_A0) 8134 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM88375_A0r_fields[] = { 8135 { XPORT_CORE0f, 1, 0, 0 } 8136 }; 8137 8138 #endif 8139 #if defined(BCM_88375_B0) 8140 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM88375_B0r_fields[] = { 8141 { XPORT_CORE0f, 1, 0, 0 } 8142 }; 8143 8144 #endif 8145 #if defined(BCM_88470_A0) 8146 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM88470_A0r_fields[] = { 8147 { XPORT_CORE0f, 1, 0, 0 } 8148 }; 8149 8150 #endif 8151 #if defined(BCM_88470_B0) 8152 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM88470_B0r_fields[] = { 8153 { XPORT_CORE0f, 1, 0, 0 } 8154 }; 8155 8156 #endif 8157 #if defined(BCM_88675_B0) 8158 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM88675_B0r_fields[] = { 8159 { XPORT_CORE0f, 1, 0, 0 } 8160 }; 8161 8162 #endif 8163 #if defined(BCM_88680_A0) 8164 soc_field_info_t soc_XLPORT_POWER_SAVE_BCM88680_A0r_fields[] = { 8165 { XPORT_CORE0f, 1, 0, 0 } 8166 }; 8167 8168 #endif 8169 #if defined(BCM_88675_A0) 8170 soc_field_info_t soc_XLPORT_SBUS_CONTROLr_fields[] = { 8171 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8172 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8173 }; 8174 8175 #endif 8176 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 8177 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 8178 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 8179 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 8180 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 8181 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 8182 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 8183 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 8184 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 8185 defined(BCM_56980_B0) 8186 soc_field_info_t soc_XLPORT_SBUS_CONTROL_BCM53400_A0r_fields[] = { 8187 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8188 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8189 }; 8190 8191 #endif 8192 #if defined(BCM_88270_A0) 8193 soc_field_info_t soc_XLPORT_SBUS_CONTROL_BCM88270_A0r_fields[] = { 8194 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8195 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8196 }; 8197 8198 #endif 8199 #if defined(BCM_88375_A0) 8200 soc_field_info_t soc_XLPORT_SBUS_CONTROL_BCM88375_A0r_fields[] = { 8201 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8202 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8203 }; 8204 8205 #endif 8206 #if defined(BCM_88375_B0) 8207 soc_field_info_t soc_XLPORT_SBUS_CONTROL_BCM88375_B0r_fields[] = { 8208 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8209 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8210 }; 8211 8212 #endif 8213 #if defined(BCM_88470_A0) 8214 soc_field_info_t soc_XLPORT_SBUS_CONTROL_BCM88470_A0r_fields[] = { 8215 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8216 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8217 }; 8218 8219 #endif 8220 #if defined(BCM_88470_B0) 8221 soc_field_info_t soc_XLPORT_SBUS_CONTROL_BCM88470_B0r_fields[] = { 8222 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8223 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8224 }; 8225 8226 #endif 8227 #if defined(BCM_88675_B0) 8228 soc_field_info_t soc_XLPORT_SBUS_CONTROL_BCM88675_B0r_fields[] = { 8229 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8230 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8231 }; 8232 8233 #endif 8234 #if defined(BCM_88680_A0) 8235 soc_field_info_t soc_XLPORT_SBUS_CONTROL_BCM88680_A0r_fields[] = { 8236 { SBUS_BCAST_BLOCK_IDf, 7, 0, SOCF_LE }, 8237 { SBUS_CHAIN_LASTf, 1, 7, 0 } 8238 }; 8239 8240 #endif 8241 #if defined(BCM_88675_A0) 8242 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRSr_fields[] = { 8243 { SGN_DETf, 1, 0, 0 } 8244 }; 8245 8246 #endif 8247 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 8248 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 8249 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 8250 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 8251 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 8252 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 8253 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 8254 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 8255 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 8256 defined(BCM_56980_B0) 8257 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRS_BCM53400_A0r_fields[] = { 8258 { SGN_DETf, 1, 0, SOCF_RES } 8259 }; 8260 8261 #endif 8262 #if defined(BCM_88270_A0) 8263 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRS_BCM88270_A0r_fields[] = { 8264 { SGN_DETf, 1, 0, 0 } 8265 }; 8266 8267 #endif 8268 #if defined(BCM_88375_A0) 8269 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRS_BCM88375_A0r_fields[] = { 8270 { SGN_DETf, 1, 0, 0 } 8271 }; 8272 8273 #endif 8274 #if defined(BCM_88375_B0) 8275 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRS_BCM88375_B0r_fields[] = { 8276 { SGN_DETf, 1, 0, 0 } 8277 }; 8278 8279 #endif 8280 #if defined(BCM_88470_A0) 8281 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRS_BCM88470_A0r_fields[] = { 8282 { SGN_DETf, 1, 0, 0 } 8283 }; 8284 8285 #endif 8286 #if defined(BCM_88470_B0) 8287 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRS_BCM88470_B0r_fields[] = { 8288 { SGN_DETf, 1, 0, 0 } 8289 }; 8290 8291 #endif 8292 #if defined(BCM_88675_B0) 8293 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRS_BCM88675_B0r_fields[] = { 8294 { SGN_DETf, 1, 0, 0 } 8295 }; 8296 8297 #endif 8298 #if defined(BCM_88680_A0) 8299 soc_field_info_t soc_XLPORT_SGNDET_EARLYCRS_BCM88680_A0r_fields[] = { 8300 { SGN_DETf, 1, 0, 0 } 8301 }; 8302 8303 #endif 8304 #if defined(BCM_88675_A0) 8305 soc_field_info_t soc_XLPORT_SOFT_RESETr_fields[] = { 8306 { FIELD_4_4f, 1, 4, 0 }, 8307 { PORT0f, 1, 0, 0 }, 8308 { PORT1f, 1, 1, 0 }, 8309 { PORT2f, 1, 2, 0 }, 8310 { PORT3f, 1, 3, 0 } 8311 }; 8312 8313 #endif 8314 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 8315 defined(BCM_56860_A0) 8316 soc_field_info_t soc_XLPORT_SOFT_RESET_BCM56850_A0r_fields[] = { 8317 { PORT0f, 1, 0, SOCF_RES }, 8318 { PORT1f, 1, 1, SOCF_RES }, 8319 { PORT2f, 1, 2, SOCF_RES }, 8320 { PORT3f, 1, 3, SOCF_RES }, 8321 { RESERVED4f, 1, 4, SOCF_RES } 8322 }; 8323 8324 #endif 8325 #if defined(BCM_88270_A0) 8326 soc_field_info_t soc_XLPORT_SOFT_RESET_BCM88270_A0r_fields[] = { 8327 { FIELD_4_4f, 1, 4, 0 }, 8328 { PORT0f, 1, 0, 0 }, 8329 { PORT1f, 1, 1, 0 }, 8330 { PORT2f, 1, 2, 0 }, 8331 { PORT3f, 1, 3, 0 } 8332 }; 8333 8334 #endif 8335 #if defined(BCM_88375_A0) 8336 soc_field_info_t soc_XLPORT_SOFT_RESET_BCM88375_A0r_fields[] = { 8337 { FIELD_4_4f, 1, 4, 0 }, 8338 { PORT0f, 1, 0, 0 }, 8339 { PORT1f, 1, 1, 0 }, 8340 { PORT2f, 1, 2, 0 }, 8341 { PORT3f, 1, 3, 0 } 8342 }; 8343 8344 #endif 8345 #if defined(BCM_88375_B0) 8346 soc_field_info_t soc_XLPORT_SOFT_RESET_BCM88375_B0r_fields[] = { 8347 { FIELD_4_4f, 1, 4, 0 }, 8348 { PORT0f, 1, 0, 0 }, 8349 { PORT1f, 1, 1, 0 }, 8350 { PORT2f, 1, 2, 0 }, 8351 { PORT3f, 1, 3, 0 } 8352 }; 8353 8354 #endif 8355 #if defined(BCM_88470_A0) 8356 soc_field_info_t soc_XLPORT_SOFT_RESET_BCM88470_A0r_fields[] = { 8357 { FIELD_4_4f, 1, 4, 0 }, 8358 { PORT0f, 1, 0, 0 }, 8359 { PORT1f, 1, 1, 0 }, 8360 { PORT2f, 1, 2, 0 }, 8361 { PORT3f, 1, 3, 0 } 8362 }; 8363 8364 #endif 8365 #if defined(BCM_88470_B0) 8366 soc_field_info_t soc_XLPORT_SOFT_RESET_BCM88470_B0r_fields[] = { 8367 { FIELD_4_4f, 1, 4, 0 }, 8368 { PORT0f, 1, 0, 0 }, 8369 { PORT1f, 1, 1, 0 }, 8370 { PORT2f, 1, 2, 0 }, 8371 { PORT3f, 1, 3, 0 } 8372 }; 8373 8374 #endif 8375 #if defined(BCM_88675_B0) 8376 soc_field_info_t soc_XLPORT_SOFT_RESET_BCM88675_B0r_fields[] = { 8377 { FIELD_4_4f, 1, 4, 0 }, 8378 { PORT0f, 1, 0, 0 }, 8379 { PORT1f, 1, 1, 0 }, 8380 { PORT2f, 1, 2, 0 }, 8381 { PORT3f, 1, 3, 0 } 8382 }; 8383 8384 #endif 8385 #if defined(BCM_88680_A0) 8386 soc_field_info_t soc_XLPORT_SOFT_RESET_BCM88680_A0r_fields[] = { 8387 { FIELD_4_4f, 1, 4, 0 }, 8388 { PORT0f, 1, 0, 0 }, 8389 { PORT1f, 1, 1, 0 }, 8390 { PORT2f, 1, 2, 0 }, 8391 { PORT3f, 1, 3, 0 } 8392 }; 8393 8394 #endif 8395 #if defined(BCM_88675_A0) 8396 soc_field_info_t soc_XLPORT_SPARE0_REGr_fields[] = { 8397 { RSVDf, 32, 0, SOCF_LE } 8398 }; 8399 8400 #endif 8401 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 8402 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 8403 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 8404 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 8405 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 8406 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 8407 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 8408 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 8409 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 8410 defined(BCM_56980_B0) 8411 soc_field_info_t soc_XLPORT_SPARE0_REG_BCM53400_A0r_fields[] = { 8412 { RSVDf, 32, 0, SOCF_LE|SOCF_RES } 8413 }; 8414 8415 #endif 8416 #if defined(BCM_88270_A0) 8417 soc_field_info_t soc_XLPORT_SPARE0_REG_BCM88270_A0r_fields[] = { 8418 { RSVDf, 32, 0, SOCF_LE } 8419 }; 8420 8421 #endif 8422 #if defined(BCM_88375_A0) 8423 soc_field_info_t soc_XLPORT_SPARE0_REG_BCM88375_A0r_fields[] = { 8424 { RSVDf, 32, 0, SOCF_LE } 8425 }; 8426 8427 #endif 8428 #if defined(BCM_88375_B0) 8429 soc_field_info_t soc_XLPORT_SPARE0_REG_BCM88375_B0r_fields[] = { 8430 { RSVDf, 32, 0, SOCF_LE } 8431 }; 8432 8433 #endif 8434 #if defined(BCM_88470_A0) 8435 soc_field_info_t soc_XLPORT_SPARE0_REG_BCM88470_A0r_fields[] = { 8436 { RSVDf, 32, 0, SOCF_LE } 8437 }; 8438 8439 #endif 8440 #if defined(BCM_88470_B0) 8441 soc_field_info_t soc_XLPORT_SPARE0_REG_BCM88470_B0r_fields[] = { 8442 { RSVDf, 32, 0, SOCF_LE } 8443 }; 8444 8445 #endif 8446 #if defined(BCM_88675_B0) 8447 soc_field_info_t soc_XLPORT_SPARE0_REG_BCM88675_B0r_fields[] = { 8448 { RSVDf, 32, 0, SOCF_LE } 8449 }; 8450 8451 #endif 8452 #if defined(BCM_88680_A0) 8453 soc_field_info_t soc_XLPORT_SPARE0_REG_BCM88680_A0r_fields[] = { 8454 { RSVDf, 32, 0, SOCF_LE } 8455 }; 8456 8457 #endif 8458 #if defined(BCM_88675_A0) 8459 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROLr_fields[] = { 8460 { FC_ENf, 1, 1, 0 }, 8461 { FC_PAUSEf, 1, 0, 0 } 8462 }; 8463 8464 #endif 8465 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 8466 defined(BCM_56860_A0) 8467 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROL_BCM56850_A0r_fields[] = { 8468 { FC_ENf, 1, 1, 0 }, 8469 { FC_PAUSEf, 1, 0, 0 } 8470 }; 8471 8472 #endif 8473 #if defined(BCM_88270_A0) 8474 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROL_BCM88270_A0r_fields[] = { 8475 { FC_ENf, 1, 1, 0 }, 8476 { FC_PAUSEf, 1, 0, 0 } 8477 }; 8478 8479 #endif 8480 #if defined(BCM_88375_A0) 8481 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROL_BCM88375_A0r_fields[] = { 8482 { FC_ENf, 1, 1, 0 }, 8483 { FC_PAUSEf, 1, 0, 0 } 8484 }; 8485 8486 #endif 8487 #if defined(BCM_88375_B0) 8488 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROL_BCM88375_B0r_fields[] = { 8489 { FC_ENf, 1, 1, 0 }, 8490 { FC_PAUSEf, 1, 0, 0 } 8491 }; 8492 8493 #endif 8494 #if defined(BCM_88470_A0) 8495 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROL_BCM88470_A0r_fields[] = { 8496 { FC_ENf, 1, 1, 0 }, 8497 { FC_PAUSEf, 1, 0, 0 } 8498 }; 8499 8500 #endif 8501 #if defined(BCM_88470_B0) 8502 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROL_BCM88470_B0r_fields[] = { 8503 { FC_ENf, 1, 1, 0 }, 8504 { FC_PAUSEf, 1, 0, 0 } 8505 }; 8506 8507 #endif 8508 #if defined(BCM_88675_B0) 8509 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROL_BCM88675_B0r_fields[] = { 8510 { FC_ENf, 1, 1, 0 }, 8511 { FC_PAUSEf, 1, 0, 0 } 8512 }; 8513 8514 #endif 8515 #if defined(BCM_88680_A0) 8516 soc_field_info_t soc_XLPORT_SW_FLOW_CONTROL_BCM88680_A0r_fields[] = { 8517 { FC_ENf, 1, 1, 0 }, 8518 { FC_PAUSEf, 1, 0, 0 } 8519 }; 8520 8521 #endif 8522 #if defined(BCM_56150_A0) 8523 soc_field_info_t soc_XLPORT_TM_CONTROLr_fields[] = { 8524 { CELL_ASM_BOD_FIFO_0_TMf, 2, 24, SOCF_LE }, 8525 { CELL_ASM_BOD_FIFO_1_TMf, 2, 22, SOCF_LE }, 8526 { CELL_ASM_BOD_FIFO_2_TMf, 2, 20, SOCF_LE }, 8527 { CELL_ASM_BOD_FIFO_3_TMf, 2, 18, SOCF_LE }, 8528 { CELL_ASM_BOD_FIFO_4_TMf, 2, 16, SOCF_LE }, 8529 { CELL_ASM_BOD_FIFO_5_TMf, 2, 14, SOCF_LE }, 8530 { CELL_ASM_BOD_FIFO_6_TMf, 2, 12, SOCF_LE }, 8531 { CELL_ASM_BOD_FIFO_7_TMf, 2, 10, SOCF_LE }, 8532 { MIB_RSC_DATA_HI_TMf, 2, 8, SOCF_LE }, 8533 { MIB_RSC_DATA_LO_TMf, 2, 6, SOCF_LE }, 8534 { MIB_TSC_DATA_HI_TMf, 2, 4, SOCF_LE }, 8535 { MIB_TSC_DATA_LO_TMf, 2, 2, SOCF_LE }, 8536 { TXFIFO_TMf, 2, 0, SOCF_LE } 8537 }; 8538 8539 #endif 8540 #if defined(BCM_88675_A0) 8541 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUSr_fields[] = { 8542 { CURRENTf, 1, 0, SOCF_RO|SOCF_SIG }, 8543 { LOSTf, 1, 1, 0 } 8544 }; 8545 8546 #endif 8547 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 8548 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 8549 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 8550 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 8551 defined(BCM_56560_B0) 8552 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53400_A0r_fields[] = { 8553 { CURRENTf, 1, 0, SOCF_RO }, 8554 { LOSTf, 1, 1, 0 } 8555 }; 8556 8557 #endif 8558 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8559 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8560 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM53570_A0r_fields[] = { 8561 { PLL0_CURRENTf, 1, 0, SOCF_RO }, 8562 { PLL0_LOSTf, 1, 1, 0 }, 8563 { PLL1_CURRENTf, 1, 2, SOCF_RO }, 8564 { PLL1_LOSTf, 1, 3, 0 } 8565 }; 8566 8567 #endif 8568 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 8569 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM56850_A0r_fields[] = { 8570 { CURRENTf, 1, 0, SOCF_RO }, 8571 { LOSTf, 1, 1, 0 } 8572 }; 8573 8574 #endif 8575 #if defined(BCM_56860_A0) 8576 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM56860_A0r_fields[] = { 8577 { CURRENTf, 1, 0, SOCF_RO|SOCF_RES }, 8578 { LOSTf, 1, 1, SOCF_RES } 8579 }; 8580 8581 #endif 8582 #if defined(BCM_88270_A0) 8583 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88270_A0r_fields[] = { 8584 { CURRENTf, 1, 0, SOCF_RO|SOCF_SIG }, 8585 { LOSTf, 1, 1, 0 } 8586 }; 8587 8588 #endif 8589 #if defined(BCM_88375_A0) 8590 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88375_A0r_fields[] = { 8591 { CURRENTf, 1, 0, SOCF_RO|SOCF_SIG }, 8592 { LOSTf, 1, 1, 0 } 8593 }; 8594 8595 #endif 8596 #if defined(BCM_88375_B0) 8597 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88375_B0r_fields[] = { 8598 { CURRENTf, 1, 0, SOCF_RO|SOCF_SIG }, 8599 { LOSTf, 1, 1, 0 } 8600 }; 8601 8602 #endif 8603 #if defined(BCM_88470_A0) 8604 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88470_A0r_fields[] = { 8605 { CURRENTf, 1, 0, SOCF_RO|SOCF_SIG }, 8606 { LOSTf, 1, 1, 0 } 8607 }; 8608 8609 #endif 8610 #if defined(BCM_88470_B0) 8611 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88470_B0r_fields[] = { 8612 { CURRENTf, 1, 0, SOCF_RO|SOCF_SIG }, 8613 { LOSTf, 1, 1, 0 } 8614 }; 8615 8616 #endif 8617 #if defined(BCM_88675_B0) 8618 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88675_B0r_fields[] = { 8619 { CURRENTf, 1, 0, SOCF_RO|SOCF_SIG }, 8620 { LOSTf, 1, 1, 0 } 8621 }; 8622 8623 #endif 8624 #if defined(BCM_88680_A0) 8625 soc_field_info_t soc_XLPORT_TSC_PLL_LOCK_STATUS_BCM88680_A0r_fields[] = { 8626 { CURRENTf, 1, 0, SOCF_RO|SOCF_SIG }, 8627 { LOSTf, 1, 1, 0 } 8628 }; 8629 8630 #endif 8631 #if defined(BCM_88675_A0) 8632 soc_field_info_t soc_XLPORT_TS_TIMER_31_0_REGr_fields[] = { 8633 { TS_TIMER_31_0_VALUEf, 32, 0, SOCF_LE } 8634 }; 8635 8636 #endif 8637 #if defined(BCM_88270_A0) 8638 soc_field_info_t soc_XLPORT_TS_TIMER_31_0_REG_BCM88270_A0r_fields[] = { 8639 { TS_TIMER_31_0_VALUEf, 32, 0, SOCF_LE } 8640 }; 8641 8642 #endif 8643 #if defined(BCM_88375_A0) 8644 soc_field_info_t soc_XLPORT_TS_TIMER_31_0_REG_BCM88375_A0r_fields[] = { 8645 { TS_TIMER_31_0_VALUEf, 32, 0, SOCF_LE } 8646 }; 8647 8648 #endif 8649 #if defined(BCM_88375_B0) 8650 soc_field_info_t soc_XLPORT_TS_TIMER_31_0_REG_BCM88375_B0r_fields[] = { 8651 { TS_TIMER_31_0_VALUEf, 32, 0, SOCF_LE } 8652 }; 8653 8654 #endif 8655 #if defined(BCM_88470_A0) 8656 soc_field_info_t soc_XLPORT_TS_TIMER_31_0_REG_BCM88470_A0r_fields[] = { 8657 { TS_TIMER_31_0_VALUEf, 32, 0, SOCF_LE } 8658 }; 8659 8660 #endif 8661 #if defined(BCM_88470_B0) 8662 soc_field_info_t soc_XLPORT_TS_TIMER_31_0_REG_BCM88470_B0r_fields[] = { 8663 { TS_TIMER_31_0_VALUEf, 32, 0, SOCF_LE } 8664 }; 8665 8666 #endif 8667 #if defined(BCM_88675_B0) 8668 soc_field_info_t soc_XLPORT_TS_TIMER_31_0_REG_BCM88675_B0r_fields[] = { 8669 { TS_TIMER_31_0_VALUEf, 32, 0, SOCF_LE } 8670 }; 8671 8672 #endif 8673 #if defined(BCM_88680_A0) 8674 soc_field_info_t soc_XLPORT_TS_TIMER_31_0_REG_BCM88680_A0r_fields[] = { 8675 { TS_TIMER_31_0_VALUEf, 32, 0, SOCF_LE } 8676 }; 8677 8678 #endif 8679 #if defined(BCM_88675_A0) 8680 soc_field_info_t soc_XLPORT_TS_TIMER_47_32_REGr_fields[] = { 8681 { TS_TIMER_47_32_VALUEf, 16, 0, SOCF_LE } 8682 }; 8683 8684 #endif 8685 #if defined(BCM_88270_A0) 8686 soc_field_info_t soc_XLPORT_TS_TIMER_47_32_REG_BCM88270_A0r_fields[] = { 8687 { TS_TIMER_47_32_VALUEf, 16, 0, SOCF_LE } 8688 }; 8689 8690 #endif 8691 #if defined(BCM_88375_A0) 8692 soc_field_info_t soc_XLPORT_TS_TIMER_47_32_REG_BCM88375_A0r_fields[] = { 8693 { TS_TIMER_47_32_VALUEf, 16, 0, SOCF_LE } 8694 }; 8695 8696 #endif 8697 #if defined(BCM_88375_B0) 8698 soc_field_info_t soc_XLPORT_TS_TIMER_47_32_REG_BCM88375_B0r_fields[] = { 8699 { TS_TIMER_47_32_VALUEf, 16, 0, SOCF_LE } 8700 }; 8701 8702 #endif 8703 #if defined(BCM_88470_A0) 8704 soc_field_info_t soc_XLPORT_TS_TIMER_47_32_REG_BCM88470_A0r_fields[] = { 8705 { TS_TIMER_47_32_VALUEf, 16, 0, SOCF_LE } 8706 }; 8707 8708 #endif 8709 #if defined(BCM_88470_B0) 8710 soc_field_info_t soc_XLPORT_TS_TIMER_47_32_REG_BCM88470_B0r_fields[] = { 8711 { TS_TIMER_47_32_VALUEf, 16, 0, SOCF_LE } 8712 }; 8713 8714 #endif 8715 #if defined(BCM_88675_B0) 8716 soc_field_info_t soc_XLPORT_TS_TIMER_47_32_REG_BCM88675_B0r_fields[] = { 8717 { TS_TIMER_47_32_VALUEf, 16, 0, SOCF_LE } 8718 }; 8719 8720 #endif 8721 #if defined(BCM_88680_A0) 8722 soc_field_info_t soc_XLPORT_TS_TIMER_47_32_REG_BCM88680_A0r_fields[] = { 8723 { TS_TIMER_47_32_VALUEf, 16, 0, SOCF_LE } 8724 }; 8725 8726 #endif 8727 #if defined(BCM_56150_A0) 8728 soc_field_info_t soc_XLPORT_TXFIFO0_ECC_STATUSr_fields[] = { 8729 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 8730 { ECC_ERRf, 1, 0, 0 }, 8731 { ENTRY_IDXf, 4, 3, SOCF_LE }, 8732 { MULTIPLE_ERRf, 1, 1, 0 } 8733 }; 8734 8735 #endif 8736 #if defined(BCM_56150_A0) 8737 soc_field_info_t soc_XLPORT_TXFIFO_CTRLr_fields[] = { 8738 { CORE_CLR_COUNTf, 1, 0, SOCF_RES }, 8739 { DELAY_PKTf, 2, 2, SOCF_LE|SOCF_RES }, 8740 { MAC_CLR_COUNTf, 1, 1, SOCF_RES } 8741 }; 8742 8743 #endif 8744 #if defined(BCM_56150_A0) 8745 soc_field_info_t soc_XLPORT_TXFIFO_OVERFLOWr_fields[] = { 8746 { TXFIFO0f, 1, 0, SOCF_RO }, 8747 { TXFIFO1f, 1, 1, SOCF_RO }, 8748 { TXFIFO2f, 1, 2, SOCF_RO }, 8749 { TXFIFO3f, 1, 3, SOCF_RO } 8750 }; 8751 8752 #endif 8753 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 8754 soc_field_info_t soc_XLPORT_TXPI_CSR_CTRL1r_fields[] = { 8755 { TXPI_CSR_CTRL_SDM_TYPEf, 2, 0, SOCF_LE }, 8756 { TXPI_CSR_CTRL_SWAP_TX_PIf, 2, 1, SOCF_LE } 8757 }; 8758 8759 #endif 8760 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8761 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8762 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_ENr_fields[] = { 8763 { TXPI_CSR_OVER_EN_0f, 1, 0, 0 }, 8764 { TXPI_CSR_OVER_EN_1f, 1, 1, 0 }, 8765 { TXPI_CSR_OVER_EN_2f, 1, 2, 0 }, 8766 { TXPI_CSR_OVER_EN_3f, 1, 3, 0 } 8767 }; 8768 8769 #endif 8770 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8771 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8772 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_VAL_0_HIGHr_fields[] = { 8773 { TXPI_CSR_OVER_VAL_0_HIGHf, 16, 0, SOCF_LE } 8774 }; 8775 8776 #endif 8777 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8778 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8779 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_VAL_0_LOWr_fields[] = { 8780 { TXPI_CSR_OVER_VAL_0_LOWf, 32, 0, SOCF_LE } 8781 }; 8782 8783 #endif 8784 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8785 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8786 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_VAL_1_HIGHr_fields[] = { 8787 { TXPI_CSR_OVER_VAL_1_HIGHf, 16, 0, SOCF_LE } 8788 }; 8789 8790 #endif 8791 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8792 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8793 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_VAL_1_LOWr_fields[] = { 8794 { TXPI_CSR_OVER_VAL_1_LOWf, 32, 0, SOCF_LE } 8795 }; 8796 8797 #endif 8798 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8799 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8800 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_VAL_2_HIGHr_fields[] = { 8801 { TXPI_CSR_OVER_VAL_2_HIGHf, 16, 0, SOCF_LE } 8802 }; 8803 8804 #endif 8805 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8806 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8807 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_VAL_2_LOWr_fields[] = { 8808 { TXPI_CSR_OVER_VAL_2_LOWf, 32, 0, SOCF_LE } 8809 }; 8810 8811 #endif 8812 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8813 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8814 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_VAL_3_HIGHr_fields[] = { 8815 { TXPI_CSR_OVER_VAL_3_HIGHf, 16, 0, SOCF_LE } 8816 }; 8817 8818 #endif 8819 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8820 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8821 soc_field_info_t soc_XLPORT_TXPI_CSR_OVER_VAL_3_LOWr_fields[] = { 8822 { TXPI_CSR_OVER_VAL_3_LOWf, 32, 0, SOCF_LE } 8823 }; 8824 8825 #endif 8826 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8827 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8828 soc_field_info_t soc_XLPORT_TXPI_DATA_OUT_STS_0_HIGHr_fields[] = { 8829 { TXPI_DATA_OUT_STS_0_HIGHf, 16, 0, SOCF_LE|SOCF_RO } 8830 }; 8831 8832 #endif 8833 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8834 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8835 soc_field_info_t soc_XLPORT_TXPI_DATA_OUT_STS_0_LOWr_fields[] = { 8836 { TXPI_DATA_OUT_STS_0_LOWf, 32, 0, SOCF_LE|SOCF_RO } 8837 }; 8838 8839 #endif 8840 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8841 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8842 soc_field_info_t soc_XLPORT_TXPI_DATA_OUT_STS_1_HIGHr_fields[] = { 8843 { TXPI_DATA_OUT_STS_1_HIGHf, 16, 0, SOCF_LE|SOCF_RO } 8844 }; 8845 8846 #endif 8847 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8848 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8849 soc_field_info_t soc_XLPORT_TXPI_DATA_OUT_STS_1_LOWr_fields[] = { 8850 { TXPI_DATA_OUT_STS_1_LOWf, 32, 0, SOCF_LE|SOCF_RO } 8851 }; 8852 8853 #endif 8854 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8855 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8856 soc_field_info_t soc_XLPORT_TXPI_DATA_OUT_STS_2_HIGHr_fields[] = { 8857 { TXPI_DATA_OUT_STS_2_HIGHf, 16, 0, SOCF_LE|SOCF_RO } 8858 }; 8859 8860 #endif 8861 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8862 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8863 soc_field_info_t soc_XLPORT_TXPI_DATA_OUT_STS_2_LOWr_fields[] = { 8864 { TXPI_DATA_OUT_STS_2_LOWf, 32, 0, SOCF_LE|SOCF_RO } 8865 }; 8866 8867 #endif 8868 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8869 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8870 soc_field_info_t soc_XLPORT_TXPI_DATA_OUT_STS_3_HIGHr_fields[] = { 8871 { TXPI_DATA_OUT_STS_3_HIGHf, 16, 0, SOCF_LE|SOCF_RO } 8872 }; 8873 8874 #endif 8875 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8876 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8877 soc_field_info_t soc_XLPORT_TXPI_DATA_OUT_STS_3_LOWr_fields[] = { 8878 { TXPI_DATA_OUT_STS_3_LOWf, 32, 0, SOCF_LE|SOCF_RO } 8879 }; 8880 8881 #endif 8882 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8883 defined(BCM_56670_A0) || defined(BCM_56670_B0) 8884 soc_field_info_t soc_XLPORT_TXPI_LANE_SELECTIONr_fields[] = { 8885 { TXPI_LANE_SELECTION_0f, 2, 0, SOCF_LE }, 8886 { TXPI_LANE_SELECTION_1f, 2, 2, SOCF_LE }, 8887 { TXPI_LANE_SELECTION_2f, 2, 4, SOCF_LE }, 8888 { TXPI_LANE_SELECTION_3f, 2, 6, SOCF_LE } 8889 }; 8890 8891 #endif 8892 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 8893 defined(BCM_88732_A0) 8894 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRLr_fields[] = { 8895 { ACCESS_MODEf, 1, 0, 0 }, 8896 { CLK_DIV_RATIOf, 2, 8, SOCF_LE }, 8897 { RD_MARGINf, 2, 10, SOCF_LE }, 8898 { UCMEM_CTRL_RESERVEDf, 7, 1, SOCF_LE|SOCF_RES }, 8899 { WR_DATA_MARGINf, 2, 14, SOCF_LE }, 8900 { WR_HOLD_MARGINf, 2, 16, SOCF_LE }, 8901 { WR_SETUP_MARGINf, 2, 12, SOCF_LE } 8902 }; 8903 8904 #endif 8905 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \ 8906 defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 8907 defined(BCM_56160_A0) || defined(BCM_56260_A0) || \ 8908 defined(BCM_56260_B0) || defined(BCM_56270_A0) || \ 8909 defined(BCM_56370_A0) || defined(BCM_56560_A0) || \ 8910 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 8911 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 8912 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 8913 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 8914 defined(BCM_56980_A0) || defined(BCM_56980_B0) 8915 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM53400_A0r_fields[] = { 8916 { ACCESS_MODEf, 1, 0, 0 }, 8917 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8918 }; 8919 8920 #endif 8921 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 8922 defined(BCM_56860_A0) 8923 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM56850_A0r_fields[] = { 8924 { ACCESS_MODEf, 1, 0, 0 }, 8925 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8926 }; 8927 8928 #endif 8929 #if defined(BCM_88270_A0) 8930 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM88270_A0r_fields[] = { 8931 { ACCESS_MODEf, 1, 0, 0 }, 8932 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8933 }; 8934 8935 #endif 8936 #if defined(BCM_88375_A0) 8937 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM88375_A0r_fields[] = { 8938 { ACCESS_MODEf, 1, 0, 0 }, 8939 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8940 }; 8941 8942 #endif 8943 #if defined(BCM_88375_B0) 8944 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM88375_B0r_fields[] = { 8945 { ACCESS_MODEf, 1, 0, 0 }, 8946 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8947 }; 8948 8949 #endif 8950 #if defined(BCM_88470_A0) 8951 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM88470_A0r_fields[] = { 8952 { ACCESS_MODEf, 1, 0, 0 }, 8953 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8954 }; 8955 8956 #endif 8957 #if defined(BCM_88470_B0) 8958 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM88470_B0r_fields[] = { 8959 { ACCESS_MODEf, 1, 0, 0 }, 8960 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8961 }; 8962 8963 #endif 8964 #if defined(BCM_88675_A0) 8965 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM88675_A0r_fields[] = { 8966 { ACCESS_MODEf, 1, 0, 0 }, 8967 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8968 }; 8969 8970 #endif 8971 #if defined(BCM_88675_B0) 8972 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM88675_B0r_fields[] = { 8973 { ACCESS_MODEf, 1, 0, 0 }, 8974 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8975 }; 8976 8977 #endif 8978 #if defined(BCM_88680_A0) 8979 soc_field_info_t soc_XLPORT_WC_UCMEM_CTRL_BCM88680_A0r_fields[] = { 8980 { ACCESS_MODEf, 1, 0, 0 }, 8981 { RSVD3_1f, 3, 1, SOCF_LE|SOCF_RES } 8982 }; 8983 8984 #endif 8985 #if defined(BCM_88675_A0) 8986 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REGr_fields[] = { 8987 { IDDQf, 1, 4, 0 }, 8988 { PWRDWNf, 1, 3, 0 }, 8989 { REFIN_ENf, 1, 2, 0 }, 8990 { REFOUT_ENf, 1, 1, 0 }, 8991 { RSTB_HWf, 1, 0, 0 } 8992 }; 8993 8994 #endif 8995 #if defined(BCM_53400_A0) || defined(BCM_56160_A0) || \ 8996 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 8997 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 8998 defined(BCM_56560_B0) || defined(BCM_56960_A0) || \ 8999 defined(BCM_56965_A0) 9000 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM53400_A0r_fields[] = { 9001 { IDDQf, 1, 4, SOCF_RES }, 9002 { PWRDWNf, 1, 3, SOCF_RES }, 9003 { REFIN_ENf, 1, 2, SOCF_RES }, 9004 { REFOUT_ENf, 1, 1, SOCF_RES }, 9005 { RSTB_HWf, 1, 0, SOCF_RES } 9006 }; 9007 9008 #endif 9009 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 9010 defined(BCM_56670_A0) || defined(BCM_56670_B0) 9011 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM53570_A0r_fields[] = { 9012 { IDDQf, 1, 4, SOCF_RES }, 9013 { PLL0_LC_REFSELf, 1, 13, SOCF_RES }, 9014 { PLL0_REFIN_ENf, 1, 12, SOCF_RES }, 9015 { PLL0_REFOUT_ENf, 1, 11, SOCF_RES }, 9016 { PLL1_LC_REFSELf, 1, 16, SOCF_RES }, 9017 { PLL1_REFIN_ENf, 1, 15, SOCF_RES }, 9018 { PLL1_REFOUT_ENf, 1, 14, SOCF_RES }, 9019 { PWRDWNf, 1, 3, SOCF_RES }, 9020 { PWRDWN_CMLf, 1, 5, SOCF_RES }, 9021 { PWRDWN_CML_LCf, 1, 6, SOCF_RES }, 9022 { REFCMOSf, 1, 7, SOCF_RES }, 9023 { REFIN_ENf, 1, 2, SOCF_RES }, 9024 { REFOUT_ENf, 1, 1, SOCF_RES }, 9025 { REFSELf, 3, 8, SOCF_LE|SOCF_RES }, 9026 { RSTB_HWf, 1, 0, SOCF_RES } 9027 }; 9028 9029 #endif 9030 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) 9031 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM56850_A0r_fields[] = { 9032 { IDDQf, 1, 8, SOCF_RES }, 9033 { PLLBYPf, 1, 0, 0 }, 9034 { PWRDWNf, 1, 6, SOCF_RES }, 9035 { REFIN_ENf, 1, 5, SOCF_RES }, 9036 { REFOUT_ENf, 1, 4, SOCF_RES }, 9037 { RSTB_HWf, 1, 2, SOCF_RES }, 9038 { RSTB_PLLf, 1, 1, SOCF_RES }, 9039 { RSTB_REFCLKf, 1, 3, SOCF_RES }, 9040 { TSCCLK_ENf, 1, 7, SOCF_RES } 9041 }; 9042 9043 #endif 9044 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 9045 defined(BCM_56970_A0) 9046 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM56970_A0r_fields[] = { 9047 { IDDQf, 1, 4, SOCF_RES }, 9048 { PWRDWNf, 1, 3, SOCF_RES }, 9049 { PWRDWN_CMLf, 1, 5, SOCF_RES }, 9050 { PWRDWN_CML_LCf, 1, 6, SOCF_RES }, 9051 { REFCMOSf, 1, 7, SOCF_RES }, 9052 { REFIN_ENf, 1, 2, SOCF_RES }, 9053 { REFOUT_ENf, 1, 1, SOCF_RES }, 9054 { REFSELf, 3, 8, SOCF_LE|SOCF_RES }, 9055 { RSTB_HWf, 1, 0, SOCF_RES } 9056 }; 9057 9058 #endif 9059 #if defined(BCM_56370_A0) || defined(BCM_56980_A0) || \ 9060 defined(BCM_56980_B0) 9061 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM56980_A0r_fields[] = { 9062 { IDDQf, 1, 4, SOCF_RES }, 9063 { PWRDWNf, 1, 3, SOCF_RES }, 9064 { PWRDWN_CMLf, 1, 5, SOCF_RES }, 9065 { PWRDWN_CML_LCf, 1, 6, SOCF_RES }, 9066 { REFCMOSf, 1, 7, SOCF_RES }, 9067 { REFIN_ENf, 1, 2, SOCF_RES }, 9068 { REFOUT_ENf, 1, 1, SOCF_RES }, 9069 { REFSELf, 3, 8, SOCF_LE|SOCF_RES }, 9070 { RSTB_HWf, 1, 0, SOCF_RES } 9071 }; 9072 9073 #endif 9074 #if defined(BCM_88270_A0) 9075 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM88270_A0r_fields[] = { 9076 { IDDQf, 1, 4, 0 }, 9077 { PWRDWNf, 1, 3, 0 }, 9078 { REFIN_ENf, 1, 2, 0 }, 9079 { REFOUT_ENf, 1, 1, 0 }, 9080 { RSTB_HWf, 1, 0, 0 } 9081 }; 9082 9083 #endif 9084 #if defined(BCM_88375_A0) 9085 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM88375_A0r_fields[] = { 9086 { IDDQf, 1, 4, 0 }, 9087 { PWRDWNf, 1, 3, 0 }, 9088 { REFIN_ENf, 1, 2, 0 }, 9089 { REFOUT_ENf, 1, 1, 0 }, 9090 { RSTB_HWf, 1, 0, 0 } 9091 }; 9092 9093 #endif 9094 #if defined(BCM_88375_B0) 9095 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM88375_B0r_fields[] = { 9096 { IDDQf, 1, 4, 0 }, 9097 { PWRDWNf, 1, 3, 0 }, 9098 { REFIN_ENf, 1, 2, 0 }, 9099 { REFOUT_ENf, 1, 1, 0 }, 9100 { RSTB_HWf, 1, 0, 0 } 9101 }; 9102 9103 #endif 9104 #if defined(BCM_88470_A0) 9105 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM88470_A0r_fields[] = { 9106 { IDDQf, 1, 4, 0 }, 9107 { PWRDWNf, 1, 3, 0 }, 9108 { REFIN_ENf, 1, 2, 0 }, 9109 { REFOUT_ENf, 1, 1, 0 }, 9110 { RSTB_HWf, 1, 0, 0 } 9111 }; 9112 9113 #endif 9114 #if defined(BCM_88470_B0) 9115 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM88470_B0r_fields[] = { 9116 { IDDQf, 1, 4, 0 }, 9117 { PWRDWNf, 1, 3, 0 }, 9118 { REFIN_ENf, 1, 2, 0 }, 9119 { REFOUT_ENf, 1, 1, 0 }, 9120 { RSTB_HWf, 1, 0, 0 } 9121 }; 9122 9123 #endif 9124 #if defined(BCM_88675_B0) 9125 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM88675_B0r_fields[] = { 9126 { IDDQf, 1, 4, 0 }, 9127 { PWRDWNf, 1, 3, 0 }, 9128 { REFIN_ENf, 1, 2, 0 }, 9129 { REFOUT_ENf, 1, 1, 0 }, 9130 { RSTB_HWf, 1, 0, 0 } 9131 }; 9132 9133 #endif 9134 #if defined(BCM_88680_A0) 9135 soc_field_info_t soc_XLPORT_XGXS0_CTRL_REG_BCM88680_A0r_fields[] = { 9136 { IDDQf, 1, 4, 0 }, 9137 { PWRDWNf, 1, 3, 0 }, 9138 { REFIN_ENf, 1, 2, 0 }, 9139 { REFOUT_ENf, 1, 1, 0 }, 9140 { RSTB_HWf, 1, 0, 0 } 9141 }; 9142 9143 #endif 9144 #if defined(BCM_88675_A0) 9145 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REGr_fields[] = { 9146 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9147 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9148 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9149 }; 9150 9151 #endif 9152 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 9153 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 9154 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 9155 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 9156 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 9157 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 9158 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 9159 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 9160 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 9161 defined(BCM_56980_B0) 9162 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM53400_A0r_fields[] = { 9163 { LINK_STATUSf, 1, 0, SOCF_RO }, 9164 { PMD_LOCKf, 1, 2, SOCF_RO }, 9165 { SIG_DETf, 1, 1, SOCF_RO } 9166 }; 9167 9168 #endif 9169 #if defined(BCM_56150_A0) || defined(BCM_56850_A0) || \ 9170 defined(BCM_56860_A0) 9171 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM56850_A0r_fields[] = { 9172 { LINK_STATUSf, 1, 0, SOCF_RO }, 9173 { PMD_LOCKf, 1, 2, SOCF_RO }, 9174 { SIG_DETf, 1, 1, SOCF_RO } 9175 }; 9176 9177 #endif 9178 #if defined(BCM_88270_A0) 9179 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88270_A0r_fields[] = { 9180 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9181 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9182 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9183 }; 9184 9185 #endif 9186 #if defined(BCM_88375_A0) 9187 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88375_A0r_fields[] = { 9188 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9189 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9190 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9191 }; 9192 9193 #endif 9194 #if defined(BCM_88375_B0) 9195 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88375_B0r_fields[] = { 9196 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9197 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9198 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9199 }; 9200 9201 #endif 9202 #if defined(BCM_88470_A0) 9203 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88470_A0r_fields[] = { 9204 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9205 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9206 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9207 }; 9208 9209 #endif 9210 #if defined(BCM_88470_B0) 9211 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88470_B0r_fields[] = { 9212 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9213 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9214 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9215 }; 9216 9217 #endif 9218 #if defined(BCM_88675_B0) 9219 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88675_B0r_fields[] = { 9220 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9221 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9222 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9223 }; 9224 9225 #endif 9226 #if defined(BCM_88680_A0) 9227 soc_field_info_t soc_XLPORT_XGXS0_LN0_STATUS0_REG_BCM88680_A0r_fields[] = { 9228 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9229 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9230 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9231 }; 9232 9233 #endif 9234 #if defined(BCM_88675_A0) 9235 soc_field_info_t soc_XLPORT_XGXS0_LN1_STATUS0_REGr_fields[] = { 9236 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9237 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9238 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9239 }; 9240 9241 #endif 9242 #if defined(BCM_88270_A0) 9243 soc_field_info_t soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88270_A0r_fields[] = { 9244 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9245 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9246 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9247 }; 9248 9249 #endif 9250 #if defined(BCM_88375_A0) 9251 soc_field_info_t soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88375_A0r_fields[] = { 9252 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9253 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9254 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9255 }; 9256 9257 #endif 9258 #if defined(BCM_88375_B0) 9259 soc_field_info_t soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88375_B0r_fields[] = { 9260 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9261 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9262 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9263 }; 9264 9265 #endif 9266 #if defined(BCM_88470_A0) 9267 soc_field_info_t soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88470_A0r_fields[] = { 9268 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9269 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9270 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9271 }; 9272 9273 #endif 9274 #if defined(BCM_88470_B0) 9275 soc_field_info_t soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88470_B0r_fields[] = { 9276 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9277 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9278 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9279 }; 9280 9281 #endif 9282 #if defined(BCM_88675_B0) 9283 soc_field_info_t soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88675_B0r_fields[] = { 9284 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9285 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9286 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9287 }; 9288 9289 #endif 9290 #if defined(BCM_88680_A0) 9291 soc_field_info_t soc_XLPORT_XGXS0_LN1_STATUS0_REG_BCM88680_A0r_fields[] = { 9292 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9293 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9294 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9295 }; 9296 9297 #endif 9298 #if defined(BCM_88675_A0) 9299 soc_field_info_t soc_XLPORT_XGXS0_LN2_STATUS0_REGr_fields[] = { 9300 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9301 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9302 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9303 }; 9304 9305 #endif 9306 #if defined(BCM_88270_A0) 9307 soc_field_info_t soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88270_A0r_fields[] = { 9308 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9309 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9310 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9311 }; 9312 9313 #endif 9314 #if defined(BCM_88375_A0) 9315 soc_field_info_t soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88375_A0r_fields[] = { 9316 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9317 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9318 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9319 }; 9320 9321 #endif 9322 #if defined(BCM_88375_B0) 9323 soc_field_info_t soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88375_B0r_fields[] = { 9324 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9325 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9326 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9327 }; 9328 9329 #endif 9330 #if defined(BCM_88470_A0) 9331 soc_field_info_t soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88470_A0r_fields[] = { 9332 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9333 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9334 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9335 }; 9336 9337 #endif 9338 #if defined(BCM_88470_B0) 9339 soc_field_info_t soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88470_B0r_fields[] = { 9340 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9341 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9342 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9343 }; 9344 9345 #endif 9346 #if defined(BCM_88675_B0) 9347 soc_field_info_t soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88675_B0r_fields[] = { 9348 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9349 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9350 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9351 }; 9352 9353 #endif 9354 #if defined(BCM_88680_A0) 9355 soc_field_info_t soc_XLPORT_XGXS0_LN2_STATUS0_REG_BCM88680_A0r_fields[] = { 9356 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9357 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9358 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9359 }; 9360 9361 #endif 9362 #if defined(BCM_88675_A0) 9363 soc_field_info_t soc_XLPORT_XGXS0_LN3_STATUS0_REGr_fields[] = { 9364 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9365 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9366 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9367 }; 9368 9369 #endif 9370 #if defined(BCM_88270_A0) 9371 soc_field_info_t soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88270_A0r_fields[] = { 9372 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9373 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9374 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9375 }; 9376 9377 #endif 9378 #if defined(BCM_88375_A0) 9379 soc_field_info_t soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88375_A0r_fields[] = { 9380 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9381 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9382 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9383 }; 9384 9385 #endif 9386 #if defined(BCM_88375_B0) 9387 soc_field_info_t soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88375_B0r_fields[] = { 9388 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9389 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9390 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9391 }; 9392 9393 #endif 9394 #if defined(BCM_88470_A0) 9395 soc_field_info_t soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88470_A0r_fields[] = { 9396 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9397 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9398 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9399 }; 9400 9401 #endif 9402 #if defined(BCM_88470_B0) 9403 soc_field_info_t soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88470_B0r_fields[] = { 9404 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9405 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9406 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9407 }; 9408 9409 #endif 9410 #if defined(BCM_88675_B0) 9411 soc_field_info_t soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88675_B0r_fields[] = { 9412 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9413 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9414 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9415 }; 9416 9417 #endif 9418 #if defined(BCM_88680_A0) 9419 soc_field_info_t soc_XLPORT_XGXS0_LN3_STATUS0_REG_BCM88680_A0r_fields[] = { 9420 { LINK_STATUSf, 1, 0, SOCF_RO|SOCF_SIG }, 9421 { PMD_LOCKf, 1, 2, SOCF_RO|SOCF_SIG }, 9422 { SIG_DETf, 1, 1, SOCF_RO|SOCF_SIG } 9423 }; 9424 9425 #endif 9426 #if defined(BCM_56840_A0) || defined(BCM_88732_A0) 9427 soc_field_info_t soc_XLPORT_XGXS0_STATUS0_REGr_fields[] = { 9428 { RX0_ACTf, 1, 7, SOCF_RO }, 9429 { TX0_ACTf, 1, 8, SOCF_RO }, 9430 { XGXS0_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 9431 { XGXS0_DUPLEX_STATUSf, 1, 1, SOCF_RO }, 9432 { XGXS0_FIBER_RXACTf, 1, 2, SOCF_RO }, 9433 { XGXS0_FIBER_TXACTf, 1, 3, SOCF_RO }, 9434 { XGXS0_LINKf, 1, 9, SOCF_RO }, 9435 { XGXS0_LINK10Gf, 1, 10, SOCF_RO }, 9436 { XGXS0_LINK_STATUSf, 1, 4, SOCF_RO }, 9437 { XGXS0_SGMIIf, 1, 5, SOCF_RO }, 9438 { XGXS0_SPEED15750_HI_DXGXSf, 1, 15, SOCF_RO }, 9439 { XGXS0_SPEED20G_DXGXSf, 1, 16, SOCF_RO }, 9440 { XGXS0_SPEED20G_HI_DXGXSf, 1, 17, SOCF_RO }, 9441 { XGXS0_SPEED40Gf, 1, 18, SOCF_RO }, 9442 { XGXS0_SPEED40G_CR4f, 1, 14, SOCF_RO }, 9443 { XGXS0_SPEED40G_KR4f, 1, 13, SOCF_RO }, 9444 { XGXS0_SPEED_R2_12000f, 1, 11, SOCF_RO }, 9445 { XGXS0_SPEED_X2_10000f, 1, 12, SOCF_RO }, 9446 { XGXS0_TICKf, 1, 6, SOCF_RO } 9447 }; 9448 9449 #endif 9450 #if defined(BCM_56840_B0) 9451 soc_field_info_t soc_XLPORT_XGXS0_STATUS0_REG_BCM56840_B0r_fields[] = { 9452 { RX0_ACTf, 1, 7, SOCF_RO }, 9453 { TX0_ACTf, 1, 8, SOCF_RO }, 9454 { XGXS0_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 9455 { XGXS0_DUPLEX_STATUSf, 1, 1, SOCF_RO }, 9456 { XGXS0_FIBER_RXACTf, 1, 2, SOCF_RO }, 9457 { XGXS0_FIBER_TXACTf, 1, 3, SOCF_RO }, 9458 { XGXS0_LINKf, 1, 9, SOCF_RO }, 9459 { XGXS0_LINK10Gf, 1, 10, SOCF_RO }, 9460 { XGXS0_LINK_STATUSf, 1, 4, SOCF_RO }, 9461 { XGXS0_RX_TICKf, 1, 19, SOCF_RO }, 9462 { XGXS0_SGMIIf, 1, 5, SOCF_RO }, 9463 { XGXS0_SPEED10G_CX1f, 1, 20, SOCF_RO }, 9464 { XGXS0_SPEED10G_ERf, 1, 24, SOCF_RO }, 9465 { XGXS0_SPEED10G_LRf, 1, 25, SOCF_RO }, 9466 { XGXS0_SPEED10G_LRMf, 1, 27, SOCF_RO }, 9467 { XGXS0_SPEED10G_SRf, 1, 26, SOCF_RO }, 9468 { XGXS0_SPEED15750_HI_DXGXSf, 1, 15, SOCF_RO }, 9469 { XGXS0_SPEED1G_CX1f, 1, 21, SOCF_RO }, 9470 { XGXS0_SPEED20G_CR2f, 1, 29, SOCF_RO }, 9471 { XGXS0_SPEED20G_DXGXSf, 1, 16, SOCF_RO }, 9472 { XGXS0_SPEED20G_HI_DXGXSf, 1, 17, SOCF_RO }, 9473 { XGXS0_SPEED20G_KR2f, 1, 28, SOCF_RO }, 9474 { XGXS0_SPEED40Gf, 1, 18, SOCF_RO }, 9475 { XGXS0_SPEED40G_CR4f, 1, 14, SOCF_RO }, 9476 { XGXS0_SPEED40G_KR4f, 1, 13, SOCF_RO }, 9477 { XGXS0_SPEED40G_LR4f, 1, 23, SOCF_RO }, 9478 { XGXS0_SPEED40G_SR4f, 1, 22, SOCF_RO }, 9479 { XGXS0_SPEED_R2_12000f, 1, 11, SOCF_RO }, 9480 { XGXS0_SPEED_X2_10000f, 1, 12, SOCF_RO }, 9481 { XGXS0_TICKf, 1, 6, SOCF_RO } 9482 }; 9483 9484 #endif 9485 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9486 defined(BCM_88732_A0) 9487 soc_field_info_t soc_XLPORT_XGXS0_STATUS1_REGr_fields[] = { 9488 { XGXS0_SPEED1000f, 1, 2, SOCF_RO }, 9489 { XGXS0_SPEED10000f, 1, 8, SOCF_RO }, 9490 { XGXS0_SPEED10000_CX4f, 1, 9, SOCF_RO }, 9491 { XGXS0_SPEED10000_DXGXSf, 1, 19, SOCF_RO }, 9492 { XGXS0_SPEED10000_HI_DXGXSf, 1, 20, SOCF_RO }, 9493 { XGXS0_SPEED10000_KRf, 1, 25, SOCF_RO }, 9494 { XGXS0_SPEED10000_KX4f, 1, 26, SOCF_RO }, 9495 { XGXS0_SPEED1000_KXf, 1, 27, SOCF_RO }, 9496 { XGXS0_SPEED10500_DXGXSf, 1, 21, SOCF_RO }, 9497 { XGXS0_SPEED10500_HI_DXGXSf, 1, 22, SOCF_RO }, 9498 { XGXS0_SPEED10G_SFIf, 1, 29, SOCF_RO }, 9499 { XGXS0_SPEED10G_SINGLEf, 1, 28, SOCF_RO }, 9500 { XGXS0_SPEED12000f, 1, 10, SOCF_RO }, 9501 { XGXS0_SPEED12500f, 1, 11, SOCF_RO }, 9502 { XGXS0_SPEED12773_DXGXSf, 1, 23, SOCF_RO }, 9503 { XGXS0_SPEED12773_HI_DXGXSf, 1, 24, SOCF_RO }, 9504 { XGXS0_SPEED13000f, 1, 12, SOCF_RO }, 9505 { XGXS0_SPEED15000f, 1, 13, SOCF_RO }, 9506 { XGXS0_SPEED16000f, 1, 14, SOCF_RO }, 9507 { XGXS0_SPEED20000f, 1, 15, SOCF_RO }, 9508 { XGXS0_SPEED21000f, 1, 16, SOCF_RO }, 9509 { XGXS0_SPEED2500f, 1, 3, SOCF_RO }, 9510 { XGXS0_SPEED25455f, 1, 17, SOCF_RO }, 9511 { XGXS0_SPEED31500f, 1, 18, SOCF_RO }, 9512 { XGXS0_SPEED5000f, 1, 4, SOCF_RO }, 9513 { XGXS0_SPEED5000_SINGLEf, 1, 5, SOCF_RO }, 9514 { XGXS0_SPEED6000f, 1, 6, SOCF_RO }, 9515 { XGXS0_SPEED6364_SINGLEf, 1, 7, SOCF_RO }, 9516 { XGXS0_SPEED_10f, 1, 0, SOCF_RO }, 9517 { XGXS0_SPEED_100f, 1, 1, SOCF_RO } 9518 }; 9519 9520 #endif 9521 #if defined(BCM_56840_A0) || defined(BCM_88732_A0) 9522 soc_field_info_t soc_XLPORT_XGXS1_STATUS0_REGr_fields[] = { 9523 { RX1_ACTf, 1, 7, SOCF_RO }, 9524 { TX1_ACTf, 1, 8, SOCF_RO }, 9525 { XGXS1_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 9526 { XGXS1_DUPLEX_STATUSf, 1, 1, SOCF_RO }, 9527 { XGXS1_FIBER_RXACTf, 1, 2, SOCF_RO }, 9528 { XGXS1_FIBER_TXACTf, 1, 3, SOCF_RO }, 9529 { XGXS1_LINKf, 1, 9, SOCF_RO }, 9530 { XGXS1_LINK10Gf, 1, 10, SOCF_RO }, 9531 { XGXS1_LINK_STATUSf, 1, 4, SOCF_RO }, 9532 { XGXS1_SGMIIf, 1, 5, SOCF_RO }, 9533 { XGXS1_SPEED15750_HI_DXGXSf, 1, 15, SOCF_RO }, 9534 { XGXS1_SPEED20G_DXGXSf, 1, 16, SOCF_RO }, 9535 { XGXS1_SPEED20G_HI_DXGXSf, 1, 17, SOCF_RO }, 9536 { XGXS1_SPEED40Gf, 1, 18, SOCF_RO }, 9537 { XGXS1_SPEED40G_CR4f, 1, 14, SOCF_RO }, 9538 { XGXS1_SPEED40G_KR4f, 1, 13, SOCF_RO }, 9539 { XGXS1_SPEED_R2_12000f, 1, 11, SOCF_RO }, 9540 { XGXS1_SPEED_X2_10000f, 1, 12, SOCF_RO }, 9541 { XGXS1_TICKf, 1, 6, SOCF_RO } 9542 }; 9543 9544 #endif 9545 #if defined(BCM_56840_B0) 9546 soc_field_info_t soc_XLPORT_XGXS1_STATUS0_REG_BCM56840_B0r_fields[] = { 9547 { RX1_ACTf, 1, 7, SOCF_RO }, 9548 { TX1_ACTf, 1, 8, SOCF_RO }, 9549 { XGXS1_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 9550 { XGXS1_DUPLEX_STATUSf, 1, 1, SOCF_RO }, 9551 { XGXS1_FIBER_RXACTf, 1, 2, SOCF_RO }, 9552 { XGXS1_FIBER_TXACTf, 1, 3, SOCF_RO }, 9553 { XGXS1_LINKf, 1, 9, SOCF_RO }, 9554 { XGXS1_LINK10Gf, 1, 10, SOCF_RO }, 9555 { XGXS1_LINK_STATUSf, 1, 4, SOCF_RO }, 9556 { XGXS1_RX_TICKf, 1, 19, SOCF_RO }, 9557 { XGXS1_SGMIIf, 1, 5, SOCF_RO }, 9558 { XGXS1_SPEED10G_CX1f, 1, 20, SOCF_RO }, 9559 { XGXS1_SPEED10G_ERf, 1, 24, SOCF_RO }, 9560 { XGXS1_SPEED10G_LRf, 1, 25, SOCF_RO }, 9561 { XGXS1_SPEED10G_LRMf, 1, 27, SOCF_RO }, 9562 { XGXS1_SPEED10G_SRf, 1, 26, SOCF_RO }, 9563 { XGXS1_SPEED15750_HI_DXGXSf, 1, 15, SOCF_RO }, 9564 { XGXS1_SPEED1G_CX1f, 1, 21, SOCF_RO }, 9565 { XGXS1_SPEED20G_CR2f, 1, 29, SOCF_RO }, 9566 { XGXS1_SPEED20G_DXGXSf, 1, 16, SOCF_RO }, 9567 { XGXS1_SPEED20G_HI_DXGXSf, 1, 17, SOCF_RO }, 9568 { XGXS1_SPEED20G_KR2f, 1, 28, SOCF_RO }, 9569 { XGXS1_SPEED40Gf, 1, 18, SOCF_RO }, 9570 { XGXS1_SPEED40G_CR4f, 1, 14, SOCF_RO }, 9571 { XGXS1_SPEED40G_KR4f, 1, 13, SOCF_RO }, 9572 { XGXS1_SPEED40G_LR4f, 1, 23, SOCF_RO }, 9573 { XGXS1_SPEED40G_SR4f, 1, 22, SOCF_RO }, 9574 { XGXS1_SPEED_R2_12000f, 1, 11, SOCF_RO }, 9575 { XGXS1_SPEED_X2_10000f, 1, 12, SOCF_RO }, 9576 { XGXS1_TICKf, 1, 6, SOCF_RO } 9577 }; 9578 9579 #endif 9580 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9581 defined(BCM_88732_A0) 9582 soc_field_info_t soc_XLPORT_XGXS1_STATUS1_REGr_fields[] = { 9583 { XGXS1_SPEED1000f, 1, 2, SOCF_RO }, 9584 { XGXS1_SPEED10000f, 1, 8, SOCF_RO }, 9585 { XGXS1_SPEED10000_CX4f, 1, 9, SOCF_RO }, 9586 { XGXS1_SPEED10000_DXGXSf, 1, 19, SOCF_RO }, 9587 { XGXS1_SPEED10000_HI_DXGXSf, 1, 20, SOCF_RO }, 9588 { XGXS1_SPEED10000_KRf, 1, 25, SOCF_RO }, 9589 { XGXS1_SPEED10000_KX4f, 1, 26, SOCF_RO }, 9590 { XGXS1_SPEED1000_KXf, 1, 27, SOCF_RO }, 9591 { XGXS1_SPEED10500_DXGXSf, 1, 21, SOCF_RO }, 9592 { XGXS1_SPEED10500_HI_DXGXSf, 1, 22, SOCF_RO }, 9593 { XGXS1_SPEED10G_SFIf, 1, 29, SOCF_RO }, 9594 { XGXS1_SPEED10G_SINGLEf, 1, 28, SOCF_RO }, 9595 { XGXS1_SPEED12000f, 1, 10, SOCF_RO }, 9596 { XGXS1_SPEED12500f, 1, 11, SOCF_RO }, 9597 { XGXS1_SPEED12773_DXGXSf, 1, 23, SOCF_RO }, 9598 { XGXS1_SPEED12773_HI_DXGXSf, 1, 24, SOCF_RO }, 9599 { XGXS1_SPEED13000f, 1, 12, SOCF_RO }, 9600 { XGXS1_SPEED15000f, 1, 13, SOCF_RO }, 9601 { XGXS1_SPEED16000f, 1, 14, SOCF_RO }, 9602 { XGXS1_SPEED20000f, 1, 15, SOCF_RO }, 9603 { XGXS1_SPEED21000f, 1, 16, SOCF_RO }, 9604 { XGXS1_SPEED2500f, 1, 3, SOCF_RO }, 9605 { XGXS1_SPEED25455f, 1, 17, SOCF_RO }, 9606 { XGXS1_SPEED31500f, 1, 18, SOCF_RO }, 9607 { XGXS1_SPEED5000f, 1, 4, SOCF_RO }, 9608 { XGXS1_SPEED5000_SINGLEf, 1, 5, SOCF_RO }, 9609 { XGXS1_SPEED6000f, 1, 6, SOCF_RO }, 9610 { XGXS1_SPEED6364_SINGLEf, 1, 7, SOCF_RO }, 9611 { XGXS1_SPEED_10f, 1, 0, SOCF_RO }, 9612 { XGXS1_SPEED_100f, 1, 1, SOCF_RO } 9613 }; 9614 9615 #endif 9616 #if defined(BCM_56840_A0) || defined(BCM_88732_A0) 9617 soc_field_info_t soc_XLPORT_XGXS2_STATUS0_REGr_fields[] = { 9618 { RX2_ACTf, 1, 7, SOCF_RO }, 9619 { TX2_ACTf, 1, 8, SOCF_RO }, 9620 { XGXS2_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 9621 { XGXS2_DUPLEX_STATUSf, 1, 1, SOCF_RO }, 9622 { XGXS2_FIBER_RXACTf, 1, 2, SOCF_RO }, 9623 { XGXS2_FIBER_TXACTf, 1, 3, SOCF_RO }, 9624 { XGXS2_LINKf, 1, 9, SOCF_RO }, 9625 { XGXS2_LINK10Gf, 1, 10, SOCF_RO }, 9626 { XGXS2_LINK_STATUSf, 1, 4, SOCF_RO }, 9627 { XGXS2_SGMIIf, 1, 5, SOCF_RO }, 9628 { XGXS2_SPEED15750_HI_DXGXSf, 1, 15, SOCF_RO }, 9629 { XGXS2_SPEED20G_DXGXSf, 1, 16, SOCF_RO }, 9630 { XGXS2_SPEED20G_HI_DXGXSf, 1, 17, SOCF_RO }, 9631 { XGXS2_SPEED40Gf, 1, 18, SOCF_RO }, 9632 { XGXS2_SPEED40G_CR4f, 1, 14, SOCF_RO }, 9633 { XGXS2_SPEED40G_KR4f, 1, 13, SOCF_RO }, 9634 { XGXS2_SPEED_R2_12000f, 1, 11, SOCF_RO }, 9635 { XGXS2_SPEED_X2_10000f, 1, 12, SOCF_RO }, 9636 { XGXS2_TICKf, 1, 6, SOCF_RO } 9637 }; 9638 9639 #endif 9640 #if defined(BCM_56840_B0) 9641 soc_field_info_t soc_XLPORT_XGXS2_STATUS0_REG_BCM56840_B0r_fields[] = { 9642 { RX2_ACTf, 1, 7, SOCF_RO }, 9643 { TX2_ACTf, 1, 8, SOCF_RO }, 9644 { XGXS2_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 9645 { XGXS2_DUPLEX_STATUSf, 1, 1, SOCF_RO }, 9646 { XGXS2_FIBER_RXACTf, 1, 2, SOCF_RO }, 9647 { XGXS2_FIBER_TXACTf, 1, 3, SOCF_RO }, 9648 { XGXS2_LINKf, 1, 9, SOCF_RO }, 9649 { XGXS2_LINK10Gf, 1, 10, SOCF_RO }, 9650 { XGXS2_LINK_STATUSf, 1, 4, SOCF_RO }, 9651 { XGXS2_RX_TICKf, 1, 19, SOCF_RO }, 9652 { XGXS2_SGMIIf, 1, 5, SOCF_RO }, 9653 { XGXS2_SPEED10G_CX1f, 1, 20, SOCF_RO }, 9654 { XGXS2_SPEED10G_ERf, 1, 24, SOCF_RO }, 9655 { XGXS2_SPEED10G_LRf, 1, 25, SOCF_RO }, 9656 { XGXS2_SPEED10G_LRMf, 1, 27, SOCF_RO }, 9657 { XGXS2_SPEED10G_SRf, 1, 26, SOCF_RO }, 9658 { XGXS2_SPEED15750_HI_DXGXSf, 1, 15, SOCF_RO }, 9659 { XGXS2_SPEED1G_CX1f, 1, 21, SOCF_RO }, 9660 { XGXS2_SPEED20G_CR2f, 1, 29, SOCF_RO }, 9661 { XGXS2_SPEED20G_DXGXSf, 1, 16, SOCF_RO }, 9662 { XGXS2_SPEED20G_HI_DXGXSf, 1, 17, SOCF_RO }, 9663 { XGXS2_SPEED20G_KR2f, 1, 28, SOCF_RO }, 9664 { XGXS2_SPEED40Gf, 1, 18, SOCF_RO }, 9665 { XGXS2_SPEED40G_CR4f, 1, 14, SOCF_RO }, 9666 { XGXS2_SPEED40G_KR4f, 1, 13, SOCF_RO }, 9667 { XGXS2_SPEED40G_LR4f, 1, 23, SOCF_RO }, 9668 { XGXS2_SPEED40G_SR4f, 1, 22, SOCF_RO }, 9669 { XGXS2_SPEED_R2_12000f, 1, 11, SOCF_RO }, 9670 { XGXS2_SPEED_X2_10000f, 1, 12, SOCF_RO }, 9671 { XGXS2_TICKf, 1, 6, SOCF_RO } 9672 }; 9673 9674 #endif 9675 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9676 defined(BCM_88732_A0) 9677 soc_field_info_t soc_XLPORT_XGXS2_STATUS1_REGr_fields[] = { 9678 { XGXS2_SPEED1000f, 1, 2, SOCF_RO }, 9679 { XGXS2_SPEED10000f, 1, 8, SOCF_RO }, 9680 { XGXS2_SPEED10000_CX4f, 1, 9, SOCF_RO }, 9681 { XGXS2_SPEED10000_DXGXSf, 1, 19, SOCF_RO }, 9682 { XGXS2_SPEED10000_HI_DXGXSf, 1, 20, SOCF_RO }, 9683 { XGXS2_SPEED10000_KRf, 1, 25, SOCF_RO }, 9684 { XGXS2_SPEED10000_KX4f, 1, 26, SOCF_RO }, 9685 { XGXS2_SPEED1000_KXf, 1, 27, SOCF_RO }, 9686 { XGXS2_SPEED10500_DXGXSf, 1, 21, SOCF_RO }, 9687 { XGXS2_SPEED10500_HI_DXGXSf, 1, 22, SOCF_RO }, 9688 { XGXS2_SPEED10G_SFIf, 1, 29, SOCF_RO }, 9689 { XGXS2_SPEED10G_SINGLEf, 1, 28, SOCF_RO }, 9690 { XGXS2_SPEED12000f, 1, 10, SOCF_RO }, 9691 { XGXS2_SPEED12500f, 1, 11, SOCF_RO }, 9692 { XGXS2_SPEED12773_DXGXSf, 1, 23, SOCF_RO }, 9693 { XGXS2_SPEED12773_HI_DXGXSf, 1, 24, SOCF_RO }, 9694 { XGXS2_SPEED13000f, 1, 12, SOCF_RO }, 9695 { XGXS2_SPEED15000f, 1, 13, SOCF_RO }, 9696 { XGXS2_SPEED16000f, 1, 14, SOCF_RO }, 9697 { XGXS2_SPEED20000f, 1, 15, SOCF_RO }, 9698 { XGXS2_SPEED21000f, 1, 16, SOCF_RO }, 9699 { XGXS2_SPEED2500f, 1, 3, SOCF_RO }, 9700 { XGXS2_SPEED25455f, 1, 17, SOCF_RO }, 9701 { XGXS2_SPEED31500f, 1, 18, SOCF_RO }, 9702 { XGXS2_SPEED5000f, 1, 4, SOCF_RO }, 9703 { XGXS2_SPEED5000_SINGLEf, 1, 5, SOCF_RO }, 9704 { XGXS2_SPEED6000f, 1, 6, SOCF_RO }, 9705 { XGXS2_SPEED6364_SINGLEf, 1, 7, SOCF_RO }, 9706 { XGXS2_SPEED_10f, 1, 0, SOCF_RO }, 9707 { XGXS2_SPEED_100f, 1, 1, SOCF_RO } 9708 }; 9709 9710 #endif 9711 #if defined(BCM_56840_A0) || defined(BCM_88732_A0) 9712 soc_field_info_t soc_XLPORT_XGXS3_STATUS0_REGr_fields[] = { 9713 { RX3_ACTf, 1, 7, SOCF_RO }, 9714 { TX3_ACTf, 1, 8, SOCF_RO }, 9715 { XGXS3_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 9716 { XGXS3_DUPLEX_STATUSf, 1, 1, SOCF_RO }, 9717 { XGXS3_FIBER_RXACTf, 1, 2, SOCF_RO }, 9718 { XGXS3_FIBER_TXACTf, 1, 3, SOCF_RO }, 9719 { XGXS3_LINKf, 1, 9, SOCF_RO }, 9720 { XGXS3_LINK10Gf, 1, 10, SOCF_RO }, 9721 { XGXS3_LINK_STATUSf, 1, 4, SOCF_RO }, 9722 { XGXS3_SGMIIf, 1, 5, SOCF_RO }, 9723 { XGXS3_SPEED15750_HI_DXGXSf, 1, 15, SOCF_RO }, 9724 { XGXS3_SPEED20G_DXGXSf, 1, 16, SOCF_RO }, 9725 { XGXS3_SPEED20G_HI_DXGXSf, 1, 17, SOCF_RO }, 9726 { XGXS3_SPEED40Gf, 1, 18, SOCF_RO }, 9727 { XGXS3_SPEED40G_CR4f, 1, 14, SOCF_RO }, 9728 { XGXS3_SPEED40G_KR4f, 1, 13, SOCF_RO }, 9729 { XGXS3_SPEED_R2_12000f, 1, 11, SOCF_RO }, 9730 { XGXS3_SPEED_X2_10000f, 1, 12, SOCF_RO }, 9731 { XGXS3_TICKf, 1, 6, SOCF_RO } 9732 }; 9733 9734 #endif 9735 #if defined(BCM_56840_B0) 9736 soc_field_info_t soc_XLPORT_XGXS3_STATUS0_REG_BCM56840_B0r_fields[] = { 9737 { RX3_ACTf, 1, 7, SOCF_RO }, 9738 { TX3_ACTf, 1, 8, SOCF_RO }, 9739 { XGXS3_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 9740 { XGXS3_DUPLEX_STATUSf, 1, 1, SOCF_RO }, 9741 { XGXS3_FIBER_RXACTf, 1, 2, SOCF_RO }, 9742 { XGXS3_FIBER_TXACTf, 1, 3, SOCF_RO }, 9743 { XGXS3_LINKf, 1, 9, SOCF_RO }, 9744 { XGXS3_LINK10Gf, 1, 10, SOCF_RO }, 9745 { XGXS3_LINK_STATUSf, 1, 4, SOCF_RO }, 9746 { XGXS3_RX_TICKf, 1, 19, SOCF_RO }, 9747 { XGXS3_SGMIIf, 1, 5, SOCF_RO }, 9748 { XGXS3_SPEED10G_CX1f, 1, 20, SOCF_RO }, 9749 { XGXS3_SPEED10G_ERf, 1, 24, SOCF_RO }, 9750 { XGXS3_SPEED10G_LRf, 1, 25, SOCF_RO }, 9751 { XGXS3_SPEED10G_LRMf, 1, 27, SOCF_RO }, 9752 { XGXS3_SPEED10G_SRf, 1, 26, SOCF_RO }, 9753 { XGXS3_SPEED15750_HI_DXGXSf, 1, 15, SOCF_RO }, 9754 { XGXS3_SPEED1G_CX1f, 1, 21, SOCF_RO }, 9755 { XGXS3_SPEED20G_CR2f, 1, 29, SOCF_RO }, 9756 { XGXS3_SPEED20G_DXGXSf, 1, 16, SOCF_RO }, 9757 { XGXS3_SPEED20G_HI_DXGXSf, 1, 17, SOCF_RO }, 9758 { XGXS3_SPEED20G_KR2f, 1, 28, SOCF_RO }, 9759 { XGXS3_SPEED40Gf, 1, 18, SOCF_RO }, 9760 { XGXS3_SPEED40G_CR4f, 1, 14, SOCF_RO }, 9761 { XGXS3_SPEED40G_KR4f, 1, 13, SOCF_RO }, 9762 { XGXS3_SPEED40G_LR4f, 1, 23, SOCF_RO }, 9763 { XGXS3_SPEED40G_SR4f, 1, 22, SOCF_RO }, 9764 { XGXS3_SPEED_R2_12000f, 1, 11, SOCF_RO }, 9765 { XGXS3_SPEED_X2_10000f, 1, 12, SOCF_RO }, 9766 { XGXS3_TICKf, 1, 6, SOCF_RO } 9767 }; 9768 9769 #endif 9770 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9771 defined(BCM_88732_A0) 9772 soc_field_info_t soc_XLPORT_XGXS3_STATUS1_REGr_fields[] = { 9773 { XGXS3_SPEED1000f, 1, 2, SOCF_RO }, 9774 { XGXS3_SPEED10000f, 1, 8, SOCF_RO }, 9775 { XGXS3_SPEED10000_CX4f, 1, 9, SOCF_RO }, 9776 { XGXS3_SPEED10000_DXGXSf, 1, 19, SOCF_RO }, 9777 { XGXS3_SPEED10000_HI_DXGXSf, 1, 20, SOCF_RO }, 9778 { XGXS3_SPEED10000_KRf, 1, 25, SOCF_RO }, 9779 { XGXS3_SPEED10000_KX4f, 1, 26, SOCF_RO }, 9780 { XGXS3_SPEED1000_KXf, 1, 27, SOCF_RO }, 9781 { XGXS3_SPEED10500_DXGXSf, 1, 21, SOCF_RO }, 9782 { XGXS3_SPEED10500_HI_DXGXSf, 1, 22, SOCF_RO }, 9783 { XGXS3_SPEED10G_SFIf, 1, 29, SOCF_RO }, 9784 { XGXS3_SPEED10G_SINGLEf, 1, 28, SOCF_RO }, 9785 { XGXS3_SPEED12000f, 1, 10, SOCF_RO }, 9786 { XGXS3_SPEED12500f, 1, 11, SOCF_RO }, 9787 { XGXS3_SPEED12773_DXGXSf, 1, 23, SOCF_RO }, 9788 { XGXS3_SPEED12773_HI_DXGXSf, 1, 24, SOCF_RO }, 9789 { XGXS3_SPEED13000f, 1, 12, SOCF_RO }, 9790 { XGXS3_SPEED15000f, 1, 13, SOCF_RO }, 9791 { XGXS3_SPEED16000f, 1, 14, SOCF_RO }, 9792 { XGXS3_SPEED20000f, 1, 15, SOCF_RO }, 9793 { XGXS3_SPEED21000f, 1, 16, SOCF_RO }, 9794 { XGXS3_SPEED2500f, 1, 3, SOCF_RO }, 9795 { XGXS3_SPEED25455f, 1, 17, SOCF_RO }, 9796 { XGXS3_SPEED31500f, 1, 18, SOCF_RO }, 9797 { XGXS3_SPEED5000f, 1, 4, SOCF_RO }, 9798 { XGXS3_SPEED5000_SINGLEf, 1, 5, SOCF_RO }, 9799 { XGXS3_SPEED6000f, 1, 6, SOCF_RO }, 9800 { XGXS3_SPEED6364_SINGLEf, 1, 7, SOCF_RO }, 9801 { XGXS3_SPEED_10f, 1, 0, SOCF_RO }, 9802 { XGXS3_SPEED_100f, 1, 1, SOCF_RO } 9803 }; 9804 9805 #endif 9806 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 9807 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9808 defined(BCM_88732_A0) 9809 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODEr_fields[] = { 9810 { CNT_MODEf, 1, 0, 0 } 9811 }; 9812 9813 #endif 9814 #if defined(BCM_53400_A0) || defined(BCM_53570_A0) || \ 9815 defined(BCM_53570_B0) || defined(BCM_56160_A0) || \ 9816 defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 9817 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 9818 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 9819 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 9820 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 9821 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 9822 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 9823 defined(BCM_56980_B0) 9824 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM53400_A0r_fields[] = { 9825 { CNT_MODEf, 1, 0, 0 } 9826 }; 9827 9828 #endif 9829 #if defined(BCM_88270_A0) 9830 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM88270_A0r_fields[] = { 9831 { CNT_MODEf, 1, 0, 0 } 9832 }; 9833 9834 #endif 9835 #if defined(BCM_88375_A0) 9836 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM88375_A0r_fields[] = { 9837 { CNT_MODEf, 1, 0, 0 } 9838 }; 9839 9840 #endif 9841 #if defined(BCM_88375_B0) 9842 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM88375_B0r_fields[] = { 9843 { CNT_MODEf, 1, 0, 0 } 9844 }; 9845 9846 #endif 9847 #if defined(BCM_88470_A0) 9848 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM88470_A0r_fields[] = { 9849 { CNT_MODEf, 1, 0, 0 } 9850 }; 9851 9852 #endif 9853 #if defined(BCM_88470_B0) 9854 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM88470_B0r_fields[] = { 9855 { CNT_MODEf, 1, 0, 0 } 9856 }; 9857 9858 #endif 9859 #if defined(BCM_88675_A0) 9860 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM88675_A0r_fields[] = { 9861 { CNT_MODEf, 1, 0, 0 } 9862 }; 9863 9864 #endif 9865 #if defined(BCM_88675_B0) 9866 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM88675_B0r_fields[] = { 9867 { CNT_MODEf, 1, 0, 0 } 9868 }; 9869 9870 #endif 9871 #if defined(BCM_88680_A0) 9872 soc_field_info_t soc_XLPORT_XGXS_COUNTER_MODE_BCM88680_A0r_fields[] = { 9873 { CNT_MODEf, 1, 0, 0 } 9874 }; 9875 9876 #endif 9877 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9878 defined(BCM_88732_A0) 9879 soc_field_info_t soc_XLPORT_XGXS_CTRL_REGr_fields[] = { 9880 { IDDQf, 1, 9, SOCF_RES }, 9881 { LCREF_ENf, 1, 11, SOCF_RES }, 9882 { PLLBYPf, 1, 10, SOCF_RES }, 9883 { PWRDWNf, 1, 1, SOCF_RES }, 9884 { PWRDWN_PLLf, 1, 0, SOCF_RES }, 9885 { RSTB_HWf, 1, 12, SOCF_RES }, 9886 { RSTB_MDIOREGSf, 1, 13, SOCF_RES }, 9887 { RSTB_PLLf, 1, 14, SOCF_RES }, 9888 { TXD10G_FIFO_RSTBf, 1, 19, SOCF_RES }, 9889 { TXD1G_FIFO_RSTBf, 4, 15, SOCF_LE|SOCF_RES }, 9890 { XLP_XGXS_RESERVED0f, 7, 2, SOCF_LE|SOCF_RES }, 9891 { XLP_XGXS_RESERVED1f, 2, 20, SOCF_LE|SOCF_RES } 9892 }; 9893 9894 #endif 9895 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9896 defined(BCM_88732_A0) 9897 soc_field_info_t soc_XLPORT_XGXS_STATUS_GEN_REGr_fields[] = { 9898 { TXPLL_LOCKf, 1, 0, SOCF_RO } 9899 }; 9900 9901 #endif 9902 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 9903 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9904 defined(BCM_88732_A0) 9905 soc_field_info_t soc_XLPORT_XMAC_CONTROLr_fields[] = { 9906 { XMAC_RESETf, 1, 0, SOCF_RES } 9907 }; 9908 9909 #endif 9910 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 9911 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 9912 defined(BCM_88732_A0) 9913 soc_field_info_t soc_XLP_EEE_COUNTER_MODEr_fields[] = { 9914 { MODE_BITf, 1, 0, 0 } 9915 }; 9916 9917 #endif 9918 #if defined(BCM_88650_A0) 9919 soc_field_info_t soc_XLP_REG_060200r_fields[] = { 9920 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG } 9921 }; 9922 9923 #endif 9924 #if defined(BCM_88650_A0) 9925 soc_field_info_t soc_XLP_REG_060300r_fields[] = { 9926 { FIELD_0_1f, 2, 0, SOCF_LE|SOCF_SIG } 9927 }; 9928 9929 #endif 9930 #if defined(BCM_88650_A0) 9931 soc_field_info_t soc_XLP_REG_061500r_fields[] = { 9932 { FIELD_0_0f, 1, 0, SOCF_SIG }, 9933 { FIELD_13_20f, 8, 13, SOCF_LE|SOCF_SIG }, 9934 { FIELD_1_1f, 1, 1, SOCF_SIG }, 9935 { FIELD_2_2f, 1, 2, SOCF_SIG }, 9936 { FIELD_3_3f, 1, 3, SOCF_SIG }, 9937 { FIELD_4_4f, 1, 4, SOCF_SIG }, 9938 { FIELD_5_12f, 8, 5, SOCF_LE|SOCF_SIG } 9939 }; 9940 9941 #endif 9942 #if defined(BCM_88650_A0) 9943 soc_field_info_t soc_XLP_REG_062000r_fields[] = { 9944 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 9945 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 9946 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 9947 }; 9948 9949 #endif 9950 #if defined(BCM_88650_A0) 9951 soc_field_info_t soc_XLP_REG_062200r_fields[] = { 9952 { FIELD_0_7f, 8, 0, SOCF_LE|SOCF_SIG }, 9953 { FIELD_10_10f, 1, 10, SOCF_SIG }, 9954 { FIELD_11_11f, 1, 11, SOCF_SIG }, 9955 { FIELD_12_19f, 8, 12, SOCF_LE|SOCF_SIG }, 9956 { FIELD_8_8f, 1, 8, SOCF_SIG }, 9957 { FIELD_9_9f, 1, 9, SOCF_SIG } 9958 }; 9959 9960 #endif 9961 #if defined(BCM_88650_A0) 9962 soc_field_info_t soc_XLP_REG_062500r_fields[] = { 9963 { FIELD_0_0f, 1, 0, SOCF_SIG }, 9964 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 9965 { FIELD_1_1f, 1, 1, SOCF_SIG }, 9966 { FIELD_2_2f, 1, 2, SOCF_SIG }, 9967 { FIELD_32_34f, 3, 32, SOCF_LE|SOCF_SIG }, 9968 { FIELD_3_34f, 32, 3, SOCF_LE|SOCF_SIG } 9969 }; 9970 9971 #endif 9972 #if defined(BCM_88675_A0) 9973 soc_field_info_t soc_XLP_REG_2022300r_fields[] = { 9974 { FIELD_0_3f, 4, 0, SOCF_LE } 9975 }; 9976 9977 #endif 9978 #if defined(BCM_88650_B0) 9979 soc_field_info_t soc_XLP_REG_060200_BCM88650_B0r_fields[] = { 9980 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG } 9981 }; 9982 9983 #endif 9984 #if defined(BCM_88660_A0) 9985 soc_field_info_t soc_XLP_REG_060200_BCM88660_A0r_fields[] = { 9986 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG } 9987 }; 9988 9989 #endif 9990 #if defined(BCM_88650_B0) 9991 soc_field_info_t soc_XLP_REG_060300_BCM88650_B0r_fields[] = { 9992 { FIELD_0_1f, 2, 0, SOCF_LE|SOCF_SIG } 9993 }; 9994 9995 #endif 9996 #if defined(BCM_88660_A0) 9997 soc_field_info_t soc_XLP_REG_060300_BCM88660_A0r_fields[] = { 9998 { FIELD_0_1f, 2, 0, SOCF_LE|SOCF_SIG } 9999 }; 10000 10001 #endif 10002 #if defined(BCM_88650_B0) 10003 soc_field_info_t soc_XLP_REG_061500_BCM88650_B0r_fields[] = { 10004 { FIELD_0_0f, 1, 0, SOCF_SIG }, 10005 { FIELD_13_20f, 8, 13, SOCF_LE|SOCF_SIG }, 10006 { FIELD_1_1f, 1, 1, SOCF_SIG }, 10007 { FIELD_2_2f, 1, 2, SOCF_SIG }, 10008 { FIELD_3_3f, 1, 3, SOCF_SIG }, 10009 { FIELD_4_4f, 1, 4, SOCF_SIG }, 10010 { FIELD_5_12f, 8, 5, SOCF_LE|SOCF_SIG } 10011 }; 10012 10013 #endif 10014 #if defined(BCM_88660_A0) 10015 soc_field_info_t soc_XLP_REG_061500_BCM88660_A0r_fields[] = { 10016 { FIELD_0_0f, 1, 0, SOCF_SIG }, 10017 { FIELD_13_20f, 8, 13, SOCF_LE|SOCF_SIG }, 10018 { FIELD_1_1f, 1, 1, SOCF_SIG }, 10019 { FIELD_2_2f, 1, 2, SOCF_SIG }, 10020 { FIELD_3_3f, 1, 3, SOCF_SIG }, 10021 { FIELD_4_4f, 1, 4, SOCF_SIG }, 10022 { FIELD_5_12f, 8, 5, SOCF_LE|SOCF_SIG } 10023 }; 10024 10025 #endif 10026 #if defined(BCM_88650_A0) 10027 soc_field_info_t soc_XLP_REG_061E00r_fields[] = { 10028 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10029 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 10030 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 10031 }; 10032 10033 #endif 10034 #if defined(BCM_88650_B0) 10035 soc_field_info_t soc_XLP_REG_061E00_BCM88650_B0r_fields[] = { 10036 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10037 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 10038 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 10039 }; 10040 10041 #endif 10042 #if defined(BCM_88660_A0) 10043 soc_field_info_t soc_XLP_REG_061E00_BCM88660_A0r_fields[] = { 10044 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10045 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 10046 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 10047 }; 10048 10049 #endif 10050 #if defined(BCM_88650_A0) 10051 soc_field_info_t soc_XLP_REG_061F00r_fields[] = { 10052 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10053 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 10054 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 10055 }; 10056 10057 #endif 10058 #if defined(BCM_88650_B0) 10059 soc_field_info_t soc_XLP_REG_061F00_BCM88650_B0r_fields[] = { 10060 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10061 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 10062 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 10063 }; 10064 10065 #endif 10066 #if defined(BCM_88660_A0) 10067 soc_field_info_t soc_XLP_REG_061F00_BCM88660_A0r_fields[] = { 10068 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10069 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 10070 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 10071 }; 10072 10073 #endif 10074 #if defined(BCM_88650_B0) 10075 soc_field_info_t soc_XLP_REG_062000_BCM88650_B0r_fields[] = { 10076 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10077 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 10078 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 10079 }; 10080 10081 #endif 10082 #if defined(BCM_88660_A0) 10083 soc_field_info_t soc_XLP_REG_062000_BCM88660_A0r_fields[] = { 10084 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10085 { FIELD_0_63f, 64, 0, SOCF_LE|SOCF_SIG }, 10086 { FIELD_32_63f, 32, 32, SOCF_LE|SOCF_SIG } 10087 }; 10088 10089 #endif 10090 #if defined(BCM_88650_B0) 10091 soc_field_info_t soc_XLP_REG_062200_BCM88650_B0r_fields[] = { 10092 { FIELD_0_7f, 8, 0, SOCF_LE|SOCF_SIG }, 10093 { FIELD_10_10f, 1, 10, SOCF_SIG }, 10094 { FIELD_11_11f, 1, 11, SOCF_SIG }, 10095 { FIELD_12_19f, 8, 12, SOCF_LE|SOCF_SIG }, 10096 { FIELD_8_8f, 1, 8, SOCF_SIG }, 10097 { FIELD_9_9f, 1, 9, SOCF_SIG } 10098 }; 10099 10100 #endif 10101 #if defined(BCM_88660_A0) 10102 soc_field_info_t soc_XLP_REG_062200_BCM88660_A0r_fields[] = { 10103 { FIELD_0_7f, 8, 0, SOCF_LE|SOCF_SIG }, 10104 { FIELD_10_10f, 1, 10, SOCF_SIG }, 10105 { FIELD_11_11f, 1, 11, SOCF_SIG }, 10106 { FIELD_12_19f, 8, 12, SOCF_LE|SOCF_SIG }, 10107 { FIELD_8_8f, 1, 8, SOCF_SIG }, 10108 { FIELD_9_9f, 1, 9, SOCF_SIG } 10109 }; 10110 10111 #endif 10112 #if defined(BCM_88650_B0) 10113 soc_field_info_t soc_XLP_REG_062500_BCM88650_B0r_fields[] = { 10114 { FIELD_0_0f, 1, 0, SOCF_SIG }, 10115 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10116 { FIELD_1_1f, 1, 1, SOCF_SIG }, 10117 { FIELD_2_2f, 1, 2, SOCF_SIG }, 10118 { FIELD_32_34f, 3, 32, SOCF_LE|SOCF_SIG }, 10119 { FIELD_3_34f, 32, 3, SOCF_LE|SOCF_SIG } 10120 }; 10121 10122 #endif 10123 #if defined(BCM_88660_A0) 10124 soc_field_info_t soc_XLP_REG_062500_BCM88660_A0r_fields[] = { 10125 { FIELD_0_0f, 1, 0, SOCF_SIG }, 10126 { FIELD_0_31f, 32, 0, SOCF_LE|SOCF_SIG }, 10127 { FIELD_1_1f, 1, 1, SOCF_SIG }, 10128 { FIELD_2_2f, 1, 2, SOCF_SIG }, 10129 { FIELD_32_34f, 3, 32, SOCF_LE|SOCF_SIG }, 10130 { FIELD_3_34f, 32, 3, SOCF_LE|SOCF_SIG } 10131 }; 10132 10133 #endif 10134 #if defined(BCM_88375_A0) 10135 soc_field_info_t soc_XLP_REG_2022300_BCM88375_A0r_fields[] = { 10136 { FIELD_0_3f, 4, 0, SOCF_LE } 10137 }; 10138 10139 #endif 10140 #if defined(BCM_88470_A0) 10141 soc_field_info_t soc_XLP_REG_2022300_BCM88470_A0r_fields[] = { 10142 { FIELD_0_3f, 4, 0, SOCF_LE } 10143 }; 10144 10145 #endif 10146 #if defined(BCM_88732_A0) 10147 soc_field_info_t soc_XLP_TO_MMU_BKP_STATUSr_fields[] = { 10148 { IL1_PRI_BITMAPf, 16, 16, SOCF_LE|SOCF_W1TC }, 10149 { PRI_BITMAPf, 16, 0, SOCF_LE|SOCF_W1TC } 10150 }; 10151 10152 #endif 10153 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 10154 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 10155 defined(BCM_88732_A0) 10156 soc_field_info_t soc_XLP_TXFIFO_CELL_CNTr_fields[] = { 10157 { CELL_CNTf, 5, 0, SOCF_LE|SOCF_RO } 10158 }; 10159 10160 #endif 10161 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 10162 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 10163 defined(BCM_88732_A0) 10164 soc_field_info_t soc_XLP_TXFIFO_CELL_REQ_CNTr_fields[] = { 10165 { REQ_CNTf, 5, 0, SOCF_LE|SOCF_RO } 10166 }; 10167 10168 #endif 10169 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 10170 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 10171 defined(BCM_88732_A0) 10172 soc_field_info_t soc_XLP_TXFIFO_PKT_DROP_CTLr_fields[] = { 10173 { DROP_ENf, 1, 0, 0 } 10174 }; 10175 10176 #endif 10177 #if defined(BCM_88650_A0) 10178 soc_field_info_t soc_XLP_XMAC_CLEAR_FIFO_STATUSr_fields[] = { 10179 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 10180 { CLEAR_RX_PKT_OVERFLOWf, 1, 0, SOCF_RO|SOCF_SIG }, 10181 { CLEAR_TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO|SOCF_SIG }, 10182 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 10183 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 10184 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 10185 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 10186 }; 10187 10188 #endif 10189 #if defined(BCM_88650_B0) 10190 soc_field_info_t soc_XLP_XMAC_CLEAR_FIFO_STATUS_BCM88650_B0r_fields[] = { 10191 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 10192 { CLEAR_RX_PKT_OVERFLOWf, 1, 0, SOCF_RO|SOCF_SIG }, 10193 { CLEAR_TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO|SOCF_SIG }, 10194 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 10195 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 10196 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 10197 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 10198 }; 10199 10200 #endif 10201 #if defined(BCM_88660_A0) 10202 soc_field_info_t soc_XLP_XMAC_CLEAR_FIFO_STATUS_BCM88660_A0r_fields[] = { 10203 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO|SOCF_SIG }, 10204 { CLEAR_RX_PKT_OVERFLOWf, 1, 0, SOCF_RO|SOCF_SIG }, 10205 { CLEAR_TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO|SOCF_SIG }, 10206 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO|SOCF_SIG }, 10207 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO|SOCF_SIG }, 10208 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO|SOCF_SIG }, 10209 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO|SOCF_SIG } 10210 }; 10211 10212 #endif 10213 #if defined(BCM_88650_A0) 10214 soc_field_info_t soc_XLP_XMAC_CLEAR_RX_LSS_STATUSr_fields[] = { 10215 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_SIG }, 10216 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, SOCF_SIG }, 10217 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, SOCF_SIG } 10218 }; 10219 10220 #endif 10221 #if defined(BCM_88650_B0) 10222 soc_field_info_t soc_XLP_XMAC_CLEAR_RX_LSS_STATUS_BCM88650_B0r_fields[] = { 10223 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_SIG }, 10224 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, SOCF_SIG }, 10225 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, SOCF_SIG } 10226 }; 10227 10228 #endif 10229 #if defined(BCM_88660_A0) 10230 soc_field_info_t soc_XLP_XMAC_CLEAR_RX_LSS_STATUS_BCM88660_A0r_fields[] = { 10231 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_SIG }, 10232 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, SOCF_SIG }, 10233 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, SOCF_SIG } 10234 }; 10235 10236 #endif 10237 #if defined(BCM_88650_A0) 10238 soc_field_info_t soc_XLP_XMAC_CTRLr_fields[] = { 10239 { FIELD_3_3f, 1, 3, SOCF_SIG }, 10240 { FIELD_5_5f, 1, 5, SOCF_SIG }, 10241 { LINE_LOCAL_LPBKf, 1, 2, SOCF_SIG }, 10242 { LINE_REMOTE_LPBKf, 1, 4, SOCF_SIG }, 10243 { LINK_STATUS_SELECTf, 1, 13, SOCF_SIG }, 10244 { LOCAL_LPBK_LEAK_ENBf, 1, 8, SOCF_SIG }, 10245 { REMOTE_LPBK_LEAK_ENBf, 1, 9, SOCF_SIG }, 10246 { RS_SOFT_RESETf, 1, 10, SOCF_SIG }, 10247 { RX_ENf, 1, 1, SOCF_SIG }, 10248 { SOFT_RESETf, 1, 6, SOCF_SIG }, 10249 { SW_LINK_STATUSf, 1, 12, SOCF_SIG }, 10250 { TX_ENf, 1, 0, SOCF_SIG }, 10251 { XGMII_IPG_CHECK_DISABLEf, 1, 11, SOCF_SIG }, 10252 { XLGMII_ALIGN_ENBf, 1, 7, SOCF_SIG } 10253 }; 10254 10255 #endif 10256 #if defined(BCM_88650_B0) 10257 soc_field_info_t soc_XLP_XMAC_CTRL_BCM88650_B0r_fields[] = { 10258 { FIELD_3_3f, 1, 3, SOCF_SIG }, 10259 { FIELD_5_5f, 1, 5, SOCF_SIG }, 10260 { LINE_LOCAL_LPBKf, 1, 2, SOCF_SIG }, 10261 { LINE_REMOTE_LPBKf, 1, 4, SOCF_SIG }, 10262 { LINK_STATUS_SELECTf, 1, 13, SOCF_SIG }, 10263 { LOCAL_LPBK_LEAK_ENBf, 1, 8, SOCF_SIG }, 10264 { REMOTE_LPBK_LEAK_ENBf, 1, 9, SOCF_SIG }, 10265 { RS_SOFT_RESETf, 1, 10, SOCF_SIG }, 10266 { RX_ENf, 1, 1, SOCF_SIG }, 10267 { SOFT_RESETf, 1, 6, SOCF_SIG }, 10268 { SW_LINK_STATUSf, 1, 12, SOCF_SIG }, 10269 { TX_ENf, 1, 0, SOCF_SIG }, 10270 { XGMII_IPG_CHECK_DISABLEf, 1, 11, SOCF_SIG }, 10271 { XLGMII_ALIGN_ENBf, 1, 7, SOCF_SIG } 10272 }; 10273 10274 #endif 10275 #if defined(BCM_88660_A0) 10276 soc_field_info_t soc_XLP_XMAC_CTRL_BCM88660_A0r_fields[] = { 10277 { FIELD_3_3f, 1, 3, SOCF_SIG }, 10278 { FIELD_5_5f, 1, 5, SOCF_SIG }, 10279 { LINE_LOCAL_LPBKf, 1, 2, SOCF_SIG }, 10280 { LINE_REMOTE_LPBKf, 1, 4, SOCF_SIG }, 10281 { LINK_STATUS_SELECTf, 1, 13, SOCF_SIG }, 10282 { LOCAL_LPBK_LEAK_ENBf, 1, 8, SOCF_SIG }, 10283 { REMOTE_LPBK_LEAK_ENBf, 1, 9, SOCF_SIG }, 10284 { RS_SOFT_RESETf, 1, 10, SOCF_SIG }, 10285 { RX_ENf, 1, 1, SOCF_SIG }, 10286 { SOFT_RESETf, 1, 6, SOCF_SIG }, 10287 { SW_LINK_STATUSf, 1, 12, SOCF_SIG }, 10288 { TX_ENf, 1, 0, SOCF_SIG }, 10289 { XGMII_IPG_CHECK_DISABLEf, 1, 11, SOCF_SIG }, 10290 { XLGMII_ALIGN_ENBf, 1, 7, SOCF_SIG } 10291 }; 10292 10293 #endif 10294 #if defined(BCM_88650_A0) 10295 soc_field_info_t soc_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMERr_fields[] = { 10296 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE|SOCF_SIG } 10297 }; 10298 10299 #endif 10300 #if defined(BCM_88650_B0) 10301 soc_field_info_t soc_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88650_B0r_fields[] = { 10302 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE|SOCF_SIG } 10303 }; 10304 10305 #endif 10306 #if defined(BCM_88660_A0) 10307 soc_field_info_t soc_XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMER_BCM88660_A0r_fields[] = { 10308 { ONE_SECOND_TIMERf, 24, 0, SOCF_LE|SOCF_SIG } 10309 }; 10310 10311 #endif 10312 #if defined(BCM_88650_A0) 10313 soc_field_info_t soc_XLP_XMAC_EEE_CTRLr_fields[] = { 10314 { EEE_ENf, 1, 0, SOCF_SIG }, 10315 { FIELD_1_1f, 1, 1, SOCF_SIG }, 10316 { FIELD_2_2f, 1, 2, SOCF_SIG }, 10317 { FIELD_3_3f, 1, 3, SOCF_SIG } 10318 }; 10319 10320 #endif 10321 #if defined(BCM_88650_B0) 10322 soc_field_info_t soc_XLP_XMAC_EEE_CTRL_BCM88650_B0r_fields[] = { 10323 { EEE_ENf, 1, 0, SOCF_SIG }, 10324 { FIELD_1_1f, 1, 1, SOCF_SIG }, 10325 { FIELD_2_2f, 1, 2, SOCF_SIG }, 10326 { FIELD_3_3f, 1, 3, SOCF_SIG } 10327 }; 10328 10329 #endif 10330 #if defined(BCM_88660_A0) 10331 soc_field_info_t soc_XLP_XMAC_EEE_CTRL_BCM88660_A0r_fields[] = { 10332 { EEE_ENf, 1, 0, SOCF_SIG }, 10333 { FIELD_1_1f, 1, 1, SOCF_SIG }, 10334 { FIELD_2_2f, 1, 2, SOCF_SIG }, 10335 { FIELD_3_3f, 1, 3, SOCF_SIG } 10336 }; 10337 10338 #endif 10339 #if defined(BCM_88650_A0) 10340 soc_field_info_t soc_XLP_XMAC_EEE_TIMERSr_fields[] = { 10341 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE|SOCF_SIG }, 10342 { EEE_REF_COUNTf, 16, 48, SOCF_LE|SOCF_SIG }, 10343 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE|SOCF_SIG }, 10344 { XMAC_EEE_TIMERS_HIf, 32, 32, SOCF_LE|SOCF_SIG }, 10345 { XMAC_EEE_TIMERS_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10346 }; 10347 10348 #endif 10349 #if defined(BCM_88650_B0) 10350 soc_field_info_t soc_XLP_XMAC_EEE_TIMERS_BCM88650_B0r_fields[] = { 10351 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE|SOCF_SIG }, 10352 { EEE_REF_COUNTf, 16, 48, SOCF_LE|SOCF_SIG }, 10353 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE|SOCF_SIG }, 10354 { XMAC_EEE_TIMERS_HIf, 32, 32, SOCF_LE|SOCF_SIG }, 10355 { XMAC_EEE_TIMERS_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10356 }; 10357 10358 #endif 10359 #if defined(BCM_88660_A0) 10360 soc_field_info_t soc_XLP_XMAC_EEE_TIMERS_BCM88660_A0r_fields[] = { 10361 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE|SOCF_SIG }, 10362 { EEE_REF_COUNTf, 16, 48, SOCF_LE|SOCF_SIG }, 10363 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE|SOCF_SIG }, 10364 { XMAC_EEE_TIMERS_HIf, 32, 32, SOCF_LE|SOCF_SIG }, 10365 { XMAC_EEE_TIMERS_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10366 }; 10367 10368 #endif 10369 #if defined(BCM_88650_A0) 10370 soc_field_info_t soc_XLP_XMAC_FIFO_STATUSr_fields[] = { 10371 { LINK_STATUSf, 1, 7, SOCF_RO }, 10372 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 10373 { RX_PKT_OVERFLOWf, 1, 0, SOCF_RO }, 10374 { TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO }, 10375 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 10376 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 10377 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 10378 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 10379 }; 10380 10381 #endif 10382 #if defined(BCM_88650_B0) 10383 soc_field_info_t soc_XLP_XMAC_FIFO_STATUS_BCM88650_B0r_fields[] = { 10384 { LINK_STATUSf, 1, 7, SOCF_RO }, 10385 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 10386 { RX_PKT_OVERFLOWf, 1, 0, SOCF_RO }, 10387 { TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO }, 10388 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 10389 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 10390 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 10391 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 10392 }; 10393 10394 #endif 10395 #if defined(BCM_88660_A0) 10396 soc_field_info_t soc_XLP_XMAC_FIFO_STATUS_BCM88660_A0r_fields[] = { 10397 { LINK_STATUSf, 1, 7, SOCF_RO }, 10398 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 10399 { RX_PKT_OVERFLOWf, 1, 0, SOCF_RO }, 10400 { TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO }, 10401 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 10402 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 10403 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 10404 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 10405 }; 10406 10407 #endif 10408 #if defined(BCM_88650_A0) 10409 soc_field_info_t soc_XLP_XMAC_GMII_EEE_CTRLr_fields[] = { 10410 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, SOCF_SIG }, 10411 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE|SOCF_SIG }, 10412 { GMII_TXCLK_DISf, 1, 17, SOCF_SIG } 10413 }; 10414 10415 #endif 10416 #if defined(BCM_88650_B0) 10417 soc_field_info_t soc_XLP_XMAC_GMII_EEE_CTRL_BCM88650_B0r_fields[] = { 10418 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, SOCF_SIG }, 10419 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE|SOCF_SIG }, 10420 { GMII_TXCLK_DISf, 1, 17, SOCF_SIG } 10421 }; 10422 10423 #endif 10424 #if defined(BCM_88660_A0) 10425 soc_field_info_t soc_XLP_XMAC_GMII_EEE_CTRL_BCM88660_A0r_fields[] = { 10426 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, SOCF_SIG }, 10427 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE|SOCF_SIG }, 10428 { GMII_TXCLK_DISf, 1, 17, SOCF_SIG } 10429 }; 10430 10431 #endif 10432 #if defined(BCM_88650_A0) 10433 soc_field_info_t soc_XLP_XMAC_LH_HDR_3r_fields[] = { 10434 { LH_HDR_3f, 64, 0, SOCF_LE|SOCF_SIG }, 10435 { LH_HDR_3_HIf, 32, 32, SOCF_LE|SOCF_SIG }, 10436 { LH_HDR_3_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10437 }; 10438 10439 #endif 10440 #if defined(BCM_88650_B0) 10441 soc_field_info_t soc_XLP_XMAC_LH_HDR_3_BCM88650_B0r_fields[] = { 10442 { LH_HDR_3f, 64, 0, SOCF_LE|SOCF_SIG }, 10443 { LH_HDR_3_HIf, 32, 32, SOCF_LE|SOCF_SIG }, 10444 { LH_HDR_3_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10445 }; 10446 10447 #endif 10448 #if defined(BCM_88660_A0) 10449 soc_field_info_t soc_XLP_XMAC_LH_HDR_3_BCM88660_A0r_fields[] = { 10450 { LH_HDR_3f, 64, 0, SOCF_LE|SOCF_SIG }, 10451 { LH_HDR_3_HIf, 32, 32, SOCF_LE|SOCF_SIG }, 10452 { LH_HDR_3_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10453 }; 10454 10455 #endif 10456 #if defined(BCM_88650_A0) 10457 soc_field_info_t soc_XLP_XMAC_LLFC_CTRLr_fields[] = { 10458 { LLFC_CRC_IGNOREf, 1, 4, SOCF_SIG }, 10459 { LLFC_CUT_THROUGH_MODEf, 1, 3, SOCF_SIG }, 10460 { LLFC_IMGf, 8, 6, SOCF_LE|SOCF_SIG }, 10461 { LLFC_IN_IPG_ONLYf, 1, 2, SOCF_SIG }, 10462 { NO_SOM_FOR_CRC_LLFCf, 1, 5, SOCF_SIG }, 10463 { RX_LLFC_ENf, 1, 1, SOCF_SIG }, 10464 { TX_LLFC_ENf, 1, 0, SOCF_SIG } 10465 }; 10466 10467 #endif 10468 #if defined(BCM_88650_B0) 10469 soc_field_info_t soc_XLP_XMAC_LLFC_CTRL_BCM88650_B0r_fields[] = { 10470 { LLFC_CRC_IGNOREf, 1, 4, SOCF_SIG }, 10471 { LLFC_CUT_THROUGH_MODEf, 1, 3, SOCF_SIG }, 10472 { LLFC_IMGf, 8, 6, SOCF_LE|SOCF_SIG }, 10473 { LLFC_IN_IPG_ONLYf, 1, 2, SOCF_SIG }, 10474 { NO_SOM_FOR_CRC_LLFCf, 1, 5, SOCF_SIG }, 10475 { RX_LLFC_ENf, 1, 1, SOCF_SIG }, 10476 { TX_LLFC_ENf, 1, 0, SOCF_SIG } 10477 }; 10478 10479 #endif 10480 #if defined(BCM_88660_A0) 10481 soc_field_info_t soc_XLP_XMAC_LLFC_CTRL_BCM88660_A0r_fields[] = { 10482 { LLFC_CRC_IGNOREf, 1, 4, SOCF_SIG }, 10483 { LLFC_CUT_THROUGH_MODEf, 1, 3, SOCF_SIG }, 10484 { LLFC_IMGf, 8, 6, SOCF_LE|SOCF_SIG }, 10485 { LLFC_IN_IPG_ONLYf, 1, 2, SOCF_SIG }, 10486 { NO_SOM_FOR_CRC_LLFCf, 1, 5, SOCF_SIG }, 10487 { RX_LLFC_ENf, 1, 1, SOCF_SIG }, 10488 { TX_LLFC_ENf, 1, 0, SOCF_SIG } 10489 }; 10490 10491 #endif 10492 #if defined(BCM_88650_A0) 10493 soc_field_info_t soc_XLP_XMAC_MODEr_fields[] = { 10494 { HDR_MODEf, 3, 0, SOCF_LE|SOCF_SIG }, 10495 { NO_SOP_FOR_CRC_HGf, 1, 3, SOCF_SIG }, 10496 { SPEED_MODEf, 3, 4, SOCF_LE|SOCF_SIG } 10497 }; 10498 10499 #endif 10500 #if defined(BCM_88650_B0) 10501 soc_field_info_t soc_XLP_XMAC_MODE_BCM88650_B0r_fields[] = { 10502 { HDR_MODEf, 3, 0, SOCF_LE|SOCF_SIG }, 10503 { NO_SOP_FOR_CRC_HGf, 1, 3, SOCF_SIG }, 10504 { SPEED_MODEf, 3, 4, SOCF_LE|SOCF_SIG } 10505 }; 10506 10507 #endif 10508 #if defined(BCM_88660_A0) 10509 soc_field_info_t soc_XLP_XMAC_MODE_BCM88660_A0r_fields[] = { 10510 { HDR_MODEf, 3, 0, SOCF_LE|SOCF_SIG }, 10511 { NO_SOP_FOR_CRC_HGf, 1, 3, SOCF_SIG }, 10512 { SPEED_MODEf, 3, 4, SOCF_LE|SOCF_SIG } 10513 }; 10514 10515 #endif 10516 #if defined(BCM_88650_A0) 10517 soc_field_info_t soc_XLP_XMAC_OSTS_TIMESTAMP_ADJUSTr_fields[] = { 10518 { TS_ADJUSTf, 9, 0, SOCF_LE|SOCF_SIG }, 10519 { TS_ADJUST_DEMUX_DELAY_0f, 6, 9, SOCF_LE|SOCF_SIG }, 10520 { TS_ADJUST_DEMUX_DELAY_1f, 6, 15, SOCF_LE|SOCF_SIG }, 10521 { TS_ADJUST_DEMUX_DELAY_2f, 6, 21, SOCF_LE|SOCF_SIG }, 10522 { TS_ADJUST_DEMUX_DELAY_3f, 6, 27, SOCF_LE|SOCF_SIG }, 10523 { XMAC_OSTS_TIMESTAMP_ADJUST_HIf, 1, 32, SOCF_SIG }, 10524 { XMAC_OSTS_TIMESTAMP_ADJUST_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10525 }; 10526 10527 #endif 10528 #if defined(BCM_88650_B0) 10529 soc_field_info_t soc_XLP_XMAC_OSTS_TIMESTAMP_ADJUST_BCM88650_B0r_fields[] = { 10530 { TS_ADJUSTf, 9, 0, SOCF_LE|SOCF_SIG }, 10531 { TS_ADJUST_DEMUX_DELAY_0f, 6, 9, SOCF_LE|SOCF_SIG }, 10532 { TS_ADJUST_DEMUX_DELAY_1f, 6, 15, SOCF_LE|SOCF_SIG }, 10533 { TS_ADJUST_DEMUX_DELAY_2f, 6, 21, SOCF_LE|SOCF_SIG }, 10534 { TS_ADJUST_DEMUX_DELAY_3f, 6, 27, SOCF_LE|SOCF_SIG }, 10535 { XMAC_OSTS_TIMESTAMP_ADJUST_HIf, 1, 32, SOCF_SIG }, 10536 { XMAC_OSTS_TIMESTAMP_ADJUST_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10537 }; 10538 10539 #endif 10540 #if defined(BCM_88660_A0) 10541 soc_field_info_t soc_XLP_XMAC_OSTS_TIMESTAMP_ADJUST_BCM88660_A0r_fields[] = { 10542 { TS_ADJUSTf, 9, 0, SOCF_LE|SOCF_SIG }, 10543 { TS_ADJUST_DEMUX_DELAY_0f, 6, 9, SOCF_LE|SOCF_SIG }, 10544 { TS_ADJUST_DEMUX_DELAY_1f, 6, 15, SOCF_LE|SOCF_SIG }, 10545 { TS_ADJUST_DEMUX_DELAY_2f, 6, 21, SOCF_LE|SOCF_SIG }, 10546 { TS_ADJUST_DEMUX_DELAY_3f, 6, 27, SOCF_LE|SOCF_SIG }, 10547 { TS_USE_CS_OFFSETf, 1, 33, SOCF_SIG }, 10548 { XMAC_OSTS_TIMESTAMP_ADJUST_HIf, 2, 32, SOCF_LE|SOCF_SIG }, 10549 { XMAC_OSTS_TIMESTAMP_ADJUST_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10550 }; 10551 10552 #endif 10553 #if defined(BCM_88650_A0) 10554 soc_field_info_t soc_XLP_XMAC_PAUSE_CTRLr_fields[] = { 10555 { PAUSE_GMII_ON_TX_LINE_SIDEf, 1, 20, SOCF_SIG }, 10556 { PAUSE_REFRESH_ENf, 1, 16, SOCF_SIG }, 10557 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE|SOCF_SIG }, 10558 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE|SOCF_SIG }, 10559 { RX_PASS_PAUSEf, 1, 19, SOCF_SIG }, 10560 { RX_PAUSE_ENf, 1, 18, SOCF_SIG }, 10561 { TX_PAUSE_ENf, 1, 17, SOCF_SIG }, 10562 { XMAC_PAUSE_CTRL_HIf, 5, 32, SOCF_LE|SOCF_SIG }, 10563 { XMAC_PAUSE_CTRL_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10564 }; 10565 10566 #endif 10567 #if defined(BCM_88650_B0) 10568 soc_field_info_t soc_XLP_XMAC_PAUSE_CTRL_BCM88650_B0r_fields[] = { 10569 { PAUSE_GMII_ON_TX_LINE_SIDEf, 1, 20, SOCF_SIG }, 10570 { PAUSE_REFRESH_ENf, 1, 16, SOCF_SIG }, 10571 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE|SOCF_SIG }, 10572 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE|SOCF_SIG }, 10573 { RX_PASS_PAUSEf, 1, 19, SOCF_SIG }, 10574 { RX_PAUSE_ENf, 1, 18, SOCF_SIG }, 10575 { TX_PAUSE_ENf, 1, 17, SOCF_SIG }, 10576 { XMAC_PAUSE_CTRL_HIf, 5, 32, SOCF_LE|SOCF_SIG }, 10577 { XMAC_PAUSE_CTRL_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10578 }; 10579 10580 #endif 10581 #if defined(BCM_88660_A0) 10582 soc_field_info_t soc_XLP_XMAC_PAUSE_CTRL_BCM88660_A0r_fields[] = { 10583 { PAUSE_GMII_ON_TX_LINE_SIDEf, 1, 20, SOCF_SIG }, 10584 { PAUSE_REFRESH_ENf, 1, 16, SOCF_SIG }, 10585 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE|SOCF_SIG }, 10586 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE|SOCF_SIG }, 10587 { RX_PASS_PAUSEf, 1, 19, SOCF_SIG }, 10588 { RX_PAUSE_ENf, 1, 18, SOCF_SIG }, 10589 { TX_PAUSE_ENf, 1, 17, SOCF_SIG }, 10590 { XMAC_PAUSE_CTRL_HIf, 5, 32, SOCF_LE|SOCF_SIG }, 10591 { XMAC_PAUSE_CTRL_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10592 }; 10593 10594 #endif 10595 #if defined(BCM_88650_A0) 10596 soc_field_info_t soc_XLP_XMAC_PFC_CTRLr_fields[] = { 10597 { FORCE_PFC_XONf, 1, 33, SOCF_SIG }, 10598 { PFC_REFRESH_ENf, 1, 32, SOCF_SIG }, 10599 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE|SOCF_SIG }, 10600 { PFC_STATS_ENf, 1, 35, SOCF_SIG }, 10601 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE|SOCF_SIG }, 10602 { RX_PASS_PFCf, 1, 34, SOCF_SIG }, 10603 { RX_PFC_ENf, 1, 36, SOCF_SIG }, 10604 { TX_PFC_ENf, 1, 37, SOCF_SIG } 10605 }; 10606 10607 #endif 10608 #if defined(BCM_88650_B0) 10609 soc_field_info_t soc_XLP_XMAC_PFC_CTRL_BCM88650_B0r_fields[] = { 10610 { FORCE_PFC_XONf, 1, 33, SOCF_SIG }, 10611 { PFC_REFRESH_ENf, 1, 32, SOCF_SIG }, 10612 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE|SOCF_SIG }, 10613 { PFC_STATS_ENf, 1, 35, SOCF_SIG }, 10614 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE|SOCF_SIG }, 10615 { RX_PASS_PFCf, 1, 34, SOCF_SIG }, 10616 { RX_PFC_ENf, 1, 36, SOCF_SIG }, 10617 { TX_PFC_ENf, 1, 37, SOCF_SIG } 10618 }; 10619 10620 #endif 10621 #if defined(BCM_88660_A0) 10622 soc_field_info_t soc_XLP_XMAC_PFC_CTRL_BCM88660_A0r_fields[] = { 10623 { FORCE_PFC_XONf, 1, 33, SOCF_SIG }, 10624 { PFC_REFRESH_ENf, 1, 32, SOCF_SIG }, 10625 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE|SOCF_SIG }, 10626 { PFC_STATS_ENf, 1, 35, SOCF_SIG }, 10627 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE|SOCF_SIG }, 10628 { RX_PASS_PFCf, 1, 34, SOCF_SIG }, 10629 { RX_PFC_ENf, 1, 36, SOCF_SIG }, 10630 { TX_PFC_ENf, 1, 37, SOCF_SIG } 10631 }; 10632 10633 #endif 10634 #if defined(BCM_88650_A0) 10635 soc_field_info_t soc_XLP_XMAC_PFC_DAr_fields[] = { 10636 { PFC_MACDAf, 48, 0, SOCF_LE|SOCF_SIG }, 10637 { PFC_MACDA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 10638 { PFC_MACDA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10639 }; 10640 10641 #endif 10642 #if defined(BCM_88650_B0) 10643 soc_field_info_t soc_XLP_XMAC_PFC_DA_BCM88650_B0r_fields[] = { 10644 { PFC_MACDAf, 48, 0, SOCF_LE|SOCF_SIG }, 10645 { PFC_MACDA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 10646 { PFC_MACDA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10647 }; 10648 10649 #endif 10650 #if defined(BCM_88660_A0) 10651 soc_field_info_t soc_XLP_XMAC_PFC_DA_BCM88660_A0r_fields[] = { 10652 { PFC_MACDAf, 48, 0, SOCF_LE|SOCF_SIG }, 10653 { PFC_MACDA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 10654 { PFC_MACDA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10655 }; 10656 10657 #endif 10658 #if defined(BCM_88650_A0) 10659 soc_field_info_t soc_XLP_XMAC_PFC_OPCODEr_fields[] = { 10660 { PFC_OPCODEf, 16, 0, SOCF_LE|SOCF_SIG } 10661 }; 10662 10663 #endif 10664 #if defined(BCM_88650_B0) 10665 soc_field_info_t soc_XLP_XMAC_PFC_OPCODE_BCM88650_B0r_fields[] = { 10666 { PFC_OPCODEf, 16, 0, SOCF_LE|SOCF_SIG } 10667 }; 10668 10669 #endif 10670 #if defined(BCM_88660_A0) 10671 soc_field_info_t soc_XLP_XMAC_PFC_OPCODE_BCM88660_A0r_fields[] = { 10672 { PFC_OPCODEf, 16, 0, SOCF_LE|SOCF_SIG } 10673 }; 10674 10675 #endif 10676 #if defined(BCM_88650_A0) 10677 soc_field_info_t soc_XLP_XMAC_PFC_TYPEr_fields[] = { 10678 { PFC_ETH_TYPEf, 16, 0, SOCF_LE|SOCF_SIG } 10679 }; 10680 10681 #endif 10682 #if defined(BCM_88650_B0) 10683 soc_field_info_t soc_XLP_XMAC_PFC_TYPE_BCM88650_B0r_fields[] = { 10684 { PFC_ETH_TYPEf, 16, 0, SOCF_LE|SOCF_SIG } 10685 }; 10686 10687 #endif 10688 #if defined(BCM_88660_A0) 10689 soc_field_info_t soc_XLP_XMAC_PFC_TYPE_BCM88660_A0r_fields[] = { 10690 { PFC_ETH_TYPEf, 16, 0, SOCF_LE|SOCF_SIG } 10691 }; 10692 10693 #endif 10694 #if defined(BCM_88650_A0) 10695 soc_field_info_t soc_XLP_XMAC_RX_CTRLr_fields[] = { 10696 { PROCESS_VARIABLE_PREAMBLEf, 1, 12, SOCF_SIG }, 10697 { RECEIVE_18_BYTE_PKTSf, 1, 11, SOCF_SIG }, 10698 { RUNT_THRESHOLDf, 7, 4, SOCF_LE|SOCF_SIG }, 10699 { RX_ANY_STARTf, 1, 1, SOCF_SIG }, 10700 { RX_PASS_CTRLf, 1, 0, SOCF_SIG }, 10701 { STRICT_PREAMBLEf, 1, 3, SOCF_SIG }, 10702 { STRIP_CRCf, 1, 2, SOCF_SIG } 10703 }; 10704 10705 #endif 10706 #if defined(BCM_88650_B0) 10707 soc_field_info_t soc_XLP_XMAC_RX_CTRL_BCM88650_B0r_fields[] = { 10708 { PROCESS_VARIABLE_PREAMBLEf, 1, 12, SOCF_SIG }, 10709 { RECEIVE_18_BYTE_PKTSf, 1, 11, SOCF_SIG }, 10710 { RUNT_THRESHOLDf, 7, 4, SOCF_LE|SOCF_SIG }, 10711 { RX_ANY_STARTf, 1, 1, SOCF_SIG }, 10712 { RX_PASS_CTRLf, 1, 0, SOCF_SIG }, 10713 { STRICT_PREAMBLEf, 1, 3, SOCF_SIG }, 10714 { STRIP_CRCf, 1, 2, SOCF_SIG } 10715 }; 10716 10717 #endif 10718 #if defined(BCM_88660_A0) 10719 soc_field_info_t soc_XLP_XMAC_RX_CTRL_BCM88660_A0r_fields[] = { 10720 { PROCESS_VARIABLE_PREAMBLEf, 1, 12, SOCF_SIG }, 10721 { RECEIVE_18_BYTE_PKTSf, 1, 11, SOCF_SIG }, 10722 { RUNT_THRESHOLDf, 7, 4, SOCF_LE|SOCF_SIG }, 10723 { RX_ANY_STARTf, 1, 1, SOCF_SIG }, 10724 { RX_PASS_CTRLf, 1, 0, SOCF_SIG }, 10725 { STRICT_PREAMBLEf, 1, 3, SOCF_SIG }, 10726 { STRIP_CRCf, 1, 2, SOCF_SIG } 10727 }; 10728 10729 #endif 10730 #if defined(BCM_88650_A0) 10731 soc_field_info_t soc_XLP_XMAC_RX_LLFC_MSG_FIELDSr_fields[] = { 10732 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE|SOCF_SIG }, 10733 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE|SOCF_SIG }, 10734 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE|SOCF_SIG }, 10735 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE|SOCF_SIG } 10736 }; 10737 10738 #endif 10739 #if defined(BCM_88650_B0) 10740 soc_field_info_t soc_XLP_XMAC_RX_LLFC_MSG_FIELDS_BCM88650_B0r_fields[] = { 10741 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE|SOCF_SIG }, 10742 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE|SOCF_SIG }, 10743 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE|SOCF_SIG }, 10744 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE|SOCF_SIG } 10745 }; 10746 10747 #endif 10748 #if defined(BCM_88660_A0) 10749 soc_field_info_t soc_XLP_XMAC_RX_LLFC_MSG_FIELDS_BCM88660_A0r_fields[] = { 10750 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE|SOCF_SIG }, 10751 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE|SOCF_SIG }, 10752 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE|SOCF_SIG }, 10753 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE|SOCF_SIG } 10754 }; 10755 10756 #endif 10757 #if defined(BCM_88650_A0) 10758 soc_field_info_t soc_XLP_XMAC_RX_LSS_CTRLr_fields[] = { 10759 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, SOCF_SIG }, 10760 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, SOCF_SIG }, 10761 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, SOCF_SIG }, 10762 { LINK_INTERRUPTION_DISABLEf, 1, 3, SOCF_SIG }, 10763 { LOCAL_FAULT_DISABLEf, 1, 0, SOCF_SIG }, 10764 { REMOTE_FAULT_DISABLEf, 1, 1, SOCF_SIG }, 10765 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, SOCF_SIG }, 10766 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, SOCF_SIG } 10767 }; 10768 10769 #endif 10770 #if defined(BCM_88650_B0) 10771 soc_field_info_t soc_XLP_XMAC_RX_LSS_CTRL_BCM88650_B0r_fields[] = { 10772 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, SOCF_SIG }, 10773 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, SOCF_SIG }, 10774 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, SOCF_SIG }, 10775 { LINK_INTERRUPTION_DISABLEf, 1, 3, SOCF_SIG }, 10776 { LOCAL_FAULT_DISABLEf, 1, 0, SOCF_SIG }, 10777 { REMOTE_FAULT_DISABLEf, 1, 1, SOCF_SIG }, 10778 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, SOCF_SIG }, 10779 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, SOCF_SIG } 10780 }; 10781 10782 #endif 10783 #if defined(BCM_88660_A0) 10784 soc_field_info_t soc_XLP_XMAC_RX_LSS_CTRL_BCM88660_A0r_fields[] = { 10785 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, SOCF_SIG }, 10786 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, SOCF_SIG }, 10787 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, SOCF_SIG }, 10788 { LINK_INTERRUPTION_DISABLEf, 1, 3, SOCF_SIG }, 10789 { LOCAL_FAULT_DISABLEf, 1, 0, SOCF_SIG }, 10790 { REMOTE_FAULT_DISABLEf, 1, 1, SOCF_SIG }, 10791 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, SOCF_SIG }, 10792 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, SOCF_SIG } 10793 }; 10794 10795 #endif 10796 #if defined(BCM_88650_A0) 10797 soc_field_info_t soc_XLP_XMAC_RX_LSS_STATUSr_fields[] = { 10798 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO }, 10799 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO }, 10800 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO } 10801 }; 10802 10803 #endif 10804 #if defined(BCM_88650_B0) 10805 soc_field_info_t soc_XLP_XMAC_RX_LSS_STATUS_BCM88650_B0r_fields[] = { 10806 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO }, 10807 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO }, 10808 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO } 10809 }; 10810 10811 #endif 10812 #if defined(BCM_88660_A0) 10813 soc_field_info_t soc_XLP_XMAC_RX_LSS_STATUS_BCM88660_A0r_fields[] = { 10814 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO }, 10815 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO }, 10816 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO } 10817 }; 10818 10819 #endif 10820 #if defined(BCM_88650_A0) 10821 soc_field_info_t soc_XLP_XMAC_RX_MAC_SAr_fields[] = { 10822 { RX_SAf, 48, 0, SOCF_LE|SOCF_SIG }, 10823 { SA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 10824 { SA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10825 }; 10826 10827 #endif 10828 #if defined(BCM_88650_B0) 10829 soc_field_info_t soc_XLP_XMAC_RX_MAC_SA_BCM88650_B0r_fields[] = { 10830 { RX_SAf, 48, 0, SOCF_LE|SOCF_SIG }, 10831 { SA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 10832 { SA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10833 }; 10834 10835 #endif 10836 #if defined(BCM_88660_A0) 10837 soc_field_info_t soc_XLP_XMAC_RX_MAC_SA_BCM88660_A0r_fields[] = { 10838 { RX_SAf, 48, 0, SOCF_LE|SOCF_SIG }, 10839 { SA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 10840 { SA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10841 }; 10842 10843 #endif 10844 #if defined(BCM_88650_A0) 10845 soc_field_info_t soc_XLP_XMAC_RX_MAX_SIZEr_fields[] = { 10846 { RX_MAX_SIZEf, 14, 0, SOCF_LE|SOCF_SIG } 10847 }; 10848 10849 #endif 10850 #if defined(BCM_88650_B0) 10851 soc_field_info_t soc_XLP_XMAC_RX_MAX_SIZE_BCM88650_B0r_fields[] = { 10852 { RX_MAX_SIZEf, 14, 0, SOCF_LE|SOCF_SIG } 10853 }; 10854 10855 #endif 10856 #if defined(BCM_88660_A0) 10857 soc_field_info_t soc_XLP_XMAC_RX_MAX_SIZE_BCM88660_A0r_fields[] = { 10858 { RX_MAX_SIZEf, 14, 0, SOCF_LE|SOCF_SIG } 10859 }; 10860 10861 #endif 10862 #if defined(BCM_88650_A0) 10863 soc_field_info_t soc_XLP_XMAC_RX_VLAN_TAGr_fields[] = { 10864 { INNER_VLAN_TAGf, 16, 0, SOCF_LE|SOCF_SIG }, 10865 { INNER_VLAN_TAG_ENABLEf, 1, 32, SOCF_SIG }, 10866 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE|SOCF_SIG }, 10867 { OUTER_VLAN_TAG_ENABLEf, 1, 33, SOCF_SIG } 10868 }; 10869 10870 #endif 10871 #if defined(BCM_88650_B0) 10872 soc_field_info_t soc_XLP_XMAC_RX_VLAN_TAG_BCM88650_B0r_fields[] = { 10873 { INNER_VLAN_TAGf, 16, 0, SOCF_LE|SOCF_SIG }, 10874 { INNER_VLAN_TAG_ENABLEf, 1, 32, SOCF_SIG }, 10875 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE|SOCF_SIG }, 10876 { OUTER_VLAN_TAG_ENABLEf, 1, 33, SOCF_SIG } 10877 }; 10878 10879 #endif 10880 #if defined(BCM_88660_A0) 10881 soc_field_info_t soc_XLP_XMAC_RX_VLAN_TAG_BCM88660_A0r_fields[] = { 10882 { INNER_VLAN_TAGf, 16, 0, SOCF_LE|SOCF_SIG }, 10883 { INNER_VLAN_TAG_ENABLEf, 1, 32, SOCF_SIG }, 10884 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE|SOCF_SIG }, 10885 { OUTER_VLAN_TAG_ENABLEf, 1, 33, SOCF_SIG } 10886 }; 10887 10888 #endif 10889 #if defined(BCM_88650_A0) 10890 soc_field_info_t soc_XLP_XMAC_TX_CTRLr_fields[] = { 10891 { AVERAGE_IPGf, 7, 12, SOCF_LE|SOCF_SIG }, 10892 { CRC_MODEf, 2, 0, SOCF_LE|SOCF_SIG }, 10893 { DISCARDf, 1, 2, SOCF_SIG }, 10894 { PAD_ENf, 1, 4, SOCF_SIG }, 10895 { PAD_THRESHOLDf, 7, 5, SOCF_LE|SOCF_SIG }, 10896 { THROT_DENOMf, 8, 25, SOCF_LE|SOCF_SIG }, 10897 { THROT_NUMf, 6, 19, SOCF_LE|SOCF_SIG }, 10898 { TX_64_BYTE_BUFFER_ENf, 1, 37, SOCF_SIG }, 10899 { TX_ANY_STARTf, 1, 3, SOCF_SIG }, 10900 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE|SOCF_SIG }, 10901 { XMAC_TX_CTRL_HIf, 6, 32, SOCF_LE|SOCF_SIG }, 10902 { XMAC_TX_CTRL_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10903 }; 10904 10905 #endif 10906 #if defined(BCM_88650_B0) 10907 soc_field_info_t soc_XLP_XMAC_TX_CTRL_BCM88650_B0r_fields[] = { 10908 { AVERAGE_IPGf, 7, 12, SOCF_LE|SOCF_SIG }, 10909 { CRC_MODEf, 2, 0, SOCF_LE|SOCF_SIG }, 10910 { DISCARDf, 1, 2, SOCF_SIG }, 10911 { PAD_ENf, 1, 4, SOCF_SIG }, 10912 { PAD_THRESHOLDf, 7, 5, SOCF_LE|SOCF_SIG }, 10913 { THROT_DENOMf, 8, 25, SOCF_LE|SOCF_SIG }, 10914 { THROT_NUMf, 6, 19, SOCF_LE|SOCF_SIG }, 10915 { TX_64_BYTE_BUFFER_ENf, 1, 37, SOCF_SIG }, 10916 { TX_ANY_STARTf, 1, 3, SOCF_SIG }, 10917 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE|SOCF_SIG }, 10918 { XMAC_TX_CTRL_HIf, 6, 32, SOCF_LE|SOCF_SIG }, 10919 { XMAC_TX_CTRL_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10920 }; 10921 10922 #endif 10923 #if defined(BCM_88660_A0) 10924 soc_field_info_t soc_XLP_XMAC_TX_CTRL_BCM88660_A0r_fields[] = { 10925 { AVERAGE_IPGf, 7, 12, SOCF_LE|SOCF_SIG }, 10926 { CRC_MODEf, 2, 0, SOCF_LE|SOCF_SIG }, 10927 { DISCARDf, 1, 2, SOCF_SIG }, 10928 { PAD_ENf, 1, 4, SOCF_SIG }, 10929 { PAD_THRESHOLDf, 7, 5, SOCF_LE|SOCF_SIG }, 10930 { THROT_DENOMf, 8, 25, SOCF_LE|SOCF_SIG }, 10931 { THROT_NUMf, 6, 19, SOCF_LE|SOCF_SIG }, 10932 { TX_64_BYTE_BUFFER_ENf, 1, 37, SOCF_SIG }, 10933 { TX_ANY_STARTf, 1, 3, SOCF_SIG }, 10934 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE|SOCF_SIG }, 10935 { XMAC_TX_CTRL_HIf, 6, 32, SOCF_LE|SOCF_SIG }, 10936 { XMAC_TX_CTRL_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10937 }; 10938 10939 #endif 10940 #if defined(BCM_88650_A0) 10941 soc_field_info_t soc_XLP_XMAC_TX_FIFO_CREDITSr_fields[] = { 10942 { DUAL_PORT_TX_CREDITSf, 6, 6, SOCF_LE|SOCF_SIG }, 10943 { QUAD_PORT_TX_CREDITSf, 6, 0, SOCF_LE|SOCF_SIG }, 10944 { SINGLE_PORT_TX_CREDITSf, 6, 12, SOCF_LE|SOCF_SIG } 10945 }; 10946 10947 #endif 10948 #if defined(BCM_88650_B0) 10949 soc_field_info_t soc_XLP_XMAC_TX_FIFO_CREDITS_BCM88650_B0r_fields[] = { 10950 { DUAL_PORT_TX_CREDITSf, 6, 6, SOCF_LE|SOCF_SIG }, 10951 { QUAD_PORT_TX_CREDITSf, 6, 0, SOCF_LE|SOCF_SIG }, 10952 { SINGLE_PORT_TX_CREDITSf, 6, 12, SOCF_LE|SOCF_SIG } 10953 }; 10954 10955 #endif 10956 #if defined(BCM_88660_A0) 10957 soc_field_info_t soc_XLP_XMAC_TX_FIFO_CREDITS_BCM88660_A0r_fields[] = { 10958 { DUAL_PORT_TX_CREDITSf, 6, 6, SOCF_LE|SOCF_SIG }, 10959 { QUAD_PORT_TX_CREDITSf, 6, 0, SOCF_LE|SOCF_SIG }, 10960 { SINGLE_PORT_TX_CREDITSf, 6, 12, SOCF_LE|SOCF_SIG } 10961 }; 10962 10963 #endif 10964 #if defined(BCM_88650_A0) 10965 soc_field_info_t soc_XLP_XMAC_TX_LLFC_MSG_FIELDSr_fields[] = { 10966 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE|SOCF_SIG }, 10967 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE|SOCF_SIG }, 10968 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE|SOCF_SIG } 10969 }; 10970 10971 #endif 10972 #if defined(BCM_88650_B0) 10973 soc_field_info_t soc_XLP_XMAC_TX_LLFC_MSG_FIELDS_BCM88650_B0r_fields[] = { 10974 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE|SOCF_SIG }, 10975 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE|SOCF_SIG }, 10976 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE|SOCF_SIG } 10977 }; 10978 10979 #endif 10980 #if defined(BCM_88660_A0) 10981 soc_field_info_t soc_XLP_XMAC_TX_LLFC_MSG_FIELDS_BCM88660_A0r_fields[] = { 10982 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE|SOCF_SIG }, 10983 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE|SOCF_SIG }, 10984 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE|SOCF_SIG } 10985 }; 10986 10987 #endif 10988 #if defined(BCM_88650_A0) 10989 soc_field_info_t soc_XLP_XMAC_TX_MAC_SAr_fields[] = { 10990 { CTRL_SAf, 48, 0, SOCF_LE|SOCF_SIG }, 10991 { SA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 10992 { SA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 10993 }; 10994 10995 #endif 10996 #if defined(BCM_88650_B0) 10997 soc_field_info_t soc_XLP_XMAC_TX_MAC_SA_BCM88650_B0r_fields[] = { 10998 { CTRL_SAf, 48, 0, SOCF_LE|SOCF_SIG }, 10999 { SA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 11000 { SA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 11001 }; 11002 11003 #endif 11004 #if defined(BCM_88660_A0) 11005 soc_field_info_t soc_XLP_XMAC_TX_MAC_SA_BCM88660_A0r_fields[] = { 11006 { CTRL_SAf, 48, 0, SOCF_LE|SOCF_SIG }, 11007 { SA_HIf, 16, 32, SOCF_LE|SOCF_SIG }, 11008 { SA_LOf, 32, 0, SOCF_LE|SOCF_SIG } 11009 }; 11010 11011 #endif 11012 #if defined(BCM_88650_A0) 11013 soc_field_info_t soc_XLP_XMAC_TX_TIMESTAMP_FIFO_DATAr_fields[] = { 11014 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO }, 11015 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO }, 11016 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO } 11017 }; 11018 11019 #endif 11020 #if defined(BCM_88650_B0) 11021 soc_field_info_t soc_XLP_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM88650_B0r_fields[] = { 11022 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO }, 11023 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO }, 11024 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO } 11025 }; 11026 11027 #endif 11028 #if defined(BCM_88660_A0) 11029 soc_field_info_t soc_XLP_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM88660_A0r_fields[] = { 11030 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO }, 11031 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO }, 11032 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO } 11033 }; 11034 11035 #endif 11036 #if defined(BCM_88650_A0) 11037 soc_field_info_t soc_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUSr_fields[] = { 11038 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO } 11039 }; 11040 11041 #endif 11042 #if defined(BCM_88650_B0) 11043 soc_field_info_t soc_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88650_B0r_fields[] = { 11044 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO } 11045 }; 11046 11047 #endif 11048 #if defined(BCM_88660_A0) 11049 soc_field_info_t soc_XLP_XMAC_TX_TIMESTAMP_FIFO_STATUS_BCM88660_A0r_fields[] = { 11050 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO } 11051 }; 11052 11053 #endif 11054 #if defined(BCM_88650_A0) 11055 soc_field_info_t soc_XLP_XMAC_VERSION_IDr_fields[] = { 11056 { XMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 11057 }; 11058 11059 #endif 11060 #if defined(BCM_88650_B0) 11061 soc_field_info_t soc_XLP_XMAC_VERSION_ID_BCM88650_B0r_fields[] = { 11062 { XMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 11063 }; 11064 11065 #endif 11066 #if defined(BCM_88660_A0) 11067 soc_field_info_t soc_XLP_XMAC_VERSION_ID_BCM88660_A0r_fields[] = { 11068 { XMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 11069 }; 11070 11071 #endif 11072 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11073 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11074 defined(BCM_88732_A0) 11075 soc_field_info_t soc_XMAC_CLEAR_FIFO_STATUSr_fields[] = { 11076 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 11077 { CLEAR_RX_PKT_OVERFLOWf, 1, 0, SOCF_RO }, 11078 { CLEAR_TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO }, 11079 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 11080 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 11081 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 11082 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 11083 }; 11084 11085 #endif 11086 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11087 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11088 defined(BCM_56640_A0) 11089 soc_field_info_t soc_XMAC_CLEAR_FIFO_STATUS_BCM56640_A0r_fields[] = { 11090 { CLEAR_RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 11091 { CLEAR_RX_PKT_OVERFLOWf, 1, 0, SOCF_RO }, 11092 { CLEAR_TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO }, 11093 { CLEAR_TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 11094 { CLEAR_TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 11095 { CLEAR_TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 11096 { CLEAR_TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 11097 }; 11098 11099 #endif 11100 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11101 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11102 defined(BCM_88732_A0) 11103 soc_field_info_t soc_XMAC_CLEAR_RX_LSS_STATUSr_fields[] = { 11104 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 11105 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 11106 }; 11107 11108 #endif 11109 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 11110 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 11111 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 11112 defined(BCM_56850_A0) || defined(BCM_56860_A0) 11113 soc_field_info_t soc_XMAC_CLEAR_RX_LSS_STATUS_BCM56640_A0r_fields[] = { 11114 { CLEAR_LINK_INTERRUPTION_STATUSf, 1, 2, 0 }, 11115 { CLEAR_LOCAL_FAULT_STATUSf, 1, 0, 0 }, 11116 { CLEAR_REMOTE_FAULT_STATUSf, 1, 1, 0 } 11117 }; 11118 11119 #endif 11120 #if defined(BCM_56840_A0) || defined(BCM_88732_A0) 11121 soc_field_info_t soc_XMAC_CTRLr_fields[] = { 11122 { CORE_LOCAL_LPBKf, 1, 3, SOCF_SC }, 11123 { CORE_REMOTE_LPBKf, 1, 5, SOCF_SC }, 11124 { LINE_LOCAL_LPBKf, 1, 2, 0 }, 11125 { LINE_REMOTE_LPBKf, 1, 4, 0 }, 11126 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 11127 { REMOTE_LPBK_LEAK_ENBf, 1, 9, 0 }, 11128 { RS_SOFT_RESETf, 1, 10, 0 }, 11129 { RX_ENf, 1, 1, 0 }, 11130 { SOFT_RESETf, 1, 6, 0 }, 11131 { TX_ENf, 1, 0, 0 }, 11132 { XLGMII_ALIGN_ENBf, 1, 7, 0 } 11133 }; 11134 11135 #endif 11136 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11137 defined(BCM_56840_B0) 11138 soc_field_info_t soc_XMAC_CTRL_BCM56840_B0r_fields[] = { 11139 { CORE_LOCAL_LPBKf, 1, 3, SOCF_SC }, 11140 { CORE_REMOTE_LPBKf, 1, 5, SOCF_SC }, 11141 { LINE_LOCAL_LPBKf, 1, 2, 0 }, 11142 { LINE_REMOTE_LPBKf, 1, 4, 0 }, 11143 { LOCAL_LPBK_LEAK_ENBf, 1, 8, 0 }, 11144 { REMOTE_LPBK_LEAK_ENBf, 1, 9, 0 }, 11145 { RS_SOFT_RESETf, 1, 10, 0 }, 11146 { RX_ENf, 1, 1, 0 }, 11147 { SOFT_RESETf, 1, 6, 0 }, 11148 { TX_ENf, 1, 0, 0 }, 11149 { XGMII_IPG_CHECK_DISABLEf, 1, 11, 0 }, 11150 { XLGMII_ALIGN_ENBf, 1, 7, 0 } 11151 }; 11152 11153 #endif 11154 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11155 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11156 defined(BCM_88732_A0) 11157 soc_field_info_t soc_XMAC_EEE_CTRLr_fields[] = { 11158 { EEE_DISABLE_RX_PAUSE_ACTIVEf, 1, 3, SOCF_SC }, 11159 { EEE_DISABLE_TX_PAUSE_XOFFf, 1, 1, SOCF_SC }, 11160 { EEE_DISABLE_TX_PFC_XOFFf, 1, 2, SOCF_SC }, 11161 { EEE_ENf, 1, 0, 0 } 11162 }; 11163 11164 #endif 11165 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11166 defined(BCM_88732_A0) 11167 soc_field_info_t soc_XMAC_EEE_TIMERSr_fields[] = { 11168 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 11169 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE }, 11170 { XMAC_EEE_TIMERS_HIf, 16, 32, SOCF_LE }, 11171 { XMAC_EEE_TIMERS_LOf, 32, 0, SOCF_LE } 11172 }; 11173 11174 #endif 11175 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11176 soc_field_info_t soc_XMAC_EEE_TIMERS_BCM56440_A0r_fields[] = { 11177 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 11178 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 11179 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE }, 11180 { XMAC_EEE_TIMERS_HIf, 32, 32, SOCF_LE }, 11181 { XMAC_EEE_TIMERS_LOf, 32, 0, SOCF_LE } 11182 }; 11183 11184 #endif 11185 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11186 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11187 defined(BCM_56640_A0) 11188 soc_field_info_t soc_XMAC_EEE_TIMERS_BCM56640_A0r_fields[] = { 11189 { EEE_DELAY_ENTRY_TIMERf, 32, 0, SOCF_LE }, 11190 { EEE_REF_COUNTf, 16, 48, SOCF_LE }, 11191 { EEE_WAKE_TIMERf, 16, 32, SOCF_LE }, 11192 { XMAC_EEE_TIMERS_HIf, 32, 32, SOCF_LE }, 11193 { XMAC_EEE_TIMERS_LOf, 32, 0, SOCF_LE } 11194 }; 11195 11196 #endif 11197 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11198 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11199 defined(BCM_88732_A0) 11200 soc_field_info_t soc_XMAC_FIFO_STATUSr_fields[] = { 11201 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 11202 { RX_PKT_OVERFLOWf, 1, 0, SOCF_RO }, 11203 { TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO }, 11204 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 11205 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 11206 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 11207 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 11208 }; 11209 11210 #endif 11211 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11212 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11213 defined(BCM_56640_A0) 11214 soc_field_info_t soc_XMAC_FIFO_STATUS_BCM56640_A0r_fields[] = { 11215 { LINK_STATUSf, 1, 7, SOCF_RO }, 11216 { RX_MSG_OVERFLOWf, 1, 1, SOCF_RO }, 11217 { RX_PKT_OVERFLOWf, 1, 0, SOCF_RO }, 11218 { TX_HCFC_MSG_OVERFLOWf, 1, 4, SOCF_RO }, 11219 { TX_LLFC_MSG_OVERFLOWf, 1, 5, SOCF_RO }, 11220 { TX_PKT_OVERFLOWf, 1, 3, SOCF_RO }, 11221 { TX_PKT_UNDERFLOWf, 1, 2, SOCF_RO }, 11222 { TX_TS_FIFO_OVERFLOWf, 1, 6, SOCF_RO } 11223 }; 11224 11225 #endif 11226 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11227 soc_field_info_t soc_XMAC_GMII_EEE_CTRLr_fields[] = { 11228 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 11229 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE }, 11230 { GMII_TXCLK_DISf, 1, 17, 0 } 11231 }; 11232 11233 #endif 11234 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11235 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11236 defined(BCM_56640_A0) 11237 soc_field_info_t soc_XMAC_GMII_EEE_CTRL_BCM56640_A0r_fields[] = { 11238 { GMII_LPI_PREDICT_MODE_ENf, 1, 16, 0 }, 11239 { GMII_LPI_PREDICT_THRESHOLDf, 16, 0, SOCF_LE }, 11240 { GMII_TXCLK_DISf, 1, 17, 0 } 11241 }; 11242 11243 #endif 11244 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11245 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11246 defined(BCM_88732_A0) 11247 soc_field_info_t soc_XMAC_HCFC_CTRLr_fields[] = { 11248 { HCFC_CRC_IGNOREf, 1, 2, 0 }, 11249 { HCFC_IMGf, 8, 13, SOCF_LE }, 11250 { HCFC_IN_IPG_ONLYf, 1, 4, 0 }, 11251 { HCFC_SOMf, 8, 5, SOCF_LE }, 11252 { NO_SOM_FOR_CRC_HCFCf, 1, 3, 0 }, 11253 { RX_HCFC_ENf, 1, 1, 0 }, 11254 { TX_HCFC_ENf, 1, 0, 0 } 11255 }; 11256 11257 #endif 11258 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11259 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11260 defined(BCM_88732_A0) 11261 soc_field_info_t soc_XMAC_LLFC_CTRLr_fields[] = { 11262 { LLFC_CRC_IGNOREf, 1, 4, 0 }, 11263 { LLFC_CUT_THROUGH_MODEf, 1, 3, 0 }, 11264 { LLFC_IMGf, 8, 6, SOCF_LE }, 11265 { LLFC_IN_IPG_ONLYf, 1, 2, 0 }, 11266 { NO_SOM_FOR_CRC_LLFCf, 1, 5, 0 }, 11267 { RX_LLFC_ENf, 1, 1, 0 }, 11268 { TX_LLFC_ENf, 1, 0, 0 } 11269 }; 11270 11271 #endif 11272 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11273 soc_field_info_t soc_XMAC_MACSEC_CTRLr_fields[] = { 11274 { MACSEC_PROG_TX_CRCf, 32, 3, SOCF_LE }, 11275 { MACSEC_TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 11276 { MACSEC_TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 11277 { MACSEC_TX_LAUNCH_ENf, 1, 0, 0 }, 11278 { XMAC_MACSEC_CTRL_HIf, 3, 32, SOCF_LE }, 11279 { XMAC_MACSEC_CTRL_LOf, 32, 0, SOCF_LE } 11280 }; 11281 11282 #endif 11283 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11284 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11285 defined(BCM_56640_A0) 11286 soc_field_info_t soc_XMAC_MACSEC_CTRL_BCM56640_A0r_fields[] = { 11287 { MACSEC_PROG_TX_CRCf, 32, 3, SOCF_LE }, 11288 { MACSEC_TX_CRC_CORRUPTION_MODEf, 1, 2, 0 }, 11289 { MACSEC_TX_CRC_CORRUPT_ENf, 1, 1, 0 }, 11290 { MACSEC_TX_LAUNCH_ENf, 1, 0, 0 }, 11291 { XMAC_MACSEC_CTRL_HIf, 3, 32, SOCF_LE }, 11292 { XMAC_MACSEC_CTRL_LOf, 32, 0, SOCF_LE } 11293 }; 11294 11295 #endif 11296 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11297 defined(BCM_88732_A0) 11298 soc_field_info_t soc_XMAC_MODEr_fields[] = { 11299 { HDR_MODEf, 3, 0, SOCF_LE }, 11300 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 } 11301 }; 11302 11303 #endif 11304 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11305 soc_field_info_t soc_XMAC_MODE_BCM56440_A0r_fields[] = { 11306 { HDR_MODEf, 3, 0, SOCF_LE }, 11307 { NO_SOP_FOR_CRC_HGf, 1, 3, 0 }, 11308 { SPEED_MODEf, 3, 4, SOCF_LE } 11309 }; 11310 11311 #endif 11312 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11313 soc_field_info_t soc_XMAC_OSTS_TIMESTAMP_ADJUSTr_fields[] = { 11314 { TS_ADJUSTf, 9, 0, SOCF_LE }, 11315 { TS_ADJUST_DEMUX_DELAY_0f, 6, 9, SOCF_LE }, 11316 { TS_ADJUST_DEMUX_DELAY_1f, 6, 15, SOCF_LE }, 11317 { TS_ADJUST_DEMUX_DELAY_2f, 6, 21, SOCF_LE }, 11318 { TS_ADJUST_DEMUX_DELAY_3f, 6, 27, SOCF_LE }, 11319 { XMAC_OSTS_TIMESTAMP_ADJUST_HIf, 1, 32, 0 }, 11320 { XMAC_OSTS_TIMESTAMP_ADJUST_LOf, 32, 0, SOCF_LE } 11321 }; 11322 11323 #endif 11324 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11325 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11326 defined(BCM_56640_A0) 11327 soc_field_info_t soc_XMAC_OSTS_TIMESTAMP_ADJUST_BCM56640_A0r_fields[] = { 11328 { TS_ADJUSTf, 9, 0, SOCF_LE }, 11329 { TS_ADJUST_DEMUX_DELAY_0f, 6, 9, SOCF_LE }, 11330 { TS_ADJUST_DEMUX_DELAY_1f, 6, 15, SOCF_LE }, 11331 { TS_ADJUST_DEMUX_DELAY_2f, 6, 21, SOCF_LE }, 11332 { TS_ADJUST_DEMUX_DELAY_3f, 6, 27, SOCF_LE }, 11333 { TS_USE_CS_OFFSETf, 1, 33, 0 }, 11334 { XMAC_OSTS_TIMESTAMP_ADJUST_HIf, 2, 32, SOCF_LE }, 11335 { XMAC_OSTS_TIMESTAMP_ADJUST_LOf, 32, 0, SOCF_LE } 11336 }; 11337 11338 #endif 11339 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11340 defined(BCM_88732_A0) 11341 soc_field_info_t soc_XMAC_PAUSE_CTRLr_fields[] = { 11342 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 11343 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 11344 { RX_PASS_PAUSEf, 1, 19, 0 }, 11345 { RX_PAUSE_ENf, 1, 18, 0 }, 11346 { TX_PAUSE_ENf, 1, 17, 0 } 11347 }; 11348 11349 #endif 11350 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11351 soc_field_info_t soc_XMAC_PAUSE_CTRL_BCM56440_A0r_fields[] = { 11352 { PAUSE_GMII_ON_TX_LINE_SIDEf, 1, 20, 0 }, 11353 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 11354 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 11355 { RX_PASS_PAUSEf, 1, 19, 0 }, 11356 { RX_PAUSE_ENf, 1, 18, 0 }, 11357 { TX_PAUSE_ENf, 1, 17, 0 } 11358 }; 11359 11360 #endif 11361 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11362 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11363 defined(BCM_56640_A0) 11364 soc_field_info_t soc_XMAC_PAUSE_CTRL_BCM56640_A0r_fields[] = { 11365 { PAUSE_GMII_ON_TX_LINE_SIDEf, 1, 20, 0 }, 11366 { PAUSE_REFRESH_ENf, 1, 16, 0 }, 11367 { PAUSE_REFRESH_TIMERf, 16, 0, SOCF_LE }, 11368 { PAUSE_XOFF_TIMERf, 16, 21, SOCF_LE }, 11369 { RX_PASS_PAUSEf, 1, 19, 0 }, 11370 { RX_PAUSE_ENf, 1, 18, 0 }, 11371 { TX_PAUSE_ENf, 1, 17, 0 }, 11372 { XMAC_PAUSE_CTRL_HIf, 5, 32, SOCF_LE }, 11373 { XMAC_PAUSE_CTRL_LOf, 32, 0, SOCF_LE } 11374 }; 11375 11376 #endif 11377 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11378 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11379 defined(BCM_88732_A0) 11380 soc_field_info_t soc_XMAC_PFC_CTRLr_fields[] = { 11381 { FORCE_PFC_XONf, 1, 33, 0 }, 11382 { PFC_REFRESH_ENf, 1, 32, 0 }, 11383 { PFC_REFRESH_TIMERf, 16, 0, SOCF_LE }, 11384 { PFC_STATS_ENf, 1, 35, 0 }, 11385 { PFC_XOFF_TIMERf, 16, 16, SOCF_LE }, 11386 { RX_PASS_PFCf, 1, 34, 0 }, 11387 { RX_PFC_ENf, 1, 36, 0 }, 11388 { TX_PFC_ENf, 1, 37, 0 } 11389 }; 11390 11391 #endif 11392 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11393 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11394 defined(BCM_88732_A0) 11395 soc_field_info_t soc_XMAC_PFC_DAr_fields[] = { 11396 { PFC_MACDAf, 48, 0, SOCF_LE }, 11397 { PFC_MACDA_HIf, 16, 32, SOCF_LE }, 11398 { PFC_MACDA_LOf, 32, 0, SOCF_LE } 11399 }; 11400 11401 #endif 11402 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11403 defined(BCM_88732_A0) 11404 soc_field_info_t soc_XMAC_RX_CTRLr_fields[] = { 11405 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 11406 { RX_ANY_STARTf, 1, 1, 0 }, 11407 { RX_PASS_CTRLf, 1, 0, 0 }, 11408 { STRICT_PREAMBLEf, 1, 3, 0 }, 11409 { STRIP_CRCf, 1, 2, 0 } 11410 }; 11411 11412 #endif 11413 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11414 soc_field_info_t soc_XMAC_RX_CTRL_BCM56440_A0r_fields[] = { 11415 { PROCESS_VARIABLE_PREAMBLEf, 1, 12, 0 }, 11416 { RECEIVE_18_BYTE_PKTSf, 1, 11, 0 }, 11417 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 11418 { RX_ANY_STARTf, 1, 1, 0 }, 11419 { RX_PASS_CTRLf, 1, 0, 0 }, 11420 { STRICT_PREAMBLEf, 1, 3, 0 }, 11421 { STRIP_CRCf, 1, 2, 0 } 11422 }; 11423 11424 #endif 11425 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11426 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11427 defined(BCM_56640_A0) 11428 soc_field_info_t soc_XMAC_RX_CTRL_BCM56640_A0r_fields[] = { 11429 { PROCESS_VARIABLE_PREAMBLEf, 1, 12, 0 }, 11430 { RECEIVE_18_BYTE_PKTSf, 1, 11, 0 }, 11431 { RUNT_THRESHOLDf, 7, 4, SOCF_LE }, 11432 { RX_ANY_STARTf, 1, 1, 0 }, 11433 { RX_PASS_CTRLf, 1, 0, 0 }, 11434 { STRICT_PREAMBLEf, 1, 3, 0 }, 11435 { STRIP_CRCf, 1, 2, 0 } 11436 }; 11437 11438 #endif 11439 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11440 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11441 defined(BCM_88732_A0) 11442 soc_field_info_t soc_XMAC_RX_LLFC_MSG_FIELDSr_fields[] = { 11443 { RX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 11444 { RX_LLFC_FC_OBJ_PHYSICALf, 4, 20, SOCF_LE }, 11445 { RX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE }, 11446 { RX_LLFC_MSG_TYPE_PHYSICALf, 8, 12, SOCF_LE } 11447 }; 11448 11449 #endif 11450 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11451 defined(BCM_88732_A0) 11452 soc_field_info_t soc_XMAC_RX_LSS_CTRLr_fields[] = { 11453 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 11454 { REMOTE_FAULT_DISABLEf, 1, 1, 0 } 11455 }; 11456 11457 #endif 11458 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11459 soc_field_info_t soc_XMAC_RX_LSS_CTRL_BCM56440_A0r_fields[] = { 11460 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 11461 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 11462 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 11463 }; 11464 11465 #endif 11466 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 11467 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 11468 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 11469 defined(BCM_56850_A0) 11470 soc_field_info_t soc_XMAC_RX_LSS_CTRL_BCM56640_A0r_fields[] = { 11471 { DROP_TX_DATA_ON_LINK_INTERRUPTf, 1, 6, 0 }, 11472 { DROP_TX_DATA_ON_LOCAL_FAULTf, 1, 4, 0 }, 11473 { DROP_TX_DATA_ON_REMOTE_FAULTf, 1, 5, 0 }, 11474 { LINK_INTERRUPTION_DISABLEf, 1, 3, 0 }, 11475 { LOCAL_FAULT_DISABLEf, 1, 0, 0 }, 11476 { REMOTE_FAULT_DISABLEf, 1, 1, 0 }, 11477 { RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWNf, 1, 7, 0 }, 11478 { USE_EXTERNAL_FAULTS_FOR_TXf, 1, 2, 0 } 11479 }; 11480 11481 #endif 11482 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11483 defined(BCM_88732_A0) 11484 soc_field_info_t soc_XMAC_RX_LSS_STATUSr_fields[] = { 11485 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO|SOCF_RES }, 11486 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO|SOCF_RES } 11487 }; 11488 11489 #endif 11490 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11491 soc_field_info_t soc_XMAC_RX_LSS_STATUS_BCM56440_A0r_fields[] = { 11492 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO }, 11493 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO } 11494 }; 11495 11496 #endif 11497 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 11498 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 11499 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 11500 defined(BCM_56850_A0) || defined(BCM_56860_A0) 11501 soc_field_info_t soc_XMAC_RX_LSS_STATUS_BCM56640_A0r_fields[] = { 11502 { LINK_INTERRUPTION_STATUSf, 1, 2, SOCF_RO }, 11503 { LOCAL_FAULT_STATUSf, 1, 0, SOCF_RO }, 11504 { REMOTE_FAULT_STATUSf, 1, 1, SOCF_RO } 11505 }; 11506 11507 #endif 11508 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11509 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11510 defined(BCM_88732_A0) 11511 soc_field_info_t soc_XMAC_RX_MAC_SAr_fields[] = { 11512 { RX_SAf, 48, 0, SOCF_LE }, 11513 { SA_HIf, 16, 32, SOCF_LE }, 11514 { SA_LOf, 32, 0, SOCF_LE } 11515 }; 11516 11517 #endif 11518 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11519 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11520 defined(BCM_88732_A0) 11521 soc_field_info_t soc_XMAC_RX_MAX_SIZEr_fields[] = { 11522 { RX_MAX_SIZEf, 14, 0, SOCF_LE } 11523 }; 11524 11525 #endif 11526 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11527 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11528 defined(BCM_88732_A0) 11529 soc_field_info_t soc_XMAC_RX_VLAN_TAGr_fields[] = { 11530 { INNER_VLAN_TAGf, 16, 0, SOCF_LE }, 11531 { INNER_VLAN_TAG_ENABLEf, 1, 32, 0 }, 11532 { OUTER_VLAN_TAGf, 16, 16, SOCF_LE }, 11533 { OUTER_VLAN_TAG_ENABLEf, 1, 33, 0 } 11534 }; 11535 11536 #endif 11537 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11538 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11539 defined(BCM_88732_A0) 11540 soc_field_info_t soc_XMAC_SPARE1r_fields[] = { 11541 { RSVDf, 2, 0, SOCF_LE } 11542 }; 11543 11544 #endif 11545 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11546 defined(BCM_88732_A0) 11547 soc_field_info_t soc_XMAC_TX_CTRLr_fields[] = { 11548 { AVERAGE_IPGf, 5, 12, SOCF_LE }, 11549 { CRC_MODEf, 2, 0, SOCF_LE }, 11550 { DISCARDf, 1, 2, 0 }, 11551 { PAD_ENf, 1, 4, 0 }, 11552 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 11553 { THROT_DENOMf, 8, 23, SOCF_LE }, 11554 { THROT_NUMf, 6, 17, SOCF_LE }, 11555 { TX_ANY_STARTf, 1, 3, 0 } 11556 }; 11557 11558 #endif 11559 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11560 soc_field_info_t soc_XMAC_TX_CTRL_BCM56440_A0r_fields[] = { 11561 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 11562 { CRC_MODEf, 2, 0, SOCF_LE }, 11563 { DISCARDf, 1, 2, 0 }, 11564 { PAD_ENf, 1, 4, 0 }, 11565 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 11566 { THROT_DENOMf, 8, 25, SOCF_LE }, 11567 { THROT_NUMf, 6, 19, SOCF_LE }, 11568 { TX_64BYTE_BUFFER_ENf, 1, 37, 0 }, 11569 { TX_ANY_STARTf, 1, 3, 0 }, 11570 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 11571 { XMAC_TX_CTRL_HIf, 6, 32, SOCF_LE }, 11572 { XMAC_TX_CTRL_LOf, 32, 0, SOCF_LE } 11573 }; 11574 11575 #endif 11576 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11577 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11578 defined(BCM_56640_A0) 11579 soc_field_info_t soc_XMAC_TX_CTRL_BCM56640_A0r_fields[] = { 11580 { AVERAGE_IPGf, 7, 12, SOCF_LE }, 11581 { CRC_MODEf, 2, 0, SOCF_LE }, 11582 { DISCARDf, 1, 2, 0 }, 11583 { PAD_ENf, 1, 4, 0 }, 11584 { PAD_THRESHOLDf, 7, 5, SOCF_LE }, 11585 { THROT_DENOMf, 8, 25, SOCF_LE }, 11586 { THROT_NUMf, 6, 19, SOCF_LE }, 11587 { TX_64BYTE_BUFFER_ENf, 1, 37, 0 }, 11588 { TX_ANY_STARTf, 1, 3, 0 }, 11589 { TX_PREAMBLE_LENGTHf, 4, 33, SOCF_LE }, 11590 { XMAC_TX_CTRL_HIf, 6, 32, SOCF_LE }, 11591 { XMAC_TX_CTRL_LOf, 32, 0, SOCF_LE } 11592 }; 11593 11594 #endif 11595 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11596 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11597 defined(BCM_88732_A0) 11598 soc_field_info_t soc_XMAC_TX_FIFO_CREDITSr_fields[] = { 11599 { DUAL_PORT_TX_CREDITSf, 6, 6, SOCF_LE }, 11600 { QUAD_PORT_TX_CREDITSf, 6, 0, SOCF_LE }, 11601 { SINGLE_PORT_TX_CREDITSf, 6, 12, SOCF_LE } 11602 }; 11603 11604 #endif 11605 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11606 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11607 defined(BCM_56640_A0) 11608 soc_field_info_t soc_XMAC_TX_FIFO_CREDITS_BCM56640_A0r_fields[] = { 11609 { DUAL_PORT_TX_CREDITSf, 6, 6, SOCF_LE }, 11610 { QUAD_PORT_TX_CREDITSf, 6, 0, SOCF_LE }, 11611 { SINGLE_PORT_TX_CREDITSf, 6, 12, SOCF_LE } 11612 }; 11613 11614 #endif 11615 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11616 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11617 defined(BCM_88732_A0) 11618 soc_field_info_t soc_XMAC_TX_LLFC_MSG_FIELDSr_fields[] = { 11619 { LLFC_XOFF_TIMEf, 16, 12, SOCF_LE }, 11620 { TX_LLFC_FC_OBJ_LOGICALf, 4, 8, SOCF_LE }, 11621 { TX_LLFC_MSG_TYPE_LOGICALf, 8, 0, SOCF_LE } 11622 }; 11623 11624 #endif 11625 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11626 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11627 defined(BCM_88732_A0) 11628 soc_field_info_t soc_XMAC_TX_MAC_SAr_fields[] = { 11629 { CTRL_SAf, 48, 0, SOCF_LE }, 11630 { SA_HIf, 16, 32, SOCF_LE }, 11631 { SA_LOf, 32, 0, SOCF_LE } 11632 }; 11633 11634 #endif 11635 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11636 defined(BCM_88732_A0) 11637 soc_field_info_t soc_XMAC_TX_TIMESTAMP_FIFO_DATAr_fields[] = { 11638 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO } 11639 }; 11640 11641 #endif 11642 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11643 soc_field_info_t soc_XMAC_TX_TIMESTAMP_FIFO_DATA_BCM56440_A0r_fields[] = { 11644 { SEQUENCE_IDf, 16, 32, SOCF_LE|SOCF_RO }, 11645 { TIME_STAMPf, 32, 0, SOCF_LE|SOCF_RO }, 11646 { TS_ENTRY_VALIDf, 1, 48, SOCF_RO } 11647 }; 11648 11649 #endif 11650 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11651 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11652 defined(BCM_88732_A0) 11653 soc_field_info_t soc_XMAC_TX_TIMESTAMP_FIFO_STATUSr_fields[] = { 11654 { ENTRY_COUNTf, 3, 0, SOCF_LE|SOCF_RO } 11655 }; 11656 11657 #endif 11658 #if defined(BCM_56640_A0) 11659 soc_field_info_t soc_XMAC_VERSION_IDr_fields[] = { 11660 { XMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 11661 }; 11662 11663 #endif 11664 #if defined(BCM_56340_A0) 11665 soc_field_info_t soc_XMAC_VERSION_ID_BCM56340_A0r_fields[] = { 11666 { XMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 11667 }; 11668 11669 #endif 11670 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 11671 defined(BCM_56450_B1) 11672 soc_field_info_t soc_XMAC_VERSION_ID_BCM56450_A0r_fields[] = { 11673 { XMAC_VERSIONf, 16, 0, SOCF_LE|SOCF_RO } 11674 }; 11675 11676 #endif 11677 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 11678 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 11679 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 11680 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11681 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11682 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11683 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11684 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11685 defined(BCM_56820_A0) 11686 soc_field_info_t soc_XMODIDr_fields[] = { 11687 { MODID0f, 8, 0, SOCF_LE }, 11688 { MODID1f, 8, 8, SOCF_LE }, 11689 { MODID2f, 8, 16, SOCF_LE }, 11690 { MODID3f, 8, 24, SOCF_LE } 11691 }; 11692 11693 #endif 11694 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 11695 defined(BCM_56450_B1) 11696 soc_field_info_t soc_XMODID_BCM56450_A0r_fields[] = { 11697 { MODID0f, 8, 0, SOCF_LE }, 11698 { MODID1f, 8, 8, SOCF_LE }, 11699 { MODID2f, 8, 16, SOCF_LE }, 11700 { MODID3f, 8, 24, SOCF_LE } 11701 }; 11702 11703 #endif 11704 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11705 defined(BCM_88732_A0) 11706 soc_field_info_t soc_XMODID_BCM56840_A0r_fields[] = { 11707 { MODID0f, 8, 0, SOCF_LE }, 11708 { MODID1f, 8, 8, SOCF_LE }, 11709 { MODID2f, 8, 16, SOCF_LE }, 11710 { MODID3f, 8, 24, SOCF_LE } 11711 }; 11712 11713 #endif 11714 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 11715 defined(BCM_56334_B0) || defined(BCM_56524_A0) || \ 11716 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11717 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11718 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11719 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11720 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11721 defined(BCM_56820_A0) 11722 soc_field_info_t soc_XMODID_ENr_fields[] = { 11723 { DUAL_MODID_ENf, 1, 4, 0 }, 11724 { MODID_EN0f, 1, 0, 0 }, 11725 { MODID_EN1f, 1, 1, 0 }, 11726 { MODID_EN2f, 1, 2, 0 }, 11727 { MODID_EN3f, 1, 3, 0 } 11728 }; 11729 11730 #endif 11731 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11732 soc_field_info_t soc_XMODID_EN_BCM56440_A0r_fields[] = { 11733 { MODID_EN0f, 1, 0, 0 }, 11734 { MODID_EN1f, 1, 1, 0 }, 11735 { MODID_EN2f, 1, 2, 0 }, 11736 { MODID_EN3f, 1, 3, 0 } 11737 }; 11738 11739 #endif 11740 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 11741 defined(BCM_56450_B1) 11742 soc_field_info_t soc_XMODID_EN_BCM56450_A0r_fields[] = { 11743 { MODID_EN0f, 1, 0, 0 }, 11744 { MODID_EN1f, 1, 1, 0 }, 11745 { MODID_EN2f, 1, 2, 0 }, 11746 { MODID_EN3f, 1, 3, 0 } 11747 }; 11748 11749 #endif 11750 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11751 defined(BCM_88732_A0) 11752 soc_field_info_t soc_XMODID_EN_BCM56840_A0r_fields[] = { 11753 { MODID_EN0f, 1, 0, 0 }, 11754 { MODID_EN1f, 1, 1, 0 }, 11755 { MODID_EN2f, 1, 2, 0 }, 11756 { MODID_EN3f, 1, 3, 0 } 11757 }; 11758 11759 #endif 11760 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11761 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11762 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11763 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11764 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11765 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11766 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11767 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11768 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11769 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11770 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11771 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11772 defined(BCM_88732_A0) 11773 soc_field_info_t soc_XPAUSE_D0r_fields[] = { 11774 { DATA_BYTES_0_3f, 32, 0, SOCF_LE } 11775 }; 11776 11777 #endif 11778 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11779 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11780 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11781 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11782 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11783 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11784 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11785 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11786 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11787 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11788 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11789 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11790 defined(BCM_88732_A0) 11791 soc_field_info_t soc_XPAUSE_D1r_fields[] = { 11792 { DATA_BYTES_4_7f, 32, 0, SOCF_LE } 11793 }; 11794 11795 #endif 11796 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11797 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11798 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11799 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11800 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11801 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11802 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11803 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11804 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11805 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11806 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11807 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11808 defined(BCM_88732_A0) 11809 soc_field_info_t soc_XPAUSE_D2r_fields[] = { 11810 { DATA_BYTES_8_11f, 32, 0, SOCF_LE } 11811 }; 11812 11813 #endif 11814 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11815 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11816 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11817 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11818 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11819 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11820 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11821 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11822 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11823 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11824 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11825 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11826 defined(BCM_88732_A0) 11827 soc_field_info_t soc_XPAUSE_D3r_fields[] = { 11828 { DATA_BYTES_12_15f, 32, 0, SOCF_LE } 11829 }; 11830 11831 #endif 11832 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11833 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11834 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11835 soc_field_info_t soc_XPAUSE_D0_BCM56640_A0r_fields[] = { 11836 { DATA_BYTES_0_3f, 32, 0, SOCF_LE } 11837 }; 11838 11839 #endif 11840 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11841 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11842 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11843 soc_field_info_t soc_XPAUSE_D1_BCM56640_A0r_fields[] = { 11844 { DATA_BYTES_4_7f, 32, 0, SOCF_LE } 11845 }; 11846 11847 #endif 11848 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11849 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11850 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11851 soc_field_info_t soc_XPAUSE_D2_BCM56640_A0r_fields[] = { 11852 { DATA_BYTES_8_11f, 32, 0, SOCF_LE } 11853 }; 11854 11855 #endif 11856 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11857 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11858 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11859 soc_field_info_t soc_XPAUSE_D3_BCM56640_A0r_fields[] = { 11860 { DATA_BYTES_12_15f, 32, 0, SOCF_LE } 11861 }; 11862 11863 #endif 11864 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11865 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11866 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11867 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11868 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11869 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11870 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11871 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11872 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11873 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11874 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11875 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11876 defined(BCM_88732_A0) 11877 soc_field_info_t soc_XPAUSE_MH0r_fields[] = { 11878 { MH_BYTES_0_3f, 32, 0, SOCF_LE } 11879 }; 11880 11881 #endif 11882 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11883 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11884 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11885 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11886 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11887 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11888 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11889 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11890 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11891 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11892 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11893 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11894 defined(BCM_88732_A0) 11895 soc_field_info_t soc_XPAUSE_MH1r_fields[] = { 11896 { MH_BYTES_4_7f, 32, 0, SOCF_LE } 11897 }; 11898 11899 #endif 11900 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11901 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11902 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11903 soc_field_info_t soc_XPAUSE_MH0_BCM56640_A0r_fields[] = { 11904 { MH_BYTES_0_3f, 32, 0, SOCF_LE } 11905 }; 11906 11907 #endif 11908 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11909 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11910 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11911 soc_field_info_t soc_XPAUSE_MH1_BCM56640_A0r_fields[] = { 11912 { MH_BYTES_4_7f, 32, 0, SOCF_LE } 11913 }; 11914 11915 #endif 11916 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11917 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11918 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11919 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11920 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11921 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11922 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11923 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11924 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11925 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11926 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11927 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11928 defined(BCM_88732_A0) 11929 soc_field_info_t soc_XPAUSE_RX_DA_LSr_fields[] = { 11930 { DAf, 32, 0, SOCF_LE } 11931 }; 11932 11933 #endif 11934 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11935 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11936 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11937 soc_field_info_t soc_XPAUSE_RX_DA_LS_BCM56640_A0r_fields[] = { 11938 { DAf, 32, 0, SOCF_LE } 11939 }; 11940 11941 #endif 11942 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11943 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11944 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11945 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11946 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11947 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11948 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11949 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11950 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11951 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11952 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11953 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11954 defined(BCM_88732_A0) 11955 soc_field_info_t soc_XPAUSE_RX_DA_MSr_fields[] = { 11956 { DAf, 16, 0, SOCF_LE } 11957 }; 11958 11959 #endif 11960 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11961 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11962 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11963 soc_field_info_t soc_XPAUSE_RX_DA_MS_BCM56640_A0r_fields[] = { 11964 { DAf, 16, 0, SOCF_LE } 11965 }; 11966 11967 #endif 11968 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11969 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11970 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11971 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11972 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11973 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 11974 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 11975 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 11976 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 11977 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 11978 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 11979 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11980 defined(BCM_88732_A0) 11981 soc_field_info_t soc_XPAUSE_RX_LENGTH_TYPEr_fields[] = { 11982 { LENGTH_TYPEf, 16, 0, SOCF_LE } 11983 }; 11984 11985 #endif 11986 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 11987 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 11988 defined(BCM_56640_A0) || defined(BCM_56850_A0) 11989 soc_field_info_t soc_XPAUSE_RX_LENGTH_TYPE_BCM56640_A0r_fields[] = { 11990 { LENGTH_TYPEf, 16, 0, SOCF_LE } 11991 }; 11992 11993 #endif 11994 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 11995 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 11996 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 11997 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 11998 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 11999 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 12000 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 12001 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 12002 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 12003 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 12004 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 12005 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 12006 defined(BCM_88732_A0) 12007 soc_field_info_t soc_XPAUSE_RX_OPCODEr_fields[] = { 12008 { OPCODEf, 16, 0, SOCF_LE } 12009 }; 12010 12011 #endif 12012 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 12013 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 12014 defined(BCM_56640_A0) || defined(BCM_56850_A0) 12015 soc_field_info_t soc_XPAUSE_RX_OPCODE_BCM56640_A0r_fields[] = { 12016 { OPCODEf, 16, 0, SOCF_LE } 12017 }; 12018 12019 #endif 12020 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 12021 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 12022 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 12023 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 12024 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 12025 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 12026 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 12027 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 12028 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 12029 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 12030 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 12031 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 12032 defined(BCM_88732_A0) 12033 soc_field_info_t soc_XPAUSE_TX_PKT_XOFF_VALr_fields[] = { 12034 { XOFF_VALf, 16, 0, SOCF_LE } 12035 }; 12036 12037 #endif 12038 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 12039 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 12040 defined(BCM_56640_A0) || defined(BCM_56850_A0) 12041 soc_field_info_t soc_XPAUSE_TX_PKT_XOFF_VAL_BCM56640_A0r_fields[] = { 12042 { XOFF_VALf, 16, 0, SOCF_LE } 12043 }; 12044 12045 #endif 12046 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 12047 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 12048 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 12049 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 12050 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 12051 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 12052 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 12053 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 12054 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 12055 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 12056 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 12057 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 12058 defined(BCM_88732_A0) 12059 soc_field_info_t soc_XPAUSE_WATCHDOG_INIT_VALr_fields[] = { 12060 { INIT_VALf, 16, 0, SOCF_LE } 12061 }; 12062 12063 #endif 12064 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 12065 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 12066 defined(BCM_56640_A0) || defined(BCM_56850_A0) 12067 soc_field_info_t soc_XPAUSE_WATCHDOG_INIT_VAL_BCM56640_A0r_fields[] = { 12068 { INIT_VALf, 16, 0, SOCF_LE } 12069 }; 12070 12071 #endif 12072 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 12073 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 12074 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 12075 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 12076 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 12077 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 12078 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 12079 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 12080 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 12081 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 12082 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 12083 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 12084 defined(BCM_88732_A0) 12085 soc_field_info_t soc_XPAUSE_WATCHDOG_THRESHr_fields[] = { 12086 { THRESHf, 16, 0, SOCF_LE } 12087 }; 12088 12089 #endif 12090 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 12091 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 12092 defined(BCM_56640_A0) || defined(BCM_56850_A0) 12093 soc_field_info_t soc_XPAUSE_WATCHDOG_THRESH_BCM56640_A0r_fields[] = { 12094 { THRESHf, 16, 0, SOCF_LE } 12095 }; 12096 12097 #endif 12098 #if defined(BCM_56504_A0) 12099 soc_field_info_t soc_XPORT_CONFIGr_fields[] = { 12100 { BIGMAC_RESETf, 1, 12, SOCF_RES }, 12101 { E2E_HOL_ENf, 1, 3, 0 }, 12102 { E2E_IBP_ENf, 1, 4, 0 }, 12103 { HIGIG_MODEf, 1, 1, 0 }, 12104 { HONOR_PAUSE_FOR_E2Ef, 1, 11, 0 }, 12105 { MY_MODIDf, 6, 5, SOCF_LE }, 12106 { XPAUSE_ENf, 1, 2, 0 }, 12107 { XPORT_ENf, 1, 0, 0 } 12108 }; 12109 12110 #endif 12111 #if defined(BCM_56142_A0) 12112 soc_field_info_t soc_XPORT_CONFIG_BCM56142_A0r_fields[] = { 12113 { BIGMAC_RESETf, 1, 13, 0 }, 12114 { E2E_IBP_ENf, 1, 4, 0 }, 12115 { HIGIG2_MODEf, 1, 15, 0 }, 12116 { HIGIG_MODEf, 1, 1, 0 }, 12117 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 12118 { MY_MODIDf, 7, 5, SOCF_LE }, 12119 { WAIT_FOR_5_EP_CELLSf, 1, 20, 0 }, 12120 { XAUI1_LANE_MODEf, 1, 19, 0 }, 12121 { XAUI_1000BASEX_MODEf, 1, 18, 0 }, 12122 { XPAUSE_ENf, 1, 2, 0 }, 12123 { XPAUSE_RX_ENf, 1, 16, 0 }, 12124 { XPAUSE_TX_ENf, 1, 17, 0 }, 12125 { XPORT_ENf, 1, 0, 0 } 12126 }; 12127 12128 #endif 12129 #if defined(BCM_56260_A0) 12130 soc_field_info_t soc_XPORT_CONFIG_BCM56260_A0r_fields[] = { 12131 { HIGIG2_MODEf, 1, 2, 0 }, 12132 { HIGIG_MODEf, 1, 0, 0 }, 12133 { MH_INBANDf, 1, 1, 0 }, 12134 { PASS_CONTROL_FRAMEf, 1, 4, 0 }, 12135 { PASS_PAUSE_FRAMEf, 1, 5, 0 }, 12136 { PASS_PFC_FRAMEf, 1, 6, 0 }, 12137 { SIRIUS_PARSER_DISABLEf, 1, 3, 0 } 12138 }; 12139 12140 #endif 12141 #if defined(BCM_56260_B0) || defined(BCM_56270_A0) 12142 soc_field_info_t soc_XPORT_CONFIG_BCM56260_B0r_fields[] = { 12143 { HIGIG2_MODEf, 1, 2, 0 }, 12144 { HIGIG_MODEf, 1, 0, 0 }, 12145 { MH_INBANDf, 1, 1, 0 }, 12146 { MII_LPI_CODEf, 1, 7, 0 }, 12147 { PASS_CONTROL_FRAMEf, 1, 4, 0 }, 12148 { PASS_PAUSE_FRAMEf, 1, 5, 0 }, 12149 { PASS_PFC_FRAMEf, 1, 6, 0 }, 12150 { SHIM_FIFO_SIZEf, 2, 8, SOCF_LE }, 12151 { SIRIUS_PARSER_DISABLEf, 1, 3, 0 } 12152 }; 12153 12154 #endif 12155 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) 12156 soc_field_info_t soc_XPORT_CONFIG_BCM56334_A0r_fields[] = { 12157 { BIGMAC_RESETf, 1, 13, 0 }, 12158 { E2E_HOL_ENf, 1, 3, 0 }, 12159 { E2E_IBP_ENf, 1, 4, 0 }, 12160 { HIGIG2_MODEf, 1, 15, 0 }, 12161 { HIGIG_MODEf, 1, 1, 0 }, 12162 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 12163 { LLFC_ENf, 1, 14, 0 }, 12164 { MY_MODIDf, 7, 5, SOCF_LE }, 12165 { PPP_ENABLEf, 1, 21, 0 }, 12166 { WAIT_FOR_5_EP_CELLSf, 1, 20, 0 }, 12167 { XAUI1_LANE_MODEf, 1, 19, 0 }, 12168 { XAUI_1000BASEX_MODEf, 1, 18, 0 }, 12169 { XPAUSE_ENf, 1, 2, 0 }, 12170 { XPAUSE_RX_ENf, 1, 16, 0 }, 12171 { XPAUSE_TX_ENf, 1, 17, 0 }, 12172 { XPORT_ENf, 1, 0, 0 } 12173 }; 12174 12175 #endif 12176 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12177 soc_field_info_t soc_XPORT_CONFIG_BCM56440_A0r_fields[] = { 12178 { DRAIN_CONDITION_ENABLEf, 1, 19, 0 }, 12179 { HIGIG2_MODEf, 1, 15, 0 }, 12180 { HIGIG_MODEf, 1, 1, 0 }, 12181 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 12182 { LLFC_ENf, 1, 14, 0 }, 12183 { MH_INBANDf, 1, 13, 0 }, 12184 { MY_MODIDf, 8, 20, SOCF_LE }, 12185 { PFC_ENABLEf, 1, 18, 0 }, 12186 { XPAUSE_ENf, 1, 2, 0 }, 12187 { XPAUSE_RX_ENf, 1, 16, 0 }, 12188 { XPAUSE_TX_ENf, 1, 17, 0 }, 12189 { XP_RES_0f, 1, 0, SOCF_RES }, 12190 { XP_RES_4_3f, 9, 3, SOCF_LE|SOCF_RES } 12191 }; 12192 12193 #endif 12194 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12195 defined(BCM_56450_B1) 12196 soc_field_info_t soc_XPORT_CONFIG_BCM56450_A0r_fields[] = { 12197 { CREDIT_RESETf, 1, 28, SOCF_SC }, 12198 { DRAIN_CONDITION_ENABLEf, 1, 19, 0 }, 12199 { HIGIG2_MODEf, 1, 15, 0 }, 12200 { HIGIG_MODEf, 1, 1, 0 }, 12201 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 12202 { LLFC_ENf, 1, 14, 0 }, 12203 { MH_INBANDf, 1, 13, 0 }, 12204 { MY_MODIDf, 8, 20, SOCF_LE }, 12205 { PFC_ENABLEf, 1, 18, 0 }, 12206 { RESERVED_14f, 1, 11, SOCF_RES }, 12207 { SIRIUS_PARSER_DISABLEf, 1, 29, 0 }, 12208 { XPAUSE_ENf, 1, 2, 0 }, 12209 { XPAUSE_RX_ENf, 1, 16, 0 }, 12210 { XPAUSE_TX_ENf, 1, 17, 0 }, 12211 { XP_RES_0f, 1, 0, SOCF_RES }, 12212 { XP_RES_4_3f, 8, 3, SOCF_LE|SOCF_RES } 12213 }; 12214 12215 #endif 12216 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) || \ 12217 defined(BCM_56514_A0) 12218 soc_field_info_t soc_XPORT_CONFIG_BCM56504_B0r_fields[] = { 12219 { BIGMAC_RESETf, 1, 12, 0 }, 12220 { E2E_HOL_ENf, 1, 3, 0 }, 12221 { E2E_IBP_ENf, 1, 4, 0 }, 12222 { HIGIG_MODEf, 1, 1, 0 }, 12223 { HONOR_PAUSE_FOR_E2Ef, 1, 11, 0 }, 12224 { MY_MODIDf, 6, 5, SOCF_LE }, 12225 { XPAUSE_ENf, 1, 2, 0 }, 12226 { XPORT_ENf, 1, 0, 0 } 12227 }; 12228 12229 #endif 12230 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 12231 defined(BCM_56680_A0) || defined(BCM_56680_B0) 12232 soc_field_info_t soc_XPORT_CONFIG_BCM56624_A0r_fields[] = { 12233 { BIGMAC_RESETf, 1, 13, 0 }, 12234 { E2E_HOL_ENf, 1, 3, 0 }, 12235 { E2E_IBP_ENf, 1, 4, 0 }, 12236 { HIGIG2_MODEf, 1, 15, 0 }, 12237 { HIGIG_MODEf, 1, 1, 0 }, 12238 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 12239 { LLFC_ENf, 1, 14, 0 }, 12240 { MY_MODIDf, 7, 5, SOCF_LE }, 12241 { WAIT_FOR_5_EP_CELLSf, 1, 20, 0 }, 12242 { XAUI1_LANE_MODEf, 1, 19, 0 }, 12243 { XAUI_1000BASEX_MODEf, 1, 18, 0 }, 12244 { XPAUSE_ENf, 1, 2, 0 }, 12245 { XPAUSE_RX_ENf, 1, 16, 0 }, 12246 { XPAUSE_TX_ENf, 1, 17, 0 }, 12247 { XPORT_ENf, 1, 0, 0 } 12248 }; 12249 12250 #endif 12251 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 12252 defined(BCM_56685_A0) 12253 soc_field_info_t soc_XPORT_CONFIG_BCM56634_A0r_fields[] = { 12254 { BIGMAC_RESETf, 1, 13, 0 }, 12255 { E2E_HOL_ENf, 1, 3, 0 }, 12256 { E2E_IBP_ENf, 1, 4, 0 }, 12257 { HIGIG2_MODEf, 1, 15, 0 }, 12258 { HIGIG_MODEf, 1, 1, 0 }, 12259 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 12260 { LLFC_ENf, 1, 14, 0 }, 12261 { MY_MODIDf, 7, 5, SOCF_LE }, 12262 { PPP_ENABLEf, 1, 21, SOCF_RES }, 12263 { WAIT_FOR_5_EP_CELLSf, 1, 20, 0 }, 12264 { XAUI1_LANE_MODEf, 1, 19, 0 }, 12265 { XAUI_1000BASEX_MODEf, 1, 18, 0 }, 12266 { XPAUSE_ENf, 1, 2, 0 }, 12267 { XPAUSE_RX_ENf, 1, 16, 0 }, 12268 { XPAUSE_TX_ENf, 1, 17, 0 }, 12269 { XPORT_ENf, 1, 0, 0 } 12270 }; 12271 12272 #endif 12273 #if defined(BCM_56524_B0) || defined(BCM_56634_B0) || \ 12274 defined(BCM_56685_B0) 12275 soc_field_info_t soc_XPORT_CONFIG_BCM56634_B0r_fields[] = { 12276 { BIGMAC_RESETf, 1, 13, 0 }, 12277 { E2E_HOL_ENf, 1, 3, 0 }, 12278 { E2E_IBP_ENf, 1, 4, 0 }, 12279 { HIGIG2_MODEf, 1, 15, 0 }, 12280 { HIGIG_MODEf, 1, 1, 0 }, 12281 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 12282 { LLFC_ENf, 1, 14, 0 }, 12283 { MY_MODIDf, 7, 5, SOCF_LE }, 12284 { PPP_ENABLEf, 1, 21, SOCF_RES }, 12285 { UNIMAC_HD_ECO_ENABLEf, 1, 19, 0 }, 12286 { WAIT_FOR_5_EP_CELLSf, 1, 20, 0 }, 12287 { XAUI1_LANE_MODEf, 1, 19, 0 }, 12288 { XAUI_1000BASEX_MODEf, 1, 18, 0 }, 12289 { XPAUSE_ENf, 1, 2, 0 }, 12290 { XPAUSE_RX_ENf, 1, 16, 0 }, 12291 { XPAUSE_TX_ENf, 1, 17, 0 }, 12292 { XPORT_ENf, 1, 0, 0 } 12293 }; 12294 12295 #endif 12296 #if defined(BCM_56800_A0) 12297 soc_field_info_t soc_XPORT_CONFIG_BCM56800_A0r_fields[] = { 12298 { BIGMAC_RESETf, 1, 13, 0 }, 12299 { E2E_HOL_ENf, 1, 3, 0 }, 12300 { E2E_IBP_ENf, 1, 4, 0 }, 12301 { HIGIG2_MODEf, 1, 15, 0 }, 12302 { HIGIG_MODEf, 1, 1, 0 }, 12303 { HONOR_PAUSE_FOR_E2Ef, 1, 12, 0 }, 12304 { LLFC_ENf, 1, 14, 0 }, 12305 { MY_MODIDf, 7, 5, SOCF_LE }, 12306 { XPAUSE_ENf, 1, 2, 0 }, 12307 { XPAUSE_RX_ENf, 1, 16, 0 }, 12308 { XPAUSE_TX_ENf, 1, 17, 0 }, 12309 { XPORT_ENf, 1, 0, 0 } 12310 }; 12311 12312 #endif 12313 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 12314 soc_field_info_t soc_XPORT_CONFIG_BCM56820_A0r_fields[] = { 12315 { BIGMAC_RESETf, 1, 14, 0 }, 12316 { E2E_HOL_ENf, 1, 3, 0 }, 12317 { E2E_IBP_ENf, 1, 4, 0 }, 12318 { HIGIG2_MODEf, 1, 16, 0 }, 12319 { HIGIG_MODEf, 1, 1, 0 }, 12320 { HONOR_PAUSE_FOR_E2Ef, 1, 13, 0 }, 12321 { LLFC_ENf, 1, 15, 0 }, 12322 { MY_MODIDf, 8, 5, SOCF_LE }, 12323 { WAIT_FOR_5_EP_CELLSf, 1, 21, 0 }, 12324 { XAUI1_LANE_MODEf, 1, 20, 0 }, 12325 { XAUI_1000BASEX_MODEf, 1, 19, 0 }, 12326 { XPAUSE_ENf, 1, 2, 0 }, 12327 { XPAUSE_RX_ENf, 1, 17, 0 }, 12328 { XPAUSE_TX_ENf, 1, 18, 0 }, 12329 { XPORT_ENf, 1, 0, 0 } 12330 }; 12331 12332 #endif 12333 #if defined(BCM_88270_A0) 12334 soc_field_info_t soc_XPORT_CONFIG_BCM88270_A0r_fields[] = { 12335 { MII_LPI_CODEf, 1, 2, 0 }, 12336 { SHIM_FIFO_SIZEf, 2, 0, SOCF_LE } 12337 }; 12338 12339 #endif 12340 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12341 soc_field_info_t soc_XPORT_ECC_CONTROLr_fields[] = { 12342 { MIB_RSC_MEM_ENf, 1, 2, 0 }, 12343 { MIB_TSC_MEM_ENf, 1, 1, 0 }, 12344 { RXFIFO_MEM_ENf, 1, 3, 0 }, 12345 { TXFIFO_MEM_ENf, 1, 0, 0 } 12346 }; 12347 12348 #endif 12349 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 12350 defined(BCM_56270_A0) 12351 soc_field_info_t soc_XPORT_ECC_CONTROL_BCM56260_A0r_fields[] = { 12352 { MIB_RSC_MEM_ENf, 1, 2, 0 }, 12353 { MIB_TSC_MEM_ENf, 1, 1, 0 }, 12354 { RXFIFO_MEM_ENf, 1, 3, 0 }, 12355 { TXFIFO_MEM_ENf, 1, 0, 0 } 12356 }; 12357 12358 #endif 12359 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12360 defined(BCM_56450_B1) 12361 soc_field_info_t soc_XPORT_ECC_CONTROL_BCM56450_A0r_fields[] = { 12362 { MIB_RSC_MEM_ENf, 1, 2, 0 }, 12363 { MIB_TSC_MEM_ENf, 1, 1, 0 }, 12364 { RXFIFO_MEM_ENf, 1, 3, 0 }, 12365 { TXFIFO_MEM_ENf, 1, 0, 0 } 12366 }; 12367 12368 #endif 12369 #if defined(BCM_88270_A0) 12370 soc_field_info_t soc_XPORT_ECC_CONTROL_BCM88270_A0r_fields[] = { 12371 { MIB_RSC_MEM_ENf, 1, 2, 0 }, 12372 { MIB_TSC_MEM_ENf, 1, 1, 0 } 12373 }; 12374 12375 #endif 12376 #if defined(BCM_88270_A0) 12377 soc_field_info_t soc_XPORT_EEE_DURATION_TIMER_PULSEr_fields[] = { 12378 { CNT_VALUEf, 13, 0, SOCF_LE } 12379 }; 12380 12381 #endif 12382 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12383 soc_field_info_t soc_XPORT_FORCE_DOUBLE_BIT_ERRORr_fields[] = { 12384 { MIB_RSC_MEM0f, 1, 5, SOCF_RES }, 12385 { MIB_RSC_MEM1f, 1, 6, SOCF_RES }, 12386 { MIB_RSC_MEM2f, 1, 7, SOCF_RES }, 12387 { MIB_RSC_MEM3f, 1, 8, SOCF_RES }, 12388 { MIB_RSC_MEM4f, 1, 9, SOCF_RES }, 12389 { MIB_TSC_MEM0f, 1, 1, SOCF_RES }, 12390 { MIB_TSC_MEM1f, 1, 2, SOCF_RES }, 12391 { MIB_TSC_MEM2f, 1, 3, SOCF_RES }, 12392 { MIB_TSC_MEM3f, 1, 4, SOCF_RES }, 12393 { RXFIFO_MEM0f, 1, 10, SOCF_RES }, 12394 { RXFIFO_MEM1f, 1, 11, SOCF_RES }, 12395 { RXFIFO_MEM2f, 1, 12, SOCF_RES }, 12396 { RXFIFO_MEM3f, 1, 13, SOCF_RES }, 12397 { RXFIFO_MEM4f, 1, 14, SOCF_RES }, 12398 { TXFIFO_MEMf, 1, 0, SOCF_RES } 12399 }; 12400 12401 #endif 12402 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 12403 defined(BCM_56270_A0) 12404 soc_field_info_t soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56260_A0r_fields[] = { 12405 { MIB_RSC_MEM0f, 1, 5, SOCF_RES }, 12406 { MIB_RSC_MEM1f, 1, 6, SOCF_RES }, 12407 { MIB_RSC_MEM2f, 1, 7, SOCF_RES }, 12408 { MIB_RSC_MEM3f, 1, 8, SOCF_RES }, 12409 { MIB_RSC_MEM4f, 1, 9, SOCF_RES }, 12410 { MIB_TSC_MEM0f, 1, 1, SOCF_RES }, 12411 { MIB_TSC_MEM1f, 1, 2, SOCF_RES }, 12412 { MIB_TSC_MEM2f, 1, 3, SOCF_RES }, 12413 { MIB_TSC_MEM3f, 1, 4, SOCF_RES }, 12414 { RXFIFO_MEMf, 1, 10, SOCF_RES }, 12415 { TXFIFO_MEMf, 1, 0, SOCF_RES } 12416 }; 12417 12418 #endif 12419 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12420 defined(BCM_56450_B1) 12421 soc_field_info_t soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM56450_A0r_fields[] = { 12422 { MIB_RSC_MEM0f, 1, 5, SOCF_RES }, 12423 { MIB_RSC_MEM1f, 1, 6, SOCF_RES }, 12424 { MIB_RSC_MEM2f, 1, 7, SOCF_RES }, 12425 { MIB_RSC_MEM3f, 1, 8, SOCF_RES }, 12426 { MIB_RSC_MEM4f, 1, 9, SOCF_RES }, 12427 { MIB_TSC_MEM0f, 1, 1, SOCF_RES }, 12428 { MIB_TSC_MEM1f, 1, 2, SOCF_RES }, 12429 { MIB_TSC_MEM2f, 1, 3, SOCF_RES }, 12430 { MIB_TSC_MEM3f, 1, 4, SOCF_RES }, 12431 { RXFIFO_MEM0f, 1, 10, SOCF_RES }, 12432 { RXFIFO_MEM1f, 1, 11, SOCF_RES }, 12433 { RXFIFO_MEM2f, 1, 12, SOCF_RES }, 12434 { RXFIFO_MEM3f, 1, 13, SOCF_RES }, 12435 { RXFIFO_MEM4f, 1, 14, SOCF_RES }, 12436 { TXFIFO_MEMf, 1, 0, SOCF_RES } 12437 }; 12438 12439 #endif 12440 #if defined(BCM_88270_A0) 12441 soc_field_info_t soc_XPORT_FORCE_DOUBLE_BIT_ERROR_BCM88270_A0r_fields[] = { 12442 { MIB_RSC_MEM0f, 1, 5, 0 }, 12443 { MIB_RSC_MEM1f, 1, 6, 0 }, 12444 { MIB_RSC_MEM2f, 1, 7, 0 }, 12445 { MIB_RSC_MEM3f, 1, 8, 0 }, 12446 { MIB_RSC_MEM4f, 1, 9, 0 }, 12447 { MIB_TSC_MEM0f, 1, 1, 0 }, 12448 { MIB_TSC_MEM1f, 1, 2, 0 }, 12449 { MIB_TSC_MEM2f, 1, 3, 0 }, 12450 { MIB_TSC_MEM3f, 1, 4, 0 } 12451 }; 12452 12453 #endif 12454 #if defined(BCM_88270_A0) 12455 soc_field_info_t soc_XPORT_FORCE_SINGLE_BIT_ERRORr_fields[] = { 12456 { MIB_RSC_MEM0f, 1, 5, 0 }, 12457 { MIB_RSC_MEM1f, 1, 6, 0 }, 12458 { MIB_RSC_MEM2f, 1, 7, 0 }, 12459 { MIB_RSC_MEM3f, 1, 8, 0 }, 12460 { MIB_RSC_MEM4f, 1, 9, 0 }, 12461 { MIB_TSC_MEM0f, 1, 1, 0 }, 12462 { MIB_TSC_MEM1f, 1, 2, 0 }, 12463 { MIB_TSC_MEM2f, 1, 3, 0 }, 12464 { MIB_TSC_MEM3f, 1, 4, 0 } 12465 }; 12466 12467 #endif 12468 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12469 soc_field_info_t soc_XPORT_INTR_ENABLEr_fields[] = { 12470 { MIB_RSC_MEM0_ERRf, 1, 5, SOCF_RO }, 12471 { MIB_RSC_MEM1_ERRf, 1, 6, SOCF_RO }, 12472 { MIB_RSC_MEM2_ERRf, 1, 7, SOCF_RO }, 12473 { MIB_RSC_MEM3_ERRf, 1, 8, SOCF_RO }, 12474 { MIB_RSC_MEM4_ERRf, 1, 9, SOCF_RO }, 12475 { MIB_TSC_MEM0_ERRf, 1, 1, SOCF_RO }, 12476 { MIB_TSC_MEM1_ERRf, 1, 2, SOCF_RO }, 12477 { MIB_TSC_MEM2_ERRf, 1, 3, SOCF_RO }, 12478 { MIB_TSC_MEM3_ERRf, 1, 4, SOCF_RO }, 12479 { RXFIFO_MEM0_ERRf, 1, 10, SOCF_RO }, 12480 { RXFIFO_MEM1_ERRf, 1, 11, SOCF_RO }, 12481 { RXFIFO_MEM2_ERRf, 1, 12, SOCF_RO }, 12482 { RXFIFO_MEM3_ERRf, 1, 13, SOCF_RO }, 12483 { RXFIFO_MEM4_ERRf, 1, 14, SOCF_RO }, 12484 { TXFIFO_MEM_ERRf, 1, 0, SOCF_RO } 12485 }; 12486 12487 #endif 12488 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 12489 defined(BCM_56270_A0) 12490 soc_field_info_t soc_XPORT_INTR_ENABLE_BCM56260_A0r_fields[] = { 12491 { MIB_RSC_MEM0_ERRf, 1, 5, 0 }, 12492 { MIB_RSC_MEM1_ERRf, 1, 6, 0 }, 12493 { MIB_RSC_MEM2_ERRf, 1, 7, 0 }, 12494 { MIB_RSC_MEM3_ERRf, 1, 8, 0 }, 12495 { MIB_RSC_MEM4_ERRf, 1, 9, 0 }, 12496 { MIB_TSC_MEM0_ERRf, 1, 1, 0 }, 12497 { MIB_TSC_MEM1_ERRf, 1, 2, 0 }, 12498 { MIB_TSC_MEM2_ERRf, 1, 3, 0 }, 12499 { MIB_TSC_MEM3_ERRf, 1, 4, 0 }, 12500 { RXFIFO_MEM_ERRf, 1, 10, 0 }, 12501 { TXFIFO_MEM_ERRf, 1, 0, 0 } 12502 }; 12503 12504 #endif 12505 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12506 defined(BCM_56450_B1) 12507 soc_field_info_t soc_XPORT_INTR_ENABLE_BCM56450_A0r_fields[] = { 12508 { MIB_RSC_MEM0_ERRf, 1, 5, SOCF_RO }, 12509 { MIB_RSC_MEM1_ERRf, 1, 6, SOCF_RO }, 12510 { MIB_RSC_MEM2_ERRf, 1, 7, SOCF_RO }, 12511 { MIB_RSC_MEM3_ERRf, 1, 8, SOCF_RO }, 12512 { MIB_RSC_MEM4_ERRf, 1, 9, SOCF_RO }, 12513 { MIB_TSC_MEM0_ERRf, 1, 1, SOCF_RO }, 12514 { MIB_TSC_MEM1_ERRf, 1, 2, SOCF_RO }, 12515 { MIB_TSC_MEM2_ERRf, 1, 3, SOCF_RO }, 12516 { MIB_TSC_MEM3_ERRf, 1, 4, SOCF_RO }, 12517 { RXFIFO_MEM0_ERRf, 1, 10, SOCF_RO }, 12518 { RXFIFO_MEM1_ERRf, 1, 11, SOCF_RO }, 12519 { RXFIFO_MEM2_ERRf, 1, 12, SOCF_RO }, 12520 { RXFIFO_MEM3_ERRf, 1, 13, SOCF_RO }, 12521 { RXFIFO_MEM4_ERRf, 1, 14, SOCF_RO }, 12522 { TXFIFO_MEM_ERRf, 1, 0, SOCF_RO } 12523 }; 12524 12525 #endif 12526 #if defined(BCM_88270_A0) 12527 soc_field_info_t soc_XPORT_INTR_ENABLE_BCM88270_A0r_fields[] = { 12528 { MIB_RSC_MEM0_ERRf, 1, 5, 0 }, 12529 { MIB_RSC_MEM1_ERRf, 1, 6, 0 }, 12530 { MIB_RSC_MEM2_ERRf, 1, 7, 0 }, 12531 { MIB_RSC_MEM3_ERRf, 1, 8, 0 }, 12532 { MIB_RSC_MEM4_ERRf, 1, 9, 0 }, 12533 { MIB_TSC_MEM0_ERRf, 1, 1, 0 }, 12534 { MIB_TSC_MEM1_ERRf, 1, 2, 0 }, 12535 { MIB_TSC_MEM2_ERRf, 1, 3, 0 }, 12536 { MIB_TSC_MEM3_ERRf, 1, 4, 0 }, 12537 { RXFIFO_MEM_ERRf, 1, 10, 0 }, 12538 { TXFIFO_MEM_ERRf, 1, 0, 0 } 12539 }; 12540 12541 #endif 12542 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12543 soc_field_info_t soc_XPORT_INTR_STATUSr_fields[] = { 12544 { MIB_RSC_MEM0_ERRf, 1, 5, SOCF_RO }, 12545 { MIB_RSC_MEM1_ERRf, 1, 6, SOCF_RO }, 12546 { MIB_RSC_MEM2_ERRf, 1, 7, SOCF_RO }, 12547 { MIB_RSC_MEM3_ERRf, 1, 8, SOCF_RO }, 12548 { MIB_RSC_MEM4_ERRf, 1, 9, SOCF_RO }, 12549 { MIB_TSC_MEM0_ERRf, 1, 1, SOCF_RO }, 12550 { MIB_TSC_MEM1_ERRf, 1, 2, SOCF_RO }, 12551 { MIB_TSC_MEM2_ERRf, 1, 3, SOCF_RO }, 12552 { MIB_TSC_MEM3_ERRf, 1, 4, SOCF_RO }, 12553 { RXFIFO_MEM0_ERRf, 1, 10, SOCF_RO }, 12554 { RXFIFO_MEM1_ERRf, 1, 11, SOCF_RO }, 12555 { RXFIFO_MEM2_ERRf, 1, 12, SOCF_RO }, 12556 { RXFIFO_MEM3_ERRf, 1, 13, SOCF_RO }, 12557 { RXFIFO_MEM4_ERRf, 1, 14, SOCF_RO }, 12558 { TXFIFO_MEM_ERRf, 1, 0, SOCF_RO } 12559 }; 12560 12561 #endif 12562 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 12563 defined(BCM_56270_A0) 12564 soc_field_info_t soc_XPORT_INTR_STATUS_BCM56260_A0r_fields[] = { 12565 { MIB_RSC_MEM0_ERRf, 1, 5, SOCF_RO }, 12566 { MIB_RSC_MEM1_ERRf, 1, 6, SOCF_RO }, 12567 { MIB_RSC_MEM2_ERRf, 1, 7, SOCF_RO }, 12568 { MIB_RSC_MEM3_ERRf, 1, 8, SOCF_RO }, 12569 { MIB_RSC_MEM4_ERRf, 1, 9, SOCF_RO }, 12570 { MIB_TSC_MEM0_ERRf, 1, 1, SOCF_RO }, 12571 { MIB_TSC_MEM1_ERRf, 1, 2, SOCF_RO }, 12572 { MIB_TSC_MEM2_ERRf, 1, 3, SOCF_RO }, 12573 { MIB_TSC_MEM3_ERRf, 1, 4, SOCF_RO }, 12574 { RXFIFO_MEM_ERRf, 1, 10, SOCF_RO }, 12575 { TXFIFO_MEM_ERRf, 1, 0, SOCF_RO } 12576 }; 12577 12578 #endif 12579 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12580 defined(BCM_56450_B1) 12581 soc_field_info_t soc_XPORT_INTR_STATUS_BCM56450_A0r_fields[] = { 12582 { MIB_RSC_MEM0_ERRf, 1, 5, SOCF_RO }, 12583 { MIB_RSC_MEM1_ERRf, 1, 6, SOCF_RO }, 12584 { MIB_RSC_MEM2_ERRf, 1, 7, SOCF_RO }, 12585 { MIB_RSC_MEM3_ERRf, 1, 8, SOCF_RO }, 12586 { MIB_RSC_MEM4_ERRf, 1, 9, SOCF_RO }, 12587 { MIB_TSC_MEM0_ERRf, 1, 1, SOCF_RO }, 12588 { MIB_TSC_MEM1_ERRf, 1, 2, SOCF_RO }, 12589 { MIB_TSC_MEM2_ERRf, 1, 3, SOCF_RO }, 12590 { MIB_TSC_MEM3_ERRf, 1, 4, SOCF_RO }, 12591 { RXFIFO_MEM0_ERRf, 1, 10, SOCF_RO }, 12592 { RXFIFO_MEM1_ERRf, 1, 11, SOCF_RO }, 12593 { RXFIFO_MEM2_ERRf, 1, 12, SOCF_RO }, 12594 { RXFIFO_MEM3_ERRf, 1, 13, SOCF_RO }, 12595 { RXFIFO_MEM4_ERRf, 1, 14, SOCF_RO }, 12596 { TXFIFO_MEM_ERRf, 1, 0, SOCF_RO } 12597 }; 12598 12599 #endif 12600 #if defined(BCM_88270_A0) 12601 soc_field_info_t soc_XPORT_INTR_STATUS_BCM88270_A0r_fields[] = { 12602 { MIB_RSC_MEM0_ERRf, 1, 5, SOCF_RO }, 12603 { MIB_RSC_MEM1_ERRf, 1, 6, SOCF_RO }, 12604 { MIB_RSC_MEM2_ERRf, 1, 7, SOCF_RO }, 12605 { MIB_RSC_MEM3_ERRf, 1, 8, SOCF_RO }, 12606 { MIB_RSC_MEM4_ERRf, 1, 9, SOCF_RO }, 12607 { MIB_TSC_MEM0_ERRf, 1, 1, SOCF_RO }, 12608 { MIB_TSC_MEM1_ERRf, 1, 2, SOCF_RO }, 12609 { MIB_TSC_MEM2_ERRf, 1, 3, SOCF_RO }, 12610 { MIB_TSC_MEM3_ERRf, 1, 4, SOCF_RO }, 12611 { RXFIFO_MEM_ERRf, 1, 10, SOCF_RO }, 12612 { TXFIFO_MEM_ERRf, 1, 0, SOCF_RO } 12613 }; 12614 12615 #endif 12616 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 12617 defined(BCM_56270_A0) 12618 soc_field_info_t soc_XPORT_LINKSTATUS_DOWNr_fields[] = { 12619 { PORT0_LINKSTATUSf, 1, 0, 0 }, 12620 { PORT1_LINKSTATUSf, 1, 1, 0 }, 12621 { PORT2_LINKSTATUSf, 1, 2, 0 }, 12622 { PORT3_LINKSTATUSf, 1, 3, 0 } 12623 }; 12624 12625 #endif 12626 #if defined(BCM_88270_A0) 12627 soc_field_info_t soc_XPORT_LINKSTATUS_DOWN_BCM88270_A0r_fields[] = { 12628 { PORT0_LINKSTATUSf, 1, 0, 0 }, 12629 { PORT1_LINKSTATUSf, 1, 1, 0 }, 12630 { PORT2_LINKSTATUSf, 1, 2, 0 }, 12631 { PORT3_LINKSTATUSf, 1, 3, 0 } 12632 }; 12633 12634 #endif 12635 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 12636 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 12637 defined(BCM_56685_A0) || defined(BCM_56685_B0) 12638 soc_field_info_t soc_XPORT_MEMORY_CONTROLr_fields[] = { 12639 { CONTROL_PKT_MIB_COUNTER_MEM0_TMf, 2, 16, SOCF_LE }, 12640 { CONTROL_PKT_MIB_COUNTER_MEM1_TMf, 2, 18, SOCF_LE }, 12641 { RX_FIFO_MEM0_TMf, 2, 4, SOCF_LE }, 12642 { RX_FIFO_MEM1_TMf, 2, 6, SOCF_LE }, 12643 { RX_MIB_COUNTER_MEM0_TMf, 2, 12, SOCF_LE }, 12644 { RX_MIB_COUNTER_MEM1_TMf, 2, 14, SOCF_LE }, 12645 { TX_FIFO_MEM0_TMf, 2, 0, SOCF_LE }, 12646 { TX_FIFO_MEM1_TMf, 2, 2, SOCF_LE }, 12647 { TX_MIB_COUNTER_MEM0_TMf, 2, 8, SOCF_LE }, 12648 { TX_MIB_COUNTER_MEM1_TMf, 2, 10, SOCF_LE } 12649 }; 12650 12651 #endif 12652 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12653 defined(BCM_56450_B1) 12654 soc_field_info_t soc_XPORT_MEMORY_CONTROL0r_fields[] = { 12655 { TXFIFO_MEM0_TMf, 8, 0, SOCF_LE|SOCF_RES }, 12656 { TXFIFO_MEM1_TMf, 8, 8, SOCF_LE|SOCF_RES } 12657 }; 12658 12659 #endif 12660 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12661 defined(BCM_56450_B1) 12662 soc_field_info_t soc_XPORT_MEMORY_CONTROL1r_fields[] = { 12663 { MIB_RSC_MEM0_TMf, 8, 0, SOCF_LE }, 12664 { MIB_RSC_MEM1_TMf, 8, 8, SOCF_LE }, 12665 { MIB_RSC_MEM2_TMf, 8, 16, SOCF_LE } 12666 }; 12667 12668 #endif 12669 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12670 defined(BCM_56450_B1) 12671 soc_field_info_t soc_XPORT_MEMORY_CONTROL2r_fields[] = { 12672 { MIB_TSC_MEM0_TMf, 8, 0, SOCF_LE }, 12673 { MIB_TSC_MEM1_TMf, 8, 8, SOCF_LE }, 12674 { MIB_TSC_MEM2_TMf, 8, 16, SOCF_LE } 12675 }; 12676 12677 #endif 12678 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 12679 soc_field_info_t soc_XPORT_MEMORY_CONTROL0_BCM56260_A0r_fields[] = { 12680 { MXQ_16X128_MEM_TMf, 8, 0, SOCF_LE|SOCF_RES }, 12681 { MXQ_16X144_MEM_TMf, 8, 8, SOCF_LE|SOCF_RES }, 12682 { MXQ_64X144_MEM_TMf, 8, 16, SOCF_LE|SOCF_RES } 12683 }; 12684 12685 #endif 12686 #if defined(BCM_56270_A0) 12687 soc_field_info_t soc_XPORT_MEMORY_CONTROL0_BCM56270_A0r_fields[] = { 12688 { MXQ_16X128_MEM_TMf, 12, 0, SOCF_LE|SOCF_RES }, 12689 { MXQ_16X144_MEM_TMf, 12, 12, SOCF_LE|SOCF_RES } 12690 }; 12691 12692 #endif 12693 #if defined(BCM_88270_A0) 12694 soc_field_info_t soc_XPORT_MEMORY_CONTROL0_BCM88270_A0r_fields[] = { 12695 { MXQ_16X128_MEM_TMf, 12, 0, SOCF_LE } 12696 }; 12697 12698 #endif 12699 #if defined(BCM_56270_A0) 12700 soc_field_info_t soc_XPORT_MEMORY_CONTROL1_BCM56270_A0r_fields[] = { 12701 { MXQ_64X144_MEM_TMf, 12, 0, SOCF_LE|SOCF_RES } 12702 }; 12703 12704 #endif 12705 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12706 soc_field_info_t soc_XPORT_MIB_RESETr_fields[] = { 12707 { CLR_CNTf, 4, 0, SOCF_LE|SOCF_RES } 12708 }; 12709 12710 #endif 12711 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 12712 defined(BCM_56270_A0) 12713 soc_field_info_t soc_XPORT_MIB_RESET_BCM56260_A0r_fields[] = { 12714 { CLR_CNTf, 4, 0, SOCF_LE|SOCF_RES } 12715 }; 12716 12717 #endif 12718 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12719 defined(BCM_56450_B1) 12720 soc_field_info_t soc_XPORT_MIB_RESET_BCM56450_A0r_fields[] = { 12721 { CLR_CNTf, 4, 0, SOCF_LE|SOCF_RES } 12722 }; 12723 12724 #endif 12725 #if defined(BCM_88270_A0) 12726 soc_field_info_t soc_XPORT_MIB_RESET_BCM88270_A0r_fields[] = { 12727 { CLR_CNTf, 4, 0, SOCF_LE } 12728 }; 12729 12730 #endif 12731 #if defined(BCM_88270_A0) 12732 soc_field_info_t soc_XPORT_MIB_RSC_MEM0_ECC_STATUSr_fields[] = { 12733 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12734 { ECC_ERRf, 1, 0, 0 }, 12735 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12736 { MULTIPLE_ERRf, 1, 1, 0 } 12737 }; 12738 12739 #endif 12740 #if defined(BCM_88270_A0) 12741 soc_field_info_t soc_XPORT_MIB_RSC_MEM1_ECC_STATUSr_fields[] = { 12742 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12743 { ECC_ERRf, 1, 0, 0 }, 12744 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12745 { MULTIPLE_ERRf, 1, 1, 0 } 12746 }; 12747 12748 #endif 12749 #if defined(BCM_88270_A0) 12750 soc_field_info_t soc_XPORT_MIB_RSC_MEM2_ECC_STATUSr_fields[] = { 12751 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12752 { ECC_ERRf, 1, 0, 0 }, 12753 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12754 { MULTIPLE_ERRf, 1, 1, 0 } 12755 }; 12756 12757 #endif 12758 #if defined(BCM_88270_A0) 12759 soc_field_info_t soc_XPORT_MIB_RSC_MEM3_ECC_STATUSr_fields[] = { 12760 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12761 { ECC_ERRf, 1, 0, 0 }, 12762 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12763 { MULTIPLE_ERRf, 1, 1, 0 } 12764 }; 12765 12766 #endif 12767 #if defined(BCM_88270_A0) 12768 soc_field_info_t soc_XPORT_MIB_RSC_MEM4_ECC_STATUSr_fields[] = { 12769 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12770 { ECC_ERRf, 1, 0, 0 }, 12771 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12772 { MULTIPLE_ERRf, 1, 1, 0 } 12773 }; 12774 12775 #endif 12776 #if defined(BCM_88270_A0) 12777 soc_field_info_t soc_XPORT_MIB_TSC_MEM0_ECC_STATUSr_fields[] = { 12778 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12779 { ECC_ERRf, 1, 0, 0 }, 12780 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12781 { MULTIPLE_ERRf, 1, 1, 0 } 12782 }; 12783 12784 #endif 12785 #if defined(BCM_88270_A0) 12786 soc_field_info_t soc_XPORT_MIB_TSC_MEM1_ECC_STATUSr_fields[] = { 12787 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12788 { ECC_ERRf, 1, 0, 0 }, 12789 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12790 { MULTIPLE_ERRf, 1, 1, 0 } 12791 }; 12792 12793 #endif 12794 #if defined(BCM_88270_A0) 12795 soc_field_info_t soc_XPORT_MIB_TSC_MEM2_ECC_STATUSr_fields[] = { 12796 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12797 { ECC_ERRf, 1, 0, 0 }, 12798 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12799 { MULTIPLE_ERRf, 1, 1, 0 } 12800 }; 12801 12802 #endif 12803 #if defined(BCM_88270_A0) 12804 soc_field_info_t soc_XPORT_MIB_TSC_MEM3_ECC_STATUSr_fields[] = { 12805 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12806 { ECC_ERRf, 1, 0, 0 }, 12807 { ENTRY_IDXf, 4, 3, SOCF_LE }, 12808 { MULTIPLE_ERRf, 1, 1, 0 } 12809 }; 12810 12811 #endif 12812 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 12813 defined(BCM_56680_A0) || defined(BCM_56680_B0) 12814 soc_field_info_t soc_XPORT_MODE_REGr_fields[] = { 12815 { XPORT_MODE_BITSf, 2, 0, SOCF_LE|SOCF_RES } 12816 }; 12817 12818 #endif 12819 #if defined(BCM_56260_A0) 12820 soc_field_info_t soc_XPORT_MODE_REG_BCM56260_A0r_fields[] = { 12821 { PHY_PORT_MODEf, 2, 0, SOCF_LE }, 12822 { PORT_GMII_MII_ENABLEf, 1, 2, 0 } 12823 }; 12824 12825 #endif 12826 #if defined(BCM_56260_B0) || defined(BCM_56270_A0) 12827 soc_field_info_t soc_XPORT_MODE_REG_BCM56260_B0r_fields[] = { 12828 { PHY_PORT_MODEf, 2, 0, SOCF_LE }, 12829 { PORT_GMII_MII_ENABLEf, 1, 2, 0 }, 12830 { SHIM_FLEX_TDM_ENf, 1, 3, 0 } 12831 }; 12832 12833 #endif 12834 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12835 soc_field_info_t soc_XPORT_MODE_REG_BCM56440_A0r_fields[] = { 12836 { CORE_PORT_MODEf, 2, 0, SOCF_LE }, 12837 { E2E_HOL_ENf, 1, 5, 0 }, 12838 { E2E_IBP_ENf, 1, 6, 0 }, 12839 { PHY_PORT_MODEf, 2, 2, SOCF_LE }, 12840 { PORT_GMII_MII_ENABLEf, 1, 4, 0 } 12841 }; 12842 12843 #endif 12844 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12845 defined(BCM_56450_B1) 12846 soc_field_info_t soc_XPORT_MODE_REG_BCM56450_A0r_fields[] = { 12847 { BYPASS_DOWNSIZERf, 1, 8, 0 }, 12848 { CORE_PORT_MODEf, 2, 0, SOCF_LE }, 12849 { E2E_HOL_ENf, 1, 5, 0 }, 12850 { E2E_IBP_ENf, 1, 6, 0 }, 12851 { E2E_LOW_LATENCY_ENf, 1, 10, 0 }, 12852 { PHY_PORT_MODEf, 2, 2, SOCF_LE }, 12853 { PORT_GMII_MII_ENABLEf, 1, 4, 0 }, 12854 { SW_RESET_DOWNSIZERf, 1, 9, 0 }, 12855 { WC_10G_21G_SELf, 1, 7, 0 } 12856 }; 12857 12858 #endif 12859 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 12860 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 12861 defined(BCM_56685_A0) || defined(BCM_56685_B0) 12862 soc_field_info_t soc_XPORT_MODE_REG_BCM56634_A0r_fields[] = { 12863 { MODE_RBf, 1, 2, 0 }, 12864 { RUNT_51B_MODEf, 1, 3, 0 }, 12865 { XPORT_MODE_BITSf, 2, 0, SOCF_LE } 12866 }; 12867 12868 #endif 12869 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 12870 soc_field_info_t soc_XPORT_MODE_REG_BCM56820_A0r_fields[] = { 12871 { XPORT_MODE_BITSf, 2, 0, SOCF_LE } 12872 }; 12873 12874 #endif 12875 #if defined(BCM_88270_A0) 12876 soc_field_info_t soc_XPORT_MODE_REG_BCM88270_A0r_fields[] = { 12877 { PORT_GMII_MII_ENABLEf, 1, 1, 0 }, 12878 { PORT_MODEf, 1, 0, 0 }, 12879 { SHIM_FLEX_TDM_ENf, 1, 2, 0 } 12880 }; 12881 12882 #endif 12883 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 12884 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 12885 defined(BCM_56965_A0) || defined(BCM_56970_A0) 12886 soc_field_info_t soc_XPORT_PFC_STATEr_fields[] = { 12887 { VECTORf, 16, 0, SOCF_LE|SOCF_RWBW } 12888 }; 12889 12890 #endif 12891 #if defined(BCM_88270_A0) 12892 soc_field_info_t soc_XPORT_PORT_ENABLEr_fields[] = { 12893 { PORT0f, 1, 0, 0 }, 12894 { PORT1f, 1, 1, 0 }, 12895 { PORT2f, 1, 2, 0 }, 12896 { PORT3f, 1, 3, 0 } 12897 }; 12898 12899 #endif 12900 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12901 soc_field_info_t soc_XPORT_RXFIFO_MEM0_ECC_STATUSr_fields[] = { 12902 { DOUBLE_BIT_ERRf, 1, 1, 0 }, 12903 { ECC_ERRf, 1, 0, 0 } 12904 }; 12905 12906 #endif 12907 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 12908 defined(BCM_56450_B1) 12909 soc_field_info_t soc_XPORT_RXFIFO_MEM0_ECC_STATUS_BCM56450_A0r_fields[] = { 12910 { DOUBLE_BIT_ERRf, 1, 1, 0 }, 12911 { ECC_ERRf, 1, 0, 0 } 12912 }; 12913 12914 #endif 12915 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 12916 defined(BCM_56270_A0) 12917 soc_field_info_t soc_XPORT_RXFIFO_MEM_ECC_STATUSr_fields[] = { 12918 { DOUBLE_BIT_ERRf, 1, 1, 0 }, 12919 { ECC_ERRf, 1, 0, 0 } 12920 }; 12921 12922 #endif 12923 #if defined(BCM_88270_A0) 12924 soc_field_info_t soc_XPORT_RXFIFO_MEM_ECC_STATUS_BCM88270_A0r_fields[] = { 12925 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 12926 { ECC_ERRf, 1, 0, 0 } 12927 }; 12928 12929 #endif 12930 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 12931 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 12932 defined(BCM_56685_A0) || defined(BCM_56685_B0) 12933 soc_field_info_t soc_XPORT_RX_FIFO_MEM_ECC_STATUSr_fields[] = { 12934 { DOUBLE_BIT_ERRf, 1, 6, 0 }, 12935 { ECC_ERRf, 1, 0, 0 }, 12936 { ENTRY_IDXf, 4, 2, SOCF_LE }, 12937 { MULTIPLE_ERRf, 1, 1, 0 } 12938 }; 12939 12940 #endif 12941 #if defined(BCM_88270_A0) 12942 soc_field_info_t soc_XPORT_SW_FLOW_CONTROLr_fields[] = { 12943 { FC_ENf, 1, 1, 0 }, 12944 { FC_PAUSEf, 1, 0, 0 } 12945 }; 12946 12947 #endif 12948 #if defined(BCM_56800_A0) 12949 soc_field_info_t soc_XPORT_TO_MMU_BKPr_fields[] = { 12950 { PRI0_BKPf, 1, 0, SOCF_RO }, 12951 { PRI14_BKPf, 1, 8, SOCF_RO }, 12952 { PRI15_BKPf, 1, 9, SOCF_RO }, 12953 { PRI1_BKPf, 1, 1, SOCF_RO }, 12954 { PRI2_BKPf, 1, 2, SOCF_RO }, 12955 { PRI3_BKPf, 1, 3, SOCF_RO }, 12956 { PRI4_BKPf, 1, 4, SOCF_RO }, 12957 { PRI5_BKPf, 1, 5, SOCF_RO }, 12958 { PRI6_BKPf, 1, 6, SOCF_RO }, 12959 { PRI7_BKPf, 1, 7, SOCF_RO } 12960 }; 12961 12962 #endif 12963 #if defined(BCM_56370_A0) 12964 soc_field_info_t soc_XPORT_TO_MMU_BKP_64r_fields[] = { 12965 { MC_COS_BKPf, 26, 26, SOCF_LE|SOCF_RWBW|SOCF_RES }, 12966 { UC_COS_BKPf, 26, 0, SOCF_LE|SOCF_RWBW|SOCF_RES } 12967 }; 12968 12969 #endif 12970 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 12971 defined(BCM_56270_A0) 12972 soc_field_info_t soc_XPORT_TO_MMU_BKP_BCM56260_A0r_fields[] = { 12973 { PRI15_0_BKPf, 16, 0, SOCF_LE } 12974 }; 12975 12976 #endif 12977 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12978 soc_field_info_t soc_XPORT_TO_MMU_BKP_BCM56440_A0r_fields[] = { 12979 { PRI15_0_BKPf, 16, 0, SOCF_LE|SOCF_RO } 12980 }; 12981 12982 #endif 12983 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 12984 defined(BCM_56670_A0) || defined(BCM_56670_B0) 12985 soc_field_info_t soc_XPORT_TO_MMU_BKP_BCM56560_A0r_fields[] = { 12986 { PRI15_0_BKPf, 16, 0, SOCF_LE|SOCF_RES } 12987 }; 12988 12989 #endif 12990 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 12991 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 12992 defined(BCM_56640_A0) 12993 soc_field_info_t soc_XPORT_TO_MMU_BKP_BCM56640_A0r_fields[] = { 12994 { PRI15_0_BKPf, 16, 0, SOCF_LE } 12995 }; 12996 12997 #endif 12998 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 12999 defined(BCM_88732_A0) 13000 soc_field_info_t soc_XPORT_TO_MMU_BKP_BCM56820_A0r_fields[] = { 13001 { PRI0_BKPf, 1, 0, 0 }, 13002 { PRI10_BKPf, 1, 10, 0 }, 13003 { PRI11_BKPf, 1, 11, 0 }, 13004 { PRI12_BKPf, 1, 12, 0 }, 13005 { PRI13_BKPf, 1, 13, 0 }, 13006 { PRI14_BKPf, 1, 14, 0 }, 13007 { PRI15_BKPf, 1, 15, 0 }, 13008 { PRI1_BKPf, 1, 1, 0 }, 13009 { PRI2_BKPf, 1, 2, 0 }, 13010 { PRI3_BKPf, 1, 3, 0 }, 13011 { PRI4_BKPf, 1, 4, 0 }, 13012 { PRI5_BKPf, 1, 5, 0 }, 13013 { PRI6_BKPf, 1, 6, 0 }, 13014 { PRI7_BKPf, 1, 7, 0 }, 13015 { PRI8_BKPf, 1, 8, 0 }, 13016 { PRI9_BKPf, 1, 9, 0 } 13017 }; 13018 13019 #endif 13020 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 13021 soc_field_info_t soc_XPORT_TO_MMU_BKP_BCM56840_A0r_fields[] = { 13022 { PRI15_0_BKPf, 16, 0, SOCF_LE|SOCF_RES } 13023 }; 13024 13025 #endif 13026 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 13027 soc_field_info_t soc_XPORT_TO_MMU_BKP_BCM56850_A0r_fields[] = { 13028 { PRI15_0_BKPf, 16, 0, SOCF_LE|SOCF_RES } 13029 }; 13030 13031 #endif 13032 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 13033 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 13034 defined(BCM_56970_A0) 13035 soc_field_info_t soc_XPORT_TO_MMU_BKP_BCM56960_A0r_fields[] = { 13036 { MC_COS_BKPf, 10, 10, SOCF_LE|SOCF_RWBW|SOCF_RES }, 13037 { UC_COS_BKPf, 10, 0, SOCF_LE|SOCF_RWBW|SOCF_RES } 13038 }; 13039 13040 #endif 13041 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 13042 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 13043 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 13044 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 13045 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 13046 defined(BCM_56685_A0) || defined(BCM_56685_B0) 13047 soc_field_info_t soc_XPORT_TO_MMU_BKP_HGr_fields[] = { 13048 { PRI15_0_BKPf, 16, 0, SOCF_LE } 13049 }; 13050 13051 #endif 13052 #if defined(BCM_88270_A0) 13053 soc_field_info_t soc_XPORT_TXFIFO_MEM_ECC_STATUSr_fields[] = { 13054 { DOUBLE_BIT_ERRf, 1, 2, 0 }, 13055 { ECC_ERRf, 1, 0, 0 } 13056 }; 13057 13058 #endif 13059 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13060 defined(BCM_56450_B1) 13061 soc_field_info_t soc_XPORT_WC_UCMEM_CTRLr_fields[] = { 13062 { ACCESS_MODEf, 1, 0, 0 }, 13063 { CLK_DIV_RATIOf, 2, 8, SOCF_LE }, 13064 { RD_MARGINf, 2, 10, SOCF_LE }, 13065 { UCMEM_CTRL_RESERVEDf, 7, 1, SOCF_LE|SOCF_RES }, 13066 { WR_DATA_MARGINf, 2, 14, SOCF_LE }, 13067 { WR_HOLD_MARGINf, 2, 16, SOCF_LE }, 13068 { WR_SETUP_MARGINf, 2, 12, SOCF_LE } 13069 }; 13070 13071 #endif 13072 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13073 defined(BCM_56450_B1) 13074 soc_field_info_t soc_XPORT_XGXS0_STATUS0_REGr_fields[] = { 13075 { RESERVED_6f, 8, 23, SOCF_LE|SOCF_RES }, 13076 { XGXS0_AUTONEG_COMPLETEf, 1, 1, SOCF_RO }, 13077 { XGXS0_DUPLEX_STATUSf, 1, 2, SOCF_RO }, 13078 { XGXS0_FIBER_RXACTf, 1, 4, SOCF_RO }, 13079 { XGXS0_FIBER_TXACTf, 1, 5, SOCF_RO }, 13080 { XGXS0_LINK_STATUSf, 1, 0, SOCF_RO }, 13081 { XGXS0_RXD1G_FIFO_ERRf, 1, 6, SOCF_RO }, 13082 { XGXS0_SGMIIf, 1, 3, SOCF_RO }, 13083 { XGXS0_SPEED1000f, 1, 10, SOCF_RO }, 13084 { XGXS0_SPEED10000f, 1, 15, SOCF_RO }, 13085 { XGXS0_SPEED10000_CX4f, 1, 14, SOCF_RO }, 13086 { XGXS0_SPEED12000f, 1, 16, SOCF_RO }, 13087 { XGXS0_SPEED12500f, 1, 17, SOCF_RO }, 13088 { XGXS0_SPEED13000f, 1, 18, SOCF_RO }, 13089 { XGXS0_SPEED15000f, 1, 19, SOCF_RO }, 13090 { XGXS0_SPEED16000f, 1, 20, SOCF_RO }, 13091 { XGXS0_SPEED20000f, 1, 21, SOCF_RO }, 13092 { XGXS0_SPEED21000f, 1, 22, SOCF_RO }, 13093 { XGXS0_SPEED2500f, 1, 11, SOCF_RO }, 13094 { XGXS0_SPEED5000f, 1, 12, SOCF_RO }, 13095 { XGXS0_SPEED6000f, 1, 13, SOCF_RO }, 13096 { XGXS0_SPEED_10f, 1, 8, SOCF_RO }, 13097 { XGXS0_SPEED_100f, 1, 9, SOCF_RO }, 13098 { XGXS0_TXD1G_FIFO_ERRf, 1, 7, SOCF_RO }, 13099 { XGXS0_TX_TICKf, 1, 31, SOCF_RO } 13100 }; 13101 13102 #endif 13103 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 13104 defined(BCM_56270_A0) 13105 soc_field_info_t soc_XPORT_XGXS0_STATUS0_REG_BCM56260_A0r_fields[] = { 13106 { XGXS0_LINK_STATUSf, 1, 0, SOCF_RO }, 13107 { XGXS0_SGMIIf, 1, 1, SOCF_RO }, 13108 { XGXS0_SPEED1000f, 1, 4, SOCF_RO }, 13109 { XGXS0_SPEED10000f, 1, 7, SOCF_RO }, 13110 { XGXS0_SPEED10000_CX4f, 1, 6, SOCF_RO }, 13111 { XGXS0_SPEED2500f, 1, 5, SOCF_RO }, 13112 { XGXS0_SPEED_10f, 1, 2, SOCF_RO }, 13113 { XGXS0_SPEED_100f, 1, 3, SOCF_RO } 13114 }; 13115 13116 #endif 13117 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13118 defined(BCM_56450_B1) 13119 soc_field_info_t soc_XPORT_XGXS0_STATUS1_REGr_fields[] = { 13120 { RESERVED_7f, 6, 26, SOCF_LE|SOCF_RES }, 13121 { XGXS0_SPEED10000_DXGXSf, 1, 0, SOCF_RO }, 13122 { XGXS0_SPEED10000_HI_DXGXSf, 1, 1, SOCF_RO }, 13123 { XGXS0_SPEED10000_KRf, 1, 12, SOCF_RO }, 13124 { XGXS0_SPEED10000_KX4f, 1, 11, SOCF_RO }, 13125 { XGXS0_SPEED1000_KXf, 1, 13, SOCF_RO }, 13126 { XGXS0_SPEED10500_DXGXSf, 1, 2, SOCF_RO }, 13127 { XGXS0_SPEED10500_HI_DXGXSf, 1, 3, SOCF_RO }, 13128 { XGXS0_SPEED10G_CX1f, 1, 18, SOCF_RO }, 13129 { XGXS0_SPEED10G_ERf, 1, 20, SOCF_RO }, 13130 { XGXS0_SPEED10G_LRf, 1, 21, SOCF_RO }, 13131 { XGXS0_SPEED10G_LRMf, 1, 23, SOCF_RO }, 13132 { XGXS0_SPEED10G_SFIf, 1, 10, SOCF_RO }, 13133 { XGXS0_SPEED10G_SINGLEf, 1, 9, SOCF_RO }, 13134 { XGXS0_SPEED10G_SRf, 1, 22, SOCF_RO }, 13135 { XGXS0_SPEED12773_DXGXSf, 1, 4, SOCF_RO }, 13136 { XGXS0_SPEED12773_HI_DXGXSf, 1, 5, SOCF_RO }, 13137 { XGXS0_SPEED15750_HI_DXGXSf, 1, 8, SOCF_RO }, 13138 { XGXS0_SPEED1G_CX1f, 1, 19, SOCF_RO }, 13139 { XGXS0_SPEED20G_CR2f, 1, 24, SOCF_RO }, 13140 { XGXS0_SPEED20G_DXGXSf, 1, 6, SOCF_RO }, 13141 { XGXS0_SPEED20G_HI_DXGXSf, 1, 7, SOCF_RO }, 13142 { XGXS0_SPEED20G_KR2f, 1, 25, SOCF_RO }, 13143 { XGXS0_SPEED5000_SINGLEf, 1, 14, SOCF_RO }, 13144 { XGXS0_SPEED6364_SINGLEf, 1, 15, SOCF_RO }, 13145 { XGXS0_SPEED_R2_12000f, 1, 16, SOCF_RO }, 13146 { XGXS0_SPEED_X2_10000f, 1, 17, SOCF_RO } 13147 }; 13148 13149 #endif 13150 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13151 defined(BCM_56450_B1) 13152 soc_field_info_t soc_XPORT_XGXS1_STATUS0_REGr_fields[] = { 13153 { RESERVED_8f, 8, 23, SOCF_LE|SOCF_RES }, 13154 { XGXS1_AUTONEG_COMPLETEf, 1, 1, SOCF_RO }, 13155 { XGXS1_DUPLEX_STATUSf, 1, 2, SOCF_RO }, 13156 { XGXS1_FIBER_RXACTf, 1, 4, SOCF_RO }, 13157 { XGXS1_FIBER_TXACTf, 1, 5, SOCF_RO }, 13158 { XGXS1_LINK_STATUSf, 1, 0, SOCF_RO }, 13159 { XGXS1_RXD1G_FIFO_ERRf, 1, 6, SOCF_RO }, 13160 { XGXS1_SGMIIf, 1, 3, SOCF_RO }, 13161 { XGXS1_SPEED1000f, 1, 10, SOCF_RO }, 13162 { XGXS1_SPEED10000f, 1, 15, SOCF_RO }, 13163 { XGXS1_SPEED10000_CX4f, 1, 14, SOCF_RO }, 13164 { XGXS1_SPEED12000f, 1, 16, SOCF_RO }, 13165 { XGXS1_SPEED12500f, 1, 17, SOCF_RO }, 13166 { XGXS1_SPEED13000f, 1, 18, SOCF_RO }, 13167 { XGXS1_SPEED15000f, 1, 19, SOCF_RO }, 13168 { XGXS1_SPEED16000f, 1, 20, SOCF_RO }, 13169 { XGXS1_SPEED20000f, 1, 21, SOCF_RO }, 13170 { XGXS1_SPEED21000f, 1, 22, SOCF_RO }, 13171 { XGXS1_SPEED2500f, 1, 11, SOCF_RO }, 13172 { XGXS1_SPEED5000f, 1, 12, SOCF_RO }, 13173 { XGXS1_SPEED6000f, 1, 13, SOCF_RO }, 13174 { XGXS1_SPEED_10f, 1, 8, SOCF_RO }, 13175 { XGXS1_SPEED_100f, 1, 9, SOCF_RO }, 13176 { XGXS1_TXD1G_FIFO_ERRf, 1, 7, SOCF_RO }, 13177 { XGXS1_TX_TICKf, 1, 31, SOCF_RO } 13178 }; 13179 13180 #endif 13181 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 13182 defined(BCM_56270_A0) 13183 soc_field_info_t soc_XPORT_XGXS1_STATUS0_REG_BCM56260_A0r_fields[] = { 13184 { XGXS1_LINK_STATUSf, 1, 0, SOCF_RO }, 13185 { XGXS1_SGMIIf, 1, 1, SOCF_RO }, 13186 { XGXS1_SPEED1000f, 1, 4, SOCF_RO }, 13187 { XGXS1_SPEED10000f, 1, 7, SOCF_RO }, 13188 { XGXS1_SPEED10000_CX4f, 1, 6, SOCF_RO }, 13189 { XGXS1_SPEED2500f, 1, 5, SOCF_RO }, 13190 { XGXS1_SPEED_10f, 1, 2, SOCF_RO }, 13191 { XGXS1_SPEED_100f, 1, 3, SOCF_RO } 13192 }; 13193 13194 #endif 13195 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13196 defined(BCM_56450_B1) 13197 soc_field_info_t soc_XPORT_XGXS1_STATUS1_REGr_fields[] = { 13198 { RESERVED_9f, 6, 26, SOCF_LE|SOCF_RES }, 13199 { XGXS1_SPEED10000_DXGXSf, 1, 0, SOCF_RO }, 13200 { XGXS1_SPEED10000_HI_DXGXSf, 1, 1, SOCF_RO }, 13201 { XGXS1_SPEED10000_KRf, 1, 12, SOCF_RO }, 13202 { XGXS1_SPEED10000_KX4f, 1, 11, SOCF_RO }, 13203 { XGXS1_SPEED1000_KXf, 1, 13, SOCF_RO }, 13204 { XGXS1_SPEED10500_DXGXSf, 1, 2, SOCF_RO }, 13205 { XGXS1_SPEED10500_HI_DXGXSf, 1, 3, SOCF_RO }, 13206 { XGXS1_SPEED10G_CX1f, 1, 18, SOCF_RO }, 13207 { XGXS1_SPEED10G_ERf, 1, 20, SOCF_RO }, 13208 { XGXS1_SPEED10G_LRf, 1, 21, SOCF_RO }, 13209 { XGXS1_SPEED10G_LRMf, 1, 23, SOCF_RO }, 13210 { XGXS1_SPEED10G_SFIf, 1, 10, SOCF_RO }, 13211 { XGXS1_SPEED10G_SINGLEf, 1, 9, SOCF_RO }, 13212 { XGXS1_SPEED10G_SRf, 1, 22, SOCF_RO }, 13213 { XGXS1_SPEED12773_DXGXSf, 1, 4, SOCF_RO }, 13214 { XGXS1_SPEED12773_HI_DXGXSf, 1, 5, SOCF_RO }, 13215 { XGXS1_SPEED15750_HI_DXGXSf, 1, 8, SOCF_RO }, 13216 { XGXS1_SPEED1G_CX1f, 1, 19, SOCF_RO }, 13217 { XGXS1_SPEED20G_CR2f, 1, 24, SOCF_RO }, 13218 { XGXS1_SPEED20G_DXGXSf, 1, 6, SOCF_RO }, 13219 { XGXS1_SPEED20G_HI_DXGXSf, 1, 7, SOCF_RO }, 13220 { XGXS1_SPEED20G_KR2f, 1, 25, SOCF_RO }, 13221 { XGXS1_SPEED5000_SINGLEf, 1, 14, SOCF_RO }, 13222 { XGXS1_SPEED6364_SINGLEf, 1, 15, SOCF_RO }, 13223 { XGXS1_SPEED_R2_12000f, 1, 16, SOCF_RO }, 13224 { XGXS1_SPEED_X2_10000f, 1, 17, SOCF_RO } 13225 }; 13226 13227 #endif 13228 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13229 defined(BCM_56450_B1) 13230 soc_field_info_t soc_XPORT_XGXS2_STATUS0_REGr_fields[] = { 13231 { RESERVED_10f, 8, 23, SOCF_LE|SOCF_RES }, 13232 { XGXS2_AUTONEG_COMPLETEf, 1, 1, SOCF_RO }, 13233 { XGXS2_DUPLEX_STATUSf, 1, 2, SOCF_RO }, 13234 { XGXS2_FIBER_RXACTf, 1, 4, SOCF_RO }, 13235 { XGXS2_FIBER_TXACTf, 1, 5, SOCF_RO }, 13236 { XGXS2_LINK_STATUSf, 1, 0, SOCF_RO }, 13237 { XGXS2_RXD1G_FIFO_ERRf, 1, 6, SOCF_RO }, 13238 { XGXS2_SGMIIf, 1, 3, SOCF_RO }, 13239 { XGXS2_SPEED1000f, 1, 10, SOCF_RO }, 13240 { XGXS2_SPEED10000f, 1, 15, SOCF_RO }, 13241 { XGXS2_SPEED10000_CX4f, 1, 14, SOCF_RO }, 13242 { XGXS2_SPEED12000f, 1, 16, SOCF_RO }, 13243 { XGXS2_SPEED12500f, 1, 17, SOCF_RO }, 13244 { XGXS2_SPEED13000f, 1, 18, SOCF_RO }, 13245 { XGXS2_SPEED15000f, 1, 19, SOCF_RO }, 13246 { XGXS2_SPEED16000f, 1, 20, SOCF_RO }, 13247 { XGXS2_SPEED20000f, 1, 21, SOCF_RO }, 13248 { XGXS2_SPEED21000f, 1, 22, SOCF_RO }, 13249 { XGXS2_SPEED2500f, 1, 11, SOCF_RO }, 13250 { XGXS2_SPEED5000f, 1, 12, SOCF_RO }, 13251 { XGXS2_SPEED6000f, 1, 13, SOCF_RO }, 13252 { XGXS2_SPEED_10f, 1, 8, SOCF_RO }, 13253 { XGXS2_SPEED_100f, 1, 9, SOCF_RO }, 13254 { XGXS2_TXD1G_FIFO_ERRf, 1, 7, SOCF_RO }, 13255 { XGXS2_TX_TICKf, 1, 31, SOCF_RO } 13256 }; 13257 13258 #endif 13259 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 13260 defined(BCM_56270_A0) 13261 soc_field_info_t soc_XPORT_XGXS2_STATUS0_REG_BCM56260_A0r_fields[] = { 13262 { XGXS2_LINK_STATUSf, 1, 0, SOCF_RO }, 13263 { XGXS2_SGMIIf, 1, 1, SOCF_RO }, 13264 { XGXS2_SPEED1000f, 1, 4, SOCF_RO }, 13265 { XGXS2_SPEED10000f, 1, 7, SOCF_RO }, 13266 { XGXS2_SPEED10000_CX4f, 1, 6, SOCF_RO }, 13267 { XGXS2_SPEED2500f, 1, 5, SOCF_RO }, 13268 { XGXS2_SPEED_10f, 1, 2, SOCF_RO }, 13269 { XGXS2_SPEED_100f, 1, 3, SOCF_RO } 13270 }; 13271 13272 #endif 13273 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13274 defined(BCM_56450_B1) 13275 soc_field_info_t soc_XPORT_XGXS2_STATUS1_REGr_fields[] = { 13276 { RESERVED_11f, 6, 26, SOCF_LE|SOCF_RES }, 13277 { XGXS2_SPEED10000_DXGXSf, 1, 0, SOCF_RO }, 13278 { XGXS2_SPEED10000_HI_DXGXSf, 1, 1, SOCF_RO }, 13279 { XGXS2_SPEED10000_KRf, 1, 12, SOCF_RO }, 13280 { XGXS2_SPEED10000_KX4f, 1, 11, SOCF_RO }, 13281 { XGXS2_SPEED1000_KXf, 1, 13, SOCF_RO }, 13282 { XGXS2_SPEED10500_DXGXSf, 1, 2, SOCF_RO }, 13283 { XGXS2_SPEED10500_HI_DXGXSf, 1, 3, SOCF_RO }, 13284 { XGXS2_SPEED10G_CX1f, 1, 18, SOCF_RO }, 13285 { XGXS2_SPEED10G_ERf, 1, 20, SOCF_RO }, 13286 { XGXS2_SPEED10G_LRf, 1, 21, SOCF_RO }, 13287 { XGXS2_SPEED10G_LRMf, 1, 23, SOCF_RO }, 13288 { XGXS2_SPEED10G_SFIf, 1, 10, SOCF_RO }, 13289 { XGXS2_SPEED10G_SINGLEf, 1, 9, SOCF_RO }, 13290 { XGXS2_SPEED10G_SRf, 1, 22, SOCF_RO }, 13291 { XGXS2_SPEED12773_DXGXSf, 1, 4, SOCF_RO }, 13292 { XGXS2_SPEED12773_HI_DXGXSf, 1, 5, SOCF_RO }, 13293 { XGXS2_SPEED15750_HI_DXGXSf, 1, 8, SOCF_RO }, 13294 { XGXS2_SPEED1G_CX1f, 1, 19, SOCF_RO }, 13295 { XGXS2_SPEED20G_CR2f, 1, 24, SOCF_RO }, 13296 { XGXS2_SPEED20G_DXGXSf, 1, 6, SOCF_RO }, 13297 { XGXS2_SPEED20G_HI_DXGXSf, 1, 7, SOCF_RO }, 13298 { XGXS2_SPEED20G_KR2f, 1, 25, SOCF_RO }, 13299 { XGXS2_SPEED5000_SINGLEf, 1, 14, SOCF_RO }, 13300 { XGXS2_SPEED6364_SINGLEf, 1, 15, SOCF_RO }, 13301 { XGXS2_SPEED_R2_12000f, 1, 16, SOCF_RO }, 13302 { XGXS2_SPEED_X2_10000f, 1, 17, SOCF_RO } 13303 }; 13304 13305 #endif 13306 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13307 defined(BCM_56450_B1) 13308 soc_field_info_t soc_XPORT_XGXS3_STATUS0_REGr_fields[] = { 13309 { RESERVED_12f, 8, 23, SOCF_LE|SOCF_RES }, 13310 { XGXS3_AUTONEG_COMPLETEf, 1, 1, SOCF_RO }, 13311 { XGXS3_DUPLEX_STATUSf, 1, 2, SOCF_RO }, 13312 { XGXS3_FIBER_RXACTf, 1, 4, SOCF_RO }, 13313 { XGXS3_FIBER_TXACTf, 1, 5, SOCF_RO }, 13314 { XGXS3_LINK_STATUSf, 1, 0, SOCF_RO }, 13315 { XGXS3_RXD1G_FIFO_ERRf, 1, 6, SOCF_RO }, 13316 { XGXS3_SGMIIf, 1, 3, SOCF_RO }, 13317 { XGXS3_SPEED1000f, 1, 10, SOCF_RO }, 13318 { XGXS3_SPEED10000f, 1, 15, SOCF_RO }, 13319 { XGXS3_SPEED10000_CX4f, 1, 14, SOCF_RO }, 13320 { XGXS3_SPEED12000f, 1, 16, SOCF_RO }, 13321 { XGXS3_SPEED12500f, 1, 17, SOCF_RO }, 13322 { XGXS3_SPEED13000f, 1, 18, SOCF_RO }, 13323 { XGXS3_SPEED15000f, 1, 19, SOCF_RO }, 13324 { XGXS3_SPEED16000f, 1, 20, SOCF_RO }, 13325 { XGXS3_SPEED20000f, 1, 21, SOCF_RO }, 13326 { XGXS3_SPEED21000f, 1, 22, SOCF_RO }, 13327 { XGXS3_SPEED2500f, 1, 11, SOCF_RO }, 13328 { XGXS3_SPEED5000f, 1, 12, SOCF_RO }, 13329 { XGXS3_SPEED6000f, 1, 13, SOCF_RO }, 13330 { XGXS3_SPEED_10f, 1, 8, SOCF_RO }, 13331 { XGXS3_SPEED_100f, 1, 9, SOCF_RO }, 13332 { XGXS3_TXD1G_FIFO_ERRf, 1, 7, SOCF_RO }, 13333 { XGXS3_TX_TICKf, 1, 31, SOCF_RO } 13334 }; 13335 13336 #endif 13337 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 13338 defined(BCM_56270_A0) 13339 soc_field_info_t soc_XPORT_XGXS3_STATUS0_REG_BCM56260_A0r_fields[] = { 13340 { XGXS3_LINK_STATUSf, 1, 0, SOCF_RO }, 13341 { XGXS3_SGMIIf, 1, 1, SOCF_RO }, 13342 { XGXS3_SPEED1000f, 1, 4, SOCF_RO }, 13343 { XGXS3_SPEED10000f, 1, 7, SOCF_RO }, 13344 { XGXS3_SPEED10000_CX4f, 1, 6, SOCF_RO }, 13345 { XGXS3_SPEED2500f, 1, 5, SOCF_RO }, 13346 { XGXS3_SPEED_10f, 1, 2, SOCF_RO }, 13347 { XGXS3_SPEED_100f, 1, 3, SOCF_RO } 13348 }; 13349 13350 #endif 13351 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13352 defined(BCM_56450_B1) 13353 soc_field_info_t soc_XPORT_XGXS3_STATUS1_REGr_fields[] = { 13354 { RESERVED_13f, 6, 26, SOCF_LE|SOCF_RES }, 13355 { XGXS3_SPEED10000_DXGXSf, 1, 0, SOCF_RO }, 13356 { XGXS3_SPEED10000_HI_DXGXSf, 1, 1, SOCF_RO }, 13357 { XGXS3_SPEED10000_KRf, 1, 12, SOCF_RO }, 13358 { XGXS3_SPEED10000_KX4f, 1, 11, SOCF_RO }, 13359 { XGXS3_SPEED1000_KXf, 1, 13, SOCF_RO }, 13360 { XGXS3_SPEED10500_DXGXSf, 1, 2, SOCF_RO }, 13361 { XGXS3_SPEED10500_HI_DXGXSf, 1, 3, SOCF_RO }, 13362 { XGXS3_SPEED10G_CX1f, 1, 18, SOCF_RO }, 13363 { XGXS3_SPEED10G_ERf, 1, 20, SOCF_RO }, 13364 { XGXS3_SPEED10G_LRf, 1, 21, SOCF_RO }, 13365 { XGXS3_SPEED10G_LRMf, 1, 23, SOCF_RO }, 13366 { XGXS3_SPEED10G_SFIf, 1, 10, SOCF_RO }, 13367 { XGXS3_SPEED10G_SINGLEf, 1, 9, SOCF_RO }, 13368 { XGXS3_SPEED10G_SRf, 1, 22, SOCF_RO }, 13369 { XGXS3_SPEED12773_DXGXSf, 1, 4, SOCF_RO }, 13370 { XGXS3_SPEED12773_HI_DXGXSf, 1, 5, SOCF_RO }, 13371 { XGXS3_SPEED15750_HI_DXGXSf, 1, 8, SOCF_RO }, 13372 { XGXS3_SPEED1G_CX1f, 1, 19, SOCF_RO }, 13373 { XGXS3_SPEED20G_CR2f, 1, 24, SOCF_RO }, 13374 { XGXS3_SPEED20G_DXGXSf, 1, 6, SOCF_RO }, 13375 { XGXS3_SPEED20G_HI_DXGXSf, 1, 7, SOCF_RO }, 13376 { XGXS3_SPEED20G_KR2f, 1, 25, SOCF_RO }, 13377 { XGXS3_SPEED5000_SINGLEf, 1, 14, SOCF_RO }, 13378 { XGXS3_SPEED6364_SINGLEf, 1, 15, SOCF_RO }, 13379 { XGXS3_SPEED_R2_12000f, 1, 16, SOCF_RO }, 13380 { XGXS3_SPEED_X2_10000f, 1, 17, SOCF_RO } 13381 }; 13382 13383 #endif 13384 #if defined(BCM_88270_A0) 13385 soc_field_info_t soc_XPORT_XGXS_COUNTER_MODEr_fields[] = { 13386 { CLEAR_ON_READ_ENABLEf, 1, 0, 0 }, 13387 { SATURATE_ENABLEf, 1, 1, 0 } 13388 }; 13389 13390 #endif 13391 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 13392 soc_field_info_t soc_XPORT_XGXS_CTRLr_fields[] = { 13393 { HW_RSTLf, 1, 2, SOCF_RES }, 13394 { IDDQf, 1, 1, SOCF_RES }, 13395 { PLLBYPf, 1, 8, 0 }, 13396 { PWRDWNf, 1, 0, SOCF_RES }, 13397 { REFDIVf, 2, 10, SOCF_LE|SOCF_RES }, 13398 { REFOUT_ENf, 1, 15, SOCF_RES }, 13399 { REFSELf, 2, 12, SOCF_LE|SOCF_RES }, 13400 { REF_TERM_SELf, 1, 14, SOCF_RES }, 13401 { RESERVEDf, 5, 19, SOCF_LE|SOCF_RES }, 13402 { RESERVED_0f, 1, 9, SOCF_RES }, 13403 { RESERVED_1f, 1, 7, SOCF_RES }, 13404 { RESERVED_2f, 1, 5, SOCF_RES }, 13405 { RSTB_MDIOREGSf, 1, 3, SOCF_RES }, 13406 { RSTB_PLLf, 1, 4, SOCF_RES }, 13407 { TXFIFO_RSTLf, 1, 6, SOCF_RES }, 13408 { TX_RESCALf, 3, 16, SOCF_LE|SOCF_RES } 13409 }; 13410 13411 #endif 13412 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 13413 defined(BCM_56270_A0) 13414 soc_field_info_t soc_XPORT_XGXS_CTRL_BCM56260_A0r_fields[] = { 13415 { IDDQf, 1, 1, SOCF_RES }, 13416 { PWRDWNf, 1, 0, SOCF_RES }, 13417 { REFSELf, 3, 5, SOCF_LE|SOCF_RES }, 13418 { RSTB_HWf, 1, 2, SOCF_RES }, 13419 { RSTB_MDIOREGSf, 1, 3, SOCF_RES }, 13420 { RSTB_PLLf, 1, 4, SOCF_RES }, 13421 { TXD10G_FIFO_RSTBf, 1, 12, SOCF_RES }, 13422 { TXD1G_FIFO_RSTBf, 4, 8, SOCF_LE|SOCF_RES } 13423 }; 13424 13425 #endif 13426 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13427 defined(BCM_56450_B1) 13428 soc_field_info_t soc_XPORT_XGXS_CTRL_BCM56450_A0r_fields[] = { 13429 { IDDQf, 1, 1, SOCF_RES }, 13430 { LCREF_ENf, 1, 9, SOCF_RES }, 13431 { PLLBYPf, 1, 8, 0 }, 13432 { PWRDWNf, 1, 0, SOCF_RES }, 13433 { REFDIVf, 2, 10, SOCF_LE|SOCF_RES }, 13434 { REFOUT_ENf, 1, 15, SOCF_RES }, 13435 { REFSELf, 2, 12, SOCF_LE|SOCF_RES }, 13436 { REF_TERM_SELf, 1, 14, SOCF_RES }, 13437 { RESERVED_1f, 4, 28, SOCF_LE|SOCF_RES }, 13438 { RESERVED_2f, 1, 19, SOCF_RES }, 13439 { RESERVED_3f, 1, 5, SOCF_RES }, 13440 { RSTB_HWf, 1, 2, SOCF_RES }, 13441 { RSTB_MDIOREGSf, 1, 3, SOCF_RES }, 13442 { RSTB_PLLf, 1, 4, SOCF_RES }, 13443 { RXN_LNSWAPf, 2, 26, SOCF_LE|SOCF_RES }, 13444 { TXD10G_FIFO_RSTBf, 1, 6, SOCF_RES }, 13445 { TXD10G_FIFO_RSTB_DXGXS1f, 1, 7, SOCF_RES }, 13446 { TXD1G_FIFO_RSTBf, 4, 20, SOCF_LE|SOCF_RES }, 13447 { TXN_LNSWAPf, 2, 24, SOCF_LE|SOCF_RES }, 13448 { TX_RESCALf, 3, 16, SOCF_LE|SOCF_RES } 13449 }; 13450 13451 #endif 13452 #if defined(BCM_88270_A0) 13453 soc_field_info_t soc_XPORT_XGXS_CTRL_BCM88270_A0r_fields[] = { 13454 { IDDQf, 1, 1, 0 }, 13455 { PWRDWNf, 1, 0, 0 }, 13456 { REFSELf, 3, 5, SOCF_LE }, 13457 { RSTB_HWf, 1, 2, 0 }, 13458 { RSTB_MDIOREGSf, 1, 3, 0 }, 13459 { RSTB_PLLf, 1, 4, 0 }, 13460 { TXD10G_FIFO_RSTBf, 1, 12, 0 }, 13461 { TXD1G_FIFO_RSTBf, 4, 8, SOCF_LE } 13462 }; 13463 13464 #endif 13465 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13466 defined(BCM_56450_B1) 13467 soc_field_info_t soc_XPORT_XGXS_GEN_STATUS_REGr_fields[] = { 13468 { LINK10G_DXGXS1f, 1, 5, SOCF_RO }, 13469 { RESERVED_4f, 8, 16, SOCF_LE|SOCF_RES }, 13470 { RESERVED_5f, 1, 7, SOCF_RES }, 13471 { RXACTIVEf, 4, 8, SOCF_LE|SOCF_RO }, 13472 { TXACTIVEf, 4, 12, SOCF_LE|SOCF_RO }, 13473 { TXPLL_LOCKf, 1, 6, SOCF_RO }, 13474 { XGXS0_LINKf, 4, 0, SOCF_LE|SOCF_RO }, 13475 { XGXS0_LINK10Gf, 1, 4, SOCF_RO } 13476 }; 13477 13478 #endif 13479 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 13480 defined(BCM_56270_A0) 13481 soc_field_info_t soc_XPORT_XGXS_GEN_STATUS_REG_BCM56260_A0r_fields[] = { 13482 { TXPLL_LOCKf, 1, 1, SOCF_RO }, 13483 { XGXS0_LINKf, 1, 0, SOCF_RO } 13484 }; 13485 13486 #endif 13487 #if defined(BCM_88270_A0) 13488 soc_field_info_t soc_XPORT_XGXS_GEN_STATUS_REG_BCM88270_A0r_fields[] = { 13489 { TXPLL_LOCKf, 1, 1, SOCF_RO }, 13490 { XGXS0_LINKf, 1, 0, SOCF_RO } 13491 }; 13492 13493 #endif 13494 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 13495 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 13496 defined(BCM_56685_A0) || defined(BCM_56685_B0) 13497 soc_field_info_t soc_XPORT_XGXS_NEWCTL_REGr_fields[] = { 13498 { TXD1G_FIFO_RSTBf, 4, 0, SOCF_LE } 13499 }; 13500 13501 #endif 13502 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 13503 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 13504 defined(BCM_56685_A0) || defined(BCM_56685_B0) 13505 soc_field_info_t soc_XPORT_XGXS_NEWSTATUS0_REGr_fields[] = { 13506 { XGXS0_AUTONEG_COMPLETEf, 4, 0, SOCF_LE|SOCF_RO }, 13507 { XGXS0_DUPLEX_STATUSf, 4, 4, SOCF_LE|SOCF_RO }, 13508 { XGXS0_FIBER_RXACTf, 4, 8, SOCF_LE|SOCF_RO }, 13509 { XGXS0_FIBER_TXACTf, 4, 12, SOCF_LE|SOCF_RO }, 13510 { XGXS0_LINK_STATUSf, 4, 16, SOCF_LE|SOCF_RO }, 13511 { XGXS0_SGMIIf, 4, 20, SOCF_LE|SOCF_RO }, 13512 { XGXS0_TICKf, 4, 24, SOCF_LE|SOCF_RO } 13513 }; 13514 13515 #endif 13516 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 13517 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 13518 defined(BCM_56685_A0) || defined(BCM_56685_B0) 13519 soc_field_info_t soc_XPORT_XGXS_NEWSTATUS1_REGr_fields[] = { 13520 { XGXS0_LINKf, 1, 24, SOCF_RO }, 13521 { XGXS0_LINK10Gf, 1, 25, SOCF_RO }, 13522 { XGXS0_SPEED1000f, 1, 2, SOCF_RO }, 13523 { XGXS0_SPEED10000f, 1, 8, SOCF_RO }, 13524 { XGXS0_SPEED10000_CX4f, 1, 9, SOCF_RO }, 13525 { XGXS0_SPEED10000_DXGXSf, 1, 18, SOCF_RO }, 13526 { XGXS0_SPEED10000_HI_DXGXSf, 1, 19, SOCF_RO }, 13527 { XGXS0_SPEED10500_DXGXSf, 1, 20, SOCF_RO }, 13528 { XGXS0_SPEED10500_HI_DXGXSf, 1, 21, SOCF_RO }, 13529 { XGXS0_SPEED12000f, 1, 10, SOCF_RO }, 13530 { XGXS0_SPEED12500f, 1, 11, SOCF_RO }, 13531 { XGXS0_SPEED12773_DXGXSf, 1, 22, SOCF_RO }, 13532 { XGXS0_SPEED12773_HI_DXGXSf, 1, 23, SOCF_RO }, 13533 { XGXS0_SPEED13000f, 1, 12, SOCF_RO }, 13534 { XGXS0_SPEED15000f, 1, 13, SOCF_RO }, 13535 { XGXS0_SPEED16000f, 1, 14, SOCF_RO }, 13536 { XGXS0_SPEED20000f, 1, 15, SOCF_RO }, 13537 { XGXS0_SPEED21000f, 1, 16, SOCF_RO }, 13538 { XGXS0_SPEED2500f, 1, 3, SOCF_RO }, 13539 { XGXS0_SPEED25455f, 1, 17, SOCF_RO }, 13540 { XGXS0_SPEED5000f, 1, 4, SOCF_RO }, 13541 { XGXS0_SPEED5000_SINGLEf, 1, 5, SOCF_RO }, 13542 { XGXS0_SPEED6000f, 1, 6, SOCF_RO }, 13543 { XGXS0_SPEED6364_SINGLEf, 1, 7, SOCF_RO }, 13544 { XGXS0_SPEED_10f, 1, 0, SOCF_RO }, 13545 { XGXS0_SPEED_100f, 1, 1, SOCF_RO } 13546 }; 13547 13548 #endif 13549 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 13550 soc_field_info_t soc_XPORT_XGXS_NEWSTATUS2_REGr_fields[] = { 13551 { XGXS0_SPEED2500f, 4, 4, SOCF_LE|SOCF_RO }, 13552 { XGXS0_SPEED5000f, 4, 12, SOCF_LE|SOCF_RO }, 13553 { XGXS0_TICKf, 4, 28, SOCF_LE|SOCF_RO } 13554 }; 13555 13556 #endif 13557 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 13558 soc_field_info_t soc_XPORT_XGXS_STATUS_REGr_fields[] = { 13559 { AUTONEG_COMPLETEf, 1, 6, SOCF_RO }, 13560 { DIG1000X_RX_FIFO_ERRORf, 1, 23, SOCF_RO }, 13561 { DIG1000X_TX_FIFO_ERRORf, 1, 22, SOCF_RO }, 13562 { DUPLEX_STATUSf, 1, 7, SOCF_RO }, 13563 { LINK10Gf, 1, 1, SOCF_RO }, 13564 { LINKOREDf, 1, 0, SOCF_RO }, 13565 { LINKSERDESf, 1, 2, SOCF_RO }, 13566 { RXACTf, 1, 3, SOCF_RO }, 13567 { SGMIIf, 1, 8, SOCF_RO }, 13568 { SPEED_10f, 1, 9, SOCF_RO }, 13569 { SPEED_100f, 1, 10, SOCF_RO }, 13570 { SPEED_1000f, 1, 11, SOCF_RO }, 13571 { SPEED_10000f, 1, 15, SOCF_RO }, 13572 { SPEED_10000_CX4f, 1, 16, SOCF_RO }, 13573 { SPEED_12000f, 1, 17, SOCF_RO }, 13574 { SPEED_12500f, 1, 18, SOCF_RO }, 13575 { SPEED_13000f, 1, 19, SOCF_RO }, 13576 { SPEED_15000f, 1, 20, SOCF_RO }, 13577 { SPEED_16000f, 1, 21, SOCF_RO }, 13578 { SPEED_2500f, 1, 12, SOCF_RO }, 13579 { SPEED_5000f, 1, 13, SOCF_RO }, 13580 { SPEED_6000f, 1, 14, SOCF_RO }, 13581 { TXACTf, 1, 4, SOCF_RO }, 13582 { TXPLL_LOCKf, 1, 5, SOCF_RO } 13583 }; 13584 13585 #endif 13586 #if defined(BCM_88270_A0) 13587 soc_field_info_t soc_XPORT_XGXS_STATUS_REG_BCM88270_A0r_fields[] = { 13588 { XGXS_LINK_STATUSf, 1, 0, SOCF_RO }, 13589 { XGXS_SGMIIf, 1, 1, SOCF_RO }, 13590 { XGXS_SPEED1000f, 1, 4, SOCF_RO }, 13591 { XGXS_SPEED10000f, 1, 7, SOCF_RO }, 13592 { XGXS_SPEED10000_CX4f, 1, 6, SOCF_RO }, 13593 { XGXS_SPEED2500f, 1, 5, SOCF_RO }, 13594 { XGXS_SPEED_10f, 1, 2, SOCF_RO }, 13595 { XGXS_SPEED_100f, 1, 3, SOCF_RO } 13596 }; 13597 13598 #endif 13599 #if defined(BCM_88270_A0) 13600 soc_field_info_t soc_XPORT_XLMAC_CONTROLr_fields[] = { 13601 { RX_SHIM_FIFO_RESETf, 1, 2, 0 }, 13602 { XLMAC_BYPASS_OSTSf, 1, 1, 0 }, 13603 { XLMAC_RESETf, 1, 0, 0 } 13604 }; 13605 13606 #endif 13607 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13608 defined(BCM_56450_B1) 13609 soc_field_info_t soc_XPORT_XMAC_CONTROLr_fields[] = { 13610 { XMAC_BYPASS_OSTSf, 1, 2, SOCF_RES }, 13611 { XMAC_RESETf, 1, 0, SOCF_RES }, 13612 { XMAC_RESET_LINE_LPBKf, 1, 1, SOCF_RES } 13613 }; 13614 13615 #endif 13616 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 13617 defined(BCM_56270_A0) 13618 soc_field_info_t soc_XPORT_XMAC_CONTROL_BCM56260_A0r_fields[] = { 13619 { RX_SHIM_FIFO_RESETf, 1, 2, SOCF_RES }, 13620 { XMAC_BYPASS_OSTSf, 1, 1, SOCF_RES }, 13621 { XMAC_RESETf, 1, 0, SOCF_RES } 13622 }; 13623 13624 #endif 13625 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13626 defined(BCM_56450_B1) 13627 soc_field_info_t soc_XP_EEE_COUNTER_MODEr_fields[] = { 13628 { MODE_BITf, 1, 0, 0 } 13629 }; 13630 13631 #endif 13632 #if defined(BCM_88270_A0) 13633 soc_field_info_t soc_XP_EEE_COUNTER_MODE_BCM88270_A0r_fields[] = { 13634 { MODE_BITf, 1, 0, 0 } 13635 }; 13636 13637 #endif 13638 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 13639 defined(BCM_56270_A0) 13640 soc_field_info_t soc_XP_FIFO_OVERFLOW_STATUSr_fields[] = { 13641 { RXFIFO_OVERFLOWf, 1, 1, 0 }, 13642 { RX_CELL_FIFO_OVERFLOWf, 1, 2, 0 }, 13643 { TXFIFO_OVERFLOWf, 1, 0, 0 } 13644 }; 13645 13646 #endif 13647 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 13648 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 13649 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 13650 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 13651 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 13652 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 13653 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 13654 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 13655 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 13656 defined(BCM_56800_A0) || defined(BCM_56820_A0) 13657 soc_field_info_t soc_XP_XBODE_CELL_CNTr_fields[] = { 13658 { CELL_CNTf, 4, 0, SOCF_LE|SOCF_RO } 13659 }; 13660 13661 #endif 13662 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 13663 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 13664 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 13665 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 13666 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 13667 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 13668 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 13669 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 13670 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 13671 defined(BCM_56800_A0) || defined(BCM_56820_A0) 13672 soc_field_info_t soc_XP_XBODE_CELL_REQ_CNTr_fields[] = { 13673 { REQ_CNTf, 4, 0, SOCF_LE|SOCF_RO } 13674 }; 13675 13676 #endif 13677 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 13678 defined(BCM_56504_B0) 13679 soc_field_info_t soc_XQCOSARBSELr_fields[] = { 13680 { COSARBf, 2, 0, SOCF_LE } 13681 }; 13682 13683 #endif 13684 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \ 13685 defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 13686 defined(BCM_56160_A0) 13687 soc_field_info_t soc_XQCOSARBSEL_BCM53400_A0r_fields[] = { 13688 { COSARBf, 2, 0, SOCF_LE }, 13689 { MTU_QUANTA_SELECTf, 2, 2, SOCF_LE } 13690 }; 13691 13692 #endif 13693 #if defined(BCM_56150_A0) 13694 soc_field_info_t soc_XQCOSARBSEL_BCM56150_A0r_fields[] = { 13695 { COSARBf, 2, 0, SOCF_LE }, 13696 { MTU_QUANTA_SELECTf, 2, 2, SOCF_LE } 13697 }; 13698 13699 #endif 13700 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 13701 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 13702 defined(BCM_56224_B0) 13703 soc_field_info_t soc_XQCOSARBSEL_BCM56224_A0r_fields[] = { 13704 { COSARBf, 2, 0, SOCF_LE }, 13705 { MTU_QUANTA_SELECTf, 2, 2, SOCF_LE } 13706 }; 13707 13708 #endif 13709 #if defined(BCM_56514_A0) 13710 soc_field_info_t soc_XQCOSARBSEL_BCM56514_A0r_fields[] = { 13711 { COSARBf, 2, 0, SOCF_LE }, 13712 { MTU_QUANTAf, 1, 2, 0 } 13713 }; 13714 13715 #endif 13716 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 13717 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 13718 defined(BCM_56224_B0) 13719 soc_field_info_t soc_XQCOSPTRr_fields[] = { 13720 { COSf, 4, 22, SOCF_LE|SOCF_SC }, 13721 { HEADPOINTERf, 11, 11, SOCF_LE|SOCF_RO|SOCF_SC }, 13722 { TAILPOINTERf, 11, 0, SOCF_LE|SOCF_RO|SOCF_SC } 13723 }; 13724 13725 #endif 13726 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 13727 soc_field_info_t soc_XQCOSPTRCTLr_fields[] = { 13728 { COSf, 6, 0, SOCF_LE|SOCF_SC } 13729 }; 13730 13731 #endif 13732 #if defined(BCM_53400_A0) 13733 soc_field_info_t soc_XQCOSPTR_BCM53400_A0r_fields[] = { 13734 { COSf, 4, 26, SOCF_LE|SOCF_SC }, 13735 { HEADPOINTERf, 13, 13, SOCF_LE|SOCF_RO|SOCF_SC }, 13736 { TAILPOINTERf, 13, 0, SOCF_LE|SOCF_RO|SOCF_SC } 13737 }; 13738 13739 #endif 13740 #if defined(BCM_53540_A0) 13741 soc_field_info_t soc_XQCOSPTR_BCM53540_A0r_fields[] = { 13742 { COSf, 4, 18, SOCF_LE|SOCF_SC }, 13743 { HEADPOINTERf, 9, 9, SOCF_LE|SOCF_RO|SOCF_SC }, 13744 { TAILPOINTERf, 9, 0, SOCF_LE|SOCF_RO|SOCF_SC } 13745 }; 13746 13747 #endif 13748 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 13749 soc_field_info_t soc_XQCOSPTR_BCM53570_A0r_fields[] = { 13750 { HEADPOINTERf, 13, 13, SOCF_LE|SOCF_RO|SOCF_SC }, 13751 { TAILPOINTERf, 13, 0, SOCF_LE|SOCF_RO|SOCF_SC } 13752 }; 13753 13754 #endif 13755 #if defined(BCM_56150_A0) 13756 soc_field_info_t soc_XQCOSPTR_BCM56150_A0r_fields[] = { 13757 { COSf, 4, 22, SOCF_LE|SOCF_SC }, 13758 { HEADPOINTERf, 11, 11, SOCF_LE|SOCF_RO|SOCF_SC }, 13759 { TAILPOINTERf, 11, 0, SOCF_LE|SOCF_RO|SOCF_SC } 13760 }; 13761 13762 #endif 13763 #if defined(BCM_56160_A0) 13764 soc_field_info_t soc_XQCOSPTR_BCM56160_A0r_fields[] = { 13765 { COSf, 4, 22, SOCF_LE|SOCF_SC }, 13766 { HEADPOINTERf, 11, 11, SOCF_LE|SOCF_RO|SOCF_SC }, 13767 { TAILPOINTERf, 11, 0, SOCF_LE|SOCF_RO|SOCF_SC } 13768 }; 13769 13770 #endif 13771 #if defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 13772 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 13773 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 13774 defined(BCM_56514_A0) 13775 soc_field_info_t soc_XQEMPTYr_fields[] = { 13776 { COS0f, 1, 0, SOCF_RO }, 13777 { COS1f, 1, 1, SOCF_RO }, 13778 { COS2f, 1, 2, SOCF_RO }, 13779 { COS3f, 1, 3, SOCF_RO }, 13780 { COS4f, 1, 4, SOCF_RO }, 13781 { COS5f, 1, 5, SOCF_RO }, 13782 { COS6f, 1, 6, SOCF_RO }, 13783 { COS7f, 1, 7, SOCF_RO } 13784 }; 13785 13786 #endif 13787 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) 13788 soc_field_info_t soc_XQEMPTY_BCM53314_A0r_fields[] = { 13789 { COS0f, 1, 0, SOCF_RO }, 13790 { COS1f, 1, 1, SOCF_RO }, 13791 { COS2f, 1, 2, SOCF_RO }, 13792 { COS3f, 1, 3, SOCF_RO } 13793 }; 13794 13795 #endif 13796 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \ 13797 defined(BCM_56160_A0) 13798 soc_field_info_t soc_XQEMPTY_BCM53400_A0r_fields[] = { 13799 { COS0f, 1, 0, SOCF_RO }, 13800 { COS1f, 1, 1, SOCF_RO }, 13801 { COS2f, 1, 2, SOCF_RO }, 13802 { COS3f, 1, 3, SOCF_RO }, 13803 { COS4f, 1, 4, SOCF_RO }, 13804 { COS5f, 1, 5, SOCF_RO }, 13805 { COS6f, 1, 6, SOCF_RO }, 13806 { COS7f, 1, 7, SOCF_RO } 13807 }; 13808 13809 #endif 13810 #if defined(BCM_56150_A0) 13811 soc_field_info_t soc_XQEMPTY_BCM56150_A0r_fields[] = { 13812 { COS0f, 1, 0, SOCF_RO }, 13813 { COS1f, 1, 1, SOCF_RO }, 13814 { COS2f, 1, 2, SOCF_RO }, 13815 { COS3f, 1, 3, SOCF_RO }, 13816 { COS4f, 1, 4, SOCF_RO }, 13817 { COS5f, 1, 5, SOCF_RO }, 13818 { COS6f, 1, 6, SOCF_RO }, 13819 { COS7f, 1, 7, SOCF_RO } 13820 }; 13821 13822 #endif 13823 #if defined(BCM_53540_A0) || defined(BCM_56160_A0) 13824 soc_field_info_t soc_XQEMPTY_DEBUGr_fields[] = { 13825 { Q_EMPTYf, 8, 0, SOCF_LE|SOCF_RO } 13826 }; 13827 13828 #endif 13829 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 13830 soc_field_info_t soc_XQEMPTY_DEBUG_QLAYER_QBMP0r_fields[] = { 13831 { Q_EMPTYf, 32, 0, SOCF_LE|SOCF_RO } 13832 }; 13833 13834 #endif 13835 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 13836 soc_field_info_t soc_XQEMPTY_QLAYER_QBMP0r_fields[] = { 13837 { EMPTY_BMPf, 32, 0, SOCF_LE|SOCF_RO } 13838 }; 13839 13840 #endif 13841 #if defined(BCM_56142_A0) 13842 soc_field_info_t soc_XQFLLPARITYERRORPTRr_fields[] = { 13843 { XQFLLPARITYERRORPTRf, 11, 0, SOCF_LE|SOCF_RO }, 13844 { XQFLLPARITYERRORTYPEf, 2, 11, SOCF_LE|SOCF_RO } 13845 }; 13846 13847 #endif 13848 #if defined(BCM_53400_A0) 13849 soc_field_info_t soc_XQFLLPARITYERRORPTR_BCM53400_A0r_fields[] = { 13850 { DOUBLE_BIT_ERRf, 1, 14, SOCF_RO }, 13851 { ENTRY_INDEXf, 13, 0, SOCF_LE|SOCF_RO }, 13852 { SINGLE_BIT_ERRf, 1, 13, SOCF_RO } 13853 }; 13854 13855 #endif 13856 #if defined(BCM_53570_A0) 13857 soc_field_info_t soc_XQFLLPARITYERRORPTR_BCM53570_A0r_fields[] = { 13858 { DOUBLE_BIT_ERRf, 1, 13, SOCF_RO }, 13859 { ENTRY_INDEXf, 12, 0, SOCF_LE|SOCF_RO }, 13860 { SINGLE_BIT_ERRf, 1, 12, SOCF_RO }, 13861 { UNDERRUN_ERRf, 1, 14, SOCF_RO } 13862 }; 13863 13864 #endif 13865 #if defined(BCM_53570_B0) 13866 soc_field_info_t soc_XQFLLPARITYERRORPTR_BCM53570_B0r_fields[] = { 13867 { DOUBLE_BIT_ERRf, 1, 13, SOCF_RO }, 13868 { ECCERR_OVERPTR_ERRf, 1, 15, SOCF_RO }, 13869 { ENTRY_INDEXf, 12, 0, SOCF_LE|SOCF_RO }, 13870 { SINGLE_BIT_ERRf, 1, 12, SOCF_RO }, 13871 { UNDERRUN_ERRf, 1, 14, SOCF_RO } 13872 }; 13873 13874 #endif 13875 #if defined(BCM_56150_A0) 13876 soc_field_info_t soc_XQFLLPARITYERRORPTR_BCM56150_A0r_fields[] = { 13877 { XQFLLPARITYERRORPTRf, 11, 0, SOCF_LE|SOCF_RO }, 13878 { XQFLLPARITYERRORTYPEf, 2, 11, SOCF_LE|SOCF_RO } 13879 }; 13880 13881 #endif 13882 #if defined(BCM_56160_A0) 13883 soc_field_info_t soc_XQFLLPARITYERRORPTR_BCM56160_A0r_fields[] = { 13884 { DOUBLE_BIT_ERRf, 1, 12, SOCF_RO }, 13885 { ENTRY_INDEXf, 11, 0, SOCF_LE|SOCF_RO }, 13886 { SINGLE_BIT_ERRf, 1, 11, SOCF_RO } 13887 }; 13888 13889 #endif 13890 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 13891 soc_field_info_t soc_XQFLLPTRr_fields[] = { 13892 { POINTERf, 12, 0, SOCF_LE|SOCF_RO|SOCF_SC } 13893 }; 13894 13895 #endif 13896 #if defined(BCM_56514_A0) 13897 soc_field_info_t soc_XQMEMDEBUGr_fields[] = { 13898 { CCMf, 1, 0, SOCF_RES }, 13899 { CT0f, 1, 4, SOCF_RES }, 13900 { CT1f, 1, 5, SOCF_RES }, 13901 { CT2f, 1, 6, SOCF_RES }, 13902 { RMf, 1, 1, SOCF_RES }, 13903 { SAMf, 2, 2, SOCF_LE|SOCF_RES } 13904 }; 13905 13906 #endif 13907 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 13908 defined(BCM_56504_B0) || defined(BCM_56514_A0) 13909 soc_field_info_t soc_XQPARITYERRORPBMr_fields[] = { 13910 { XQPARITYERRORPBMf, 29, 0, SOCF_LE|SOCF_RO } 13911 }; 13912 13913 #endif 13914 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) 13915 soc_field_info_t soc_XQPARITYERRORPBM_BCM53314_A0r_fields[] = { 13916 { XQPARITYERRORPBMf, 25, 0, SOCF_LE|SOCF_RO } 13917 }; 13918 13919 #endif 13920 #if defined(BCM_56150_A0) 13921 soc_field_info_t soc_XQPARITYERRORPBM_BCM56150_A0r_fields[] = { 13922 { XQPARITYERRORPBMf, 30, 0, SOCF_LE|SOCF_RO } 13923 }; 13924 13925 #endif 13926 #if defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 13927 defined(BCM_56224_B0) 13928 soc_field_info_t soc_XQPARITYERRORPBM_BCM56224_A0r_fields[] = { 13929 { XQPARITYERRORPBMf, 30, 0, SOCF_LE|SOCF_RO } 13930 }; 13931 13932 #endif 13933 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 13934 defined(BCM_56504_B0) || defined(BCM_56514_A0) 13935 soc_field_info_t soc_XQPARITYERRORPTRr_fields[] = { 13936 { XQPARITYERRORPKTPTRf, 14, 11, SOCF_LE|SOCF_RO }, 13937 { XQPARITYERRORPTRf, 11, 0, SOCF_LE|SOCF_RO } 13938 }; 13939 13940 #endif 13941 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) 13942 soc_field_info_t soc_XQPARITYERRORPTR_BCM53314_A0r_fields[] = { 13943 { XQPARITYERRORPKTPTRf, 12, 9, SOCF_LE|SOCF_RO }, 13944 { XQPARITYERRORPTRf, 9, 0, SOCF_LE|SOCF_RO }, 13945 { XQPARITYERRORTYPEf, 4, 21, SOCF_LE|SOCF_RO } 13946 }; 13947 13948 #endif 13949 #if defined(BCM_53400_A0) 13950 soc_field_info_t soc_XQPARITYERRORPTR_BCM53400_A0r_fields[] = { 13951 { DOUBLE_BIT_ERRf, 1, 28, SOCF_RO }, 13952 { ENTRY_INDEXf, 13, 0, SOCF_LE|SOCF_RO }, 13953 { SINGLE_BIT_ERRf, 1, 27, SOCF_RO }, 13954 { XQPARITYERRORPKTPTRf, 14, 13, SOCF_LE|SOCF_RO } 13955 }; 13956 13957 #endif 13958 #if defined(BCM_53540_A0) 13959 soc_field_info_t soc_XQPARITYERRORPTR_BCM53540_A0r_fields[] = { 13960 { DOUBLE_BIT_ERRf, 1, 22, SOCF_RO }, 13961 { ENTRY_INDEXf, 9, 0, SOCF_LE|SOCF_RO }, 13962 { SINGLE_BIT_ERRf, 1, 21, SOCF_RO }, 13963 { XQPARITYERRORPKTPTRf, 12, 9, SOCF_LE|SOCF_RO } 13964 }; 13965 13966 #endif 13967 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 13968 soc_field_info_t soc_XQPARITYERRORPTR_BCM53570_A0r_fields[] = { 13969 { DOUBLE_BIT_ERRf, 1, 29, SOCF_RO }, 13970 { ENTRY_INDEXf, 13, 0, SOCF_LE|SOCF_RO }, 13971 { SINGLE_BIT_ERRf, 1, 28, SOCF_RO }, 13972 { XQPARITYERRORPKTPTRf, 15, 13, SOCF_LE|SOCF_RO } 13973 }; 13974 13975 #endif 13976 #if defined(BCM_56142_A0) 13977 soc_field_info_t soc_XQPARITYERRORPTR_BCM56142_A0r_fields[] = { 13978 { XQPARITYERRORPKTPTRf, 14, 11, SOCF_LE|SOCF_RO }, 13979 { XQPARITYERRORPTRf, 11, 0, SOCF_LE|SOCF_RO }, 13980 { XQPARITYERRORTYPEf, 3, 25, SOCF_LE|SOCF_RO } 13981 }; 13982 13983 #endif 13984 #if defined(BCM_56150_A0) 13985 soc_field_info_t soc_XQPARITYERRORPTR_BCM56150_A0r_fields[] = { 13986 { XQPARITYERRORPKTPTRf, 14, 11, SOCF_LE|SOCF_RO }, 13987 { XQPARITYERRORPTRf, 11, 0, SOCF_LE|SOCF_RO }, 13988 { XQPARITYERRORTYPEf, 3, 25, SOCF_LE|SOCF_RO } 13989 }; 13990 13991 #endif 13992 #if defined(BCM_56160_A0) 13993 soc_field_info_t soc_XQPARITYERRORPTR_BCM56160_A0r_fields[] = { 13994 { DOUBLE_BIT_ERRf, 1, 26, SOCF_RO }, 13995 { ENTRY_INDEXf, 11, 0, SOCF_LE|SOCF_RO }, 13996 { SINGLE_BIT_ERRf, 1, 25, SOCF_RO }, 13997 { XQPARITYERRORPKTPTRf, 14, 11, SOCF_LE|SOCF_RO } 13998 }; 13999 14000 #endif 14001 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) 14002 soc_field_info_t soc_XQPARITYERRORPTR_BCM56224_A0r_fields[] = { 14003 { XQPARITYERRORPKTPTRf, 14, 11, SOCF_LE|SOCF_RO }, 14004 { XQPARITYERRORPTRf, 11, 0, SOCF_LE|SOCF_RO }, 14005 { XQPARITYERRORTYPEf, 4, 25, SOCF_LE|SOCF_RO } 14006 }; 14007 14008 #endif 14009 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 14010 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 14011 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 14012 defined(BCM_56685_A0) || defined(BCM_56685_B0) 14013 soc_field_info_t soc_XQPORT_FORCE_DOUBLE_BIT_ERRORr_fields[] = { 14014 { EHG_RX_DATAf, 1, 1, SOCF_RES }, 14015 { EHG_RX_MASKf, 1, 2, SOCF_RES }, 14016 { EHG_TX_DATAf, 1, 0, SOCF_RES }, 14017 { XQBODE_TXFIFOf, 1, 4, SOCF_RES }, 14018 { XQBOD_RXFIFOf, 1, 3, SOCF_RES } 14019 }; 14020 14021 #endif 14022 #if defined(BCM_56142_A0) 14023 soc_field_info_t soc_XQPORT_FORCE_DOUBLE_BIT_ERROR_BCM56142_A0r_fields[] = { 14024 { XQBODE_TXFIFOf, 1, 4, SOCF_RES }, 14025 { XQBOD_RXFIFOf, 1, 3, SOCF_RES } 14026 }; 14027 14028 #endif 14029 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 14030 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 14031 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 14032 defined(BCM_56685_A0) || defined(BCM_56685_B0) 14033 soc_field_info_t soc_XQPORT_INTR_ENABLEr_fields[] = { 14034 { EHG_RX_DATAf, 1, 1, 0 }, 14035 { EHG_RX_MASKf, 1, 2, 0 }, 14036 { EHG_TX_DATAf, 1, 0, 0 }, 14037 { XQBODE_TXFIFOf, 1, 4, 0 }, 14038 { XQBOD_RXFIFOf, 1, 3, 0 } 14039 }; 14040 14041 #endif 14042 #if defined(BCM_56142_A0) 14043 soc_field_info_t soc_XQPORT_INTR_ENABLE_BCM56142_A0r_fields[] = { 14044 { XQBODE_TXFIFOf, 1, 4, 0 }, 14045 { XQBOD_RXFIFOf, 1, 3, 0 } 14046 }; 14047 14048 #endif 14049 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 14050 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 14051 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 14052 defined(BCM_56685_A0) || defined(BCM_56685_B0) 14053 soc_field_info_t soc_XQPORT_INTR_STATUSr_fields[] = { 14054 { EHG_RX_DATAf, 1, 1, SOCF_RO }, 14055 { EHG_RX_MASKf, 1, 2, SOCF_RO }, 14056 { EHG_TX_DATAf, 1, 0, SOCF_RO }, 14057 { XQBODE_TXFIFOf, 1, 4, SOCF_RO }, 14058 { XQBOD_RXFIFOf, 1, 3, SOCF_RO } 14059 }; 14060 14061 #endif 14062 #if defined(BCM_56142_A0) 14063 soc_field_info_t soc_XQPORT_INTR_STATUS_BCM56142_A0r_fields[] = { 14064 { XQBODE_TXFIFOf, 1, 4, SOCF_RO }, 14065 { XQBOD_RXFIFOf, 1, 3, SOCF_RO } 14066 }; 14067 14068 #endif 14069 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 14070 defined(BCM_56334_B0) || defined(BCM_56524_A0) || \ 14071 defined(BCM_56524_B0) || defined(BCM_56634_A0) || \ 14072 defined(BCM_56634_B0) || defined(BCM_56685_A0) || \ 14073 defined(BCM_56685_B0) 14074 soc_field_info_t soc_XQPORT_MODE_REGr_fields[] = { 14075 { XQPORT_MODE_BITSf, 2, 0, SOCF_LE|SOCF_RES } 14076 }; 14077 14078 #endif 14079 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 14080 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 14081 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 14082 defined(BCM_56524_B0) || defined(BCM_56634_A0) || \ 14083 defined(BCM_56634_B0) || defined(BCM_56685_A0) || \ 14084 defined(BCM_56685_B0) 14085 soc_field_info_t soc_XQPORT_XGXS_NEWCTL_REGr_fields[] = { 14086 { TXD1G_FIFO_RSTBf, 4, 0, SOCF_LE } 14087 }; 14088 14089 #endif 14090 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 14091 defined(BCM_56334_B0) 14092 soc_field_info_t soc_XQPORT_XGXS_NEWSTATUS0_REGr_fields[] = { 14093 { XGXS0_AUTONEG_COMPLETEf, 1, 0, SOCF_RO }, 14094 { XGXS0_DUPLEX_STATUSf, 1, 4, SOCF_RO }, 14095 { XGXS0_FIBER_RXACTf, 1, 8, SOCF_RO }, 14096 { XGXS0_FIBER_TXACTf, 1, 12, SOCF_RO }, 14097 { XGXS0_LINK_STATUSf, 1, 16, SOCF_RO }, 14098 { XGXS0_SGMIIf, 1, 20, SOCF_RO }, 14099 { XGXS0_SPEED_10f, 1, 24, SOCF_RO }, 14100 { XGXS0_SPEED_100f, 1, 28, SOCF_RO } 14101 }; 14102 14103 #endif 14104 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 14105 defined(BCM_56334_B0) 14106 soc_field_info_t soc_XQPORT_XGXS_NEWSTATUS1_REGr_fields[] = { 14107 { XGXS0_SPEED1000f, 1, 0, SOCF_RO }, 14108 { XGXS0_SPEED10000f, 1, 4, SOCF_RO }, 14109 { XGXS0_SPEED10000_CX4f, 1, 8, SOCF_RO }, 14110 { XGXS0_SPEED12000f, 1, 12, SOCF_RO }, 14111 { XGXS0_SPEED12500f, 1, 16, SOCF_RO }, 14112 { XGXS0_SPEED13000f, 1, 20, SOCF_RO }, 14113 { XGXS0_SPEED15000f, 1, 24, SOCF_RO }, 14114 { XGXS0_SPEED16000f, 1, 28, SOCF_RO } 14115 }; 14116 14117 #endif 14118 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 14119 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 14120 defined(BCM_56685_A0) || defined(BCM_56685_B0) 14121 soc_field_info_t soc_XQPORT_XGXS_NEWSTATUS2_REGr_fields[] = { 14122 { XGXS0_SPEED20000f, 4, 0, SOCF_LE|SOCF_RO }, 14123 { XGXS0_SPEED2500f, 4, 4, SOCF_LE|SOCF_RO }, 14124 { XGXS0_SPEED25455f, 4, 8, SOCF_LE|SOCF_RO }, 14125 { XGXS0_SPEED5000f, 4, 12, SOCF_LE|SOCF_RO }, 14126 { XGXS0_SPEED5000_SINGLEf, 4, 16, SOCF_LE|SOCF_RO }, 14127 { XGXS0_SPEED6000f, 4, 20, SOCF_LE|SOCF_RO }, 14128 { XGXS0_SPEED6364_SINGLEf, 4, 24, SOCF_LE|SOCF_RO }, 14129 { XGXS0_TICKf, 4, 28, SOCF_LE|SOCF_RO } 14130 }; 14131 14132 #endif 14133 #if defined(BCM_56142_A0) 14134 soc_field_info_t soc_XQPORT_XGXS_NEWSTATUS2_REG_BCM56142_A0r_fields[] = { 14135 { XGXS0_SPEED2500f, 1, 4, SOCF_RO }, 14136 { XGXS0_SPEED5000f, 1, 12, SOCF_RO }, 14137 { XGXS0_SPEED5000_SINGLEf, 1, 16, SOCF_RO }, 14138 { XGXS0_SPEED6364_SINGLEf, 1, 24, SOCF_RO }, 14139 { XGXS0_TICKf, 1, 28, SOCF_RO } 14140 }; 14141 14142 #endif 14143 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) 14144 soc_field_info_t soc_XQPORT_XGXS_NEWSTATUS2_REG_BCM56334_A0r_fields[] = { 14145 { XGXS0_SPEED2500f, 1, 4, SOCF_RO }, 14146 { XGXS0_SPEED5000f, 1, 12, SOCF_RO }, 14147 { XGXS0_TICKf, 1, 28, SOCF_RO } 14148 }; 14149 14150 #endif 14151 #if defined(BCM_56142_A0) 14152 soc_field_info_t soc_XQPORT_XGXS_NEWSTATUS3_REGr_fields[] = { 14153 { XGXS0_LINKf, 1, 0, SOCF_RO }, 14154 { XGXS0_LINK10Gf, 1, 1, SOCF_RO }, 14155 { XGXS0_SPEED10000_DUALf, 2, 12, SOCF_LE|SOCF_RO }, 14156 { XGXS0_SPEED10000_HI_DUALf, 2, 14, SOCF_LE|SOCF_RO }, 14157 { XGXS0_SPEED10500_DUALf, 2, 16, SOCF_LE|SOCF_RO }, 14158 { XGXS0_SPEED10500_HI_DUALf, 2, 18, SOCF_LE|SOCF_RO }, 14159 { XGXS0_SPEED12773_DUALf, 2, 20, SOCF_LE|SOCF_RO }, 14160 { XGXS0_SPEED12773_HI_DUALf, 2, 22, SOCF_LE|SOCF_RO }, 14161 { XGXS0_SPEED5000_DUALf, 2, 8, SOCF_LE|SOCF_RO }, 14162 { XGXS0_SPEED5000_HI_DUALf, 2, 10, SOCF_LE|SOCF_RO } 14163 }; 14164 14165 #endif 14166 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 14167 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 14168 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 14169 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 14170 defined(BCM_56514_A0) 14171 soc_field_info_t soc_XQREADPOINTERr_fields[] = { 14172 { COSf, 3, 11, SOCF_LE|SOCF_RO|SOCF_SC }, 14173 { READPOINTERf, 11, 0, SOCF_LE|SOCF_RO|SOCF_SC } 14174 }; 14175 14176 #endif 14177 #if defined(BCM_53400_A0) || defined(BCM_56160_A0) 14178 soc_field_info_t soc_XQREADPOINTER_BCM53400_A0r_fields[] = { 14179 { COSf, 3, 11, SOCF_LE|SOCF_RO|SOCF_SC }, 14180 { READPOINTERf, 11, 0, SOCF_LE|SOCF_RO|SOCF_SC } 14181 }; 14182 14183 #endif 14184 #if defined(BCM_53540_A0) 14185 soc_field_info_t soc_XQREADPOINTER_BCM53540_A0r_fields[] = { 14186 { COSf, 3, 9, SOCF_LE|SOCF_RO|SOCF_SC }, 14187 { READPOINTERf, 9, 0, SOCF_LE|SOCF_RO|SOCF_SC } 14188 }; 14189 14190 #endif 14191 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 14192 soc_field_info_t soc_XQREADPOINTER_BCM53570_A0r_fields[] = { 14193 { COSf, 3, 13, SOCF_LE|SOCF_RO|SOCF_SC }, 14194 { READPOINTERf, 13, 0, SOCF_LE|SOCF_RO|SOCF_SC } 14195 }; 14196 14197 #endif 14198 #if defined(BCM_56150_A0) 14199 soc_field_info_t soc_XQREADPOINTER_BCM56150_A0r_fields[] = { 14200 { COSf, 3, 11, SOCF_LE|SOCF_RO|SOCF_SC }, 14201 { READPOINTERf, 11, 0, SOCF_LE|SOCF_RO|SOCF_SC } 14202 }; 14203 14204 #endif 14205 #if defined(BCM_56142_A0) || defined(BCM_56314_A0) || \ 14206 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 14207 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 14208 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 14209 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 14210 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 14211 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 14212 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 14213 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 14214 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 14215 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 14216 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 14217 defined(BCM_88732_A0) 14218 soc_field_info_t soc_XTHOLr_fields[] = { 14219 { COUNTf, 32, 0, SOCF_LE } 14220 }; 14221 14222 #endif 14223 #if defined(BCM_88270_A0) 14224 soc_field_info_t soc_XTHOL_BCM88270_A0r_fields[] = { 14225 { COUNTf, 40, 0, SOCF_LE } 14226 }; 14227 14228 #endif 14229 #if defined(BCM_88375_A0) 14230 soc_field_info_t soc_XTHOL_BCM88375_A0r_fields[] = { 14231 { COUNTf, 40, 0, SOCF_LE } 14232 }; 14233 14234 #endif 14235 #if defined(BCM_88375_B0) 14236 soc_field_info_t soc_XTHOL_BCM88375_B0r_fields[] = { 14237 { COUNTf, 40, 0, SOCF_LE } 14238 }; 14239 14240 #endif 14241 #if defined(BCM_88470_A0) 14242 soc_field_info_t soc_XTHOL_BCM88470_A0r_fields[] = { 14243 { COUNTf, 40, 0, SOCF_LE } 14244 }; 14245 14246 #endif 14247 #if defined(BCM_88470_B0) 14248 soc_field_info_t soc_XTHOL_BCM88470_B0r_fields[] = { 14249 { COUNTf, 40, 0, SOCF_LE } 14250 }; 14251 14252 #endif 14253 #if defined(BCM_88675_A0) 14254 soc_field_info_t soc_XTHOL_BCM88675_A0r_fields[] = { 14255 { COUNTf, 40, 0, SOCF_LE } 14256 }; 14257 14258 #endif 14259 #if defined(BCM_88675_B0) 14260 soc_field_info_t soc_XTHOL_BCM88675_B0r_fields[] = { 14261 { COUNTf, 40, 0, SOCF_LE } 14262 }; 14263 14264 #endif 14265 #if defined(BCM_88680_A0) 14266 soc_field_info_t soc_XTHOL_BCM88680_A0r_fields[] = { 14267 { COUNTf, 40, 0, SOCF_LE } 14268 }; 14269 14270 #endif 14271 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 14272 soc_field_info_t soc_X_CPU_SLOT_COUNTr_fields[] = { 14273 { BUBBLE_CNTLf, 2, 10, SOCF_LE }, 14274 { COUNT_VALUEf, 10, 0, SOCF_LE } 14275 }; 14276 14277 #endif 14278 #if defined(BCM_88270_A0) 14279 soc_field_info_t soc_X_GPORT_CNTMAXSIZEr_fields[] = { 14280 { CNTMAXSIZEf, 14, 0, SOCF_LE } 14281 }; 14282 14283 #endif 14284 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 14285 defined(BCM_56450_B1) 14286 soc_field_info_t soc_X_GPORT_CONFIGr_fields[] = { 14287 { NO_CONNECTf, 1, 0, SOCF_RES } 14288 }; 14289 14290 #endif 14291 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 14292 defined(BCM_56450_B1) 14293 soc_field_info_t soc_X_GPORT_SGNDET_EARLYCRSr_fields[] = { 14294 { EARLY_CRSf, 1, 1, 0 }, 14295 { SGN_DETf, 1, 0, 0 } 14296 }; 14297 14298 #endif 14299 #if defined(BCM_88270_A0) 14300 soc_field_info_t soc_X_GPORT_SGNDET_EARLYCRS_BCM88270_A0r_fields[] = { 14301 { SGN_DETf, 1, 0, 0 } 14302 }; 14303 14304 #endif 14305 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 14306 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 14307 defined(BCM_88732_A0) 14308 soc_field_info_t soc_XLPORT_WC_UCMEM_DATAm_fields[] = { 14309 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14310 }; 14311 #endif 14312 14313 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \ 14314 defined(BCM_53570_A0) || defined(BCM_53570_B0) || \ 14315 defined(BCM_56160_A0) || defined(BCM_56260_A0) || \ 14316 defined(BCM_56260_B0) || defined(BCM_56270_A0) || \ 14317 defined(BCM_56370_A0) || defined(BCM_56560_A0) || \ 14318 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 14319 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 14320 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 14321 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 14322 defined(BCM_56980_A0) || defined(BCM_56980_B0) 14323 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM53400_A0m_fields[] = { 14324 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14325 }; 14326 #endif 14327 14328 #if defined(BCM_88270_A0) 14329 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM88270_A0m_fields[] = { 14330 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14331 }; 14332 #endif 14333 14334 #if defined(BCM_88375_A0) 14335 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM88375_A0m_fields[] = { 14336 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14337 }; 14338 #endif 14339 14340 #if defined(BCM_88375_B0) 14341 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM88375_B0m_fields[] = { 14342 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14343 }; 14344 #endif 14345 14346 #if defined(BCM_88470_A0) 14347 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM88470_A0m_fields[] = { 14348 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14349 }; 14350 #endif 14351 14352 #if defined(BCM_88470_B0) 14353 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM88470_B0m_fields[] = { 14354 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14355 }; 14356 #endif 14357 14358 #if defined(BCM_88675_A0) 14359 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM88675_A0m_fields[] = { 14360 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14361 }; 14362 #endif 14363 14364 #if defined(BCM_88675_B0) 14365 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM88675_B0m_fields[] = { 14366 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14367 }; 14368 #endif 14369 14370 #if defined(BCM_88680_A0) 14371 soc_field_info_t soc_XLPORT_WC_UCMEM_DATA_BCM88680_A0m_fields[] = { 14372 { UC_DATAf, 128, 0, SOCF_LE | SOCF_GLOBAL } 14373 }; 14374 #endif 14375 14376 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 14377 soc_field_info_t soc_X_ARB_TDM_TABLEm_fields[] = { 14378 { PORT_NUMf, 5, 0, SOCF_LE | SOCF_GLOBAL }, 14379 { WRAP_ENf, 1, 5, 0 | SOCF_GLOBAL } 14380 }; 14381 #endif 14382 14383 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 14384 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 14385 defined(BCM_56624_A0) || defined(BCM_56634_A0) || \ 14386 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 14387 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 14388 defined(BCM_56840_A0) || defined(BCM_56840_B0) 14389 soc_field_info_t soc_XGPORT_TO_EP_PORT_MODE_BUSfmt_fields[] = { 14390 { MODEf, 2, 0, SOCF_LE } 14391 }; 14392 #endif 14393 14394 #if defined(BCM_56624_B0) || defined(BCM_56680_B0) 14395 soc_field_info_t soc_XGPORT_TO_EP_PORT_MODE_BUS_BCM56624_B0fmt_fields[] = { 14396 { MODEf, 3, 0, SOCF_LE } 14397 }; 14398 #endif 14399 14400 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 14401 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 14402 defined(BCM_56640_A0) || defined(BCM_56850_A0) || \ 14403 defined(BCM_56860_A0) 14404 soc_field_info_t soc_XGPORT_TO_EP_PORT_MODE_BUS_BCM56640_A0fmt_fields[] = { 14405 { MODEf, 2, 0, SOCF_LE } 14406 }; 14407 #endif 14408 14409 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 14410 defined(BCM_56270_A0) || defined(BCM_56370_A0) || \ 14411 defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 14412 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 14413 defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 14414 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 14415 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 14416 defined(BCM_56980_B0) 14417 soc_field_info_t soc_XGPORT_TO_EP_PORT_MODE_BUS_BCM56960_A0fmt_fields[] = { 14418 { MODEf, 2, 0, SOCF_LE } 14419 }; 14420 #endif 14421 14422 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14423 defined(BCM_56680_A0) || defined(BCM_56680_B0) 14424 soc_field_info_t soc_XGPORT_TO_IP_CONTROL_WORDfmt_fields[] = { 14425 { CELL_BCOUNTf, 8, 2, SOCF_LE }, 14426 { CELL_SRC_PORTf, 4, 13, SOCF_LE }, 14427 { EOPf, 1, 1, 0 }, 14428 { LAG_FAIL_LOOPBACK_PKTf, 1, 12, 0 }, 14429 { PAUSE_PACKETf, 1, 11, 0 }, 14430 { PURGEf, 1, 10, 0 }, 14431 { SOPf, 1, 0, 0 } 14432 }; 14433 #endif 14434 14435 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 14436 defined(BCM_56334_B0) || defined(BCM_56524_A0) || \ 14437 defined(BCM_56524_B0) || defined(BCM_56634_A0) || \ 14438 defined(BCM_56634_B0) || defined(BCM_56685_A0) || \ 14439 defined(BCM_56685_B0) 14440 soc_field_info_t soc_XGPORT_TO_IP_CONTROL_WORD_BCM56634_A0fmt_fields[] = { 14441 { CELL_BCOUNTf, 8, 17, SOCF_LE }, 14442 { CELL_SRC_PORTf, 4, 28, SOCF_LE }, 14443 { E2Ef, 1, 13, 0 }, 14444 { EOPf, 1, 16, 0 }, 14445 { LAG_FAIL_LOOPBACK_PKTf, 1, 27, 0 }, 14446 { MH_VALIDf, 1, 14, 0 }, 14447 { PAUSE_PACKETf, 1, 26, 0 }, 14448 { PURGEf, 1, 25, 0 }, 14449 { RESERVEDf, 13, 0, SOCF_LE|SOCF_RES }, 14450 { SOPf, 1, 15, 0 } 14451 }; 14452 #endif 14453 14454 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14455 defined(BCM_56680_A0) || defined(BCM_56680_B0) 14456 soc_field_info_t soc_XGPORT_TO_IP_CTRL_BUSfmt_fields[] = { 14457 { BYTE_COUNTf, 8, 2, SOCF_LE }, 14458 { EOPf, 1, 1, 0 }, 14459 { LPBKf, 1, 12, 0 }, 14460 { PAUSEf, 1, 11, 0 }, 14461 { PURGEf, 1, 10, 0 }, 14462 { SOPf, 1, 0, 0 }, 14463 { SRC_PORTf, 4, 13, SOCF_LE } 14464 }; 14465 #endif 14466 14467 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 14468 soc_field_info_t soc_XPE_ENQ_TO_PQE_INFOfmt_fields[] = { 14469 { CELL_PTRf, 15, 0, SOCF_LE }, 14470 { DISCARDf, 1, 17, 0 }, 14471 { ENQUEUEDf, 1, 24, 0 }, 14472 { EOPf, 1, 16, 0 }, 14473 { SOPf, 1, 15, 0 }, 14474 { SRC_PORTf, 6, 18, SOCF_LE } 14475 }; 14476 #endif 14477 14478 #if defined(BCM_56370_A0) 14479 soc_field_info_t soc_XPE_ENQ_TO_PQE_INFO_BCM56370_A0fmt_fields[] = { 14480 { CELL_PTRf, 16, 0, SOCF_LE }, 14481 { DISCARDf, 1, 18, 0 }, 14482 { ENQUEUEDf, 1, 26, 0 }, 14483 { EOPf, 1, 17, 0 }, 14484 { SOPf, 1, 16, 0 }, 14485 { SRC_PORTf, 7, 19, SOCF_LE } 14486 }; 14487 #endif 14488 14489 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 14490 soc_field_info_t soc_XPE_ENQ_TO_PQE_INFO_BCM56870_A0fmt_fields[] = { 14491 { CELL_PTRf, 18, 0, SOCF_LE }, 14492 { DISCARDf, 1, 20, 0 }, 14493 { ENQUEUEDf, 1, 28, 0 }, 14494 { EOPf, 1, 19, 0 }, 14495 { SOPf, 1, 18, 0 }, 14496 { SRC_PORTf, 7, 21, SOCF_LE } 14497 }; 14498 #endif 14499 14500 #if defined(BCM_56970_A0) 14501 soc_field_info_t soc_XPE_ENQ_TO_PQE_INFO_BCM56970_A0fmt_fields[] = { 14502 { CELL_PTRf, 16, 0, SOCF_LE }, 14503 { DISCARDf, 1, 18, 0 }, 14504 { ENQUEUEDf, 1, 25, 0 }, 14505 { EOPf, 1, 17, 0 }, 14506 { SOPf, 1, 16, 0 }, 14507 { SRC_PORTf, 6, 19, SOCF_LE } 14508 }; 14509 #endif 14510 14511 #if defined(BCM_56142_A0) 14512 soc_field_info_t soc_XQFREE_S_RFfmt_fields[] = { 14513 { S_RFf, 9, 0, SOCF_LE } 14514 }; 14515 #endif 14516